1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
2 /* Copyright 2017-2019 NXP */
5 #include <linux/bpf_trace.h>
8 #include <linux/vmalloc.h>
9 #include <linux/ptp_classify.h>
10 #include <net/ip6_checksum.h>
11 #include <net/pkt_sched.h>
14 static int enetc_num_stack_tx_queues(struct enetc_ndev_priv *priv)
16 int num_tx_rings = priv->num_tx_rings;
19 for (i = 0; i < priv->num_rx_rings; i++)
20 if (priv->rx_ring[i]->xdp.prog)
21 return num_tx_rings - num_possible_cpus();
26 static struct enetc_bdr *enetc_rx_ring_from_xdp_tx_ring(struct enetc_ndev_priv *priv,
27 struct enetc_bdr *tx_ring)
29 int index = &priv->tx_ring[tx_ring->index] - priv->xdp_tx_ring;
31 return priv->rx_ring[index];
34 static struct sk_buff *enetc_tx_swbd_get_skb(struct enetc_tx_swbd *tx_swbd)
36 if (tx_swbd->is_xdp_tx || tx_swbd->is_xdp_redirect)
42 static struct xdp_frame *
43 enetc_tx_swbd_get_xdp_frame(struct enetc_tx_swbd *tx_swbd)
45 if (tx_swbd->is_xdp_redirect)
46 return tx_swbd->xdp_frame;
51 static void enetc_unmap_tx_buff(struct enetc_bdr *tx_ring,
52 struct enetc_tx_swbd *tx_swbd)
54 /* For XDP_TX, pages come from RX, whereas for the other contexts where
55 * we have is_dma_page_set, those come from skb_frag_dma_map. We need
56 * to match the DMA mapping length, so we need to differentiate those.
58 if (tx_swbd->is_dma_page)
59 dma_unmap_page(tx_ring->dev, tx_swbd->dma,
60 tx_swbd->is_xdp_tx ? PAGE_SIZE : tx_swbd->len,
63 dma_unmap_single(tx_ring->dev, tx_swbd->dma,
64 tx_swbd->len, tx_swbd->dir);
68 static void enetc_free_tx_frame(struct enetc_bdr *tx_ring,
69 struct enetc_tx_swbd *tx_swbd)
71 struct xdp_frame *xdp_frame = enetc_tx_swbd_get_xdp_frame(tx_swbd);
72 struct sk_buff *skb = enetc_tx_swbd_get_skb(tx_swbd);
75 enetc_unmap_tx_buff(tx_ring, tx_swbd);
78 xdp_return_frame(tx_swbd->xdp_frame);
79 tx_swbd->xdp_frame = NULL;
81 dev_kfree_skb_any(skb);
86 /* Let H/W know BD ring has been updated */
87 static void enetc_update_tx_ring_tail(struct enetc_bdr *tx_ring)
90 enetc_wr_reg_hot(tx_ring->tpir, tx_ring->next_to_use);
93 static int enetc_ptp_parse(struct sk_buff *skb, u8 *udp,
94 u8 *msgtype, u8 *twostep,
95 u16 *correction_offset, u16 *body_offset)
97 unsigned int ptp_class;
98 struct ptp_header *hdr;
102 ptp_class = ptp_classify_raw(skb);
103 if (ptp_class == PTP_CLASS_NONE)
106 hdr = ptp_parse_header(skb, ptp_class);
110 type = ptp_class & PTP_CLASS_PMASK;
111 if (type == PTP_CLASS_IPV4 || type == PTP_CLASS_IPV6)
116 *msgtype = ptp_get_msgtype(hdr, ptp_class);
117 *twostep = hdr->flag_field[0] & 0x2;
119 base = skb_mac_header(skb);
120 *correction_offset = (u8 *)&hdr->correction - base;
121 *body_offset = (u8 *)hdr + sizeof(struct ptp_header) - base;
126 static int enetc_map_tx_buffs(struct enetc_bdr *tx_ring, struct sk_buff *skb)
128 bool do_vlan, do_onestep_tstamp = false, do_twostep_tstamp = false;
129 struct enetc_ndev_priv *priv = netdev_priv(tx_ring->ndev);
130 struct enetc_hw *hw = &priv->si->hw;
131 struct enetc_tx_swbd *tx_swbd;
132 int len = skb_headlen(skb);
133 union enetc_tx_bd temp_bd;
134 u8 msgtype, twostep, udp;
135 union enetc_tx_bd *txbd;
136 u16 offset1, offset2;
143 i = tx_ring->next_to_use;
144 txbd = ENETC_TXBD(*tx_ring, i);
147 dma = dma_map_single(tx_ring->dev, skb->data, len, DMA_TO_DEVICE);
148 if (unlikely(dma_mapping_error(tx_ring->dev, dma)))
151 temp_bd.addr = cpu_to_le64(dma);
152 temp_bd.buf_len = cpu_to_le16(len);
155 tx_swbd = &tx_ring->tx_swbd[i];
158 tx_swbd->is_dma_page = 0;
159 tx_swbd->dir = DMA_TO_DEVICE;
162 do_vlan = skb_vlan_tag_present(skb);
163 if (skb->cb[0] & ENETC_F_TX_ONESTEP_SYNC_TSTAMP) {
164 if (enetc_ptp_parse(skb, &udp, &msgtype, &twostep, &offset1,
166 msgtype != PTP_MSGTYPE_SYNC || twostep)
167 WARN_ONCE(1, "Bad packet for one-step timestamping\n");
169 do_onestep_tstamp = true;
170 } else if (skb->cb[0] & ENETC_F_TX_TSTAMP) {
171 do_twostep_tstamp = true;
174 tx_swbd->do_twostep_tstamp = do_twostep_tstamp;
175 tx_swbd->qbv_en = !!(priv->active_offloads & ENETC_F_QBV);
176 tx_swbd->check_wb = tx_swbd->do_twostep_tstamp || tx_swbd->qbv_en;
178 if (do_vlan || do_onestep_tstamp || do_twostep_tstamp)
179 flags |= ENETC_TXBD_FLAGS_EX;
181 if (tx_ring->tsd_enable)
182 flags |= ENETC_TXBD_FLAGS_TSE | ENETC_TXBD_FLAGS_TXSTART;
184 /* first BD needs frm_len and offload flags set */
185 temp_bd.frm_len = cpu_to_le16(skb->len);
186 temp_bd.flags = flags;
188 if (flags & ENETC_TXBD_FLAGS_TSE)
189 temp_bd.txstart = enetc_txbd_set_tx_start(skb->skb_mstamp_ns,
192 if (flags & ENETC_TXBD_FLAGS_EX) {
195 enetc_clear_tx_bd(&temp_bd);
197 /* add extension BD for VLAN and/or timestamping */
202 if (unlikely(i == tx_ring->bd_count)) {
204 tx_swbd = tx_ring->tx_swbd;
205 txbd = ENETC_TXBD(*tx_ring, 0);
210 temp_bd.ext.vid = cpu_to_le16(skb_vlan_tag_get(skb));
211 temp_bd.ext.tpid = 0; /* < C-TAG */
212 e_flags |= ENETC_TXBD_E_FLAGS_VLAN_INS;
215 if (do_onestep_tstamp) {
220 lo = enetc_rd_hot(hw, ENETC_SICTR0);
221 hi = enetc_rd_hot(hw, ENETC_SICTR1);
222 sec = (u64)hi << 32 | lo;
223 nsec = do_div(sec, 1000000000);
225 /* Configure extension BD */
226 temp_bd.ext.tstamp = cpu_to_le32(lo & 0x3fffffff);
227 e_flags |= ENETC_TXBD_E_FLAGS_ONE_STEP_PTP;
229 /* Update originTimestamp field of Sync packet
230 * - 48 bits seconds field
231 * - 32 bits nanseconds field
233 data = skb_mac_header(skb);
234 *(__be16 *)(data + offset2) =
235 htons((sec >> 32) & 0xffff);
236 *(__be32 *)(data + offset2 + 2) =
237 htonl(sec & 0xffffffff);
238 *(__be32 *)(data + offset2 + 6) = htonl(nsec);
240 /* Configure single-step register */
241 val = ENETC_PM0_SINGLE_STEP_EN;
242 val |= ENETC_SET_SINGLE_STEP_OFFSET(offset1);
244 val |= ENETC_PM0_SINGLE_STEP_CH;
246 enetc_port_wr(hw, ENETC_PM0_SINGLE_STEP, val);
247 enetc_port_wr(hw, ENETC_PM1_SINGLE_STEP, val);
248 } else if (do_twostep_tstamp) {
249 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
250 e_flags |= ENETC_TXBD_E_FLAGS_TWO_STEP_PTP;
253 temp_bd.ext.e_flags = e_flags;
257 frag = &skb_shinfo(skb)->frags[0];
258 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++, frag++) {
259 len = skb_frag_size(frag);
260 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, len,
262 if (dma_mapping_error(tx_ring->dev, dma))
266 enetc_clear_tx_bd(&temp_bd);
272 if (unlikely(i == tx_ring->bd_count)) {
274 tx_swbd = tx_ring->tx_swbd;
275 txbd = ENETC_TXBD(*tx_ring, 0);
279 temp_bd.addr = cpu_to_le64(dma);
280 temp_bd.buf_len = cpu_to_le16(len);
284 tx_swbd->is_dma_page = 1;
285 tx_swbd->dir = DMA_TO_DEVICE;
289 /* last BD needs 'F' bit set */
290 flags |= ENETC_TXBD_FLAGS_F;
291 temp_bd.flags = flags;
294 tx_ring->tx_swbd[i].is_eof = true;
295 tx_ring->tx_swbd[i].skb = skb;
297 enetc_bdr_idx_inc(tx_ring, &i);
298 tx_ring->next_to_use = i;
300 skb_tx_timestamp(skb);
302 enetc_update_tx_ring_tail(tx_ring);
307 dev_err(tx_ring->dev, "DMA map error");
310 tx_swbd = &tx_ring->tx_swbd[i];
311 enetc_free_tx_frame(tx_ring, tx_swbd);
313 i = tx_ring->bd_count;
320 static void enetc_map_tx_tso_hdr(struct enetc_bdr *tx_ring, struct sk_buff *skb,
321 struct enetc_tx_swbd *tx_swbd,
322 union enetc_tx_bd *txbd, int *i, int hdr_len,
325 union enetc_tx_bd txbd_tmp;
326 u8 flags = 0, e_flags = 0;
329 enetc_clear_tx_bd(&txbd_tmp);
330 addr = tx_ring->tso_headers_dma + *i * TSO_HEADER_SIZE;
332 if (skb_vlan_tag_present(skb))
333 flags |= ENETC_TXBD_FLAGS_EX;
335 txbd_tmp.addr = cpu_to_le64(addr);
336 txbd_tmp.buf_len = cpu_to_le16(hdr_len);
338 /* first BD needs frm_len and offload flags set */
339 txbd_tmp.frm_len = cpu_to_le16(hdr_len + data_len);
340 txbd_tmp.flags = flags;
342 /* For the TSO header we do not set the dma address since we do not
343 * want it unmapped when we do cleanup. We still set len so that we
344 * count the bytes sent.
346 tx_swbd->len = hdr_len;
347 tx_swbd->do_twostep_tstamp = false;
348 tx_swbd->check_wb = false;
350 /* Actually write the header in the BD */
353 /* Add extension BD for VLAN */
354 if (flags & ENETC_TXBD_FLAGS_EX) {
355 /* Get the next BD */
356 enetc_bdr_idx_inc(tx_ring, i);
357 txbd = ENETC_TXBD(*tx_ring, *i);
358 tx_swbd = &tx_ring->tx_swbd[*i];
361 /* Setup the VLAN fields */
362 enetc_clear_tx_bd(&txbd_tmp);
363 txbd_tmp.ext.vid = cpu_to_le16(skb_vlan_tag_get(skb));
364 txbd_tmp.ext.tpid = 0; /* < C-TAG */
365 e_flags |= ENETC_TXBD_E_FLAGS_VLAN_INS;
368 txbd_tmp.ext.e_flags = e_flags;
373 static int enetc_map_tx_tso_data(struct enetc_bdr *tx_ring, struct sk_buff *skb,
374 struct enetc_tx_swbd *tx_swbd,
375 union enetc_tx_bd *txbd, char *data,
376 int size, bool last_bd)
378 union enetc_tx_bd txbd_tmp;
382 enetc_clear_tx_bd(&txbd_tmp);
384 addr = dma_map_single(tx_ring->dev, data, size, DMA_TO_DEVICE);
385 if (unlikely(dma_mapping_error(tx_ring->dev, addr))) {
386 netdev_err(tx_ring->ndev, "DMA map error\n");
391 flags |= ENETC_TXBD_FLAGS_F;
395 txbd_tmp.addr = cpu_to_le64(addr);
396 txbd_tmp.buf_len = cpu_to_le16(size);
397 txbd_tmp.flags = flags;
401 tx_swbd->dir = DMA_TO_DEVICE;
408 static __wsum enetc_tso_hdr_csum(struct tso_t *tso, struct sk_buff *skb,
409 char *hdr, int hdr_len, int *l4_hdr_len)
411 char *l4_hdr = hdr + skb_transport_offset(skb);
412 int mac_hdr_len = skb_network_offset(skb);
414 if (tso->tlen != sizeof(struct udphdr)) {
415 struct tcphdr *tcph = (struct tcphdr *)(l4_hdr);
419 struct udphdr *udph = (struct udphdr *)(l4_hdr);
424 /* Compute the IP checksum. This is necessary since tso_build_hdr()
425 * already incremented the IP ID field.
428 struct iphdr *iph = (void *)(hdr + mac_hdr_len);
431 iph->check = ip_fast_csum((unsigned char *)iph, iph->ihl);
434 /* Compute the checksum over the L4 header. */
435 *l4_hdr_len = hdr_len - skb_transport_offset(skb);
436 return csum_partial(l4_hdr, *l4_hdr_len, 0);
439 static void enetc_tso_complete_csum(struct enetc_bdr *tx_ring, struct tso_t *tso,
440 struct sk_buff *skb, char *hdr, int len,
443 char *l4_hdr = hdr + skb_transport_offset(skb);
446 /* Complete the L4 checksum by appending the pseudo-header to the
447 * already computed checksum.
450 csum_final = csum_tcpudp_magic(ip_hdr(skb)->saddr,
452 len, ip_hdr(skb)->protocol, sum);
454 csum_final = csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
455 &ipv6_hdr(skb)->daddr,
456 len, ipv6_hdr(skb)->nexthdr, sum);
458 if (tso->tlen != sizeof(struct udphdr)) {
459 struct tcphdr *tcph = (struct tcphdr *)(l4_hdr);
461 tcph->check = csum_final;
463 struct udphdr *udph = (struct udphdr *)(l4_hdr);
465 udph->check = csum_final;
469 static int enetc_map_tx_tso_buffs(struct enetc_bdr *tx_ring, struct sk_buff *skb)
471 int hdr_len, total_len, data_len;
472 struct enetc_tx_swbd *tx_swbd;
473 union enetc_tx_bd *txbd;
477 int err, i, bd_data_num;
479 /* Initialize the TSO handler, and prepare the first payload */
480 hdr_len = tso_start(skb, &tso);
481 total_len = skb->len - hdr_len;
482 i = tx_ring->next_to_use;
484 while (total_len > 0) {
488 txbd = ENETC_TXBD(*tx_ring, i);
489 tx_swbd = &tx_ring->tx_swbd[i];
492 /* Determine the length of this packet */
493 data_len = min_t(int, skb_shinfo(skb)->gso_size, total_len);
494 total_len -= data_len;
496 /* prepare packet headers: MAC + IP + TCP */
497 hdr = tx_ring->tso_headers + i * TSO_HEADER_SIZE;
498 tso_build_hdr(skb, hdr, &tso, data_len, total_len == 0);
500 /* compute the csum over the L4 header */
501 csum = enetc_tso_hdr_csum(&tso, skb, hdr, hdr_len, &pos);
502 enetc_map_tx_tso_hdr(tx_ring, skb, tx_swbd, txbd, &i, hdr_len, data_len);
506 while (data_len > 0) {
509 size = min_t(int, tso.size, data_len);
511 /* Advance the index in the BDR */
512 enetc_bdr_idx_inc(tx_ring, &i);
513 txbd = ENETC_TXBD(*tx_ring, i);
514 tx_swbd = &tx_ring->tx_swbd[i];
517 /* Compute the checksum over this segment of data and
518 * add it to the csum already computed (over the L4
519 * header and possible other data segments).
521 csum2 = csum_partial(tso.data, size, 0);
522 csum = csum_block_add(csum, csum2, pos);
525 err = enetc_map_tx_tso_data(tx_ring, skb, tx_swbd, txbd,
534 tso_build_data(skb, &tso, size);
536 if (unlikely(bd_data_num >= ENETC_MAX_SKB_FRAGS && data_len))
540 enetc_tso_complete_csum(tx_ring, &tso, skb, hdr, pos, csum);
545 /* Go to the next BD */
546 enetc_bdr_idx_inc(tx_ring, &i);
549 tx_ring->next_to_use = i;
550 enetc_update_tx_ring_tail(tx_ring);
555 dev_err(tx_ring->dev, "DMA map error");
559 tx_swbd = &tx_ring->tx_swbd[i];
560 enetc_free_tx_frame(tx_ring, tx_swbd);
562 i = tx_ring->bd_count;
569 static netdev_tx_t enetc_start_xmit(struct sk_buff *skb,
570 struct net_device *ndev)
572 struct enetc_ndev_priv *priv = netdev_priv(ndev);
573 struct enetc_bdr *tx_ring;
576 /* Queue one-step Sync packet if already locked */
577 if (skb->cb[0] & ENETC_F_TX_ONESTEP_SYNC_TSTAMP) {
578 if (test_and_set_bit_lock(ENETC_TX_ONESTEP_TSTAMP_IN_PROGRESS,
580 skb_queue_tail(&priv->tx_skbs, skb);
585 tx_ring = priv->tx_ring[skb->queue_mapping];
587 if (skb_is_gso(skb)) {
588 if (enetc_bd_unused(tx_ring) < tso_count_descs(skb)) {
589 netif_stop_subqueue(ndev, tx_ring->index);
590 return NETDEV_TX_BUSY;
594 count = enetc_map_tx_tso_buffs(tx_ring, skb);
597 if (unlikely(skb_shinfo(skb)->nr_frags > ENETC_MAX_SKB_FRAGS))
598 if (unlikely(skb_linearize(skb)))
599 goto drop_packet_err;
601 count = skb_shinfo(skb)->nr_frags + 1; /* fragments + head */
602 if (enetc_bd_unused(tx_ring) < ENETC_TXBDS_NEEDED(count)) {
603 netif_stop_subqueue(ndev, tx_ring->index);
604 return NETDEV_TX_BUSY;
607 if (skb->ip_summed == CHECKSUM_PARTIAL) {
608 err = skb_checksum_help(skb);
610 goto drop_packet_err;
613 count = enetc_map_tx_buffs(tx_ring, skb);
617 if (unlikely(!count))
618 goto drop_packet_err;
620 if (enetc_bd_unused(tx_ring) < ENETC_TXBDS_MAX_NEEDED)
621 netif_stop_subqueue(ndev, tx_ring->index);
626 dev_kfree_skb_any(skb);
630 netdev_tx_t enetc_xmit(struct sk_buff *skb, struct net_device *ndev)
632 struct enetc_ndev_priv *priv = netdev_priv(ndev);
633 u8 udp, msgtype, twostep;
634 u16 offset1, offset2;
636 /* Mark tx timestamp type on skb->cb[0] if requires */
637 if ((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
638 (priv->active_offloads & ENETC_F_TX_TSTAMP_MASK)) {
639 skb->cb[0] = priv->active_offloads & ENETC_F_TX_TSTAMP_MASK;
644 /* Fall back to two-step timestamp if not one-step Sync packet */
645 if (skb->cb[0] & ENETC_F_TX_ONESTEP_SYNC_TSTAMP) {
646 if (enetc_ptp_parse(skb, &udp, &msgtype, &twostep,
647 &offset1, &offset2) ||
648 msgtype != PTP_MSGTYPE_SYNC || twostep != 0)
649 skb->cb[0] = ENETC_F_TX_TSTAMP;
652 return enetc_start_xmit(skb, ndev);
655 static irqreturn_t enetc_msix(int irq, void *data)
657 struct enetc_int_vector *v = data;
662 /* disable interrupts */
663 enetc_wr_reg_hot(v->rbier, 0);
664 enetc_wr_reg_hot(v->ricr1, v->rx_ictt);
666 for_each_set_bit(i, &v->tx_rings_map, ENETC_MAX_NUM_TXQS)
667 enetc_wr_reg_hot(v->tbier_base + ENETC_BDR_OFF(i), 0);
671 napi_schedule(&v->napi);
676 static void enetc_rx_dim_work(struct work_struct *w)
678 struct dim *dim = container_of(w, struct dim, work);
679 struct dim_cq_moder moder =
680 net_dim_get_rx_moderation(dim->mode, dim->profile_ix);
681 struct enetc_int_vector *v =
682 container_of(dim, struct enetc_int_vector, rx_dim);
684 v->rx_ictt = enetc_usecs_to_cycles(moder.usec);
685 dim->state = DIM_START_MEASURE;
688 static void enetc_rx_net_dim(struct enetc_int_vector *v)
690 struct dim_sample dim_sample = {};
694 if (!v->rx_napi_work)
697 dim_update_sample(v->comp_cnt,
698 v->rx_ring.stats.packets,
699 v->rx_ring.stats.bytes,
701 net_dim(&v->rx_dim, dim_sample);
704 static int enetc_bd_ready_count(struct enetc_bdr *tx_ring, int ci)
706 int pi = enetc_rd_reg_hot(tx_ring->tcir) & ENETC_TBCIR_IDX_MASK;
708 return pi >= ci ? pi - ci : tx_ring->bd_count - ci + pi;
711 static bool enetc_page_reusable(struct page *page)
713 return (!page_is_pfmemalloc(page) && page_ref_count(page) == 1);
716 static void enetc_reuse_page(struct enetc_bdr *rx_ring,
717 struct enetc_rx_swbd *old)
719 struct enetc_rx_swbd *new;
721 new = &rx_ring->rx_swbd[rx_ring->next_to_alloc];
723 /* next buf that may reuse a page */
724 enetc_bdr_idx_inc(rx_ring, &rx_ring->next_to_alloc);
726 /* copy page reference */
730 static void enetc_get_tx_tstamp(struct enetc_hw *hw, union enetc_tx_bd *txbd,
733 u32 lo, hi, tstamp_lo;
735 lo = enetc_rd_hot(hw, ENETC_SICTR0);
736 hi = enetc_rd_hot(hw, ENETC_SICTR1);
737 tstamp_lo = le32_to_cpu(txbd->wb.tstamp);
740 *tstamp = (u64)hi << 32 | tstamp_lo;
743 static void enetc_tstamp_tx(struct sk_buff *skb, u64 tstamp)
745 struct skb_shared_hwtstamps shhwtstamps;
747 if (skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS) {
748 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
749 shhwtstamps.hwtstamp = ns_to_ktime(tstamp);
750 skb_txtime_consumed(skb);
751 skb_tstamp_tx(skb, &shhwtstamps);
755 static void enetc_recycle_xdp_tx_buff(struct enetc_bdr *tx_ring,
756 struct enetc_tx_swbd *tx_swbd)
758 struct enetc_ndev_priv *priv = netdev_priv(tx_ring->ndev);
759 struct enetc_rx_swbd rx_swbd = {
761 .page = tx_swbd->page,
762 .page_offset = tx_swbd->page_offset,
766 struct enetc_bdr *rx_ring;
768 rx_ring = enetc_rx_ring_from_xdp_tx_ring(priv, tx_ring);
770 if (likely(enetc_swbd_unused(rx_ring))) {
771 enetc_reuse_page(rx_ring, &rx_swbd);
773 /* sync for use by the device */
774 dma_sync_single_range_for_device(rx_ring->dev, rx_swbd.dma,
776 ENETC_RXB_DMA_SIZE_XDP,
779 rx_ring->stats.recycles++;
781 /* RX ring is already full, we need to unmap and free the
782 * page, since there's nothing useful we can do with it.
784 rx_ring->stats.recycle_failures++;
786 dma_unmap_page(rx_ring->dev, rx_swbd.dma, PAGE_SIZE,
788 __free_page(rx_swbd.page);
791 rx_ring->xdp.xdp_tx_in_flight--;
794 static bool enetc_clean_tx_ring(struct enetc_bdr *tx_ring, int napi_budget)
796 int tx_frm_cnt = 0, tx_byte_cnt = 0, tx_win_drop = 0;
797 struct net_device *ndev = tx_ring->ndev;
798 struct enetc_ndev_priv *priv = netdev_priv(ndev);
799 struct enetc_tx_swbd *tx_swbd;
801 bool do_twostep_tstamp;
804 i = tx_ring->next_to_clean;
805 tx_swbd = &tx_ring->tx_swbd[i];
807 bds_to_clean = enetc_bd_ready_count(tx_ring, i);
809 do_twostep_tstamp = false;
811 while (bds_to_clean && tx_frm_cnt < ENETC_DEFAULT_TX_WORK) {
812 struct xdp_frame *xdp_frame = enetc_tx_swbd_get_xdp_frame(tx_swbd);
813 struct sk_buff *skb = enetc_tx_swbd_get_skb(tx_swbd);
814 bool is_eof = tx_swbd->is_eof;
816 if (unlikely(tx_swbd->check_wb)) {
817 union enetc_tx_bd *txbd = ENETC_TXBD(*tx_ring, i);
819 if (txbd->flags & ENETC_TXBD_FLAGS_W &&
820 tx_swbd->do_twostep_tstamp) {
821 enetc_get_tx_tstamp(&priv->si->hw, txbd,
823 do_twostep_tstamp = true;
826 if (tx_swbd->qbv_en &&
827 txbd->wb.status & ENETC_TXBD_STATS_WIN)
831 if (tx_swbd->is_xdp_tx)
832 enetc_recycle_xdp_tx_buff(tx_ring, tx_swbd);
833 else if (likely(tx_swbd->dma))
834 enetc_unmap_tx_buff(tx_ring, tx_swbd);
837 xdp_return_frame(xdp_frame);
839 if (unlikely(skb->cb[0] & ENETC_F_TX_ONESTEP_SYNC_TSTAMP)) {
840 /* Start work to release lock for next one-step
841 * timestamping packet. And send one skb in
842 * tx_skbs queue if has.
844 schedule_work(&priv->tx_onestep_tstamp);
845 } else if (unlikely(do_twostep_tstamp)) {
846 enetc_tstamp_tx(skb, tstamp);
847 do_twostep_tstamp = false;
849 napi_consume_skb(skb, napi_budget);
852 tx_byte_cnt += tx_swbd->len;
853 /* Scrub the swbd here so we don't have to do that
854 * when we reuse it during xmit
856 memset(tx_swbd, 0, sizeof(*tx_swbd));
861 if (unlikely(i == tx_ring->bd_count)) {
863 tx_swbd = tx_ring->tx_swbd;
866 /* BD iteration loop end */
869 /* re-arm interrupt source */
870 enetc_wr_reg_hot(tx_ring->idr, BIT(tx_ring->index) |
871 BIT(16 + tx_ring->index));
874 if (unlikely(!bds_to_clean))
875 bds_to_clean = enetc_bd_ready_count(tx_ring, i);
878 tx_ring->next_to_clean = i;
879 tx_ring->stats.packets += tx_frm_cnt;
880 tx_ring->stats.bytes += tx_byte_cnt;
881 tx_ring->stats.win_drop += tx_win_drop;
883 if (unlikely(tx_frm_cnt && netif_carrier_ok(ndev) &&
884 __netif_subqueue_stopped(ndev, tx_ring->index) &&
885 (enetc_bd_unused(tx_ring) >= ENETC_TXBDS_MAX_NEEDED))) {
886 netif_wake_subqueue(ndev, tx_ring->index);
889 return tx_frm_cnt != ENETC_DEFAULT_TX_WORK;
892 static bool enetc_new_page(struct enetc_bdr *rx_ring,
893 struct enetc_rx_swbd *rx_swbd)
895 bool xdp = !!(rx_ring->xdp.prog);
899 page = dev_alloc_page();
903 /* For XDP_TX, we forgo dma_unmap -> dma_map */
904 rx_swbd->dir = xdp ? DMA_BIDIRECTIONAL : DMA_FROM_DEVICE;
906 addr = dma_map_page(rx_ring->dev, page, 0, PAGE_SIZE, rx_swbd->dir);
907 if (unlikely(dma_mapping_error(rx_ring->dev, addr))) {
914 rx_swbd->page = page;
915 rx_swbd->page_offset = rx_ring->buffer_offset;
920 static int enetc_refill_rx_ring(struct enetc_bdr *rx_ring, const int buff_cnt)
922 struct enetc_rx_swbd *rx_swbd;
923 union enetc_rx_bd *rxbd;
926 i = rx_ring->next_to_use;
927 rx_swbd = &rx_ring->rx_swbd[i];
928 rxbd = enetc_rxbd(rx_ring, i);
930 for (j = 0; j < buff_cnt; j++) {
932 if (unlikely(!rx_swbd->page)) {
933 if (unlikely(!enetc_new_page(rx_ring, rx_swbd))) {
934 rx_ring->stats.rx_alloc_errs++;
940 rxbd->w.addr = cpu_to_le64(rx_swbd->dma +
941 rx_swbd->page_offset);
942 /* clear 'R" as well */
945 enetc_rxbd_next(rx_ring, &rxbd, &i);
946 rx_swbd = &rx_ring->rx_swbd[i];
950 rx_ring->next_to_alloc = i; /* keep track from page reuse */
951 rx_ring->next_to_use = i;
953 /* update ENETC's consumer index */
954 enetc_wr_reg_hot(rx_ring->rcir, rx_ring->next_to_use);
960 #ifdef CONFIG_FSL_ENETC_PTP_CLOCK
961 static void enetc_get_rx_tstamp(struct net_device *ndev,
962 union enetc_rx_bd *rxbd,
965 struct skb_shared_hwtstamps *shhwtstamps = skb_hwtstamps(skb);
966 struct enetc_ndev_priv *priv = netdev_priv(ndev);
967 struct enetc_hw *hw = &priv->si->hw;
968 u32 lo, hi, tstamp_lo;
971 if (le16_to_cpu(rxbd->r.flags) & ENETC_RXBD_FLAG_TSTMP) {
972 lo = enetc_rd_reg_hot(hw->reg + ENETC_SICTR0);
973 hi = enetc_rd_reg_hot(hw->reg + ENETC_SICTR1);
974 rxbd = enetc_rxbd_ext(rxbd);
975 tstamp_lo = le32_to_cpu(rxbd->ext.tstamp);
979 tstamp = (u64)hi << 32 | tstamp_lo;
980 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
981 shhwtstamps->hwtstamp = ns_to_ktime(tstamp);
986 static void enetc_get_offloads(struct enetc_bdr *rx_ring,
987 union enetc_rx_bd *rxbd, struct sk_buff *skb)
989 struct enetc_ndev_priv *priv = netdev_priv(rx_ring->ndev);
992 if (rx_ring->ndev->features & NETIF_F_RXCSUM) {
993 u16 inet_csum = le16_to_cpu(rxbd->r.inet_csum);
995 skb->csum = csum_unfold((__force __sum16)~htons(inet_csum));
996 skb->ip_summed = CHECKSUM_COMPLETE;
999 if (le16_to_cpu(rxbd->r.flags) & ENETC_RXBD_FLAG_VLAN) {
1002 switch (le16_to_cpu(rxbd->r.flags) & ENETC_RXBD_FLAG_TPID) {
1004 tpid = htons(ETH_P_8021Q);
1007 tpid = htons(ETH_P_8021AD);
1010 tpid = htons(enetc_port_rd(&priv->si->hw,
1014 tpid = htons(enetc_port_rd(&priv->si->hw,
1021 __vlan_hwaccel_put_tag(skb, tpid, le16_to_cpu(rxbd->r.vlan_opt));
1024 #ifdef CONFIG_FSL_ENETC_PTP_CLOCK
1025 if (priv->active_offloads & ENETC_F_RX_TSTAMP)
1026 enetc_get_rx_tstamp(rx_ring->ndev, rxbd, skb);
1030 /* This gets called during the non-XDP NAPI poll cycle as well as on XDP_PASS,
1031 * so it needs to work with both DMA_FROM_DEVICE as well as DMA_BIDIRECTIONAL
1034 static struct enetc_rx_swbd *enetc_get_rx_buff(struct enetc_bdr *rx_ring,
1037 struct enetc_rx_swbd *rx_swbd = &rx_ring->rx_swbd[i];
1039 dma_sync_single_range_for_cpu(rx_ring->dev, rx_swbd->dma,
1040 rx_swbd->page_offset,
1041 size, rx_swbd->dir);
1045 /* Reuse the current page without performing half-page buffer flipping */
1046 static void enetc_put_rx_buff(struct enetc_bdr *rx_ring,
1047 struct enetc_rx_swbd *rx_swbd)
1049 size_t buffer_size = ENETC_RXB_TRUESIZE - rx_ring->buffer_offset;
1051 enetc_reuse_page(rx_ring, rx_swbd);
1053 dma_sync_single_range_for_device(rx_ring->dev, rx_swbd->dma,
1054 rx_swbd->page_offset,
1055 buffer_size, rx_swbd->dir);
1057 rx_swbd->page = NULL;
1060 /* Reuse the current page by performing half-page buffer flipping */
1061 static void enetc_flip_rx_buff(struct enetc_bdr *rx_ring,
1062 struct enetc_rx_swbd *rx_swbd)
1064 if (likely(enetc_page_reusable(rx_swbd->page))) {
1065 rx_swbd->page_offset ^= ENETC_RXB_TRUESIZE;
1066 page_ref_inc(rx_swbd->page);
1068 enetc_put_rx_buff(rx_ring, rx_swbd);
1070 dma_unmap_page(rx_ring->dev, rx_swbd->dma, PAGE_SIZE,
1072 rx_swbd->page = NULL;
1076 static struct sk_buff *enetc_map_rx_buff_to_skb(struct enetc_bdr *rx_ring,
1079 struct enetc_rx_swbd *rx_swbd = enetc_get_rx_buff(rx_ring, i, size);
1080 struct sk_buff *skb;
1083 ba = page_address(rx_swbd->page) + rx_swbd->page_offset;
1084 skb = build_skb(ba - rx_ring->buffer_offset, ENETC_RXB_TRUESIZE);
1085 if (unlikely(!skb)) {
1086 rx_ring->stats.rx_alloc_errs++;
1090 skb_reserve(skb, rx_ring->buffer_offset);
1091 __skb_put(skb, size);
1093 enetc_flip_rx_buff(rx_ring, rx_swbd);
1098 static void enetc_add_rx_buff_to_skb(struct enetc_bdr *rx_ring, int i,
1099 u16 size, struct sk_buff *skb)
1101 struct enetc_rx_swbd *rx_swbd = enetc_get_rx_buff(rx_ring, i, size);
1103 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, rx_swbd->page,
1104 rx_swbd->page_offset, size, ENETC_RXB_TRUESIZE);
1106 enetc_flip_rx_buff(rx_ring, rx_swbd);
1109 static bool enetc_check_bd_errors_and_consume(struct enetc_bdr *rx_ring,
1111 union enetc_rx_bd **rxbd, int *i)
1113 if (likely(!(bd_status & ENETC_RXBD_LSTATUS(ENETC_RXBD_ERR_MASK))))
1116 enetc_put_rx_buff(rx_ring, &rx_ring->rx_swbd[*i]);
1117 enetc_rxbd_next(rx_ring, rxbd, i);
1119 while (!(bd_status & ENETC_RXBD_LSTATUS_F)) {
1121 bd_status = le32_to_cpu((*rxbd)->r.lstatus);
1123 enetc_put_rx_buff(rx_ring, &rx_ring->rx_swbd[*i]);
1124 enetc_rxbd_next(rx_ring, rxbd, i);
1127 rx_ring->ndev->stats.rx_dropped++;
1128 rx_ring->ndev->stats.rx_errors++;
1133 static struct sk_buff *enetc_build_skb(struct enetc_bdr *rx_ring,
1134 u32 bd_status, union enetc_rx_bd **rxbd,
1135 int *i, int *cleaned_cnt, int buffer_size)
1137 struct sk_buff *skb;
1140 size = le16_to_cpu((*rxbd)->r.buf_len);
1141 skb = enetc_map_rx_buff_to_skb(rx_ring, *i, size);
1145 enetc_get_offloads(rx_ring, *rxbd, skb);
1149 enetc_rxbd_next(rx_ring, rxbd, i);
1151 /* not last BD in frame? */
1152 while (!(bd_status & ENETC_RXBD_LSTATUS_F)) {
1153 bd_status = le32_to_cpu((*rxbd)->r.lstatus);
1156 if (bd_status & ENETC_RXBD_LSTATUS_F) {
1158 size = le16_to_cpu((*rxbd)->r.buf_len);
1161 enetc_add_rx_buff_to_skb(rx_ring, *i, size, skb);
1165 enetc_rxbd_next(rx_ring, rxbd, i);
1168 skb_record_rx_queue(skb, rx_ring->index);
1169 skb->protocol = eth_type_trans(skb, rx_ring->ndev);
1174 #define ENETC_RXBD_BUNDLE 16 /* # of BDs to update at once */
1176 static int enetc_clean_rx_ring(struct enetc_bdr *rx_ring,
1177 struct napi_struct *napi, int work_limit)
1179 int rx_frm_cnt = 0, rx_byte_cnt = 0;
1182 cleaned_cnt = enetc_bd_unused(rx_ring);
1183 /* next descriptor to process */
1184 i = rx_ring->next_to_clean;
1186 while (likely(rx_frm_cnt < work_limit)) {
1187 union enetc_rx_bd *rxbd;
1188 struct sk_buff *skb;
1191 if (cleaned_cnt >= ENETC_RXBD_BUNDLE)
1192 cleaned_cnt -= enetc_refill_rx_ring(rx_ring,
1195 rxbd = enetc_rxbd(rx_ring, i);
1196 bd_status = le32_to_cpu(rxbd->r.lstatus);
1200 enetc_wr_reg_hot(rx_ring->idr, BIT(rx_ring->index));
1201 dma_rmb(); /* for reading other rxbd fields */
1203 if (enetc_check_bd_errors_and_consume(rx_ring, bd_status,
1207 skb = enetc_build_skb(rx_ring, bd_status, &rxbd, &i,
1208 &cleaned_cnt, ENETC_RXB_DMA_SIZE);
1212 rx_byte_cnt += skb->len;
1215 napi_gro_receive(napi, skb);
1218 rx_ring->next_to_clean = i;
1220 rx_ring->stats.packets += rx_frm_cnt;
1221 rx_ring->stats.bytes += rx_byte_cnt;
1226 static void enetc_xdp_map_tx_buff(struct enetc_bdr *tx_ring, int i,
1227 struct enetc_tx_swbd *tx_swbd,
1230 union enetc_tx_bd *txbd = ENETC_TXBD(*tx_ring, i);
1234 enetc_clear_tx_bd(txbd);
1235 txbd->addr = cpu_to_le64(tx_swbd->dma + tx_swbd->page_offset);
1236 txbd->buf_len = cpu_to_le16(tx_swbd->len);
1237 txbd->frm_len = cpu_to_le16(frm_len);
1239 memcpy(&tx_ring->tx_swbd[i], tx_swbd, sizeof(*tx_swbd));
1242 /* Puts in the TX ring one XDP frame, mapped as an array of TX software buffer
1245 static bool enetc_xdp_tx(struct enetc_bdr *tx_ring,
1246 struct enetc_tx_swbd *xdp_tx_arr, int num_tx_swbd)
1248 struct enetc_tx_swbd *tmp_tx_swbd = xdp_tx_arr;
1249 int i, k, frm_len = tmp_tx_swbd->len;
1251 if (unlikely(enetc_bd_unused(tx_ring) < ENETC_TXBDS_NEEDED(num_tx_swbd)))
1254 while (unlikely(!tmp_tx_swbd->is_eof)) {
1256 frm_len += tmp_tx_swbd->len;
1259 i = tx_ring->next_to_use;
1261 for (k = 0; k < num_tx_swbd; k++) {
1262 struct enetc_tx_swbd *xdp_tx_swbd = &xdp_tx_arr[k];
1264 enetc_xdp_map_tx_buff(tx_ring, i, xdp_tx_swbd, frm_len);
1266 /* last BD needs 'F' bit set */
1267 if (xdp_tx_swbd->is_eof) {
1268 union enetc_tx_bd *txbd = ENETC_TXBD(*tx_ring, i);
1270 txbd->flags = ENETC_TXBD_FLAGS_F;
1273 enetc_bdr_idx_inc(tx_ring, &i);
1276 tx_ring->next_to_use = i;
1281 static int enetc_xdp_frame_to_xdp_tx_swbd(struct enetc_bdr *tx_ring,
1282 struct enetc_tx_swbd *xdp_tx_arr,
1283 struct xdp_frame *xdp_frame)
1285 struct enetc_tx_swbd *xdp_tx_swbd = &xdp_tx_arr[0];
1286 struct skb_shared_info *shinfo;
1287 void *data = xdp_frame->data;
1288 int len = xdp_frame->len;
1294 dma = dma_map_single(tx_ring->dev, data, len, DMA_TO_DEVICE);
1295 if (unlikely(dma_mapping_error(tx_ring->dev, dma))) {
1296 netdev_err(tx_ring->ndev, "DMA map error\n");
1300 xdp_tx_swbd->dma = dma;
1301 xdp_tx_swbd->dir = DMA_TO_DEVICE;
1302 xdp_tx_swbd->len = len;
1303 xdp_tx_swbd->is_xdp_redirect = true;
1304 xdp_tx_swbd->is_eof = false;
1305 xdp_tx_swbd->xdp_frame = NULL;
1308 xdp_tx_swbd = &xdp_tx_arr[n];
1310 shinfo = xdp_get_shared_info_from_frame(xdp_frame);
1312 for (f = 0, frag = &shinfo->frags[0]; f < shinfo->nr_frags;
1314 data = skb_frag_address(frag);
1315 len = skb_frag_size(frag);
1317 dma = dma_map_single(tx_ring->dev, data, len, DMA_TO_DEVICE);
1318 if (unlikely(dma_mapping_error(tx_ring->dev, dma))) {
1319 /* Undo the DMA mapping for all fragments */
1321 enetc_unmap_tx_buff(tx_ring, &xdp_tx_arr[n]);
1323 netdev_err(tx_ring->ndev, "DMA map error\n");
1327 xdp_tx_swbd->dma = dma;
1328 xdp_tx_swbd->dir = DMA_TO_DEVICE;
1329 xdp_tx_swbd->len = len;
1330 xdp_tx_swbd->is_xdp_redirect = true;
1331 xdp_tx_swbd->is_eof = false;
1332 xdp_tx_swbd->xdp_frame = NULL;
1335 xdp_tx_swbd = &xdp_tx_arr[n];
1338 xdp_tx_arr[n - 1].is_eof = true;
1339 xdp_tx_arr[n - 1].xdp_frame = xdp_frame;
1344 int enetc_xdp_xmit(struct net_device *ndev, int num_frames,
1345 struct xdp_frame **frames, u32 flags)
1347 struct enetc_tx_swbd xdp_redirect_arr[ENETC_MAX_SKB_FRAGS] = {0};
1348 struct enetc_ndev_priv *priv = netdev_priv(ndev);
1349 struct enetc_bdr *tx_ring;
1350 int xdp_tx_bd_cnt, i, k;
1351 int xdp_tx_frm_cnt = 0;
1355 tx_ring = priv->xdp_tx_ring[smp_processor_id()];
1357 prefetchw(ENETC_TXBD(*tx_ring, tx_ring->next_to_use));
1359 for (k = 0; k < num_frames; k++) {
1360 xdp_tx_bd_cnt = enetc_xdp_frame_to_xdp_tx_swbd(tx_ring,
1363 if (unlikely(xdp_tx_bd_cnt < 0))
1366 if (unlikely(!enetc_xdp_tx(tx_ring, xdp_redirect_arr,
1368 for (i = 0; i < xdp_tx_bd_cnt; i++)
1369 enetc_unmap_tx_buff(tx_ring,
1370 &xdp_redirect_arr[i]);
1371 tx_ring->stats.xdp_tx_drops++;
1378 if (unlikely((flags & XDP_XMIT_FLUSH) || k != xdp_tx_frm_cnt))
1379 enetc_update_tx_ring_tail(tx_ring);
1381 tx_ring->stats.xdp_tx += xdp_tx_frm_cnt;
1383 enetc_unlock_mdio();
1385 return xdp_tx_frm_cnt;
1388 static void enetc_map_rx_buff_to_xdp(struct enetc_bdr *rx_ring, int i,
1389 struct xdp_buff *xdp_buff, u16 size)
1391 struct enetc_rx_swbd *rx_swbd = enetc_get_rx_buff(rx_ring, i, size);
1392 void *hard_start = page_address(rx_swbd->page) + rx_swbd->page_offset;
1393 struct skb_shared_info *shinfo;
1395 /* To be used for XDP_TX */
1396 rx_swbd->len = size;
1398 xdp_prepare_buff(xdp_buff, hard_start - rx_ring->buffer_offset,
1399 rx_ring->buffer_offset, size, false);
1401 shinfo = xdp_get_shared_info_from_buff(xdp_buff);
1402 shinfo->nr_frags = 0;
1405 static void enetc_add_rx_buff_to_xdp(struct enetc_bdr *rx_ring, int i,
1406 u16 size, struct xdp_buff *xdp_buff)
1408 struct skb_shared_info *shinfo = xdp_get_shared_info_from_buff(xdp_buff);
1409 struct enetc_rx_swbd *rx_swbd = enetc_get_rx_buff(rx_ring, i, size);
1410 skb_frag_t *frag = &shinfo->frags[shinfo->nr_frags];
1412 /* To be used for XDP_TX */
1413 rx_swbd->len = size;
1415 skb_frag_off_set(frag, rx_swbd->page_offset);
1416 skb_frag_size_set(frag, size);
1417 __skb_frag_set_page(frag, rx_swbd->page);
1422 static void enetc_build_xdp_buff(struct enetc_bdr *rx_ring, u32 bd_status,
1423 union enetc_rx_bd **rxbd, int *i,
1424 int *cleaned_cnt, struct xdp_buff *xdp_buff)
1426 u16 size = le16_to_cpu((*rxbd)->r.buf_len);
1428 xdp_init_buff(xdp_buff, ENETC_RXB_TRUESIZE, &rx_ring->xdp.rxq);
1430 enetc_map_rx_buff_to_xdp(rx_ring, *i, xdp_buff, size);
1432 enetc_rxbd_next(rx_ring, rxbd, i);
1434 /* not last BD in frame? */
1435 while (!(bd_status & ENETC_RXBD_LSTATUS_F)) {
1436 bd_status = le32_to_cpu((*rxbd)->r.lstatus);
1437 size = ENETC_RXB_DMA_SIZE_XDP;
1439 if (bd_status & ENETC_RXBD_LSTATUS_F) {
1441 size = le16_to_cpu((*rxbd)->r.buf_len);
1444 enetc_add_rx_buff_to_xdp(rx_ring, *i, size, xdp_buff);
1446 enetc_rxbd_next(rx_ring, rxbd, i);
1450 /* Convert RX buffer descriptors to TX buffer descriptors. These will be
1451 * recycled back into the RX ring in enetc_clean_tx_ring.
1453 static int enetc_rx_swbd_to_xdp_tx_swbd(struct enetc_tx_swbd *xdp_tx_arr,
1454 struct enetc_bdr *rx_ring,
1455 int rx_ring_first, int rx_ring_last)
1459 for (; rx_ring_first != rx_ring_last;
1460 n++, enetc_bdr_idx_inc(rx_ring, &rx_ring_first)) {
1461 struct enetc_rx_swbd *rx_swbd = &rx_ring->rx_swbd[rx_ring_first];
1462 struct enetc_tx_swbd *tx_swbd = &xdp_tx_arr[n];
1464 /* No need to dma_map, we already have DMA_BIDIRECTIONAL */
1465 tx_swbd->dma = rx_swbd->dma;
1466 tx_swbd->dir = rx_swbd->dir;
1467 tx_swbd->page = rx_swbd->page;
1468 tx_swbd->page_offset = rx_swbd->page_offset;
1469 tx_swbd->len = rx_swbd->len;
1470 tx_swbd->is_dma_page = true;
1471 tx_swbd->is_xdp_tx = true;
1472 tx_swbd->is_eof = false;
1475 /* We rely on caller providing an rx_ring_last > rx_ring_first */
1476 xdp_tx_arr[n - 1].is_eof = true;
1481 static void enetc_xdp_drop(struct enetc_bdr *rx_ring, int rx_ring_first,
1484 while (rx_ring_first != rx_ring_last) {
1485 enetc_put_rx_buff(rx_ring,
1486 &rx_ring->rx_swbd[rx_ring_first]);
1487 enetc_bdr_idx_inc(rx_ring, &rx_ring_first);
1489 rx_ring->stats.xdp_drops++;
1492 static void enetc_xdp_free(struct enetc_bdr *rx_ring, int rx_ring_first,
1495 while (rx_ring_first != rx_ring_last) {
1496 struct enetc_rx_swbd *rx_swbd = &rx_ring->rx_swbd[rx_ring_first];
1498 if (rx_swbd->page) {
1499 dma_unmap_page(rx_ring->dev, rx_swbd->dma, PAGE_SIZE,
1501 __free_page(rx_swbd->page);
1502 rx_swbd->page = NULL;
1504 enetc_bdr_idx_inc(rx_ring, &rx_ring_first);
1506 rx_ring->stats.xdp_redirect_failures++;
1509 static int enetc_clean_rx_ring_xdp(struct enetc_bdr *rx_ring,
1510 struct napi_struct *napi, int work_limit,
1511 struct bpf_prog *prog)
1513 int xdp_tx_bd_cnt, xdp_tx_frm_cnt = 0, xdp_redirect_frm_cnt = 0;
1514 struct enetc_tx_swbd xdp_tx_arr[ENETC_MAX_SKB_FRAGS] = {0};
1515 struct enetc_ndev_priv *priv = netdev_priv(rx_ring->ndev);
1516 int rx_frm_cnt = 0, rx_byte_cnt = 0;
1517 struct enetc_bdr *tx_ring;
1521 cleaned_cnt = enetc_bd_unused(rx_ring);
1522 /* next descriptor to process */
1523 i = rx_ring->next_to_clean;
1525 while (likely(rx_frm_cnt < work_limit)) {
1526 union enetc_rx_bd *rxbd, *orig_rxbd;
1527 int orig_i, orig_cleaned_cnt;
1528 struct xdp_buff xdp_buff;
1529 struct sk_buff *skb;
1530 int tmp_orig_i, err;
1533 rxbd = enetc_rxbd(rx_ring, i);
1534 bd_status = le32_to_cpu(rxbd->r.lstatus);
1538 enetc_wr_reg_hot(rx_ring->idr, BIT(rx_ring->index));
1539 dma_rmb(); /* for reading other rxbd fields */
1541 if (enetc_check_bd_errors_and_consume(rx_ring, bd_status,
1546 orig_cleaned_cnt = cleaned_cnt;
1549 enetc_build_xdp_buff(rx_ring, bd_status, &rxbd, &i,
1550 &cleaned_cnt, &xdp_buff);
1552 xdp_act = bpf_prog_run_xdp(prog, &xdp_buff);
1556 bpf_warn_invalid_xdp_action(rx_ring->ndev, prog, xdp_act);
1559 trace_xdp_exception(rx_ring->ndev, prog, xdp_act);
1562 enetc_xdp_drop(rx_ring, orig_i, i);
1566 cleaned_cnt = orig_cleaned_cnt;
1569 skb = enetc_build_skb(rx_ring, bd_status, &rxbd,
1571 ENETC_RXB_DMA_SIZE_XDP);
1575 napi_gro_receive(napi, skb);
1578 tx_ring = priv->xdp_tx_ring[rx_ring->index];
1579 xdp_tx_bd_cnt = enetc_rx_swbd_to_xdp_tx_swbd(xdp_tx_arr,
1583 if (!enetc_xdp_tx(tx_ring, xdp_tx_arr, xdp_tx_bd_cnt)) {
1584 enetc_xdp_drop(rx_ring, orig_i, i);
1585 tx_ring->stats.xdp_tx_drops++;
1587 tx_ring->stats.xdp_tx += xdp_tx_bd_cnt;
1588 rx_ring->xdp.xdp_tx_in_flight += xdp_tx_bd_cnt;
1590 /* The XDP_TX enqueue was successful, so we
1591 * need to scrub the RX software BDs because
1592 * the ownership of the buffers no longer
1593 * belongs to the RX ring, and we must prevent
1594 * enetc_refill_rx_ring() from reusing
1597 while (orig_i != i) {
1598 rx_ring->rx_swbd[orig_i].page = NULL;
1599 enetc_bdr_idx_inc(rx_ring, &orig_i);
1604 /* xdp_return_frame does not support S/G in the sense
1605 * that it leaks the fragments (__xdp_return should not
1606 * call page_frag_free only for the initial buffer).
1607 * Until XDP_REDIRECT gains support for S/G let's keep
1608 * the code structure in place, but dead. We drop the
1609 * S/G frames ourselves to avoid memory leaks which
1610 * would otherwise leave the kernel OOM.
1612 if (unlikely(cleaned_cnt - orig_cleaned_cnt != 1)) {
1613 enetc_xdp_drop(rx_ring, orig_i, i);
1614 rx_ring->stats.xdp_redirect_sg++;
1618 tmp_orig_i = orig_i;
1620 while (orig_i != i) {
1621 enetc_flip_rx_buff(rx_ring,
1622 &rx_ring->rx_swbd[orig_i]);
1623 enetc_bdr_idx_inc(rx_ring, &orig_i);
1626 err = xdp_do_redirect(rx_ring->ndev, &xdp_buff, prog);
1627 if (unlikely(err)) {
1628 enetc_xdp_free(rx_ring, tmp_orig_i, i);
1630 xdp_redirect_frm_cnt++;
1631 rx_ring->stats.xdp_redirect++;
1639 rx_ring->next_to_clean = i;
1641 rx_ring->stats.packets += rx_frm_cnt;
1642 rx_ring->stats.bytes += rx_byte_cnt;
1644 if (xdp_redirect_frm_cnt)
1648 enetc_update_tx_ring_tail(tx_ring);
1650 if (cleaned_cnt > rx_ring->xdp.xdp_tx_in_flight)
1651 enetc_refill_rx_ring(rx_ring, enetc_bd_unused(rx_ring) -
1652 rx_ring->xdp.xdp_tx_in_flight);
1657 static int enetc_poll(struct napi_struct *napi, int budget)
1659 struct enetc_int_vector
1660 *v = container_of(napi, struct enetc_int_vector, napi);
1661 struct enetc_bdr *rx_ring = &v->rx_ring;
1662 struct bpf_prog *prog;
1663 bool complete = true;
1669 for (i = 0; i < v->count_tx_rings; i++)
1670 if (!enetc_clean_tx_ring(&v->tx_ring[i], budget))
1673 prog = rx_ring->xdp.prog;
1675 work_done = enetc_clean_rx_ring_xdp(rx_ring, napi, budget, prog);
1677 work_done = enetc_clean_rx_ring(rx_ring, napi, budget);
1678 if (work_done == budget)
1681 v->rx_napi_work = true;
1684 enetc_unlock_mdio();
1688 napi_complete_done(napi, work_done);
1690 if (likely(v->rx_dim_en))
1691 enetc_rx_net_dim(v);
1693 v->rx_napi_work = false;
1695 /* enable interrupts */
1696 enetc_wr_reg_hot(v->rbier, ENETC_RBIER_RXTIE);
1698 for_each_set_bit(i, &v->tx_rings_map, ENETC_MAX_NUM_TXQS)
1699 enetc_wr_reg_hot(v->tbier_base + ENETC_BDR_OFF(i),
1702 enetc_unlock_mdio();
1707 /* Probing and Init */
1708 #define ENETC_MAX_RFS_SIZE 64
1709 void enetc_get_si_caps(struct enetc_si *si)
1711 struct enetc_hw *hw = &si->hw;
1714 /* find out how many of various resources we have to work with */
1715 val = enetc_rd(hw, ENETC_SICAPR0);
1716 si->num_rx_rings = (val >> 16) & 0xff;
1717 si->num_tx_rings = val & 0xff;
1719 val = enetc_rd(hw, ENETC_SIRFSCAPR);
1720 si->num_fs_entries = ENETC_SIRFSCAPR_GET_NUM_RFS(val);
1721 si->num_fs_entries = min(si->num_fs_entries, ENETC_MAX_RFS_SIZE);
1724 val = enetc_rd(hw, ENETC_SIPCAPR0);
1725 if (val & ENETC_SIPCAPR0_RSS) {
1728 rss = enetc_rd(hw, ENETC_SIRSSCAPR);
1729 si->num_rss = ENETC_SIRSSCAPR_GET_NUM_RSS(rss);
1732 if (val & ENETC_SIPCAPR0_QBV)
1733 si->hw_features |= ENETC_SI_F_QBV;
1735 if (val & ENETC_SIPCAPR0_PSFP)
1736 si->hw_features |= ENETC_SI_F_PSFP;
1739 static int enetc_dma_alloc_bdr(struct enetc_bdr *r, size_t bd_size)
1741 r->bd_base = dma_alloc_coherent(r->dev, r->bd_count * bd_size,
1742 &r->bd_dma_base, GFP_KERNEL);
1746 /* h/w requires 128B alignment */
1747 if (!IS_ALIGNED(r->bd_dma_base, 128)) {
1748 dma_free_coherent(r->dev, r->bd_count * bd_size, r->bd_base,
1756 static int enetc_alloc_txbdr(struct enetc_bdr *txr)
1760 txr->tx_swbd = vzalloc(txr->bd_count * sizeof(struct enetc_tx_swbd));
1764 err = enetc_dma_alloc_bdr(txr, sizeof(union enetc_tx_bd));
1768 txr->tso_headers = dma_alloc_coherent(txr->dev,
1769 txr->bd_count * TSO_HEADER_SIZE,
1770 &txr->tso_headers_dma,
1772 if (!txr->tso_headers) {
1777 txr->next_to_clean = 0;
1778 txr->next_to_use = 0;
1783 dma_free_coherent(txr->dev, txr->bd_count * sizeof(union enetc_tx_bd),
1784 txr->bd_base, txr->bd_dma_base);
1785 txr->bd_base = NULL;
1787 vfree(txr->tx_swbd);
1788 txr->tx_swbd = NULL;
1793 static void enetc_free_txbdr(struct enetc_bdr *txr)
1797 for (i = 0; i < txr->bd_count; i++)
1798 enetc_free_tx_frame(txr, &txr->tx_swbd[i]);
1800 size = txr->bd_count * sizeof(union enetc_tx_bd);
1802 dma_free_coherent(txr->dev, txr->bd_count * TSO_HEADER_SIZE,
1803 txr->tso_headers, txr->tso_headers_dma);
1804 txr->tso_headers = NULL;
1806 dma_free_coherent(txr->dev, size, txr->bd_base, txr->bd_dma_base);
1807 txr->bd_base = NULL;
1809 vfree(txr->tx_swbd);
1810 txr->tx_swbd = NULL;
1813 static int enetc_alloc_tx_resources(struct enetc_ndev_priv *priv)
1817 for (i = 0; i < priv->num_tx_rings; i++) {
1818 err = enetc_alloc_txbdr(priv->tx_ring[i]);
1828 enetc_free_txbdr(priv->tx_ring[i]);
1833 static void enetc_free_tx_resources(struct enetc_ndev_priv *priv)
1837 for (i = 0; i < priv->num_tx_rings; i++)
1838 enetc_free_txbdr(priv->tx_ring[i]);
1841 static int enetc_alloc_rxbdr(struct enetc_bdr *rxr, bool extended)
1843 size_t size = sizeof(union enetc_rx_bd);
1846 rxr->rx_swbd = vzalloc(rxr->bd_count * sizeof(struct enetc_rx_swbd));
1853 err = enetc_dma_alloc_bdr(rxr, size);
1855 vfree(rxr->rx_swbd);
1859 rxr->next_to_clean = 0;
1860 rxr->next_to_use = 0;
1861 rxr->next_to_alloc = 0;
1862 rxr->ext_en = extended;
1867 static void enetc_free_rxbdr(struct enetc_bdr *rxr)
1871 size = rxr->bd_count * sizeof(union enetc_rx_bd);
1873 dma_free_coherent(rxr->dev, size, rxr->bd_base, rxr->bd_dma_base);
1874 rxr->bd_base = NULL;
1876 vfree(rxr->rx_swbd);
1877 rxr->rx_swbd = NULL;
1880 static int enetc_alloc_rx_resources(struct enetc_ndev_priv *priv)
1882 bool extended = !!(priv->active_offloads & ENETC_F_RX_TSTAMP);
1885 for (i = 0; i < priv->num_rx_rings; i++) {
1886 err = enetc_alloc_rxbdr(priv->rx_ring[i], extended);
1896 enetc_free_rxbdr(priv->rx_ring[i]);
1901 static void enetc_free_rx_resources(struct enetc_ndev_priv *priv)
1905 for (i = 0; i < priv->num_rx_rings; i++)
1906 enetc_free_rxbdr(priv->rx_ring[i]);
1909 static void enetc_free_tx_ring(struct enetc_bdr *tx_ring)
1913 if (!tx_ring->tx_swbd)
1916 for (i = 0; i < tx_ring->bd_count; i++) {
1917 struct enetc_tx_swbd *tx_swbd = &tx_ring->tx_swbd[i];
1919 enetc_free_tx_frame(tx_ring, tx_swbd);
1922 tx_ring->next_to_clean = 0;
1923 tx_ring->next_to_use = 0;
1926 static void enetc_free_rx_ring(struct enetc_bdr *rx_ring)
1930 if (!rx_ring->rx_swbd)
1933 for (i = 0; i < rx_ring->bd_count; i++) {
1934 struct enetc_rx_swbd *rx_swbd = &rx_ring->rx_swbd[i];
1939 dma_unmap_page(rx_ring->dev, rx_swbd->dma, PAGE_SIZE,
1941 __free_page(rx_swbd->page);
1942 rx_swbd->page = NULL;
1945 rx_ring->next_to_clean = 0;
1946 rx_ring->next_to_use = 0;
1947 rx_ring->next_to_alloc = 0;
1950 static void enetc_free_rxtx_rings(struct enetc_ndev_priv *priv)
1954 for (i = 0; i < priv->num_rx_rings; i++)
1955 enetc_free_rx_ring(priv->rx_ring[i]);
1957 for (i = 0; i < priv->num_tx_rings; i++)
1958 enetc_free_tx_ring(priv->tx_ring[i]);
1961 static int enetc_setup_default_rss_table(struct enetc_si *si, int num_groups)
1966 rss_table = kmalloc_array(si->num_rss, sizeof(*rss_table), GFP_KERNEL);
1970 /* Set up RSS table defaults */
1971 for (i = 0; i < si->num_rss; i++)
1972 rss_table[i] = i % num_groups;
1974 enetc_set_rss_table(si, rss_table, si->num_rss);
1981 int enetc_configure_si(struct enetc_ndev_priv *priv)
1983 struct enetc_si *si = priv->si;
1984 struct enetc_hw *hw = &si->hw;
1987 /* set SI cache attributes */
1988 enetc_wr(hw, ENETC_SICAR0,
1989 ENETC_SICAR_RD_COHERENT | ENETC_SICAR_WR_COHERENT);
1990 enetc_wr(hw, ENETC_SICAR1, ENETC_SICAR_MSI);
1992 enetc_wr(hw, ENETC_SIMR, ENETC_SIMR_EN);
1995 err = enetc_setup_default_rss_table(si, priv->num_rx_rings);
2003 void enetc_init_si_rings_params(struct enetc_ndev_priv *priv)
2005 struct enetc_si *si = priv->si;
2006 int cpus = num_online_cpus();
2008 priv->tx_bd_count = ENETC_TX_RING_DEFAULT_SIZE;
2009 priv->rx_bd_count = ENETC_RX_RING_DEFAULT_SIZE;
2011 /* Enable all available TX rings in order to configure as many
2012 * priorities as possible, when needed.
2013 * TODO: Make # of TX rings run-time configurable
2015 priv->num_rx_rings = min_t(int, cpus, si->num_rx_rings);
2016 priv->num_tx_rings = si->num_tx_rings;
2017 priv->bdr_int_num = cpus;
2018 priv->ic_mode = ENETC_IC_RX_ADAPTIVE | ENETC_IC_TX_MANUAL;
2019 priv->tx_ictt = ENETC_TXIC_TIMETHR;
2022 int enetc_alloc_si_resources(struct enetc_ndev_priv *priv)
2024 struct enetc_si *si = priv->si;
2026 priv->cls_rules = kcalloc(si->num_fs_entries, sizeof(*priv->cls_rules),
2028 if (!priv->cls_rules)
2034 void enetc_free_si_resources(struct enetc_ndev_priv *priv)
2036 kfree(priv->cls_rules);
2039 static void enetc_setup_txbdr(struct enetc_hw *hw, struct enetc_bdr *tx_ring)
2041 int idx = tx_ring->index;
2044 enetc_txbdr_wr(hw, idx, ENETC_TBBAR0,
2045 lower_32_bits(tx_ring->bd_dma_base));
2047 enetc_txbdr_wr(hw, idx, ENETC_TBBAR1,
2048 upper_32_bits(tx_ring->bd_dma_base));
2050 WARN_ON(!IS_ALIGNED(tx_ring->bd_count, 64)); /* multiple of 64 */
2051 enetc_txbdr_wr(hw, idx, ENETC_TBLENR,
2052 ENETC_RTBLENR_LEN(tx_ring->bd_count));
2054 /* clearing PI/CI registers for Tx not supported, adjust sw indexes */
2055 tx_ring->next_to_use = enetc_txbdr_rd(hw, idx, ENETC_TBPIR);
2056 tx_ring->next_to_clean = enetc_txbdr_rd(hw, idx, ENETC_TBCIR);
2058 /* enable Tx ints by setting pkt thr to 1 */
2059 enetc_txbdr_wr(hw, idx, ENETC_TBICR0, ENETC_TBICR0_ICEN | 0x1);
2061 tbmr = ENETC_TBMR_EN;
2062 if (tx_ring->ndev->features & NETIF_F_HW_VLAN_CTAG_TX)
2063 tbmr |= ENETC_TBMR_VIH;
2066 enetc_txbdr_wr(hw, idx, ENETC_TBMR, tbmr);
2068 tx_ring->tpir = hw->reg + ENETC_BDR(TX, idx, ENETC_TBPIR);
2069 tx_ring->tcir = hw->reg + ENETC_BDR(TX, idx, ENETC_TBCIR);
2070 tx_ring->idr = hw->reg + ENETC_SITXIDR;
2073 static void enetc_setup_rxbdr(struct enetc_hw *hw, struct enetc_bdr *rx_ring)
2075 int idx = rx_ring->index;
2078 enetc_rxbdr_wr(hw, idx, ENETC_RBBAR0,
2079 lower_32_bits(rx_ring->bd_dma_base));
2081 enetc_rxbdr_wr(hw, idx, ENETC_RBBAR1,
2082 upper_32_bits(rx_ring->bd_dma_base));
2084 WARN_ON(!IS_ALIGNED(rx_ring->bd_count, 64)); /* multiple of 64 */
2085 enetc_rxbdr_wr(hw, idx, ENETC_RBLENR,
2086 ENETC_RTBLENR_LEN(rx_ring->bd_count));
2088 if (rx_ring->xdp.prog)
2089 enetc_rxbdr_wr(hw, idx, ENETC_RBBSR, ENETC_RXB_DMA_SIZE_XDP);
2091 enetc_rxbdr_wr(hw, idx, ENETC_RBBSR, ENETC_RXB_DMA_SIZE);
2093 enetc_rxbdr_wr(hw, idx, ENETC_RBPIR, 0);
2095 /* enable Rx ints by setting pkt thr to 1 */
2096 enetc_rxbdr_wr(hw, idx, ENETC_RBICR0, ENETC_RBICR0_ICEN | 0x1);
2098 rbmr = ENETC_RBMR_EN;
2100 if (rx_ring->ext_en)
2101 rbmr |= ENETC_RBMR_BDS;
2103 if (rx_ring->ndev->features & NETIF_F_HW_VLAN_CTAG_RX)
2104 rbmr |= ENETC_RBMR_VTE;
2106 rx_ring->rcir = hw->reg + ENETC_BDR(RX, idx, ENETC_RBCIR);
2107 rx_ring->idr = hw->reg + ENETC_SIRXIDR;
2110 enetc_refill_rx_ring(rx_ring, enetc_bd_unused(rx_ring));
2111 enetc_unlock_mdio();
2114 enetc_rxbdr_wr(hw, idx, ENETC_RBMR, rbmr);
2117 static void enetc_setup_bdrs(struct enetc_ndev_priv *priv)
2121 for (i = 0; i < priv->num_tx_rings; i++)
2122 enetc_setup_txbdr(&priv->si->hw, priv->tx_ring[i]);
2124 for (i = 0; i < priv->num_rx_rings; i++)
2125 enetc_setup_rxbdr(&priv->si->hw, priv->rx_ring[i]);
2128 static void enetc_clear_rxbdr(struct enetc_hw *hw, struct enetc_bdr *rx_ring)
2130 int idx = rx_ring->index;
2132 /* disable EN bit on ring */
2133 enetc_rxbdr_wr(hw, idx, ENETC_RBMR, 0);
2136 static void enetc_clear_txbdr(struct enetc_hw *hw, struct enetc_bdr *tx_ring)
2138 int delay = 8, timeout = 100;
2139 int idx = tx_ring->index;
2141 /* disable EN bit on ring */
2142 enetc_txbdr_wr(hw, idx, ENETC_TBMR, 0);
2144 /* wait for busy to clear */
2145 while (delay < timeout &&
2146 enetc_txbdr_rd(hw, idx, ENETC_TBSR) & ENETC_TBSR_BUSY) {
2151 if (delay >= timeout)
2152 netdev_warn(tx_ring->ndev, "timeout for tx ring #%d clear\n",
2156 static void enetc_clear_bdrs(struct enetc_ndev_priv *priv)
2160 for (i = 0; i < priv->num_tx_rings; i++)
2161 enetc_clear_txbdr(&priv->si->hw, priv->tx_ring[i]);
2163 for (i = 0; i < priv->num_rx_rings; i++)
2164 enetc_clear_rxbdr(&priv->si->hw, priv->rx_ring[i]);
2169 static int enetc_setup_irqs(struct enetc_ndev_priv *priv)
2171 struct pci_dev *pdev = priv->si->pdev;
2174 for (i = 0; i < priv->bdr_int_num; i++) {
2175 int irq = pci_irq_vector(pdev, ENETC_BDR_INT_BASE_IDX + i);
2176 struct enetc_int_vector *v = priv->int_vector[i];
2177 int entry = ENETC_BDR_INT_BASE_IDX + i;
2178 struct enetc_hw *hw = &priv->si->hw;
2180 snprintf(v->name, sizeof(v->name), "%s-rxtx%d",
2181 priv->ndev->name, i);
2182 err = request_irq(irq, enetc_msix, 0, v->name, v);
2184 dev_err(priv->dev, "request_irq() failed!\n");
2189 v->tbier_base = hw->reg + ENETC_BDR(TX, 0, ENETC_TBIER);
2190 v->rbier = hw->reg + ENETC_BDR(RX, i, ENETC_RBIER);
2191 v->ricr1 = hw->reg + ENETC_BDR(RX, i, ENETC_RBICR1);
2193 enetc_wr(hw, ENETC_SIMSIRRV(i), entry);
2195 for (j = 0; j < v->count_tx_rings; j++) {
2196 int idx = v->tx_ring[j].index;
2198 enetc_wr(hw, ENETC_SIMSITRV(idx), entry);
2200 irq_set_affinity_hint(irq, get_cpu_mask(i % num_online_cpus()));
2207 int irq = pci_irq_vector(pdev, ENETC_BDR_INT_BASE_IDX + i);
2209 irq_set_affinity_hint(irq, NULL);
2210 free_irq(irq, priv->int_vector[i]);
2216 static void enetc_free_irqs(struct enetc_ndev_priv *priv)
2218 struct pci_dev *pdev = priv->si->pdev;
2221 for (i = 0; i < priv->bdr_int_num; i++) {
2222 int irq = pci_irq_vector(pdev, ENETC_BDR_INT_BASE_IDX + i);
2224 irq_set_affinity_hint(irq, NULL);
2225 free_irq(irq, priv->int_vector[i]);
2229 static void enetc_setup_interrupts(struct enetc_ndev_priv *priv)
2231 struct enetc_hw *hw = &priv->si->hw;
2235 /* enable Tx & Rx event indication */
2237 (ENETC_IC_RX_MANUAL | ENETC_IC_RX_ADAPTIVE)) {
2238 icpt = ENETC_RBICR0_SET_ICPT(ENETC_RXIC_PKTTHR);
2239 /* init to non-0 minimum, will be adjusted later */
2242 icpt = 0x1; /* enable Rx ints by setting pkt thr to 1 */
2246 for (i = 0; i < priv->num_rx_rings; i++) {
2247 enetc_rxbdr_wr(hw, i, ENETC_RBICR1, ictt);
2248 enetc_rxbdr_wr(hw, i, ENETC_RBICR0, ENETC_RBICR0_ICEN | icpt);
2249 enetc_rxbdr_wr(hw, i, ENETC_RBIER, ENETC_RBIER_RXTIE);
2252 if (priv->ic_mode & ENETC_IC_TX_MANUAL)
2253 icpt = ENETC_TBICR0_SET_ICPT(ENETC_TXIC_PKTTHR);
2255 icpt = 0x1; /* enable Tx ints by setting pkt thr to 1 */
2257 for (i = 0; i < priv->num_tx_rings; i++) {
2258 enetc_txbdr_wr(hw, i, ENETC_TBICR1, priv->tx_ictt);
2259 enetc_txbdr_wr(hw, i, ENETC_TBICR0, ENETC_TBICR0_ICEN | icpt);
2260 enetc_txbdr_wr(hw, i, ENETC_TBIER, ENETC_TBIER_TXTIE);
2264 static void enetc_clear_interrupts(struct enetc_ndev_priv *priv)
2268 for (i = 0; i < priv->num_tx_rings; i++)
2269 enetc_txbdr_wr(&priv->si->hw, i, ENETC_TBIER, 0);
2271 for (i = 0; i < priv->num_rx_rings; i++)
2272 enetc_rxbdr_wr(&priv->si->hw, i, ENETC_RBIER, 0);
2275 static int enetc_phylink_connect(struct net_device *ndev)
2277 struct enetc_ndev_priv *priv = netdev_priv(ndev);
2278 struct ethtool_eee edata;
2282 return 0; /* phy-less mode */
2284 err = phylink_of_phy_connect(priv->phylink, priv->dev->of_node, 0);
2286 dev_err(&ndev->dev, "could not attach to PHY\n");
2290 /* disable EEE autoneg, until ENETC driver supports it */
2291 memset(&edata, 0, sizeof(struct ethtool_eee));
2292 phylink_ethtool_set_eee(priv->phylink, &edata);
2297 static void enetc_tx_onestep_tstamp(struct work_struct *work)
2299 struct enetc_ndev_priv *priv;
2300 struct sk_buff *skb;
2302 priv = container_of(work, struct enetc_ndev_priv, tx_onestep_tstamp);
2304 netif_tx_lock(priv->ndev);
2306 clear_bit_unlock(ENETC_TX_ONESTEP_TSTAMP_IN_PROGRESS, &priv->flags);
2307 skb = skb_dequeue(&priv->tx_skbs);
2309 enetc_start_xmit(skb, priv->ndev);
2311 netif_tx_unlock(priv->ndev);
2314 static void enetc_tx_onestep_tstamp_init(struct enetc_ndev_priv *priv)
2316 INIT_WORK(&priv->tx_onestep_tstamp, enetc_tx_onestep_tstamp);
2317 skb_queue_head_init(&priv->tx_skbs);
2320 void enetc_start(struct net_device *ndev)
2322 struct enetc_ndev_priv *priv = netdev_priv(ndev);
2325 enetc_setup_interrupts(priv);
2327 for (i = 0; i < priv->bdr_int_num; i++) {
2328 int irq = pci_irq_vector(priv->si->pdev,
2329 ENETC_BDR_INT_BASE_IDX + i);
2331 napi_enable(&priv->int_vector[i]->napi);
2336 phylink_start(priv->phylink);
2338 netif_carrier_on(ndev);
2340 netif_tx_start_all_queues(ndev);
2343 int enetc_open(struct net_device *ndev)
2345 struct enetc_ndev_priv *priv = netdev_priv(ndev);
2346 int num_stack_tx_queues;
2349 err = enetc_setup_irqs(priv);
2353 err = enetc_phylink_connect(ndev);
2355 goto err_phy_connect;
2357 err = enetc_alloc_tx_resources(priv);
2361 err = enetc_alloc_rx_resources(priv);
2365 num_stack_tx_queues = enetc_num_stack_tx_queues(priv);
2367 err = netif_set_real_num_tx_queues(ndev, num_stack_tx_queues);
2369 goto err_set_queues;
2371 err = netif_set_real_num_rx_queues(ndev, priv->num_rx_rings);
2373 goto err_set_queues;
2375 enetc_tx_onestep_tstamp_init(priv);
2376 enetc_setup_bdrs(priv);
2382 enetc_free_rx_resources(priv);
2384 enetc_free_tx_resources(priv);
2387 phylink_disconnect_phy(priv->phylink);
2389 enetc_free_irqs(priv);
2394 void enetc_stop(struct net_device *ndev)
2396 struct enetc_ndev_priv *priv = netdev_priv(ndev);
2399 netif_tx_stop_all_queues(ndev);
2401 for (i = 0; i < priv->bdr_int_num; i++) {
2402 int irq = pci_irq_vector(priv->si->pdev,
2403 ENETC_BDR_INT_BASE_IDX + i);
2406 napi_synchronize(&priv->int_vector[i]->napi);
2407 napi_disable(&priv->int_vector[i]->napi);
2411 phylink_stop(priv->phylink);
2413 netif_carrier_off(ndev);
2415 enetc_clear_interrupts(priv);
2418 int enetc_close(struct net_device *ndev)
2420 struct enetc_ndev_priv *priv = netdev_priv(ndev);
2423 enetc_clear_bdrs(priv);
2426 phylink_disconnect_phy(priv->phylink);
2427 enetc_free_rxtx_rings(priv);
2428 enetc_free_rx_resources(priv);
2429 enetc_free_tx_resources(priv);
2430 enetc_free_irqs(priv);
2435 int enetc_setup_tc_mqprio(struct net_device *ndev, void *type_data)
2437 struct enetc_ndev_priv *priv = netdev_priv(ndev);
2438 struct tc_mqprio_qopt *mqprio = type_data;
2439 struct enetc_bdr *tx_ring;
2440 int num_stack_tx_queues;
2444 num_stack_tx_queues = enetc_num_stack_tx_queues(priv);
2445 mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS;
2446 num_tc = mqprio->num_tc;
2449 netdev_reset_tc(ndev);
2450 netif_set_real_num_tx_queues(ndev, num_stack_tx_queues);
2452 /* Reset all ring priorities to 0 */
2453 for (i = 0; i < priv->num_tx_rings; i++) {
2454 tx_ring = priv->tx_ring[i];
2455 enetc_set_bdr_prio(&priv->si->hw, tx_ring->index, 0);
2461 /* Check if we have enough BD rings available to accommodate all TCs */
2462 if (num_tc > num_stack_tx_queues) {
2463 netdev_err(ndev, "Max %d traffic classes supported\n",
2464 priv->num_tx_rings);
2468 /* For the moment, we use only one BD ring per TC.
2470 * Configure num_tc BD rings with increasing priorities.
2472 for (i = 0; i < num_tc; i++) {
2473 tx_ring = priv->tx_ring[i];
2474 enetc_set_bdr_prio(&priv->si->hw, tx_ring->index, i);
2477 /* Reset the number of netdev queues based on the TC count */
2478 netif_set_real_num_tx_queues(ndev, num_tc);
2480 netdev_set_num_tc(ndev, num_tc);
2482 /* Each TC is associated with one netdev queue */
2483 for (i = 0; i < num_tc; i++)
2484 netdev_set_tc_queue(ndev, i, 1, i);
2489 static int enetc_setup_xdp_prog(struct net_device *dev, struct bpf_prog *prog,
2490 struct netlink_ext_ack *extack)
2492 struct enetc_ndev_priv *priv = netdev_priv(dev);
2493 struct bpf_prog *old_prog;
2497 /* The buffer layout is changing, so we need to drain the old
2498 * RX buffers and seed new ones.
2500 is_up = netif_running(dev);
2504 old_prog = xchg(&priv->xdp_prog, prog);
2506 bpf_prog_put(old_prog);
2508 for (i = 0; i < priv->num_rx_rings; i++) {
2509 struct enetc_bdr *rx_ring = priv->rx_ring[i];
2511 rx_ring->xdp.prog = prog;
2514 rx_ring->buffer_offset = XDP_PACKET_HEADROOM;
2516 rx_ring->buffer_offset = ENETC_RXB_PAD;
2520 return dev_open(dev, extack);
2525 int enetc_setup_bpf(struct net_device *dev, struct netdev_bpf *xdp)
2527 switch (xdp->command) {
2528 case XDP_SETUP_PROG:
2529 return enetc_setup_xdp_prog(dev, xdp->prog, xdp->extack);
2537 struct net_device_stats *enetc_get_stats(struct net_device *ndev)
2539 struct enetc_ndev_priv *priv = netdev_priv(ndev);
2540 struct net_device_stats *stats = &ndev->stats;
2541 unsigned long packets = 0, bytes = 0;
2542 unsigned long tx_dropped = 0;
2545 for (i = 0; i < priv->num_rx_rings; i++) {
2546 packets += priv->rx_ring[i]->stats.packets;
2547 bytes += priv->rx_ring[i]->stats.bytes;
2550 stats->rx_packets = packets;
2551 stats->rx_bytes = bytes;
2555 for (i = 0; i < priv->num_tx_rings; i++) {
2556 packets += priv->tx_ring[i]->stats.packets;
2557 bytes += priv->tx_ring[i]->stats.bytes;
2558 tx_dropped += priv->tx_ring[i]->stats.win_drop;
2561 stats->tx_packets = packets;
2562 stats->tx_bytes = bytes;
2563 stats->tx_dropped = tx_dropped;
2568 static int enetc_set_rss(struct net_device *ndev, int en)
2570 struct enetc_ndev_priv *priv = netdev_priv(ndev);
2571 struct enetc_hw *hw = &priv->si->hw;
2574 enetc_wr(hw, ENETC_SIRBGCR, priv->num_rx_rings);
2576 reg = enetc_rd(hw, ENETC_SIMR);
2577 reg &= ~ENETC_SIMR_RSSE;
2578 reg |= (en) ? ENETC_SIMR_RSSE : 0;
2579 enetc_wr(hw, ENETC_SIMR, reg);
2584 static void enetc_enable_rxvlan(struct net_device *ndev, bool en)
2586 struct enetc_ndev_priv *priv = netdev_priv(ndev);
2589 for (i = 0; i < priv->num_rx_rings; i++)
2590 enetc_bdr_enable_rxvlan(&priv->si->hw, i, en);
2593 static void enetc_enable_txvlan(struct net_device *ndev, bool en)
2595 struct enetc_ndev_priv *priv = netdev_priv(ndev);
2598 for (i = 0; i < priv->num_tx_rings; i++)
2599 enetc_bdr_enable_txvlan(&priv->si->hw, i, en);
2602 void enetc_set_features(struct net_device *ndev, netdev_features_t features)
2604 netdev_features_t changed = ndev->features ^ features;
2606 if (changed & NETIF_F_RXHASH)
2607 enetc_set_rss(ndev, !!(features & NETIF_F_RXHASH));
2609 if (changed & NETIF_F_HW_VLAN_CTAG_RX)
2610 enetc_enable_rxvlan(ndev,
2611 !!(features & NETIF_F_HW_VLAN_CTAG_RX));
2613 if (changed & NETIF_F_HW_VLAN_CTAG_TX)
2614 enetc_enable_txvlan(ndev,
2615 !!(features & NETIF_F_HW_VLAN_CTAG_TX));
2618 #ifdef CONFIG_FSL_ENETC_PTP_CLOCK
2619 static int enetc_hwtstamp_set(struct net_device *ndev, struct ifreq *ifr)
2621 struct enetc_ndev_priv *priv = netdev_priv(ndev);
2622 struct hwtstamp_config config;
2625 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
2628 switch (config.tx_type) {
2629 case HWTSTAMP_TX_OFF:
2630 priv->active_offloads &= ~ENETC_F_TX_TSTAMP_MASK;
2632 case HWTSTAMP_TX_ON:
2633 priv->active_offloads &= ~ENETC_F_TX_TSTAMP_MASK;
2634 priv->active_offloads |= ENETC_F_TX_TSTAMP;
2636 case HWTSTAMP_TX_ONESTEP_SYNC:
2637 priv->active_offloads &= ~ENETC_F_TX_TSTAMP_MASK;
2638 priv->active_offloads |= ENETC_F_TX_ONESTEP_SYNC_TSTAMP;
2644 ao = priv->active_offloads;
2645 switch (config.rx_filter) {
2646 case HWTSTAMP_FILTER_NONE:
2647 priv->active_offloads &= ~ENETC_F_RX_TSTAMP;
2650 priv->active_offloads |= ENETC_F_RX_TSTAMP;
2651 config.rx_filter = HWTSTAMP_FILTER_ALL;
2654 if (netif_running(ndev) && ao != priv->active_offloads) {
2659 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
2663 static int enetc_hwtstamp_get(struct net_device *ndev, struct ifreq *ifr)
2665 struct enetc_ndev_priv *priv = netdev_priv(ndev);
2666 struct hwtstamp_config config;
2670 if (priv->active_offloads & ENETC_F_TX_ONESTEP_SYNC_TSTAMP)
2671 config.tx_type = HWTSTAMP_TX_ONESTEP_SYNC;
2672 else if (priv->active_offloads & ENETC_F_TX_TSTAMP)
2673 config.tx_type = HWTSTAMP_TX_ON;
2675 config.tx_type = HWTSTAMP_TX_OFF;
2677 config.rx_filter = (priv->active_offloads & ENETC_F_RX_TSTAMP) ?
2678 HWTSTAMP_FILTER_ALL : HWTSTAMP_FILTER_NONE;
2680 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
2685 int enetc_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd)
2687 struct enetc_ndev_priv *priv = netdev_priv(ndev);
2688 #ifdef CONFIG_FSL_ENETC_PTP_CLOCK
2689 if (cmd == SIOCSHWTSTAMP)
2690 return enetc_hwtstamp_set(ndev, rq);
2691 if (cmd == SIOCGHWTSTAMP)
2692 return enetc_hwtstamp_get(ndev, rq);
2698 return phylink_mii_ioctl(priv->phylink, rq, cmd);
2701 int enetc_alloc_msix(struct enetc_ndev_priv *priv)
2703 struct pci_dev *pdev = priv->si->pdev;
2704 int first_xdp_tx_ring;
2705 int i, n, err, nvec;
2708 nvec = ENETC_BDR_INT_BASE_IDX + priv->bdr_int_num;
2709 /* allocate MSIX for both messaging and Rx/Tx interrupts */
2710 n = pci_alloc_irq_vectors(pdev, nvec, nvec, PCI_IRQ_MSIX);
2718 /* # of tx rings per int vector */
2719 v_tx_rings = priv->num_tx_rings / priv->bdr_int_num;
2721 for (i = 0; i < priv->bdr_int_num; i++) {
2722 struct enetc_int_vector *v;
2723 struct enetc_bdr *bdr;
2726 v = kzalloc(struct_size(v, tx_ring, v_tx_rings), GFP_KERNEL);
2732 priv->int_vector[i] = v;
2736 bdr->ndev = priv->ndev;
2737 bdr->dev = priv->dev;
2738 bdr->bd_count = priv->rx_bd_count;
2739 bdr->buffer_offset = ENETC_RXB_PAD;
2740 priv->rx_ring[i] = bdr;
2742 err = xdp_rxq_info_reg(&bdr->xdp.rxq, priv->ndev, i, 0);
2748 err = xdp_rxq_info_reg_mem_model(&bdr->xdp.rxq,
2749 MEM_TYPE_PAGE_SHARED, NULL);
2751 xdp_rxq_info_unreg(&bdr->xdp.rxq);
2756 /* init defaults for adaptive IC */
2757 if (priv->ic_mode & ENETC_IC_RX_ADAPTIVE) {
2759 v->rx_dim_en = true;
2761 INIT_WORK(&v->rx_dim.work, enetc_rx_dim_work);
2762 netif_napi_add(priv->ndev, &v->napi, enetc_poll,
2764 v->count_tx_rings = v_tx_rings;
2766 for (j = 0; j < v_tx_rings; j++) {
2769 /* default tx ring mapping policy */
2770 idx = priv->bdr_int_num * j + i;
2771 __set_bit(idx, &v->tx_rings_map);
2772 bdr = &v->tx_ring[j];
2774 bdr->ndev = priv->ndev;
2775 bdr->dev = priv->dev;
2776 bdr->bd_count = priv->tx_bd_count;
2777 priv->tx_ring[idx] = bdr;
2781 first_xdp_tx_ring = priv->num_tx_rings - num_possible_cpus();
2782 priv->xdp_tx_ring = &priv->tx_ring[first_xdp_tx_ring];
2788 struct enetc_int_vector *v = priv->int_vector[i];
2789 struct enetc_bdr *rx_ring = &v->rx_ring;
2791 xdp_rxq_info_unreg_mem_model(&rx_ring->xdp.rxq);
2792 xdp_rxq_info_unreg(&rx_ring->xdp.rxq);
2793 netif_napi_del(&v->napi);
2794 cancel_work_sync(&v->rx_dim.work);
2798 pci_free_irq_vectors(pdev);
2803 void enetc_free_msix(struct enetc_ndev_priv *priv)
2807 for (i = 0; i < priv->bdr_int_num; i++) {
2808 struct enetc_int_vector *v = priv->int_vector[i];
2809 struct enetc_bdr *rx_ring = &v->rx_ring;
2811 xdp_rxq_info_unreg_mem_model(&rx_ring->xdp.rxq);
2812 xdp_rxq_info_unreg(&rx_ring->xdp.rxq);
2813 netif_napi_del(&v->napi);
2814 cancel_work_sync(&v->rx_dim.work);
2817 for (i = 0; i < priv->num_rx_rings; i++)
2818 priv->rx_ring[i] = NULL;
2820 for (i = 0; i < priv->num_tx_rings; i++)
2821 priv->tx_ring[i] = NULL;
2823 for (i = 0; i < priv->bdr_int_num; i++) {
2824 kfree(priv->int_vector[i]);
2825 priv->int_vector[i] = NULL;
2828 /* disable all MSIX for this device */
2829 pci_free_irq_vectors(priv->si->pdev);
2832 static void enetc_kfree_si(struct enetc_si *si)
2834 char *p = (char *)si - si->pad;
2839 static void enetc_detect_errata(struct enetc_si *si)
2841 if (si->pdev->revision == ENETC_REV1)
2842 si->errata = ENETC_ERR_VLAN_ISOL | ENETC_ERR_UCMCSWP;
2845 int enetc_pci_probe(struct pci_dev *pdev, const char *name, int sizeof_priv)
2847 struct enetc_si *si, *p;
2848 struct enetc_hw *hw;
2853 err = pci_enable_device_mem(pdev);
2855 return dev_err_probe(&pdev->dev, err, "device enable failed\n");
2857 /* set up for high or low dma */
2858 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
2860 dev_err(&pdev->dev, "DMA configuration failed: 0x%x\n", err);
2864 err = pci_request_mem_regions(pdev, name);
2866 dev_err(&pdev->dev, "pci_request_regions failed err=%d\n", err);
2867 goto err_pci_mem_reg;
2870 pci_set_master(pdev);
2872 alloc_size = sizeof(struct enetc_si);
2874 /* align priv to 32B */
2875 alloc_size = ALIGN(alloc_size, ENETC_SI_ALIGN);
2876 alloc_size += sizeof_priv;
2878 /* force 32B alignment for enetc_si */
2879 alloc_size += ENETC_SI_ALIGN - 1;
2881 p = kzalloc(alloc_size, GFP_KERNEL);
2887 si = PTR_ALIGN(p, ENETC_SI_ALIGN);
2888 si->pad = (char *)si - (char *)p;
2890 pci_set_drvdata(pdev, si);
2894 len = pci_resource_len(pdev, ENETC_BAR_REGS);
2895 hw->reg = ioremap(pci_resource_start(pdev, ENETC_BAR_REGS), len);
2898 dev_err(&pdev->dev, "ioremap() failed\n");
2901 if (len > ENETC_PORT_BASE)
2902 hw->port = hw->reg + ENETC_PORT_BASE;
2903 if (len > ENETC_GLOBAL_BASE)
2904 hw->global = hw->reg + ENETC_GLOBAL_BASE;
2906 enetc_detect_errata(si);
2913 pci_release_mem_regions(pdev);
2916 pci_disable_device(pdev);
2921 void enetc_pci_remove(struct pci_dev *pdev)
2923 struct enetc_si *si = pci_get_drvdata(pdev);
2924 struct enetc_hw *hw = &si->hw;
2928 pci_release_mem_regions(pdev);
2929 pci_disable_device(pdev);