1 /* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
2 /* Copyright 2014-2016 Freescale Semiconductor Inc.
3 * Copyright 2016-2020 NXP
9 #include <linux/netdevice.h>
10 #include <linux/if_vlan.h>
11 #include <linux/fsl/mc.h>
13 #include <soc/fsl/dpaa2-io.h>
14 #include <soc/fsl/dpaa2-fd.h>
18 #include "dpaa2-eth-trace.h"
19 #include "dpaa2-eth-debugfs.h"
20 #include "dpaa2-mac.h"
22 #define DPAA2_WRIOP_VERSION(x, y, z) ((x) << 10 | (y) << 5 | (z) << 0)
24 #define DPAA2_ETH_STORE_SIZE 16
26 /* Maximum number of scatter-gather entries in an ingress frame,
27 * considering the maximum receive frame size is 64K
29 #define DPAA2_ETH_MAX_SG_ENTRIES ((64 * 1024) / DPAA2_ETH_RX_BUF_SIZE)
31 /* Maximum acceptable MTU value. It is in direct relation with the hardware
32 * enforced Max Frame Length (currently 10k).
34 #define DPAA2_ETH_MFL (10 * 1024)
35 #define DPAA2_ETH_MAX_MTU (DPAA2_ETH_MFL - VLAN_ETH_HLEN)
36 /* Convert L3 MTU to L2 MFL */
37 #define DPAA2_ETH_L2_MAX_FRM(mtu) ((mtu) + VLAN_ETH_HLEN)
39 /* Set the taildrop threshold (in bytes) to allow the enqueue of several jumbo
40 * frames in the Rx queues (length of the current frame is not
41 * taken into account when making the taildrop decision)
43 #define DPAA2_ETH_TAILDROP_THRESH (64 * 1024)
45 /* Maximum number of Tx confirmation frames to be processed
46 * in a single NAPI call
48 #define DPAA2_ETH_TXCONF_PER_NAPI 256
50 /* Buffer quota per queue. Must be large enough such that for minimum sized
51 * frames taildrop kicks in before the bpool gets depleted, so we compute
52 * how many 64B frames fit inside the taildrop threshold and add a margin
53 * to accommodate the buffer refill delay.
55 #define DPAA2_ETH_MAX_FRAMES_PER_QUEUE (DPAA2_ETH_TAILDROP_THRESH / 64)
56 #define DPAA2_ETH_NUM_BUFS (DPAA2_ETH_MAX_FRAMES_PER_QUEUE + 256)
57 #define DPAA2_ETH_REFILL_THRESH \
58 (DPAA2_ETH_NUM_BUFS - DPAA2_ETH_BUFS_PER_CMD)
60 /* Maximum number of buffers that can be acquired/released through a single
63 #define DPAA2_ETH_BUFS_PER_CMD 7
65 /* Hardware requires alignment for ingress/egress buffer addresses */
66 #define DPAA2_ETH_TX_BUF_ALIGN 64
68 #define DPAA2_ETH_RX_BUF_RAW_SIZE PAGE_SIZE
69 #define DPAA2_ETH_RX_BUF_TAILROOM \
70 SKB_DATA_ALIGN(sizeof(struct skb_shared_info))
71 #define DPAA2_ETH_RX_BUF_SIZE \
72 (DPAA2_ETH_RX_BUF_RAW_SIZE - DPAA2_ETH_RX_BUF_TAILROOM)
74 /* Hardware annotation area in RX/TX buffers */
75 #define DPAA2_ETH_RX_HWA_SIZE 64
76 #define DPAA2_ETH_TX_HWA_SIZE 128
78 /* PTP nominal frequency 1GHz */
79 #define DPAA2_PTP_CLK_PERIOD_NS 1
81 /* Due to a limitation in WRIOP 1.0.0, the RX buffer data must be aligned
82 * to 256B. For newer revisions, the requirement is only for 64B alignment
84 #define DPAA2_ETH_RX_BUF_ALIGN_REV1 256
85 #define DPAA2_ETH_RX_BUF_ALIGN 64
87 /* We are accommodating a skb backpointer and some S/G info
88 * in the frame's software annotation. The hardware
89 * options are either 0 or 64, so we choose the latter.
91 #define DPAA2_ETH_SWA_SIZE 64
93 /* We store different information in the software annotation area of a Tx frame
94 * based on what type of frame it is
96 enum dpaa2_eth_swa_type {
102 /* Must keep this struct smaller than DPAA2_ETH_SWA_SIZE */
103 struct dpaa2_eth_swa {
104 enum dpaa2_eth_swa_type type;
111 struct scatterlist *scl;
117 struct xdp_frame *xdpf;
122 /* Annotation valid bits in FD FRC */
123 #define DPAA2_FD_FRC_FASV 0x8000
124 #define DPAA2_FD_FRC_FAEADV 0x4000
125 #define DPAA2_FD_FRC_FAPRV 0x2000
126 #define DPAA2_FD_FRC_FAIADV 0x1000
127 #define DPAA2_FD_FRC_FASWOV 0x0800
128 #define DPAA2_FD_FRC_FAICFDV 0x0400
130 /* Error bits in FD CTRL */
131 #define DPAA2_FD_RX_ERR_MASK (FD_CTRL_SBE | FD_CTRL_FAERR)
132 #define DPAA2_FD_TX_ERR_MASK (FD_CTRL_UFD | \
137 /* Annotation bits in FD CTRL */
138 #define DPAA2_FD_CTRL_ASAL 0x00020000 /* ASAL = 128B */
140 /* Frame annotation status */
148 /* Frame annotation status word is located in the first 8 bytes
149 * of the buffer's hardware annoatation area
151 #define DPAA2_FAS_OFFSET 0
152 #define DPAA2_FAS_SIZE (sizeof(struct dpaa2_fas))
154 /* Timestamp is located in the next 8 bytes of the buffer's
155 * hardware annotation area
157 #define DPAA2_TS_OFFSET 0x8
159 /* Frame annotation egress action descriptor */
160 #define DPAA2_FAEAD_OFFSET 0x58
167 #define DPAA2_FAEAD_A2V 0x20000000
168 #define DPAA2_FAEAD_A4V 0x08000000
169 #define DPAA2_FAEAD_UPDV 0x00001000
170 #define DPAA2_FAEAD_EBDDV 0x00002000
171 #define DPAA2_FAEAD_UPD 0x00000010
173 /* Accessors for the hardware annotation fields that we use */
174 static inline void *dpaa2_get_hwa(void *buf_addr, bool swa)
176 return buf_addr + (swa ? DPAA2_ETH_SWA_SIZE : 0);
179 static inline struct dpaa2_fas *dpaa2_get_fas(void *buf_addr, bool swa)
181 return dpaa2_get_hwa(buf_addr, swa) + DPAA2_FAS_OFFSET;
184 static inline __le64 *dpaa2_get_ts(void *buf_addr, bool swa)
186 return dpaa2_get_hwa(buf_addr, swa) + DPAA2_TS_OFFSET;
189 static inline struct dpaa2_faead *dpaa2_get_faead(void *buf_addr, bool swa)
191 return dpaa2_get_hwa(buf_addr, swa) + DPAA2_FAEAD_OFFSET;
194 /* Error and status bits in the frame annotation status word */
195 /* Debug frame, otherwise supposed to be discarded */
196 #define DPAA2_FAS_DISC 0x80000000
198 #define DPAA2_FAS_MS 0x40000000
199 #define DPAA2_FAS_PTP 0x08000000
200 /* Ethernet multicast frame */
201 #define DPAA2_FAS_MC 0x04000000
202 /* Ethernet broadcast frame */
203 #define DPAA2_FAS_BC 0x02000000
204 #define DPAA2_FAS_KSE 0x00040000
205 #define DPAA2_FAS_EOFHE 0x00020000
206 #define DPAA2_FAS_MNLE 0x00010000
207 #define DPAA2_FAS_TIDE 0x00008000
208 #define DPAA2_FAS_PIEE 0x00004000
209 /* Frame length error */
210 #define DPAA2_FAS_FLE 0x00002000
211 /* Frame physical error */
212 #define DPAA2_FAS_FPE 0x00001000
213 #define DPAA2_FAS_PTE 0x00000080
214 #define DPAA2_FAS_ISP 0x00000040
215 #define DPAA2_FAS_PHE 0x00000020
216 #define DPAA2_FAS_BLE 0x00000010
217 /* L3 csum validation performed */
218 #define DPAA2_FAS_L3CV 0x00000008
220 #define DPAA2_FAS_L3CE 0x00000004
221 /* L4 csum validation performed */
222 #define DPAA2_FAS_L4CV 0x00000002
224 #define DPAA2_FAS_L4CE 0x00000001
225 /* Possible errors on the ingress path */
226 #define DPAA2_FAS_RX_ERR_MASK (DPAA2_FAS_KSE | \
240 /* Time in milliseconds between link state updates */
241 #define DPAA2_ETH_LINK_STATE_REFRESH 1000
243 /* Number of times to retry a frame enqueue before giving up.
244 * Value determined empirically, in order to minimize the number
245 * of frames dropped on Tx
247 #define DPAA2_ETH_ENQUEUE_RETRIES 10
249 /* Number of times to retry DPIO portal operations while waiting
250 * for portal to finish executing current command and become
251 * available. We want to avoid being stuck in a while loop in case
252 * hardware becomes unresponsive, but not give up too easily if
253 * the portal really is busy for valid reasons
255 #define DPAA2_ETH_SWP_BUSY_RETRIES 1000
257 /* Driver statistics, other than those in struct rtnl_link_stats64.
258 * These are usually collected per-CPU and aggregated by ethtool.
260 struct dpaa2_eth_drv_stats {
261 __u64 tx_conf_frames;
268 /* Enqueues retried due to portal busy */
269 __u64 tx_portal_busy;
272 /* Per-FQ statistics */
273 struct dpaa2_eth_fq_stats {
274 /* Number of frames received on this queue */
278 /* Per-channel statistics */
279 struct dpaa2_eth_ch_stats {
280 /* Volatile dequeues retried due to portal busy */
281 __u64 dequeue_portal_busy;
284 /* Number of CDANs; useful to estimate avg NAPI len */
293 /* Maximum number of queues associated with a DPNI */
294 #define DPAA2_ETH_MAX_TCS 8
295 #define DPAA2_ETH_MAX_RX_QUEUES 16
296 #define DPAA2_ETH_MAX_TX_QUEUES 16
297 #define DPAA2_ETH_MAX_QUEUES (DPAA2_ETH_MAX_RX_QUEUES + \
298 DPAA2_ETH_MAX_TX_QUEUES)
299 #define DPAA2_ETH_MAX_NETDEV_QUEUES \
300 (DPAA2_ETH_MAX_TX_QUEUES * DPAA2_ETH_MAX_TCS)
302 #define DPAA2_ETH_MAX_DPCONS 16
304 enum dpaa2_eth_fq_type {
309 struct dpaa2_eth_priv;
311 struct dpaa2_eth_fq {
314 u32 tx_fqid[DPAA2_ETH_MAX_TCS];
320 struct dpaa2_eth_channel *channel;
321 enum dpaa2_eth_fq_type type;
323 void (*consume)(struct dpaa2_eth_priv *priv,
324 struct dpaa2_eth_channel *ch,
325 const struct dpaa2_fd *fd,
326 struct dpaa2_eth_fq *fq);
327 struct dpaa2_eth_fq_stats stats;
329 struct dpaa2_fd xdp_fds[DEV_MAP_BULK_SIZE];
332 struct dpaa2_eth_ch_xdp {
333 struct bpf_prog *prog;
334 u64 drop_bufs[DPAA2_ETH_BUFS_PER_CMD];
339 struct dpaa2_eth_channel {
340 struct dpaa2_io_notification_ctx nctx;
341 struct fsl_mc_device *dpcon;
344 struct napi_struct napi;
345 struct dpaa2_io *dpio;
346 struct dpaa2_io_store *store;
347 struct dpaa2_eth_priv *priv;
349 struct dpaa2_eth_ch_stats stats;
350 struct dpaa2_eth_ch_xdp xdp;
351 struct xdp_rxq_info xdp_rxq;
352 struct list_head *rx_list;
355 struct dpaa2_eth_dist_fields {
357 enum net_prot cls_prot;
363 struct dpaa2_eth_cls_rule {
364 struct ethtool_rx_flow_spec fs;
368 /* Driver private data */
369 struct dpaa2_eth_priv {
370 struct net_device *net_dev;
373 struct dpaa2_eth_fq fq[DPAA2_ETH_MAX_QUEUES];
374 int (*enqueue)(struct dpaa2_eth_priv *priv,
375 struct dpaa2_eth_fq *fq,
376 struct dpaa2_fd *fd, u8 prio,
378 int *frames_enqueued);
381 struct dpaa2_eth_channel *channel[DPAA2_ETH_MAX_DPCONS];
383 struct dpni_attr dpni_attrs;
388 struct fsl_mc_device *dpbp_dev;
390 struct iommu_domain *iommu_domain;
392 bool tx_tstamp; /* Tx timestamping enabled */
393 bool rx_tstamp; /* Rx timestamping enabled */
396 struct fsl_mc_io *mc_io;
397 /* Cores which have an affine DPIO/DPCON.
398 * This is the cpu set on which Rx and Tx conf frames are processed
400 struct cpumask dpio_cpumask;
402 /* Standard statistics */
403 struct rtnl_link_stats64 __percpu *percpu_stats;
404 /* Extra stats, in addition to the ones known by the kernel */
405 struct dpaa2_eth_drv_stats __percpu *percpu_extras;
410 struct dpni_link_state link_state;
412 struct task_struct *poll_thread;
414 /* enabled ethtool hashing bits */
417 struct dpaa2_eth_cls_rule *cls_rules;
419 struct bpf_prog *xdp_prog;
420 #ifdef CONFIG_DEBUG_FS
421 struct dpaa2_debugfs dbg;
424 struct dpaa2_mac *mac;
427 #define DPAA2_RXH_SUPPORTED (RXH_L2DA | RXH_VLAN | RXH_L3_PROTO \
428 | RXH_IP_SRC | RXH_IP_DST | RXH_L4_B_0_1 \
431 /* default Rx hash options, set during probing */
432 #define DPAA2_RXH_DEFAULT (RXH_L3_PROTO | RXH_IP_SRC | RXH_IP_DST | \
433 RXH_L4_B_0_1 | RXH_L4_B_2_3)
435 #define dpaa2_eth_hash_enabled(priv) \
436 ((priv)->dpni_attrs.num_queues > 1)
438 /* Required by struct dpni_rx_tc_dist_cfg::key_cfg_iova */
439 #define DPAA2_CLASSIFIER_DMA_SIZE 256
441 extern const struct ethtool_ops dpaa2_ethtool_ops;
442 extern int dpaa2_phc_index;
444 static inline int dpaa2_eth_cmp_dpni_ver(struct dpaa2_eth_priv *priv,
445 u16 ver_major, u16 ver_minor)
447 if (priv->dpni_ver_major == ver_major)
448 return priv->dpni_ver_minor - ver_minor;
449 return priv->dpni_ver_major - ver_major;
452 /* Minimum firmware version that supports a more flexible API
453 * for configuring the Rx flow hash key
455 #define DPNI_RX_DIST_KEY_VER_MAJOR 7
456 #define DPNI_RX_DIST_KEY_VER_MINOR 5
458 #define dpaa2_eth_has_legacy_dist(priv) \
459 (dpaa2_eth_cmp_dpni_ver((priv), DPNI_RX_DIST_KEY_VER_MAJOR, \
460 DPNI_RX_DIST_KEY_VER_MINOR) < 0)
462 #define dpaa2_eth_fs_enabled(priv) \
463 (!((priv)->dpni_attrs.options & DPNI_OPT_NO_FS))
465 #define dpaa2_eth_fs_mask_enabled(priv) \
466 ((priv)->dpni_attrs.options & DPNI_OPT_HAS_KEY_MASKING)
468 #define dpaa2_eth_fs_count(priv) \
469 ((priv)->dpni_attrs.fs_entries)
471 #define dpaa2_eth_tc_count(priv) \
472 ((priv)->dpni_attrs.num_tcs)
474 /* We have exactly one {Rx, Tx conf} queue per channel */
475 #define dpaa2_eth_queue_count(priv) \
476 ((priv)->num_channels)
478 enum dpaa2_eth_rx_dist {
479 DPAA2_ETH_RX_DIST_HASH,
480 DPAA2_ETH_RX_DIST_CLS
483 /* Unique IDs for the supported Rx classification header fields */
484 #define DPAA2_ETH_DIST_ETHDST BIT(0)
485 #define DPAA2_ETH_DIST_ETHSRC BIT(1)
486 #define DPAA2_ETH_DIST_ETHTYPE BIT(2)
487 #define DPAA2_ETH_DIST_VLAN BIT(3)
488 #define DPAA2_ETH_DIST_IPSRC BIT(4)
489 #define DPAA2_ETH_DIST_IPDST BIT(5)
490 #define DPAA2_ETH_DIST_IPPROTO BIT(6)
491 #define DPAA2_ETH_DIST_L4SRC BIT(7)
492 #define DPAA2_ETH_DIST_L4DST BIT(8)
493 #define DPAA2_ETH_DIST_ALL (~0ULL)
495 #define DPNI_PAUSE_VER_MAJOR 7
496 #define DPNI_PAUSE_VER_MINOR 13
497 #define dpaa2_eth_has_pause_support(priv) \
498 (dpaa2_eth_cmp_dpni_ver((priv), DPNI_PAUSE_VER_MAJOR, \
499 DPNI_PAUSE_VER_MINOR) >= 0)
502 unsigned int dpaa2_eth_needed_headroom(struct dpaa2_eth_priv *priv,
505 unsigned int headroom = DPAA2_ETH_SWA_SIZE;
507 /* If we don't have an skb (e.g. XDP buffer), we only need space for
508 * the software annotation area
513 /* For non-linear skbs we have no headroom requirement, as we build a
514 * SG frame with a newly allocated SGT buffer
516 if (skb_is_nonlinear(skb))
519 /* If we have Tx timestamping, need 128B hardware annotation */
520 if (priv->tx_tstamp && skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)
521 headroom += DPAA2_ETH_TX_HWA_SIZE;
526 /* Extra headroom space requested to hardware, in order to make sure there's
527 * no realloc'ing in forwarding scenarios
529 static inline unsigned int dpaa2_eth_rx_head_room(struct dpaa2_eth_priv *priv)
531 return priv->tx_data_offset - DPAA2_ETH_RX_HWA_SIZE;
534 int dpaa2_eth_set_hash(struct net_device *net_dev, u64 flags);
535 int dpaa2_eth_set_cls(struct net_device *net_dev, u64 key);
536 int dpaa2_eth_cls_key_size(u64 key);
537 int dpaa2_eth_cls_fld_off(int prot, int field);
538 void dpaa2_eth_cls_trim_rule(void *key_mem, u64 fields);
540 #endif /* __DPAA2_H */