2 * Copyright (C) 2005 - 2011 Emulex
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License version 2
7 * as published by the Free Software Foundation. The full GNU General
8 * Public License is included in this distribution in the file called COPYING.
10 * Contact Information:
11 * linux-drivers@emulex.com
15 * Costa Mesa, CA 92626
18 /********* Mailbox door bell *************/
19 /* Used for driver communication with the FW.
20 * The software must write this register twice to post any command. First,
21 * it writes the register with hi=1 and the upper bits of the physical address
22 * for the MAILBOX structure. Software must poll the ready bit until this
23 * is acknowledged. Then, sotware writes the register with hi=0 with the lower
24 * bits in the address. It must poll the ready bit until the command is
25 * complete. Upon completion, the MAILBOX will contain a valid completion
28 #define MPU_MAILBOX_DB_OFFSET 0x160
29 #define MPU_MAILBOX_DB_RDY_MASK 0x1 /* bit 0 */
30 #define MPU_MAILBOX_DB_HI_MASK 0x2 /* bit 1 */
32 #define MPU_EP_CONTROL 0
34 /********** MPU semphore ******************/
35 #define MPU_EP_SEMAPHORE_OFFSET 0xac
36 #define MPU_EP_SEMAPHORE_IF_TYPE2_OFFSET 0x400
37 #define EP_SEMAPHORE_POST_STAGE_MASK 0x0000FFFF
38 #define EP_SEMAPHORE_POST_ERR_MASK 0x1
39 #define EP_SEMAPHORE_POST_ERR_SHIFT 31
41 /* MPU semphore POST stage values */
42 #define POST_STAGE_AWAITING_HOST_RDY 0x1 /* FW awaiting goahead from host */
43 #define POST_STAGE_HOST_RDY 0x2 /* Host has given go-ahed to FW */
44 #define POST_STAGE_BE_RESET 0x3 /* Host wants to reset chip */
45 #define POST_STAGE_ARMFW_RDY 0xc000 /* FW is done with POST */
48 /* Lancer SLIPORT_CONTROL SLIPORT_STATUS registers */
49 #define SLIPORT_STATUS_OFFSET 0x404
50 #define SLIPORT_CONTROL_OFFSET 0x408
51 #define SLIPORT_ERROR1_OFFSET 0x40C
52 #define SLIPORT_ERROR2_OFFSET 0x410
54 #define SLIPORT_STATUS_ERR_MASK 0x80000000
55 #define SLIPORT_STATUS_RN_MASK 0x01000000
56 #define SLIPORT_STATUS_RDY_MASK 0x00800000
59 #define SLI_PORT_CONTROL_IP_MASK 0x08000000
61 #define PCICFG_CUST_SCRATCHPAD_CSR 0x1EC
63 /********* Memory BAR register ************/
64 #define PCICFG_MEMBAR_CTRL_INT_CTRL_OFFSET 0xfc
65 /* Host Interrupt Enable, if set interrupts are enabled although "PCI Interrupt
66 * Disable" may still globally block interrupts in addition to individual
67 * interrupt masks; a mechanism for the device driver to block all interrupts
68 * atomically without having to arbitrate for the PCI Interrupt Disable bit
71 #define MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK (1 << 29) /* bit 29 */
73 /********* Power management (WOL) **********/
74 #define PCICFG_PM_CONTROL_OFFSET 0x44
75 #define PCICFG_PM_CONTROL_MASK 0x108 /* bits 3 & 8 */
77 /********* Online Control Registers *******/
78 #define PCICFG_ONLINE0 0xB0
79 #define PCICFG_ONLINE1 0xB4
81 /********* UE Status and Mask Registers ***/
82 #define PCICFG_UE_STATUS_LOW 0xA0
83 #define PCICFG_UE_STATUS_HIGH 0xA4
84 #define PCICFG_UE_STATUS_LOW_MASK 0xA8
85 #define PCICFG_UE_STATUS_HI_MASK 0xAC
87 /******** SLI_INTF ***********************/
88 #define SLI_INTF_REG_OFFSET 0x58
89 #define SLI_INTF_VALID_MASK 0xE0000000
90 #define SLI_INTF_VALID 0xC0000000
91 #define SLI_INTF_HINT2_MASK 0x1F000000
92 #define SLI_INTF_HINT2_SHIFT 24
93 #define SLI_INTF_HINT1_MASK 0x00FF0000
94 #define SLI_INTF_HINT1_SHIFT 16
95 #define SLI_INTF_FAMILY_MASK 0x00000F00
96 #define SLI_INTF_FAMILY_SHIFT 8
97 #define SLI_INTF_IF_TYPE_MASK 0x0000F000
98 #define SLI_INTF_IF_TYPE_SHIFT 12
99 #define SLI_INTF_REV_MASK 0x000000F0
100 #define SLI_INTF_REV_SHIFT 4
101 #define SLI_INTF_FT_MASK 0x00000001
103 #define SLI_INTF_TYPE_2 2
104 #define SLI_INTF_TYPE_3 3
107 #define BE_SLI_FAMILY 0x0
108 #define LANCER_A0_SLI_FAMILY 0xA
109 #define SKYHAWK_SLI_FAMILY 0x2
111 /********* ISR0 Register offset **********/
112 #define CEV_ISR0_OFFSET 0xC18
113 #define CEV_ISR_SIZE 4
115 /********* Event Q door bell *************/
116 #define DB_EQ_OFFSET DB_CQ_OFFSET
117 #define DB_EQ_RING_ID_MASK 0x1FF /* bits 0 - 8 */
118 #define DB_EQ_RING_ID_EXT_MASK 0x3e00 /* bits 9-13 */
119 #define DB_EQ_RING_ID_EXT_MASK_SHIFT (2) /* qid bits 9-13 placing at 11-15 */
121 /* Clear the interrupt for this eq */
122 #define DB_EQ_CLR_SHIFT (9) /* bit 9 */
124 #define DB_EQ_EVNT_SHIFT (10) /* bit 10 */
125 /* Number of event entries processed */
126 #define DB_EQ_NUM_POPPED_SHIFT (16) /* bits 16 - 28 */
128 #define DB_EQ_REARM_SHIFT (29) /* bit 29 */
130 /********* Compl Q door bell *************/
131 #define DB_CQ_OFFSET 0x120
132 #define DB_CQ_RING_ID_MASK 0x3FF /* bits 0 - 9 */
133 #define DB_CQ_RING_ID_EXT_MASK 0x7C00 /* bits 10-14 */
134 #define DB_CQ_RING_ID_EXT_MASK_SHIFT (1) /* qid bits 10-14
137 /* Number of event entries processed */
138 #define DB_CQ_NUM_POPPED_SHIFT (16) /* bits 16 - 28 */
140 #define DB_CQ_REARM_SHIFT (29) /* bit 29 */
142 /********** TX ULP door bell *************/
143 #define DB_TXULP1_OFFSET 0x60
144 #define DB_TXULP_RING_ID_MASK 0x7FF /* bits 0 - 10 */
145 /* Number of tx entries posted */
146 #define DB_TXULP_NUM_POSTED_SHIFT (16) /* bits 16 - 29 */
147 #define DB_TXULP_NUM_POSTED_MASK 0x3FFF /* bits 16 - 29 */
149 /********** RQ(erx) door bell ************/
150 #define DB_RQ_OFFSET 0x100
151 #define DB_RQ_RING_ID_MASK 0x3FF /* bits 0 - 9 */
152 /* Number of rx frags posted */
153 #define DB_RQ_NUM_POSTED_SHIFT (24) /* bits 24 - 31 */
155 /********** MCC door bell ************/
156 #define DB_MCCQ_OFFSET 0x140
157 #define DB_MCCQ_RING_ID_MASK 0x7FF /* bits 0 - 10 */
158 /* Number of entries posted */
159 #define DB_MCCQ_NUM_POSTED_SHIFT (16) /* bits 16 - 29 */
161 /********** SRIOV VF PCICFG OFFSET ********/
162 #define SRIOV_VF_PCICFG_OFFSET (4096)
164 /********** FAT TABLE ********/
165 #define RETRIEVE_FAT 0
168 /* Flashrom related descriptors */
169 #define MAX_FLASH_COMP 32
170 #define IMAGE_TYPE_FIRMWARE 160
171 #define IMAGE_TYPE_BOOTCODE 224
172 #define IMAGE_TYPE_OPTIONROM 32
174 #define NUM_FLASHDIR_ENTRIES 32
176 #define OPTYPE_ISCSI_ACTIVE 0
177 #define OPTYPE_REDBOOT 1
178 #define OPTYPE_BIOS 2
179 #define OPTYPE_PXE_BIOS 3
180 #define OPTYPE_FCOE_BIOS 8
181 #define OPTYPE_ISCSI_BACKUP 9
182 #define OPTYPE_FCOE_FW_ACTIVE 10
183 #define OPTYPE_FCOE_FW_BACKUP 11
184 #define OPTYPE_NCSI_FW 13
185 #define OPTYPE_PHY_FW 99
188 #define ILLEGAL_IOCTL_REQ 2
189 #define FLASHROM_OPER_PHY_FLASH 9
190 #define FLASHROM_OPER_PHY_SAVE 10
191 #define FLASHROM_OPER_FLASH 1
192 #define FLASHROM_OPER_SAVE 2
193 #define FLASHROM_OPER_REPORT 4
195 #define FLASH_IMAGE_MAX_SIZE_g2 (1310720) /* Max firmware image size */
196 #define FLASH_BIOS_IMAGE_MAX_SIZE_g2 (262144) /* Max OPTION ROM image sz */
197 #define FLASH_REDBOOT_IMAGE_MAX_SIZE_g2 (262144) /* Max Redboot image sz */
198 #define FLASH_IMAGE_MAX_SIZE_g3 (2097152) /* Max firmware image size */
199 #define FLASH_BIOS_IMAGE_MAX_SIZE_g3 (524288) /* Max OPTION ROM image sz */
200 #define FLASH_REDBOOT_IMAGE_MAX_SIZE_g3 (1048576) /* Max Redboot image sz */
201 #define FLASH_NCSI_IMAGE_MAX_SIZE_g3 (262144)
202 #define FLASH_PHY_FW_IMAGE_MAX_SIZE_g3 262144
204 #define FLASH_NCSI_MAGIC (0x16032009)
205 #define FLASH_NCSI_DISABLED (0)
206 #define FLASH_NCSI_ENABLED (1)
208 #define FLASH_NCSI_BITFILE_HDR_OFFSET (0x600000)
210 /* Offsets for components on Flash. */
211 #define FLASH_iSCSI_PRIMARY_IMAGE_START_g2 (1048576)
212 #define FLASH_iSCSI_BACKUP_IMAGE_START_g2 (2359296)
213 #define FLASH_FCoE_PRIMARY_IMAGE_START_g2 (3670016)
214 #define FLASH_FCoE_BACKUP_IMAGE_START_g2 (4980736)
215 #define FLASH_iSCSI_BIOS_START_g2 (7340032)
216 #define FLASH_PXE_BIOS_START_g2 (7864320)
217 #define FLASH_FCoE_BIOS_START_g2 (524288)
218 #define FLASH_REDBOOT_START_g2 (0)
220 #define FLASH_NCSI_START_g3 (15990784)
221 #define FLASH_iSCSI_PRIMARY_IMAGE_START_g3 (2097152)
222 #define FLASH_iSCSI_BACKUP_IMAGE_START_g3 (4194304)
223 #define FLASH_FCoE_PRIMARY_IMAGE_START_g3 (6291456)
224 #define FLASH_FCoE_BACKUP_IMAGE_START_g3 (8388608)
225 #define FLASH_iSCSI_BIOS_START_g3 (12582912)
226 #define FLASH_PXE_BIOS_START_g3 (13107200)
227 #define FLASH_FCoE_BIOS_START_g3 (13631488)
228 #define FLASH_REDBOOT_START_g3 (262144)
229 #define FLASH_PHY_FW_START_g3 1310720
231 #define IMAGE_NCSI 16
232 #define IMAGE_OPTION_ROM_PXE 32
233 #define IMAGE_OPTION_ROM_FCoE 33
234 #define IMAGE_OPTION_ROM_ISCSI 34
235 #define IMAGE_FLASHISM_JUMPVECTOR 48
236 #define IMAGE_FLASH_ISM 49
237 #define IMAGE_JUMP_VECTOR 50
238 #define IMAGE_FIRMWARE_iSCSI 160
239 #define IMAGE_FIRMWARE_COMP_iSCSI 161
240 #define IMAGE_FIRMWARE_FCoE 162
241 #define IMAGE_FIRMWARE_COMP_FCoE 163
242 #define IMAGE_FIRMWARE_BACKUP_iSCSI 176
243 #define IMAGE_FIRMWARE_BACKUP_COMP_iSCSI 177
244 #define IMAGE_FIRMWARE_BACKUP_FCoE 178
245 #define IMAGE_FIRMWARE_BACKUP_COMP_FCoE 179
246 #define IMAGE_FIRMWARE_PHY 192
247 #define IMAGE_BOOT_CODE 224
249 /************* Rx Packet Type Encoding **************/
250 #define BE_UNICAST_PACKET 0
251 #define BE_MULTICAST_PACKET 1
252 #define BE_BROADCAST_PACKET 2
253 #define BE_RSVD_PACKET 3
256 * BE descriptors: host memory data structures whose formats
257 * are hardwired in BE silicon.
259 /* Event Queue Descriptor */
260 #define EQ_ENTRY_VALID_MASK 0x1 /* bit 0 */
261 #define EQ_ENTRY_RES_ID_MASK 0xFFFF /* bits 16 - 31 */
262 #define EQ_ENTRY_RES_ID_SHIFT 16
268 /* TX Queue Descriptor */
269 #define ETH_WRB_FRAG_LEN_MASK 0xFFFF
271 u32 frag_pa_hi; /* dword 0 */
272 u32 frag_pa_lo; /* dword 1 */
273 u32 rsvd0; /* dword 2 */
274 u32 frag_len; /* dword 3: bits 0 - 15 */
277 /* Pseudo amap definition for eth_hdr_wrb in which each bit of the
278 * actual structure is defined as a byte : used to calculate
279 * offset/shift/mask of each field */
280 struct amap_eth_hdr_wrb {
281 u8 rsvd0[32]; /* dword 0 */
282 u8 rsvd1[32]; /* dword 1 */
283 u8 complete; /* dword 2 */
297 u8 len[16]; /* dword 3 */
301 struct be_eth_hdr_wrb {
305 /* TX Compl Queue Descriptor */
307 /* Pseudo amap definition for eth_tx_compl in which each bit of the
308 * actual structure is defined as a byte: used to calculate
309 * offset/shift/mask of each field */
310 struct amap_eth_tx_compl {
311 u8 wrb_index[16]; /* dword 0 */
312 u8 ct[2]; /* dword 0 */
313 u8 port[2]; /* dword 0 */
314 u8 rsvd0[8]; /* dword 0 */
315 u8 status[4]; /* dword 0 */
316 u8 user_bytes[16]; /* dword 1 */
317 u8 nwh_bytes[8]; /* dword 1 */
318 u8 lso; /* dword 1 */
319 u8 cast_enc[2]; /* dword 1 */
320 u8 rsvd1[5]; /* dword 1 */
321 u8 rsvd2[32]; /* dword 2 */
322 u8 pkts[16]; /* dword 3 */
323 u8 ringid[11]; /* dword 3 */
324 u8 hash_val[4]; /* dword 3 */
325 u8 valid; /* dword 3 */
328 struct be_eth_tx_compl {
332 /* RX Queue Descriptor */
338 /* RX Compl Queue Descriptor */
340 /* Pseudo amap definition for BE2 and BE3 legacy mode eth_rx_compl in which
341 * each bit of the actual structure is defined as a byte: used to calculate
342 * offset/shift/mask of each field */
343 struct amap_eth_rx_compl_v0 {
344 u8 vlan_tag[16]; /* dword 0 */
345 u8 pktsize[14]; /* dword 0 */
346 u8 port; /* dword 0 */
347 u8 ip_opt; /* dword 0 */
348 u8 err; /* dword 1 */
349 u8 rsshp; /* dword 1 */
350 u8 ipf; /* dword 1 */
351 u8 tcpf; /* dword 1 */
352 u8 udpf; /* dword 1 */
353 u8 ipcksm; /* dword 1 */
354 u8 l4_cksm; /* dword 1 */
355 u8 ip_version; /* dword 1 */
356 u8 macdst[6]; /* dword 1 */
357 u8 vtp; /* dword 1 */
358 u8 rsvd0; /* dword 1 */
359 u8 fragndx[10]; /* dword 1 */
360 u8 ct[2]; /* dword 1 */
362 u8 numfrags[3]; /* dword 1 */
363 u8 rss_flush; /* dword 2 */
364 u8 cast_enc[2]; /* dword 2 */
365 u8 vtm; /* dword 2 */
366 u8 rss_bank; /* dword 2 */
367 u8 rsvd1[23]; /* dword 2 */
368 u8 lro_pkt; /* dword 2 */
369 u8 rsvd2[2]; /* dword 2 */
370 u8 valid; /* dword 2 */
371 u8 rsshash[32]; /* dword 3 */
374 /* Pseudo amap definition for BE3 native mode eth_rx_compl in which
375 * each bit of the actual structure is defined as a byte: used to calculate
376 * offset/shift/mask of each field */
377 struct amap_eth_rx_compl_v1 {
378 u8 vlan_tag[16]; /* dword 0 */
379 u8 pktsize[14]; /* dword 0 */
380 u8 vtp; /* dword 0 */
381 u8 ip_opt; /* dword 0 */
382 u8 err; /* dword 1 */
383 u8 rsshp; /* dword 1 */
384 u8 ipf; /* dword 1 */
385 u8 tcpf; /* dword 1 */
386 u8 udpf; /* dword 1 */
387 u8 ipcksm; /* dword 1 */
388 u8 l4_cksm; /* dword 1 */
389 u8 ip_version; /* dword 1 */
390 u8 macdst[7]; /* dword 1 */
391 u8 rsvd0; /* dword 1 */
392 u8 fragndx[10]; /* dword 1 */
393 u8 ct[2]; /* dword 1 */
395 u8 numfrags[3]; /* dword 1 */
396 u8 rss_flush; /* dword 2 */
397 u8 cast_enc[2]; /* dword 2 */
398 u8 vtm; /* dword 2 */
399 u8 rss_bank; /* dword 2 */
400 u8 port[2]; /* dword 2 */
401 u8 vntagp; /* dword 2 */
402 u8 header_len[8]; /* dword 2 */
403 u8 header_split[2]; /* dword 2 */
404 u8 rsvd1[13]; /* dword 2 */
405 u8 valid; /* dword 2 */
406 u8 rsshash[32]; /* dword 3 */
409 struct be_eth_rx_compl {
413 struct mgmt_hba_attribs {
414 u8 flashrom_version_string[32];
415 u8 manufacturer_name[32];
418 u8 ncsi_ver_string[12];
419 u32 default_extended_timeout;
420 u8 controller_model_number[32];
421 u8 controller_description[64];
422 u8 controller_serial_number[32];
423 u8 ip_version_string[32];
424 u8 firmware_version_string[32];
425 u8 bios_version_string[32];
426 u8 redboot_version_string[32];
427 u8 driver_version_string[32];
428 u8 fw_on_flash_version_string[32];
429 u32 functionalities_supported;
432 u8 generational_guid[16];
434 u16 default_link_down_timeout;
435 u8 iscsi_ver_min_max;
436 u8 multifunction_device;
439 u8 max_domains_supported;
441 u32 firmware_post_status;
446 struct mgmt_controller_attrib {
447 struct mgmt_hba_attribs hba_attribs;
450 u16 pci_sub_vendor_id;
451 u16 pci_sub_system_id;
453 u8 pci_device_number;
454 u8 pci_function_number;
456 u64 unique_identifier;
460 struct controller_id {
468 unsigned long offset;
479 u8 image_version[32];
481 struct flash_file_hdr_g2 {
485 struct controller_id cont_id;
493 struct flash_file_hdr_g3 {
504 struct flash_section_hdr {
513 struct flash_section_hdr_g2 {
522 struct flash_section_entry {
534 struct flash_section_info {
536 struct flash_section_hdr fsec_hdr;
537 struct flash_section_entry fsec_entry[32];
540 struct flash_section_info_g2 {
542 struct flash_section_hdr_g2 fsec_hdr;
543 struct flash_section_entry fsec_entry[32];