2 * Copyright (C) 2005 - 2011 Emulex
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License version 2
7 * as published by the Free Software Foundation. The full GNU General
8 * Public License is included in this distribution in the file called COPYING.
10 * Contact Information:
11 * linux-drivers@emulex.com
15 * Costa Mesa, CA 92626
21 #include <linux/pci.h>
22 #include <linux/etherdevice.h>
23 #include <linux/delay.h>
27 #include <linux/if_vlan.h>
28 #include <linux/workqueue.h>
29 #include <linux/interrupt.h>
30 #include <linux/firmware.h>
31 #include <linux/slab.h>
32 #include <linux/u64_stats_sync.h>
37 #define DRV_VER "4.2.220u"
38 #define DRV_NAME "be2net"
39 #define BE_NAME "ServerEngines BladeEngine2 10Gbps NIC"
40 #define BE3_NAME "ServerEngines BladeEngine3 10Gbps NIC"
41 #define OC_NAME "Emulex OneConnect 10Gbps NIC"
42 #define OC_NAME_BE OC_NAME "(be3)"
43 #define OC_NAME_LANCER OC_NAME "(Lancer)"
44 #define OC_NAME_SH OC_NAME "(Skyhawk)"
45 #define DRV_DESC "ServerEngines BladeEngine 10Gbps NIC Driver"
47 #define BE_VENDOR_ID 0x19a2
48 #define EMULEX_VENDOR_ID 0x10df
49 #define BE_DEVICE_ID1 0x211
50 #define BE_DEVICE_ID2 0x221
51 #define OC_DEVICE_ID1 0x700 /* Device Id for BE2 cards */
52 #define OC_DEVICE_ID2 0x710 /* Device Id for BE3 cards */
53 #define OC_DEVICE_ID3 0xe220 /* Device id for Lancer cards */
54 #define OC_DEVICE_ID4 0xe228 /* Device id for VF in Lancer */
55 #define OC_DEVICE_ID5 0x720 /* Device Id for Skyhawk cards */
56 #define OC_SUBSYS_DEVICE_ID1 0xE602
57 #define OC_SUBSYS_DEVICE_ID2 0xE642
58 #define OC_SUBSYS_DEVICE_ID3 0xE612
59 #define OC_SUBSYS_DEVICE_ID4 0xE652
61 static inline char *nic_name(struct pci_dev *pdev)
63 switch (pdev->device) {
70 return OC_NAME_LANCER;
80 /* Number of bytes of an RX frame that are copied to skb->data */
81 #define BE_HDR_LEN ((u16) 64)
82 /* allocate extra space to allow tunneling decapsulation without head reallocation */
83 #define BE_RX_SKB_ALLOC_SIZE (BE_HDR_LEN + 64)
85 #define BE_MAX_JUMBO_FRAME_SIZE 9018
86 #define BE_MIN_MTU 256
88 #define BE_NUM_VLANS_SUPPORTED 64
89 #define BE_MAX_EQD 96u
90 #define BE_MAX_TX_FRAG_COUNT 30
92 #define EVNT_Q_LEN 1024
94 #define TX_CQ_LEN 1024
95 #define RX_Q_LEN 1024 /* Does not support any other value */
96 #define RX_CQ_LEN 1024
97 #define MCC_Q_LEN 128 /* total size not to exceed 8 pages */
98 #define MCC_CQ_LEN 256
100 #define BE3_MAX_RSS_QS 8
101 #define BE2_MAX_RSS_QS 4
102 #define MAX_RSS_QS BE3_MAX_RSS_QS
103 #define MAX_RX_QS (MAX_RSS_QS + 1) /* RSS qs + 1 def Rx */
106 #define MAX_ROCE_EQS 5
107 #define MAX_MSIX_VECTORS (MAX_RSS_QS + MAX_ROCE_EQS) /* RSS qs + RoCE */
108 #define BE_TX_BUDGET 256
109 #define BE_NAPI_WEIGHT 64
110 #define MAX_RX_POST BE_NAPI_WEIGHT /* Frags posted at a time */
111 #define RX_FRAGS_REFILL_WM (RX_Q_LEN - MAX_RX_POST)
113 #define FW_VER_LEN 32
121 struct be_queue_info {
122 struct be_dma_mem dma_mem;
124 u16 entry_size; /* Size of an element in the queue */
128 atomic_t used; /* Number of valid elements in the queue */
131 static inline u32 MODULO(u16 val, u16 limit)
133 BUG_ON(limit & (limit - 1));
134 return val & (limit - 1);
137 static inline void index_adv(u16 *index, u16 val, u16 limit)
139 *index = MODULO((*index + val), limit);
142 static inline void index_inc(u16 *index, u16 limit)
144 *index = MODULO((*index + 1), limit);
147 static inline void *queue_head_node(struct be_queue_info *q)
149 return q->dma_mem.va + q->head * q->entry_size;
152 static inline void *queue_tail_node(struct be_queue_info *q)
154 return q->dma_mem.va + q->tail * q->entry_size;
157 static inline void *queue_index_node(struct be_queue_info *q, u16 index)
159 return q->dma_mem.va + index * q->entry_size;
162 static inline void queue_head_inc(struct be_queue_info *q)
164 index_inc(&q->head, q->len);
167 static inline void index_dec(u16 *index, u16 limit)
169 *index = MODULO((*index - 1), limit);
172 static inline void queue_tail_inc(struct be_queue_info *q)
174 index_inc(&q->tail, q->len);
178 struct be_queue_info q;
181 /* Adaptive interrupt coalescing (AIC) info */
183 u32 min_eqd; /* in usecs */
184 u32 max_eqd; /* in usecs */
185 u32 eqd; /* configured val when aic is off */
186 u32 cur_eqd; /* in usecs */
188 u8 idx; /* array index */
190 struct napi_struct napi;
191 struct be_adapter *adapter;
192 } ____cacheline_aligned_in_smp;
195 struct be_queue_info q;
196 struct be_queue_info cq;
208 struct u64_stats_sync sync;
209 struct u64_stats_sync sync_compl;
213 struct be_queue_info q;
214 struct be_queue_info cq;
215 /* Remember the skbs that were transmitted */
216 struct sk_buff *sent_skb_list[TX_Q_LEN];
217 struct be_tx_stats stats;
218 } ____cacheline_aligned_in_smp;
220 /* Struct to remember the pages posted for rx frags */
221 struct be_rx_page_info {
223 DEFINE_DMA_UNMAP_ADDR(bus);
233 u32 rx_drops_no_skbs; /* skb allocation errors */
234 u32 rx_drops_no_frags; /* HW has no fetched frags */
235 u32 rx_post_fail; /* page post alloc failures */
238 u32 rx_compl_err; /* completions with err set */
239 u32 rx_pps; /* pkts per second */
240 struct u64_stats_sync sync;
243 struct be_rx_compl_info {
263 struct be_adapter *adapter;
264 struct be_queue_info q;
265 struct be_queue_info cq;
266 struct be_rx_compl_info rxcp;
267 struct be_rx_page_info page_info_tbl[RX_Q_LEN];
268 struct be_rx_stats stats;
270 bool rx_post_starved; /* Zero rx frags have been posted to BE */
271 } ____cacheline_aligned_in_smp;
273 struct be_drv_stats {
274 u32 be_on_die_temperature;
276 u32 rx_drops_no_pbuf;
277 u32 rx_drops_no_txpb;
278 u32 rx_drops_no_erx_descr;
279 u32 rx_drops_no_tpre_descr;
280 u32 rx_drops_too_many_frags;
281 u32 forwarded_packets;
284 u32 rx_alignment_symbol_errors;
286 u32 rx_priority_pause_frames;
287 u32 rx_control_frames;
288 u32 rx_in_range_errors;
289 u32 rx_out_range_errors;
290 u32 rx_frame_too_long;
291 u32 rx_address_mismatch_drops;
292 u32 rx_dropped_too_small;
293 u32 rx_dropped_too_short;
294 u32 rx_dropped_header_too_small;
295 u32 rx_dropped_tcp_length;
297 u32 rx_ip_checksum_errs;
298 u32 rx_tcp_checksum_errs;
299 u32 rx_udp_checksum_errs;
301 u32 tx_priority_pauseframes;
302 u32 tx_controlframes;
303 u32 rxpp_fifo_overflow_drop;
304 u32 rx_input_fifo_overflow_drop;
305 u32 pmem_fifo_overflow_drop;
310 unsigned char mac_addr[ETH_ALEN];
323 #define BE_FLAGS_LINK_STATUS_INIT 1
324 #define BE_FLAGS_WORKER_SCHEDULED (1 << 3)
325 #define BE_UC_PMAC_COUNT 30
326 #define BE_VF_UC_PMAC_COUNT 2
336 u16 auto_speeds_supported;
337 u16 fixed_speeds_supported;
339 int forced_port_speed;
346 struct pci_dev *pdev;
347 struct net_device *netdev;
350 u8 __iomem *db; /* Door Bell */
352 struct mutex mbox_lock; /* For serializing mbox cmds to BE card */
353 struct be_dma_mem mbox_mem;
354 /* Mbox mem is adjusted to align to 16 bytes. The allocated addr
355 * is stored for freeing purpose */
356 struct be_dma_mem mbox_mem_alloced;
358 struct be_mcc_obj mcc_obj;
359 spinlock_t mcc_lock; /* For serializing mcc cmds to BE card */
360 spinlock_t mcc_cq_lock;
364 struct be_eq_obj eq_obj[MAX_MSIX_VECTORS];
365 struct msix_entry msix_entries[MAX_MSIX_VECTORS];
370 struct be_tx_obj tx_obj[MAX_TX_QS];
374 struct be_rx_obj rx_obj[MAX_RX_QS];
375 u32 big_page_size; /* Compounded page size shared by rx wrbs */
378 struct be_drv_stats drv_stats;
381 u16 max_vlans; /* Number of vlans supported */
382 u8 vlan_tag[VLAN_N_VID];
383 u8 vlan_prio_bmap; /* Available Priority BitMap */
384 u16 recommended_prio; /* Recommended Priority */
385 struct be_dma_mem rx_filter; /* Cmd DMA mem for rx-filter */
387 struct be_dma_mem stats_cmd;
388 /* Work queue used to perform periodic tasks like getting statistics */
389 struct delayed_work work;
393 /* Ethtool knobs and info */
394 char fw_ver[FW_VER_LEN];
395 int if_handle; /* Used to configure filtering */
396 u32 *pmac_id; /* MAC addr handle used by BE card */
397 u32 beacon_state; /* for set_phys_id */
406 u32 rx_fc; /* Rx flow control */
407 u32 tx_fc; /* Tx flow control */
409 u8 generation; /* BladeEngine ASIC generation */
412 u8 __iomem *base; /* Door Bell */
417 u32 num_msix_roce_vec;
418 struct ocrdma_dev *ocrdma_dev;
419 struct list_head entry;
422 struct completion flash_compl;
424 u32 num_vfs; /* Number of VFs provisioned by PF driver */
425 u32 dev_num_vfs; /* Number of VFs supported by HW */
427 struct be_vf_cfg *vf_cfg;
435 u32 max_pmac_cnt; /* Max secondary UC MACs programmable */
436 u32 uc_macs; /* Count of secondary UC MAC programmed */
440 #define be_physfn(adapter) (!adapter->virtfn)
441 #define sriov_enabled(adapter) (adapter->num_vfs > 0)
442 #define sriov_want(adapter) (adapter->dev_num_vfs && num_vfs && \
444 #define for_all_vfs(adapter, vf_cfg, i) \
445 for (i = 0, vf_cfg = &adapter->vf_cfg[i]; i < adapter->num_vfs; \
448 /* BladeEngine Generation numbers */
454 #define lancer_chip(adapter) ((adapter->pdev->device == OC_DEVICE_ID3) || \
455 (adapter->pdev->device == OC_DEVICE_ID4))
457 #define be_roce_supported(adapter) ((adapter->if_type == SLI_INTF_TYPE_3 || \
458 adapter->sli_family == SKYHAWK_SLI_FAMILY) && \
459 (adapter->function_mode & RDMA_ENABLED))
461 extern const struct ethtool_ops be_ethtool_ops;
463 #define msix_enabled(adapter) (adapter->num_msix_vec > 0)
464 #define num_irqs(adapter) (msix_enabled(adapter) ? \
465 adapter->num_msix_vec : 1)
466 #define tx_stats(txo) (&(txo)->stats)
467 #define rx_stats(rxo) (&(rxo)->stats)
469 /* The default RXQ is the last RXQ */
470 #define default_rxo(adpt) (&adpt->rx_obj[adpt->num_rx_qs - 1])
472 #define for_all_rx_queues(adapter, rxo, i) \
473 for (i = 0, rxo = &adapter->rx_obj[i]; i < adapter->num_rx_qs; \
476 /* Skip the default non-rss queue (last one)*/
477 #define for_all_rss_queues(adapter, rxo, i) \
478 for (i = 0, rxo = &adapter->rx_obj[i]; i < (adapter->num_rx_qs - 1);\
481 #define for_all_tx_queues(adapter, txo, i) \
482 for (i = 0, txo = &adapter->tx_obj[i]; i < adapter->num_tx_qs; \
485 #define for_all_evt_queues(adapter, eqo, i) \
486 for (i = 0, eqo = &adapter->eq_obj[i]; i < adapter->num_evt_qs; \
489 #define is_mcc_eqo(eqo) (eqo->idx == 0)
490 #define mcc_eqo(adapter) (&adapter->eq_obj[0])
492 #define PAGE_SHIFT_4K 12
493 #define PAGE_SIZE_4K (1 << PAGE_SHIFT_4K)
495 /* Returns number of pages spanned by the data starting at the given addr */
496 #define PAGES_4K_SPANNED(_address, size) \
497 ((u32)((((size_t)(_address) & (PAGE_SIZE_4K - 1)) + \
498 (size) + (PAGE_SIZE_4K - 1)) >> PAGE_SHIFT_4K))
500 /* Returns bit offset within a DWORD of a bitfield */
501 #define AMAP_BIT_OFFSET(_struct, field) \
502 (((size_t)&(((_struct *)0)->field))%32)
504 /* Returns the bit mask of the field that is NOT shifted into location. */
505 static inline u32 amap_mask(u32 bitsize)
507 return (bitsize == 32 ? 0xFFFFFFFF : (1 << bitsize) - 1);
511 amap_set(void *ptr, u32 dw_offset, u32 mask, u32 offset, u32 value)
513 u32 *dw = (u32 *) ptr + dw_offset;
514 *dw &= ~(mask << offset);
515 *dw |= (mask & value) << offset;
518 #define AMAP_SET_BITS(_struct, field, ptr, val) \
520 offsetof(_struct, field)/32, \
521 amap_mask(sizeof(((_struct *)0)->field)), \
522 AMAP_BIT_OFFSET(_struct, field), \
525 static inline u32 amap_get(void *ptr, u32 dw_offset, u32 mask, u32 offset)
527 u32 *dw = (u32 *) ptr;
528 return mask & (*(dw + dw_offset) >> offset);
531 #define AMAP_GET_BITS(_struct, field, ptr) \
533 offsetof(_struct, field)/32, \
534 amap_mask(sizeof(((_struct *)0)->field)), \
535 AMAP_BIT_OFFSET(_struct, field))
537 #define be_dws_cpu_to_le(wrb, len) swap_dws(wrb, len)
538 #define be_dws_le_to_cpu(wrb, len) swap_dws(wrb, len)
539 static inline void swap_dws(void *wrb, int len)
545 *dw = cpu_to_le32(*dw);
549 #endif /* __BIG_ENDIAN */
552 static inline u8 is_tcp_pkt(struct sk_buff *skb)
556 if (ip_hdr(skb)->version == 4)
557 val = (ip_hdr(skb)->protocol == IPPROTO_TCP);
558 else if (ip_hdr(skb)->version == 6)
559 val = (ipv6_hdr(skb)->nexthdr == NEXTHDR_TCP);
564 static inline u8 is_udp_pkt(struct sk_buff *skb)
568 if (ip_hdr(skb)->version == 4)
569 val = (ip_hdr(skb)->protocol == IPPROTO_UDP);
570 else if (ip_hdr(skb)->version == 6)
571 val = (ipv6_hdr(skb)->nexthdr == NEXTHDR_UDP);
576 static inline void be_vf_eth_addr_generate(struct be_adapter *adapter, u8 *mac)
580 addr = jhash(adapter->netdev->dev_addr, ETH_ALEN, 0);
582 mac[5] = (u8)(addr & 0xFF);
583 mac[4] = (u8)((addr >> 8) & 0xFF);
584 mac[3] = (u8)((addr >> 16) & 0xFF);
585 /* Use the OUI from the current MAC address */
586 memcpy(mac, adapter->netdev->dev_addr, 3);
589 static inline bool be_multi_rxq(const struct be_adapter *adapter)
591 return adapter->num_rx_qs > 1;
594 static inline bool be_error(struct be_adapter *adapter)
596 return adapter->eeh_err || adapter->ue_detected || adapter->fw_timeout;
599 static inline bool be_is_wol_excluded(struct be_adapter *adapter)
601 struct pci_dev *pdev = adapter->pdev;
603 if (!be_physfn(adapter))
606 switch (pdev->subsystem_device) {
607 case OC_SUBSYS_DEVICE_ID1:
608 case OC_SUBSYS_DEVICE_ID2:
609 case OC_SUBSYS_DEVICE_ID3:
610 case OC_SUBSYS_DEVICE_ID4:
617 static inline bool be_type_2_3(struct be_adapter *adapter)
619 return (adapter->if_type == SLI_INTF_TYPE_2 ||
620 adapter->if_type == SLI_INTF_TYPE_3) ? true : false;
623 extern void be_cq_notify(struct be_adapter *adapter, u16 qid, bool arm,
625 extern void be_link_status_update(struct be_adapter *adapter, u8 link_status);
626 extern void be_parse_stats(struct be_adapter *adapter);
627 extern int be_load_fw(struct be_adapter *adapter, u8 *func);
628 extern bool be_is_wol_supported(struct be_adapter *adapter);
629 extern bool be_pause_supported(struct be_adapter *adapter);
630 extern u32 be_get_fw_log_level(struct be_adapter *adapter);
633 * internal function to initialize-cleanup roce device.
635 extern void be_roce_dev_add(struct be_adapter *);
636 extern void be_roce_dev_remove(struct be_adapter *);
639 * internal function to open-close roce device during ifup-ifdown.
641 extern void be_roce_dev_open(struct be_adapter *);
642 extern void be_roce_dev_close(struct be_adapter *);