1 /* sundance.c: A Linux device driver for the Sundance ST201 "Alta". */
3 Written 1999-2000 by Donald Becker.
5 This software may be used and distributed according to the terms of
6 the GNU General Public License (GPL), incorporated herein by reference.
7 Drivers based on or derived from this code fall under the GPL and must
8 retain the authorship, copyright and license notice. This file is not
9 a complete program and may only be used when the entire operating
10 system is licensed under the GPL.
12 The author may be reached as becker@scyld.com, or C/O
13 Scyld Computing Corporation
14 410 Severn Ave., Suite 210
17 Support and updates available at
18 http://www.scyld.com/network/sundance.html
19 [link no longer provides useful info -jgarzik]
20 Archives of the mailing list are still available at
21 http://www.beowulf.org/pipermail/netdrivers/
25 #define DRV_NAME "sundance"
26 #define DRV_VERSION "1.2"
27 #define DRV_RELDATE "11-Sep-2006"
30 /* The user-configurable values.
31 These may be modified when a driver module is loaded.*/
32 static int debug = 1; /* 1 normal messages, 0 quiet .. 7 verbose. */
33 /* Maximum number of multicast addresses to filter (vs. rx-all-multicast).
34 Typical is a 64 element hash table based on the Ethernet CRC. */
35 static const int multicast_filter_limit = 32;
37 /* Set the copy breakpoint for the copy-only-tiny-frames scheme.
38 Setting to > 1518 effectively disables this feature.
39 This chip can receive into offset buffers, so the Alpha does not
41 static int rx_copybreak;
42 static int flowctrl=1;
44 /* media[] specifies the media type the NIC operates at.
45 autosense Autosensing active media.
46 10mbps_hd 10Mbps half duplex.
47 10mbps_fd 10Mbps full duplex.
48 100mbps_hd 100Mbps half duplex.
49 100mbps_fd 100Mbps full duplex.
50 0 Autosensing active media.
53 3 100Mbps half duplex.
54 4 100Mbps full duplex.
57 static char *media[MAX_UNITS];
60 /* Operational parameters that are set at compile time. */
62 /* Keep the ring sizes a power of two for compile efficiency.
63 The compiler will convert <unsigned>'%'<2^N> into a bit mask.
64 Making the Tx ring too large decreases the effectiveness of channel
65 bonding and packet priority, and more than 128 requires modifying the
67 Large receive rings merely waste memory. */
68 #define TX_RING_SIZE 32
69 #define TX_QUEUE_LEN (TX_RING_SIZE - 1) /* Limit ring entries actually used. */
70 #define RX_RING_SIZE 64
72 #define TX_TOTAL_SIZE TX_RING_SIZE*sizeof(struct netdev_desc)
73 #define RX_TOTAL_SIZE RX_RING_SIZE*sizeof(struct netdev_desc)
75 /* Operational parameters that usually are not changed. */
76 /* Time in jiffies before concluding the transmitter is hung. */
77 #define TX_TIMEOUT (4*HZ)
78 #define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer.*/
80 /* Include files, designed to support most kernel versions 2.0.0 and later. */
81 #include <linux/module.h>
82 #include <linux/kernel.h>
83 #include <linux/string.h>
84 #include <linux/timer.h>
85 #include <linux/errno.h>
86 #include <linux/ioport.h>
87 #include <linux/interrupt.h>
88 #include <linux/pci.h>
89 #include <linux/netdevice.h>
90 #include <linux/etherdevice.h>
91 #include <linux/skbuff.h>
92 #include <linux/init.h>
93 #include <linux/bitops.h>
94 #include <asm/uaccess.h>
95 #include <asm/processor.h> /* Processor type for cache alignment. */
97 #include <linux/delay.h>
98 #include <linux/spinlock.h>
99 #include <linux/dma-mapping.h>
100 #include <linux/crc32.h>
101 #include <linux/ethtool.h>
102 #include <linux/mii.h>
104 /* These identify the driver base version and may not be removed. */
105 static const char version[] =
106 KERN_INFO DRV_NAME ".c:v" DRV_VERSION " " DRV_RELDATE
107 " Written by Donald Becker\n";
109 MODULE_AUTHOR("Donald Becker <becker@scyld.com>");
110 MODULE_DESCRIPTION("Sundance Alta Ethernet driver");
111 MODULE_LICENSE("GPL");
113 module_param(debug, int, 0);
114 module_param(rx_copybreak, int, 0);
115 module_param_array(media, charp, NULL, 0);
116 module_param(flowctrl, int, 0);
117 MODULE_PARM_DESC(debug, "Sundance Alta debug level (0-5)");
118 MODULE_PARM_DESC(rx_copybreak, "Sundance Alta copy breakpoint for copy-only-tiny-frames");
119 MODULE_PARM_DESC(flowctrl, "Sundance Alta flow control [0|1]");
124 I. Board Compatibility
126 This driver is designed for the Sundance Technologies "Alta" ST201 chip.
128 II. Board-specific settings
130 III. Driver operation
134 This driver uses two statically allocated fixed-size descriptor lists
135 formed into rings by a branch from the final descriptor to the beginning of
136 the list. The ring sizes are set at compile time by RX/TX_RING_SIZE.
137 Some chips explicitly use only 2^N sized rings, while others use a
138 'next descriptor' pointer that the driver forms into rings.
140 IIIb/c. Transmit/Receive Structure
142 This driver uses a zero-copy receive and transmit scheme.
143 The driver allocates full frame size skbuffs for the Rx ring buffers at
144 open() time and passes the skb->data field to the chip as receive data
145 buffers. When an incoming frame is less than RX_COPYBREAK bytes long,
146 a fresh skbuff is allocated and the frame is copied to the new skbuff.
147 When the incoming frame is larger, the skbuff is passed directly up the
148 protocol stack. Buffers consumed this way are replaced by newly allocated
149 skbuffs in a later phase of receives.
151 The RX_COPYBREAK value is chosen to trade-off the memory wasted by
152 using a full-sized skbuff for small frames vs. the copying costs of larger
153 frames. New boards are typically used in generously configured machines
154 and the underfilled buffers have negligible impact compared to the benefit of
155 a single allocation size, so the default value of zero results in never
156 copying packets. When copying is done, the cost is usually mitigated by using
157 a combined copy/checksum routine. Copying also preloads the cache, which is
158 most useful with small frames.
160 A subtle aspect of the operation is that the IP header at offset 14 in an
161 ethernet frame isn't longword aligned for further processing.
162 Unaligned buffers are permitted by the Sundance hardware, so
163 frames are received into the skbuff at an offset of "+2", 16-byte aligning
166 IIId. Synchronization
168 The driver runs as two independent, single-threaded flows of control. One
169 is the send-packet routine, which enforces single-threaded use by the
170 dev->tbusy flag. The other thread is the interrupt handler, which is single
171 threaded by the hardware and interrupt handling software.
173 The send packet thread has partial control over the Tx ring and 'dev->tbusy'
174 flag. It sets the tbusy flag whenever it's queuing a Tx packet. If the next
175 queue slot is empty, it clears the tbusy flag when finished otherwise it sets
176 the 'lp->tx_full' flag.
178 The interrupt handler has exclusive control over the Rx ring and records stats
179 from the Tx ring. After reaping the stats, it marks the Tx queue entry as
180 empty by incrementing the dirty_tx mark. Iff the 'lp->tx_full' flag is set, it
181 clears both the tx_full and tbusy flags.
187 The Sundance ST201 datasheet, preliminary version.
188 The Kendin KS8723 datasheet, preliminary version.
189 The ICplus IP100 datasheet, preliminary version.
190 http://www.scyld.com/expert/100mbps.html
191 http://www.scyld.com/expert/NWay.html
197 /* Work-around for Kendin chip bugs. */
198 #ifndef CONFIG_SUNDANCE_MMIO
202 static const struct pci_device_id sundance_pci_tbl[] = {
203 { 0x1186, 0x1002, 0x1186, 0x1002, 0, 0, 0 },
204 { 0x1186, 0x1002, 0x1186, 0x1003, 0, 0, 1 },
205 { 0x1186, 0x1002, 0x1186, 0x1012, 0, 0, 2 },
206 { 0x1186, 0x1002, 0x1186, 0x1040, 0, 0, 3 },
207 { 0x1186, 0x1002, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4 },
208 { 0x13F0, 0x0201, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5 },
209 { 0x13F0, 0x0200, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 6 },
212 MODULE_DEVICE_TABLE(pci, sundance_pci_tbl);
221 static const struct pci_id_info pci_id_tbl[] = {
222 {"D-Link DFE-550TX FAST Ethernet Adapter"},
223 {"D-Link DFE-550FX 100Mbps Fiber-optics Adapter"},
224 {"D-Link DFE-580TX 4 port Server Adapter"},
225 {"D-Link DFE-530TXS FAST Ethernet Adapter"},
226 {"D-Link DL10050-based FAST Ethernet Adapter"},
227 {"Sundance Technology Alta"},
228 {"IC Plus Corporation IP100A FAST Ethernet Adapter"},
229 { } /* terminate list. */
232 /* This driver was written to use PCI memory space, however x86-oriented
233 hardware often uses I/O space accesses. */
235 /* Offsets to the device registers.
236 Unlike software-only systems, device drivers interact with complex hardware.
237 It's not useful to define symbolic names for every register bit in the
238 device. The name can only partially document the semantics and make
239 the driver longer and more difficult to read.
240 In general, only the important configuration values or bits changed
241 multiple times should be defined symbolically.
246 TxDMABurstThresh = 0x08,
247 TxDMAUrgentThresh = 0x09,
248 TxDMAPollPeriod = 0x0a,
253 RxDMABurstThresh = 0x14,
254 RxDMAUrgentThresh = 0x15,
255 RxDMAPollPeriod = 0x16,
275 MulticastFilter0 = 0x60,
276 MulticastFilter1 = 0x64,
283 StatsCarrierError = 0x74,
284 StatsLateColl = 0x75,
285 StatsMultiColl = 0x76,
289 StatsTxXSDefer = 0x7a,
295 /* Aliased and bogus values! */
299 #define ASIC_HI_WORD(x) ((x) + 2)
301 enum ASICCtrl_HiWord_bit {
302 GlobalReset = 0x0001,
307 NetworkReset = 0x0020,
312 /* Bits in the interrupt status/mask registers. */
313 enum intr_status_bits {
314 IntrSummary=0x0001, IntrPCIErr=0x0002, IntrMACCtrl=0x0008,
315 IntrTxDone=0x0004, IntrRxDone=0x0010, IntrRxStart=0x0020,
317 StatsMax=0x0080, LinkChange=0x0100,
318 IntrTxDMADone=0x0200, IntrRxDMADone=0x0400,
321 /* Bits in the RxMode register. */
323 AcceptAllIPMulti=0x20, AcceptMultiHash=0x10, AcceptAll=0x08,
324 AcceptBroadcast=0x04, AcceptMulticast=0x02, AcceptMyPhys=0x01,
326 /* Bits in MACCtrl. */
327 enum mac_ctrl0_bits {
328 EnbFullDuplex=0x20, EnbRcvLargeFrame=0x40,
329 EnbFlowCtrl=0x100, EnbPassRxCRC=0x200,
331 enum mac_ctrl1_bits {
332 StatsEnable=0x0020, StatsDisable=0x0040, StatsEnabled=0x0080,
333 TxEnable=0x0100, TxDisable=0x0200, TxEnabled=0x0400,
334 RxEnable=0x0800, RxDisable=0x1000, RxEnabled=0x2000,
337 /* Bits in WakeEvent register. */
338 enum wake_event_bits {
339 WakePktEnable = 0x01,
340 MagicPktEnable = 0x02,
341 LinkEventEnable = 0x04,
345 /* The Rx and Tx buffer descriptors. */
346 /* Note that using only 32 bit fields simplifies conversion to big-endian
351 struct desc_frag { __le32 addr, length; } frag[1];
354 /* Bits in netdev_desc.status */
355 enum desc_status_bits {
357 DescEndPacket=0x4000,
361 DescIntrOnDMADone=0x80000000,
362 DisableAlign = 0x00000001,
365 #define PRIV_ALIGN 15 /* Required alignment mask */
366 /* Use __attribute__((aligned (L1_CACHE_BYTES))) to maintain alignment
367 within the structure. */
369 struct netdev_private {
370 /* Descriptor rings first for alignment. */
371 struct netdev_desc *rx_ring;
372 struct netdev_desc *tx_ring;
373 struct sk_buff* rx_skbuff[RX_RING_SIZE];
374 struct sk_buff* tx_skbuff[TX_RING_SIZE];
375 dma_addr_t tx_ring_dma;
376 dma_addr_t rx_ring_dma;
377 struct timer_list timer; /* Media monitoring timer. */
378 /* ethtool extra stats */
380 u64 tx_multiple_collisions;
381 u64 tx_single_collisions;
382 u64 tx_late_collisions;
384 u64 tx_deferred_excessive;
391 /* Frequently used values: keep some adjacent for cache effect. */
395 unsigned int cur_rx, dirty_rx; /* Producer/consumer ring indices */
396 unsigned int rx_buf_sz; /* Based on MTU+slack. */
397 struct netdev_desc *last_tx; /* Last Tx descriptor used. */
398 unsigned int cur_tx, dirty_tx;
399 /* These values are keep track of the transceiver/media in use. */
400 unsigned int flowctrl:1;
401 unsigned int default_port:4; /* Last dev->if_port value. */
402 unsigned int an_enable:1;
404 unsigned int wol_enabled:1; /* Wake on LAN enabled */
405 struct tasklet_struct rx_tasklet;
406 struct tasklet_struct tx_tasklet;
409 /* Multicast and receive mode. */
410 spinlock_t mcastlock; /* SMP lock multicast updates. */
412 /* MII transceiver section. */
413 struct mii_if_info mii_if;
414 int mii_preamble_required;
415 unsigned char phys[MII_CNT]; /* MII device addresses, only first one used. */
416 struct pci_dev *pci_dev;
421 /* The station address location in the EEPROM. */
422 #define EEPROM_SA_OFFSET 0x10
423 #define DEFAULT_INTR (IntrRxDMADone | IntrPCIErr | \
424 IntrDrvRqst | IntrTxDone | StatsMax | \
427 static int change_mtu(struct net_device *dev, int new_mtu);
428 static int eeprom_read(void __iomem *ioaddr, int location);
429 static int mdio_read(struct net_device *dev, int phy_id, int location);
430 static void mdio_write(struct net_device *dev, int phy_id, int location, int value);
431 static int mdio_wait_link(struct net_device *dev, int wait);
432 static int netdev_open(struct net_device *dev);
433 static void check_duplex(struct net_device *dev);
434 static void netdev_timer(unsigned long data);
435 static void tx_timeout(struct net_device *dev);
436 static void init_ring(struct net_device *dev);
437 static netdev_tx_t start_tx(struct sk_buff *skb, struct net_device *dev);
438 static int reset_tx (struct net_device *dev);
439 static irqreturn_t intr_handler(int irq, void *dev_instance);
440 static void rx_poll(unsigned long data);
441 static void tx_poll(unsigned long data);
442 static void refill_rx (struct net_device *dev);
443 static void netdev_error(struct net_device *dev, int intr_status);
444 static void netdev_error(struct net_device *dev, int intr_status);
445 static void set_rx_mode(struct net_device *dev);
446 static int __set_mac_addr(struct net_device *dev);
447 static int sundance_set_mac_addr(struct net_device *dev, void *data);
448 static struct net_device_stats *get_stats(struct net_device *dev);
449 static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
450 static int netdev_close(struct net_device *dev);
451 static const struct ethtool_ops ethtool_ops;
453 static void sundance_reset(struct net_device *dev, unsigned long reset_cmd)
455 struct netdev_private *np = netdev_priv(dev);
456 void __iomem *ioaddr = np->base + ASICCtrl;
459 /* ST201 documentation states ASICCtrl is a 32bit register */
460 iowrite32 (reset_cmd | ioread32 (ioaddr), ioaddr);
461 /* ST201 documentation states reset can take up to 1 ms */
463 while (ioread32 (ioaddr) & (ResetBusy << 16)) {
464 if (--countdown == 0) {
465 printk(KERN_WARNING "%s : reset not completed !!\n", dev->name);
472 #ifdef CONFIG_NET_POLL_CONTROLLER
473 static void sundance_poll_controller(struct net_device *dev)
475 struct netdev_private *np = netdev_priv(dev);
477 disable_irq(np->pci_dev->irq);
478 intr_handler(np->pci_dev->irq, dev);
479 enable_irq(np->pci_dev->irq);
483 static const struct net_device_ops netdev_ops = {
484 .ndo_open = netdev_open,
485 .ndo_stop = netdev_close,
486 .ndo_start_xmit = start_tx,
487 .ndo_get_stats = get_stats,
488 .ndo_set_rx_mode = set_rx_mode,
489 .ndo_do_ioctl = netdev_ioctl,
490 .ndo_tx_timeout = tx_timeout,
491 .ndo_change_mtu = change_mtu,
492 .ndo_set_mac_address = sundance_set_mac_addr,
493 .ndo_validate_addr = eth_validate_addr,
494 #ifdef CONFIG_NET_POLL_CONTROLLER
495 .ndo_poll_controller = sundance_poll_controller,
499 static int sundance_probe1(struct pci_dev *pdev,
500 const struct pci_device_id *ent)
502 struct net_device *dev;
503 struct netdev_private *np;
505 int chip_idx = ent->driver_data;
508 void __iomem *ioaddr;
517 int phy, phy_end, phy_idx = 0;
519 /* when built into the kernel, we only print version if device is found */
521 static int printed_version;
522 if (!printed_version++)
526 if (pci_enable_device(pdev))
528 pci_set_master(pdev);
532 dev = alloc_etherdev(sizeof(*np));
535 SET_NETDEV_DEV(dev, &pdev->dev);
537 if (pci_request_regions(pdev, DRV_NAME))
540 ioaddr = pci_iomap(pdev, bar, netdev_io_size);
544 for (i = 0; i < 3; i++)
545 ((__le16 *)dev->dev_addr)[i] =
546 cpu_to_le16(eeprom_read(ioaddr, i + EEPROM_SA_OFFSET));
548 np = netdev_priv(dev);
551 np->chip_id = chip_idx;
552 np->msg_enable = (1 << debug) - 1;
553 spin_lock_init(&np->lock);
554 spin_lock_init(&np->statlock);
555 tasklet_init(&np->rx_tasklet, rx_poll, (unsigned long)dev);
556 tasklet_init(&np->tx_tasklet, tx_poll, (unsigned long)dev);
558 ring_space = dma_alloc_coherent(&pdev->dev, TX_TOTAL_SIZE,
559 &ring_dma, GFP_KERNEL);
561 goto err_out_cleardev;
562 np->tx_ring = (struct netdev_desc *)ring_space;
563 np->tx_ring_dma = ring_dma;
565 ring_space = dma_alloc_coherent(&pdev->dev, RX_TOTAL_SIZE,
566 &ring_dma, GFP_KERNEL);
568 goto err_out_unmap_tx;
569 np->rx_ring = (struct netdev_desc *)ring_space;
570 np->rx_ring_dma = ring_dma;
572 np->mii_if.dev = dev;
573 np->mii_if.mdio_read = mdio_read;
574 np->mii_if.mdio_write = mdio_write;
575 np->mii_if.phy_id_mask = 0x1f;
576 np->mii_if.reg_num_mask = 0x1f;
578 /* The chip-specific entries in the device structure. */
579 dev->netdev_ops = &netdev_ops;
580 dev->ethtool_ops = ðtool_ops;
581 dev->watchdog_timeo = TX_TIMEOUT;
583 /* MTU range: 68 - 8191 */
584 dev->min_mtu = ETH_MIN_MTU;
587 pci_set_drvdata(pdev, dev);
589 i = register_netdev(dev);
591 goto err_out_unmap_rx;
593 printk(KERN_INFO "%s: %s at %p, %pM, IRQ %d.\n",
594 dev->name, pci_id_tbl[chip_idx].name, ioaddr,
597 np->phys[0] = 1; /* Default setting */
598 np->mii_preamble_required++;
601 * It seems some phys doesn't deal well with address 0 being accessed
604 if (sundance_pci_tbl[np->chip_id].device == 0x0200) {
609 phy_end = 32; /* wraps to zero, due to 'phy & 0x1f' */
611 for (; phy <= phy_end && phy_idx < MII_CNT; phy++) {
612 int phyx = phy & 0x1f;
613 int mii_status = mdio_read(dev, phyx, MII_BMSR);
614 if (mii_status != 0xffff && mii_status != 0x0000) {
615 np->phys[phy_idx++] = phyx;
616 np->mii_if.advertising = mdio_read(dev, phyx, MII_ADVERTISE);
617 if ((mii_status & 0x0040) == 0)
618 np->mii_preamble_required++;
619 printk(KERN_INFO "%s: MII PHY found at address %d, status "
620 "0x%4.4x advertising %4.4x.\n",
621 dev->name, phyx, mii_status, np->mii_if.advertising);
624 np->mii_preamble_required--;
627 printk(KERN_INFO "%s: No MII transceiver found, aborting. ASIC status %x\n",
628 dev->name, ioread32(ioaddr + ASICCtrl));
629 goto err_out_unregister;
632 np->mii_if.phy_id = np->phys[0];
634 /* Parse override configuration */
636 if (card_idx < MAX_UNITS) {
637 if (media[card_idx] != NULL) {
639 if (strcmp (media[card_idx], "100mbps_fd") == 0 ||
640 strcmp (media[card_idx], "4") == 0) {
642 np->mii_if.full_duplex = 1;
643 } else if (strcmp (media[card_idx], "100mbps_hd") == 0 ||
644 strcmp (media[card_idx], "3") == 0) {
646 np->mii_if.full_duplex = 0;
647 } else if (strcmp (media[card_idx], "10mbps_fd") == 0 ||
648 strcmp (media[card_idx], "2") == 0) {
650 np->mii_if.full_duplex = 1;
651 } else if (strcmp (media[card_idx], "10mbps_hd") == 0 ||
652 strcmp (media[card_idx], "1") == 0) {
654 np->mii_if.full_duplex = 0;
664 if (ioread32 (ioaddr + ASICCtrl) & 0x80) {
665 /* Default 100Mbps Full */
668 np->mii_if.full_duplex = 1;
673 mdio_write (dev, np->phys[0], MII_BMCR, BMCR_RESET);
675 /* If flow control enabled, we need to advertise it.*/
677 mdio_write (dev, np->phys[0], MII_ADVERTISE, np->mii_if.advertising | 0x0400);
678 mdio_write (dev, np->phys[0], MII_BMCR, BMCR_ANENABLE|BMCR_ANRESTART);
679 /* Force media type */
680 if (!np->an_enable) {
682 mii_ctl |= (np->speed == 100) ? BMCR_SPEED100 : 0;
683 mii_ctl |= (np->mii_if.full_duplex) ? BMCR_FULLDPLX : 0;
684 mdio_write (dev, np->phys[0], MII_BMCR, mii_ctl);
685 printk (KERN_INFO "Override speed=%d, %s duplex\n",
686 np->speed, np->mii_if.full_duplex ? "Full" : "Half");
690 /* Perhaps move the reset here? */
691 /* Reset the chip to erase previous misconfiguration. */
692 if (netif_msg_hw(np))
693 printk("ASIC Control is %x.\n", ioread32(ioaddr + ASICCtrl));
694 sundance_reset(dev, 0x00ff << 16);
695 if (netif_msg_hw(np))
696 printk("ASIC Control is now %x.\n", ioread32(ioaddr + ASICCtrl));
702 unregister_netdev(dev);
704 dma_free_coherent(&pdev->dev, RX_TOTAL_SIZE,
705 np->rx_ring, np->rx_ring_dma);
707 dma_free_coherent(&pdev->dev, TX_TOTAL_SIZE,
708 np->tx_ring, np->tx_ring_dma);
710 pci_iounmap(pdev, ioaddr);
712 pci_release_regions(pdev);
718 static int change_mtu(struct net_device *dev, int new_mtu)
720 if (netif_running(dev))
726 #define eeprom_delay(ee_addr) ioread32(ee_addr)
727 /* Read the EEPROM and MII Management Data I/O (MDIO) interfaces. */
728 static int eeprom_read(void __iomem *ioaddr, int location)
730 int boguscnt = 10000; /* Typical 1900 ticks. */
731 iowrite16(0x0200 | (location & 0xff), ioaddr + EECtrl);
733 eeprom_delay(ioaddr + EECtrl);
734 if (! (ioread16(ioaddr + EECtrl) & 0x8000)) {
735 return ioread16(ioaddr + EEData);
737 } while (--boguscnt > 0);
741 /* MII transceiver control section.
742 Read and write the MII registers using software-generated serial
743 MDIO protocol. See the MII specifications or DP83840A data sheet
746 The maximum data clock rate is 2.5 Mhz. The minimum timing is usually
747 met by back-to-back 33Mhz PCI cycles. */
748 #define mdio_delay() ioread8(mdio_addr)
751 MDIO_ShiftClk=0x0001, MDIO_Data=0x0002, MDIO_EnbOutput=0x0004,
753 #define MDIO_EnbIn (0)
754 #define MDIO_WRITE0 (MDIO_EnbOutput)
755 #define MDIO_WRITE1 (MDIO_Data | MDIO_EnbOutput)
757 /* Generate the preamble required for initial synchronization and
758 a few older transceivers. */
759 static void mdio_sync(void __iomem *mdio_addr)
763 /* Establish sync by sending at least 32 logic ones. */
764 while (--bits >= 0) {
765 iowrite8(MDIO_WRITE1, mdio_addr);
767 iowrite8(MDIO_WRITE1 | MDIO_ShiftClk, mdio_addr);
772 static int mdio_read(struct net_device *dev, int phy_id, int location)
774 struct netdev_private *np = netdev_priv(dev);
775 void __iomem *mdio_addr = np->base + MIICtrl;
776 int mii_cmd = (0xf6 << 10) | (phy_id << 5) | location;
779 if (np->mii_preamble_required)
780 mdio_sync(mdio_addr);
782 /* Shift the read command bits out. */
783 for (i = 15; i >= 0; i--) {
784 int dataval = (mii_cmd & (1 << i)) ? MDIO_WRITE1 : MDIO_WRITE0;
786 iowrite8(dataval, mdio_addr);
788 iowrite8(dataval | MDIO_ShiftClk, mdio_addr);
791 /* Read the two transition, 16 data, and wire-idle bits. */
792 for (i = 19; i > 0; i--) {
793 iowrite8(MDIO_EnbIn, mdio_addr);
795 retval = (retval << 1) | ((ioread8(mdio_addr) & MDIO_Data) ? 1 : 0);
796 iowrite8(MDIO_EnbIn | MDIO_ShiftClk, mdio_addr);
799 return (retval>>1) & 0xffff;
802 static void mdio_write(struct net_device *dev, int phy_id, int location, int value)
804 struct netdev_private *np = netdev_priv(dev);
805 void __iomem *mdio_addr = np->base + MIICtrl;
806 int mii_cmd = (0x5002 << 16) | (phy_id << 23) | (location<<18) | value;
809 if (np->mii_preamble_required)
810 mdio_sync(mdio_addr);
812 /* Shift the command bits out. */
813 for (i = 31; i >= 0; i--) {
814 int dataval = (mii_cmd & (1 << i)) ? MDIO_WRITE1 : MDIO_WRITE0;
816 iowrite8(dataval, mdio_addr);
818 iowrite8(dataval | MDIO_ShiftClk, mdio_addr);
821 /* Clear out extra bits. */
822 for (i = 2; i > 0; i--) {
823 iowrite8(MDIO_EnbIn, mdio_addr);
825 iowrite8(MDIO_EnbIn | MDIO_ShiftClk, mdio_addr);
830 static int mdio_wait_link(struct net_device *dev, int wait)
834 struct netdev_private *np;
836 np = netdev_priv(dev);
837 phy_id = np->phys[0];
840 bmsr = mdio_read(dev, phy_id, MII_BMSR);
844 } while (--wait > 0);
848 static int netdev_open(struct net_device *dev)
850 struct netdev_private *np = netdev_priv(dev);
851 void __iomem *ioaddr = np->base;
852 const int irq = np->pci_dev->irq;
856 sundance_reset(dev, 0x00ff << 16);
858 i = request_irq(irq, intr_handler, IRQF_SHARED, dev->name, dev);
862 if (netif_msg_ifup(np))
863 printk(KERN_DEBUG "%s: netdev_open() irq %d\n", dev->name, irq);
867 iowrite32(np->rx_ring_dma, ioaddr + RxListPtr);
868 /* The Tx list pointer is written as packets are queued. */
870 /* Initialize other registers. */
872 #if IS_ENABLED(CONFIG_VLAN_8021Q)
873 iowrite16(dev->mtu + 18, ioaddr + MaxFrameSize);
875 iowrite16(dev->mtu + 14, ioaddr + MaxFrameSize);
878 iowrite32(ioread32(ioaddr + ASICCtrl) | 0x0C, ioaddr + ASICCtrl);
880 /* Configure the PCI bus bursts and FIFO thresholds. */
882 if (dev->if_port == 0)
883 dev->if_port = np->default_port;
885 spin_lock_init(&np->mcastlock);
888 iowrite16(0, ioaddr + IntrEnable);
889 iowrite16(0, ioaddr + DownCounter);
890 /* Set the chip to poll every N*320nsec. */
891 iowrite8(100, ioaddr + RxDMAPollPeriod);
892 iowrite8(127, ioaddr + TxDMAPollPeriod);
893 /* Fix DFE-580TX packet drop issue */
894 if (np->pci_dev->revision >= 0x14)
895 iowrite8(0x01, ioaddr + DebugCtrl1);
896 netif_start_queue(dev);
898 spin_lock_irqsave(&np->lock, flags);
900 spin_unlock_irqrestore(&np->lock, flags);
902 iowrite16 (StatsEnable | RxEnable | TxEnable, ioaddr + MACCtrl1);
905 iowrite8(ioread8(ioaddr + WakeEvent) | 0x00, ioaddr + WakeEvent);
908 if (netif_msg_ifup(np))
909 printk(KERN_DEBUG "%s: Done netdev_open(), status: Rx %x Tx %x "
910 "MAC Control %x, %4.4x %4.4x.\n",
911 dev->name, ioread32(ioaddr + RxStatus), ioread8(ioaddr + TxStatus),
912 ioread32(ioaddr + MACCtrl0),
913 ioread16(ioaddr + MACCtrl1), ioread16(ioaddr + MACCtrl0));
915 /* Set the timer to check for link beat. */
916 init_timer(&np->timer);
917 np->timer.expires = jiffies + 3*HZ;
918 np->timer.data = (unsigned long)dev;
919 np->timer.function = netdev_timer; /* timer handler */
920 add_timer(&np->timer);
922 /* Enable interrupts by setting the interrupt mask. */
923 iowrite16(DEFAULT_INTR, ioaddr + IntrEnable);
928 static void check_duplex(struct net_device *dev)
930 struct netdev_private *np = netdev_priv(dev);
931 void __iomem *ioaddr = np->base;
932 int mii_lpa = mdio_read(dev, np->phys[0], MII_LPA);
933 int negotiated = mii_lpa & np->mii_if.advertising;
937 if (!np->an_enable || mii_lpa == 0xffff) {
938 if (np->mii_if.full_duplex)
939 iowrite16 (ioread16 (ioaddr + MACCtrl0) | EnbFullDuplex,
944 /* Autonegotiation */
945 duplex = (negotiated & 0x0100) || (negotiated & 0x01C0) == 0x0040;
946 if (np->mii_if.full_duplex != duplex) {
947 np->mii_if.full_duplex = duplex;
948 if (netif_msg_link(np))
949 printk(KERN_INFO "%s: Setting %s-duplex based on MII #%d "
950 "negotiated capability %4.4x.\n", dev->name,
951 duplex ? "full" : "half", np->phys[0], negotiated);
952 iowrite16(ioread16(ioaddr + MACCtrl0) | (duplex ? 0x20 : 0), ioaddr + MACCtrl0);
956 static void netdev_timer(unsigned long data)
958 struct net_device *dev = (struct net_device *)data;
959 struct netdev_private *np = netdev_priv(dev);
960 void __iomem *ioaddr = np->base;
961 int next_tick = 10*HZ;
963 if (netif_msg_timer(np)) {
964 printk(KERN_DEBUG "%s: Media selection timer tick, intr status %4.4x, "
966 dev->name, ioread16(ioaddr + IntrEnable),
967 ioread8(ioaddr + TxStatus), ioread32(ioaddr + RxStatus));
970 np->timer.expires = jiffies + next_tick;
971 add_timer(&np->timer);
974 static void tx_timeout(struct net_device *dev)
976 struct netdev_private *np = netdev_priv(dev);
977 void __iomem *ioaddr = np->base;
980 netif_stop_queue(dev);
981 tasklet_disable(&np->tx_tasklet);
982 iowrite16(0, ioaddr + IntrEnable);
983 printk(KERN_WARNING "%s: Transmit timed out, TxStatus %2.2x "
985 " resetting...\n", dev->name, ioread8(ioaddr + TxStatus),
986 ioread8(ioaddr + TxFrameId));
990 for (i=0; i<TX_RING_SIZE; i++) {
991 printk(KERN_DEBUG "%02x %08llx %08x %08x(%02x) %08x %08x\n", i,
992 (unsigned long long)(np->tx_ring_dma + i*sizeof(*np->tx_ring)),
993 le32_to_cpu(np->tx_ring[i].next_desc),
994 le32_to_cpu(np->tx_ring[i].status),
995 (le32_to_cpu(np->tx_ring[i].status) >> 2) & 0xff,
996 le32_to_cpu(np->tx_ring[i].frag[0].addr),
997 le32_to_cpu(np->tx_ring[i].frag[0].length));
999 printk(KERN_DEBUG "TxListPtr=%08x netif_queue_stopped=%d\n",
1000 ioread32(np->base + TxListPtr),
1001 netif_queue_stopped(dev));
1002 printk(KERN_DEBUG "cur_tx=%d(%02x) dirty_tx=%d(%02x)\n",
1003 np->cur_tx, np->cur_tx % TX_RING_SIZE,
1004 np->dirty_tx, np->dirty_tx % TX_RING_SIZE);
1005 printk(KERN_DEBUG "cur_rx=%d dirty_rx=%d\n", np->cur_rx, np->dirty_rx);
1006 printk(KERN_DEBUG "cur_task=%d\n", np->cur_task);
1008 spin_lock_irqsave(&np->lock, flag);
1010 /* Stop and restart the chip's Tx processes . */
1012 spin_unlock_irqrestore(&np->lock, flag);
1016 netif_trans_update(dev); /* prevent tx timeout */
1017 dev->stats.tx_errors++;
1018 if (np->cur_tx - np->dirty_tx < TX_QUEUE_LEN - 4) {
1019 netif_wake_queue(dev);
1021 iowrite16(DEFAULT_INTR, ioaddr + IntrEnable);
1022 tasklet_enable(&np->tx_tasklet);
1026 /* Initialize the Rx and Tx rings, along with various 'dev' bits. */
1027 static void init_ring(struct net_device *dev)
1029 struct netdev_private *np = netdev_priv(dev);
1032 np->cur_rx = np->cur_tx = 0;
1033 np->dirty_rx = np->dirty_tx = 0;
1036 np->rx_buf_sz = (dev->mtu <= 1520 ? PKT_BUF_SZ : dev->mtu + 16);
1038 /* Initialize all Rx descriptors. */
1039 for (i = 0; i < RX_RING_SIZE; i++) {
1040 np->rx_ring[i].next_desc = cpu_to_le32(np->rx_ring_dma +
1041 ((i+1)%RX_RING_SIZE)*sizeof(*np->rx_ring));
1042 np->rx_ring[i].status = 0;
1043 np->rx_ring[i].frag[0].length = 0;
1044 np->rx_skbuff[i] = NULL;
1047 /* Fill in the Rx buffers. Handle allocation failure gracefully. */
1048 for (i = 0; i < RX_RING_SIZE; i++) {
1049 struct sk_buff *skb =
1050 netdev_alloc_skb(dev, np->rx_buf_sz + 2);
1051 np->rx_skbuff[i] = skb;
1054 skb_reserve(skb, 2); /* 16 byte align the IP header. */
1055 np->rx_ring[i].frag[0].addr = cpu_to_le32(
1056 dma_map_single(&np->pci_dev->dev, skb->data,
1057 np->rx_buf_sz, DMA_FROM_DEVICE));
1058 if (dma_mapping_error(&np->pci_dev->dev,
1059 np->rx_ring[i].frag[0].addr)) {
1061 np->rx_skbuff[i] = NULL;
1064 np->rx_ring[i].frag[0].length = cpu_to_le32(np->rx_buf_sz | LastFrag);
1066 np->dirty_rx = (unsigned int)(i - RX_RING_SIZE);
1068 for (i = 0; i < TX_RING_SIZE; i++) {
1069 np->tx_skbuff[i] = NULL;
1070 np->tx_ring[i].status = 0;
1074 static void tx_poll (unsigned long data)
1076 struct net_device *dev = (struct net_device *)data;
1077 struct netdev_private *np = netdev_priv(dev);
1078 unsigned head = np->cur_task % TX_RING_SIZE;
1079 struct netdev_desc *txdesc =
1080 &np->tx_ring[(np->cur_tx - 1) % TX_RING_SIZE];
1082 /* Chain the next pointer */
1083 for (; np->cur_tx - np->cur_task > 0; np->cur_task++) {
1084 int entry = np->cur_task % TX_RING_SIZE;
1085 txdesc = &np->tx_ring[entry];
1087 np->last_tx->next_desc = cpu_to_le32(np->tx_ring_dma +
1088 entry*sizeof(struct netdev_desc));
1090 np->last_tx = txdesc;
1092 /* Indicate the latest descriptor of tx ring */
1093 txdesc->status |= cpu_to_le32(DescIntrOnTx);
1095 if (ioread32 (np->base + TxListPtr) == 0)
1096 iowrite32 (np->tx_ring_dma + head * sizeof(struct netdev_desc),
1097 np->base + TxListPtr);
1101 start_tx (struct sk_buff *skb, struct net_device *dev)
1103 struct netdev_private *np = netdev_priv(dev);
1104 struct netdev_desc *txdesc;
1107 /* Calculate the next Tx descriptor entry. */
1108 entry = np->cur_tx % TX_RING_SIZE;
1109 np->tx_skbuff[entry] = skb;
1110 txdesc = &np->tx_ring[entry];
1112 txdesc->next_desc = 0;
1113 txdesc->status = cpu_to_le32 ((entry << 2) | DisableAlign);
1114 txdesc->frag[0].addr = cpu_to_le32(dma_map_single(&np->pci_dev->dev,
1115 skb->data, skb->len, DMA_TO_DEVICE));
1116 if (dma_mapping_error(&np->pci_dev->dev,
1117 txdesc->frag[0].addr))
1119 txdesc->frag[0].length = cpu_to_le32 (skb->len | LastFrag);
1121 /* Increment cur_tx before tasklet_schedule() */
1124 /* Schedule a tx_poll() task */
1125 tasklet_schedule(&np->tx_tasklet);
1127 /* On some architectures: explicitly flush cache lines here. */
1128 if (np->cur_tx - np->dirty_tx < TX_QUEUE_LEN - 1 &&
1129 !netif_queue_stopped(dev)) {
1132 netif_stop_queue (dev);
1134 if (netif_msg_tx_queued(np)) {
1136 "%s: Transmit frame #%d queued in slot %d.\n",
1137 dev->name, np->cur_tx, entry);
1139 return NETDEV_TX_OK;
1142 dev_kfree_skb_any(skb);
1143 np->tx_skbuff[entry] = NULL;
1144 dev->stats.tx_dropped++;
1145 return NETDEV_TX_OK;
1148 /* Reset hardware tx and free all of tx buffers */
1150 reset_tx (struct net_device *dev)
1152 struct netdev_private *np = netdev_priv(dev);
1153 void __iomem *ioaddr = np->base;
1154 struct sk_buff *skb;
1157 /* Reset tx logic, TxListPtr will be cleaned */
1158 iowrite16 (TxDisable, ioaddr + MACCtrl1);
1159 sundance_reset(dev, (NetworkReset|FIFOReset|DMAReset|TxReset) << 16);
1161 /* free all tx skbuff */
1162 for (i = 0; i < TX_RING_SIZE; i++) {
1163 np->tx_ring[i].next_desc = 0;
1165 skb = np->tx_skbuff[i];
1167 dma_unmap_single(&np->pci_dev->dev,
1168 le32_to_cpu(np->tx_ring[i].frag[0].addr),
1169 skb->len, DMA_TO_DEVICE);
1170 dev_kfree_skb_any(skb);
1171 np->tx_skbuff[i] = NULL;
1172 dev->stats.tx_dropped++;
1175 np->cur_tx = np->dirty_tx = 0;
1179 iowrite8(127, ioaddr + TxDMAPollPeriod);
1181 iowrite16 (StatsEnable | RxEnable | TxEnable, ioaddr + MACCtrl1);
1185 /* The interrupt handler cleans up after the Tx thread,
1186 and schedule a Rx thread work */
1187 static irqreturn_t intr_handler(int irq, void *dev_instance)
1189 struct net_device *dev = (struct net_device *)dev_instance;
1190 struct netdev_private *np = netdev_priv(dev);
1191 void __iomem *ioaddr = np->base;
1200 int intr_status = ioread16(ioaddr + IntrStatus);
1201 iowrite16(intr_status, ioaddr + IntrStatus);
1203 if (netif_msg_intr(np))
1204 printk(KERN_DEBUG "%s: Interrupt, status %4.4x.\n",
1205 dev->name, intr_status);
1207 if (!(intr_status & DEFAULT_INTR))
1212 if (intr_status & (IntrRxDMADone)) {
1213 iowrite16(DEFAULT_INTR & ~(IntrRxDone|IntrRxDMADone),
1214 ioaddr + IntrEnable);
1216 np->budget = RX_BUDGET;
1217 tasklet_schedule(&np->rx_tasklet);
1219 if (intr_status & (IntrTxDone | IntrDrvRqst)) {
1220 tx_status = ioread16 (ioaddr + TxStatus);
1221 for (tx_cnt=32; tx_status & 0x80; --tx_cnt) {
1222 if (netif_msg_tx_done(np))
1224 ("%s: Transmit status is %2.2x.\n",
1225 dev->name, tx_status);
1226 if (tx_status & 0x1e) {
1227 if (netif_msg_tx_err(np))
1228 printk("%s: Transmit error status %4.4x.\n",
1229 dev->name, tx_status);
1230 dev->stats.tx_errors++;
1231 if (tx_status & 0x10)
1232 dev->stats.tx_fifo_errors++;
1233 if (tx_status & 0x08)
1234 dev->stats.collisions++;
1235 if (tx_status & 0x04)
1236 dev->stats.tx_fifo_errors++;
1237 if (tx_status & 0x02)
1238 dev->stats.tx_window_errors++;
1241 ** This reset has been verified on
1242 ** DFE-580TX boards ! phdm@macqel.be.
1244 if (tx_status & 0x10) { /* TxUnderrun */
1245 /* Restart Tx FIFO and transmitter */
1246 sundance_reset(dev, (NetworkReset|FIFOReset|TxReset) << 16);
1247 /* No need to reset the Tx pointer here */
1249 /* Restart the Tx. Need to make sure tx enabled */
1252 iowrite16(ioread16(ioaddr + MACCtrl1) | TxEnable, ioaddr + MACCtrl1);
1253 if (ioread16(ioaddr + MACCtrl1) & TxEnabled)
1258 /* Yup, this is a documentation bug. It cost me *hours*. */
1259 iowrite16 (0, ioaddr + TxStatus);
1261 iowrite32(5000, ioaddr + DownCounter);
1264 tx_status = ioread16 (ioaddr + TxStatus);
1266 hw_frame_id = (tx_status >> 8) & 0xff;
1268 hw_frame_id = ioread8(ioaddr + TxFrameId);
1271 if (np->pci_dev->revision >= 0x14) {
1272 spin_lock(&np->lock);
1273 for (; np->cur_tx - np->dirty_tx > 0; np->dirty_tx++) {
1274 int entry = np->dirty_tx % TX_RING_SIZE;
1275 struct sk_buff *skb;
1277 sw_frame_id = (le32_to_cpu(
1278 np->tx_ring[entry].status) >> 2) & 0xff;
1279 if (sw_frame_id == hw_frame_id &&
1280 !(le32_to_cpu(np->tx_ring[entry].status)
1283 if (sw_frame_id == (hw_frame_id + 1) %
1286 skb = np->tx_skbuff[entry];
1287 /* Free the original skb. */
1288 dma_unmap_single(&np->pci_dev->dev,
1289 le32_to_cpu(np->tx_ring[entry].frag[0].addr),
1290 skb->len, DMA_TO_DEVICE);
1291 dev_kfree_skb_irq (np->tx_skbuff[entry]);
1292 np->tx_skbuff[entry] = NULL;
1293 np->tx_ring[entry].frag[0].addr = 0;
1294 np->tx_ring[entry].frag[0].length = 0;
1296 spin_unlock(&np->lock);
1298 spin_lock(&np->lock);
1299 for (; np->cur_tx - np->dirty_tx > 0; np->dirty_tx++) {
1300 int entry = np->dirty_tx % TX_RING_SIZE;
1301 struct sk_buff *skb;
1302 if (!(le32_to_cpu(np->tx_ring[entry].status)
1305 skb = np->tx_skbuff[entry];
1306 /* Free the original skb. */
1307 dma_unmap_single(&np->pci_dev->dev,
1308 le32_to_cpu(np->tx_ring[entry].frag[0].addr),
1309 skb->len, DMA_TO_DEVICE);
1310 dev_kfree_skb_irq (np->tx_skbuff[entry]);
1311 np->tx_skbuff[entry] = NULL;
1312 np->tx_ring[entry].frag[0].addr = 0;
1313 np->tx_ring[entry].frag[0].length = 0;
1315 spin_unlock(&np->lock);
1318 if (netif_queue_stopped(dev) &&
1319 np->cur_tx - np->dirty_tx < TX_QUEUE_LEN - 4) {
1320 /* The ring is no longer full, clear busy flag. */
1321 netif_wake_queue (dev);
1323 /* Abnormal error summary/uncommon events handlers. */
1324 if (intr_status & (IntrPCIErr | LinkChange | StatsMax))
1325 netdev_error(dev, intr_status);
1327 if (netif_msg_intr(np))
1328 printk(KERN_DEBUG "%s: exiting interrupt, status=%#4.4x.\n",
1329 dev->name, ioread16(ioaddr + IntrStatus));
1330 return IRQ_RETVAL(handled);
1333 static void rx_poll(unsigned long data)
1335 struct net_device *dev = (struct net_device *)data;
1336 struct netdev_private *np = netdev_priv(dev);
1337 int entry = np->cur_rx % RX_RING_SIZE;
1338 int boguscnt = np->budget;
1339 void __iomem *ioaddr = np->base;
1342 /* If EOP is set on the next entry, it's a new packet. Send it up. */
1344 struct netdev_desc *desc = &(np->rx_ring[entry]);
1345 u32 frame_status = le32_to_cpu(desc->status);
1348 if (--boguscnt < 0) {
1351 if (!(frame_status & DescOwn))
1353 pkt_len = frame_status & 0x1fff; /* Chip omits the CRC. */
1354 if (netif_msg_rx_status(np))
1355 printk(KERN_DEBUG " netdev_rx() status was %8.8x.\n",
1357 if (frame_status & 0x001f4000) {
1358 /* There was a error. */
1359 if (netif_msg_rx_err(np))
1360 printk(KERN_DEBUG " netdev_rx() Rx error was %8.8x.\n",
1362 dev->stats.rx_errors++;
1363 if (frame_status & 0x00100000)
1364 dev->stats.rx_length_errors++;
1365 if (frame_status & 0x00010000)
1366 dev->stats.rx_fifo_errors++;
1367 if (frame_status & 0x00060000)
1368 dev->stats.rx_frame_errors++;
1369 if (frame_status & 0x00080000)
1370 dev->stats.rx_crc_errors++;
1371 if (frame_status & 0x00100000) {
1372 printk(KERN_WARNING "%s: Oversized Ethernet frame,"
1374 dev->name, frame_status);
1377 struct sk_buff *skb;
1378 #ifndef final_version
1379 if (netif_msg_rx_status(np))
1380 printk(KERN_DEBUG " netdev_rx() normal Rx pkt length %d"
1381 ", bogus_cnt %d.\n",
1384 /* Check if the packet is long enough to accept without copying
1385 to a minimally-sized skbuff. */
1386 if (pkt_len < rx_copybreak &&
1387 (skb = netdev_alloc_skb(dev, pkt_len + 2)) != NULL) {
1388 skb_reserve(skb, 2); /* 16 byte align the IP header */
1389 dma_sync_single_for_cpu(&np->pci_dev->dev,
1390 le32_to_cpu(desc->frag[0].addr),
1391 np->rx_buf_sz, DMA_FROM_DEVICE);
1392 skb_copy_to_linear_data(skb, np->rx_skbuff[entry]->data, pkt_len);
1393 dma_sync_single_for_device(&np->pci_dev->dev,
1394 le32_to_cpu(desc->frag[0].addr),
1395 np->rx_buf_sz, DMA_FROM_DEVICE);
1396 skb_put(skb, pkt_len);
1398 dma_unmap_single(&np->pci_dev->dev,
1399 le32_to_cpu(desc->frag[0].addr),
1400 np->rx_buf_sz, DMA_FROM_DEVICE);
1401 skb_put(skb = np->rx_skbuff[entry], pkt_len);
1402 np->rx_skbuff[entry] = NULL;
1404 skb->protocol = eth_type_trans(skb, dev);
1405 /* Note: checksum -> skb->ip_summed = CHECKSUM_UNNECESSARY; */
1408 entry = (entry + 1) % RX_RING_SIZE;
1413 np->budget -= received;
1414 iowrite16(DEFAULT_INTR, ioaddr + IntrEnable);
1422 np->budget -= received;
1423 if (np->budget <= 0)
1424 np->budget = RX_BUDGET;
1425 tasklet_schedule(&np->rx_tasklet);
1428 static void refill_rx (struct net_device *dev)
1430 struct netdev_private *np = netdev_priv(dev);
1434 /* Refill the Rx ring buffers. */
1435 for (;(np->cur_rx - np->dirty_rx + RX_RING_SIZE) % RX_RING_SIZE > 0;
1436 np->dirty_rx = (np->dirty_rx + 1) % RX_RING_SIZE) {
1437 struct sk_buff *skb;
1438 entry = np->dirty_rx % RX_RING_SIZE;
1439 if (np->rx_skbuff[entry] == NULL) {
1440 skb = netdev_alloc_skb(dev, np->rx_buf_sz + 2);
1441 np->rx_skbuff[entry] = skb;
1443 break; /* Better luck next round. */
1444 skb_reserve(skb, 2); /* Align IP on 16 byte boundaries */
1445 np->rx_ring[entry].frag[0].addr = cpu_to_le32(
1446 dma_map_single(&np->pci_dev->dev, skb->data,
1447 np->rx_buf_sz, DMA_FROM_DEVICE));
1448 if (dma_mapping_error(&np->pci_dev->dev,
1449 np->rx_ring[entry].frag[0].addr)) {
1450 dev_kfree_skb_irq(skb);
1451 np->rx_skbuff[entry] = NULL;
1455 /* Perhaps we need not reset this field. */
1456 np->rx_ring[entry].frag[0].length =
1457 cpu_to_le32(np->rx_buf_sz | LastFrag);
1458 np->rx_ring[entry].status = 0;
1462 static void netdev_error(struct net_device *dev, int intr_status)
1464 struct netdev_private *np = netdev_priv(dev);
1465 void __iomem *ioaddr = np->base;
1466 u16 mii_ctl, mii_advertise, mii_lpa;
1469 if (intr_status & LinkChange) {
1470 if (mdio_wait_link(dev, 10) == 0) {
1471 printk(KERN_INFO "%s: Link up\n", dev->name);
1472 if (np->an_enable) {
1473 mii_advertise = mdio_read(dev, np->phys[0],
1475 mii_lpa = mdio_read(dev, np->phys[0], MII_LPA);
1476 mii_advertise &= mii_lpa;
1477 printk(KERN_INFO "%s: Link changed: ",
1479 if (mii_advertise & ADVERTISE_100FULL) {
1481 printk("100Mbps, full duplex\n");
1482 } else if (mii_advertise & ADVERTISE_100HALF) {
1484 printk("100Mbps, half duplex\n");
1485 } else if (mii_advertise & ADVERTISE_10FULL) {
1487 printk("10Mbps, full duplex\n");
1488 } else if (mii_advertise & ADVERTISE_10HALF) {
1490 printk("10Mbps, half duplex\n");
1495 mii_ctl = mdio_read(dev, np->phys[0], MII_BMCR);
1496 speed = (mii_ctl & BMCR_SPEED100) ? 100 : 10;
1498 printk(KERN_INFO "%s: Link changed: %dMbps ,",
1500 printk("%s duplex.\n",
1501 (mii_ctl & BMCR_FULLDPLX) ?
1505 if (np->flowctrl && np->mii_if.full_duplex) {
1506 iowrite16(ioread16(ioaddr + MulticastFilter1+2) | 0x0200,
1507 ioaddr + MulticastFilter1+2);
1508 iowrite16(ioread16(ioaddr + MACCtrl0) | EnbFlowCtrl,
1511 netif_carrier_on(dev);
1513 printk(KERN_INFO "%s: Link down\n", dev->name);
1514 netif_carrier_off(dev);
1517 if (intr_status & StatsMax) {
1520 if (intr_status & IntrPCIErr) {
1521 printk(KERN_ERR "%s: Something Wicked happened! %4.4x.\n",
1522 dev->name, intr_status);
1523 /* We must do a global reset of DMA to continue. */
1527 static struct net_device_stats *get_stats(struct net_device *dev)
1529 struct netdev_private *np = netdev_priv(dev);
1530 void __iomem *ioaddr = np->base;
1531 unsigned long flags;
1532 u8 late_coll, single_coll, mult_coll;
1534 spin_lock_irqsave(&np->statlock, flags);
1535 /* The chip only need report frame silently dropped. */
1536 dev->stats.rx_missed_errors += ioread8(ioaddr + RxMissed);
1537 dev->stats.tx_packets += ioread16(ioaddr + TxFramesOK);
1538 dev->stats.rx_packets += ioread16(ioaddr + RxFramesOK);
1539 dev->stats.tx_carrier_errors += ioread8(ioaddr + StatsCarrierError);
1541 mult_coll = ioread8(ioaddr + StatsMultiColl);
1542 np->xstats.tx_multiple_collisions += mult_coll;
1543 single_coll = ioread8(ioaddr + StatsOneColl);
1544 np->xstats.tx_single_collisions += single_coll;
1545 late_coll = ioread8(ioaddr + StatsLateColl);
1546 np->xstats.tx_late_collisions += late_coll;
1547 dev->stats.collisions += mult_coll
1551 np->xstats.tx_deferred += ioread8(ioaddr + StatsTxDefer);
1552 np->xstats.tx_deferred_excessive += ioread8(ioaddr + StatsTxXSDefer);
1553 np->xstats.tx_aborted += ioread8(ioaddr + StatsTxAbort);
1554 np->xstats.tx_bcasts += ioread8(ioaddr + StatsBcastTx);
1555 np->xstats.rx_bcasts += ioread8(ioaddr + StatsBcastRx);
1556 np->xstats.tx_mcasts += ioread8(ioaddr + StatsMcastTx);
1557 np->xstats.rx_mcasts += ioread8(ioaddr + StatsMcastRx);
1559 dev->stats.tx_bytes += ioread16(ioaddr + TxOctetsLow);
1560 dev->stats.tx_bytes += ioread16(ioaddr + TxOctetsHigh) << 16;
1561 dev->stats.rx_bytes += ioread16(ioaddr + RxOctetsLow);
1562 dev->stats.rx_bytes += ioread16(ioaddr + RxOctetsHigh) << 16;
1564 spin_unlock_irqrestore(&np->statlock, flags);
1569 static void set_rx_mode(struct net_device *dev)
1571 struct netdev_private *np = netdev_priv(dev);
1572 void __iomem *ioaddr = np->base;
1573 u16 mc_filter[4]; /* Multicast hash filter */
1577 if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */
1578 memset(mc_filter, 0xff, sizeof(mc_filter));
1579 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptAll | AcceptMyPhys;
1580 } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
1581 (dev->flags & IFF_ALLMULTI)) {
1582 /* Too many to match, or accept all multicasts. */
1583 memset(mc_filter, 0xff, sizeof(mc_filter));
1584 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
1585 } else if (!netdev_mc_empty(dev)) {
1586 struct netdev_hw_addr *ha;
1590 memset (mc_filter, 0, sizeof (mc_filter));
1591 netdev_for_each_mc_addr(ha, dev) {
1592 crc = ether_crc_le(ETH_ALEN, ha->addr);
1593 for (index=0, bit=0; bit < 6; bit++, crc <<= 1)
1594 if (crc & 0x80000000) index |= 1 << bit;
1595 mc_filter[index/16] |= (1 << (index % 16));
1597 rx_mode = AcceptBroadcast | AcceptMultiHash | AcceptMyPhys;
1599 iowrite8(AcceptBroadcast | AcceptMyPhys, ioaddr + RxMode);
1602 if (np->mii_if.full_duplex && np->flowctrl)
1603 mc_filter[3] |= 0x0200;
1605 for (i = 0; i < 4; i++)
1606 iowrite16(mc_filter[i], ioaddr + MulticastFilter0 + i*2);
1607 iowrite8(rx_mode, ioaddr + RxMode);
1610 static int __set_mac_addr(struct net_device *dev)
1612 struct netdev_private *np = netdev_priv(dev);
1615 addr16 = (dev->dev_addr[0] | (dev->dev_addr[1] << 8));
1616 iowrite16(addr16, np->base + StationAddr);
1617 addr16 = (dev->dev_addr[2] | (dev->dev_addr[3] << 8));
1618 iowrite16(addr16, np->base + StationAddr+2);
1619 addr16 = (dev->dev_addr[4] | (dev->dev_addr[5] << 8));
1620 iowrite16(addr16, np->base + StationAddr+4);
1624 /* Invoked with rtnl_lock held */
1625 static int sundance_set_mac_addr(struct net_device *dev, void *data)
1627 const struct sockaddr *addr = data;
1629 if (!is_valid_ether_addr(addr->sa_data))
1630 return -EADDRNOTAVAIL;
1631 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
1632 __set_mac_addr(dev);
1637 static const struct {
1638 const char name[ETH_GSTRING_LEN];
1639 } sundance_stats[] = {
1640 { "tx_multiple_collisions" },
1641 { "tx_single_collisions" },
1642 { "tx_late_collisions" },
1644 { "tx_deferred_excessive" },
1652 static int check_if_running(struct net_device *dev)
1654 if (!netif_running(dev))
1659 static void get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
1661 struct netdev_private *np = netdev_priv(dev);
1662 strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
1663 strlcpy(info->version, DRV_VERSION, sizeof(info->version));
1664 strlcpy(info->bus_info, pci_name(np->pci_dev), sizeof(info->bus_info));
1667 static int get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
1669 struct netdev_private *np = netdev_priv(dev);
1670 spin_lock_irq(&np->lock);
1671 mii_ethtool_gset(&np->mii_if, ecmd);
1672 spin_unlock_irq(&np->lock);
1676 static int set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
1678 struct netdev_private *np = netdev_priv(dev);
1680 spin_lock_irq(&np->lock);
1681 res = mii_ethtool_sset(&np->mii_if, ecmd);
1682 spin_unlock_irq(&np->lock);
1686 static int nway_reset(struct net_device *dev)
1688 struct netdev_private *np = netdev_priv(dev);
1689 return mii_nway_restart(&np->mii_if);
1692 static u32 get_link(struct net_device *dev)
1694 struct netdev_private *np = netdev_priv(dev);
1695 return mii_link_ok(&np->mii_if);
1698 static u32 get_msglevel(struct net_device *dev)
1700 struct netdev_private *np = netdev_priv(dev);
1701 return np->msg_enable;
1704 static void set_msglevel(struct net_device *dev, u32 val)
1706 struct netdev_private *np = netdev_priv(dev);
1707 np->msg_enable = val;
1710 static void get_strings(struct net_device *dev, u32 stringset,
1713 if (stringset == ETH_SS_STATS)
1714 memcpy(data, sundance_stats, sizeof(sundance_stats));
1717 static int get_sset_count(struct net_device *dev, int sset)
1721 return ARRAY_SIZE(sundance_stats);
1727 static void get_ethtool_stats(struct net_device *dev,
1728 struct ethtool_stats *stats, u64 *data)
1730 struct netdev_private *np = netdev_priv(dev);
1734 data[i++] = np->xstats.tx_multiple_collisions;
1735 data[i++] = np->xstats.tx_single_collisions;
1736 data[i++] = np->xstats.tx_late_collisions;
1737 data[i++] = np->xstats.tx_deferred;
1738 data[i++] = np->xstats.tx_deferred_excessive;
1739 data[i++] = np->xstats.tx_aborted;
1740 data[i++] = np->xstats.tx_bcasts;
1741 data[i++] = np->xstats.rx_bcasts;
1742 data[i++] = np->xstats.tx_mcasts;
1743 data[i++] = np->xstats.rx_mcasts;
1748 static void sundance_get_wol(struct net_device *dev,
1749 struct ethtool_wolinfo *wol)
1751 struct netdev_private *np = netdev_priv(dev);
1752 void __iomem *ioaddr = np->base;
1757 wol->supported = (WAKE_PHY | WAKE_MAGIC);
1758 if (!np->wol_enabled)
1761 wol_bits = ioread8(ioaddr + WakeEvent);
1762 if (wol_bits & MagicPktEnable)
1763 wol->wolopts |= WAKE_MAGIC;
1764 if (wol_bits & LinkEventEnable)
1765 wol->wolopts |= WAKE_PHY;
1768 static int sundance_set_wol(struct net_device *dev,
1769 struct ethtool_wolinfo *wol)
1771 struct netdev_private *np = netdev_priv(dev);
1772 void __iomem *ioaddr = np->base;
1775 if (!device_can_wakeup(&np->pci_dev->dev))
1778 np->wol_enabled = !!(wol->wolopts);
1779 wol_bits = ioread8(ioaddr + WakeEvent);
1780 wol_bits &= ~(WakePktEnable | MagicPktEnable |
1781 LinkEventEnable | WolEnable);
1783 if (np->wol_enabled) {
1784 if (wol->wolopts & WAKE_MAGIC)
1785 wol_bits |= (MagicPktEnable | WolEnable);
1786 if (wol->wolopts & WAKE_PHY)
1787 wol_bits |= (LinkEventEnable | WolEnable);
1789 iowrite8(wol_bits, ioaddr + WakeEvent);
1791 device_set_wakeup_enable(&np->pci_dev->dev, np->wol_enabled);
1796 #define sundance_get_wol NULL
1797 #define sundance_set_wol NULL
1798 #endif /* CONFIG_PM */
1800 static const struct ethtool_ops ethtool_ops = {
1801 .begin = check_if_running,
1802 .get_drvinfo = get_drvinfo,
1803 .get_settings = get_settings,
1804 .set_settings = set_settings,
1805 .nway_reset = nway_reset,
1806 .get_link = get_link,
1807 .get_wol = sundance_get_wol,
1808 .set_wol = sundance_set_wol,
1809 .get_msglevel = get_msglevel,
1810 .set_msglevel = set_msglevel,
1811 .get_strings = get_strings,
1812 .get_sset_count = get_sset_count,
1813 .get_ethtool_stats = get_ethtool_stats,
1816 static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1818 struct netdev_private *np = netdev_priv(dev);
1821 if (!netif_running(dev))
1824 spin_lock_irq(&np->lock);
1825 rc = generic_mii_ioctl(&np->mii_if, if_mii(rq), cmd, NULL);
1826 spin_unlock_irq(&np->lock);
1831 static int netdev_close(struct net_device *dev)
1833 struct netdev_private *np = netdev_priv(dev);
1834 void __iomem *ioaddr = np->base;
1835 struct sk_buff *skb;
1838 /* Wait and kill tasklet */
1839 tasklet_kill(&np->rx_tasklet);
1840 tasklet_kill(&np->tx_tasklet);
1846 netif_stop_queue(dev);
1848 if (netif_msg_ifdown(np)) {
1849 printk(KERN_DEBUG "%s: Shutting down ethercard, status was Tx %2.2x "
1850 "Rx %4.4x Int %2.2x.\n",
1851 dev->name, ioread8(ioaddr + TxStatus),
1852 ioread32(ioaddr + RxStatus), ioread16(ioaddr + IntrStatus));
1853 printk(KERN_DEBUG "%s: Queue pointers were Tx %d / %d, Rx %d / %d.\n",
1854 dev->name, np->cur_tx, np->dirty_tx, np->cur_rx, np->dirty_rx);
1857 /* Disable interrupts by clearing the interrupt mask. */
1858 iowrite16(0x0000, ioaddr + IntrEnable);
1860 /* Disable Rx and Tx DMA for safely release resource */
1861 iowrite32(0x500, ioaddr + DMACtrl);
1863 /* Stop the chip's Tx and Rx processes. */
1864 iowrite16(TxDisable | RxDisable | StatsDisable, ioaddr + MACCtrl1);
1866 for (i = 2000; i > 0; i--) {
1867 if ((ioread32(ioaddr + DMACtrl) & 0xc000) == 0)
1872 iowrite16(GlobalReset | DMAReset | FIFOReset | NetworkReset,
1873 ioaddr + ASIC_HI_WORD(ASICCtrl));
1875 for (i = 2000; i > 0; i--) {
1876 if ((ioread16(ioaddr + ASIC_HI_WORD(ASICCtrl)) & ResetBusy) == 0)
1882 if (netif_msg_hw(np)) {
1883 printk(KERN_DEBUG " Tx ring at %8.8x:\n",
1884 (int)(np->tx_ring_dma));
1885 for (i = 0; i < TX_RING_SIZE; i++)
1886 printk(KERN_DEBUG " #%d desc. %4.4x %8.8x %8.8x.\n",
1887 i, np->tx_ring[i].status, np->tx_ring[i].frag[0].addr,
1888 np->tx_ring[i].frag[0].length);
1889 printk(KERN_DEBUG " Rx ring %8.8x:\n",
1890 (int)(np->rx_ring_dma));
1891 for (i = 0; i < /*RX_RING_SIZE*/4 ; i++) {
1892 printk(KERN_DEBUG " #%d desc. %4.4x %4.4x %8.8x\n",
1893 i, np->rx_ring[i].status, np->rx_ring[i].frag[0].addr,
1894 np->rx_ring[i].frag[0].length);
1897 #endif /* __i386__ debugging only */
1899 free_irq(np->pci_dev->irq, dev);
1901 del_timer_sync(&np->timer);
1903 /* Free all the skbuffs in the Rx queue. */
1904 for (i = 0; i < RX_RING_SIZE; i++) {
1905 np->rx_ring[i].status = 0;
1906 skb = np->rx_skbuff[i];
1908 dma_unmap_single(&np->pci_dev->dev,
1909 le32_to_cpu(np->rx_ring[i].frag[0].addr),
1910 np->rx_buf_sz, DMA_FROM_DEVICE);
1912 np->rx_skbuff[i] = NULL;
1914 np->rx_ring[i].frag[0].addr = cpu_to_le32(0xBADF00D0); /* poison */
1916 for (i = 0; i < TX_RING_SIZE; i++) {
1917 np->tx_ring[i].next_desc = 0;
1918 skb = np->tx_skbuff[i];
1920 dma_unmap_single(&np->pci_dev->dev,
1921 le32_to_cpu(np->tx_ring[i].frag[0].addr),
1922 skb->len, DMA_TO_DEVICE);
1924 np->tx_skbuff[i] = NULL;
1931 static void sundance_remove1(struct pci_dev *pdev)
1933 struct net_device *dev = pci_get_drvdata(pdev);
1936 struct netdev_private *np = netdev_priv(dev);
1937 unregister_netdev(dev);
1938 dma_free_coherent(&pdev->dev, RX_TOTAL_SIZE,
1939 np->rx_ring, np->rx_ring_dma);
1940 dma_free_coherent(&pdev->dev, TX_TOTAL_SIZE,
1941 np->tx_ring, np->tx_ring_dma);
1942 pci_iounmap(pdev, np->base);
1943 pci_release_regions(pdev);
1950 static int sundance_suspend(struct pci_dev *pci_dev, pm_message_t state)
1952 struct net_device *dev = pci_get_drvdata(pci_dev);
1953 struct netdev_private *np = netdev_priv(dev);
1954 void __iomem *ioaddr = np->base;
1956 if (!netif_running(dev))
1960 netif_device_detach(dev);
1962 pci_save_state(pci_dev);
1963 if (np->wol_enabled) {
1964 iowrite8(AcceptBroadcast | AcceptMyPhys, ioaddr + RxMode);
1965 iowrite16(RxEnable, ioaddr + MACCtrl1);
1967 pci_enable_wake(pci_dev, pci_choose_state(pci_dev, state),
1969 pci_set_power_state(pci_dev, pci_choose_state(pci_dev, state));
1974 static int sundance_resume(struct pci_dev *pci_dev)
1976 struct net_device *dev = pci_get_drvdata(pci_dev);
1979 if (!netif_running(dev))
1982 pci_set_power_state(pci_dev, PCI_D0);
1983 pci_restore_state(pci_dev);
1984 pci_enable_wake(pci_dev, PCI_D0, 0);
1986 err = netdev_open(dev);
1988 printk(KERN_ERR "%s: Can't resume interface!\n",
1993 netif_device_attach(dev);
1999 #endif /* CONFIG_PM */
2001 static struct pci_driver sundance_driver = {
2003 .id_table = sundance_pci_tbl,
2004 .probe = sundance_probe1,
2005 .remove = sundance_remove1,
2007 .suspend = sundance_suspend,
2008 .resume = sundance_resume,
2009 #endif /* CONFIG_PM */
2012 static int __init sundance_init(void)
2014 /* when a module, this is printed whether or not devices are found in probe */
2018 return pci_register_driver(&sundance_driver);
2021 static void __exit sundance_exit(void)
2023 pci_unregister_driver(&sundance_driver);
2026 module_init(sundance_init);
2027 module_exit(sundance_exit);