2 * This file is part of the Chelsio T4 Ethernet driver for Linux.
4 * Copyright (c) 2009-2010 Chelsio Communications, Inc. All rights reserved.
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
35 #ifndef _T4FW_INTERFACE_H_
36 #define _T4FW_INTERFACE_H_
38 #define FW_T4VF_SGE_BASE_ADDR 0x0000
39 #define FW_T4VF_MPS_BASE_ADDR 0x0100
40 #define FW_T4VF_PL_BASE_ADDR 0x0200
41 #define FW_T4VF_MBDATA_BASE_ADDR 0x0240
42 #define FW_T4VF_CIM_BASE_ADDR 0x0300
48 FW_ETH_TX_PKT_WR = 0x08,
50 FW_OFLD_TX_DATA_WR = 0x0b,
52 FW_ETH_TX_PKT_VM_WR = 0x11,
55 FW_RI_RDMA_WRITE_WR = 0x14,
57 FW_RI_RDMA_READ_WR = 0x16,
59 FW_RI_BIND_MW_WR = 0x18,
60 FW_RI_FR_NSMR_WR = 0x19,
61 FW_RI_INV_LSTAG_WR = 0x1a,
70 #define FW_WR_OP(x) ((x) << 24)
71 #define FW_WR_ATOMIC(x) ((x) << 23)
72 #define FW_WR_FLUSH(x) ((x) << 22)
73 #define FW_WR_COMPL(x) ((x) << 21)
74 #define FW_WR_IMMDLEN_MASK 0xff
75 #define FW_WR_IMMDLEN(x) ((x) << 0)
77 #define FW_WR_EQUIQ (1U << 31)
78 #define FW_WR_EQUEQ (1U << 30)
79 #define FW_WR_FLOWID(x) ((x) << 8)
80 #define FW_WR_LEN16(x) ((x) << 0)
82 #define HW_TPL_FR_MT_PR_IV_P_FC 0X32B
96 struct fw_eth_tx_pkt_wr {
98 __be32 equiq_to_len16;
103 FW_FLOWC_MNEM_PFNVFN, /* PFN [15:8] VFN [7:0] */
107 FW_FLOWC_MNEM_SNDNXT,
108 FW_FLOWC_MNEM_RCVNXT,
109 FW_FLOWC_MNEM_SNDBUF,
113 struct fw_flowc_mnemval {
120 __be32 op_to_nparams;
121 #define FW_FLOWC_WR_NPARAMS(x) ((x) << 0)
123 struct fw_flowc_mnemval mnemval[0];
126 struct fw_ofld_tx_data_wr {
127 __be32 op_to_immdlen;
130 __be32 tunnel_to_proxy;
131 #define FW_OFLD_TX_DATA_WR_TUNNEL(x) ((x) << 19)
132 #define FW_OFLD_TX_DATA_WR_SAVE(x) ((x) << 18)
133 #define FW_OFLD_TX_DATA_WR_FLUSH(x) ((x) << 17)
134 #define FW_OFLD_TX_DATA_WR_URGENT(x) ((x) << 16)
135 #define FW_OFLD_TX_DATA_WR_MORE(x) ((x) << 15)
136 #define FW_OFLD_TX_DATA_WR_SHOVE(x) ((x) << 14)
137 #define FW_OFLD_TX_DATA_WR_ULPMODE(x) ((x) << 10)
138 #define FW_OFLD_TX_DATA_WR_ULPSUBMODE(x) ((x) << 6)
143 #define FW_CMD_WR_DMA (1U << 17)
148 struct fw_eth_tx_pkt_vm_wr {
150 __be32 equiq_to_len16;
158 #define FW_CMD_MAX_TIMEOUT 3000
161 * If a host driver does a HELLO and discovers that there's already a MASTER
162 * selected, we may have to wait for that MASTER to finish issuing RESET,
163 * configuration and INITIALIZE commands. Also, there's a possibility that
164 * our own HELLO may get lost if it happens right as the MASTER is issuign a
165 * RESET command, so we need to be willing to make a few retries of our HELLO.
167 #define FW_CMD_HELLO_TIMEOUT (3 * FW_CMD_MAX_TIMEOUT)
168 #define FW_CMD_HELLO_RETRIES 3
171 enum fw_cmd_opcodes {
176 FW_INITIALIZE_CMD = 0x06,
177 FW_CAPS_CONFIG_CMD = 0x07,
178 FW_PARAMS_CMD = 0x08,
181 FW_EQ_MNGT_CMD = 0x11,
182 FW_EQ_ETH_CMD = 0x12,
183 FW_EQ_CTRL_CMD = 0x13,
184 FW_EQ_OFLD_CMD = 0x21,
186 FW_VI_MAC_CMD = 0x15,
187 FW_VI_RXMODE_CMD = 0x16,
188 FW_VI_ENABLE_CMD = 0x17,
189 FW_ACL_MAC_CMD = 0x18,
190 FW_ACL_VLAN_CMD = 0x19,
191 FW_VI_STATS_CMD = 0x1a,
193 FW_PORT_STATS_CMD = 0x1c,
194 FW_PORT_LB_STATS_CMD = 0x1d,
195 FW_PORT_TRACE_CMD = 0x1e,
196 FW_PORT_TRACE_MMAP_CMD = 0x1f,
197 FW_RSS_IND_TBL_CMD = 0x20,
198 FW_RSS_GLB_CONFIG_CMD = 0x22,
199 FW_RSS_VI_CONFIG_CMD = 0x23,
200 FW_LASTC2E_CMD = 0x40,
206 FW_CMD_CAP_PF = 0x01,
207 FW_CMD_CAP_DMAQ = 0x02,
208 FW_CMD_CAP_PORT = 0x04,
209 FW_CMD_CAP_PORTPROMISC = 0x08,
210 FW_CMD_CAP_PORTSTATS = 0x10,
211 FW_CMD_CAP_VF = 0x80,
215 * Generic command header flit0
222 #define FW_CMD_OP(x) ((x) << 24)
223 #define FW_CMD_OP_GET(x) (((x) >> 24) & 0xff)
224 #define FW_CMD_REQUEST (1U << 23)
225 #define FW_CMD_READ (1U << 22)
226 #define FW_CMD_WRITE (1U << 21)
227 #define FW_CMD_EXEC (1U << 20)
228 #define FW_CMD_RAMASK(x) ((x) << 20)
229 #define FW_CMD_RETVAL(x) ((x) << 8)
230 #define FW_CMD_RETVAL_GET(x) (((x) >> 8) & 0xff)
231 #define FW_CMD_LEN16(x) ((x) << 0)
233 enum fw_ldst_addrspc {
234 FW_LDST_ADDRSPC_FIRMWARE = 0x0001,
235 FW_LDST_ADDRSPC_SGE_EGRC = 0x0008,
236 FW_LDST_ADDRSPC_SGE_INGC = 0x0009,
237 FW_LDST_ADDRSPC_SGE_FLMC = 0x000a,
238 FW_LDST_ADDRSPC_SGE_CONMC = 0x000b,
239 FW_LDST_ADDRSPC_TP_PIO = 0x0010,
240 FW_LDST_ADDRSPC_TP_TM_PIO = 0x0011,
241 FW_LDST_ADDRSPC_TP_MIB = 0x0012,
242 FW_LDST_ADDRSPC_MDIO = 0x0018,
243 FW_LDST_ADDRSPC_MPS = 0x0020,
244 FW_LDST_ADDRSPC_FUNC = 0x0028
247 enum fw_ldst_mps_fid {
252 enum fw_ldst_func_access_ctl {
253 FW_LDST_FUNC_ACC_CTL_VIID,
254 FW_LDST_FUNC_ACC_CTL_FID
257 enum fw_ldst_func_mod_index {
262 __be32 op_to_addrspace;
263 #define FW_LDST_CMD_ADDRSPACE(x) ((x) << 0)
264 __be32 cycles_to_len16;
266 struct fw_ldst_addrval {
270 struct fw_ldst_idctxt {
282 struct fw_ldst_mdio {
298 struct fw_ldst_func {
309 #define FW_LDST_CMD_MSG(x) ((x) << 31)
310 #define FW_LDST_CMD_PADDR(x) ((x) << 8)
311 #define FW_LDST_CMD_MMD(x) ((x) << 0)
312 #define FW_LDST_CMD_FID(x) ((x) << 15)
313 #define FW_LDST_CMD_CTL(x) ((x) << 0)
314 #define FW_LDST_CMD_RPLCPF(x) ((x) << 0)
316 struct fw_reset_cmd {
324 fw_hello_cmd_stage_os = 0x0
327 struct fw_hello_cmd {
330 __be32 err_to_mbasyncnot;
331 #define FW_HELLO_CMD_ERR (1U << 31)
332 #define FW_HELLO_CMD_INIT (1U << 30)
333 #define FW_HELLO_CMD_MASTERDIS(x) ((x) << 29)
334 #define FW_HELLO_CMD_MASTERFORCE(x) ((x) << 28)
335 #define FW_HELLO_CMD_MBMASTER_MASK 0xfU
336 #define FW_HELLO_CMD_MBMASTER_SHIFT 24
337 #define FW_HELLO_CMD_MBMASTER(x) ((x) << FW_HELLO_CMD_MBMASTER_SHIFT)
338 #define FW_HELLO_CMD_MBMASTER_GET(x) \
339 (((x) >> FW_HELLO_CMD_MBMASTER_SHIFT) & FW_HELLO_CMD_MBMASTER_MASK)
340 #define FW_HELLO_CMD_MBASYNCNOT(x) ((x) << 20)
341 #define FW_HELLO_CMD_STAGE(x) ((x) << 17)
342 #define FW_HELLO_CMD_CLEARINIT (1U << 16)
352 struct fw_initialize_cmd {
358 enum fw_caps_config_hm {
359 FW_CAPS_CONFIG_HM_PCIE = 0x00000001,
360 FW_CAPS_CONFIG_HM_PL = 0x00000002,
361 FW_CAPS_CONFIG_HM_SGE = 0x00000004,
362 FW_CAPS_CONFIG_HM_CIM = 0x00000008,
363 FW_CAPS_CONFIG_HM_ULPTX = 0x00000010,
364 FW_CAPS_CONFIG_HM_TP = 0x00000020,
365 FW_CAPS_CONFIG_HM_ULPRX = 0x00000040,
366 FW_CAPS_CONFIG_HM_PMRX = 0x00000080,
367 FW_CAPS_CONFIG_HM_PMTX = 0x00000100,
368 FW_CAPS_CONFIG_HM_MC = 0x00000200,
369 FW_CAPS_CONFIG_HM_LE = 0x00000400,
370 FW_CAPS_CONFIG_HM_MPS = 0x00000800,
371 FW_CAPS_CONFIG_HM_XGMAC = 0x00001000,
372 FW_CAPS_CONFIG_HM_CPLSWITCH = 0x00002000,
373 FW_CAPS_CONFIG_HM_T4DBG = 0x00004000,
374 FW_CAPS_CONFIG_HM_MI = 0x00008000,
375 FW_CAPS_CONFIG_HM_I2CM = 0x00010000,
376 FW_CAPS_CONFIG_HM_NCSI = 0x00020000,
377 FW_CAPS_CONFIG_HM_SMB = 0x00040000,
378 FW_CAPS_CONFIG_HM_MA = 0x00080000,
379 FW_CAPS_CONFIG_HM_EDRAM = 0x00100000,
380 FW_CAPS_CONFIG_HM_PMU = 0x00200000,
381 FW_CAPS_CONFIG_HM_UART = 0x00400000,
382 FW_CAPS_CONFIG_HM_SF = 0x00800000,
385 enum fw_caps_config_nbm {
386 FW_CAPS_CONFIG_NBM_IPMI = 0x00000001,
387 FW_CAPS_CONFIG_NBM_NCSI = 0x00000002,
390 enum fw_caps_config_link {
391 FW_CAPS_CONFIG_LINK_PPP = 0x00000001,
392 FW_CAPS_CONFIG_LINK_QFC = 0x00000002,
393 FW_CAPS_CONFIG_LINK_DCBX = 0x00000004,
396 enum fw_caps_config_switch {
397 FW_CAPS_CONFIG_SWITCH_INGRESS = 0x00000001,
398 FW_CAPS_CONFIG_SWITCH_EGRESS = 0x00000002,
401 enum fw_caps_config_nic {
402 FW_CAPS_CONFIG_NIC = 0x00000001,
403 FW_CAPS_CONFIG_NIC_VM = 0x00000002,
406 enum fw_caps_config_ofld {
407 FW_CAPS_CONFIG_OFLD = 0x00000001,
410 enum fw_caps_config_rdma {
411 FW_CAPS_CONFIG_RDMA_RDDP = 0x00000001,
412 FW_CAPS_CONFIG_RDMA_RDMAC = 0x00000002,
415 enum fw_caps_config_iscsi {
416 FW_CAPS_CONFIG_ISCSI_INITIATOR_PDU = 0x00000001,
417 FW_CAPS_CONFIG_ISCSI_TARGET_PDU = 0x00000002,
418 FW_CAPS_CONFIG_ISCSI_INITIATOR_CNXOFLD = 0x00000004,
419 FW_CAPS_CONFIG_ISCSI_TARGET_CNXOFLD = 0x00000008,
422 enum fw_caps_config_fcoe {
423 FW_CAPS_CONFIG_FCOE_INITIATOR = 0x00000001,
424 FW_CAPS_CONFIG_FCOE_TARGET = 0x00000002,
428 FW_MEMTYPE_CF_EDC0 = 0x0,
429 FW_MEMTYPE_CF_EDC1 = 0x1,
430 FW_MEMTYPE_CF_EXTMEM = 0x2,
431 FW_MEMTYPE_CF_FLASH = 0x4,
432 FW_MEMTYPE_CF_INTERNAL = 0x5,
435 struct fw_caps_config_cmd {
455 #define FW_CAPS_CONFIG_CMD_CFVALID (1U << 27)
456 #define FW_CAPS_CONFIG_CMD_MEMTYPE_CF(x) ((x) << 24)
457 #define FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(x) ((x) << 16)
460 * params command mnemonics
462 enum fw_params_mnem {
463 FW_PARAMS_MNEM_DEV = 1, /* device params */
464 FW_PARAMS_MNEM_PFVF = 2, /* function params */
465 FW_PARAMS_MNEM_REG = 3, /* limited register access */
466 FW_PARAMS_MNEM_DMAQ = 4, /* dma queue params */
473 enum fw_params_param_dev {
474 FW_PARAMS_PARAM_DEV_CCLK = 0x00, /* chip core clock in khz */
475 FW_PARAMS_PARAM_DEV_PORTVEC = 0x01, /* the port vector */
476 FW_PARAMS_PARAM_DEV_NTID = 0x02, /* reads the number of TIDs
477 * allocated by the device's
480 FW_PARAMS_PARAM_DEV_FLOWC_BUFFIFO_SZ = 0x03,
481 FW_PARAMS_PARAM_DEV_INTVER_NIC = 0x04,
482 FW_PARAMS_PARAM_DEV_INTVER_VNIC = 0x05,
483 FW_PARAMS_PARAM_DEV_INTVER_OFLD = 0x06,
484 FW_PARAMS_PARAM_DEV_INTVER_RI = 0x07,
485 FW_PARAMS_PARAM_DEV_INTVER_ISCSIPDU = 0x08,
486 FW_PARAMS_PARAM_DEV_INTVER_ISCSI = 0x09,
487 FW_PARAMS_PARAM_DEV_INTVER_FCOE = 0x0A,
488 FW_PARAMS_PARAM_DEV_FWREV = 0x0B,
489 FW_PARAMS_PARAM_DEV_TPREV = 0x0C,
490 FW_PARAMS_PARAM_DEV_CF = 0x0D,
494 * physical and virtual function parameters
496 enum fw_params_param_pfvf {
497 FW_PARAMS_PARAM_PFVF_RWXCAPS = 0x00,
498 FW_PARAMS_PARAM_PFVF_ROUTE_START = 0x01,
499 FW_PARAMS_PARAM_PFVF_ROUTE_END = 0x02,
500 FW_PARAMS_PARAM_PFVF_CLIP_START = 0x03,
501 FW_PARAMS_PARAM_PFVF_CLIP_END = 0x04,
502 FW_PARAMS_PARAM_PFVF_FILTER_START = 0x05,
503 FW_PARAMS_PARAM_PFVF_FILTER_END = 0x06,
504 FW_PARAMS_PARAM_PFVF_SERVER_START = 0x07,
505 FW_PARAMS_PARAM_PFVF_SERVER_END = 0x08,
506 FW_PARAMS_PARAM_PFVF_TDDP_START = 0x09,
507 FW_PARAMS_PARAM_PFVF_TDDP_END = 0x0A,
508 FW_PARAMS_PARAM_PFVF_ISCSI_START = 0x0B,
509 FW_PARAMS_PARAM_PFVF_ISCSI_END = 0x0C,
510 FW_PARAMS_PARAM_PFVF_STAG_START = 0x0D,
511 FW_PARAMS_PARAM_PFVF_STAG_END = 0x0E,
512 FW_PARAMS_PARAM_PFVF_RQ_START = 0x1F,
513 FW_PARAMS_PARAM_PFVF_RQ_END = 0x10,
514 FW_PARAMS_PARAM_PFVF_PBL_START = 0x11,
515 FW_PARAMS_PARAM_PFVF_PBL_END = 0x12,
516 FW_PARAMS_PARAM_PFVF_L2T_START = 0x13,
517 FW_PARAMS_PARAM_PFVF_L2T_END = 0x14,
518 FW_PARAMS_PARAM_PFVF_SQRQ_START = 0x15,
519 FW_PARAMS_PARAM_PFVF_SQRQ_END = 0x16,
520 FW_PARAMS_PARAM_PFVF_CQ_START = 0x17,
521 FW_PARAMS_PARAM_PFVF_CQ_END = 0x18,
522 FW_PARAMS_PARAM_PFVF_SCHEDCLASS_ETH = 0x20,
523 FW_PARAMS_PARAM_PFVF_VIID = 0x24,
524 FW_PARAMS_PARAM_PFVF_CPMASK = 0x25,
525 FW_PARAMS_PARAM_PFVF_OCQ_START = 0x26,
526 FW_PARAMS_PARAM_PFVF_OCQ_END = 0x27,
527 FW_PARAMS_PARAM_PFVF_CONM_MAP = 0x28,
528 FW_PARAMS_PARAM_PFVF_IQFLINT_START = 0x29,
529 FW_PARAMS_PARAM_PFVF_IQFLINT_END = 0x2A,
530 FW_PARAMS_PARAM_PFVF_EQ_START = 0x2B,
531 FW_PARAMS_PARAM_PFVF_EQ_END = 0x2C,
532 FW_PARAMS_PARAM_PFVF_ACTIVE_FILTER_START = 0x2D,
533 FW_PARAMS_PARAM_PFVF_ACTIVE_FILTER_END = 0x2E
537 * dma queue parameters
539 enum fw_params_param_dmaq {
540 FW_PARAMS_PARAM_DMAQ_IQ_DCAEN_DCACPU = 0x00,
541 FW_PARAMS_PARAM_DMAQ_IQ_INTCNTTHRESH = 0x01,
542 FW_PARAMS_PARAM_DMAQ_EQ_CMPLIQID_MNGT = 0x10,
543 FW_PARAMS_PARAM_DMAQ_EQ_CMPLIQID_CTRL = 0x11,
544 FW_PARAMS_PARAM_DMAQ_EQ_SCHEDCLASS_ETH = 0x12,
547 #define FW_PARAMS_MNEM(x) ((x) << 24)
548 #define FW_PARAMS_PARAM_X(x) ((x) << 16)
549 #define FW_PARAMS_PARAM_Y_SHIFT 8
550 #define FW_PARAMS_PARAM_Y_MASK 0xffU
551 #define FW_PARAMS_PARAM_Y(x) ((x) << FW_PARAMS_PARAM_Y_SHIFT)
552 #define FW_PARAMS_PARAM_Y_GET(x) (((x) >> FW_PARAMS_PARAM_Y_SHIFT) &\
553 FW_PARAMS_PARAM_Y_MASK)
554 #define FW_PARAMS_PARAM_Z_SHIFT 0
555 #define FW_PARAMS_PARAM_Z_MASK 0xffu
556 #define FW_PARAMS_PARAM_Z(x) ((x) << FW_PARAMS_PARAM_Z_SHIFT)
557 #define FW_PARAMS_PARAM_Z_GET(x) (((x) >> FW_PARAMS_PARAM_Z_SHIFT) &\
558 FW_PARAMS_PARAM_Z_MASK)
559 #define FW_PARAMS_PARAM_XYZ(x) ((x) << 0)
560 #define FW_PARAMS_PARAM_YZ(x) ((x) << 0)
562 struct fw_params_cmd {
565 struct fw_params_param {
571 #define FW_PARAMS_CMD_PFN(x) ((x) << 8)
572 #define FW_PARAMS_CMD_VFN(x) ((x) << 0)
579 __be32 tc_to_nexactf;
580 __be32 r_caps_to_nethctrl;
586 #define FW_PFVF_CMD_PFN(x) ((x) << 8)
587 #define FW_PFVF_CMD_VFN(x) ((x) << 0)
589 #define FW_PFVF_CMD_NIQFLINT(x) ((x) << 20)
590 #define FW_PFVF_CMD_NIQFLINT_GET(x) (((x) >> 20) & 0xfff)
592 #define FW_PFVF_CMD_NIQ(x) ((x) << 0)
593 #define FW_PFVF_CMD_NIQ_GET(x) (((x) >> 0) & 0xfffff)
595 #define FW_PFVF_CMD_TYPE (1 << 31)
596 #define FW_PFVF_CMD_TYPE_GET(x) (((x) >> 31) & 0x1)
598 #define FW_PFVF_CMD_CMASK(x) ((x) << 24)
599 #define FW_PFVF_CMD_CMASK_MASK 0xf
600 #define FW_PFVF_CMD_CMASK_GET(x) (((x) >> 24) & FW_PFVF_CMD_CMASK_MASK)
602 #define FW_PFVF_CMD_PMASK(x) ((x) << 20)
603 #define FW_PFVF_CMD_PMASK_MASK 0xf
604 #define FW_PFVF_CMD_PMASK_GET(x) (((x) >> 20) & FW_PFVF_CMD_PMASK_MASK)
606 #define FW_PFVF_CMD_NEQ(x) ((x) << 0)
607 #define FW_PFVF_CMD_NEQ_GET(x) (((x) >> 0) & 0xfffff)
609 #define FW_PFVF_CMD_TC(x) ((x) << 24)
610 #define FW_PFVF_CMD_TC_GET(x) (((x) >> 24) & 0xff)
612 #define FW_PFVF_CMD_NVI(x) ((x) << 16)
613 #define FW_PFVF_CMD_NVI_GET(x) (((x) >> 16) & 0xff)
615 #define FW_PFVF_CMD_NEXACTF(x) ((x) << 0)
616 #define FW_PFVF_CMD_NEXACTF_GET(x) (((x) >> 0) & 0xffff)
618 #define FW_PFVF_CMD_R_CAPS(x) ((x) << 24)
619 #define FW_PFVF_CMD_R_CAPS_GET(x) (((x) >> 24) & 0xff)
621 #define FW_PFVF_CMD_WX_CAPS(x) ((x) << 16)
622 #define FW_PFVF_CMD_WX_CAPS_GET(x) (((x) >> 16) & 0xff)
624 #define FW_PFVF_CMD_NETHCTRL(x) ((x) << 0)
625 #define FW_PFVF_CMD_NETHCTRL_GET(x) (((x) >> 0) & 0xffff)
628 FW_IQ_TYPE_FL_INT_CAP,
629 FW_IQ_TYPE_NO_FL_INT_CAP
634 __be32 alloc_to_len16;
639 __be32 type_to_iqandstindex;
640 __be16 iqdroprss_to_iqesize;
643 __be32 iqns_to_fl0congen;
644 __be16 fl0dcaen_to_fl0cidxfthresh;
647 __be32 fl1cngchmap_to_fl1congen;
648 __be16 fl1dcaen_to_fl1cidxfthresh;
653 #define FW_IQ_CMD_PFN(x) ((x) << 8)
654 #define FW_IQ_CMD_VFN(x) ((x) << 0)
656 #define FW_IQ_CMD_ALLOC (1U << 31)
657 #define FW_IQ_CMD_FREE (1U << 30)
658 #define FW_IQ_CMD_MODIFY (1U << 29)
659 #define FW_IQ_CMD_IQSTART(x) ((x) << 28)
660 #define FW_IQ_CMD_IQSTOP(x) ((x) << 27)
662 #define FW_IQ_CMD_TYPE(x) ((x) << 29)
663 #define FW_IQ_CMD_IQASYNCH(x) ((x) << 28)
664 #define FW_IQ_CMD_VIID(x) ((x) << 16)
665 #define FW_IQ_CMD_IQANDST(x) ((x) << 15)
666 #define FW_IQ_CMD_IQANUS(x) ((x) << 14)
667 #define FW_IQ_CMD_IQANUD(x) ((x) << 12)
668 #define FW_IQ_CMD_IQANDSTINDEX(x) ((x) << 0)
670 #define FW_IQ_CMD_IQDROPRSS (1U << 15)
671 #define FW_IQ_CMD_IQGTSMODE (1U << 14)
672 #define FW_IQ_CMD_IQPCIECH(x) ((x) << 12)
673 #define FW_IQ_CMD_IQDCAEN(x) ((x) << 11)
674 #define FW_IQ_CMD_IQDCACPU(x) ((x) << 6)
675 #define FW_IQ_CMD_IQINTCNTTHRESH(x) ((x) << 4)
676 #define FW_IQ_CMD_IQO (1U << 3)
677 #define FW_IQ_CMD_IQCPRIO(x) ((x) << 2)
678 #define FW_IQ_CMD_IQESIZE(x) ((x) << 0)
680 #define FW_IQ_CMD_IQNS(x) ((x) << 31)
681 #define FW_IQ_CMD_IQRO(x) ((x) << 30)
682 #define FW_IQ_CMD_IQFLINTIQHSEN(x) ((x) << 28)
683 #define FW_IQ_CMD_IQFLINTCONGEN(x) ((x) << 27)
684 #define FW_IQ_CMD_IQFLINTISCSIC(x) ((x) << 26)
685 #define FW_IQ_CMD_FL0CNGCHMAP(x) ((x) << 20)
686 #define FW_IQ_CMD_FL0CACHELOCK(x) ((x) << 15)
687 #define FW_IQ_CMD_FL0DBP(x) ((x) << 14)
688 #define FW_IQ_CMD_FL0DATANS(x) ((x) << 13)
689 #define FW_IQ_CMD_FL0DATARO(x) ((x) << 12)
690 #define FW_IQ_CMD_FL0CONGCIF(x) ((x) << 11)
691 #define FW_IQ_CMD_FL0ONCHIP(x) ((x) << 10)
692 #define FW_IQ_CMD_FL0STATUSPGNS(x) ((x) << 9)
693 #define FW_IQ_CMD_FL0STATUSPGRO(x) ((x) << 8)
694 #define FW_IQ_CMD_FL0FETCHNS(x) ((x) << 7)
695 #define FW_IQ_CMD_FL0FETCHRO(x) ((x) << 6)
696 #define FW_IQ_CMD_FL0HOSTFCMODE(x) ((x) << 4)
697 #define FW_IQ_CMD_FL0CPRIO(x) ((x) << 3)
698 #define FW_IQ_CMD_FL0PADEN (1U << 2)
699 #define FW_IQ_CMD_FL0PACKEN (1U << 1)
700 #define FW_IQ_CMD_FL0CONGEN (1U << 0)
702 #define FW_IQ_CMD_FL0DCAEN(x) ((x) << 15)
703 #define FW_IQ_CMD_FL0DCACPU(x) ((x) << 10)
704 #define FW_IQ_CMD_FL0FBMIN(x) ((x) << 7)
705 #define FW_IQ_CMD_FL0FBMAX(x) ((x) << 4)
706 #define FW_IQ_CMD_FL0CIDXFTHRESHO (1U << 3)
707 #define FW_IQ_CMD_FL0CIDXFTHRESH(x) ((x) << 0)
709 #define FW_IQ_CMD_FL1CNGCHMAP(x) ((x) << 20)
710 #define FW_IQ_CMD_FL1CACHELOCK(x) ((x) << 15)
711 #define FW_IQ_CMD_FL1DBP(x) ((x) << 14)
712 #define FW_IQ_CMD_FL1DATANS(x) ((x) << 13)
713 #define FW_IQ_CMD_FL1DATARO(x) ((x) << 12)
714 #define FW_IQ_CMD_FL1CONGCIF(x) ((x) << 11)
715 #define FW_IQ_CMD_FL1ONCHIP(x) ((x) << 10)
716 #define FW_IQ_CMD_FL1STATUSPGNS(x) ((x) << 9)
717 #define FW_IQ_CMD_FL1STATUSPGRO(x) ((x) << 8)
718 #define FW_IQ_CMD_FL1FETCHNS(x) ((x) << 7)
719 #define FW_IQ_CMD_FL1FETCHRO(x) ((x) << 6)
720 #define FW_IQ_CMD_FL1HOSTFCMODE(x) ((x) << 4)
721 #define FW_IQ_CMD_FL1CPRIO(x) ((x) << 3)
722 #define FW_IQ_CMD_FL1PADEN (1U << 2)
723 #define FW_IQ_CMD_FL1PACKEN (1U << 1)
724 #define FW_IQ_CMD_FL1CONGEN (1U << 0)
726 #define FW_IQ_CMD_FL1DCAEN(x) ((x) << 15)
727 #define FW_IQ_CMD_FL1DCACPU(x) ((x) << 10)
728 #define FW_IQ_CMD_FL1FBMIN(x) ((x) << 7)
729 #define FW_IQ_CMD_FL1FBMAX(x) ((x) << 4)
730 #define FW_IQ_CMD_FL1CIDXFTHRESHO (1U << 3)
731 #define FW_IQ_CMD_FL1CIDXFTHRESH(x) ((x) << 0)
733 struct fw_eq_eth_cmd {
735 __be32 alloc_to_len16;
738 __be32 fetchszm_to_iqid;
739 __be32 dcaen_to_eqsize;
746 #define FW_EQ_ETH_CMD_PFN(x) ((x) << 8)
747 #define FW_EQ_ETH_CMD_VFN(x) ((x) << 0)
748 #define FW_EQ_ETH_CMD_ALLOC (1U << 31)
749 #define FW_EQ_ETH_CMD_FREE (1U << 30)
750 #define FW_EQ_ETH_CMD_MODIFY (1U << 29)
751 #define FW_EQ_ETH_CMD_EQSTART (1U << 28)
752 #define FW_EQ_ETH_CMD_EQSTOP (1U << 27)
754 #define FW_EQ_ETH_CMD_EQID(x) ((x) << 0)
755 #define FW_EQ_ETH_CMD_EQID_GET(x) (((x) >> 0) & 0xfffff)
756 #define FW_EQ_ETH_CMD_PHYSEQID(x) ((x) << 0)
757 #define FW_EQ_ETH_CMD_PHYSEQID_GET(x) (((x) >> 0) & 0xfffff)
759 #define FW_EQ_ETH_CMD_FETCHSZM(x) ((x) << 26)
760 #define FW_EQ_ETH_CMD_STATUSPGNS(x) ((x) << 25)
761 #define FW_EQ_ETH_CMD_STATUSPGRO(x) ((x) << 24)
762 #define FW_EQ_ETH_CMD_FETCHNS(x) ((x) << 23)
763 #define FW_EQ_ETH_CMD_FETCHRO(x) ((x) << 22)
764 #define FW_EQ_ETH_CMD_HOSTFCMODE(x) ((x) << 20)
765 #define FW_EQ_ETH_CMD_CPRIO(x) ((x) << 19)
766 #define FW_EQ_ETH_CMD_ONCHIP(x) ((x) << 18)
767 #define FW_EQ_ETH_CMD_PCIECHN(x) ((x) << 16)
768 #define FW_EQ_ETH_CMD_IQID(x) ((x) << 0)
770 #define FW_EQ_ETH_CMD_DCAEN(x) ((x) << 31)
771 #define FW_EQ_ETH_CMD_DCACPU(x) ((x) << 26)
772 #define FW_EQ_ETH_CMD_FBMIN(x) ((x) << 23)
773 #define FW_EQ_ETH_CMD_FBMAX(x) ((x) << 20)
774 #define FW_EQ_ETH_CMD_CIDXFTHRESHO(x) ((x) << 19)
775 #define FW_EQ_ETH_CMD_CIDXFTHRESH(x) ((x) << 16)
776 #define FW_EQ_ETH_CMD_EQSIZE(x) ((x) << 0)
778 #define FW_EQ_ETH_CMD_VIID(x) ((x) << 16)
780 struct fw_eq_ctrl_cmd {
782 __be32 alloc_to_len16;
783 __be32 cmpliqid_eqid;
785 __be32 fetchszm_to_iqid;
786 __be32 dcaen_to_eqsize;
790 #define FW_EQ_CTRL_CMD_PFN(x) ((x) << 8)
791 #define FW_EQ_CTRL_CMD_VFN(x) ((x) << 0)
793 #define FW_EQ_CTRL_CMD_ALLOC (1U << 31)
794 #define FW_EQ_CTRL_CMD_FREE (1U << 30)
795 #define FW_EQ_CTRL_CMD_MODIFY (1U << 29)
796 #define FW_EQ_CTRL_CMD_EQSTART (1U << 28)
797 #define FW_EQ_CTRL_CMD_EQSTOP (1U << 27)
799 #define FW_EQ_CTRL_CMD_CMPLIQID(x) ((x) << 20)
800 #define FW_EQ_CTRL_CMD_EQID(x) ((x) << 0)
801 #define FW_EQ_CTRL_CMD_EQID_GET(x) (((x) >> 0) & 0xfffff)
802 #define FW_EQ_CTRL_CMD_PHYSEQID_GET(x) (((x) >> 0) & 0xfffff)
804 #define FW_EQ_CTRL_CMD_FETCHSZM (1U << 26)
805 #define FW_EQ_CTRL_CMD_STATUSPGNS (1U << 25)
806 #define FW_EQ_CTRL_CMD_STATUSPGRO (1U << 24)
807 #define FW_EQ_CTRL_CMD_FETCHNS (1U << 23)
808 #define FW_EQ_CTRL_CMD_FETCHRO (1U << 22)
809 #define FW_EQ_CTRL_CMD_HOSTFCMODE(x) ((x) << 20)
810 #define FW_EQ_CTRL_CMD_CPRIO(x) ((x) << 19)
811 #define FW_EQ_CTRL_CMD_ONCHIP(x) ((x) << 18)
812 #define FW_EQ_CTRL_CMD_PCIECHN(x) ((x) << 16)
813 #define FW_EQ_CTRL_CMD_IQID(x) ((x) << 0)
815 #define FW_EQ_CTRL_CMD_DCAEN(x) ((x) << 31)
816 #define FW_EQ_CTRL_CMD_DCACPU(x) ((x) << 26)
817 #define FW_EQ_CTRL_CMD_FBMIN(x) ((x) << 23)
818 #define FW_EQ_CTRL_CMD_FBMAX(x) ((x) << 20)
819 #define FW_EQ_CTRL_CMD_CIDXFTHRESHO(x) ((x) << 19)
820 #define FW_EQ_CTRL_CMD_CIDXFTHRESH(x) ((x) << 16)
821 #define FW_EQ_CTRL_CMD_EQSIZE(x) ((x) << 0)
823 struct fw_eq_ofld_cmd {
825 __be32 alloc_to_len16;
828 __be32 fetchszm_to_iqid;
829 __be32 dcaen_to_eqsize;
833 #define FW_EQ_OFLD_CMD_PFN(x) ((x) << 8)
834 #define FW_EQ_OFLD_CMD_VFN(x) ((x) << 0)
836 #define FW_EQ_OFLD_CMD_ALLOC (1U << 31)
837 #define FW_EQ_OFLD_CMD_FREE (1U << 30)
838 #define FW_EQ_OFLD_CMD_MODIFY (1U << 29)
839 #define FW_EQ_OFLD_CMD_EQSTART (1U << 28)
840 #define FW_EQ_OFLD_CMD_EQSTOP (1U << 27)
842 #define FW_EQ_OFLD_CMD_EQID(x) ((x) << 0)
843 #define FW_EQ_OFLD_CMD_EQID_GET(x) (((x) >> 0) & 0xfffff)
844 #define FW_EQ_OFLD_CMD_PHYSEQID_GET(x) (((x) >> 0) & 0xfffff)
846 #define FW_EQ_OFLD_CMD_FETCHSZM(x) ((x) << 26)
847 #define FW_EQ_OFLD_CMD_STATUSPGNS(x) ((x) << 25)
848 #define FW_EQ_OFLD_CMD_STATUSPGRO(x) ((x) << 24)
849 #define FW_EQ_OFLD_CMD_FETCHNS(x) ((x) << 23)
850 #define FW_EQ_OFLD_CMD_FETCHRO(x) ((x) << 22)
851 #define FW_EQ_OFLD_CMD_HOSTFCMODE(x) ((x) << 20)
852 #define FW_EQ_OFLD_CMD_CPRIO(x) ((x) << 19)
853 #define FW_EQ_OFLD_CMD_ONCHIP(x) ((x) << 18)
854 #define FW_EQ_OFLD_CMD_PCIECHN(x) ((x) << 16)
855 #define FW_EQ_OFLD_CMD_IQID(x) ((x) << 0)
857 #define FW_EQ_OFLD_CMD_DCAEN(x) ((x) << 31)
858 #define FW_EQ_OFLD_CMD_DCACPU(x) ((x) << 26)
859 #define FW_EQ_OFLD_CMD_FBMIN(x) ((x) << 23)
860 #define FW_EQ_OFLD_CMD_FBMAX(x) ((x) << 20)
861 #define FW_EQ_OFLD_CMD_CIDXFTHRESHO(x) ((x) << 19)
862 #define FW_EQ_OFLD_CMD_CIDXFTHRESH(x) ((x) << 16)
863 #define FW_EQ_OFLD_CMD_EQSIZE(x) ((x) << 0)
866 * Macros for VIID parsing:
867 * VIID - [10:8] PFN, [7] VI Valid, [6:0] VI number
869 #define FW_VIID_PFN_GET(x) (((x) >> 8) & 0x7)
870 #define FW_VIID_VIVLD_GET(x) (((x) >> 7) & 0x1)
871 #define FW_VIID_VIN_GET(x) (((x) >> 0) & 0x7F)
875 __be32 alloc_to_len16;
891 #define FW_VI_CMD_PFN(x) ((x) << 8)
892 #define FW_VI_CMD_VFN(x) ((x) << 0)
893 #define FW_VI_CMD_ALLOC (1U << 31)
894 #define FW_VI_CMD_FREE (1U << 30)
895 #define FW_VI_CMD_VIID(x) ((x) << 0)
896 #define FW_VI_CMD_VIID_GET(x) ((x) & 0xfff)
897 #define FW_VI_CMD_PORTID(x) ((x) << 4)
898 #define FW_VI_CMD_PORTID_GET(x) (((x) >> 4) & 0xf)
899 #define FW_VI_CMD_RSSSIZE_GET(x) (((x) >> 0) & 0x7ff)
901 /* Special VI_MAC command index ids */
902 #define FW_VI_MAC_ADD_MAC 0x3FF
903 #define FW_VI_MAC_ADD_PERSIST_MAC 0x3FE
904 #define FW_VI_MAC_MAC_BASED_FREE 0x3FD
905 #define FW_CLS_TCAM_NUM_ENTRIES 336
907 enum fw_vi_mac_smac {
908 FW_VI_MAC_MPS_TCAM_ENTRY,
909 FW_VI_MAC_MPS_TCAM_ONLY,
911 FW_VI_MAC_SMT_AND_MPSTCAM
914 enum fw_vi_mac_result {
916 FW_VI_MAC_R_F_NONEXISTENT_NOMEM,
917 FW_VI_MAC_R_SMAC_FAIL,
918 FW_VI_MAC_R_F_ACL_CHECK
921 struct fw_vi_mac_cmd {
923 __be32 freemacs_to_len16;
925 struct fw_vi_mac_exact {
929 struct fw_vi_mac_hash {
935 #define FW_VI_MAC_CMD_VIID(x) ((x) << 0)
936 #define FW_VI_MAC_CMD_FREEMACS(x) ((x) << 31)
937 #define FW_VI_MAC_CMD_HASHVECEN (1U << 23)
938 #define FW_VI_MAC_CMD_HASHUNIEN(x) ((x) << 22)
939 #define FW_VI_MAC_CMD_VALID (1U << 15)
940 #define FW_VI_MAC_CMD_PRIO(x) ((x) << 12)
941 #define FW_VI_MAC_CMD_SMAC_RESULT(x) ((x) << 10)
942 #define FW_VI_MAC_CMD_SMAC_RESULT_GET(x) (((x) >> 10) & 0x3)
943 #define FW_VI_MAC_CMD_IDX(x) ((x) << 0)
944 #define FW_VI_MAC_CMD_IDX_GET(x) (((x) >> 0) & 0x3ff)
946 #define FW_RXMODE_MTU_NO_CHG 65535
948 struct fw_vi_rxmode_cmd {
951 __be32 mtu_to_vlanexen;
955 #define FW_VI_RXMODE_CMD_VIID(x) ((x) << 0)
956 #define FW_VI_RXMODE_CMD_MTU_MASK 0xffff
957 #define FW_VI_RXMODE_CMD_MTU(x) ((x) << 16)
958 #define FW_VI_RXMODE_CMD_PROMISCEN_MASK 0x3
959 #define FW_VI_RXMODE_CMD_PROMISCEN(x) ((x) << 14)
960 #define FW_VI_RXMODE_CMD_ALLMULTIEN_MASK 0x3
961 #define FW_VI_RXMODE_CMD_ALLMULTIEN(x) ((x) << 12)
962 #define FW_VI_RXMODE_CMD_BROADCASTEN_MASK 0x3
963 #define FW_VI_RXMODE_CMD_BROADCASTEN(x) ((x) << 10)
964 #define FW_VI_RXMODE_CMD_VLANEXEN_MASK 0x3
965 #define FW_VI_RXMODE_CMD_VLANEXEN(x) ((x) << 8)
967 struct fw_vi_enable_cmd {
975 #define FW_VI_ENABLE_CMD_VIID(x) ((x) << 0)
976 #define FW_VI_ENABLE_CMD_IEN(x) ((x) << 31)
977 #define FW_VI_ENABLE_CMD_EEN(x) ((x) << 30)
978 #define FW_VI_ENABLE_CMD_LED (1U << 29)
980 /* VI VF stats offset definitions */
981 #define VI_VF_NUM_STATS 16
982 enum fw_vi_stats_vf_index {
983 FW_VI_VF_STAT_TX_BCAST_BYTES_IX,
984 FW_VI_VF_STAT_TX_BCAST_FRAMES_IX,
985 FW_VI_VF_STAT_TX_MCAST_BYTES_IX,
986 FW_VI_VF_STAT_TX_MCAST_FRAMES_IX,
987 FW_VI_VF_STAT_TX_UCAST_BYTES_IX,
988 FW_VI_VF_STAT_TX_UCAST_FRAMES_IX,
989 FW_VI_VF_STAT_TX_DROP_FRAMES_IX,
990 FW_VI_VF_STAT_TX_OFLD_BYTES_IX,
991 FW_VI_VF_STAT_TX_OFLD_FRAMES_IX,
992 FW_VI_VF_STAT_RX_BCAST_BYTES_IX,
993 FW_VI_VF_STAT_RX_BCAST_FRAMES_IX,
994 FW_VI_VF_STAT_RX_MCAST_BYTES_IX,
995 FW_VI_VF_STAT_RX_MCAST_FRAMES_IX,
996 FW_VI_VF_STAT_RX_UCAST_BYTES_IX,
997 FW_VI_VF_STAT_RX_UCAST_FRAMES_IX,
998 FW_VI_VF_STAT_RX_ERR_FRAMES_IX
1001 /* VI PF stats offset definitions */
1002 #define VI_PF_NUM_STATS 17
1003 enum fw_vi_stats_pf_index {
1004 FW_VI_PF_STAT_TX_BCAST_BYTES_IX,
1005 FW_VI_PF_STAT_TX_BCAST_FRAMES_IX,
1006 FW_VI_PF_STAT_TX_MCAST_BYTES_IX,
1007 FW_VI_PF_STAT_TX_MCAST_FRAMES_IX,
1008 FW_VI_PF_STAT_TX_UCAST_BYTES_IX,
1009 FW_VI_PF_STAT_TX_UCAST_FRAMES_IX,
1010 FW_VI_PF_STAT_TX_OFLD_BYTES_IX,
1011 FW_VI_PF_STAT_TX_OFLD_FRAMES_IX,
1012 FW_VI_PF_STAT_RX_BYTES_IX,
1013 FW_VI_PF_STAT_RX_FRAMES_IX,
1014 FW_VI_PF_STAT_RX_BCAST_BYTES_IX,
1015 FW_VI_PF_STAT_RX_BCAST_FRAMES_IX,
1016 FW_VI_PF_STAT_RX_MCAST_BYTES_IX,
1017 FW_VI_PF_STAT_RX_MCAST_FRAMES_IX,
1018 FW_VI_PF_STAT_RX_UCAST_BYTES_IX,
1019 FW_VI_PF_STAT_RX_UCAST_FRAMES_IX,
1020 FW_VI_PF_STAT_RX_ERR_FRAMES_IX
1023 struct fw_vi_stats_cmd {
1025 __be32 retval_len16;
1027 struct fw_vi_stats_ctl {
1038 struct fw_vi_stats_pf {
1039 __be64 tx_bcast_bytes;
1040 __be64 tx_bcast_frames;
1041 __be64 tx_mcast_bytes;
1042 __be64 tx_mcast_frames;
1043 __be64 tx_ucast_bytes;
1044 __be64 tx_ucast_frames;
1045 __be64 tx_offload_bytes;
1046 __be64 tx_offload_frames;
1048 __be64 rx_pf_frames;
1049 __be64 rx_bcast_bytes;
1050 __be64 rx_bcast_frames;
1051 __be64 rx_mcast_bytes;
1052 __be64 rx_mcast_frames;
1053 __be64 rx_ucast_bytes;
1054 __be64 rx_ucast_frames;
1055 __be64 rx_err_frames;
1057 struct fw_vi_stats_vf {
1058 __be64 tx_bcast_bytes;
1059 __be64 tx_bcast_frames;
1060 __be64 tx_mcast_bytes;
1061 __be64 tx_mcast_frames;
1062 __be64 tx_ucast_bytes;
1063 __be64 tx_ucast_frames;
1064 __be64 tx_drop_frames;
1065 __be64 tx_offload_bytes;
1066 __be64 tx_offload_frames;
1067 __be64 rx_bcast_bytes;
1068 __be64 rx_bcast_frames;
1069 __be64 rx_mcast_bytes;
1070 __be64 rx_mcast_frames;
1071 __be64 rx_ucast_bytes;
1072 __be64 rx_ucast_frames;
1073 __be64 rx_err_frames;
1078 #define FW_VI_STATS_CMD_VIID(x) ((x) << 0)
1079 #define FW_VI_STATS_CMD_NSTATS(x) ((x) << 12)
1080 #define FW_VI_STATS_CMD_IX(x) ((x) << 0)
1082 struct fw_acl_mac_cmd {
1097 #define FW_ACL_MAC_CMD_PFN(x) ((x) << 8)
1098 #define FW_ACL_MAC_CMD_VFN(x) ((x) << 0)
1099 #define FW_ACL_MAC_CMD_EN(x) ((x) << 31)
1101 struct fw_acl_vlan_cmd {
1110 #define FW_ACL_VLAN_CMD_PFN(x) ((x) << 8)
1111 #define FW_ACL_VLAN_CMD_VFN(x) ((x) << 0)
1112 #define FW_ACL_VLAN_CMD_EN(x) ((x) << 31)
1113 #define FW_ACL_VLAN_CMD_DROPNOVLAN(x) ((x) << 7)
1114 #define FW_ACL_VLAN_CMD_FM(x) ((x) << 6)
1117 FW_PORT_CAP_SPEED_100M = 0x0001,
1118 FW_PORT_CAP_SPEED_1G = 0x0002,
1119 FW_PORT_CAP_SPEED_2_5G = 0x0004,
1120 FW_PORT_CAP_SPEED_10G = 0x0008,
1121 FW_PORT_CAP_SPEED_40G = 0x0010,
1122 FW_PORT_CAP_SPEED_100G = 0x0020,
1123 FW_PORT_CAP_FC_RX = 0x0040,
1124 FW_PORT_CAP_FC_TX = 0x0080,
1125 FW_PORT_CAP_ANEG = 0x0100,
1126 FW_PORT_CAP_MDI_0 = 0x0200,
1127 FW_PORT_CAP_MDI_1 = 0x0400,
1128 FW_PORT_CAP_BEAN = 0x0800,
1129 FW_PORT_CAP_PMA_LPBK = 0x1000,
1130 FW_PORT_CAP_PCS_LPBK = 0x2000,
1131 FW_PORT_CAP_PHYXS_LPBK = 0x4000,
1132 FW_PORT_CAP_FAR_END_LPBK = 0x8000,
1136 FW_PORT_MDI_UNCHANGED,
1138 FW_PORT_MDI_F_STRAIGHT,
1139 FW_PORT_MDI_F_CROSSOVER
1142 #define FW_PORT_MDI(x) ((x) << 9)
1144 enum fw_port_action {
1145 FW_PORT_ACTION_L1_CFG = 0x0001,
1146 FW_PORT_ACTION_L2_CFG = 0x0002,
1147 FW_PORT_ACTION_GET_PORT_INFO = 0x0003,
1148 FW_PORT_ACTION_L2_PPP_CFG = 0x0004,
1149 FW_PORT_ACTION_L2_DCB_CFG = 0x0005,
1150 FW_PORT_ACTION_LOW_PWR_TO_NORMAL = 0x0010,
1151 FW_PORT_ACTION_L1_LOW_PWR_EN = 0x0011,
1152 FW_PORT_ACTION_L2_WOL_MODE_EN = 0x0012,
1153 FW_PORT_ACTION_LPBK_TO_NORMAL = 0x0020,
1154 FW_PORT_ACTION_L1_LPBK = 0x0021,
1155 FW_PORT_ACTION_L1_PMA_LPBK = 0x0022,
1156 FW_PORT_ACTION_L1_PCS_LPBK = 0x0023,
1157 FW_PORT_ACTION_L1_PHYXS_CSIDE_LPBK = 0x0024,
1158 FW_PORT_ACTION_L1_PHYXS_ESIDE_LPBK = 0x0025,
1159 FW_PORT_ACTION_PHY_RESET = 0x0040,
1160 FW_PORT_ACTION_PMA_RESET = 0x0041,
1161 FW_PORT_ACTION_PCS_RESET = 0x0042,
1162 FW_PORT_ACTION_PHYXS_RESET = 0x0043,
1163 FW_PORT_ACTION_DTEXS_REEST = 0x0044,
1164 FW_PORT_ACTION_AN_RESET = 0x0045
1167 enum fw_port_l2cfg_ctlbf {
1168 FW_PORT_L2_CTLBF_OVLAN0 = 0x01,
1169 FW_PORT_L2_CTLBF_OVLAN1 = 0x02,
1170 FW_PORT_L2_CTLBF_OVLAN2 = 0x04,
1171 FW_PORT_L2_CTLBF_OVLAN3 = 0x08,
1172 FW_PORT_L2_CTLBF_IVLAN = 0x10,
1173 FW_PORT_L2_CTLBF_TXIPG = 0x20
1176 enum fw_port_dcb_cfg {
1177 FW_PORT_DCB_CFG_PG = 0x01,
1178 FW_PORT_DCB_CFG_PFC = 0x02,
1179 FW_PORT_DCB_CFG_APPL = 0x04
1182 enum fw_port_dcb_cfg_rc {
1183 FW_PORT_DCB_CFG_SUCCESS = 0x0,
1184 FW_PORT_DCB_CFG_ERROR = 0x1
1187 struct fw_port_cmd {
1188 __be32 op_to_portid;
1189 __be32 action_to_len16;
1191 struct fw_port_l1cfg {
1195 struct fw_port_l2cfg {
1196 __be16 ctlbf_to_ivlan0;
1208 struct fw_port_info {
1209 __be32 lstatus_to_modtype;
1218 struct fw_port_ppp {
1219 __be32 pppen_to_ncsich;
1222 struct fw_port_dcb {
1229 __be32 pgid0_to_pgid7;
1236 #define FW_PORT_CMD_READ (1U << 22)
1238 #define FW_PORT_CMD_PORTID(x) ((x) << 0)
1239 #define FW_PORT_CMD_PORTID_GET(x) (((x) >> 0) & 0xf)
1241 #define FW_PORT_CMD_ACTION(x) ((x) << 16)
1242 #define FW_PORT_CMD_ACTION_GET(x) (((x) >> 16) & 0xffff)
1244 #define FW_PORT_CMD_CTLBF(x) ((x) << 10)
1245 #define FW_PORT_CMD_OVLAN3(x) ((x) << 7)
1246 #define FW_PORT_CMD_OVLAN2(x) ((x) << 6)
1247 #define FW_PORT_CMD_OVLAN1(x) ((x) << 5)
1248 #define FW_PORT_CMD_OVLAN0(x) ((x) << 4)
1249 #define FW_PORT_CMD_IVLAN0(x) ((x) << 3)
1251 #define FW_PORT_CMD_TXIPG(x) ((x) << 19)
1253 #define FW_PORT_CMD_LSTATUS (1U << 31)
1254 #define FW_PORT_CMD_LSPEED(x) ((x) << 24)
1255 #define FW_PORT_CMD_LSPEED_GET(x) (((x) >> 24) & 0x3f)
1256 #define FW_PORT_CMD_TXPAUSE (1U << 23)
1257 #define FW_PORT_CMD_RXPAUSE (1U << 22)
1258 #define FW_PORT_CMD_MDIOCAP (1U << 21)
1259 #define FW_PORT_CMD_MDIOADDR_GET(x) (((x) >> 16) & 0x1f)
1260 #define FW_PORT_CMD_LPTXPAUSE (1U << 15)
1261 #define FW_PORT_CMD_LPRXPAUSE (1U << 14)
1262 #define FW_PORT_CMD_PTYPE_MASK 0x1f
1263 #define FW_PORT_CMD_PTYPE_GET(x) (((x) >> 8) & FW_PORT_CMD_PTYPE_MASK)
1264 #define FW_PORT_CMD_MODTYPE_MASK 0x1f
1265 #define FW_PORT_CMD_MODTYPE_GET(x) (((x) >> 0) & FW_PORT_CMD_MODTYPE_MASK)
1267 #define FW_PORT_CMD_PPPEN(x) ((x) << 31)
1268 #define FW_PORT_CMD_TPSRC(x) ((x) << 28)
1269 #define FW_PORT_CMD_NCSISRC(x) ((x) << 24)
1271 #define FW_PORT_CMD_CH0(x) ((x) << 20)
1272 #define FW_PORT_CMD_CH1(x) ((x) << 16)
1273 #define FW_PORT_CMD_CH2(x) ((x) << 12)
1274 #define FW_PORT_CMD_CH3(x) ((x) << 8)
1275 #define FW_PORT_CMD_NCSICH(x) ((x) << 4)
1278 FW_PORT_TYPE_FIBER_XFI,
1279 FW_PORT_TYPE_FIBER_XAUI,
1280 FW_PORT_TYPE_BT_SGMII,
1281 FW_PORT_TYPE_BT_XFI,
1282 FW_PORT_TYPE_BT_XAUI,
1289 FW_PORT_TYPE_BP4_AP,
1291 FW_PORT_TYPE_NONE = FW_PORT_CMD_PTYPE_MASK
1294 enum fw_port_module_type {
1295 FW_PORT_MOD_TYPE_NA,
1296 FW_PORT_MOD_TYPE_LR,
1297 FW_PORT_MOD_TYPE_SR,
1298 FW_PORT_MOD_TYPE_ER,
1299 FW_PORT_MOD_TYPE_TWINAX_PASSIVE,
1300 FW_PORT_MOD_TYPE_TWINAX_ACTIVE,
1301 FW_PORT_MOD_TYPE_LRM,
1303 FW_PORT_MOD_TYPE_NONE = FW_PORT_CMD_MODTYPE_MASK
1307 #define FW_NUM_PORT_STATS 50
1308 #define FW_NUM_PORT_TX_STATS 23
1309 #define FW_NUM_PORT_RX_STATS 27
1311 enum fw_port_stats_tx_index {
1312 FW_STAT_TX_PORT_BYTES_IX,
1313 FW_STAT_TX_PORT_FRAMES_IX,
1314 FW_STAT_TX_PORT_BCAST_IX,
1315 FW_STAT_TX_PORT_MCAST_IX,
1316 FW_STAT_TX_PORT_UCAST_IX,
1317 FW_STAT_TX_PORT_ERROR_IX,
1318 FW_STAT_TX_PORT_64B_IX,
1319 FW_STAT_TX_PORT_65B_127B_IX,
1320 FW_STAT_TX_PORT_128B_255B_IX,
1321 FW_STAT_TX_PORT_256B_511B_IX,
1322 FW_STAT_TX_PORT_512B_1023B_IX,
1323 FW_STAT_TX_PORT_1024B_1518B_IX,
1324 FW_STAT_TX_PORT_1519B_MAX_IX,
1325 FW_STAT_TX_PORT_DROP_IX,
1326 FW_STAT_TX_PORT_PAUSE_IX,
1327 FW_STAT_TX_PORT_PPP0_IX,
1328 FW_STAT_TX_PORT_PPP1_IX,
1329 FW_STAT_TX_PORT_PPP2_IX,
1330 FW_STAT_TX_PORT_PPP3_IX,
1331 FW_STAT_TX_PORT_PPP4_IX,
1332 FW_STAT_TX_PORT_PPP5_IX,
1333 FW_STAT_TX_PORT_PPP6_IX,
1334 FW_STAT_TX_PORT_PPP7_IX
1337 enum fw_port_stat_rx_index {
1338 FW_STAT_RX_PORT_BYTES_IX,
1339 FW_STAT_RX_PORT_FRAMES_IX,
1340 FW_STAT_RX_PORT_BCAST_IX,
1341 FW_STAT_RX_PORT_MCAST_IX,
1342 FW_STAT_RX_PORT_UCAST_IX,
1343 FW_STAT_RX_PORT_MTU_ERROR_IX,
1344 FW_STAT_RX_PORT_MTU_CRC_ERROR_IX,
1345 FW_STAT_RX_PORT_CRC_ERROR_IX,
1346 FW_STAT_RX_PORT_LEN_ERROR_IX,
1347 FW_STAT_RX_PORT_SYM_ERROR_IX,
1348 FW_STAT_RX_PORT_64B_IX,
1349 FW_STAT_RX_PORT_65B_127B_IX,
1350 FW_STAT_RX_PORT_128B_255B_IX,
1351 FW_STAT_RX_PORT_256B_511B_IX,
1352 FW_STAT_RX_PORT_512B_1023B_IX,
1353 FW_STAT_RX_PORT_1024B_1518B_IX,
1354 FW_STAT_RX_PORT_1519B_MAX_IX,
1355 FW_STAT_RX_PORT_PAUSE_IX,
1356 FW_STAT_RX_PORT_PPP0_IX,
1357 FW_STAT_RX_PORT_PPP1_IX,
1358 FW_STAT_RX_PORT_PPP2_IX,
1359 FW_STAT_RX_PORT_PPP3_IX,
1360 FW_STAT_RX_PORT_PPP4_IX,
1361 FW_STAT_RX_PORT_PPP5_IX,
1362 FW_STAT_RX_PORT_PPP6_IX,
1363 FW_STAT_RX_PORT_PPP7_IX,
1364 FW_STAT_RX_PORT_LESS_64B_IX
1367 struct fw_port_stats_cmd {
1368 __be32 op_to_portid;
1369 __be32 retval_len16;
1370 union fw_port_stats {
1371 struct fw_port_stats_ctl {
1383 struct fw_port_stats_all {
1392 __be64 tx_128b_255b;
1393 __be64 tx_256b_511b;
1394 __be64 tx_512b_1023b;
1395 __be64 tx_1024b_1518b;
1396 __be64 tx_1519b_max;
1412 __be64 rx_mtu_error;
1413 __be64 rx_mtu_crc_error;
1414 __be64 rx_crc_error;
1415 __be64 rx_len_error;
1416 __be64 rx_sym_error;
1419 __be64 rx_128b_255b;
1420 __be64 rx_256b_511b;
1421 __be64 rx_512b_1023b;
1422 __be64 rx_1024b_1518b;
1423 __be64 rx_1519b_max;
1440 #define FW_PORT_STATS_CMD_NSTATS(x) ((x) << 4)
1441 #define FW_PORT_STATS_CMD_BG_BM(x) ((x) << 0)
1442 #define FW_PORT_STATS_CMD_TX(x) ((x) << 7)
1443 #define FW_PORT_STATS_CMD_IX(x) ((x) << 0)
1445 /* port loopback stats */
1446 #define FW_NUM_LB_STATS 16
1447 enum fw_port_lb_stats_index {
1448 FW_STAT_LB_PORT_BYTES_IX,
1449 FW_STAT_LB_PORT_FRAMES_IX,
1450 FW_STAT_LB_PORT_BCAST_IX,
1451 FW_STAT_LB_PORT_MCAST_IX,
1452 FW_STAT_LB_PORT_UCAST_IX,
1453 FW_STAT_LB_PORT_ERROR_IX,
1454 FW_STAT_LB_PORT_64B_IX,
1455 FW_STAT_LB_PORT_65B_127B_IX,
1456 FW_STAT_LB_PORT_128B_255B_IX,
1457 FW_STAT_LB_PORT_256B_511B_IX,
1458 FW_STAT_LB_PORT_512B_1023B_IX,
1459 FW_STAT_LB_PORT_1024B_1518B_IX,
1460 FW_STAT_LB_PORT_1519B_MAX_IX,
1461 FW_STAT_LB_PORT_DROP_FRAMES_IX
1464 struct fw_port_lb_stats_cmd {
1465 __be32 op_to_lbport;
1466 __be32 retval_len16;
1467 union fw_port_lb_stats {
1468 struct fw_port_lb_stats_ctl {
1480 struct fw_port_lb_stats_all {
1489 __be64 tx_128b_255b;
1490 __be64 tx_256b_511b;
1491 __be64 tx_512b_1023b;
1492 __be64 tx_1024b_1518b;
1493 __be64 tx_1519b_max;
1500 #define FW_PORT_LB_STATS_CMD_LBPORT(x) ((x) << 0)
1501 #define FW_PORT_LB_STATS_CMD_NSTATS(x) ((x) << 4)
1502 #define FW_PORT_LB_STATS_CMD_BG_BM(x) ((x) << 0)
1503 #define FW_PORT_LB_STATS_CMD_IX(x) ((x) << 0)
1505 struct fw_rss_ind_tbl_cmd {
1507 #define FW_RSS_IND_TBL_CMD_VIID(x) ((x) << 0)
1508 __be32 retval_len16;
1513 #define FW_RSS_IND_TBL_CMD_IQ0(x) ((x) << 20)
1514 #define FW_RSS_IND_TBL_CMD_IQ1(x) ((x) << 10)
1515 #define FW_RSS_IND_TBL_CMD_IQ2(x) ((x) << 0)
1519 __be32 iq12_to_iq14;
1520 __be32 iq15_to_iq17;
1521 __be32 iq18_to_iq20;
1522 __be32 iq21_to_iq23;
1523 __be32 iq24_to_iq26;
1524 __be32 iq27_to_iq29;
1529 struct fw_rss_glb_config_cmd {
1531 __be32 retval_len16;
1532 union fw_rss_glb_config {
1533 struct fw_rss_glb_config_manual {
1539 struct fw_rss_glb_config_basicvirtual {
1541 __be32 synmapen_to_hashtoeplitz;
1542 #define FW_RSS_GLB_CONFIG_CMD_SYNMAPEN (1U << 8)
1543 #define FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6 (1U << 7)
1544 #define FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6 (1U << 6)
1545 #define FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4 (1U << 5)
1546 #define FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4 (1U << 4)
1547 #define FW_RSS_GLB_CONFIG_CMD_OFDMAPEN (1U << 3)
1548 #define FW_RSS_GLB_CONFIG_CMD_TNLMAPEN (1U << 2)
1549 #define FW_RSS_GLB_CONFIG_CMD_TNLALLLKP (1U << 1)
1550 #define FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ (1U << 0)
1557 #define FW_RSS_GLB_CONFIG_CMD_MODE(x) ((x) << 28)
1558 #define FW_RSS_GLB_CONFIG_CMD_MODE_GET(x) (((x) >> 28) & 0xf)
1560 #define FW_RSS_GLB_CONFIG_CMD_MODE_MANUAL 0
1561 #define FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL 1
1563 struct fw_rss_vi_config_cmd {
1565 #define FW_RSS_VI_CONFIG_CMD_VIID(x) ((x) << 0)
1566 __be32 retval_len16;
1567 union fw_rss_vi_config {
1568 struct fw_rss_vi_config_manual {
1573 struct fw_rss_vi_config_basicvirtual {
1575 __be32 defaultq_to_udpen;
1576 #define FW_RSS_VI_CONFIG_CMD_DEFAULTQ(x) ((x) << 16)
1577 #define FW_RSS_VI_CONFIG_CMD_DEFAULTQ_GET(x) (((x) >> 16) & 0x3ff)
1578 #define FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN (1U << 4)
1579 #define FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN (1U << 3)
1580 #define FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN (1U << 2)
1581 #define FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN (1U << 1)
1582 #define FW_RSS_VI_CONFIG_CMD_UDPEN (1U << 0)
1589 enum fw_error_type {
1590 FW_ERROR_TYPE_EXCEPTION = 0x0,
1591 FW_ERROR_TYPE_HWMODULE = 0x1,
1592 FW_ERROR_TYPE_WR = 0x2,
1593 FW_ERROR_TYPE_ACL = 0x3,
1596 struct fw_error_cmd {
1600 struct fw_error_exception {
1603 struct fw_error_hwmodule {
1607 struct fw_error_wr {
1613 struct fw_error_acl {
1624 struct fw_debug_cmd {
1626 #define FW_DEBUG_CMD_TYPE_GET(x) ((x) & 0xff)
1629 struct fw_debug_assert {
1635 u8 filename_8_15[8];
1638 struct fw_debug_prt {
1641 __be32 dprtstrparam0;
1642 __be32 dprtstrparam1;
1643 __be32 dprtstrparam2;
1644 __be32 dprtstrparam3;
1649 #define FW_PCIE_FW_ERR (1U << 31)
1650 #define FW_PCIE_FW_INIT (1U << 30)
1651 #define FW_PCIE_FW_MASTER_VLD (1U << 15)
1652 #define FW_PCIE_FW_MASTER_MASK 0x7
1653 #define FW_PCIE_FW_MASTER_SHIFT 12
1654 #define FW_PCIE_FW_MASTER(x) ((x) << FW_PCIE_FW_MASTER_SHIFT)
1655 #define FW_PCIE_FW_MASTER_GET(x) (((x) >> FW_PCIE_FW_MASTER_SHIFT) & \
1656 FW_PCIE_FW_MASTER_MASK)
1661 __be16 len512; /* bin length in units of 512-bytes */
1662 __be32 fw_ver; /* firmware version */
1663 __be32 tp_microcode_ver;
1668 u8 intfver_iscsipdu;
1672 __be32 reserved3[27];
1675 #define FW_HDR_FW_VER_MAJOR_GET(x) (((x) >> 24) & 0xff)
1676 #define FW_HDR_FW_VER_MINOR_GET(x) (((x) >> 16) & 0xff)
1677 #define FW_HDR_FW_VER_MICRO_GET(x) (((x) >> 8) & 0xff)
1678 #define FW_HDR_FW_VER_BUILD_GET(x) (((x) >> 0) & 0xff)
1680 #endif /* _T4FW_INTERFACE_H_ */