drivers/net/ethernet/chelsio/cxgb4/t4fw_api.h

   1 /*
   2  * This file is part of the Chelsio T4 Ethernet driver for Linux.
   3  *
   4  * Copyright (c) 2009-2016 Chelsio Communications, Inc. All rights reserved.
   5  *
   6  * This software is available to you under a choice of one of two
   7  * licenses.  You may choose to be licensed under the terms of the GNU
   8  * General Public License (GPL) Version 2, available from the file
   9  * COPYING in the main directory of this source tree, or the
  10  * OpenIB.org BSD license below:
  11  *
  12  *     Redistribution and use in source and binary forms, with or
  13  *     without modification, are permitted provided that the following
  14  *     conditions are met:
  15  *
  16  *      - Redistributions of source code must retain the above
  17  *        copyright notice, this list of conditions and the following
  18  *        disclaimer.
  19  *
  20  *      - Redistributions in binary form must reproduce the above
  21  *        copyright notice, this list of conditions and the following
  22  *        disclaimer in the documentation and/or other materials
  23  *        provided with the distribution.
  24  *
  25  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  26  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  27  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  28  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  29  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  30  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  31  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  32  * SOFTWARE.
  33  */
  34
  35 #ifndef _T4FW_INTERFACE_H_
  36 #define _T4FW_INTERFACE_H_
  37
  38 enum fw_retval {
  39         FW_SUCCESS              = 0,    /* completed successfully */
  40         FW_EPERM                = 1,    /* operation not permitted */
  41         FW_ENOENT               = 2,    /* no such file or directory */
  42         FW_EIO                  = 5,    /* input/output error; hw bad */
  43         FW_ENOEXEC              = 8,    /* exec format error; inv microcode */
  44         FW_EAGAIN               = 11,   /* try again */
  45         FW_ENOMEM               = 12,   /* out of memory */
  46         FW_EFAULT               = 14,   /* bad address; fw bad */
  47         FW_EBUSY                = 16,   /* resource busy */
  48         FW_EEXIST               = 17,   /* file exists */
  49         FW_ENODEV               = 19,   /* no such device */
  50         FW_EINVAL               = 22,   /* invalid argument */
  51         FW_ENOSPC               = 28,   /* no space left on device */
  52         FW_ENOSYS               = 38,   /* functionality not implemented */
  53         FW_ENODATA              = 61,   /* no data available */
  54         FW_EPROTO               = 71,   /* protocol error */
  55         FW_EADDRINUSE           = 98,   /* address already in use */
  56         FW_EADDRNOTAVAIL        = 99,   /* cannot assigned requested address */
  57         FW_ENETDOWN             = 100,  /* network is down */
  58         FW_ENETUNREACH          = 101,  /* network is unreachable */
  59         FW_ENOBUFS              = 105,  /* no buffer space available */
  60         FW_ETIMEDOUT            = 110,  /* timeout */
  61         FW_EINPROGRESS          = 115,  /* fw internal */
  62         FW_SCSI_ABORT_REQUESTED = 128,  /* */
  63         FW_SCSI_ABORT_TIMEDOUT  = 129,  /* */
  64         FW_SCSI_ABORTED         = 130,  /* */
  65         FW_SCSI_CLOSE_REQUESTED = 131,  /* */
  66         FW_ERR_LINK_DOWN        = 132,  /* */
  67         FW_RDEV_NOT_READY       = 133,  /* */
  68         FW_ERR_RDEV_LOST        = 134,  /* */
  69         FW_ERR_RDEV_LOGO        = 135,  /* */
  70         FW_FCOE_NO_XCHG         = 136,  /* */
  71         FW_SCSI_RSP_ERR         = 137,  /* */
  72         FW_ERR_RDEV_IMPL_LOGO   = 138,  /* */
  73         FW_SCSI_UNDER_FLOW_ERR  = 139,  /* */
  74         FW_SCSI_OVER_FLOW_ERR   = 140,  /* */
  75         FW_SCSI_DDP_ERR         = 141,  /* DDP error*/
  76         FW_SCSI_TASK_ERR        = 142,  /* No SCSI tasks available */
  77 };
  78
  79 #define FW_T4VF_SGE_BASE_ADDR      0x0000
  80 #define FW_T4VF_MPS_BASE_ADDR      0x0100
  81 #define FW_T4VF_PL_BASE_ADDR       0x0200
  82 #define FW_T4VF_MBDATA_BASE_ADDR   0x0240
  83 #define FW_T4VF_CIM_BASE_ADDR      0x0300
  84
  85 enum fw_wr_opcodes {
  86         FW_FILTER_WR                   = 0x02,
  87         FW_ULPTX_WR                    = 0x04,
  88         FW_TP_WR                       = 0x05,
  89         FW_ETH_TX_PKT_WR               = 0x08,
  90         FW_OFLD_CONNECTION_WR          = 0x2f,
  91         FW_FLOWC_WR                    = 0x0a,
  92         FW_OFLD_TX_DATA_WR             = 0x0b,
  93         FW_CMD_WR                      = 0x10,
  94         FW_ETH_TX_PKT_VM_WR            = 0x11,
  95         FW_RI_RES_WR                   = 0x0c,
  96         FW_RI_INIT_WR                  = 0x0d,
  97         FW_RI_RDMA_WRITE_WR            = 0x14,
  98         FW_RI_SEND_WR                  = 0x15,
  99         FW_RI_RDMA_READ_WR             = 0x16,
 100         FW_RI_RECV_WR                  = 0x17,
 101         FW_RI_BIND_MW_WR               = 0x18,
 102         FW_RI_FR_NSMR_WR               = 0x19,
 103         FW_RI_FR_NSMR_TPTE_WR          = 0x20,
 104         FW_RI_INV_LSTAG_WR             = 0x1a,
 105         FW_ISCSI_TX_DATA_WR            = 0x45,
 106         FW_PTP_TX_PKT_WR               = 0x46,
 107         FW_CRYPTO_LOOKASIDE_WR         = 0X6d,
 108         FW_LASTC2E_WR                  = 0x70,
 109         FW_FILTER2_WR                  = 0x77
 110 };
 111
 112 struct fw_wr_hdr {
 113         __be32 hi;
 114         __be32 lo;
 115 };
 116
 117 /* work request opcode (hi) */
 118 #define FW_WR_OP_S      24
 119 #define FW_WR_OP_M      0xff
 120 #define FW_WR_OP_V(x)   ((x) << FW_WR_OP_S)
 121 #define FW_WR_OP_G(x)   (((x) >> FW_WR_OP_S) & FW_WR_OP_M)
 122
 123 /* atomic flag (hi) - firmware encapsulates CPLs in CPL_BARRIER */
 124 #define FW_WR_ATOMIC_S          23
 125 #define FW_WR_ATOMIC_V(x)       ((x) << FW_WR_ATOMIC_S)
 126
 127 /* flush flag (hi) - firmware flushes flushable work request buffered
 128  * in the flow context.
 129  */
 130 #define FW_WR_FLUSH_S     22
 131 #define FW_WR_FLUSH_V(x)  ((x) << FW_WR_FLUSH_S)
 132
 133 /* completion flag (hi) - firmware generates a cpl_fw6_ack */
 134 #define FW_WR_COMPL_S     21
 135 #define FW_WR_COMPL_V(x)  ((x) << FW_WR_COMPL_S)
 136 #define FW_WR_COMPL_F     FW_WR_COMPL_V(1U)
 137
 138 /* work request immediate data length (hi) */
 139 #define FW_WR_IMMDLEN_S 0
 140 #define FW_WR_IMMDLEN_M 0xff
 141 #define FW_WR_IMMDLEN_V(x)      ((x) << FW_WR_IMMDLEN_S)
 142
 143 /* egress queue status update to associated ingress queue entry (lo) */
 144 #define FW_WR_EQUIQ_S           31
 145 #define FW_WR_EQUIQ_V(x)        ((x) << FW_WR_EQUIQ_S)
 146 #define FW_WR_EQUIQ_F           FW_WR_EQUIQ_V(1U)
 147
 148 /* egress queue status update to egress queue status entry (lo) */
 149 #define FW_WR_EQUEQ_S           30
 150 #define FW_WR_EQUEQ_V(x)        ((x) << FW_WR_EQUEQ_S)
 151 #define FW_WR_EQUEQ_F           FW_WR_EQUEQ_V(1U)
 152
 153 /* flow context identifier (lo) */
 154 #define FW_WR_FLOWID_S          8
 155 #define FW_WR_FLOWID_V(x)       ((x) << FW_WR_FLOWID_S)
 156
 157 /* length in units of 16-bytes (lo) */
 158 #define FW_WR_LEN16_S           0
 159 #define FW_WR_LEN16_V(x)        ((x) << FW_WR_LEN16_S)
 160
 161 #define HW_TPL_FR_MT_PR_IV_P_FC         0X32B
 162 #define HW_TPL_FR_MT_PR_OV_P_FC         0X327
 163
 164 /* filter wr reply code in cookie in CPL_SET_TCB_RPL */
 165 enum fw_filter_wr_cookie {
 166         FW_FILTER_WR_SUCCESS,
 167         FW_FILTER_WR_FLT_ADDED,
 168         FW_FILTER_WR_FLT_DELETED,
 169         FW_FILTER_WR_SMT_TBL_FULL,
 170         FW_FILTER_WR_EINVAL,
 171 };
 172
 173 struct fw_filter_wr {
 174         __be32 op_pkd;
 175         __be32 len16_pkd;
 176         __be64 r3;
 177         __be32 tid_to_iq;
 178         __be32 del_filter_to_l2tix;
 179         __be16 ethtype;
 180         __be16 ethtypem;
 181         __u8   frag_to_ovlan_vldm;
 182         __u8   smac_sel;
 183         __be16 rx_chan_rx_rpl_iq;
 184         __be32 maci_to_matchtypem;
 185         __u8   ptcl;
 186         __u8   ptclm;
 187         __u8   ttyp;
 188         __u8   ttypm;
 189         __be16 ivlan;
 190         __be16 ivlanm;
 191         __be16 ovlan;
 192         __be16 ovlanm;
 193         __u8   lip[16];
 194         __u8   lipm[16];
 195         __u8   fip[16];
 196         __u8   fipm[16];
 197         __be16 lp;
 198         __be16 lpm;
 199         __be16 fp;
 200         __be16 fpm;
 201         __be16 r7;
 202         __u8   sma[6];
 203 };
 204
 205 struct fw_filter2_wr {
 206         __be32 op_pkd;
 207         __be32 len16_pkd;
 208         __be64 r3;
 209         __be32 tid_to_iq;
 210         __be32 del_filter_to_l2tix;
 211         __be16 ethtype;
 212         __be16 ethtypem;
 213         __u8   frag_to_ovlan_vldm;
 214         __u8   smac_sel;
 215         __be16 rx_chan_rx_rpl_iq;
 216         __be32 maci_to_matchtypem;
 217         __u8   ptcl;
 218         __u8   ptclm;
 219         __u8   ttyp;
 220         __u8   ttypm;
 221         __be16 ivlan;
 222         __be16 ivlanm;
 223         __be16 ovlan;
 224         __be16 ovlanm;
 225         __u8   lip[16];
 226         __u8   lipm[16];
 227         __u8   fip[16];
 228         __u8   fipm[16];
 229         __be16 lp;
 230         __be16 lpm;
 231         __be16 fp;
 232         __be16 fpm;
 233         __be16 r7;
 234         __u8   sma[6];
 235         __be16 r8;
 236         __u8   filter_type_swapmac;
 237         __u8   natmode_to_ulp_type;
 238         __be16 newlport;
 239         __be16 newfport;
 240         __u8   newlip[16];
 241         __u8   newfip[16];
 242         __be32 natseqcheck;
 243         __be32 r9;
 244         __be64 r10;
 245         __be64 r11;
 246         __be64 r12;
 247         __be64 r13;
 248 };
 249
 250 #define FW_FILTER_WR_TID_S      12
 251 #define FW_FILTER_WR_TID_M      0xfffff
 252 #define FW_FILTER_WR_TID_V(x)   ((x) << FW_FILTER_WR_TID_S)
 253 #define FW_FILTER_WR_TID_G(x)   \
 254         (((x) >> FW_FILTER_WR_TID_S) & FW_FILTER_WR_TID_M)
 255
 256 #define FW_FILTER_WR_RQTYPE_S           11
 257 #define FW_FILTER_WR_RQTYPE_M           0x1
 258 #define FW_FILTER_WR_RQTYPE_V(x)        ((x) << FW_FILTER_WR_RQTYPE_S)
 259 #define FW_FILTER_WR_RQTYPE_G(x)        \
 260         (((x) >> FW_FILTER_WR_RQTYPE_S) & FW_FILTER_WR_RQTYPE_M)
 261 #define FW_FILTER_WR_RQTYPE_F   FW_FILTER_WR_RQTYPE_V(1U)
 262
 263 #define FW_FILTER_WR_NOREPLY_S          10
 264 #define FW_FILTER_WR_NOREPLY_M          0x1
 265 #define FW_FILTER_WR_NOREPLY_V(x)       ((x) << FW_FILTER_WR_NOREPLY_S)
 266 #define FW_FILTER_WR_NOREPLY_G(x)       \
 267         (((x) >> FW_FILTER_WR_NOREPLY_S) & FW_FILTER_WR_NOREPLY_M)
 268 #define FW_FILTER_WR_NOREPLY_F  FW_FILTER_WR_NOREPLY_V(1U)
 269
 270 #define FW_FILTER_WR_IQ_S       0
 271 #define FW_FILTER_WR_IQ_M       0x3ff
 272 #define FW_FILTER_WR_IQ_V(x)    ((x) << FW_FILTER_WR_IQ_S)
 273 #define FW_FILTER_WR_IQ_G(x)    \
 274         (((x) >> FW_FILTER_WR_IQ_S) & FW_FILTER_WR_IQ_M)
 275
 276 #define FW_FILTER_WR_DEL_FILTER_S       31
 277 #define FW_FILTER_WR_DEL_FILTER_M       0x1
 278 #define FW_FILTER_WR_DEL_FILTER_V(x)    ((x) << FW_FILTER_WR_DEL_FILTER_S)
 279 #define FW_FILTER_WR_DEL_FILTER_G(x)    \
 280         (((x) >> FW_FILTER_WR_DEL_FILTER_S) & FW_FILTER_WR_DEL_FILTER_M)
 281 #define FW_FILTER_WR_DEL_FILTER_F       FW_FILTER_WR_DEL_FILTER_V(1U)
 282
 283 #define FW_FILTER_WR_RPTTID_S           25
 284 #define FW_FILTER_WR_RPTTID_M           0x1
 285 #define FW_FILTER_WR_RPTTID_V(x)        ((x) << FW_FILTER_WR_RPTTID_S)
 286 #define FW_FILTER_WR_RPTTID_G(x)        \
 287         (((x) >> FW_FILTER_WR_RPTTID_S) & FW_FILTER_WR_RPTTID_M)
 288 #define FW_FILTER_WR_RPTTID_F   FW_FILTER_WR_RPTTID_V(1U)
 289
 290 #define FW_FILTER_WR_DROP_S     24
 291 #define FW_FILTER_WR_DROP_M     0x1
 292 #define FW_FILTER_WR_DROP_V(x)  ((x) << FW_FILTER_WR_DROP_S)
 293 #define FW_FILTER_WR_DROP_G(x)  \
 294         (((x) >> FW_FILTER_WR_DROP_S) & FW_FILTER_WR_DROP_M)
 295 #define FW_FILTER_WR_DROP_F     FW_FILTER_WR_DROP_V(1U)
 296
 297 #define FW_FILTER_WR_DIRSTEER_S         23
 298 #define FW_FILTER_WR_DIRSTEER_M         0x1
 299 #define FW_FILTER_WR_DIRSTEER_V(x)      ((x) << FW_FILTER_WR_DIRSTEER_S)
 300 #define FW_FILTER_WR_DIRSTEER_G(x)      \
 301         (((x) >> FW_FILTER_WR_DIRSTEER_S) & FW_FILTER_WR_DIRSTEER_M)
 302 #define FW_FILTER_WR_DIRSTEER_F FW_FILTER_WR_DIRSTEER_V(1U)
 303
 304 #define FW_FILTER_WR_MASKHASH_S         22
 305 #define FW_FILTER_WR_MASKHASH_M         0x1
 306 #define FW_FILTER_WR_MASKHASH_V(x)      ((x) << FW_FILTER_WR_MASKHASH_S)
 307 #define FW_FILTER_WR_MASKHASH_G(x)      \
 308         (((x) >> FW_FILTER_WR_MASKHASH_S) & FW_FILTER_WR_MASKHASH_M)
 309 #define FW_FILTER_WR_MASKHASH_F FW_FILTER_WR_MASKHASH_V(1U)
 310
 311 #define FW_FILTER_WR_DIRSTEERHASH_S     21
 312 #define FW_FILTER_WR_DIRSTEERHASH_M     0x1
 313 #define FW_FILTER_WR_DIRSTEERHASH_V(x)  ((x) << FW_FILTER_WR_DIRSTEERHASH_S)
 314 #define FW_FILTER_WR_DIRSTEERHASH_G(x)  \
 315         (((x) >> FW_FILTER_WR_DIRSTEERHASH_S) & FW_FILTER_WR_DIRSTEERHASH_M)
 316 #define FW_FILTER_WR_DIRSTEERHASH_F     FW_FILTER_WR_DIRSTEERHASH_V(1U)
 317
 318 #define FW_FILTER_WR_LPBK_S     20
 319 #define FW_FILTER_WR_LPBK_M     0x1
 320 #define FW_FILTER_WR_LPBK_V(x)  ((x) << FW_FILTER_WR_LPBK_S)
 321 #define FW_FILTER_WR_LPBK_G(x)  \
 322         (((x) >> FW_FILTER_WR_LPBK_S) & FW_FILTER_WR_LPBK_M)
 323 #define FW_FILTER_WR_LPBK_F     FW_FILTER_WR_LPBK_V(1U)
 324
 325 #define FW_FILTER_WR_DMAC_S     19
 326 #define FW_FILTER_WR_DMAC_M     0x1
 327 #define FW_FILTER_WR_DMAC_V(x)  ((x) << FW_FILTER_WR_DMAC_S)
 328 #define FW_FILTER_WR_DMAC_G(x)  \
 329         (((x) >> FW_FILTER_WR_DMAC_S) & FW_FILTER_WR_DMAC_M)
 330 #define FW_FILTER_WR_DMAC_F     FW_FILTER_WR_DMAC_V(1U)
 331
 332 #define FW_FILTER_WR_SMAC_S     18
 333 #define FW_FILTER_WR_SMAC_M     0x1
 334 #define FW_FILTER_WR_SMAC_V(x)  ((x) << FW_FILTER_WR_SMAC_S)
 335 #define FW_FILTER_WR_SMAC_G(x)  \
 336         (((x) >> FW_FILTER_WR_SMAC_S) & FW_FILTER_WR_SMAC_M)
 337 #define FW_FILTER_WR_SMAC_F     FW_FILTER_WR_SMAC_V(1U)
 338
 339 #define FW_FILTER_WR_INSVLAN_S          17
 340 #define FW_FILTER_WR_INSVLAN_M          0x1
 341 #define FW_FILTER_WR_INSVLAN_V(x)       ((x) << FW_FILTER_WR_INSVLAN_S)
 342 #define FW_FILTER_WR_INSVLAN_G(x)       \
 343         (((x) >> FW_FILTER_WR_INSVLAN_S) & FW_FILTER_WR_INSVLAN_M)
 344 #define FW_FILTER_WR_INSVLAN_F  FW_FILTER_WR_INSVLAN_V(1U)
 345
 346 #define FW_FILTER_WR_RMVLAN_S           16
 347 #define FW_FILTER_WR_RMVLAN_M           0x1
 348 #define FW_FILTER_WR_RMVLAN_V(x)        ((x) << FW_FILTER_WR_RMVLAN_S)
 349 #define FW_FILTER_WR_RMVLAN_G(x)        \
 350         (((x) >> FW_FILTER_WR_RMVLAN_S) & FW_FILTER_WR_RMVLAN_M)
 351 #define FW_FILTER_WR_RMVLAN_F   FW_FILTER_WR_RMVLAN_V(1U)
 352
 353 #define FW_FILTER_WR_HITCNTS_S          15
 354 #define FW_FILTER_WR_HITCNTS_M          0x1
 355 #define FW_FILTER_WR_HITCNTS_V(x)       ((x) << FW_FILTER_WR_HITCNTS_S)
 356 #define FW_FILTER_WR_HITCNTS_G(x)       \
 357         (((x) >> FW_FILTER_WR_HITCNTS_S) & FW_FILTER_WR_HITCNTS_M)
 358 #define FW_FILTER_WR_HITCNTS_F  FW_FILTER_WR_HITCNTS_V(1U)
 359
 360 #define FW_FILTER_WR_TXCHAN_S           13
 361 #define FW_FILTER_WR_TXCHAN_M           0x3
 362 #define FW_FILTER_WR_TXCHAN_V(x)        ((x) << FW_FILTER_WR_TXCHAN_S)
 363 #define FW_FILTER_WR_TXCHAN_G(x)        \
 364         (((x) >> FW_FILTER_WR_TXCHAN_S) & FW_FILTER_WR_TXCHAN_M)
 365
 366 #define FW_FILTER_WR_PRIO_S     12
 367 #define FW_FILTER_WR_PRIO_M     0x1
 368 #define FW_FILTER_WR_PRIO_V(x)  ((x) << FW_FILTER_WR_PRIO_S)
 369 #define FW_FILTER_WR_PRIO_G(x)  \
 370         (((x) >> FW_FILTER_WR_PRIO_S) & FW_FILTER_WR_PRIO_M)
 371 #define FW_FILTER_WR_PRIO_F     FW_FILTER_WR_PRIO_V(1U)
 372
 373 #define FW_FILTER_WR_L2TIX_S    0
 374 #define FW_FILTER_WR_L2TIX_M    0xfff
 375 #define FW_FILTER_WR_L2TIX_V(x) ((x) << FW_FILTER_WR_L2TIX_S)
 376 #define FW_FILTER_WR_L2TIX_G(x) \
 377         (((x) >> FW_FILTER_WR_L2TIX_S) & FW_FILTER_WR_L2TIX_M)
 378
 379 #define FW_FILTER_WR_FRAG_S     7
 380 #define FW_FILTER_WR_FRAG_M     0x1
 381 #define FW_FILTER_WR_FRAG_V(x)  ((x) << FW_FILTER_WR_FRAG_S)
 382 #define FW_FILTER_WR_FRAG_G(x)  \
 383         (((x) >> FW_FILTER_WR_FRAG_S) & FW_FILTER_WR_FRAG_M)
 384 #define FW_FILTER_WR_FRAG_F     FW_FILTER_WR_FRAG_V(1U)
 385
 386 #define FW_FILTER_WR_FRAGM_S    6
 387 #define FW_FILTER_WR_FRAGM_M    0x1
 388 #define FW_FILTER_WR_FRAGM_V(x) ((x) << FW_FILTER_WR_FRAGM_S)
 389 #define FW_FILTER_WR_FRAGM_G(x) \
 390         (((x) >> FW_FILTER_WR_FRAGM_S) & FW_FILTER_WR_FRAGM_M)
 391 #define FW_FILTER_WR_FRAGM_F    FW_FILTER_WR_FRAGM_V(1U)
 392
 393 #define FW_FILTER_WR_IVLAN_VLD_S        5
 394 #define FW_FILTER_WR_IVLAN_VLD_M        0x1
 395 #define FW_FILTER_WR_IVLAN_VLD_V(x)     ((x) << FW_FILTER_WR_IVLAN_VLD_S)
 396 #define FW_FILTER_WR_IVLAN_VLD_G(x)     \
 397         (((x) >> FW_FILTER_WR_IVLAN_VLD_S) & FW_FILTER_WR_IVLAN_VLD_M)
 398 #define FW_FILTER_WR_IVLAN_VLD_F        FW_FILTER_WR_IVLAN_VLD_V(1U)
 399
 400 #define FW_FILTER_WR_OVLAN_VLD_S        4
 401 #define FW_FILTER_WR_OVLAN_VLD_M        0x1
 402 #define FW_FILTER_WR_OVLAN_VLD_V(x)     ((x) << FW_FILTER_WR_OVLAN_VLD_S)
 403 #define FW_FILTER_WR_OVLAN_VLD_G(x)     \
 404         (((x) >> FW_FILTER_WR_OVLAN_VLD_S) & FW_FILTER_WR_OVLAN_VLD_M)
 405 #define FW_FILTER_WR_OVLAN_VLD_F        FW_FILTER_WR_OVLAN_VLD_V(1U)
 406
 407 #define FW_FILTER_WR_IVLAN_VLDM_S       3
 408 #define FW_FILTER_WR_IVLAN_VLDM_M       0x1
 409 #define FW_FILTER_WR_IVLAN_VLDM_V(x)    ((x) << FW_FILTER_WR_IVLAN_VLDM_S)
 410 #define FW_FILTER_WR_IVLAN_VLDM_G(x)    \
 411         (((x) >> FW_FILTER_WR_IVLAN_VLDM_S) & FW_FILTER_WR_IVLAN_VLDM_M)
 412 #define FW_FILTER_WR_IVLAN_VLDM_F       FW_FILTER_WR_IVLAN_VLDM_V(1U)
 413
 414 #define FW_FILTER_WR_OVLAN_VLDM_S       2
 415 #define FW_FILTER_WR_OVLAN_VLDM_M       0x1
 416 #define FW_FILTER_WR_OVLAN_VLDM_V(x)    ((x) << FW_FILTER_WR_OVLAN_VLDM_S)
 417 #define FW_FILTER_WR_OVLAN_VLDM_G(x)    \
 418         (((x) >> FW_FILTER_WR_OVLAN_VLDM_S) & FW_FILTER_WR_OVLAN_VLDM_M)
 419 #define FW_FILTER_WR_OVLAN_VLDM_F       FW_FILTER_WR_OVLAN_VLDM_V(1U)
 420
 421 #define FW_FILTER_WR_RX_CHAN_S          15
 422 #define FW_FILTER_WR_RX_CHAN_M          0x1
 423 #define FW_FILTER_WR_RX_CHAN_V(x)       ((x) << FW_FILTER_WR_RX_CHAN_S)
 424 #define FW_FILTER_WR_RX_CHAN_G(x)       \
 425         (((x) >> FW_FILTER_WR_RX_CHAN_S) & FW_FILTER_WR_RX_CHAN_M)
 426 #define FW_FILTER_WR_RX_CHAN_F  FW_FILTER_WR_RX_CHAN_V(1U)
 427
 428 #define FW_FILTER_WR_RX_RPL_IQ_S        0
 429 #define FW_FILTER_WR_RX_RPL_IQ_M        0x3ff
 430 #define FW_FILTER_WR_RX_RPL_IQ_V(x)     ((x) << FW_FILTER_WR_RX_RPL_IQ_S)
 431 #define FW_FILTER_WR_RX_RPL_IQ_G(x)     \
 432         (((x) >> FW_FILTER_WR_RX_RPL_IQ_S) & FW_FILTER_WR_RX_RPL_IQ_M)
 433
 434 #define FW_FILTER2_WR_FILTER_TYPE_S     1
 435 #define FW_FILTER2_WR_FILTER_TYPE_M     0x1
 436 #define FW_FILTER2_WR_FILTER_TYPE_V(x)  ((x) << FW_FILTER2_WR_FILTER_TYPE_S)
 437 #define FW_FILTER2_WR_FILTER_TYPE_G(x)  \
 438         (((x) >> FW_FILTER2_WR_FILTER_TYPE_S) & FW_FILTER2_WR_FILTER_TYPE_M)
 439 #define FW_FILTER2_WR_FILTER_TYPE_F     FW_FILTER2_WR_FILTER_TYPE_V(1U)
 440
 441 #define FW_FILTER2_WR_NATMODE_S         5
 442 #define FW_FILTER2_WR_NATMODE_M         0x7
 443 #define FW_FILTER2_WR_NATMODE_V(x)      ((x) << FW_FILTER2_WR_NATMODE_S)
 444 #define FW_FILTER2_WR_NATMODE_G(x)      \
 445         (((x) >> FW_FILTER2_WR_NATMODE_S) & FW_FILTER2_WR_NATMODE_M)
 446
 447 #define FW_FILTER2_WR_NATFLAGCHECK_S    4
 448 #define FW_FILTER2_WR_NATFLAGCHECK_M    0x1
 449 #define FW_FILTER2_WR_NATFLAGCHECK_V(x) ((x) << FW_FILTER2_WR_NATFLAGCHECK_S)
 450 #define FW_FILTER2_WR_NATFLAGCHECK_G(x) \
 451         (((x) >> FW_FILTER2_WR_NATFLAGCHECK_S) & FW_FILTER2_WR_NATFLAGCHECK_M)
 452 #define FW_FILTER2_WR_NATFLAGCHECK_F    FW_FILTER2_WR_NATFLAGCHECK_V(1U)
 453
 454 #define FW_FILTER2_WR_ULP_TYPE_S        0
 455 #define FW_FILTER2_WR_ULP_TYPE_M        0xf
 456 #define FW_FILTER2_WR_ULP_TYPE_V(x)     ((x) << FW_FILTER2_WR_ULP_TYPE_S)
 457 #define FW_FILTER2_WR_ULP_TYPE_G(x)     \
 458         (((x) >> FW_FILTER2_WR_ULP_TYPE_S) & FW_FILTER2_WR_ULP_TYPE_M)
 459
 460 #define FW_FILTER_WR_MACI_S     23
 461 #define FW_FILTER_WR_MACI_M     0x1ff
 462 #define FW_FILTER_WR_MACI_V(x)  ((x) << FW_FILTER_WR_MACI_S)
 463 #define FW_FILTER_WR_MACI_G(x)  \
 464         (((x) >> FW_FILTER_WR_MACI_S) & FW_FILTER_WR_MACI_M)
 465
 466 #define FW_FILTER_WR_MACIM_S    14
 467 #define FW_FILTER_WR_MACIM_M    0x1ff
 468 #define FW_FILTER_WR_MACIM_V(x) ((x) << FW_FILTER_WR_MACIM_S)
 469 #define FW_FILTER_WR_MACIM_G(x) \
 470         (((x) >> FW_FILTER_WR_MACIM_S) & FW_FILTER_WR_MACIM_M)
 471
 472 #define FW_FILTER_WR_FCOE_S     13
 473 #define FW_FILTER_WR_FCOE_M     0x1
 474 #define FW_FILTER_WR_FCOE_V(x)  ((x) << FW_FILTER_WR_FCOE_S)
 475 #define FW_FILTER_WR_FCOE_G(x)  \
 476         (((x) >> FW_FILTER_WR_FCOE_S) & FW_FILTER_WR_FCOE_M)
 477 #define FW_FILTER_WR_FCOE_F     FW_FILTER_WR_FCOE_V(1U)
 478
 479 #define FW_FILTER_WR_FCOEM_S    12
 480 #define FW_FILTER_WR_FCOEM_M    0x1
 481 #define FW_FILTER_WR_FCOEM_V(x) ((x) << FW_FILTER_WR_FCOEM_S)
 482 #define FW_FILTER_WR_FCOEM_G(x) \
 483         (((x) >> FW_FILTER_WR_FCOEM_S) & FW_FILTER_WR_FCOEM_M)
 484 #define FW_FILTER_WR_FCOEM_F    FW_FILTER_WR_FCOEM_V(1U)
 485
 486 #define FW_FILTER_WR_PORT_S     9
 487 #define FW_FILTER_WR_PORT_M     0x7
 488 #define FW_FILTER_WR_PORT_V(x)  ((x) << FW_FILTER_WR_PORT_S)
 489 #define FW_FILTER_WR_PORT_G(x)  \
 490         (((x) >> FW_FILTER_WR_PORT_S) & FW_FILTER_WR_PORT_M)
 491
 492 #define FW_FILTER_WR_PORTM_S    6
 493 #define FW_FILTER_WR_PORTM_M    0x7
 494 #define FW_FILTER_WR_PORTM_V(x) ((x) << FW_FILTER_WR_PORTM_S)
 495 #define FW_FILTER_WR_PORTM_G(x) \
 496         (((x) >> FW_FILTER_WR_PORTM_S) & FW_FILTER_WR_PORTM_M)
 497
 498 #define FW_FILTER_WR_MATCHTYPE_S        3
 499 #define FW_FILTER_WR_MATCHTYPE_M        0x7
 500 #define FW_FILTER_WR_MATCHTYPE_V(x)     ((x) << FW_FILTER_WR_MATCHTYPE_S)
 501 #define FW_FILTER_WR_MATCHTYPE_G(x)     \
 502         (((x) >> FW_FILTER_WR_MATCHTYPE_S) & FW_FILTER_WR_MATCHTYPE_M)
 503
 504 #define FW_FILTER_WR_MATCHTYPEM_S       0
 505 #define FW_FILTER_WR_MATCHTYPEM_M       0x7
 506 #define FW_FILTER_WR_MATCHTYPEM_V(x)    ((x) << FW_FILTER_WR_MATCHTYPEM_S)
 507 #define FW_FILTER_WR_MATCHTYPEM_G(x)    \
 508         (((x) >> FW_FILTER_WR_MATCHTYPEM_S) & FW_FILTER_WR_MATCHTYPEM_M)
 509
 510 struct fw_ulptx_wr {
 511         __be32 op_to_compl;
 512         __be32 flowid_len16;
 513         u64 cookie;
 514 };
 515
 516 struct fw_tp_wr {
 517         __be32 op_to_immdlen;
 518         __be32 flowid_len16;
 519         u64 cookie;
 520 };
 521
 522 struct fw_eth_tx_pkt_wr {
 523         __be32 op_immdlen;
 524         __be32 equiq_to_len16;
 525         __be64 r3;
 526 };
 527
 528 struct fw_ofld_connection_wr {
 529         __be32 op_compl;
 530         __be32 len16_pkd;
 531         __u64  cookie;
 532         __be64 r2;
 533         __be64 r3;
 534         struct fw_ofld_connection_le {
 535                 __be32 version_cpl;
 536                 __be32 filter;
 537                 __be32 r1;
 538                 __be16 lport;
 539                 __be16 pport;
 540                 union fw_ofld_connection_leip {
 541                         struct fw_ofld_connection_le_ipv4 {
 542                                 __be32 pip;
 543                                 __be32 lip;
 544                                 __be64 r0;
 545                                 __be64 r1;
 546                                 __be64 r2;
 547                         } ipv4;
 548                         struct fw_ofld_connection_le_ipv6 {
 549                                 __be64 pip_hi;
 550                                 __be64 pip_lo;
 551                                 __be64 lip_hi;
 552                                 __be64 lip_lo;
 553                         } ipv6;
 554                 } u;
 555         } le;
 556         struct fw_ofld_connection_tcb {
 557                 __be32 t_state_to_astid;
 558                 __be16 cplrxdataack_cplpassacceptrpl;
 559                 __be16 rcv_adv;
 560                 __be32 rcv_nxt;
 561                 __be32 tx_max;
 562                 __be64 opt0;
 563                 __be32 opt2;
 564                 __be32 r1;
 565                 __be64 r2;
 566                 __be64 r3;
 567         } tcb;
 568 };
 569
 570 #define FW_OFLD_CONNECTION_WR_VERSION_S                31
 571 #define FW_OFLD_CONNECTION_WR_VERSION_M                0x1
 572 #define FW_OFLD_CONNECTION_WR_VERSION_V(x)     \
 573         ((x) << FW_OFLD_CONNECTION_WR_VERSION_S)
 574 #define FW_OFLD_CONNECTION_WR_VERSION_G(x)     \
 575         (((x) >> FW_OFLD_CONNECTION_WR_VERSION_S) & \
 576         FW_OFLD_CONNECTION_WR_VERSION_M)
 577 #define FW_OFLD_CONNECTION_WR_VERSION_F        \
 578         FW_OFLD_CONNECTION_WR_VERSION_V(1U)
 579
 580 #define FW_OFLD_CONNECTION_WR_CPL_S    30
 581 #define FW_OFLD_CONNECTION_WR_CPL_M    0x1
 582 #define FW_OFLD_CONNECTION_WR_CPL_V(x) ((x) << FW_OFLD_CONNECTION_WR_CPL_S)
 583 #define FW_OFLD_CONNECTION_WR_CPL_G(x) \
 584         (((x) >> FW_OFLD_CONNECTION_WR_CPL_S) & FW_OFLD_CONNECTION_WR_CPL_M)
 585 #define FW_OFLD_CONNECTION_WR_CPL_F    FW_OFLD_CONNECTION_WR_CPL_V(1U)
 586
 587 #define FW_OFLD_CONNECTION_WR_T_STATE_S                28
 588 #define FW_OFLD_CONNECTION_WR_T_STATE_M                0xf
 589 #define FW_OFLD_CONNECTION_WR_T_STATE_V(x)     \
 590         ((x) << FW_OFLD_CONNECTION_WR_T_STATE_S)
 591 #define FW_OFLD_CONNECTION_WR_T_STATE_G(x)     \
 592         (((x) >> FW_OFLD_CONNECTION_WR_T_STATE_S) & \
 593         FW_OFLD_CONNECTION_WR_T_STATE_M)
 594
 595 #define FW_OFLD_CONNECTION_WR_RCV_SCALE_S      24
 596 #define FW_OFLD_CONNECTION_WR_RCV_SCALE_M      0xf
 597 #define FW_OFLD_CONNECTION_WR_RCV_SCALE_V(x)   \
 598         ((x) << FW_OFLD_CONNECTION_WR_RCV_SCALE_S)
 599 #define FW_OFLD_CONNECTION_WR_RCV_SCALE_G(x)   \
 600         (((x) >> FW_OFLD_CONNECTION_WR_RCV_SCALE_S) & \
 601         FW_OFLD_CONNECTION_WR_RCV_SCALE_M)
 602
 603 #define FW_OFLD_CONNECTION_WR_ASTID_S          0
 604 #define FW_OFLD_CONNECTION_WR_ASTID_M          0xffffff
 605 #define FW_OFLD_CONNECTION_WR_ASTID_V(x)       \
 606         ((x) << FW_OFLD_CONNECTION_WR_ASTID_S)
 607 #define FW_OFLD_CONNECTION_WR_ASTID_G(x)       \
 608         (((x) >> FW_OFLD_CONNECTION_WR_ASTID_S) & FW_OFLD_CONNECTION_WR_ASTID_M)
 609
 610 #define FW_OFLD_CONNECTION_WR_CPLRXDATAACK_S   15
 611 #define FW_OFLD_CONNECTION_WR_CPLRXDATAACK_M   0x1
 612 #define FW_OFLD_CONNECTION_WR_CPLRXDATAACK_V(x)        \
 613         ((x) << FW_OFLD_CONNECTION_WR_CPLRXDATAACK_S)
 614 #define FW_OFLD_CONNECTION_WR_CPLRXDATAACK_G(x)        \
 615         (((x) >> FW_OFLD_CONNECTION_WR_CPLRXDATAACK_S) & \
 616         FW_OFLD_CONNECTION_WR_CPLRXDATAACK_M)
 617 #define FW_OFLD_CONNECTION_WR_CPLRXDATAACK_F   \
 618         FW_OFLD_CONNECTION_WR_CPLRXDATAACK_V(1U)
 619
 620 #define FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_S       14
 621 #define FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_M       0x1
 622 #define FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_V(x)    \
 623         ((x) << FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_S)
 624 #define FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_G(x)    \
 625         (((x) >> FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_S) & \
 626         FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_M)
 627 #define FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_F       \
 628         FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_V(1U)
 629
 630 enum fw_flowc_mnem {
 631         FW_FLOWC_MNEM_PFNVFN,           /* PFN [15:8] VFN [7:0] */
 632         FW_FLOWC_MNEM_CH,
 633         FW_FLOWC_MNEM_PORT,
 634         FW_FLOWC_MNEM_IQID,
 635         FW_FLOWC_MNEM_SNDNXT,
 636         FW_FLOWC_MNEM_RCVNXT,
 637         FW_FLOWC_MNEM_SNDBUF,
 638         FW_FLOWC_MNEM_MSS,
 639         FW_FLOWC_MNEM_TXDATAPLEN_MAX,
 640         FW_FLOWC_MNEM_TCPSTATE,
 641         FW_FLOWC_MNEM_EOSTATE,
 642         FW_FLOWC_MNEM_SCHEDCLASS,
 643         FW_FLOWC_MNEM_DCBPRIO,
 644         FW_FLOWC_MNEM_SND_SCALE,
 645         FW_FLOWC_MNEM_RCV_SCALE,
 646 };
 647
 648 struct fw_flowc_mnemval {
 649         u8 mnemonic;
 650         u8 r4[3];
 651         __be32 val;
 652 };
 653
 654 struct fw_flowc_wr {
 655         __be32 op_to_nparams;
 656         __be32 flowid_len16;
 657         struct fw_flowc_mnemval mnemval[0];
 658 };
 659
 660 #define FW_FLOWC_WR_NPARAMS_S           0
 661 #define FW_FLOWC_WR_NPARAMS_V(x)        ((x) << FW_FLOWC_WR_NPARAMS_S)
 662
 663 struct fw_ofld_tx_data_wr {
 664         __be32 op_to_immdlen;
 665         __be32 flowid_len16;
 666         __be32 plen;
 667         __be32 tunnel_to_proxy;
 668 };
 669
 670 #define FW_OFLD_TX_DATA_WR_TUNNEL_S     19
 671 #define FW_OFLD_TX_DATA_WR_TUNNEL_V(x)  ((x) << FW_OFLD_TX_DATA_WR_TUNNEL_S)
 672
 673 #define FW_OFLD_TX_DATA_WR_SAVE_S       18
 674 #define FW_OFLD_TX_DATA_WR_SAVE_V(x)    ((x) << FW_OFLD_TX_DATA_WR_SAVE_S)
 675
 676 #define FW_OFLD_TX_DATA_WR_FLUSH_S      17
 677 #define FW_OFLD_TX_DATA_WR_FLUSH_V(x)   ((x) << FW_OFLD_TX_DATA_WR_FLUSH_S)
 678 #define FW_OFLD_TX_DATA_WR_FLUSH_F      FW_OFLD_TX_DATA_WR_FLUSH_V(1U)
 679
 680 #define FW_OFLD_TX_DATA_WR_URGENT_S     16
 681 #define FW_OFLD_TX_DATA_WR_URGENT_V(x)  ((x) << FW_OFLD_TX_DATA_WR_URGENT_S)
 682
 683 #define FW_OFLD_TX_DATA_WR_MORE_S       15
 684 #define FW_OFLD_TX_DATA_WR_MORE_V(x)    ((x) << FW_OFLD_TX_DATA_WR_MORE_S)
 685
 686 #define FW_OFLD_TX_DATA_WR_SHOVE_S      14
 687 #define FW_OFLD_TX_DATA_WR_SHOVE_V(x)   ((x) << FW_OFLD_TX_DATA_WR_SHOVE_S)
 688 #define FW_OFLD_TX_DATA_WR_SHOVE_F      FW_OFLD_TX_DATA_WR_SHOVE_V(1U)
 689
 690 #define FW_OFLD_TX_DATA_WR_ULPMODE_S    10
 691 #define FW_OFLD_TX_DATA_WR_ULPMODE_V(x) ((x) << FW_OFLD_TX_DATA_WR_ULPMODE_S)
 692
 693 #define FW_OFLD_TX_DATA_WR_ULPSUBMODE_S         6
 694 #define FW_OFLD_TX_DATA_WR_ULPSUBMODE_V(x)      \
 695         ((x) << FW_OFLD_TX_DATA_WR_ULPSUBMODE_S)
 696
 697 struct fw_cmd_wr {
 698         __be32 op_dma;
 699         __be32 len16_pkd;
 700         __be64 cookie_daddr;
 701 };
 702
 703 #define FW_CMD_WR_DMA_S         17
 704 #define FW_CMD_WR_DMA_V(x)      ((x) << FW_CMD_WR_DMA_S)
 705
 706 struct fw_eth_tx_pkt_vm_wr {
 707         __be32 op_immdlen;
 708         __be32 equiq_to_len16;
 709         __be32 r3[2];
 710         u8 ethmacdst[6];
 711         u8 ethmacsrc[6];
 712         __be16 ethtype;
 713         __be16 vlantci;
 714 };
 715
 716 #define FW_CMD_MAX_TIMEOUT 10000
 717
 718 /*
 719  * If a host driver does a HELLO and discovers that there's already a MASTER
 720  * selected, we may have to wait for that MASTER to finish issuing RESET,
 721  * configuration and INITIALIZE commands.  Also, there's a possibility that
 722  * our own HELLO may get lost if it happens right as the MASTER is issuign a
 723  * RESET command, so we need to be willing to make a few retries of our HELLO.
 724  */
 725 #define FW_CMD_HELLO_TIMEOUT    (3 * FW_CMD_MAX_TIMEOUT)
 726 #define FW_CMD_HELLO_RETRIES    3
 727
 728
 729 enum fw_cmd_opcodes {
 730         FW_LDST_CMD                    = 0x01,
 731         FW_RESET_CMD                   = 0x03,
 732         FW_HELLO_CMD                   = 0x04,
 733         FW_BYE_CMD                     = 0x05,
 734         FW_INITIALIZE_CMD              = 0x06,
 735         FW_CAPS_CONFIG_CMD             = 0x07,
 736         FW_PARAMS_CMD                  = 0x08,
 737         FW_PFVF_CMD                    = 0x09,
 738         FW_IQ_CMD                      = 0x10,
 739         FW_EQ_MNGT_CMD                 = 0x11,
 740         FW_EQ_ETH_CMD                  = 0x12,
 741         FW_EQ_CTRL_CMD                 = 0x13,
 742         FW_EQ_OFLD_CMD                 = 0x21,
 743         FW_VI_CMD                      = 0x14,
 744         FW_VI_MAC_CMD                  = 0x15,
 745         FW_VI_RXMODE_CMD               = 0x16,
 746         FW_VI_ENABLE_CMD               = 0x17,
 747         FW_ACL_MAC_CMD                 = 0x18,
 748         FW_ACL_VLAN_CMD                = 0x19,
 749         FW_VI_STATS_CMD                = 0x1a,
 750         FW_PORT_CMD                    = 0x1b,
 751         FW_PORT_STATS_CMD              = 0x1c,
 752         FW_PORT_LB_STATS_CMD           = 0x1d,
 753         FW_PORT_TRACE_CMD              = 0x1e,
 754         FW_PORT_TRACE_MMAP_CMD         = 0x1f,
 755         FW_RSS_IND_TBL_CMD             = 0x20,
 756         FW_RSS_GLB_CONFIG_CMD          = 0x22,
 757         FW_RSS_VI_CONFIG_CMD           = 0x23,
 758         FW_SCHED_CMD                   = 0x24,
 759         FW_DEVLOG_CMD                  = 0x25,
 760         FW_CLIP_CMD                    = 0x28,
 761         FW_PTP_CMD                     = 0x3e,
 762         FW_LASTC2E_CMD                 = 0x40,
 763         FW_ERROR_CMD                   = 0x80,
 764         FW_DEBUG_CMD                   = 0x81,
 765 };
 766
 767 enum fw_cmd_cap {
 768         FW_CMD_CAP_PF                  = 0x01,
 769         FW_CMD_CAP_DMAQ                = 0x02,
 770         FW_CMD_CAP_PORT                = 0x04,
 771         FW_CMD_CAP_PORTPROMISC         = 0x08,
 772         FW_CMD_CAP_PORTSTATS           = 0x10,
 773         FW_CMD_CAP_VF                  = 0x80,
 774 };
 775
 776 /*
 777  * Generic command header flit0
 778  */
 779 struct fw_cmd_hdr {
 780         __be32 hi;
 781         __be32 lo;
 782 };
 783
 784 #define FW_CMD_OP_S             24
 785 #define FW_CMD_OP_M             0xff
 786 #define FW_CMD_OP_V(x)          ((x) << FW_CMD_OP_S)
 787 #define FW_CMD_OP_G(x)          (((x) >> FW_CMD_OP_S) & FW_CMD_OP_M)
 788
 789 #define FW_CMD_REQUEST_S        23
 790 #define FW_CMD_REQUEST_V(x)     ((x) << FW_CMD_REQUEST_S)
 791 #define FW_CMD_REQUEST_F        FW_CMD_REQUEST_V(1U)
 792
 793 #define FW_CMD_READ_S           22
 794 #define FW_CMD_READ_V(x)        ((x) << FW_CMD_READ_S)
 795 #define FW_CMD_READ_F           FW_CMD_READ_V(1U)
 796
 797 #define FW_CMD_WRITE_S          21
 798 #define FW_CMD_WRITE_V(x)       ((x) << FW_CMD_WRITE_S)
 799 #define FW_CMD_WRITE_F          FW_CMD_WRITE_V(1U)
 800
 801 #define FW_CMD_EXEC_S           20
 802 #define FW_CMD_EXEC_V(x)        ((x) << FW_CMD_EXEC_S)
 803 #define FW_CMD_EXEC_F           FW_CMD_EXEC_V(1U)
 804
 805 #define FW_CMD_RAMASK_S         20
 806 #define FW_CMD_RAMASK_V(x)      ((x) << FW_CMD_RAMASK_S)
 807
 808 #define FW_CMD_RETVAL_S         8
 809 #define FW_CMD_RETVAL_M         0xff
 810 #define FW_CMD_RETVAL_V(x)      ((x) << FW_CMD_RETVAL_S)
 811 #define FW_CMD_RETVAL_G(x)      (((x) >> FW_CMD_RETVAL_S) & FW_CMD_RETVAL_M)
 812
 813 #define FW_CMD_LEN16_S          0
 814 #define FW_CMD_LEN16_V(x)       ((x) << FW_CMD_LEN16_S)
 815
 816 #define FW_LEN16(fw_struct)     FW_CMD_LEN16_V(sizeof(fw_struct) / 16)
 817
 818 enum fw_ldst_addrspc {
 819         FW_LDST_ADDRSPC_FIRMWARE  = 0x0001,
 820         FW_LDST_ADDRSPC_SGE_EGRC  = 0x0008,
 821         FW_LDST_ADDRSPC_SGE_INGC  = 0x0009,
 822         FW_LDST_ADDRSPC_SGE_FLMC  = 0x000a,
 823         FW_LDST_ADDRSPC_SGE_CONMC = 0x000b,
 824         FW_LDST_ADDRSPC_TP_PIO    = 0x0010,
 825         FW_LDST_ADDRSPC_TP_TM_PIO = 0x0011,
 826         FW_LDST_ADDRSPC_TP_MIB    = 0x0012,
 827         FW_LDST_ADDRSPC_MDIO      = 0x0018,
 828         FW_LDST_ADDRSPC_MPS       = 0x0020,
 829         FW_LDST_ADDRSPC_FUNC      = 0x0028,
 830         FW_LDST_ADDRSPC_FUNC_PCIE = 0x0029,
 831 };
 832
 833 enum fw_ldst_mps_fid {
 834         FW_LDST_MPS_ATRB,
 835         FW_LDST_MPS_RPLC
 836 };
 837
 838 enum fw_ldst_func_access_ctl {
 839         FW_LDST_FUNC_ACC_CTL_VIID,
 840         FW_LDST_FUNC_ACC_CTL_FID
 841 };
 842
 843 enum fw_ldst_func_mod_index {
 844         FW_LDST_FUNC_MPS
 845 };
 846
 847 struct fw_ldst_cmd {
 848         __be32 op_to_addrspace;
 849         __be32 cycles_to_len16;
 850         union fw_ldst {
 851                 struct fw_ldst_addrval {
 852                         __be32 addr;
 853                         __be32 val;
 854                 } addrval;
 855                 struct fw_ldst_idctxt {
 856                         __be32 physid;
 857                         __be32 msg_ctxtflush;
 858                         __be32 ctxt_data7;
 859                         __be32 ctxt_data6;
 860                         __be32 ctxt_data5;
 861                         __be32 ctxt_data4;
 862                         __be32 ctxt_data3;
 863                         __be32 ctxt_data2;
 864                         __be32 ctxt_data1;
 865                         __be32 ctxt_data0;
 866                 } idctxt;
 867                 struct fw_ldst_mdio {
 868                         __be16 paddr_mmd;
 869                         __be16 raddr;
 870                         __be16 vctl;
 871                         __be16 rval;
 872                 } mdio;
 873                 struct fw_ldst_cim_rq {
 874                         u8 req_first64[8];
 875                         u8 req_second64[8];
 876                         u8 resp_first64[8];
 877                         u8 resp_second64[8];
 878                         __be32 r3[2];
 879                 } cim_rq;
 880                 union fw_ldst_mps {
 881                         struct fw_ldst_mps_rplc {
 882                                 __be16 fid_idx;
 883                                 __be16 rplcpf_pkd;
 884                                 __be32 rplc255_224;
 885                                 __be32 rplc223_192;
 886                                 __be32 rplc191_160;
 887                                 __be32 rplc159_128;
 888                                 __be32 rplc127_96;
 889                                 __be32 rplc95_64;
 890                                 __be32 rplc63_32;
 891                                 __be32 rplc31_0;
 892                         } rplc;
 893                         struct fw_ldst_mps_atrb {
 894                                 __be16 fid_mpsid;
 895                                 __be16 r2[3];
 896                                 __be32 r3[2];
 897                                 __be32 r4;
 898                                 __be32 atrb;
 899                                 __be16 vlan[16];
 900                         } atrb;
 901                 } mps;
 902                 struct fw_ldst_func {
 903                         u8 access_ctl;
 904                         u8 mod_index;
 905                         __be16 ctl_id;
 906                         __be32 offset;
 907                         __be64 data0;
 908                         __be64 data1;
 909                 } func;
 910                 struct fw_ldst_pcie {
 911                         u8 ctrl_to_fn;
 912                         u8 bnum;
 913                         u8 r;
 914                         u8 ext_r;
 915                         u8 select_naccess;
 916                         u8 pcie_fn;
 917                         __be16 nset_pkd;
 918                         __be32 data[12];
 919                 } pcie;
 920                 struct fw_ldst_i2c_deprecated {
 921                         u8 pid_pkd;
 922                         u8 base;
 923                         u8 boffset;
 924                         u8 data;
 925                         __be32 r9;
 926                 } i2c_deprecated;
 927                 struct fw_ldst_i2c {
 928                         u8 pid;
 929                         u8 did;
 930                         u8 boffset;
 931                         u8 blen;
 932                         __be32 r9;
 933                         __u8   data[48];
 934                 } i2c;
 935                 struct fw_ldst_le {
 936                         __be32 index;
 937                         __be32 r9;
 938                         u8 val[33];
 939                         u8 r11[7];
 940                 } le;
 941         } u;
 942 };
 943
 944 #define FW_LDST_CMD_ADDRSPACE_S         0
 945 #define FW_LDST_CMD_ADDRSPACE_V(x)      ((x) << FW_LDST_CMD_ADDRSPACE_S)
 946
 947 #define FW_LDST_CMD_MSG_S       31
 948 #define FW_LDST_CMD_MSG_V(x)    ((x) << FW_LDST_CMD_MSG_S)
 949
 950 #define FW_LDST_CMD_CTXTFLUSH_S         30
 951 #define FW_LDST_CMD_CTXTFLUSH_V(x)      ((x) << FW_LDST_CMD_CTXTFLUSH_S)
 952 #define FW_LDST_CMD_CTXTFLUSH_F         FW_LDST_CMD_CTXTFLUSH_V(1U)
 953
 954 #define FW_LDST_CMD_PADDR_S     8
 955 #define FW_LDST_CMD_PADDR_V(x)  ((x) << FW_LDST_CMD_PADDR_S)
 956
 957 #define FW_LDST_CMD_MMD_S       0
 958 #define FW_LDST_CMD_MMD_V(x)    ((x) << FW_LDST_CMD_MMD_S)
 959
 960 #define FW_LDST_CMD_FID_S       15
 961 #define FW_LDST_CMD_FID_V(x)    ((x) << FW_LDST_CMD_FID_S)
 962
 963 #define FW_LDST_CMD_IDX_S       0
 964 #define FW_LDST_CMD_IDX_V(x)    ((x) << FW_LDST_CMD_IDX_S)
 965
 966 #define FW_LDST_CMD_RPLCPF_S    0
 967 #define FW_LDST_CMD_RPLCPF_V(x) ((x) << FW_LDST_CMD_RPLCPF_S)
 968
 969 #define FW_LDST_CMD_LC_S        4
 970 #define FW_LDST_CMD_LC_V(x)     ((x) << FW_LDST_CMD_LC_S)
 971 #define FW_LDST_CMD_LC_F        FW_LDST_CMD_LC_V(1U)
 972
 973 #define FW_LDST_CMD_FN_S        0
 974 #define FW_LDST_CMD_FN_V(x)     ((x) << FW_LDST_CMD_FN_S)
 975
 976 #define FW_LDST_CMD_NACCESS_S           0
 977 #define FW_LDST_CMD_NACCESS_V(x)        ((x) << FW_LDST_CMD_NACCESS_S)
 978
 979 struct fw_reset_cmd {
 980         __be32 op_to_write;
 981         __be32 retval_len16;
 982         __be32 val;
 983         __be32 halt_pkd;
 984 };
 985
 986 #define FW_RESET_CMD_HALT_S     31
 987 #define FW_RESET_CMD_HALT_M     0x1
 988 #define FW_RESET_CMD_HALT_V(x)  ((x) << FW_RESET_CMD_HALT_S)
 989 #define FW_RESET_CMD_HALT_G(x)  \
 990         (((x) >> FW_RESET_CMD_HALT_S) & FW_RESET_CMD_HALT_M)
 991 #define FW_RESET_CMD_HALT_F     FW_RESET_CMD_HALT_V(1U)
 992
 993 enum fw_hellow_cmd {
 994         fw_hello_cmd_stage_os           = 0x0
 995 };
 996
 997 struct fw_hello_cmd {
 998         __be32 op_to_write;
 999         __be32 retval_len16;
1000         __be32 err_to_clearinit;
1001         __be32 fwrev;
1002 };
1003
1004 #define FW_HELLO_CMD_ERR_S      31
1005 #define FW_HELLO_CMD_ERR_V(x)   ((x) << FW_HELLO_CMD_ERR_S)
1006 #define FW_HELLO_CMD_ERR_F      FW_HELLO_CMD_ERR_V(1U)
1007
1008 #define FW_HELLO_CMD_INIT_S     30
1009 #define FW_HELLO_CMD_INIT_V(x)  ((x) << FW_HELLO_CMD_INIT_S)
1010 #define FW_HELLO_CMD_INIT_F     FW_HELLO_CMD_INIT_V(1U)
1011
1012 #define FW_HELLO_CMD_MASTERDIS_S        29
1013 #define FW_HELLO_CMD_MASTERDIS_V(x)     ((x) << FW_HELLO_CMD_MASTERDIS_S)
1014
1015 #define FW_HELLO_CMD_MASTERFORCE_S      28
1016 #define FW_HELLO_CMD_MASTERFORCE_V(x)   ((x) << FW_HELLO_CMD_MASTERFORCE_S)
1017
1018 #define FW_HELLO_CMD_MBMASTER_S         24
1019 #define FW_HELLO_CMD_MBMASTER_M         0xfU
1020 #define FW_HELLO_CMD_MBMASTER_V(x)      ((x) << FW_HELLO_CMD_MBMASTER_S)
1021 #define FW_HELLO_CMD_MBMASTER_G(x)      \
1022         (((x) >> FW_HELLO_CMD_MBMASTER_S) & FW_HELLO_CMD_MBMASTER_M)
1023
1024 #define FW_HELLO_CMD_MBASYNCNOTINT_S    23
1025 #define FW_HELLO_CMD_MBASYNCNOTINT_V(x) ((x) << FW_HELLO_CMD_MBASYNCNOTINT_S)
1026
1027 #define FW_HELLO_CMD_MBASYNCNOT_S       20
1028 #define FW_HELLO_CMD_MBASYNCNOT_V(x)    ((x) << FW_HELLO_CMD_MBASYNCNOT_S)
1029
1030 #define FW_HELLO_CMD_STAGE_S            17
1031 #define FW_HELLO_CMD_STAGE_V(x)         ((x) << FW_HELLO_CMD_STAGE_S)
1032
1033 #define FW_HELLO_CMD_CLEARINIT_S        16
1034 #define FW_HELLO_CMD_CLEARINIT_V(x)     ((x) << FW_HELLO_CMD_CLEARINIT_S)
1035 #define FW_HELLO_CMD_CLEARINIT_F        FW_HELLO_CMD_CLEARINIT_V(1U)
1036
1037 struct fw_bye_cmd {
1038         __be32 op_to_write;
1039         __be32 retval_len16;
1040         __be64 r3;
1041 };
1042
1043 struct fw_initialize_cmd {
1044         __be32 op_to_write;
1045         __be32 retval_len16;
1046         __be64 r3;
1047 };
1048
1049 enum fw_caps_config_hm {
1050         FW_CAPS_CONFIG_HM_PCIE          = 0x00000001,
1051         FW_CAPS_CONFIG_HM_PL            = 0x00000002,
1052         FW_CAPS_CONFIG_HM_SGE           = 0x00000004,
1053         FW_CAPS_CONFIG_HM_CIM           = 0x00000008,
1054         FW_CAPS_CONFIG_HM_ULPTX         = 0x00000010,
1055         FW_CAPS_CONFIG_HM_TP            = 0x00000020,
1056         FW_CAPS_CONFIG_HM_ULPRX         = 0x00000040,
1057         FW_CAPS_CONFIG_HM_PMRX          = 0x00000080,
1058         FW_CAPS_CONFIG_HM_PMTX          = 0x00000100,
1059         FW_CAPS_CONFIG_HM_MC            = 0x00000200,
1060         FW_CAPS_CONFIG_HM_LE            = 0x00000400,
1061         FW_CAPS_CONFIG_HM_MPS           = 0x00000800,
1062         FW_CAPS_CONFIG_HM_XGMAC         = 0x00001000,
1063         FW_CAPS_CONFIG_HM_CPLSWITCH     = 0x00002000,
1064         FW_CAPS_CONFIG_HM_T4DBG         = 0x00004000,
1065         FW_CAPS_CONFIG_HM_MI            = 0x00008000,
1066         FW_CAPS_CONFIG_HM_I2CM          = 0x00010000,
1067         FW_CAPS_CONFIG_HM_NCSI          = 0x00020000,
1068         FW_CAPS_CONFIG_HM_SMB           = 0x00040000,
1069         FW_CAPS_CONFIG_HM_MA            = 0x00080000,
1070         FW_CAPS_CONFIG_HM_EDRAM         = 0x00100000,
1071         FW_CAPS_CONFIG_HM_PMU           = 0x00200000,
1072         FW_CAPS_CONFIG_HM_UART          = 0x00400000,
1073         FW_CAPS_CONFIG_HM_SF            = 0x00800000,
1074 };
1075
1076 enum fw_caps_config_nbm {
1077         FW_CAPS_CONFIG_NBM_IPMI         = 0x00000001,
1078         FW_CAPS_CONFIG_NBM_NCSI         = 0x00000002,
1079 };
1080
1081 enum fw_caps_config_link {
1082         FW_CAPS_CONFIG_LINK_PPP         = 0x00000001,
1083         FW_CAPS_CONFIG_LINK_QFC         = 0x00000002,
1084         FW_CAPS_CONFIG_LINK_DCBX        = 0x00000004,
1085 };
1086
1087 enum fw_caps_config_switch {
1088         FW_CAPS_CONFIG_SWITCH_INGRESS   = 0x00000001,
1089         FW_CAPS_CONFIG_SWITCH_EGRESS    = 0x00000002,
1090 };
1091
1092 enum fw_caps_config_nic {
1093         FW_CAPS_CONFIG_NIC              = 0x00000001,
1094         FW_CAPS_CONFIG_NIC_VM           = 0x00000002,
1095         FW_CAPS_CONFIG_NIC_HASHFILTER   = 0x00000020,
1096 };
1097
1098 enum fw_caps_config_ofld {
1099         FW_CAPS_CONFIG_OFLD             = 0x00000001,
1100 };
1101
1102 enum fw_caps_config_rdma {
1103         FW_CAPS_CONFIG_RDMA_RDDP        = 0x00000001,
1104         FW_CAPS_CONFIG_RDMA_RDMAC       = 0x00000002,
1105 };
1106
1107 enum fw_caps_config_iscsi {
1108         FW_CAPS_CONFIG_ISCSI_INITIATOR_PDU = 0x00000001,
1109         FW_CAPS_CONFIG_ISCSI_TARGET_PDU = 0x00000002,
1110         FW_CAPS_CONFIG_ISCSI_INITIATOR_CNXOFLD = 0x00000004,
1111         FW_CAPS_CONFIG_ISCSI_TARGET_CNXOFLD = 0x00000008,
1112 };
1113
1114 enum fw_caps_config_fcoe {
1115         FW_CAPS_CONFIG_FCOE_INITIATOR   = 0x00000001,
1116         FW_CAPS_CONFIG_FCOE_TARGET      = 0x00000002,
1117         FW_CAPS_CONFIG_FCOE_CTRL_OFLD   = 0x00000004,
1118 };
1119
1120 enum fw_memtype_cf {
1121         FW_MEMTYPE_CF_EDC0              = 0x0,
1122         FW_MEMTYPE_CF_EDC1              = 0x1,
1123         FW_MEMTYPE_CF_EXTMEM            = 0x2,
1124         FW_MEMTYPE_CF_FLASH             = 0x4,
1125         FW_MEMTYPE_CF_INTERNAL          = 0x5,
1126         FW_MEMTYPE_CF_EXTMEM1           = 0x6,
1127 };
1128
1129 struct fw_caps_config_cmd {
1130         __be32 op_to_write;
1131         __be32 cfvalid_to_len16;
1132         __be32 r2;
1133         __be32 hwmbitmap;
1134         __be16 nbmcaps;
1135         __be16 linkcaps;
1136         __be16 switchcaps;
1137         __be16 r3;
1138         __be16 niccaps;
1139         __be16 ofldcaps;
1140         __be16 rdmacaps;
1141         __be16 cryptocaps;
1142         __be16 iscsicaps;
1143         __be16 fcoecaps;
1144         __be32 cfcsum;
1145         __be32 finiver;
1146         __be32 finicsum;
1147 };
1148
1149 #define FW_CAPS_CONFIG_CMD_CFVALID_S    27
1150 #define FW_CAPS_CONFIG_CMD_CFVALID_V(x) ((x) << FW_CAPS_CONFIG_CMD_CFVALID_S)
1151 #define FW_CAPS_CONFIG_CMD_CFVALID_F    FW_CAPS_CONFIG_CMD_CFVALID_V(1U)
1152
1153 #define FW_CAPS_CONFIG_CMD_MEMTYPE_CF_S         24
1154 #define FW_CAPS_CONFIG_CMD_MEMTYPE_CF_V(x)      \
1155         ((x) << FW_CAPS_CONFIG_CMD_MEMTYPE_CF_S)
1156
1157 #define FW_CAPS_CONFIG_CMD_MEMADDR64K_CF_S      16
1158 #define FW_CAPS_CONFIG_CMD_MEMADDR64K_CF_V(x)   \
1159         ((x) << FW_CAPS_CONFIG_CMD_MEMADDR64K_CF_S)
1160
1161 /*
1162  * params command mnemonics
1163  */
1164 enum fw_params_mnem {
1165         FW_PARAMS_MNEM_DEV              = 1,    /* device params */
1166         FW_PARAMS_MNEM_PFVF             = 2,    /* function params */
1167         FW_PARAMS_MNEM_REG              = 3,    /* limited register access */
1168         FW_PARAMS_MNEM_DMAQ             = 4,    /* dma queue params */
1169         FW_PARAMS_MNEM_CHNET            = 5,    /* chnet params */
1170         FW_PARAMS_MNEM_LAST
1171 };
1172
1173 /*
1174  * device parameters
1175  */
1176 enum fw_params_param_dev {
1177         FW_PARAMS_PARAM_DEV_CCLK        = 0x00, /* chip core clock in khz */
1178         FW_PARAMS_PARAM_DEV_PORTVEC     = 0x01, /* the port vector */
1179         FW_PARAMS_PARAM_DEV_NTID        = 0x02, /* reads the number of TIDs
1180                                                  * allocated by the device's
1181                                                  * Lookup Engine
1182                                                  */
1183         FW_PARAMS_PARAM_DEV_FLOWC_BUFFIFO_SZ = 0x03,
1184         FW_PARAMS_PARAM_DEV_INTVER_NIC  = 0x04,
1185         FW_PARAMS_PARAM_DEV_INTVER_VNIC = 0x05,
1186         FW_PARAMS_PARAM_DEV_INTVER_OFLD = 0x06,
1187         FW_PARAMS_PARAM_DEV_INTVER_RI   = 0x07,
1188         FW_PARAMS_PARAM_DEV_INTVER_ISCSIPDU = 0x08,
1189         FW_PARAMS_PARAM_DEV_INTVER_ISCSI = 0x09,
1190         FW_PARAMS_PARAM_DEV_INTVER_FCOE = 0x0A,
1191         FW_PARAMS_PARAM_DEV_FWREV = 0x0B,
1192         FW_PARAMS_PARAM_DEV_TPREV = 0x0C,
1193         FW_PARAMS_PARAM_DEV_CF = 0x0D,
1194         FW_PARAMS_PARAM_DEV_PHYFW = 0x0F,
1195         FW_PARAMS_PARAM_DEV_DIAG = 0x11,
1196         FW_PARAMS_PARAM_DEV_MAXORDIRD_QP = 0x13, /* max supported QP IRD/ORD */
1197         FW_PARAMS_PARAM_DEV_MAXIRD_ADAPTER = 0x14, /* max supported adap IRD */
1198         FW_PARAMS_PARAM_DEV_ULPTX_MEMWRITE_DSGL = 0x17,
1199         FW_PARAMS_PARAM_DEV_FWCACHE = 0x18,
1200         FW_PARAMS_PARAM_DEV_SCFGREV = 0x1A,
1201         FW_PARAMS_PARAM_DEV_VPDREV = 0x1B,
1202         FW_PARAMS_PARAM_DEV_RI_FR_NSMR_TPTE_WR  = 0x1C,
1203         FW_PARAMS_PARAM_DEV_FILTER2_WR  = 0x1D,
1204         FW_PARAMS_PARAM_DEV_MPSBGMAP    = 0x1E,
1205 };
1206
1207 /*
1208  * physical and virtual function parameters
1209  */
1210 enum fw_params_param_pfvf {
1211         FW_PARAMS_PARAM_PFVF_RWXCAPS    = 0x00,
1212         FW_PARAMS_PARAM_PFVF_ROUTE_START = 0x01,
1213         FW_PARAMS_PARAM_PFVF_ROUTE_END = 0x02,
1214         FW_PARAMS_PARAM_PFVF_CLIP_START = 0x03,
1215         FW_PARAMS_PARAM_PFVF_CLIP_END = 0x04,
1216         FW_PARAMS_PARAM_PFVF_FILTER_START = 0x05,
1217         FW_PARAMS_PARAM_PFVF_FILTER_END = 0x06,
1218         FW_PARAMS_PARAM_PFVF_SERVER_START = 0x07,
1219         FW_PARAMS_PARAM_PFVF_SERVER_END = 0x08,
1220         FW_PARAMS_PARAM_PFVF_TDDP_START = 0x09,
1221         FW_PARAMS_PARAM_PFVF_TDDP_END = 0x0A,
1222         FW_PARAMS_PARAM_PFVF_ISCSI_START = 0x0B,
1223         FW_PARAMS_PARAM_PFVF_ISCSI_END = 0x0C,
1224         FW_PARAMS_PARAM_PFVF_STAG_START = 0x0D,
1225         FW_PARAMS_PARAM_PFVF_STAG_END = 0x0E,
1226         FW_PARAMS_PARAM_PFVF_RQ_START = 0x1F,
1227         FW_PARAMS_PARAM_PFVF_RQ_END     = 0x10,
1228         FW_PARAMS_PARAM_PFVF_PBL_START = 0x11,
1229         FW_PARAMS_PARAM_PFVF_PBL_END    = 0x12,
1230         FW_PARAMS_PARAM_PFVF_L2T_START = 0x13,
1231         FW_PARAMS_PARAM_PFVF_L2T_END = 0x14,
1232         FW_PARAMS_PARAM_PFVF_SQRQ_START = 0x15,
1233         FW_PARAMS_PARAM_PFVF_SQRQ_END   = 0x16,
1234         FW_PARAMS_PARAM_PFVF_CQ_START   = 0x17,
1235         FW_PARAMS_PARAM_PFVF_CQ_END     = 0x18,
1236         FW_PARAMS_PARAM_PFVF_SCHEDCLASS_ETH = 0x20,
1237         FW_PARAMS_PARAM_PFVF_VIID       = 0x24,
1238         FW_PARAMS_PARAM_PFVF_CPMASK     = 0x25,
1239         FW_PARAMS_PARAM_PFVF_OCQ_START  = 0x26,
1240         FW_PARAMS_PARAM_PFVF_OCQ_END    = 0x27,
1241         FW_PARAMS_PARAM_PFVF_CONM_MAP   = 0x28,
1242         FW_PARAMS_PARAM_PFVF_IQFLINT_START = 0x29,
1243         FW_PARAMS_PARAM_PFVF_IQFLINT_END = 0x2A,
1244         FW_PARAMS_PARAM_PFVF_EQ_START   = 0x2B,
1245         FW_PARAMS_PARAM_PFVF_EQ_END     = 0x2C,
1246         FW_PARAMS_PARAM_PFVF_ACTIVE_FILTER_START = 0x2D,
1247         FW_PARAMS_PARAM_PFVF_ACTIVE_FILTER_END = 0x2E,
1248         FW_PARAMS_PARAM_PFVF_ETHOFLD_START = 0x2F,
1249         FW_PARAMS_PARAM_PFVF_ETHOFLD_END = 0x30,
1250         FW_PARAMS_PARAM_PFVF_CPLFW4MSG_ENCAP = 0x31,
1251         FW_PARAMS_PARAM_PFVF_HPFILTER_START = 0x32,
1252         FW_PARAMS_PARAM_PFVF_HPFILTER_END = 0x33,
1253         FW_PARAMS_PARAM_PFVF_NCRYPTO_LOOKASIDE = 0x39,
1254         FW_PARAMS_PARAM_PFVF_PORT_CAPS32 = 0x3A,
1255 };
1256
1257 /*
1258  * dma queue parameters
1259  */
1260 enum fw_params_param_dmaq {
1261         FW_PARAMS_PARAM_DMAQ_IQ_DCAEN_DCACPU = 0x00,
1262         FW_PARAMS_PARAM_DMAQ_IQ_INTCNTTHRESH = 0x01,
1263         FW_PARAMS_PARAM_DMAQ_EQ_CMPLIQID_MNGT = 0x10,
1264         FW_PARAMS_PARAM_DMAQ_EQ_CMPLIQID_CTRL = 0x11,
1265         FW_PARAMS_PARAM_DMAQ_EQ_SCHEDCLASS_ETH = 0x12,
1266         FW_PARAMS_PARAM_DMAQ_EQ_DCBPRIO_ETH = 0x13,
1267         FW_PARAMS_PARAM_DMAQ_CONM_CTXT = 0x20,
1268 };
1269
1270 enum fw_params_param_dev_phyfw {
1271         FW_PARAMS_PARAM_DEV_PHYFW_DOWNLOAD = 0x00,
1272         FW_PARAMS_PARAM_DEV_PHYFW_VERSION = 0x01,
1273 };
1274
1275 enum fw_params_param_dev_diag {
1276         FW_PARAM_DEV_DIAG_TMP           = 0x00,
1277         FW_PARAM_DEV_DIAG_VDD           = 0x01,
1278 };
1279
1280 enum fw_params_param_dev_fwcache {
1281         FW_PARAM_DEV_FWCACHE_FLUSH      = 0x00,
1282         FW_PARAM_DEV_FWCACHE_FLUSHINV   = 0x01,
1283 };
1284
1285 #define FW_PARAMS_MNEM_S        24
1286 #define FW_PARAMS_MNEM_V(x)     ((x) << FW_PARAMS_MNEM_S)
1287
1288 #define FW_PARAMS_PARAM_X_S     16
1289 #define FW_PARAMS_PARAM_X_V(x)  ((x) << FW_PARAMS_PARAM_X_S)
1290
1291 #define FW_PARAMS_PARAM_Y_S     8
1292 #define FW_PARAMS_PARAM_Y_M     0xffU
1293 #define FW_PARAMS_PARAM_Y_V(x)  ((x) << FW_PARAMS_PARAM_Y_S)
1294 #define FW_PARAMS_PARAM_Y_G(x)  (((x) >> FW_PARAMS_PARAM_Y_S) &\
1295                 FW_PARAMS_PARAM_Y_M)
1296
1297 #define FW_PARAMS_PARAM_Z_S     0
1298 #define FW_PARAMS_PARAM_Z_M     0xffu
1299 #define FW_PARAMS_PARAM_Z_V(x)  ((x) << FW_PARAMS_PARAM_Z_S)
1300 #define FW_PARAMS_PARAM_Z_G(x)  (((x) >> FW_PARAMS_PARAM_Z_S) &\
1301                 FW_PARAMS_PARAM_Z_M)
1302
1303 #define FW_PARAMS_PARAM_XYZ_S           0
1304 #define FW_PARAMS_PARAM_XYZ_V(x)        ((x) << FW_PARAMS_PARAM_XYZ_S)
1305
1306 #define FW_PARAMS_PARAM_YZ_S            0
1307 #define FW_PARAMS_PARAM_YZ_V(x)         ((x) << FW_PARAMS_PARAM_YZ_S)
1308
1309 struct fw_params_cmd {
1310         __be32 op_to_vfn;
1311         __be32 retval_len16;
1312         struct fw_params_param {
1313                 __be32 mnem;
1314                 __be32 val;
1315         } param[7];
1316 };
1317
1318 #define FW_PARAMS_CMD_PFN_S     8
1319 #define FW_PARAMS_CMD_PFN_V(x)  ((x) << FW_PARAMS_CMD_PFN_S)
1320
1321 #define FW_PARAMS_CMD_VFN_S     0
1322 #define FW_PARAMS_CMD_VFN_V(x)  ((x) << FW_PARAMS_CMD_VFN_S)
1323
1324 struct fw_pfvf_cmd {
1325         __be32 op_to_vfn;
1326         __be32 retval_len16;
1327         __be32 niqflint_niq;
1328         __be32 type_to_neq;
1329         __be32 tc_to_nexactf;
1330         __be32 r_caps_to_nethctrl;
1331         __be16 nricq;
1332         __be16 nriqp;
1333         __be32 r4;
1334 };
1335
1336 #define FW_PFVF_CMD_PFN_S       8
1337 #define FW_PFVF_CMD_PFN_V(x)    ((x) << FW_PFVF_CMD_PFN_S)
1338
1339 #define FW_PFVF_CMD_VFN_S       0
1340 #define FW_PFVF_CMD_VFN_V(x)    ((x) << FW_PFVF_CMD_VFN_S)
1341
1342 #define FW_PFVF_CMD_NIQFLINT_S          20
1343 #define FW_PFVF_CMD_NIQFLINT_M          0xfff
1344 #define FW_PFVF_CMD_NIQFLINT_V(x)       ((x) << FW_PFVF_CMD_NIQFLINT_S)
1345 #define FW_PFVF_CMD_NIQFLINT_G(x)       \
1346         (((x) >> FW_PFVF_CMD_NIQFLINT_S) & FW_PFVF_CMD_NIQFLINT_M)
1347
1348 #define FW_PFVF_CMD_NIQ_S       0
1349 #define FW_PFVF_CMD_NIQ_M       0xfffff
1350 #define FW_PFVF_CMD_NIQ_V(x)    ((x) << FW_PFVF_CMD_NIQ_S)
1351 #define FW_PFVF_CMD_NIQ_G(x)    \
1352         (((x) >> FW_PFVF_CMD_NIQ_S) & FW_PFVF_CMD_NIQ_M)
1353
1354 #define FW_PFVF_CMD_TYPE_S      31
1355 #define FW_PFVF_CMD_TYPE_M      0x1
1356 #define FW_PFVF_CMD_TYPE_V(x)   ((x) << FW_PFVF_CMD_TYPE_S)
1357 #define FW_PFVF_CMD_TYPE_G(x)   \
1358         (((x) >> FW_PFVF_CMD_TYPE_S) & FW_PFVF_CMD_TYPE_M)
1359 #define FW_PFVF_CMD_TYPE_F      FW_PFVF_CMD_TYPE_V(1U)
1360
1361 #define FW_PFVF_CMD_CMASK_S     24
1362 #define FW_PFVF_CMD_CMASK_M     0xf
1363 #define FW_PFVF_CMD_CMASK_V(x)  ((x) << FW_PFVF_CMD_CMASK_S)
1364 #define FW_PFVF_CMD_CMASK_G(x)  \
1365         (((x) >> FW_PFVF_CMD_CMASK_S) & FW_PFVF_CMD_CMASK_M)
1366
1367 #define FW_PFVF_CMD_PMASK_S     20
1368 #define FW_PFVF_CMD_PMASK_M     0xf
1369 #define FW_PFVF_CMD_PMASK_V(x)  ((x) << FW_PFVF_CMD_PMASK_S)
1370 #define FW_PFVF_CMD_PMASK_G(x) \
1371         (((x) >> FW_PFVF_CMD_PMASK_S) & FW_PFVF_CMD_PMASK_M)
1372
1373 #define FW_PFVF_CMD_NEQ_S       0
1374 #define FW_PFVF_CMD_NEQ_M       0xfffff
1375 #define FW_PFVF_CMD_NEQ_V(x)    ((x) << FW_PFVF_CMD_NEQ_S)
1376 #define FW_PFVF_CMD_NEQ_G(x)    \
1377         (((x) >> FW_PFVF_CMD_NEQ_S) & FW_PFVF_CMD_NEQ_M)
1378
1379 #define FW_PFVF_CMD_TC_S        24
1380 #define FW_PFVF_CMD_TC_M        0xff
1381 #define FW_PFVF_CMD_TC_V(x)     ((x) << FW_PFVF_CMD_TC_S)
1382 #define FW_PFVF_CMD_TC_G(x)     (((x) >> FW_PFVF_CMD_TC_S) & FW_PFVF_CMD_TC_M)
1383
1384 #define FW_PFVF_CMD_NVI_S       16
1385 #define FW_PFVF_CMD_NVI_M       0xff
1386 #define FW_PFVF_CMD_NVI_V(x)    ((x) << FW_PFVF_CMD_NVI_S)
1387 #define FW_PFVF_CMD_NVI_G(x)    (((x) >> FW_PFVF_CMD_NVI_S) & FW_PFVF_CMD_NVI_M)
1388
1389 #define FW_PFVF_CMD_NEXACTF_S           0
1390 #define FW_PFVF_CMD_NEXACTF_M           0xffff
1391 #define FW_PFVF_CMD_NEXACTF_V(x)        ((x) << FW_PFVF_CMD_NEXACTF_S)
1392 #define FW_PFVF_CMD_NEXACTF_G(x)        \
1393         (((x) >> FW_PFVF_CMD_NEXACTF_S) & FW_PFVF_CMD_NEXACTF_M)
1394
1395 #define FW_PFVF_CMD_R_CAPS_S    24
1396 #define FW_PFVF_CMD_R_CAPS_M    0xff
1397 #define FW_PFVF_CMD_R_CAPS_V(x) ((x) << FW_PFVF_CMD_R_CAPS_S)
1398 #define FW_PFVF_CMD_R_CAPS_G(x) \
1399         (((x) >> FW_PFVF_CMD_R_CAPS_S) & FW_PFVF_CMD_R_CAPS_M)
1400
1401 #define FW_PFVF_CMD_WX_CAPS_S           16
1402 #define FW_PFVF_CMD_WX_CAPS_M           0xff
1403 #define FW_PFVF_CMD_WX_CAPS_V(x)        ((x) << FW_PFVF_CMD_WX_CAPS_S)
1404 #define FW_PFVF_CMD_WX_CAPS_G(x)        \
1405         (((x) >> FW_PFVF_CMD_WX_CAPS_S) & FW_PFVF_CMD_WX_CAPS_M)
1406
1407 #define FW_PFVF_CMD_NETHCTRL_S          0
1408 #define FW_PFVF_CMD_NETHCTRL_M          0xffff
1409 #define FW_PFVF_CMD_NETHCTRL_V(x)       ((x) << FW_PFVF_CMD_NETHCTRL_S)
1410 #define FW_PFVF_CMD_NETHCTRL_G(x)       \
1411         (((x) >> FW_PFVF_CMD_NETHCTRL_S) & FW_PFVF_CMD_NETHCTRL_M)
1412
1413 enum fw_iq_type {
1414         FW_IQ_TYPE_FL_INT_CAP,
1415         FW_IQ_TYPE_NO_FL_INT_CAP
1416 };
1417
1418 struct fw_iq_cmd {
1419         __be32 op_to_vfn;
1420         __be32 alloc_to_len16;
1421         __be16 physiqid;
1422         __be16 iqid;
1423         __be16 fl0id;
1424         __be16 fl1id;
1425         __be32 type_to_iqandstindex;
1426         __be16 iqdroprss_to_iqesize;
1427         __be16 iqsize;
1428         __be64 iqaddr;
1429         __be32 iqns_to_fl0congen;
1430         __be16 fl0dcaen_to_fl0cidxfthresh;
1431         __be16 fl0size;
1432         __be64 fl0addr;
1433         __be32 fl1cngchmap_to_fl1congen;
1434         __be16 fl1dcaen_to_fl1cidxfthresh;
1435         __be16 fl1size;
1436         __be64 fl1addr;
1437 };
1438
1439 #define FW_IQ_CMD_PFN_S         8
1440 #define FW_IQ_CMD_PFN_V(x)      ((x) << FW_IQ_CMD_PFN_S)
1441
1442 #define FW_IQ_CMD_VFN_S         0
1443 #define FW_IQ_CMD_VFN_V(x)      ((x) << FW_IQ_CMD_VFN_S)
1444
1445 #define FW_IQ_CMD_ALLOC_S       31
1446 #define FW_IQ_CMD_ALLOC_V(x)    ((x) << FW_IQ_CMD_ALLOC_S)
1447 #define FW_IQ_CMD_ALLOC_F       FW_IQ_CMD_ALLOC_V(1U)
1448
1449 #define FW_IQ_CMD_FREE_S        30
1450 #define FW_IQ_CMD_FREE_V(x)     ((x) << FW_IQ_CMD_FREE_S)
1451 #define FW_IQ_CMD_FREE_F        FW_IQ_CMD_FREE_V(1U)
1452
1453 #define FW_IQ_CMD_MODIFY_S      29
1454 #define FW_IQ_CMD_MODIFY_V(x)   ((x) << FW_IQ_CMD_MODIFY_S)
1455 #define FW_IQ_CMD_MODIFY_F      FW_IQ_CMD_MODIFY_V(1U)
1456
1457 #define FW_IQ_CMD_IQSTART_S     28
1458 #define FW_IQ_CMD_IQSTART_V(x)  ((x) << FW_IQ_CMD_IQSTART_S)
1459 #define FW_IQ_CMD_IQSTART_F     FW_IQ_CMD_IQSTART_V(1U)
1460
1461 #define FW_IQ_CMD_IQSTOP_S      27
1462 #define FW_IQ_CMD_IQSTOP_V(x)   ((x) << FW_IQ_CMD_IQSTOP_S)
1463 #define FW_IQ_CMD_IQSTOP_F      FW_IQ_CMD_IQSTOP_V(1U)
1464
1465 #define FW_IQ_CMD_TYPE_S        29
1466 #define FW_IQ_CMD_TYPE_V(x)     ((x) << FW_IQ_CMD_TYPE_S)
1467
1468 #define FW_IQ_CMD_IQASYNCH_S    28
1469 #define FW_IQ_CMD_IQASYNCH_V(x) ((x) << FW_IQ_CMD_IQASYNCH_S)
1470
1471 #define FW_IQ_CMD_VIID_S        16
1472 #define FW_IQ_CMD_VIID_V(x)     ((x) << FW_IQ_CMD_VIID_S)
1473
1474 #define FW_IQ_CMD_IQANDST_S     15
1475 #define FW_IQ_CMD_IQANDST_V(x)  ((x) << FW_IQ_CMD_IQANDST_S)
1476
1477 #define FW_IQ_CMD_IQANUS_S      14
1478 #define FW_IQ_CMD_IQANUS_V(x)   ((x) << FW_IQ_CMD_IQANUS_S)
1479
1480 #define FW_IQ_CMD_IQANUD_S      12
1481 #define FW_IQ_CMD_IQANUD_V(x)   ((x) << FW_IQ_CMD_IQANUD_S)
1482
1483 #define FW_IQ_CMD_IQANDSTINDEX_S        0
1484 #define FW_IQ_CMD_IQANDSTINDEX_V(x)     ((x) << FW_IQ_CMD_IQANDSTINDEX_S)
1485
1486 #define FW_IQ_CMD_IQDROPRSS_S           15
1487 #define FW_IQ_CMD_IQDROPRSS_V(x)        ((x) << FW_IQ_CMD_IQDROPRSS_S)
1488 #define FW_IQ_CMD_IQDROPRSS_F   FW_IQ_CMD_IQDROPRSS_V(1U)
1489
1490 #define FW_IQ_CMD_IQGTSMODE_S           14
1491 #define FW_IQ_CMD_IQGTSMODE_V(x)        ((x) << FW_IQ_CMD_IQGTSMODE_S)
1492 #define FW_IQ_CMD_IQGTSMODE_F           FW_IQ_CMD_IQGTSMODE_V(1U)
1493
1494 #define FW_IQ_CMD_IQPCIECH_S    12
1495 #define FW_IQ_CMD_IQPCIECH_V(x) ((x) << FW_IQ_CMD_IQPCIECH_S)
1496
1497 #define FW_IQ_CMD_IQDCAEN_S     11
1498 #define FW_IQ_CMD_IQDCAEN_V(x)  ((x) << FW_IQ_CMD_IQDCAEN_S)
1499
1500 #define FW_IQ_CMD_IQDCACPU_S    6
1501 #define FW_IQ_CMD_IQDCACPU_V(x) ((x) << FW_IQ_CMD_IQDCACPU_S)
1502
1503 #define FW_IQ_CMD_IQINTCNTTHRESH_S      4
1504 #define FW_IQ_CMD_IQINTCNTTHRESH_V(x)   ((x) << FW_IQ_CMD_IQINTCNTTHRESH_S)
1505
1506 #define FW_IQ_CMD_IQO_S         3
1507 #define FW_IQ_CMD_IQO_V(x)      ((x) << FW_IQ_CMD_IQO_S)
1508 #define FW_IQ_CMD_IQO_F         FW_IQ_CMD_IQO_V(1U)
1509
1510 #define FW_IQ_CMD_IQCPRIO_S     2
1511 #define FW_IQ_CMD_IQCPRIO_V(x)  ((x) << FW_IQ_CMD_IQCPRIO_S)
1512
1513 #define FW_IQ_CMD_IQESIZE_S     0
1514 #define FW_IQ_CMD_IQESIZE_V(x)  ((x) << FW_IQ_CMD_IQESIZE_S)
1515
1516 #define FW_IQ_CMD_IQNS_S        31
1517 #define FW_IQ_CMD_IQNS_V(x)     ((x) << FW_IQ_CMD_IQNS_S)
1518
1519 #define FW_IQ_CMD_IQRO_S        30
1520 #define FW_IQ_CMD_IQRO_V(x)     ((x) << FW_IQ_CMD_IQRO_S)
1521
1522 #define FW_IQ_CMD_IQFLINTIQHSEN_S       28
1523 #define FW_IQ_CMD_IQFLINTIQHSEN_V(x)    ((x) << FW_IQ_CMD_IQFLINTIQHSEN_S)
1524
1525 #define FW_IQ_CMD_IQFLINTCONGEN_S       27
1526 #define FW_IQ_CMD_IQFLINTCONGEN_V(x)    ((x) << FW_IQ_CMD_IQFLINTCONGEN_S)
1527 #define FW_IQ_CMD_IQFLINTCONGEN_F       FW_IQ_CMD_IQFLINTCONGEN_V(1U)
1528
1529 #define FW_IQ_CMD_IQFLINTISCSIC_S       26
1530 #define FW_IQ_CMD_IQFLINTISCSIC_V(x)    ((x) << FW_IQ_CMD_IQFLINTISCSIC_S)
1531
1532 #define FW_IQ_CMD_FL0CNGCHMAP_S         20
1533 #define FW_IQ_CMD_FL0CNGCHMAP_V(x)      ((x) << FW_IQ_CMD_FL0CNGCHMAP_S)
1534
1535 #define FW_IQ_CMD_FL0CACHELOCK_S        15
1536 #define FW_IQ_CMD_FL0CACHELOCK_V(x)     ((x) << FW_IQ_CMD_FL0CACHELOCK_S)
1537
1538 #define FW_IQ_CMD_FL0DBP_S      14
1539 #define FW_IQ_CMD_FL0DBP_V(x)   ((x) << FW_IQ_CMD_FL0DBP_S)
1540
1541 #define FW_IQ_CMD_FL0DATANS_S           13
1542 #define FW_IQ_CMD_FL0DATANS_V(x)        ((x) << FW_IQ_CMD_FL0DATANS_S)
1543
1544 #define FW_IQ_CMD_FL0DATARO_S           12
1545 #define FW_IQ_CMD_FL0DATARO_V(x)        ((x) << FW_IQ_CMD_FL0DATARO_S)
1546 #define FW_IQ_CMD_FL0DATARO_F           FW_IQ_CMD_FL0DATARO_V(1U)
1547
1548 #define FW_IQ_CMD_FL0CONGCIF_S          11
1549 #define FW_IQ_CMD_FL0CONGCIF_V(x)       ((x) << FW_IQ_CMD_FL0CONGCIF_S)
1550 #define FW_IQ_CMD_FL0CONGCIF_F          FW_IQ_CMD_FL0CONGCIF_V(1U)
1551
1552 #define FW_IQ_CMD_FL0ONCHIP_S           10
1553 #define FW_IQ_CMD_FL0ONCHIP_V(x)        ((x) << FW_IQ_CMD_FL0ONCHIP_S)
1554
1555 #define FW_IQ_CMD_FL0STATUSPGNS_S       9
1556 #define FW_IQ_CMD_FL0STATUSPGNS_V(x)    ((x) << FW_IQ_CMD_FL0STATUSPGNS_S)
1557
1558 #define FW_IQ_CMD_FL0STATUSPGRO_S       8
1559 #define FW_IQ_CMD_FL0STATUSPGRO_V(x)    ((x) << FW_IQ_CMD_FL0STATUSPGRO_S)
1560
1561 #define FW_IQ_CMD_FL0FETCHNS_S          7
1562 #define FW_IQ_CMD_FL0FETCHNS_V(x)       ((x) << FW_IQ_CMD_FL0FETCHNS_S)
1563
1564 #define FW_IQ_CMD_FL0FETCHRO_S          6
1565 #define FW_IQ_CMD_FL0FETCHRO_V(x)       ((x) << FW_IQ_CMD_FL0FETCHRO_S)
1566 #define FW_IQ_CMD_FL0FETCHRO_F          FW_IQ_CMD_FL0FETCHRO_V(1U)
1567
1568 #define FW_IQ_CMD_FL0HOSTFCMODE_S       4
1569 #define FW_IQ_CMD_FL0HOSTFCMODE_V(x)    ((x) << FW_IQ_CMD_FL0HOSTFCMODE_S)
1570
1571 #define FW_IQ_CMD_FL0CPRIO_S    3
1572 #define FW_IQ_CMD_FL0CPRIO_V(x) ((x) << FW_IQ_CMD_FL0CPRIO_S)
1573
1574 #define FW_IQ_CMD_FL0PADEN_S    2
1575 #define FW_IQ_CMD_FL0PADEN_V(x) ((x) << FW_IQ_CMD_FL0PADEN_S)
1576 #define FW_IQ_CMD_FL0PADEN_F    FW_IQ_CMD_FL0PADEN_V(1U)
1577
1578 #define FW_IQ_CMD_FL0PACKEN_S           1
1579 #define FW_IQ_CMD_FL0PACKEN_V(x)        ((x) << FW_IQ_CMD_FL0PACKEN_S)
1580 #define FW_IQ_CMD_FL0PACKEN_F           FW_IQ_CMD_FL0PACKEN_V(1U)
1581
1582 #define FW_IQ_CMD_FL0CONGEN_S           0
1583 #define FW_IQ_CMD_FL0CONGEN_V(x)        ((x) << FW_IQ_CMD_FL0CONGEN_S)
1584 #define FW_IQ_CMD_FL0CONGEN_F           FW_IQ_CMD_FL0CONGEN_V(1U)
1585
1586 #define FW_IQ_CMD_FL0DCAEN_S    15
1587 #define FW_IQ_CMD_FL0DCAEN_V(x) ((x) << FW_IQ_CMD_FL0DCAEN_S)
1588
1589 #define FW_IQ_CMD_FL0DCACPU_S           10
1590 #define FW_IQ_CMD_FL0DCACPU_V(x)        ((x) << FW_IQ_CMD_FL0DCACPU_S)
1591
1592 #define FW_IQ_CMD_FL0FBMIN_S    7
1593 #define FW_IQ_CMD_FL0FBMIN_V(x) ((x) << FW_IQ_CMD_FL0FBMIN_S)
1594
1595 #define FW_IQ_CMD_FL0FBMAX_S    4
1596 #define FW_IQ_CMD_FL0FBMAX_V(x) ((x) << FW_IQ_CMD_FL0FBMAX_S)
1597
1598 #define FW_IQ_CMD_FL0CIDXFTHRESHO_S     3
1599 #define FW_IQ_CMD_FL0CIDXFTHRESHO_V(x)  ((x) << FW_IQ_CMD_FL0CIDXFTHRESHO_S)
1600 #define FW_IQ_CMD_FL0CIDXFTHRESHO_F     FW_IQ_CMD_FL0CIDXFTHRESHO_V(1U)
1601
1602 #define FW_IQ_CMD_FL0CIDXFTHRESH_S      0
1603 #define FW_IQ_CMD_FL0CIDXFTHRESH_V(x)   ((x) << FW_IQ_CMD_FL0CIDXFTHRESH_S)
1604
1605 #define FW_IQ_CMD_FL1CNGCHMAP_S         20
1606 #define FW_IQ_CMD_FL1CNGCHMAP_V(x)      ((x) << FW_IQ_CMD_FL1CNGCHMAP_S)
1607
1608 #define FW_IQ_CMD_FL1CACHELOCK_S        15
1609 #define FW_IQ_CMD_FL1CACHELOCK_V(x)     ((x) << FW_IQ_CMD_FL1CACHELOCK_S)
1610
1611 #define FW_IQ_CMD_FL1DBP_S      14
1612 #define FW_IQ_CMD_FL1DBP_V(x)   ((x) << FW_IQ_CMD_FL1DBP_S)
1613
1614 #define FW_IQ_CMD_FL1DATANS_S           13
1615 #define FW_IQ_CMD_FL1DATANS_V(x)        ((x) << FW_IQ_CMD_FL1DATANS_S)
1616
1617 #define FW_IQ_CMD_FL1DATARO_S           12
1618 #define FW_IQ_CMD_FL1DATARO_V(x)        ((x) << FW_IQ_CMD_FL1DATARO_S)
1619
1620 #define FW_IQ_CMD_FL1CONGCIF_S          11
1621 #define FW_IQ_CMD_FL1CONGCIF_V(x)       ((x) << FW_IQ_CMD_FL1CONGCIF_S)
1622
1623 #define FW_IQ_CMD_FL1ONCHIP_S           10
1624 #define FW_IQ_CMD_FL1ONCHIP_V(x)        ((x) << FW_IQ_CMD_FL1ONCHIP_S)
1625
1626 #define FW_IQ_CMD_FL1STATUSPGNS_S       9
1627 #define FW_IQ_CMD_FL1STATUSPGNS_V(x)    ((x) << FW_IQ_CMD_FL1STATUSPGNS_S)
1628
1629 #define FW_IQ_CMD_FL1STATUSPGRO_S       8
1630 #define FW_IQ_CMD_FL1STATUSPGRO_V(x)    ((x) << FW_IQ_CMD_FL1STATUSPGRO_S)
1631
1632 #define FW_IQ_CMD_FL1FETCHNS_S          7
1633 #define FW_IQ_CMD_FL1FETCHNS_V(x)       ((x) << FW_IQ_CMD_FL1FETCHNS_S)
1634
1635 #define FW_IQ_CMD_FL1FETCHRO_S          6
1636 #define FW_IQ_CMD_FL1FETCHRO_V(x)       ((x) << FW_IQ_CMD_FL1FETCHRO_S)
1637
1638 #define FW_IQ_CMD_FL1HOSTFCMODE_S       4
1639 #define FW_IQ_CMD_FL1HOSTFCMODE_V(x)    ((x) << FW_IQ_CMD_FL1HOSTFCMODE_S)
1640
1641 #define FW_IQ_CMD_FL1CPRIO_S    3
1642 #define FW_IQ_CMD_FL1CPRIO_V(x) ((x) << FW_IQ_CMD_FL1CPRIO_S)
1643
1644 #define FW_IQ_CMD_FL1PADEN_S    2
1645 #define FW_IQ_CMD_FL1PADEN_V(x) ((x) << FW_IQ_CMD_FL1PADEN_S)
1646 #define FW_IQ_CMD_FL1PADEN_F    FW_IQ_CMD_FL1PADEN_V(1U)
1647
1648 #define FW_IQ_CMD_FL1PACKEN_S           1
1649 #define FW_IQ_CMD_FL1PACKEN_V(x)        ((x) << FW_IQ_CMD_FL1PACKEN_S)
1650 #define FW_IQ_CMD_FL1PACKEN_F   FW_IQ_CMD_FL1PACKEN_V(1U)
1651
1652 #define FW_IQ_CMD_FL1CONGEN_S           0
1653 #define FW_IQ_CMD_FL1CONGEN_V(x)        ((x) << FW_IQ_CMD_FL1CONGEN_S)
1654 #define FW_IQ_CMD_FL1CONGEN_F   FW_IQ_CMD_FL1CONGEN_V(1U)
1655
1656 #define FW_IQ_CMD_FL1DCAEN_S    15
1657 #define FW_IQ_CMD_FL1DCAEN_V(x) ((x) << FW_IQ_CMD_FL1DCAEN_S)
1658
1659 #define FW_IQ_CMD_FL1DCACPU_S           10
1660 #define FW_IQ_CMD_FL1DCACPU_V(x)        ((x) << FW_IQ_CMD_FL1DCACPU_S)
1661
1662 #define FW_IQ_CMD_FL1FBMIN_S    7
1663 #define FW_IQ_CMD_FL1FBMIN_V(x) ((x) << FW_IQ_CMD_FL1FBMIN_S)
1664
1665 #define FW_IQ_CMD_FL1FBMAX_S    4
1666 #define FW_IQ_CMD_FL1FBMAX_V(x) ((x) << FW_IQ_CMD_FL1FBMAX_S)
1667
1668 #define FW_IQ_CMD_FL1CIDXFTHRESHO_S     3
1669 #define FW_IQ_CMD_FL1CIDXFTHRESHO_V(x)  ((x) << FW_IQ_CMD_FL1CIDXFTHRESHO_S)
1670 #define FW_IQ_CMD_FL1CIDXFTHRESHO_F     FW_IQ_CMD_FL1CIDXFTHRESHO_V(1U)
1671
1672 #define FW_IQ_CMD_FL1CIDXFTHRESH_S      0
1673 #define FW_IQ_CMD_FL1CIDXFTHRESH_V(x)   ((x) << FW_IQ_CMD_FL1CIDXFTHRESH_S)
1674
1675 struct fw_eq_eth_cmd {
1676         __be32 op_to_vfn;
1677         __be32 alloc_to_len16;
1678         __be32 eqid_pkd;
1679         __be32 physeqid_pkd;
1680         __be32 fetchszm_to_iqid;
1681         __be32 dcaen_to_eqsize;
1682         __be64 eqaddr;
1683         __be32 viid_pkd;
1684         __be32 r8_lo;
1685         __be64 r9;
1686 };
1687
1688 #define FW_EQ_ETH_CMD_PFN_S     8
1689 #define FW_EQ_ETH_CMD_PFN_V(x)  ((x) << FW_EQ_ETH_CMD_PFN_S)
1690
1691 #define FW_EQ_ETH_CMD_VFN_S     0
1692 #define FW_EQ_ETH_CMD_VFN_V(x)  ((x) << FW_EQ_ETH_CMD_VFN_S)
1693
1694 #define FW_EQ_ETH_CMD_ALLOC_S           31
1695 #define FW_EQ_ETH_CMD_ALLOC_V(x)        ((x) << FW_EQ_ETH_CMD_ALLOC_S)
1696 #define FW_EQ_ETH_CMD_ALLOC_F   FW_EQ_ETH_CMD_ALLOC_V(1U)
1697
1698 #define FW_EQ_ETH_CMD_FREE_S    30
1699 #define FW_EQ_ETH_CMD_FREE_V(x) ((x) << FW_EQ_ETH_CMD_FREE_S)
1700 #define FW_EQ_ETH_CMD_FREE_F    FW_EQ_ETH_CMD_FREE_V(1U)
1701
1702 #define FW_EQ_ETH_CMD_MODIFY_S          29
1703 #define FW_EQ_ETH_CMD_MODIFY_V(x)       ((x) << FW_EQ_ETH_CMD_MODIFY_S)
1704 #define FW_EQ_ETH_CMD_MODIFY_F  FW_EQ_ETH_CMD_MODIFY_V(1U)
1705
1706 #define FW_EQ_ETH_CMD_EQSTART_S         28
1707 #define FW_EQ_ETH_CMD_EQSTART_V(x)      ((x) << FW_EQ_ETH_CMD_EQSTART_S)
1708 #define FW_EQ_ETH_CMD_EQSTART_F FW_EQ_ETH_CMD_EQSTART_V(1U)
1709
1710 #define FW_EQ_ETH_CMD_EQSTOP_S          27
1711 #define FW_EQ_ETH_CMD_EQSTOP_V(x)       ((x) << FW_EQ_ETH_CMD_EQSTOP_S)
1712 #define FW_EQ_ETH_CMD_EQSTOP_F  FW_EQ_ETH_CMD_EQSTOP_V(1U)
1713
1714 #define FW_EQ_ETH_CMD_EQID_S    0
1715 #define FW_EQ_ETH_CMD_EQID_M    0xfffff
1716 #define FW_EQ_ETH_CMD_EQID_V(x) ((x) << FW_EQ_ETH_CMD_EQID_S)
1717 #define FW_EQ_ETH_CMD_EQID_G(x) \
1718         (((x) >> FW_EQ_ETH_CMD_EQID_S) & FW_EQ_ETH_CMD_EQID_M)
1719
1720 #define FW_EQ_ETH_CMD_PHYSEQID_S        0
1721 #define FW_EQ_ETH_CMD_PHYSEQID_M        0xfffff
1722 #define FW_EQ_ETH_CMD_PHYSEQID_V(x)     ((x) << FW_EQ_ETH_CMD_PHYSEQID_S)
1723 #define FW_EQ_ETH_CMD_PHYSEQID_G(x)     \
1724         (((x) >> FW_EQ_ETH_CMD_PHYSEQID_S) & FW_EQ_ETH_CMD_PHYSEQID_M)
1725
1726 #define FW_EQ_ETH_CMD_FETCHSZM_S        26
1727 #define FW_EQ_ETH_CMD_FETCHSZM_V(x)     ((x) << FW_EQ_ETH_CMD_FETCHSZM_S)
1728 #define FW_EQ_ETH_CMD_FETCHSZM_F        FW_EQ_ETH_CMD_FETCHSZM_V(1U)
1729
1730 #define FW_EQ_ETH_CMD_STATUSPGNS_S      25
1731 #define FW_EQ_ETH_CMD_STATUSPGNS_V(x)   ((x) << FW_EQ_ETH_CMD_STATUSPGNS_S)
1732
1733 #define FW_EQ_ETH_CMD_STATUSPGRO_S      24
1734 #define FW_EQ_ETH_CMD_STATUSPGRO_V(x)   ((x) << FW_EQ_ETH_CMD_STATUSPGRO_S)
1735
1736 #define FW_EQ_ETH_CMD_FETCHNS_S         23
1737 #define FW_EQ_ETH_CMD_FETCHNS_V(x)      ((x) << FW_EQ_ETH_CMD_FETCHNS_S)
1738
1739 #define FW_EQ_ETH_CMD_FETCHRO_S         22
1740 #define FW_EQ_ETH_CMD_FETCHRO_V(x)      ((x) << FW_EQ_ETH_CMD_FETCHRO_S)
1741 #define FW_EQ_ETH_CMD_FETCHRO_F         FW_EQ_ETH_CMD_FETCHRO_V(1U)
1742
1743 #define FW_EQ_ETH_CMD_HOSTFCMODE_S      20
1744 #define FW_EQ_ETH_CMD_HOSTFCMODE_V(x)   ((x) << FW_EQ_ETH_CMD_HOSTFCMODE_S)
1745
1746 #define FW_EQ_ETH_CMD_CPRIO_S           19
1747 #define FW_EQ_ETH_CMD_CPRIO_V(x)        ((x) << FW_EQ_ETH_CMD_CPRIO_S)
1748
1749 #define FW_EQ_ETH_CMD_ONCHIP_S          18
1750 #define FW_EQ_ETH_CMD_ONCHIP_V(x)       ((x) << FW_EQ_ETH_CMD_ONCHIP_S)
1751
1752 #define FW_EQ_ETH_CMD_PCIECHN_S         16
1753 #define FW_EQ_ETH_CMD_PCIECHN_V(x)      ((x) << FW_EQ_ETH_CMD_PCIECHN_S)
1754
1755 #define FW_EQ_ETH_CMD_IQID_S    0
1756 #define FW_EQ_ETH_CMD_IQID_V(x) ((x) << FW_EQ_ETH_CMD_IQID_S)
1757
1758 #define FW_EQ_ETH_CMD_DCAEN_S           31
1759 #define FW_EQ_ETH_CMD_DCAEN_V(x)        ((x) << FW_EQ_ETH_CMD_DCAEN_S)
1760
1761 #define FW_EQ_ETH_CMD_DCACPU_S          26
1762 #define FW_EQ_ETH_CMD_DCACPU_V(x)       ((x) << FW_EQ_ETH_CMD_DCACPU_S)
1763
1764 #define FW_EQ_ETH_CMD_FBMIN_S           23
1765 #define FW_EQ_ETH_CMD_FBMIN_V(x)        ((x) << FW_EQ_ETH_CMD_FBMIN_S)
1766
1767 #define FW_EQ_ETH_CMD_FBMAX_S           20
1768 #define FW_EQ_ETH_CMD_FBMAX_V(x)        ((x) << FW_EQ_ETH_CMD_FBMAX_S)
1769
1770 #define FW_EQ_ETH_CMD_CIDXFTHRESHO_S    19
1771 #define FW_EQ_ETH_CMD_CIDXFTHRESHO_V(x) ((x) << FW_EQ_ETH_CMD_CIDXFTHRESHO_S)
1772
1773 #define FW_EQ_ETH_CMD_CIDXFTHRESH_S     16
1774 #define FW_EQ_ETH_CMD_CIDXFTHRESH_V(x)  ((x) << FW_EQ_ETH_CMD_CIDXFTHRESH_S)
1775
1776 #define FW_EQ_ETH_CMD_EQSIZE_S          0
1777 #define FW_EQ_ETH_CMD_EQSIZE_V(x)       ((x) << FW_EQ_ETH_CMD_EQSIZE_S)
1778
1779 #define FW_EQ_ETH_CMD_AUTOEQUEQE_S      30
1780 #define FW_EQ_ETH_CMD_AUTOEQUEQE_V(x)   ((x) << FW_EQ_ETH_CMD_AUTOEQUEQE_S)
1781 #define FW_EQ_ETH_CMD_AUTOEQUEQE_F      FW_EQ_ETH_CMD_AUTOEQUEQE_V(1U)
1782
1783 #define FW_EQ_ETH_CMD_VIID_S    16
1784 #define FW_EQ_ETH_CMD_VIID_V(x) ((x) << FW_EQ_ETH_CMD_VIID_S)
1785
1786 struct fw_eq_ctrl_cmd {
1787         __be32 op_to_vfn;
1788         __be32 alloc_to_len16;
1789         __be32 cmpliqid_eqid;
1790         __be32 physeqid_pkd;
1791         __be32 fetchszm_to_iqid;
1792         __be32 dcaen_to_eqsize;
1793         __be64 eqaddr;
1794 };
1795
1796 #define FW_EQ_CTRL_CMD_PFN_S    8
1797 #define FW_EQ_CTRL_CMD_PFN_V(x) ((x) << FW_EQ_CTRL_CMD_PFN_S)
1798
1799 #define FW_EQ_CTRL_CMD_VFN_S    0
1800 #define FW_EQ_CTRL_CMD_VFN_V(x) ((x) << FW_EQ_CTRL_CMD_VFN_S)
1801
1802 #define FW_EQ_CTRL_CMD_ALLOC_S          31
1803 #define FW_EQ_CTRL_CMD_ALLOC_V(x)       ((x) << FW_EQ_CTRL_CMD_ALLOC_S)
1804 #define FW_EQ_CTRL_CMD_ALLOC_F          FW_EQ_CTRL_CMD_ALLOC_V(1U)
1805
1806 #define FW_EQ_CTRL_CMD_FREE_S           30
1807 #define FW_EQ_CTRL_CMD_FREE_V(x)        ((x) << FW_EQ_CTRL_CMD_FREE_S)
1808 #define FW_EQ_CTRL_CMD_FREE_F           FW_EQ_CTRL_CMD_FREE_V(1U)
1809
1810 #define FW_EQ_CTRL_CMD_MODIFY_S         29
1811 #define FW_EQ_CTRL_CMD_MODIFY_V(x)      ((x) << FW_EQ_CTRL_CMD_MODIFY_S)
1812 #define FW_EQ_CTRL_CMD_MODIFY_F         FW_EQ_CTRL_CMD_MODIFY_V(1U)
1813
1814 #define FW_EQ_CTRL_CMD_EQSTART_S        28
1815 #define FW_EQ_CTRL_CMD_EQSTART_V(x)     ((x) << FW_EQ_CTRL_CMD_EQSTART_S)
1816 #define FW_EQ_CTRL_CMD_EQSTART_F        FW_EQ_CTRL_CMD_EQSTART_V(1U)
1817
1818 #define FW_EQ_CTRL_CMD_EQSTOP_S         27
1819 #define FW_EQ_CTRL_CMD_EQSTOP_V(x)      ((x) << FW_EQ_CTRL_CMD_EQSTOP_S)
1820 #define FW_EQ_CTRL_CMD_EQSTOP_F         FW_EQ_CTRL_CMD_EQSTOP_V(1U)
1821
1822 #define FW_EQ_CTRL_CMD_CMPLIQID_S       20
1823 #define FW_EQ_CTRL_CMD_CMPLIQID_V(x)    ((x) << FW_EQ_CTRL_CMD_CMPLIQID_S)
1824
1825 #define FW_EQ_CTRL_CMD_EQID_S           0
1826 #define FW_EQ_CTRL_CMD_EQID_M           0xfffff
1827 #define FW_EQ_CTRL_CMD_EQID_V(x)        ((x) << FW_EQ_CTRL_CMD_EQID_S)
1828 #define FW_EQ_CTRL_CMD_EQID_G(x)        \
1829         (((x) >> FW_EQ_CTRL_CMD_EQID_S) & FW_EQ_CTRL_CMD_EQID_M)
1830
1831 #define FW_EQ_CTRL_CMD_PHYSEQID_S       0
1832 #define FW_EQ_CTRL_CMD_PHYSEQID_M       0xfffff
1833 #define FW_EQ_CTRL_CMD_PHYSEQID_G(x)    \
1834         (((x) >> FW_EQ_CTRL_CMD_PHYSEQID_S) & FW_EQ_CTRL_CMD_PHYSEQID_M)
1835
1836 #define FW_EQ_CTRL_CMD_FETCHSZM_S       26
1837 #define FW_EQ_CTRL_CMD_FETCHSZM_V(x)    ((x) << FW_EQ_CTRL_CMD_FETCHSZM_S)
1838 #define FW_EQ_CTRL_CMD_FETCHSZM_F       FW_EQ_CTRL_CMD_FETCHSZM_V(1U)
1839
1840 #define FW_EQ_CTRL_CMD_STATUSPGNS_S     25
1841 #define FW_EQ_CTRL_CMD_STATUSPGNS_V(x)  ((x) << FW_EQ_CTRL_CMD_STATUSPGNS_S)
1842 #define FW_EQ_CTRL_CMD_STATUSPGNS_F     FW_EQ_CTRL_CMD_STATUSPGNS_V(1U)
1843
1844 #define FW_EQ_CTRL_CMD_STATUSPGRO_S     24
1845 #define FW_EQ_CTRL_CMD_STATUSPGRO_V(x)  ((x) << FW_EQ_CTRL_CMD_STATUSPGRO_S)
1846 #define FW_EQ_CTRL_CMD_STATUSPGRO_F     FW_EQ_CTRL_CMD_STATUSPGRO_V(1U)
1847
1848 #define FW_EQ_CTRL_CMD_FETCHNS_S        23
1849 #define FW_EQ_CTRL_CMD_FETCHNS_V(x)     ((x) << FW_EQ_CTRL_CMD_FETCHNS_S)
1850 #define FW_EQ_CTRL_CMD_FETCHNS_F        FW_EQ_CTRL_CMD_FETCHNS_V(1U)
1851
1852 #define FW_EQ_CTRL_CMD_FETCHRO_S        22
1853 #define FW_EQ_CTRL_CMD_FETCHRO_V(x)     ((x) << FW_EQ_CTRL_CMD_FETCHRO_S)
1854 #define FW_EQ_CTRL_CMD_FETCHRO_F        FW_EQ_CTRL_CMD_FETCHRO_V(1U)
1855
1856 #define FW_EQ_CTRL_CMD_HOSTFCMODE_S     20
1857 #define FW_EQ_CTRL_CMD_HOSTFCMODE_V(x)  ((x) << FW_EQ_CTRL_CMD_HOSTFCMODE_S)
1858
1859 #define FW_EQ_CTRL_CMD_CPRIO_S          19
1860 #define FW_EQ_CTRL_CMD_CPRIO_V(x)       ((x) << FW_EQ_CTRL_CMD_CPRIO_S)
1861
1862 #define FW_EQ_CTRL_CMD_ONCHIP_S         18
1863 #define FW_EQ_CTRL_CMD_ONCHIP_V(x)      ((x) << FW_EQ_CTRL_CMD_ONCHIP_S)
1864
1865 #define FW_EQ_CTRL_CMD_PCIECHN_S        16
1866 #define FW_EQ_CTRL_CMD_PCIECHN_V(x)     ((x) << FW_EQ_CTRL_CMD_PCIECHN_S)
1867
1868 #define FW_EQ_CTRL_CMD_IQID_S           0
1869 #define FW_EQ_CTRL_CMD_IQID_V(x)        ((x) << FW_EQ_CTRL_CMD_IQID_S)
1870
1871 #define FW_EQ_CTRL_CMD_DCAEN_S          31
1872 #define FW_EQ_CTRL_CMD_DCAEN_V(x)       ((x) << FW_EQ_CTRL_CMD_DCAEN_S)
1873
1874 #define FW_EQ_CTRL_CMD_DCACPU_S         26
1875 #define FW_EQ_CTRL_CMD_DCACPU_V(x)      ((x) << FW_EQ_CTRL_CMD_DCACPU_S)
1876
1877 #define FW_EQ_CTRL_CMD_FBMIN_S          23
1878 #define FW_EQ_CTRL_CMD_FBMIN_V(x)       ((x) << FW_EQ_CTRL_CMD_FBMIN_S)
1879
1880 #define FW_EQ_CTRL_CMD_FBMAX_S          20
1881 #define FW_EQ_CTRL_CMD_FBMAX_V(x)       ((x) << FW_EQ_CTRL_CMD_FBMAX_S)
1882
1883 #define FW_EQ_CTRL_CMD_CIDXFTHRESHO_S           19
1884 #define FW_EQ_CTRL_CMD_CIDXFTHRESHO_V(x)        \
1885         ((x) << FW_EQ_CTRL_CMD_CIDXFTHRESHO_S)
1886
1887 #define FW_EQ_CTRL_CMD_CIDXFTHRESH_S    16
1888 #define FW_EQ_CTRL_CMD_CIDXFTHRESH_V(x) ((x) << FW_EQ_CTRL_CMD_CIDXFTHRESH_S)
1889
1890 #define FW_EQ_CTRL_CMD_EQSIZE_S         0
1891 #define FW_EQ_CTRL_CMD_EQSIZE_V(x)      ((x) << FW_EQ_CTRL_CMD_EQSIZE_S)
1892
1893 struct fw_eq_ofld_cmd {
1894         __be32 op_to_vfn;
1895         __be32 alloc_to_len16;
1896         __be32 eqid_pkd;
1897         __be32 physeqid_pkd;
1898         __be32 fetchszm_to_iqid;
1899         __be32 dcaen_to_eqsize;
1900         __be64 eqaddr;
1901 };
1902
1903 #define FW_EQ_OFLD_CMD_PFN_S    8
1904 #define FW_EQ_OFLD_CMD_PFN_V(x) ((x) << FW_EQ_OFLD_CMD_PFN_S)
1905
1906 #define FW_EQ_OFLD_CMD_VFN_S    0
1907 #define FW_EQ_OFLD_CMD_VFN_V(x) ((x) << FW_EQ_OFLD_CMD_VFN_S)
1908
1909 #define FW_EQ_OFLD_CMD_ALLOC_S          31
1910 #define FW_EQ_OFLD_CMD_ALLOC_V(x)       ((x) << FW_EQ_OFLD_CMD_ALLOC_S)
1911 #define FW_EQ_OFLD_CMD_ALLOC_F          FW_EQ_OFLD_CMD_ALLOC_V(1U)
1912
1913 #define FW_EQ_OFLD_CMD_FREE_S           30
1914 #define FW_EQ_OFLD_CMD_FREE_V(x)        ((x) << FW_EQ_OFLD_CMD_FREE_S)
1915 #define FW_EQ_OFLD_CMD_FREE_F           FW_EQ_OFLD_CMD_FREE_V(1U)
1916
1917 #define FW_EQ_OFLD_CMD_MODIFY_S         29
1918 #define FW_EQ_OFLD_CMD_MODIFY_V(x)      ((x) << FW_EQ_OFLD_CMD_MODIFY_S)
1919 #define FW_EQ_OFLD_CMD_MODIFY_F         FW_EQ_OFLD_CMD_MODIFY_V(1U)
1920
1921 #define FW_EQ_OFLD_CMD_EQSTART_S        28
1922 #define FW_EQ_OFLD_CMD_EQSTART_V(x)     ((x) << FW_EQ_OFLD_CMD_EQSTART_S)
1923 #define FW_EQ_OFLD_CMD_EQSTART_F        FW_EQ_OFLD_CMD_EQSTART_V(1U)
1924
1925 #define FW_EQ_OFLD_CMD_EQSTOP_S         27
1926 #define FW_EQ_OFLD_CMD_EQSTOP_V(x)      ((x) << FW_EQ_OFLD_CMD_EQSTOP_S)
1927 #define FW_EQ_OFLD_CMD_EQSTOP_F         FW_EQ_OFLD_CMD_EQSTOP_V(1U)
1928
1929 #define FW_EQ_OFLD_CMD_EQID_S           0
1930 #define FW_EQ_OFLD_CMD_EQID_M           0xfffff
1931 #define FW_EQ_OFLD_CMD_EQID_V(x)        ((x) << FW_EQ_OFLD_CMD_EQID_S)
1932 #define FW_EQ_OFLD_CMD_EQID_G(x)        \
1933         (((x) >> FW_EQ_OFLD_CMD_EQID_S) & FW_EQ_OFLD_CMD_EQID_M)
1934
1935 #define FW_EQ_OFLD_CMD_PHYSEQID_S       0
1936 #define FW_EQ_OFLD_CMD_PHYSEQID_M       0xfffff
1937 #define FW_EQ_OFLD_CMD_PHYSEQID_G(x)    \
1938         (((x) >> FW_EQ_OFLD_CMD_PHYSEQID_S) & FW_EQ_OFLD_CMD_PHYSEQID_M)
1939
1940 #define FW_EQ_OFLD_CMD_FETCHSZM_S       26
1941 #define FW_EQ_OFLD_CMD_FETCHSZM_V(x)    ((x) << FW_EQ_OFLD_CMD_FETCHSZM_S)
1942
1943 #define FW_EQ_OFLD_CMD_STATUSPGNS_S     25
1944 #define FW_EQ_OFLD_CMD_STATUSPGNS_V(x)  ((x) << FW_EQ_OFLD_CMD_STATUSPGNS_S)
1945
1946 #define FW_EQ_OFLD_CMD_STATUSPGRO_S     24
1947 #define FW_EQ_OFLD_CMD_STATUSPGRO_V(x)  ((x) << FW_EQ_OFLD_CMD_STATUSPGRO_S)
1948
1949 #define FW_EQ_OFLD_CMD_FETCHNS_S        23
1950 #define FW_EQ_OFLD_CMD_FETCHNS_V(x)     ((x) << FW_EQ_OFLD_CMD_FETCHNS_S)
1951
1952 #define FW_EQ_OFLD_CMD_FETCHRO_S        22
1953 #define FW_EQ_OFLD_CMD_FETCHRO_V(x)     ((x) << FW_EQ_OFLD_CMD_FETCHRO_S)
1954 #define FW_EQ_OFLD_CMD_FETCHRO_F        FW_EQ_OFLD_CMD_FETCHRO_V(1U)
1955
1956 #define FW_EQ_OFLD_CMD_HOSTFCMODE_S     20
1957 #define FW_EQ_OFLD_CMD_HOSTFCMODE_V(x)  ((x) << FW_EQ_OFLD_CMD_HOSTFCMODE_S)
1958
1959 #define FW_EQ_OFLD_CMD_CPRIO_S          19
1960 #define FW_EQ_OFLD_CMD_CPRIO_V(x)       ((x) << FW_EQ_OFLD_CMD_CPRIO_S)
1961
1962 #define FW_EQ_OFLD_CMD_ONCHIP_S         18
1963 #define FW_EQ_OFLD_CMD_ONCHIP_V(x)      ((x) << FW_EQ_OFLD_CMD_ONCHIP_S)
1964
1965 #define FW_EQ_OFLD_CMD_PCIECHN_S        16
1966 #define FW_EQ_OFLD_CMD_PCIECHN_V(x)     ((x) << FW_EQ_OFLD_CMD_PCIECHN_S)
1967
1968 #define FW_EQ_OFLD_CMD_IQID_S           0
1969 #define FW_EQ_OFLD_CMD_IQID_V(x)        ((x) << FW_EQ_OFLD_CMD_IQID_S)
1970
1971 #define FW_EQ_OFLD_CMD_DCAEN_S          31
1972 #define FW_EQ_OFLD_CMD_DCAEN_V(x)       ((x) << FW_EQ_OFLD_CMD_DCAEN_S)
1973
1974 #define FW_EQ_OFLD_CMD_DCACPU_S         26
1975 #define FW_EQ_OFLD_CMD_DCACPU_V(x)      ((x) << FW_EQ_OFLD_CMD_DCACPU_S)
1976
1977 #define FW_EQ_OFLD_CMD_FBMIN_S          23
1978 #define FW_EQ_OFLD_CMD_FBMIN_V(x)       ((x) << FW_EQ_OFLD_CMD_FBMIN_S)
1979
1980 #define FW_EQ_OFLD_CMD_FBMAX_S          20
1981 #define FW_EQ_OFLD_CMD_FBMAX_V(x)       ((x) << FW_EQ_OFLD_CMD_FBMAX_S)
1982
1983 #define FW_EQ_OFLD_CMD_CIDXFTHRESHO_S           19
1984 #define FW_EQ_OFLD_CMD_CIDXFTHRESHO_V(x)        \
1985         ((x) << FW_EQ_OFLD_CMD_CIDXFTHRESHO_S)
1986
1987 #define FW_EQ_OFLD_CMD_CIDXFTHRESH_S    16
1988 #define FW_EQ_OFLD_CMD_CIDXFTHRESH_V(x) ((x) << FW_EQ_OFLD_CMD_CIDXFTHRESH_S)
1989
1990 #define FW_EQ_OFLD_CMD_EQSIZE_S         0
1991 #define FW_EQ_OFLD_CMD_EQSIZE_V(x)      ((x) << FW_EQ_OFLD_CMD_EQSIZE_S)
1992
1993 /*
1994  * Macros for VIID parsing:
1995  * VIID - [10:8] PFN, [7] VI Valid, [6:0] VI number
1996  */
1997
1998 #define FW_VIID_PFN_S           8
1999 #define FW_VIID_PFN_M           0x7
2000 #define FW_VIID_PFN_G(x)        (((x) >> FW_VIID_PFN_S) & FW_VIID_PFN_M)
2001
2002 #define FW_VIID_VIVLD_S         7
2003 #define FW_VIID_VIVLD_M         0x1
2004 #define FW_VIID_VIVLD_G(x)      (((x) >> FW_VIID_VIVLD_S) & FW_VIID_VIVLD_M)
2005
2006 #define FW_VIID_VIN_S           0
2007 #define FW_VIID_VIN_M           0x7F
2008 #define FW_VIID_VIN_G(x)        (((x) >> FW_VIID_VIN_S) & FW_VIID_VIN_M)
2009
2010 struct fw_vi_cmd {
2011         __be32 op_to_vfn;
2012         __be32 alloc_to_len16;
2013         __be16 type_viid;
2014         u8 mac[6];
2015         u8 portid_pkd;
2016         u8 nmac;
2017         u8 nmac0[6];
2018         __be16 rsssize_pkd;
2019         u8 nmac1[6];
2020         __be16 idsiiq_pkd;
2021         u8 nmac2[6];
2022         __be16 idseiq_pkd;
2023         u8 nmac3[6];
2024         __be64 r9;
2025         __be64 r10;
2026 };
2027
2028 #define FW_VI_CMD_PFN_S         8
2029 #define FW_VI_CMD_PFN_V(x)      ((x) << FW_VI_CMD_PFN_S)
2030
2031 #define FW_VI_CMD_VFN_S         0
2032 #define FW_VI_CMD_VFN_V(x)      ((x) << FW_VI_CMD_VFN_S)
2033
2034 #define FW_VI_CMD_ALLOC_S       31
2035 #define FW_VI_CMD_ALLOC_V(x)    ((x) << FW_VI_CMD_ALLOC_S)
2036 #define FW_VI_CMD_ALLOC_F       FW_VI_CMD_ALLOC_V(1U)
2037
2038 #define FW_VI_CMD_FREE_S        30
2039 #define FW_VI_CMD_FREE_V(x)     ((x) << FW_VI_CMD_FREE_S)
2040 #define FW_VI_CMD_FREE_F        FW_VI_CMD_FREE_V(1U)
2041
2042 #define FW_VI_CMD_VIID_S        0
2043 #define FW_VI_CMD_VIID_M        0xfff
2044 #define FW_VI_CMD_VIID_V(x)     ((x) << FW_VI_CMD_VIID_S)
2045 #define FW_VI_CMD_VIID_G(x)     (((x) >> FW_VI_CMD_VIID_S) & FW_VI_CMD_VIID_M)
2046
2047 #define FW_VI_CMD_PORTID_S      4
2048 #define FW_VI_CMD_PORTID_M      0xf
2049 #define FW_VI_CMD_PORTID_V(x)   ((x) << FW_VI_CMD_PORTID_S)
2050 #define FW_VI_CMD_PORTID_G(x)   \
2051         (((x) >> FW_VI_CMD_PORTID_S) & FW_VI_CMD_PORTID_M)
2052
2053 #define FW_VI_CMD_RSSSIZE_S     0
2054 #define FW_VI_CMD_RSSSIZE_M     0x7ff
2055 #define FW_VI_CMD_RSSSIZE_G(x)  \
2056         (((x) >> FW_VI_CMD_RSSSIZE_S) & FW_VI_CMD_RSSSIZE_M)
2057
2058 /* Special VI_MAC command index ids */
2059 #define FW_VI_MAC_ADD_MAC               0x3FF
2060 #define FW_VI_MAC_ADD_PERSIST_MAC       0x3FE
2061 #define FW_VI_MAC_MAC_BASED_FREE        0x3FD
2062 #define FW_CLS_TCAM_NUM_ENTRIES         336
2063
2064 enum fw_vi_mac_smac {
2065         FW_VI_MAC_MPS_TCAM_ENTRY,
2066         FW_VI_MAC_MPS_TCAM_ONLY,
2067         FW_VI_MAC_SMT_ONLY,
2068         FW_VI_MAC_SMT_AND_MPSTCAM
2069 };
2070
2071 enum fw_vi_mac_result {
2072         FW_VI_MAC_R_SUCCESS,
2073         FW_VI_MAC_R_F_NONEXISTENT_NOMEM,
2074         FW_VI_MAC_R_SMAC_FAIL,
2075         FW_VI_MAC_R_F_ACL_CHECK
2076 };
2077
2078 struct fw_vi_mac_cmd {
2079         __be32 op_to_viid;
2080         __be32 freemacs_to_len16;
2081         union fw_vi_mac {
2082                 struct fw_vi_mac_exact {
2083                         __be16 valid_to_idx;
2084                         u8 macaddr[6];
2085                 } exact[7];
2086                 struct fw_vi_mac_hash {
2087                         __be64 hashvec;
2088                 } hash;
2089         } u;
2090 };
2091
2092 #define FW_VI_MAC_CMD_VIID_S    0
2093 #define FW_VI_MAC_CMD_VIID_V(x) ((x) << FW_VI_MAC_CMD_VIID_S)
2094
2095 #define FW_VI_MAC_CMD_FREEMACS_S        31
2096 #define FW_VI_MAC_CMD_FREEMACS_V(x)     ((x) << FW_VI_MAC_CMD_FREEMACS_S)
2097
2098 #define FW_VI_MAC_CMD_HASHVECEN_S       23
2099 #define FW_VI_MAC_CMD_HASHVECEN_V(x)    ((x) << FW_VI_MAC_CMD_HASHVECEN_S)
2100 #define FW_VI_MAC_CMD_HASHVECEN_F       FW_VI_MAC_CMD_HASHVECEN_V(1U)
2101
2102 #define FW_VI_MAC_CMD_HASHUNIEN_S       22
2103 #define FW_VI_MAC_CMD_HASHUNIEN_V(x)    ((x) << FW_VI_MAC_CMD_HASHUNIEN_S)
2104
2105 #define FW_VI_MAC_CMD_VALID_S           15
2106 #define FW_VI_MAC_CMD_VALID_V(x)        ((x) << FW_VI_MAC_CMD_VALID_S)
2107 #define FW_VI_MAC_CMD_VALID_F   FW_VI_MAC_CMD_VALID_V(1U)
2108
2109 #define FW_VI_MAC_CMD_PRIO_S    12
2110 #define FW_VI_MAC_CMD_PRIO_V(x) ((x) << FW_VI_MAC_CMD_PRIO_S)
2111
2112 #define FW_VI_MAC_CMD_SMAC_RESULT_S     10
2113 #define FW_VI_MAC_CMD_SMAC_RESULT_M     0x3
2114 #define FW_VI_MAC_CMD_SMAC_RESULT_V(x)  ((x) << FW_VI_MAC_CMD_SMAC_RESULT_S)
2115 #define FW_VI_MAC_CMD_SMAC_RESULT_G(x)  \
2116         (((x) >> FW_VI_MAC_CMD_SMAC_RESULT_S) & FW_VI_MAC_CMD_SMAC_RESULT_M)
2117
2118 #define FW_VI_MAC_CMD_IDX_S     0
2119 #define FW_VI_MAC_CMD_IDX_M     0x3ff
2120 #define FW_VI_MAC_CMD_IDX_V(x)  ((x) << FW_VI_MAC_CMD_IDX_S)
2121 #define FW_VI_MAC_CMD_IDX_G(x)  \
2122         (((x) >> FW_VI_MAC_CMD_IDX_S) & FW_VI_MAC_CMD_IDX_M)
2123
2124 #define FW_RXMODE_MTU_NO_CHG    65535
2125
2126 struct fw_vi_rxmode_cmd {
2127         __be32 op_to_viid;
2128         __be32 retval_len16;
2129         __be32 mtu_to_vlanexen;
2130         __be32 r4_lo;
2131 };
2132
2133 #define FW_VI_RXMODE_CMD_VIID_S         0
2134 #define FW_VI_RXMODE_CMD_VIID_V(x)      ((x) << FW_VI_RXMODE_CMD_VIID_S)
2135
2136 #define FW_VI_RXMODE_CMD_MTU_S          16
2137 #define FW_VI_RXMODE_CMD_MTU_M          0xffff
2138 #define FW_VI_RXMODE_CMD_MTU_V(x)       ((x) << FW_VI_RXMODE_CMD_MTU_S)
2139
2140 #define FW_VI_RXMODE_CMD_PROMISCEN_S    14
2141 #define FW_VI_RXMODE_CMD_PROMISCEN_M    0x3
2142 #define FW_VI_RXMODE_CMD_PROMISCEN_V(x) ((x) << FW_VI_RXMODE_CMD_PROMISCEN_S)
2143
2144 #define FW_VI_RXMODE_CMD_ALLMULTIEN_S           12
2145 #define FW_VI_RXMODE_CMD_ALLMULTIEN_M           0x3
2146 #define FW_VI_RXMODE_CMD_ALLMULTIEN_V(x)        \
2147         ((x) << FW_VI_RXMODE_CMD_ALLMULTIEN_S)
2148
2149 #define FW_VI_RXMODE_CMD_BROADCASTEN_S          10
2150 #define FW_VI_RXMODE_CMD_BROADCASTEN_M          0x3
2151 #define FW_VI_RXMODE_CMD_BROADCASTEN_V(x)       \
2152         ((x) << FW_VI_RXMODE_CMD_BROADCASTEN_S)
2153
2154 #define FW_VI_RXMODE_CMD_VLANEXEN_S     8
2155 #define FW_VI_RXMODE_CMD_VLANEXEN_M     0x3
2156 #define FW_VI_RXMODE_CMD_VLANEXEN_V(x)  ((x) << FW_VI_RXMODE_CMD_VLANEXEN_S)
2157
2158 struct fw_vi_enable_cmd {
2159         __be32 op_to_viid;
2160         __be32 ien_to_len16;
2161         __be16 blinkdur;
2162         __be16 r3;
2163         __be32 r4;
2164 };
2165
2166 #define FW_VI_ENABLE_CMD_VIID_S         0
2167 #define FW_VI_ENABLE_CMD_VIID_V(x)      ((x) << FW_VI_ENABLE_CMD_VIID_S)
2168
2169 #define FW_VI_ENABLE_CMD_IEN_S          31
2170 #define FW_VI_ENABLE_CMD_IEN_V(x)       ((x) << FW_VI_ENABLE_CMD_IEN_S)
2171
2172 #define FW_VI_ENABLE_CMD_EEN_S          30
2173 #define FW_VI_ENABLE_CMD_EEN_V(x)       ((x) << FW_VI_ENABLE_CMD_EEN_S)
2174
2175 #define FW_VI_ENABLE_CMD_LED_S          29
2176 #define FW_VI_ENABLE_CMD_LED_V(x)       ((x) << FW_VI_ENABLE_CMD_LED_S)
2177 #define FW_VI_ENABLE_CMD_LED_F  FW_VI_ENABLE_CMD_LED_V(1U)
2178
2179 #define FW_VI_ENABLE_CMD_DCB_INFO_S     28
2180 #define FW_VI_ENABLE_CMD_DCB_INFO_V(x)  ((x) << FW_VI_ENABLE_CMD_DCB_INFO_S)
2181
2182 /* VI VF stats offset definitions */
2183 #define VI_VF_NUM_STATS 16
2184 enum fw_vi_stats_vf_index {
2185         FW_VI_VF_STAT_TX_BCAST_BYTES_IX,
2186         FW_VI_VF_STAT_TX_BCAST_FRAMES_IX,
2187         FW_VI_VF_STAT_TX_MCAST_BYTES_IX,
2188         FW_VI_VF_STAT_TX_MCAST_FRAMES_IX,
2189         FW_VI_VF_STAT_TX_UCAST_BYTES_IX,
2190         FW_VI_VF_STAT_TX_UCAST_FRAMES_IX,
2191         FW_VI_VF_STAT_TX_DROP_FRAMES_IX,
2192         FW_VI_VF_STAT_TX_OFLD_BYTES_IX,
2193         FW_VI_VF_STAT_TX_OFLD_FRAMES_IX,
2194         FW_VI_VF_STAT_RX_BCAST_BYTES_IX,
2195         FW_VI_VF_STAT_RX_BCAST_FRAMES_IX,
2196         FW_VI_VF_STAT_RX_MCAST_BYTES_IX,
2197         FW_VI_VF_STAT_RX_MCAST_FRAMES_IX,
2198         FW_VI_VF_STAT_RX_UCAST_BYTES_IX,
2199         FW_VI_VF_STAT_RX_UCAST_FRAMES_IX,
2200         FW_VI_VF_STAT_RX_ERR_FRAMES_IX
2201 };
2202
2203 /* VI PF stats offset definitions */
2204 #define VI_PF_NUM_STATS 17
2205 enum fw_vi_stats_pf_index {
2206         FW_VI_PF_STAT_TX_BCAST_BYTES_IX,
2207         FW_VI_PF_STAT_TX_BCAST_FRAMES_IX,
2208         FW_VI_PF_STAT_TX_MCAST_BYTES_IX,
2209         FW_VI_PF_STAT_TX_MCAST_FRAMES_IX,
2210         FW_VI_PF_STAT_TX_UCAST_BYTES_IX,
2211         FW_VI_PF_STAT_TX_UCAST_FRAMES_IX,
2212         FW_VI_PF_STAT_TX_OFLD_BYTES_IX,
2213         FW_VI_PF_STAT_TX_OFLD_FRAMES_IX,
2214         FW_VI_PF_STAT_RX_BYTES_IX,
2215         FW_VI_PF_STAT_RX_FRAMES_IX,
2216         FW_VI_PF_STAT_RX_BCAST_BYTES_IX,
2217         FW_VI_PF_STAT_RX_BCAST_FRAMES_IX,
2218         FW_VI_PF_STAT_RX_MCAST_BYTES_IX,
2219         FW_VI_PF_STAT_RX_MCAST_FRAMES_IX,
2220         FW_VI_PF_STAT_RX_UCAST_BYTES_IX,
2221         FW_VI_PF_STAT_RX_UCAST_FRAMES_IX,
2222         FW_VI_PF_STAT_RX_ERR_FRAMES_IX
2223 };
2224
2225 struct fw_vi_stats_cmd {
2226         __be32 op_to_viid;
2227         __be32 retval_len16;
2228         union fw_vi_stats {
2229                 struct fw_vi_stats_ctl {
2230                         __be16 nstats_ix;
2231                         __be16 r6;
2232                         __be32 r7;
2233                         __be64 stat0;
2234                         __be64 stat1;
2235                         __be64 stat2;
2236                         __be64 stat3;
2237                         __be64 stat4;
2238                         __be64 stat5;
2239                 } ctl;
2240                 struct fw_vi_stats_pf {
2241                         __be64 tx_bcast_bytes;
2242                         __be64 tx_bcast_frames;
2243                         __be64 tx_mcast_bytes;
2244                         __be64 tx_mcast_frames;
2245                         __be64 tx_ucast_bytes;
2246                         __be64 tx_ucast_frames;
2247                         __be64 tx_offload_bytes;
2248                         __be64 tx_offload_frames;
2249                         __be64 rx_pf_bytes;
2250                         __be64 rx_pf_frames;
2251                         __be64 rx_bcast_bytes;
2252                         __be64 rx_bcast_frames;
2253                         __be64 rx_mcast_bytes;
2254                         __be64 rx_mcast_frames;
2255                         __be64 rx_ucast_bytes;
2256                         __be64 rx_ucast_frames;
2257                         __be64 rx_err_frames;
2258                 } pf;
2259                 struct fw_vi_stats_vf {
2260                         __be64 tx_bcast_bytes;
2261                         __be64 tx_bcast_frames;
2262                         __be64 tx_mcast_bytes;
2263                         __be64 tx_mcast_frames;
2264                         __be64 tx_ucast_bytes;
2265                         __be64 tx_ucast_frames;
2266                         __be64 tx_drop_frames;
2267                         __be64 tx_offload_bytes;
2268                         __be64 tx_offload_frames;
2269                         __be64 rx_bcast_bytes;
2270                         __be64 rx_bcast_frames;
2271                         __be64 rx_mcast_bytes;
2272                         __be64 rx_mcast_frames;
2273                         __be64 rx_ucast_bytes;
2274                         __be64 rx_ucast_frames;
2275                         __be64 rx_err_frames;
2276                 } vf;
2277         } u;
2278 };
2279
2280 #define FW_VI_STATS_CMD_VIID_S          0
2281 #define FW_VI_STATS_CMD_VIID_V(x)       ((x) << FW_VI_STATS_CMD_VIID_S)
2282
2283 #define FW_VI_STATS_CMD_NSTATS_S        12
2284 #define FW_VI_STATS_CMD_NSTATS_V(x)     ((x) << FW_VI_STATS_CMD_NSTATS_S)
2285
2286 #define FW_VI_STATS_CMD_IX_S    0
2287 #define FW_VI_STATS_CMD_IX_V(x) ((x) << FW_VI_STATS_CMD_IX_S)
2288
2289 struct fw_acl_mac_cmd {
2290         __be32 op_to_vfn;
2291         __be32 en_to_len16;
2292         u8 nmac;
2293         u8 r3[7];
2294         __be16 r4;
2295         u8 macaddr0[6];
2296         __be16 r5;
2297         u8 macaddr1[6];
2298         __be16 r6;
2299         u8 macaddr2[6];
2300         __be16 r7;
2301         u8 macaddr3[6];
2302 };
2303
2304 #define FW_ACL_MAC_CMD_PFN_S    8
2305 #define FW_ACL_MAC_CMD_PFN_V(x) ((x) << FW_ACL_MAC_CMD_PFN_S)
2306
2307 #define FW_ACL_MAC_CMD_VFN_S    0
2308 #define FW_ACL_MAC_CMD_VFN_V(x) ((x) << FW_ACL_MAC_CMD_VFN_S)
2309
2310 #define FW_ACL_MAC_CMD_EN_S     31
2311 #define FW_ACL_MAC_CMD_EN_V(x)  ((x) << FW_ACL_MAC_CMD_EN_S)
2312
2313 struct fw_acl_vlan_cmd {
2314         __be32 op_to_vfn;
2315         __be32 en_to_len16;
2316         u8 nvlan;
2317         u8 dropnovlan_fm;
2318         u8 r3_lo[6];
2319         __be16 vlanid[16];
2320 };
2321
2322 #define FW_ACL_VLAN_CMD_PFN_S           8
2323 #define FW_ACL_VLAN_CMD_PFN_V(x)        ((x) << FW_ACL_VLAN_CMD_PFN_S)
2324
2325 #define FW_ACL_VLAN_CMD_VFN_S           0
2326 #define FW_ACL_VLAN_CMD_VFN_V(x)        ((x) << FW_ACL_VLAN_CMD_VFN_S)
2327
2328 #define FW_ACL_VLAN_CMD_EN_S    31
2329 #define FW_ACL_VLAN_CMD_EN_V(x) ((x) << FW_ACL_VLAN_CMD_EN_S)
2330
2331 #define FW_ACL_VLAN_CMD_DROPNOVLAN_S    7
2332 #define FW_ACL_VLAN_CMD_DROPNOVLAN_V(x) ((x) << FW_ACL_VLAN_CMD_DROPNOVLAN_S)
2333
2334 #define FW_ACL_VLAN_CMD_FM_S    6
2335 #define FW_ACL_VLAN_CMD_FM_V(x) ((x) << FW_ACL_VLAN_CMD_FM_S)
2336
2337 /* old 16-bit port capabilities bitmap (fw_port_cap16_t) */
2338 enum fw_port_cap {
2339         FW_PORT_CAP_SPEED_100M          = 0x0001,
2340         FW_PORT_CAP_SPEED_1G            = 0x0002,
2341         FW_PORT_CAP_SPEED_25G           = 0x0004,
2342         FW_PORT_CAP_SPEED_10G           = 0x0008,
2343         FW_PORT_CAP_SPEED_40G           = 0x0010,
2344         FW_PORT_CAP_SPEED_100G          = 0x0020,
2345         FW_PORT_CAP_FC_RX               = 0x0040,
2346         FW_PORT_CAP_FC_TX               = 0x0080,
2347         FW_PORT_CAP_ANEG                = 0x0100,
2348         FW_PORT_CAP_MDIX                = 0x0200,
2349         FW_PORT_CAP_MDIAUTO             = 0x0400,
2350         FW_PORT_CAP_FEC_RS              = 0x0800,
2351         FW_PORT_CAP_FEC_BASER_RS        = 0x1000,
2352         FW_PORT_CAP_FEC_RESERVED        = 0x2000,
2353         FW_PORT_CAP_802_3_PAUSE         = 0x4000,
2354         FW_PORT_CAP_802_3_ASM_DIR       = 0x8000,
2355 };
2356
2357 #define FW_PORT_CAP_SPEED_S     0
2358 #define FW_PORT_CAP_SPEED_M     0x3f
2359 #define FW_PORT_CAP_SPEED_V(x)  ((x) << FW_PORT_CAP_SPEED_S)
2360 #define FW_PORT_CAP_SPEED_G(x) \
2361         (((x) >> FW_PORT_CAP_SPEED_S) & FW_PORT_CAP_SPEED_M)
2362
2363 enum fw_port_mdi {
2364         FW_PORT_CAP_MDI_UNCHANGED,
2365         FW_PORT_CAP_MDI_AUTO,
2366         FW_PORT_CAP_MDI_F_STRAIGHT,
2367         FW_PORT_CAP_MDI_F_CROSSOVER
2368 };
2369
2370 #define FW_PORT_CAP_MDI_S 9
2371 #define FW_PORT_CAP_MDI_V(x) ((x) << FW_PORT_CAP_MDI_S)
2372
2373 /* new 32-bit port capabilities bitmap (fw_port_cap32_t) */
2374 #define FW_PORT_CAP32_SPEED_100M        0x00000001UL
2375 #define FW_PORT_CAP32_SPEED_1G          0x00000002UL
2376 #define FW_PORT_CAP32_SPEED_10G         0x00000004UL
2377 #define FW_PORT_CAP32_SPEED_25G         0x00000008UL
2378 #define FW_PORT_CAP32_SPEED_40G         0x00000010UL
2379 #define FW_PORT_CAP32_SPEED_50G         0x00000020UL
2380 #define FW_PORT_CAP32_SPEED_100G        0x00000040UL
2381 #define FW_PORT_CAP32_SPEED_200G        0x00000080UL
2382 #define FW_PORT_CAP32_SPEED_400G        0x00000100UL
2383 #define FW_PORT_CAP32_SPEED_RESERVED1   0x00000200UL
2384 #define FW_PORT_CAP32_SPEED_RESERVED2   0x00000400UL
2385 #define FW_PORT_CAP32_SPEED_RESERVED3   0x00000800UL
2386 #define FW_PORT_CAP32_RESERVED1         0x0000f000UL
2387 #define FW_PORT_CAP32_FC_RX             0x00010000UL
2388 #define FW_PORT_CAP32_FC_TX             0x00020000UL
2389 #define FW_PORT_CAP32_802_3_PAUSE       0x00040000UL
2390 #define FW_PORT_CAP32_802_3_ASM_DIR     0x00080000UL
2391 #define FW_PORT_CAP32_ANEG              0x00100000UL
2392 #define FW_PORT_CAP32_MDIX              0x00200000UL
2393 #define FW_PORT_CAP32_MDIAUTO           0x00400000UL
2394 #define FW_PORT_CAP32_FEC_RS            0x00800000UL
2395 #define FW_PORT_CAP32_FEC_BASER_RS      0x01000000UL
2396 #define FW_PORT_CAP32_FEC_RESERVED1     0x02000000UL
2397 #define FW_PORT_CAP32_FEC_RESERVED2     0x04000000UL
2398 #define FW_PORT_CAP32_FEC_RESERVED3     0x08000000UL
2399 #define FW_PORT_CAP32_RESERVED2         0xf0000000UL
2400
2401 #define FW_PORT_CAP32_SPEED_S   0
2402 #define FW_PORT_CAP32_SPEED_M   0xfff
2403 #define FW_PORT_CAP32_SPEED_V(x)        ((x) << FW_PORT_CAP32_SPEED_S)
2404 #define FW_PORT_CAP32_SPEED_G(x) \
2405         (((x) >> FW_PORT_CAP32_SPEED_S) & FW_PORT_CAP32_SPEED_M)
2406
2407 #define FW_PORT_CAP32_FC_S      16
2408 #define FW_PORT_CAP32_FC_M      0x3
2409 #define FW_PORT_CAP32_FC_V(x)   ((x) << FW_PORT_CAP32_FC_S)
2410 #define FW_PORT_CAP32_FC_G(x) \
2411         (((x) >> FW_PORT_CAP32_FC_S) & FW_PORT_CAP32_FC_M)
2412
2413 #define FW_PORT_CAP32_802_3_S   18
2414 #define FW_PORT_CAP32_802_3_M   0x3
2415 #define FW_PORT_CAP32_802_3_V(x)        ((x) << FW_PORT_CAP32_802_3_S)
2416 #define FW_PORT_CAP32_802_3_G(x) \
2417         (((x) >> FW_PORT_CAP32_802_3_S) & FW_PORT_CAP32_802_3_M)
2418
2419 #define FW_PORT_CAP32_ANEG_S    20
2420 #define FW_PORT_CAP32_ANEG_M    0x1
2421 #define FW_PORT_CAP32_ANEG_V(x) ((x) << FW_PORT_CAP32_ANEG_S)
2422 #define FW_PORT_CAP32_ANEG_G(x) \
2423         (((x) >> FW_PORT_CAP32_ANEG_S) & FW_PORT_CAP32_ANEG_M)
2424
2425 enum fw_port_mdi32 {
2426         FW_PORT_CAP32_MDI_UNCHANGED,
2427         FW_PORT_CAP32_MDI_AUTO,
2428         FW_PORT_CAP32_MDI_F_STRAIGHT,
2429         FW_PORT_CAP32_MDI_F_CROSSOVER
2430 };
2431
2432 #define FW_PORT_CAP32_MDI_S 21
2433 #define FW_PORT_CAP32_MDI_M 3
2434 #define FW_PORT_CAP32_MDI_V(x) ((x) << FW_PORT_CAP32_MDI_S)
2435 #define FW_PORT_CAP32_MDI_G(x) \
2436         (((x) >> FW_PORT_CAP32_MDI_S) & FW_PORT_CAP32_MDI_M)
2437
2438 #define FW_PORT_CAP32_FEC_S     23
2439 #define FW_PORT_CAP32_FEC_M     0x1f
2440 #define FW_PORT_CAP32_FEC_V(x)  ((x) << FW_PORT_CAP32_FEC_S)
2441 #define FW_PORT_CAP32_FEC_G(x) \
2442         (((x) >> FW_PORT_CAP32_FEC_S) & FW_PORT_CAP32_FEC_M)
2443
2444 /* macros to isolate various 32-bit Port Capabilities sub-fields */
2445 #define CAP32_SPEED(__cap32) \
2446         (FW_PORT_CAP32_SPEED_V(FW_PORT_CAP32_SPEED_M) & __cap32)
2447
2448 #define CAP32_FEC(__cap32) \
2449         (FW_PORT_CAP32_FEC_V(FW_PORT_CAP32_FEC_M) & __cap32)
2450
2451 enum fw_port_action {
2452         FW_PORT_ACTION_L1_CFG           = 0x0001,
2453         FW_PORT_ACTION_L2_CFG           = 0x0002,
2454         FW_PORT_ACTION_GET_PORT_INFO    = 0x0003,
2455         FW_PORT_ACTION_L2_PPP_CFG       = 0x0004,
2456         FW_PORT_ACTION_L2_DCB_CFG       = 0x0005,
2457         FW_PORT_ACTION_DCB_READ_TRANS   = 0x0006,
2458         FW_PORT_ACTION_DCB_READ_RECV    = 0x0007,
2459         FW_PORT_ACTION_DCB_READ_DET     = 0x0008,
2460         FW_PORT_ACTION_L1_CFG32         = 0x0009,
2461         FW_PORT_ACTION_GET_PORT_INFO32  = 0x000a,
2462         FW_PORT_ACTION_LOW_PWR_TO_NORMAL = 0x0010,
2463         FW_PORT_ACTION_L1_LOW_PWR_EN    = 0x0011,
2464         FW_PORT_ACTION_L2_WOL_MODE_EN   = 0x0012,
2465         FW_PORT_ACTION_LPBK_TO_NORMAL   = 0x0020,
2466         FW_PORT_ACTION_L1_LPBK          = 0x0021,
2467         FW_PORT_ACTION_L1_PMA_LPBK      = 0x0022,
2468         FW_PORT_ACTION_L1_PCS_LPBK      = 0x0023,
2469         FW_PORT_ACTION_L1_PHYXS_CSIDE_LPBK = 0x0024,
2470         FW_PORT_ACTION_L1_PHYXS_ESIDE_LPBK = 0x0025,
2471         FW_PORT_ACTION_PHY_RESET        = 0x0040,
2472         FW_PORT_ACTION_PMA_RESET        = 0x0041,
2473         FW_PORT_ACTION_PCS_RESET        = 0x0042,
2474         FW_PORT_ACTION_PHYXS_RESET      = 0x0043,
2475         FW_PORT_ACTION_DTEXS_REEST      = 0x0044,
2476         FW_PORT_ACTION_AN_RESET         = 0x0045
2477 };
2478
2479 enum fw_port_l2cfg_ctlbf {
2480         FW_PORT_L2_CTLBF_OVLAN0 = 0x01,
2481         FW_PORT_L2_CTLBF_OVLAN1 = 0x02,
2482         FW_PORT_L2_CTLBF_OVLAN2 = 0x04,
2483         FW_PORT_L2_CTLBF_OVLAN3 = 0x08,
2484         FW_PORT_L2_CTLBF_IVLAN  = 0x10,
2485         FW_PORT_L2_CTLBF_TXIPG  = 0x20
2486 };
2487
2488 enum fw_port_dcb_versions {
2489         FW_PORT_DCB_VER_UNKNOWN,
2490         FW_PORT_DCB_VER_CEE1D0,
2491         FW_PORT_DCB_VER_CEE1D01,
2492         FW_PORT_DCB_VER_IEEE,
2493         FW_PORT_DCB_VER_AUTO = 7
2494 };
2495
2496 enum fw_port_dcb_cfg {
2497         FW_PORT_DCB_CFG_PG      = 0x01,
2498         FW_PORT_DCB_CFG_PFC     = 0x02,
2499         FW_PORT_DCB_CFG_APPL    = 0x04
2500 };
2501
2502 enum fw_port_dcb_cfg_rc {
2503         FW_PORT_DCB_CFG_SUCCESS = 0x0,
2504         FW_PORT_DCB_CFG_ERROR   = 0x1
2505 };
2506
2507 enum fw_port_dcb_type {
2508         FW_PORT_DCB_TYPE_PGID           = 0x00,
2509         FW_PORT_DCB_TYPE_PGRATE         = 0x01,
2510         FW_PORT_DCB_TYPE_PRIORATE       = 0x02,
2511         FW_PORT_DCB_TYPE_PFC            = 0x03,
2512         FW_PORT_DCB_TYPE_APP_ID         = 0x04,
2513         FW_PORT_DCB_TYPE_CONTROL        = 0x05,
2514 };
2515
2516 enum fw_port_dcb_feature_state {
2517         FW_PORT_DCB_FEATURE_STATE_PENDING = 0x0,
2518         FW_PORT_DCB_FEATURE_STATE_SUCCESS = 0x1,
2519         FW_PORT_DCB_FEATURE_STATE_ERROR = 0x2,
2520         FW_PORT_DCB_FEATURE_STATE_TIMEOUT = 0x3,
2521 };
2522
2523 struct fw_port_cmd {
2524         __be32 op_to_portid;
2525         __be32 action_to_len16;
2526         union fw_port {
2527                 struct fw_port_l1cfg {
2528                         __be32 rcap;
2529                         __be32 r;
2530                 } l1cfg;
2531                 struct fw_port_l2cfg {
2532                         __u8   ctlbf;
2533                         __u8   ovlan3_to_ivlan0;
2534                         __be16 ivlantype;
2535                         __be16 txipg_force_pinfo;
2536                         __be16 mtu;
2537                         __be16 ovlan0mask;
2538                         __be16 ovlan0type;
2539                         __be16 ovlan1mask;
2540                         __be16 ovlan1type;
2541                         __be16 ovlan2mask;
2542                         __be16 ovlan2type;
2543                         __be16 ovlan3mask;
2544                         __be16 ovlan3type;
2545                 } l2cfg;
2546                 struct fw_port_info {
2547                         __be32 lstatus_to_modtype;
2548                         __be16 pcap;
2549                         __be16 acap;
2550                         __be16 mtu;
2551                         __u8   cbllen;
2552                         __u8   auxlinfo;
2553                         __u8   dcbxdis_pkd;
2554                         __u8   r8_lo;
2555                         __be16 lpacap;
2556                         __be64 r9;
2557                 } info;
2558                 struct fw_port_diags {
2559                         __u8   diagop;
2560                         __u8   r[3];
2561                         __be32 diagval;
2562                 } diags;
2563                 union fw_port_dcb {
2564                         struct fw_port_dcb_pgid {
2565                                 __u8   type;
2566                                 __u8   apply_pkd;
2567                                 __u8   r10_lo[2];
2568                                 __be32 pgid;
2569                                 __be64 r11;
2570                         } pgid;
2571                         struct fw_port_dcb_pgrate {
2572                                 __u8   type;
2573                                 __u8   apply_pkd;
2574                                 __u8   r10_lo[5];
2575                                 __u8   num_tcs_supported;
2576                                 __u8   pgrate[8];
2577                                 __u8   tsa[8];
2578                         } pgrate;
2579                         struct fw_port_dcb_priorate {
2580                                 __u8   type;
2581                                 __u8   apply_pkd;
2582                                 __u8   r10_lo[6];
2583                                 __u8   strict_priorate[8];
2584                         } priorate;
2585                         struct fw_port_dcb_pfc {
2586                                 __u8   type;
2587                                 __u8   pfcen;
2588                                 __u8   r10[5];
2589                                 __u8   max_pfc_tcs;
2590                                 __be64 r11;
2591                         } pfc;
2592                         struct fw_port_app_priority {
2593                                 __u8   type;
2594                                 __u8   r10[2];
2595                                 __u8   idx;
2596                                 __u8   user_prio_map;
2597                                 __u8   sel_field;
2598                                 __be16 protocolid;
2599                                 __be64 r12;
2600                         } app_priority;
2601                         struct fw_port_dcb_control {
2602                                 __u8   type;
2603                                 __u8   all_syncd_pkd;
2604                                 __be16 dcb_version_to_app_state;
2605                                 __be32 r11;
2606                                 __be64 r12;
2607                         } control;
2608                 } dcb;
2609                 struct fw_port_l1cfg32 {
2610                         __be32 rcap32;
2611                         __be32 r;
2612                 } l1cfg32;
2613                 struct fw_port_info32 {
2614                         __be32 lstatus32_to_cbllen32;
2615                         __be32 auxlinfo32_mtu32;
2616                         __be32 linkattr32;
2617                         __be32 pcaps32;
2618                         __be32 acaps32;
2619                         __be32 lpacaps32;
2620                 } info32;
2621         } u;
2622 };
2623
2624 #define FW_PORT_CMD_READ_S      22
2625 #define FW_PORT_CMD_READ_V(x)   ((x) << FW_PORT_CMD_READ_S)
2626 #define FW_PORT_CMD_READ_F      FW_PORT_CMD_READ_V(1U)
2627
2628 #define FW_PORT_CMD_PORTID_S    0
2629 #define FW_PORT_CMD_PORTID_M    0xf
2630 #define FW_PORT_CMD_PORTID_V(x) ((x) << FW_PORT_CMD_PORTID_S)
2631 #define FW_PORT_CMD_PORTID_G(x) \
2632         (((x) >> FW_PORT_CMD_PORTID_S) & FW_PORT_CMD_PORTID_M)
2633
2634 #define FW_PORT_CMD_ACTION_S    16
2635 #define FW_PORT_CMD_ACTION_M    0xffff
2636 #define FW_PORT_CMD_ACTION_V(x) ((x) << FW_PORT_CMD_ACTION_S)
2637 #define FW_PORT_CMD_ACTION_G(x) \
2638         (((x) >> FW_PORT_CMD_ACTION_S) & FW_PORT_CMD_ACTION_M)
2639
2640 #define FW_PORT_CMD_OVLAN3_S    7
2641 #define FW_PORT_CMD_OVLAN3_V(x) ((x) << FW_PORT_CMD_OVLAN3_S)
2642
2643 #define FW_PORT_CMD_OVLAN2_S    6
2644 #define FW_PORT_CMD_OVLAN2_V(x) ((x) << FW_PORT_CMD_OVLAN2_S)
2645
2646 #define FW_PORT_CMD_OVLAN1_S    5
2647 #define FW_PORT_CMD_OVLAN1_V(x) ((x) << FW_PORT_CMD_OVLAN1_S)
2648
2649 #define FW_PORT_CMD_OVLAN0_S    4
2650 #define FW_PORT_CMD_OVLAN0_V(x) ((x) << FW_PORT_CMD_OVLAN0_S)
2651
2652 #define FW_PORT_CMD_IVLAN0_S    3
2653 #define FW_PORT_CMD_IVLAN0_V(x) ((x) << FW_PORT_CMD_IVLAN0_S)
2654
2655 #define FW_PORT_CMD_TXIPG_S     3
2656 #define FW_PORT_CMD_TXIPG_V(x)  ((x) << FW_PORT_CMD_TXIPG_S)
2657
2658 #define FW_PORT_CMD_LSTATUS_S           31
2659 #define FW_PORT_CMD_LSTATUS_M           0x1
2660 #define FW_PORT_CMD_LSTATUS_V(x)        ((x) << FW_PORT_CMD_LSTATUS_S)
2661 #define FW_PORT_CMD_LSTATUS_G(x)        \
2662         (((x) >> FW_PORT_CMD_LSTATUS_S) & FW_PORT_CMD_LSTATUS_M)
2663 #define FW_PORT_CMD_LSTATUS_F   FW_PORT_CMD_LSTATUS_V(1U)
2664
2665 #define FW_PORT_CMD_LSPEED_S    24
2666 #define FW_PORT_CMD_LSPEED_M    0x3f
2667 #define FW_PORT_CMD_LSPEED_V(x) ((x) << FW_PORT_CMD_LSPEED_S)
2668 #define FW_PORT_CMD_LSPEED_G(x) \
2669         (((x) >> FW_PORT_CMD_LSPEED_S) & FW_PORT_CMD_LSPEED_M)
2670
2671 #define FW_PORT_CMD_TXPAUSE_S           23
2672 #define FW_PORT_CMD_TXPAUSE_V(x)        ((x) << FW_PORT_CMD_TXPAUSE_S)
2673 #define FW_PORT_CMD_TXPAUSE_F   FW_PORT_CMD_TXPAUSE_V(1U)
2674
2675 #define FW_PORT_CMD_RXPAUSE_S           22
2676 #define FW_PORT_CMD_RXPAUSE_V(x)        ((x) << FW_PORT_CMD_RXPAUSE_S)
2677 #define FW_PORT_CMD_RXPAUSE_F   FW_PORT_CMD_RXPAUSE_V(1U)
2678
2679 #define FW_PORT_CMD_MDIOCAP_S           21
2680 #define FW_PORT_CMD_MDIOCAP_V(x)        ((x) << FW_PORT_CMD_MDIOCAP_S)
2681 #define FW_PORT_CMD_MDIOCAP_F   FW_PORT_CMD_MDIOCAP_V(1U)
2682
2683 #define FW_PORT_CMD_MDIOADDR_S          16
2684 #define FW_PORT_CMD_MDIOADDR_M          0x1f
2685 #define FW_PORT_CMD_MDIOADDR_G(x)       \
2686         (((x) >> FW_PORT_CMD_MDIOADDR_S) & FW_PORT_CMD_MDIOADDR_M)
2687
2688 #define FW_PORT_CMD_LPTXPAUSE_S         15
2689 #define FW_PORT_CMD_LPTXPAUSE_V(x)      ((x) << FW_PORT_CMD_LPTXPAUSE_S)
2690 #define FW_PORT_CMD_LPTXPAUSE_F FW_PORT_CMD_LPTXPAUSE_V(1U)
2691
2692 #define FW_PORT_CMD_LPRXPAUSE_S         14
2693 #define FW_PORT_CMD_LPRXPAUSE_V(x)      ((x) << FW_PORT_CMD_LPRXPAUSE_S)
2694 #define FW_PORT_CMD_LPRXPAUSE_F FW_PORT_CMD_LPRXPAUSE_V(1U)
2695
2696 #define FW_PORT_CMD_PTYPE_S     8
2697 #define FW_PORT_CMD_PTYPE_M     0x1f
2698 #define FW_PORT_CMD_PTYPE_G(x)  \
2699         (((x) >> FW_PORT_CMD_PTYPE_S) & FW_PORT_CMD_PTYPE_M)
2700
2701 #define FW_PORT_CMD_LINKDNRC_S          5
2702 #define FW_PORT_CMD_LINKDNRC_M          0x7
2703 #define FW_PORT_CMD_LINKDNRC_G(x)       \
2704         (((x) >> FW_PORT_CMD_LINKDNRC_S) & FW_PORT_CMD_LINKDNRC_M)
2705
2706 #define FW_PORT_CMD_MODTYPE_S           0
2707 #define FW_PORT_CMD_MODTYPE_M           0x1f
2708 #define FW_PORT_CMD_MODTYPE_V(x)        ((x) << FW_PORT_CMD_MODTYPE_S)
2709 #define FW_PORT_CMD_MODTYPE_G(x)        \
2710         (((x) >> FW_PORT_CMD_MODTYPE_S) & FW_PORT_CMD_MODTYPE_M)
2711
2712 #define FW_PORT_CMD_DCBXDIS_S           7
2713 #define FW_PORT_CMD_DCBXDIS_V(x)        ((x) << FW_PORT_CMD_DCBXDIS_S)
2714 #define FW_PORT_CMD_DCBXDIS_F   FW_PORT_CMD_DCBXDIS_V(1U)
2715
2716 #define FW_PORT_CMD_APPLY_S     7
2717 #define FW_PORT_CMD_APPLY_V(x)  ((x) << FW_PORT_CMD_APPLY_S)
2718 #define FW_PORT_CMD_APPLY_F     FW_PORT_CMD_APPLY_V(1U)
2719
2720 #define FW_PORT_CMD_ALL_SYNCD_S         7
2721 #define FW_PORT_CMD_ALL_SYNCD_V(x)      ((x) << FW_PORT_CMD_ALL_SYNCD_S)
2722 #define FW_PORT_CMD_ALL_SYNCD_F FW_PORT_CMD_ALL_SYNCD_V(1U)
2723
2724 #define FW_PORT_CMD_DCB_VERSION_S       12
2725 #define FW_PORT_CMD_DCB_VERSION_M       0x7
2726 #define FW_PORT_CMD_DCB_VERSION_G(x)    \
2727         (((x) >> FW_PORT_CMD_DCB_VERSION_S) & FW_PORT_CMD_DCB_VERSION_M)
2728
2729 #define FW_PORT_CMD_LSTATUS32_S         31
2730 #define FW_PORT_CMD_LSTATUS32_M         0x1
2731 #define FW_PORT_CMD_LSTATUS32_V(x)      ((x) << FW_PORT_CMD_LSTATUS32_S)
2732 #define FW_PORT_CMD_LSTATUS32_G(x)      \
2733         (((x) >> FW_PORT_CMD_LSTATUS32_S) & FW_PORT_CMD_LSTATUS32_M)
2734 #define FW_PORT_CMD_LSTATUS32_F FW_PORT_CMD_LSTATUS32_V(1U)
2735
2736 #define FW_PORT_CMD_LINKDNRC32_S        28
2737 #define FW_PORT_CMD_LINKDNRC32_M        0x7
2738 #define FW_PORT_CMD_LINKDNRC32_V(x)     ((x) << FW_PORT_CMD_LINKDNRC32_S)
2739 #define FW_PORT_CMD_LINKDNRC32_G(x)     \
2740         (((x) >> FW_PORT_CMD_LINKDNRC32_S) & FW_PORT_CMD_LINKDNRC32_M)
2741
2742 #define FW_PORT_CMD_DCBXDIS32_S         27
2743 #define FW_PORT_CMD_DCBXDIS32_M         0x1
2744 #define FW_PORT_CMD_DCBXDIS32_V(x)      ((x) << FW_PORT_CMD_DCBXDIS32_S)
2745 #define FW_PORT_CMD_DCBXDIS32_G(x)      \
2746         (((x) >> FW_PORT_CMD_DCBXDIS32_S) & FW_PORT_CMD_DCBXDIS32_M)
2747 #define FW_PORT_CMD_DCBXDIS32_F FW_PORT_CMD_DCBXDIS32_V(1U)
2748
2749 #define FW_PORT_CMD_MDIOCAP32_S         26
2750 #define FW_PORT_CMD_MDIOCAP32_M         0x1
2751 #define FW_PORT_CMD_MDIOCAP32_V(x)      ((x) << FW_PORT_CMD_MDIOCAP32_S)
2752 #define FW_PORT_CMD_MDIOCAP32_G(x)      \
2753         (((x) >> FW_PORT_CMD_MDIOCAP32_S) & FW_PORT_CMD_MDIOCAP32_M)
2754 #define FW_PORT_CMD_MDIOCAP32_F FW_PORT_CMD_MDIOCAP32_V(1U)
2755
2756 #define FW_PORT_CMD_MDIOADDR32_S        21
2757 #define FW_PORT_CMD_MDIOADDR32_M        0x1f
2758 #define FW_PORT_CMD_MDIOADDR32_V(x)     ((x) << FW_PORT_CMD_MDIOADDR32_S)
2759 #define FW_PORT_CMD_MDIOADDR32_G(x)     \
2760         (((x) >> FW_PORT_CMD_MDIOADDR32_S) & FW_PORT_CMD_MDIOADDR32_M)
2761
2762 #define FW_PORT_CMD_PORTTYPE32_S        13
2763 #define FW_PORT_CMD_PORTTYPE32_M        0xff
2764 #define FW_PORT_CMD_PORTTYPE32_V(x)     ((x) << FW_PORT_CMD_PORTTYPE32_S)
2765 #define FW_PORT_CMD_PORTTYPE32_G(x)     \
2766         (((x) >> FW_PORT_CMD_PORTTYPE32_S) & FW_PORT_CMD_PORTTYPE32_M)
2767
2768 #define FW_PORT_CMD_MODTYPE32_S         8
2769 #define FW_PORT_CMD_MODTYPE32_M         0x1f
2770 #define FW_PORT_CMD_MODTYPE32_V(x)      ((x) << FW_PORT_CMD_MODTYPE32_S)
2771 #define FW_PORT_CMD_MODTYPE32_G(x)      \
2772         (((x) >> FW_PORT_CMD_MODTYPE32_S) & FW_PORT_CMD_MODTYPE32_M)
2773
2774 #define FW_PORT_CMD_CBLLEN32_S          0
2775 #define FW_PORT_CMD_CBLLEN32_M          0xff
2776 #define FW_PORT_CMD_CBLLEN32_V(x)       ((x) << FW_PORT_CMD_CBLLEN32_S)
2777 #define FW_PORT_CMD_CBLLEN32_G(x)       \
2778         (((x) >> FW_PORT_CMD_CBLLEN32_S) & FW_PORT_CMD_CBLLEN32_M)
2779
2780 #define FW_PORT_CMD_AUXLINFO32_S        24
2781 #define FW_PORT_CMD_AUXLINFO32_M        0xff
2782 #define FW_PORT_CMD_AUXLINFO32_V(x)     ((x) << FW_PORT_CMD_AUXLINFO32_S)
2783 #define FW_PORT_CMD_AUXLINFO32_G(x)     \
2784         (((x) >> FW_PORT_CMD_AUXLINFO32_S) & FW_PORT_CMD_AUXLINFO32_M)
2785
2786 #define FW_PORT_AUXLINFO32_KX4_S        2
2787 #define FW_PORT_AUXLINFO32_KX4_M        0x1
2788 #define FW_PORT_AUXLINFO32_KX4_V(x) \
2789         ((x) << FW_PORT_AUXLINFO32_KX4_S)
2790 #define FW_PORT_AUXLINFO32_KX4_G(x) \
2791         (((x) >> FW_PORT_AUXLINFO32_KX4_S) & FW_PORT_AUXLINFO32_KX4_M)
2792 #define FW_PORT_AUXLINFO32_KX4_F        FW_PORT_AUXLINFO32_KX4_V(1U)
2793
2794 #define FW_PORT_AUXLINFO32_KR_S 1
2795 #define FW_PORT_AUXLINFO32_KR_M 0x1
2796 #define FW_PORT_AUXLINFO32_KR_V(x) \
2797         ((x) << FW_PORT_AUXLINFO32_KR_S)
2798 #define FW_PORT_AUXLINFO32_KR_G(x) \
2799         (((x) >> FW_PORT_AUXLINFO32_KR_S) & FW_PORT_AUXLINFO32_KR_M)
2800 #define FW_PORT_AUXLINFO32_KR_F FW_PORT_AUXLINFO32_KR_V(1U)
2801
2802 #define FW_PORT_CMD_MTU32_S     0
2803 #define FW_PORT_CMD_MTU32_M     0xffff
2804 #define FW_PORT_CMD_MTU32_V(x)  ((x) << FW_PORT_CMD_MTU32_S)
2805 #define FW_PORT_CMD_MTU32_G(x)  \
2806         (((x) >> FW_PORT_CMD_MTU32_S) & FW_PORT_CMD_MTU32_M)
2807
2808 enum fw_port_type {
2809         FW_PORT_TYPE_FIBER_XFI,
2810         FW_PORT_TYPE_FIBER_XAUI,
2811         FW_PORT_TYPE_BT_SGMII,
2812         FW_PORT_TYPE_BT_XFI,
2813         FW_PORT_TYPE_BT_XAUI,
2814         FW_PORT_TYPE_KX4,
2815         FW_PORT_TYPE_CX4,
2816         FW_PORT_TYPE_KX,
2817         FW_PORT_TYPE_KR,
2818         FW_PORT_TYPE_SFP,
2819         FW_PORT_TYPE_BP_AP,
2820         FW_PORT_TYPE_BP4_AP,
2821         FW_PORT_TYPE_QSFP_10G,
2822         FW_PORT_TYPE_QSA,
2823         FW_PORT_TYPE_QSFP,
2824         FW_PORT_TYPE_BP40_BA,
2825         FW_PORT_TYPE_KR4_100G,
2826         FW_PORT_TYPE_CR4_QSFP,
2827         FW_PORT_TYPE_CR_QSFP,
2828         FW_PORT_TYPE_CR2_QSFP,
2829         FW_PORT_TYPE_SFP28,
2830         FW_PORT_TYPE_KR_SFP28,
2831
2832         FW_PORT_TYPE_NONE = FW_PORT_CMD_PTYPE_M
2833 };
2834
2835 enum fw_port_module_type {
2836         FW_PORT_MOD_TYPE_NA,
2837         FW_PORT_MOD_TYPE_LR,
2838         FW_PORT_MOD_TYPE_SR,
2839         FW_PORT_MOD_TYPE_ER,
2840         FW_PORT_MOD_TYPE_TWINAX_PASSIVE,
2841         FW_PORT_MOD_TYPE_TWINAX_ACTIVE,
2842         FW_PORT_MOD_TYPE_LRM,
2843         FW_PORT_MOD_TYPE_ERROR          = FW_PORT_CMD_MODTYPE_M - 3,
2844         FW_PORT_MOD_TYPE_UNKNOWN        = FW_PORT_CMD_MODTYPE_M - 2,
2845         FW_PORT_MOD_TYPE_NOTSUPPORTED   = FW_PORT_CMD_MODTYPE_M - 1,
2846
2847         FW_PORT_MOD_TYPE_NONE = FW_PORT_CMD_MODTYPE_M
2848 };
2849
2850 enum fw_port_mod_sub_type {
2851         FW_PORT_MOD_SUB_TYPE_NA,
2852         FW_PORT_MOD_SUB_TYPE_MV88E114X = 0x1,
2853         FW_PORT_MOD_SUB_TYPE_TN8022 = 0x2,
2854         FW_PORT_MOD_SUB_TYPE_AQ1202 = 0x3,
2855         FW_PORT_MOD_SUB_TYPE_88x3120 = 0x4,
2856         FW_PORT_MOD_SUB_TYPE_BCM84834 = 0x5,
2857         FW_PORT_MOD_SUB_TYPE_BT_VSC8634 = 0x8,
2858
2859         /* The following will never been in the VPD.  They are TWINAX cable
2860          * lengths decoded from SFP+ module i2c PROMs.  These should
2861          * almost certainly go somewhere else ...
2862          */
2863         FW_PORT_MOD_SUB_TYPE_TWINAX_1 = 0x9,
2864         FW_PORT_MOD_SUB_TYPE_TWINAX_3 = 0xA,
2865         FW_PORT_MOD_SUB_TYPE_TWINAX_5 = 0xB,
2866         FW_PORT_MOD_SUB_TYPE_TWINAX_7 = 0xC,
2867 };
2868
2869 enum fw_port_stats_tx_index {
2870         FW_STAT_TX_PORT_BYTES_IX = 0,
2871         FW_STAT_TX_PORT_FRAMES_IX,
2872         FW_STAT_TX_PORT_BCAST_IX,
2873         FW_STAT_TX_PORT_MCAST_IX,
2874         FW_STAT_TX_PORT_UCAST_IX,
2875         FW_STAT_TX_PORT_ERROR_IX,
2876         FW_STAT_TX_PORT_64B_IX,
2877         FW_STAT_TX_PORT_65B_127B_IX,
2878         FW_STAT_TX_PORT_128B_255B_IX,
2879         FW_STAT_TX_PORT_256B_511B_IX,
2880         FW_STAT_TX_PORT_512B_1023B_IX,
2881         FW_STAT_TX_PORT_1024B_1518B_IX,
2882         FW_STAT_TX_PORT_1519B_MAX_IX,
2883         FW_STAT_TX_PORT_DROP_IX,
2884         FW_STAT_TX_PORT_PAUSE_IX,
2885         FW_STAT_TX_PORT_PPP0_IX,
2886         FW_STAT_TX_PORT_PPP1_IX,
2887         FW_STAT_TX_PORT_PPP2_IX,
2888         FW_STAT_TX_PORT_PPP3_IX,
2889         FW_STAT_TX_PORT_PPP4_IX,
2890         FW_STAT_TX_PORT_PPP5_IX,
2891         FW_STAT_TX_PORT_PPP6_IX,
2892         FW_STAT_TX_PORT_PPP7_IX,
2893         FW_NUM_PORT_TX_STATS
2894 };
2895
2896 enum fw_port_stat_rx_index {
2897         FW_STAT_RX_PORT_BYTES_IX = 0,
2898         FW_STAT_RX_PORT_FRAMES_IX,
2899         FW_STAT_RX_PORT_BCAST_IX,
2900         FW_STAT_RX_PORT_MCAST_IX,
2901         FW_STAT_RX_PORT_UCAST_IX,
2902         FW_STAT_RX_PORT_MTU_ERROR_IX,
2903         FW_STAT_RX_PORT_MTU_CRC_ERROR_IX,
2904         FW_STAT_RX_PORT_CRC_ERROR_IX,
2905         FW_STAT_RX_PORT_LEN_ERROR_IX,
2906         FW_STAT_RX_PORT_SYM_ERROR_IX,
2907         FW_STAT_RX_PORT_64B_IX,
2908         FW_STAT_RX_PORT_65B_127B_IX,
2909         FW_STAT_RX_PORT_128B_255B_IX,
2910         FW_STAT_RX_PORT_256B_511B_IX,
2911         FW_STAT_RX_PORT_512B_1023B_IX,
2912         FW_STAT_RX_PORT_1024B_1518B_IX,
2913         FW_STAT_RX_PORT_1519B_MAX_IX,
2914         FW_STAT_RX_PORT_PAUSE_IX,
2915         FW_STAT_RX_PORT_PPP0_IX,
2916         FW_STAT_RX_PORT_PPP1_IX,
2917         FW_STAT_RX_PORT_PPP2_IX,
2918         FW_STAT_RX_PORT_PPP3_IX,
2919         FW_STAT_RX_PORT_PPP4_IX,
2920         FW_STAT_RX_PORT_PPP5_IX,
2921         FW_STAT_RX_PORT_PPP6_IX,
2922         FW_STAT_RX_PORT_PPP7_IX,
2923         FW_STAT_RX_PORT_LESS_64B_IX,
2924         FW_STAT_RX_PORT_MAC_ERROR_IX,
2925         FW_NUM_PORT_RX_STATS
2926 };
2927
2928 /* port stats */
2929 #define FW_NUM_PORT_STATS (FW_NUM_PORT_TX_STATS + FW_NUM_PORT_RX_STATS)
2930
2931 struct fw_port_stats_cmd {
2932         __be32 op_to_portid;
2933         __be32 retval_len16;
2934         union fw_port_stats {
2935                 struct fw_port_stats_ctl {
2936                         u8 nstats_bg_bm;
2937                         u8 tx_ix;
2938                         __be16 r6;
2939                         __be32 r7;
2940                         __be64 stat0;
2941                         __be64 stat1;
2942                         __be64 stat2;
2943                         __be64 stat3;
2944                         __be64 stat4;
2945                         __be64 stat5;
2946                 } ctl;
2947                 struct fw_port_stats_all {
2948                         __be64 tx_bytes;
2949                         __be64 tx_frames;
2950                         __be64 tx_bcast;
2951                         __be64 tx_mcast;
2952                         __be64 tx_ucast;
2953                         __be64 tx_error;
2954                         __be64 tx_64b;
2955                         __be64 tx_65b_127b;
2956                         __be64 tx_128b_255b;
2957                         __be64 tx_256b_511b;
2958                         __be64 tx_512b_1023b;
2959                         __be64 tx_1024b_1518b;
2960                         __be64 tx_1519b_max;
2961                         __be64 tx_drop;
2962                         __be64 tx_pause;
2963                         __be64 tx_ppp0;
2964                         __be64 tx_ppp1;
2965                         __be64 tx_ppp2;
2966                         __be64 tx_ppp3;
2967                         __be64 tx_ppp4;
2968                         __be64 tx_ppp5;
2969                         __be64 tx_ppp6;
2970                         __be64 tx_ppp7;
2971                         __be64 rx_bytes;
2972                         __be64 rx_frames;
2973                         __be64 rx_bcast;
2974                         __be64 rx_mcast;
2975                         __be64 rx_ucast;
2976                         __be64 rx_mtu_error;
2977                         __be64 rx_mtu_crc_error;
2978                         __be64 rx_crc_error;
2979                         __be64 rx_len_error;
2980                         __be64 rx_sym_error;
2981                         __be64 rx_64b;
2982                         __be64 rx_65b_127b;
2983                         __be64 rx_128b_255b;
2984                         __be64 rx_256b_511b;
2985                         __be64 rx_512b_1023b;
2986                         __be64 rx_1024b_1518b;
2987                         __be64 rx_1519b_max;
2988                         __be64 rx_pause;
2989                         __be64 rx_ppp0;
2990                         __be64 rx_ppp1;
2991                         __be64 rx_ppp2;
2992                         __be64 rx_ppp3;
2993                         __be64 rx_ppp4;
2994                         __be64 rx_ppp5;
2995                         __be64 rx_ppp6;
2996                         __be64 rx_ppp7;
2997                         __be64 rx_less_64b;
2998                         __be64 rx_bg_drop;
2999                         __be64 rx_bg_trunc;
3000                 } all;
3001         } u;
3002 };
3003
3004 /* port loopback stats */
3005 #define FW_NUM_LB_STATS 16
3006 enum fw_port_lb_stats_index {
3007         FW_STAT_LB_PORT_BYTES_IX,
3008         FW_STAT_LB_PORT_FRAMES_IX,
3009         FW_STAT_LB_PORT_BCAST_IX,
3010         FW_STAT_LB_PORT_MCAST_IX,
3011         FW_STAT_LB_PORT_UCAST_IX,
3012         FW_STAT_LB_PORT_ERROR_IX,
3013         FW_STAT_LB_PORT_64B_IX,
3014         FW_STAT_LB_PORT_65B_127B_IX,
3015         FW_STAT_LB_PORT_128B_255B_IX,
3016         FW_STAT_LB_PORT_256B_511B_IX,
3017         FW_STAT_LB_PORT_512B_1023B_IX,
3018         FW_STAT_LB_PORT_1024B_1518B_IX,
3019         FW_STAT_LB_PORT_1519B_MAX_IX,
3020         FW_STAT_LB_PORT_DROP_FRAMES_IX
3021 };
3022
3023 struct fw_port_lb_stats_cmd {
3024         __be32 op_to_lbport;
3025         __be32 retval_len16;
3026         union fw_port_lb_stats {
3027                 struct fw_port_lb_stats_ctl {
3028                         u8 nstats_bg_bm;
3029                         u8 ix_pkd;
3030                         __be16 r6;
3031                         __be32 r7;
3032                         __be64 stat0;
3033                         __be64 stat1;
3034                         __be64 stat2;
3035                         __be64 stat3;
3036                         __be64 stat4;
3037                         __be64 stat5;
3038                 } ctl;
3039                 struct fw_port_lb_stats_all {
3040                         __be64 tx_bytes;
3041                         __be64 tx_frames;
3042                         __be64 tx_bcast;
3043                         __be64 tx_mcast;
3044                         __be64 tx_ucast;
3045                         __be64 tx_error;
3046                         __be64 tx_64b;
3047                         __be64 tx_65b_127b;
3048                         __be64 tx_128b_255b;
3049                         __be64 tx_256b_511b;
3050                         __be64 tx_512b_1023b;
3051                         __be64 tx_1024b_1518b;
3052                         __be64 tx_1519b_max;
3053                         __be64 rx_lb_drop;
3054                         __be64 rx_lb_trunc;
3055                 } all;
3056         } u;
3057 };
3058
3059 enum fw_ptp_subop {
3060         /* none */
3061         FW_PTP_SC_INIT_TIMER            = 0x00,
3062         FW_PTP_SC_TX_TYPE               = 0x01,
3063         /* init */
3064         FW_PTP_SC_RXTIME_STAMP          = 0x08,
3065         FW_PTP_SC_RDRX_TYPE             = 0x09,
3066         /* ts */
3067         FW_PTP_SC_ADJ_FREQ              = 0x10,
3068         FW_PTP_SC_ADJ_TIME              = 0x11,
3069         FW_PTP_SC_ADJ_FTIME             = 0x12,
3070         FW_PTP_SC_WALL_CLOCK            = 0x13,
3071         FW_PTP_SC_GET_TIME              = 0x14,
3072         FW_PTP_SC_SET_TIME              = 0x15,
3073 };
3074
3075 struct fw_ptp_cmd {
3076         __be32 op_to_portid;
3077         __be32 retval_len16;
3078         union fw_ptp {
3079                 struct fw_ptp_sc {
3080                         __u8   sc;
3081                         __u8   r3[7];
3082                 } scmd;
3083                 struct fw_ptp_init {
3084                         __u8   sc;
3085                         __u8   txchan;
3086                         __be16 absid;
3087                         __be16 mode;
3088                         __be16 r3;
3089                 } init;
3090                 struct fw_ptp_ts {
3091                         __u8   sc;
3092                         __u8   sign;
3093                         __be16 r3;
3094                         __be32 ppb;
3095                         __be64 tm;
3096                 } ts;
3097         } u;
3098         __be64 r3;
3099 };
3100
3101 #define FW_PTP_CMD_PORTID_S             0
3102 #define FW_PTP_CMD_PORTID_M             0xf
3103 #define FW_PTP_CMD_PORTID_V(x)          ((x) << FW_PTP_CMD_PORTID_S)
3104 #define FW_PTP_CMD_PORTID_G(x)          \
3105         (((x) >> FW_PTP_CMD_PORTID_S) & FW_PTP_CMD_PORTID_M)
3106
3107 struct fw_rss_ind_tbl_cmd {
3108         __be32 op_to_viid;
3109         __be32 retval_len16;
3110         __be16 niqid;
3111         __be16 startidx;
3112         __be32 r3;
3113         __be32 iq0_to_iq2;
3114         __be32 iq3_to_iq5;
3115         __be32 iq6_to_iq8;
3116         __be32 iq9_to_iq11;
3117         __be32 iq12_to_iq14;
3118         __be32 iq15_to_iq17;
3119         __be32 iq18_to_iq20;
3120         __be32 iq21_to_iq23;
3121         __be32 iq24_to_iq26;
3122         __be32 iq27_to_iq29;
3123         __be32 iq30_iq31;
3124         __be32 r15_lo;
3125 };
3126
3127 #define FW_RSS_IND_TBL_CMD_VIID_S       0
3128 #define FW_RSS_IND_TBL_CMD_VIID_V(x)    ((x) << FW_RSS_IND_TBL_CMD_VIID_S)
3129
3130 #define FW_RSS_IND_TBL_CMD_IQ0_S        20
3131 #define FW_RSS_IND_TBL_CMD_IQ0_V(x)     ((x) << FW_RSS_IND_TBL_CMD_IQ0_S)
3132
3133 #define FW_RSS_IND_TBL_CMD_IQ1_S        10
3134 #define FW_RSS_IND_TBL_CMD_IQ1_V(x)     ((x) << FW_RSS_IND_TBL_CMD_IQ1_S)
3135
3136 #define FW_RSS_IND_TBL_CMD_IQ2_S        0
3137 #define FW_RSS_IND_TBL_CMD_IQ2_V(x)     ((x) << FW_RSS_IND_TBL_CMD_IQ2_S)
3138
3139 struct fw_rss_glb_config_cmd {
3140         __be32 op_to_write;
3141         __be32 retval_len16;
3142         union fw_rss_glb_config {
3143                 struct fw_rss_glb_config_manual {
3144                         __be32 mode_pkd;
3145                         __be32 r3;
3146                         __be64 r4;
3147                         __be64 r5;
3148                 } manual;
3149                 struct fw_rss_glb_config_basicvirtual {
3150                         __be32 mode_pkd;
3151                         __be32 synmapen_to_hashtoeplitz;
3152                         __be64 r8;
3153                         __be64 r9;
3154                 } basicvirtual;
3155         } u;
3156 };
3157
3158 #define FW_RSS_GLB_CONFIG_CMD_MODE_S    28
3159 #define FW_RSS_GLB_CONFIG_CMD_MODE_M    0xf
3160 #define FW_RSS_GLB_CONFIG_CMD_MODE_V(x) ((x) << FW_RSS_GLB_CONFIG_CMD_MODE_S)
3161 #define FW_RSS_GLB_CONFIG_CMD_MODE_G(x) \
3162         (((x) >> FW_RSS_GLB_CONFIG_CMD_MODE_S) & FW_RSS_GLB_CONFIG_CMD_MODE_M)
3163
3164 #define FW_RSS_GLB_CONFIG_CMD_MODE_MANUAL       0
3165 #define FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL 1
3166
3167 #define FW_RSS_GLB_CONFIG_CMD_SYNMAPEN_S        8
3168 #define FW_RSS_GLB_CONFIG_CMD_SYNMAPEN_V(x)     \
3169         ((x) << FW_RSS_GLB_CONFIG_CMD_SYNMAPEN_S)
3170 #define FW_RSS_GLB_CONFIG_CMD_SYNMAPEN_F        \
3171         FW_RSS_GLB_CONFIG_CMD_SYNMAPEN_V(1U)
3172
3173 #define FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6_S           7
3174 #define FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6_V(x)        \
3175         ((x) << FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6_S)
3176 #define FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6_F   \
3177         FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6_V(1U)
3178
3179 #define FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6_S           6
3180 #define FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6_V(x)        \
3181         ((x) << FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6_S)
3182 #define FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6_F   \
3183         FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6_V(1U)
3184
3185 #define FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4_S           5
3186 #define FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4_V(x)        \
3187         ((x) << FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4_S)
3188 #define FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4_F   \
3189         FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4_V(1U)
3190
3191 #define FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4_S           4
3192 #define FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4_V(x)        \
3193         ((x) << FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4_S)
3194 #define FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4_F   \
3195         FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4_V(1U)
3196
3197 #define FW_RSS_GLB_CONFIG_CMD_OFDMAPEN_S        3
3198 #define FW_RSS_GLB_CONFIG_CMD_OFDMAPEN_V(x)     \
3199         ((x) << FW_RSS_GLB_CONFIG_CMD_OFDMAPEN_S)
3200 #define FW_RSS_GLB_CONFIG_CMD_OFDMAPEN_F        \
3201         FW_RSS_GLB_CONFIG_CMD_OFDMAPEN_V(1U)
3202
3203 #define FW_RSS_GLB_CONFIG_CMD_TNLMAPEN_S        2
3204 #define FW_RSS_GLB_CONFIG_CMD_TNLMAPEN_V(x)     \
3205         ((x) << FW_RSS_GLB_CONFIG_CMD_TNLMAPEN_S)
3206 #define FW_RSS_GLB_CONFIG_CMD_TNLMAPEN_F        \
3207         FW_RSS_GLB_CONFIG_CMD_TNLMAPEN_V(1U)
3208
3209 #define FW_RSS_GLB_CONFIG_CMD_TNLALLLKP_S       1
3210 #define FW_RSS_GLB_CONFIG_CMD_TNLALLLKP_V(x)    \
3211         ((x) << FW_RSS_GLB_CONFIG_CMD_TNLALLLKP_S)
3212 #define FW_RSS_GLB_CONFIG_CMD_TNLALLLKP_F       \
3213         FW_RSS_GLB_CONFIG_CMD_TNLALLLKP_V(1U)
3214
3215 #define FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ_S    0
3216 #define FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ_V(x) \
3217         ((x) << FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ_S)
3218 #define FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ_F    \
3219         FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ_V(1U)
3220
3221 struct fw_rss_vi_config_cmd {
3222         __be32 op_to_viid;
3223 #define FW_RSS_VI_CONFIG_CMD_VIID(x) ((x) << 0)
3224         __be32 retval_len16;
3225         union fw_rss_vi_config {
3226                 struct fw_rss_vi_config_manual {
3227                         __be64 r3;
3228                         __be64 r4;
3229                         __be64 r5;
3230                 } manual;
3231                 struct fw_rss_vi_config_basicvirtual {
3232                         __be32 r6;
3233                         __be32 defaultq_to_udpen;
3234                         __be64 r9;
3235                         __be64 r10;
3236                 } basicvirtual;
3237         } u;
3238 };
3239
3240 #define FW_RSS_VI_CONFIG_CMD_VIID_S     0
3241 #define FW_RSS_VI_CONFIG_CMD_VIID_V(x)  ((x) << FW_RSS_VI_CONFIG_CMD_VIID_S)
3242
3243 #define FW_RSS_VI_CONFIG_CMD_DEFAULTQ_S         16
3244 #define FW_RSS_VI_CONFIG_CMD_DEFAULTQ_M         0x3ff
3245 #define FW_RSS_VI_CONFIG_CMD_DEFAULTQ_V(x)      \
3246         ((x) << FW_RSS_VI_CONFIG_CMD_DEFAULTQ_S)
3247 #define FW_RSS_VI_CONFIG_CMD_DEFAULTQ_G(x)      \
3248         (((x) >> FW_RSS_VI_CONFIG_CMD_DEFAULTQ_S) & \
3249          FW_RSS_VI_CONFIG_CMD_DEFAULTQ_M)
3250
3251 #define FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN_S     4
3252 #define FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN_V(x)  \
3253         ((x) << FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN_S)
3254 #define FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN_F     \
3255         FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN_V(1U)
3256
3257 #define FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN_S      3
3258 #define FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN_V(x)   \
3259         ((x) << FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN_S)
3260 #define FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN_F      \
3261         FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN_V(1U)
3262
3263 #define FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN_S     2
3264 #define FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN_V(x)  \
3265         ((x) << FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN_S)
3266 #define FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN_F     \
3267         FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN_V(1U)
3268
3269 #define FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN_S      1
3270 #define FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN_V(x)   \
3271         ((x) << FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN_S)
3272 #define FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN_F      \
3273         FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN_V(1U)
3274
3275 #define FW_RSS_VI_CONFIG_CMD_UDPEN_S    0
3276 #define FW_RSS_VI_CONFIG_CMD_UDPEN_V(x) ((x) << FW_RSS_VI_CONFIG_CMD_UDPEN_S)
3277 #define FW_RSS_VI_CONFIG_CMD_UDPEN_F    FW_RSS_VI_CONFIG_CMD_UDPEN_V(1U)
3278
3279 enum fw_sched_sc {
3280         FW_SCHED_SC_PARAMS              = 1,
3281 };
3282
3283 struct fw_sched_cmd {
3284         __be32 op_to_write;
3285         __be32 retval_len16;
3286         union fw_sched {
3287                 struct fw_sched_config {
3288                         __u8   sc;
3289                         __u8   type;
3290                         __u8   minmaxen;
3291                         __u8   r3[5];
3292                         __u8   nclasses[4];
3293                         __be32 r4;
3294                 } config;
3295                 struct fw_sched_params {
3296                         __u8   sc;
3297                         __u8   type;
3298                         __u8   level;
3299                         __u8   mode;
3300                         __u8   unit;
3301                         __u8   rate;
3302                         __u8   ch;
3303                         __u8   cl;
3304                         __be32 min;
3305                         __be32 max;
3306                         __be16 weight;
3307                         __be16 pktsize;
3308                         __be16 burstsize;
3309                         __be16 r4;
3310                 } params;
3311         } u;
3312 };
3313
3314 struct fw_clip_cmd {
3315         __be32 op_to_write;
3316         __be32 alloc_to_len16;
3317         __be64 ip_hi;
3318         __be64 ip_lo;
3319         __be32 r4[2];
3320 };
3321
3322 #define FW_CLIP_CMD_ALLOC_S     31
3323 #define FW_CLIP_CMD_ALLOC_V(x)  ((x) << FW_CLIP_CMD_ALLOC_S)
3324 #define FW_CLIP_CMD_ALLOC_F     FW_CLIP_CMD_ALLOC_V(1U)
3325
3326 #define FW_CLIP_CMD_FREE_S      30
3327 #define FW_CLIP_CMD_FREE_V(x)   ((x) << FW_CLIP_CMD_FREE_S)
3328 #define FW_CLIP_CMD_FREE_F      FW_CLIP_CMD_FREE_V(1U)
3329
3330 enum fw_error_type {
3331         FW_ERROR_TYPE_EXCEPTION         = 0x0,
3332         FW_ERROR_TYPE_HWMODULE          = 0x1,
3333         FW_ERROR_TYPE_WR                = 0x2,
3334         FW_ERROR_TYPE_ACL               = 0x3,
3335 };
3336
3337 struct fw_error_cmd {
3338         __be32 op_to_type;
3339         __be32 len16_pkd;
3340         union fw_error {
3341                 struct fw_error_exception {
3342                         __be32 info[6];
3343                 } exception;
3344                 struct fw_error_hwmodule {
3345                         __be32 regaddr;
3346                         __be32 regval;
3347                 } hwmodule;
3348                 struct fw_error_wr {
3349                         __be16 cidx;
3350                         __be16 pfn_vfn;
3351                         __be32 eqid;
3352                         u8 wrhdr[16];
3353                 } wr;
3354                 struct fw_error_acl {
3355                         __be16 cidx;
3356                         __be16 pfn_vfn;
3357                         __be32 eqid;
3358                         __be16 mv_pkd;
3359                         u8 val[6];
3360                         __be64 r4;
3361                 } acl;
3362         } u;
3363 };
3364
3365 struct fw_debug_cmd {
3366         __be32 op_type;
3367         __be32 len16_pkd;
3368         union fw_debug {
3369                 struct fw_debug_assert {
3370                         __be32 fcid;
3371                         __be32 line;
3372                         __be32 x;
3373                         __be32 y;
3374                         u8 filename_0_7[8];
3375                         u8 filename_8_15[8];
3376                         __be64 r3;
3377                 } assert;
3378                 struct fw_debug_prt {
3379                         __be16 dprtstridx;
3380                         __be16 r3[3];
3381                         __be32 dprtstrparam0;
3382                         __be32 dprtstrparam1;
3383                         __be32 dprtstrparam2;
3384                         __be32 dprtstrparam3;
3385                 } prt;
3386         } u;
3387 };
3388
3389 #define FW_DEBUG_CMD_TYPE_S     0
3390 #define FW_DEBUG_CMD_TYPE_M     0xff
3391 #define FW_DEBUG_CMD_TYPE_G(x)  \
3392         (((x) >> FW_DEBUG_CMD_TYPE_S) & FW_DEBUG_CMD_TYPE_M)
3393
3394 enum pcie_fw_eval {
3395         PCIE_FW_EVAL_CRASH = 0,
3396 };
3397
3398 #define PCIE_FW_ERR_S           31
3399 #define PCIE_FW_ERR_V(x)        ((x) << PCIE_FW_ERR_S)
3400 #define PCIE_FW_ERR_F           PCIE_FW_ERR_V(1U)
3401
3402 #define PCIE_FW_INIT_S          30
3403 #define PCIE_FW_INIT_V(x)       ((x) << PCIE_FW_INIT_S)
3404 #define PCIE_FW_INIT_F          PCIE_FW_INIT_V(1U)
3405
3406 #define PCIE_FW_HALT_S          29
3407 #define PCIE_FW_HALT_V(x)       ((x) << PCIE_FW_HALT_S)
3408 #define PCIE_FW_HALT_F          PCIE_FW_HALT_V(1U)
3409
3410 #define PCIE_FW_EVAL_S          24
3411 #define PCIE_FW_EVAL_M          0x7
3412 #define PCIE_FW_EVAL_G(x)       (((x) >> PCIE_FW_EVAL_S) & PCIE_FW_EVAL_M)
3413
3414 #define PCIE_FW_MASTER_VLD_S    15
3415 #define PCIE_FW_MASTER_VLD_V(x) ((x) << PCIE_FW_MASTER_VLD_S)
3416 #define PCIE_FW_MASTER_VLD_F    PCIE_FW_MASTER_VLD_V(1U)
3417
3418 #define PCIE_FW_MASTER_S        12
3419 #define PCIE_FW_MASTER_M        0x7
3420 #define PCIE_FW_MASTER_V(x)     ((x) << PCIE_FW_MASTER_S)
3421 #define PCIE_FW_MASTER_G(x)     (((x) >> PCIE_FW_MASTER_S) & PCIE_FW_MASTER_M)
3422
3423 struct fw_hdr {
3424         u8 ver;
3425         u8 chip;                        /* terminator chip type */
3426         __be16  len512;                 /* bin length in units of 512-bytes */
3427         __be32  fw_ver;                 /* firmware version */
3428         __be32  tp_microcode_ver;
3429         u8 intfver_nic;
3430         u8 intfver_vnic;
3431         u8 intfver_ofld;
3432         u8 intfver_ri;
3433         u8 intfver_iscsipdu;
3434         u8 intfver_iscsi;
3435         u8 intfver_fcoepdu;
3436         u8 intfver_fcoe;
3437         __u32   reserved2;
3438         __u32   reserved3;
3439         __u32   reserved4;
3440         __be32  flags;
3441         __be32  reserved6[23];
3442 };
3443
3444 enum fw_hdr_chip {
3445         FW_HDR_CHIP_T4,
3446         FW_HDR_CHIP_T5,
3447         FW_HDR_CHIP_T6
3448 };
3449
3450 #define FW_HDR_FW_VER_MAJOR_S   24
3451 #define FW_HDR_FW_VER_MAJOR_M   0xff
3452 #define FW_HDR_FW_VER_MAJOR_V(x) \
3453         ((x) << FW_HDR_FW_VER_MAJOR_S)
3454 #define FW_HDR_FW_VER_MAJOR_G(x) \
3455         (((x) >> FW_HDR_FW_VER_MAJOR_S) & FW_HDR_FW_VER_MAJOR_M)
3456
3457 #define FW_HDR_FW_VER_MINOR_S   16
3458 #define FW_HDR_FW_VER_MINOR_M   0xff
3459 #define FW_HDR_FW_VER_MINOR_V(x) \
3460         ((x) << FW_HDR_FW_VER_MINOR_S)
3461 #define FW_HDR_FW_VER_MINOR_G(x) \
3462         (((x) >> FW_HDR_FW_VER_MINOR_S) & FW_HDR_FW_VER_MINOR_M)
3463
3464 #define FW_HDR_FW_VER_MICRO_S   8
3465 #define FW_HDR_FW_VER_MICRO_M   0xff
3466 #define FW_HDR_FW_VER_MICRO_V(x) \
3467         ((x) << FW_HDR_FW_VER_MICRO_S)
3468 #define FW_HDR_FW_VER_MICRO_G(x) \
3469         (((x) >> FW_HDR_FW_VER_MICRO_S) & FW_HDR_FW_VER_MICRO_M)
3470
3471 #define FW_HDR_FW_VER_BUILD_S   0
3472 #define FW_HDR_FW_VER_BUILD_M   0xff
3473 #define FW_HDR_FW_VER_BUILD_V(x) \
3474         ((x) << FW_HDR_FW_VER_BUILD_S)
3475 #define FW_HDR_FW_VER_BUILD_G(x) \
3476         (((x) >> FW_HDR_FW_VER_BUILD_S) & FW_HDR_FW_VER_BUILD_M)
3477
3478 enum fw_hdr_intfver {
3479         FW_HDR_INTFVER_NIC      = 0x00,
3480         FW_HDR_INTFVER_VNIC     = 0x00,
3481         FW_HDR_INTFVER_OFLD     = 0x00,
3482         FW_HDR_INTFVER_RI       = 0x00,
3483         FW_HDR_INTFVER_ISCSIPDU = 0x00,
3484         FW_HDR_INTFVER_ISCSI    = 0x00,
3485         FW_HDR_INTFVER_FCOEPDU  = 0x00,
3486         FW_HDR_INTFVER_FCOE     = 0x00,
3487 };
3488
3489 enum fw_hdr_flags {
3490         FW_HDR_FLAGS_RESET_HALT = 0x00000001,
3491 };
3492
3493 /* length of the formatting string  */
3494 #define FW_DEVLOG_FMT_LEN       192
3495
3496 /* maximum number of the formatting string parameters */
3497 #define FW_DEVLOG_FMT_PARAMS_NUM 8
3498
3499 /* priority levels */
3500 enum fw_devlog_level {
3501         FW_DEVLOG_LEVEL_EMERG   = 0x0,
3502         FW_DEVLOG_LEVEL_CRIT    = 0x1,
3503         FW_DEVLOG_LEVEL_ERR     = 0x2,
3504         FW_DEVLOG_LEVEL_NOTICE  = 0x3,
3505         FW_DEVLOG_LEVEL_INFO    = 0x4,
3506         FW_DEVLOG_LEVEL_DEBUG   = 0x5,
3507         FW_DEVLOG_LEVEL_MAX     = 0x5,
3508 };
3509
3510 /* facilities that may send a log message */
3511 enum fw_devlog_facility {
3512         FW_DEVLOG_FACILITY_CORE         = 0x00,
3513         FW_DEVLOG_FACILITY_CF           = 0x01,
3514         FW_DEVLOG_FACILITY_SCHED        = 0x02,
3515         FW_DEVLOG_FACILITY_TIMER        = 0x04,
3516         FW_DEVLOG_FACILITY_RES          = 0x06,
3517         FW_DEVLOG_FACILITY_HW           = 0x08,
3518         FW_DEVLOG_FACILITY_FLR          = 0x10,
3519         FW_DEVLOG_FACILITY_DMAQ         = 0x12,
3520         FW_DEVLOG_FACILITY_PHY          = 0x14,
3521         FW_DEVLOG_FACILITY_MAC          = 0x16,
3522         FW_DEVLOG_FACILITY_PORT         = 0x18,
3523         FW_DEVLOG_FACILITY_VI           = 0x1A,
3524         FW_DEVLOG_FACILITY_FILTER       = 0x1C,
3525         FW_DEVLOG_FACILITY_ACL          = 0x1E,
3526         FW_DEVLOG_FACILITY_TM           = 0x20,
3527         FW_DEVLOG_FACILITY_QFC          = 0x22,
3528         FW_DEVLOG_FACILITY_DCB          = 0x24,
3529         FW_DEVLOG_FACILITY_ETH          = 0x26,
3530         FW_DEVLOG_FACILITY_OFLD         = 0x28,
3531         FW_DEVLOG_FACILITY_RI           = 0x2A,
3532         FW_DEVLOG_FACILITY_ISCSI        = 0x2C,
3533         FW_DEVLOG_FACILITY_FCOE         = 0x2E,
3534         FW_DEVLOG_FACILITY_FOISCSI      = 0x30,
3535         FW_DEVLOG_FACILITY_FOFCOE       = 0x32,
3536         FW_DEVLOG_FACILITY_CHNET        = 0x34,
3537         FW_DEVLOG_FACILITY_MAX          = 0x34,
3538 };
3539
3540 /* log message format */
3541 struct fw_devlog_e {
3542         __be64  timestamp;
3543         __be32  seqno;
3544         __be16  reserved1;
3545         __u8    level;
3546         __u8    facility;
3547         __u8    fmt[FW_DEVLOG_FMT_LEN];
3548         __be32  params[FW_DEVLOG_FMT_PARAMS_NUM];
3549         __be32  reserved3[4];
3550 };
3551
3552 struct fw_devlog_cmd {
3553         __be32 op_to_write;
3554         __be32 retval_len16;
3555         __u8   level;
3556         __u8   r2[7];
3557         __be32 memtype_devlog_memaddr16_devlog;
3558         __be32 memsize_devlog;
3559         __be32 r3[2];
3560 };
3561
3562 #define FW_DEVLOG_CMD_MEMTYPE_DEVLOG_S          28
3563 #define FW_DEVLOG_CMD_MEMTYPE_DEVLOG_M          0xf
3564 #define FW_DEVLOG_CMD_MEMTYPE_DEVLOG_G(x)       \
3565         (((x) >> FW_DEVLOG_CMD_MEMTYPE_DEVLOG_S) & \
3566          FW_DEVLOG_CMD_MEMTYPE_DEVLOG_M)
3567
3568 #define FW_DEVLOG_CMD_MEMADDR16_DEVLOG_S        0
3569 #define FW_DEVLOG_CMD_MEMADDR16_DEVLOG_M        0xfffffff
3570 #define FW_DEVLOG_CMD_MEMADDR16_DEVLOG_G(x)     \
3571         (((x) >> FW_DEVLOG_CMD_MEMADDR16_DEVLOG_S) & \
3572          FW_DEVLOG_CMD_MEMADDR16_DEVLOG_M)
3573
3574 /* P C I E   F W   P F 7   R E G I S T E R */
3575
3576 /* PF7 stores the Firmware Device Log parameters which allows Host Drivers to
3577  * access the "devlog" which needing to contact firmware.  The encoding is
3578  * mostly the same as that returned by the DEVLOG command except for the size
3579  * which is encoded as the number of entries in multiples-1 of 128 here rather
3580  * than the memory size as is done in the DEVLOG command.  Thus, 0 means 128
3581  * and 15 means 2048.  This of course in turn constrains the allowed values
3582  * for the devlog size ...
3583  */
3584 #define PCIE_FW_PF_DEVLOG               7
3585
3586 #define PCIE_FW_PF_DEVLOG_NENTRIES128_S 28
3587 #define PCIE_FW_PF_DEVLOG_NENTRIES128_M 0xf
3588 #define PCIE_FW_PF_DEVLOG_NENTRIES128_V(x) \
3589         ((x) << PCIE_FW_PF_DEVLOG_NENTRIES128_S)
3590 #define PCIE_FW_PF_DEVLOG_NENTRIES128_G(x) \
3591         (((x) >> PCIE_FW_PF_DEVLOG_NENTRIES128_S) & \
3592          PCIE_FW_PF_DEVLOG_NENTRIES128_M)
3593
3594 #define PCIE_FW_PF_DEVLOG_ADDR16_S      4
3595 #define PCIE_FW_PF_DEVLOG_ADDR16_M      0xffffff
3596 #define PCIE_FW_PF_DEVLOG_ADDR16_V(x)   ((x) << PCIE_FW_PF_DEVLOG_ADDR16_S)
3597 #define PCIE_FW_PF_DEVLOG_ADDR16_G(x) \
3598         (((x) >> PCIE_FW_PF_DEVLOG_ADDR16_S) & PCIE_FW_PF_DEVLOG_ADDR16_M)
3599
3600 #define PCIE_FW_PF_DEVLOG_MEMTYPE_S     0
3601 #define PCIE_FW_PF_DEVLOG_MEMTYPE_M     0xf
3602 #define PCIE_FW_PF_DEVLOG_MEMTYPE_V(x)  ((x) << PCIE_FW_PF_DEVLOG_MEMTYPE_S)
3603 #define PCIE_FW_PF_DEVLOG_MEMTYPE_G(x) \
3604         (((x) >> PCIE_FW_PF_DEVLOG_MEMTYPE_S) & PCIE_FW_PF_DEVLOG_MEMTYPE_M)
3605
3606 #define MAX_IMM_OFLD_TX_DATA_WR_LEN (0xff + sizeof(struct fw_ofld_tx_data_wr))
3607
3608 struct fw_crypto_lookaside_wr {
3609         __be32 op_to_cctx_size;
3610         __be32 len16_pkd;
3611         __be32 session_id;
3612         __be32 rx_chid_to_rx_q_id;
3613         __be32 key_addr;
3614         __be32 pld_size_hash_size;
3615         __be64 cookie;
3616 };
3617
3618 #define FW_CRYPTO_LOOKASIDE_WR_OPCODE_S 24
3619 #define FW_CRYPTO_LOOKASIDE_WR_OPCODE_M 0xff
3620 #define FW_CRYPTO_LOOKASIDE_WR_OPCODE_V(x) \
3621         ((x) << FW_CRYPTO_LOOKASIDE_WR_OPCODE_S)
3622 #define FW_CRYPTO_LOOKASIDE_WR_OPCODE_G(x) \
3623         (((x) >> FW_CRYPTO_LOOKASIDE_WR_OPCODE_S) & \
3624          FW_CRYPTO_LOOKASIDE_WR_OPCODE_M)
3625
3626 #define FW_CRYPTO_LOOKASIDE_WR_COMPL_S 23
3627 #define FW_CRYPTO_LOOKASIDE_WR_COMPL_M 0x1
3628 #define FW_CRYPTO_LOOKASIDE_WR_COMPL_V(x) \
3629         ((x) << FW_CRYPTO_LOOKASIDE_WR_COMPL_S)
3630 #define FW_CRYPTO_LOOKASIDE_WR_COMPL_G(x) \
3631         (((x) >> FW_CRYPTO_LOOKASIDE_WR_COMPL_S) & \
3632          FW_CRYPTO_LOOKASIDE_WR_COMPL_M)
3633 #define FW_CRYPTO_LOOKASIDE_WR_COMPL_F FW_CRYPTO_LOOKASIDE_WR_COMPL_V(1U)
3634
3635 #define FW_CRYPTO_LOOKASIDE_WR_IMM_LEN_S 15
3636 #define FW_CRYPTO_LOOKASIDE_WR_IMM_LEN_M 0xff
3637 #define FW_CRYPTO_LOOKASIDE_WR_IMM_LEN_V(x) \
3638         ((x) << FW_CRYPTO_LOOKASIDE_WR_IMM_LEN_S)
3639 #define FW_CRYPTO_LOOKASIDE_WR_IMM_LEN_G(x) \
3640         (((x) >> FW_CRYPTO_LOOKASIDE_WR_IMM_LEN_S) & \
3641          FW_CRYPTO_LOOKASIDE_WR_IMM_LEN_M)
3642
3643 #define FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC_S 5
3644 #define FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC_M 0x3
3645 #define FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC_V(x) \
3646         ((x) << FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC_S)
3647 #define FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC_G(x) \
3648         (((x) >> FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC_S) & \
3649          FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC_M)
3650
3651 #define FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE_S 0
3652 #define FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE_M 0x1f
3653 #define FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE_V(x) \
3654         ((x) << FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE_S)
3655 #define FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE_G(x) \
3656         (((x) >> FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE_S) & \
3657          FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE_M)
3658
3659 #define FW_CRYPTO_LOOKASIDE_WR_LEN16_S 0
3660 #define FW_CRYPTO_LOOKASIDE_WR_LEN16_M 0xff
3661 #define FW_CRYPTO_LOOKASIDE_WR_LEN16_V(x) \
3662         ((x) << FW_CRYPTO_LOOKASIDE_WR_LEN16_S)
3663 #define FW_CRYPTO_LOOKASIDE_WR_LEN16_G(x) \
3664         (((x) >> FW_CRYPTO_LOOKASIDE_WR_LEN16_S) & \
3665          FW_CRYPTO_LOOKASIDE_WR_LEN16_M)
3666
3667 #define FW_CRYPTO_LOOKASIDE_WR_RX_CHID_S 29
3668 #define FW_CRYPTO_LOOKASIDE_WR_RX_CHID_M 0x3
3669 #define FW_CRYPTO_LOOKASIDE_WR_RX_CHID_V(x) \
3670         ((x) << FW_CRYPTO_LOOKASIDE_WR_RX_CHID_S)
3671 #define FW_CRYPTO_LOOKASIDE_WR_RX_CHID_G(x) \
3672         (((x) >> FW_CRYPTO_LOOKASIDE_WR_RX_CHID_S) & \
3673          FW_CRYPTO_LOOKASIDE_WR_RX_CHID_M)
3674
3675 #define FW_CRYPTO_LOOKASIDE_WR_LCB_S  27
3676 #define FW_CRYPTO_LOOKASIDE_WR_LCB_M  0x3
3677 #define FW_CRYPTO_LOOKASIDE_WR_LCB_V(x) \
3678         ((x) << FW_CRYPTO_LOOKASIDE_WR_LCB_S)
3679 #define FW_CRYPTO_LOOKASIDE_WR_LCB_G(x) \
3680         (((x) >> FW_CRYPTO_LOOKASIDE_WR_LCB_S) & FW_CRYPTO_LOOKASIDE_WR_LCB_M)
3681
3682 #define FW_CRYPTO_LOOKASIDE_WR_PHASH_S 25
3683 #define FW_CRYPTO_LOOKASIDE_WR_PHASH_M 0x3
3684 #define FW_CRYPTO_LOOKASIDE_WR_PHASH_V(x) \
3685         ((x) << FW_CRYPTO_LOOKASIDE_WR_PHASH_S)
3686 #define FW_CRYPTO_LOOKASIDE_WR_PHASH_G(x) \
3687         (((x) >> FW_CRYPTO_LOOKASIDE_WR_PHASH_S) & \
3688          FW_CRYPTO_LOOKASIDE_WR_PHASH_M)
3689
3690 #define FW_CRYPTO_LOOKASIDE_WR_IV_S   23
3691 #define FW_CRYPTO_LOOKASIDE_WR_IV_M   0x3
3692 #define FW_CRYPTO_LOOKASIDE_WR_IV_V(x) \
3693         ((x) << FW_CRYPTO_LOOKASIDE_WR_IV_S)
3694 #define FW_CRYPTO_LOOKASIDE_WR_IV_G(x) \
3695         (((x) >> FW_CRYPTO_LOOKASIDE_WR_IV_S) & FW_CRYPTO_LOOKASIDE_WR_IV_M)
3696
3697 #define FW_CRYPTO_LOOKASIDE_WR_FQIDX_S   15
3698 #define FW_CRYPTO_LOOKASIDE_WR_FQIDX_M   0xff
3699 #define FW_CRYPTO_LOOKASIDE_WR_FQIDX_V(x) \
3700         ((x) << FW_CRYPTO_LOOKASIDE_WR_FQIDX_S)
3701 #define FW_CRYPTO_LOOKASIDE_WR_FQIDX_G(x) \
3702         (((x) >> FW_CRYPTO_LOOKASIDE_WR_FQIDX_S) & \
3703          FW_CRYPTO_LOOKASIDE_WR_FQIDX_M)
3704
3705 #define FW_CRYPTO_LOOKASIDE_WR_TX_CH_S 10
3706 #define FW_CRYPTO_LOOKASIDE_WR_TX_CH_M 0x3
3707 #define FW_CRYPTO_LOOKASIDE_WR_TX_CH_V(x) \
3708         ((x) << FW_CRYPTO_LOOKASIDE_WR_TX_CH_S)
3709 #define FW_CRYPTO_LOOKASIDE_WR_TX_CH_G(x) \
3710         (((x) >> FW_CRYPTO_LOOKASIDE_WR_TX_CH_S) & \
3711          FW_CRYPTO_LOOKASIDE_WR_TX_CH_M)
3712
3713 #define FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID_S 0
3714 #define FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID_M 0x3ff
3715 #define FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID_V(x) \
3716         ((x) << FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID_S)
3717 #define FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID_G(x) \
3718         (((x) >> FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID_S) & \
3719          FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID_M)
3720
3721 #define FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE_S 24
3722 #define FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE_M 0xff
3723 #define FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE_V(x) \
3724         ((x) << FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE_S)
3725 #define FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE_G(x) \
3726         (((x) >> FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE_S) & \
3727          FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE_M)
3728
3729 #define FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE_S 17
3730 #define FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE_M 0x7f
3731 #define FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE_V(x) \
3732         ((x) << FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE_S)
3733 #define FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE_G(x) \
3734         (((x) >> FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE_S) & \
3735          FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE_M)
3736
3737 #endif /* _T4FW_INTERFACE_H_ */