2 * This file is part of the Chelsio T4 Ethernet driver for Linux.
4 * Copyright (c) 2003-2014 Chelsio Communications, Inc. All rights reserved.
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
35 #include <linux/delay.h>
38 #include "t4_values.h"
40 #include "t4fw_version.h"
43 * t4_wait_op_done_val - wait until an operation is completed
44 * @adapter: the adapter performing the operation
45 * @reg: the register to check for completion
46 * @mask: a single-bit field within @reg that indicates completion
47 * @polarity: the value of the field when the operation is completed
48 * @attempts: number of check iterations
49 * @delay: delay in usecs between iterations
50 * @valp: where to store the value of the register at completion time
52 * Wait until an operation is completed by checking a bit in a register
53 * up to @attempts times. If @valp is not NULL the value of the register
54 * at the time it indicated completion is stored there. Returns 0 if the
55 * operation completes and -EAGAIN otherwise.
57 static int t4_wait_op_done_val(struct adapter *adapter, int reg, u32 mask,
58 int polarity, int attempts, int delay, u32 *valp)
61 u32 val = t4_read_reg(adapter, reg);
63 if (!!(val & mask) == polarity) {
75 static inline int t4_wait_op_done(struct adapter *adapter, int reg, u32 mask,
76 int polarity, int attempts, int delay)
78 return t4_wait_op_done_val(adapter, reg, mask, polarity, attempts,
83 * t4_set_reg_field - set a register field to a value
84 * @adapter: the adapter to program
85 * @addr: the register address
86 * @mask: specifies the portion of the register to modify
87 * @val: the new value for the register field
89 * Sets a register field specified by the supplied mask to the
92 void t4_set_reg_field(struct adapter *adapter, unsigned int addr, u32 mask,
95 u32 v = t4_read_reg(adapter, addr) & ~mask;
97 t4_write_reg(adapter, addr, v | val);
98 (void) t4_read_reg(adapter, addr); /* flush */
102 * t4_read_indirect - read indirectly addressed registers
104 * @addr_reg: register holding the indirect address
105 * @data_reg: register holding the value of the indirect register
106 * @vals: where the read register values are stored
107 * @nregs: how many indirect registers to read
108 * @start_idx: index of first indirect register to read
110 * Reads registers that are accessed indirectly through an address/data
113 void t4_read_indirect(struct adapter *adap, unsigned int addr_reg,
114 unsigned int data_reg, u32 *vals,
115 unsigned int nregs, unsigned int start_idx)
118 t4_write_reg(adap, addr_reg, start_idx);
119 *vals++ = t4_read_reg(adap, data_reg);
125 * t4_write_indirect - write indirectly addressed registers
127 * @addr_reg: register holding the indirect addresses
128 * @data_reg: register holding the value for the indirect registers
129 * @vals: values to write
130 * @nregs: how many indirect registers to write
131 * @start_idx: address of first indirect register to write
133 * Writes a sequential block of registers that are accessed indirectly
134 * through an address/data register pair.
136 void t4_write_indirect(struct adapter *adap, unsigned int addr_reg,
137 unsigned int data_reg, const u32 *vals,
138 unsigned int nregs, unsigned int start_idx)
141 t4_write_reg(adap, addr_reg, start_idx++);
142 t4_write_reg(adap, data_reg, *vals++);
147 * Read a 32-bit PCI Configuration Space register via the PCI-E backdoor
148 * mechanism. This guarantees that we get the real value even if we're
149 * operating within a Virtual Machine and the Hypervisor is trapping our
150 * Configuration Space accesses.
152 void t4_hw_pci_read_cfg4(struct adapter *adap, int reg, u32 *val)
154 u32 req = FUNCTION_V(adap->pf) | REGISTER_V(reg);
156 if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5)
161 if (is_t4(adap->params.chip))
164 t4_write_reg(adap, PCIE_CFG_SPACE_REQ_A, req);
165 *val = t4_read_reg(adap, PCIE_CFG_SPACE_DATA_A);
167 /* Reset ENABLE to 0 so reads of PCIE_CFG_SPACE_DATA won't cause a
168 * Configuration Space read. (None of the other fields matter when
169 * ENABLE is 0 so a simple register write is easier than a
170 * read-modify-write via t4_set_reg_field().)
172 t4_write_reg(adap, PCIE_CFG_SPACE_REQ_A, 0);
176 * t4_report_fw_error - report firmware error
179 * The adapter firmware can indicate error conditions to the host.
180 * If the firmware has indicated an error, print out the reason for
181 * the firmware error.
183 static void t4_report_fw_error(struct adapter *adap)
185 static const char *const reason[] = {
186 "Crash", /* PCIE_FW_EVAL_CRASH */
187 "During Device Preparation", /* PCIE_FW_EVAL_PREP */
188 "During Device Configuration", /* PCIE_FW_EVAL_CONF */
189 "During Device Initialization", /* PCIE_FW_EVAL_INIT */
190 "Unexpected Event", /* PCIE_FW_EVAL_UNEXPECTEDEVENT */
191 "Insufficient Airflow", /* PCIE_FW_EVAL_OVERHEAT */
192 "Device Shutdown", /* PCIE_FW_EVAL_DEVICESHUTDOWN */
193 "Reserved", /* reserved */
197 pcie_fw = t4_read_reg(adap, PCIE_FW_A);
198 if (pcie_fw & PCIE_FW_ERR_F)
199 dev_err(adap->pdev_dev, "Firmware reports adapter error: %s\n",
200 reason[PCIE_FW_EVAL_G(pcie_fw)]);
204 * Get the reply to a mailbox command and store it in @rpl in big-endian order.
206 static void get_mbox_rpl(struct adapter *adap, __be64 *rpl, int nflit,
209 for ( ; nflit; nflit--, mbox_addr += 8)
210 *rpl++ = cpu_to_be64(t4_read_reg64(adap, mbox_addr));
214 * Handle a FW assertion reported in a mailbox.
216 static void fw_asrt(struct adapter *adap, u32 mbox_addr)
218 struct fw_debug_cmd asrt;
220 get_mbox_rpl(adap, (__be64 *)&asrt, sizeof(asrt) / 8, mbox_addr);
221 dev_alert(adap->pdev_dev,
222 "FW assertion at %.16s:%u, val0 %#x, val1 %#x\n",
223 asrt.u.assert.filename_0_7, be32_to_cpu(asrt.u.assert.line),
224 be32_to_cpu(asrt.u.assert.x), be32_to_cpu(asrt.u.assert.y));
227 static void dump_mbox(struct adapter *adap, int mbox, u32 data_reg)
229 dev_err(adap->pdev_dev,
230 "mbox %d: %llx %llx %llx %llx %llx %llx %llx %llx\n", mbox,
231 (unsigned long long)t4_read_reg64(adap, data_reg),
232 (unsigned long long)t4_read_reg64(adap, data_reg + 8),
233 (unsigned long long)t4_read_reg64(adap, data_reg + 16),
234 (unsigned long long)t4_read_reg64(adap, data_reg + 24),
235 (unsigned long long)t4_read_reg64(adap, data_reg + 32),
236 (unsigned long long)t4_read_reg64(adap, data_reg + 40),
237 (unsigned long long)t4_read_reg64(adap, data_reg + 48),
238 (unsigned long long)t4_read_reg64(adap, data_reg + 56));
242 * t4_wr_mbox_meat_timeout - send a command to FW through the given mailbox
244 * @mbox: index of the mailbox to use
245 * @cmd: the command to write
246 * @size: command length in bytes
247 * @rpl: where to optionally store the reply
248 * @sleep_ok: if true we may sleep while awaiting command completion
249 * @timeout: time to wait for command to finish before timing out
251 * Sends the given command to FW through the selected mailbox and waits
252 * for the FW to execute the command. If @rpl is not %NULL it is used to
253 * store the FW's reply to the command. The command and its optional
254 * reply are of the same length. FW can take up to %FW_CMD_MAX_TIMEOUT ms
255 * to respond. @sleep_ok determines whether we may sleep while awaiting
256 * the response. If sleeping is allowed we use progressive backoff
259 * The return value is 0 on success or a negative errno on failure. A
260 * failure can happen either because we are not able to execute the
261 * command or FW executes it but signals an error. In the latter case
262 * the return value is the error code indicated by FW (negated).
264 int t4_wr_mbox_meat_timeout(struct adapter *adap, int mbox, const void *cmd,
265 int size, void *rpl, bool sleep_ok, int timeout)
267 static const int delay[] = {
268 1, 1, 3, 5, 10, 10, 20, 50, 100, 200
273 int i, ms, delay_idx;
274 const __be64 *p = cmd;
275 u32 data_reg = PF_REG(mbox, CIM_PF_MAILBOX_DATA_A);
276 u32 ctl_reg = PF_REG(mbox, CIM_PF_MAILBOX_CTRL_A);
278 if ((size & 15) || size > MBOX_LEN)
282 * If the device is off-line, as in EEH, commands will time out.
283 * Fail them early so we don't waste time waiting.
285 if (adap->pdev->error_state != pci_channel_io_normal)
288 v = MBOWNER_G(t4_read_reg(adap, ctl_reg));
289 for (i = 0; v == MBOX_OWNER_NONE && i < 3; i++)
290 v = MBOWNER_G(t4_read_reg(adap, ctl_reg));
292 if (v != MBOX_OWNER_DRV)
293 return v ? -EBUSY : -ETIMEDOUT;
295 for (i = 0; i < size; i += 8)
296 t4_write_reg64(adap, data_reg + i, be64_to_cpu(*p++));
298 t4_write_reg(adap, ctl_reg, MBMSGVALID_F | MBOWNER_V(MBOX_OWNER_FW));
299 t4_read_reg(adap, ctl_reg); /* flush write */
304 for (i = 0; i < timeout; i += ms) {
306 ms = delay[delay_idx]; /* last element may repeat */
307 if (delay_idx < ARRAY_SIZE(delay) - 1)
313 v = t4_read_reg(adap, ctl_reg);
314 if (MBOWNER_G(v) == MBOX_OWNER_DRV) {
315 if (!(v & MBMSGVALID_F)) {
316 t4_write_reg(adap, ctl_reg, 0);
320 res = t4_read_reg64(adap, data_reg);
321 if (FW_CMD_OP_G(res >> 32) == FW_DEBUG_CMD) {
322 fw_asrt(adap, data_reg);
323 res = FW_CMD_RETVAL_V(EIO);
325 get_mbox_rpl(adap, rpl, size / 8, data_reg);
328 if (FW_CMD_RETVAL_G((int)res))
329 dump_mbox(adap, mbox, data_reg);
330 t4_write_reg(adap, ctl_reg, 0);
331 return -FW_CMD_RETVAL_G((int)res);
335 dump_mbox(adap, mbox, data_reg);
336 dev_err(adap->pdev_dev, "command %#x in mailbox %d timed out\n",
337 *(const u8 *)cmd, mbox);
338 t4_report_fw_error(adap);
342 int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size,
343 void *rpl, bool sleep_ok)
345 return t4_wr_mbox_meat_timeout(adap, mbox, cmd, size, rpl, sleep_ok,
349 static int t4_edc_err_read(struct adapter *adap, int idx)
351 u32 edc_ecc_err_addr_reg;
354 if (is_t4(adap->params.chip)) {
355 CH_WARN(adap, "%s: T4 NOT supported.\n", __func__);
358 if (idx != 0 && idx != 1) {
359 CH_WARN(adap, "%s: idx %d NOT supported.\n", __func__, idx);
363 edc_ecc_err_addr_reg = EDC_T5_REG(EDC_H_ECC_ERR_ADDR_A, idx);
364 rdata_reg = EDC_T5_REG(EDC_H_BIST_STATUS_RDATA_A, idx);
367 "edc%d err addr 0x%x: 0x%x.\n",
368 idx, edc_ecc_err_addr_reg,
369 t4_read_reg(adap, edc_ecc_err_addr_reg));
371 "bist: 0x%x, status %llx %llx %llx %llx %llx %llx %llx %llx %llx.\n",
373 (unsigned long long)t4_read_reg64(adap, rdata_reg),
374 (unsigned long long)t4_read_reg64(adap, rdata_reg + 8),
375 (unsigned long long)t4_read_reg64(adap, rdata_reg + 16),
376 (unsigned long long)t4_read_reg64(adap, rdata_reg + 24),
377 (unsigned long long)t4_read_reg64(adap, rdata_reg + 32),
378 (unsigned long long)t4_read_reg64(adap, rdata_reg + 40),
379 (unsigned long long)t4_read_reg64(adap, rdata_reg + 48),
380 (unsigned long long)t4_read_reg64(adap, rdata_reg + 56),
381 (unsigned long long)t4_read_reg64(adap, rdata_reg + 64));
387 * t4_memory_rw - read/write EDC 0, EDC 1 or MC via PCIE memory window
389 * @win: PCI-E Memory Window to use
390 * @mtype: memory type: MEM_EDC0, MEM_EDC1 or MEM_MC
391 * @addr: address within indicated memory type
392 * @len: amount of memory to transfer
393 * @hbuf: host memory buffer
394 * @dir: direction of transfer T4_MEMORY_READ (1) or T4_MEMORY_WRITE (0)
396 * Reads/writes an [almost] arbitrary memory region in the firmware: the
397 * firmware memory address and host buffer must be aligned on 32-bit
398 * boudaries; the length may be arbitrary. The memory is transferred as
399 * a raw byte sequence from/to the firmware's memory. If this memory
400 * contains data structures which contain multi-byte integers, it's the
401 * caller's responsibility to perform appropriate byte order conversions.
403 int t4_memory_rw(struct adapter *adap, int win, int mtype, u32 addr,
404 u32 len, void *hbuf, int dir)
406 u32 pos, offset, resid, memoffset;
407 u32 edc_size, mc_size, win_pf, mem_reg, mem_aperture, mem_base;
410 /* Argument sanity checks ...
412 if (addr & 0x3 || (uintptr_t)hbuf & 0x3)
416 /* It's convenient to be able to handle lengths which aren't a
417 * multiple of 32-bits because we often end up transferring files to
418 * the firmware. So we'll handle that by normalizing the length here
419 * and then handling any residual transfer at the end.
424 /* Offset into the region of memory which is being accessed
427 * MEM_MC = 2 -- MEM_MC for chips with only 1 memory controller
428 * MEM_MC1 = 3 -- for chips with 2 memory controllers (e.g. T5)
430 edc_size = EDRAM0_SIZE_G(t4_read_reg(adap, MA_EDRAM0_BAR_A));
431 if (mtype != MEM_MC1)
432 memoffset = (mtype * (edc_size * 1024 * 1024));
434 mc_size = EXT_MEM0_SIZE_G(t4_read_reg(adap,
435 MA_EXT_MEMORY0_BAR_A));
436 memoffset = (MEM_MC0 * edc_size + mc_size) * 1024 * 1024;
439 /* Determine the PCIE_MEM_ACCESS_OFFSET */
440 addr = addr + memoffset;
442 /* Each PCI-E Memory Window is programmed with a window size -- or
443 * "aperture" -- which controls the granularity of its mapping onto
444 * adapter memory. We need to grab that aperture in order to know
445 * how to use the specified window. The window is also programmed
446 * with the base address of the Memory Window in BAR0's address
447 * space. For T4 this is an absolute PCI-E Bus Address. For T5
448 * the address is relative to BAR0.
450 mem_reg = t4_read_reg(adap,
451 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A,
453 mem_aperture = 1 << (WINDOW_G(mem_reg) + WINDOW_SHIFT_X);
454 mem_base = PCIEOFST_G(mem_reg) << PCIEOFST_SHIFT_X;
455 if (is_t4(adap->params.chip))
456 mem_base -= adap->t4_bar0;
457 win_pf = is_t4(adap->params.chip) ? 0 : PFNUM_V(adap->pf);
459 /* Calculate our initial PCI-E Memory Window Position and Offset into
462 pos = addr & ~(mem_aperture-1);
465 /* Set up initial PCI-E Memory Window to cover the start of our
466 * transfer. (Read it back to ensure that changes propagate before we
467 * attempt to use the new value.)
470 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, win),
473 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, win));
475 /* Transfer data to/from the adapter as long as there's an integral
476 * number of 32-bit transfers to complete.
478 * A note on Endianness issues:
480 * The "register" reads and writes below from/to the PCI-E Memory
481 * Window invoke the standard adapter Big-Endian to PCI-E Link
482 * Little-Endian "swizzel." As a result, if we have the following
483 * data in adapter memory:
485 * Memory: ... | b0 | b1 | b2 | b3 | ...
486 * Address: i+0 i+1 i+2 i+3
488 * Then a read of the adapter memory via the PCI-E Memory Window
493 * [ b3 | b2 | b1 | b0 ]
495 * If this value is stored into local memory on a Little-Endian system
496 * it will show up correctly in local memory as:
498 * ( ..., b0, b1, b2, b3, ... )
500 * But on a Big-Endian system, the store will show up in memory
501 * incorrectly swizzled as:
503 * ( ..., b3, b2, b1, b0, ... )
505 * So we need to account for this in the reads and writes to the
506 * PCI-E Memory Window below by undoing the register read/write
510 if (dir == T4_MEMORY_READ)
511 *buf++ = le32_to_cpu((__force __le32)t4_read_reg(adap,
514 t4_write_reg(adap, mem_base + offset,
515 (__force u32)cpu_to_le32(*buf++));
516 offset += sizeof(__be32);
517 len -= sizeof(__be32);
519 /* If we've reached the end of our current window aperture,
520 * move the PCI-E Memory Window on to the next. Note that
521 * doing this here after "len" may be 0 allows us to set up
522 * the PCI-E Memory Window for a possible final residual
525 if (offset == mem_aperture) {
529 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A,
532 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A,
537 /* If the original transfer had a length which wasn't a multiple of
538 * 32-bits, now's where we need to finish off the transfer of the
539 * residual amount. The PCI-E Memory Window has already been moved
540 * above (if necessary) to cover this final transfer.
550 if (dir == T4_MEMORY_READ) {
551 last.word = le32_to_cpu(
552 (__force __le32)t4_read_reg(adap,
554 for (bp = (unsigned char *)buf, i = resid; i < 4; i++)
555 bp[i] = last.byte[i];
558 for (i = resid; i < 4; i++)
560 t4_write_reg(adap, mem_base + offset,
561 (__force u32)cpu_to_le32(last.word));
568 /* Return the specified PCI-E Configuration Space register from our Physical
569 * Function. We try first via a Firmware LDST Command since we prefer to let
570 * the firmware own all of these registers, but if that fails we go for it
571 * directly ourselves.
573 u32 t4_read_pcie_cfg4(struct adapter *adap, int reg)
575 u32 val, ldst_addrspace;
577 /* If fw_attach != 0, construct and send the Firmware LDST Command to
578 * retrieve the specified PCI-E Configuration Space register.
580 struct fw_ldst_cmd ldst_cmd;
583 memset(&ldst_cmd, 0, sizeof(ldst_cmd));
584 ldst_addrspace = FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_FUNC_PCIE);
585 ldst_cmd.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
589 ldst_cmd.cycles_to_len16 = cpu_to_be32(FW_LEN16(ldst_cmd));
590 ldst_cmd.u.pcie.select_naccess = FW_LDST_CMD_NACCESS_V(1);
591 ldst_cmd.u.pcie.ctrl_to_fn =
592 (FW_LDST_CMD_LC_F | FW_LDST_CMD_FN_V(adap->pf));
593 ldst_cmd.u.pcie.r = reg;
595 /* If the LDST Command succeeds, return the result, otherwise
596 * fall through to reading it directly ourselves ...
598 ret = t4_wr_mbox(adap, adap->mbox, &ldst_cmd, sizeof(ldst_cmd),
601 val = be32_to_cpu(ldst_cmd.u.pcie.data[0]);
603 /* Read the desired Configuration Space register via the PCI-E
604 * Backdoor mechanism.
606 t4_hw_pci_read_cfg4(adap, reg, &val);
610 /* Get the window based on base passed to it.
611 * Window aperture is currently unhandled, but there is no use case for it
614 static u32 t4_get_window(struct adapter *adap, u32 pci_base, u64 pci_mask,
619 if (is_t4(adap->params.chip)) {
622 /* Truncation intentional: we only read the bottom 32-bits of
623 * the 64-bit BAR0/BAR1 ... We use the hardware backdoor
624 * mechanism to read BAR0 instead of using
625 * pci_resource_start() because we could be operating from
626 * within a Virtual Machine which is trapping our accesses to
627 * our Configuration Space and we need to set up the PCI-E
628 * Memory Window decoders with the actual addresses which will
629 * be coming across the PCI-E link.
631 bar0 = t4_read_pcie_cfg4(adap, pci_base);
633 adap->t4_bar0 = bar0;
635 ret = bar0 + memwin_base;
637 /* For T5, only relative offset inside the PCIe BAR is passed */
643 /* Get the default utility window (win0) used by everyone */
644 u32 t4_get_util_window(struct adapter *adap)
646 return t4_get_window(adap, PCI_BASE_ADDRESS_0,
647 PCI_BASE_ADDRESS_MEM_MASK, MEMWIN0_BASE);
650 /* Set up memory window for accessing adapter memory ranges. (Read
651 * back MA register to ensure that changes propagate before we attempt
652 * to use the new values.)
654 void t4_setup_memwin(struct adapter *adap, u32 memwin_base, u32 window)
657 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A, window),
658 memwin_base | BIR_V(0) |
659 WINDOW_V(ilog2(MEMWIN0_APERTURE) - WINDOW_SHIFT_X));
661 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A, window));
665 * t4_get_regs_len - return the size of the chips register set
666 * @adapter: the adapter
668 * Returns the size of the chip's BAR0 register space.
670 unsigned int t4_get_regs_len(struct adapter *adapter)
672 unsigned int chip_version = CHELSIO_CHIP_VERSION(adapter->params.chip);
674 switch (chip_version) {
676 return T4_REGMAP_SIZE;
680 return T5_REGMAP_SIZE;
683 dev_err(adapter->pdev_dev,
684 "Unsupported chip version %d\n", chip_version);
689 * t4_get_regs - read chip registers into provided buffer
691 * @buf: register buffer
692 * @buf_size: size (in bytes) of register buffer
694 * If the provided register buffer isn't large enough for the chip's
695 * full register range, the register dump will be truncated to the
696 * register buffer's size.
698 void t4_get_regs(struct adapter *adap, void *buf, size_t buf_size)
700 static const unsigned int t4_reg_ranges[] = {
1158 static const unsigned int t5_reg_ranges[] = {
1933 static const unsigned int t6_reg_ranges[] = {
2510 u32 *buf_end = (u32 *)((char *)buf + buf_size);
2511 const unsigned int *reg_ranges;
2512 int reg_ranges_size, range;
2513 unsigned int chip_version = CHELSIO_CHIP_VERSION(adap->params.chip);
2515 /* Select the right set of register ranges to dump depending on the
2516 * adapter chip type.
2518 switch (chip_version) {
2520 reg_ranges = t4_reg_ranges;
2521 reg_ranges_size = ARRAY_SIZE(t4_reg_ranges);
2525 reg_ranges = t5_reg_ranges;
2526 reg_ranges_size = ARRAY_SIZE(t5_reg_ranges);
2530 reg_ranges = t6_reg_ranges;
2531 reg_ranges_size = ARRAY_SIZE(t6_reg_ranges);
2535 dev_err(adap->pdev_dev,
2536 "Unsupported chip version %d\n", chip_version);
2540 /* Clear the register buffer and insert the appropriate register
2541 * values selected by the above register ranges.
2543 memset(buf, 0, buf_size);
2544 for (range = 0; range < reg_ranges_size; range += 2) {
2545 unsigned int reg = reg_ranges[range];
2546 unsigned int last_reg = reg_ranges[range + 1];
2547 u32 *bufp = (u32 *)((char *)buf + reg);
2549 /* Iterate across the register range filling in the register
2550 * buffer but don't write past the end of the register buffer.
2552 while (reg <= last_reg && bufp < buf_end) {
2553 *bufp++ = t4_read_reg(adap, reg);
2559 #define EEPROM_STAT_ADDR 0x7bfc
2560 #define VPD_BASE 0x400
2561 #define VPD_BASE_OLD 0
2562 #define VPD_LEN 1024
2563 #define CHELSIO_VPD_UNIQUE_ID 0x82
2566 * t4_seeprom_wp - enable/disable EEPROM write protection
2567 * @adapter: the adapter
2568 * @enable: whether to enable or disable write protection
2570 * Enables or disables write protection on the serial EEPROM.
2572 int t4_seeprom_wp(struct adapter *adapter, bool enable)
2574 unsigned int v = enable ? 0xc : 0;
2575 int ret = pci_write_vpd(adapter->pdev, EEPROM_STAT_ADDR, 4, &v);
2576 return ret < 0 ? ret : 0;
2580 * t4_get_raw_vpd_params - read VPD parameters from VPD EEPROM
2581 * @adapter: adapter to read
2582 * @p: where to store the parameters
2584 * Reads card parameters stored in VPD EEPROM.
2586 int t4_get_raw_vpd_params(struct adapter *adapter, struct vpd_params *p)
2588 int i, ret = 0, addr;
2591 unsigned int vpdr_len, kw_offset, id_len;
2593 vpd = vmalloc(VPD_LEN);
2597 /* Card information normally starts at VPD_BASE but early cards had
2600 ret = pci_read_vpd(adapter->pdev, VPD_BASE, sizeof(u32), vpd);
2604 /* The VPD shall have a unique identifier specified by the PCI SIG.
2605 * For chelsio adapters, the identifier is 0x82. The first byte of a VPD
2606 * shall be CHELSIO_VPD_UNIQUE_ID (0x82). The VPD programming software
2607 * is expected to automatically put this entry at the
2608 * beginning of the VPD.
2610 addr = *vpd == CHELSIO_VPD_UNIQUE_ID ? VPD_BASE : VPD_BASE_OLD;
2612 ret = pci_read_vpd(adapter->pdev, addr, VPD_LEN, vpd);
2616 if (vpd[0] != PCI_VPD_LRDT_ID_STRING) {
2617 dev_err(adapter->pdev_dev, "missing VPD ID string\n");
2622 id_len = pci_vpd_lrdt_size(vpd);
2623 if (id_len > ID_LEN)
2626 i = pci_vpd_find_tag(vpd, 0, VPD_LEN, PCI_VPD_LRDT_RO_DATA);
2628 dev_err(adapter->pdev_dev, "missing VPD-R section\n");
2633 vpdr_len = pci_vpd_lrdt_size(&vpd[i]);
2634 kw_offset = i + PCI_VPD_LRDT_TAG_SIZE;
2635 if (vpdr_len + kw_offset > VPD_LEN) {
2636 dev_err(adapter->pdev_dev, "bad VPD-R length %u\n", vpdr_len);
2641 #define FIND_VPD_KW(var, name) do { \
2642 var = pci_vpd_find_info_keyword(vpd, kw_offset, vpdr_len, name); \
2644 dev_err(adapter->pdev_dev, "missing VPD keyword " name "\n"); \
2648 var += PCI_VPD_INFO_FLD_HDR_SIZE; \
2651 FIND_VPD_KW(i, "RV");
2652 for (csum = 0; i >= 0; i--)
2656 dev_err(adapter->pdev_dev,
2657 "corrupted VPD EEPROM, actual csum %u\n", csum);
2662 FIND_VPD_KW(ec, "EC");
2663 FIND_VPD_KW(sn, "SN");
2664 FIND_VPD_KW(pn, "PN");
2665 FIND_VPD_KW(na, "NA");
2668 memcpy(p->id, vpd + PCI_VPD_LRDT_TAG_SIZE, id_len);
2670 memcpy(p->ec, vpd + ec, EC_LEN);
2672 i = pci_vpd_info_field_size(vpd + sn - PCI_VPD_INFO_FLD_HDR_SIZE);
2673 memcpy(p->sn, vpd + sn, min(i, SERNUM_LEN));
2675 i = pci_vpd_info_field_size(vpd + pn - PCI_VPD_INFO_FLD_HDR_SIZE);
2676 memcpy(p->pn, vpd + pn, min(i, PN_LEN));
2678 memcpy(p->na, vpd + na, min(i, MACADDR_LEN));
2679 strim((char *)p->na);
2687 * t4_get_vpd_params - read VPD parameters & retrieve Core Clock
2688 * @adapter: adapter to read
2689 * @p: where to store the parameters
2691 * Reads card parameters stored in VPD EEPROM and retrieves the Core
2692 * Clock. This can only be called after a connection to the firmware
2695 int t4_get_vpd_params(struct adapter *adapter, struct vpd_params *p)
2697 u32 cclk_param, cclk_val;
2700 /* Grab the raw VPD parameters.
2702 ret = t4_get_raw_vpd_params(adapter, p);
2706 /* Ask firmware for the Core Clock since it knows how to translate the
2707 * Reference Clock ('V2') VPD field into a Core Clock value ...
2709 cclk_param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
2710 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_CCLK));
2711 ret = t4_query_params(adapter, adapter->mbox, adapter->pf, 0,
2712 1, &cclk_param, &cclk_val);
2721 /* serial flash and firmware constants */
2723 SF_ATTEMPTS = 10, /* max retries for SF operations */
2725 /* flash command opcodes */
2726 SF_PROG_PAGE = 2, /* program page */
2727 SF_WR_DISABLE = 4, /* disable writes */
2728 SF_RD_STATUS = 5, /* read status register */
2729 SF_WR_ENABLE = 6, /* enable writes */
2730 SF_RD_DATA_FAST = 0xb, /* read flash */
2731 SF_RD_ID = 0x9f, /* read ID */
2732 SF_ERASE_SECTOR = 0xd8, /* erase sector */
2734 FW_MAX_SIZE = 16 * SF_SEC_SIZE,
2738 * sf1_read - read data from the serial flash
2739 * @adapter: the adapter
2740 * @byte_cnt: number of bytes to read
2741 * @cont: whether another operation will be chained
2742 * @lock: whether to lock SF for PL access only
2743 * @valp: where to store the read data
2745 * Reads up to 4 bytes of data from the serial flash. The location of
2746 * the read needs to be specified prior to calling this by issuing the
2747 * appropriate commands to the serial flash.
2749 static int sf1_read(struct adapter *adapter, unsigned int byte_cnt, int cont,
2750 int lock, u32 *valp)
2754 if (!byte_cnt || byte_cnt > 4)
2756 if (t4_read_reg(adapter, SF_OP_A) & SF_BUSY_F)
2758 t4_write_reg(adapter, SF_OP_A, SF_LOCK_V(lock) |
2759 SF_CONT_V(cont) | BYTECNT_V(byte_cnt - 1));
2760 ret = t4_wait_op_done(adapter, SF_OP_A, SF_BUSY_F, 0, SF_ATTEMPTS, 5);
2762 *valp = t4_read_reg(adapter, SF_DATA_A);
2767 * sf1_write - write data to the serial flash
2768 * @adapter: the adapter
2769 * @byte_cnt: number of bytes to write
2770 * @cont: whether another operation will be chained
2771 * @lock: whether to lock SF for PL access only
2772 * @val: value to write
2774 * Writes up to 4 bytes of data to the serial flash. The location of
2775 * the write needs to be specified prior to calling this by issuing the
2776 * appropriate commands to the serial flash.
2778 static int sf1_write(struct adapter *adapter, unsigned int byte_cnt, int cont,
2781 if (!byte_cnt || byte_cnt > 4)
2783 if (t4_read_reg(adapter, SF_OP_A) & SF_BUSY_F)
2785 t4_write_reg(adapter, SF_DATA_A, val);
2786 t4_write_reg(adapter, SF_OP_A, SF_LOCK_V(lock) |
2787 SF_CONT_V(cont) | BYTECNT_V(byte_cnt - 1) | OP_V(1));
2788 return t4_wait_op_done(adapter, SF_OP_A, SF_BUSY_F, 0, SF_ATTEMPTS, 5);
2792 * flash_wait_op - wait for a flash operation to complete
2793 * @adapter: the adapter
2794 * @attempts: max number of polls of the status register
2795 * @delay: delay between polls in ms
2797 * Wait for a flash operation to complete by polling the status register.
2799 static int flash_wait_op(struct adapter *adapter, int attempts, int delay)
2805 if ((ret = sf1_write(adapter, 1, 1, 1, SF_RD_STATUS)) != 0 ||
2806 (ret = sf1_read(adapter, 1, 0, 1, &status)) != 0)
2810 if (--attempts == 0)
2818 * t4_read_flash - read words from serial flash
2819 * @adapter: the adapter
2820 * @addr: the start address for the read
2821 * @nwords: how many 32-bit words to read
2822 * @data: where to store the read data
2823 * @byte_oriented: whether to store data as bytes or as words
2825 * Read the specified number of 32-bit words from the serial flash.
2826 * If @byte_oriented is set the read data is stored as a byte array
2827 * (i.e., big-endian), otherwise as 32-bit words in the platform's
2828 * natural endianness.
2830 int t4_read_flash(struct adapter *adapter, unsigned int addr,
2831 unsigned int nwords, u32 *data, int byte_oriented)
2835 if (addr + nwords * sizeof(u32) > adapter->params.sf_size || (addr & 3))
2838 addr = swab32(addr) | SF_RD_DATA_FAST;
2840 if ((ret = sf1_write(adapter, 4, 1, 0, addr)) != 0 ||
2841 (ret = sf1_read(adapter, 1, 1, 0, data)) != 0)
2844 for ( ; nwords; nwords--, data++) {
2845 ret = sf1_read(adapter, 4, nwords > 1, nwords == 1, data);
2847 t4_write_reg(adapter, SF_OP_A, 0); /* unlock SF */
2851 *data = (__force __u32)(cpu_to_be32(*data));
2857 * t4_write_flash - write up to a page of data to the serial flash
2858 * @adapter: the adapter
2859 * @addr: the start address to write
2860 * @n: length of data to write in bytes
2861 * @data: the data to write
2863 * Writes up to a page of data (256 bytes) to the serial flash starting
2864 * at the given address. All the data must be written to the same page.
2866 static int t4_write_flash(struct adapter *adapter, unsigned int addr,
2867 unsigned int n, const u8 *data)
2871 unsigned int i, c, left, val, offset = addr & 0xff;
2873 if (addr >= adapter->params.sf_size || offset + n > SF_PAGE_SIZE)
2876 val = swab32(addr) | SF_PROG_PAGE;
2878 if ((ret = sf1_write(adapter, 1, 0, 1, SF_WR_ENABLE)) != 0 ||
2879 (ret = sf1_write(adapter, 4, 1, 1, val)) != 0)
2882 for (left = n; left; left -= c) {
2884 for (val = 0, i = 0; i < c; ++i)
2885 val = (val << 8) + *data++;
2887 ret = sf1_write(adapter, c, c != left, 1, val);
2891 ret = flash_wait_op(adapter, 8, 1);
2895 t4_write_reg(adapter, SF_OP_A, 0); /* unlock SF */
2897 /* Read the page to verify the write succeeded */
2898 ret = t4_read_flash(adapter, addr & ~0xff, ARRAY_SIZE(buf), buf, 1);
2902 if (memcmp(data - n, (u8 *)buf + offset, n)) {
2903 dev_err(adapter->pdev_dev,
2904 "failed to correctly write the flash page at %#x\n",
2911 t4_write_reg(adapter, SF_OP_A, 0); /* unlock SF */
2916 * t4_get_fw_version - read the firmware version
2917 * @adapter: the adapter
2918 * @vers: where to place the version
2920 * Reads the FW version from flash.
2922 int t4_get_fw_version(struct adapter *adapter, u32 *vers)
2924 return t4_read_flash(adapter, FLASH_FW_START +
2925 offsetof(struct fw_hdr, fw_ver), 1,
2930 * t4_get_tp_version - read the TP microcode version
2931 * @adapter: the adapter
2932 * @vers: where to place the version
2934 * Reads the TP microcode version from flash.
2936 int t4_get_tp_version(struct adapter *adapter, u32 *vers)
2938 return t4_read_flash(adapter, FLASH_FW_START +
2939 offsetof(struct fw_hdr, tp_microcode_ver),
2944 * t4_get_exprom_version - return the Expansion ROM version (if any)
2945 * @adapter: the adapter
2946 * @vers: where to place the version
2948 * Reads the Expansion ROM header from FLASH and returns the version
2949 * number (if present) through the @vers return value pointer. We return
2950 * this in the Firmware Version Format since it's convenient. Return
2951 * 0 on success, -ENOENT if no Expansion ROM is present.
2953 int t4_get_exprom_version(struct adapter *adap, u32 *vers)
2955 struct exprom_header {
2956 unsigned char hdr_arr[16]; /* must start with 0x55aa */
2957 unsigned char hdr_ver[4]; /* Expansion ROM version */
2959 u32 exprom_header_buf[DIV_ROUND_UP(sizeof(struct exprom_header),
2963 ret = t4_read_flash(adap, FLASH_EXP_ROM_START,
2964 ARRAY_SIZE(exprom_header_buf), exprom_header_buf,
2969 hdr = (struct exprom_header *)exprom_header_buf;
2970 if (hdr->hdr_arr[0] != 0x55 || hdr->hdr_arr[1] != 0xaa)
2973 *vers = (FW_HDR_FW_VER_MAJOR_V(hdr->hdr_ver[0]) |
2974 FW_HDR_FW_VER_MINOR_V(hdr->hdr_ver[1]) |
2975 FW_HDR_FW_VER_MICRO_V(hdr->hdr_ver[2]) |
2976 FW_HDR_FW_VER_BUILD_V(hdr->hdr_ver[3]));
2981 * t4_check_fw_version - check if the FW is supported with this driver
2982 * @adap: the adapter
2984 * Checks if an adapter's FW is compatible with the driver. Returns 0
2985 * if there's exact match, a negative error if the version could not be
2986 * read or there's a major version mismatch
2988 int t4_check_fw_version(struct adapter *adap)
2990 int i, ret, major, minor, micro;
2991 int exp_major, exp_minor, exp_micro;
2992 unsigned int chip_version = CHELSIO_CHIP_VERSION(adap->params.chip);
2994 ret = t4_get_fw_version(adap, &adap->params.fw_vers);
2995 /* Try multiple times before returning error */
2996 for (i = 0; (ret == -EBUSY || ret == -EAGAIN) && i < 3; i++)
2997 ret = t4_get_fw_version(adap, &adap->params.fw_vers);
3002 major = FW_HDR_FW_VER_MAJOR_G(adap->params.fw_vers);
3003 minor = FW_HDR_FW_VER_MINOR_G(adap->params.fw_vers);
3004 micro = FW_HDR_FW_VER_MICRO_G(adap->params.fw_vers);
3006 switch (chip_version) {
3008 exp_major = T4FW_MIN_VERSION_MAJOR;
3009 exp_minor = T4FW_MIN_VERSION_MINOR;
3010 exp_micro = T4FW_MIN_VERSION_MICRO;
3013 exp_major = T5FW_MIN_VERSION_MAJOR;
3014 exp_minor = T5FW_MIN_VERSION_MINOR;
3015 exp_micro = T5FW_MIN_VERSION_MICRO;
3018 exp_major = T6FW_MIN_VERSION_MAJOR;
3019 exp_minor = T6FW_MIN_VERSION_MINOR;
3020 exp_micro = T6FW_MIN_VERSION_MICRO;
3023 dev_err(adap->pdev_dev, "Unsupported chip type, %x\n",
3028 if (major < exp_major || (major == exp_major && minor < exp_minor) ||
3029 (major == exp_major && minor == exp_minor && micro < exp_micro)) {
3030 dev_err(adap->pdev_dev,
3031 "Card has firmware version %u.%u.%u, minimum "
3032 "supported firmware is %u.%u.%u.\n", major, minor,
3033 micro, exp_major, exp_minor, exp_micro);
3039 /* Is the given firmware API compatible with the one the driver was compiled
3042 static int fw_compatible(const struct fw_hdr *hdr1, const struct fw_hdr *hdr2)
3045 /* short circuit if it's the exact same firmware version */
3046 if (hdr1->chip == hdr2->chip && hdr1->fw_ver == hdr2->fw_ver)
3049 #define SAME_INTF(x) (hdr1->intfver_##x == hdr2->intfver_##x)
3050 if (hdr1->chip == hdr2->chip && SAME_INTF(nic) && SAME_INTF(vnic) &&
3051 SAME_INTF(ri) && SAME_INTF(iscsi) && SAME_INTF(fcoe))
3058 /* The firmware in the filesystem is usable, but should it be installed?
3059 * This routine explains itself in detail if it indicates the filesystem
3060 * firmware should be installed.
3062 static int should_install_fs_fw(struct adapter *adap, int card_fw_usable,
3067 if (!card_fw_usable) {
3068 reason = "incompatible or unusable";
3073 reason = "older than the version supported with this driver";
3080 dev_err(adap->pdev_dev, "firmware on card (%u.%u.%u.%u) is %s, "
3081 "installing firmware %u.%u.%u.%u on card.\n",
3082 FW_HDR_FW_VER_MAJOR_G(c), FW_HDR_FW_VER_MINOR_G(c),
3083 FW_HDR_FW_VER_MICRO_G(c), FW_HDR_FW_VER_BUILD_G(c), reason,
3084 FW_HDR_FW_VER_MAJOR_G(k), FW_HDR_FW_VER_MINOR_G(k),
3085 FW_HDR_FW_VER_MICRO_G(k), FW_HDR_FW_VER_BUILD_G(k));
3090 int t4_prep_fw(struct adapter *adap, struct fw_info *fw_info,
3091 const u8 *fw_data, unsigned int fw_size,
3092 struct fw_hdr *card_fw, enum dev_state state,
3095 int ret, card_fw_usable, fs_fw_usable;
3096 const struct fw_hdr *fs_fw;
3097 const struct fw_hdr *drv_fw;
3099 drv_fw = &fw_info->fw_hdr;
3101 /* Read the header of the firmware on the card */
3102 ret = -t4_read_flash(adap, FLASH_FW_START,
3103 sizeof(*card_fw) / sizeof(uint32_t),
3104 (uint32_t *)card_fw, 1);
3106 card_fw_usable = fw_compatible(drv_fw, (const void *)card_fw);
3108 dev_err(adap->pdev_dev,
3109 "Unable to read card's firmware header: %d\n", ret);
3113 if (fw_data != NULL) {
3114 fs_fw = (const void *)fw_data;
3115 fs_fw_usable = fw_compatible(drv_fw, fs_fw);
3121 if (card_fw_usable && card_fw->fw_ver == drv_fw->fw_ver &&
3122 (!fs_fw_usable || fs_fw->fw_ver == drv_fw->fw_ver)) {
3123 /* Common case: the firmware on the card is an exact match and
3124 * the filesystem one is an exact match too, or the filesystem
3125 * one is absent/incompatible.
3127 } else if (fs_fw_usable && state == DEV_STATE_UNINIT &&
3128 should_install_fs_fw(adap, card_fw_usable,
3129 be32_to_cpu(fs_fw->fw_ver),
3130 be32_to_cpu(card_fw->fw_ver))) {
3131 ret = -t4_fw_upgrade(adap, adap->mbox, fw_data,
3134 dev_err(adap->pdev_dev,
3135 "failed to install firmware: %d\n", ret);
3139 /* Installed successfully, update the cached header too. */
3142 *reset = 0; /* already reset as part of load_fw */
3145 if (!card_fw_usable) {
3148 d = be32_to_cpu(drv_fw->fw_ver);
3149 c = be32_to_cpu(card_fw->fw_ver);
3150 k = fs_fw ? be32_to_cpu(fs_fw->fw_ver) : 0;
3152 dev_err(adap->pdev_dev, "Cannot find a usable firmware: "
3154 "driver compiled with %d.%d.%d.%d, "
3155 "card has %d.%d.%d.%d, filesystem has %d.%d.%d.%d\n",
3157 FW_HDR_FW_VER_MAJOR_G(d), FW_HDR_FW_VER_MINOR_G(d),
3158 FW_HDR_FW_VER_MICRO_G(d), FW_HDR_FW_VER_BUILD_G(d),
3159 FW_HDR_FW_VER_MAJOR_G(c), FW_HDR_FW_VER_MINOR_G(c),
3160 FW_HDR_FW_VER_MICRO_G(c), FW_HDR_FW_VER_BUILD_G(c),
3161 FW_HDR_FW_VER_MAJOR_G(k), FW_HDR_FW_VER_MINOR_G(k),
3162 FW_HDR_FW_VER_MICRO_G(k), FW_HDR_FW_VER_BUILD_G(k));
3167 /* We're using whatever's on the card and it's known to be good. */
3168 adap->params.fw_vers = be32_to_cpu(card_fw->fw_ver);
3169 adap->params.tp_vers = be32_to_cpu(card_fw->tp_microcode_ver);
3176 * t4_flash_erase_sectors - erase a range of flash sectors
3177 * @adapter: the adapter
3178 * @start: the first sector to erase
3179 * @end: the last sector to erase
3181 * Erases the sectors in the given inclusive range.
3183 static int t4_flash_erase_sectors(struct adapter *adapter, int start, int end)
3187 if (end >= adapter->params.sf_nsec)
3190 while (start <= end) {
3191 if ((ret = sf1_write(adapter, 1, 0, 1, SF_WR_ENABLE)) != 0 ||
3192 (ret = sf1_write(adapter, 4, 0, 1,
3193 SF_ERASE_SECTOR | (start << 8))) != 0 ||
3194 (ret = flash_wait_op(adapter, 14, 500)) != 0) {
3195 dev_err(adapter->pdev_dev,
3196 "erase of flash sector %d failed, error %d\n",
3202 t4_write_reg(adapter, SF_OP_A, 0); /* unlock SF */
3207 * t4_flash_cfg_addr - return the address of the flash configuration file
3208 * @adapter: the adapter
3210 * Return the address within the flash where the Firmware Configuration
3213 unsigned int t4_flash_cfg_addr(struct adapter *adapter)
3215 if (adapter->params.sf_size == 0x100000)
3216 return FLASH_FPGA_CFG_START;
3218 return FLASH_CFG_START;
3221 /* Return TRUE if the specified firmware matches the adapter. I.e. T4
3222 * firmware for T4 adapters, T5 firmware for T5 adapters, etc. We go ahead
3223 * and emit an error message for mismatched firmware to save our caller the
3226 static bool t4_fw_matches_chip(const struct adapter *adap,
3227 const struct fw_hdr *hdr)
3229 /* The expression below will return FALSE for any unsupported adapter
3230 * which will keep us "honest" in the future ...
3232 if ((is_t4(adap->params.chip) && hdr->chip == FW_HDR_CHIP_T4) ||
3233 (is_t5(adap->params.chip) && hdr->chip == FW_HDR_CHIP_T5) ||
3234 (is_t6(adap->params.chip) && hdr->chip == FW_HDR_CHIP_T6))
3237 dev_err(adap->pdev_dev,
3238 "FW image (%d) is not suitable for this adapter (%d)\n",
3239 hdr->chip, CHELSIO_CHIP_VERSION(adap->params.chip));
3244 * t4_load_fw - download firmware
3245 * @adap: the adapter
3246 * @fw_data: the firmware image to write
3249 * Write the supplied firmware image to the card's serial flash.
3251 int t4_load_fw(struct adapter *adap, const u8 *fw_data, unsigned int size)
3256 u8 first_page[SF_PAGE_SIZE];
3257 const __be32 *p = (const __be32 *)fw_data;
3258 const struct fw_hdr *hdr = (const struct fw_hdr *)fw_data;
3259 unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec;
3260 unsigned int fw_img_start = adap->params.sf_fw_start;
3261 unsigned int fw_start_sec = fw_img_start / sf_sec_size;
3264 dev_err(adap->pdev_dev, "FW image has no data\n");
3268 dev_err(adap->pdev_dev,
3269 "FW image size not multiple of 512 bytes\n");
3272 if ((unsigned int)be16_to_cpu(hdr->len512) * 512 != size) {
3273 dev_err(adap->pdev_dev,
3274 "FW image size differs from size in FW header\n");
3277 if (size > FW_MAX_SIZE) {
3278 dev_err(adap->pdev_dev, "FW image too large, max is %u bytes\n",
3282 if (!t4_fw_matches_chip(adap, hdr))
3285 for (csum = 0, i = 0; i < size / sizeof(csum); i++)
3286 csum += be32_to_cpu(p[i]);
3288 if (csum != 0xffffffff) {
3289 dev_err(adap->pdev_dev,
3290 "corrupted firmware image, checksum %#x\n", csum);
3294 i = DIV_ROUND_UP(size, sf_sec_size); /* # of sectors spanned */
3295 ret = t4_flash_erase_sectors(adap, fw_start_sec, fw_start_sec + i - 1);
3300 * We write the correct version at the end so the driver can see a bad
3301 * version if the FW write fails. Start by writing a copy of the
3302 * first page with a bad version.
3304 memcpy(first_page, fw_data, SF_PAGE_SIZE);
3305 ((struct fw_hdr *)first_page)->fw_ver = cpu_to_be32(0xffffffff);
3306 ret = t4_write_flash(adap, fw_img_start, SF_PAGE_SIZE, first_page);
3310 addr = fw_img_start;
3311 for (size -= SF_PAGE_SIZE; size; size -= SF_PAGE_SIZE) {
3312 addr += SF_PAGE_SIZE;
3313 fw_data += SF_PAGE_SIZE;
3314 ret = t4_write_flash(adap, addr, SF_PAGE_SIZE, fw_data);
3319 ret = t4_write_flash(adap,
3320 fw_img_start + offsetof(struct fw_hdr, fw_ver),
3321 sizeof(hdr->fw_ver), (const u8 *)&hdr->fw_ver);
3324 dev_err(adap->pdev_dev, "firmware download failed, error %d\n",
3327 ret = t4_get_fw_version(adap, &adap->params.fw_vers);
3332 * t4_phy_fw_ver - return current PHY firmware version
3333 * @adap: the adapter
3334 * @phy_fw_ver: return value buffer for PHY firmware version
3336 * Returns the current version of external PHY firmware on the
3339 int t4_phy_fw_ver(struct adapter *adap, int *phy_fw_ver)
3344 param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3345 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_PHYFW) |
3346 FW_PARAMS_PARAM_Y_V(adap->params.portvec) |
3347 FW_PARAMS_PARAM_Z_V(FW_PARAMS_PARAM_DEV_PHYFW_VERSION));
3348 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1,
3357 * t4_load_phy_fw - download port PHY firmware
3358 * @adap: the adapter
3359 * @win: the PCI-E Memory Window index to use for t4_memory_rw()
3360 * @win_lock: the lock to use to guard the memory copy
3361 * @phy_fw_version: function to check PHY firmware versions
3362 * @phy_fw_data: the PHY firmware image to write
3363 * @phy_fw_size: image size
3365 * Transfer the specified PHY firmware to the adapter. If a non-NULL
3366 * @phy_fw_version is supplied, then it will be used to determine if
3367 * it's necessary to perform the transfer by comparing the version
3368 * of any existing adapter PHY firmware with that of the passed in
3369 * PHY firmware image. If @win_lock is non-NULL then it will be used
3370 * around the call to t4_memory_rw() which transfers the PHY firmware
3373 * A negative error number will be returned if an error occurs. If
3374 * version number support is available and there's no need to upgrade
3375 * the firmware, 0 will be returned. If firmware is successfully
3376 * transferred to the adapter, 1 will be retured.
3378 * NOTE: some adapters only have local RAM to store the PHY firmware. As
3379 * a result, a RESET of the adapter would cause that RAM to lose its
3380 * contents. Thus, loading PHY firmware on such adapters must happen
3381 * after any FW_RESET_CMDs ...
3383 int t4_load_phy_fw(struct adapter *adap,
3384 int win, spinlock_t *win_lock,
3385 int (*phy_fw_version)(const u8 *, size_t),
3386 const u8 *phy_fw_data, size_t phy_fw_size)
3388 unsigned long mtype = 0, maddr = 0;
3390 int cur_phy_fw_ver = 0, new_phy_fw_vers = 0;
3393 /* If we have version number support, then check to see if the adapter
3394 * already has up-to-date PHY firmware loaded.
3396 if (phy_fw_version) {
3397 new_phy_fw_vers = phy_fw_version(phy_fw_data, phy_fw_size);
3398 ret = t4_phy_fw_ver(adap, &cur_phy_fw_ver);
3402 if (cur_phy_fw_ver >= new_phy_fw_vers) {
3403 CH_WARN(adap, "PHY Firmware already up-to-date, "
3404 "version %#x\n", cur_phy_fw_ver);
3409 /* Ask the firmware where it wants us to copy the PHY firmware image.
3410 * The size of the file requires a special version of the READ coommand
3411 * which will pass the file size via the values field in PARAMS_CMD and
3412 * retrieve the return value from firmware and place it in the same
3415 param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3416 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_PHYFW) |
3417 FW_PARAMS_PARAM_Y_V(adap->params.portvec) |
3418 FW_PARAMS_PARAM_Z_V(FW_PARAMS_PARAM_DEV_PHYFW_DOWNLOAD));
3420 ret = t4_query_params_rw(adap, adap->mbox, adap->pf, 0, 1,
3425 maddr = (val & 0xff) << 16;
3427 /* Copy the supplied PHY Firmware image to the adapter memory location
3428 * allocated by the adapter firmware.
3431 spin_lock_bh(win_lock);
3432 ret = t4_memory_rw(adap, win, mtype, maddr,
3433 phy_fw_size, (__be32 *)phy_fw_data,
3436 spin_unlock_bh(win_lock);
3440 /* Tell the firmware that the PHY firmware image has been written to
3441 * RAM and it can now start copying it over to the PHYs. The chip
3442 * firmware will RESET the affected PHYs as part of this operation
3443 * leaving them running the new PHY firmware image.
3445 param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3446 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_PHYFW) |
3447 FW_PARAMS_PARAM_Y_V(adap->params.portvec) |
3448 FW_PARAMS_PARAM_Z_V(FW_PARAMS_PARAM_DEV_PHYFW_DOWNLOAD));
3449 ret = t4_set_params_timeout(adap, adap->mbox, adap->pf, 0, 1,
3450 ¶m, &val, 30000);
3452 /* If we have version number support, then check to see that the new
3453 * firmware got loaded properly.
3455 if (phy_fw_version) {
3456 ret = t4_phy_fw_ver(adap, &cur_phy_fw_ver);
3460 if (cur_phy_fw_ver != new_phy_fw_vers) {
3461 CH_WARN(adap, "PHY Firmware did not update: "
3462 "version on adapter %#x, "
3463 "version flashed %#x\n",
3464 cur_phy_fw_ver, new_phy_fw_vers);
3473 * t4_fwcache - firmware cache operation
3474 * @adap: the adapter
3475 * @op : the operation (flush or flush and invalidate)
3477 int t4_fwcache(struct adapter *adap, enum fw_params_param_dev_fwcache op)
3479 struct fw_params_cmd c;
3481 memset(&c, 0, sizeof(c));
3483 cpu_to_be32(FW_CMD_OP_V(FW_PARAMS_CMD) |
3484 FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
3485 FW_PARAMS_CMD_PFN_V(adap->pf) |
3486 FW_PARAMS_CMD_VFN_V(0));
3487 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
3489 cpu_to_be32(FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3490 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_FWCACHE));
3491 c.param[0].val = (__force __be32)op;
3493 return t4_wr_mbox(adap, adap->mbox, &c, sizeof(c), NULL);
3496 void t4_cim_read_pif_la(struct adapter *adap, u32 *pif_req, u32 *pif_rsp,
3497 unsigned int *pif_req_wrptr,
3498 unsigned int *pif_rsp_wrptr)
3501 u32 cfg, val, req, rsp;
3503 cfg = t4_read_reg(adap, CIM_DEBUGCFG_A);
3504 if (cfg & LADBGEN_F)
3505 t4_write_reg(adap, CIM_DEBUGCFG_A, cfg ^ LADBGEN_F);
3507 val = t4_read_reg(adap, CIM_DEBUGSTS_A);
3508 req = POLADBGWRPTR_G(val);
3509 rsp = PILADBGWRPTR_G(val);
3511 *pif_req_wrptr = req;
3513 *pif_rsp_wrptr = rsp;
3515 for (i = 0; i < CIM_PIFLA_SIZE; i++) {
3516 for (j = 0; j < 6; j++) {
3517 t4_write_reg(adap, CIM_DEBUGCFG_A, POLADBGRDPTR_V(req) |
3518 PILADBGRDPTR_V(rsp));
3519 *pif_req++ = t4_read_reg(adap, CIM_PO_LA_DEBUGDATA_A);
3520 *pif_rsp++ = t4_read_reg(adap, CIM_PI_LA_DEBUGDATA_A);
3524 req = (req + 2) & POLADBGRDPTR_M;
3525 rsp = (rsp + 2) & PILADBGRDPTR_M;
3527 t4_write_reg(adap, CIM_DEBUGCFG_A, cfg);
3530 void t4_cim_read_ma_la(struct adapter *adap, u32 *ma_req, u32 *ma_rsp)
3535 cfg = t4_read_reg(adap, CIM_DEBUGCFG_A);
3536 if (cfg & LADBGEN_F)
3537 t4_write_reg(adap, CIM_DEBUGCFG_A, cfg ^ LADBGEN_F);
3539 for (i = 0; i < CIM_MALA_SIZE; i++) {
3540 for (j = 0; j < 5; j++) {
3542 t4_write_reg(adap, CIM_DEBUGCFG_A, POLADBGRDPTR_V(idx) |
3543 PILADBGRDPTR_V(idx));
3544 *ma_req++ = t4_read_reg(adap, CIM_PO_LA_MADEBUGDATA_A);
3545 *ma_rsp++ = t4_read_reg(adap, CIM_PI_LA_MADEBUGDATA_A);
3548 t4_write_reg(adap, CIM_DEBUGCFG_A, cfg);
3551 void t4_ulprx_read_la(struct adapter *adap, u32 *la_buf)
3555 for (i = 0; i < 8; i++) {
3556 u32 *p = la_buf + i;
3558 t4_write_reg(adap, ULP_RX_LA_CTL_A, i);
3559 j = t4_read_reg(adap, ULP_RX_LA_WRPTR_A);
3560 t4_write_reg(adap, ULP_RX_LA_RDPTR_A, j);
3561 for (j = 0; j < ULPRX_LA_SIZE; j++, p += 8)
3562 *p = t4_read_reg(adap, ULP_RX_LA_RDDATA_A);
3566 #define ADVERT_MASK (FW_PORT_CAP_SPEED_100M | FW_PORT_CAP_SPEED_1G |\
3567 FW_PORT_CAP_SPEED_10G | FW_PORT_CAP_SPEED_40G | \
3571 * t4_link_l1cfg - apply link configuration to MAC/PHY
3572 * @phy: the PHY to setup
3573 * @mac: the MAC to setup
3574 * @lc: the requested link configuration
3576 * Set up a port's MAC and PHY according to a desired link configuration.
3577 * - If the PHY can auto-negotiate first decide what to advertise, then
3578 * enable/disable auto-negotiation as desired, and reset.
3579 * - If the PHY does not auto-negotiate just reset it.
3580 * - If auto-negotiation is off set the MAC to the proper speed/duplex/FC,
3581 * otherwise do it later based on the outcome of auto-negotiation.
3583 int t4_link_l1cfg(struct adapter *adap, unsigned int mbox, unsigned int port,
3584 struct link_config *lc)
3586 struct fw_port_cmd c;
3587 unsigned int fc = 0, mdi = FW_PORT_CAP_MDI_V(FW_PORT_CAP_MDI_AUTO);
3590 if (lc->requested_fc & PAUSE_RX)
3591 fc |= FW_PORT_CAP_FC_RX;
3592 if (lc->requested_fc & PAUSE_TX)
3593 fc |= FW_PORT_CAP_FC_TX;
3595 memset(&c, 0, sizeof(c));
3596 c.op_to_portid = cpu_to_be32(FW_CMD_OP_V(FW_PORT_CMD) |
3597 FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
3598 FW_PORT_CMD_PORTID_V(port));
3600 cpu_to_be32(FW_PORT_CMD_ACTION_V(FW_PORT_ACTION_L1_CFG) |
3603 if (!(lc->supported & FW_PORT_CAP_ANEG)) {
3604 c.u.l1cfg.rcap = cpu_to_be32((lc->supported & ADVERT_MASK) |
3606 lc->fc = lc->requested_fc & (PAUSE_RX | PAUSE_TX);
3607 } else if (lc->autoneg == AUTONEG_DISABLE) {
3608 c.u.l1cfg.rcap = cpu_to_be32(lc->requested_speed | fc | mdi);
3609 lc->fc = lc->requested_fc & (PAUSE_RX | PAUSE_TX);
3611 c.u.l1cfg.rcap = cpu_to_be32(lc->advertising | fc | mdi);
3613 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
3617 * t4_restart_aneg - restart autonegotiation
3618 * @adap: the adapter
3619 * @mbox: mbox to use for the FW command
3620 * @port: the port id
3622 * Restarts autonegotiation for the selected port.
3624 int t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port)
3626 struct fw_port_cmd c;
3628 memset(&c, 0, sizeof(c));
3629 c.op_to_portid = cpu_to_be32(FW_CMD_OP_V(FW_PORT_CMD) |
3630 FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
3631 FW_PORT_CMD_PORTID_V(port));
3633 cpu_to_be32(FW_PORT_CMD_ACTION_V(FW_PORT_ACTION_L1_CFG) |
3635 c.u.l1cfg.rcap = cpu_to_be32(FW_PORT_CAP_ANEG);
3636 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
3639 typedef void (*int_handler_t)(struct adapter *adap);
3642 unsigned int mask; /* bits to check in interrupt status */
3643 const char *msg; /* message to print or NULL */
3644 short stat_idx; /* stat counter to increment or -1 */
3645 unsigned short fatal; /* whether the condition reported is fatal */
3646 int_handler_t int_handler; /* platform-specific int handler */
3650 * t4_handle_intr_status - table driven interrupt handler
3651 * @adapter: the adapter that generated the interrupt
3652 * @reg: the interrupt status register to process
3653 * @acts: table of interrupt actions
3655 * A table driven interrupt handler that applies a set of masks to an
3656 * interrupt status word and performs the corresponding actions if the
3657 * interrupts described by the mask have occurred. The actions include
3658 * optionally emitting a warning or alert message. The table is terminated
3659 * by an entry specifying mask 0. Returns the number of fatal interrupt
3662 static int t4_handle_intr_status(struct adapter *adapter, unsigned int reg,
3663 const struct intr_info *acts)
3666 unsigned int mask = 0;
3667 unsigned int status = t4_read_reg(adapter, reg);
3669 for ( ; acts->mask; ++acts) {
3670 if (!(status & acts->mask))
3674 dev_alert(adapter->pdev_dev, "%s (0x%x)\n", acts->msg,
3675 status & acts->mask);
3676 } else if (acts->msg && printk_ratelimit())
3677 dev_warn(adapter->pdev_dev, "%s (0x%x)\n", acts->msg,
3678 status & acts->mask);
3679 if (acts->int_handler)
3680 acts->int_handler(adapter);
3684 if (status) /* clear processed interrupts */
3685 t4_write_reg(adapter, reg, status);
3690 * Interrupt handler for the PCIE module.
3692 static void pcie_intr_handler(struct adapter *adapter)
3694 static const struct intr_info sysbus_intr_info[] = {
3695 { RNPP_F, "RXNP array parity error", -1, 1 },
3696 { RPCP_F, "RXPC array parity error", -1, 1 },
3697 { RCIP_F, "RXCIF array parity error", -1, 1 },
3698 { RCCP_F, "Rx completions control array parity error", -1, 1 },
3699 { RFTP_F, "RXFT array parity error", -1, 1 },
3702 static const struct intr_info pcie_port_intr_info[] = {
3703 { TPCP_F, "TXPC array parity error", -1, 1 },
3704 { TNPP_F, "TXNP array parity error", -1, 1 },
3705 { TFTP_F, "TXFT array parity error", -1, 1 },
3706 { TCAP_F, "TXCA array parity error", -1, 1 },
3707 { TCIP_F, "TXCIF array parity error", -1, 1 },
3708 { RCAP_F, "RXCA array parity error", -1, 1 },
3709 { OTDD_F, "outbound request TLP discarded", -1, 1 },
3710 { RDPE_F, "Rx data parity error", -1, 1 },
3711 { TDUE_F, "Tx uncorrectable data error", -1, 1 },
3714 static const struct intr_info pcie_intr_info[] = {
3715 { MSIADDRLPERR_F, "MSI AddrL parity error", -1, 1 },
3716 { MSIADDRHPERR_F, "MSI AddrH parity error", -1, 1 },
3717 { MSIDATAPERR_F, "MSI data parity error", -1, 1 },
3718 { MSIXADDRLPERR_F, "MSI-X AddrL parity error", -1, 1 },
3719 { MSIXADDRHPERR_F, "MSI-X AddrH parity error", -1, 1 },
3720 { MSIXDATAPERR_F, "MSI-X data parity error", -1, 1 },
3721 { MSIXDIPERR_F, "MSI-X DI parity error", -1, 1 },
3722 { PIOCPLPERR_F, "PCI PIO completion FIFO parity error", -1, 1 },
3723 { PIOREQPERR_F, "PCI PIO request FIFO parity error", -1, 1 },
3724 { TARTAGPERR_F, "PCI PCI target tag FIFO parity error", -1, 1 },
3725 { CCNTPERR_F, "PCI CMD channel count parity error", -1, 1 },
3726 { CREQPERR_F, "PCI CMD channel request parity error", -1, 1 },
3727 { CRSPPERR_F, "PCI CMD channel response parity error", -1, 1 },
3728 { DCNTPERR_F, "PCI DMA channel count parity error", -1, 1 },
3729 { DREQPERR_F, "PCI DMA channel request parity error", -1, 1 },
3730 { DRSPPERR_F, "PCI DMA channel response parity error", -1, 1 },
3731 { HCNTPERR_F, "PCI HMA channel count parity error", -1, 1 },
3732 { HREQPERR_F, "PCI HMA channel request parity error", -1, 1 },
3733 { HRSPPERR_F, "PCI HMA channel response parity error", -1, 1 },
3734 { CFGSNPPERR_F, "PCI config snoop FIFO parity error", -1, 1 },
3735 { FIDPERR_F, "PCI FID parity error", -1, 1 },
3736 { INTXCLRPERR_F, "PCI INTx clear parity error", -1, 1 },
3737 { MATAGPERR_F, "PCI MA tag parity error", -1, 1 },
3738 { PIOTAGPERR_F, "PCI PIO tag parity error", -1, 1 },
3739 { RXCPLPERR_F, "PCI Rx completion parity error", -1, 1 },
3740 { RXWRPERR_F, "PCI Rx write parity error", -1, 1 },
3741 { RPLPERR_F, "PCI replay buffer parity error", -1, 1 },
3742 { PCIESINT_F, "PCI core secondary fault", -1, 1 },
3743 { PCIEPINT_F, "PCI core primary fault", -1, 1 },
3744 { UNXSPLCPLERR_F, "PCI unexpected split completion error",
3749 static struct intr_info t5_pcie_intr_info[] = {
3750 { MSTGRPPERR_F, "Master Response Read Queue parity error",
3752 { MSTTIMEOUTPERR_F, "Master Timeout FIFO parity error", -1, 1 },
3753 { MSIXSTIPERR_F, "MSI-X STI SRAM parity error", -1, 1 },
3754 { MSIXADDRLPERR_F, "MSI-X AddrL parity error", -1, 1 },
3755 { MSIXADDRHPERR_F, "MSI-X AddrH parity error", -1, 1 },
3756 { MSIXDATAPERR_F, "MSI-X data parity error", -1, 1 },
3757 { MSIXDIPERR_F, "MSI-X DI parity error", -1, 1 },
3758 { PIOCPLGRPPERR_F, "PCI PIO completion Group FIFO parity error",
3760 { PIOREQGRPPERR_F, "PCI PIO request Group FIFO parity error",
3762 { TARTAGPERR_F, "PCI PCI target tag FIFO parity error", -1, 1 },
3763 { MSTTAGQPERR_F, "PCI master tag queue parity error", -1, 1 },
3764 { CREQPERR_F, "PCI CMD channel request parity error", -1, 1 },
3765 { CRSPPERR_F, "PCI CMD channel response parity error", -1, 1 },
3766 { DREQWRPERR_F, "PCI DMA channel write request parity error",
3768 { DREQPERR_F, "PCI DMA channel request parity error", -1, 1 },
3769 { DRSPPERR_F, "PCI DMA channel response parity error", -1, 1 },
3770 { HREQWRPERR_F, "PCI HMA channel count parity error", -1, 1 },
3771 { HREQPERR_F, "PCI HMA channel request parity error", -1, 1 },
3772 { HRSPPERR_F, "PCI HMA channel response parity error", -1, 1 },
3773 { CFGSNPPERR_F, "PCI config snoop FIFO parity error", -1, 1 },
3774 { FIDPERR_F, "PCI FID parity error", -1, 1 },
3775 { VFIDPERR_F, "PCI INTx clear parity error", -1, 1 },
3776 { MAGRPPERR_F, "PCI MA group FIFO parity error", -1, 1 },
3777 { PIOTAGPERR_F, "PCI PIO tag parity error", -1, 1 },
3778 { IPRXHDRGRPPERR_F, "PCI IP Rx header group parity error",
3780 { IPRXDATAGRPPERR_F, "PCI IP Rx data group parity error",
3782 { RPLPERR_F, "PCI IP replay buffer parity error", -1, 1 },
3783 { IPSOTPERR_F, "PCI IP SOT buffer parity error", -1, 1 },
3784 { TRGT1GRPPERR_F, "PCI TRGT1 group FIFOs parity error", -1, 1 },
3785 { READRSPERR_F, "Outbound read error", -1, 0 },
3791 if (is_t4(adapter->params.chip))
3792 fat = t4_handle_intr_status(adapter,
3793 PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS_A,
3795 t4_handle_intr_status(adapter,
3796 PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS_A,
3797 pcie_port_intr_info) +
3798 t4_handle_intr_status(adapter, PCIE_INT_CAUSE_A,
3801 fat = t4_handle_intr_status(adapter, PCIE_INT_CAUSE_A,
3805 t4_fatal_err(adapter);
3809 * TP interrupt handler.
3811 static void tp_intr_handler(struct adapter *adapter)
3813 static const struct intr_info tp_intr_info[] = {
3814 { 0x3fffffff, "TP parity error", -1, 1 },
3815 { FLMTXFLSTEMPTY_F, "TP out of Tx pages", -1, 1 },
3819 if (t4_handle_intr_status(adapter, TP_INT_CAUSE_A, tp_intr_info))
3820 t4_fatal_err(adapter);
3824 * SGE interrupt handler.
3826 static void sge_intr_handler(struct adapter *adapter)
3831 static const struct intr_info sge_intr_info[] = {
3832 { ERR_CPL_EXCEED_IQE_SIZE_F,
3833 "SGE received CPL exceeding IQE size", -1, 1 },
3834 { ERR_INVALID_CIDX_INC_F,
3835 "SGE GTS CIDX increment too large", -1, 0 },
3836 { ERR_CPL_OPCODE_0_F, "SGE received 0-length CPL", -1, 0 },
3837 { DBFIFO_LP_INT_F, NULL, -1, 0, t4_db_full },
3838 { ERR_DATA_CPL_ON_HIGH_QID1_F | ERR_DATA_CPL_ON_HIGH_QID0_F,
3839 "SGE IQID > 1023 received CPL for FL", -1, 0 },
3840 { ERR_BAD_DB_PIDX3_F, "SGE DBP 3 pidx increment too large", -1,
3842 { ERR_BAD_DB_PIDX2_F, "SGE DBP 2 pidx increment too large", -1,
3844 { ERR_BAD_DB_PIDX1_F, "SGE DBP 1 pidx increment too large", -1,
3846 { ERR_BAD_DB_PIDX0_F, "SGE DBP 0 pidx increment too large", -1,
3848 { ERR_ING_CTXT_PRIO_F,
3849 "SGE too many priority ingress contexts", -1, 0 },
3850 { INGRESS_SIZE_ERR_F, "SGE illegal ingress QID", -1, 0 },
3851 { EGRESS_SIZE_ERR_F, "SGE illegal egress QID", -1, 0 },
3855 static struct intr_info t4t5_sge_intr_info[] = {
3856 { ERR_DROPPED_DB_F, NULL, -1, 0, t4_db_dropped },
3857 { DBFIFO_HP_INT_F, NULL, -1, 0, t4_db_full },
3858 { ERR_EGR_CTXT_PRIO_F,
3859 "SGE too many priority egress contexts", -1, 0 },
3863 v = (u64)t4_read_reg(adapter, SGE_INT_CAUSE1_A) |
3864 ((u64)t4_read_reg(adapter, SGE_INT_CAUSE2_A) << 32);
3866 dev_alert(adapter->pdev_dev, "SGE parity error (%#llx)\n",
3867 (unsigned long long)v);
3868 t4_write_reg(adapter, SGE_INT_CAUSE1_A, v);
3869 t4_write_reg(adapter, SGE_INT_CAUSE2_A, v >> 32);
3872 v |= t4_handle_intr_status(adapter, SGE_INT_CAUSE3_A, sge_intr_info);
3873 if (CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5)
3874 v |= t4_handle_intr_status(adapter, SGE_INT_CAUSE3_A,
3875 t4t5_sge_intr_info);
3877 err = t4_read_reg(adapter, SGE_ERROR_STATS_A);
3878 if (err & ERROR_QID_VALID_F) {
3879 dev_err(adapter->pdev_dev, "SGE error for queue %u\n",
3881 if (err & UNCAPTURED_ERROR_F)
3882 dev_err(adapter->pdev_dev,
3883 "SGE UNCAPTURED_ERROR set (clearing)\n");
3884 t4_write_reg(adapter, SGE_ERROR_STATS_A, ERROR_QID_VALID_F |
3885 UNCAPTURED_ERROR_F);
3889 t4_fatal_err(adapter);
3892 #define CIM_OBQ_INTR (OBQULP0PARERR_F | OBQULP1PARERR_F | OBQULP2PARERR_F |\
3893 OBQULP3PARERR_F | OBQSGEPARERR_F | OBQNCSIPARERR_F)
3894 #define CIM_IBQ_INTR (IBQTP0PARERR_F | IBQTP1PARERR_F | IBQULPPARERR_F |\
3895 IBQSGEHIPARERR_F | IBQSGELOPARERR_F | IBQNCSIPARERR_F)
3898 * CIM interrupt handler.
3900 static void cim_intr_handler(struct adapter *adapter)
3902 static const struct intr_info cim_intr_info[] = {
3903 { PREFDROPINT_F, "CIM control register prefetch drop", -1, 1 },
3904 { CIM_OBQ_INTR, "CIM OBQ parity error", -1, 1 },
3905 { CIM_IBQ_INTR, "CIM IBQ parity error", -1, 1 },
3906 { MBUPPARERR_F, "CIM mailbox uP parity error", -1, 1 },
3907 { MBHOSTPARERR_F, "CIM mailbox host parity error", -1, 1 },
3908 { TIEQINPARERRINT_F, "CIM TIEQ outgoing parity error", -1, 1 },
3909 { TIEQOUTPARERRINT_F, "CIM TIEQ incoming parity error", -1, 1 },
3912 static const struct intr_info cim_upintr_info[] = {
3913 { RSVDSPACEINT_F, "CIM reserved space access", -1, 1 },
3914 { ILLTRANSINT_F, "CIM illegal transaction", -1, 1 },
3915 { ILLWRINT_F, "CIM illegal write", -1, 1 },
3916 { ILLRDINT_F, "CIM illegal read", -1, 1 },
3917 { ILLRDBEINT_F, "CIM illegal read BE", -1, 1 },
3918 { ILLWRBEINT_F, "CIM illegal write BE", -1, 1 },
3919 { SGLRDBOOTINT_F, "CIM single read from boot space", -1, 1 },
3920 { SGLWRBOOTINT_F, "CIM single write to boot space", -1, 1 },
3921 { BLKWRBOOTINT_F, "CIM block write to boot space", -1, 1 },
3922 { SGLRDFLASHINT_F, "CIM single read from flash space", -1, 1 },
3923 { SGLWRFLASHINT_F, "CIM single write to flash space", -1, 1 },
3924 { BLKWRFLASHINT_F, "CIM block write to flash space", -1, 1 },
3925 { SGLRDEEPROMINT_F, "CIM single EEPROM read", -1, 1 },
3926 { SGLWREEPROMINT_F, "CIM single EEPROM write", -1, 1 },
3927 { BLKRDEEPROMINT_F, "CIM block EEPROM read", -1, 1 },
3928 { BLKWREEPROMINT_F, "CIM block EEPROM write", -1, 1 },
3929 { SGLRDCTLINT_F, "CIM single read from CTL space", -1, 1 },
3930 { SGLWRCTLINT_F, "CIM single write to CTL space", -1, 1 },
3931 { BLKRDCTLINT_F, "CIM block read from CTL space", -1, 1 },
3932 { BLKWRCTLINT_F, "CIM block write to CTL space", -1, 1 },
3933 { SGLRDPLINT_F, "CIM single read from PL space", -1, 1 },
3934 { SGLWRPLINT_F, "CIM single write to PL space", -1, 1 },
3935 { BLKRDPLINT_F, "CIM block read from PL space", -1, 1 },
3936 { BLKWRPLINT_F, "CIM block write to PL space", -1, 1 },
3937 { REQOVRLOOKUPINT_F, "CIM request FIFO overwrite", -1, 1 },
3938 { RSPOVRLOOKUPINT_F, "CIM response FIFO overwrite", -1, 1 },
3939 { TIMEOUTINT_F, "CIM PIF timeout", -1, 1 },
3940 { TIMEOUTMAINT_F, "CIM PIF MA timeout", -1, 1 },
3946 if (t4_read_reg(adapter, PCIE_FW_A) & PCIE_FW_ERR_F)
3947 t4_report_fw_error(adapter);
3949 fat = t4_handle_intr_status(adapter, CIM_HOST_INT_CAUSE_A,
3951 t4_handle_intr_status(adapter, CIM_HOST_UPACC_INT_CAUSE_A,
3954 t4_fatal_err(adapter);
3958 * ULP RX interrupt handler.
3960 static void ulprx_intr_handler(struct adapter *adapter)
3962 static const struct intr_info ulprx_intr_info[] = {
3963 { 0x1800000, "ULPRX context error", -1, 1 },
3964 { 0x7fffff, "ULPRX parity error", -1, 1 },
3968 if (t4_handle_intr_status(adapter, ULP_RX_INT_CAUSE_A, ulprx_intr_info))
3969 t4_fatal_err(adapter);
3973 * ULP TX interrupt handler.
3975 static void ulptx_intr_handler(struct adapter *adapter)
3977 static const struct intr_info ulptx_intr_info[] = {
3978 { PBL_BOUND_ERR_CH3_F, "ULPTX channel 3 PBL out of bounds", -1,
3980 { PBL_BOUND_ERR_CH2_F, "ULPTX channel 2 PBL out of bounds", -1,
3982 { PBL_BOUND_ERR_CH1_F, "ULPTX channel 1 PBL out of bounds", -1,
3984 { PBL_BOUND_ERR_CH0_F, "ULPTX channel 0 PBL out of bounds", -1,
3986 { 0xfffffff, "ULPTX parity error", -1, 1 },
3990 if (t4_handle_intr_status(adapter, ULP_TX_INT_CAUSE_A, ulptx_intr_info))
3991 t4_fatal_err(adapter);
3995 * PM TX interrupt handler.
3997 static void pmtx_intr_handler(struct adapter *adapter)
3999 static const struct intr_info pmtx_intr_info[] = {
4000 { PCMD_LEN_OVFL0_F, "PMTX channel 0 pcmd too large", -1, 1 },
4001 { PCMD_LEN_OVFL1_F, "PMTX channel 1 pcmd too large", -1, 1 },
4002 { PCMD_LEN_OVFL2_F, "PMTX channel 2 pcmd too large", -1, 1 },
4003 { ZERO_C_CMD_ERROR_F, "PMTX 0-length pcmd", -1, 1 },
4004 { PMTX_FRAMING_ERROR_F, "PMTX framing error", -1, 1 },
4005 { OESPI_PAR_ERROR_F, "PMTX oespi parity error", -1, 1 },
4006 { DB_OPTIONS_PAR_ERROR_F, "PMTX db_options parity error",
4008 { ICSPI_PAR_ERROR_F, "PMTX icspi parity error", -1, 1 },
4009 { PMTX_C_PCMD_PAR_ERROR_F, "PMTX c_pcmd parity error", -1, 1},
4013 if (t4_handle_intr_status(adapter, PM_TX_INT_CAUSE_A, pmtx_intr_info))
4014 t4_fatal_err(adapter);
4018 * PM RX interrupt handler.
4020 static void pmrx_intr_handler(struct adapter *adapter)
4022 static const struct intr_info pmrx_intr_info[] = {
4023 { ZERO_E_CMD_ERROR_F, "PMRX 0-length pcmd", -1, 1 },
4024 { PMRX_FRAMING_ERROR_F, "PMRX framing error", -1, 1 },
4025 { OCSPI_PAR_ERROR_F, "PMRX ocspi parity error", -1, 1 },
4026 { DB_OPTIONS_PAR_ERROR_F, "PMRX db_options parity error",
4028 { IESPI_PAR_ERROR_F, "PMRX iespi parity error", -1, 1 },
4029 { PMRX_E_PCMD_PAR_ERROR_F, "PMRX e_pcmd parity error", -1, 1},
4033 if (t4_handle_intr_status(adapter, PM_RX_INT_CAUSE_A, pmrx_intr_info))
4034 t4_fatal_err(adapter);
4038 * CPL switch interrupt handler.
4040 static void cplsw_intr_handler(struct adapter *adapter)
4042 static const struct intr_info cplsw_intr_info[] = {
4043 { CIM_OP_MAP_PERR_F, "CPLSW CIM op_map parity error", -1, 1 },
4044 { CIM_OVFL_ERROR_F, "CPLSW CIM overflow", -1, 1 },
4045 { TP_FRAMING_ERROR_F, "CPLSW TP framing error", -1, 1 },
4046 { SGE_FRAMING_ERROR_F, "CPLSW SGE framing error", -1, 1 },
4047 { CIM_FRAMING_ERROR_F, "CPLSW CIM framing error", -1, 1 },
4048 { ZERO_SWITCH_ERROR_F, "CPLSW no-switch error", -1, 1 },
4052 if (t4_handle_intr_status(adapter, CPL_INTR_CAUSE_A, cplsw_intr_info))
4053 t4_fatal_err(adapter);
4057 * LE interrupt handler.
4059 static void le_intr_handler(struct adapter *adap)
4061 enum chip_type chip = CHELSIO_CHIP_VERSION(adap->params.chip);
4062 static const struct intr_info le_intr_info[] = {
4063 { LIPMISS_F, "LE LIP miss", -1, 0 },
4064 { LIP0_F, "LE 0 LIP error", -1, 0 },
4065 { PARITYERR_F, "LE parity error", -1, 1 },
4066 { UNKNOWNCMD_F, "LE unknown command", -1, 1 },
4067 { REQQPARERR_F, "LE request queue parity error", -1, 1 },
4071 static struct intr_info t6_le_intr_info[] = {
4072 { T6_LIPMISS_F, "LE LIP miss", -1, 0 },
4073 { T6_LIP0_F, "LE 0 LIP error", -1, 0 },
4074 { TCAMINTPERR_F, "LE parity error", -1, 1 },
4075 { T6_UNKNOWNCMD_F, "LE unknown command", -1, 1 },
4076 { SSRAMINTPERR_F, "LE request queue parity error", -1, 1 },
4080 if (t4_handle_intr_status(adap, LE_DB_INT_CAUSE_A,
4081 (chip <= CHELSIO_T5) ?
4082 le_intr_info : t6_le_intr_info))
4087 * MPS interrupt handler.
4089 static void mps_intr_handler(struct adapter *adapter)
4091 static const struct intr_info mps_rx_intr_info[] = {
4092 { 0xffffff, "MPS Rx parity error", -1, 1 },
4095 static const struct intr_info mps_tx_intr_info[] = {
4096 { TPFIFO_V(TPFIFO_M), "MPS Tx TP FIFO parity error", -1, 1 },
4097 { NCSIFIFO_F, "MPS Tx NC-SI FIFO parity error", -1, 1 },
4098 { TXDATAFIFO_V(TXDATAFIFO_M), "MPS Tx data FIFO parity error",
4100 { TXDESCFIFO_V(TXDESCFIFO_M), "MPS Tx desc FIFO parity error",
4102 { BUBBLE_F, "MPS Tx underflow", -1, 1 },
4103 { SECNTERR_F, "MPS Tx SOP/EOP error", -1, 1 },
4104 { FRMERR_F, "MPS Tx framing error", -1, 1 },
4107 static const struct intr_info mps_trc_intr_info[] = {
4108 { FILTMEM_V(FILTMEM_M), "MPS TRC filter parity error", -1, 1 },
4109 { PKTFIFO_V(PKTFIFO_M), "MPS TRC packet FIFO parity error",
4111 { MISCPERR_F, "MPS TRC misc parity error", -1, 1 },
4114 static const struct intr_info mps_stat_sram_intr_info[] = {
4115 { 0x1fffff, "MPS statistics SRAM parity error", -1, 1 },
4118 static const struct intr_info mps_stat_tx_intr_info[] = {
4119 { 0xfffff, "MPS statistics Tx FIFO parity error", -1, 1 },
4122 static const struct intr_info mps_stat_rx_intr_info[] = {
4123 { 0xffffff, "MPS statistics Rx FIFO parity error", -1, 1 },
4126 static const struct intr_info mps_cls_intr_info[] = {
4127 { MATCHSRAM_F, "MPS match SRAM parity error", -1, 1 },
4128 { MATCHTCAM_F, "MPS match TCAM parity error", -1, 1 },
4129 { HASHSRAM_F, "MPS hash SRAM parity error", -1, 1 },
4135 fat = t4_handle_intr_status(adapter, MPS_RX_PERR_INT_CAUSE_A,
4137 t4_handle_intr_status(adapter, MPS_TX_INT_CAUSE_A,
4139 t4_handle_intr_status(adapter, MPS_TRC_INT_CAUSE_A,
4140 mps_trc_intr_info) +
4141 t4_handle_intr_status(adapter, MPS_STAT_PERR_INT_CAUSE_SRAM_A,
4142 mps_stat_sram_intr_info) +
4143 t4_handle_intr_status(adapter, MPS_STAT_PERR_INT_CAUSE_TX_FIFO_A,
4144 mps_stat_tx_intr_info) +
4145 t4_handle_intr_status(adapter, MPS_STAT_PERR_INT_CAUSE_RX_FIFO_A,
4146 mps_stat_rx_intr_info) +
4147 t4_handle_intr_status(adapter, MPS_CLS_INT_CAUSE_A,
4150 t4_write_reg(adapter, MPS_INT_CAUSE_A, 0);
4151 t4_read_reg(adapter, MPS_INT_CAUSE_A); /* flush */
4153 t4_fatal_err(adapter);
4156 #define MEM_INT_MASK (PERR_INT_CAUSE_F | ECC_CE_INT_CAUSE_F | \
4160 * EDC/MC interrupt handler.
4162 static void mem_intr_handler(struct adapter *adapter, int idx)
4164 static const char name[4][7] = { "EDC0", "EDC1", "MC/MC0", "MC1" };
4166 unsigned int addr, cnt_addr, v;
4168 if (idx <= MEM_EDC1) {
4169 addr = EDC_REG(EDC_INT_CAUSE_A, idx);
4170 cnt_addr = EDC_REG(EDC_ECC_STATUS_A, idx);
4171 } else if (idx == MEM_MC) {
4172 if (is_t4(adapter->params.chip)) {
4173 addr = MC_INT_CAUSE_A;
4174 cnt_addr = MC_ECC_STATUS_A;
4176 addr = MC_P_INT_CAUSE_A;
4177 cnt_addr = MC_P_ECC_STATUS_A;
4180 addr = MC_REG(MC_P_INT_CAUSE_A, 1);
4181 cnt_addr = MC_REG(MC_P_ECC_STATUS_A, 1);
4184 v = t4_read_reg(adapter, addr) & MEM_INT_MASK;
4185 if (v & PERR_INT_CAUSE_F)
4186 dev_alert(adapter->pdev_dev, "%s FIFO parity error\n",
4188 if (v & ECC_CE_INT_CAUSE_F) {
4189 u32 cnt = ECC_CECNT_G(t4_read_reg(adapter, cnt_addr));
4191 t4_edc_err_read(adapter, idx);
4193 t4_write_reg(adapter, cnt_addr, ECC_CECNT_V(ECC_CECNT_M));
4194 if (printk_ratelimit())
4195 dev_warn(adapter->pdev_dev,
4196 "%u %s correctable ECC data error%s\n",
4197 cnt, name[idx], cnt > 1 ? "s" : "");
4199 if (v & ECC_UE_INT_CAUSE_F)
4200 dev_alert(adapter->pdev_dev,
4201 "%s uncorrectable ECC data error\n", name[idx]);
4203 t4_write_reg(adapter, addr, v);
4204 if (v & (PERR_INT_CAUSE_F | ECC_UE_INT_CAUSE_F))
4205 t4_fatal_err(adapter);
4209 * MA interrupt handler.
4211 static void ma_intr_handler(struct adapter *adap)
4213 u32 v, status = t4_read_reg(adap, MA_INT_CAUSE_A);
4215 if (status & MEM_PERR_INT_CAUSE_F) {
4216 dev_alert(adap->pdev_dev,
4217 "MA parity error, parity status %#x\n",
4218 t4_read_reg(adap, MA_PARITY_ERROR_STATUS1_A));
4219 if (is_t5(adap->params.chip))
4220 dev_alert(adap->pdev_dev,
4221 "MA parity error, parity status %#x\n",
4223 MA_PARITY_ERROR_STATUS2_A));
4225 if (status & MEM_WRAP_INT_CAUSE_F) {
4226 v = t4_read_reg(adap, MA_INT_WRAP_STATUS_A);
4227 dev_alert(adap->pdev_dev, "MA address wrap-around error by "
4228 "client %u to address %#x\n",
4229 MEM_WRAP_CLIENT_NUM_G(v),
4230 MEM_WRAP_ADDRESS_G(v) << 4);
4232 t4_write_reg(adap, MA_INT_CAUSE_A, status);
4237 * SMB interrupt handler.
4239 static void smb_intr_handler(struct adapter *adap)
4241 static const struct intr_info smb_intr_info[] = {
4242 { MSTTXFIFOPARINT_F, "SMB master Tx FIFO parity error", -1, 1 },
4243 { MSTRXFIFOPARINT_F, "SMB master Rx FIFO parity error", -1, 1 },
4244 { SLVFIFOPARINT_F, "SMB slave FIFO parity error", -1, 1 },
4248 if (t4_handle_intr_status(adap, SMB_INT_CAUSE_A, smb_intr_info))
4253 * NC-SI interrupt handler.
4255 static void ncsi_intr_handler(struct adapter *adap)
4257 static const struct intr_info ncsi_intr_info[] = {
4258 { CIM_DM_PRTY_ERR_F, "NC-SI CIM parity error", -1, 1 },
4259 { MPS_DM_PRTY_ERR_F, "NC-SI MPS parity error", -1, 1 },
4260 { TXFIFO_PRTY_ERR_F, "NC-SI Tx FIFO parity error", -1, 1 },
4261 { RXFIFO_PRTY_ERR_F, "NC-SI Rx FIFO parity error", -1, 1 },
4265 if (t4_handle_intr_status(adap, NCSI_INT_CAUSE_A, ncsi_intr_info))
4270 * XGMAC interrupt handler.
4272 static void xgmac_intr_handler(struct adapter *adap, int port)
4274 u32 v, int_cause_reg;
4276 if (is_t4(adap->params.chip))
4277 int_cause_reg = PORT_REG(port, XGMAC_PORT_INT_CAUSE_A);
4279 int_cause_reg = T5_PORT_REG(port, MAC_PORT_INT_CAUSE_A);
4281 v = t4_read_reg(adap, int_cause_reg);
4283 v &= TXFIFO_PRTY_ERR_F | RXFIFO_PRTY_ERR_F;
4287 if (v & TXFIFO_PRTY_ERR_F)
4288 dev_alert(adap->pdev_dev, "XGMAC %d Tx FIFO parity error\n",
4290 if (v & RXFIFO_PRTY_ERR_F)
4291 dev_alert(adap->pdev_dev, "XGMAC %d Rx FIFO parity error\n",
4293 t4_write_reg(adap, PORT_REG(port, XGMAC_PORT_INT_CAUSE_A), v);
4298 * PL interrupt handler.
4300 static void pl_intr_handler(struct adapter *adap)
4302 static const struct intr_info pl_intr_info[] = {
4303 { FATALPERR_F, "T4 fatal parity error", -1, 1 },
4304 { PERRVFID_F, "PL VFID_MAP parity error", -1, 1 },
4308 if (t4_handle_intr_status(adap, PL_PL_INT_CAUSE_A, pl_intr_info))
4312 #define PF_INTR_MASK (PFSW_F)
4313 #define GLBL_INTR_MASK (CIM_F | MPS_F | PL_F | PCIE_F | MC_F | EDC0_F | \
4314 EDC1_F | LE_F | TP_F | MA_F | PM_TX_F | PM_RX_F | ULP_RX_F | \
4315 CPL_SWITCH_F | SGE_F | ULP_TX_F)
4318 * t4_slow_intr_handler - control path interrupt handler
4319 * @adapter: the adapter
4321 * T4 interrupt handler for non-data global interrupt events, e.g., errors.
4322 * The designation 'slow' is because it involves register reads, while
4323 * data interrupts typically don't involve any MMIOs.
4325 int t4_slow_intr_handler(struct adapter *adapter)
4327 u32 cause = t4_read_reg(adapter, PL_INT_CAUSE_A);
4329 if (!(cause & GLBL_INTR_MASK))
4332 cim_intr_handler(adapter);
4334 mps_intr_handler(adapter);
4336 ncsi_intr_handler(adapter);
4338 pl_intr_handler(adapter);
4340 smb_intr_handler(adapter);
4341 if (cause & XGMAC0_F)
4342 xgmac_intr_handler(adapter, 0);
4343 if (cause & XGMAC1_F)
4344 xgmac_intr_handler(adapter, 1);
4345 if (cause & XGMAC_KR0_F)
4346 xgmac_intr_handler(adapter, 2);
4347 if (cause & XGMAC_KR1_F)
4348 xgmac_intr_handler(adapter, 3);
4350 pcie_intr_handler(adapter);
4352 mem_intr_handler(adapter, MEM_MC);
4353 if (is_t5(adapter->params.chip) && (cause & MC1_F))
4354 mem_intr_handler(adapter, MEM_MC1);
4356 mem_intr_handler(adapter, MEM_EDC0);
4358 mem_intr_handler(adapter, MEM_EDC1);
4360 le_intr_handler(adapter);
4362 tp_intr_handler(adapter);
4364 ma_intr_handler(adapter);
4365 if (cause & PM_TX_F)
4366 pmtx_intr_handler(adapter);
4367 if (cause & PM_RX_F)
4368 pmrx_intr_handler(adapter);
4369 if (cause & ULP_RX_F)
4370 ulprx_intr_handler(adapter);
4371 if (cause & CPL_SWITCH_F)
4372 cplsw_intr_handler(adapter);
4374 sge_intr_handler(adapter);
4375 if (cause & ULP_TX_F)
4376 ulptx_intr_handler(adapter);
4378 /* Clear the interrupts just processed for which we are the master. */
4379 t4_write_reg(adapter, PL_INT_CAUSE_A, cause & GLBL_INTR_MASK);
4380 (void)t4_read_reg(adapter, PL_INT_CAUSE_A); /* flush */
4385 * t4_intr_enable - enable interrupts
4386 * @adapter: the adapter whose interrupts should be enabled
4388 * Enable PF-specific interrupts for the calling function and the top-level
4389 * interrupt concentrator for global interrupts. Interrupts are already
4390 * enabled at each module, here we just enable the roots of the interrupt
4393 * Note: this function should be called only when the driver manages
4394 * non PF-specific interrupts from the various HW modules. Only one PCI
4395 * function at a time should be doing this.
4397 void t4_intr_enable(struct adapter *adapter)
4400 u32 whoami = t4_read_reg(adapter, PL_WHOAMI_A);
4401 u32 pf = CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5 ?
4402 SOURCEPF_G(whoami) : T6_SOURCEPF_G(whoami);
4404 if (CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5)
4405 val = ERR_DROPPED_DB_F | ERR_EGR_CTXT_PRIO_F | DBFIFO_HP_INT_F;
4406 t4_write_reg(adapter, SGE_INT_ENABLE3_A, ERR_CPL_EXCEED_IQE_SIZE_F |
4407 ERR_INVALID_CIDX_INC_F | ERR_CPL_OPCODE_0_F |
4408 ERR_DATA_CPL_ON_HIGH_QID1_F | INGRESS_SIZE_ERR_F |
4409 ERR_DATA_CPL_ON_HIGH_QID0_F | ERR_BAD_DB_PIDX3_F |
4410 ERR_BAD_DB_PIDX2_F | ERR_BAD_DB_PIDX1_F |
4411 ERR_BAD_DB_PIDX0_F | ERR_ING_CTXT_PRIO_F |
4412 DBFIFO_LP_INT_F | EGRESS_SIZE_ERR_F | val);
4413 t4_write_reg(adapter, MYPF_REG(PL_PF_INT_ENABLE_A), PF_INTR_MASK);
4414 t4_set_reg_field(adapter, PL_INT_MAP0_A, 0, 1 << pf);
4418 * t4_intr_disable - disable interrupts
4419 * @adapter: the adapter whose interrupts should be disabled
4421 * Disable interrupts. We only disable the top-level interrupt
4422 * concentrators. The caller must be a PCI function managing global
4425 void t4_intr_disable(struct adapter *adapter)
4427 u32 whoami = t4_read_reg(adapter, PL_WHOAMI_A);
4428 u32 pf = CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5 ?
4429 SOURCEPF_G(whoami) : T6_SOURCEPF_G(whoami);
4431 t4_write_reg(adapter, MYPF_REG(PL_PF_INT_ENABLE_A), 0);
4432 t4_set_reg_field(adapter, PL_INT_MAP0_A, 1 << pf, 0);
4436 * t4_config_rss_range - configure a portion of the RSS mapping table
4437 * @adapter: the adapter
4438 * @mbox: mbox to use for the FW command
4439 * @viid: virtual interface whose RSS subtable is to be written
4440 * @start: start entry in the table to write
4441 * @n: how many table entries to write
4442 * @rspq: values for the response queue lookup table
4443 * @nrspq: number of values in @rspq
4445 * Programs the selected part of the VI's RSS mapping table with the
4446 * provided values. If @nrspq < @n the supplied values are used repeatedly
4447 * until the full table range is populated.
4449 * The caller must ensure the values in @rspq are in the range allowed for
4452 int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid,
4453 int start, int n, const u16 *rspq, unsigned int nrspq)
4456 const u16 *rsp = rspq;
4457 const u16 *rsp_end = rspq + nrspq;
4458 struct fw_rss_ind_tbl_cmd cmd;
4460 memset(&cmd, 0, sizeof(cmd));
4461 cmd.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_RSS_IND_TBL_CMD) |
4462 FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
4463 FW_RSS_IND_TBL_CMD_VIID_V(viid));
4464 cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd));
4466 /* each fw_rss_ind_tbl_cmd takes up to 32 entries */
4468 int nq = min(n, 32);
4469 __be32 *qp = &cmd.iq0_to_iq2;
4471 cmd.niqid = cpu_to_be16(nq);
4472 cmd.startidx = cpu_to_be16(start);
4480 v = FW_RSS_IND_TBL_CMD_IQ0_V(*rsp);
4481 if (++rsp >= rsp_end)
4483 v |= FW_RSS_IND_TBL_CMD_IQ1_V(*rsp);
4484 if (++rsp >= rsp_end)
4486 v |= FW_RSS_IND_TBL_CMD_IQ2_V(*rsp);
4487 if (++rsp >= rsp_end)
4490 *qp++ = cpu_to_be32(v);
4494 ret = t4_wr_mbox(adapter, mbox, &cmd, sizeof(cmd), NULL);
4502 * t4_config_glbl_rss - configure the global RSS mode
4503 * @adapter: the adapter
4504 * @mbox: mbox to use for the FW command
4505 * @mode: global RSS mode
4506 * @flags: mode-specific flags
4508 * Sets the global RSS mode.
4510 int t4_config_glbl_rss(struct adapter *adapter, int mbox, unsigned int mode,
4513 struct fw_rss_glb_config_cmd c;
4515 memset(&c, 0, sizeof(c));
4516 c.op_to_write = cpu_to_be32(FW_CMD_OP_V(FW_RSS_GLB_CONFIG_CMD) |
4517 FW_CMD_REQUEST_F | FW_CMD_WRITE_F);
4518 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
4519 if (mode == FW_RSS_GLB_CONFIG_CMD_MODE_MANUAL) {
4520 c.u.manual.mode_pkd =
4521 cpu_to_be32(FW_RSS_GLB_CONFIG_CMD_MODE_V(mode));
4522 } else if (mode == FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL) {
4523 c.u.basicvirtual.mode_pkd =
4524 cpu_to_be32(FW_RSS_GLB_CONFIG_CMD_MODE_V(mode));
4525 c.u.basicvirtual.synmapen_to_hashtoeplitz = cpu_to_be32(flags);
4528 return t4_wr_mbox(adapter, mbox, &c, sizeof(c), NULL);
4532 * t4_config_vi_rss - configure per VI RSS settings
4533 * @adapter: the adapter
4534 * @mbox: mbox to use for the FW command
4537 * @defq: id of the default RSS queue for the VI.
4539 * Configures VI-specific RSS properties.
4541 int t4_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid,
4542 unsigned int flags, unsigned int defq)
4544 struct fw_rss_vi_config_cmd c;
4546 memset(&c, 0, sizeof(c));
4547 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_RSS_VI_CONFIG_CMD) |
4548 FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
4549 FW_RSS_VI_CONFIG_CMD_VIID_V(viid));
4550 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
4551 c.u.basicvirtual.defaultq_to_udpen = cpu_to_be32(flags |
4552 FW_RSS_VI_CONFIG_CMD_DEFAULTQ_V(defq));
4553 return t4_wr_mbox(adapter, mbox, &c, sizeof(c), NULL);
4556 /* Read an RSS table row */
4557 static int rd_rss_row(struct adapter *adap, int row, u32 *val)
4559 t4_write_reg(adap, TP_RSS_LKP_TABLE_A, 0xfff00000 | row);
4560 return t4_wait_op_done_val(adap, TP_RSS_LKP_TABLE_A, LKPTBLROWVLD_F, 1,
4565 * t4_read_rss - read the contents of the RSS mapping table
4566 * @adapter: the adapter
4567 * @map: holds the contents of the RSS mapping table
4569 * Reads the contents of the RSS hash->queue mapping table.
4571 int t4_read_rss(struct adapter *adapter, u16 *map)
4576 for (i = 0; i < RSS_NENTRIES / 2; ++i) {
4577 ret = rd_rss_row(adapter, i, &val);
4580 *map++ = LKPTBLQUEUE0_G(val);
4581 *map++ = LKPTBLQUEUE1_G(val);
4586 static unsigned int t4_use_ldst(struct adapter *adap)
4588 return (adap->flags & FW_OK) || !adap->use_bd;
4592 * t4_fw_tp_pio_rw - Access TP PIO through LDST
4593 * @adap: the adapter
4594 * @vals: where the indirect register values are stored/written
4595 * @nregs: how many indirect registers to read/write
4596 * @start_idx: index of first indirect register to read/write
4597 * @rw: Read (1) or Write (0)
4599 * Access TP PIO registers through LDST
4601 static void t4_fw_tp_pio_rw(struct adapter *adap, u32 *vals, unsigned int nregs,
4602 unsigned int start_index, unsigned int rw)
4605 int cmd = FW_LDST_ADDRSPC_TP_PIO;
4606 struct fw_ldst_cmd c;
4608 for (i = 0 ; i < nregs; i++) {
4609 memset(&c, 0, sizeof(c));
4610 c.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
4612 (rw ? FW_CMD_READ_F :
4614 FW_LDST_CMD_ADDRSPACE_V(cmd));
4615 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
4617 c.u.addrval.addr = cpu_to_be32(start_index + i);
4618 c.u.addrval.val = rw ? 0 : cpu_to_be32(vals[i]);
4619 ret = t4_wr_mbox(adap, adap->mbox, &c, sizeof(c), &c);
4621 vals[i] = be32_to_cpu(c.u.addrval.val);
4626 * t4_read_rss_key - read the global RSS key
4627 * @adap: the adapter
4628 * @key: 10-entry array holding the 320-bit RSS key
4630 * Reads the global 320-bit RSS key.
4632 void t4_read_rss_key(struct adapter *adap, u32 *key)
4634 if (t4_use_ldst(adap))
4635 t4_fw_tp_pio_rw(adap, key, 10, TP_RSS_SECRET_KEY0_A, 1);
4637 t4_read_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A, key, 10,
4638 TP_RSS_SECRET_KEY0_A);
4642 * t4_write_rss_key - program one of the RSS keys
4643 * @adap: the adapter
4644 * @key: 10-entry array holding the 320-bit RSS key
4645 * @idx: which RSS key to write
4647 * Writes one of the RSS keys with the given 320-bit value. If @idx is
4648 * 0..15 the corresponding entry in the RSS key table is written,
4649 * otherwise the global RSS key is written.
4651 void t4_write_rss_key(struct adapter *adap, const u32 *key, int idx)
4653 u8 rss_key_addr_cnt = 16;
4654 u32 vrt = t4_read_reg(adap, TP_RSS_CONFIG_VRT_A);
4656 /* T6 and later: for KeyMode 3 (per-vf and per-vf scramble),
4657 * allows access to key addresses 16-63 by using KeyWrAddrX
4658 * as index[5:4](upper 2) into key table
4660 if ((CHELSIO_CHIP_VERSION(adap->params.chip) > CHELSIO_T5) &&
4661 (vrt & KEYEXTEND_F) && (KEYMODE_G(vrt) == 3))
4662 rss_key_addr_cnt = 32;
4664 if (t4_use_ldst(adap))
4665 t4_fw_tp_pio_rw(adap, (void *)key, 10, TP_RSS_SECRET_KEY0_A, 0);
4667 t4_write_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A, key, 10,
4668 TP_RSS_SECRET_KEY0_A);
4670 if (idx >= 0 && idx < rss_key_addr_cnt) {
4671 if (rss_key_addr_cnt > 16)
4672 t4_write_reg(adap, TP_RSS_CONFIG_VRT_A,
4673 KEYWRADDRX_V(idx >> 4) |
4674 T6_VFWRADDR_V(idx) | KEYWREN_F);
4676 t4_write_reg(adap, TP_RSS_CONFIG_VRT_A,
4677 KEYWRADDR_V(idx) | KEYWREN_F);
4682 * t4_read_rss_pf_config - read PF RSS Configuration Table
4683 * @adapter: the adapter
4684 * @index: the entry in the PF RSS table to read
4685 * @valp: where to store the returned value
4687 * Reads the PF RSS Configuration Table at the specified index and returns
4688 * the value found there.
4690 void t4_read_rss_pf_config(struct adapter *adapter, unsigned int index,
4693 if (t4_use_ldst(adapter))
4694 t4_fw_tp_pio_rw(adapter, valp, 1,
4695 TP_RSS_PF0_CONFIG_A + index, 1);
4697 t4_read_indirect(adapter, TP_PIO_ADDR_A, TP_PIO_DATA_A,
4698 valp, 1, TP_RSS_PF0_CONFIG_A + index);
4702 * t4_read_rss_vf_config - read VF RSS Configuration Table
4703 * @adapter: the adapter
4704 * @index: the entry in the VF RSS table to read
4705 * @vfl: where to store the returned VFL
4706 * @vfh: where to store the returned VFH
4708 * Reads the VF RSS Configuration Table at the specified index and returns
4709 * the (VFL, VFH) values found there.
4711 void t4_read_rss_vf_config(struct adapter *adapter, unsigned int index,
4714 u32 vrt, mask, data;
4716 if (CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5) {
4717 mask = VFWRADDR_V(VFWRADDR_M);
4718 data = VFWRADDR_V(index);
4720 mask = T6_VFWRADDR_V(T6_VFWRADDR_M);
4721 data = T6_VFWRADDR_V(index);
4724 /* Request that the index'th VF Table values be read into VFL/VFH.
4726 vrt = t4_read_reg(adapter, TP_RSS_CONFIG_VRT_A);
4727 vrt &= ~(VFRDRG_F | VFWREN_F | KEYWREN_F | mask);
4728 vrt |= data | VFRDEN_F;
4729 t4_write_reg(adapter, TP_RSS_CONFIG_VRT_A, vrt);
4731 /* Grab the VFL/VFH values ...
4733 if (t4_use_ldst(adapter)) {
4734 t4_fw_tp_pio_rw(adapter, vfl, 1, TP_RSS_VFL_CONFIG_A, 1);
4735 t4_fw_tp_pio_rw(adapter, vfh, 1, TP_RSS_VFH_CONFIG_A, 1);
4737 t4_read_indirect(adapter, TP_PIO_ADDR_A, TP_PIO_DATA_A,
4738 vfl, 1, TP_RSS_VFL_CONFIG_A);
4739 t4_read_indirect(adapter, TP_PIO_ADDR_A, TP_PIO_DATA_A,
4740 vfh, 1, TP_RSS_VFH_CONFIG_A);
4745 * t4_read_rss_pf_map - read PF RSS Map
4746 * @adapter: the adapter
4748 * Reads the PF RSS Map register and returns its value.
4750 u32 t4_read_rss_pf_map(struct adapter *adapter)
4754 if (t4_use_ldst(adapter))
4755 t4_fw_tp_pio_rw(adapter, &pfmap, 1, TP_RSS_PF_MAP_A, 1);
4757 t4_read_indirect(adapter, TP_PIO_ADDR_A, TP_PIO_DATA_A,
4758 &pfmap, 1, TP_RSS_PF_MAP_A);
4763 * t4_read_rss_pf_mask - read PF RSS Mask
4764 * @adapter: the adapter
4766 * Reads the PF RSS Mask register and returns its value.
4768 u32 t4_read_rss_pf_mask(struct adapter *adapter)
4772 if (t4_use_ldst(adapter))
4773 t4_fw_tp_pio_rw(adapter, &pfmask, 1, TP_RSS_PF_MSK_A, 1);
4775 t4_read_indirect(adapter, TP_PIO_ADDR_A, TP_PIO_DATA_A,
4776 &pfmask, 1, TP_RSS_PF_MSK_A);
4781 * t4_tp_get_tcp_stats - read TP's TCP MIB counters
4782 * @adap: the adapter
4783 * @v4: holds the TCP/IP counter values
4784 * @v6: holds the TCP/IPv6 counter values
4786 * Returns the values of TP's TCP/IP and TCP/IPv6 MIB counters.
4787 * Either @v4 or @v6 may be %NULL to skip the corresponding stats.
4789 void t4_tp_get_tcp_stats(struct adapter *adap, struct tp_tcp_stats *v4,
4790 struct tp_tcp_stats *v6)
4792 u32 val[TP_MIB_TCP_RXT_SEG_LO_A - TP_MIB_TCP_OUT_RST_A + 1];
4794 #define STAT_IDX(x) ((TP_MIB_TCP_##x##_A) - TP_MIB_TCP_OUT_RST_A)
4795 #define STAT(x) val[STAT_IDX(x)]
4796 #define STAT64(x) (((u64)STAT(x##_HI) << 32) | STAT(x##_LO))
4799 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, val,
4800 ARRAY_SIZE(val), TP_MIB_TCP_OUT_RST_A);
4801 v4->tcp_out_rsts = STAT(OUT_RST);
4802 v4->tcp_in_segs = STAT64(IN_SEG);
4803 v4->tcp_out_segs = STAT64(OUT_SEG);
4804 v4->tcp_retrans_segs = STAT64(RXT_SEG);
4807 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, val,
4808 ARRAY_SIZE(val), TP_MIB_TCP_V6OUT_RST_A);
4809 v6->tcp_out_rsts = STAT(OUT_RST);
4810 v6->tcp_in_segs = STAT64(IN_SEG);
4811 v6->tcp_out_segs = STAT64(OUT_SEG);
4812 v6->tcp_retrans_segs = STAT64(RXT_SEG);
4820 * t4_tp_get_err_stats - read TP's error MIB counters
4821 * @adap: the adapter
4822 * @st: holds the counter values
4824 * Returns the values of TP's error counters.
4826 void t4_tp_get_err_stats(struct adapter *adap, struct tp_err_stats *st)
4828 int nchan = adap->params.arch.nchan;
4830 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A,
4831 st->mac_in_errs, nchan, TP_MIB_MAC_IN_ERR_0_A);
4832 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A,
4833 st->hdr_in_errs, nchan, TP_MIB_HDR_IN_ERR_0_A);
4834 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A,
4835 st->tcp_in_errs, nchan, TP_MIB_TCP_IN_ERR_0_A);
4836 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A,
4837 st->tnl_cong_drops, nchan, TP_MIB_TNL_CNG_DROP_0_A);
4838 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A,
4839 st->ofld_chan_drops, nchan, TP_MIB_OFD_CHN_DROP_0_A);
4840 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A,
4841 st->tnl_tx_drops, nchan, TP_MIB_TNL_DROP_0_A);
4842 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A,
4843 st->ofld_vlan_drops, nchan, TP_MIB_OFD_VLN_DROP_0_A);
4844 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A,
4845 st->tcp6_in_errs, nchan, TP_MIB_TCP_V6IN_ERR_0_A);
4847 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A,
4848 &st->ofld_no_neigh, 2, TP_MIB_OFD_ARP_DROP_A);
4852 * t4_tp_get_cpl_stats - read TP's CPL MIB counters
4853 * @adap: the adapter
4854 * @st: holds the counter values
4856 * Returns the values of TP's CPL counters.
4858 void t4_tp_get_cpl_stats(struct adapter *adap, struct tp_cpl_stats *st)
4860 int nchan = adap->params.arch.nchan;
4862 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, st->req,
4863 nchan, TP_MIB_CPL_IN_REQ_0_A);
4864 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, st->rsp,
4865 nchan, TP_MIB_CPL_OUT_RSP_0_A);
4870 * t4_tp_get_rdma_stats - read TP's RDMA MIB counters
4871 * @adap: the adapter
4872 * @st: holds the counter values
4874 * Returns the values of TP's RDMA counters.
4876 void t4_tp_get_rdma_stats(struct adapter *adap, struct tp_rdma_stats *st)
4878 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, &st->rqe_dfr_pkt,
4879 2, TP_MIB_RQE_DFR_PKT_A);
4883 * t4_get_fcoe_stats - read TP's FCoE MIB counters for a port
4884 * @adap: the adapter
4885 * @idx: the port index
4886 * @st: holds the counter values
4888 * Returns the values of TP's FCoE counters for the selected port.
4890 void t4_get_fcoe_stats(struct adapter *adap, unsigned int idx,
4891 struct tp_fcoe_stats *st)
4895 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, &st->frames_ddp,
4896 1, TP_MIB_FCOE_DDP_0_A + idx);
4897 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, &st->frames_drop,
4898 1, TP_MIB_FCOE_DROP_0_A + idx);
4899 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, val,
4900 2, TP_MIB_FCOE_BYTE_0_HI_A + 2 * idx);
4901 st->octets_ddp = ((u64)val[0] << 32) | val[1];
4905 * t4_get_usm_stats - read TP's non-TCP DDP MIB counters
4906 * @adap: the adapter
4907 * @st: holds the counter values
4909 * Returns the values of TP's counters for non-TCP directly-placed packets.
4911 void t4_get_usm_stats(struct adapter *adap, struct tp_usm_stats *st)
4915 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, val, 4,
4917 st->frames = val[0];
4919 st->octets = ((u64)val[2] << 32) | val[3];
4923 * t4_read_mtu_tbl - returns the values in the HW path MTU table
4924 * @adap: the adapter
4925 * @mtus: where to store the MTU values
4926 * @mtu_log: where to store the MTU base-2 log (may be %NULL)
4928 * Reads the HW path MTU table.
4930 void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log)
4935 for (i = 0; i < NMTUS; ++i) {
4936 t4_write_reg(adap, TP_MTU_TABLE_A,
4937 MTUINDEX_V(0xff) | MTUVALUE_V(i));
4938 v = t4_read_reg(adap, TP_MTU_TABLE_A);
4939 mtus[i] = MTUVALUE_G(v);
4941 mtu_log[i] = MTUWIDTH_G(v);
4946 * t4_read_cong_tbl - reads the congestion control table
4947 * @adap: the adapter
4948 * @incr: where to store the alpha values
4950 * Reads the additive increments programmed into the HW congestion
4953 void t4_read_cong_tbl(struct adapter *adap, u16 incr[NMTUS][NCCTRL_WIN])
4955 unsigned int mtu, w;
4957 for (mtu = 0; mtu < NMTUS; ++mtu)
4958 for (w = 0; w < NCCTRL_WIN; ++w) {
4959 t4_write_reg(adap, TP_CCTRL_TABLE_A,
4960 ROWINDEX_V(0xffff) | (mtu << 5) | w);
4961 incr[mtu][w] = (u16)t4_read_reg(adap,
4962 TP_CCTRL_TABLE_A) & 0x1fff;
4967 * t4_tp_wr_bits_indirect - set/clear bits in an indirect TP register
4968 * @adap: the adapter
4969 * @addr: the indirect TP register address
4970 * @mask: specifies the field within the register to modify
4971 * @val: new value for the field
4973 * Sets a field of an indirect TP register to the given value.
4975 void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr,
4976 unsigned int mask, unsigned int val)
4978 t4_write_reg(adap, TP_PIO_ADDR_A, addr);
4979 val |= t4_read_reg(adap, TP_PIO_DATA_A) & ~mask;
4980 t4_write_reg(adap, TP_PIO_DATA_A, val);
4984 * init_cong_ctrl - initialize congestion control parameters
4985 * @a: the alpha values for congestion control
4986 * @b: the beta values for congestion control
4988 * Initialize the congestion control parameters.
4990 static void init_cong_ctrl(unsigned short *a, unsigned short *b)
4992 a[0] = a[1] = a[2] = a[3] = a[4] = a[5] = a[6] = a[7] = a[8] = 1;
5017 b[0] = b[1] = b[2] = b[3] = b[4] = b[5] = b[6] = b[7] = b[8] = 0;
5020 b[13] = b[14] = b[15] = b[16] = 3;
5021 b[17] = b[18] = b[19] = b[20] = b[21] = 4;
5022 b[22] = b[23] = b[24] = b[25] = b[26] = b[27] = 5;
5027 /* The minimum additive increment value for the congestion control table */
5028 #define CC_MIN_INCR 2U
5031 * t4_load_mtus - write the MTU and congestion control HW tables
5032 * @adap: the adapter
5033 * @mtus: the values for the MTU table
5034 * @alpha: the values for the congestion control alpha parameter
5035 * @beta: the values for the congestion control beta parameter
5037 * Write the HW MTU table with the supplied MTUs and the high-speed
5038 * congestion control table with the supplied alpha, beta, and MTUs.
5039 * We write the two tables together because the additive increments
5040 * depend on the MTUs.
5042 void t4_load_mtus(struct adapter *adap, const unsigned short *mtus,
5043 const unsigned short *alpha, const unsigned short *beta)
5045 static const unsigned int avg_pkts[NCCTRL_WIN] = {
5046 2, 6, 10, 14, 20, 28, 40, 56, 80, 112, 160, 224, 320, 448, 640,
5047 896, 1281, 1792, 2560, 3584, 5120, 7168, 10240, 14336, 20480,
5048 28672, 40960, 57344, 81920, 114688, 163840, 229376
5053 for (i = 0; i < NMTUS; ++i) {
5054 unsigned int mtu = mtus[i];
5055 unsigned int log2 = fls(mtu);
5057 if (!(mtu & ((1 << log2) >> 2))) /* round */
5059 t4_write_reg(adap, TP_MTU_TABLE_A, MTUINDEX_V(i) |
5060 MTUWIDTH_V(log2) | MTUVALUE_V(mtu));
5062 for (w = 0; w < NCCTRL_WIN; ++w) {
5065 inc = max(((mtu - 40) * alpha[w]) / avg_pkts[w],
5068 t4_write_reg(adap, TP_CCTRL_TABLE_A, (i << 21) |
5069 (w << 16) | (beta[w] << 13) | inc);
5074 /* Calculates a rate in bytes/s given the number of 256-byte units per 4K core
5075 * clocks. The formula is
5077 * bytes/s = bytes256 * 256 * ClkFreq / 4096
5079 * which is equivalent to
5081 * bytes/s = 62.5 * bytes256 * ClkFreq_ms
5083 static u64 chan_rate(struct adapter *adap, unsigned int bytes256)
5085 u64 v = bytes256 * adap->params.vpd.cclk;
5087 return v * 62 + v / 2;
5091 * t4_get_chan_txrate - get the current per channel Tx rates
5092 * @adap: the adapter
5093 * @nic_rate: rates for NIC traffic
5094 * @ofld_rate: rates for offloaded traffic
5096 * Return the current Tx rates in bytes/s for NIC and offloaded traffic
5099 void t4_get_chan_txrate(struct adapter *adap, u64 *nic_rate, u64 *ofld_rate)
5103 v = t4_read_reg(adap, TP_TX_TRATE_A);
5104 nic_rate[0] = chan_rate(adap, TNLRATE0_G(v));
5105 nic_rate[1] = chan_rate(adap, TNLRATE1_G(v));
5106 if (adap->params.arch.nchan == NCHAN) {
5107 nic_rate[2] = chan_rate(adap, TNLRATE2_G(v));
5108 nic_rate[3] = chan_rate(adap, TNLRATE3_G(v));
5111 v = t4_read_reg(adap, TP_TX_ORATE_A);
5112 ofld_rate[0] = chan_rate(adap, OFDRATE0_G(v));
5113 ofld_rate[1] = chan_rate(adap, OFDRATE1_G(v));
5114 if (adap->params.arch.nchan == NCHAN) {
5115 ofld_rate[2] = chan_rate(adap, OFDRATE2_G(v));
5116 ofld_rate[3] = chan_rate(adap, OFDRATE3_G(v));
5121 * t4_set_trace_filter - configure one of the tracing filters
5122 * @adap: the adapter
5123 * @tp: the desired trace filter parameters
5124 * @idx: which filter to configure
5125 * @enable: whether to enable or disable the filter
5127 * Configures one of the tracing filters available in HW. If @enable is
5128 * %0 @tp is not examined and may be %NULL. The user is responsible to
5129 * set the single/multiple trace mode by writing to MPS_TRC_CFG_A register
5131 int t4_set_trace_filter(struct adapter *adap, const struct trace_params *tp,
5132 int idx, int enable)
5134 int i, ofst = idx * 4;
5135 u32 data_reg, mask_reg, cfg;
5136 u32 multitrc = TRCMULTIFILTER_F;
5139 t4_write_reg(adap, MPS_TRC_FILTER_MATCH_CTL_A_A + ofst, 0);
5143 cfg = t4_read_reg(adap, MPS_TRC_CFG_A);
5144 if (cfg & TRCMULTIFILTER_F) {
5145 /* If multiple tracers are enabled, then maximum
5146 * capture size is 2.5KB (FIFO size of a single channel)
5147 * minus 2 flits for CPL_TRACE_PKT header.
5149 if (tp->snap_len > ((10 * 1024 / 4) - (2 * 8)))
5152 /* If multiple tracers are disabled, to avoid deadlocks
5153 * maximum packet capture size of 9600 bytes is recommended.
5154 * Also in this mode, only trace0 can be enabled and running.
5157 if (tp->snap_len > 9600 || idx)
5161 if (tp->port > (is_t4(adap->params.chip) ? 11 : 19) || tp->invert > 1 ||
5162 tp->skip_len > TFLENGTH_M || tp->skip_ofst > TFOFFSET_M ||
5163 tp->min_len > TFMINPKTSIZE_M)
5166 /* stop the tracer we'll be changing */
5167 t4_write_reg(adap, MPS_TRC_FILTER_MATCH_CTL_A_A + ofst, 0);
5169 idx *= (MPS_TRC_FILTER1_MATCH_A - MPS_TRC_FILTER0_MATCH_A);
5170 data_reg = MPS_TRC_FILTER0_MATCH_A + idx;
5171 mask_reg = MPS_TRC_FILTER0_DONT_CARE_A + idx;
5173 for (i = 0; i < TRACE_LEN / 4; i++, data_reg += 4, mask_reg += 4) {
5174 t4_write_reg(adap, data_reg, tp->data[i]);
5175 t4_write_reg(adap, mask_reg, ~tp->mask[i]);
5177 t4_write_reg(adap, MPS_TRC_FILTER_MATCH_CTL_B_A + ofst,
5178 TFCAPTUREMAX_V(tp->snap_len) |
5179 TFMINPKTSIZE_V(tp->min_len));
5180 t4_write_reg(adap, MPS_TRC_FILTER_MATCH_CTL_A_A + ofst,
5181 TFOFFSET_V(tp->skip_ofst) | TFLENGTH_V(tp->skip_len) |
5182 (is_t4(adap->params.chip) ?
5183 TFPORT_V(tp->port) | TFEN_F | TFINVERTMATCH_V(tp->invert) :
5184 T5_TFPORT_V(tp->port) | T5_TFEN_F |
5185 T5_TFINVERTMATCH_V(tp->invert)));
5191 * t4_get_trace_filter - query one of the tracing filters
5192 * @adap: the adapter
5193 * @tp: the current trace filter parameters
5194 * @idx: which trace filter to query
5195 * @enabled: non-zero if the filter is enabled
5197 * Returns the current settings of one of the HW tracing filters.
5199 void t4_get_trace_filter(struct adapter *adap, struct trace_params *tp, int idx,
5203 int i, ofst = idx * 4;
5204 u32 data_reg, mask_reg;
5206 ctla = t4_read_reg(adap, MPS_TRC_FILTER_MATCH_CTL_A_A + ofst);
5207 ctlb = t4_read_reg(adap, MPS_TRC_FILTER_MATCH_CTL_B_A + ofst);
5209 if (is_t4(adap->params.chip)) {
5210 *enabled = !!(ctla & TFEN_F);
5211 tp->port = TFPORT_G(ctla);
5212 tp->invert = !!(ctla & TFINVERTMATCH_F);
5214 *enabled = !!(ctla & T5_TFEN_F);
5215 tp->port = T5_TFPORT_G(ctla);
5216 tp->invert = !!(ctla & T5_TFINVERTMATCH_F);
5218 tp->snap_len = TFCAPTUREMAX_G(ctlb);
5219 tp->min_len = TFMINPKTSIZE_G(ctlb);
5220 tp->skip_ofst = TFOFFSET_G(ctla);
5221 tp->skip_len = TFLENGTH_G(ctla);
5223 ofst = (MPS_TRC_FILTER1_MATCH_A - MPS_TRC_FILTER0_MATCH_A) * idx;
5224 data_reg = MPS_TRC_FILTER0_MATCH_A + ofst;
5225 mask_reg = MPS_TRC_FILTER0_DONT_CARE_A + ofst;
5227 for (i = 0; i < TRACE_LEN / 4; i++, data_reg += 4, mask_reg += 4) {
5228 tp->mask[i] = ~t4_read_reg(adap, mask_reg);
5229 tp->data[i] = t4_read_reg(adap, data_reg) & tp->mask[i];
5234 * t4_pmtx_get_stats - returns the HW stats from PMTX
5235 * @adap: the adapter
5236 * @cnt: where to store the count statistics
5237 * @cycles: where to store the cycle statistics
5239 * Returns performance statistics from PMTX.
5241 void t4_pmtx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[])
5246 for (i = 0; i < adap->params.arch.pm_stats_cnt; i++) {
5247 t4_write_reg(adap, PM_TX_STAT_CONFIG_A, i + 1);
5248 cnt[i] = t4_read_reg(adap, PM_TX_STAT_COUNT_A);
5249 if (is_t4(adap->params.chip)) {
5250 cycles[i] = t4_read_reg64(adap, PM_TX_STAT_LSB_A);
5252 t4_read_indirect(adap, PM_TX_DBG_CTRL_A,
5253 PM_TX_DBG_DATA_A, data, 2,
5254 PM_TX_DBG_STAT_MSB_A);
5255 cycles[i] = (((u64)data[0] << 32) | data[1]);
5261 * t4_pmrx_get_stats - returns the HW stats from PMRX
5262 * @adap: the adapter
5263 * @cnt: where to store the count statistics
5264 * @cycles: where to store the cycle statistics
5266 * Returns performance statistics from PMRX.
5268 void t4_pmrx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[])
5273 for (i = 0; i < adap->params.arch.pm_stats_cnt; i++) {
5274 t4_write_reg(adap, PM_RX_STAT_CONFIG_A, i + 1);
5275 cnt[i] = t4_read_reg(adap, PM_RX_STAT_COUNT_A);
5276 if (is_t4(adap->params.chip)) {
5277 cycles[i] = t4_read_reg64(adap, PM_RX_STAT_LSB_A);
5279 t4_read_indirect(adap, PM_RX_DBG_CTRL_A,
5280 PM_RX_DBG_DATA_A, data, 2,
5281 PM_RX_DBG_STAT_MSB_A);
5282 cycles[i] = (((u64)data[0] << 32) | data[1]);
5288 * t4_get_mps_bg_map - return the buffer groups associated with a port
5289 * @adap: the adapter
5290 * @idx: the port index
5292 * Returns a bitmap indicating which MPS buffer groups are associated
5293 * with the given port. Bit i is set if buffer group i is used by the
5296 unsigned int t4_get_mps_bg_map(struct adapter *adap, int idx)
5298 u32 n = NUMPORTS_G(t4_read_reg(adap, MPS_CMN_CTL_A));
5301 return idx == 0 ? 0xf : 0;
5302 /* In T6 (which is a 2 port card),
5303 * port 0 is mapped to channel 0 and port 1 is mapped to channel 1.
5304 * For 2 port T4/T5 adapter,
5305 * port 0 is mapped to channel 0 and 1,
5306 * port 1 is mapped to channel 2 and 3.
5309 (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5))
5310 return idx < 2 ? (3 << (2 * idx)) : 0;
5315 * t4_get_port_type_description - return Port Type string description
5316 * @port_type: firmware Port Type enumeration
5318 const char *t4_get_port_type_description(enum fw_port_type port_type)
5320 static const char *const port_type_description[] = {
5339 if (port_type < ARRAY_SIZE(port_type_description))
5340 return port_type_description[port_type];
5345 * t4_get_port_stats_offset - collect port stats relative to a previous
5347 * @adap: The adapter
5349 * @stats: Current stats to fill
5350 * @offset: Previous stats snapshot
5352 void t4_get_port_stats_offset(struct adapter *adap, int idx,
5353 struct port_stats *stats,
5354 struct port_stats *offset)
5359 t4_get_port_stats(adap, idx, stats);
5360 for (i = 0, s = (u64 *)stats, o = (u64 *)offset;
5361 i < (sizeof(struct port_stats) / sizeof(u64));
5367 * t4_get_port_stats - collect port statistics
5368 * @adap: the adapter
5369 * @idx: the port index
5370 * @p: the stats structure to fill
5372 * Collect statistics related to the given port from HW.
5374 void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p)
5376 u32 bgmap = t4_get_mps_bg_map(adap, idx);
5378 #define GET_STAT(name) \
5379 t4_read_reg64(adap, \
5380 (is_t4(adap->params.chip) ? PORT_REG(idx, MPS_PORT_STAT_##name##_L) : \
5381 T5_PORT_REG(idx, MPS_PORT_STAT_##name##_L)))
5382 #define GET_STAT_COM(name) t4_read_reg64(adap, MPS_STAT_##name##_L)
5384 p->tx_octets = GET_STAT(TX_PORT_BYTES);
5385 p->tx_frames = GET_STAT(TX_PORT_FRAMES);
5386 p->tx_bcast_frames = GET_STAT(TX_PORT_BCAST);
5387 p->tx_mcast_frames = GET_STAT(TX_PORT_MCAST);
5388 p->tx_ucast_frames = GET_STAT(TX_PORT_UCAST);
5389 p->tx_error_frames = GET_STAT(TX_PORT_ERROR);
5390 p->tx_frames_64 = GET_STAT(TX_PORT_64B);
5391 p->tx_frames_65_127 = GET_STAT(TX_PORT_65B_127B);
5392 p->tx_frames_128_255 = GET_STAT(TX_PORT_128B_255B);
5393 p->tx_frames_256_511 = GET_STAT(TX_PORT_256B_511B);
5394 p->tx_frames_512_1023 = GET_STAT(TX_PORT_512B_1023B);
5395 p->tx_frames_1024_1518 = GET_STAT(TX_PORT_1024B_1518B);
5396 p->tx_frames_1519_max = GET_STAT(TX_PORT_1519B_MAX);
5397 p->tx_drop = GET_STAT(TX_PORT_DROP);
5398 p->tx_pause = GET_STAT(TX_PORT_PAUSE);
5399 p->tx_ppp0 = GET_STAT(TX_PORT_PPP0);
5400 p->tx_ppp1 = GET_STAT(TX_PORT_PPP1);
5401 p->tx_ppp2 = GET_STAT(TX_PORT_PPP2);
5402 p->tx_ppp3 = GET_STAT(TX_PORT_PPP3);
5403 p->tx_ppp4 = GET_STAT(TX_PORT_PPP4);
5404 p->tx_ppp5 = GET_STAT(TX_PORT_PPP5);
5405 p->tx_ppp6 = GET_STAT(TX_PORT_PPP6);
5406 p->tx_ppp7 = GET_STAT(TX_PORT_PPP7);
5408 p->rx_octets = GET_STAT(RX_PORT_BYTES);
5409 p->rx_frames = GET_STAT(RX_PORT_FRAMES);
5410 p->rx_bcast_frames = GET_STAT(RX_PORT_BCAST);
5411 p->rx_mcast_frames = GET_STAT(RX_PORT_MCAST);
5412 p->rx_ucast_frames = GET_STAT(RX_PORT_UCAST);
5413 p->rx_too_long = GET_STAT(RX_PORT_MTU_ERROR);
5414 p->rx_jabber = GET_STAT(RX_PORT_MTU_CRC_ERROR);
5415 p->rx_fcs_err = GET_STAT(RX_PORT_CRC_ERROR);
5416 p->rx_len_err = GET_STAT(RX_PORT_LEN_ERROR);
5417 p->rx_symbol_err = GET_STAT(RX_PORT_SYM_ERROR);
5418 p->rx_runt = GET_STAT(RX_PORT_LESS_64B);
5419 p->rx_frames_64 = GET_STAT(RX_PORT_64B);
5420 p->rx_frames_65_127 = GET_STAT(RX_PORT_65B_127B);
5421 p->rx_frames_128_255 = GET_STAT(RX_PORT_128B_255B);
5422 p->rx_frames_256_511 = GET_STAT(RX_PORT_256B_511B);
5423 p->rx_frames_512_1023 = GET_STAT(RX_PORT_512B_1023B);
5424 p->rx_frames_1024_1518 = GET_STAT(RX_PORT_1024B_1518B);
5425 p->rx_frames_1519_max = GET_STAT(RX_PORT_1519B_MAX);
5426 p->rx_pause = GET_STAT(RX_PORT_PAUSE);
5427 p->rx_ppp0 = GET_STAT(RX_PORT_PPP0);
5428 p->rx_ppp1 = GET_STAT(RX_PORT_PPP1);
5429 p->rx_ppp2 = GET_STAT(RX_PORT_PPP2);
5430 p->rx_ppp3 = GET_STAT(RX_PORT_PPP3);
5431 p->rx_ppp4 = GET_STAT(RX_PORT_PPP4);
5432 p->rx_ppp5 = GET_STAT(RX_PORT_PPP5);
5433 p->rx_ppp6 = GET_STAT(RX_PORT_PPP6);
5434 p->rx_ppp7 = GET_STAT(RX_PORT_PPP7);
5436 p->rx_ovflow0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_MAC_DROP_FRAME) : 0;
5437 p->rx_ovflow1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_MAC_DROP_FRAME) : 0;
5438 p->rx_ovflow2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_MAC_DROP_FRAME) : 0;
5439 p->rx_ovflow3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_MAC_DROP_FRAME) : 0;
5440 p->rx_trunc0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_MAC_TRUNC_FRAME) : 0;
5441 p->rx_trunc1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_MAC_TRUNC_FRAME) : 0;
5442 p->rx_trunc2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_MAC_TRUNC_FRAME) : 0;
5443 p->rx_trunc3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_MAC_TRUNC_FRAME) : 0;
5450 * t4_get_lb_stats - collect loopback port statistics
5451 * @adap: the adapter
5452 * @idx: the loopback port index
5453 * @p: the stats structure to fill
5455 * Return HW statistics for the given loopback port.
5457 void t4_get_lb_stats(struct adapter *adap, int idx, struct lb_port_stats *p)
5459 u32 bgmap = t4_get_mps_bg_map(adap, idx);
5461 #define GET_STAT(name) \
5462 t4_read_reg64(adap, \
5463 (is_t4(adap->params.chip) ? \
5464 PORT_REG(idx, MPS_PORT_STAT_LB_PORT_##name##_L) : \
5465 T5_PORT_REG(idx, MPS_PORT_STAT_LB_PORT_##name##_L)))
5466 #define GET_STAT_COM(name) t4_read_reg64(adap, MPS_STAT_##name##_L)
5468 p->octets = GET_STAT(BYTES);
5469 p->frames = GET_STAT(FRAMES);
5470 p->bcast_frames = GET_STAT(BCAST);
5471 p->mcast_frames = GET_STAT(MCAST);
5472 p->ucast_frames = GET_STAT(UCAST);
5473 p->error_frames = GET_STAT(ERROR);
5475 p->frames_64 = GET_STAT(64B);
5476 p->frames_65_127 = GET_STAT(65B_127B);
5477 p->frames_128_255 = GET_STAT(128B_255B);
5478 p->frames_256_511 = GET_STAT(256B_511B);
5479 p->frames_512_1023 = GET_STAT(512B_1023B);
5480 p->frames_1024_1518 = GET_STAT(1024B_1518B);
5481 p->frames_1519_max = GET_STAT(1519B_MAX);
5482 p->drop = GET_STAT(DROP_FRAMES);
5484 p->ovflow0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_LB_DROP_FRAME) : 0;
5485 p->ovflow1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_LB_DROP_FRAME) : 0;
5486 p->ovflow2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_LB_DROP_FRAME) : 0;
5487 p->ovflow3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_LB_DROP_FRAME) : 0;
5488 p->trunc0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_LB_TRUNC_FRAME) : 0;
5489 p->trunc1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_LB_TRUNC_FRAME) : 0;
5490 p->trunc2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_LB_TRUNC_FRAME) : 0;
5491 p->trunc3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_LB_TRUNC_FRAME) : 0;
5497 /* t4_mk_filtdelwr - create a delete filter WR
5498 * @ftid: the filter ID
5499 * @wr: the filter work request to populate
5500 * @qid: ingress queue to receive the delete notification
5502 * Creates a filter work request to delete the supplied filter. If @qid is
5503 * negative the delete notification is suppressed.
5505 void t4_mk_filtdelwr(unsigned int ftid, struct fw_filter_wr *wr, int qid)
5507 memset(wr, 0, sizeof(*wr));
5508 wr->op_pkd = cpu_to_be32(FW_WR_OP_V(FW_FILTER_WR));
5509 wr->len16_pkd = cpu_to_be32(FW_WR_LEN16_V(sizeof(*wr) / 16));
5510 wr->tid_to_iq = cpu_to_be32(FW_FILTER_WR_TID_V(ftid) |
5511 FW_FILTER_WR_NOREPLY_V(qid < 0));
5512 wr->del_filter_to_l2tix = cpu_to_be32(FW_FILTER_WR_DEL_FILTER_F);
5514 wr->rx_chan_rx_rpl_iq =
5515 cpu_to_be16(FW_FILTER_WR_RX_RPL_IQ_V(qid));
5518 #define INIT_CMD(var, cmd, rd_wr) do { \
5519 (var).op_to_write = cpu_to_be32(FW_CMD_OP_V(FW_##cmd##_CMD) | \
5520 FW_CMD_REQUEST_F | \
5521 FW_CMD_##rd_wr##_F); \
5522 (var).retval_len16 = cpu_to_be32(FW_LEN16(var)); \
5525 int t4_fwaddrspace_write(struct adapter *adap, unsigned int mbox,
5529 struct fw_ldst_cmd c;
5531 memset(&c, 0, sizeof(c));
5532 ldst_addrspace = FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_FIRMWARE);
5533 c.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
5537 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
5538 c.u.addrval.addr = cpu_to_be32(addr);
5539 c.u.addrval.val = cpu_to_be32(val);
5541 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
5545 * t4_mdio_rd - read a PHY register through MDIO
5546 * @adap: the adapter
5547 * @mbox: mailbox to use for the FW command
5548 * @phy_addr: the PHY address
5549 * @mmd: the PHY MMD to access (0 for clause 22 PHYs)
5550 * @reg: the register to read
5551 * @valp: where to store the value
5553 * Issues a FW command through the given mailbox to read a PHY register.
5555 int t4_mdio_rd(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
5556 unsigned int mmd, unsigned int reg, u16 *valp)
5560 struct fw_ldst_cmd c;
5562 memset(&c, 0, sizeof(c));
5563 ldst_addrspace = FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_MDIO);
5564 c.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
5565 FW_CMD_REQUEST_F | FW_CMD_READ_F |
5567 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
5568 c.u.mdio.paddr_mmd = cpu_to_be16(FW_LDST_CMD_PADDR_V(phy_addr) |
5569 FW_LDST_CMD_MMD_V(mmd));
5570 c.u.mdio.raddr = cpu_to_be16(reg);
5572 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
5574 *valp = be16_to_cpu(c.u.mdio.rval);
5579 * t4_mdio_wr - write a PHY register through MDIO
5580 * @adap: the adapter
5581 * @mbox: mailbox to use for the FW command
5582 * @phy_addr: the PHY address
5583 * @mmd: the PHY MMD to access (0 for clause 22 PHYs)
5584 * @reg: the register to write
5585 * @valp: value to write
5587 * Issues a FW command through the given mailbox to write a PHY register.
5589 int t4_mdio_wr(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
5590 unsigned int mmd, unsigned int reg, u16 val)
5593 struct fw_ldst_cmd c;
5595 memset(&c, 0, sizeof(c));
5596 ldst_addrspace = FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_MDIO);
5597 c.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
5598 FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
5600 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
5601 c.u.mdio.paddr_mmd = cpu_to_be16(FW_LDST_CMD_PADDR_V(phy_addr) |
5602 FW_LDST_CMD_MMD_V(mmd));
5603 c.u.mdio.raddr = cpu_to_be16(reg);
5604 c.u.mdio.rval = cpu_to_be16(val);
5606 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
5610 * t4_sge_decode_idma_state - decode the idma state
5611 * @adap: the adapter
5612 * @state: the state idma is stuck in
5614 void t4_sge_decode_idma_state(struct adapter *adapter, int state)
5616 static const char * const t4_decode[] = {
5618 "IDMA_PUSH_MORE_CPL_FIFO",
5619 "IDMA_PUSH_CPL_MSG_HEADER_TO_FIFO",
5621 "IDMA_PHYSADDR_SEND_PCIEHDR",
5622 "IDMA_PHYSADDR_SEND_PAYLOAD_FIRST",
5623 "IDMA_PHYSADDR_SEND_PAYLOAD",
5624 "IDMA_SEND_FIFO_TO_IMSG",
5625 "IDMA_FL_REQ_DATA_FL_PREP",
5626 "IDMA_FL_REQ_DATA_FL",
5628 "IDMA_FL_H_REQ_HEADER_FL",
5629 "IDMA_FL_H_SEND_PCIEHDR",
5630 "IDMA_FL_H_PUSH_CPL_FIFO",
5631 "IDMA_FL_H_SEND_CPL",
5632 "IDMA_FL_H_SEND_IP_HDR_FIRST",
5633 "IDMA_FL_H_SEND_IP_HDR",
5634 "IDMA_FL_H_REQ_NEXT_HEADER_FL",
5635 "IDMA_FL_H_SEND_NEXT_PCIEHDR",
5636 "IDMA_FL_H_SEND_IP_HDR_PADDING",
5637 "IDMA_FL_D_SEND_PCIEHDR",
5638 "IDMA_FL_D_SEND_CPL_AND_IP_HDR",
5639 "IDMA_FL_D_REQ_NEXT_DATA_FL",
5640 "IDMA_FL_SEND_PCIEHDR",
5641 "IDMA_FL_PUSH_CPL_FIFO",
5643 "IDMA_FL_SEND_PAYLOAD_FIRST",
5644 "IDMA_FL_SEND_PAYLOAD",
5645 "IDMA_FL_REQ_NEXT_DATA_FL",
5646 "IDMA_FL_SEND_NEXT_PCIEHDR",
5647 "IDMA_FL_SEND_PADDING",
5648 "IDMA_FL_SEND_COMPLETION_TO_IMSG",
5649 "IDMA_FL_SEND_FIFO_TO_IMSG",
5650 "IDMA_FL_REQ_DATAFL_DONE",
5651 "IDMA_FL_REQ_HEADERFL_DONE",
5653 static const char * const t5_decode[] = {
5656 "IDMA_PUSH_MORE_CPL_FIFO",
5657 "IDMA_PUSH_CPL_MSG_HEADER_TO_FIFO",
5658 "IDMA_SGEFLRFLUSH_SEND_PCIEHDR",
5659 "IDMA_PHYSADDR_SEND_PCIEHDR",
5660 "IDMA_PHYSADDR_SEND_PAYLOAD_FIRST",
5661 "IDMA_PHYSADDR_SEND_PAYLOAD",
5662 "IDMA_SEND_FIFO_TO_IMSG",
5663 "IDMA_FL_REQ_DATA_FL",
5665 "IDMA_FL_DROP_SEND_INC",
5666 "IDMA_FL_H_REQ_HEADER_FL",
5667 "IDMA_FL_H_SEND_PCIEHDR",
5668 "IDMA_FL_H_PUSH_CPL_FIFO",
5669 "IDMA_FL_H_SEND_CPL",
5670 "IDMA_FL_H_SEND_IP_HDR_FIRST",
5671 "IDMA_FL_H_SEND_IP_HDR",
5672 "IDMA_FL_H_REQ_NEXT_HEADER_FL",
5673 "IDMA_FL_H_SEND_NEXT_PCIEHDR",
5674 "IDMA_FL_H_SEND_IP_HDR_PADDING",
5675 "IDMA_FL_D_SEND_PCIEHDR",
5676 "IDMA_FL_D_SEND_CPL_AND_IP_HDR",
5677 "IDMA_FL_D_REQ_NEXT_DATA_FL",
5678 "IDMA_FL_SEND_PCIEHDR",
5679 "IDMA_FL_PUSH_CPL_FIFO",
5681 "IDMA_FL_SEND_PAYLOAD_FIRST",
5682 "IDMA_FL_SEND_PAYLOAD",
5683 "IDMA_FL_REQ_NEXT_DATA_FL",
5684 "IDMA_FL_SEND_NEXT_PCIEHDR",
5685 "IDMA_FL_SEND_PADDING",
5686 "IDMA_FL_SEND_COMPLETION_TO_IMSG",
5688 static const char * const t6_decode[] = {
5690 "IDMA_PUSH_MORE_CPL_FIFO",
5691 "IDMA_PUSH_CPL_MSG_HEADER_TO_FIFO",
5692 "IDMA_SGEFLRFLUSH_SEND_PCIEHDR",
5693 "IDMA_PHYSADDR_SEND_PCIEHDR",
5694 "IDMA_PHYSADDR_SEND_PAYLOAD_FIRST",
5695 "IDMA_PHYSADDR_SEND_PAYLOAD",
5696 "IDMA_FL_REQ_DATA_FL",
5698 "IDMA_FL_DROP_SEND_INC",
5699 "IDMA_FL_H_REQ_HEADER_FL",
5700 "IDMA_FL_H_SEND_PCIEHDR",
5701 "IDMA_FL_H_PUSH_CPL_FIFO",
5702 "IDMA_FL_H_SEND_CPL",
5703 "IDMA_FL_H_SEND_IP_HDR_FIRST",
5704 "IDMA_FL_H_SEND_IP_HDR",
5705 "IDMA_FL_H_REQ_NEXT_HEADER_FL",
5706 "IDMA_FL_H_SEND_NEXT_PCIEHDR",
5707 "IDMA_FL_H_SEND_IP_HDR_PADDING",
5708 "IDMA_FL_D_SEND_PCIEHDR",
5709 "IDMA_FL_D_SEND_CPL_AND_IP_HDR",
5710 "IDMA_FL_D_REQ_NEXT_DATA_FL",
5711 "IDMA_FL_SEND_PCIEHDR",
5712 "IDMA_FL_PUSH_CPL_FIFO",
5714 "IDMA_FL_SEND_PAYLOAD_FIRST",
5715 "IDMA_FL_SEND_PAYLOAD",
5716 "IDMA_FL_REQ_NEXT_DATA_FL",
5717 "IDMA_FL_SEND_NEXT_PCIEHDR",
5718 "IDMA_FL_SEND_PADDING",
5719 "IDMA_FL_SEND_COMPLETION_TO_IMSG",
5721 static const u32 sge_regs[] = {
5722 SGE_DEBUG_DATA_LOW_INDEX_2_A,
5723 SGE_DEBUG_DATA_LOW_INDEX_3_A,
5724 SGE_DEBUG_DATA_HIGH_INDEX_10_A,
5726 const char **sge_idma_decode;
5727 int sge_idma_decode_nstates;
5729 unsigned int chip_version = CHELSIO_CHIP_VERSION(adapter->params.chip);
5731 /* Select the right set of decode strings to dump depending on the
5732 * adapter chip type.
5734 switch (chip_version) {
5736 sge_idma_decode = (const char **)t4_decode;
5737 sge_idma_decode_nstates = ARRAY_SIZE(t4_decode);
5741 sge_idma_decode = (const char **)t5_decode;
5742 sge_idma_decode_nstates = ARRAY_SIZE(t5_decode);
5746 sge_idma_decode = (const char **)t6_decode;
5747 sge_idma_decode_nstates = ARRAY_SIZE(t6_decode);
5751 dev_err(adapter->pdev_dev,
5752 "Unsupported chip version %d\n", chip_version);
5756 if (is_t4(adapter->params.chip)) {
5757 sge_idma_decode = (const char **)t4_decode;
5758 sge_idma_decode_nstates = ARRAY_SIZE(t4_decode);
5760 sge_idma_decode = (const char **)t5_decode;
5761 sge_idma_decode_nstates = ARRAY_SIZE(t5_decode);
5764 if (state < sge_idma_decode_nstates)
5765 CH_WARN(adapter, "idma state %s\n", sge_idma_decode[state]);
5767 CH_WARN(adapter, "idma state %d unknown\n", state);
5769 for (i = 0; i < ARRAY_SIZE(sge_regs); i++)
5770 CH_WARN(adapter, "SGE register %#x value %#x\n",
5771 sge_regs[i], t4_read_reg(adapter, sge_regs[i]));
5775 * t4_sge_ctxt_flush - flush the SGE context cache
5776 * @adap: the adapter
5777 * @mbox: mailbox to use for the FW command
5779 * Issues a FW command through the given mailbox to flush the
5780 * SGE context cache.
5782 int t4_sge_ctxt_flush(struct adapter *adap, unsigned int mbox)
5786 struct fw_ldst_cmd c;
5788 memset(&c, 0, sizeof(c));
5789 ldst_addrspace = FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_SGE_EGRC);
5790 c.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
5791 FW_CMD_REQUEST_F | FW_CMD_READ_F |
5793 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
5794 c.u.idctxt.msg_ctxtflush = cpu_to_be32(FW_LDST_CMD_CTXTFLUSH_F);
5796 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
5801 * t4_fw_hello - establish communication with FW
5802 * @adap: the adapter
5803 * @mbox: mailbox to use for the FW command
5804 * @evt_mbox: mailbox to receive async FW events
5805 * @master: specifies the caller's willingness to be the device master
5806 * @state: returns the current device state (if non-NULL)
5808 * Issues a command to establish communication with FW. Returns either
5809 * an error (negative integer) or the mailbox of the Master PF.
5811 int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox,
5812 enum dev_master master, enum dev_state *state)
5815 struct fw_hello_cmd c;
5817 unsigned int master_mbox;
5818 int retries = FW_CMD_HELLO_RETRIES;
5821 memset(&c, 0, sizeof(c));
5822 INIT_CMD(c, HELLO, WRITE);
5823 c.err_to_clearinit = cpu_to_be32(
5824 FW_HELLO_CMD_MASTERDIS_V(master == MASTER_CANT) |
5825 FW_HELLO_CMD_MASTERFORCE_V(master == MASTER_MUST) |
5826 FW_HELLO_CMD_MBMASTER_V(master == MASTER_MUST ?
5827 mbox : FW_HELLO_CMD_MBMASTER_M) |
5828 FW_HELLO_CMD_MBASYNCNOT_V(evt_mbox) |
5829 FW_HELLO_CMD_STAGE_V(fw_hello_cmd_stage_os) |
5830 FW_HELLO_CMD_CLEARINIT_F);
5833 * Issue the HELLO command to the firmware. If it's not successful
5834 * but indicates that we got a "busy" or "timeout" condition, retry
5835 * the HELLO until we exhaust our retry limit. If we do exceed our
5836 * retry limit, check to see if the firmware left us any error
5837 * information and report that if so.
5839 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
5841 if ((ret == -EBUSY || ret == -ETIMEDOUT) && retries-- > 0)
5843 if (t4_read_reg(adap, PCIE_FW_A) & PCIE_FW_ERR_F)
5844 t4_report_fw_error(adap);
5848 v = be32_to_cpu(c.err_to_clearinit);
5849 master_mbox = FW_HELLO_CMD_MBMASTER_G(v);
5851 if (v & FW_HELLO_CMD_ERR_F)
5852 *state = DEV_STATE_ERR;
5853 else if (v & FW_HELLO_CMD_INIT_F)
5854 *state = DEV_STATE_INIT;
5856 *state = DEV_STATE_UNINIT;
5860 * If we're not the Master PF then we need to wait around for the
5861 * Master PF Driver to finish setting up the adapter.
5863 * Note that we also do this wait if we're a non-Master-capable PF and
5864 * there is no current Master PF; a Master PF may show up momentarily
5865 * and we wouldn't want to fail pointlessly. (This can happen when an
5866 * OS loads lots of different drivers rapidly at the same time). In
5867 * this case, the Master PF returned by the firmware will be
5868 * PCIE_FW_MASTER_M so the test below will work ...
5870 if ((v & (FW_HELLO_CMD_ERR_F|FW_HELLO_CMD_INIT_F)) == 0 &&
5871 master_mbox != mbox) {
5872 int waiting = FW_CMD_HELLO_TIMEOUT;
5875 * Wait for the firmware to either indicate an error or
5876 * initialized state. If we see either of these we bail out
5877 * and report the issue to the caller. If we exhaust the
5878 * "hello timeout" and we haven't exhausted our retries, try
5879 * again. Otherwise bail with a timeout error.
5888 * If neither Error nor Initialialized are indicated
5889 * by the firmware keep waiting till we exaust our
5890 * timeout ... and then retry if we haven't exhausted
5893 pcie_fw = t4_read_reg(adap, PCIE_FW_A);
5894 if (!(pcie_fw & (PCIE_FW_ERR_F|PCIE_FW_INIT_F))) {
5905 * We either have an Error or Initialized condition
5906 * report errors preferentially.
5909 if (pcie_fw & PCIE_FW_ERR_F)
5910 *state = DEV_STATE_ERR;
5911 else if (pcie_fw & PCIE_FW_INIT_F)
5912 *state = DEV_STATE_INIT;
5916 * If we arrived before a Master PF was selected and
5917 * there's not a valid Master PF, grab its identity
5920 if (master_mbox == PCIE_FW_MASTER_M &&
5921 (pcie_fw & PCIE_FW_MASTER_VLD_F))
5922 master_mbox = PCIE_FW_MASTER_G(pcie_fw);
5931 * t4_fw_bye - end communication with FW
5932 * @adap: the adapter
5933 * @mbox: mailbox to use for the FW command
5935 * Issues a command to terminate communication with FW.
5937 int t4_fw_bye(struct adapter *adap, unsigned int mbox)
5939 struct fw_bye_cmd c;
5941 memset(&c, 0, sizeof(c));
5942 INIT_CMD(c, BYE, WRITE);
5943 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
5947 * t4_init_cmd - ask FW to initialize the device
5948 * @adap: the adapter
5949 * @mbox: mailbox to use for the FW command
5951 * Issues a command to FW to partially initialize the device. This
5952 * performs initialization that generally doesn't depend on user input.
5954 int t4_early_init(struct adapter *adap, unsigned int mbox)
5956 struct fw_initialize_cmd c;
5958 memset(&c, 0, sizeof(c));
5959 INIT_CMD(c, INITIALIZE, WRITE);
5960 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
5964 * t4_fw_reset - issue a reset to FW
5965 * @adap: the adapter
5966 * @mbox: mailbox to use for the FW command
5967 * @reset: specifies the type of reset to perform
5969 * Issues a reset command of the specified type to FW.
5971 int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset)
5973 struct fw_reset_cmd c;
5975 memset(&c, 0, sizeof(c));
5976 INIT_CMD(c, RESET, WRITE);
5977 c.val = cpu_to_be32(reset);
5978 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
5982 * t4_fw_halt - issue a reset/halt to FW and put uP into RESET
5983 * @adap: the adapter
5984 * @mbox: mailbox to use for the FW RESET command (if desired)
5985 * @force: force uP into RESET even if FW RESET command fails
5987 * Issues a RESET command to firmware (if desired) with a HALT indication
5988 * and then puts the microprocessor into RESET state. The RESET command
5989 * will only be issued if a legitimate mailbox is provided (mbox <=
5990 * PCIE_FW_MASTER_M).
5992 * This is generally used in order for the host to safely manipulate the
5993 * adapter without fear of conflicting with whatever the firmware might
5994 * be doing. The only way out of this state is to RESTART the firmware
5997 static int t4_fw_halt(struct adapter *adap, unsigned int mbox, int force)
6002 * If a legitimate mailbox is provided, issue a RESET command
6003 * with a HALT indication.
6005 if (mbox <= PCIE_FW_MASTER_M) {
6006 struct fw_reset_cmd c;
6008 memset(&c, 0, sizeof(c));
6009 INIT_CMD(c, RESET, WRITE);
6010 c.val = cpu_to_be32(PIORST_F | PIORSTMODE_F);
6011 c.halt_pkd = cpu_to_be32(FW_RESET_CMD_HALT_F);
6012 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
6016 * Normally we won't complete the operation if the firmware RESET
6017 * command fails but if our caller insists we'll go ahead and put the
6018 * uP into RESET. This can be useful if the firmware is hung or even
6019 * missing ... We'll have to take the risk of putting the uP into
6020 * RESET without the cooperation of firmware in that case.
6022 * We also force the firmware's HALT flag to be on in case we bypassed
6023 * the firmware RESET command above or we're dealing with old firmware
6024 * which doesn't have the HALT capability. This will serve as a flag
6025 * for the incoming firmware to know that it's coming out of a HALT
6026 * rather than a RESET ... if it's new enough to understand that ...
6028 if (ret == 0 || force) {
6029 t4_set_reg_field(adap, CIM_BOOT_CFG_A, UPCRST_F, UPCRST_F);
6030 t4_set_reg_field(adap, PCIE_FW_A, PCIE_FW_HALT_F,
6035 * And we always return the result of the firmware RESET command
6036 * even when we force the uP into RESET ...
6042 * t4_fw_restart - restart the firmware by taking the uP out of RESET
6043 * @adap: the adapter
6044 * @reset: if we want to do a RESET to restart things
6046 * Restart firmware previously halted by t4_fw_halt(). On successful
6047 * return the previous PF Master remains as the new PF Master and there
6048 * is no need to issue a new HELLO command, etc.
6050 * We do this in two ways:
6052 * 1. If we're dealing with newer firmware we'll simply want to take
6053 * the chip's microprocessor out of RESET. This will cause the
6054 * firmware to start up from its start vector. And then we'll loop
6055 * until the firmware indicates it's started again (PCIE_FW.HALT
6056 * reset to 0) or we timeout.
6058 * 2. If we're dealing with older firmware then we'll need to RESET
6059 * the chip since older firmware won't recognize the PCIE_FW.HALT
6060 * flag and automatically RESET itself on startup.
6062 static int t4_fw_restart(struct adapter *adap, unsigned int mbox, int reset)
6066 * Since we're directing the RESET instead of the firmware
6067 * doing it automatically, we need to clear the PCIE_FW.HALT
6070 t4_set_reg_field(adap, PCIE_FW_A, PCIE_FW_HALT_F, 0);
6073 * If we've been given a valid mailbox, first try to get the
6074 * firmware to do the RESET. If that works, great and we can
6075 * return success. Otherwise, if we haven't been given a
6076 * valid mailbox or the RESET command failed, fall back to
6077 * hitting the chip with a hammer.
6079 if (mbox <= PCIE_FW_MASTER_M) {
6080 t4_set_reg_field(adap, CIM_BOOT_CFG_A, UPCRST_F, 0);
6082 if (t4_fw_reset(adap, mbox,
6083 PIORST_F | PIORSTMODE_F) == 0)
6087 t4_write_reg(adap, PL_RST_A, PIORST_F | PIORSTMODE_F);
6092 t4_set_reg_field(adap, CIM_BOOT_CFG_A, UPCRST_F, 0);
6093 for (ms = 0; ms < FW_CMD_MAX_TIMEOUT; ) {
6094 if (!(t4_read_reg(adap, PCIE_FW_A) & PCIE_FW_HALT_F))
6105 * t4_fw_upgrade - perform all of the steps necessary to upgrade FW
6106 * @adap: the adapter
6107 * @mbox: mailbox to use for the FW RESET command (if desired)
6108 * @fw_data: the firmware image to write
6110 * @force: force upgrade even if firmware doesn't cooperate
6112 * Perform all of the steps necessary for upgrading an adapter's
6113 * firmware image. Normally this requires the cooperation of the
6114 * existing firmware in order to halt all existing activities
6115 * but if an invalid mailbox token is passed in we skip that step
6116 * (though we'll still put the adapter microprocessor into RESET in
6119 * On successful return the new firmware will have been loaded and
6120 * the adapter will have been fully RESET losing all previous setup
6121 * state. On unsuccessful return the adapter may be completely hosed ...
6122 * positive errno indicates that the adapter is ~probably~ intact, a
6123 * negative errno indicates that things are looking bad ...
6125 int t4_fw_upgrade(struct adapter *adap, unsigned int mbox,
6126 const u8 *fw_data, unsigned int size, int force)
6128 const struct fw_hdr *fw_hdr = (const struct fw_hdr *)fw_data;
6131 if (!t4_fw_matches_chip(adap, fw_hdr))
6134 ret = t4_fw_halt(adap, mbox, force);
6135 if (ret < 0 && !force)
6138 ret = t4_load_fw(adap, fw_data, size);
6143 * Older versions of the firmware don't understand the new
6144 * PCIE_FW.HALT flag and so won't know to perform a RESET when they
6145 * restart. So for newly loaded older firmware we'll have to do the
6146 * RESET for it so it starts up on a clean slate. We can tell if
6147 * the newly loaded firmware will handle this right by checking
6148 * its header flags to see if it advertises the capability.
6150 reset = ((be32_to_cpu(fw_hdr->flags) & FW_HDR_FLAGS_RESET_HALT) == 0);
6151 return t4_fw_restart(adap, mbox, reset);
6155 * t4_fl_pkt_align - return the fl packet alignment
6156 * @adap: the adapter
6158 * T4 has a single field to specify the packing and padding boundary.
6159 * T5 onwards has separate fields for this and hence the alignment for
6160 * next packet offset is maximum of these two.
6163 int t4_fl_pkt_align(struct adapter *adap)
6165 u32 sge_control, sge_control2;
6166 unsigned int ingpadboundary, ingpackboundary, fl_align, ingpad_shift;
6168 sge_control = t4_read_reg(adap, SGE_CONTROL_A);
6170 /* T4 uses a single control field to specify both the PCIe Padding and
6171 * Packing Boundary. T5 introduced the ability to specify these
6172 * separately. The actual Ingress Packet Data alignment boundary
6173 * within Packed Buffer Mode is the maximum of these two
6174 * specifications. (Note that it makes no real practical sense to
6175 * have the Pading Boudary be larger than the Packing Boundary but you
6176 * could set the chip up that way and, in fact, legacy T4 code would
6177 * end doing this because it would initialize the Padding Boundary and
6178 * leave the Packing Boundary initialized to 0 (16 bytes).)
6179 * Padding Boundary values in T6 starts from 8B,
6180 * where as it is 32B for T4 and T5.
6182 if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5)
6183 ingpad_shift = INGPADBOUNDARY_SHIFT_X;
6185 ingpad_shift = T6_INGPADBOUNDARY_SHIFT_X;
6187 ingpadboundary = 1 << (INGPADBOUNDARY_G(sge_control) + ingpad_shift);
6189 fl_align = ingpadboundary;
6190 if (!is_t4(adap->params.chip)) {
6191 /* T5 has a weird interpretation of one of the PCIe Packing
6192 * Boundary values. No idea why ...
6194 sge_control2 = t4_read_reg(adap, SGE_CONTROL2_A);
6195 ingpackboundary = INGPACKBOUNDARY_G(sge_control2);
6196 if (ingpackboundary == INGPACKBOUNDARY_16B_X)
6197 ingpackboundary = 16;
6199 ingpackboundary = 1 << (ingpackboundary +
6200 INGPACKBOUNDARY_SHIFT_X);
6202 fl_align = max(ingpadboundary, ingpackboundary);
6208 * t4_fixup_host_params - fix up host-dependent parameters
6209 * @adap: the adapter
6210 * @page_size: the host's Base Page Size
6211 * @cache_line_size: the host's Cache Line Size
6213 * Various registers in T4 contain values which are dependent on the
6214 * host's Base Page and Cache Line Sizes. This function will fix all of
6215 * those registers with the appropriate values as passed in ...
6217 int t4_fixup_host_params(struct adapter *adap, unsigned int page_size,
6218 unsigned int cache_line_size)
6220 unsigned int page_shift = fls(page_size) - 1;
6221 unsigned int sge_hps = page_shift - 10;
6222 unsigned int stat_len = cache_line_size > 64 ? 128 : 64;
6223 unsigned int fl_align = cache_line_size < 32 ? 32 : cache_line_size;
6224 unsigned int fl_align_log = fls(fl_align) - 1;
6225 unsigned int ingpad;
6227 t4_write_reg(adap, SGE_HOST_PAGE_SIZE_A,
6228 HOSTPAGESIZEPF0_V(sge_hps) |
6229 HOSTPAGESIZEPF1_V(sge_hps) |
6230 HOSTPAGESIZEPF2_V(sge_hps) |
6231 HOSTPAGESIZEPF3_V(sge_hps) |
6232 HOSTPAGESIZEPF4_V(sge_hps) |
6233 HOSTPAGESIZEPF5_V(sge_hps) |
6234 HOSTPAGESIZEPF6_V(sge_hps) |
6235 HOSTPAGESIZEPF7_V(sge_hps));
6237 if (is_t4(adap->params.chip)) {
6238 t4_set_reg_field(adap, SGE_CONTROL_A,
6239 INGPADBOUNDARY_V(INGPADBOUNDARY_M) |
6240 EGRSTATUSPAGESIZE_F,
6241 INGPADBOUNDARY_V(fl_align_log -
6242 INGPADBOUNDARY_SHIFT_X) |
6243 EGRSTATUSPAGESIZE_V(stat_len != 64));
6245 /* T5 introduced the separation of the Free List Padding and
6246 * Packing Boundaries. Thus, we can select a smaller Padding
6247 * Boundary to avoid uselessly chewing up PCIe Link and Memory
6248 * Bandwidth, and use a Packing Boundary which is large enough
6249 * to avoid false sharing between CPUs, etc.
6251 * For the PCI Link, the smaller the Padding Boundary the
6252 * better. For the Memory Controller, a smaller Padding
6253 * Boundary is better until we cross under the Memory Line
6254 * Size (the minimum unit of transfer to/from Memory). If we
6255 * have a Padding Boundary which is smaller than the Memory
6256 * Line Size, that'll involve a Read-Modify-Write cycle on the
6257 * Memory Controller which is never good. For T5 the smallest
6258 * Padding Boundary which we can select is 32 bytes which is
6259 * larger than any known Memory Controller Line Size so we'll
6262 * T5 has a different interpretation of the "0" value for the
6263 * Packing Boundary. This corresponds to 16 bytes instead of
6264 * the expected 32 bytes. We never have a Packing Boundary
6265 * less than 32 bytes so we can't use that special value but
6266 * on the other hand, if we wanted 32 bytes, the best we can
6267 * really do is 64 bytes.
6269 if (fl_align <= 32) {
6274 if (is_t5(adap->params.chip))
6275 ingpad = INGPCIEBOUNDARY_32B_X;
6277 ingpad = T6_INGPADBOUNDARY_32B_X;
6279 t4_set_reg_field(adap, SGE_CONTROL_A,
6280 INGPADBOUNDARY_V(INGPADBOUNDARY_M) |
6281 EGRSTATUSPAGESIZE_F,
6282 INGPADBOUNDARY_V(ingpad) |
6283 EGRSTATUSPAGESIZE_V(stat_len != 64));
6284 t4_set_reg_field(adap, SGE_CONTROL2_A,
6285 INGPACKBOUNDARY_V(INGPACKBOUNDARY_M),
6286 INGPACKBOUNDARY_V(fl_align_log -
6287 INGPACKBOUNDARY_SHIFT_X));
6290 * Adjust various SGE Free List Host Buffer Sizes.
6292 * This is something of a crock since we're using fixed indices into
6293 * the array which are also known by the sge.c code and the T4
6294 * Firmware Configuration File. We need to come up with a much better
6295 * approach to managing this array. For now, the first four entries
6300 * 2: Buffer size corresponding to 1500 byte MTU (unpacked mode)
6301 * 3: Buffer size corresponding to 9000 byte MTU (unpacked mode)
6303 * For the single-MTU buffers in unpacked mode we need to include
6304 * space for the SGE Control Packet Shift, 14 byte Ethernet header,
6305 * possible 4 byte VLAN tag, all rounded up to the next Ingress Packet
6306 * Padding boundary. All of these are accommodated in the Factory
6307 * Default Firmware Configuration File but we need to adjust it for
6308 * this host's cache line size.
6310 t4_write_reg(adap, SGE_FL_BUFFER_SIZE0_A, page_size);
6311 t4_write_reg(adap, SGE_FL_BUFFER_SIZE2_A,
6312 (t4_read_reg(adap, SGE_FL_BUFFER_SIZE2_A) + fl_align-1)
6314 t4_write_reg(adap, SGE_FL_BUFFER_SIZE3_A,
6315 (t4_read_reg(adap, SGE_FL_BUFFER_SIZE3_A) + fl_align-1)
6318 t4_write_reg(adap, ULP_RX_TDDP_PSZ_A, HPZ0_V(page_shift - 12));
6324 * t4_fw_initialize - ask FW to initialize the device
6325 * @adap: the adapter
6326 * @mbox: mailbox to use for the FW command
6328 * Issues a command to FW to partially initialize the device. This
6329 * performs initialization that generally doesn't depend on user input.
6331 int t4_fw_initialize(struct adapter *adap, unsigned int mbox)
6333 struct fw_initialize_cmd c;
6335 memset(&c, 0, sizeof(c));
6336 INIT_CMD(c, INITIALIZE, WRITE);
6337 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
6341 * t4_query_params_rw - query FW or device parameters
6342 * @adap: the adapter
6343 * @mbox: mailbox to use for the FW command
6346 * @nparams: the number of parameters
6347 * @params: the parameter names
6348 * @val: the parameter values
6349 * @rw: Write and read flag
6351 * Reads the value of FW or device parameters. Up to 7 parameters can be
6354 int t4_query_params_rw(struct adapter *adap, unsigned int mbox, unsigned int pf,
6355 unsigned int vf, unsigned int nparams, const u32 *params,
6359 struct fw_params_cmd c;
6360 __be32 *p = &c.param[0].mnem;
6365 memset(&c, 0, sizeof(c));
6366 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_PARAMS_CMD) |
6367 FW_CMD_REQUEST_F | FW_CMD_READ_F |
6368 FW_PARAMS_CMD_PFN_V(pf) |
6369 FW_PARAMS_CMD_VFN_V(vf));
6370 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
6372 for (i = 0; i < nparams; i++) {
6373 *p++ = cpu_to_be32(*params++);
6375 *p = cpu_to_be32(*(val + i));
6379 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
6381 for (i = 0, p = &c.param[0].val; i < nparams; i++, p += 2)
6382 *val++ = be32_to_cpu(*p);
6386 int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
6387 unsigned int vf, unsigned int nparams, const u32 *params,
6390 return t4_query_params_rw(adap, mbox, pf, vf, nparams, params, val, 0);
6394 * t4_set_params_timeout - sets FW or device parameters
6395 * @adap: the adapter
6396 * @mbox: mailbox to use for the FW command
6399 * @nparams: the number of parameters
6400 * @params: the parameter names
6401 * @val: the parameter values
6402 * @timeout: the timeout time
6404 * Sets the value of FW or device parameters. Up to 7 parameters can be
6405 * specified at once.
6407 int t4_set_params_timeout(struct adapter *adap, unsigned int mbox,
6408 unsigned int pf, unsigned int vf,
6409 unsigned int nparams, const u32 *params,
6410 const u32 *val, int timeout)
6412 struct fw_params_cmd c;
6413 __be32 *p = &c.param[0].mnem;
6418 memset(&c, 0, sizeof(c));
6419 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_PARAMS_CMD) |
6420 FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
6421 FW_PARAMS_CMD_PFN_V(pf) |
6422 FW_PARAMS_CMD_VFN_V(vf));
6423 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
6426 *p++ = cpu_to_be32(*params++);
6427 *p++ = cpu_to_be32(*val++);
6430 return t4_wr_mbox_timeout(adap, mbox, &c, sizeof(c), NULL, timeout);
6434 * t4_set_params - sets FW or device parameters
6435 * @adap: the adapter
6436 * @mbox: mailbox to use for the FW command
6439 * @nparams: the number of parameters
6440 * @params: the parameter names
6441 * @val: the parameter values
6443 * Sets the value of FW or device parameters. Up to 7 parameters can be
6444 * specified at once.
6446 int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
6447 unsigned int vf, unsigned int nparams, const u32 *params,
6450 return t4_set_params_timeout(adap, mbox, pf, vf, nparams, params, val,
6451 FW_CMD_MAX_TIMEOUT);
6455 * t4_cfg_pfvf - configure PF/VF resource limits
6456 * @adap: the adapter
6457 * @mbox: mailbox to use for the FW command
6458 * @pf: the PF being configured
6459 * @vf: the VF being configured
6460 * @txq: the max number of egress queues
6461 * @txq_eth_ctrl: the max number of egress Ethernet or control queues
6462 * @rxqi: the max number of interrupt-capable ingress queues
6463 * @rxq: the max number of interruptless ingress queues
6464 * @tc: the PCI traffic class
6465 * @vi: the max number of virtual interfaces
6466 * @cmask: the channel access rights mask for the PF/VF
6467 * @pmask: the port access rights mask for the PF/VF
6468 * @nexact: the maximum number of exact MPS filters
6469 * @rcaps: read capabilities
6470 * @wxcaps: write/execute capabilities
6472 * Configures resource limits and capabilities for a physical or virtual
6475 int t4_cfg_pfvf(struct adapter *adap, unsigned int mbox, unsigned int pf,
6476 unsigned int vf, unsigned int txq, unsigned int txq_eth_ctrl,
6477 unsigned int rxqi, unsigned int rxq, unsigned int tc,
6478 unsigned int vi, unsigned int cmask, unsigned int pmask,
6479 unsigned int nexact, unsigned int rcaps, unsigned int wxcaps)
6481 struct fw_pfvf_cmd c;
6483 memset(&c, 0, sizeof(c));
6484 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_PFVF_CMD) | FW_CMD_REQUEST_F |
6485 FW_CMD_WRITE_F | FW_PFVF_CMD_PFN_V(pf) |
6486 FW_PFVF_CMD_VFN_V(vf));
6487 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
6488 c.niqflint_niq = cpu_to_be32(FW_PFVF_CMD_NIQFLINT_V(rxqi) |
6489 FW_PFVF_CMD_NIQ_V(rxq));
6490 c.type_to_neq = cpu_to_be32(FW_PFVF_CMD_CMASK_V(cmask) |
6491 FW_PFVF_CMD_PMASK_V(pmask) |
6492 FW_PFVF_CMD_NEQ_V(txq));
6493 c.tc_to_nexactf = cpu_to_be32(FW_PFVF_CMD_TC_V(tc) |
6494 FW_PFVF_CMD_NVI_V(vi) |
6495 FW_PFVF_CMD_NEXACTF_V(nexact));
6496 c.r_caps_to_nethctrl = cpu_to_be32(FW_PFVF_CMD_R_CAPS_V(rcaps) |
6497 FW_PFVF_CMD_WX_CAPS_V(wxcaps) |
6498 FW_PFVF_CMD_NETHCTRL_V(txq_eth_ctrl));
6499 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
6503 * t4_alloc_vi - allocate a virtual interface
6504 * @adap: the adapter
6505 * @mbox: mailbox to use for the FW command
6506 * @port: physical port associated with the VI
6507 * @pf: the PF owning the VI
6508 * @vf: the VF owning the VI
6509 * @nmac: number of MAC addresses needed (1 to 5)
6510 * @mac: the MAC addresses of the VI
6511 * @rss_size: size of RSS table slice associated with this VI
6513 * Allocates a virtual interface for the given physical port. If @mac is
6514 * not %NULL it contains the MAC addresses of the VI as assigned by FW.
6515 * @mac should be large enough to hold @nmac Ethernet addresses, they are
6516 * stored consecutively so the space needed is @nmac * 6 bytes.
6517 * Returns a negative error number or the non-negative VI id.
6519 int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port,
6520 unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac,
6521 unsigned int *rss_size)
6526 memset(&c, 0, sizeof(c));
6527 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_VI_CMD) | FW_CMD_REQUEST_F |
6528 FW_CMD_WRITE_F | FW_CMD_EXEC_F |
6529 FW_VI_CMD_PFN_V(pf) | FW_VI_CMD_VFN_V(vf));
6530 c.alloc_to_len16 = cpu_to_be32(FW_VI_CMD_ALLOC_F | FW_LEN16(c));
6531 c.portid_pkd = FW_VI_CMD_PORTID_V(port);
6534 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
6539 memcpy(mac, c.mac, sizeof(c.mac));
6542 memcpy(mac + 24, c.nmac3, sizeof(c.nmac3));
6544 memcpy(mac + 18, c.nmac2, sizeof(c.nmac2));
6546 memcpy(mac + 12, c.nmac1, sizeof(c.nmac1));
6548 memcpy(mac + 6, c.nmac0, sizeof(c.nmac0));
6552 *rss_size = FW_VI_CMD_RSSSIZE_G(be16_to_cpu(c.rsssize_pkd));
6553 return FW_VI_CMD_VIID_G(be16_to_cpu(c.type_viid));
6557 * t4_free_vi - free a virtual interface
6558 * @adap: the adapter
6559 * @mbox: mailbox to use for the FW command
6560 * @pf: the PF owning the VI
6561 * @vf: the VF owning the VI
6562 * @viid: virtual interface identifiler
6564 * Free a previously allocated virtual interface.
6566 int t4_free_vi(struct adapter *adap, unsigned int mbox, unsigned int pf,
6567 unsigned int vf, unsigned int viid)
6571 memset(&c, 0, sizeof(c));
6572 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_VI_CMD) |
6575 FW_VI_CMD_PFN_V(pf) |
6576 FW_VI_CMD_VFN_V(vf));
6577 c.alloc_to_len16 = cpu_to_be32(FW_VI_CMD_FREE_F | FW_LEN16(c));
6578 c.type_viid = cpu_to_be16(FW_VI_CMD_VIID_V(viid));
6580 return t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
6584 * t4_set_rxmode - set Rx properties of a virtual interface
6585 * @adap: the adapter
6586 * @mbox: mailbox to use for the FW command
6588 * @mtu: the new MTU or -1
6589 * @promisc: 1 to enable promiscuous mode, 0 to disable it, -1 no change
6590 * @all_multi: 1 to enable all-multi mode, 0 to disable it, -1 no change
6591 * @bcast: 1 to enable broadcast Rx, 0 to disable it, -1 no change
6592 * @vlanex: 1 to enable HW VLAN extraction, 0 to disable it, -1 no change
6593 * @sleep_ok: if true we may sleep while awaiting command completion
6595 * Sets Rx properties of a virtual interface.
6597 int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid,
6598 int mtu, int promisc, int all_multi, int bcast, int vlanex,
6601 struct fw_vi_rxmode_cmd c;
6603 /* convert to FW values */
6605 mtu = FW_RXMODE_MTU_NO_CHG;
6607 promisc = FW_VI_RXMODE_CMD_PROMISCEN_M;
6609 all_multi = FW_VI_RXMODE_CMD_ALLMULTIEN_M;
6611 bcast = FW_VI_RXMODE_CMD_BROADCASTEN_M;
6613 vlanex = FW_VI_RXMODE_CMD_VLANEXEN_M;
6615 memset(&c, 0, sizeof(c));
6616 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_RXMODE_CMD) |
6617 FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
6618 FW_VI_RXMODE_CMD_VIID_V(viid));
6619 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
6621 cpu_to_be32(FW_VI_RXMODE_CMD_MTU_V(mtu) |
6622 FW_VI_RXMODE_CMD_PROMISCEN_V(promisc) |
6623 FW_VI_RXMODE_CMD_ALLMULTIEN_V(all_multi) |
6624 FW_VI_RXMODE_CMD_BROADCASTEN_V(bcast) |
6625 FW_VI_RXMODE_CMD_VLANEXEN_V(vlanex));
6626 return t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), NULL, sleep_ok);
6630 * t4_alloc_mac_filt - allocates exact-match filters for MAC addresses
6631 * @adap: the adapter
6632 * @mbox: mailbox to use for the FW command
6634 * @free: if true any existing filters for this VI id are first removed
6635 * @naddr: the number of MAC addresses to allocate filters for (up to 7)
6636 * @addr: the MAC address(es)
6637 * @idx: where to store the index of each allocated filter
6638 * @hash: pointer to hash address filter bitmap
6639 * @sleep_ok: call is allowed to sleep
6641 * Allocates an exact-match filter for each of the supplied addresses and
6642 * sets it to the corresponding address. If @idx is not %NULL it should
6643 * have at least @naddr entries, each of which will be set to the index of
6644 * the filter allocated for the corresponding MAC address. If a filter
6645 * could not be allocated for an address its index is set to 0xffff.
6646 * If @hash is not %NULL addresses that fail to allocate an exact filter
6647 * are hashed and update the hash filter bitmap pointed at by @hash.
6649 * Returns a negative error number or the number of filters allocated.
6651 int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox,
6652 unsigned int viid, bool free, unsigned int naddr,
6653 const u8 **addr, u16 *idx, u64 *hash, bool sleep_ok)
6655 int offset, ret = 0;
6656 struct fw_vi_mac_cmd c;
6657 unsigned int nfilters = 0;
6658 unsigned int max_naddr = adap->params.arch.mps_tcam_size;
6659 unsigned int rem = naddr;
6661 if (naddr > max_naddr)
6664 for (offset = 0; offset < naddr ; /**/) {
6665 unsigned int fw_naddr = (rem < ARRAY_SIZE(c.u.exact) ?
6666 rem : ARRAY_SIZE(c.u.exact));
6667 size_t len16 = DIV_ROUND_UP(offsetof(struct fw_vi_mac_cmd,
6668 u.exact[fw_naddr]), 16);
6669 struct fw_vi_mac_exact *p;
6672 memset(&c, 0, sizeof(c));
6673 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD) |
6676 FW_CMD_EXEC_V(free) |
6677 FW_VI_MAC_CMD_VIID_V(viid));
6678 c.freemacs_to_len16 =
6679 cpu_to_be32(FW_VI_MAC_CMD_FREEMACS_V(free) |
6680 FW_CMD_LEN16_V(len16));
6682 for (i = 0, p = c.u.exact; i < fw_naddr; i++, p++) {
6684 cpu_to_be16(FW_VI_MAC_CMD_VALID_F |
6685 FW_VI_MAC_CMD_IDX_V(
6686 FW_VI_MAC_ADD_MAC));
6687 memcpy(p->macaddr, addr[offset + i],
6688 sizeof(p->macaddr));
6691 /* It's okay if we run out of space in our MAC address arena.
6692 * Some of the addresses we submit may get stored so we need
6693 * to run through the reply to see what the results were ...
6695 ret = t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), &c, sleep_ok);
6696 if (ret && ret != -FW_ENOMEM)
6699 for (i = 0, p = c.u.exact; i < fw_naddr; i++, p++) {
6700 u16 index = FW_VI_MAC_CMD_IDX_G(
6701 be16_to_cpu(p->valid_to_idx));
6704 idx[offset + i] = (index >= max_naddr ?
6706 if (index < max_naddr)
6710 hash_mac_addr(addr[offset + i]));
6718 if (ret == 0 || ret == -FW_ENOMEM)
6724 * t4_free_mac_filt - frees exact-match filters of given MAC addresses
6725 * @adap: the adapter
6726 * @mbox: mailbox to use for the FW command
6728 * @naddr: the number of MAC addresses to allocate filters for (up to 7)
6729 * @addr: the MAC address(es)
6730 * @sleep_ok: call is allowed to sleep
6732 * Frees the exact-match filter for each of the supplied addresses
6734 * Returns a negative error number or the number of filters freed.
6736 int t4_free_mac_filt(struct adapter *adap, unsigned int mbox,
6737 unsigned int viid, unsigned int naddr,
6738 const u8 **addr, bool sleep_ok)
6740 int offset, ret = 0;
6741 struct fw_vi_mac_cmd c;
6742 unsigned int nfilters = 0;
6743 unsigned int max_naddr = is_t4(adap->params.chip) ?
6744 NUM_MPS_CLS_SRAM_L_INSTANCES :
6745 NUM_MPS_T5_CLS_SRAM_L_INSTANCES;
6746 unsigned int rem = naddr;
6748 if (naddr > max_naddr)
6751 for (offset = 0; offset < (int)naddr ; /**/) {
6752 unsigned int fw_naddr = (rem < ARRAY_SIZE(c.u.exact)
6754 : ARRAY_SIZE(c.u.exact));
6755 size_t len16 = DIV_ROUND_UP(offsetof(struct fw_vi_mac_cmd,
6756 u.exact[fw_naddr]), 16);
6757 struct fw_vi_mac_exact *p;
6760 memset(&c, 0, sizeof(c));
6761 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD) |
6765 FW_VI_MAC_CMD_VIID_V(viid));
6766 c.freemacs_to_len16 =
6767 cpu_to_be32(FW_VI_MAC_CMD_FREEMACS_V(0) |
6768 FW_CMD_LEN16_V(len16));
6770 for (i = 0, p = c.u.exact; i < (int)fw_naddr; i++, p++) {
6771 p->valid_to_idx = cpu_to_be16(
6772 FW_VI_MAC_CMD_VALID_F |
6773 FW_VI_MAC_CMD_IDX_V(FW_VI_MAC_MAC_BASED_FREE));
6774 memcpy(p->macaddr, addr[offset+i], sizeof(p->macaddr));
6777 ret = t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), &c, sleep_ok);
6781 for (i = 0, p = c.u.exact; i < fw_naddr; i++, p++) {
6782 u16 index = FW_VI_MAC_CMD_IDX_G(
6783 be16_to_cpu(p->valid_to_idx));
6785 if (index < max_naddr)
6799 * t4_change_mac - modifies the exact-match filter for a MAC address
6800 * @adap: the adapter
6801 * @mbox: mailbox to use for the FW command
6803 * @idx: index of existing filter for old value of MAC address, or -1
6804 * @addr: the new MAC address value
6805 * @persist: whether a new MAC allocation should be persistent
6806 * @add_smt: if true also add the address to the HW SMT
6808 * Modifies an exact-match filter and sets it to the new MAC address.
6809 * Note that in general it is not possible to modify the value of a given
6810 * filter so the generic way to modify an address filter is to free the one
6811 * being used by the old address value and allocate a new filter for the
6812 * new address value. @idx can be -1 if the address is a new addition.
6814 * Returns a negative error number or the index of the filter with the new
6817 int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid,
6818 int idx, const u8 *addr, bool persist, bool add_smt)
6821 struct fw_vi_mac_cmd c;
6822 struct fw_vi_mac_exact *p = c.u.exact;
6823 unsigned int max_mac_addr = adap->params.arch.mps_tcam_size;
6825 if (idx < 0) /* new allocation */
6826 idx = persist ? FW_VI_MAC_ADD_PERSIST_MAC : FW_VI_MAC_ADD_MAC;
6827 mode = add_smt ? FW_VI_MAC_SMT_AND_MPSTCAM : FW_VI_MAC_MPS_TCAM_ENTRY;
6829 memset(&c, 0, sizeof(c));
6830 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD) |
6831 FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
6832 FW_VI_MAC_CMD_VIID_V(viid));
6833 c.freemacs_to_len16 = cpu_to_be32(FW_CMD_LEN16_V(1));
6834 p->valid_to_idx = cpu_to_be16(FW_VI_MAC_CMD_VALID_F |
6835 FW_VI_MAC_CMD_SMAC_RESULT_V(mode) |
6836 FW_VI_MAC_CMD_IDX_V(idx));
6837 memcpy(p->macaddr, addr, sizeof(p->macaddr));
6839 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
6841 ret = FW_VI_MAC_CMD_IDX_G(be16_to_cpu(p->valid_to_idx));
6842 if (ret >= max_mac_addr)
6849 * t4_set_addr_hash - program the MAC inexact-match hash filter
6850 * @adap: the adapter
6851 * @mbox: mailbox to use for the FW command
6853 * @ucast: whether the hash filter should also match unicast addresses
6854 * @vec: the value to be written to the hash filter
6855 * @sleep_ok: call is allowed to sleep
6857 * Sets the 64-bit inexact-match hash filter for a virtual interface.
6859 int t4_set_addr_hash(struct adapter *adap, unsigned int mbox, unsigned int viid,
6860 bool ucast, u64 vec, bool sleep_ok)
6862 struct fw_vi_mac_cmd c;
6864 memset(&c, 0, sizeof(c));
6865 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD) |
6866 FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
6867 FW_VI_ENABLE_CMD_VIID_V(viid));
6868 c.freemacs_to_len16 = cpu_to_be32(FW_VI_MAC_CMD_HASHVECEN_F |
6869 FW_VI_MAC_CMD_HASHUNIEN_V(ucast) |
6871 c.u.hash.hashvec = cpu_to_be64(vec);
6872 return t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), NULL, sleep_ok);
6876 * t4_enable_vi_params - enable/disable a virtual interface
6877 * @adap: the adapter
6878 * @mbox: mailbox to use for the FW command
6880 * @rx_en: 1=enable Rx, 0=disable Rx
6881 * @tx_en: 1=enable Tx, 0=disable Tx
6882 * @dcb_en: 1=enable delivery of Data Center Bridging messages.
6884 * Enables/disables a virtual interface. Note that setting DCB Enable
6885 * only makes sense when enabling a Virtual Interface ...
6887 int t4_enable_vi_params(struct adapter *adap, unsigned int mbox,
6888 unsigned int viid, bool rx_en, bool tx_en, bool dcb_en)
6890 struct fw_vi_enable_cmd c;
6892 memset(&c, 0, sizeof(c));
6893 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_ENABLE_CMD) |
6894 FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
6895 FW_VI_ENABLE_CMD_VIID_V(viid));
6896 c.ien_to_len16 = cpu_to_be32(FW_VI_ENABLE_CMD_IEN_V(rx_en) |
6897 FW_VI_ENABLE_CMD_EEN_V(tx_en) |
6898 FW_VI_ENABLE_CMD_DCB_INFO_V(dcb_en) |
6900 return t4_wr_mbox_ns(adap, mbox, &c, sizeof(c), NULL);
6904 * t4_enable_vi - enable/disable a virtual interface
6905 * @adap: the adapter
6906 * @mbox: mailbox to use for the FW command
6908 * @rx_en: 1=enable Rx, 0=disable Rx
6909 * @tx_en: 1=enable Tx, 0=disable Tx
6911 * Enables/disables a virtual interface.
6913 int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid,
6914 bool rx_en, bool tx_en)
6916 return t4_enable_vi_params(adap, mbox, viid, rx_en, tx_en, 0);
6920 * t4_identify_port - identify a VI's port by blinking its LED
6921 * @adap: the adapter
6922 * @mbox: mailbox to use for the FW command
6924 * @nblinks: how many times to blink LED at 2.5 Hz
6926 * Identifies a VI's port by blinking its LED.
6928 int t4_identify_port(struct adapter *adap, unsigned int mbox, unsigned int viid,
6929 unsigned int nblinks)
6931 struct fw_vi_enable_cmd c;
6933 memset(&c, 0, sizeof(c));
6934 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_ENABLE_CMD) |
6935 FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
6936 FW_VI_ENABLE_CMD_VIID_V(viid));
6937 c.ien_to_len16 = cpu_to_be32(FW_VI_ENABLE_CMD_LED_F | FW_LEN16(c));
6938 c.blinkdur = cpu_to_be16(nblinks);
6939 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
6943 * t4_iq_free - free an ingress queue and its FLs
6944 * @adap: the adapter
6945 * @mbox: mailbox to use for the FW command
6946 * @pf: the PF owning the queues
6947 * @vf: the VF owning the queues
6948 * @iqtype: the ingress queue type
6949 * @iqid: ingress queue id
6950 * @fl0id: FL0 queue id or 0xffff if no attached FL0
6951 * @fl1id: FL1 queue id or 0xffff if no attached FL1
6953 * Frees an ingress queue and its associated FLs, if any.
6955 int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
6956 unsigned int vf, unsigned int iqtype, unsigned int iqid,
6957 unsigned int fl0id, unsigned int fl1id)
6961 memset(&c, 0, sizeof(c));
6962 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_IQ_CMD) | FW_CMD_REQUEST_F |
6963 FW_CMD_EXEC_F | FW_IQ_CMD_PFN_V(pf) |
6964 FW_IQ_CMD_VFN_V(vf));
6965 c.alloc_to_len16 = cpu_to_be32(FW_IQ_CMD_FREE_F | FW_LEN16(c));
6966 c.type_to_iqandstindex = cpu_to_be32(FW_IQ_CMD_TYPE_V(iqtype));
6967 c.iqid = cpu_to_be16(iqid);
6968 c.fl0id = cpu_to_be16(fl0id);
6969 c.fl1id = cpu_to_be16(fl1id);
6970 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
6974 * t4_eth_eq_free - free an Ethernet egress queue
6975 * @adap: the adapter
6976 * @mbox: mailbox to use for the FW command
6977 * @pf: the PF owning the queue
6978 * @vf: the VF owning the queue
6979 * @eqid: egress queue id
6981 * Frees an Ethernet egress queue.
6983 int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
6984 unsigned int vf, unsigned int eqid)
6986 struct fw_eq_eth_cmd c;
6988 memset(&c, 0, sizeof(c));
6989 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_EQ_ETH_CMD) |
6990 FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
6991 FW_EQ_ETH_CMD_PFN_V(pf) |
6992 FW_EQ_ETH_CMD_VFN_V(vf));
6993 c.alloc_to_len16 = cpu_to_be32(FW_EQ_ETH_CMD_FREE_F | FW_LEN16(c));
6994 c.eqid_pkd = cpu_to_be32(FW_EQ_ETH_CMD_EQID_V(eqid));
6995 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
6999 * t4_ctrl_eq_free - free a control egress queue
7000 * @adap: the adapter
7001 * @mbox: mailbox to use for the FW command
7002 * @pf: the PF owning the queue
7003 * @vf: the VF owning the queue
7004 * @eqid: egress queue id
7006 * Frees a control egress queue.
7008 int t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
7009 unsigned int vf, unsigned int eqid)
7011 struct fw_eq_ctrl_cmd c;
7013 memset(&c, 0, sizeof(c));
7014 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_EQ_CTRL_CMD) |
7015 FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
7016 FW_EQ_CTRL_CMD_PFN_V(pf) |
7017 FW_EQ_CTRL_CMD_VFN_V(vf));
7018 c.alloc_to_len16 = cpu_to_be32(FW_EQ_CTRL_CMD_FREE_F | FW_LEN16(c));
7019 c.cmpliqid_eqid = cpu_to_be32(FW_EQ_CTRL_CMD_EQID_V(eqid));
7020 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7024 * t4_ofld_eq_free - free an offload egress queue
7025 * @adap: the adapter
7026 * @mbox: mailbox to use for the FW command
7027 * @pf: the PF owning the queue
7028 * @vf: the VF owning the queue
7029 * @eqid: egress queue id
7031 * Frees a control egress queue.
7033 int t4_ofld_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
7034 unsigned int vf, unsigned int eqid)
7036 struct fw_eq_ofld_cmd c;
7038 memset(&c, 0, sizeof(c));
7039 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_EQ_OFLD_CMD) |
7040 FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
7041 FW_EQ_OFLD_CMD_PFN_V(pf) |
7042 FW_EQ_OFLD_CMD_VFN_V(vf));
7043 c.alloc_to_len16 = cpu_to_be32(FW_EQ_OFLD_CMD_FREE_F | FW_LEN16(c));
7044 c.eqid_pkd = cpu_to_be32(FW_EQ_OFLD_CMD_EQID_V(eqid));
7045 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7049 * t4_handle_fw_rpl - process a FW reply message
7050 * @adap: the adapter
7051 * @rpl: start of the FW message
7053 * Processes a FW message, such as link state change messages.
7055 int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl)
7057 u8 opcode = *(const u8 *)rpl;
7059 if (opcode == FW_PORT_CMD) { /* link/module state change message */
7060 int speed = 0, fc = 0;
7061 const struct fw_port_cmd *p = (void *)rpl;
7062 int chan = FW_PORT_CMD_PORTID_G(be32_to_cpu(p->op_to_portid));
7063 int port = adap->chan_map[chan];
7064 struct port_info *pi = adap2pinfo(adap, port);
7065 struct link_config *lc = &pi->link_cfg;
7066 u32 stat = be32_to_cpu(p->u.info.lstatus_to_modtype);
7067 int link_ok = (stat & FW_PORT_CMD_LSTATUS_F) != 0;
7068 u32 mod = FW_PORT_CMD_MODTYPE_G(stat);
7070 if (stat & FW_PORT_CMD_RXPAUSE_F)
7072 if (stat & FW_PORT_CMD_TXPAUSE_F)
7074 if (stat & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_100M))
7076 else if (stat & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_1G))
7078 else if (stat & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_10G))
7080 else if (stat & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_40G))
7083 if (link_ok != lc->link_ok || speed != lc->speed ||
7084 fc != lc->fc) { /* something changed */
7085 lc->link_ok = link_ok;
7088 lc->supported = be16_to_cpu(p->u.info.pcap);
7089 t4_os_link_changed(adap, port, link_ok);
7091 if (mod != pi->mod_type) {
7093 t4_os_portmod_changed(adap, port);
7099 static void get_pci_mode(struct adapter *adapter, struct pci_params *p)
7103 if (pci_is_pcie(adapter->pdev)) {
7104 pcie_capability_read_word(adapter->pdev, PCI_EXP_LNKSTA, &val);
7105 p->speed = val & PCI_EXP_LNKSTA_CLS;
7106 p->width = (val & PCI_EXP_LNKSTA_NLW) >> 4;
7111 * init_link_config - initialize a link's SW state
7112 * @lc: structure holding the link state
7113 * @caps: link capabilities
7115 * Initializes the SW state maintained for each link, including the link's
7116 * capabilities and default speed/flow-control/autonegotiation settings.
7118 static void init_link_config(struct link_config *lc, unsigned int caps)
7120 lc->supported = caps;
7121 lc->requested_speed = 0;
7123 lc->requested_fc = lc->fc = PAUSE_RX | PAUSE_TX;
7124 if (lc->supported & FW_PORT_CAP_ANEG) {
7125 lc->advertising = lc->supported & ADVERT_MASK;
7126 lc->autoneg = AUTONEG_ENABLE;
7127 lc->requested_fc |= PAUSE_AUTONEG;
7129 lc->advertising = 0;
7130 lc->autoneg = AUTONEG_DISABLE;
7134 #define CIM_PF_NOACCESS 0xeeeeeeee
7136 int t4_wait_dev_ready(void __iomem *regs)
7140 whoami = readl(regs + PL_WHOAMI_A);
7141 if (whoami != 0xffffffff && whoami != CIM_PF_NOACCESS)
7145 whoami = readl(regs + PL_WHOAMI_A);
7146 return (whoami != 0xffffffff && whoami != CIM_PF_NOACCESS ? 0 : -EIO);
7150 u32 vendor_and_model_id;
7154 static int get_flash_params(struct adapter *adap)
7156 /* Table for non-Numonix supported flash parts. Numonix parts are left
7157 * to the preexisting code. All flash parts have 64KB sectors.
7159 static struct flash_desc supported_flash[] = {
7160 { 0x150201, 4 << 20 }, /* Spansion 4MB S25FL032P */
7166 ret = sf1_write(adap, 1, 1, 0, SF_RD_ID);
7168 ret = sf1_read(adap, 3, 0, 1, &info);
7169 t4_write_reg(adap, SF_OP_A, 0); /* unlock SF */
7173 for (ret = 0; ret < ARRAY_SIZE(supported_flash); ++ret)
7174 if (supported_flash[ret].vendor_and_model_id == info) {
7175 adap->params.sf_size = supported_flash[ret].size_mb;
7176 adap->params.sf_nsec =
7177 adap->params.sf_size / SF_SEC_SIZE;
7181 if ((info & 0xff) != 0x20) /* not a Numonix flash */
7183 info >>= 16; /* log2 of size */
7184 if (info >= 0x14 && info < 0x18)
7185 adap->params.sf_nsec = 1 << (info - 16);
7186 else if (info == 0x18)
7187 adap->params.sf_nsec = 64;
7190 adap->params.sf_size = 1 << info;
7191 adap->params.sf_fw_start =
7192 t4_read_reg(adap, CIM_BOOT_CFG_A) & BOOTADDR_M;
7194 if (adap->params.sf_size < FLASH_MIN_SIZE)
7195 dev_warn(adap->pdev_dev, "WARNING!!! FLASH size %#x < %#x!!!\n",
7196 adap->params.sf_size, FLASH_MIN_SIZE);
7200 static void set_pcie_completion_timeout(struct adapter *adapter, u8 range)
7205 pcie_cap = pci_find_capability(adapter->pdev, PCI_CAP_ID_EXP);
7207 pci_read_config_word(adapter->pdev,
7208 pcie_cap + PCI_EXP_DEVCTL2, &val);
7209 val &= ~PCI_EXP_DEVCTL2_COMP_TIMEOUT;
7211 pci_write_config_word(adapter->pdev,
7212 pcie_cap + PCI_EXP_DEVCTL2, val);
7217 * t4_prep_adapter - prepare SW and HW for operation
7218 * @adapter: the adapter
7219 * @reset: if true perform a HW reset
7221 * Initialize adapter SW state for the various HW modules, set initial
7222 * values for some adapter tunables, take PHYs out of reset, and
7223 * initialize the MDIO interface.
7225 int t4_prep_adapter(struct adapter *adapter)
7231 get_pci_mode(adapter, &adapter->params.pci);
7232 pl_rev = REV_G(t4_read_reg(adapter, PL_REV_A));
7234 ret = get_flash_params(adapter);
7236 dev_err(adapter->pdev_dev, "error %d identifying flash\n", ret);
7240 /* Retrieve adapter's device ID
7242 pci_read_config_word(adapter->pdev, PCI_DEVICE_ID, &device_id);
7243 ver = device_id >> 12;
7244 adapter->params.chip = 0;
7247 adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T4, pl_rev);
7248 adapter->params.arch.sge_fl_db = DBPRIO_F;
7249 adapter->params.arch.mps_tcam_size =
7250 NUM_MPS_CLS_SRAM_L_INSTANCES;
7251 adapter->params.arch.mps_rplc_size = 128;
7252 adapter->params.arch.nchan = NCHAN;
7253 adapter->params.arch.pm_stats_cnt = PM_NSTATS;
7254 adapter->params.arch.vfcount = 128;
7255 /* Congestion map is for 4 channels so that
7256 * MPS can have 4 priority per port.
7258 adapter->params.arch.cng_ch_bits_log = 2;
7261 adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T5, pl_rev);
7262 adapter->params.arch.sge_fl_db = DBPRIO_F | DBTYPE_F;
7263 adapter->params.arch.mps_tcam_size =
7264 NUM_MPS_T5_CLS_SRAM_L_INSTANCES;
7265 adapter->params.arch.mps_rplc_size = 128;
7266 adapter->params.arch.nchan = NCHAN;
7267 adapter->params.arch.pm_stats_cnt = PM_NSTATS;
7268 adapter->params.arch.vfcount = 128;
7269 adapter->params.arch.cng_ch_bits_log = 2;
7272 adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T6, pl_rev);
7273 adapter->params.arch.sge_fl_db = 0;
7274 adapter->params.arch.mps_tcam_size =
7275 NUM_MPS_T5_CLS_SRAM_L_INSTANCES;
7276 adapter->params.arch.mps_rplc_size = 256;
7277 adapter->params.arch.nchan = 2;
7278 adapter->params.arch.pm_stats_cnt = T6_PM_NSTATS;
7279 adapter->params.arch.vfcount = 256;
7280 /* Congestion map will be for 2 channels so that
7281 * MPS can have 8 priority per port.
7283 adapter->params.arch.cng_ch_bits_log = 3;
7286 dev_err(adapter->pdev_dev, "Device %d is not supported\n",
7291 adapter->params.cim_la_size = CIMLA_SIZE;
7292 init_cong_ctrl(adapter->params.a_wnd, adapter->params.b_wnd);
7295 * Default port for debugging in case we can't reach FW.
7297 adapter->params.nports = 1;
7298 adapter->params.portvec = 1;
7299 adapter->params.vpd.cclk = 50000;
7301 /* Set pci completion timeout value to 4 seconds. */
7302 set_pcie_completion_timeout(adapter, 0xd);
7307 * t4_bar2_sge_qregs - return BAR2 SGE Queue register information
7308 * @adapter: the adapter
7309 * @qid: the Queue ID
7310 * @qtype: the Ingress or Egress type for @qid
7311 * @user: true if this request is for a user mode queue
7312 * @pbar2_qoffset: BAR2 Queue Offset
7313 * @pbar2_qid: BAR2 Queue ID or 0 for Queue ID inferred SGE Queues
7315 * Returns the BAR2 SGE Queue Registers information associated with the
7316 * indicated Absolute Queue ID. These are passed back in return value
7317 * pointers. @qtype should be T4_BAR2_QTYPE_EGRESS for Egress Queue
7318 * and T4_BAR2_QTYPE_INGRESS for Ingress Queues.
7320 * This may return an error which indicates that BAR2 SGE Queue
7321 * registers aren't available. If an error is not returned, then the
7322 * following values are returned:
7324 * *@pbar2_qoffset: the BAR2 Offset of the @qid Registers
7325 * *@pbar2_qid: the BAR2 SGE Queue ID or 0 of @qid
7327 * If the returned BAR2 Queue ID is 0, then BAR2 SGE registers which
7328 * require the "Inferred Queue ID" ability may be used. E.g. the
7329 * Write Combining Doorbell Buffer. If the BAR2 Queue ID is not 0,
7330 * then these "Inferred Queue ID" register may not be used.
7332 int t4_bar2_sge_qregs(struct adapter *adapter,
7334 enum t4_bar2_qtype qtype,
7337 unsigned int *pbar2_qid)
7339 unsigned int page_shift, page_size, qpp_shift, qpp_mask;
7340 u64 bar2_page_offset, bar2_qoffset;
7341 unsigned int bar2_qid, bar2_qid_offset, bar2_qinferred;
7343 /* T4 doesn't support BAR2 SGE Queue registers for kernel mode queues */
7344 if (!user && is_t4(adapter->params.chip))
7347 /* Get our SGE Page Size parameters.
7349 page_shift = adapter->params.sge.hps + 10;
7350 page_size = 1 << page_shift;
7352 /* Get the right Queues per Page parameters for our Queue.
7354 qpp_shift = (qtype == T4_BAR2_QTYPE_EGRESS
7355 ? adapter->params.sge.eq_qpp
7356 : adapter->params.sge.iq_qpp);
7357 qpp_mask = (1 << qpp_shift) - 1;
7359 /* Calculate the basics of the BAR2 SGE Queue register area:
7360 * o The BAR2 page the Queue registers will be in.
7361 * o The BAR2 Queue ID.
7362 * o The BAR2 Queue ID Offset into the BAR2 page.
7364 bar2_page_offset = ((u64)(qid >> qpp_shift) << page_shift);
7365 bar2_qid = qid & qpp_mask;
7366 bar2_qid_offset = bar2_qid * SGE_UDB_SIZE;
7368 /* If the BAR2 Queue ID Offset is less than the Page Size, then the
7369 * hardware will infer the Absolute Queue ID simply from the writes to
7370 * the BAR2 Queue ID Offset within the BAR2 Page (and we need to use a
7371 * BAR2 Queue ID of 0 for those writes). Otherwise, we'll simply
7372 * write to the first BAR2 SGE Queue Area within the BAR2 Page with
7373 * the BAR2 Queue ID and the hardware will infer the Absolute Queue ID
7374 * from the BAR2 Page and BAR2 Queue ID.
7376 * One important censequence of this is that some BAR2 SGE registers
7377 * have a "Queue ID" field and we can write the BAR2 SGE Queue ID
7378 * there. But other registers synthesize the SGE Queue ID purely
7379 * from the writes to the registers -- the Write Combined Doorbell
7380 * Buffer is a good example. These BAR2 SGE Registers are only
7381 * available for those BAR2 SGE Register areas where the SGE Absolute
7382 * Queue ID can be inferred from simple writes.
7384 bar2_qoffset = bar2_page_offset;
7385 bar2_qinferred = (bar2_qid_offset < page_size);
7386 if (bar2_qinferred) {
7387 bar2_qoffset += bar2_qid_offset;
7391 *pbar2_qoffset = bar2_qoffset;
7392 *pbar2_qid = bar2_qid;
7397 * t4_init_devlog_params - initialize adapter->params.devlog
7398 * @adap: the adapter
7400 * Initialize various fields of the adapter's Firmware Device Log
7401 * Parameters structure.
7403 int t4_init_devlog_params(struct adapter *adap)
7405 struct devlog_params *dparams = &adap->params.devlog;
7407 unsigned int devlog_meminfo;
7408 struct fw_devlog_cmd devlog_cmd;
7411 /* If we're dealing with newer firmware, the Device Log Paramerters
7412 * are stored in a designated register which allows us to access the
7413 * Device Log even if we can't talk to the firmware.
7416 t4_read_reg(adap, PCIE_FW_REG(PCIE_FW_PF_A, PCIE_FW_PF_DEVLOG));
7418 unsigned int nentries, nentries128;
7420 dparams->memtype = PCIE_FW_PF_DEVLOG_MEMTYPE_G(pf_dparams);
7421 dparams->start = PCIE_FW_PF_DEVLOG_ADDR16_G(pf_dparams) << 4;
7423 nentries128 = PCIE_FW_PF_DEVLOG_NENTRIES128_G(pf_dparams);
7424 nentries = (nentries128 + 1) * 128;
7425 dparams->size = nentries * sizeof(struct fw_devlog_e);
7430 /* Otherwise, ask the firmware for it's Device Log Parameters.
7432 memset(&devlog_cmd, 0, sizeof(devlog_cmd));
7433 devlog_cmd.op_to_write = cpu_to_be32(FW_CMD_OP_V(FW_DEVLOG_CMD) |
7434 FW_CMD_REQUEST_F | FW_CMD_READ_F);
7435 devlog_cmd.retval_len16 = cpu_to_be32(FW_LEN16(devlog_cmd));
7436 ret = t4_wr_mbox(adap, adap->mbox, &devlog_cmd, sizeof(devlog_cmd),
7442 be32_to_cpu(devlog_cmd.memtype_devlog_memaddr16_devlog);
7443 dparams->memtype = FW_DEVLOG_CMD_MEMTYPE_DEVLOG_G(devlog_meminfo);
7444 dparams->start = FW_DEVLOG_CMD_MEMADDR16_DEVLOG_G(devlog_meminfo) << 4;
7445 dparams->size = be32_to_cpu(devlog_cmd.memsize_devlog);
7451 * t4_init_sge_params - initialize adap->params.sge
7452 * @adapter: the adapter
7454 * Initialize various fields of the adapter's SGE Parameters structure.
7456 int t4_init_sge_params(struct adapter *adapter)
7458 struct sge_params *sge_params = &adapter->params.sge;
7460 unsigned int s_hps, s_qpp;
7462 /* Extract the SGE Page Size for our PF.
7464 hps = t4_read_reg(adapter, SGE_HOST_PAGE_SIZE_A);
7465 s_hps = (HOSTPAGESIZEPF0_S +
7466 (HOSTPAGESIZEPF1_S - HOSTPAGESIZEPF0_S) * adapter->pf);
7467 sge_params->hps = ((hps >> s_hps) & HOSTPAGESIZEPF0_M);
7469 /* Extract the SGE Egress and Ingess Queues Per Page for our PF.
7471 s_qpp = (QUEUESPERPAGEPF0_S +
7472 (QUEUESPERPAGEPF1_S - QUEUESPERPAGEPF0_S) * adapter->pf);
7473 qpp = t4_read_reg(adapter, SGE_EGRESS_QUEUES_PER_PAGE_PF_A);
7474 sge_params->eq_qpp = ((qpp >> s_qpp) & QUEUESPERPAGEPF0_M);
7475 qpp = t4_read_reg(adapter, SGE_INGRESS_QUEUES_PER_PAGE_PF_A);
7476 sge_params->iq_qpp = ((qpp >> s_qpp) & QUEUESPERPAGEPF0_M);
7482 * t4_init_tp_params - initialize adap->params.tp
7483 * @adap: the adapter
7485 * Initialize various fields of the adapter's TP Parameters structure.
7487 int t4_init_tp_params(struct adapter *adap)
7492 v = t4_read_reg(adap, TP_TIMER_RESOLUTION_A);
7493 adap->params.tp.tre = TIMERRESOLUTION_G(v);
7494 adap->params.tp.dack_re = DELAYEDACKRESOLUTION_G(v);
7496 /* MODQ_REQ_MAP defaults to setting queues 0-3 to chan 0-3 */
7497 for (chan = 0; chan < NCHAN; chan++)
7498 adap->params.tp.tx_modq[chan] = chan;
7500 /* Cache the adapter's Compressed Filter Mode and global Incress
7503 if (t4_use_ldst(adap)) {
7504 t4_fw_tp_pio_rw(adap, &adap->params.tp.vlan_pri_map, 1,
7505 TP_VLAN_PRI_MAP_A, 1);
7506 t4_fw_tp_pio_rw(adap, &adap->params.tp.ingress_config, 1,
7507 TP_INGRESS_CONFIG_A, 1);
7509 t4_read_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A,
7510 &adap->params.tp.vlan_pri_map, 1,
7512 t4_read_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A,
7513 &adap->params.tp.ingress_config, 1,
7514 TP_INGRESS_CONFIG_A);
7517 /* Now that we have TP_VLAN_PRI_MAP cached, we can calculate the field
7518 * shift positions of several elements of the Compressed Filter Tuple
7519 * for this adapter which we need frequently ...
7521 adap->params.tp.vlan_shift = t4_filter_field_shift(adap, VLAN_F);
7522 adap->params.tp.vnic_shift = t4_filter_field_shift(adap, VNIC_ID_F);
7523 adap->params.tp.port_shift = t4_filter_field_shift(adap, PORT_F);
7524 adap->params.tp.protocol_shift = t4_filter_field_shift(adap,
7527 /* If TP_INGRESS_CONFIG.VNID == 0, then TP_VLAN_PRI_MAP.VNIC_ID
7528 * represents the presence of an Outer VLAN instead of a VNIC ID.
7530 if ((adap->params.tp.ingress_config & VNIC_F) == 0)
7531 adap->params.tp.vnic_shift = -1;
7537 * t4_filter_field_shift - calculate filter field shift
7538 * @adap: the adapter
7539 * @filter_sel: the desired field (from TP_VLAN_PRI_MAP bits)
7541 * Return the shift position of a filter field within the Compressed
7542 * Filter Tuple. The filter field is specified via its selection bit
7543 * within TP_VLAN_PRI_MAL (filter mode). E.g. F_VLAN.
7545 int t4_filter_field_shift(const struct adapter *adap, int filter_sel)
7547 unsigned int filter_mode = adap->params.tp.vlan_pri_map;
7551 if ((filter_mode & filter_sel) == 0)
7554 for (sel = 1, field_shift = 0; sel < filter_sel; sel <<= 1) {
7555 switch (filter_mode & sel) {
7557 field_shift += FT_FCOE_W;
7560 field_shift += FT_PORT_W;
7563 field_shift += FT_VNIC_ID_W;
7566 field_shift += FT_VLAN_W;
7569 field_shift += FT_TOS_W;
7572 field_shift += FT_PROTOCOL_W;
7575 field_shift += FT_ETHERTYPE_W;
7578 field_shift += FT_MACMATCH_W;
7581 field_shift += FT_MPSHITTYPE_W;
7583 case FRAGMENTATION_F:
7584 field_shift += FT_FRAGMENTATION_W;
7591 int t4_init_rss_mode(struct adapter *adap, int mbox)
7594 struct fw_rss_vi_config_cmd rvc;
7596 memset(&rvc, 0, sizeof(rvc));
7598 for_each_port(adap, i) {
7599 struct port_info *p = adap2pinfo(adap, i);
7602 cpu_to_be32(FW_CMD_OP_V(FW_RSS_VI_CONFIG_CMD) |
7603 FW_CMD_REQUEST_F | FW_CMD_READ_F |
7604 FW_RSS_VI_CONFIG_CMD_VIID_V(p->viid));
7605 rvc.retval_len16 = cpu_to_be32(FW_LEN16(rvc));
7606 ret = t4_wr_mbox(adap, mbox, &rvc, sizeof(rvc), &rvc);
7609 p->rss_mode = be32_to_cpu(rvc.u.basicvirtual.defaultq_to_udpen);
7614 int t4_port_init(struct adapter *adap, int mbox, int pf, int vf)
7618 struct fw_port_cmd c;
7619 struct fw_rss_vi_config_cmd rvc;
7621 memset(&c, 0, sizeof(c));
7622 memset(&rvc, 0, sizeof(rvc));
7624 for_each_port(adap, i) {
7625 unsigned int rss_size;
7626 struct port_info *p = adap2pinfo(adap, i);
7628 while ((adap->params.portvec & (1 << j)) == 0)
7631 c.op_to_portid = cpu_to_be32(FW_CMD_OP_V(FW_PORT_CMD) |
7632 FW_CMD_REQUEST_F | FW_CMD_READ_F |
7633 FW_PORT_CMD_PORTID_V(j));
7634 c.action_to_len16 = cpu_to_be32(
7635 FW_PORT_CMD_ACTION_V(FW_PORT_ACTION_GET_PORT_INFO) |
7637 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
7641 ret = t4_alloc_vi(adap, mbox, j, pf, vf, 1, addr, &rss_size);
7648 p->rss_size = rss_size;
7649 memcpy(adap->port[i]->dev_addr, addr, ETH_ALEN);
7650 adap->port[i]->dev_port = j;
7652 ret = be32_to_cpu(c.u.info.lstatus_to_modtype);
7653 p->mdio_addr = (ret & FW_PORT_CMD_MDIOCAP_F) ?
7654 FW_PORT_CMD_MDIOADDR_G(ret) : -1;
7655 p->port_type = FW_PORT_CMD_PTYPE_G(ret);
7656 p->mod_type = FW_PORT_MOD_TYPE_NA;
7659 cpu_to_be32(FW_CMD_OP_V(FW_RSS_VI_CONFIG_CMD) |
7660 FW_CMD_REQUEST_F | FW_CMD_READ_F |
7661 FW_RSS_VI_CONFIG_CMD_VIID(p->viid));
7662 rvc.retval_len16 = cpu_to_be32(FW_LEN16(rvc));
7663 ret = t4_wr_mbox(adap, mbox, &rvc, sizeof(rvc), &rvc);
7666 p->rss_mode = be32_to_cpu(rvc.u.basicvirtual.defaultq_to_udpen);
7668 init_link_config(&p->link_cfg, be16_to_cpu(c.u.info.pcap));
7675 * t4_read_cimq_cfg - read CIM queue configuration
7676 * @adap: the adapter
7677 * @base: holds the queue base addresses in bytes
7678 * @size: holds the queue sizes in bytes
7679 * @thres: holds the queue full thresholds in bytes
7681 * Returns the current configuration of the CIM queues, starting with
7682 * the IBQs, then the OBQs.
7684 void t4_read_cimq_cfg(struct adapter *adap, u16 *base, u16 *size, u16 *thres)
7687 int cim_num_obq = is_t4(adap->params.chip) ?
7688 CIM_NUM_OBQ : CIM_NUM_OBQ_T5;
7690 for (i = 0; i < CIM_NUM_IBQ; i++) {
7691 t4_write_reg(adap, CIM_QUEUE_CONFIG_REF_A, IBQSELECT_F |
7693 v = t4_read_reg(adap, CIM_QUEUE_CONFIG_CTRL_A);
7694 /* value is in 256-byte units */
7695 *base++ = CIMQBASE_G(v) * 256;
7696 *size++ = CIMQSIZE_G(v) * 256;
7697 *thres++ = QUEFULLTHRSH_G(v) * 8; /* 8-byte unit */
7699 for (i = 0; i < cim_num_obq; i++) {
7700 t4_write_reg(adap, CIM_QUEUE_CONFIG_REF_A, OBQSELECT_F |
7702 v = t4_read_reg(adap, CIM_QUEUE_CONFIG_CTRL_A);
7703 /* value is in 256-byte units */
7704 *base++ = CIMQBASE_G(v) * 256;
7705 *size++ = CIMQSIZE_G(v) * 256;
7710 * t4_read_cim_ibq - read the contents of a CIM inbound queue
7711 * @adap: the adapter
7712 * @qid: the queue index
7713 * @data: where to store the queue contents
7714 * @n: capacity of @data in 32-bit words
7716 * Reads the contents of the selected CIM queue starting at address 0 up
7717 * to the capacity of @data. @n must be a multiple of 4. Returns < 0 on
7718 * error and the number of 32-bit words actually read on success.
7720 int t4_read_cim_ibq(struct adapter *adap, unsigned int qid, u32 *data, size_t n)
7722 int i, err, attempts;
7724 const unsigned int nwords = CIM_IBQ_SIZE * 4;
7726 if (qid > 5 || (n & 3))
7729 addr = qid * nwords;
7733 /* It might take 3-10ms before the IBQ debug read access is allowed.
7734 * Wait for 1 Sec with a delay of 1 usec.
7738 for (i = 0; i < n; i++, addr++) {
7739 t4_write_reg(adap, CIM_IBQ_DBG_CFG_A, IBQDBGADDR_V(addr) |
7741 err = t4_wait_op_done(adap, CIM_IBQ_DBG_CFG_A, IBQDBGBUSY_F, 0,
7745 *data++ = t4_read_reg(adap, CIM_IBQ_DBG_DATA_A);
7747 t4_write_reg(adap, CIM_IBQ_DBG_CFG_A, 0);
7752 * t4_read_cim_obq - read the contents of a CIM outbound queue
7753 * @adap: the adapter
7754 * @qid: the queue index
7755 * @data: where to store the queue contents
7756 * @n: capacity of @data in 32-bit words
7758 * Reads the contents of the selected CIM queue starting at address 0 up
7759 * to the capacity of @data. @n must be a multiple of 4. Returns < 0 on
7760 * error and the number of 32-bit words actually read on success.
7762 int t4_read_cim_obq(struct adapter *adap, unsigned int qid, u32 *data, size_t n)
7765 unsigned int addr, v, nwords;
7766 int cim_num_obq = is_t4(adap->params.chip) ?
7767 CIM_NUM_OBQ : CIM_NUM_OBQ_T5;
7769 if ((qid > (cim_num_obq - 1)) || (n & 3))
7772 t4_write_reg(adap, CIM_QUEUE_CONFIG_REF_A, OBQSELECT_F |
7773 QUENUMSELECT_V(qid));
7774 v = t4_read_reg(adap, CIM_QUEUE_CONFIG_CTRL_A);
7776 addr = CIMQBASE_G(v) * 64; /* muliple of 256 -> muliple of 4 */
7777 nwords = CIMQSIZE_G(v) * 64; /* same */
7781 for (i = 0; i < n; i++, addr++) {
7782 t4_write_reg(adap, CIM_OBQ_DBG_CFG_A, OBQDBGADDR_V(addr) |
7784 err = t4_wait_op_done(adap, CIM_OBQ_DBG_CFG_A, OBQDBGBUSY_F, 0,
7788 *data++ = t4_read_reg(adap, CIM_OBQ_DBG_DATA_A);
7790 t4_write_reg(adap, CIM_OBQ_DBG_CFG_A, 0);
7795 * t4_cim_read - read a block from CIM internal address space
7796 * @adap: the adapter
7797 * @addr: the start address within the CIM address space
7798 * @n: number of words to read
7799 * @valp: where to store the result
7801 * Reads a block of 4-byte words from the CIM intenal address space.
7803 int t4_cim_read(struct adapter *adap, unsigned int addr, unsigned int n,
7808 if (t4_read_reg(adap, CIM_HOST_ACC_CTRL_A) & HOSTBUSY_F)
7811 for ( ; !ret && n--; addr += 4) {
7812 t4_write_reg(adap, CIM_HOST_ACC_CTRL_A, addr);
7813 ret = t4_wait_op_done(adap, CIM_HOST_ACC_CTRL_A, HOSTBUSY_F,
7816 *valp++ = t4_read_reg(adap, CIM_HOST_ACC_DATA_A);
7822 * t4_cim_write - write a block into CIM internal address space
7823 * @adap: the adapter
7824 * @addr: the start address within the CIM address space
7825 * @n: number of words to write
7826 * @valp: set of values to write
7828 * Writes a block of 4-byte words into the CIM intenal address space.
7830 int t4_cim_write(struct adapter *adap, unsigned int addr, unsigned int n,
7831 const unsigned int *valp)
7835 if (t4_read_reg(adap, CIM_HOST_ACC_CTRL_A) & HOSTBUSY_F)
7838 for ( ; !ret && n--; addr += 4) {
7839 t4_write_reg(adap, CIM_HOST_ACC_DATA_A, *valp++);
7840 t4_write_reg(adap, CIM_HOST_ACC_CTRL_A, addr | HOSTWRITE_F);
7841 ret = t4_wait_op_done(adap, CIM_HOST_ACC_CTRL_A, HOSTBUSY_F,
7847 static int t4_cim_write1(struct adapter *adap, unsigned int addr,
7850 return t4_cim_write(adap, addr, 1, &val);
7854 * t4_cim_read_la - read CIM LA capture buffer
7855 * @adap: the adapter
7856 * @la_buf: where to store the LA data
7857 * @wrptr: the HW write pointer within the capture buffer
7859 * Reads the contents of the CIM LA buffer with the most recent entry at
7860 * the end of the returned data and with the entry at @wrptr first.
7861 * We try to leave the LA in the running state we find it in.
7863 int t4_cim_read_la(struct adapter *adap, u32 *la_buf, unsigned int *wrptr)
7866 unsigned int cfg, val, idx;
7868 ret = t4_cim_read(adap, UP_UP_DBG_LA_CFG_A, 1, &cfg);
7872 if (cfg & UPDBGLAEN_F) { /* LA is running, freeze it */
7873 ret = t4_cim_write1(adap, UP_UP_DBG_LA_CFG_A, 0);
7878 ret = t4_cim_read(adap, UP_UP_DBG_LA_CFG_A, 1, &val);
7882 idx = UPDBGLAWRPTR_G(val);
7886 for (i = 0; i < adap->params.cim_la_size; i++) {
7887 ret = t4_cim_write1(adap, UP_UP_DBG_LA_CFG_A,
7888 UPDBGLARDPTR_V(idx) | UPDBGLARDEN_F);
7891 ret = t4_cim_read(adap, UP_UP_DBG_LA_CFG_A, 1, &val);
7894 if (val & UPDBGLARDEN_F) {
7898 ret = t4_cim_read(adap, UP_UP_DBG_LA_DATA_A, 1, &la_buf[i]);
7901 idx = (idx + 1) & UPDBGLARDPTR_M;
7904 if (cfg & UPDBGLAEN_F) {
7905 int r = t4_cim_write1(adap, UP_UP_DBG_LA_CFG_A,
7906 cfg & ~UPDBGLARDEN_F);
7914 * t4_tp_read_la - read TP LA capture buffer
7915 * @adap: the adapter
7916 * @la_buf: where to store the LA data
7917 * @wrptr: the HW write pointer within the capture buffer
7919 * Reads the contents of the TP LA buffer with the most recent entry at
7920 * the end of the returned data and with the entry at @wrptr first.
7921 * We leave the LA in the running state we find it in.
7923 void t4_tp_read_la(struct adapter *adap, u64 *la_buf, unsigned int *wrptr)
7925 bool last_incomplete;
7926 unsigned int i, cfg, val, idx;
7928 cfg = t4_read_reg(adap, TP_DBG_LA_CONFIG_A) & 0xffff;
7929 if (cfg & DBGLAENABLE_F) /* freeze LA */
7930 t4_write_reg(adap, TP_DBG_LA_CONFIG_A,
7931 adap->params.tp.la_mask | (cfg ^ DBGLAENABLE_F));
7933 val = t4_read_reg(adap, TP_DBG_LA_CONFIG_A);
7934 idx = DBGLAWPTR_G(val);
7935 last_incomplete = DBGLAMODE_G(val) >= 2 && (val & DBGLAWHLF_F) == 0;
7936 if (last_incomplete)
7937 idx = (idx + 1) & DBGLARPTR_M;
7942 val &= ~DBGLARPTR_V(DBGLARPTR_M);
7943 val |= adap->params.tp.la_mask;
7945 for (i = 0; i < TPLA_SIZE; i++) {
7946 t4_write_reg(adap, TP_DBG_LA_CONFIG_A, DBGLARPTR_V(idx) | val);
7947 la_buf[i] = t4_read_reg64(adap, TP_DBG_LA_DATAL_A);
7948 idx = (idx + 1) & DBGLARPTR_M;
7951 /* Wipe out last entry if it isn't valid */
7952 if (last_incomplete)
7953 la_buf[TPLA_SIZE - 1] = ~0ULL;
7955 if (cfg & DBGLAENABLE_F) /* restore running state */
7956 t4_write_reg(adap, TP_DBG_LA_CONFIG_A,
7957 cfg | adap->params.tp.la_mask);
7960 /* SGE Hung Ingress DMA Warning Threshold time and Warning Repeat Rate (in
7961 * seconds). If we find one of the SGE Ingress DMA State Machines in the same
7962 * state for more than the Warning Threshold then we'll issue a warning about
7963 * a potential hang. We'll repeat the warning as the SGE Ingress DMA Channel
7964 * appears to be hung every Warning Repeat second till the situation clears.
7965 * If the situation clears, we'll note that as well.
7967 #define SGE_IDMA_WARN_THRESH 1
7968 #define SGE_IDMA_WARN_REPEAT 300
7971 * t4_idma_monitor_init - initialize SGE Ingress DMA Monitor
7972 * @adapter: the adapter
7973 * @idma: the adapter IDMA Monitor state
7975 * Initialize the state of an SGE Ingress DMA Monitor.
7977 void t4_idma_monitor_init(struct adapter *adapter,
7978 struct sge_idma_monitor_state *idma)
7980 /* Initialize the state variables for detecting an SGE Ingress DMA
7981 * hang. The SGE has internal counters which count up on each clock
7982 * tick whenever the SGE finds its Ingress DMA State Engines in the
7983 * same state they were on the previous clock tick. The clock used is
7984 * the Core Clock so we have a limit on the maximum "time" they can
7985 * record; typically a very small number of seconds. For instance,
7986 * with a 600MHz Core Clock, we can only count up to a bit more than
7987 * 7s. So we'll synthesize a larger counter in order to not run the
7988 * risk of having the "timers" overflow and give us the flexibility to
7989 * maintain a Hung SGE State Machine of our own which operates across
7990 * a longer time frame.
7992 idma->idma_1s_thresh = core_ticks_per_usec(adapter) * 1000000; /* 1s */
7993 idma->idma_stalled[0] = 0;
7994 idma->idma_stalled[1] = 0;
7998 * t4_idma_monitor - monitor SGE Ingress DMA state
7999 * @adapter: the adapter
8000 * @idma: the adapter IDMA Monitor state
8001 * @hz: number of ticks/second
8002 * @ticks: number of ticks since the last IDMA Monitor call
8004 void t4_idma_monitor(struct adapter *adapter,
8005 struct sge_idma_monitor_state *idma,
8008 int i, idma_same_state_cnt[2];
8010 /* Read the SGE Debug Ingress DMA Same State Count registers. These
8011 * are counters inside the SGE which count up on each clock when the
8012 * SGE finds its Ingress DMA State Engines in the same states they
8013 * were in the previous clock. The counters will peg out at
8014 * 0xffffffff without wrapping around so once they pass the 1s
8015 * threshold they'll stay above that till the IDMA state changes.
8017 t4_write_reg(adapter, SGE_DEBUG_INDEX_A, 13);
8018 idma_same_state_cnt[0] = t4_read_reg(adapter, SGE_DEBUG_DATA_HIGH_A);
8019 idma_same_state_cnt[1] = t4_read_reg(adapter, SGE_DEBUG_DATA_LOW_A);
8021 for (i = 0; i < 2; i++) {
8022 u32 debug0, debug11;
8024 /* If the Ingress DMA Same State Counter ("timer") is less
8025 * than 1s, then we can reset our synthesized Stall Timer and
8026 * continue. If we have previously emitted warnings about a
8027 * potential stalled Ingress Queue, issue a note indicating
8028 * that the Ingress Queue has resumed forward progress.
8030 if (idma_same_state_cnt[i] < idma->idma_1s_thresh) {
8031 if (idma->idma_stalled[i] >= SGE_IDMA_WARN_THRESH * hz)
8032 dev_warn(adapter->pdev_dev, "SGE idma%d, queue %u, "
8033 "resumed after %d seconds\n",
8034 i, idma->idma_qid[i],
8035 idma->idma_stalled[i] / hz);
8036 idma->idma_stalled[i] = 0;
8040 /* Synthesize an SGE Ingress DMA Same State Timer in the Hz
8041 * domain. The first time we get here it'll be because we
8042 * passed the 1s Threshold; each additional time it'll be
8043 * because the RX Timer Callback is being fired on its regular
8046 * If the stall is below our Potential Hung Ingress Queue
8047 * Warning Threshold, continue.
8049 if (idma->idma_stalled[i] == 0) {
8050 idma->idma_stalled[i] = hz;
8051 idma->idma_warn[i] = 0;
8053 idma->idma_stalled[i] += ticks;
8054 idma->idma_warn[i] -= ticks;
8057 if (idma->idma_stalled[i] < SGE_IDMA_WARN_THRESH * hz)
8060 /* We'll issue a warning every SGE_IDMA_WARN_REPEAT seconds.
8062 if (idma->idma_warn[i] > 0)
8064 idma->idma_warn[i] = SGE_IDMA_WARN_REPEAT * hz;
8066 /* Read and save the SGE IDMA State and Queue ID information.
8067 * We do this every time in case it changes across time ...
8068 * can't be too careful ...
8070 t4_write_reg(adapter, SGE_DEBUG_INDEX_A, 0);
8071 debug0 = t4_read_reg(adapter, SGE_DEBUG_DATA_LOW_A);
8072 idma->idma_state[i] = (debug0 >> (i * 9)) & 0x3f;
8074 t4_write_reg(adapter, SGE_DEBUG_INDEX_A, 11);
8075 debug11 = t4_read_reg(adapter, SGE_DEBUG_DATA_LOW_A);
8076 idma->idma_qid[i] = (debug11 >> (i * 16)) & 0xffff;
8078 dev_warn(adapter->pdev_dev, "SGE idma%u, queue %u, potentially stuck in "
8079 "state %u for %d seconds (debug0=%#x, debug11=%#x)\n",
8080 i, idma->idma_qid[i], idma->idma_state[i],
8081 idma->idma_stalled[i] / hz,
8083 t4_sge_decode_idma_state(adapter, idma->idma_state[i]);