2 * This file is part of the Chelsio T4 Ethernet driver for Linux.
4 * Copyright (c) 2003-2014 Chelsio Communications, Inc. All rights reserved.
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
35 #include <linux/delay.h>
38 #include "t4_values.h"
40 #include "t4fw_version.h"
43 * t4_wait_op_done_val - wait until an operation is completed
44 * @adapter: the adapter performing the operation
45 * @reg: the register to check for completion
46 * @mask: a single-bit field within @reg that indicates completion
47 * @polarity: the value of the field when the operation is completed
48 * @attempts: number of check iterations
49 * @delay: delay in usecs between iterations
50 * @valp: where to store the value of the register at completion time
52 * Wait until an operation is completed by checking a bit in a register
53 * up to @attempts times. If @valp is not NULL the value of the register
54 * at the time it indicated completion is stored there. Returns 0 if the
55 * operation completes and -EAGAIN otherwise.
57 static int t4_wait_op_done_val(struct adapter *adapter, int reg, u32 mask,
58 int polarity, int attempts, int delay, u32 *valp)
61 u32 val = t4_read_reg(adapter, reg);
63 if (!!(val & mask) == polarity) {
75 static inline int t4_wait_op_done(struct adapter *adapter, int reg, u32 mask,
76 int polarity, int attempts, int delay)
78 return t4_wait_op_done_val(adapter, reg, mask, polarity, attempts,
83 * t4_set_reg_field - set a register field to a value
84 * @adapter: the adapter to program
85 * @addr: the register address
86 * @mask: specifies the portion of the register to modify
87 * @val: the new value for the register field
89 * Sets a register field specified by the supplied mask to the
92 void t4_set_reg_field(struct adapter *adapter, unsigned int addr, u32 mask,
95 u32 v = t4_read_reg(adapter, addr) & ~mask;
97 t4_write_reg(adapter, addr, v | val);
98 (void) t4_read_reg(adapter, addr); /* flush */
102 * t4_read_indirect - read indirectly addressed registers
104 * @addr_reg: register holding the indirect address
105 * @data_reg: register holding the value of the indirect register
106 * @vals: where the read register values are stored
107 * @nregs: how many indirect registers to read
108 * @start_idx: index of first indirect register to read
110 * Reads registers that are accessed indirectly through an address/data
113 void t4_read_indirect(struct adapter *adap, unsigned int addr_reg,
114 unsigned int data_reg, u32 *vals,
115 unsigned int nregs, unsigned int start_idx)
118 t4_write_reg(adap, addr_reg, start_idx);
119 *vals++ = t4_read_reg(adap, data_reg);
125 * t4_write_indirect - write indirectly addressed registers
127 * @addr_reg: register holding the indirect addresses
128 * @data_reg: register holding the value for the indirect registers
129 * @vals: values to write
130 * @nregs: how many indirect registers to write
131 * @start_idx: address of first indirect register to write
133 * Writes a sequential block of registers that are accessed indirectly
134 * through an address/data register pair.
136 void t4_write_indirect(struct adapter *adap, unsigned int addr_reg,
137 unsigned int data_reg, const u32 *vals,
138 unsigned int nregs, unsigned int start_idx)
141 t4_write_reg(adap, addr_reg, start_idx++);
142 t4_write_reg(adap, data_reg, *vals++);
147 * Read a 32-bit PCI Configuration Space register via the PCI-E backdoor
148 * mechanism. This guarantees that we get the real value even if we're
149 * operating within a Virtual Machine and the Hypervisor is trapping our
150 * Configuration Space accesses.
152 void t4_hw_pci_read_cfg4(struct adapter *adap, int reg, u32 *val)
154 u32 req = FUNCTION_V(adap->pf) | REGISTER_V(reg);
156 if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5)
161 if (is_t4(adap->params.chip))
164 t4_write_reg(adap, PCIE_CFG_SPACE_REQ_A, req);
165 *val = t4_read_reg(adap, PCIE_CFG_SPACE_DATA_A);
167 /* Reset ENABLE to 0 so reads of PCIE_CFG_SPACE_DATA won't cause a
168 * Configuration Space read. (None of the other fields matter when
169 * ENABLE is 0 so a simple register write is easier than a
170 * read-modify-write via t4_set_reg_field().)
172 t4_write_reg(adap, PCIE_CFG_SPACE_REQ_A, 0);
176 * t4_report_fw_error - report firmware error
179 * The adapter firmware can indicate error conditions to the host.
180 * If the firmware has indicated an error, print out the reason for
181 * the firmware error.
183 static void t4_report_fw_error(struct adapter *adap)
185 static const char *const reason[] = {
186 "Crash", /* PCIE_FW_EVAL_CRASH */
187 "During Device Preparation", /* PCIE_FW_EVAL_PREP */
188 "During Device Configuration", /* PCIE_FW_EVAL_CONF */
189 "During Device Initialization", /* PCIE_FW_EVAL_INIT */
190 "Unexpected Event", /* PCIE_FW_EVAL_UNEXPECTEDEVENT */
191 "Insufficient Airflow", /* PCIE_FW_EVAL_OVERHEAT */
192 "Device Shutdown", /* PCIE_FW_EVAL_DEVICESHUTDOWN */
193 "Reserved", /* reserved */
197 pcie_fw = t4_read_reg(adap, PCIE_FW_A);
198 if (pcie_fw & PCIE_FW_ERR_F)
199 dev_err(adap->pdev_dev, "Firmware reports adapter error: %s\n",
200 reason[PCIE_FW_EVAL_G(pcie_fw)]);
204 * Get the reply to a mailbox command and store it in @rpl in big-endian order.
206 static void get_mbox_rpl(struct adapter *adap, __be64 *rpl, int nflit,
209 for ( ; nflit; nflit--, mbox_addr += 8)
210 *rpl++ = cpu_to_be64(t4_read_reg64(adap, mbox_addr));
214 * Handle a FW assertion reported in a mailbox.
216 static void fw_asrt(struct adapter *adap, u32 mbox_addr)
218 struct fw_debug_cmd asrt;
220 get_mbox_rpl(adap, (__be64 *)&asrt, sizeof(asrt) / 8, mbox_addr);
221 dev_alert(adap->pdev_dev,
222 "FW assertion at %.16s:%u, val0 %#x, val1 %#x\n",
223 asrt.u.assert.filename_0_7, be32_to_cpu(asrt.u.assert.line),
224 be32_to_cpu(asrt.u.assert.x), be32_to_cpu(asrt.u.assert.y));
227 static void dump_mbox(struct adapter *adap, int mbox, u32 data_reg)
229 dev_err(adap->pdev_dev,
230 "mbox %d: %llx %llx %llx %llx %llx %llx %llx %llx\n", mbox,
231 (unsigned long long)t4_read_reg64(adap, data_reg),
232 (unsigned long long)t4_read_reg64(adap, data_reg + 8),
233 (unsigned long long)t4_read_reg64(adap, data_reg + 16),
234 (unsigned long long)t4_read_reg64(adap, data_reg + 24),
235 (unsigned long long)t4_read_reg64(adap, data_reg + 32),
236 (unsigned long long)t4_read_reg64(adap, data_reg + 40),
237 (unsigned long long)t4_read_reg64(adap, data_reg + 48),
238 (unsigned long long)t4_read_reg64(adap, data_reg + 56));
242 * t4_wr_mbox_meat_timeout - send a command to FW through the given mailbox
244 * @mbox: index of the mailbox to use
245 * @cmd: the command to write
246 * @size: command length in bytes
247 * @rpl: where to optionally store the reply
248 * @sleep_ok: if true we may sleep while awaiting command completion
249 * @timeout: time to wait for command to finish before timing out
251 * Sends the given command to FW through the selected mailbox and waits
252 * for the FW to execute the command. If @rpl is not %NULL it is used to
253 * store the FW's reply to the command. The command and its optional
254 * reply are of the same length. FW can take up to %FW_CMD_MAX_TIMEOUT ms
255 * to respond. @sleep_ok determines whether we may sleep while awaiting
256 * the response. If sleeping is allowed we use progressive backoff
259 * The return value is 0 on success or a negative errno on failure. A
260 * failure can happen either because we are not able to execute the
261 * command or FW executes it but signals an error. In the latter case
262 * the return value is the error code indicated by FW (negated).
264 int t4_wr_mbox_meat_timeout(struct adapter *adap, int mbox, const void *cmd,
265 int size, void *rpl, bool sleep_ok, int timeout)
267 static const int delay[] = {
268 1, 1, 3, 5, 10, 10, 20, 50, 100, 200
273 int i, ms, delay_idx;
274 const __be64 *p = cmd;
275 u32 data_reg = PF_REG(mbox, CIM_PF_MAILBOX_DATA_A);
276 u32 ctl_reg = PF_REG(mbox, CIM_PF_MAILBOX_CTRL_A);
278 if ((size & 15) || size > MBOX_LEN)
282 * If the device is off-line, as in EEH, commands will time out.
283 * Fail them early so we don't waste time waiting.
285 if (adap->pdev->error_state != pci_channel_io_normal)
288 v = MBOWNER_G(t4_read_reg(adap, ctl_reg));
289 for (i = 0; v == MBOX_OWNER_NONE && i < 3; i++)
290 v = MBOWNER_G(t4_read_reg(adap, ctl_reg));
292 if (v != MBOX_OWNER_DRV)
293 return v ? -EBUSY : -ETIMEDOUT;
295 for (i = 0; i < size; i += 8)
296 t4_write_reg64(adap, data_reg + i, be64_to_cpu(*p++));
298 t4_write_reg(adap, ctl_reg, MBMSGVALID_F | MBOWNER_V(MBOX_OWNER_FW));
299 t4_read_reg(adap, ctl_reg); /* flush write */
304 for (i = 0; i < timeout; i += ms) {
306 ms = delay[delay_idx]; /* last element may repeat */
307 if (delay_idx < ARRAY_SIZE(delay) - 1)
313 v = t4_read_reg(adap, ctl_reg);
314 if (MBOWNER_G(v) == MBOX_OWNER_DRV) {
315 if (!(v & MBMSGVALID_F)) {
316 t4_write_reg(adap, ctl_reg, 0);
320 res = t4_read_reg64(adap, data_reg);
321 if (FW_CMD_OP_G(res >> 32) == FW_DEBUG_CMD) {
322 fw_asrt(adap, data_reg);
323 res = FW_CMD_RETVAL_V(EIO);
325 get_mbox_rpl(adap, rpl, size / 8, data_reg);
328 if (FW_CMD_RETVAL_G((int)res))
329 dump_mbox(adap, mbox, data_reg);
330 t4_write_reg(adap, ctl_reg, 0);
331 return -FW_CMD_RETVAL_G((int)res);
335 dump_mbox(adap, mbox, data_reg);
336 dev_err(adap->pdev_dev, "command %#x in mailbox %d timed out\n",
337 *(const u8 *)cmd, mbox);
338 t4_report_fw_error(adap);
342 int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size,
343 void *rpl, bool sleep_ok)
345 return t4_wr_mbox_meat_timeout(adap, mbox, cmd, size, rpl, sleep_ok,
349 static int t4_edc_err_read(struct adapter *adap, int idx)
351 u32 edc_ecc_err_addr_reg;
354 if (is_t4(adap->params.chip)) {
355 CH_WARN(adap, "%s: T4 NOT supported.\n", __func__);
358 if (idx != 0 && idx != 1) {
359 CH_WARN(adap, "%s: idx %d NOT supported.\n", __func__, idx);
363 edc_ecc_err_addr_reg = EDC_T5_REG(EDC_H_ECC_ERR_ADDR_A, idx);
364 rdata_reg = EDC_T5_REG(EDC_H_BIST_STATUS_RDATA_A, idx);
367 "edc%d err addr 0x%x: 0x%x.\n",
368 idx, edc_ecc_err_addr_reg,
369 t4_read_reg(adap, edc_ecc_err_addr_reg));
371 "bist: 0x%x, status %llx %llx %llx %llx %llx %llx %llx %llx %llx.\n",
373 (unsigned long long)t4_read_reg64(adap, rdata_reg),
374 (unsigned long long)t4_read_reg64(adap, rdata_reg + 8),
375 (unsigned long long)t4_read_reg64(adap, rdata_reg + 16),
376 (unsigned long long)t4_read_reg64(adap, rdata_reg + 24),
377 (unsigned long long)t4_read_reg64(adap, rdata_reg + 32),
378 (unsigned long long)t4_read_reg64(adap, rdata_reg + 40),
379 (unsigned long long)t4_read_reg64(adap, rdata_reg + 48),
380 (unsigned long long)t4_read_reg64(adap, rdata_reg + 56),
381 (unsigned long long)t4_read_reg64(adap, rdata_reg + 64));
387 * t4_memory_rw - read/write EDC 0, EDC 1 or MC via PCIE memory window
389 * @win: PCI-E Memory Window to use
390 * @mtype: memory type: MEM_EDC0, MEM_EDC1 or MEM_MC
391 * @addr: address within indicated memory type
392 * @len: amount of memory to transfer
393 * @hbuf: host memory buffer
394 * @dir: direction of transfer T4_MEMORY_READ (1) or T4_MEMORY_WRITE (0)
396 * Reads/writes an [almost] arbitrary memory region in the firmware: the
397 * firmware memory address and host buffer must be aligned on 32-bit
398 * boudaries; the length may be arbitrary. The memory is transferred as
399 * a raw byte sequence from/to the firmware's memory. If this memory
400 * contains data structures which contain multi-byte integers, it's the
401 * caller's responsibility to perform appropriate byte order conversions.
403 int t4_memory_rw(struct adapter *adap, int win, int mtype, u32 addr,
404 u32 len, void *hbuf, int dir)
406 u32 pos, offset, resid, memoffset;
407 u32 edc_size, mc_size, win_pf, mem_reg, mem_aperture, mem_base;
410 /* Argument sanity checks ...
412 if (addr & 0x3 || (uintptr_t)hbuf & 0x3)
416 /* It's convenient to be able to handle lengths which aren't a
417 * multiple of 32-bits because we often end up transferring files to
418 * the firmware. So we'll handle that by normalizing the length here
419 * and then handling any residual transfer at the end.
424 /* Offset into the region of memory which is being accessed
427 * MEM_MC = 2 -- MEM_MC for chips with only 1 memory controller
428 * MEM_MC1 = 3 -- for chips with 2 memory controllers (e.g. T5)
430 edc_size = EDRAM0_SIZE_G(t4_read_reg(adap, MA_EDRAM0_BAR_A));
431 if (mtype != MEM_MC1)
432 memoffset = (mtype * (edc_size * 1024 * 1024));
434 mc_size = EXT_MEM0_SIZE_G(t4_read_reg(adap,
435 MA_EXT_MEMORY0_BAR_A));
436 memoffset = (MEM_MC0 * edc_size + mc_size) * 1024 * 1024;
439 /* Determine the PCIE_MEM_ACCESS_OFFSET */
440 addr = addr + memoffset;
442 /* Each PCI-E Memory Window is programmed with a window size -- or
443 * "aperture" -- which controls the granularity of its mapping onto
444 * adapter memory. We need to grab that aperture in order to know
445 * how to use the specified window. The window is also programmed
446 * with the base address of the Memory Window in BAR0's address
447 * space. For T4 this is an absolute PCI-E Bus Address. For T5
448 * the address is relative to BAR0.
450 mem_reg = t4_read_reg(adap,
451 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A,
453 mem_aperture = 1 << (WINDOW_G(mem_reg) + WINDOW_SHIFT_X);
454 mem_base = PCIEOFST_G(mem_reg) << PCIEOFST_SHIFT_X;
455 if (is_t4(adap->params.chip))
456 mem_base -= adap->t4_bar0;
457 win_pf = is_t4(adap->params.chip) ? 0 : PFNUM_V(adap->pf);
459 /* Calculate our initial PCI-E Memory Window Position and Offset into
462 pos = addr & ~(mem_aperture-1);
465 /* Set up initial PCI-E Memory Window to cover the start of our
466 * transfer. (Read it back to ensure that changes propagate before we
467 * attempt to use the new value.)
470 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, win),
473 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, win));
475 /* Transfer data to/from the adapter as long as there's an integral
476 * number of 32-bit transfers to complete.
478 * A note on Endianness issues:
480 * The "register" reads and writes below from/to the PCI-E Memory
481 * Window invoke the standard adapter Big-Endian to PCI-E Link
482 * Little-Endian "swizzel." As a result, if we have the following
483 * data in adapter memory:
485 * Memory: ... | b0 | b1 | b2 | b3 | ...
486 * Address: i+0 i+1 i+2 i+3
488 * Then a read of the adapter memory via the PCI-E Memory Window
493 * [ b3 | b2 | b1 | b0 ]
495 * If this value is stored into local memory on a Little-Endian system
496 * it will show up correctly in local memory as:
498 * ( ..., b0, b1, b2, b3, ... )
500 * But on a Big-Endian system, the store will show up in memory
501 * incorrectly swizzled as:
503 * ( ..., b3, b2, b1, b0, ... )
505 * So we need to account for this in the reads and writes to the
506 * PCI-E Memory Window below by undoing the register read/write
510 if (dir == T4_MEMORY_READ)
511 *buf++ = le32_to_cpu((__force __le32)t4_read_reg(adap,
514 t4_write_reg(adap, mem_base + offset,
515 (__force u32)cpu_to_le32(*buf++));
516 offset += sizeof(__be32);
517 len -= sizeof(__be32);
519 /* If we've reached the end of our current window aperture,
520 * move the PCI-E Memory Window on to the next. Note that
521 * doing this here after "len" may be 0 allows us to set up
522 * the PCI-E Memory Window for a possible final residual
525 if (offset == mem_aperture) {
529 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A,
532 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A,
537 /* If the original transfer had a length which wasn't a multiple of
538 * 32-bits, now's where we need to finish off the transfer of the
539 * residual amount. The PCI-E Memory Window has already been moved
540 * above (if necessary) to cover this final transfer.
550 if (dir == T4_MEMORY_READ) {
551 last.word = le32_to_cpu(
552 (__force __le32)t4_read_reg(adap,
554 for (bp = (unsigned char *)buf, i = resid; i < 4; i++)
555 bp[i] = last.byte[i];
558 for (i = resid; i < 4; i++)
560 t4_write_reg(adap, mem_base + offset,
561 (__force u32)cpu_to_le32(last.word));
568 /* Return the specified PCI-E Configuration Space register from our Physical
569 * Function. We try first via a Firmware LDST Command since we prefer to let
570 * the firmware own all of these registers, but if that fails we go for it
571 * directly ourselves.
573 u32 t4_read_pcie_cfg4(struct adapter *adap, int reg)
575 u32 val, ldst_addrspace;
577 /* If fw_attach != 0, construct and send the Firmware LDST Command to
578 * retrieve the specified PCI-E Configuration Space register.
580 struct fw_ldst_cmd ldst_cmd;
583 memset(&ldst_cmd, 0, sizeof(ldst_cmd));
584 ldst_addrspace = FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_FUNC_PCIE);
585 ldst_cmd.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
589 ldst_cmd.cycles_to_len16 = cpu_to_be32(FW_LEN16(ldst_cmd));
590 ldst_cmd.u.pcie.select_naccess = FW_LDST_CMD_NACCESS_V(1);
591 ldst_cmd.u.pcie.ctrl_to_fn =
592 (FW_LDST_CMD_LC_F | FW_LDST_CMD_FN_V(adap->pf));
593 ldst_cmd.u.pcie.r = reg;
595 /* If the LDST Command succeeds, return the result, otherwise
596 * fall through to reading it directly ourselves ...
598 ret = t4_wr_mbox(adap, adap->mbox, &ldst_cmd, sizeof(ldst_cmd),
601 val = be32_to_cpu(ldst_cmd.u.pcie.data[0]);
603 /* Read the desired Configuration Space register via the PCI-E
604 * Backdoor mechanism.
606 t4_hw_pci_read_cfg4(adap, reg, &val);
610 /* Get the window based on base passed to it.
611 * Window aperture is currently unhandled, but there is no use case for it
614 static u32 t4_get_window(struct adapter *adap, u32 pci_base, u64 pci_mask,
619 if (is_t4(adap->params.chip)) {
622 /* Truncation intentional: we only read the bottom 32-bits of
623 * the 64-bit BAR0/BAR1 ... We use the hardware backdoor
624 * mechanism to read BAR0 instead of using
625 * pci_resource_start() because we could be operating from
626 * within a Virtual Machine which is trapping our accesses to
627 * our Configuration Space and we need to set up the PCI-E
628 * Memory Window decoders with the actual addresses which will
629 * be coming across the PCI-E link.
631 bar0 = t4_read_pcie_cfg4(adap, pci_base);
633 adap->t4_bar0 = bar0;
635 ret = bar0 + memwin_base;
637 /* For T5, only relative offset inside the PCIe BAR is passed */
643 /* Get the default utility window (win0) used by everyone */
644 u32 t4_get_util_window(struct adapter *adap)
646 return t4_get_window(adap, PCI_BASE_ADDRESS_0,
647 PCI_BASE_ADDRESS_MEM_MASK, MEMWIN0_BASE);
650 /* Set up memory window for accessing adapter memory ranges. (Read
651 * back MA register to ensure that changes propagate before we attempt
652 * to use the new values.)
654 void t4_setup_memwin(struct adapter *adap, u32 memwin_base, u32 window)
657 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A, window),
658 memwin_base | BIR_V(0) |
659 WINDOW_V(ilog2(MEMWIN0_APERTURE) - WINDOW_SHIFT_X));
661 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A, window));
665 * t4_get_regs_len - return the size of the chips register set
666 * @adapter: the adapter
668 * Returns the size of the chip's BAR0 register space.
670 unsigned int t4_get_regs_len(struct adapter *adapter)
672 unsigned int chip_version = CHELSIO_CHIP_VERSION(adapter->params.chip);
674 switch (chip_version) {
676 return T4_REGMAP_SIZE;
680 return T5_REGMAP_SIZE;
683 dev_err(adapter->pdev_dev,
684 "Unsupported chip version %d\n", chip_version);
689 * t4_get_regs - read chip registers into provided buffer
691 * @buf: register buffer
692 * @buf_size: size (in bytes) of register buffer
694 * If the provided register buffer isn't large enough for the chip's
695 * full register range, the register dump will be truncated to the
696 * register buffer's size.
698 void t4_get_regs(struct adapter *adap, void *buf, size_t buf_size)
700 static const unsigned int t4_reg_ranges[] = {
1158 static const unsigned int t5_reg_ranges[] = {
1933 static const unsigned int t6_reg_ranges[] = {
2510 u32 *buf_end = (u32 *)((char *)buf + buf_size);
2511 const unsigned int *reg_ranges;
2512 int reg_ranges_size, range;
2513 unsigned int chip_version = CHELSIO_CHIP_VERSION(adap->params.chip);
2515 /* Select the right set of register ranges to dump depending on the
2516 * adapter chip type.
2518 switch (chip_version) {
2520 reg_ranges = t4_reg_ranges;
2521 reg_ranges_size = ARRAY_SIZE(t4_reg_ranges);
2525 reg_ranges = t5_reg_ranges;
2526 reg_ranges_size = ARRAY_SIZE(t5_reg_ranges);
2530 reg_ranges = t6_reg_ranges;
2531 reg_ranges_size = ARRAY_SIZE(t6_reg_ranges);
2535 dev_err(adap->pdev_dev,
2536 "Unsupported chip version %d\n", chip_version);
2540 /* Clear the register buffer and insert the appropriate register
2541 * values selected by the above register ranges.
2543 memset(buf, 0, buf_size);
2544 for (range = 0; range < reg_ranges_size; range += 2) {
2545 unsigned int reg = reg_ranges[range];
2546 unsigned int last_reg = reg_ranges[range + 1];
2547 u32 *bufp = (u32 *)((char *)buf + reg);
2549 /* Iterate across the register range filling in the register
2550 * buffer but don't write past the end of the register buffer.
2552 while (reg <= last_reg && bufp < buf_end) {
2553 *bufp++ = t4_read_reg(adap, reg);
2559 #define EEPROM_STAT_ADDR 0x7bfc
2560 #define VPD_SIZE 0x800
2561 #define VPD_BASE 0x400
2562 #define VPD_BASE_OLD 0
2563 #define VPD_LEN 1024
2564 #define CHELSIO_VPD_UNIQUE_ID 0x82
2567 * t4_seeprom_wp - enable/disable EEPROM write protection
2568 * @adapter: the adapter
2569 * @enable: whether to enable or disable write protection
2571 * Enables or disables write protection on the serial EEPROM.
2573 int t4_seeprom_wp(struct adapter *adapter, bool enable)
2575 unsigned int v = enable ? 0xc : 0;
2576 int ret = pci_write_vpd(adapter->pdev, EEPROM_STAT_ADDR, 4, &v);
2577 return ret < 0 ? ret : 0;
2581 * t4_get_raw_vpd_params - read VPD parameters from VPD EEPROM
2582 * @adapter: adapter to read
2583 * @p: where to store the parameters
2585 * Reads card parameters stored in VPD EEPROM.
2587 int t4_get_raw_vpd_params(struct adapter *adapter, struct vpd_params *p)
2589 int i, ret = 0, addr;
2592 unsigned int vpdr_len, kw_offset, id_len;
2594 vpd = vmalloc(VPD_LEN);
2598 /* We have two VPD data structures stored in the adapter VPD area.
2599 * By default, Linux calculates the size of the VPD area by traversing
2600 * the first VPD area at offset 0x0, so we need to tell the OS what
2601 * our real VPD size is.
2603 ret = pci_set_vpd_size(adapter->pdev, VPD_SIZE);
2607 /* Card information normally starts at VPD_BASE but early cards had
2610 ret = pci_read_vpd(adapter->pdev, VPD_BASE, sizeof(u32), vpd);
2614 /* The VPD shall have a unique identifier specified by the PCI SIG.
2615 * For chelsio adapters, the identifier is 0x82. The first byte of a VPD
2616 * shall be CHELSIO_VPD_UNIQUE_ID (0x82). The VPD programming software
2617 * is expected to automatically put this entry at the
2618 * beginning of the VPD.
2620 addr = *vpd == CHELSIO_VPD_UNIQUE_ID ? VPD_BASE : VPD_BASE_OLD;
2622 ret = pci_read_vpd(adapter->pdev, addr, VPD_LEN, vpd);
2626 if (vpd[0] != PCI_VPD_LRDT_ID_STRING) {
2627 dev_err(adapter->pdev_dev, "missing VPD ID string\n");
2632 id_len = pci_vpd_lrdt_size(vpd);
2633 if (id_len > ID_LEN)
2636 i = pci_vpd_find_tag(vpd, 0, VPD_LEN, PCI_VPD_LRDT_RO_DATA);
2638 dev_err(adapter->pdev_dev, "missing VPD-R section\n");
2643 vpdr_len = pci_vpd_lrdt_size(&vpd[i]);
2644 kw_offset = i + PCI_VPD_LRDT_TAG_SIZE;
2645 if (vpdr_len + kw_offset > VPD_LEN) {
2646 dev_err(adapter->pdev_dev, "bad VPD-R length %u\n", vpdr_len);
2651 #define FIND_VPD_KW(var, name) do { \
2652 var = pci_vpd_find_info_keyword(vpd, kw_offset, vpdr_len, name); \
2654 dev_err(adapter->pdev_dev, "missing VPD keyword " name "\n"); \
2658 var += PCI_VPD_INFO_FLD_HDR_SIZE; \
2661 FIND_VPD_KW(i, "RV");
2662 for (csum = 0; i >= 0; i--)
2666 dev_err(adapter->pdev_dev,
2667 "corrupted VPD EEPROM, actual csum %u\n", csum);
2672 FIND_VPD_KW(ec, "EC");
2673 FIND_VPD_KW(sn, "SN");
2674 FIND_VPD_KW(pn, "PN");
2675 FIND_VPD_KW(na, "NA");
2678 memcpy(p->id, vpd + PCI_VPD_LRDT_TAG_SIZE, id_len);
2680 memcpy(p->ec, vpd + ec, EC_LEN);
2682 i = pci_vpd_info_field_size(vpd + sn - PCI_VPD_INFO_FLD_HDR_SIZE);
2683 memcpy(p->sn, vpd + sn, min(i, SERNUM_LEN));
2685 i = pci_vpd_info_field_size(vpd + pn - PCI_VPD_INFO_FLD_HDR_SIZE);
2686 memcpy(p->pn, vpd + pn, min(i, PN_LEN));
2688 memcpy(p->na, vpd + na, min(i, MACADDR_LEN));
2689 strim((char *)p->na);
2697 * t4_get_vpd_params - read VPD parameters & retrieve Core Clock
2698 * @adapter: adapter to read
2699 * @p: where to store the parameters
2701 * Reads card parameters stored in VPD EEPROM and retrieves the Core
2702 * Clock. This can only be called after a connection to the firmware
2705 int t4_get_vpd_params(struct adapter *adapter, struct vpd_params *p)
2707 u32 cclk_param, cclk_val;
2710 /* Grab the raw VPD parameters.
2712 ret = t4_get_raw_vpd_params(adapter, p);
2716 /* Ask firmware for the Core Clock since it knows how to translate the
2717 * Reference Clock ('V2') VPD field into a Core Clock value ...
2719 cclk_param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
2720 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_CCLK));
2721 ret = t4_query_params(adapter, adapter->mbox, adapter->pf, 0,
2722 1, &cclk_param, &cclk_val);
2731 /* serial flash and firmware constants */
2733 SF_ATTEMPTS = 10, /* max retries for SF operations */
2735 /* flash command opcodes */
2736 SF_PROG_PAGE = 2, /* program page */
2737 SF_WR_DISABLE = 4, /* disable writes */
2738 SF_RD_STATUS = 5, /* read status register */
2739 SF_WR_ENABLE = 6, /* enable writes */
2740 SF_RD_DATA_FAST = 0xb, /* read flash */
2741 SF_RD_ID = 0x9f, /* read ID */
2742 SF_ERASE_SECTOR = 0xd8, /* erase sector */
2744 FW_MAX_SIZE = 16 * SF_SEC_SIZE,
2748 * sf1_read - read data from the serial flash
2749 * @adapter: the adapter
2750 * @byte_cnt: number of bytes to read
2751 * @cont: whether another operation will be chained
2752 * @lock: whether to lock SF for PL access only
2753 * @valp: where to store the read data
2755 * Reads up to 4 bytes of data from the serial flash. The location of
2756 * the read needs to be specified prior to calling this by issuing the
2757 * appropriate commands to the serial flash.
2759 static int sf1_read(struct adapter *adapter, unsigned int byte_cnt, int cont,
2760 int lock, u32 *valp)
2764 if (!byte_cnt || byte_cnt > 4)
2766 if (t4_read_reg(adapter, SF_OP_A) & SF_BUSY_F)
2768 t4_write_reg(adapter, SF_OP_A, SF_LOCK_V(lock) |
2769 SF_CONT_V(cont) | BYTECNT_V(byte_cnt - 1));
2770 ret = t4_wait_op_done(adapter, SF_OP_A, SF_BUSY_F, 0, SF_ATTEMPTS, 5);
2772 *valp = t4_read_reg(adapter, SF_DATA_A);
2777 * sf1_write - write data to the serial flash
2778 * @adapter: the adapter
2779 * @byte_cnt: number of bytes to write
2780 * @cont: whether another operation will be chained
2781 * @lock: whether to lock SF for PL access only
2782 * @val: value to write
2784 * Writes up to 4 bytes of data to the serial flash. The location of
2785 * the write needs to be specified prior to calling this by issuing the
2786 * appropriate commands to the serial flash.
2788 static int sf1_write(struct adapter *adapter, unsigned int byte_cnt, int cont,
2791 if (!byte_cnt || byte_cnt > 4)
2793 if (t4_read_reg(adapter, SF_OP_A) & SF_BUSY_F)
2795 t4_write_reg(adapter, SF_DATA_A, val);
2796 t4_write_reg(adapter, SF_OP_A, SF_LOCK_V(lock) |
2797 SF_CONT_V(cont) | BYTECNT_V(byte_cnt - 1) | OP_V(1));
2798 return t4_wait_op_done(adapter, SF_OP_A, SF_BUSY_F, 0, SF_ATTEMPTS, 5);
2802 * flash_wait_op - wait for a flash operation to complete
2803 * @adapter: the adapter
2804 * @attempts: max number of polls of the status register
2805 * @delay: delay between polls in ms
2807 * Wait for a flash operation to complete by polling the status register.
2809 static int flash_wait_op(struct adapter *adapter, int attempts, int delay)
2815 if ((ret = sf1_write(adapter, 1, 1, 1, SF_RD_STATUS)) != 0 ||
2816 (ret = sf1_read(adapter, 1, 0, 1, &status)) != 0)
2820 if (--attempts == 0)
2828 * t4_read_flash - read words from serial flash
2829 * @adapter: the adapter
2830 * @addr: the start address for the read
2831 * @nwords: how many 32-bit words to read
2832 * @data: where to store the read data
2833 * @byte_oriented: whether to store data as bytes or as words
2835 * Read the specified number of 32-bit words from the serial flash.
2836 * If @byte_oriented is set the read data is stored as a byte array
2837 * (i.e., big-endian), otherwise as 32-bit words in the platform's
2838 * natural endianness.
2840 int t4_read_flash(struct adapter *adapter, unsigned int addr,
2841 unsigned int nwords, u32 *data, int byte_oriented)
2845 if (addr + nwords * sizeof(u32) > adapter->params.sf_size || (addr & 3))
2848 addr = swab32(addr) | SF_RD_DATA_FAST;
2850 if ((ret = sf1_write(adapter, 4, 1, 0, addr)) != 0 ||
2851 (ret = sf1_read(adapter, 1, 1, 0, data)) != 0)
2854 for ( ; nwords; nwords--, data++) {
2855 ret = sf1_read(adapter, 4, nwords > 1, nwords == 1, data);
2857 t4_write_reg(adapter, SF_OP_A, 0); /* unlock SF */
2861 *data = (__force __u32)(cpu_to_be32(*data));
2867 * t4_write_flash - write up to a page of data to the serial flash
2868 * @adapter: the adapter
2869 * @addr: the start address to write
2870 * @n: length of data to write in bytes
2871 * @data: the data to write
2873 * Writes up to a page of data (256 bytes) to the serial flash starting
2874 * at the given address. All the data must be written to the same page.
2876 static int t4_write_flash(struct adapter *adapter, unsigned int addr,
2877 unsigned int n, const u8 *data)
2881 unsigned int i, c, left, val, offset = addr & 0xff;
2883 if (addr >= adapter->params.sf_size || offset + n > SF_PAGE_SIZE)
2886 val = swab32(addr) | SF_PROG_PAGE;
2888 if ((ret = sf1_write(adapter, 1, 0, 1, SF_WR_ENABLE)) != 0 ||
2889 (ret = sf1_write(adapter, 4, 1, 1, val)) != 0)
2892 for (left = n; left; left -= c) {
2894 for (val = 0, i = 0; i < c; ++i)
2895 val = (val << 8) + *data++;
2897 ret = sf1_write(adapter, c, c != left, 1, val);
2901 ret = flash_wait_op(adapter, 8, 1);
2905 t4_write_reg(adapter, SF_OP_A, 0); /* unlock SF */
2907 /* Read the page to verify the write succeeded */
2908 ret = t4_read_flash(adapter, addr & ~0xff, ARRAY_SIZE(buf), buf, 1);
2912 if (memcmp(data - n, (u8 *)buf + offset, n)) {
2913 dev_err(adapter->pdev_dev,
2914 "failed to correctly write the flash page at %#x\n",
2921 t4_write_reg(adapter, SF_OP_A, 0); /* unlock SF */
2926 * t4_get_fw_version - read the firmware version
2927 * @adapter: the adapter
2928 * @vers: where to place the version
2930 * Reads the FW version from flash.
2932 int t4_get_fw_version(struct adapter *adapter, u32 *vers)
2934 return t4_read_flash(adapter, FLASH_FW_START +
2935 offsetof(struct fw_hdr, fw_ver), 1,
2940 * t4_get_tp_version - read the TP microcode version
2941 * @adapter: the adapter
2942 * @vers: where to place the version
2944 * Reads the TP microcode version from flash.
2946 int t4_get_tp_version(struct adapter *adapter, u32 *vers)
2948 return t4_read_flash(adapter, FLASH_FW_START +
2949 offsetof(struct fw_hdr, tp_microcode_ver),
2954 * t4_get_exprom_version - return the Expansion ROM version (if any)
2955 * @adapter: the adapter
2956 * @vers: where to place the version
2958 * Reads the Expansion ROM header from FLASH and returns the version
2959 * number (if present) through the @vers return value pointer. We return
2960 * this in the Firmware Version Format since it's convenient. Return
2961 * 0 on success, -ENOENT if no Expansion ROM is present.
2963 int t4_get_exprom_version(struct adapter *adap, u32 *vers)
2965 struct exprom_header {
2966 unsigned char hdr_arr[16]; /* must start with 0x55aa */
2967 unsigned char hdr_ver[4]; /* Expansion ROM version */
2969 u32 exprom_header_buf[DIV_ROUND_UP(sizeof(struct exprom_header),
2973 ret = t4_read_flash(adap, FLASH_EXP_ROM_START,
2974 ARRAY_SIZE(exprom_header_buf), exprom_header_buf,
2979 hdr = (struct exprom_header *)exprom_header_buf;
2980 if (hdr->hdr_arr[0] != 0x55 || hdr->hdr_arr[1] != 0xaa)
2983 *vers = (FW_HDR_FW_VER_MAJOR_V(hdr->hdr_ver[0]) |
2984 FW_HDR_FW_VER_MINOR_V(hdr->hdr_ver[1]) |
2985 FW_HDR_FW_VER_MICRO_V(hdr->hdr_ver[2]) |
2986 FW_HDR_FW_VER_BUILD_V(hdr->hdr_ver[3]));
2991 * t4_check_fw_version - check if the FW is supported with this driver
2992 * @adap: the adapter
2994 * Checks if an adapter's FW is compatible with the driver. Returns 0
2995 * if there's exact match, a negative error if the version could not be
2996 * read or there's a major version mismatch
2998 int t4_check_fw_version(struct adapter *adap)
3000 int i, ret, major, minor, micro;
3001 int exp_major, exp_minor, exp_micro;
3002 unsigned int chip_version = CHELSIO_CHIP_VERSION(adap->params.chip);
3004 ret = t4_get_fw_version(adap, &adap->params.fw_vers);
3005 /* Try multiple times before returning error */
3006 for (i = 0; (ret == -EBUSY || ret == -EAGAIN) && i < 3; i++)
3007 ret = t4_get_fw_version(adap, &adap->params.fw_vers);
3012 major = FW_HDR_FW_VER_MAJOR_G(adap->params.fw_vers);
3013 minor = FW_HDR_FW_VER_MINOR_G(adap->params.fw_vers);
3014 micro = FW_HDR_FW_VER_MICRO_G(adap->params.fw_vers);
3016 switch (chip_version) {
3018 exp_major = T4FW_MIN_VERSION_MAJOR;
3019 exp_minor = T4FW_MIN_VERSION_MINOR;
3020 exp_micro = T4FW_MIN_VERSION_MICRO;
3023 exp_major = T5FW_MIN_VERSION_MAJOR;
3024 exp_minor = T5FW_MIN_VERSION_MINOR;
3025 exp_micro = T5FW_MIN_VERSION_MICRO;
3028 exp_major = T6FW_MIN_VERSION_MAJOR;
3029 exp_minor = T6FW_MIN_VERSION_MINOR;
3030 exp_micro = T6FW_MIN_VERSION_MICRO;
3033 dev_err(adap->pdev_dev, "Unsupported chip type, %x\n",
3038 if (major < exp_major || (major == exp_major && minor < exp_minor) ||
3039 (major == exp_major && minor == exp_minor && micro < exp_micro)) {
3040 dev_err(adap->pdev_dev,
3041 "Card has firmware version %u.%u.%u, minimum "
3042 "supported firmware is %u.%u.%u.\n", major, minor,
3043 micro, exp_major, exp_minor, exp_micro);
3049 /* Is the given firmware API compatible with the one the driver was compiled
3052 static int fw_compatible(const struct fw_hdr *hdr1, const struct fw_hdr *hdr2)
3055 /* short circuit if it's the exact same firmware version */
3056 if (hdr1->chip == hdr2->chip && hdr1->fw_ver == hdr2->fw_ver)
3059 #define SAME_INTF(x) (hdr1->intfver_##x == hdr2->intfver_##x)
3060 if (hdr1->chip == hdr2->chip && SAME_INTF(nic) && SAME_INTF(vnic) &&
3061 SAME_INTF(ri) && SAME_INTF(iscsi) && SAME_INTF(fcoe))
3068 /* The firmware in the filesystem is usable, but should it be installed?
3069 * This routine explains itself in detail if it indicates the filesystem
3070 * firmware should be installed.
3072 static int should_install_fs_fw(struct adapter *adap, int card_fw_usable,
3077 if (!card_fw_usable) {
3078 reason = "incompatible or unusable";
3083 reason = "older than the version supported with this driver";
3090 dev_err(adap->pdev_dev, "firmware on card (%u.%u.%u.%u) is %s, "
3091 "installing firmware %u.%u.%u.%u on card.\n",
3092 FW_HDR_FW_VER_MAJOR_G(c), FW_HDR_FW_VER_MINOR_G(c),
3093 FW_HDR_FW_VER_MICRO_G(c), FW_HDR_FW_VER_BUILD_G(c), reason,
3094 FW_HDR_FW_VER_MAJOR_G(k), FW_HDR_FW_VER_MINOR_G(k),
3095 FW_HDR_FW_VER_MICRO_G(k), FW_HDR_FW_VER_BUILD_G(k));
3100 int t4_prep_fw(struct adapter *adap, struct fw_info *fw_info,
3101 const u8 *fw_data, unsigned int fw_size,
3102 struct fw_hdr *card_fw, enum dev_state state,
3105 int ret, card_fw_usable, fs_fw_usable;
3106 const struct fw_hdr *fs_fw;
3107 const struct fw_hdr *drv_fw;
3109 drv_fw = &fw_info->fw_hdr;
3111 /* Read the header of the firmware on the card */
3112 ret = -t4_read_flash(adap, FLASH_FW_START,
3113 sizeof(*card_fw) / sizeof(uint32_t),
3114 (uint32_t *)card_fw, 1);
3116 card_fw_usable = fw_compatible(drv_fw, (const void *)card_fw);
3118 dev_err(adap->pdev_dev,
3119 "Unable to read card's firmware header: %d\n", ret);
3123 if (fw_data != NULL) {
3124 fs_fw = (const void *)fw_data;
3125 fs_fw_usable = fw_compatible(drv_fw, fs_fw);
3131 if (card_fw_usable && card_fw->fw_ver == drv_fw->fw_ver &&
3132 (!fs_fw_usable || fs_fw->fw_ver == drv_fw->fw_ver)) {
3133 /* Common case: the firmware on the card is an exact match and
3134 * the filesystem one is an exact match too, or the filesystem
3135 * one is absent/incompatible.
3137 } else if (fs_fw_usable && state == DEV_STATE_UNINIT &&
3138 should_install_fs_fw(adap, card_fw_usable,
3139 be32_to_cpu(fs_fw->fw_ver),
3140 be32_to_cpu(card_fw->fw_ver))) {
3141 ret = -t4_fw_upgrade(adap, adap->mbox, fw_data,
3144 dev_err(adap->pdev_dev,
3145 "failed to install firmware: %d\n", ret);
3149 /* Installed successfully, update the cached header too. */
3152 *reset = 0; /* already reset as part of load_fw */
3155 if (!card_fw_usable) {
3158 d = be32_to_cpu(drv_fw->fw_ver);
3159 c = be32_to_cpu(card_fw->fw_ver);
3160 k = fs_fw ? be32_to_cpu(fs_fw->fw_ver) : 0;
3162 dev_err(adap->pdev_dev, "Cannot find a usable firmware: "
3164 "driver compiled with %d.%d.%d.%d, "
3165 "card has %d.%d.%d.%d, filesystem has %d.%d.%d.%d\n",
3167 FW_HDR_FW_VER_MAJOR_G(d), FW_HDR_FW_VER_MINOR_G(d),
3168 FW_HDR_FW_VER_MICRO_G(d), FW_HDR_FW_VER_BUILD_G(d),
3169 FW_HDR_FW_VER_MAJOR_G(c), FW_HDR_FW_VER_MINOR_G(c),
3170 FW_HDR_FW_VER_MICRO_G(c), FW_HDR_FW_VER_BUILD_G(c),
3171 FW_HDR_FW_VER_MAJOR_G(k), FW_HDR_FW_VER_MINOR_G(k),
3172 FW_HDR_FW_VER_MICRO_G(k), FW_HDR_FW_VER_BUILD_G(k));
3177 /* We're using whatever's on the card and it's known to be good. */
3178 adap->params.fw_vers = be32_to_cpu(card_fw->fw_ver);
3179 adap->params.tp_vers = be32_to_cpu(card_fw->tp_microcode_ver);
3186 * t4_flash_erase_sectors - erase a range of flash sectors
3187 * @adapter: the adapter
3188 * @start: the first sector to erase
3189 * @end: the last sector to erase
3191 * Erases the sectors in the given inclusive range.
3193 static int t4_flash_erase_sectors(struct adapter *adapter, int start, int end)
3197 if (end >= adapter->params.sf_nsec)
3200 while (start <= end) {
3201 if ((ret = sf1_write(adapter, 1, 0, 1, SF_WR_ENABLE)) != 0 ||
3202 (ret = sf1_write(adapter, 4, 0, 1,
3203 SF_ERASE_SECTOR | (start << 8))) != 0 ||
3204 (ret = flash_wait_op(adapter, 14, 500)) != 0) {
3205 dev_err(adapter->pdev_dev,
3206 "erase of flash sector %d failed, error %d\n",
3212 t4_write_reg(adapter, SF_OP_A, 0); /* unlock SF */
3217 * t4_flash_cfg_addr - return the address of the flash configuration file
3218 * @adapter: the adapter
3220 * Return the address within the flash where the Firmware Configuration
3223 unsigned int t4_flash_cfg_addr(struct adapter *adapter)
3225 if (adapter->params.sf_size == 0x100000)
3226 return FLASH_FPGA_CFG_START;
3228 return FLASH_CFG_START;
3231 /* Return TRUE if the specified firmware matches the adapter. I.e. T4
3232 * firmware for T4 adapters, T5 firmware for T5 adapters, etc. We go ahead
3233 * and emit an error message for mismatched firmware to save our caller the
3236 static bool t4_fw_matches_chip(const struct adapter *adap,
3237 const struct fw_hdr *hdr)
3239 /* The expression below will return FALSE for any unsupported adapter
3240 * which will keep us "honest" in the future ...
3242 if ((is_t4(adap->params.chip) && hdr->chip == FW_HDR_CHIP_T4) ||
3243 (is_t5(adap->params.chip) && hdr->chip == FW_HDR_CHIP_T5) ||
3244 (is_t6(adap->params.chip) && hdr->chip == FW_HDR_CHIP_T6))
3247 dev_err(adap->pdev_dev,
3248 "FW image (%d) is not suitable for this adapter (%d)\n",
3249 hdr->chip, CHELSIO_CHIP_VERSION(adap->params.chip));
3254 * t4_load_fw - download firmware
3255 * @adap: the adapter
3256 * @fw_data: the firmware image to write
3259 * Write the supplied firmware image to the card's serial flash.
3261 int t4_load_fw(struct adapter *adap, const u8 *fw_data, unsigned int size)
3266 u8 first_page[SF_PAGE_SIZE];
3267 const __be32 *p = (const __be32 *)fw_data;
3268 const struct fw_hdr *hdr = (const struct fw_hdr *)fw_data;
3269 unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec;
3270 unsigned int fw_img_start = adap->params.sf_fw_start;
3271 unsigned int fw_start_sec = fw_img_start / sf_sec_size;
3274 dev_err(adap->pdev_dev, "FW image has no data\n");
3278 dev_err(adap->pdev_dev,
3279 "FW image size not multiple of 512 bytes\n");
3282 if ((unsigned int)be16_to_cpu(hdr->len512) * 512 != size) {
3283 dev_err(adap->pdev_dev,
3284 "FW image size differs from size in FW header\n");
3287 if (size > FW_MAX_SIZE) {
3288 dev_err(adap->pdev_dev, "FW image too large, max is %u bytes\n",
3292 if (!t4_fw_matches_chip(adap, hdr))
3295 for (csum = 0, i = 0; i < size / sizeof(csum); i++)
3296 csum += be32_to_cpu(p[i]);
3298 if (csum != 0xffffffff) {
3299 dev_err(adap->pdev_dev,
3300 "corrupted firmware image, checksum %#x\n", csum);
3304 i = DIV_ROUND_UP(size, sf_sec_size); /* # of sectors spanned */
3305 ret = t4_flash_erase_sectors(adap, fw_start_sec, fw_start_sec + i - 1);
3310 * We write the correct version at the end so the driver can see a bad
3311 * version if the FW write fails. Start by writing a copy of the
3312 * first page with a bad version.
3314 memcpy(first_page, fw_data, SF_PAGE_SIZE);
3315 ((struct fw_hdr *)first_page)->fw_ver = cpu_to_be32(0xffffffff);
3316 ret = t4_write_flash(adap, fw_img_start, SF_PAGE_SIZE, first_page);
3320 addr = fw_img_start;
3321 for (size -= SF_PAGE_SIZE; size; size -= SF_PAGE_SIZE) {
3322 addr += SF_PAGE_SIZE;
3323 fw_data += SF_PAGE_SIZE;
3324 ret = t4_write_flash(adap, addr, SF_PAGE_SIZE, fw_data);
3329 ret = t4_write_flash(adap,
3330 fw_img_start + offsetof(struct fw_hdr, fw_ver),
3331 sizeof(hdr->fw_ver), (const u8 *)&hdr->fw_ver);
3334 dev_err(adap->pdev_dev, "firmware download failed, error %d\n",
3337 ret = t4_get_fw_version(adap, &adap->params.fw_vers);
3342 * t4_phy_fw_ver - return current PHY firmware version
3343 * @adap: the adapter
3344 * @phy_fw_ver: return value buffer for PHY firmware version
3346 * Returns the current version of external PHY firmware on the
3349 int t4_phy_fw_ver(struct adapter *adap, int *phy_fw_ver)
3354 param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3355 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_PHYFW) |
3356 FW_PARAMS_PARAM_Y_V(adap->params.portvec) |
3357 FW_PARAMS_PARAM_Z_V(FW_PARAMS_PARAM_DEV_PHYFW_VERSION));
3358 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1,
3367 * t4_load_phy_fw - download port PHY firmware
3368 * @adap: the adapter
3369 * @win: the PCI-E Memory Window index to use for t4_memory_rw()
3370 * @win_lock: the lock to use to guard the memory copy
3371 * @phy_fw_version: function to check PHY firmware versions
3372 * @phy_fw_data: the PHY firmware image to write
3373 * @phy_fw_size: image size
3375 * Transfer the specified PHY firmware to the adapter. If a non-NULL
3376 * @phy_fw_version is supplied, then it will be used to determine if
3377 * it's necessary to perform the transfer by comparing the version
3378 * of any existing adapter PHY firmware with that of the passed in
3379 * PHY firmware image. If @win_lock is non-NULL then it will be used
3380 * around the call to t4_memory_rw() which transfers the PHY firmware
3383 * A negative error number will be returned if an error occurs. If
3384 * version number support is available and there's no need to upgrade
3385 * the firmware, 0 will be returned. If firmware is successfully
3386 * transferred to the adapter, 1 will be retured.
3388 * NOTE: some adapters only have local RAM to store the PHY firmware. As
3389 * a result, a RESET of the adapter would cause that RAM to lose its
3390 * contents. Thus, loading PHY firmware on such adapters must happen
3391 * after any FW_RESET_CMDs ...
3393 int t4_load_phy_fw(struct adapter *adap,
3394 int win, spinlock_t *win_lock,
3395 int (*phy_fw_version)(const u8 *, size_t),
3396 const u8 *phy_fw_data, size_t phy_fw_size)
3398 unsigned long mtype = 0, maddr = 0;
3400 int cur_phy_fw_ver = 0, new_phy_fw_vers = 0;
3403 /* If we have version number support, then check to see if the adapter
3404 * already has up-to-date PHY firmware loaded.
3406 if (phy_fw_version) {
3407 new_phy_fw_vers = phy_fw_version(phy_fw_data, phy_fw_size);
3408 ret = t4_phy_fw_ver(adap, &cur_phy_fw_ver);
3412 if (cur_phy_fw_ver >= new_phy_fw_vers) {
3413 CH_WARN(adap, "PHY Firmware already up-to-date, "
3414 "version %#x\n", cur_phy_fw_ver);
3419 /* Ask the firmware where it wants us to copy the PHY firmware image.
3420 * The size of the file requires a special version of the READ coommand
3421 * which will pass the file size via the values field in PARAMS_CMD and
3422 * retrieve the return value from firmware and place it in the same
3425 param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3426 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_PHYFW) |
3427 FW_PARAMS_PARAM_Y_V(adap->params.portvec) |
3428 FW_PARAMS_PARAM_Z_V(FW_PARAMS_PARAM_DEV_PHYFW_DOWNLOAD));
3430 ret = t4_query_params_rw(adap, adap->mbox, adap->pf, 0, 1,
3435 maddr = (val & 0xff) << 16;
3437 /* Copy the supplied PHY Firmware image to the adapter memory location
3438 * allocated by the adapter firmware.
3441 spin_lock_bh(win_lock);
3442 ret = t4_memory_rw(adap, win, mtype, maddr,
3443 phy_fw_size, (__be32 *)phy_fw_data,
3446 spin_unlock_bh(win_lock);
3450 /* Tell the firmware that the PHY firmware image has been written to
3451 * RAM and it can now start copying it over to the PHYs. The chip
3452 * firmware will RESET the affected PHYs as part of this operation
3453 * leaving them running the new PHY firmware image.
3455 param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3456 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_PHYFW) |
3457 FW_PARAMS_PARAM_Y_V(adap->params.portvec) |
3458 FW_PARAMS_PARAM_Z_V(FW_PARAMS_PARAM_DEV_PHYFW_DOWNLOAD));
3459 ret = t4_set_params_timeout(adap, adap->mbox, adap->pf, 0, 1,
3460 ¶m, &val, 30000);
3462 /* If we have version number support, then check to see that the new
3463 * firmware got loaded properly.
3465 if (phy_fw_version) {
3466 ret = t4_phy_fw_ver(adap, &cur_phy_fw_ver);
3470 if (cur_phy_fw_ver != new_phy_fw_vers) {
3471 CH_WARN(adap, "PHY Firmware did not update: "
3472 "version on adapter %#x, "
3473 "version flashed %#x\n",
3474 cur_phy_fw_ver, new_phy_fw_vers);
3483 * t4_fwcache - firmware cache operation
3484 * @adap: the adapter
3485 * @op : the operation (flush or flush and invalidate)
3487 int t4_fwcache(struct adapter *adap, enum fw_params_param_dev_fwcache op)
3489 struct fw_params_cmd c;
3491 memset(&c, 0, sizeof(c));
3493 cpu_to_be32(FW_CMD_OP_V(FW_PARAMS_CMD) |
3494 FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
3495 FW_PARAMS_CMD_PFN_V(adap->pf) |
3496 FW_PARAMS_CMD_VFN_V(0));
3497 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
3499 cpu_to_be32(FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3500 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_FWCACHE));
3501 c.param[0].val = (__force __be32)op;
3503 return t4_wr_mbox(adap, adap->mbox, &c, sizeof(c), NULL);
3506 void t4_cim_read_pif_la(struct adapter *adap, u32 *pif_req, u32 *pif_rsp,
3507 unsigned int *pif_req_wrptr,
3508 unsigned int *pif_rsp_wrptr)
3511 u32 cfg, val, req, rsp;
3513 cfg = t4_read_reg(adap, CIM_DEBUGCFG_A);
3514 if (cfg & LADBGEN_F)
3515 t4_write_reg(adap, CIM_DEBUGCFG_A, cfg ^ LADBGEN_F);
3517 val = t4_read_reg(adap, CIM_DEBUGSTS_A);
3518 req = POLADBGWRPTR_G(val);
3519 rsp = PILADBGWRPTR_G(val);
3521 *pif_req_wrptr = req;
3523 *pif_rsp_wrptr = rsp;
3525 for (i = 0; i < CIM_PIFLA_SIZE; i++) {
3526 for (j = 0; j < 6; j++) {
3527 t4_write_reg(adap, CIM_DEBUGCFG_A, POLADBGRDPTR_V(req) |
3528 PILADBGRDPTR_V(rsp));
3529 *pif_req++ = t4_read_reg(adap, CIM_PO_LA_DEBUGDATA_A);
3530 *pif_rsp++ = t4_read_reg(adap, CIM_PI_LA_DEBUGDATA_A);
3534 req = (req + 2) & POLADBGRDPTR_M;
3535 rsp = (rsp + 2) & PILADBGRDPTR_M;
3537 t4_write_reg(adap, CIM_DEBUGCFG_A, cfg);
3540 void t4_cim_read_ma_la(struct adapter *adap, u32 *ma_req, u32 *ma_rsp)
3545 cfg = t4_read_reg(adap, CIM_DEBUGCFG_A);
3546 if (cfg & LADBGEN_F)
3547 t4_write_reg(adap, CIM_DEBUGCFG_A, cfg ^ LADBGEN_F);
3549 for (i = 0; i < CIM_MALA_SIZE; i++) {
3550 for (j = 0; j < 5; j++) {
3552 t4_write_reg(adap, CIM_DEBUGCFG_A, POLADBGRDPTR_V(idx) |
3553 PILADBGRDPTR_V(idx));
3554 *ma_req++ = t4_read_reg(adap, CIM_PO_LA_MADEBUGDATA_A);
3555 *ma_rsp++ = t4_read_reg(adap, CIM_PI_LA_MADEBUGDATA_A);
3558 t4_write_reg(adap, CIM_DEBUGCFG_A, cfg);
3561 void t4_ulprx_read_la(struct adapter *adap, u32 *la_buf)
3565 for (i = 0; i < 8; i++) {
3566 u32 *p = la_buf + i;
3568 t4_write_reg(adap, ULP_RX_LA_CTL_A, i);
3569 j = t4_read_reg(adap, ULP_RX_LA_WRPTR_A);
3570 t4_write_reg(adap, ULP_RX_LA_RDPTR_A, j);
3571 for (j = 0; j < ULPRX_LA_SIZE; j++, p += 8)
3572 *p = t4_read_reg(adap, ULP_RX_LA_RDDATA_A);
3576 #define ADVERT_MASK (FW_PORT_CAP_SPEED_100M | FW_PORT_CAP_SPEED_1G |\
3577 FW_PORT_CAP_SPEED_10G | FW_PORT_CAP_SPEED_40G | \
3581 * t4_link_l1cfg - apply link configuration to MAC/PHY
3582 * @phy: the PHY to setup
3583 * @mac: the MAC to setup
3584 * @lc: the requested link configuration
3586 * Set up a port's MAC and PHY according to a desired link configuration.
3587 * - If the PHY can auto-negotiate first decide what to advertise, then
3588 * enable/disable auto-negotiation as desired, and reset.
3589 * - If the PHY does not auto-negotiate just reset it.
3590 * - If auto-negotiation is off set the MAC to the proper speed/duplex/FC,
3591 * otherwise do it later based on the outcome of auto-negotiation.
3593 int t4_link_l1cfg(struct adapter *adap, unsigned int mbox, unsigned int port,
3594 struct link_config *lc)
3596 struct fw_port_cmd c;
3597 unsigned int fc = 0, mdi = FW_PORT_CAP_MDI_V(FW_PORT_CAP_MDI_AUTO);
3600 if (lc->requested_fc & PAUSE_RX)
3601 fc |= FW_PORT_CAP_FC_RX;
3602 if (lc->requested_fc & PAUSE_TX)
3603 fc |= FW_PORT_CAP_FC_TX;
3605 memset(&c, 0, sizeof(c));
3606 c.op_to_portid = cpu_to_be32(FW_CMD_OP_V(FW_PORT_CMD) |
3607 FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
3608 FW_PORT_CMD_PORTID_V(port));
3610 cpu_to_be32(FW_PORT_CMD_ACTION_V(FW_PORT_ACTION_L1_CFG) |
3613 if (!(lc->supported & FW_PORT_CAP_ANEG)) {
3614 c.u.l1cfg.rcap = cpu_to_be32((lc->supported & ADVERT_MASK) |
3616 lc->fc = lc->requested_fc & (PAUSE_RX | PAUSE_TX);
3617 } else if (lc->autoneg == AUTONEG_DISABLE) {
3618 c.u.l1cfg.rcap = cpu_to_be32(lc->requested_speed | fc | mdi);
3619 lc->fc = lc->requested_fc & (PAUSE_RX | PAUSE_TX);
3621 c.u.l1cfg.rcap = cpu_to_be32(lc->advertising | fc | mdi);
3623 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
3627 * t4_restart_aneg - restart autonegotiation
3628 * @adap: the adapter
3629 * @mbox: mbox to use for the FW command
3630 * @port: the port id
3632 * Restarts autonegotiation for the selected port.
3634 int t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port)
3636 struct fw_port_cmd c;
3638 memset(&c, 0, sizeof(c));
3639 c.op_to_portid = cpu_to_be32(FW_CMD_OP_V(FW_PORT_CMD) |
3640 FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
3641 FW_PORT_CMD_PORTID_V(port));
3643 cpu_to_be32(FW_PORT_CMD_ACTION_V(FW_PORT_ACTION_L1_CFG) |
3645 c.u.l1cfg.rcap = cpu_to_be32(FW_PORT_CAP_ANEG);
3646 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
3649 typedef void (*int_handler_t)(struct adapter *adap);
3652 unsigned int mask; /* bits to check in interrupt status */
3653 const char *msg; /* message to print or NULL */
3654 short stat_idx; /* stat counter to increment or -1 */
3655 unsigned short fatal; /* whether the condition reported is fatal */
3656 int_handler_t int_handler; /* platform-specific int handler */
3660 * t4_handle_intr_status - table driven interrupt handler
3661 * @adapter: the adapter that generated the interrupt
3662 * @reg: the interrupt status register to process
3663 * @acts: table of interrupt actions
3665 * A table driven interrupt handler that applies a set of masks to an
3666 * interrupt status word and performs the corresponding actions if the
3667 * interrupts described by the mask have occurred. The actions include
3668 * optionally emitting a warning or alert message. The table is terminated
3669 * by an entry specifying mask 0. Returns the number of fatal interrupt
3672 static int t4_handle_intr_status(struct adapter *adapter, unsigned int reg,
3673 const struct intr_info *acts)
3676 unsigned int mask = 0;
3677 unsigned int status = t4_read_reg(adapter, reg);
3679 for ( ; acts->mask; ++acts) {
3680 if (!(status & acts->mask))
3684 dev_alert(adapter->pdev_dev, "%s (0x%x)\n", acts->msg,
3685 status & acts->mask);
3686 } else if (acts->msg && printk_ratelimit())
3687 dev_warn(adapter->pdev_dev, "%s (0x%x)\n", acts->msg,
3688 status & acts->mask);
3689 if (acts->int_handler)
3690 acts->int_handler(adapter);
3694 if (status) /* clear processed interrupts */
3695 t4_write_reg(adapter, reg, status);
3700 * Interrupt handler for the PCIE module.
3702 static void pcie_intr_handler(struct adapter *adapter)
3704 static const struct intr_info sysbus_intr_info[] = {
3705 { RNPP_F, "RXNP array parity error", -1, 1 },
3706 { RPCP_F, "RXPC array parity error", -1, 1 },
3707 { RCIP_F, "RXCIF array parity error", -1, 1 },
3708 { RCCP_F, "Rx completions control array parity error", -1, 1 },
3709 { RFTP_F, "RXFT array parity error", -1, 1 },
3712 static const struct intr_info pcie_port_intr_info[] = {
3713 { TPCP_F, "TXPC array parity error", -1, 1 },
3714 { TNPP_F, "TXNP array parity error", -1, 1 },
3715 { TFTP_F, "TXFT array parity error", -1, 1 },
3716 { TCAP_F, "TXCA array parity error", -1, 1 },
3717 { TCIP_F, "TXCIF array parity error", -1, 1 },
3718 { RCAP_F, "RXCA array parity error", -1, 1 },
3719 { OTDD_F, "outbound request TLP discarded", -1, 1 },
3720 { RDPE_F, "Rx data parity error", -1, 1 },
3721 { TDUE_F, "Tx uncorrectable data error", -1, 1 },
3724 static const struct intr_info pcie_intr_info[] = {
3725 { MSIADDRLPERR_F, "MSI AddrL parity error", -1, 1 },
3726 { MSIADDRHPERR_F, "MSI AddrH parity error", -1, 1 },
3727 { MSIDATAPERR_F, "MSI data parity error", -1, 1 },
3728 { MSIXADDRLPERR_F, "MSI-X AddrL parity error", -1, 1 },
3729 { MSIXADDRHPERR_F, "MSI-X AddrH parity error", -1, 1 },
3730 { MSIXDATAPERR_F, "MSI-X data parity error", -1, 1 },
3731 { MSIXDIPERR_F, "MSI-X DI parity error", -1, 1 },
3732 { PIOCPLPERR_F, "PCI PIO completion FIFO parity error", -1, 1 },
3733 { PIOREQPERR_F, "PCI PIO request FIFO parity error", -1, 1 },
3734 { TARTAGPERR_F, "PCI PCI target tag FIFO parity error", -1, 1 },
3735 { CCNTPERR_F, "PCI CMD channel count parity error", -1, 1 },
3736 { CREQPERR_F, "PCI CMD channel request parity error", -1, 1 },
3737 { CRSPPERR_F, "PCI CMD channel response parity error", -1, 1 },
3738 { DCNTPERR_F, "PCI DMA channel count parity error", -1, 1 },
3739 { DREQPERR_F, "PCI DMA channel request parity error", -1, 1 },
3740 { DRSPPERR_F, "PCI DMA channel response parity error", -1, 1 },
3741 { HCNTPERR_F, "PCI HMA channel count parity error", -1, 1 },
3742 { HREQPERR_F, "PCI HMA channel request parity error", -1, 1 },
3743 { HRSPPERR_F, "PCI HMA channel response parity error", -1, 1 },
3744 { CFGSNPPERR_F, "PCI config snoop FIFO parity error", -1, 1 },
3745 { FIDPERR_F, "PCI FID parity error", -1, 1 },
3746 { INTXCLRPERR_F, "PCI INTx clear parity error", -1, 1 },
3747 { MATAGPERR_F, "PCI MA tag parity error", -1, 1 },
3748 { PIOTAGPERR_F, "PCI PIO tag parity error", -1, 1 },
3749 { RXCPLPERR_F, "PCI Rx completion parity error", -1, 1 },
3750 { RXWRPERR_F, "PCI Rx write parity error", -1, 1 },
3751 { RPLPERR_F, "PCI replay buffer parity error", -1, 1 },
3752 { PCIESINT_F, "PCI core secondary fault", -1, 1 },
3753 { PCIEPINT_F, "PCI core primary fault", -1, 1 },
3754 { UNXSPLCPLERR_F, "PCI unexpected split completion error",
3759 static struct intr_info t5_pcie_intr_info[] = {
3760 { MSTGRPPERR_F, "Master Response Read Queue parity error",
3762 { MSTTIMEOUTPERR_F, "Master Timeout FIFO parity error", -1, 1 },
3763 { MSIXSTIPERR_F, "MSI-X STI SRAM parity error", -1, 1 },
3764 { MSIXADDRLPERR_F, "MSI-X AddrL parity error", -1, 1 },
3765 { MSIXADDRHPERR_F, "MSI-X AddrH parity error", -1, 1 },
3766 { MSIXDATAPERR_F, "MSI-X data parity error", -1, 1 },
3767 { MSIXDIPERR_F, "MSI-X DI parity error", -1, 1 },
3768 { PIOCPLGRPPERR_F, "PCI PIO completion Group FIFO parity error",
3770 { PIOREQGRPPERR_F, "PCI PIO request Group FIFO parity error",
3772 { TARTAGPERR_F, "PCI PCI target tag FIFO parity error", -1, 1 },
3773 { MSTTAGQPERR_F, "PCI master tag queue parity error", -1, 1 },
3774 { CREQPERR_F, "PCI CMD channel request parity error", -1, 1 },
3775 { CRSPPERR_F, "PCI CMD channel response parity error", -1, 1 },
3776 { DREQWRPERR_F, "PCI DMA channel write request parity error",
3778 { DREQPERR_F, "PCI DMA channel request parity error", -1, 1 },
3779 { DRSPPERR_F, "PCI DMA channel response parity error", -1, 1 },
3780 { HREQWRPERR_F, "PCI HMA channel count parity error", -1, 1 },
3781 { HREQPERR_F, "PCI HMA channel request parity error", -1, 1 },
3782 { HRSPPERR_F, "PCI HMA channel response parity error", -1, 1 },
3783 { CFGSNPPERR_F, "PCI config snoop FIFO parity error", -1, 1 },
3784 { FIDPERR_F, "PCI FID parity error", -1, 1 },
3785 { VFIDPERR_F, "PCI INTx clear parity error", -1, 1 },
3786 { MAGRPPERR_F, "PCI MA group FIFO parity error", -1, 1 },
3787 { PIOTAGPERR_F, "PCI PIO tag parity error", -1, 1 },
3788 { IPRXHDRGRPPERR_F, "PCI IP Rx header group parity error",
3790 { IPRXDATAGRPPERR_F, "PCI IP Rx data group parity error",
3792 { RPLPERR_F, "PCI IP replay buffer parity error", -1, 1 },
3793 { IPSOTPERR_F, "PCI IP SOT buffer parity error", -1, 1 },
3794 { TRGT1GRPPERR_F, "PCI TRGT1 group FIFOs parity error", -1, 1 },
3795 { READRSPERR_F, "Outbound read error", -1, 0 },
3801 if (is_t4(adapter->params.chip))
3802 fat = t4_handle_intr_status(adapter,
3803 PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS_A,
3805 t4_handle_intr_status(adapter,
3806 PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS_A,
3807 pcie_port_intr_info) +
3808 t4_handle_intr_status(adapter, PCIE_INT_CAUSE_A,
3811 fat = t4_handle_intr_status(adapter, PCIE_INT_CAUSE_A,
3815 t4_fatal_err(adapter);
3819 * TP interrupt handler.
3821 static void tp_intr_handler(struct adapter *adapter)
3823 static const struct intr_info tp_intr_info[] = {
3824 { 0x3fffffff, "TP parity error", -1, 1 },
3825 { FLMTXFLSTEMPTY_F, "TP out of Tx pages", -1, 1 },
3829 if (t4_handle_intr_status(adapter, TP_INT_CAUSE_A, tp_intr_info))
3830 t4_fatal_err(adapter);
3834 * SGE interrupt handler.
3836 static void sge_intr_handler(struct adapter *adapter)
3841 static const struct intr_info sge_intr_info[] = {
3842 { ERR_CPL_EXCEED_IQE_SIZE_F,
3843 "SGE received CPL exceeding IQE size", -1, 1 },
3844 { ERR_INVALID_CIDX_INC_F,
3845 "SGE GTS CIDX increment too large", -1, 0 },
3846 { ERR_CPL_OPCODE_0_F, "SGE received 0-length CPL", -1, 0 },
3847 { DBFIFO_LP_INT_F, NULL, -1, 0, t4_db_full },
3848 { ERR_DATA_CPL_ON_HIGH_QID1_F | ERR_DATA_CPL_ON_HIGH_QID0_F,
3849 "SGE IQID > 1023 received CPL for FL", -1, 0 },
3850 { ERR_BAD_DB_PIDX3_F, "SGE DBP 3 pidx increment too large", -1,
3852 { ERR_BAD_DB_PIDX2_F, "SGE DBP 2 pidx increment too large", -1,
3854 { ERR_BAD_DB_PIDX1_F, "SGE DBP 1 pidx increment too large", -1,
3856 { ERR_BAD_DB_PIDX0_F, "SGE DBP 0 pidx increment too large", -1,
3858 { ERR_ING_CTXT_PRIO_F,
3859 "SGE too many priority ingress contexts", -1, 0 },
3860 { INGRESS_SIZE_ERR_F, "SGE illegal ingress QID", -1, 0 },
3861 { EGRESS_SIZE_ERR_F, "SGE illegal egress QID", -1, 0 },
3865 static struct intr_info t4t5_sge_intr_info[] = {
3866 { ERR_DROPPED_DB_F, NULL, -1, 0, t4_db_dropped },
3867 { DBFIFO_HP_INT_F, NULL, -1, 0, t4_db_full },
3868 { ERR_EGR_CTXT_PRIO_F,
3869 "SGE too many priority egress contexts", -1, 0 },
3873 v = (u64)t4_read_reg(adapter, SGE_INT_CAUSE1_A) |
3874 ((u64)t4_read_reg(adapter, SGE_INT_CAUSE2_A) << 32);
3876 dev_alert(adapter->pdev_dev, "SGE parity error (%#llx)\n",
3877 (unsigned long long)v);
3878 t4_write_reg(adapter, SGE_INT_CAUSE1_A, v);
3879 t4_write_reg(adapter, SGE_INT_CAUSE2_A, v >> 32);
3882 v |= t4_handle_intr_status(adapter, SGE_INT_CAUSE3_A, sge_intr_info);
3883 if (CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5)
3884 v |= t4_handle_intr_status(adapter, SGE_INT_CAUSE3_A,
3885 t4t5_sge_intr_info);
3887 err = t4_read_reg(adapter, SGE_ERROR_STATS_A);
3888 if (err & ERROR_QID_VALID_F) {
3889 dev_err(adapter->pdev_dev, "SGE error for queue %u\n",
3891 if (err & UNCAPTURED_ERROR_F)
3892 dev_err(adapter->pdev_dev,
3893 "SGE UNCAPTURED_ERROR set (clearing)\n");
3894 t4_write_reg(adapter, SGE_ERROR_STATS_A, ERROR_QID_VALID_F |
3895 UNCAPTURED_ERROR_F);
3899 t4_fatal_err(adapter);
3902 #define CIM_OBQ_INTR (OBQULP0PARERR_F | OBQULP1PARERR_F | OBQULP2PARERR_F |\
3903 OBQULP3PARERR_F | OBQSGEPARERR_F | OBQNCSIPARERR_F)
3904 #define CIM_IBQ_INTR (IBQTP0PARERR_F | IBQTP1PARERR_F | IBQULPPARERR_F |\
3905 IBQSGEHIPARERR_F | IBQSGELOPARERR_F | IBQNCSIPARERR_F)
3908 * CIM interrupt handler.
3910 static void cim_intr_handler(struct adapter *adapter)
3912 static const struct intr_info cim_intr_info[] = {
3913 { PREFDROPINT_F, "CIM control register prefetch drop", -1, 1 },
3914 { CIM_OBQ_INTR, "CIM OBQ parity error", -1, 1 },
3915 { CIM_IBQ_INTR, "CIM IBQ parity error", -1, 1 },
3916 { MBUPPARERR_F, "CIM mailbox uP parity error", -1, 1 },
3917 { MBHOSTPARERR_F, "CIM mailbox host parity error", -1, 1 },
3918 { TIEQINPARERRINT_F, "CIM TIEQ outgoing parity error", -1, 1 },
3919 { TIEQOUTPARERRINT_F, "CIM TIEQ incoming parity error", -1, 1 },
3922 static const struct intr_info cim_upintr_info[] = {
3923 { RSVDSPACEINT_F, "CIM reserved space access", -1, 1 },
3924 { ILLTRANSINT_F, "CIM illegal transaction", -1, 1 },
3925 { ILLWRINT_F, "CIM illegal write", -1, 1 },
3926 { ILLRDINT_F, "CIM illegal read", -1, 1 },
3927 { ILLRDBEINT_F, "CIM illegal read BE", -1, 1 },
3928 { ILLWRBEINT_F, "CIM illegal write BE", -1, 1 },
3929 { SGLRDBOOTINT_F, "CIM single read from boot space", -1, 1 },
3930 { SGLWRBOOTINT_F, "CIM single write to boot space", -1, 1 },
3931 { BLKWRBOOTINT_F, "CIM block write to boot space", -1, 1 },
3932 { SGLRDFLASHINT_F, "CIM single read from flash space", -1, 1 },
3933 { SGLWRFLASHINT_F, "CIM single write to flash space", -1, 1 },
3934 { BLKWRFLASHINT_F, "CIM block write to flash space", -1, 1 },
3935 { SGLRDEEPROMINT_F, "CIM single EEPROM read", -1, 1 },
3936 { SGLWREEPROMINT_F, "CIM single EEPROM write", -1, 1 },
3937 { BLKRDEEPROMINT_F, "CIM block EEPROM read", -1, 1 },
3938 { BLKWREEPROMINT_F, "CIM block EEPROM write", -1, 1 },
3939 { SGLRDCTLINT_F, "CIM single read from CTL space", -1, 1 },
3940 { SGLWRCTLINT_F, "CIM single write to CTL space", -1, 1 },
3941 { BLKRDCTLINT_F, "CIM block read from CTL space", -1, 1 },
3942 { BLKWRCTLINT_F, "CIM block write to CTL space", -1, 1 },
3943 { SGLRDPLINT_F, "CIM single read from PL space", -1, 1 },
3944 { SGLWRPLINT_F, "CIM single write to PL space", -1, 1 },
3945 { BLKRDPLINT_F, "CIM block read from PL space", -1, 1 },
3946 { BLKWRPLINT_F, "CIM block write to PL space", -1, 1 },
3947 { REQOVRLOOKUPINT_F, "CIM request FIFO overwrite", -1, 1 },
3948 { RSPOVRLOOKUPINT_F, "CIM response FIFO overwrite", -1, 1 },
3949 { TIMEOUTINT_F, "CIM PIF timeout", -1, 1 },
3950 { TIMEOUTMAINT_F, "CIM PIF MA timeout", -1, 1 },
3956 if (t4_read_reg(adapter, PCIE_FW_A) & PCIE_FW_ERR_F)
3957 t4_report_fw_error(adapter);
3959 fat = t4_handle_intr_status(adapter, CIM_HOST_INT_CAUSE_A,
3961 t4_handle_intr_status(adapter, CIM_HOST_UPACC_INT_CAUSE_A,
3964 t4_fatal_err(adapter);
3968 * ULP RX interrupt handler.
3970 static void ulprx_intr_handler(struct adapter *adapter)
3972 static const struct intr_info ulprx_intr_info[] = {
3973 { 0x1800000, "ULPRX context error", -1, 1 },
3974 { 0x7fffff, "ULPRX parity error", -1, 1 },
3978 if (t4_handle_intr_status(adapter, ULP_RX_INT_CAUSE_A, ulprx_intr_info))
3979 t4_fatal_err(adapter);
3983 * ULP TX interrupt handler.
3985 static void ulptx_intr_handler(struct adapter *adapter)
3987 static const struct intr_info ulptx_intr_info[] = {
3988 { PBL_BOUND_ERR_CH3_F, "ULPTX channel 3 PBL out of bounds", -1,
3990 { PBL_BOUND_ERR_CH2_F, "ULPTX channel 2 PBL out of bounds", -1,
3992 { PBL_BOUND_ERR_CH1_F, "ULPTX channel 1 PBL out of bounds", -1,
3994 { PBL_BOUND_ERR_CH0_F, "ULPTX channel 0 PBL out of bounds", -1,
3996 { 0xfffffff, "ULPTX parity error", -1, 1 },
4000 if (t4_handle_intr_status(adapter, ULP_TX_INT_CAUSE_A, ulptx_intr_info))
4001 t4_fatal_err(adapter);
4005 * PM TX interrupt handler.
4007 static void pmtx_intr_handler(struct adapter *adapter)
4009 static const struct intr_info pmtx_intr_info[] = {
4010 { PCMD_LEN_OVFL0_F, "PMTX channel 0 pcmd too large", -1, 1 },
4011 { PCMD_LEN_OVFL1_F, "PMTX channel 1 pcmd too large", -1, 1 },
4012 { PCMD_LEN_OVFL2_F, "PMTX channel 2 pcmd too large", -1, 1 },
4013 { ZERO_C_CMD_ERROR_F, "PMTX 0-length pcmd", -1, 1 },
4014 { PMTX_FRAMING_ERROR_F, "PMTX framing error", -1, 1 },
4015 { OESPI_PAR_ERROR_F, "PMTX oespi parity error", -1, 1 },
4016 { DB_OPTIONS_PAR_ERROR_F, "PMTX db_options parity error",
4018 { ICSPI_PAR_ERROR_F, "PMTX icspi parity error", -1, 1 },
4019 { PMTX_C_PCMD_PAR_ERROR_F, "PMTX c_pcmd parity error", -1, 1},
4023 if (t4_handle_intr_status(adapter, PM_TX_INT_CAUSE_A, pmtx_intr_info))
4024 t4_fatal_err(adapter);
4028 * PM RX interrupt handler.
4030 static void pmrx_intr_handler(struct adapter *adapter)
4032 static const struct intr_info pmrx_intr_info[] = {
4033 { ZERO_E_CMD_ERROR_F, "PMRX 0-length pcmd", -1, 1 },
4034 { PMRX_FRAMING_ERROR_F, "PMRX framing error", -1, 1 },
4035 { OCSPI_PAR_ERROR_F, "PMRX ocspi parity error", -1, 1 },
4036 { DB_OPTIONS_PAR_ERROR_F, "PMRX db_options parity error",
4038 { IESPI_PAR_ERROR_F, "PMRX iespi parity error", -1, 1 },
4039 { PMRX_E_PCMD_PAR_ERROR_F, "PMRX e_pcmd parity error", -1, 1},
4043 if (t4_handle_intr_status(adapter, PM_RX_INT_CAUSE_A, pmrx_intr_info))
4044 t4_fatal_err(adapter);
4048 * CPL switch interrupt handler.
4050 static void cplsw_intr_handler(struct adapter *adapter)
4052 static const struct intr_info cplsw_intr_info[] = {
4053 { CIM_OP_MAP_PERR_F, "CPLSW CIM op_map parity error", -1, 1 },
4054 { CIM_OVFL_ERROR_F, "CPLSW CIM overflow", -1, 1 },
4055 { TP_FRAMING_ERROR_F, "CPLSW TP framing error", -1, 1 },
4056 { SGE_FRAMING_ERROR_F, "CPLSW SGE framing error", -1, 1 },
4057 { CIM_FRAMING_ERROR_F, "CPLSW CIM framing error", -1, 1 },
4058 { ZERO_SWITCH_ERROR_F, "CPLSW no-switch error", -1, 1 },
4062 if (t4_handle_intr_status(adapter, CPL_INTR_CAUSE_A, cplsw_intr_info))
4063 t4_fatal_err(adapter);
4067 * LE interrupt handler.
4069 static void le_intr_handler(struct adapter *adap)
4071 enum chip_type chip = CHELSIO_CHIP_VERSION(adap->params.chip);
4072 static const struct intr_info le_intr_info[] = {
4073 { LIPMISS_F, "LE LIP miss", -1, 0 },
4074 { LIP0_F, "LE 0 LIP error", -1, 0 },
4075 { PARITYERR_F, "LE parity error", -1, 1 },
4076 { UNKNOWNCMD_F, "LE unknown command", -1, 1 },
4077 { REQQPARERR_F, "LE request queue parity error", -1, 1 },
4081 static struct intr_info t6_le_intr_info[] = {
4082 { T6_LIPMISS_F, "LE LIP miss", -1, 0 },
4083 { T6_LIP0_F, "LE 0 LIP error", -1, 0 },
4084 { TCAMINTPERR_F, "LE parity error", -1, 1 },
4085 { T6_UNKNOWNCMD_F, "LE unknown command", -1, 1 },
4086 { SSRAMINTPERR_F, "LE request queue parity error", -1, 1 },
4090 if (t4_handle_intr_status(adap, LE_DB_INT_CAUSE_A,
4091 (chip <= CHELSIO_T5) ?
4092 le_intr_info : t6_le_intr_info))
4097 * MPS interrupt handler.
4099 static void mps_intr_handler(struct adapter *adapter)
4101 static const struct intr_info mps_rx_intr_info[] = {
4102 { 0xffffff, "MPS Rx parity error", -1, 1 },
4105 static const struct intr_info mps_tx_intr_info[] = {
4106 { TPFIFO_V(TPFIFO_M), "MPS Tx TP FIFO parity error", -1, 1 },
4107 { NCSIFIFO_F, "MPS Tx NC-SI FIFO parity error", -1, 1 },
4108 { TXDATAFIFO_V(TXDATAFIFO_M), "MPS Tx data FIFO parity error",
4110 { TXDESCFIFO_V(TXDESCFIFO_M), "MPS Tx desc FIFO parity error",
4112 { BUBBLE_F, "MPS Tx underflow", -1, 1 },
4113 { SECNTERR_F, "MPS Tx SOP/EOP error", -1, 1 },
4114 { FRMERR_F, "MPS Tx framing error", -1, 1 },
4117 static const struct intr_info mps_trc_intr_info[] = {
4118 { FILTMEM_V(FILTMEM_M), "MPS TRC filter parity error", -1, 1 },
4119 { PKTFIFO_V(PKTFIFO_M), "MPS TRC packet FIFO parity error",
4121 { MISCPERR_F, "MPS TRC misc parity error", -1, 1 },
4124 static const struct intr_info mps_stat_sram_intr_info[] = {
4125 { 0x1fffff, "MPS statistics SRAM parity error", -1, 1 },
4128 static const struct intr_info mps_stat_tx_intr_info[] = {
4129 { 0xfffff, "MPS statistics Tx FIFO parity error", -1, 1 },
4132 static const struct intr_info mps_stat_rx_intr_info[] = {
4133 { 0xffffff, "MPS statistics Rx FIFO parity error", -1, 1 },
4136 static const struct intr_info mps_cls_intr_info[] = {
4137 { MATCHSRAM_F, "MPS match SRAM parity error", -1, 1 },
4138 { MATCHTCAM_F, "MPS match TCAM parity error", -1, 1 },
4139 { HASHSRAM_F, "MPS hash SRAM parity error", -1, 1 },
4145 fat = t4_handle_intr_status(adapter, MPS_RX_PERR_INT_CAUSE_A,
4147 t4_handle_intr_status(adapter, MPS_TX_INT_CAUSE_A,
4149 t4_handle_intr_status(adapter, MPS_TRC_INT_CAUSE_A,
4150 mps_trc_intr_info) +
4151 t4_handle_intr_status(adapter, MPS_STAT_PERR_INT_CAUSE_SRAM_A,
4152 mps_stat_sram_intr_info) +
4153 t4_handle_intr_status(adapter, MPS_STAT_PERR_INT_CAUSE_TX_FIFO_A,
4154 mps_stat_tx_intr_info) +
4155 t4_handle_intr_status(adapter, MPS_STAT_PERR_INT_CAUSE_RX_FIFO_A,
4156 mps_stat_rx_intr_info) +
4157 t4_handle_intr_status(adapter, MPS_CLS_INT_CAUSE_A,
4160 t4_write_reg(adapter, MPS_INT_CAUSE_A, 0);
4161 t4_read_reg(adapter, MPS_INT_CAUSE_A); /* flush */
4163 t4_fatal_err(adapter);
4166 #define MEM_INT_MASK (PERR_INT_CAUSE_F | ECC_CE_INT_CAUSE_F | \
4170 * EDC/MC interrupt handler.
4172 static void mem_intr_handler(struct adapter *adapter, int idx)
4174 static const char name[4][7] = { "EDC0", "EDC1", "MC/MC0", "MC1" };
4176 unsigned int addr, cnt_addr, v;
4178 if (idx <= MEM_EDC1) {
4179 addr = EDC_REG(EDC_INT_CAUSE_A, idx);
4180 cnt_addr = EDC_REG(EDC_ECC_STATUS_A, idx);
4181 } else if (idx == MEM_MC) {
4182 if (is_t4(adapter->params.chip)) {
4183 addr = MC_INT_CAUSE_A;
4184 cnt_addr = MC_ECC_STATUS_A;
4186 addr = MC_P_INT_CAUSE_A;
4187 cnt_addr = MC_P_ECC_STATUS_A;
4190 addr = MC_REG(MC_P_INT_CAUSE_A, 1);
4191 cnt_addr = MC_REG(MC_P_ECC_STATUS_A, 1);
4194 v = t4_read_reg(adapter, addr) & MEM_INT_MASK;
4195 if (v & PERR_INT_CAUSE_F)
4196 dev_alert(adapter->pdev_dev, "%s FIFO parity error\n",
4198 if (v & ECC_CE_INT_CAUSE_F) {
4199 u32 cnt = ECC_CECNT_G(t4_read_reg(adapter, cnt_addr));
4201 t4_edc_err_read(adapter, idx);
4203 t4_write_reg(adapter, cnt_addr, ECC_CECNT_V(ECC_CECNT_M));
4204 if (printk_ratelimit())
4205 dev_warn(adapter->pdev_dev,
4206 "%u %s correctable ECC data error%s\n",
4207 cnt, name[idx], cnt > 1 ? "s" : "");
4209 if (v & ECC_UE_INT_CAUSE_F)
4210 dev_alert(adapter->pdev_dev,
4211 "%s uncorrectable ECC data error\n", name[idx]);
4213 t4_write_reg(adapter, addr, v);
4214 if (v & (PERR_INT_CAUSE_F | ECC_UE_INT_CAUSE_F))
4215 t4_fatal_err(adapter);
4219 * MA interrupt handler.
4221 static void ma_intr_handler(struct adapter *adap)
4223 u32 v, status = t4_read_reg(adap, MA_INT_CAUSE_A);
4225 if (status & MEM_PERR_INT_CAUSE_F) {
4226 dev_alert(adap->pdev_dev,
4227 "MA parity error, parity status %#x\n",
4228 t4_read_reg(adap, MA_PARITY_ERROR_STATUS1_A));
4229 if (is_t5(adap->params.chip))
4230 dev_alert(adap->pdev_dev,
4231 "MA parity error, parity status %#x\n",
4233 MA_PARITY_ERROR_STATUS2_A));
4235 if (status & MEM_WRAP_INT_CAUSE_F) {
4236 v = t4_read_reg(adap, MA_INT_WRAP_STATUS_A);
4237 dev_alert(adap->pdev_dev, "MA address wrap-around error by "
4238 "client %u to address %#x\n",
4239 MEM_WRAP_CLIENT_NUM_G(v),
4240 MEM_WRAP_ADDRESS_G(v) << 4);
4242 t4_write_reg(adap, MA_INT_CAUSE_A, status);
4247 * SMB interrupt handler.
4249 static void smb_intr_handler(struct adapter *adap)
4251 static const struct intr_info smb_intr_info[] = {
4252 { MSTTXFIFOPARINT_F, "SMB master Tx FIFO parity error", -1, 1 },
4253 { MSTRXFIFOPARINT_F, "SMB master Rx FIFO parity error", -1, 1 },
4254 { SLVFIFOPARINT_F, "SMB slave FIFO parity error", -1, 1 },
4258 if (t4_handle_intr_status(adap, SMB_INT_CAUSE_A, smb_intr_info))
4263 * NC-SI interrupt handler.
4265 static void ncsi_intr_handler(struct adapter *adap)
4267 static const struct intr_info ncsi_intr_info[] = {
4268 { CIM_DM_PRTY_ERR_F, "NC-SI CIM parity error", -1, 1 },
4269 { MPS_DM_PRTY_ERR_F, "NC-SI MPS parity error", -1, 1 },
4270 { TXFIFO_PRTY_ERR_F, "NC-SI Tx FIFO parity error", -1, 1 },
4271 { RXFIFO_PRTY_ERR_F, "NC-SI Rx FIFO parity error", -1, 1 },
4275 if (t4_handle_intr_status(adap, NCSI_INT_CAUSE_A, ncsi_intr_info))
4280 * XGMAC interrupt handler.
4282 static void xgmac_intr_handler(struct adapter *adap, int port)
4284 u32 v, int_cause_reg;
4286 if (is_t4(adap->params.chip))
4287 int_cause_reg = PORT_REG(port, XGMAC_PORT_INT_CAUSE_A);
4289 int_cause_reg = T5_PORT_REG(port, MAC_PORT_INT_CAUSE_A);
4291 v = t4_read_reg(adap, int_cause_reg);
4293 v &= TXFIFO_PRTY_ERR_F | RXFIFO_PRTY_ERR_F;
4297 if (v & TXFIFO_PRTY_ERR_F)
4298 dev_alert(adap->pdev_dev, "XGMAC %d Tx FIFO parity error\n",
4300 if (v & RXFIFO_PRTY_ERR_F)
4301 dev_alert(adap->pdev_dev, "XGMAC %d Rx FIFO parity error\n",
4303 t4_write_reg(adap, PORT_REG(port, XGMAC_PORT_INT_CAUSE_A), v);
4308 * PL interrupt handler.
4310 static void pl_intr_handler(struct adapter *adap)
4312 static const struct intr_info pl_intr_info[] = {
4313 { FATALPERR_F, "T4 fatal parity error", -1, 1 },
4314 { PERRVFID_F, "PL VFID_MAP parity error", -1, 1 },
4318 if (t4_handle_intr_status(adap, PL_PL_INT_CAUSE_A, pl_intr_info))
4322 #define PF_INTR_MASK (PFSW_F)
4323 #define GLBL_INTR_MASK (CIM_F | MPS_F | PL_F | PCIE_F | MC_F | EDC0_F | \
4324 EDC1_F | LE_F | TP_F | MA_F | PM_TX_F | PM_RX_F | ULP_RX_F | \
4325 CPL_SWITCH_F | SGE_F | ULP_TX_F)
4328 * t4_slow_intr_handler - control path interrupt handler
4329 * @adapter: the adapter
4331 * T4 interrupt handler for non-data global interrupt events, e.g., errors.
4332 * The designation 'slow' is because it involves register reads, while
4333 * data interrupts typically don't involve any MMIOs.
4335 int t4_slow_intr_handler(struct adapter *adapter)
4337 u32 cause = t4_read_reg(adapter, PL_INT_CAUSE_A);
4339 if (!(cause & GLBL_INTR_MASK))
4342 cim_intr_handler(adapter);
4344 mps_intr_handler(adapter);
4346 ncsi_intr_handler(adapter);
4348 pl_intr_handler(adapter);
4350 smb_intr_handler(adapter);
4351 if (cause & XGMAC0_F)
4352 xgmac_intr_handler(adapter, 0);
4353 if (cause & XGMAC1_F)
4354 xgmac_intr_handler(adapter, 1);
4355 if (cause & XGMAC_KR0_F)
4356 xgmac_intr_handler(adapter, 2);
4357 if (cause & XGMAC_KR1_F)
4358 xgmac_intr_handler(adapter, 3);
4360 pcie_intr_handler(adapter);
4362 mem_intr_handler(adapter, MEM_MC);
4363 if (is_t5(adapter->params.chip) && (cause & MC1_F))
4364 mem_intr_handler(adapter, MEM_MC1);
4366 mem_intr_handler(adapter, MEM_EDC0);
4368 mem_intr_handler(adapter, MEM_EDC1);
4370 le_intr_handler(adapter);
4372 tp_intr_handler(adapter);
4374 ma_intr_handler(adapter);
4375 if (cause & PM_TX_F)
4376 pmtx_intr_handler(adapter);
4377 if (cause & PM_RX_F)
4378 pmrx_intr_handler(adapter);
4379 if (cause & ULP_RX_F)
4380 ulprx_intr_handler(adapter);
4381 if (cause & CPL_SWITCH_F)
4382 cplsw_intr_handler(adapter);
4384 sge_intr_handler(adapter);
4385 if (cause & ULP_TX_F)
4386 ulptx_intr_handler(adapter);
4388 /* Clear the interrupts just processed for which we are the master. */
4389 t4_write_reg(adapter, PL_INT_CAUSE_A, cause & GLBL_INTR_MASK);
4390 (void)t4_read_reg(adapter, PL_INT_CAUSE_A); /* flush */
4395 * t4_intr_enable - enable interrupts
4396 * @adapter: the adapter whose interrupts should be enabled
4398 * Enable PF-specific interrupts for the calling function and the top-level
4399 * interrupt concentrator for global interrupts. Interrupts are already
4400 * enabled at each module, here we just enable the roots of the interrupt
4403 * Note: this function should be called only when the driver manages
4404 * non PF-specific interrupts from the various HW modules. Only one PCI
4405 * function at a time should be doing this.
4407 void t4_intr_enable(struct adapter *adapter)
4410 u32 whoami = t4_read_reg(adapter, PL_WHOAMI_A);
4411 u32 pf = CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5 ?
4412 SOURCEPF_G(whoami) : T6_SOURCEPF_G(whoami);
4414 if (CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5)
4415 val = ERR_DROPPED_DB_F | ERR_EGR_CTXT_PRIO_F | DBFIFO_HP_INT_F;
4416 t4_write_reg(adapter, SGE_INT_ENABLE3_A, ERR_CPL_EXCEED_IQE_SIZE_F |
4417 ERR_INVALID_CIDX_INC_F | ERR_CPL_OPCODE_0_F |
4418 ERR_DATA_CPL_ON_HIGH_QID1_F | INGRESS_SIZE_ERR_F |
4419 ERR_DATA_CPL_ON_HIGH_QID0_F | ERR_BAD_DB_PIDX3_F |
4420 ERR_BAD_DB_PIDX2_F | ERR_BAD_DB_PIDX1_F |
4421 ERR_BAD_DB_PIDX0_F | ERR_ING_CTXT_PRIO_F |
4422 DBFIFO_LP_INT_F | EGRESS_SIZE_ERR_F | val);
4423 t4_write_reg(adapter, MYPF_REG(PL_PF_INT_ENABLE_A), PF_INTR_MASK);
4424 t4_set_reg_field(adapter, PL_INT_MAP0_A, 0, 1 << pf);
4428 * t4_intr_disable - disable interrupts
4429 * @adapter: the adapter whose interrupts should be disabled
4431 * Disable interrupts. We only disable the top-level interrupt
4432 * concentrators. The caller must be a PCI function managing global
4435 void t4_intr_disable(struct adapter *adapter)
4437 u32 whoami = t4_read_reg(adapter, PL_WHOAMI_A);
4438 u32 pf = CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5 ?
4439 SOURCEPF_G(whoami) : T6_SOURCEPF_G(whoami);
4441 t4_write_reg(adapter, MYPF_REG(PL_PF_INT_ENABLE_A), 0);
4442 t4_set_reg_field(adapter, PL_INT_MAP0_A, 1 << pf, 0);
4446 * t4_config_rss_range - configure a portion of the RSS mapping table
4447 * @adapter: the adapter
4448 * @mbox: mbox to use for the FW command
4449 * @viid: virtual interface whose RSS subtable is to be written
4450 * @start: start entry in the table to write
4451 * @n: how many table entries to write
4452 * @rspq: values for the response queue lookup table
4453 * @nrspq: number of values in @rspq
4455 * Programs the selected part of the VI's RSS mapping table with the
4456 * provided values. If @nrspq < @n the supplied values are used repeatedly
4457 * until the full table range is populated.
4459 * The caller must ensure the values in @rspq are in the range allowed for
4462 int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid,
4463 int start, int n, const u16 *rspq, unsigned int nrspq)
4466 const u16 *rsp = rspq;
4467 const u16 *rsp_end = rspq + nrspq;
4468 struct fw_rss_ind_tbl_cmd cmd;
4470 memset(&cmd, 0, sizeof(cmd));
4471 cmd.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_RSS_IND_TBL_CMD) |
4472 FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
4473 FW_RSS_IND_TBL_CMD_VIID_V(viid));
4474 cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd));
4476 /* each fw_rss_ind_tbl_cmd takes up to 32 entries */
4478 int nq = min(n, 32);
4479 __be32 *qp = &cmd.iq0_to_iq2;
4481 cmd.niqid = cpu_to_be16(nq);
4482 cmd.startidx = cpu_to_be16(start);
4490 v = FW_RSS_IND_TBL_CMD_IQ0_V(*rsp);
4491 if (++rsp >= rsp_end)
4493 v |= FW_RSS_IND_TBL_CMD_IQ1_V(*rsp);
4494 if (++rsp >= rsp_end)
4496 v |= FW_RSS_IND_TBL_CMD_IQ2_V(*rsp);
4497 if (++rsp >= rsp_end)
4500 *qp++ = cpu_to_be32(v);
4504 ret = t4_wr_mbox(adapter, mbox, &cmd, sizeof(cmd), NULL);
4512 * t4_config_glbl_rss - configure the global RSS mode
4513 * @adapter: the adapter
4514 * @mbox: mbox to use for the FW command
4515 * @mode: global RSS mode
4516 * @flags: mode-specific flags
4518 * Sets the global RSS mode.
4520 int t4_config_glbl_rss(struct adapter *adapter, int mbox, unsigned int mode,
4523 struct fw_rss_glb_config_cmd c;
4525 memset(&c, 0, sizeof(c));
4526 c.op_to_write = cpu_to_be32(FW_CMD_OP_V(FW_RSS_GLB_CONFIG_CMD) |
4527 FW_CMD_REQUEST_F | FW_CMD_WRITE_F);
4528 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
4529 if (mode == FW_RSS_GLB_CONFIG_CMD_MODE_MANUAL) {
4530 c.u.manual.mode_pkd =
4531 cpu_to_be32(FW_RSS_GLB_CONFIG_CMD_MODE_V(mode));
4532 } else if (mode == FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL) {
4533 c.u.basicvirtual.mode_pkd =
4534 cpu_to_be32(FW_RSS_GLB_CONFIG_CMD_MODE_V(mode));
4535 c.u.basicvirtual.synmapen_to_hashtoeplitz = cpu_to_be32(flags);
4538 return t4_wr_mbox(adapter, mbox, &c, sizeof(c), NULL);
4542 * t4_config_vi_rss - configure per VI RSS settings
4543 * @adapter: the adapter
4544 * @mbox: mbox to use for the FW command
4547 * @defq: id of the default RSS queue for the VI.
4549 * Configures VI-specific RSS properties.
4551 int t4_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid,
4552 unsigned int flags, unsigned int defq)
4554 struct fw_rss_vi_config_cmd c;
4556 memset(&c, 0, sizeof(c));
4557 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_RSS_VI_CONFIG_CMD) |
4558 FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
4559 FW_RSS_VI_CONFIG_CMD_VIID_V(viid));
4560 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
4561 c.u.basicvirtual.defaultq_to_udpen = cpu_to_be32(flags |
4562 FW_RSS_VI_CONFIG_CMD_DEFAULTQ_V(defq));
4563 return t4_wr_mbox(adapter, mbox, &c, sizeof(c), NULL);
4566 /* Read an RSS table row */
4567 static int rd_rss_row(struct adapter *adap, int row, u32 *val)
4569 t4_write_reg(adap, TP_RSS_LKP_TABLE_A, 0xfff00000 | row);
4570 return t4_wait_op_done_val(adap, TP_RSS_LKP_TABLE_A, LKPTBLROWVLD_F, 1,
4575 * t4_read_rss - read the contents of the RSS mapping table
4576 * @adapter: the adapter
4577 * @map: holds the contents of the RSS mapping table
4579 * Reads the contents of the RSS hash->queue mapping table.
4581 int t4_read_rss(struct adapter *adapter, u16 *map)
4586 for (i = 0; i < RSS_NENTRIES / 2; ++i) {
4587 ret = rd_rss_row(adapter, i, &val);
4590 *map++ = LKPTBLQUEUE0_G(val);
4591 *map++ = LKPTBLQUEUE1_G(val);
4596 static unsigned int t4_use_ldst(struct adapter *adap)
4598 return (adap->flags & FW_OK) || !adap->use_bd;
4602 * t4_fw_tp_pio_rw - Access TP PIO through LDST
4603 * @adap: the adapter
4604 * @vals: where the indirect register values are stored/written
4605 * @nregs: how many indirect registers to read/write
4606 * @start_idx: index of first indirect register to read/write
4607 * @rw: Read (1) or Write (0)
4609 * Access TP PIO registers through LDST
4611 static void t4_fw_tp_pio_rw(struct adapter *adap, u32 *vals, unsigned int nregs,
4612 unsigned int start_index, unsigned int rw)
4615 int cmd = FW_LDST_ADDRSPC_TP_PIO;
4616 struct fw_ldst_cmd c;
4618 for (i = 0 ; i < nregs; i++) {
4619 memset(&c, 0, sizeof(c));
4620 c.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
4622 (rw ? FW_CMD_READ_F :
4624 FW_LDST_CMD_ADDRSPACE_V(cmd));
4625 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
4627 c.u.addrval.addr = cpu_to_be32(start_index + i);
4628 c.u.addrval.val = rw ? 0 : cpu_to_be32(vals[i]);
4629 ret = t4_wr_mbox(adap, adap->mbox, &c, sizeof(c), &c);
4631 vals[i] = be32_to_cpu(c.u.addrval.val);
4636 * t4_read_rss_key - read the global RSS key
4637 * @adap: the adapter
4638 * @key: 10-entry array holding the 320-bit RSS key
4640 * Reads the global 320-bit RSS key.
4642 void t4_read_rss_key(struct adapter *adap, u32 *key)
4644 if (t4_use_ldst(adap))
4645 t4_fw_tp_pio_rw(adap, key, 10, TP_RSS_SECRET_KEY0_A, 1);
4647 t4_read_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A, key, 10,
4648 TP_RSS_SECRET_KEY0_A);
4652 * t4_write_rss_key - program one of the RSS keys
4653 * @adap: the adapter
4654 * @key: 10-entry array holding the 320-bit RSS key
4655 * @idx: which RSS key to write
4657 * Writes one of the RSS keys with the given 320-bit value. If @idx is
4658 * 0..15 the corresponding entry in the RSS key table is written,
4659 * otherwise the global RSS key is written.
4661 void t4_write_rss_key(struct adapter *adap, const u32 *key, int idx)
4663 u8 rss_key_addr_cnt = 16;
4664 u32 vrt = t4_read_reg(adap, TP_RSS_CONFIG_VRT_A);
4666 /* T6 and later: for KeyMode 3 (per-vf and per-vf scramble),
4667 * allows access to key addresses 16-63 by using KeyWrAddrX
4668 * as index[5:4](upper 2) into key table
4670 if ((CHELSIO_CHIP_VERSION(adap->params.chip) > CHELSIO_T5) &&
4671 (vrt & KEYEXTEND_F) && (KEYMODE_G(vrt) == 3))
4672 rss_key_addr_cnt = 32;
4674 if (t4_use_ldst(adap))
4675 t4_fw_tp_pio_rw(adap, (void *)key, 10, TP_RSS_SECRET_KEY0_A, 0);
4677 t4_write_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A, key, 10,
4678 TP_RSS_SECRET_KEY0_A);
4680 if (idx >= 0 && idx < rss_key_addr_cnt) {
4681 if (rss_key_addr_cnt > 16)
4682 t4_write_reg(adap, TP_RSS_CONFIG_VRT_A,
4683 KEYWRADDRX_V(idx >> 4) |
4684 T6_VFWRADDR_V(idx) | KEYWREN_F);
4686 t4_write_reg(adap, TP_RSS_CONFIG_VRT_A,
4687 KEYWRADDR_V(idx) | KEYWREN_F);
4692 * t4_read_rss_pf_config - read PF RSS Configuration Table
4693 * @adapter: the adapter
4694 * @index: the entry in the PF RSS table to read
4695 * @valp: where to store the returned value
4697 * Reads the PF RSS Configuration Table at the specified index and returns
4698 * the value found there.
4700 void t4_read_rss_pf_config(struct adapter *adapter, unsigned int index,
4703 if (t4_use_ldst(adapter))
4704 t4_fw_tp_pio_rw(adapter, valp, 1,
4705 TP_RSS_PF0_CONFIG_A + index, 1);
4707 t4_read_indirect(adapter, TP_PIO_ADDR_A, TP_PIO_DATA_A,
4708 valp, 1, TP_RSS_PF0_CONFIG_A + index);
4712 * t4_read_rss_vf_config - read VF RSS Configuration Table
4713 * @adapter: the adapter
4714 * @index: the entry in the VF RSS table to read
4715 * @vfl: where to store the returned VFL
4716 * @vfh: where to store the returned VFH
4718 * Reads the VF RSS Configuration Table at the specified index and returns
4719 * the (VFL, VFH) values found there.
4721 void t4_read_rss_vf_config(struct adapter *adapter, unsigned int index,
4724 u32 vrt, mask, data;
4726 if (CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5) {
4727 mask = VFWRADDR_V(VFWRADDR_M);
4728 data = VFWRADDR_V(index);
4730 mask = T6_VFWRADDR_V(T6_VFWRADDR_M);
4731 data = T6_VFWRADDR_V(index);
4734 /* Request that the index'th VF Table values be read into VFL/VFH.
4736 vrt = t4_read_reg(adapter, TP_RSS_CONFIG_VRT_A);
4737 vrt &= ~(VFRDRG_F | VFWREN_F | KEYWREN_F | mask);
4738 vrt |= data | VFRDEN_F;
4739 t4_write_reg(adapter, TP_RSS_CONFIG_VRT_A, vrt);
4741 /* Grab the VFL/VFH values ...
4743 if (t4_use_ldst(adapter)) {
4744 t4_fw_tp_pio_rw(adapter, vfl, 1, TP_RSS_VFL_CONFIG_A, 1);
4745 t4_fw_tp_pio_rw(adapter, vfh, 1, TP_RSS_VFH_CONFIG_A, 1);
4747 t4_read_indirect(adapter, TP_PIO_ADDR_A, TP_PIO_DATA_A,
4748 vfl, 1, TP_RSS_VFL_CONFIG_A);
4749 t4_read_indirect(adapter, TP_PIO_ADDR_A, TP_PIO_DATA_A,
4750 vfh, 1, TP_RSS_VFH_CONFIG_A);
4755 * t4_read_rss_pf_map - read PF RSS Map
4756 * @adapter: the adapter
4758 * Reads the PF RSS Map register and returns its value.
4760 u32 t4_read_rss_pf_map(struct adapter *adapter)
4764 if (t4_use_ldst(adapter))
4765 t4_fw_tp_pio_rw(adapter, &pfmap, 1, TP_RSS_PF_MAP_A, 1);
4767 t4_read_indirect(adapter, TP_PIO_ADDR_A, TP_PIO_DATA_A,
4768 &pfmap, 1, TP_RSS_PF_MAP_A);
4773 * t4_read_rss_pf_mask - read PF RSS Mask
4774 * @adapter: the adapter
4776 * Reads the PF RSS Mask register and returns its value.
4778 u32 t4_read_rss_pf_mask(struct adapter *adapter)
4782 if (t4_use_ldst(adapter))
4783 t4_fw_tp_pio_rw(adapter, &pfmask, 1, TP_RSS_PF_MSK_A, 1);
4785 t4_read_indirect(adapter, TP_PIO_ADDR_A, TP_PIO_DATA_A,
4786 &pfmask, 1, TP_RSS_PF_MSK_A);
4791 * t4_tp_get_tcp_stats - read TP's TCP MIB counters
4792 * @adap: the adapter
4793 * @v4: holds the TCP/IP counter values
4794 * @v6: holds the TCP/IPv6 counter values
4796 * Returns the values of TP's TCP/IP and TCP/IPv6 MIB counters.
4797 * Either @v4 or @v6 may be %NULL to skip the corresponding stats.
4799 void t4_tp_get_tcp_stats(struct adapter *adap, struct tp_tcp_stats *v4,
4800 struct tp_tcp_stats *v6)
4802 u32 val[TP_MIB_TCP_RXT_SEG_LO_A - TP_MIB_TCP_OUT_RST_A + 1];
4804 #define STAT_IDX(x) ((TP_MIB_TCP_##x##_A) - TP_MIB_TCP_OUT_RST_A)
4805 #define STAT(x) val[STAT_IDX(x)]
4806 #define STAT64(x) (((u64)STAT(x##_HI) << 32) | STAT(x##_LO))
4809 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, val,
4810 ARRAY_SIZE(val), TP_MIB_TCP_OUT_RST_A);
4811 v4->tcp_out_rsts = STAT(OUT_RST);
4812 v4->tcp_in_segs = STAT64(IN_SEG);
4813 v4->tcp_out_segs = STAT64(OUT_SEG);
4814 v4->tcp_retrans_segs = STAT64(RXT_SEG);
4817 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, val,
4818 ARRAY_SIZE(val), TP_MIB_TCP_V6OUT_RST_A);
4819 v6->tcp_out_rsts = STAT(OUT_RST);
4820 v6->tcp_in_segs = STAT64(IN_SEG);
4821 v6->tcp_out_segs = STAT64(OUT_SEG);
4822 v6->tcp_retrans_segs = STAT64(RXT_SEG);
4830 * t4_tp_get_err_stats - read TP's error MIB counters
4831 * @adap: the adapter
4832 * @st: holds the counter values
4834 * Returns the values of TP's error counters.
4836 void t4_tp_get_err_stats(struct adapter *adap, struct tp_err_stats *st)
4838 int nchan = adap->params.arch.nchan;
4840 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A,
4841 st->mac_in_errs, nchan, TP_MIB_MAC_IN_ERR_0_A);
4842 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A,
4843 st->hdr_in_errs, nchan, TP_MIB_HDR_IN_ERR_0_A);
4844 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A,
4845 st->tcp_in_errs, nchan, TP_MIB_TCP_IN_ERR_0_A);
4846 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A,
4847 st->tnl_cong_drops, nchan, TP_MIB_TNL_CNG_DROP_0_A);
4848 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A,
4849 st->ofld_chan_drops, nchan, TP_MIB_OFD_CHN_DROP_0_A);
4850 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A,
4851 st->tnl_tx_drops, nchan, TP_MIB_TNL_DROP_0_A);
4852 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A,
4853 st->ofld_vlan_drops, nchan, TP_MIB_OFD_VLN_DROP_0_A);
4854 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A,
4855 st->tcp6_in_errs, nchan, TP_MIB_TCP_V6IN_ERR_0_A);
4857 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A,
4858 &st->ofld_no_neigh, 2, TP_MIB_OFD_ARP_DROP_A);
4862 * t4_tp_get_cpl_stats - read TP's CPL MIB counters
4863 * @adap: the adapter
4864 * @st: holds the counter values
4866 * Returns the values of TP's CPL counters.
4868 void t4_tp_get_cpl_stats(struct adapter *adap, struct tp_cpl_stats *st)
4870 int nchan = adap->params.arch.nchan;
4872 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, st->req,
4873 nchan, TP_MIB_CPL_IN_REQ_0_A);
4874 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, st->rsp,
4875 nchan, TP_MIB_CPL_OUT_RSP_0_A);
4880 * t4_tp_get_rdma_stats - read TP's RDMA MIB counters
4881 * @adap: the adapter
4882 * @st: holds the counter values
4884 * Returns the values of TP's RDMA counters.
4886 void t4_tp_get_rdma_stats(struct adapter *adap, struct tp_rdma_stats *st)
4888 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, &st->rqe_dfr_pkt,
4889 2, TP_MIB_RQE_DFR_PKT_A);
4893 * t4_get_fcoe_stats - read TP's FCoE MIB counters for a port
4894 * @adap: the adapter
4895 * @idx: the port index
4896 * @st: holds the counter values
4898 * Returns the values of TP's FCoE counters for the selected port.
4900 void t4_get_fcoe_stats(struct adapter *adap, unsigned int idx,
4901 struct tp_fcoe_stats *st)
4905 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, &st->frames_ddp,
4906 1, TP_MIB_FCOE_DDP_0_A + idx);
4907 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, &st->frames_drop,
4908 1, TP_MIB_FCOE_DROP_0_A + idx);
4909 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, val,
4910 2, TP_MIB_FCOE_BYTE_0_HI_A + 2 * idx);
4911 st->octets_ddp = ((u64)val[0] << 32) | val[1];
4915 * t4_get_usm_stats - read TP's non-TCP DDP MIB counters
4916 * @adap: the adapter
4917 * @st: holds the counter values
4919 * Returns the values of TP's counters for non-TCP directly-placed packets.
4921 void t4_get_usm_stats(struct adapter *adap, struct tp_usm_stats *st)
4925 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, val, 4,
4927 st->frames = val[0];
4929 st->octets = ((u64)val[2] << 32) | val[3];
4933 * t4_read_mtu_tbl - returns the values in the HW path MTU table
4934 * @adap: the adapter
4935 * @mtus: where to store the MTU values
4936 * @mtu_log: where to store the MTU base-2 log (may be %NULL)
4938 * Reads the HW path MTU table.
4940 void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log)
4945 for (i = 0; i < NMTUS; ++i) {
4946 t4_write_reg(adap, TP_MTU_TABLE_A,
4947 MTUINDEX_V(0xff) | MTUVALUE_V(i));
4948 v = t4_read_reg(adap, TP_MTU_TABLE_A);
4949 mtus[i] = MTUVALUE_G(v);
4951 mtu_log[i] = MTUWIDTH_G(v);
4956 * t4_read_cong_tbl - reads the congestion control table
4957 * @adap: the adapter
4958 * @incr: where to store the alpha values
4960 * Reads the additive increments programmed into the HW congestion
4963 void t4_read_cong_tbl(struct adapter *adap, u16 incr[NMTUS][NCCTRL_WIN])
4965 unsigned int mtu, w;
4967 for (mtu = 0; mtu < NMTUS; ++mtu)
4968 for (w = 0; w < NCCTRL_WIN; ++w) {
4969 t4_write_reg(adap, TP_CCTRL_TABLE_A,
4970 ROWINDEX_V(0xffff) | (mtu << 5) | w);
4971 incr[mtu][w] = (u16)t4_read_reg(adap,
4972 TP_CCTRL_TABLE_A) & 0x1fff;
4977 * t4_tp_wr_bits_indirect - set/clear bits in an indirect TP register
4978 * @adap: the adapter
4979 * @addr: the indirect TP register address
4980 * @mask: specifies the field within the register to modify
4981 * @val: new value for the field
4983 * Sets a field of an indirect TP register to the given value.
4985 void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr,
4986 unsigned int mask, unsigned int val)
4988 t4_write_reg(adap, TP_PIO_ADDR_A, addr);
4989 val |= t4_read_reg(adap, TP_PIO_DATA_A) & ~mask;
4990 t4_write_reg(adap, TP_PIO_DATA_A, val);
4994 * init_cong_ctrl - initialize congestion control parameters
4995 * @a: the alpha values for congestion control
4996 * @b: the beta values for congestion control
4998 * Initialize the congestion control parameters.
5000 static void init_cong_ctrl(unsigned short *a, unsigned short *b)
5002 a[0] = a[1] = a[2] = a[3] = a[4] = a[5] = a[6] = a[7] = a[8] = 1;
5027 b[0] = b[1] = b[2] = b[3] = b[4] = b[5] = b[6] = b[7] = b[8] = 0;
5030 b[13] = b[14] = b[15] = b[16] = 3;
5031 b[17] = b[18] = b[19] = b[20] = b[21] = 4;
5032 b[22] = b[23] = b[24] = b[25] = b[26] = b[27] = 5;
5037 /* The minimum additive increment value for the congestion control table */
5038 #define CC_MIN_INCR 2U
5041 * t4_load_mtus - write the MTU and congestion control HW tables
5042 * @adap: the adapter
5043 * @mtus: the values for the MTU table
5044 * @alpha: the values for the congestion control alpha parameter
5045 * @beta: the values for the congestion control beta parameter
5047 * Write the HW MTU table with the supplied MTUs and the high-speed
5048 * congestion control table with the supplied alpha, beta, and MTUs.
5049 * We write the two tables together because the additive increments
5050 * depend on the MTUs.
5052 void t4_load_mtus(struct adapter *adap, const unsigned short *mtus,
5053 const unsigned short *alpha, const unsigned short *beta)
5055 static const unsigned int avg_pkts[NCCTRL_WIN] = {
5056 2, 6, 10, 14, 20, 28, 40, 56, 80, 112, 160, 224, 320, 448, 640,
5057 896, 1281, 1792, 2560, 3584, 5120, 7168, 10240, 14336, 20480,
5058 28672, 40960, 57344, 81920, 114688, 163840, 229376
5063 for (i = 0; i < NMTUS; ++i) {
5064 unsigned int mtu = mtus[i];
5065 unsigned int log2 = fls(mtu);
5067 if (!(mtu & ((1 << log2) >> 2))) /* round */
5069 t4_write_reg(adap, TP_MTU_TABLE_A, MTUINDEX_V(i) |
5070 MTUWIDTH_V(log2) | MTUVALUE_V(mtu));
5072 for (w = 0; w < NCCTRL_WIN; ++w) {
5075 inc = max(((mtu - 40) * alpha[w]) / avg_pkts[w],
5078 t4_write_reg(adap, TP_CCTRL_TABLE_A, (i << 21) |
5079 (w << 16) | (beta[w] << 13) | inc);
5084 /* Calculates a rate in bytes/s given the number of 256-byte units per 4K core
5085 * clocks. The formula is
5087 * bytes/s = bytes256 * 256 * ClkFreq / 4096
5089 * which is equivalent to
5091 * bytes/s = 62.5 * bytes256 * ClkFreq_ms
5093 static u64 chan_rate(struct adapter *adap, unsigned int bytes256)
5095 u64 v = bytes256 * adap->params.vpd.cclk;
5097 return v * 62 + v / 2;
5101 * t4_get_chan_txrate - get the current per channel Tx rates
5102 * @adap: the adapter
5103 * @nic_rate: rates for NIC traffic
5104 * @ofld_rate: rates for offloaded traffic
5106 * Return the current Tx rates in bytes/s for NIC and offloaded traffic
5109 void t4_get_chan_txrate(struct adapter *adap, u64 *nic_rate, u64 *ofld_rate)
5113 v = t4_read_reg(adap, TP_TX_TRATE_A);
5114 nic_rate[0] = chan_rate(adap, TNLRATE0_G(v));
5115 nic_rate[1] = chan_rate(adap, TNLRATE1_G(v));
5116 if (adap->params.arch.nchan == NCHAN) {
5117 nic_rate[2] = chan_rate(adap, TNLRATE2_G(v));
5118 nic_rate[3] = chan_rate(adap, TNLRATE3_G(v));
5121 v = t4_read_reg(adap, TP_TX_ORATE_A);
5122 ofld_rate[0] = chan_rate(adap, OFDRATE0_G(v));
5123 ofld_rate[1] = chan_rate(adap, OFDRATE1_G(v));
5124 if (adap->params.arch.nchan == NCHAN) {
5125 ofld_rate[2] = chan_rate(adap, OFDRATE2_G(v));
5126 ofld_rate[3] = chan_rate(adap, OFDRATE3_G(v));
5131 * t4_set_trace_filter - configure one of the tracing filters
5132 * @adap: the adapter
5133 * @tp: the desired trace filter parameters
5134 * @idx: which filter to configure
5135 * @enable: whether to enable or disable the filter
5137 * Configures one of the tracing filters available in HW. If @enable is
5138 * %0 @tp is not examined and may be %NULL. The user is responsible to
5139 * set the single/multiple trace mode by writing to MPS_TRC_CFG_A register
5141 int t4_set_trace_filter(struct adapter *adap, const struct trace_params *tp,
5142 int idx, int enable)
5144 int i, ofst = idx * 4;
5145 u32 data_reg, mask_reg, cfg;
5146 u32 multitrc = TRCMULTIFILTER_F;
5149 t4_write_reg(adap, MPS_TRC_FILTER_MATCH_CTL_A_A + ofst, 0);
5153 cfg = t4_read_reg(adap, MPS_TRC_CFG_A);
5154 if (cfg & TRCMULTIFILTER_F) {
5155 /* If multiple tracers are enabled, then maximum
5156 * capture size is 2.5KB (FIFO size of a single channel)
5157 * minus 2 flits for CPL_TRACE_PKT header.
5159 if (tp->snap_len > ((10 * 1024 / 4) - (2 * 8)))
5162 /* If multiple tracers are disabled, to avoid deadlocks
5163 * maximum packet capture size of 9600 bytes is recommended.
5164 * Also in this mode, only trace0 can be enabled and running.
5167 if (tp->snap_len > 9600 || idx)
5171 if (tp->port > (is_t4(adap->params.chip) ? 11 : 19) || tp->invert > 1 ||
5172 tp->skip_len > TFLENGTH_M || tp->skip_ofst > TFOFFSET_M ||
5173 tp->min_len > TFMINPKTSIZE_M)
5176 /* stop the tracer we'll be changing */
5177 t4_write_reg(adap, MPS_TRC_FILTER_MATCH_CTL_A_A + ofst, 0);
5179 idx *= (MPS_TRC_FILTER1_MATCH_A - MPS_TRC_FILTER0_MATCH_A);
5180 data_reg = MPS_TRC_FILTER0_MATCH_A + idx;
5181 mask_reg = MPS_TRC_FILTER0_DONT_CARE_A + idx;
5183 for (i = 0; i < TRACE_LEN / 4; i++, data_reg += 4, mask_reg += 4) {
5184 t4_write_reg(adap, data_reg, tp->data[i]);
5185 t4_write_reg(adap, mask_reg, ~tp->mask[i]);
5187 t4_write_reg(adap, MPS_TRC_FILTER_MATCH_CTL_B_A + ofst,
5188 TFCAPTUREMAX_V(tp->snap_len) |
5189 TFMINPKTSIZE_V(tp->min_len));
5190 t4_write_reg(adap, MPS_TRC_FILTER_MATCH_CTL_A_A + ofst,
5191 TFOFFSET_V(tp->skip_ofst) | TFLENGTH_V(tp->skip_len) |
5192 (is_t4(adap->params.chip) ?
5193 TFPORT_V(tp->port) | TFEN_F | TFINVERTMATCH_V(tp->invert) :
5194 T5_TFPORT_V(tp->port) | T5_TFEN_F |
5195 T5_TFINVERTMATCH_V(tp->invert)));
5201 * t4_get_trace_filter - query one of the tracing filters
5202 * @adap: the adapter
5203 * @tp: the current trace filter parameters
5204 * @idx: which trace filter to query
5205 * @enabled: non-zero if the filter is enabled
5207 * Returns the current settings of one of the HW tracing filters.
5209 void t4_get_trace_filter(struct adapter *adap, struct trace_params *tp, int idx,
5213 int i, ofst = idx * 4;
5214 u32 data_reg, mask_reg;
5216 ctla = t4_read_reg(adap, MPS_TRC_FILTER_MATCH_CTL_A_A + ofst);
5217 ctlb = t4_read_reg(adap, MPS_TRC_FILTER_MATCH_CTL_B_A + ofst);
5219 if (is_t4(adap->params.chip)) {
5220 *enabled = !!(ctla & TFEN_F);
5221 tp->port = TFPORT_G(ctla);
5222 tp->invert = !!(ctla & TFINVERTMATCH_F);
5224 *enabled = !!(ctla & T5_TFEN_F);
5225 tp->port = T5_TFPORT_G(ctla);
5226 tp->invert = !!(ctla & T5_TFINVERTMATCH_F);
5228 tp->snap_len = TFCAPTUREMAX_G(ctlb);
5229 tp->min_len = TFMINPKTSIZE_G(ctlb);
5230 tp->skip_ofst = TFOFFSET_G(ctla);
5231 tp->skip_len = TFLENGTH_G(ctla);
5233 ofst = (MPS_TRC_FILTER1_MATCH_A - MPS_TRC_FILTER0_MATCH_A) * idx;
5234 data_reg = MPS_TRC_FILTER0_MATCH_A + ofst;
5235 mask_reg = MPS_TRC_FILTER0_DONT_CARE_A + ofst;
5237 for (i = 0; i < TRACE_LEN / 4; i++, data_reg += 4, mask_reg += 4) {
5238 tp->mask[i] = ~t4_read_reg(adap, mask_reg);
5239 tp->data[i] = t4_read_reg(adap, data_reg) & tp->mask[i];
5244 * t4_pmtx_get_stats - returns the HW stats from PMTX
5245 * @adap: the adapter
5246 * @cnt: where to store the count statistics
5247 * @cycles: where to store the cycle statistics
5249 * Returns performance statistics from PMTX.
5251 void t4_pmtx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[])
5256 for (i = 0; i < adap->params.arch.pm_stats_cnt; i++) {
5257 t4_write_reg(adap, PM_TX_STAT_CONFIG_A, i + 1);
5258 cnt[i] = t4_read_reg(adap, PM_TX_STAT_COUNT_A);
5259 if (is_t4(adap->params.chip)) {
5260 cycles[i] = t4_read_reg64(adap, PM_TX_STAT_LSB_A);
5262 t4_read_indirect(adap, PM_TX_DBG_CTRL_A,
5263 PM_TX_DBG_DATA_A, data, 2,
5264 PM_TX_DBG_STAT_MSB_A);
5265 cycles[i] = (((u64)data[0] << 32) | data[1]);
5271 * t4_pmrx_get_stats - returns the HW stats from PMRX
5272 * @adap: the adapter
5273 * @cnt: where to store the count statistics
5274 * @cycles: where to store the cycle statistics
5276 * Returns performance statistics from PMRX.
5278 void t4_pmrx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[])
5283 for (i = 0; i < adap->params.arch.pm_stats_cnt; i++) {
5284 t4_write_reg(adap, PM_RX_STAT_CONFIG_A, i + 1);
5285 cnt[i] = t4_read_reg(adap, PM_RX_STAT_COUNT_A);
5286 if (is_t4(adap->params.chip)) {
5287 cycles[i] = t4_read_reg64(adap, PM_RX_STAT_LSB_A);
5289 t4_read_indirect(adap, PM_RX_DBG_CTRL_A,
5290 PM_RX_DBG_DATA_A, data, 2,
5291 PM_RX_DBG_STAT_MSB_A);
5292 cycles[i] = (((u64)data[0] << 32) | data[1]);
5298 * t4_get_mps_bg_map - return the buffer groups associated with a port
5299 * @adap: the adapter
5300 * @idx: the port index
5302 * Returns a bitmap indicating which MPS buffer groups are associated
5303 * with the given port. Bit i is set if buffer group i is used by the
5306 unsigned int t4_get_mps_bg_map(struct adapter *adap, int idx)
5308 u32 n = NUMPORTS_G(t4_read_reg(adap, MPS_CMN_CTL_A));
5311 return idx == 0 ? 0xf : 0;
5312 /* In T6 (which is a 2 port card),
5313 * port 0 is mapped to channel 0 and port 1 is mapped to channel 1.
5314 * For 2 port T4/T5 adapter,
5315 * port 0 is mapped to channel 0 and 1,
5316 * port 1 is mapped to channel 2 and 3.
5319 (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5))
5320 return idx < 2 ? (3 << (2 * idx)) : 0;
5325 * t4_get_port_type_description - return Port Type string description
5326 * @port_type: firmware Port Type enumeration
5328 const char *t4_get_port_type_description(enum fw_port_type port_type)
5330 static const char *const port_type_description[] = {
5349 if (port_type < ARRAY_SIZE(port_type_description))
5350 return port_type_description[port_type];
5355 * t4_get_port_stats_offset - collect port stats relative to a previous
5357 * @adap: The adapter
5359 * @stats: Current stats to fill
5360 * @offset: Previous stats snapshot
5362 void t4_get_port_stats_offset(struct adapter *adap, int idx,
5363 struct port_stats *stats,
5364 struct port_stats *offset)
5369 t4_get_port_stats(adap, idx, stats);
5370 for (i = 0, s = (u64 *)stats, o = (u64 *)offset;
5371 i < (sizeof(struct port_stats) / sizeof(u64));
5377 * t4_get_port_stats - collect port statistics
5378 * @adap: the adapter
5379 * @idx: the port index
5380 * @p: the stats structure to fill
5382 * Collect statistics related to the given port from HW.
5384 void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p)
5386 u32 bgmap = t4_get_mps_bg_map(adap, idx);
5388 #define GET_STAT(name) \
5389 t4_read_reg64(adap, \
5390 (is_t4(adap->params.chip) ? PORT_REG(idx, MPS_PORT_STAT_##name##_L) : \
5391 T5_PORT_REG(idx, MPS_PORT_STAT_##name##_L)))
5392 #define GET_STAT_COM(name) t4_read_reg64(adap, MPS_STAT_##name##_L)
5394 p->tx_octets = GET_STAT(TX_PORT_BYTES);
5395 p->tx_frames = GET_STAT(TX_PORT_FRAMES);
5396 p->tx_bcast_frames = GET_STAT(TX_PORT_BCAST);
5397 p->tx_mcast_frames = GET_STAT(TX_PORT_MCAST);
5398 p->tx_ucast_frames = GET_STAT(TX_PORT_UCAST);
5399 p->tx_error_frames = GET_STAT(TX_PORT_ERROR);
5400 p->tx_frames_64 = GET_STAT(TX_PORT_64B);
5401 p->tx_frames_65_127 = GET_STAT(TX_PORT_65B_127B);
5402 p->tx_frames_128_255 = GET_STAT(TX_PORT_128B_255B);
5403 p->tx_frames_256_511 = GET_STAT(TX_PORT_256B_511B);
5404 p->tx_frames_512_1023 = GET_STAT(TX_PORT_512B_1023B);
5405 p->tx_frames_1024_1518 = GET_STAT(TX_PORT_1024B_1518B);
5406 p->tx_frames_1519_max = GET_STAT(TX_PORT_1519B_MAX);
5407 p->tx_drop = GET_STAT(TX_PORT_DROP);
5408 p->tx_pause = GET_STAT(TX_PORT_PAUSE);
5409 p->tx_ppp0 = GET_STAT(TX_PORT_PPP0);
5410 p->tx_ppp1 = GET_STAT(TX_PORT_PPP1);
5411 p->tx_ppp2 = GET_STAT(TX_PORT_PPP2);
5412 p->tx_ppp3 = GET_STAT(TX_PORT_PPP3);
5413 p->tx_ppp4 = GET_STAT(TX_PORT_PPP4);
5414 p->tx_ppp5 = GET_STAT(TX_PORT_PPP5);
5415 p->tx_ppp6 = GET_STAT(TX_PORT_PPP6);
5416 p->tx_ppp7 = GET_STAT(TX_PORT_PPP7);
5418 p->rx_octets = GET_STAT(RX_PORT_BYTES);
5419 p->rx_frames = GET_STAT(RX_PORT_FRAMES);
5420 p->rx_bcast_frames = GET_STAT(RX_PORT_BCAST);
5421 p->rx_mcast_frames = GET_STAT(RX_PORT_MCAST);
5422 p->rx_ucast_frames = GET_STAT(RX_PORT_UCAST);
5423 p->rx_too_long = GET_STAT(RX_PORT_MTU_ERROR);
5424 p->rx_jabber = GET_STAT(RX_PORT_MTU_CRC_ERROR);
5425 p->rx_fcs_err = GET_STAT(RX_PORT_CRC_ERROR);
5426 p->rx_len_err = GET_STAT(RX_PORT_LEN_ERROR);
5427 p->rx_symbol_err = GET_STAT(RX_PORT_SYM_ERROR);
5428 p->rx_runt = GET_STAT(RX_PORT_LESS_64B);
5429 p->rx_frames_64 = GET_STAT(RX_PORT_64B);
5430 p->rx_frames_65_127 = GET_STAT(RX_PORT_65B_127B);
5431 p->rx_frames_128_255 = GET_STAT(RX_PORT_128B_255B);
5432 p->rx_frames_256_511 = GET_STAT(RX_PORT_256B_511B);
5433 p->rx_frames_512_1023 = GET_STAT(RX_PORT_512B_1023B);
5434 p->rx_frames_1024_1518 = GET_STAT(RX_PORT_1024B_1518B);
5435 p->rx_frames_1519_max = GET_STAT(RX_PORT_1519B_MAX);
5436 p->rx_pause = GET_STAT(RX_PORT_PAUSE);
5437 p->rx_ppp0 = GET_STAT(RX_PORT_PPP0);
5438 p->rx_ppp1 = GET_STAT(RX_PORT_PPP1);
5439 p->rx_ppp2 = GET_STAT(RX_PORT_PPP2);
5440 p->rx_ppp3 = GET_STAT(RX_PORT_PPP3);
5441 p->rx_ppp4 = GET_STAT(RX_PORT_PPP4);
5442 p->rx_ppp5 = GET_STAT(RX_PORT_PPP5);
5443 p->rx_ppp6 = GET_STAT(RX_PORT_PPP6);
5444 p->rx_ppp7 = GET_STAT(RX_PORT_PPP7);
5446 p->rx_ovflow0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_MAC_DROP_FRAME) : 0;
5447 p->rx_ovflow1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_MAC_DROP_FRAME) : 0;
5448 p->rx_ovflow2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_MAC_DROP_FRAME) : 0;
5449 p->rx_ovflow3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_MAC_DROP_FRAME) : 0;
5450 p->rx_trunc0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_MAC_TRUNC_FRAME) : 0;
5451 p->rx_trunc1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_MAC_TRUNC_FRAME) : 0;
5452 p->rx_trunc2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_MAC_TRUNC_FRAME) : 0;
5453 p->rx_trunc3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_MAC_TRUNC_FRAME) : 0;
5460 * t4_get_lb_stats - collect loopback port statistics
5461 * @adap: the adapter
5462 * @idx: the loopback port index
5463 * @p: the stats structure to fill
5465 * Return HW statistics for the given loopback port.
5467 void t4_get_lb_stats(struct adapter *adap, int idx, struct lb_port_stats *p)
5469 u32 bgmap = t4_get_mps_bg_map(adap, idx);
5471 #define GET_STAT(name) \
5472 t4_read_reg64(adap, \
5473 (is_t4(adap->params.chip) ? \
5474 PORT_REG(idx, MPS_PORT_STAT_LB_PORT_##name##_L) : \
5475 T5_PORT_REG(idx, MPS_PORT_STAT_LB_PORT_##name##_L)))
5476 #define GET_STAT_COM(name) t4_read_reg64(adap, MPS_STAT_##name##_L)
5478 p->octets = GET_STAT(BYTES);
5479 p->frames = GET_STAT(FRAMES);
5480 p->bcast_frames = GET_STAT(BCAST);
5481 p->mcast_frames = GET_STAT(MCAST);
5482 p->ucast_frames = GET_STAT(UCAST);
5483 p->error_frames = GET_STAT(ERROR);
5485 p->frames_64 = GET_STAT(64B);
5486 p->frames_65_127 = GET_STAT(65B_127B);
5487 p->frames_128_255 = GET_STAT(128B_255B);
5488 p->frames_256_511 = GET_STAT(256B_511B);
5489 p->frames_512_1023 = GET_STAT(512B_1023B);
5490 p->frames_1024_1518 = GET_STAT(1024B_1518B);
5491 p->frames_1519_max = GET_STAT(1519B_MAX);
5492 p->drop = GET_STAT(DROP_FRAMES);
5494 p->ovflow0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_LB_DROP_FRAME) : 0;
5495 p->ovflow1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_LB_DROP_FRAME) : 0;
5496 p->ovflow2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_LB_DROP_FRAME) : 0;
5497 p->ovflow3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_LB_DROP_FRAME) : 0;
5498 p->trunc0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_LB_TRUNC_FRAME) : 0;
5499 p->trunc1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_LB_TRUNC_FRAME) : 0;
5500 p->trunc2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_LB_TRUNC_FRAME) : 0;
5501 p->trunc3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_LB_TRUNC_FRAME) : 0;
5507 /* t4_mk_filtdelwr - create a delete filter WR
5508 * @ftid: the filter ID
5509 * @wr: the filter work request to populate
5510 * @qid: ingress queue to receive the delete notification
5512 * Creates a filter work request to delete the supplied filter. If @qid is
5513 * negative the delete notification is suppressed.
5515 void t4_mk_filtdelwr(unsigned int ftid, struct fw_filter_wr *wr, int qid)
5517 memset(wr, 0, sizeof(*wr));
5518 wr->op_pkd = cpu_to_be32(FW_WR_OP_V(FW_FILTER_WR));
5519 wr->len16_pkd = cpu_to_be32(FW_WR_LEN16_V(sizeof(*wr) / 16));
5520 wr->tid_to_iq = cpu_to_be32(FW_FILTER_WR_TID_V(ftid) |
5521 FW_FILTER_WR_NOREPLY_V(qid < 0));
5522 wr->del_filter_to_l2tix = cpu_to_be32(FW_FILTER_WR_DEL_FILTER_F);
5524 wr->rx_chan_rx_rpl_iq =
5525 cpu_to_be16(FW_FILTER_WR_RX_RPL_IQ_V(qid));
5528 #define INIT_CMD(var, cmd, rd_wr) do { \
5529 (var).op_to_write = cpu_to_be32(FW_CMD_OP_V(FW_##cmd##_CMD) | \
5530 FW_CMD_REQUEST_F | \
5531 FW_CMD_##rd_wr##_F); \
5532 (var).retval_len16 = cpu_to_be32(FW_LEN16(var)); \
5535 int t4_fwaddrspace_write(struct adapter *adap, unsigned int mbox,
5539 struct fw_ldst_cmd c;
5541 memset(&c, 0, sizeof(c));
5542 ldst_addrspace = FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_FIRMWARE);
5543 c.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
5547 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
5548 c.u.addrval.addr = cpu_to_be32(addr);
5549 c.u.addrval.val = cpu_to_be32(val);
5551 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
5555 * t4_mdio_rd - read a PHY register through MDIO
5556 * @adap: the adapter
5557 * @mbox: mailbox to use for the FW command
5558 * @phy_addr: the PHY address
5559 * @mmd: the PHY MMD to access (0 for clause 22 PHYs)
5560 * @reg: the register to read
5561 * @valp: where to store the value
5563 * Issues a FW command through the given mailbox to read a PHY register.
5565 int t4_mdio_rd(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
5566 unsigned int mmd, unsigned int reg, u16 *valp)
5570 struct fw_ldst_cmd c;
5572 memset(&c, 0, sizeof(c));
5573 ldst_addrspace = FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_MDIO);
5574 c.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
5575 FW_CMD_REQUEST_F | FW_CMD_READ_F |
5577 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
5578 c.u.mdio.paddr_mmd = cpu_to_be16(FW_LDST_CMD_PADDR_V(phy_addr) |
5579 FW_LDST_CMD_MMD_V(mmd));
5580 c.u.mdio.raddr = cpu_to_be16(reg);
5582 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
5584 *valp = be16_to_cpu(c.u.mdio.rval);
5589 * t4_mdio_wr - write a PHY register through MDIO
5590 * @adap: the adapter
5591 * @mbox: mailbox to use for the FW command
5592 * @phy_addr: the PHY address
5593 * @mmd: the PHY MMD to access (0 for clause 22 PHYs)
5594 * @reg: the register to write
5595 * @valp: value to write
5597 * Issues a FW command through the given mailbox to write a PHY register.
5599 int t4_mdio_wr(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
5600 unsigned int mmd, unsigned int reg, u16 val)
5603 struct fw_ldst_cmd c;
5605 memset(&c, 0, sizeof(c));
5606 ldst_addrspace = FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_MDIO);
5607 c.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
5608 FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
5610 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
5611 c.u.mdio.paddr_mmd = cpu_to_be16(FW_LDST_CMD_PADDR_V(phy_addr) |
5612 FW_LDST_CMD_MMD_V(mmd));
5613 c.u.mdio.raddr = cpu_to_be16(reg);
5614 c.u.mdio.rval = cpu_to_be16(val);
5616 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
5620 * t4_sge_decode_idma_state - decode the idma state
5621 * @adap: the adapter
5622 * @state: the state idma is stuck in
5624 void t4_sge_decode_idma_state(struct adapter *adapter, int state)
5626 static const char * const t4_decode[] = {
5628 "IDMA_PUSH_MORE_CPL_FIFO",
5629 "IDMA_PUSH_CPL_MSG_HEADER_TO_FIFO",
5631 "IDMA_PHYSADDR_SEND_PCIEHDR",
5632 "IDMA_PHYSADDR_SEND_PAYLOAD_FIRST",
5633 "IDMA_PHYSADDR_SEND_PAYLOAD",
5634 "IDMA_SEND_FIFO_TO_IMSG",
5635 "IDMA_FL_REQ_DATA_FL_PREP",
5636 "IDMA_FL_REQ_DATA_FL",
5638 "IDMA_FL_H_REQ_HEADER_FL",
5639 "IDMA_FL_H_SEND_PCIEHDR",
5640 "IDMA_FL_H_PUSH_CPL_FIFO",
5641 "IDMA_FL_H_SEND_CPL",
5642 "IDMA_FL_H_SEND_IP_HDR_FIRST",
5643 "IDMA_FL_H_SEND_IP_HDR",
5644 "IDMA_FL_H_REQ_NEXT_HEADER_FL",
5645 "IDMA_FL_H_SEND_NEXT_PCIEHDR",
5646 "IDMA_FL_H_SEND_IP_HDR_PADDING",
5647 "IDMA_FL_D_SEND_PCIEHDR",
5648 "IDMA_FL_D_SEND_CPL_AND_IP_HDR",
5649 "IDMA_FL_D_REQ_NEXT_DATA_FL",
5650 "IDMA_FL_SEND_PCIEHDR",
5651 "IDMA_FL_PUSH_CPL_FIFO",
5653 "IDMA_FL_SEND_PAYLOAD_FIRST",
5654 "IDMA_FL_SEND_PAYLOAD",
5655 "IDMA_FL_REQ_NEXT_DATA_FL",
5656 "IDMA_FL_SEND_NEXT_PCIEHDR",
5657 "IDMA_FL_SEND_PADDING",
5658 "IDMA_FL_SEND_COMPLETION_TO_IMSG",
5659 "IDMA_FL_SEND_FIFO_TO_IMSG",
5660 "IDMA_FL_REQ_DATAFL_DONE",
5661 "IDMA_FL_REQ_HEADERFL_DONE",
5663 static const char * const t5_decode[] = {
5666 "IDMA_PUSH_MORE_CPL_FIFO",
5667 "IDMA_PUSH_CPL_MSG_HEADER_TO_FIFO",
5668 "IDMA_SGEFLRFLUSH_SEND_PCIEHDR",
5669 "IDMA_PHYSADDR_SEND_PCIEHDR",
5670 "IDMA_PHYSADDR_SEND_PAYLOAD_FIRST",
5671 "IDMA_PHYSADDR_SEND_PAYLOAD",
5672 "IDMA_SEND_FIFO_TO_IMSG",
5673 "IDMA_FL_REQ_DATA_FL",
5675 "IDMA_FL_DROP_SEND_INC",
5676 "IDMA_FL_H_REQ_HEADER_FL",
5677 "IDMA_FL_H_SEND_PCIEHDR",
5678 "IDMA_FL_H_PUSH_CPL_FIFO",
5679 "IDMA_FL_H_SEND_CPL",
5680 "IDMA_FL_H_SEND_IP_HDR_FIRST",
5681 "IDMA_FL_H_SEND_IP_HDR",
5682 "IDMA_FL_H_REQ_NEXT_HEADER_FL",
5683 "IDMA_FL_H_SEND_NEXT_PCIEHDR",
5684 "IDMA_FL_H_SEND_IP_HDR_PADDING",
5685 "IDMA_FL_D_SEND_PCIEHDR",
5686 "IDMA_FL_D_SEND_CPL_AND_IP_HDR",
5687 "IDMA_FL_D_REQ_NEXT_DATA_FL",
5688 "IDMA_FL_SEND_PCIEHDR",
5689 "IDMA_FL_PUSH_CPL_FIFO",
5691 "IDMA_FL_SEND_PAYLOAD_FIRST",
5692 "IDMA_FL_SEND_PAYLOAD",
5693 "IDMA_FL_REQ_NEXT_DATA_FL",
5694 "IDMA_FL_SEND_NEXT_PCIEHDR",
5695 "IDMA_FL_SEND_PADDING",
5696 "IDMA_FL_SEND_COMPLETION_TO_IMSG",
5698 static const char * const t6_decode[] = {
5700 "IDMA_PUSH_MORE_CPL_FIFO",
5701 "IDMA_PUSH_CPL_MSG_HEADER_TO_FIFO",
5702 "IDMA_SGEFLRFLUSH_SEND_PCIEHDR",
5703 "IDMA_PHYSADDR_SEND_PCIEHDR",
5704 "IDMA_PHYSADDR_SEND_PAYLOAD_FIRST",
5705 "IDMA_PHYSADDR_SEND_PAYLOAD",
5706 "IDMA_FL_REQ_DATA_FL",
5708 "IDMA_FL_DROP_SEND_INC",
5709 "IDMA_FL_H_REQ_HEADER_FL",
5710 "IDMA_FL_H_SEND_PCIEHDR",
5711 "IDMA_FL_H_PUSH_CPL_FIFO",
5712 "IDMA_FL_H_SEND_CPL",
5713 "IDMA_FL_H_SEND_IP_HDR_FIRST",
5714 "IDMA_FL_H_SEND_IP_HDR",
5715 "IDMA_FL_H_REQ_NEXT_HEADER_FL",
5716 "IDMA_FL_H_SEND_NEXT_PCIEHDR",
5717 "IDMA_FL_H_SEND_IP_HDR_PADDING",
5718 "IDMA_FL_D_SEND_PCIEHDR",
5719 "IDMA_FL_D_SEND_CPL_AND_IP_HDR",
5720 "IDMA_FL_D_REQ_NEXT_DATA_FL",
5721 "IDMA_FL_SEND_PCIEHDR",
5722 "IDMA_FL_PUSH_CPL_FIFO",
5724 "IDMA_FL_SEND_PAYLOAD_FIRST",
5725 "IDMA_FL_SEND_PAYLOAD",
5726 "IDMA_FL_REQ_NEXT_DATA_FL",
5727 "IDMA_FL_SEND_NEXT_PCIEHDR",
5728 "IDMA_FL_SEND_PADDING",
5729 "IDMA_FL_SEND_COMPLETION_TO_IMSG",
5731 static const u32 sge_regs[] = {
5732 SGE_DEBUG_DATA_LOW_INDEX_2_A,
5733 SGE_DEBUG_DATA_LOW_INDEX_3_A,
5734 SGE_DEBUG_DATA_HIGH_INDEX_10_A,
5736 const char **sge_idma_decode;
5737 int sge_idma_decode_nstates;
5739 unsigned int chip_version = CHELSIO_CHIP_VERSION(adapter->params.chip);
5741 /* Select the right set of decode strings to dump depending on the
5742 * adapter chip type.
5744 switch (chip_version) {
5746 sge_idma_decode = (const char **)t4_decode;
5747 sge_idma_decode_nstates = ARRAY_SIZE(t4_decode);
5751 sge_idma_decode = (const char **)t5_decode;
5752 sge_idma_decode_nstates = ARRAY_SIZE(t5_decode);
5756 sge_idma_decode = (const char **)t6_decode;
5757 sge_idma_decode_nstates = ARRAY_SIZE(t6_decode);
5761 dev_err(adapter->pdev_dev,
5762 "Unsupported chip version %d\n", chip_version);
5766 if (is_t4(adapter->params.chip)) {
5767 sge_idma_decode = (const char **)t4_decode;
5768 sge_idma_decode_nstates = ARRAY_SIZE(t4_decode);
5770 sge_idma_decode = (const char **)t5_decode;
5771 sge_idma_decode_nstates = ARRAY_SIZE(t5_decode);
5774 if (state < sge_idma_decode_nstates)
5775 CH_WARN(adapter, "idma state %s\n", sge_idma_decode[state]);
5777 CH_WARN(adapter, "idma state %d unknown\n", state);
5779 for (i = 0; i < ARRAY_SIZE(sge_regs); i++)
5780 CH_WARN(adapter, "SGE register %#x value %#x\n",
5781 sge_regs[i], t4_read_reg(adapter, sge_regs[i]));
5785 * t4_sge_ctxt_flush - flush the SGE context cache
5786 * @adap: the adapter
5787 * @mbox: mailbox to use for the FW command
5789 * Issues a FW command through the given mailbox to flush the
5790 * SGE context cache.
5792 int t4_sge_ctxt_flush(struct adapter *adap, unsigned int mbox)
5796 struct fw_ldst_cmd c;
5798 memset(&c, 0, sizeof(c));
5799 ldst_addrspace = FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_SGE_EGRC);
5800 c.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
5801 FW_CMD_REQUEST_F | FW_CMD_READ_F |
5803 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
5804 c.u.idctxt.msg_ctxtflush = cpu_to_be32(FW_LDST_CMD_CTXTFLUSH_F);
5806 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
5811 * t4_fw_hello - establish communication with FW
5812 * @adap: the adapter
5813 * @mbox: mailbox to use for the FW command
5814 * @evt_mbox: mailbox to receive async FW events
5815 * @master: specifies the caller's willingness to be the device master
5816 * @state: returns the current device state (if non-NULL)
5818 * Issues a command to establish communication with FW. Returns either
5819 * an error (negative integer) or the mailbox of the Master PF.
5821 int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox,
5822 enum dev_master master, enum dev_state *state)
5825 struct fw_hello_cmd c;
5827 unsigned int master_mbox;
5828 int retries = FW_CMD_HELLO_RETRIES;
5831 memset(&c, 0, sizeof(c));
5832 INIT_CMD(c, HELLO, WRITE);
5833 c.err_to_clearinit = cpu_to_be32(
5834 FW_HELLO_CMD_MASTERDIS_V(master == MASTER_CANT) |
5835 FW_HELLO_CMD_MASTERFORCE_V(master == MASTER_MUST) |
5836 FW_HELLO_CMD_MBMASTER_V(master == MASTER_MUST ?
5837 mbox : FW_HELLO_CMD_MBMASTER_M) |
5838 FW_HELLO_CMD_MBASYNCNOT_V(evt_mbox) |
5839 FW_HELLO_CMD_STAGE_V(fw_hello_cmd_stage_os) |
5840 FW_HELLO_CMD_CLEARINIT_F);
5843 * Issue the HELLO command to the firmware. If it's not successful
5844 * but indicates that we got a "busy" or "timeout" condition, retry
5845 * the HELLO until we exhaust our retry limit. If we do exceed our
5846 * retry limit, check to see if the firmware left us any error
5847 * information and report that if so.
5849 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
5851 if ((ret == -EBUSY || ret == -ETIMEDOUT) && retries-- > 0)
5853 if (t4_read_reg(adap, PCIE_FW_A) & PCIE_FW_ERR_F)
5854 t4_report_fw_error(adap);
5858 v = be32_to_cpu(c.err_to_clearinit);
5859 master_mbox = FW_HELLO_CMD_MBMASTER_G(v);
5861 if (v & FW_HELLO_CMD_ERR_F)
5862 *state = DEV_STATE_ERR;
5863 else if (v & FW_HELLO_CMD_INIT_F)
5864 *state = DEV_STATE_INIT;
5866 *state = DEV_STATE_UNINIT;
5870 * If we're not the Master PF then we need to wait around for the
5871 * Master PF Driver to finish setting up the adapter.
5873 * Note that we also do this wait if we're a non-Master-capable PF and
5874 * there is no current Master PF; a Master PF may show up momentarily
5875 * and we wouldn't want to fail pointlessly. (This can happen when an
5876 * OS loads lots of different drivers rapidly at the same time). In
5877 * this case, the Master PF returned by the firmware will be
5878 * PCIE_FW_MASTER_M so the test below will work ...
5880 if ((v & (FW_HELLO_CMD_ERR_F|FW_HELLO_CMD_INIT_F)) == 0 &&
5881 master_mbox != mbox) {
5882 int waiting = FW_CMD_HELLO_TIMEOUT;
5885 * Wait for the firmware to either indicate an error or
5886 * initialized state. If we see either of these we bail out
5887 * and report the issue to the caller. If we exhaust the
5888 * "hello timeout" and we haven't exhausted our retries, try
5889 * again. Otherwise bail with a timeout error.
5898 * If neither Error nor Initialialized are indicated
5899 * by the firmware keep waiting till we exaust our
5900 * timeout ... and then retry if we haven't exhausted
5903 pcie_fw = t4_read_reg(adap, PCIE_FW_A);
5904 if (!(pcie_fw & (PCIE_FW_ERR_F|PCIE_FW_INIT_F))) {
5915 * We either have an Error or Initialized condition
5916 * report errors preferentially.
5919 if (pcie_fw & PCIE_FW_ERR_F)
5920 *state = DEV_STATE_ERR;
5921 else if (pcie_fw & PCIE_FW_INIT_F)
5922 *state = DEV_STATE_INIT;
5926 * If we arrived before a Master PF was selected and
5927 * there's not a valid Master PF, grab its identity
5930 if (master_mbox == PCIE_FW_MASTER_M &&
5931 (pcie_fw & PCIE_FW_MASTER_VLD_F))
5932 master_mbox = PCIE_FW_MASTER_G(pcie_fw);
5941 * t4_fw_bye - end communication with FW
5942 * @adap: the adapter
5943 * @mbox: mailbox to use for the FW command
5945 * Issues a command to terminate communication with FW.
5947 int t4_fw_bye(struct adapter *adap, unsigned int mbox)
5949 struct fw_bye_cmd c;
5951 memset(&c, 0, sizeof(c));
5952 INIT_CMD(c, BYE, WRITE);
5953 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
5957 * t4_init_cmd - ask FW to initialize the device
5958 * @adap: the adapter
5959 * @mbox: mailbox to use for the FW command
5961 * Issues a command to FW to partially initialize the device. This
5962 * performs initialization that generally doesn't depend on user input.
5964 int t4_early_init(struct adapter *adap, unsigned int mbox)
5966 struct fw_initialize_cmd c;
5968 memset(&c, 0, sizeof(c));
5969 INIT_CMD(c, INITIALIZE, WRITE);
5970 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
5974 * t4_fw_reset - issue a reset to FW
5975 * @adap: the adapter
5976 * @mbox: mailbox to use for the FW command
5977 * @reset: specifies the type of reset to perform
5979 * Issues a reset command of the specified type to FW.
5981 int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset)
5983 struct fw_reset_cmd c;
5985 memset(&c, 0, sizeof(c));
5986 INIT_CMD(c, RESET, WRITE);
5987 c.val = cpu_to_be32(reset);
5988 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
5992 * t4_fw_halt - issue a reset/halt to FW and put uP into RESET
5993 * @adap: the adapter
5994 * @mbox: mailbox to use for the FW RESET command (if desired)
5995 * @force: force uP into RESET even if FW RESET command fails
5997 * Issues a RESET command to firmware (if desired) with a HALT indication
5998 * and then puts the microprocessor into RESET state. The RESET command
5999 * will only be issued if a legitimate mailbox is provided (mbox <=
6000 * PCIE_FW_MASTER_M).
6002 * This is generally used in order for the host to safely manipulate the
6003 * adapter without fear of conflicting with whatever the firmware might
6004 * be doing. The only way out of this state is to RESTART the firmware
6007 static int t4_fw_halt(struct adapter *adap, unsigned int mbox, int force)
6012 * If a legitimate mailbox is provided, issue a RESET command
6013 * with a HALT indication.
6015 if (mbox <= PCIE_FW_MASTER_M) {
6016 struct fw_reset_cmd c;
6018 memset(&c, 0, sizeof(c));
6019 INIT_CMD(c, RESET, WRITE);
6020 c.val = cpu_to_be32(PIORST_F | PIORSTMODE_F);
6021 c.halt_pkd = cpu_to_be32(FW_RESET_CMD_HALT_F);
6022 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
6026 * Normally we won't complete the operation if the firmware RESET
6027 * command fails but if our caller insists we'll go ahead and put the
6028 * uP into RESET. This can be useful if the firmware is hung or even
6029 * missing ... We'll have to take the risk of putting the uP into
6030 * RESET without the cooperation of firmware in that case.
6032 * We also force the firmware's HALT flag to be on in case we bypassed
6033 * the firmware RESET command above or we're dealing with old firmware
6034 * which doesn't have the HALT capability. This will serve as a flag
6035 * for the incoming firmware to know that it's coming out of a HALT
6036 * rather than a RESET ... if it's new enough to understand that ...
6038 if (ret == 0 || force) {
6039 t4_set_reg_field(adap, CIM_BOOT_CFG_A, UPCRST_F, UPCRST_F);
6040 t4_set_reg_field(adap, PCIE_FW_A, PCIE_FW_HALT_F,
6045 * And we always return the result of the firmware RESET command
6046 * even when we force the uP into RESET ...
6052 * t4_fw_restart - restart the firmware by taking the uP out of RESET
6053 * @adap: the adapter
6054 * @reset: if we want to do a RESET to restart things
6056 * Restart firmware previously halted by t4_fw_halt(). On successful
6057 * return the previous PF Master remains as the new PF Master and there
6058 * is no need to issue a new HELLO command, etc.
6060 * We do this in two ways:
6062 * 1. If we're dealing with newer firmware we'll simply want to take
6063 * the chip's microprocessor out of RESET. This will cause the
6064 * firmware to start up from its start vector. And then we'll loop
6065 * until the firmware indicates it's started again (PCIE_FW.HALT
6066 * reset to 0) or we timeout.
6068 * 2. If we're dealing with older firmware then we'll need to RESET
6069 * the chip since older firmware won't recognize the PCIE_FW.HALT
6070 * flag and automatically RESET itself on startup.
6072 static int t4_fw_restart(struct adapter *adap, unsigned int mbox, int reset)
6076 * Since we're directing the RESET instead of the firmware
6077 * doing it automatically, we need to clear the PCIE_FW.HALT
6080 t4_set_reg_field(adap, PCIE_FW_A, PCIE_FW_HALT_F, 0);
6083 * If we've been given a valid mailbox, first try to get the
6084 * firmware to do the RESET. If that works, great and we can
6085 * return success. Otherwise, if we haven't been given a
6086 * valid mailbox or the RESET command failed, fall back to
6087 * hitting the chip with a hammer.
6089 if (mbox <= PCIE_FW_MASTER_M) {
6090 t4_set_reg_field(adap, CIM_BOOT_CFG_A, UPCRST_F, 0);
6092 if (t4_fw_reset(adap, mbox,
6093 PIORST_F | PIORSTMODE_F) == 0)
6097 t4_write_reg(adap, PL_RST_A, PIORST_F | PIORSTMODE_F);
6102 t4_set_reg_field(adap, CIM_BOOT_CFG_A, UPCRST_F, 0);
6103 for (ms = 0; ms < FW_CMD_MAX_TIMEOUT; ) {
6104 if (!(t4_read_reg(adap, PCIE_FW_A) & PCIE_FW_HALT_F))
6115 * t4_fw_upgrade - perform all of the steps necessary to upgrade FW
6116 * @adap: the adapter
6117 * @mbox: mailbox to use for the FW RESET command (if desired)
6118 * @fw_data: the firmware image to write
6120 * @force: force upgrade even if firmware doesn't cooperate
6122 * Perform all of the steps necessary for upgrading an adapter's
6123 * firmware image. Normally this requires the cooperation of the
6124 * existing firmware in order to halt all existing activities
6125 * but if an invalid mailbox token is passed in we skip that step
6126 * (though we'll still put the adapter microprocessor into RESET in
6129 * On successful return the new firmware will have been loaded and
6130 * the adapter will have been fully RESET losing all previous setup
6131 * state. On unsuccessful return the adapter may be completely hosed ...
6132 * positive errno indicates that the adapter is ~probably~ intact, a
6133 * negative errno indicates that things are looking bad ...
6135 int t4_fw_upgrade(struct adapter *adap, unsigned int mbox,
6136 const u8 *fw_data, unsigned int size, int force)
6138 const struct fw_hdr *fw_hdr = (const struct fw_hdr *)fw_data;
6141 if (!t4_fw_matches_chip(adap, fw_hdr))
6144 ret = t4_fw_halt(adap, mbox, force);
6145 if (ret < 0 && !force)
6148 ret = t4_load_fw(adap, fw_data, size);
6153 * Older versions of the firmware don't understand the new
6154 * PCIE_FW.HALT flag and so won't know to perform a RESET when they
6155 * restart. So for newly loaded older firmware we'll have to do the
6156 * RESET for it so it starts up on a clean slate. We can tell if
6157 * the newly loaded firmware will handle this right by checking
6158 * its header flags to see if it advertises the capability.
6160 reset = ((be32_to_cpu(fw_hdr->flags) & FW_HDR_FLAGS_RESET_HALT) == 0);
6161 return t4_fw_restart(adap, mbox, reset);
6165 * t4_fl_pkt_align - return the fl packet alignment
6166 * @adap: the adapter
6168 * T4 has a single field to specify the packing and padding boundary.
6169 * T5 onwards has separate fields for this and hence the alignment for
6170 * next packet offset is maximum of these two.
6173 int t4_fl_pkt_align(struct adapter *adap)
6175 u32 sge_control, sge_control2;
6176 unsigned int ingpadboundary, ingpackboundary, fl_align, ingpad_shift;
6178 sge_control = t4_read_reg(adap, SGE_CONTROL_A);
6180 /* T4 uses a single control field to specify both the PCIe Padding and
6181 * Packing Boundary. T5 introduced the ability to specify these
6182 * separately. The actual Ingress Packet Data alignment boundary
6183 * within Packed Buffer Mode is the maximum of these two
6184 * specifications. (Note that it makes no real practical sense to
6185 * have the Pading Boudary be larger than the Packing Boundary but you
6186 * could set the chip up that way and, in fact, legacy T4 code would
6187 * end doing this because it would initialize the Padding Boundary and
6188 * leave the Packing Boundary initialized to 0 (16 bytes).)
6189 * Padding Boundary values in T6 starts from 8B,
6190 * where as it is 32B for T4 and T5.
6192 if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5)
6193 ingpad_shift = INGPADBOUNDARY_SHIFT_X;
6195 ingpad_shift = T6_INGPADBOUNDARY_SHIFT_X;
6197 ingpadboundary = 1 << (INGPADBOUNDARY_G(sge_control) + ingpad_shift);
6199 fl_align = ingpadboundary;
6200 if (!is_t4(adap->params.chip)) {
6201 /* T5 has a weird interpretation of one of the PCIe Packing
6202 * Boundary values. No idea why ...
6204 sge_control2 = t4_read_reg(adap, SGE_CONTROL2_A);
6205 ingpackboundary = INGPACKBOUNDARY_G(sge_control2);
6206 if (ingpackboundary == INGPACKBOUNDARY_16B_X)
6207 ingpackboundary = 16;
6209 ingpackboundary = 1 << (ingpackboundary +
6210 INGPACKBOUNDARY_SHIFT_X);
6212 fl_align = max(ingpadboundary, ingpackboundary);
6218 * t4_fixup_host_params - fix up host-dependent parameters
6219 * @adap: the adapter
6220 * @page_size: the host's Base Page Size
6221 * @cache_line_size: the host's Cache Line Size
6223 * Various registers in T4 contain values which are dependent on the
6224 * host's Base Page and Cache Line Sizes. This function will fix all of
6225 * those registers with the appropriate values as passed in ...
6227 int t4_fixup_host_params(struct adapter *adap, unsigned int page_size,
6228 unsigned int cache_line_size)
6230 unsigned int page_shift = fls(page_size) - 1;
6231 unsigned int sge_hps = page_shift - 10;
6232 unsigned int stat_len = cache_line_size > 64 ? 128 : 64;
6233 unsigned int fl_align = cache_line_size < 32 ? 32 : cache_line_size;
6234 unsigned int fl_align_log = fls(fl_align) - 1;
6235 unsigned int ingpad;
6237 t4_write_reg(adap, SGE_HOST_PAGE_SIZE_A,
6238 HOSTPAGESIZEPF0_V(sge_hps) |
6239 HOSTPAGESIZEPF1_V(sge_hps) |
6240 HOSTPAGESIZEPF2_V(sge_hps) |
6241 HOSTPAGESIZEPF3_V(sge_hps) |
6242 HOSTPAGESIZEPF4_V(sge_hps) |
6243 HOSTPAGESIZEPF5_V(sge_hps) |
6244 HOSTPAGESIZEPF6_V(sge_hps) |
6245 HOSTPAGESIZEPF7_V(sge_hps));
6247 if (is_t4(adap->params.chip)) {
6248 t4_set_reg_field(adap, SGE_CONTROL_A,
6249 INGPADBOUNDARY_V(INGPADBOUNDARY_M) |
6250 EGRSTATUSPAGESIZE_F,
6251 INGPADBOUNDARY_V(fl_align_log -
6252 INGPADBOUNDARY_SHIFT_X) |
6253 EGRSTATUSPAGESIZE_V(stat_len != 64));
6255 /* T5 introduced the separation of the Free List Padding and
6256 * Packing Boundaries. Thus, we can select a smaller Padding
6257 * Boundary to avoid uselessly chewing up PCIe Link and Memory
6258 * Bandwidth, and use a Packing Boundary which is large enough
6259 * to avoid false sharing between CPUs, etc.
6261 * For the PCI Link, the smaller the Padding Boundary the
6262 * better. For the Memory Controller, a smaller Padding
6263 * Boundary is better until we cross under the Memory Line
6264 * Size (the minimum unit of transfer to/from Memory). If we
6265 * have a Padding Boundary which is smaller than the Memory
6266 * Line Size, that'll involve a Read-Modify-Write cycle on the
6267 * Memory Controller which is never good. For T5 the smallest
6268 * Padding Boundary which we can select is 32 bytes which is
6269 * larger than any known Memory Controller Line Size so we'll
6272 * T5 has a different interpretation of the "0" value for the
6273 * Packing Boundary. This corresponds to 16 bytes instead of
6274 * the expected 32 bytes. We never have a Packing Boundary
6275 * less than 32 bytes so we can't use that special value but
6276 * on the other hand, if we wanted 32 bytes, the best we can
6277 * really do is 64 bytes.
6279 if (fl_align <= 32) {
6284 if (is_t5(adap->params.chip))
6285 ingpad = INGPCIEBOUNDARY_32B_X;
6287 ingpad = T6_INGPADBOUNDARY_32B_X;
6289 t4_set_reg_field(adap, SGE_CONTROL_A,
6290 INGPADBOUNDARY_V(INGPADBOUNDARY_M) |
6291 EGRSTATUSPAGESIZE_F,
6292 INGPADBOUNDARY_V(ingpad) |
6293 EGRSTATUSPAGESIZE_V(stat_len != 64));
6294 t4_set_reg_field(adap, SGE_CONTROL2_A,
6295 INGPACKBOUNDARY_V(INGPACKBOUNDARY_M),
6296 INGPACKBOUNDARY_V(fl_align_log -
6297 INGPACKBOUNDARY_SHIFT_X));
6300 * Adjust various SGE Free List Host Buffer Sizes.
6302 * This is something of a crock since we're using fixed indices into
6303 * the array which are also known by the sge.c code and the T4
6304 * Firmware Configuration File. We need to come up with a much better
6305 * approach to managing this array. For now, the first four entries
6310 * 2: Buffer size corresponding to 1500 byte MTU (unpacked mode)
6311 * 3: Buffer size corresponding to 9000 byte MTU (unpacked mode)
6313 * For the single-MTU buffers in unpacked mode we need to include
6314 * space for the SGE Control Packet Shift, 14 byte Ethernet header,
6315 * possible 4 byte VLAN tag, all rounded up to the next Ingress Packet
6316 * Padding boundary. All of these are accommodated in the Factory
6317 * Default Firmware Configuration File but we need to adjust it for
6318 * this host's cache line size.
6320 t4_write_reg(adap, SGE_FL_BUFFER_SIZE0_A, page_size);
6321 t4_write_reg(adap, SGE_FL_BUFFER_SIZE2_A,
6322 (t4_read_reg(adap, SGE_FL_BUFFER_SIZE2_A) + fl_align-1)
6324 t4_write_reg(adap, SGE_FL_BUFFER_SIZE3_A,
6325 (t4_read_reg(adap, SGE_FL_BUFFER_SIZE3_A) + fl_align-1)
6328 t4_write_reg(adap, ULP_RX_TDDP_PSZ_A, HPZ0_V(page_shift - 12));
6334 * t4_fw_initialize - ask FW to initialize the device
6335 * @adap: the adapter
6336 * @mbox: mailbox to use for the FW command
6338 * Issues a command to FW to partially initialize the device. This
6339 * performs initialization that generally doesn't depend on user input.
6341 int t4_fw_initialize(struct adapter *adap, unsigned int mbox)
6343 struct fw_initialize_cmd c;
6345 memset(&c, 0, sizeof(c));
6346 INIT_CMD(c, INITIALIZE, WRITE);
6347 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
6351 * t4_query_params_rw - query FW or device parameters
6352 * @adap: the adapter
6353 * @mbox: mailbox to use for the FW command
6356 * @nparams: the number of parameters
6357 * @params: the parameter names
6358 * @val: the parameter values
6359 * @rw: Write and read flag
6361 * Reads the value of FW or device parameters. Up to 7 parameters can be
6364 int t4_query_params_rw(struct adapter *adap, unsigned int mbox, unsigned int pf,
6365 unsigned int vf, unsigned int nparams, const u32 *params,
6369 struct fw_params_cmd c;
6370 __be32 *p = &c.param[0].mnem;
6375 memset(&c, 0, sizeof(c));
6376 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_PARAMS_CMD) |
6377 FW_CMD_REQUEST_F | FW_CMD_READ_F |
6378 FW_PARAMS_CMD_PFN_V(pf) |
6379 FW_PARAMS_CMD_VFN_V(vf));
6380 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
6382 for (i = 0; i < nparams; i++) {
6383 *p++ = cpu_to_be32(*params++);
6385 *p = cpu_to_be32(*(val + i));
6389 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
6391 for (i = 0, p = &c.param[0].val; i < nparams; i++, p += 2)
6392 *val++ = be32_to_cpu(*p);
6396 int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
6397 unsigned int vf, unsigned int nparams, const u32 *params,
6400 return t4_query_params_rw(adap, mbox, pf, vf, nparams, params, val, 0);
6404 * t4_set_params_timeout - sets FW or device parameters
6405 * @adap: the adapter
6406 * @mbox: mailbox to use for the FW command
6409 * @nparams: the number of parameters
6410 * @params: the parameter names
6411 * @val: the parameter values
6412 * @timeout: the timeout time
6414 * Sets the value of FW or device parameters. Up to 7 parameters can be
6415 * specified at once.
6417 int t4_set_params_timeout(struct adapter *adap, unsigned int mbox,
6418 unsigned int pf, unsigned int vf,
6419 unsigned int nparams, const u32 *params,
6420 const u32 *val, int timeout)
6422 struct fw_params_cmd c;
6423 __be32 *p = &c.param[0].mnem;
6428 memset(&c, 0, sizeof(c));
6429 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_PARAMS_CMD) |
6430 FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
6431 FW_PARAMS_CMD_PFN_V(pf) |
6432 FW_PARAMS_CMD_VFN_V(vf));
6433 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
6436 *p++ = cpu_to_be32(*params++);
6437 *p++ = cpu_to_be32(*val++);
6440 return t4_wr_mbox_timeout(adap, mbox, &c, sizeof(c), NULL, timeout);
6444 * t4_set_params - sets FW or device parameters
6445 * @adap: the adapter
6446 * @mbox: mailbox to use for the FW command
6449 * @nparams: the number of parameters
6450 * @params: the parameter names
6451 * @val: the parameter values
6453 * Sets the value of FW or device parameters. Up to 7 parameters can be
6454 * specified at once.
6456 int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
6457 unsigned int vf, unsigned int nparams, const u32 *params,
6460 return t4_set_params_timeout(adap, mbox, pf, vf, nparams, params, val,
6461 FW_CMD_MAX_TIMEOUT);
6465 * t4_cfg_pfvf - configure PF/VF resource limits
6466 * @adap: the adapter
6467 * @mbox: mailbox to use for the FW command
6468 * @pf: the PF being configured
6469 * @vf: the VF being configured
6470 * @txq: the max number of egress queues
6471 * @txq_eth_ctrl: the max number of egress Ethernet or control queues
6472 * @rxqi: the max number of interrupt-capable ingress queues
6473 * @rxq: the max number of interruptless ingress queues
6474 * @tc: the PCI traffic class
6475 * @vi: the max number of virtual interfaces
6476 * @cmask: the channel access rights mask for the PF/VF
6477 * @pmask: the port access rights mask for the PF/VF
6478 * @nexact: the maximum number of exact MPS filters
6479 * @rcaps: read capabilities
6480 * @wxcaps: write/execute capabilities
6482 * Configures resource limits and capabilities for a physical or virtual
6485 int t4_cfg_pfvf(struct adapter *adap, unsigned int mbox, unsigned int pf,
6486 unsigned int vf, unsigned int txq, unsigned int txq_eth_ctrl,
6487 unsigned int rxqi, unsigned int rxq, unsigned int tc,
6488 unsigned int vi, unsigned int cmask, unsigned int pmask,
6489 unsigned int nexact, unsigned int rcaps, unsigned int wxcaps)
6491 struct fw_pfvf_cmd c;
6493 memset(&c, 0, sizeof(c));
6494 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_PFVF_CMD) | FW_CMD_REQUEST_F |
6495 FW_CMD_WRITE_F | FW_PFVF_CMD_PFN_V(pf) |
6496 FW_PFVF_CMD_VFN_V(vf));
6497 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
6498 c.niqflint_niq = cpu_to_be32(FW_PFVF_CMD_NIQFLINT_V(rxqi) |
6499 FW_PFVF_CMD_NIQ_V(rxq));
6500 c.type_to_neq = cpu_to_be32(FW_PFVF_CMD_CMASK_V(cmask) |
6501 FW_PFVF_CMD_PMASK_V(pmask) |
6502 FW_PFVF_CMD_NEQ_V(txq));
6503 c.tc_to_nexactf = cpu_to_be32(FW_PFVF_CMD_TC_V(tc) |
6504 FW_PFVF_CMD_NVI_V(vi) |
6505 FW_PFVF_CMD_NEXACTF_V(nexact));
6506 c.r_caps_to_nethctrl = cpu_to_be32(FW_PFVF_CMD_R_CAPS_V(rcaps) |
6507 FW_PFVF_CMD_WX_CAPS_V(wxcaps) |
6508 FW_PFVF_CMD_NETHCTRL_V(txq_eth_ctrl));
6509 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
6513 * t4_alloc_vi - allocate a virtual interface
6514 * @adap: the adapter
6515 * @mbox: mailbox to use for the FW command
6516 * @port: physical port associated with the VI
6517 * @pf: the PF owning the VI
6518 * @vf: the VF owning the VI
6519 * @nmac: number of MAC addresses needed (1 to 5)
6520 * @mac: the MAC addresses of the VI
6521 * @rss_size: size of RSS table slice associated with this VI
6523 * Allocates a virtual interface for the given physical port. If @mac is
6524 * not %NULL it contains the MAC addresses of the VI as assigned by FW.
6525 * @mac should be large enough to hold @nmac Ethernet addresses, they are
6526 * stored consecutively so the space needed is @nmac * 6 bytes.
6527 * Returns a negative error number or the non-negative VI id.
6529 int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port,
6530 unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac,
6531 unsigned int *rss_size)
6536 memset(&c, 0, sizeof(c));
6537 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_VI_CMD) | FW_CMD_REQUEST_F |
6538 FW_CMD_WRITE_F | FW_CMD_EXEC_F |
6539 FW_VI_CMD_PFN_V(pf) | FW_VI_CMD_VFN_V(vf));
6540 c.alloc_to_len16 = cpu_to_be32(FW_VI_CMD_ALLOC_F | FW_LEN16(c));
6541 c.portid_pkd = FW_VI_CMD_PORTID_V(port);
6544 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
6549 memcpy(mac, c.mac, sizeof(c.mac));
6552 memcpy(mac + 24, c.nmac3, sizeof(c.nmac3));
6554 memcpy(mac + 18, c.nmac2, sizeof(c.nmac2));
6556 memcpy(mac + 12, c.nmac1, sizeof(c.nmac1));
6558 memcpy(mac + 6, c.nmac0, sizeof(c.nmac0));
6562 *rss_size = FW_VI_CMD_RSSSIZE_G(be16_to_cpu(c.rsssize_pkd));
6563 return FW_VI_CMD_VIID_G(be16_to_cpu(c.type_viid));
6567 * t4_free_vi - free a virtual interface
6568 * @adap: the adapter
6569 * @mbox: mailbox to use for the FW command
6570 * @pf: the PF owning the VI
6571 * @vf: the VF owning the VI
6572 * @viid: virtual interface identifiler
6574 * Free a previously allocated virtual interface.
6576 int t4_free_vi(struct adapter *adap, unsigned int mbox, unsigned int pf,
6577 unsigned int vf, unsigned int viid)
6581 memset(&c, 0, sizeof(c));
6582 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_VI_CMD) |
6585 FW_VI_CMD_PFN_V(pf) |
6586 FW_VI_CMD_VFN_V(vf));
6587 c.alloc_to_len16 = cpu_to_be32(FW_VI_CMD_FREE_F | FW_LEN16(c));
6588 c.type_viid = cpu_to_be16(FW_VI_CMD_VIID_V(viid));
6590 return t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
6594 * t4_set_rxmode - set Rx properties of a virtual interface
6595 * @adap: the adapter
6596 * @mbox: mailbox to use for the FW command
6598 * @mtu: the new MTU or -1
6599 * @promisc: 1 to enable promiscuous mode, 0 to disable it, -1 no change
6600 * @all_multi: 1 to enable all-multi mode, 0 to disable it, -1 no change
6601 * @bcast: 1 to enable broadcast Rx, 0 to disable it, -1 no change
6602 * @vlanex: 1 to enable HW VLAN extraction, 0 to disable it, -1 no change
6603 * @sleep_ok: if true we may sleep while awaiting command completion
6605 * Sets Rx properties of a virtual interface.
6607 int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid,
6608 int mtu, int promisc, int all_multi, int bcast, int vlanex,
6611 struct fw_vi_rxmode_cmd c;
6613 /* convert to FW values */
6615 mtu = FW_RXMODE_MTU_NO_CHG;
6617 promisc = FW_VI_RXMODE_CMD_PROMISCEN_M;
6619 all_multi = FW_VI_RXMODE_CMD_ALLMULTIEN_M;
6621 bcast = FW_VI_RXMODE_CMD_BROADCASTEN_M;
6623 vlanex = FW_VI_RXMODE_CMD_VLANEXEN_M;
6625 memset(&c, 0, sizeof(c));
6626 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_RXMODE_CMD) |
6627 FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
6628 FW_VI_RXMODE_CMD_VIID_V(viid));
6629 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
6631 cpu_to_be32(FW_VI_RXMODE_CMD_MTU_V(mtu) |
6632 FW_VI_RXMODE_CMD_PROMISCEN_V(promisc) |
6633 FW_VI_RXMODE_CMD_ALLMULTIEN_V(all_multi) |
6634 FW_VI_RXMODE_CMD_BROADCASTEN_V(bcast) |
6635 FW_VI_RXMODE_CMD_VLANEXEN_V(vlanex));
6636 return t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), NULL, sleep_ok);
6640 * t4_alloc_mac_filt - allocates exact-match filters for MAC addresses
6641 * @adap: the adapter
6642 * @mbox: mailbox to use for the FW command
6644 * @free: if true any existing filters for this VI id are first removed
6645 * @naddr: the number of MAC addresses to allocate filters for (up to 7)
6646 * @addr: the MAC address(es)
6647 * @idx: where to store the index of each allocated filter
6648 * @hash: pointer to hash address filter bitmap
6649 * @sleep_ok: call is allowed to sleep
6651 * Allocates an exact-match filter for each of the supplied addresses and
6652 * sets it to the corresponding address. If @idx is not %NULL it should
6653 * have at least @naddr entries, each of which will be set to the index of
6654 * the filter allocated for the corresponding MAC address. If a filter
6655 * could not be allocated for an address its index is set to 0xffff.
6656 * If @hash is not %NULL addresses that fail to allocate an exact filter
6657 * are hashed and update the hash filter bitmap pointed at by @hash.
6659 * Returns a negative error number or the number of filters allocated.
6661 int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox,
6662 unsigned int viid, bool free, unsigned int naddr,
6663 const u8 **addr, u16 *idx, u64 *hash, bool sleep_ok)
6665 int offset, ret = 0;
6666 struct fw_vi_mac_cmd c;
6667 unsigned int nfilters = 0;
6668 unsigned int max_naddr = adap->params.arch.mps_tcam_size;
6669 unsigned int rem = naddr;
6671 if (naddr > max_naddr)
6674 for (offset = 0; offset < naddr ; /**/) {
6675 unsigned int fw_naddr = (rem < ARRAY_SIZE(c.u.exact) ?
6676 rem : ARRAY_SIZE(c.u.exact));
6677 size_t len16 = DIV_ROUND_UP(offsetof(struct fw_vi_mac_cmd,
6678 u.exact[fw_naddr]), 16);
6679 struct fw_vi_mac_exact *p;
6682 memset(&c, 0, sizeof(c));
6683 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD) |
6686 FW_CMD_EXEC_V(free) |
6687 FW_VI_MAC_CMD_VIID_V(viid));
6688 c.freemacs_to_len16 =
6689 cpu_to_be32(FW_VI_MAC_CMD_FREEMACS_V(free) |
6690 FW_CMD_LEN16_V(len16));
6692 for (i = 0, p = c.u.exact; i < fw_naddr; i++, p++) {
6694 cpu_to_be16(FW_VI_MAC_CMD_VALID_F |
6695 FW_VI_MAC_CMD_IDX_V(
6696 FW_VI_MAC_ADD_MAC));
6697 memcpy(p->macaddr, addr[offset + i],
6698 sizeof(p->macaddr));
6701 /* It's okay if we run out of space in our MAC address arena.
6702 * Some of the addresses we submit may get stored so we need
6703 * to run through the reply to see what the results were ...
6705 ret = t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), &c, sleep_ok);
6706 if (ret && ret != -FW_ENOMEM)
6709 for (i = 0, p = c.u.exact; i < fw_naddr; i++, p++) {
6710 u16 index = FW_VI_MAC_CMD_IDX_G(
6711 be16_to_cpu(p->valid_to_idx));
6714 idx[offset + i] = (index >= max_naddr ?
6716 if (index < max_naddr)
6720 hash_mac_addr(addr[offset + i]));
6728 if (ret == 0 || ret == -FW_ENOMEM)
6734 * t4_free_mac_filt - frees exact-match filters of given MAC addresses
6735 * @adap: the adapter
6736 * @mbox: mailbox to use for the FW command
6738 * @naddr: the number of MAC addresses to allocate filters for (up to 7)
6739 * @addr: the MAC address(es)
6740 * @sleep_ok: call is allowed to sleep
6742 * Frees the exact-match filter for each of the supplied addresses
6744 * Returns a negative error number or the number of filters freed.
6746 int t4_free_mac_filt(struct adapter *adap, unsigned int mbox,
6747 unsigned int viid, unsigned int naddr,
6748 const u8 **addr, bool sleep_ok)
6750 int offset, ret = 0;
6751 struct fw_vi_mac_cmd c;
6752 unsigned int nfilters = 0;
6753 unsigned int max_naddr = is_t4(adap->params.chip) ?
6754 NUM_MPS_CLS_SRAM_L_INSTANCES :
6755 NUM_MPS_T5_CLS_SRAM_L_INSTANCES;
6756 unsigned int rem = naddr;
6758 if (naddr > max_naddr)
6761 for (offset = 0; offset < (int)naddr ; /**/) {
6762 unsigned int fw_naddr = (rem < ARRAY_SIZE(c.u.exact)
6764 : ARRAY_SIZE(c.u.exact));
6765 size_t len16 = DIV_ROUND_UP(offsetof(struct fw_vi_mac_cmd,
6766 u.exact[fw_naddr]), 16);
6767 struct fw_vi_mac_exact *p;
6770 memset(&c, 0, sizeof(c));
6771 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD) |
6775 FW_VI_MAC_CMD_VIID_V(viid));
6776 c.freemacs_to_len16 =
6777 cpu_to_be32(FW_VI_MAC_CMD_FREEMACS_V(0) |
6778 FW_CMD_LEN16_V(len16));
6780 for (i = 0, p = c.u.exact; i < (int)fw_naddr; i++, p++) {
6781 p->valid_to_idx = cpu_to_be16(
6782 FW_VI_MAC_CMD_VALID_F |
6783 FW_VI_MAC_CMD_IDX_V(FW_VI_MAC_MAC_BASED_FREE));
6784 memcpy(p->macaddr, addr[offset+i], sizeof(p->macaddr));
6787 ret = t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), &c, sleep_ok);
6791 for (i = 0, p = c.u.exact; i < fw_naddr; i++, p++) {
6792 u16 index = FW_VI_MAC_CMD_IDX_G(
6793 be16_to_cpu(p->valid_to_idx));
6795 if (index < max_naddr)
6809 * t4_change_mac - modifies the exact-match filter for a MAC address
6810 * @adap: the adapter
6811 * @mbox: mailbox to use for the FW command
6813 * @idx: index of existing filter for old value of MAC address, or -1
6814 * @addr: the new MAC address value
6815 * @persist: whether a new MAC allocation should be persistent
6816 * @add_smt: if true also add the address to the HW SMT
6818 * Modifies an exact-match filter and sets it to the new MAC address.
6819 * Note that in general it is not possible to modify the value of a given
6820 * filter so the generic way to modify an address filter is to free the one
6821 * being used by the old address value and allocate a new filter for the
6822 * new address value. @idx can be -1 if the address is a new addition.
6824 * Returns a negative error number or the index of the filter with the new
6827 int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid,
6828 int idx, const u8 *addr, bool persist, bool add_smt)
6831 struct fw_vi_mac_cmd c;
6832 struct fw_vi_mac_exact *p = c.u.exact;
6833 unsigned int max_mac_addr = adap->params.arch.mps_tcam_size;
6835 if (idx < 0) /* new allocation */
6836 idx = persist ? FW_VI_MAC_ADD_PERSIST_MAC : FW_VI_MAC_ADD_MAC;
6837 mode = add_smt ? FW_VI_MAC_SMT_AND_MPSTCAM : FW_VI_MAC_MPS_TCAM_ENTRY;
6839 memset(&c, 0, sizeof(c));
6840 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD) |
6841 FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
6842 FW_VI_MAC_CMD_VIID_V(viid));
6843 c.freemacs_to_len16 = cpu_to_be32(FW_CMD_LEN16_V(1));
6844 p->valid_to_idx = cpu_to_be16(FW_VI_MAC_CMD_VALID_F |
6845 FW_VI_MAC_CMD_SMAC_RESULT_V(mode) |
6846 FW_VI_MAC_CMD_IDX_V(idx));
6847 memcpy(p->macaddr, addr, sizeof(p->macaddr));
6849 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
6851 ret = FW_VI_MAC_CMD_IDX_G(be16_to_cpu(p->valid_to_idx));
6852 if (ret >= max_mac_addr)
6859 * t4_set_addr_hash - program the MAC inexact-match hash filter
6860 * @adap: the adapter
6861 * @mbox: mailbox to use for the FW command
6863 * @ucast: whether the hash filter should also match unicast addresses
6864 * @vec: the value to be written to the hash filter
6865 * @sleep_ok: call is allowed to sleep
6867 * Sets the 64-bit inexact-match hash filter for a virtual interface.
6869 int t4_set_addr_hash(struct adapter *adap, unsigned int mbox, unsigned int viid,
6870 bool ucast, u64 vec, bool sleep_ok)
6872 struct fw_vi_mac_cmd c;
6874 memset(&c, 0, sizeof(c));
6875 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD) |
6876 FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
6877 FW_VI_ENABLE_CMD_VIID_V(viid));
6878 c.freemacs_to_len16 = cpu_to_be32(FW_VI_MAC_CMD_HASHVECEN_F |
6879 FW_VI_MAC_CMD_HASHUNIEN_V(ucast) |
6881 c.u.hash.hashvec = cpu_to_be64(vec);
6882 return t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), NULL, sleep_ok);
6886 * t4_enable_vi_params - enable/disable a virtual interface
6887 * @adap: the adapter
6888 * @mbox: mailbox to use for the FW command
6890 * @rx_en: 1=enable Rx, 0=disable Rx
6891 * @tx_en: 1=enable Tx, 0=disable Tx
6892 * @dcb_en: 1=enable delivery of Data Center Bridging messages.
6894 * Enables/disables a virtual interface. Note that setting DCB Enable
6895 * only makes sense when enabling a Virtual Interface ...
6897 int t4_enable_vi_params(struct adapter *adap, unsigned int mbox,
6898 unsigned int viid, bool rx_en, bool tx_en, bool dcb_en)
6900 struct fw_vi_enable_cmd c;
6902 memset(&c, 0, sizeof(c));
6903 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_ENABLE_CMD) |
6904 FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
6905 FW_VI_ENABLE_CMD_VIID_V(viid));
6906 c.ien_to_len16 = cpu_to_be32(FW_VI_ENABLE_CMD_IEN_V(rx_en) |
6907 FW_VI_ENABLE_CMD_EEN_V(tx_en) |
6908 FW_VI_ENABLE_CMD_DCB_INFO_V(dcb_en) |
6910 return t4_wr_mbox_ns(adap, mbox, &c, sizeof(c), NULL);
6914 * t4_enable_vi - enable/disable a virtual interface
6915 * @adap: the adapter
6916 * @mbox: mailbox to use for the FW command
6918 * @rx_en: 1=enable Rx, 0=disable Rx
6919 * @tx_en: 1=enable Tx, 0=disable Tx
6921 * Enables/disables a virtual interface.
6923 int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid,
6924 bool rx_en, bool tx_en)
6926 return t4_enable_vi_params(adap, mbox, viid, rx_en, tx_en, 0);
6930 * t4_identify_port - identify a VI's port by blinking its LED
6931 * @adap: the adapter
6932 * @mbox: mailbox to use for the FW command
6934 * @nblinks: how many times to blink LED at 2.5 Hz
6936 * Identifies a VI's port by blinking its LED.
6938 int t4_identify_port(struct adapter *adap, unsigned int mbox, unsigned int viid,
6939 unsigned int nblinks)
6941 struct fw_vi_enable_cmd c;
6943 memset(&c, 0, sizeof(c));
6944 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_ENABLE_CMD) |
6945 FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
6946 FW_VI_ENABLE_CMD_VIID_V(viid));
6947 c.ien_to_len16 = cpu_to_be32(FW_VI_ENABLE_CMD_LED_F | FW_LEN16(c));
6948 c.blinkdur = cpu_to_be16(nblinks);
6949 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
6953 * t4_iq_stop - stop an ingress queue and its FLs
6954 * @adap: the adapter
6955 * @mbox: mailbox to use for the FW command
6956 * @pf: the PF owning the queues
6957 * @vf: the VF owning the queues
6958 * @iqtype: the ingress queue type (FW_IQ_TYPE_FL_INT_CAP, etc.)
6959 * @iqid: ingress queue id
6960 * @fl0id: FL0 queue id or 0xffff if no attached FL0
6961 * @fl1id: FL1 queue id or 0xffff if no attached FL1
6963 * Stops an ingress queue and its associated FLs, if any. This causes
6964 * any current or future data/messages destined for these queues to be
6967 int t4_iq_stop(struct adapter *adap, unsigned int mbox, unsigned int pf,
6968 unsigned int vf, unsigned int iqtype, unsigned int iqid,
6969 unsigned int fl0id, unsigned int fl1id)
6973 memset(&c, 0, sizeof(c));
6974 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_IQ_CMD) | FW_CMD_REQUEST_F |
6975 FW_CMD_EXEC_F | FW_IQ_CMD_PFN_V(pf) |
6976 FW_IQ_CMD_VFN_V(vf));
6977 c.alloc_to_len16 = cpu_to_be32(FW_IQ_CMD_IQSTOP_F | FW_LEN16(c));
6978 c.type_to_iqandstindex = cpu_to_be32(FW_IQ_CMD_TYPE_V(iqtype));
6979 c.iqid = cpu_to_be16(iqid);
6980 c.fl0id = cpu_to_be16(fl0id);
6981 c.fl1id = cpu_to_be16(fl1id);
6982 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
6986 * t4_iq_free - free an ingress queue and its FLs
6987 * @adap: the adapter
6988 * @mbox: mailbox to use for the FW command
6989 * @pf: the PF owning the queues
6990 * @vf: the VF owning the queues
6991 * @iqtype: the ingress queue type
6992 * @iqid: ingress queue id
6993 * @fl0id: FL0 queue id or 0xffff if no attached FL0
6994 * @fl1id: FL1 queue id or 0xffff if no attached FL1
6996 * Frees an ingress queue and its associated FLs, if any.
6998 int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
6999 unsigned int vf, unsigned int iqtype, unsigned int iqid,
7000 unsigned int fl0id, unsigned int fl1id)
7004 memset(&c, 0, sizeof(c));
7005 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_IQ_CMD) | FW_CMD_REQUEST_F |
7006 FW_CMD_EXEC_F | FW_IQ_CMD_PFN_V(pf) |
7007 FW_IQ_CMD_VFN_V(vf));
7008 c.alloc_to_len16 = cpu_to_be32(FW_IQ_CMD_FREE_F | FW_LEN16(c));
7009 c.type_to_iqandstindex = cpu_to_be32(FW_IQ_CMD_TYPE_V(iqtype));
7010 c.iqid = cpu_to_be16(iqid);
7011 c.fl0id = cpu_to_be16(fl0id);
7012 c.fl1id = cpu_to_be16(fl1id);
7013 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7017 * t4_eth_eq_free - free an Ethernet egress queue
7018 * @adap: the adapter
7019 * @mbox: mailbox to use for the FW command
7020 * @pf: the PF owning the queue
7021 * @vf: the VF owning the queue
7022 * @eqid: egress queue id
7024 * Frees an Ethernet egress queue.
7026 int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
7027 unsigned int vf, unsigned int eqid)
7029 struct fw_eq_eth_cmd c;
7031 memset(&c, 0, sizeof(c));
7032 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_EQ_ETH_CMD) |
7033 FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
7034 FW_EQ_ETH_CMD_PFN_V(pf) |
7035 FW_EQ_ETH_CMD_VFN_V(vf));
7036 c.alloc_to_len16 = cpu_to_be32(FW_EQ_ETH_CMD_FREE_F | FW_LEN16(c));
7037 c.eqid_pkd = cpu_to_be32(FW_EQ_ETH_CMD_EQID_V(eqid));
7038 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7042 * t4_ctrl_eq_free - free a control egress queue
7043 * @adap: the adapter
7044 * @mbox: mailbox to use for the FW command
7045 * @pf: the PF owning the queue
7046 * @vf: the VF owning the queue
7047 * @eqid: egress queue id
7049 * Frees a control egress queue.
7051 int t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
7052 unsigned int vf, unsigned int eqid)
7054 struct fw_eq_ctrl_cmd c;
7056 memset(&c, 0, sizeof(c));
7057 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_EQ_CTRL_CMD) |
7058 FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
7059 FW_EQ_CTRL_CMD_PFN_V(pf) |
7060 FW_EQ_CTRL_CMD_VFN_V(vf));
7061 c.alloc_to_len16 = cpu_to_be32(FW_EQ_CTRL_CMD_FREE_F | FW_LEN16(c));
7062 c.cmpliqid_eqid = cpu_to_be32(FW_EQ_CTRL_CMD_EQID_V(eqid));
7063 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7067 * t4_ofld_eq_free - free an offload egress queue
7068 * @adap: the adapter
7069 * @mbox: mailbox to use for the FW command
7070 * @pf: the PF owning the queue
7071 * @vf: the VF owning the queue
7072 * @eqid: egress queue id
7074 * Frees a control egress queue.
7076 int t4_ofld_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
7077 unsigned int vf, unsigned int eqid)
7079 struct fw_eq_ofld_cmd c;
7081 memset(&c, 0, sizeof(c));
7082 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_EQ_OFLD_CMD) |
7083 FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
7084 FW_EQ_OFLD_CMD_PFN_V(pf) |
7085 FW_EQ_OFLD_CMD_VFN_V(vf));
7086 c.alloc_to_len16 = cpu_to_be32(FW_EQ_OFLD_CMD_FREE_F | FW_LEN16(c));
7087 c.eqid_pkd = cpu_to_be32(FW_EQ_OFLD_CMD_EQID_V(eqid));
7088 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7092 * t4_handle_fw_rpl - process a FW reply message
7093 * @adap: the adapter
7094 * @rpl: start of the FW message
7096 * Processes a FW message, such as link state change messages.
7098 int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl)
7100 u8 opcode = *(const u8 *)rpl;
7102 if (opcode == FW_PORT_CMD) { /* link/module state change message */
7103 int speed = 0, fc = 0;
7104 const struct fw_port_cmd *p = (void *)rpl;
7105 int chan = FW_PORT_CMD_PORTID_G(be32_to_cpu(p->op_to_portid));
7106 int port = adap->chan_map[chan];
7107 struct port_info *pi = adap2pinfo(adap, port);
7108 struct link_config *lc = &pi->link_cfg;
7109 u32 stat = be32_to_cpu(p->u.info.lstatus_to_modtype);
7110 int link_ok = (stat & FW_PORT_CMD_LSTATUS_F) != 0;
7111 u32 mod = FW_PORT_CMD_MODTYPE_G(stat);
7113 if (stat & FW_PORT_CMD_RXPAUSE_F)
7115 if (stat & FW_PORT_CMD_TXPAUSE_F)
7117 if (stat & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_100M))
7119 else if (stat & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_1G))
7121 else if (stat & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_10G))
7123 else if (stat & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_40G))
7126 if (link_ok != lc->link_ok || speed != lc->speed ||
7127 fc != lc->fc) { /* something changed */
7128 lc->link_ok = link_ok;
7131 lc->supported = be16_to_cpu(p->u.info.pcap);
7132 t4_os_link_changed(adap, port, link_ok);
7134 if (mod != pi->mod_type) {
7136 t4_os_portmod_changed(adap, port);
7142 static void get_pci_mode(struct adapter *adapter, struct pci_params *p)
7146 if (pci_is_pcie(adapter->pdev)) {
7147 pcie_capability_read_word(adapter->pdev, PCI_EXP_LNKSTA, &val);
7148 p->speed = val & PCI_EXP_LNKSTA_CLS;
7149 p->width = (val & PCI_EXP_LNKSTA_NLW) >> 4;
7154 * init_link_config - initialize a link's SW state
7155 * @lc: structure holding the link state
7156 * @caps: link capabilities
7158 * Initializes the SW state maintained for each link, including the link's
7159 * capabilities and default speed/flow-control/autonegotiation settings.
7161 static void init_link_config(struct link_config *lc, unsigned int caps)
7163 lc->supported = caps;
7164 lc->requested_speed = 0;
7166 lc->requested_fc = lc->fc = PAUSE_RX | PAUSE_TX;
7167 if (lc->supported & FW_PORT_CAP_ANEG) {
7168 lc->advertising = lc->supported & ADVERT_MASK;
7169 lc->autoneg = AUTONEG_ENABLE;
7170 lc->requested_fc |= PAUSE_AUTONEG;
7172 lc->advertising = 0;
7173 lc->autoneg = AUTONEG_DISABLE;
7177 #define CIM_PF_NOACCESS 0xeeeeeeee
7179 int t4_wait_dev_ready(void __iomem *regs)
7183 whoami = readl(regs + PL_WHOAMI_A);
7184 if (whoami != 0xffffffff && whoami != CIM_PF_NOACCESS)
7188 whoami = readl(regs + PL_WHOAMI_A);
7189 return (whoami != 0xffffffff && whoami != CIM_PF_NOACCESS ? 0 : -EIO);
7193 u32 vendor_and_model_id;
7197 static int get_flash_params(struct adapter *adap)
7199 /* Table for non-Numonix supported flash parts. Numonix parts are left
7200 * to the preexisting code. All flash parts have 64KB sectors.
7202 static struct flash_desc supported_flash[] = {
7203 { 0x150201, 4 << 20 }, /* Spansion 4MB S25FL032P */
7209 ret = sf1_write(adap, 1, 1, 0, SF_RD_ID);
7211 ret = sf1_read(adap, 3, 0, 1, &info);
7212 t4_write_reg(adap, SF_OP_A, 0); /* unlock SF */
7216 for (ret = 0; ret < ARRAY_SIZE(supported_flash); ++ret)
7217 if (supported_flash[ret].vendor_and_model_id == info) {
7218 adap->params.sf_size = supported_flash[ret].size_mb;
7219 adap->params.sf_nsec =
7220 adap->params.sf_size / SF_SEC_SIZE;
7224 if ((info & 0xff) != 0x20) /* not a Numonix flash */
7226 info >>= 16; /* log2 of size */
7227 if (info >= 0x14 && info < 0x18)
7228 adap->params.sf_nsec = 1 << (info - 16);
7229 else if (info == 0x18)
7230 adap->params.sf_nsec = 64;
7233 adap->params.sf_size = 1 << info;
7234 adap->params.sf_fw_start =
7235 t4_read_reg(adap, CIM_BOOT_CFG_A) & BOOTADDR_M;
7237 if (adap->params.sf_size < FLASH_MIN_SIZE)
7238 dev_warn(adap->pdev_dev, "WARNING!!! FLASH size %#x < %#x!!!\n",
7239 adap->params.sf_size, FLASH_MIN_SIZE);
7243 static void set_pcie_completion_timeout(struct adapter *adapter, u8 range)
7248 pcie_cap = pci_find_capability(adapter->pdev, PCI_CAP_ID_EXP);
7250 pci_read_config_word(adapter->pdev,
7251 pcie_cap + PCI_EXP_DEVCTL2, &val);
7252 val &= ~PCI_EXP_DEVCTL2_COMP_TIMEOUT;
7254 pci_write_config_word(adapter->pdev,
7255 pcie_cap + PCI_EXP_DEVCTL2, val);
7260 * t4_prep_adapter - prepare SW and HW for operation
7261 * @adapter: the adapter
7262 * @reset: if true perform a HW reset
7264 * Initialize adapter SW state for the various HW modules, set initial
7265 * values for some adapter tunables, take PHYs out of reset, and
7266 * initialize the MDIO interface.
7268 int t4_prep_adapter(struct adapter *adapter)
7274 get_pci_mode(adapter, &adapter->params.pci);
7275 pl_rev = REV_G(t4_read_reg(adapter, PL_REV_A));
7277 ret = get_flash_params(adapter);
7279 dev_err(adapter->pdev_dev, "error %d identifying flash\n", ret);
7283 /* Retrieve adapter's device ID
7285 pci_read_config_word(adapter->pdev, PCI_DEVICE_ID, &device_id);
7286 ver = device_id >> 12;
7287 adapter->params.chip = 0;
7290 adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T4, pl_rev);
7291 adapter->params.arch.sge_fl_db = DBPRIO_F;
7292 adapter->params.arch.mps_tcam_size =
7293 NUM_MPS_CLS_SRAM_L_INSTANCES;
7294 adapter->params.arch.mps_rplc_size = 128;
7295 adapter->params.arch.nchan = NCHAN;
7296 adapter->params.arch.pm_stats_cnt = PM_NSTATS;
7297 adapter->params.arch.vfcount = 128;
7298 /* Congestion map is for 4 channels so that
7299 * MPS can have 4 priority per port.
7301 adapter->params.arch.cng_ch_bits_log = 2;
7304 adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T5, pl_rev);
7305 adapter->params.arch.sge_fl_db = DBPRIO_F | DBTYPE_F;
7306 adapter->params.arch.mps_tcam_size =
7307 NUM_MPS_T5_CLS_SRAM_L_INSTANCES;
7308 adapter->params.arch.mps_rplc_size = 128;
7309 adapter->params.arch.nchan = NCHAN;
7310 adapter->params.arch.pm_stats_cnt = PM_NSTATS;
7311 adapter->params.arch.vfcount = 128;
7312 adapter->params.arch.cng_ch_bits_log = 2;
7315 adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T6, pl_rev);
7316 adapter->params.arch.sge_fl_db = 0;
7317 adapter->params.arch.mps_tcam_size =
7318 NUM_MPS_T5_CLS_SRAM_L_INSTANCES;
7319 adapter->params.arch.mps_rplc_size = 256;
7320 adapter->params.arch.nchan = 2;
7321 adapter->params.arch.pm_stats_cnt = T6_PM_NSTATS;
7322 adapter->params.arch.vfcount = 256;
7323 /* Congestion map will be for 2 channels so that
7324 * MPS can have 8 priority per port.
7326 adapter->params.arch.cng_ch_bits_log = 3;
7329 dev_err(adapter->pdev_dev, "Device %d is not supported\n",
7334 adapter->params.cim_la_size = CIMLA_SIZE;
7335 init_cong_ctrl(adapter->params.a_wnd, adapter->params.b_wnd);
7338 * Default port for debugging in case we can't reach FW.
7340 adapter->params.nports = 1;
7341 adapter->params.portvec = 1;
7342 adapter->params.vpd.cclk = 50000;
7344 /* Set pci completion timeout value to 4 seconds. */
7345 set_pcie_completion_timeout(adapter, 0xd);
7350 * t4_bar2_sge_qregs - return BAR2 SGE Queue register information
7351 * @adapter: the adapter
7352 * @qid: the Queue ID
7353 * @qtype: the Ingress or Egress type for @qid
7354 * @user: true if this request is for a user mode queue
7355 * @pbar2_qoffset: BAR2 Queue Offset
7356 * @pbar2_qid: BAR2 Queue ID or 0 for Queue ID inferred SGE Queues
7358 * Returns the BAR2 SGE Queue Registers information associated with the
7359 * indicated Absolute Queue ID. These are passed back in return value
7360 * pointers. @qtype should be T4_BAR2_QTYPE_EGRESS for Egress Queue
7361 * and T4_BAR2_QTYPE_INGRESS for Ingress Queues.
7363 * This may return an error which indicates that BAR2 SGE Queue
7364 * registers aren't available. If an error is not returned, then the
7365 * following values are returned:
7367 * *@pbar2_qoffset: the BAR2 Offset of the @qid Registers
7368 * *@pbar2_qid: the BAR2 SGE Queue ID or 0 of @qid
7370 * If the returned BAR2 Queue ID is 0, then BAR2 SGE registers which
7371 * require the "Inferred Queue ID" ability may be used. E.g. the
7372 * Write Combining Doorbell Buffer. If the BAR2 Queue ID is not 0,
7373 * then these "Inferred Queue ID" register may not be used.
7375 int t4_bar2_sge_qregs(struct adapter *adapter,
7377 enum t4_bar2_qtype qtype,
7380 unsigned int *pbar2_qid)
7382 unsigned int page_shift, page_size, qpp_shift, qpp_mask;
7383 u64 bar2_page_offset, bar2_qoffset;
7384 unsigned int bar2_qid, bar2_qid_offset, bar2_qinferred;
7386 /* T4 doesn't support BAR2 SGE Queue registers for kernel mode queues */
7387 if (!user && is_t4(adapter->params.chip))
7390 /* Get our SGE Page Size parameters.
7392 page_shift = adapter->params.sge.hps + 10;
7393 page_size = 1 << page_shift;
7395 /* Get the right Queues per Page parameters for our Queue.
7397 qpp_shift = (qtype == T4_BAR2_QTYPE_EGRESS
7398 ? adapter->params.sge.eq_qpp
7399 : adapter->params.sge.iq_qpp);
7400 qpp_mask = (1 << qpp_shift) - 1;
7402 /* Calculate the basics of the BAR2 SGE Queue register area:
7403 * o The BAR2 page the Queue registers will be in.
7404 * o The BAR2 Queue ID.
7405 * o The BAR2 Queue ID Offset into the BAR2 page.
7407 bar2_page_offset = ((u64)(qid >> qpp_shift) << page_shift);
7408 bar2_qid = qid & qpp_mask;
7409 bar2_qid_offset = bar2_qid * SGE_UDB_SIZE;
7411 /* If the BAR2 Queue ID Offset is less than the Page Size, then the
7412 * hardware will infer the Absolute Queue ID simply from the writes to
7413 * the BAR2 Queue ID Offset within the BAR2 Page (and we need to use a
7414 * BAR2 Queue ID of 0 for those writes). Otherwise, we'll simply
7415 * write to the first BAR2 SGE Queue Area within the BAR2 Page with
7416 * the BAR2 Queue ID and the hardware will infer the Absolute Queue ID
7417 * from the BAR2 Page and BAR2 Queue ID.
7419 * One important censequence of this is that some BAR2 SGE registers
7420 * have a "Queue ID" field and we can write the BAR2 SGE Queue ID
7421 * there. But other registers synthesize the SGE Queue ID purely
7422 * from the writes to the registers -- the Write Combined Doorbell
7423 * Buffer is a good example. These BAR2 SGE Registers are only
7424 * available for those BAR2 SGE Register areas where the SGE Absolute
7425 * Queue ID can be inferred from simple writes.
7427 bar2_qoffset = bar2_page_offset;
7428 bar2_qinferred = (bar2_qid_offset < page_size);
7429 if (bar2_qinferred) {
7430 bar2_qoffset += bar2_qid_offset;
7434 *pbar2_qoffset = bar2_qoffset;
7435 *pbar2_qid = bar2_qid;
7440 * t4_init_devlog_params - initialize adapter->params.devlog
7441 * @adap: the adapter
7443 * Initialize various fields of the adapter's Firmware Device Log
7444 * Parameters structure.
7446 int t4_init_devlog_params(struct adapter *adap)
7448 struct devlog_params *dparams = &adap->params.devlog;
7450 unsigned int devlog_meminfo;
7451 struct fw_devlog_cmd devlog_cmd;
7454 /* If we're dealing with newer firmware, the Device Log Paramerters
7455 * are stored in a designated register which allows us to access the
7456 * Device Log even if we can't talk to the firmware.
7459 t4_read_reg(adap, PCIE_FW_REG(PCIE_FW_PF_A, PCIE_FW_PF_DEVLOG));
7461 unsigned int nentries, nentries128;
7463 dparams->memtype = PCIE_FW_PF_DEVLOG_MEMTYPE_G(pf_dparams);
7464 dparams->start = PCIE_FW_PF_DEVLOG_ADDR16_G(pf_dparams) << 4;
7466 nentries128 = PCIE_FW_PF_DEVLOG_NENTRIES128_G(pf_dparams);
7467 nentries = (nentries128 + 1) * 128;
7468 dparams->size = nentries * sizeof(struct fw_devlog_e);
7473 /* Otherwise, ask the firmware for it's Device Log Parameters.
7475 memset(&devlog_cmd, 0, sizeof(devlog_cmd));
7476 devlog_cmd.op_to_write = cpu_to_be32(FW_CMD_OP_V(FW_DEVLOG_CMD) |
7477 FW_CMD_REQUEST_F | FW_CMD_READ_F);
7478 devlog_cmd.retval_len16 = cpu_to_be32(FW_LEN16(devlog_cmd));
7479 ret = t4_wr_mbox(adap, adap->mbox, &devlog_cmd, sizeof(devlog_cmd),
7485 be32_to_cpu(devlog_cmd.memtype_devlog_memaddr16_devlog);
7486 dparams->memtype = FW_DEVLOG_CMD_MEMTYPE_DEVLOG_G(devlog_meminfo);
7487 dparams->start = FW_DEVLOG_CMD_MEMADDR16_DEVLOG_G(devlog_meminfo) << 4;
7488 dparams->size = be32_to_cpu(devlog_cmd.memsize_devlog);
7494 * t4_init_sge_params - initialize adap->params.sge
7495 * @adapter: the adapter
7497 * Initialize various fields of the adapter's SGE Parameters structure.
7499 int t4_init_sge_params(struct adapter *adapter)
7501 struct sge_params *sge_params = &adapter->params.sge;
7503 unsigned int s_hps, s_qpp;
7505 /* Extract the SGE Page Size for our PF.
7507 hps = t4_read_reg(adapter, SGE_HOST_PAGE_SIZE_A);
7508 s_hps = (HOSTPAGESIZEPF0_S +
7509 (HOSTPAGESIZEPF1_S - HOSTPAGESIZEPF0_S) * adapter->pf);
7510 sge_params->hps = ((hps >> s_hps) & HOSTPAGESIZEPF0_M);
7512 /* Extract the SGE Egress and Ingess Queues Per Page for our PF.
7514 s_qpp = (QUEUESPERPAGEPF0_S +
7515 (QUEUESPERPAGEPF1_S - QUEUESPERPAGEPF0_S) * adapter->pf);
7516 qpp = t4_read_reg(adapter, SGE_EGRESS_QUEUES_PER_PAGE_PF_A);
7517 sge_params->eq_qpp = ((qpp >> s_qpp) & QUEUESPERPAGEPF0_M);
7518 qpp = t4_read_reg(adapter, SGE_INGRESS_QUEUES_PER_PAGE_PF_A);
7519 sge_params->iq_qpp = ((qpp >> s_qpp) & QUEUESPERPAGEPF0_M);
7525 * t4_init_tp_params - initialize adap->params.tp
7526 * @adap: the adapter
7528 * Initialize various fields of the adapter's TP Parameters structure.
7530 int t4_init_tp_params(struct adapter *adap)
7535 v = t4_read_reg(adap, TP_TIMER_RESOLUTION_A);
7536 adap->params.tp.tre = TIMERRESOLUTION_G(v);
7537 adap->params.tp.dack_re = DELAYEDACKRESOLUTION_G(v);
7539 /* MODQ_REQ_MAP defaults to setting queues 0-3 to chan 0-3 */
7540 for (chan = 0; chan < NCHAN; chan++)
7541 adap->params.tp.tx_modq[chan] = chan;
7543 /* Cache the adapter's Compressed Filter Mode and global Incress
7546 if (t4_use_ldst(adap)) {
7547 t4_fw_tp_pio_rw(adap, &adap->params.tp.vlan_pri_map, 1,
7548 TP_VLAN_PRI_MAP_A, 1);
7549 t4_fw_tp_pio_rw(adap, &adap->params.tp.ingress_config, 1,
7550 TP_INGRESS_CONFIG_A, 1);
7552 t4_read_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A,
7553 &adap->params.tp.vlan_pri_map, 1,
7555 t4_read_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A,
7556 &adap->params.tp.ingress_config, 1,
7557 TP_INGRESS_CONFIG_A);
7560 /* Now that we have TP_VLAN_PRI_MAP cached, we can calculate the field
7561 * shift positions of several elements of the Compressed Filter Tuple
7562 * for this adapter which we need frequently ...
7564 adap->params.tp.vlan_shift = t4_filter_field_shift(adap, VLAN_F);
7565 adap->params.tp.vnic_shift = t4_filter_field_shift(adap, VNIC_ID_F);
7566 adap->params.tp.port_shift = t4_filter_field_shift(adap, PORT_F);
7567 adap->params.tp.protocol_shift = t4_filter_field_shift(adap,
7570 /* If TP_INGRESS_CONFIG.VNID == 0, then TP_VLAN_PRI_MAP.VNIC_ID
7571 * represents the presence of an Outer VLAN instead of a VNIC ID.
7573 if ((adap->params.tp.ingress_config & VNIC_F) == 0)
7574 adap->params.tp.vnic_shift = -1;
7580 * t4_filter_field_shift - calculate filter field shift
7581 * @adap: the adapter
7582 * @filter_sel: the desired field (from TP_VLAN_PRI_MAP bits)
7584 * Return the shift position of a filter field within the Compressed
7585 * Filter Tuple. The filter field is specified via its selection bit
7586 * within TP_VLAN_PRI_MAL (filter mode). E.g. F_VLAN.
7588 int t4_filter_field_shift(const struct adapter *adap, int filter_sel)
7590 unsigned int filter_mode = adap->params.tp.vlan_pri_map;
7594 if ((filter_mode & filter_sel) == 0)
7597 for (sel = 1, field_shift = 0; sel < filter_sel; sel <<= 1) {
7598 switch (filter_mode & sel) {
7600 field_shift += FT_FCOE_W;
7603 field_shift += FT_PORT_W;
7606 field_shift += FT_VNIC_ID_W;
7609 field_shift += FT_VLAN_W;
7612 field_shift += FT_TOS_W;
7615 field_shift += FT_PROTOCOL_W;
7618 field_shift += FT_ETHERTYPE_W;
7621 field_shift += FT_MACMATCH_W;
7624 field_shift += FT_MPSHITTYPE_W;
7626 case FRAGMENTATION_F:
7627 field_shift += FT_FRAGMENTATION_W;
7634 int t4_init_rss_mode(struct adapter *adap, int mbox)
7637 struct fw_rss_vi_config_cmd rvc;
7639 memset(&rvc, 0, sizeof(rvc));
7641 for_each_port(adap, i) {
7642 struct port_info *p = adap2pinfo(adap, i);
7645 cpu_to_be32(FW_CMD_OP_V(FW_RSS_VI_CONFIG_CMD) |
7646 FW_CMD_REQUEST_F | FW_CMD_READ_F |
7647 FW_RSS_VI_CONFIG_CMD_VIID_V(p->viid));
7648 rvc.retval_len16 = cpu_to_be32(FW_LEN16(rvc));
7649 ret = t4_wr_mbox(adap, mbox, &rvc, sizeof(rvc), &rvc);
7652 p->rss_mode = be32_to_cpu(rvc.u.basicvirtual.defaultq_to_udpen);
7657 int t4_port_init(struct adapter *adap, int mbox, int pf, int vf)
7661 struct fw_port_cmd c;
7662 struct fw_rss_vi_config_cmd rvc;
7664 memset(&c, 0, sizeof(c));
7665 memset(&rvc, 0, sizeof(rvc));
7667 for_each_port(adap, i) {
7668 unsigned int rss_size;
7669 struct port_info *p = adap2pinfo(adap, i);
7671 while ((adap->params.portvec & (1 << j)) == 0)
7674 c.op_to_portid = cpu_to_be32(FW_CMD_OP_V(FW_PORT_CMD) |
7675 FW_CMD_REQUEST_F | FW_CMD_READ_F |
7676 FW_PORT_CMD_PORTID_V(j));
7677 c.action_to_len16 = cpu_to_be32(
7678 FW_PORT_CMD_ACTION_V(FW_PORT_ACTION_GET_PORT_INFO) |
7680 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
7684 ret = t4_alloc_vi(adap, mbox, j, pf, vf, 1, addr, &rss_size);
7691 p->rss_size = rss_size;
7692 memcpy(adap->port[i]->dev_addr, addr, ETH_ALEN);
7693 adap->port[i]->dev_port = j;
7695 ret = be32_to_cpu(c.u.info.lstatus_to_modtype);
7696 p->mdio_addr = (ret & FW_PORT_CMD_MDIOCAP_F) ?
7697 FW_PORT_CMD_MDIOADDR_G(ret) : -1;
7698 p->port_type = FW_PORT_CMD_PTYPE_G(ret);
7699 p->mod_type = FW_PORT_MOD_TYPE_NA;
7702 cpu_to_be32(FW_CMD_OP_V(FW_RSS_VI_CONFIG_CMD) |
7703 FW_CMD_REQUEST_F | FW_CMD_READ_F |
7704 FW_RSS_VI_CONFIG_CMD_VIID(p->viid));
7705 rvc.retval_len16 = cpu_to_be32(FW_LEN16(rvc));
7706 ret = t4_wr_mbox(adap, mbox, &rvc, sizeof(rvc), &rvc);
7709 p->rss_mode = be32_to_cpu(rvc.u.basicvirtual.defaultq_to_udpen);
7711 init_link_config(&p->link_cfg, be16_to_cpu(c.u.info.pcap));
7718 * t4_read_cimq_cfg - read CIM queue configuration
7719 * @adap: the adapter
7720 * @base: holds the queue base addresses in bytes
7721 * @size: holds the queue sizes in bytes
7722 * @thres: holds the queue full thresholds in bytes
7724 * Returns the current configuration of the CIM queues, starting with
7725 * the IBQs, then the OBQs.
7727 void t4_read_cimq_cfg(struct adapter *adap, u16 *base, u16 *size, u16 *thres)
7730 int cim_num_obq = is_t4(adap->params.chip) ?
7731 CIM_NUM_OBQ : CIM_NUM_OBQ_T5;
7733 for (i = 0; i < CIM_NUM_IBQ; i++) {
7734 t4_write_reg(adap, CIM_QUEUE_CONFIG_REF_A, IBQSELECT_F |
7736 v = t4_read_reg(adap, CIM_QUEUE_CONFIG_CTRL_A);
7737 /* value is in 256-byte units */
7738 *base++ = CIMQBASE_G(v) * 256;
7739 *size++ = CIMQSIZE_G(v) * 256;
7740 *thres++ = QUEFULLTHRSH_G(v) * 8; /* 8-byte unit */
7742 for (i = 0; i < cim_num_obq; i++) {
7743 t4_write_reg(adap, CIM_QUEUE_CONFIG_REF_A, OBQSELECT_F |
7745 v = t4_read_reg(adap, CIM_QUEUE_CONFIG_CTRL_A);
7746 /* value is in 256-byte units */
7747 *base++ = CIMQBASE_G(v) * 256;
7748 *size++ = CIMQSIZE_G(v) * 256;
7753 * t4_read_cim_ibq - read the contents of a CIM inbound queue
7754 * @adap: the adapter
7755 * @qid: the queue index
7756 * @data: where to store the queue contents
7757 * @n: capacity of @data in 32-bit words
7759 * Reads the contents of the selected CIM queue starting at address 0 up
7760 * to the capacity of @data. @n must be a multiple of 4. Returns < 0 on
7761 * error and the number of 32-bit words actually read on success.
7763 int t4_read_cim_ibq(struct adapter *adap, unsigned int qid, u32 *data, size_t n)
7765 int i, err, attempts;
7767 const unsigned int nwords = CIM_IBQ_SIZE * 4;
7769 if (qid > 5 || (n & 3))
7772 addr = qid * nwords;
7776 /* It might take 3-10ms before the IBQ debug read access is allowed.
7777 * Wait for 1 Sec with a delay of 1 usec.
7781 for (i = 0; i < n; i++, addr++) {
7782 t4_write_reg(adap, CIM_IBQ_DBG_CFG_A, IBQDBGADDR_V(addr) |
7784 err = t4_wait_op_done(adap, CIM_IBQ_DBG_CFG_A, IBQDBGBUSY_F, 0,
7788 *data++ = t4_read_reg(adap, CIM_IBQ_DBG_DATA_A);
7790 t4_write_reg(adap, CIM_IBQ_DBG_CFG_A, 0);
7795 * t4_read_cim_obq - read the contents of a CIM outbound queue
7796 * @adap: the adapter
7797 * @qid: the queue index
7798 * @data: where to store the queue contents
7799 * @n: capacity of @data in 32-bit words
7801 * Reads the contents of the selected CIM queue starting at address 0 up
7802 * to the capacity of @data. @n must be a multiple of 4. Returns < 0 on
7803 * error and the number of 32-bit words actually read on success.
7805 int t4_read_cim_obq(struct adapter *adap, unsigned int qid, u32 *data, size_t n)
7808 unsigned int addr, v, nwords;
7809 int cim_num_obq = is_t4(adap->params.chip) ?
7810 CIM_NUM_OBQ : CIM_NUM_OBQ_T5;
7812 if ((qid > (cim_num_obq - 1)) || (n & 3))
7815 t4_write_reg(adap, CIM_QUEUE_CONFIG_REF_A, OBQSELECT_F |
7816 QUENUMSELECT_V(qid));
7817 v = t4_read_reg(adap, CIM_QUEUE_CONFIG_CTRL_A);
7819 addr = CIMQBASE_G(v) * 64; /* muliple of 256 -> muliple of 4 */
7820 nwords = CIMQSIZE_G(v) * 64; /* same */
7824 for (i = 0; i < n; i++, addr++) {
7825 t4_write_reg(adap, CIM_OBQ_DBG_CFG_A, OBQDBGADDR_V(addr) |
7827 err = t4_wait_op_done(adap, CIM_OBQ_DBG_CFG_A, OBQDBGBUSY_F, 0,
7831 *data++ = t4_read_reg(adap, CIM_OBQ_DBG_DATA_A);
7833 t4_write_reg(adap, CIM_OBQ_DBG_CFG_A, 0);
7838 * t4_cim_read - read a block from CIM internal address space
7839 * @adap: the adapter
7840 * @addr: the start address within the CIM address space
7841 * @n: number of words to read
7842 * @valp: where to store the result
7844 * Reads a block of 4-byte words from the CIM intenal address space.
7846 int t4_cim_read(struct adapter *adap, unsigned int addr, unsigned int n,
7851 if (t4_read_reg(adap, CIM_HOST_ACC_CTRL_A) & HOSTBUSY_F)
7854 for ( ; !ret && n--; addr += 4) {
7855 t4_write_reg(adap, CIM_HOST_ACC_CTRL_A, addr);
7856 ret = t4_wait_op_done(adap, CIM_HOST_ACC_CTRL_A, HOSTBUSY_F,
7859 *valp++ = t4_read_reg(adap, CIM_HOST_ACC_DATA_A);
7865 * t4_cim_write - write a block into CIM internal address space
7866 * @adap: the adapter
7867 * @addr: the start address within the CIM address space
7868 * @n: number of words to write
7869 * @valp: set of values to write
7871 * Writes a block of 4-byte words into the CIM intenal address space.
7873 int t4_cim_write(struct adapter *adap, unsigned int addr, unsigned int n,
7874 const unsigned int *valp)
7878 if (t4_read_reg(adap, CIM_HOST_ACC_CTRL_A) & HOSTBUSY_F)
7881 for ( ; !ret && n--; addr += 4) {
7882 t4_write_reg(adap, CIM_HOST_ACC_DATA_A, *valp++);
7883 t4_write_reg(adap, CIM_HOST_ACC_CTRL_A, addr | HOSTWRITE_F);
7884 ret = t4_wait_op_done(adap, CIM_HOST_ACC_CTRL_A, HOSTBUSY_F,
7890 static int t4_cim_write1(struct adapter *adap, unsigned int addr,
7893 return t4_cim_write(adap, addr, 1, &val);
7897 * t4_cim_read_la - read CIM LA capture buffer
7898 * @adap: the adapter
7899 * @la_buf: where to store the LA data
7900 * @wrptr: the HW write pointer within the capture buffer
7902 * Reads the contents of the CIM LA buffer with the most recent entry at
7903 * the end of the returned data and with the entry at @wrptr first.
7904 * We try to leave the LA in the running state we find it in.
7906 int t4_cim_read_la(struct adapter *adap, u32 *la_buf, unsigned int *wrptr)
7909 unsigned int cfg, val, idx;
7911 ret = t4_cim_read(adap, UP_UP_DBG_LA_CFG_A, 1, &cfg);
7915 if (cfg & UPDBGLAEN_F) { /* LA is running, freeze it */
7916 ret = t4_cim_write1(adap, UP_UP_DBG_LA_CFG_A, 0);
7921 ret = t4_cim_read(adap, UP_UP_DBG_LA_CFG_A, 1, &val);
7925 idx = UPDBGLAWRPTR_G(val);
7929 for (i = 0; i < adap->params.cim_la_size; i++) {
7930 ret = t4_cim_write1(adap, UP_UP_DBG_LA_CFG_A,
7931 UPDBGLARDPTR_V(idx) | UPDBGLARDEN_F);
7934 ret = t4_cim_read(adap, UP_UP_DBG_LA_CFG_A, 1, &val);
7937 if (val & UPDBGLARDEN_F) {
7941 ret = t4_cim_read(adap, UP_UP_DBG_LA_DATA_A, 1, &la_buf[i]);
7944 idx = (idx + 1) & UPDBGLARDPTR_M;
7947 if (cfg & UPDBGLAEN_F) {
7948 int r = t4_cim_write1(adap, UP_UP_DBG_LA_CFG_A,
7949 cfg & ~UPDBGLARDEN_F);
7957 * t4_tp_read_la - read TP LA capture buffer
7958 * @adap: the adapter
7959 * @la_buf: where to store the LA data
7960 * @wrptr: the HW write pointer within the capture buffer
7962 * Reads the contents of the TP LA buffer with the most recent entry at
7963 * the end of the returned data and with the entry at @wrptr first.
7964 * We leave the LA in the running state we find it in.
7966 void t4_tp_read_la(struct adapter *adap, u64 *la_buf, unsigned int *wrptr)
7968 bool last_incomplete;
7969 unsigned int i, cfg, val, idx;
7971 cfg = t4_read_reg(adap, TP_DBG_LA_CONFIG_A) & 0xffff;
7972 if (cfg & DBGLAENABLE_F) /* freeze LA */
7973 t4_write_reg(adap, TP_DBG_LA_CONFIG_A,
7974 adap->params.tp.la_mask | (cfg ^ DBGLAENABLE_F));
7976 val = t4_read_reg(adap, TP_DBG_LA_CONFIG_A);
7977 idx = DBGLAWPTR_G(val);
7978 last_incomplete = DBGLAMODE_G(val) >= 2 && (val & DBGLAWHLF_F) == 0;
7979 if (last_incomplete)
7980 idx = (idx + 1) & DBGLARPTR_M;
7985 val &= ~DBGLARPTR_V(DBGLARPTR_M);
7986 val |= adap->params.tp.la_mask;
7988 for (i = 0; i < TPLA_SIZE; i++) {
7989 t4_write_reg(adap, TP_DBG_LA_CONFIG_A, DBGLARPTR_V(idx) | val);
7990 la_buf[i] = t4_read_reg64(adap, TP_DBG_LA_DATAL_A);
7991 idx = (idx + 1) & DBGLARPTR_M;
7994 /* Wipe out last entry if it isn't valid */
7995 if (last_incomplete)
7996 la_buf[TPLA_SIZE - 1] = ~0ULL;
7998 if (cfg & DBGLAENABLE_F) /* restore running state */
7999 t4_write_reg(adap, TP_DBG_LA_CONFIG_A,
8000 cfg | adap->params.tp.la_mask);
8003 /* SGE Hung Ingress DMA Warning Threshold time and Warning Repeat Rate (in
8004 * seconds). If we find one of the SGE Ingress DMA State Machines in the same
8005 * state for more than the Warning Threshold then we'll issue a warning about
8006 * a potential hang. We'll repeat the warning as the SGE Ingress DMA Channel
8007 * appears to be hung every Warning Repeat second till the situation clears.
8008 * If the situation clears, we'll note that as well.
8010 #define SGE_IDMA_WARN_THRESH 1
8011 #define SGE_IDMA_WARN_REPEAT 300
8014 * t4_idma_monitor_init - initialize SGE Ingress DMA Monitor
8015 * @adapter: the adapter
8016 * @idma: the adapter IDMA Monitor state
8018 * Initialize the state of an SGE Ingress DMA Monitor.
8020 void t4_idma_monitor_init(struct adapter *adapter,
8021 struct sge_idma_monitor_state *idma)
8023 /* Initialize the state variables for detecting an SGE Ingress DMA
8024 * hang. The SGE has internal counters which count up on each clock
8025 * tick whenever the SGE finds its Ingress DMA State Engines in the
8026 * same state they were on the previous clock tick. The clock used is
8027 * the Core Clock so we have a limit on the maximum "time" they can
8028 * record; typically a very small number of seconds. For instance,
8029 * with a 600MHz Core Clock, we can only count up to a bit more than
8030 * 7s. So we'll synthesize a larger counter in order to not run the
8031 * risk of having the "timers" overflow and give us the flexibility to
8032 * maintain a Hung SGE State Machine of our own which operates across
8033 * a longer time frame.
8035 idma->idma_1s_thresh = core_ticks_per_usec(adapter) * 1000000; /* 1s */
8036 idma->idma_stalled[0] = 0;
8037 idma->idma_stalled[1] = 0;
8041 * t4_idma_monitor - monitor SGE Ingress DMA state
8042 * @adapter: the adapter
8043 * @idma: the adapter IDMA Monitor state
8044 * @hz: number of ticks/second
8045 * @ticks: number of ticks since the last IDMA Monitor call
8047 void t4_idma_monitor(struct adapter *adapter,
8048 struct sge_idma_monitor_state *idma,
8051 int i, idma_same_state_cnt[2];
8053 /* Read the SGE Debug Ingress DMA Same State Count registers. These
8054 * are counters inside the SGE which count up on each clock when the
8055 * SGE finds its Ingress DMA State Engines in the same states they
8056 * were in the previous clock. The counters will peg out at
8057 * 0xffffffff without wrapping around so once they pass the 1s
8058 * threshold they'll stay above that till the IDMA state changes.
8060 t4_write_reg(adapter, SGE_DEBUG_INDEX_A, 13);
8061 idma_same_state_cnt[0] = t4_read_reg(adapter, SGE_DEBUG_DATA_HIGH_A);
8062 idma_same_state_cnt[1] = t4_read_reg(adapter, SGE_DEBUG_DATA_LOW_A);
8064 for (i = 0; i < 2; i++) {
8065 u32 debug0, debug11;
8067 /* If the Ingress DMA Same State Counter ("timer") is less
8068 * than 1s, then we can reset our synthesized Stall Timer and
8069 * continue. If we have previously emitted warnings about a
8070 * potential stalled Ingress Queue, issue a note indicating
8071 * that the Ingress Queue has resumed forward progress.
8073 if (idma_same_state_cnt[i] < idma->idma_1s_thresh) {
8074 if (idma->idma_stalled[i] >= SGE_IDMA_WARN_THRESH * hz)
8075 dev_warn(adapter->pdev_dev, "SGE idma%d, queue %u, "
8076 "resumed after %d seconds\n",
8077 i, idma->idma_qid[i],
8078 idma->idma_stalled[i] / hz);
8079 idma->idma_stalled[i] = 0;
8083 /* Synthesize an SGE Ingress DMA Same State Timer in the Hz
8084 * domain. The first time we get here it'll be because we
8085 * passed the 1s Threshold; each additional time it'll be
8086 * because the RX Timer Callback is being fired on its regular
8089 * If the stall is below our Potential Hung Ingress Queue
8090 * Warning Threshold, continue.
8092 if (idma->idma_stalled[i] == 0) {
8093 idma->idma_stalled[i] = hz;
8094 idma->idma_warn[i] = 0;
8096 idma->idma_stalled[i] += ticks;
8097 idma->idma_warn[i] -= ticks;
8100 if (idma->idma_stalled[i] < SGE_IDMA_WARN_THRESH * hz)
8103 /* We'll issue a warning every SGE_IDMA_WARN_REPEAT seconds.
8105 if (idma->idma_warn[i] > 0)
8107 idma->idma_warn[i] = SGE_IDMA_WARN_REPEAT * hz;
8109 /* Read and save the SGE IDMA State and Queue ID information.
8110 * We do this every time in case it changes across time ...
8111 * can't be too careful ...
8113 t4_write_reg(adapter, SGE_DEBUG_INDEX_A, 0);
8114 debug0 = t4_read_reg(adapter, SGE_DEBUG_DATA_LOW_A);
8115 idma->idma_state[i] = (debug0 >> (i * 9)) & 0x3f;
8117 t4_write_reg(adapter, SGE_DEBUG_INDEX_A, 11);
8118 debug11 = t4_read_reg(adapter, SGE_DEBUG_DATA_LOW_A);
8119 idma->idma_qid[i] = (debug11 >> (i * 16)) & 0xffff;
8121 dev_warn(adapter->pdev_dev, "SGE idma%u, queue %u, potentially stuck in "
8122 "state %u for %d seconds (debug0=%#x, debug11=%#x)\n",
8123 i, idma->idma_qid[i], idma->idma_state[i],
8124 idma->idma_stalled[i] / hz,
8126 t4_sge_decode_idma_state(adapter, idma->idma_state[i]);