2 * This file is part of the Chelsio T4 Ethernet driver for Linux.
4 * Copyright (c) 2003-2014 Chelsio Communications, Inc. All rights reserved.
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
35 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
37 #include <linux/bitmap.h>
38 #include <linux/crc32.h>
39 #include <linux/ctype.h>
40 #include <linux/debugfs.h>
41 #include <linux/err.h>
42 #include <linux/etherdevice.h>
43 #include <linux/firmware.h>
45 #include <linux/if_vlan.h>
46 #include <linux/init.h>
47 #include <linux/log2.h>
48 #include <linux/mdio.h>
49 #include <linux/module.h>
50 #include <linux/moduleparam.h>
51 #include <linux/mutex.h>
52 #include <linux/netdevice.h>
53 #include <linux/pci.h>
54 #include <linux/aer.h>
55 #include <linux/rtnetlink.h>
56 #include <linux/sched.h>
57 #include <linux/seq_file.h>
58 #include <linux/sockios.h>
59 #include <linux/vmalloc.h>
60 #include <linux/workqueue.h>
61 #include <net/neighbour.h>
62 #include <net/netevent.h>
63 #include <net/addrconf.h>
64 #include <net/bonding.h>
65 #include <net/addrconf.h>
66 #include <asm/uaccess.h>
70 #include "t4_values.h"
73 #include "t4fw_version.h"
74 #include "cxgb4_dcb.h"
75 #include "cxgb4_debugfs.h"
79 char cxgb4_driver_name[] = KBUILD_MODNAME;
84 #define DRV_VERSION "2.0.0-ko"
85 const char cxgb4_driver_version[] = DRV_VERSION;
86 #define DRV_DESC "Chelsio T4/T5/T6 Network Driver"
88 /* Host shadow copy of ingress filter entry. This is in host native format
89 * and doesn't match the ordering or bit order, etc. of the hardware of the
90 * firmware command. The use of bit-field structure elements is purely to
91 * remind ourselves of the field size limitations and save memory in the case
92 * where the filter table is large.
95 /* Administrative fields for filter.
97 u32 valid:1; /* filter allocated and valid */
98 u32 locked:1; /* filter is administratively locked */
100 u32 pending:1; /* filter action is pending firmware reply */
101 u32 smtidx:8; /* Source MAC Table index for smac */
102 struct l2t_entry *l2t; /* Layer Two Table entry for dmac */
104 /* The filter itself. Most of this is a straight copy of information
105 * provided by the extended ioctl(). Some fields are translated to
106 * internal forms -- for instance the Ingress Queue ID passed in from
107 * the ioctl() is translated into the Absolute Ingress Queue ID.
109 struct ch_filter_specification fs;
112 #define DFLT_MSG_ENABLE (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK | \
113 NETIF_MSG_TIMER | NETIF_MSG_IFDOWN | NETIF_MSG_IFUP |\
114 NETIF_MSG_RX_ERR | NETIF_MSG_TX_ERR)
116 /* Macros needed to support the PCI Device ID Table ...
118 #define CH_PCI_DEVICE_ID_TABLE_DEFINE_BEGIN \
119 static const struct pci_device_id cxgb4_pci_tbl[] = {
120 #define CH_PCI_DEVICE_ID_FUNCTION 0x4
122 /* Include PCI Device IDs for both PF4 and PF0-3 so our PCI probe() routine is
125 #define CH_PCI_DEVICE_ID_FUNCTION2 0x0
127 #define CH_PCI_ID_TABLE_ENTRY(devid) \
128 {PCI_VDEVICE(CHELSIO, (devid)), 4}
130 #define CH_PCI_DEVICE_ID_TABLE_DEFINE_END \
134 #include "t4_pci_id_tbl.h"
136 #define FW4_FNAME "cxgb4/t4fw.bin"
137 #define FW5_FNAME "cxgb4/t5fw.bin"
138 #define FW6_FNAME "cxgb4/t6fw.bin"
139 #define FW4_CFNAME "cxgb4/t4-config.txt"
140 #define FW5_CFNAME "cxgb4/t5-config.txt"
141 #define FW6_CFNAME "cxgb4/t6-config.txt"
142 #define PHY_AQ1202_FIRMWARE "cxgb4/aq1202_fw.cld"
143 #define PHY_BCM84834_FIRMWARE "cxgb4/bcm8483.bin"
144 #define PHY_AQ1202_DEVICEID 0x4409
145 #define PHY_BCM84834_DEVICEID 0x4486
147 MODULE_DESCRIPTION(DRV_DESC);
148 MODULE_AUTHOR("Chelsio Communications");
149 MODULE_LICENSE("Dual BSD/GPL");
150 MODULE_VERSION(DRV_VERSION);
151 MODULE_DEVICE_TABLE(pci, cxgb4_pci_tbl);
152 MODULE_FIRMWARE(FW4_FNAME);
153 MODULE_FIRMWARE(FW5_FNAME);
154 MODULE_FIRMWARE(FW6_FNAME);
157 * Normally we're willing to become the firmware's Master PF but will be happy
158 * if another PF has already become the Master and initialized the adapter.
159 * Setting "force_init" will cause this driver to forcibly establish itself as
160 * the Master PF and initialize the adapter.
162 static uint force_init;
164 module_param(force_init, uint, 0644);
165 MODULE_PARM_DESC(force_init, "Forcibly become Master PF and initialize adapter");
168 * Normally if the firmware we connect to has Configuration File support, we
169 * use that and only fall back to the old Driver-based initialization if the
170 * Configuration File fails for some reason. If force_old_init is set, then
171 * we'll always use the old Driver-based initialization sequence.
173 static uint force_old_init;
175 module_param(force_old_init, uint, 0644);
176 MODULE_PARM_DESC(force_old_init, "Force old initialization sequence, deprecated"
179 static int dflt_msg_enable = DFLT_MSG_ENABLE;
181 module_param(dflt_msg_enable, int, 0644);
182 MODULE_PARM_DESC(dflt_msg_enable, "Chelsio T4 default message enable bitmap");
185 * The driver uses the best interrupt scheme available on a platform in the
186 * order MSI-X, MSI, legacy INTx interrupts. This parameter determines which
187 * of these schemes the driver may consider as follows:
189 * msi = 2: choose from among all three options
190 * msi = 1: only consider MSI and INTx interrupts
191 * msi = 0: force INTx interrupts
195 module_param(msi, int, 0644);
196 MODULE_PARM_DESC(msi, "whether to use INTx (0), MSI (1) or MSI-X (2)");
199 * Queue interrupt hold-off timer values. Queues default to the first of these
202 static unsigned int intr_holdoff[SGE_NTIMERS - 1] = { 5, 10, 20, 50, 100 };
204 module_param_array(intr_holdoff, uint, NULL, 0644);
205 MODULE_PARM_DESC(intr_holdoff, "values for queue interrupt hold-off timers "
206 "0..4 in microseconds, deprecated parameter");
208 static unsigned int intr_cnt[SGE_NCOUNTERS - 1] = { 4, 8, 16 };
210 module_param_array(intr_cnt, uint, NULL, 0644);
211 MODULE_PARM_DESC(intr_cnt,
212 "thresholds 1..3 for queue interrupt packet counters, "
213 "deprecated parameter");
216 * Normally we tell the chip to deliver Ingress Packets into our DMA buffers
217 * offset by 2 bytes in order to have the IP headers line up on 4-byte
218 * boundaries. This is a requirement for many architectures which will throw
219 * a machine check fault if an attempt is made to access one of the 4-byte IP
220 * header fields on a non-4-byte boundary. And it's a major performance issue
221 * even on some architectures which allow it like some implementations of the
222 * x86 ISA. However, some architectures don't mind this and for some very
223 * edge-case performance sensitive applications (like forwarding large volumes
224 * of small packets), setting this DMA offset to 0 will decrease the number of
225 * PCI-E Bus transfers enough to measurably affect performance.
227 static int rx_dma_offset = 2;
231 #ifdef CONFIG_PCI_IOV
232 module_param(vf_acls, bool, 0644);
233 MODULE_PARM_DESC(vf_acls, "if set enable virtualization L2 ACL enforcement, "
234 "deprecated parameter");
236 /* Configure the number of PCI-E Virtual Function which are to be instantiated
237 * on SR-IOV Capable Physical Functions.
239 static unsigned int num_vf[NUM_OF_PF_WITH_SRIOV];
241 module_param_array(num_vf, uint, NULL, 0644);
242 MODULE_PARM_DESC(num_vf, "number of VFs for each of PFs 0-3");
245 /* TX Queue select used to determine what algorithm to use for selecting TX
246 * queue. Select between the kernel provided function (select_queue=0) or user
247 * cxgb_select_queue function (select_queue=1)
249 * Default: select_queue=0
251 static int select_queue;
252 module_param(select_queue, int, 0644);
253 MODULE_PARM_DESC(select_queue,
254 "Select between kernel provided method of selecting or driver method of selecting TX queue. Default is kernel method.");
256 static unsigned int tp_vlan_pri_map = HW_TPL_FR_MT_PR_IV_P_FC;
258 module_param(tp_vlan_pri_map, uint, 0644);
259 MODULE_PARM_DESC(tp_vlan_pri_map, "global compressed filter configuration, "
260 "deprecated parameter");
262 static struct dentry *cxgb4_debugfs_root;
264 static LIST_HEAD(adapter_list);
265 static DEFINE_MUTEX(uld_mutex);
266 /* Adapter list to be accessed from atomic context */
267 static LIST_HEAD(adap_rcu_list);
268 static DEFINE_SPINLOCK(adap_rcu_lock);
269 static struct cxgb4_uld_info ulds[CXGB4_ULD_MAX];
270 static const char *uld_str[] = { "RDMA", "iSCSI" };
272 static void link_report(struct net_device *dev)
274 if (!netif_carrier_ok(dev))
275 netdev_info(dev, "link down\n");
277 static const char *fc[] = { "no", "Rx", "Tx", "Tx/Rx" };
280 const struct port_info *p = netdev_priv(dev);
282 switch (p->link_cfg.speed) {
296 pr_info("%s: unsupported speed: %d\n",
297 dev->name, p->link_cfg.speed);
301 netdev_info(dev, "link up, %s, full-duplex, %s PAUSE\n", s,
306 #ifdef CONFIG_CHELSIO_T4_DCB
307 /* Set up/tear down Data Center Bridging Priority mapping for a net device. */
308 static void dcb_tx_queue_prio_enable(struct net_device *dev, int enable)
310 struct port_info *pi = netdev_priv(dev);
311 struct adapter *adap = pi->adapter;
312 struct sge_eth_txq *txq = &adap->sge.ethtxq[pi->first_qset];
315 /* We use a simple mapping of Port TX Queue Index to DCB
316 * Priority when we're enabling DCB.
318 for (i = 0; i < pi->nqsets; i++, txq++) {
322 name = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DMAQ) |
324 FW_PARAMS_PARAM_DMAQ_EQ_DCBPRIO_ETH) |
325 FW_PARAMS_PARAM_YZ_V(txq->q.cntxt_id));
326 value = enable ? i : 0xffffffff;
328 /* Since we can be called while atomic (from "interrupt
329 * level") we need to issue the Set Parameters Commannd
330 * without sleeping (timeout < 0).
332 err = t4_set_params_timeout(adap, adap->mbox, adap->pf, 0, 1,
334 -FW_CMD_MAX_TIMEOUT);
337 dev_err(adap->pdev_dev,
338 "Can't %s DCB Priority on port %d, TX Queue %d: err=%d\n",
339 enable ? "set" : "unset", pi->port_id, i, -err);
341 txq->dcb_prio = value;
344 #endif /* CONFIG_CHELSIO_T4_DCB */
346 void t4_os_link_changed(struct adapter *adapter, int port_id, int link_stat)
348 struct net_device *dev = adapter->port[port_id];
350 /* Skip changes from disabled ports. */
351 if (netif_running(dev) && link_stat != netif_carrier_ok(dev)) {
353 netif_carrier_on(dev);
355 #ifdef CONFIG_CHELSIO_T4_DCB
356 cxgb4_dcb_state_init(dev);
357 dcb_tx_queue_prio_enable(dev, false);
358 #endif /* CONFIG_CHELSIO_T4_DCB */
359 netif_carrier_off(dev);
366 void t4_os_portmod_changed(const struct adapter *adap, int port_id)
368 static const char *mod_str[] = {
369 NULL, "LR", "SR", "ER", "passive DA", "active DA", "LRM"
372 const struct net_device *dev = adap->port[port_id];
373 const struct port_info *pi = netdev_priv(dev);
375 if (pi->mod_type == FW_PORT_MOD_TYPE_NONE)
376 netdev_info(dev, "port module unplugged\n");
377 else if (pi->mod_type < ARRAY_SIZE(mod_str))
378 netdev_info(dev, "%s module inserted\n", mod_str[pi->mod_type]);
382 * Configure the exact and hash address filters to handle a port's multicast
383 * and secondary unicast MAC addresses.
385 static int set_addr_filters(const struct net_device *dev, bool sleep)
393 const struct netdev_hw_addr *ha;
394 int uc_cnt = netdev_uc_count(dev);
395 int mc_cnt = netdev_mc_count(dev);
396 const struct port_info *pi = netdev_priv(dev);
397 unsigned int mb = pi->adapter->pf;
399 /* first do the secondary unicast addresses */
400 netdev_for_each_uc_addr(ha, dev) {
401 addr[naddr++] = ha->addr;
402 if (--uc_cnt == 0 || naddr >= ARRAY_SIZE(addr)) {
403 ret = t4_alloc_mac_filt(pi->adapter, mb, pi->viid, free,
404 naddr, addr, filt_idx, &uhash, sleep);
413 /* next set up the multicast addresses */
414 netdev_for_each_mc_addr(ha, dev) {
415 addr[naddr++] = ha->addr;
416 if (--mc_cnt == 0 || naddr >= ARRAY_SIZE(addr)) {
417 ret = t4_alloc_mac_filt(pi->adapter, mb, pi->viid, free,
418 naddr, addr, filt_idx, &mhash, sleep);
427 return t4_set_addr_hash(pi->adapter, mb, pi->viid, uhash != 0,
428 uhash | mhash, sleep);
431 int dbfifo_int_thresh = 10; /* 10 == 640 entry threshold */
432 module_param(dbfifo_int_thresh, int, 0644);
433 MODULE_PARM_DESC(dbfifo_int_thresh, "doorbell fifo interrupt threshold");
436 * usecs to sleep while draining the dbfifo
438 static int dbfifo_drain_delay = 1000;
439 module_param(dbfifo_drain_delay, int, 0644);
440 MODULE_PARM_DESC(dbfifo_drain_delay,
441 "usecs to sleep while draining the dbfifo");
444 * Set Rx properties of a port, such as promiscruity, address filters, and MTU.
445 * If @mtu is -1 it is left unchanged.
447 static int set_rxmode(struct net_device *dev, int mtu, bool sleep_ok)
450 struct port_info *pi = netdev_priv(dev);
452 ret = set_addr_filters(dev, sleep_ok);
454 ret = t4_set_rxmode(pi->adapter, pi->adapter->pf, pi->viid, mtu,
455 (dev->flags & IFF_PROMISC) ? 1 : 0,
456 (dev->flags & IFF_ALLMULTI) ? 1 : 0, 1, -1,
462 * link_start - enable a port
463 * @dev: the port to enable
465 * Performs the MAC and PHY actions needed to enable a port.
467 static int link_start(struct net_device *dev)
470 struct port_info *pi = netdev_priv(dev);
471 unsigned int mb = pi->adapter->pf;
474 * We do not set address filters and promiscuity here, the stack does
475 * that step explicitly.
477 ret = t4_set_rxmode(pi->adapter, mb, pi->viid, dev->mtu, -1, -1, -1,
478 !!(dev->features & NETIF_F_HW_VLAN_CTAG_RX), true);
480 ret = t4_change_mac(pi->adapter, mb, pi->viid,
481 pi->xact_addr_filt, dev->dev_addr, true,
484 pi->xact_addr_filt = ret;
489 ret = t4_link_l1cfg(pi->adapter, mb, pi->tx_chan,
493 ret = t4_enable_vi_params(pi->adapter, mb, pi->viid, true,
494 true, CXGB4_DCB_ENABLED);
501 int cxgb4_dcb_enabled(const struct net_device *dev)
503 #ifdef CONFIG_CHELSIO_T4_DCB
504 struct port_info *pi = netdev_priv(dev);
506 if (!pi->dcb.enabled)
509 return ((pi->dcb.state == CXGB4_DCB_STATE_FW_ALLSYNCED) ||
510 (pi->dcb.state == CXGB4_DCB_STATE_HOST));
515 EXPORT_SYMBOL(cxgb4_dcb_enabled);
517 #ifdef CONFIG_CHELSIO_T4_DCB
518 /* Handle a Data Center Bridging update message from the firmware. */
519 static void dcb_rpl(struct adapter *adap, const struct fw_port_cmd *pcmd)
521 int port = FW_PORT_CMD_PORTID_G(ntohl(pcmd->op_to_portid));
522 struct net_device *dev = adap->port[port];
523 int old_dcb_enabled = cxgb4_dcb_enabled(dev);
526 cxgb4_dcb_handle_fw_update(adap, pcmd);
527 new_dcb_enabled = cxgb4_dcb_enabled(dev);
529 /* If the DCB has become enabled or disabled on the port then we're
530 * going to need to set up/tear down DCB Priority parameters for the
531 * TX Queues associated with the port.
533 if (new_dcb_enabled != old_dcb_enabled)
534 dcb_tx_queue_prio_enable(dev, new_dcb_enabled);
536 #endif /* CONFIG_CHELSIO_T4_DCB */
538 /* Clear a filter and release any of its resources that we own. This also
539 * clears the filter's "pending" status.
541 static void clear_filter(struct adapter *adap, struct filter_entry *f)
543 /* If the new or old filter have loopback rewriteing rules then we'll
544 * need to free any existing Layer Two Table (L2T) entries of the old
545 * filter rule. The firmware will handle freeing up any Source MAC
546 * Table (SMT) entries used for rewriting Source MAC Addresses in
550 cxgb4_l2t_release(f->l2t);
552 /* The zeroing of the filter rule below clears the filter valid,
553 * pending, locked flags, l2t pointer, etc. so it's all we need for
556 memset(f, 0, sizeof(*f));
559 /* Handle a filter write/deletion reply.
561 static void filter_rpl(struct adapter *adap, const struct cpl_set_tcb_rpl *rpl)
563 unsigned int idx = GET_TID(rpl);
564 unsigned int nidx = idx - adap->tids.ftid_base;
566 struct filter_entry *f;
568 if (idx >= adap->tids.ftid_base && nidx <
569 (adap->tids.nftids + adap->tids.nsftids)) {
571 ret = TCB_COOKIE_G(rpl->cookie);
572 f = &adap->tids.ftid_tab[idx];
574 if (ret == FW_FILTER_WR_FLT_DELETED) {
575 /* Clear the filter when we get confirmation from the
576 * hardware that the filter has been deleted.
578 clear_filter(adap, f);
579 } else if (ret == FW_FILTER_WR_SMT_TBL_FULL) {
580 dev_err(adap->pdev_dev, "filter %u setup failed due to full SMT\n",
582 clear_filter(adap, f);
583 } else if (ret == FW_FILTER_WR_FLT_ADDED) {
584 f->smtidx = (be64_to_cpu(rpl->oldval) >> 24) & 0xff;
585 f->pending = 0; /* asynchronous setup completed */
588 /* Something went wrong. Issue a warning about the
589 * problem and clear everything out.
591 dev_err(adap->pdev_dev, "filter %u setup failed with error %u\n",
593 clear_filter(adap, f);
598 /* Response queue handler for the FW event queue.
600 static int fwevtq_handler(struct sge_rspq *q, const __be64 *rsp,
601 const struct pkt_gl *gl)
603 u8 opcode = ((const struct rss_header *)rsp)->opcode;
605 rsp++; /* skip RSS header */
607 /* FW can send EGR_UPDATEs encapsulated in a CPL_FW4_MSG.
609 if (unlikely(opcode == CPL_FW4_MSG &&
610 ((const struct cpl_fw4_msg *)rsp)->type == FW_TYPE_RSSCPL)) {
612 opcode = ((const struct rss_header *)rsp)->opcode;
614 if (opcode != CPL_SGE_EGR_UPDATE) {
615 dev_err(q->adap->pdev_dev, "unexpected FW4/CPL %#x on FW event queue\n"
621 if (likely(opcode == CPL_SGE_EGR_UPDATE)) {
622 const struct cpl_sge_egr_update *p = (void *)rsp;
623 unsigned int qid = EGR_QID_G(ntohl(p->opcode_qid));
626 txq = q->adap->sge.egr_map[qid - q->adap->sge.egr_start];
628 if ((u8 *)txq < (u8 *)q->adap->sge.ofldtxq) {
629 struct sge_eth_txq *eq;
631 eq = container_of(txq, struct sge_eth_txq, q);
632 netif_tx_wake_queue(eq->txq);
634 struct sge_ofld_txq *oq;
636 oq = container_of(txq, struct sge_ofld_txq, q);
637 tasklet_schedule(&oq->qresume_tsk);
639 } else if (opcode == CPL_FW6_MSG || opcode == CPL_FW4_MSG) {
640 const struct cpl_fw6_msg *p = (void *)rsp;
642 #ifdef CONFIG_CHELSIO_T4_DCB
643 const struct fw_port_cmd *pcmd = (const void *)p->data;
644 unsigned int cmd = FW_CMD_OP_G(ntohl(pcmd->op_to_portid));
645 unsigned int action =
646 FW_PORT_CMD_ACTION_G(ntohl(pcmd->action_to_len16));
648 if (cmd == FW_PORT_CMD &&
649 action == FW_PORT_ACTION_GET_PORT_INFO) {
650 int port = FW_PORT_CMD_PORTID_G(
651 be32_to_cpu(pcmd->op_to_portid));
652 struct net_device *dev = q->adap->port[port];
653 int state_input = ((pcmd->u.info.dcbxdis_pkd &
654 FW_PORT_CMD_DCBXDIS_F)
655 ? CXGB4_DCB_INPUT_FW_DISABLED
656 : CXGB4_DCB_INPUT_FW_ENABLED);
658 cxgb4_dcb_state_fsm(dev, state_input);
661 if (cmd == FW_PORT_CMD &&
662 action == FW_PORT_ACTION_L2_DCB_CFG)
663 dcb_rpl(q->adap, pcmd);
667 t4_handle_fw_rpl(q->adap, p->data);
668 } else if (opcode == CPL_L2T_WRITE_RPL) {
669 const struct cpl_l2t_write_rpl *p = (void *)rsp;
671 do_l2t_write_rpl(q->adap, p);
672 } else if (opcode == CPL_SET_TCB_RPL) {
673 const struct cpl_set_tcb_rpl *p = (void *)rsp;
675 filter_rpl(q->adap, p);
677 dev_err(q->adap->pdev_dev,
678 "unexpected CPL %#x on FW event queue\n", opcode);
684 * uldrx_handler - response queue handler for ULD queues
685 * @q: the response queue that received the packet
686 * @rsp: the response queue descriptor holding the offload message
687 * @gl: the gather list of packet fragments
689 * Deliver an ingress offload packet to a ULD. All processing is done by
690 * the ULD, we just maintain statistics.
692 static int uldrx_handler(struct sge_rspq *q, const __be64 *rsp,
693 const struct pkt_gl *gl)
695 struct sge_ofld_rxq *rxq = container_of(q, struct sge_ofld_rxq, rspq);
697 /* FW can send CPLs encapsulated in a CPL_FW4_MSG.
699 if (((const struct rss_header *)rsp)->opcode == CPL_FW4_MSG &&
700 ((const struct cpl_fw4_msg *)(rsp + 1))->type == FW_TYPE_RSSCPL)
703 if (ulds[q->uld].rx_handler(q->adap->uld_handle[q->uld], rsp, gl)) {
709 else if (gl == CXGB4_MSG_AN)
716 static void disable_msi(struct adapter *adapter)
718 if (adapter->flags & USING_MSIX) {
719 pci_disable_msix(adapter->pdev);
720 adapter->flags &= ~USING_MSIX;
721 } else if (adapter->flags & USING_MSI) {
722 pci_disable_msi(adapter->pdev);
723 adapter->flags &= ~USING_MSI;
728 * Interrupt handler for non-data events used with MSI-X.
730 static irqreturn_t t4_nondata_intr(int irq, void *cookie)
732 struct adapter *adap = cookie;
733 u32 v = t4_read_reg(adap, MYPF_REG(PL_PF_INT_CAUSE_A));
737 t4_write_reg(adap, MYPF_REG(PL_PF_INT_CAUSE_A), v);
739 if (adap->flags & MASTER_PF)
740 t4_slow_intr_handler(adap);
745 * Name the MSI-X interrupts.
747 static void name_msix_vecs(struct adapter *adap)
749 int i, j, msi_idx = 2, n = sizeof(adap->msix_info[0].desc);
751 /* non-data interrupts */
752 snprintf(adap->msix_info[0].desc, n, "%s", adap->port[0]->name);
755 snprintf(adap->msix_info[1].desc, n, "%s-FWeventq",
756 adap->port[0]->name);
758 /* Ethernet queues */
759 for_each_port(adap, j) {
760 struct net_device *d = adap->port[j];
761 const struct port_info *pi = netdev_priv(d);
763 for (i = 0; i < pi->nqsets; i++, msi_idx++)
764 snprintf(adap->msix_info[msi_idx].desc, n, "%s-Rx%d",
769 for_each_ofldrxq(&adap->sge, i)
770 snprintf(adap->msix_info[msi_idx++].desc, n, "%s-ofld%d",
771 adap->port[0]->name, i);
773 for_each_rdmarxq(&adap->sge, i)
774 snprintf(adap->msix_info[msi_idx++].desc, n, "%s-rdma%d",
775 adap->port[0]->name, i);
777 for_each_rdmaciq(&adap->sge, i)
778 snprintf(adap->msix_info[msi_idx++].desc, n, "%s-rdma-ciq%d",
779 adap->port[0]->name, i);
782 static int request_msix_queue_irqs(struct adapter *adap)
784 struct sge *s = &adap->sge;
785 int err, ethqidx, ofldqidx = 0, rdmaqidx = 0, rdmaciqqidx = 0;
788 err = request_irq(adap->msix_info[1].vec, t4_sge_intr_msix, 0,
789 adap->msix_info[1].desc, &s->fw_evtq);
793 for_each_ethrxq(s, ethqidx) {
794 err = request_irq(adap->msix_info[msi_index].vec,
796 adap->msix_info[msi_index].desc,
797 &s->ethrxq[ethqidx].rspq);
802 for_each_ofldrxq(s, ofldqidx) {
803 err = request_irq(adap->msix_info[msi_index].vec,
805 adap->msix_info[msi_index].desc,
806 &s->ofldrxq[ofldqidx].rspq);
811 for_each_rdmarxq(s, rdmaqidx) {
812 err = request_irq(adap->msix_info[msi_index].vec,
814 adap->msix_info[msi_index].desc,
815 &s->rdmarxq[rdmaqidx].rspq);
820 for_each_rdmaciq(s, rdmaciqqidx) {
821 err = request_irq(adap->msix_info[msi_index].vec,
823 adap->msix_info[msi_index].desc,
824 &s->rdmaciq[rdmaciqqidx].rspq);
832 while (--rdmaciqqidx >= 0)
833 free_irq(adap->msix_info[--msi_index].vec,
834 &s->rdmaciq[rdmaciqqidx].rspq);
835 while (--rdmaqidx >= 0)
836 free_irq(adap->msix_info[--msi_index].vec,
837 &s->rdmarxq[rdmaqidx].rspq);
838 while (--ofldqidx >= 0)
839 free_irq(adap->msix_info[--msi_index].vec,
840 &s->ofldrxq[ofldqidx].rspq);
841 while (--ethqidx >= 0)
842 free_irq(adap->msix_info[--msi_index].vec,
843 &s->ethrxq[ethqidx].rspq);
844 free_irq(adap->msix_info[1].vec, &s->fw_evtq);
848 static void free_msix_queue_irqs(struct adapter *adap)
850 int i, msi_index = 2;
851 struct sge *s = &adap->sge;
853 free_irq(adap->msix_info[1].vec, &s->fw_evtq);
854 for_each_ethrxq(s, i)
855 free_irq(adap->msix_info[msi_index++].vec, &s->ethrxq[i].rspq);
856 for_each_ofldrxq(s, i)
857 free_irq(adap->msix_info[msi_index++].vec, &s->ofldrxq[i].rspq);
858 for_each_rdmarxq(s, i)
859 free_irq(adap->msix_info[msi_index++].vec, &s->rdmarxq[i].rspq);
860 for_each_rdmaciq(s, i)
861 free_irq(adap->msix_info[msi_index++].vec, &s->rdmaciq[i].rspq);
865 * cxgb4_write_rss - write the RSS table for a given port
867 * @queues: array of queue indices for RSS
869 * Sets up the portion of the HW RSS table for the port's VI to distribute
870 * packets to the Rx queues in @queues.
871 * Should never be called before setting up sge eth rx queues
873 int cxgb4_write_rss(const struct port_info *pi, const u16 *queues)
877 struct adapter *adapter = pi->adapter;
878 const struct sge_eth_rxq *rxq;
880 rxq = &adapter->sge.ethrxq[pi->first_qset];
881 rss = kmalloc(pi->rss_size * sizeof(u16), GFP_KERNEL);
885 /* map the queue indices to queue ids */
886 for (i = 0; i < pi->rss_size; i++, queues++)
887 rss[i] = rxq[*queues].rspq.abs_id;
889 err = t4_config_rss_range(adapter, adapter->pf, pi->viid, 0,
890 pi->rss_size, rss, pi->rss_size);
891 /* If Tunnel All Lookup isn't specified in the global RSS
892 * Configuration, then we need to specify a default Ingress
893 * Queue for any ingress packets which aren't hashed. We'll
894 * use our first ingress queue ...
897 err = t4_config_vi_rss(adapter, adapter->mbox, pi->viid,
898 FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN_F |
899 FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN_F |
900 FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN_F |
901 FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN_F |
902 FW_RSS_VI_CONFIG_CMD_UDPEN_F,
909 * setup_rss - configure RSS
912 * Sets up RSS for each port.
914 static int setup_rss(struct adapter *adap)
918 for_each_port(adap, i) {
919 const struct port_info *pi = adap2pinfo(adap, i);
921 /* Fill default values with equal distribution */
922 for (j = 0; j < pi->rss_size; j++)
923 pi->rss[j] = j % pi->nqsets;
925 err = cxgb4_write_rss(pi, pi->rss);
933 * Return the channel of the ingress queue with the given qid.
935 static unsigned int rxq_to_chan(const struct sge *p, unsigned int qid)
937 qid -= p->ingr_start;
938 return netdev2pinfo(p->ingr_map[qid]->netdev)->tx_chan;
942 * Wait until all NAPI handlers are descheduled.
944 static void quiesce_rx(struct adapter *adap)
948 for (i = 0; i < adap->sge.ingr_sz; i++) {
949 struct sge_rspq *q = adap->sge.ingr_map[i];
951 if (q && q->handler) {
952 napi_disable(&q->napi);
954 while (!cxgb_poll_lock_napi(q))
962 /* Disable interrupt and napi handler */
963 static void disable_interrupts(struct adapter *adap)
965 if (adap->flags & FULL_INIT_DONE) {
966 t4_intr_disable(adap);
967 if (adap->flags & USING_MSIX) {
968 free_msix_queue_irqs(adap);
969 free_irq(adap->msix_info[0].vec, adap);
971 free_irq(adap->pdev->irq, adap);
978 * Enable NAPI scheduling and interrupt generation for all Rx queues.
980 static void enable_rx(struct adapter *adap)
984 for (i = 0; i < adap->sge.ingr_sz; i++) {
985 struct sge_rspq *q = adap->sge.ingr_map[i];
990 cxgb_busy_poll_init_lock(q);
991 napi_enable(&q->napi);
993 /* 0-increment GTS to start the timer and enable interrupts */
994 t4_write_reg(adap, MYPF_REG(SGE_PF_GTS_A),
995 SEINTARM_V(q->intr_params) |
996 INGRESSQID_V(q->cntxt_id));
1000 static int alloc_ofld_rxqs(struct adapter *adap, struct sge_ofld_rxq *q,
1001 unsigned int nq, unsigned int per_chan, int msi_idx,
1006 for (i = 0; i < nq; i++, q++) {
1009 err = t4_sge_alloc_rxq(adap, &q->rspq, false,
1010 adap->port[i / per_chan],
1011 msi_idx, q->fl.size ? &q->fl : NULL,
1015 memset(&q->stats, 0, sizeof(q->stats));
1017 ids[i] = q->rspq.abs_id;
1023 * setup_sge_queues - configure SGE Tx/Rx/response queues
1024 * @adap: the adapter
1026 * Determines how many sets of SGE queues to use and initializes them.
1027 * We support multiple queue sets per port if we have MSI-X, otherwise
1028 * just one queue set per port.
1030 static int setup_sge_queues(struct adapter *adap)
1032 int err, msi_idx, i, j;
1033 struct sge *s = &adap->sge;
1035 bitmap_zero(s->starving_fl, s->egr_sz);
1036 bitmap_zero(s->txq_maperr, s->egr_sz);
1038 if (adap->flags & USING_MSIX)
1039 msi_idx = 1; /* vector 0 is for non-queue interrupts */
1041 err = t4_sge_alloc_rxq(adap, &s->intrq, false, adap->port[0], 0,
1045 msi_idx = -((int)s->intrq.abs_id + 1);
1048 /* NOTE: If you add/delete any Ingress/Egress Queue allocations in here,
1049 * don't forget to update the following which need to be
1050 * synchronized to and changes here.
1052 * 1. The calculations of MAX_INGQ in cxgb4.h.
1054 * 2. Update enable_msix/name_msix_vecs/request_msix_queue_irqs
1055 * to accommodate any new/deleted Ingress Queues
1056 * which need MSI-X Vectors.
1058 * 3. Update sge_qinfo_show() to include information on the
1059 * new/deleted queues.
1061 err = t4_sge_alloc_rxq(adap, &s->fw_evtq, true, adap->port[0],
1062 msi_idx, NULL, fwevtq_handler, -1);
1064 freeout: t4_free_sge_resources(adap);
1068 for_each_port(adap, i) {
1069 struct net_device *dev = adap->port[i];
1070 struct port_info *pi = netdev_priv(dev);
1071 struct sge_eth_rxq *q = &s->ethrxq[pi->first_qset];
1072 struct sge_eth_txq *t = &s->ethtxq[pi->first_qset];
1074 for (j = 0; j < pi->nqsets; j++, q++) {
1077 err = t4_sge_alloc_rxq(adap, &q->rspq, false, dev,
1080 t4_get_mps_bg_map(adap,
1085 memset(&q->stats, 0, sizeof(q->stats));
1087 for (j = 0; j < pi->nqsets; j++, t++) {
1088 err = t4_sge_alloc_eth_txq(adap, t, dev,
1089 netdev_get_tx_queue(dev, j),
1090 s->fw_evtq.cntxt_id);
1096 j = s->ofldqsets / adap->params.nports; /* ofld queues per channel */
1097 for_each_ofldrxq(s, i) {
1098 err = t4_sge_alloc_ofld_txq(adap, &s->ofldtxq[i],
1100 s->fw_evtq.cntxt_id);
1105 #define ALLOC_OFLD_RXQS(firstq, nq, per_chan, ids) do { \
1106 err = alloc_ofld_rxqs(adap, firstq, nq, per_chan, msi_idx, ids); \
1113 ALLOC_OFLD_RXQS(s->ofldrxq, s->ofldqsets, j, s->ofld_rxq);
1114 ALLOC_OFLD_RXQS(s->rdmarxq, s->rdmaqs, 1, s->rdma_rxq);
1115 j = s->rdmaciqs / adap->params.nports; /* rdmaq queues per channel */
1116 ALLOC_OFLD_RXQS(s->rdmaciq, s->rdmaciqs, j, s->rdma_ciq);
1118 #undef ALLOC_OFLD_RXQS
1120 for_each_port(adap, i) {
1122 * Note that ->rdmarxq[i].rspq.cntxt_id below is 0 if we don't
1123 * have RDMA queues, and that's the right value.
1125 err = t4_sge_alloc_ctrl_txq(adap, &s->ctrlq[i], adap->port[i],
1126 s->fw_evtq.cntxt_id,
1127 s->rdmarxq[i].rspq.cntxt_id);
1132 t4_write_reg(adap, is_t4(adap->params.chip) ?
1133 MPS_TRC_RSS_CONTROL_A :
1134 MPS_T5_TRC_RSS_CONTROL_A,
1135 RSSCONTROL_V(netdev2pinfo(adap->port[0])->tx_chan) |
1136 QUEUENUMBER_V(s->ethrxq[0].rspq.abs_id));
1141 * Allocate a chunk of memory using kmalloc or, if that fails, vmalloc.
1142 * The allocated memory is cleared.
1144 void *t4_alloc_mem(size_t size)
1146 void *p = kzalloc(size, GFP_KERNEL | __GFP_NOWARN);
1154 * Free memory allocated through alloc_mem().
1156 void t4_free_mem(void *addr)
1161 /* Send a Work Request to write the filter at a specified index. We construct
1162 * a Firmware Filter Work Request to have the work done and put the indicated
1163 * filter into "pending" mode which will prevent any further actions against
1164 * it till we get a reply from the firmware on the completion status of the
1167 static int set_filter_wr(struct adapter *adapter, int fidx)
1169 struct filter_entry *f = &adapter->tids.ftid_tab[fidx];
1170 struct sk_buff *skb;
1171 struct fw_filter_wr *fwr;
1174 skb = alloc_skb(sizeof(*fwr), GFP_KERNEL);
1178 /* If the new filter requires loopback Destination MAC and/or VLAN
1179 * rewriting then we need to allocate a Layer 2 Table (L2T) entry for
1182 if (f->fs.newdmac || f->fs.newvlan) {
1183 /* allocate L2T entry for new filter */
1184 f->l2t = t4_l2t_alloc_switching(adapter->l2t);
1185 if (f->l2t == NULL) {
1189 if (t4_l2t_set_switching(adapter, f->l2t, f->fs.vlan,
1190 f->fs.eport, f->fs.dmac)) {
1191 cxgb4_l2t_release(f->l2t);
1198 ftid = adapter->tids.ftid_base + fidx;
1200 fwr = (struct fw_filter_wr *)__skb_put(skb, sizeof(*fwr));
1201 memset(fwr, 0, sizeof(*fwr));
1203 /* It would be nice to put most of the following in t4_hw.c but most
1204 * of the work is translating the cxgbtool ch_filter_specification
1205 * into the Work Request and the definition of that structure is
1206 * currently in cxgbtool.h which isn't appropriate to pull into the
1207 * common code. We may eventually try to come up with a more neutral
1208 * filter specification structure but for now it's easiest to simply
1209 * put this fairly direct code in line ...
1211 fwr->op_pkd = htonl(FW_WR_OP_V(FW_FILTER_WR));
1212 fwr->len16_pkd = htonl(FW_WR_LEN16_V(sizeof(*fwr)/16));
1214 htonl(FW_FILTER_WR_TID_V(ftid) |
1215 FW_FILTER_WR_RQTYPE_V(f->fs.type) |
1216 FW_FILTER_WR_NOREPLY_V(0) |
1217 FW_FILTER_WR_IQ_V(f->fs.iq));
1218 fwr->del_filter_to_l2tix =
1219 htonl(FW_FILTER_WR_RPTTID_V(f->fs.rpttid) |
1220 FW_FILTER_WR_DROP_V(f->fs.action == FILTER_DROP) |
1221 FW_FILTER_WR_DIRSTEER_V(f->fs.dirsteer) |
1222 FW_FILTER_WR_MASKHASH_V(f->fs.maskhash) |
1223 FW_FILTER_WR_DIRSTEERHASH_V(f->fs.dirsteerhash) |
1224 FW_FILTER_WR_LPBK_V(f->fs.action == FILTER_SWITCH) |
1225 FW_FILTER_WR_DMAC_V(f->fs.newdmac) |
1226 FW_FILTER_WR_SMAC_V(f->fs.newsmac) |
1227 FW_FILTER_WR_INSVLAN_V(f->fs.newvlan == VLAN_INSERT ||
1228 f->fs.newvlan == VLAN_REWRITE) |
1229 FW_FILTER_WR_RMVLAN_V(f->fs.newvlan == VLAN_REMOVE ||
1230 f->fs.newvlan == VLAN_REWRITE) |
1231 FW_FILTER_WR_HITCNTS_V(f->fs.hitcnts) |
1232 FW_FILTER_WR_TXCHAN_V(f->fs.eport) |
1233 FW_FILTER_WR_PRIO_V(f->fs.prio) |
1234 FW_FILTER_WR_L2TIX_V(f->l2t ? f->l2t->idx : 0));
1235 fwr->ethtype = htons(f->fs.val.ethtype);
1236 fwr->ethtypem = htons(f->fs.mask.ethtype);
1237 fwr->frag_to_ovlan_vldm =
1238 (FW_FILTER_WR_FRAG_V(f->fs.val.frag) |
1239 FW_FILTER_WR_FRAGM_V(f->fs.mask.frag) |
1240 FW_FILTER_WR_IVLAN_VLD_V(f->fs.val.ivlan_vld) |
1241 FW_FILTER_WR_OVLAN_VLD_V(f->fs.val.ovlan_vld) |
1242 FW_FILTER_WR_IVLAN_VLDM_V(f->fs.mask.ivlan_vld) |
1243 FW_FILTER_WR_OVLAN_VLDM_V(f->fs.mask.ovlan_vld));
1245 fwr->rx_chan_rx_rpl_iq =
1246 htons(FW_FILTER_WR_RX_CHAN_V(0) |
1247 FW_FILTER_WR_RX_RPL_IQ_V(adapter->sge.fw_evtq.abs_id));
1248 fwr->maci_to_matchtypem =
1249 htonl(FW_FILTER_WR_MACI_V(f->fs.val.macidx) |
1250 FW_FILTER_WR_MACIM_V(f->fs.mask.macidx) |
1251 FW_FILTER_WR_FCOE_V(f->fs.val.fcoe) |
1252 FW_FILTER_WR_FCOEM_V(f->fs.mask.fcoe) |
1253 FW_FILTER_WR_PORT_V(f->fs.val.iport) |
1254 FW_FILTER_WR_PORTM_V(f->fs.mask.iport) |
1255 FW_FILTER_WR_MATCHTYPE_V(f->fs.val.matchtype) |
1256 FW_FILTER_WR_MATCHTYPEM_V(f->fs.mask.matchtype));
1257 fwr->ptcl = f->fs.val.proto;
1258 fwr->ptclm = f->fs.mask.proto;
1259 fwr->ttyp = f->fs.val.tos;
1260 fwr->ttypm = f->fs.mask.tos;
1261 fwr->ivlan = htons(f->fs.val.ivlan);
1262 fwr->ivlanm = htons(f->fs.mask.ivlan);
1263 fwr->ovlan = htons(f->fs.val.ovlan);
1264 fwr->ovlanm = htons(f->fs.mask.ovlan);
1265 memcpy(fwr->lip, f->fs.val.lip, sizeof(fwr->lip));
1266 memcpy(fwr->lipm, f->fs.mask.lip, sizeof(fwr->lipm));
1267 memcpy(fwr->fip, f->fs.val.fip, sizeof(fwr->fip));
1268 memcpy(fwr->fipm, f->fs.mask.fip, sizeof(fwr->fipm));
1269 fwr->lp = htons(f->fs.val.lport);
1270 fwr->lpm = htons(f->fs.mask.lport);
1271 fwr->fp = htons(f->fs.val.fport);
1272 fwr->fpm = htons(f->fs.mask.fport);
1274 memcpy(fwr->sma, f->fs.smac, sizeof(fwr->sma));
1276 /* Mark the filter as "pending" and ship off the Filter Work Request.
1277 * When we get the Work Request Reply we'll clear the pending status.
1280 set_wr_txq(skb, CPL_PRIORITY_CONTROL, f->fs.val.iport & 0x3);
1281 t4_ofld_send(adapter, skb);
1285 /* Delete the filter at a specified index.
1287 static int del_filter_wr(struct adapter *adapter, int fidx)
1289 struct filter_entry *f = &adapter->tids.ftid_tab[fidx];
1290 struct sk_buff *skb;
1291 struct fw_filter_wr *fwr;
1292 unsigned int len, ftid;
1295 ftid = adapter->tids.ftid_base + fidx;
1297 skb = alloc_skb(len, GFP_KERNEL);
1301 fwr = (struct fw_filter_wr *)__skb_put(skb, len);
1302 t4_mk_filtdelwr(ftid, fwr, adapter->sge.fw_evtq.abs_id);
1304 /* Mark the filter as "pending" and ship off the Filter Work Request.
1305 * When we get the Work Request Reply we'll clear the pending status.
1308 t4_mgmt_tx(adapter, skb);
1312 static u16 cxgb_select_queue(struct net_device *dev, struct sk_buff *skb,
1313 void *accel_priv, select_queue_fallback_t fallback)
1317 #ifdef CONFIG_CHELSIO_T4_DCB
1318 /* If a Data Center Bridging has been successfully negotiated on this
1319 * link then we'll use the skb's priority to map it to a TX Queue.
1320 * The skb's priority is determined via the VLAN Tag Priority Code
1323 if (cxgb4_dcb_enabled(dev)) {
1327 err = vlan_get_tag(skb, &vlan_tci);
1328 if (unlikely(err)) {
1329 if (net_ratelimit())
1331 "TX Packet without VLAN Tag on DCB Link\n");
1334 txq = (vlan_tci & VLAN_PRIO_MASK) >> VLAN_PRIO_SHIFT;
1335 #ifdef CONFIG_CHELSIO_T4_FCOE
1336 if (skb->protocol == htons(ETH_P_FCOE))
1337 txq = skb->priority & 0x7;
1338 #endif /* CONFIG_CHELSIO_T4_FCOE */
1342 #endif /* CONFIG_CHELSIO_T4_DCB */
1345 txq = (skb_rx_queue_recorded(skb)
1346 ? skb_get_rx_queue(skb)
1347 : smp_processor_id());
1349 while (unlikely(txq >= dev->real_num_tx_queues))
1350 txq -= dev->real_num_tx_queues;
1355 return fallback(dev, skb) % dev->real_num_tx_queues;
1358 static int closest_timer(const struct sge *s, int time)
1360 int i, delta, match = 0, min_delta = INT_MAX;
1362 for (i = 0; i < ARRAY_SIZE(s->timer_val); i++) {
1363 delta = time - s->timer_val[i];
1366 if (delta < min_delta) {
1374 static int closest_thres(const struct sge *s, int thres)
1376 int i, delta, match = 0, min_delta = INT_MAX;
1378 for (i = 0; i < ARRAY_SIZE(s->counter_val); i++) {
1379 delta = thres - s->counter_val[i];
1382 if (delta < min_delta) {
1391 * cxgb4_set_rspq_intr_params - set a queue's interrupt holdoff parameters
1393 * @us: the hold-off time in us, or 0 to disable timer
1394 * @cnt: the hold-off packet count, or 0 to disable counter
1396 * Sets an Rx queue's interrupt hold-off time and packet count. At least
1397 * one of the two needs to be enabled for the queue to generate interrupts.
1399 int cxgb4_set_rspq_intr_params(struct sge_rspq *q,
1400 unsigned int us, unsigned int cnt)
1402 struct adapter *adap = q->adap;
1404 if ((us | cnt) == 0)
1411 new_idx = closest_thres(&adap->sge, cnt);
1412 if (q->desc && q->pktcnt_idx != new_idx) {
1413 /* the queue has already been created, update it */
1414 v = FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DMAQ) |
1415 FW_PARAMS_PARAM_X_V(
1416 FW_PARAMS_PARAM_DMAQ_IQ_INTCNTTHRESH) |
1417 FW_PARAMS_PARAM_YZ_V(q->cntxt_id);
1418 err = t4_set_params(adap, adap->mbox, adap->pf, 0, 1,
1423 q->pktcnt_idx = new_idx;
1426 us = us == 0 ? 6 : closest_timer(&adap->sge, us);
1427 q->intr_params = QINTR_TIMER_IDX_V(us) | QINTR_CNT_EN_V(cnt > 0);
1431 static int cxgb_set_features(struct net_device *dev, netdev_features_t features)
1433 const struct port_info *pi = netdev_priv(dev);
1434 netdev_features_t changed = dev->features ^ features;
1437 if (!(changed & NETIF_F_HW_VLAN_CTAG_RX))
1440 err = t4_set_rxmode(pi->adapter, pi->adapter->pf, pi->viid, -1,
1442 !!(features & NETIF_F_HW_VLAN_CTAG_RX), true);
1444 dev->features = features ^ NETIF_F_HW_VLAN_CTAG_RX;
1448 static int setup_debugfs(struct adapter *adap)
1450 if (IS_ERR_OR_NULL(adap->debugfs_root))
1453 #ifdef CONFIG_DEBUG_FS
1454 t4_setup_debugfs(adap);
1460 * upper-layer driver support
1464 * Allocate an active-open TID and set it to the supplied value.
1466 int cxgb4_alloc_atid(struct tid_info *t, void *data)
1470 spin_lock_bh(&t->atid_lock);
1472 union aopen_entry *p = t->afree;
1474 atid = (p - t->atid_tab) + t->atid_base;
1479 spin_unlock_bh(&t->atid_lock);
1482 EXPORT_SYMBOL(cxgb4_alloc_atid);
1485 * Release an active-open TID.
1487 void cxgb4_free_atid(struct tid_info *t, unsigned int atid)
1489 union aopen_entry *p = &t->atid_tab[atid - t->atid_base];
1491 spin_lock_bh(&t->atid_lock);
1495 spin_unlock_bh(&t->atid_lock);
1497 EXPORT_SYMBOL(cxgb4_free_atid);
1500 * Allocate a server TID and set it to the supplied value.
1502 int cxgb4_alloc_stid(struct tid_info *t, int family, void *data)
1506 spin_lock_bh(&t->stid_lock);
1507 if (family == PF_INET) {
1508 stid = find_first_zero_bit(t->stid_bmap, t->nstids);
1509 if (stid < t->nstids)
1510 __set_bit(stid, t->stid_bmap);
1514 stid = bitmap_find_free_region(t->stid_bmap, t->nstids, 2);
1519 t->stid_tab[stid].data = data;
1520 stid += t->stid_base;
1521 /* IPv6 requires max of 520 bits or 16 cells in TCAM
1522 * This is equivalent to 4 TIDs. With CLIP enabled it
1525 if (family == PF_INET)
1528 t->stids_in_use += 4;
1530 spin_unlock_bh(&t->stid_lock);
1533 EXPORT_SYMBOL(cxgb4_alloc_stid);
1535 /* Allocate a server filter TID and set it to the supplied value.
1537 int cxgb4_alloc_sftid(struct tid_info *t, int family, void *data)
1541 spin_lock_bh(&t->stid_lock);
1542 if (family == PF_INET) {
1543 stid = find_next_zero_bit(t->stid_bmap,
1544 t->nstids + t->nsftids, t->nstids);
1545 if (stid < (t->nstids + t->nsftids))
1546 __set_bit(stid, t->stid_bmap);
1553 t->stid_tab[stid].data = data;
1555 stid += t->sftid_base;
1558 spin_unlock_bh(&t->stid_lock);
1561 EXPORT_SYMBOL(cxgb4_alloc_sftid);
1563 /* Release a server TID.
1565 void cxgb4_free_stid(struct tid_info *t, unsigned int stid, int family)
1567 /* Is it a server filter TID? */
1568 if (t->nsftids && (stid >= t->sftid_base)) {
1569 stid -= t->sftid_base;
1572 stid -= t->stid_base;
1575 spin_lock_bh(&t->stid_lock);
1576 if (family == PF_INET)
1577 __clear_bit(stid, t->stid_bmap);
1579 bitmap_release_region(t->stid_bmap, stid, 2);
1580 t->stid_tab[stid].data = NULL;
1581 if (stid < t->nstids) {
1582 if (family == PF_INET)
1585 t->stids_in_use -= 4;
1589 spin_unlock_bh(&t->stid_lock);
1591 EXPORT_SYMBOL(cxgb4_free_stid);
1594 * Populate a TID_RELEASE WR. Caller must properly size the skb.
1596 static void mk_tid_release(struct sk_buff *skb, unsigned int chan,
1599 struct cpl_tid_release *req;
1601 set_wr_txq(skb, CPL_PRIORITY_SETUP, chan);
1602 req = (struct cpl_tid_release *)__skb_put(skb, sizeof(*req));
1603 INIT_TP_WR(req, tid);
1604 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_TID_RELEASE, tid));
1608 * Queue a TID release request and if necessary schedule a work queue to
1611 static void cxgb4_queue_tid_release(struct tid_info *t, unsigned int chan,
1614 void **p = &t->tid_tab[tid];
1615 struct adapter *adap = container_of(t, struct adapter, tids);
1617 spin_lock_bh(&adap->tid_release_lock);
1618 *p = adap->tid_release_head;
1619 /* Low 2 bits encode the Tx channel number */
1620 adap->tid_release_head = (void **)((uintptr_t)p | chan);
1621 if (!adap->tid_release_task_busy) {
1622 adap->tid_release_task_busy = true;
1623 queue_work(adap->workq, &adap->tid_release_task);
1625 spin_unlock_bh(&adap->tid_release_lock);
1629 * Process the list of pending TID release requests.
1631 static void process_tid_release_list(struct work_struct *work)
1633 struct sk_buff *skb;
1634 struct adapter *adap;
1636 adap = container_of(work, struct adapter, tid_release_task);
1638 spin_lock_bh(&adap->tid_release_lock);
1639 while (adap->tid_release_head) {
1640 void **p = adap->tid_release_head;
1641 unsigned int chan = (uintptr_t)p & 3;
1642 p = (void *)p - chan;
1644 adap->tid_release_head = *p;
1646 spin_unlock_bh(&adap->tid_release_lock);
1648 while (!(skb = alloc_skb(sizeof(struct cpl_tid_release),
1650 schedule_timeout_uninterruptible(1);
1652 mk_tid_release(skb, chan, p - adap->tids.tid_tab);
1653 t4_ofld_send(adap, skb);
1654 spin_lock_bh(&adap->tid_release_lock);
1656 adap->tid_release_task_busy = false;
1657 spin_unlock_bh(&adap->tid_release_lock);
1661 * Release a TID and inform HW. If we are unable to allocate the release
1662 * message we defer to a work queue.
1664 void cxgb4_remove_tid(struct tid_info *t, unsigned int chan, unsigned int tid)
1666 struct sk_buff *skb;
1667 struct adapter *adap = container_of(t, struct adapter, tids);
1669 WARN_ON(tid >= t->ntids);
1671 if (t->tid_tab[tid]) {
1672 t->tid_tab[tid] = NULL;
1673 if (t->hash_base && (tid >= t->hash_base))
1674 atomic_dec(&t->hash_tids_in_use);
1676 atomic_dec(&t->tids_in_use);
1679 skb = alloc_skb(sizeof(struct cpl_tid_release), GFP_ATOMIC);
1681 mk_tid_release(skb, chan, tid);
1682 t4_ofld_send(adap, skb);
1684 cxgb4_queue_tid_release(t, chan, tid);
1686 EXPORT_SYMBOL(cxgb4_remove_tid);
1689 * Allocate and initialize the TID tables. Returns 0 on success.
1691 static int tid_init(struct tid_info *t)
1694 unsigned int stid_bmap_size;
1695 unsigned int natids = t->natids;
1696 struct adapter *adap = container_of(t, struct adapter, tids);
1698 stid_bmap_size = BITS_TO_LONGS(t->nstids + t->nsftids);
1699 size = t->ntids * sizeof(*t->tid_tab) +
1700 natids * sizeof(*t->atid_tab) +
1701 t->nstids * sizeof(*t->stid_tab) +
1702 t->nsftids * sizeof(*t->stid_tab) +
1703 stid_bmap_size * sizeof(long) +
1704 t->nftids * sizeof(*t->ftid_tab) +
1705 t->nsftids * sizeof(*t->ftid_tab);
1707 t->tid_tab = t4_alloc_mem(size);
1711 t->atid_tab = (union aopen_entry *)&t->tid_tab[t->ntids];
1712 t->stid_tab = (struct serv_entry *)&t->atid_tab[natids];
1713 t->stid_bmap = (unsigned long *)&t->stid_tab[t->nstids + t->nsftids];
1714 t->ftid_tab = (struct filter_entry *)&t->stid_bmap[stid_bmap_size];
1715 spin_lock_init(&t->stid_lock);
1716 spin_lock_init(&t->atid_lock);
1718 t->stids_in_use = 0;
1719 t->sftids_in_use = 0;
1721 t->atids_in_use = 0;
1722 atomic_set(&t->tids_in_use, 0);
1723 atomic_set(&t->hash_tids_in_use, 0);
1725 /* Setup the free list for atid_tab and clear the stid bitmap. */
1728 t->atid_tab[natids - 1].next = &t->atid_tab[natids];
1729 t->afree = t->atid_tab;
1731 bitmap_zero(t->stid_bmap, t->nstids + t->nsftids);
1732 /* Reserve stid 0 for T4/T5 adapters */
1733 if (!t->stid_base &&
1734 (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5))
1735 __set_bit(0, t->stid_bmap);
1741 * cxgb4_create_server - create an IP server
1743 * @stid: the server TID
1744 * @sip: local IP address to bind server to
1745 * @sport: the server's TCP port
1746 * @queue: queue to direct messages from this server to
1748 * Create an IP server for the given port and address.
1749 * Returns <0 on error and one of the %NET_XMIT_* values on success.
1751 int cxgb4_create_server(const struct net_device *dev, unsigned int stid,
1752 __be32 sip, __be16 sport, __be16 vlan,
1756 struct sk_buff *skb;
1757 struct adapter *adap;
1758 struct cpl_pass_open_req *req;
1761 skb = alloc_skb(sizeof(*req), GFP_KERNEL);
1765 adap = netdev2adap(dev);
1766 req = (struct cpl_pass_open_req *)__skb_put(skb, sizeof(*req));
1768 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_PASS_OPEN_REQ, stid));
1769 req->local_port = sport;
1770 req->peer_port = htons(0);
1771 req->local_ip = sip;
1772 req->peer_ip = htonl(0);
1773 chan = rxq_to_chan(&adap->sge, queue);
1774 req->opt0 = cpu_to_be64(TX_CHAN_V(chan));
1775 req->opt1 = cpu_to_be64(CONN_POLICY_V(CPL_CONN_POLICY_ASK) |
1776 SYN_RSS_ENABLE_F | SYN_RSS_QUEUE_V(queue));
1777 ret = t4_mgmt_tx(adap, skb);
1778 return net_xmit_eval(ret);
1780 EXPORT_SYMBOL(cxgb4_create_server);
1782 /* cxgb4_create_server6 - create an IPv6 server
1784 * @stid: the server TID
1785 * @sip: local IPv6 address to bind server to
1786 * @sport: the server's TCP port
1787 * @queue: queue to direct messages from this server to
1789 * Create an IPv6 server for the given port and address.
1790 * Returns <0 on error and one of the %NET_XMIT_* values on success.
1792 int cxgb4_create_server6(const struct net_device *dev, unsigned int stid,
1793 const struct in6_addr *sip, __be16 sport,
1797 struct sk_buff *skb;
1798 struct adapter *adap;
1799 struct cpl_pass_open_req6 *req;
1802 skb = alloc_skb(sizeof(*req), GFP_KERNEL);
1806 adap = netdev2adap(dev);
1807 req = (struct cpl_pass_open_req6 *)__skb_put(skb, sizeof(*req));
1809 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_PASS_OPEN_REQ6, stid));
1810 req->local_port = sport;
1811 req->peer_port = htons(0);
1812 req->local_ip_hi = *(__be64 *)(sip->s6_addr);
1813 req->local_ip_lo = *(__be64 *)(sip->s6_addr + 8);
1814 req->peer_ip_hi = cpu_to_be64(0);
1815 req->peer_ip_lo = cpu_to_be64(0);
1816 chan = rxq_to_chan(&adap->sge, queue);
1817 req->opt0 = cpu_to_be64(TX_CHAN_V(chan));
1818 req->opt1 = cpu_to_be64(CONN_POLICY_V(CPL_CONN_POLICY_ASK) |
1819 SYN_RSS_ENABLE_F | SYN_RSS_QUEUE_V(queue));
1820 ret = t4_mgmt_tx(adap, skb);
1821 return net_xmit_eval(ret);
1823 EXPORT_SYMBOL(cxgb4_create_server6);
1825 int cxgb4_remove_server(const struct net_device *dev, unsigned int stid,
1826 unsigned int queue, bool ipv6)
1828 struct sk_buff *skb;
1829 struct adapter *adap;
1830 struct cpl_close_listsvr_req *req;
1833 adap = netdev2adap(dev);
1835 skb = alloc_skb(sizeof(*req), GFP_KERNEL);
1839 req = (struct cpl_close_listsvr_req *)__skb_put(skb, sizeof(*req));
1841 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_CLOSE_LISTSRV_REQ, stid));
1842 req->reply_ctrl = htons(NO_REPLY_V(0) | (ipv6 ? LISTSVR_IPV6_V(1) :
1843 LISTSVR_IPV6_V(0)) | QUEUENO_V(queue));
1844 ret = t4_mgmt_tx(adap, skb);
1845 return net_xmit_eval(ret);
1847 EXPORT_SYMBOL(cxgb4_remove_server);
1850 * cxgb4_best_mtu - find the entry in the MTU table closest to an MTU
1851 * @mtus: the HW MTU table
1852 * @mtu: the target MTU
1853 * @idx: index of selected entry in the MTU table
1855 * Returns the index and the value in the HW MTU table that is closest to
1856 * but does not exceed @mtu, unless @mtu is smaller than any value in the
1857 * table, in which case that smallest available value is selected.
1859 unsigned int cxgb4_best_mtu(const unsigned short *mtus, unsigned short mtu,
1864 while (i < NMTUS - 1 && mtus[i + 1] <= mtu)
1870 EXPORT_SYMBOL(cxgb4_best_mtu);
1873 * cxgb4_best_aligned_mtu - find best MTU, [hopefully] data size aligned
1874 * @mtus: the HW MTU table
1875 * @header_size: Header Size
1876 * @data_size_max: maximum Data Segment Size
1877 * @data_size_align: desired Data Segment Size Alignment (2^N)
1878 * @mtu_idxp: HW MTU Table Index return value pointer (possibly NULL)
1880 * Similar to cxgb4_best_mtu() but instead of searching the Hardware
1881 * MTU Table based solely on a Maximum MTU parameter, we break that
1882 * parameter up into a Header Size and Maximum Data Segment Size, and
1883 * provide a desired Data Segment Size Alignment. If we find an MTU in
1884 * the Hardware MTU Table which will result in a Data Segment Size with
1885 * the requested alignment _and_ that MTU isn't "too far" from the
1886 * closest MTU, then we'll return that rather than the closest MTU.
1888 unsigned int cxgb4_best_aligned_mtu(const unsigned short *mtus,
1889 unsigned short header_size,
1890 unsigned short data_size_max,
1891 unsigned short data_size_align,
1892 unsigned int *mtu_idxp)
1894 unsigned short max_mtu = header_size + data_size_max;
1895 unsigned short data_size_align_mask = data_size_align - 1;
1896 int mtu_idx, aligned_mtu_idx;
1898 /* Scan the MTU Table till we find an MTU which is larger than our
1899 * Maximum MTU or we reach the end of the table. Along the way,
1900 * record the last MTU found, if any, which will result in a Data
1901 * Segment Length matching the requested alignment.
1903 for (mtu_idx = 0, aligned_mtu_idx = -1; mtu_idx < NMTUS; mtu_idx++) {
1904 unsigned short data_size = mtus[mtu_idx] - header_size;
1906 /* If this MTU minus the Header Size would result in a
1907 * Data Segment Size of the desired alignment, remember it.
1909 if ((data_size & data_size_align_mask) == 0)
1910 aligned_mtu_idx = mtu_idx;
1912 /* If we're not at the end of the Hardware MTU Table and the
1913 * next element is larger than our Maximum MTU, drop out of
1916 if (mtu_idx+1 < NMTUS && mtus[mtu_idx+1] > max_mtu)
1920 /* If we fell out of the loop because we ran to the end of the table,
1921 * then we just have to use the last [largest] entry.
1923 if (mtu_idx == NMTUS)
1926 /* If we found an MTU which resulted in the requested Data Segment
1927 * Length alignment and that's "not far" from the largest MTU which is
1928 * less than or equal to the maximum MTU, then use that.
1930 if (aligned_mtu_idx >= 0 &&
1931 mtu_idx - aligned_mtu_idx <= 1)
1932 mtu_idx = aligned_mtu_idx;
1934 /* If the caller has passed in an MTU Index pointer, pass the
1935 * MTU Index back. Return the MTU value.
1938 *mtu_idxp = mtu_idx;
1939 return mtus[mtu_idx];
1941 EXPORT_SYMBOL(cxgb4_best_aligned_mtu);
1944 * cxgb4_tp_smt_idx - Get the Source Mac Table index for this VI
1946 * @viid: VI id of the given port
1948 * Return the SMT index for this VI.
1950 unsigned int cxgb4_tp_smt_idx(enum chip_type chip, unsigned int viid)
1952 /* In T4/T5, SMT contains 256 SMAC entries organized in
1953 * 128 rows of 2 entries each.
1954 * In T6, SMT contains 256 SMAC entries in 256 rows.
1955 * TODO: The below code needs to be updated when we add support
1958 if (CHELSIO_CHIP_VERSION(chip) <= CHELSIO_T5)
1959 return ((viid & 0x7f) << 1);
1961 return (viid & 0x7f);
1963 EXPORT_SYMBOL(cxgb4_tp_smt_idx);
1966 * cxgb4_port_chan - get the HW channel of a port
1967 * @dev: the net device for the port
1969 * Return the HW Tx channel of the given port.
1971 unsigned int cxgb4_port_chan(const struct net_device *dev)
1973 return netdev2pinfo(dev)->tx_chan;
1975 EXPORT_SYMBOL(cxgb4_port_chan);
1977 unsigned int cxgb4_dbfifo_count(const struct net_device *dev, int lpfifo)
1979 struct adapter *adap = netdev2adap(dev);
1980 u32 v1, v2, lp_count, hp_count;
1982 v1 = t4_read_reg(adap, SGE_DBFIFO_STATUS_A);
1983 v2 = t4_read_reg(adap, SGE_DBFIFO_STATUS2_A);
1984 if (is_t4(adap->params.chip)) {
1985 lp_count = LP_COUNT_G(v1);
1986 hp_count = HP_COUNT_G(v1);
1988 lp_count = LP_COUNT_T5_G(v1);
1989 hp_count = HP_COUNT_T5_G(v2);
1991 return lpfifo ? lp_count : hp_count;
1993 EXPORT_SYMBOL(cxgb4_dbfifo_count);
1996 * cxgb4_port_viid - get the VI id of a port
1997 * @dev: the net device for the port
1999 * Return the VI id of the given port.
2001 unsigned int cxgb4_port_viid(const struct net_device *dev)
2003 return netdev2pinfo(dev)->viid;
2005 EXPORT_SYMBOL(cxgb4_port_viid);
2008 * cxgb4_port_idx - get the index of a port
2009 * @dev: the net device for the port
2011 * Return the index of the given port.
2013 unsigned int cxgb4_port_idx(const struct net_device *dev)
2015 return netdev2pinfo(dev)->port_id;
2017 EXPORT_SYMBOL(cxgb4_port_idx);
2019 void cxgb4_get_tcp_stats(struct pci_dev *pdev, struct tp_tcp_stats *v4,
2020 struct tp_tcp_stats *v6)
2022 struct adapter *adap = pci_get_drvdata(pdev);
2024 spin_lock(&adap->stats_lock);
2025 t4_tp_get_tcp_stats(adap, v4, v6);
2026 spin_unlock(&adap->stats_lock);
2028 EXPORT_SYMBOL(cxgb4_get_tcp_stats);
2030 void cxgb4_iscsi_init(struct net_device *dev, unsigned int tag_mask,
2031 const unsigned int *pgsz_order)
2033 struct adapter *adap = netdev2adap(dev);
2035 t4_write_reg(adap, ULP_RX_ISCSI_TAGMASK_A, tag_mask);
2036 t4_write_reg(adap, ULP_RX_ISCSI_PSZ_A, HPZ0_V(pgsz_order[0]) |
2037 HPZ1_V(pgsz_order[1]) | HPZ2_V(pgsz_order[2]) |
2038 HPZ3_V(pgsz_order[3]));
2040 EXPORT_SYMBOL(cxgb4_iscsi_init);
2042 int cxgb4_flush_eq_cache(struct net_device *dev)
2044 struct adapter *adap = netdev2adap(dev);
2046 return t4_sge_ctxt_flush(adap, adap->mbox);
2048 EXPORT_SYMBOL(cxgb4_flush_eq_cache);
2050 static int read_eq_indices(struct adapter *adap, u16 qid, u16 *pidx, u16 *cidx)
2052 u32 addr = t4_read_reg(adap, SGE_DBQ_CTXT_BADDR_A) + 24 * qid + 8;
2056 spin_lock(&adap->win0_lock);
2057 ret = t4_memory_rw(adap, 0, MEM_EDC0, addr,
2058 sizeof(indices), (__be32 *)&indices,
2060 spin_unlock(&adap->win0_lock);
2062 *cidx = (be64_to_cpu(indices) >> 25) & 0xffff;
2063 *pidx = (be64_to_cpu(indices) >> 9) & 0xffff;
2068 int cxgb4_sync_txq_pidx(struct net_device *dev, u16 qid, u16 pidx,
2071 struct adapter *adap = netdev2adap(dev);
2072 u16 hw_pidx, hw_cidx;
2075 ret = read_eq_indices(adap, qid, &hw_pidx, &hw_cidx);
2079 if (pidx != hw_pidx) {
2083 if (pidx >= hw_pidx)
2084 delta = pidx - hw_pidx;
2086 delta = size - hw_pidx + pidx;
2088 if (is_t4(adap->params.chip))
2089 val = PIDX_V(delta);
2091 val = PIDX_T5_V(delta);
2093 t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL_A),
2099 EXPORT_SYMBOL(cxgb4_sync_txq_pidx);
2101 int cxgb4_read_tpte(struct net_device *dev, u32 stag, __be32 *tpte)
2103 struct adapter *adap;
2104 u32 offset, memtype, memaddr;
2105 u32 edc0_size, edc1_size, mc0_size, mc1_size, size;
2106 u32 edc0_end, edc1_end, mc0_end, mc1_end;
2109 adap = netdev2adap(dev);
2111 offset = ((stag >> 8) * 32) + adap->vres.stag.start;
2113 /* Figure out where the offset lands in the Memory Type/Address scheme.
2114 * This code assumes that the memory is laid out starting at offset 0
2115 * with no breaks as: EDC0, EDC1, MC0, MC1. All cards have both EDC0
2116 * and EDC1. Some cards will have neither MC0 nor MC1, most cards have
2117 * MC0, and some have both MC0 and MC1.
2119 size = t4_read_reg(adap, MA_EDRAM0_BAR_A);
2120 edc0_size = EDRAM0_SIZE_G(size) << 20;
2121 size = t4_read_reg(adap, MA_EDRAM1_BAR_A);
2122 edc1_size = EDRAM1_SIZE_G(size) << 20;
2123 size = t4_read_reg(adap, MA_EXT_MEMORY0_BAR_A);
2124 mc0_size = EXT_MEM0_SIZE_G(size) << 20;
2126 edc0_end = edc0_size;
2127 edc1_end = edc0_end + edc1_size;
2128 mc0_end = edc1_end + mc0_size;
2130 if (offset < edc0_end) {
2133 } else if (offset < edc1_end) {
2135 memaddr = offset - edc0_end;
2137 if (offset < mc0_end) {
2139 memaddr = offset - edc1_end;
2140 } else if (is_t5(adap->params.chip)) {
2141 size = t4_read_reg(adap, MA_EXT_MEMORY1_BAR_A);
2142 mc1_size = EXT_MEM1_SIZE_G(size) << 20;
2143 mc1_end = mc0_end + mc1_size;
2144 if (offset < mc1_end) {
2146 memaddr = offset - mc0_end;
2148 /* offset beyond the end of any memory */
2152 /* T4/T6 only has a single memory channel */
2157 spin_lock(&adap->win0_lock);
2158 ret = t4_memory_rw(adap, 0, memtype, memaddr, 32, tpte, T4_MEMORY_READ);
2159 spin_unlock(&adap->win0_lock);
2163 dev_err(adap->pdev_dev, "stag %#x, offset %#x out of range\n",
2167 EXPORT_SYMBOL(cxgb4_read_tpte);
2169 u64 cxgb4_read_sge_timestamp(struct net_device *dev)
2172 struct adapter *adap;
2174 adap = netdev2adap(dev);
2175 lo = t4_read_reg(adap, SGE_TIMESTAMP_LO_A);
2176 hi = TSVAL_G(t4_read_reg(adap, SGE_TIMESTAMP_HI_A));
2178 return ((u64)hi << 32) | (u64)lo;
2180 EXPORT_SYMBOL(cxgb4_read_sge_timestamp);
2182 int cxgb4_bar2_sge_qregs(struct net_device *dev,
2184 enum cxgb4_bar2_qtype qtype,
2187 unsigned int *pbar2_qid)
2189 return t4_bar2_sge_qregs(netdev2adap(dev),
2191 (qtype == CXGB4_BAR2_QTYPE_EGRESS
2192 ? T4_BAR2_QTYPE_EGRESS
2193 : T4_BAR2_QTYPE_INGRESS),
2198 EXPORT_SYMBOL(cxgb4_bar2_sge_qregs);
2200 static struct pci_driver cxgb4_driver;
2202 static void check_neigh_update(struct neighbour *neigh)
2204 const struct device *parent;
2205 const struct net_device *netdev = neigh->dev;
2207 if (netdev->priv_flags & IFF_802_1Q_VLAN)
2208 netdev = vlan_dev_real_dev(netdev);
2209 parent = netdev->dev.parent;
2210 if (parent && parent->driver == &cxgb4_driver.driver)
2211 t4_l2t_update(dev_get_drvdata(parent), neigh);
2214 static int netevent_cb(struct notifier_block *nb, unsigned long event,
2218 case NETEVENT_NEIGH_UPDATE:
2219 check_neigh_update(data);
2221 case NETEVENT_REDIRECT:
2228 static bool netevent_registered;
2229 static struct notifier_block cxgb4_netevent_nb = {
2230 .notifier_call = netevent_cb
2233 static void drain_db_fifo(struct adapter *adap, int usecs)
2235 u32 v1, v2, lp_count, hp_count;
2238 v1 = t4_read_reg(adap, SGE_DBFIFO_STATUS_A);
2239 v2 = t4_read_reg(adap, SGE_DBFIFO_STATUS2_A);
2240 if (is_t4(adap->params.chip)) {
2241 lp_count = LP_COUNT_G(v1);
2242 hp_count = HP_COUNT_G(v1);
2244 lp_count = LP_COUNT_T5_G(v1);
2245 hp_count = HP_COUNT_T5_G(v2);
2248 if (lp_count == 0 && hp_count == 0)
2250 set_current_state(TASK_UNINTERRUPTIBLE);
2251 schedule_timeout(usecs_to_jiffies(usecs));
2255 static void disable_txq_db(struct sge_txq *q)
2257 unsigned long flags;
2259 spin_lock_irqsave(&q->db_lock, flags);
2261 spin_unlock_irqrestore(&q->db_lock, flags);
2264 static void enable_txq_db(struct adapter *adap, struct sge_txq *q)
2266 spin_lock_irq(&q->db_lock);
2267 if (q->db_pidx_inc) {
2268 /* Make sure that all writes to the TX descriptors
2269 * are committed before we tell HW about them.
2272 t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL_A),
2273 QID_V(q->cntxt_id) | PIDX_V(q->db_pidx_inc));
2277 spin_unlock_irq(&q->db_lock);
2280 static void disable_dbs(struct adapter *adap)
2284 for_each_ethrxq(&adap->sge, i)
2285 disable_txq_db(&adap->sge.ethtxq[i].q);
2286 for_each_ofldrxq(&adap->sge, i)
2287 disable_txq_db(&adap->sge.ofldtxq[i].q);
2288 for_each_port(adap, i)
2289 disable_txq_db(&adap->sge.ctrlq[i].q);
2292 static void enable_dbs(struct adapter *adap)
2296 for_each_ethrxq(&adap->sge, i)
2297 enable_txq_db(adap, &adap->sge.ethtxq[i].q);
2298 for_each_ofldrxq(&adap->sge, i)
2299 enable_txq_db(adap, &adap->sge.ofldtxq[i].q);
2300 for_each_port(adap, i)
2301 enable_txq_db(adap, &adap->sge.ctrlq[i].q);
2304 static void notify_rdma_uld(struct adapter *adap, enum cxgb4_control cmd)
2306 if (adap->uld_handle[CXGB4_ULD_RDMA])
2307 ulds[CXGB4_ULD_RDMA].control(adap->uld_handle[CXGB4_ULD_RDMA],
2311 static void process_db_full(struct work_struct *work)
2313 struct adapter *adap;
2315 adap = container_of(work, struct adapter, db_full_task);
2317 drain_db_fifo(adap, dbfifo_drain_delay);
2319 notify_rdma_uld(adap, CXGB4_CONTROL_DB_EMPTY);
2320 if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5)
2321 t4_set_reg_field(adap, SGE_INT_ENABLE3_A,
2322 DBFIFO_HP_INT_F | DBFIFO_LP_INT_F,
2323 DBFIFO_HP_INT_F | DBFIFO_LP_INT_F);
2325 t4_set_reg_field(adap, SGE_INT_ENABLE3_A,
2326 DBFIFO_LP_INT_F, DBFIFO_LP_INT_F);
2329 static void sync_txq_pidx(struct adapter *adap, struct sge_txq *q)
2331 u16 hw_pidx, hw_cidx;
2334 spin_lock_irq(&q->db_lock);
2335 ret = read_eq_indices(adap, (u16)q->cntxt_id, &hw_pidx, &hw_cidx);
2338 if (q->db_pidx != hw_pidx) {
2342 if (q->db_pidx >= hw_pidx)
2343 delta = q->db_pidx - hw_pidx;
2345 delta = q->size - hw_pidx + q->db_pidx;
2347 if (is_t4(adap->params.chip))
2348 val = PIDX_V(delta);
2350 val = PIDX_T5_V(delta);
2352 t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL_A),
2353 QID_V(q->cntxt_id) | val);
2358 spin_unlock_irq(&q->db_lock);
2360 CH_WARN(adap, "DB drop recovery failed.\n");
2362 static void recover_all_queues(struct adapter *adap)
2366 for_each_ethrxq(&adap->sge, i)
2367 sync_txq_pidx(adap, &adap->sge.ethtxq[i].q);
2368 for_each_ofldrxq(&adap->sge, i)
2369 sync_txq_pidx(adap, &adap->sge.ofldtxq[i].q);
2370 for_each_port(adap, i)
2371 sync_txq_pidx(adap, &adap->sge.ctrlq[i].q);
2374 static void process_db_drop(struct work_struct *work)
2376 struct adapter *adap;
2378 adap = container_of(work, struct adapter, db_drop_task);
2380 if (is_t4(adap->params.chip)) {
2381 drain_db_fifo(adap, dbfifo_drain_delay);
2382 notify_rdma_uld(adap, CXGB4_CONTROL_DB_DROP);
2383 drain_db_fifo(adap, dbfifo_drain_delay);
2384 recover_all_queues(adap);
2385 drain_db_fifo(adap, dbfifo_drain_delay);
2387 notify_rdma_uld(adap, CXGB4_CONTROL_DB_EMPTY);
2388 } else if (is_t5(adap->params.chip)) {
2389 u32 dropped_db = t4_read_reg(adap, 0x010ac);
2390 u16 qid = (dropped_db >> 15) & 0x1ffff;
2391 u16 pidx_inc = dropped_db & 0x1fff;
2393 unsigned int bar2_qid;
2396 ret = t4_bar2_sge_qregs(adap, qid, T4_BAR2_QTYPE_EGRESS,
2397 0, &bar2_qoffset, &bar2_qid);
2399 dev_err(adap->pdev_dev, "doorbell drop recovery: "
2400 "qid=%d, pidx_inc=%d\n", qid, pidx_inc);
2402 writel(PIDX_T5_V(pidx_inc) | QID_V(bar2_qid),
2403 adap->bar2 + bar2_qoffset + SGE_UDB_KDOORBELL);
2405 /* Re-enable BAR2 WC */
2406 t4_set_reg_field(adap, 0x10b0, 1<<15, 1<<15);
2409 if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5)
2410 t4_set_reg_field(adap, SGE_DOORBELL_CONTROL_A, DROPPED_DB_F, 0);
2413 void t4_db_full(struct adapter *adap)
2415 if (is_t4(adap->params.chip)) {
2417 notify_rdma_uld(adap, CXGB4_CONTROL_DB_FULL);
2418 t4_set_reg_field(adap, SGE_INT_ENABLE3_A,
2419 DBFIFO_HP_INT_F | DBFIFO_LP_INT_F, 0);
2420 queue_work(adap->workq, &adap->db_full_task);
2424 void t4_db_dropped(struct adapter *adap)
2426 if (is_t4(adap->params.chip)) {
2428 notify_rdma_uld(adap, CXGB4_CONTROL_DB_FULL);
2430 queue_work(adap->workq, &adap->db_drop_task);
2433 static void uld_attach(struct adapter *adap, unsigned int uld)
2436 struct cxgb4_lld_info lli;
2439 lli.pdev = adap->pdev;
2441 lli.l2t = adap->l2t;
2442 lli.tids = &adap->tids;
2443 lli.ports = adap->port;
2444 lli.vr = &adap->vres;
2445 lli.mtus = adap->params.mtus;
2446 if (uld == CXGB4_ULD_RDMA) {
2447 lli.rxq_ids = adap->sge.rdma_rxq;
2448 lli.ciq_ids = adap->sge.rdma_ciq;
2449 lli.nrxq = adap->sge.rdmaqs;
2450 lli.nciq = adap->sge.rdmaciqs;
2451 } else if (uld == CXGB4_ULD_ISCSI) {
2452 lli.rxq_ids = adap->sge.ofld_rxq;
2453 lli.nrxq = adap->sge.ofldqsets;
2455 lli.ntxq = adap->sge.ofldqsets;
2456 lli.nchan = adap->params.nports;
2457 lli.nports = adap->params.nports;
2458 lli.wr_cred = adap->params.ofldq_wr_cred;
2459 lli.adapter_type = adap->params.chip;
2460 lli.iscsi_iolen = MAXRXDATA_G(t4_read_reg(adap, TP_PARA_REG2_A));
2461 lli.cclk_ps = 1000000000 / adap->params.vpd.cclk;
2462 lli.udb_density = 1 << adap->params.sge.eq_qpp;
2463 lli.ucq_density = 1 << adap->params.sge.iq_qpp;
2464 lli.filt_mode = adap->params.tp.vlan_pri_map;
2465 /* MODQ_REQ_MAP sets queues 0-3 to chan 0-3 */
2466 for (i = 0; i < NCHAN; i++)
2468 lli.gts_reg = adap->regs + MYPF_REG(SGE_PF_GTS_A);
2469 lli.db_reg = adap->regs + MYPF_REG(SGE_PF_KDOORBELL_A);
2470 lli.fw_vers = adap->params.fw_vers;
2471 lli.dbfifo_int_thresh = dbfifo_int_thresh;
2472 lli.sge_ingpadboundary = adap->sge.fl_align;
2473 lli.sge_egrstatuspagesize = adap->sge.stat_len;
2474 lli.sge_pktshift = adap->sge.pktshift;
2475 lli.enable_fw_ofld_conn = adap->flags & FW_OFLD_CONN;
2476 lli.max_ordird_qp = adap->params.max_ordird_qp;
2477 lli.max_ird_adapter = adap->params.max_ird_adapter;
2478 lli.ulptx_memwrite_dsgl = adap->params.ulptx_memwrite_dsgl;
2479 lli.nodeid = dev_to_node(adap->pdev_dev);
2481 handle = ulds[uld].add(&lli);
2482 if (IS_ERR(handle)) {
2483 dev_warn(adap->pdev_dev,
2484 "could not attach to the %s driver, error %ld\n",
2485 uld_str[uld], PTR_ERR(handle));
2489 adap->uld_handle[uld] = handle;
2491 if (!netevent_registered) {
2492 register_netevent_notifier(&cxgb4_netevent_nb);
2493 netevent_registered = true;
2496 if (adap->flags & FULL_INIT_DONE)
2497 ulds[uld].state_change(handle, CXGB4_STATE_UP);
2500 static void attach_ulds(struct adapter *adap)
2504 spin_lock(&adap_rcu_lock);
2505 list_add_tail_rcu(&adap->rcu_node, &adap_rcu_list);
2506 spin_unlock(&adap_rcu_lock);
2508 mutex_lock(&uld_mutex);
2509 list_add_tail(&adap->list_node, &adapter_list);
2510 for (i = 0; i < CXGB4_ULD_MAX; i++)
2512 uld_attach(adap, i);
2513 mutex_unlock(&uld_mutex);
2516 static void detach_ulds(struct adapter *adap)
2520 mutex_lock(&uld_mutex);
2521 list_del(&adap->list_node);
2522 for (i = 0; i < CXGB4_ULD_MAX; i++)
2523 if (adap->uld_handle[i]) {
2524 ulds[i].state_change(adap->uld_handle[i],
2525 CXGB4_STATE_DETACH);
2526 adap->uld_handle[i] = NULL;
2528 if (netevent_registered && list_empty(&adapter_list)) {
2529 unregister_netevent_notifier(&cxgb4_netevent_nb);
2530 netevent_registered = false;
2532 mutex_unlock(&uld_mutex);
2534 spin_lock(&adap_rcu_lock);
2535 list_del_rcu(&adap->rcu_node);
2536 spin_unlock(&adap_rcu_lock);
2539 static void notify_ulds(struct adapter *adap, enum cxgb4_state new_state)
2543 mutex_lock(&uld_mutex);
2544 for (i = 0; i < CXGB4_ULD_MAX; i++)
2545 if (adap->uld_handle[i])
2546 ulds[i].state_change(adap->uld_handle[i], new_state);
2547 mutex_unlock(&uld_mutex);
2551 * cxgb4_register_uld - register an upper-layer driver
2552 * @type: the ULD type
2553 * @p: the ULD methods
2555 * Registers an upper-layer driver with this driver and notifies the ULD
2556 * about any presently available devices that support its type. Returns
2557 * %-EBUSY if a ULD of the same type is already registered.
2559 int cxgb4_register_uld(enum cxgb4_uld type, const struct cxgb4_uld_info *p)
2562 struct adapter *adap;
2564 if (type >= CXGB4_ULD_MAX)
2566 mutex_lock(&uld_mutex);
2567 if (ulds[type].add) {
2572 list_for_each_entry(adap, &adapter_list, list_node)
2573 uld_attach(adap, type);
2574 out: mutex_unlock(&uld_mutex);
2577 EXPORT_SYMBOL(cxgb4_register_uld);
2580 * cxgb4_unregister_uld - unregister an upper-layer driver
2581 * @type: the ULD type
2583 * Unregisters an existing upper-layer driver.
2585 int cxgb4_unregister_uld(enum cxgb4_uld type)
2587 struct adapter *adap;
2589 if (type >= CXGB4_ULD_MAX)
2591 mutex_lock(&uld_mutex);
2592 list_for_each_entry(adap, &adapter_list, list_node)
2593 adap->uld_handle[type] = NULL;
2594 ulds[type].add = NULL;
2595 mutex_unlock(&uld_mutex);
2598 EXPORT_SYMBOL(cxgb4_unregister_uld);
2600 #if IS_ENABLED(CONFIG_IPV6)
2601 static int cxgb4_inet6addr_handler(struct notifier_block *this,
2602 unsigned long event, void *data)
2604 struct inet6_ifaddr *ifa = data;
2605 struct net_device *event_dev = ifa->idev->dev;
2606 const struct device *parent = NULL;
2607 #if IS_ENABLED(CONFIG_BONDING)
2608 struct adapter *adap;
2610 if (event_dev->priv_flags & IFF_802_1Q_VLAN)
2611 event_dev = vlan_dev_real_dev(event_dev);
2612 #if IS_ENABLED(CONFIG_BONDING)
2613 if (event_dev->flags & IFF_MASTER) {
2614 list_for_each_entry(adap, &adapter_list, list_node) {
2617 cxgb4_clip_get(adap->port[0],
2618 (const u32 *)ifa, 1);
2621 cxgb4_clip_release(adap->port[0],
2622 (const u32 *)ifa, 1);
2633 parent = event_dev->dev.parent;
2635 if (parent && parent->driver == &cxgb4_driver.driver) {
2638 cxgb4_clip_get(event_dev, (const u32 *)ifa, 1);
2641 cxgb4_clip_release(event_dev, (const u32 *)ifa, 1);
2650 static bool inet6addr_registered;
2651 static struct notifier_block cxgb4_inet6addr_notifier = {
2652 .notifier_call = cxgb4_inet6addr_handler
2655 static void update_clip(const struct adapter *adap)
2658 struct net_device *dev;
2663 for (i = 0; i < MAX_NPORTS; i++) {
2664 dev = adap->port[i];
2668 ret = cxgb4_update_root_dev_clip(dev);
2675 #endif /* IS_ENABLED(CONFIG_IPV6) */
2678 * cxgb_up - enable the adapter
2679 * @adap: adapter being enabled
2681 * Called when the first port is enabled, this function performs the
2682 * actions necessary to make an adapter operational, such as completing
2683 * the initialization of HW modules, and enabling interrupts.
2685 * Must be called with the rtnl lock held.
2687 static int cxgb_up(struct adapter *adap)
2691 err = setup_sge_queues(adap);
2694 err = setup_rss(adap);
2698 if (adap->flags & USING_MSIX) {
2699 name_msix_vecs(adap);
2700 err = request_irq(adap->msix_info[0].vec, t4_nondata_intr, 0,
2701 adap->msix_info[0].desc, adap);
2705 err = request_msix_queue_irqs(adap);
2707 free_irq(adap->msix_info[0].vec, adap);
2711 err = request_irq(adap->pdev->irq, t4_intr_handler(adap),
2712 (adap->flags & USING_MSI) ? 0 : IRQF_SHARED,
2713 adap->port[0]->name, adap);
2719 t4_intr_enable(adap);
2720 adap->flags |= FULL_INIT_DONE;
2721 notify_ulds(adap, CXGB4_STATE_UP);
2722 #if IS_ENABLED(CONFIG_IPV6)
2728 dev_err(adap->pdev_dev, "request_irq failed, err %d\n", err);
2730 t4_free_sge_resources(adap);
2734 static void cxgb_down(struct adapter *adapter)
2736 cancel_work_sync(&adapter->tid_release_task);
2737 cancel_work_sync(&adapter->db_full_task);
2738 cancel_work_sync(&adapter->db_drop_task);
2739 adapter->tid_release_task_busy = false;
2740 adapter->tid_release_head = NULL;
2742 t4_sge_stop(adapter);
2743 t4_free_sge_resources(adapter);
2744 adapter->flags &= ~FULL_INIT_DONE;
2748 * net_device operations
2750 static int cxgb_open(struct net_device *dev)
2753 struct port_info *pi = netdev_priv(dev);
2754 struct adapter *adapter = pi->adapter;
2756 netif_carrier_off(dev);
2758 if (!(adapter->flags & FULL_INIT_DONE)) {
2759 err = cxgb_up(adapter);
2764 err = link_start(dev);
2766 netif_tx_start_all_queues(dev);
2770 static int cxgb_close(struct net_device *dev)
2772 struct port_info *pi = netdev_priv(dev);
2773 struct adapter *adapter = pi->adapter;
2775 netif_tx_stop_all_queues(dev);
2776 netif_carrier_off(dev);
2777 return t4_enable_vi(adapter, adapter->pf, pi->viid, false, false);
2780 /* Return an error number if the indicated filter isn't writable ...
2782 static int writable_filter(struct filter_entry *f)
2792 /* Delete the filter at the specified index (if valid). The checks for all
2793 * the common problems with doing this like the filter being locked, currently
2794 * pending in another operation, etc.
2796 static int delete_filter(struct adapter *adapter, unsigned int fidx)
2798 struct filter_entry *f;
2801 if (fidx >= adapter->tids.nftids + adapter->tids.nsftids)
2804 f = &adapter->tids.ftid_tab[fidx];
2805 ret = writable_filter(f);
2809 return del_filter_wr(adapter, fidx);
2814 int cxgb4_create_server_filter(const struct net_device *dev, unsigned int stid,
2815 __be32 sip, __be16 sport, __be16 vlan,
2816 unsigned int queue, unsigned char port, unsigned char mask)
2819 struct filter_entry *f;
2820 struct adapter *adap;
2824 adap = netdev2adap(dev);
2826 /* Adjust stid to correct filter index */
2827 stid -= adap->tids.sftid_base;
2828 stid += adap->tids.nftids;
2830 /* Check to make sure the filter requested is writable ...
2832 f = &adap->tids.ftid_tab[stid];
2833 ret = writable_filter(f);
2837 /* Clear out any old resources being used by the filter before
2838 * we start constructing the new filter.
2841 clear_filter(adap, f);
2843 /* Clear out filter specifications */
2844 memset(&f->fs, 0, sizeof(struct ch_filter_specification));
2845 f->fs.val.lport = cpu_to_be16(sport);
2846 f->fs.mask.lport = ~0;
2848 if ((val[0] | val[1] | val[2] | val[3]) != 0) {
2849 for (i = 0; i < 4; i++) {
2850 f->fs.val.lip[i] = val[i];
2851 f->fs.mask.lip[i] = ~0;
2853 if (adap->params.tp.vlan_pri_map & PORT_F) {
2854 f->fs.val.iport = port;
2855 f->fs.mask.iport = mask;
2859 if (adap->params.tp.vlan_pri_map & PROTOCOL_F) {
2860 f->fs.val.proto = IPPROTO_TCP;
2861 f->fs.mask.proto = ~0;
2866 /* Mark filter as locked */
2870 ret = set_filter_wr(adap, stid);
2872 clear_filter(adap, f);
2878 EXPORT_SYMBOL(cxgb4_create_server_filter);
2880 int cxgb4_remove_server_filter(const struct net_device *dev, unsigned int stid,
2881 unsigned int queue, bool ipv6)
2884 struct filter_entry *f;
2885 struct adapter *adap;
2887 adap = netdev2adap(dev);
2889 /* Adjust stid to correct filter index */
2890 stid -= adap->tids.sftid_base;
2891 stid += adap->tids.nftids;
2893 f = &adap->tids.ftid_tab[stid];
2894 /* Unlock the filter */
2897 ret = delete_filter(adap, stid);
2903 EXPORT_SYMBOL(cxgb4_remove_server_filter);
2905 static struct rtnl_link_stats64 *cxgb_get_stats(struct net_device *dev,
2906 struct rtnl_link_stats64 *ns)
2908 struct port_stats stats;
2909 struct port_info *p = netdev_priv(dev);
2910 struct adapter *adapter = p->adapter;
2912 /* Block retrieving statistics during EEH error
2913 * recovery. Otherwise, the recovery might fail
2914 * and the PCI device will be removed permanently
2916 spin_lock(&adapter->stats_lock);
2917 if (!netif_device_present(dev)) {
2918 spin_unlock(&adapter->stats_lock);
2921 t4_get_port_stats_offset(adapter, p->tx_chan, &stats,
2923 spin_unlock(&adapter->stats_lock);
2925 ns->tx_bytes = stats.tx_octets;
2926 ns->tx_packets = stats.tx_frames;
2927 ns->rx_bytes = stats.rx_octets;
2928 ns->rx_packets = stats.rx_frames;
2929 ns->multicast = stats.rx_mcast_frames;
2931 /* detailed rx_errors */
2932 ns->rx_length_errors = stats.rx_jabber + stats.rx_too_long +
2934 ns->rx_over_errors = 0;
2935 ns->rx_crc_errors = stats.rx_fcs_err;
2936 ns->rx_frame_errors = stats.rx_symbol_err;
2937 ns->rx_fifo_errors = stats.rx_ovflow0 + stats.rx_ovflow1 +
2938 stats.rx_ovflow2 + stats.rx_ovflow3 +
2939 stats.rx_trunc0 + stats.rx_trunc1 +
2940 stats.rx_trunc2 + stats.rx_trunc3;
2941 ns->rx_missed_errors = 0;
2943 /* detailed tx_errors */
2944 ns->tx_aborted_errors = 0;
2945 ns->tx_carrier_errors = 0;
2946 ns->tx_fifo_errors = 0;
2947 ns->tx_heartbeat_errors = 0;
2948 ns->tx_window_errors = 0;
2950 ns->tx_errors = stats.tx_error_frames;
2951 ns->rx_errors = stats.rx_symbol_err + stats.rx_fcs_err +
2952 ns->rx_length_errors + stats.rx_len_err + ns->rx_fifo_errors;
2956 static int cxgb_ioctl(struct net_device *dev, struct ifreq *req, int cmd)
2959 int ret = 0, prtad, devad;
2960 struct port_info *pi = netdev_priv(dev);
2961 struct mii_ioctl_data *data = (struct mii_ioctl_data *)&req->ifr_data;
2965 if (pi->mdio_addr < 0)
2967 data->phy_id = pi->mdio_addr;
2971 if (mdio_phy_id_is_c45(data->phy_id)) {
2972 prtad = mdio_phy_id_prtad(data->phy_id);
2973 devad = mdio_phy_id_devad(data->phy_id);
2974 } else if (data->phy_id < 32) {
2975 prtad = data->phy_id;
2977 data->reg_num &= 0x1f;
2981 mbox = pi->adapter->pf;
2982 if (cmd == SIOCGMIIREG)
2983 ret = t4_mdio_rd(pi->adapter, mbox, prtad, devad,
2984 data->reg_num, &data->val_out);
2986 ret = t4_mdio_wr(pi->adapter, mbox, prtad, devad,
2987 data->reg_num, data->val_in);
2990 return copy_to_user(req->ifr_data, &pi->tstamp_config,
2991 sizeof(pi->tstamp_config)) ?
2994 if (copy_from_user(&pi->tstamp_config, req->ifr_data,
2995 sizeof(pi->tstamp_config)))
2998 switch (pi->tstamp_config.rx_filter) {
2999 case HWTSTAMP_FILTER_NONE:
3000 pi->rxtstamp = false;
3002 case HWTSTAMP_FILTER_ALL:
3003 pi->rxtstamp = true;
3006 pi->tstamp_config.rx_filter = HWTSTAMP_FILTER_NONE;
3010 return copy_to_user(req->ifr_data, &pi->tstamp_config,
3011 sizeof(pi->tstamp_config)) ?
3019 static void cxgb_set_rxmode(struct net_device *dev)
3021 /* unfortunately we can't return errors to the stack */
3022 set_rxmode(dev, -1, false);
3025 static int cxgb_change_mtu(struct net_device *dev, int new_mtu)
3028 struct port_info *pi = netdev_priv(dev);
3030 if (new_mtu < 81 || new_mtu > MAX_MTU) /* accommodate SACK */
3032 ret = t4_set_rxmode(pi->adapter, pi->adapter->pf, pi->viid, new_mtu, -1,
3039 static int cxgb_set_mac_addr(struct net_device *dev, void *p)
3042 struct sockaddr *addr = p;
3043 struct port_info *pi = netdev_priv(dev);
3045 if (!is_valid_ether_addr(addr->sa_data))
3046 return -EADDRNOTAVAIL;
3048 ret = t4_change_mac(pi->adapter, pi->adapter->pf, pi->viid,
3049 pi->xact_addr_filt, addr->sa_data, true, true);
3053 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
3054 pi->xact_addr_filt = ret;
3058 #ifdef CONFIG_NET_POLL_CONTROLLER
3059 static void cxgb_netpoll(struct net_device *dev)
3061 struct port_info *pi = netdev_priv(dev);
3062 struct adapter *adap = pi->adapter;
3064 if (adap->flags & USING_MSIX) {
3066 struct sge_eth_rxq *rx = &adap->sge.ethrxq[pi->first_qset];
3068 for (i = pi->nqsets; i; i--, rx++)
3069 t4_sge_intr_msix(0, &rx->rspq);
3071 t4_intr_handler(adap)(0, adap);
3075 static const struct net_device_ops cxgb4_netdev_ops = {
3076 .ndo_open = cxgb_open,
3077 .ndo_stop = cxgb_close,
3078 .ndo_start_xmit = t4_eth_xmit,
3079 .ndo_select_queue = cxgb_select_queue,
3080 .ndo_get_stats64 = cxgb_get_stats,
3081 .ndo_set_rx_mode = cxgb_set_rxmode,
3082 .ndo_set_mac_address = cxgb_set_mac_addr,
3083 .ndo_set_features = cxgb_set_features,
3084 .ndo_validate_addr = eth_validate_addr,
3085 .ndo_do_ioctl = cxgb_ioctl,
3086 .ndo_change_mtu = cxgb_change_mtu,
3087 #ifdef CONFIG_NET_POLL_CONTROLLER
3088 .ndo_poll_controller = cxgb_netpoll,
3090 #ifdef CONFIG_CHELSIO_T4_FCOE
3091 .ndo_fcoe_enable = cxgb_fcoe_enable,
3092 .ndo_fcoe_disable = cxgb_fcoe_disable,
3093 #endif /* CONFIG_CHELSIO_T4_FCOE */
3094 #ifdef CONFIG_NET_RX_BUSY_POLL
3095 .ndo_busy_poll = cxgb_busy_poll,
3100 void t4_fatal_err(struct adapter *adap)
3102 t4_set_reg_field(adap, SGE_CONTROL_A, GLOBALENABLE_F, 0);
3103 t4_intr_disable(adap);
3104 dev_alert(adap->pdev_dev, "encountered fatal error, adapter stopped\n");
3107 static void setup_memwin(struct adapter *adap)
3109 u32 nic_win_base = t4_get_util_window(adap);
3111 t4_setup_memwin(adap, nic_win_base, MEMWIN_NIC);
3114 static void setup_memwin_rdma(struct adapter *adap)
3116 if (adap->vres.ocq.size) {
3120 start = t4_read_pcie_cfg4(adap, PCI_BASE_ADDRESS_2);
3121 start &= PCI_BASE_ADDRESS_MEM_MASK;
3122 start += OCQ_WIN_OFFSET(adap->pdev, &adap->vres);
3123 sz_kb = roundup_pow_of_two(adap->vres.ocq.size) >> 10;
3125 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A, 3),
3126 start | BIR_V(1) | WINDOW_V(ilog2(sz_kb)));
3128 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, 3),
3129 adap->vres.ocq.start);
3131 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, 3));
3135 static int adap_init1(struct adapter *adap, struct fw_caps_config_cmd *c)
3140 /* get device capabilities */
3141 memset(c, 0, sizeof(*c));
3142 c->op_to_write = htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) |
3143 FW_CMD_REQUEST_F | FW_CMD_READ_F);
3144 c->cfvalid_to_len16 = htonl(FW_LEN16(*c));
3145 ret = t4_wr_mbox(adap, adap->mbox, c, sizeof(*c), c);
3149 /* select capabilities we'll be using */
3150 if (c->niccaps & htons(FW_CAPS_CONFIG_NIC_VM)) {
3152 c->niccaps ^= htons(FW_CAPS_CONFIG_NIC_VM);
3154 c->niccaps = htons(FW_CAPS_CONFIG_NIC_VM);
3155 } else if (vf_acls) {
3156 dev_err(adap->pdev_dev, "virtualization ACLs not supported");
3159 c->op_to_write = htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) |
3160 FW_CMD_REQUEST_F | FW_CMD_WRITE_F);
3161 ret = t4_wr_mbox(adap, adap->mbox, c, sizeof(*c), NULL);
3165 ret = t4_config_glbl_rss(adap, adap->pf,
3166 FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL,
3167 FW_RSS_GLB_CONFIG_CMD_TNLMAPEN_F |
3168 FW_RSS_GLB_CONFIG_CMD_TNLALLLKP_F);
3172 ret = t4_cfg_pfvf(adap, adap->mbox, adap->pf, 0, adap->sge.egr_sz, 64,
3173 MAX_INGQ, 0, 0, 4, 0xf, 0xf, 16, FW_CMD_CAP_PF,
3180 /* tweak some settings */
3181 t4_write_reg(adap, TP_SHIFT_CNT_A, 0x64f8849);
3182 t4_write_reg(adap, ULP_RX_TDDP_PSZ_A, HPZ0_V(PAGE_SHIFT - 12));
3183 t4_write_reg(adap, TP_PIO_ADDR_A, TP_INGRESS_CONFIG_A);
3184 v = t4_read_reg(adap, TP_PIO_DATA_A);
3185 t4_write_reg(adap, TP_PIO_DATA_A, v & ~CSUM_HAS_PSEUDO_HDR_F);
3187 /* first 4 Tx modulation queues point to consecutive Tx channels */
3188 adap->params.tp.tx_modq_map = 0xE4;
3189 t4_write_reg(adap, TP_TX_MOD_QUEUE_REQ_MAP_A,
3190 TX_MOD_QUEUE_REQ_MAP_V(adap->params.tp.tx_modq_map));
3192 /* associate each Tx modulation queue with consecutive Tx channels */
3194 t4_write_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A,
3195 &v, 1, TP_TX_SCHED_HDR_A);
3196 t4_write_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A,
3197 &v, 1, TP_TX_SCHED_FIFO_A);
3198 t4_write_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A,
3199 &v, 1, TP_TX_SCHED_PCMD_A);
3201 #define T4_TX_MODQ_10G_WEIGHT_DEFAULT 16 /* in KB units */
3202 if (is_offload(adap)) {
3203 t4_write_reg(adap, TP_TX_MOD_QUEUE_WEIGHT0_A,
3204 TX_MODQ_WEIGHT0_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
3205 TX_MODQ_WEIGHT1_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
3206 TX_MODQ_WEIGHT2_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
3207 TX_MODQ_WEIGHT3_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT));
3208 t4_write_reg(adap, TP_TX_MOD_CHANNEL_WEIGHT_A,
3209 TX_MODQ_WEIGHT0_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
3210 TX_MODQ_WEIGHT1_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
3211 TX_MODQ_WEIGHT2_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
3212 TX_MODQ_WEIGHT3_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT));
3215 /* get basic stuff going */
3216 return t4_early_init(adap, adap->pf);
3220 * Max # of ATIDs. The absolute HW max is 16K but we keep it lower.
3222 #define MAX_ATIDS 8192U
3225 * Phase 0 of initialization: contact FW, obtain config, perform basic init.
3227 * If the firmware we're dealing with has Configuration File support, then
3228 * we use that to perform all configuration
3232 * Tweak configuration based on module parameters, etc. Most of these have
3233 * defaults assigned to them by Firmware Configuration Files (if we're using
3234 * them) but need to be explicitly set if we're using hard-coded
3235 * initialization. But even in the case of using Firmware Configuration
3236 * Files, we'd like to expose the ability to change these via module
3237 * parameters so these are essentially common tweaks/settings for
3238 * Configuration Files and hard-coded initialization ...
3240 static int adap_init0_tweaks(struct adapter *adapter)
3243 * Fix up various Host-Dependent Parameters like Page Size, Cache
3244 * Line Size, etc. The firmware default is for a 4KB Page Size and
3245 * 64B Cache Line Size ...
3247 t4_fixup_host_params(adapter, PAGE_SIZE, L1_CACHE_BYTES);
3250 * Process module parameters which affect early initialization.
3252 if (rx_dma_offset != 2 && rx_dma_offset != 0) {
3253 dev_err(&adapter->pdev->dev,
3254 "Ignoring illegal rx_dma_offset=%d, using 2\n",
3258 t4_set_reg_field(adapter, SGE_CONTROL_A,
3259 PKTSHIFT_V(PKTSHIFT_M),
3260 PKTSHIFT_V(rx_dma_offset));
3263 * Don't include the "IP Pseudo Header" in CPL_RX_PKT checksums: Linux
3264 * adds the pseudo header itself.
3266 t4_tp_wr_bits_indirect(adapter, TP_INGRESS_CONFIG_A,
3267 CSUM_HAS_PSEUDO_HDR_F, 0);
3272 /* 10Gb/s-BT PHY Support. chip-external 10Gb/s-BT PHYs are complex chips
3273 * unto themselves and they contain their own firmware to perform their
3276 static int phy_aq1202_version(const u8 *phy_fw_data,
3281 /* At offset 0x8 you're looking for the primary image's
3282 * starting offset which is 3 Bytes wide
3284 * At offset 0xa of the primary image, you look for the offset
3285 * of the DRAM segment which is 3 Bytes wide.
3287 * The FW version is at offset 0x27e of the DRAM and is 2 Bytes
3290 #define be16(__p) (((__p)[0] << 8) | (__p)[1])
3291 #define le16(__p) ((__p)[0] | ((__p)[1] << 8))
3292 #define le24(__p) (le16(__p) | ((__p)[2] << 16))
3294 offset = le24(phy_fw_data + 0x8) << 12;
3295 offset = le24(phy_fw_data + offset + 0xa);
3296 return be16(phy_fw_data + offset + 0x27e);
3303 static struct info_10gbt_phy_fw {
3304 unsigned int phy_fw_id; /* PCI Device ID */
3305 char *phy_fw_file; /* /lib/firmware/ PHY Firmware file */
3306 int (*phy_fw_version)(const u8 *phy_fw_data, size_t phy_fw_size);
3307 int phy_flash; /* Has FLASH for PHY Firmware */
3308 } phy_info_array[] = {
3310 PHY_AQ1202_DEVICEID,
3311 PHY_AQ1202_FIRMWARE,
3316 PHY_BCM84834_DEVICEID,
3317 PHY_BCM84834_FIRMWARE,
3324 static struct info_10gbt_phy_fw *find_phy_info(int devid)
3328 for (i = 0; i < ARRAY_SIZE(phy_info_array); i++) {
3329 if (phy_info_array[i].phy_fw_id == devid)
3330 return &phy_info_array[i];
3335 /* Handle updating of chip-external 10Gb/s-BT PHY firmware. This needs to
3336 * happen after the FW_RESET_CMD but before the FW_INITIALIZE_CMD. On error
3337 * we return a negative error number. If we transfer new firmware we return 1
3338 * (from t4_load_phy_fw()). If we don't do anything we return 0.
3340 static int adap_init0_phy(struct adapter *adap)
3342 const struct firmware *phyf;
3344 struct info_10gbt_phy_fw *phy_info;
3346 /* Use the device ID to determine which PHY file to flash.
3348 phy_info = find_phy_info(adap->pdev->device);
3350 dev_warn(adap->pdev_dev,
3351 "No PHY Firmware file found for this PHY\n");
3355 /* If we have a T4 PHY firmware file under /lib/firmware/cxgb4/, then
3356 * use that. The adapter firmware provides us with a memory buffer
3357 * where we can load a PHY firmware file from the host if we want to
3358 * override the PHY firmware File in flash.
3360 ret = request_firmware_direct(&phyf, phy_info->phy_fw_file,
3363 /* For adapters without FLASH attached to PHY for their
3364 * firmware, it's obviously a fatal error if we can't get the
3365 * firmware to the adapter. For adapters with PHY firmware
3366 * FLASH storage, it's worth a warning if we can't find the
3367 * PHY Firmware but we'll neuter the error ...
3369 dev_err(adap->pdev_dev, "unable to find PHY Firmware image "
3370 "/lib/firmware/%s, error %d\n",
3371 phy_info->phy_fw_file, -ret);
3372 if (phy_info->phy_flash) {
3373 int cur_phy_fw_ver = 0;
3375 t4_phy_fw_ver(adap, &cur_phy_fw_ver);
3376 dev_warn(adap->pdev_dev, "continuing with, on-adapter "
3377 "FLASH copy, version %#x\n", cur_phy_fw_ver);
3384 /* Load PHY Firmware onto adapter.
3386 ret = t4_load_phy_fw(adap, MEMWIN_NIC, &adap->win0_lock,
3387 phy_info->phy_fw_version,
3388 (u8 *)phyf->data, phyf->size);
3390 dev_err(adap->pdev_dev, "PHY Firmware transfer error %d\n",
3393 int new_phy_fw_ver = 0;
3395 if (phy_info->phy_fw_version)
3396 new_phy_fw_ver = phy_info->phy_fw_version(phyf->data,
3398 dev_info(adap->pdev_dev, "Successfully transferred PHY "
3399 "Firmware /lib/firmware/%s, version %#x\n",
3400 phy_info->phy_fw_file, new_phy_fw_ver);
3403 release_firmware(phyf);
3409 * Attempt to initialize the adapter via a Firmware Configuration File.
3411 static int adap_init0_config(struct adapter *adapter, int reset)
3413 struct fw_caps_config_cmd caps_cmd;
3414 const struct firmware *cf;
3415 unsigned long mtype = 0, maddr = 0;
3416 u32 finiver, finicsum, cfcsum;
3418 int config_issued = 0;
3419 char *fw_config_file, fw_config_file_path[256];
3420 char *config_name = NULL;
3423 * Reset device if necessary.
3426 ret = t4_fw_reset(adapter, adapter->mbox,
3427 PIORSTMODE_F | PIORST_F);
3432 /* If this is a 10Gb/s-BT adapter make sure the chip-external
3433 * 10Gb/s-BT PHYs have up-to-date firmware. Note that this step needs
3434 * to be performed after any global adapter RESET above since some
3435 * PHYs only have local RAM copies of the PHY firmware.
3437 if (is_10gbt_device(adapter->pdev->device)) {
3438 ret = adap_init0_phy(adapter);
3443 * If we have a T4 configuration file under /lib/firmware/cxgb4/,
3444 * then use that. Otherwise, use the configuration file stored
3445 * in the adapter flash ...
3447 switch (CHELSIO_CHIP_VERSION(adapter->params.chip)) {
3449 fw_config_file = FW4_CFNAME;
3452 fw_config_file = FW5_CFNAME;
3455 fw_config_file = FW6_CFNAME;
3458 dev_err(adapter->pdev_dev, "Device %d is not supported\n",
3459 adapter->pdev->device);
3464 ret = request_firmware(&cf, fw_config_file, adapter->pdev_dev);
3466 config_name = "On FLASH";
3467 mtype = FW_MEMTYPE_CF_FLASH;
3468 maddr = t4_flash_cfg_addr(adapter);
3470 u32 params[7], val[7];
3472 sprintf(fw_config_file_path,
3473 "/lib/firmware/%s", fw_config_file);
3474 config_name = fw_config_file_path;
3476 if (cf->size >= FLASH_CFG_MAX_SIZE)
3479 params[0] = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3480 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_CF));
3481 ret = t4_query_params(adapter, adapter->mbox,
3482 adapter->pf, 0, 1, params, val);
3485 * For t4_memory_rw() below addresses and
3486 * sizes have to be in terms of multiples of 4
3487 * bytes. So, if the Configuration File isn't
3488 * a multiple of 4 bytes in length we'll have
3489 * to write that out separately since we can't
3490 * guarantee that the bytes following the
3491 * residual byte in the buffer returned by
3492 * request_firmware() are zeroed out ...
3494 size_t resid = cf->size & 0x3;
3495 size_t size = cf->size & ~0x3;
3496 __be32 *data = (__be32 *)cf->data;
3498 mtype = FW_PARAMS_PARAM_Y_G(val[0]);
3499 maddr = FW_PARAMS_PARAM_Z_G(val[0]) << 16;
3501 spin_lock(&adapter->win0_lock);
3502 ret = t4_memory_rw(adapter, 0, mtype, maddr,
3503 size, data, T4_MEMORY_WRITE);
3504 if (ret == 0 && resid != 0) {
3511 last.word = data[size >> 2];
3512 for (i = resid; i < 4; i++)
3514 ret = t4_memory_rw(adapter, 0, mtype,
3519 spin_unlock(&adapter->win0_lock);
3523 release_firmware(cf);
3529 * Issue a Capability Configuration command to the firmware to get it
3530 * to parse the Configuration File. We don't use t4_fw_config_file()
3531 * because we want the ability to modify various features after we've
3532 * processed the configuration file ...
3534 memset(&caps_cmd, 0, sizeof(caps_cmd));
3535 caps_cmd.op_to_write =
3536 htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) |
3539 caps_cmd.cfvalid_to_len16 =
3540 htonl(FW_CAPS_CONFIG_CMD_CFVALID_F |
3541 FW_CAPS_CONFIG_CMD_MEMTYPE_CF_V(mtype) |
3542 FW_CAPS_CONFIG_CMD_MEMADDR64K_CF_V(maddr >> 16) |
3543 FW_LEN16(caps_cmd));
3544 ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd, sizeof(caps_cmd),
3547 /* If the CAPS_CONFIG failed with an ENOENT (for a Firmware
3548 * Configuration File in FLASH), our last gasp effort is to use the
3549 * Firmware Configuration File which is embedded in the firmware. A
3550 * very few early versions of the firmware didn't have one embedded
3551 * but we can ignore those.
3553 if (ret == -ENOENT) {
3554 memset(&caps_cmd, 0, sizeof(caps_cmd));
3555 caps_cmd.op_to_write =
3556 htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) |
3559 caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd));
3560 ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd,
3561 sizeof(caps_cmd), &caps_cmd);
3562 config_name = "Firmware Default";
3569 finiver = ntohl(caps_cmd.finiver);
3570 finicsum = ntohl(caps_cmd.finicsum);
3571 cfcsum = ntohl(caps_cmd.cfcsum);
3572 if (finicsum != cfcsum)
3573 dev_warn(adapter->pdev_dev, "Configuration File checksum "\
3574 "mismatch: [fini] csum=%#x, computed csum=%#x\n",
3578 * And now tell the firmware to use the configuration we just loaded.
3580 caps_cmd.op_to_write =
3581 htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) |
3584 caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd));
3585 ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd, sizeof(caps_cmd),
3591 * Tweak configuration based on system architecture, module
3594 ret = adap_init0_tweaks(adapter);
3599 * And finally tell the firmware to initialize itself using the
3600 * parameters from the Configuration File.
3602 ret = t4_fw_initialize(adapter, adapter->mbox);
3606 /* Emit Firmware Configuration File information and return
3609 dev_info(adapter->pdev_dev, "Successfully configured using Firmware "\
3610 "Configuration File \"%s\", version %#x, computed checksum %#x\n",
3611 config_name, finiver, cfcsum);
3615 * Something bad happened. Return the error ... (If the "error"
3616 * is that there's no Configuration File on the adapter we don't
3617 * want to issue a warning since this is fairly common.)
3620 if (config_issued && ret != -ENOENT)
3621 dev_warn(adapter->pdev_dev, "\"%s\" configuration file error %d\n",
3626 static struct fw_info fw_info_array[] = {
3629 .fs_name = FW4_CFNAME,
3630 .fw_mod_name = FW4_FNAME,
3632 .chip = FW_HDR_CHIP_T4,
3633 .fw_ver = __cpu_to_be32(FW_VERSION(T4)),
3634 .intfver_nic = FW_INTFVER(T4, NIC),
3635 .intfver_vnic = FW_INTFVER(T4, VNIC),
3636 .intfver_ri = FW_INTFVER(T4, RI),
3637 .intfver_iscsi = FW_INTFVER(T4, ISCSI),
3638 .intfver_fcoe = FW_INTFVER(T4, FCOE),
3642 .fs_name = FW5_CFNAME,
3643 .fw_mod_name = FW5_FNAME,
3645 .chip = FW_HDR_CHIP_T5,
3646 .fw_ver = __cpu_to_be32(FW_VERSION(T5)),
3647 .intfver_nic = FW_INTFVER(T5, NIC),
3648 .intfver_vnic = FW_INTFVER(T5, VNIC),
3649 .intfver_ri = FW_INTFVER(T5, RI),
3650 .intfver_iscsi = FW_INTFVER(T5, ISCSI),
3651 .intfver_fcoe = FW_INTFVER(T5, FCOE),
3655 .fs_name = FW6_CFNAME,
3656 .fw_mod_name = FW6_FNAME,
3658 .chip = FW_HDR_CHIP_T6,
3659 .fw_ver = __cpu_to_be32(FW_VERSION(T6)),
3660 .intfver_nic = FW_INTFVER(T6, NIC),
3661 .intfver_vnic = FW_INTFVER(T6, VNIC),
3662 .intfver_ofld = FW_INTFVER(T6, OFLD),
3663 .intfver_ri = FW_INTFVER(T6, RI),
3664 .intfver_iscsipdu = FW_INTFVER(T6, ISCSIPDU),
3665 .intfver_iscsi = FW_INTFVER(T6, ISCSI),
3666 .intfver_fcoepdu = FW_INTFVER(T6, FCOEPDU),
3667 .intfver_fcoe = FW_INTFVER(T6, FCOE),
3673 static struct fw_info *find_fw_info(int chip)
3677 for (i = 0; i < ARRAY_SIZE(fw_info_array); i++) {
3678 if (fw_info_array[i].chip == chip)
3679 return &fw_info_array[i];
3685 * Phase 0 of initialization: contact FW, obtain config, perform basic init.
3687 static int adap_init0(struct adapter *adap)
3691 enum dev_state state;
3692 u32 params[7], val[7];
3693 struct fw_caps_config_cmd caps_cmd;
3696 /* Grab Firmware Device Log parameters as early as possible so we have
3697 * access to it for debugging, etc.
3699 ret = t4_init_devlog_params(adap);
3703 /* Contact FW, advertising Master capability */
3704 ret = t4_fw_hello(adap, adap->mbox, adap->mbox, MASTER_MAY, &state);
3706 dev_err(adap->pdev_dev, "could not connect to FW, error %d\n",
3710 if (ret == adap->mbox)
3711 adap->flags |= MASTER_PF;
3714 * If we're the Master PF Driver and the device is uninitialized,
3715 * then let's consider upgrading the firmware ... (We always want
3716 * to check the firmware version number in order to A. get it for
3717 * later reporting and B. to warn if the currently loaded firmware
3718 * is excessively mismatched relative to the driver.)
3720 t4_get_fw_version(adap, &adap->params.fw_vers);
3721 t4_get_tp_version(adap, &adap->params.tp_vers);
3722 ret = t4_check_fw_version(adap);
3723 /* If firmware is too old (not supported by driver) force an update. */
3725 state = DEV_STATE_UNINIT;
3726 if ((adap->flags & MASTER_PF) && state != DEV_STATE_INIT) {
3727 struct fw_info *fw_info;
3728 struct fw_hdr *card_fw;
3729 const struct firmware *fw;
3730 const u8 *fw_data = NULL;
3731 unsigned int fw_size = 0;
3733 /* This is the firmware whose headers the driver was compiled
3736 fw_info = find_fw_info(CHELSIO_CHIP_VERSION(adap->params.chip));
3737 if (fw_info == NULL) {
3738 dev_err(adap->pdev_dev,
3739 "unable to get firmware info for chip %d.\n",
3740 CHELSIO_CHIP_VERSION(adap->params.chip));
3744 /* allocate memory to read the header of the firmware on the
3747 card_fw = t4_alloc_mem(sizeof(*card_fw));
3749 /* Get FW from from /lib/firmware/ */
3750 ret = request_firmware(&fw, fw_info->fw_mod_name,
3753 dev_err(adap->pdev_dev,
3754 "unable to load firmware image %s, error %d\n",
3755 fw_info->fw_mod_name, ret);
3761 /* upgrade FW logic */
3762 ret = t4_prep_fw(adap, fw_info, fw_data, fw_size, card_fw,
3766 release_firmware(fw);
3767 t4_free_mem(card_fw);
3774 * Grab VPD parameters. This should be done after we establish a
3775 * connection to the firmware since some of the VPD parameters
3776 * (notably the Core Clock frequency) are retrieved via requests to
3777 * the firmware. On the other hand, we need these fairly early on
3778 * so we do this right after getting ahold of the firmware.
3780 ret = t4_get_vpd_params(adap, &adap->params.vpd);
3785 * Find out what ports are available to us. Note that we need to do
3786 * this before calling adap_init0_no_config() since it needs nports
3790 FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3791 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_PORTVEC);
3792 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1, &v, &port_vec);
3796 adap->params.nports = hweight32(port_vec);
3797 adap->params.portvec = port_vec;
3799 /* If the firmware is initialized already, emit a simply note to that
3800 * effect. Otherwise, it's time to try initializing the adapter.
3802 if (state == DEV_STATE_INIT) {
3803 dev_info(adap->pdev_dev, "Coming up as %s: "\
3804 "Adapter already initialized\n",
3805 adap->flags & MASTER_PF ? "MASTER" : "SLAVE");
3807 dev_info(adap->pdev_dev, "Coming up as MASTER: "\
3808 "Initializing adapter\n");
3810 /* Find out whether we're dealing with a version of the
3811 * firmware which has configuration file support.
3813 params[0] = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3814 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_CF));
3815 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1,
3818 /* If the firmware doesn't support Configuration Files,
3822 dev_err(adap->pdev_dev, "firmware doesn't support "
3823 "Firmware Configuration Files\n");
3827 /* The firmware provides us with a memory buffer where we can
3828 * load a Configuration File from the host if we want to
3829 * override the Configuration File in flash.
3831 ret = adap_init0_config(adap, reset);
3832 if (ret == -ENOENT) {
3833 dev_err(adap->pdev_dev, "no Configuration File "
3834 "present on adapter.\n");
3838 dev_err(adap->pdev_dev, "could not initialize "
3839 "adapter, error %d\n", -ret);
3844 /* Give the SGE code a chance to pull in anything that it needs ...
3845 * Note that this must be called after we retrieve our VPD parameters
3846 * in order to know how to convert core ticks to seconds, etc.
3848 ret = t4_sge_init(adap);
3852 if (is_bypass_device(adap->pdev->device))
3853 adap->params.bypass = 1;
3856 * Grab some of our basic fundamental operating parameters.
3858 #define FW_PARAM_DEV(param) \
3859 (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) | \
3860 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_##param))
3862 #define FW_PARAM_PFVF(param) \
3863 FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_PFVF) | \
3864 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_PFVF_##param)| \
3865 FW_PARAMS_PARAM_Y_V(0) | \
3866 FW_PARAMS_PARAM_Z_V(0)
3868 params[0] = FW_PARAM_PFVF(EQ_START);
3869 params[1] = FW_PARAM_PFVF(L2T_START);
3870 params[2] = FW_PARAM_PFVF(L2T_END);
3871 params[3] = FW_PARAM_PFVF(FILTER_START);
3872 params[4] = FW_PARAM_PFVF(FILTER_END);
3873 params[5] = FW_PARAM_PFVF(IQFLINT_START);
3874 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 6, params, val);
3877 adap->sge.egr_start = val[0];
3878 adap->l2t_start = val[1];
3879 adap->l2t_end = val[2];
3880 adap->tids.ftid_base = val[3];
3881 adap->tids.nftids = val[4] - val[3] + 1;
3882 adap->sge.ingr_start = val[5];
3884 /* qids (ingress/egress) returned from firmware can be anywhere
3885 * in the range from EQ(IQFLINT)_START to EQ(IQFLINT)_END.
3886 * Hence driver needs to allocate memory for this range to
3887 * store the queue info. Get the highest IQFLINT/EQ index returned
3888 * in FW_EQ_*_CMD.alloc command.
3890 params[0] = FW_PARAM_PFVF(EQ_END);
3891 params[1] = FW_PARAM_PFVF(IQFLINT_END);
3892 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, params, val);
3895 adap->sge.egr_sz = val[0] - adap->sge.egr_start + 1;
3896 adap->sge.ingr_sz = val[1] - adap->sge.ingr_start + 1;
3898 adap->sge.egr_map = kcalloc(adap->sge.egr_sz,
3899 sizeof(*adap->sge.egr_map), GFP_KERNEL);
3900 if (!adap->sge.egr_map) {
3905 adap->sge.ingr_map = kcalloc(adap->sge.ingr_sz,
3906 sizeof(*adap->sge.ingr_map), GFP_KERNEL);
3907 if (!adap->sge.ingr_map) {
3912 /* Allocate the memory for the vaious egress queue bitmaps
3913 * ie starving_fl, txq_maperr and blocked_fl.
3915 adap->sge.starving_fl = kcalloc(BITS_TO_LONGS(adap->sge.egr_sz),
3916 sizeof(long), GFP_KERNEL);
3917 if (!adap->sge.starving_fl) {
3922 adap->sge.txq_maperr = kcalloc(BITS_TO_LONGS(adap->sge.egr_sz),
3923 sizeof(long), GFP_KERNEL);
3924 if (!adap->sge.txq_maperr) {
3929 #ifdef CONFIG_DEBUG_FS
3930 adap->sge.blocked_fl = kcalloc(BITS_TO_LONGS(adap->sge.egr_sz),
3931 sizeof(long), GFP_KERNEL);
3932 if (!adap->sge.blocked_fl) {
3938 params[0] = FW_PARAM_PFVF(CLIP_START);
3939 params[1] = FW_PARAM_PFVF(CLIP_END);
3940 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, params, val);
3943 adap->clipt_start = val[0];
3944 adap->clipt_end = val[1];
3946 /* query params related to active filter region */
3947 params[0] = FW_PARAM_PFVF(ACTIVE_FILTER_START);
3948 params[1] = FW_PARAM_PFVF(ACTIVE_FILTER_END);
3949 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, params, val);
3950 /* If Active filter size is set we enable establishing
3951 * offload connection through firmware work request
3953 if ((val[0] != val[1]) && (ret >= 0)) {
3954 adap->flags |= FW_OFLD_CONN;
3955 adap->tids.aftid_base = val[0];
3956 adap->tids.aftid_end = val[1];
3959 /* If we're running on newer firmware, let it know that we're
3960 * prepared to deal with encapsulated CPL messages. Older
3961 * firmware won't understand this and we'll just get
3962 * unencapsulated messages ...
3964 params[0] = FW_PARAM_PFVF(CPLFW4MSG_ENCAP);
3966 (void)t4_set_params(adap, adap->mbox, adap->pf, 0, 1, params, val);
3969 * Find out whether we're allowed to use the T5+ ULPTX MEMWRITE DSGL
3970 * capability. Earlier versions of the firmware didn't have the
3971 * ULPTX_MEMWRITE_DSGL so we'll interpret a query failure as no
3972 * permission to use ULPTX MEMWRITE DSGL.
3974 if (is_t4(adap->params.chip)) {
3975 adap->params.ulptx_memwrite_dsgl = false;
3977 params[0] = FW_PARAM_DEV(ULPTX_MEMWRITE_DSGL);
3978 ret = t4_query_params(adap, adap->mbox, adap->pf, 0,
3980 adap->params.ulptx_memwrite_dsgl = (ret == 0 && val[0] != 0);
3984 * Get device capabilities so we can determine what resources we need
3987 memset(&caps_cmd, 0, sizeof(caps_cmd));
3988 caps_cmd.op_to_write = htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) |
3989 FW_CMD_REQUEST_F | FW_CMD_READ_F);
3990 caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd));
3991 ret = t4_wr_mbox(adap, adap->mbox, &caps_cmd, sizeof(caps_cmd),
3996 if (caps_cmd.ofldcaps) {
3997 /* query offload-related parameters */
3998 params[0] = FW_PARAM_DEV(NTID);
3999 params[1] = FW_PARAM_PFVF(SERVER_START);
4000 params[2] = FW_PARAM_PFVF(SERVER_END);
4001 params[3] = FW_PARAM_PFVF(TDDP_START);
4002 params[4] = FW_PARAM_PFVF(TDDP_END);
4003 params[5] = FW_PARAM_DEV(FLOWC_BUFFIFO_SZ);
4004 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 6,
4008 adap->tids.ntids = val[0];
4009 adap->tids.natids = min(adap->tids.ntids / 2, MAX_ATIDS);
4010 adap->tids.stid_base = val[1];
4011 adap->tids.nstids = val[2] - val[1] + 1;
4013 * Setup server filter region. Divide the available filter
4014 * region into two parts. Regular filters get 1/3rd and server
4015 * filters get 2/3rd part. This is only enabled if workarond
4017 * 1. For regular filters.
4018 * 2. Server filter: This are special filters which are used
4019 * to redirect SYN packets to offload queue.
4021 if (adap->flags & FW_OFLD_CONN && !is_bypass(adap)) {
4022 adap->tids.sftid_base = adap->tids.ftid_base +
4023 DIV_ROUND_UP(adap->tids.nftids, 3);
4024 adap->tids.nsftids = adap->tids.nftids -
4025 DIV_ROUND_UP(adap->tids.nftids, 3);
4026 adap->tids.nftids = adap->tids.sftid_base -
4027 adap->tids.ftid_base;
4029 adap->vres.ddp.start = val[3];
4030 adap->vres.ddp.size = val[4] - val[3] + 1;
4031 adap->params.ofldq_wr_cred = val[5];
4033 adap->params.offload = 1;
4035 if (caps_cmd.rdmacaps) {
4036 params[0] = FW_PARAM_PFVF(STAG_START);
4037 params[1] = FW_PARAM_PFVF(STAG_END);
4038 params[2] = FW_PARAM_PFVF(RQ_START);
4039 params[3] = FW_PARAM_PFVF(RQ_END);
4040 params[4] = FW_PARAM_PFVF(PBL_START);
4041 params[5] = FW_PARAM_PFVF(PBL_END);
4042 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 6,
4046 adap->vres.stag.start = val[0];
4047 adap->vres.stag.size = val[1] - val[0] + 1;
4048 adap->vres.rq.start = val[2];
4049 adap->vres.rq.size = val[3] - val[2] + 1;
4050 adap->vres.pbl.start = val[4];
4051 adap->vres.pbl.size = val[5] - val[4] + 1;
4053 params[0] = FW_PARAM_PFVF(SQRQ_START);
4054 params[1] = FW_PARAM_PFVF(SQRQ_END);
4055 params[2] = FW_PARAM_PFVF(CQ_START);
4056 params[3] = FW_PARAM_PFVF(CQ_END);
4057 params[4] = FW_PARAM_PFVF(OCQ_START);
4058 params[5] = FW_PARAM_PFVF(OCQ_END);
4059 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 6, params,
4063 adap->vres.qp.start = val[0];
4064 adap->vres.qp.size = val[1] - val[0] + 1;
4065 adap->vres.cq.start = val[2];
4066 adap->vres.cq.size = val[3] - val[2] + 1;
4067 adap->vres.ocq.start = val[4];
4068 adap->vres.ocq.size = val[5] - val[4] + 1;
4070 params[0] = FW_PARAM_DEV(MAXORDIRD_QP);
4071 params[1] = FW_PARAM_DEV(MAXIRD_ADAPTER);
4072 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, params,
4075 adap->params.max_ordird_qp = 8;
4076 adap->params.max_ird_adapter = 32 * adap->tids.ntids;
4079 adap->params.max_ordird_qp = val[0];
4080 adap->params.max_ird_adapter = val[1];
4082 dev_info(adap->pdev_dev,
4083 "max_ordird_qp %d max_ird_adapter %d\n",
4084 adap->params.max_ordird_qp,
4085 adap->params.max_ird_adapter);
4087 if (caps_cmd.iscsicaps) {
4088 params[0] = FW_PARAM_PFVF(ISCSI_START);
4089 params[1] = FW_PARAM_PFVF(ISCSI_END);
4090 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2,
4094 adap->vres.iscsi.start = val[0];
4095 adap->vres.iscsi.size = val[1] - val[0] + 1;
4097 #undef FW_PARAM_PFVF
4100 /* The MTU/MSS Table is initialized by now, so load their values. If
4101 * we're initializing the adapter, then we'll make any modifications
4102 * we want to the MTU/MSS Table and also initialize the congestion
4105 t4_read_mtu_tbl(adap, adap->params.mtus, NULL);
4106 if (state != DEV_STATE_INIT) {
4109 /* The default MTU Table contains values 1492 and 1500.
4110 * However, for TCP, it's better to have two values which are
4111 * a multiple of 8 +/- 4 bytes apart near this popular MTU.
4112 * This allows us to have a TCP Data Payload which is a
4113 * multiple of 8 regardless of what combination of TCP Options
4114 * are in use (always a multiple of 4 bytes) which is
4115 * important for performance reasons. For instance, if no
4116 * options are in use, then we have a 20-byte IP header and a
4117 * 20-byte TCP header. In this case, a 1500-byte MSS would
4118 * result in a TCP Data Payload of 1500 - 40 == 1460 bytes
4119 * which is not a multiple of 8. So using an MSS of 1488 in
4120 * this case results in a TCP Data Payload of 1448 bytes which
4121 * is a multiple of 8. On the other hand, if 12-byte TCP Time
4122 * Stamps have been negotiated, then an MTU of 1500 bytes
4123 * results in a TCP Data Payload of 1448 bytes which, as
4124 * above, is a multiple of 8 bytes ...
4126 for (i = 0; i < NMTUS; i++)
4127 if (adap->params.mtus[i] == 1492) {
4128 adap->params.mtus[i] = 1488;
4132 t4_load_mtus(adap, adap->params.mtus, adap->params.a_wnd,
4133 adap->params.b_wnd);
4135 t4_init_sge_params(adap);
4136 adap->flags |= FW_OK;
4137 t4_init_tp_params(adap);
4141 * Something bad happened. If a command timed out or failed with EIO
4142 * FW does not operate within its spec or something catastrophic
4143 * happened to HW/FW, stop issuing commands.
4146 kfree(adap->sge.egr_map);
4147 kfree(adap->sge.ingr_map);
4148 kfree(adap->sge.starving_fl);
4149 kfree(adap->sge.txq_maperr);
4150 #ifdef CONFIG_DEBUG_FS
4151 kfree(adap->sge.blocked_fl);
4153 if (ret != -ETIMEDOUT && ret != -EIO)
4154 t4_fw_bye(adap, adap->mbox);
4160 static pci_ers_result_t eeh_err_detected(struct pci_dev *pdev,
4161 pci_channel_state_t state)
4164 struct adapter *adap = pci_get_drvdata(pdev);
4170 adap->flags &= ~FW_OK;
4171 notify_ulds(adap, CXGB4_STATE_START_RECOVERY);
4172 spin_lock(&adap->stats_lock);
4173 for_each_port(adap, i) {
4174 struct net_device *dev = adap->port[i];
4176 netif_device_detach(dev);
4177 netif_carrier_off(dev);
4179 spin_unlock(&adap->stats_lock);
4180 disable_interrupts(adap);
4181 if (adap->flags & FULL_INIT_DONE)
4184 if ((adap->flags & DEV_ENABLED)) {
4185 pci_disable_device(pdev);
4186 adap->flags &= ~DEV_ENABLED;
4188 out: return state == pci_channel_io_perm_failure ?
4189 PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET;
4192 static pci_ers_result_t eeh_slot_reset(struct pci_dev *pdev)
4195 struct fw_caps_config_cmd c;
4196 struct adapter *adap = pci_get_drvdata(pdev);
4199 pci_restore_state(pdev);
4200 pci_save_state(pdev);
4201 return PCI_ERS_RESULT_RECOVERED;
4204 if (!(adap->flags & DEV_ENABLED)) {
4205 if (pci_enable_device(pdev)) {
4206 dev_err(&pdev->dev, "Cannot reenable PCI "
4207 "device after reset\n");
4208 return PCI_ERS_RESULT_DISCONNECT;
4210 adap->flags |= DEV_ENABLED;
4213 pci_set_master(pdev);
4214 pci_restore_state(pdev);
4215 pci_save_state(pdev);
4216 pci_cleanup_aer_uncorrect_error_status(pdev);
4218 if (t4_wait_dev_ready(adap->regs) < 0)
4219 return PCI_ERS_RESULT_DISCONNECT;
4220 if (t4_fw_hello(adap, adap->mbox, adap->pf, MASTER_MUST, NULL) < 0)
4221 return PCI_ERS_RESULT_DISCONNECT;
4222 adap->flags |= FW_OK;
4223 if (adap_init1(adap, &c))
4224 return PCI_ERS_RESULT_DISCONNECT;
4226 for_each_port(adap, i) {
4227 struct port_info *p = adap2pinfo(adap, i);
4229 ret = t4_alloc_vi(adap, adap->mbox, p->tx_chan, adap->pf, 0, 1,
4232 return PCI_ERS_RESULT_DISCONNECT;
4234 p->xact_addr_filt = -1;
4237 t4_load_mtus(adap, adap->params.mtus, adap->params.a_wnd,
4238 adap->params.b_wnd);
4241 return PCI_ERS_RESULT_DISCONNECT;
4242 return PCI_ERS_RESULT_RECOVERED;
4245 static void eeh_resume(struct pci_dev *pdev)
4248 struct adapter *adap = pci_get_drvdata(pdev);
4254 for_each_port(adap, i) {
4255 struct net_device *dev = adap->port[i];
4257 if (netif_running(dev)) {
4259 cxgb_set_rxmode(dev);
4261 netif_device_attach(dev);
4266 static const struct pci_error_handlers cxgb4_eeh = {
4267 .error_detected = eeh_err_detected,
4268 .slot_reset = eeh_slot_reset,
4269 .resume = eeh_resume,
4272 static inline bool is_x_10g_port(const struct link_config *lc)
4274 return (lc->supported & FW_PORT_CAP_SPEED_10G) != 0 ||
4275 (lc->supported & FW_PORT_CAP_SPEED_40G) != 0;
4278 static inline void init_rspq(struct adapter *adap, struct sge_rspq *q,
4279 unsigned int us, unsigned int cnt,
4280 unsigned int size, unsigned int iqe_size)
4283 cxgb4_set_rspq_intr_params(q, us, cnt);
4284 q->iqe_len = iqe_size;
4289 * Perform default configuration of DMA queues depending on the number and type
4290 * of ports we found and the number of available CPUs. Most settings can be
4291 * modified by the admin prior to actual use.
4293 static void cfg_queues(struct adapter *adap)
4295 struct sge *s = &adap->sge;
4296 int i, n10g = 0, qidx = 0;
4297 #ifndef CONFIG_CHELSIO_T4_DCB
4302 for_each_port(adap, i)
4303 n10g += is_x_10g_port(&adap2pinfo(adap, i)->link_cfg);
4304 #ifdef CONFIG_CHELSIO_T4_DCB
4305 /* For Data Center Bridging support we need to be able to support up
4306 * to 8 Traffic Priorities; each of which will be assigned to its
4307 * own TX Queue in order to prevent Head-Of-Line Blocking.
4309 if (adap->params.nports * 8 > MAX_ETH_QSETS) {
4310 dev_err(adap->pdev_dev, "MAX_ETH_QSETS=%d < %d!\n",
4311 MAX_ETH_QSETS, adap->params.nports * 8);
4315 for_each_port(adap, i) {
4316 struct port_info *pi = adap2pinfo(adap, i);
4318 pi->first_qset = qidx;
4322 #else /* !CONFIG_CHELSIO_T4_DCB */
4324 * We default to 1 queue per non-10G port and up to # of cores queues
4328 q10g = (MAX_ETH_QSETS - (adap->params.nports - n10g)) / n10g;
4329 if (q10g > netif_get_num_default_rss_queues())
4330 q10g = netif_get_num_default_rss_queues();
4332 for_each_port(adap, i) {
4333 struct port_info *pi = adap2pinfo(adap, i);
4335 pi->first_qset = qidx;
4336 pi->nqsets = is_x_10g_port(&pi->link_cfg) ? q10g : 1;
4339 #endif /* !CONFIG_CHELSIO_T4_DCB */
4342 s->max_ethqsets = qidx; /* MSI-X may lower it later */
4344 if (is_offload(adap)) {
4346 * For offload we use 1 queue/channel if all ports are up to 1G,
4347 * otherwise we divide all available queues amongst the channels
4348 * capped by the number of available cores.
4351 i = min_t(int, ARRAY_SIZE(s->ofldrxq),
4353 s->ofldqsets = roundup(i, adap->params.nports);
4355 s->ofldqsets = adap->params.nports;
4356 /* For RDMA one Rx queue per channel suffices */
4357 s->rdmaqs = adap->params.nports;
4358 /* Try and allow at least 1 CIQ per cpu rounding down
4359 * to the number of ports, with a minimum of 1 per port.
4360 * A 2 port card in a 6 cpu system: 6 CIQs, 3 / port.
4361 * A 4 port card in a 6 cpu system: 4 CIQs, 1 / port.
4362 * A 4 port card in a 2 cpu system: 4 CIQs, 1 / port.
4364 s->rdmaciqs = min_t(int, MAX_RDMA_CIQS, num_online_cpus());
4365 s->rdmaciqs = (s->rdmaciqs / adap->params.nports) *
4366 adap->params.nports;
4367 s->rdmaciqs = max_t(int, s->rdmaciqs, adap->params.nports);
4370 for (i = 0; i < ARRAY_SIZE(s->ethrxq); i++) {
4371 struct sge_eth_rxq *r = &s->ethrxq[i];
4373 init_rspq(adap, &r->rspq, 5, 10, 1024, 64);
4377 for (i = 0; i < ARRAY_SIZE(s->ethtxq); i++)
4378 s->ethtxq[i].q.size = 1024;
4380 for (i = 0; i < ARRAY_SIZE(s->ctrlq); i++)
4381 s->ctrlq[i].q.size = 512;
4383 for (i = 0; i < ARRAY_SIZE(s->ofldtxq); i++)
4384 s->ofldtxq[i].q.size = 1024;
4386 for (i = 0; i < ARRAY_SIZE(s->ofldrxq); i++) {
4387 struct sge_ofld_rxq *r = &s->ofldrxq[i];
4389 init_rspq(adap, &r->rspq, 5, 1, 1024, 64);
4390 r->rspq.uld = CXGB4_ULD_ISCSI;
4394 for (i = 0; i < ARRAY_SIZE(s->rdmarxq); i++) {
4395 struct sge_ofld_rxq *r = &s->rdmarxq[i];
4397 init_rspq(adap, &r->rspq, 5, 1, 511, 64);
4398 r->rspq.uld = CXGB4_ULD_RDMA;
4402 ciq_size = 64 + adap->vres.cq.size + adap->tids.nftids;
4403 if (ciq_size > SGE_MAX_IQ_SIZE) {
4404 CH_WARN(adap, "CIQ size too small for available IQs\n");
4405 ciq_size = SGE_MAX_IQ_SIZE;
4408 for (i = 0; i < ARRAY_SIZE(s->rdmaciq); i++) {
4409 struct sge_ofld_rxq *r = &s->rdmaciq[i];
4411 init_rspq(adap, &r->rspq, 5, 1, ciq_size, 64);
4412 r->rspq.uld = CXGB4_ULD_RDMA;
4415 init_rspq(adap, &s->fw_evtq, 0, 1, 1024, 64);
4416 init_rspq(adap, &s->intrq, 0, 1, 2 * MAX_INGQ, 64);
4420 * Reduce the number of Ethernet queues across all ports to at most n.
4421 * n provides at least one queue per port.
4423 static void reduce_ethqs(struct adapter *adap, int n)
4426 struct port_info *pi;
4428 while (n < adap->sge.ethqsets)
4429 for_each_port(adap, i) {
4430 pi = adap2pinfo(adap, i);
4431 if (pi->nqsets > 1) {
4433 adap->sge.ethqsets--;
4434 if (adap->sge.ethqsets <= n)
4440 for_each_port(adap, i) {
4441 pi = adap2pinfo(adap, i);
4447 /* 2 MSI-X vectors needed for the FW queue and non-data interrupts */
4448 #define EXTRA_VECS 2
4450 static int enable_msix(struct adapter *adap)
4453 int i, want, need, allocated;
4454 struct sge *s = &adap->sge;
4455 unsigned int nchan = adap->params.nports;
4456 struct msix_entry *entries;
4458 entries = kmalloc(sizeof(*entries) * (MAX_INGQ + 1),
4463 for (i = 0; i < MAX_INGQ + 1; ++i)
4464 entries[i].entry = i;
4466 want = s->max_ethqsets + EXTRA_VECS;
4467 if (is_offload(adap)) {
4468 want += s->rdmaqs + s->rdmaciqs + s->ofldqsets;
4469 /* need nchan for each possible ULD */
4470 ofld_need = 3 * nchan;
4472 #ifdef CONFIG_CHELSIO_T4_DCB
4473 /* For Data Center Bridging we need 8 Ethernet TX Priority Queues for
4476 need = 8 * adap->params.nports + EXTRA_VECS + ofld_need;
4478 need = adap->params.nports + EXTRA_VECS + ofld_need;
4480 allocated = pci_enable_msix_range(adap->pdev, entries, need, want);
4481 if (allocated < 0) {
4482 dev_info(adap->pdev_dev, "not enough MSI-X vectors left,"
4483 " not using MSI-X\n");
4488 /* Distribute available vectors to the various queue groups.
4489 * Every group gets its minimum requirement and NIC gets top
4490 * priority for leftovers.
4492 i = allocated - EXTRA_VECS - ofld_need;
4493 if (i < s->max_ethqsets) {
4494 s->max_ethqsets = i;
4495 if (i < s->ethqsets)
4496 reduce_ethqs(adap, i);
4498 if (is_offload(adap)) {
4499 if (allocated < want) {
4501 s->rdmaciqs = nchan;
4504 /* leftovers go to OFLD */
4505 i = allocated - EXTRA_VECS - s->max_ethqsets -
4506 s->rdmaqs - s->rdmaciqs;
4507 s->ofldqsets = (i / nchan) * nchan; /* round down */
4509 for (i = 0; i < allocated; ++i)
4510 adap->msix_info[i].vec = entries[i].vector;
4511 dev_info(adap->pdev_dev, "%d MSI-X vectors allocated, "
4512 "nic %d iscsi %d rdma cpl %d rdma ciq %d\n",
4513 allocated, s->max_ethqsets, s->ofldqsets, s->rdmaqs,
4522 static int init_rss(struct adapter *adap)
4527 err = t4_init_rss_mode(adap, adap->mbox);
4531 for_each_port(adap, i) {
4532 struct port_info *pi = adap2pinfo(adap, i);
4534 pi->rss = kcalloc(pi->rss_size, sizeof(u16), GFP_KERNEL);
4541 static void print_port_info(const struct net_device *dev)
4545 const char *spd = "";
4546 const struct port_info *pi = netdev_priv(dev);
4547 const struct adapter *adap = pi->adapter;
4549 if (adap->params.pci.speed == PCI_EXP_LNKSTA_CLS_2_5GB)
4551 else if (adap->params.pci.speed == PCI_EXP_LNKSTA_CLS_5_0GB)
4553 else if (adap->params.pci.speed == PCI_EXP_LNKSTA_CLS_8_0GB)
4556 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_100M)
4557 bufp += sprintf(bufp, "100/");
4558 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_1G)
4559 bufp += sprintf(bufp, "1000/");
4560 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_10G)
4561 bufp += sprintf(bufp, "10G/");
4562 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_40G)
4563 bufp += sprintf(bufp, "40G/");
4566 sprintf(bufp, "BASE-%s", t4_get_port_type_description(pi->port_type));
4568 netdev_info(dev, "Chelsio %s rev %d %s %sNIC PCIe x%d%s%s\n",
4569 adap->params.vpd.id,
4570 CHELSIO_CHIP_RELEASE(adap->params.chip), buf,
4571 is_offload(adap) ? "R" : "", adap->params.pci.width, spd,
4572 (adap->flags & USING_MSIX) ? " MSI-X" :
4573 (adap->flags & USING_MSI) ? " MSI" : "");
4574 netdev_info(dev, "S/N: %s, P/N: %s\n",
4575 adap->params.vpd.sn, adap->params.vpd.pn);
4578 static void enable_pcie_relaxed_ordering(struct pci_dev *dev)
4580 pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_RELAX_EN);
4584 * Free the following resources:
4585 * - memory used for tables
4588 * - resources FW is holding for us
4590 static void free_some_resources(struct adapter *adapter)
4594 t4_free_mem(adapter->l2t);
4595 t4_free_mem(adapter->tids.tid_tab);
4596 kfree(adapter->sge.egr_map);
4597 kfree(adapter->sge.ingr_map);
4598 kfree(adapter->sge.starving_fl);
4599 kfree(adapter->sge.txq_maperr);
4600 #ifdef CONFIG_DEBUG_FS
4601 kfree(adapter->sge.blocked_fl);
4603 disable_msi(adapter);
4605 for_each_port(adapter, i)
4606 if (adapter->port[i]) {
4607 struct port_info *pi = adap2pinfo(adapter, i);
4610 t4_free_vi(adapter, adapter->mbox, adapter->pf,
4612 kfree(adap2pinfo(adapter, i)->rss);
4613 free_netdev(adapter->port[i]);
4615 if (adapter->flags & FW_OK)
4616 t4_fw_bye(adapter, adapter->pf);
4619 #define TSO_FLAGS (NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_TSO_ECN)
4620 #define VLAN_FEAT (NETIF_F_SG | NETIF_F_IP_CSUM | TSO_FLAGS | \
4621 NETIF_F_IPV6_CSUM | NETIF_F_HIGHDMA)
4622 #define SEGMENT_SIZE 128
4624 static int get_chip_type(struct pci_dev *pdev, u32 pl_rev)
4628 /* Retrieve adapter's device ID */
4629 pci_read_config_word(pdev, PCI_DEVICE_ID, &device_id);
4631 switch (device_id >> 12) {
4633 return CHELSIO_CHIP_CODE(CHELSIO_T4, pl_rev);
4635 return CHELSIO_CHIP_CODE(CHELSIO_T5, pl_rev);
4637 return CHELSIO_CHIP_CODE(CHELSIO_T6, pl_rev);
4639 dev_err(&pdev->dev, "Device %d is not supported\n",
4645 static int init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
4647 int func, i, err, s_qpp, qpp, num_seg;
4648 struct port_info *pi;
4649 bool highdma = false;
4650 struct adapter *adapter = NULL;
4653 enum chip_type chip;
4655 printk_once(KERN_INFO "%s - version %s\n", DRV_DESC, DRV_VERSION);
4657 err = pci_request_regions(pdev, KBUILD_MODNAME);
4659 /* Just info, some other driver may have claimed the device. */
4660 dev_info(&pdev->dev, "cannot obtain PCI resources\n");
4664 err = pci_enable_device(pdev);
4666 dev_err(&pdev->dev, "cannot enable PCI device\n");
4667 goto out_release_regions;
4670 regs = pci_ioremap_bar(pdev, 0);
4672 dev_err(&pdev->dev, "cannot map device registers\n");
4674 goto out_disable_device;
4677 err = t4_wait_dev_ready(regs);
4679 goto out_unmap_bar0;
4681 /* We control everything through one PF */
4682 whoami = readl(regs + PL_WHOAMI_A);
4683 pl_rev = REV_G(readl(regs + PL_REV_A));
4684 chip = get_chip_type(pdev, pl_rev);
4685 func = CHELSIO_CHIP_VERSION(chip) <= CHELSIO_T5 ?
4686 SOURCEPF_G(whoami) : T6_SOURCEPF_G(whoami);
4687 if (func != ent->driver_data) {
4689 pci_disable_device(pdev);
4690 pci_save_state(pdev); /* to restore SR-IOV later */
4694 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
4696 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
4698 dev_err(&pdev->dev, "unable to obtain 64-bit DMA for "
4699 "coherent allocations\n");
4700 goto out_unmap_bar0;
4703 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
4705 dev_err(&pdev->dev, "no usable DMA configuration\n");
4706 goto out_unmap_bar0;
4710 pci_enable_pcie_error_reporting(pdev);
4711 enable_pcie_relaxed_ordering(pdev);
4712 pci_set_master(pdev);
4713 pci_save_state(pdev);
4715 adapter = kzalloc(sizeof(*adapter), GFP_KERNEL);
4718 goto out_unmap_bar0;
4721 adapter->workq = create_singlethread_workqueue("cxgb4");
4722 if (!adapter->workq) {
4724 goto out_free_adapter;
4727 /* PCI device has been enabled */
4728 adapter->flags |= DEV_ENABLED;
4730 adapter->regs = regs;
4731 adapter->pdev = pdev;
4732 adapter->pdev_dev = &pdev->dev;
4733 adapter->mbox = func;
4735 adapter->msg_enable = dflt_msg_enable;
4736 memset(adapter->chan_map, 0xff, sizeof(adapter->chan_map));
4738 spin_lock_init(&adapter->stats_lock);
4739 spin_lock_init(&adapter->tid_release_lock);
4740 spin_lock_init(&adapter->win0_lock);
4742 INIT_WORK(&adapter->tid_release_task, process_tid_release_list);
4743 INIT_WORK(&adapter->db_full_task, process_db_full);
4744 INIT_WORK(&adapter->db_drop_task, process_db_drop);
4746 err = t4_prep_adapter(adapter);
4748 goto out_free_adapter;
4751 if (!is_t4(adapter->params.chip)) {
4752 s_qpp = (QUEUESPERPAGEPF0_S +
4753 (QUEUESPERPAGEPF1_S - QUEUESPERPAGEPF0_S) *
4755 qpp = 1 << QUEUESPERPAGEPF0_G(t4_read_reg(adapter,
4756 SGE_EGRESS_QUEUES_PER_PAGE_PF_A) >> s_qpp);
4757 num_seg = PAGE_SIZE / SEGMENT_SIZE;
4759 /* Each segment size is 128B. Write coalescing is enabled only
4760 * when SGE_EGRESS_QUEUES_PER_PAGE_PF reg value for the
4761 * queue is less no of segments that can be accommodated in
4764 if (qpp > num_seg) {
4766 "Incorrect number of egress queues per page\n");
4768 goto out_free_adapter;
4770 adapter->bar2 = ioremap_wc(pci_resource_start(pdev, 2),
4771 pci_resource_len(pdev, 2));
4772 if (!adapter->bar2) {
4773 dev_err(&pdev->dev, "cannot map device bar2 region\n");
4775 goto out_free_adapter;
4779 setup_memwin(adapter);
4780 err = adap_init0(adapter);
4781 #ifdef CONFIG_DEBUG_FS
4782 bitmap_zero(adapter->sge.blocked_fl, adapter->sge.egr_sz);
4784 setup_memwin_rdma(adapter);
4788 /* configure SGE_STAT_CFG_A to read WC stats */
4789 if (!is_t4(adapter->params.chip))
4790 t4_write_reg(adapter, SGE_STAT_CFG_A,
4791 STATSOURCE_T5_V(7) | STATMODE_V(0));
4793 for_each_port(adapter, i) {
4794 struct net_device *netdev;
4796 netdev = alloc_etherdev_mq(sizeof(struct port_info),
4803 SET_NETDEV_DEV(netdev, &pdev->dev);
4805 adapter->port[i] = netdev;
4806 pi = netdev_priv(netdev);
4807 pi->adapter = adapter;
4808 pi->xact_addr_filt = -1;
4810 netdev->irq = pdev->irq;
4812 netdev->hw_features = NETIF_F_SG | TSO_FLAGS |
4813 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
4814 NETIF_F_RXCSUM | NETIF_F_RXHASH |
4815 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
4817 netdev->hw_features |= NETIF_F_HIGHDMA;
4818 netdev->features |= netdev->hw_features;
4819 netdev->vlan_features = netdev->features & VLAN_FEAT;
4821 netdev->priv_flags |= IFF_UNICAST_FLT;
4823 netdev->netdev_ops = &cxgb4_netdev_ops;
4824 #ifdef CONFIG_CHELSIO_T4_DCB
4825 netdev->dcbnl_ops = &cxgb4_dcb_ops;
4826 cxgb4_dcb_state_init(netdev);
4828 cxgb4_set_ethtool_ops(netdev);
4831 pci_set_drvdata(pdev, adapter);
4833 if (adapter->flags & FW_OK) {
4834 err = t4_port_init(adapter, func, func, 0);
4837 } else if (adapter->params.nports == 1) {
4838 /* If we don't have a connection to the firmware -- possibly
4839 * because of an error -- grab the raw VPD parameters so we
4840 * can set the proper MAC Address on the debug network
4841 * interface that we've created.
4843 u8 hw_addr[ETH_ALEN];
4844 u8 *na = adapter->params.vpd.na;
4846 err = t4_get_raw_vpd_params(adapter, &adapter->params.vpd);
4848 for (i = 0; i < ETH_ALEN; i++)
4849 hw_addr[i] = (hex2val(na[2 * i + 0]) * 16 +
4850 hex2val(na[2 * i + 1]));
4851 t4_set_hw_addr(adapter, 0, hw_addr);
4855 /* Configure queues and allocate tables now, they can be needed as
4856 * soon as the first register_netdev completes.
4858 cfg_queues(adapter);
4860 adapter->l2t = t4_init_l2t(adapter->l2t_start, adapter->l2t_end);
4861 if (!adapter->l2t) {
4862 /* We tolerate a lack of L2T, giving up some functionality */
4863 dev_warn(&pdev->dev, "could not allocate L2T, continuing\n");
4864 adapter->params.offload = 0;
4867 #if IS_ENABLED(CONFIG_IPV6)
4868 adapter->clipt = t4_init_clip_tbl(adapter->clipt_start,
4869 adapter->clipt_end);
4870 if (!adapter->clipt) {
4871 /* We tolerate a lack of clip_table, giving up
4872 * some functionality
4874 dev_warn(&pdev->dev,
4875 "could not allocate Clip table, continuing\n");
4876 adapter->params.offload = 0;
4879 if (is_offload(adapter) && tid_init(&adapter->tids) < 0) {
4880 dev_warn(&pdev->dev, "could not allocate TID table, "
4882 adapter->params.offload = 0;
4885 if (is_offload(adapter)) {
4886 if (t4_read_reg(adapter, LE_DB_CONFIG_A) & HASHEN_F) {
4887 u32 hash_base, hash_reg;
4889 if (chip <= CHELSIO_T5) {
4890 hash_reg = LE_DB_TID_HASHBASE_A;
4891 hash_base = t4_read_reg(adapter, hash_reg);
4892 adapter->tids.hash_base = hash_base / 4;
4894 hash_reg = T6_LE_DB_HASH_TID_BASE_A;
4895 hash_base = t4_read_reg(adapter, hash_reg);
4896 adapter->tids.hash_base = hash_base;
4901 /* See what interrupts we'll be using */
4902 if (msi > 1 && enable_msix(adapter) == 0)
4903 adapter->flags |= USING_MSIX;
4904 else if (msi > 0 && pci_enable_msi(pdev) == 0)
4905 adapter->flags |= USING_MSI;
4907 err = init_rss(adapter);
4912 * The card is now ready to go. If any errors occur during device
4913 * registration we do not fail the whole card but rather proceed only
4914 * with the ports we manage to register successfully. However we must
4915 * register at least one net device.
4917 for_each_port(adapter, i) {
4918 pi = adap2pinfo(adapter, i);
4919 netif_set_real_num_tx_queues(adapter->port[i], pi->nqsets);
4920 netif_set_real_num_rx_queues(adapter->port[i], pi->nqsets);
4922 err = register_netdev(adapter->port[i]);
4925 adapter->chan_map[pi->tx_chan] = i;
4926 print_port_info(adapter->port[i]);
4929 dev_err(&pdev->dev, "could not register any net devices\n");
4933 dev_warn(&pdev->dev, "only %d net devices registered\n", i);
4937 if (cxgb4_debugfs_root) {
4938 adapter->debugfs_root = debugfs_create_dir(pci_name(pdev),
4939 cxgb4_debugfs_root);
4940 setup_debugfs(adapter);
4943 /* PCIe EEH recovery on powerpc platforms needs fundamental reset */
4944 pdev->needs_freset = 1;
4946 if (is_offload(adapter))
4947 attach_ulds(adapter);
4950 #ifdef CONFIG_PCI_IOV
4951 if (func < ARRAY_SIZE(num_vf) && num_vf[func] > 0)
4952 if (pci_enable_sriov(pdev, num_vf[func]) == 0)
4953 dev_info(&pdev->dev,
4954 "instantiated %u virtual functions\n",
4960 free_some_resources(adapter);
4962 if (!is_t4(adapter->params.chip))
4963 iounmap(adapter->bar2);
4966 destroy_workqueue(adapter->workq);
4972 pci_disable_pcie_error_reporting(pdev);
4973 pci_disable_device(pdev);
4974 out_release_regions:
4975 pci_release_regions(pdev);
4979 static void remove_one(struct pci_dev *pdev)
4981 struct adapter *adapter = pci_get_drvdata(pdev);
4983 #ifdef CONFIG_PCI_IOV
4984 pci_disable_sriov(pdev);
4991 /* Tear down per-adapter Work Queue first since it can contain
4992 * references to our adapter data structure.
4994 destroy_workqueue(adapter->workq);
4996 if (is_offload(adapter))
4997 detach_ulds(adapter);
4999 disable_interrupts(adapter);
5001 for_each_port(adapter, i)
5002 if (adapter->port[i]->reg_state == NETREG_REGISTERED)
5003 unregister_netdev(adapter->port[i]);
5005 debugfs_remove_recursive(adapter->debugfs_root);
5007 /* If we allocated filters, free up state associated with any
5010 if (adapter->tids.ftid_tab) {
5011 struct filter_entry *f = &adapter->tids.ftid_tab[0];
5012 for (i = 0; i < (adapter->tids.nftids +
5013 adapter->tids.nsftids); i++, f++)
5015 clear_filter(adapter, f);
5018 if (adapter->flags & FULL_INIT_DONE)
5021 free_some_resources(adapter);
5022 #if IS_ENABLED(CONFIG_IPV6)
5023 t4_cleanup_clip_tbl(adapter);
5025 iounmap(adapter->regs);
5026 if (!is_t4(adapter->params.chip))
5027 iounmap(adapter->bar2);
5028 pci_disable_pcie_error_reporting(pdev);
5029 if ((adapter->flags & DEV_ENABLED)) {
5030 pci_disable_device(pdev);
5031 adapter->flags &= ~DEV_ENABLED;
5033 pci_release_regions(pdev);
5037 pci_release_regions(pdev);
5040 static struct pci_driver cxgb4_driver = {
5041 .name = KBUILD_MODNAME,
5042 .id_table = cxgb4_pci_tbl,
5044 .remove = remove_one,
5045 .shutdown = remove_one,
5046 .err_handler = &cxgb4_eeh,
5049 static int __init cxgb4_init_module(void)
5053 /* Debugfs support is optional, just warn if this fails */
5054 cxgb4_debugfs_root = debugfs_create_dir(KBUILD_MODNAME, NULL);
5055 if (!cxgb4_debugfs_root)
5056 pr_warn("could not create debugfs entry, continuing\n");
5058 ret = pci_register_driver(&cxgb4_driver);
5060 debugfs_remove(cxgb4_debugfs_root);
5062 #if IS_ENABLED(CONFIG_IPV6)
5063 if (!inet6addr_registered) {
5064 register_inet6addr_notifier(&cxgb4_inet6addr_notifier);
5065 inet6addr_registered = true;
5072 static void __exit cxgb4_cleanup_module(void)
5074 #if IS_ENABLED(CONFIG_IPV6)
5075 if (inet6addr_registered) {
5076 unregister_inet6addr_notifier(&cxgb4_inet6addr_notifier);
5077 inet6addr_registered = false;
5080 pci_unregister_driver(&cxgb4_driver);
5081 debugfs_remove(cxgb4_debugfs_root); /* NULL ok */
5084 module_init(cxgb4_init_module);
5085 module_exit(cxgb4_cleanup_module);