drivers/net/ethernet/chelsio/cxgb4/cudbg_lib.c

   1 /*
   2  *  Copyright (C) 2017 Chelsio Communications.  All rights reserved.
   3  *
   4  *  This program is free software; you can redistribute it and/or modify it
   5  *  under the terms and conditions of the GNU General Public License,
   6  *  version 2, as published by the Free Software Foundation.
   7  *
   8  *  This program is distributed in the hope it will be useful, but WITHOUT
   9  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  10  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  11  *  more details.
  12  *
  13  *  The full GNU General Public License is included in this distribution in
  14  *  the file called "COPYING".
  15  *
  16  */
  17
  18 #include <linux/sort.h>
  19
  20 #include "t4_regs.h"
  21 #include "cxgb4.h"
  22 #include "cudbg_if.h"
  23 #include "cudbg_lib_common.h"
  24 #include "cudbg_entity.h"
  25 #include "cudbg_lib.h"
  26 #include "cudbg_zlib.h"
  27
  28 static int cudbg_do_compression(struct cudbg_init *pdbg_init,
  29                                 struct cudbg_buffer *pin_buff,
  30                                 struct cudbg_buffer *dbg_buff)
  31 {
  32         struct cudbg_buffer temp_in_buff = { 0 };
  33         int bytes_left, bytes_read, bytes;
  34         u32 offset = dbg_buff->offset;
  35         int rc;
  36
  37         temp_in_buff.offset = pin_buff->offset;
  38         temp_in_buff.data = pin_buff->data;
  39         temp_in_buff.size = pin_buff->size;
  40
  41         bytes_left = pin_buff->size;
  42         bytes_read = 0;
  43         while (bytes_left > 0) {
  44                 /* Do compression in smaller chunks */
  45                 bytes = min_t(unsigned long, bytes_left,
  46                               (unsigned long)CUDBG_CHUNK_SIZE);
  47                 temp_in_buff.data = (char *)pin_buff->data + bytes_read;
  48                 temp_in_buff.size = bytes;
  49                 rc = cudbg_compress_buff(pdbg_init, &temp_in_buff, dbg_buff);
  50                 if (rc)
  51                         return rc;
  52                 bytes_left -= bytes;
  53                 bytes_read += bytes;
  54         }
  55
  56         pin_buff->size = dbg_buff->offset - offset;
  57         return 0;
  58 }
  59
  60 static int cudbg_write_and_release_buff(struct cudbg_init *pdbg_init,
  61                                         struct cudbg_buffer *pin_buff,
  62                                         struct cudbg_buffer *dbg_buff)
  63 {
  64         int rc = 0;
  65
  66         if (pdbg_init->compress_type == CUDBG_COMPRESSION_NONE) {
  67                 cudbg_update_buff(pin_buff, dbg_buff);
  68         } else {
  69                 rc = cudbg_do_compression(pdbg_init, pin_buff, dbg_buff);
  70                 if (rc)
  71                         goto out;
  72         }
  73
  74 out:
  75         cudbg_put_buff(pdbg_init, pin_buff);
  76         return rc;
  77 }
  78
  79 static int is_fw_attached(struct cudbg_init *pdbg_init)
  80 {
  81         struct adapter *padap = pdbg_init->adap;
  82
  83         if (!(padap->flags & FW_OK) || padap->use_bd)
  84                 return 0;
  85
  86         return 1;
  87 }
  88
  89 /* This function will add additional padding bytes into debug_buffer to make it
  90  * 4 byte aligned.
  91  */
  92 void cudbg_align_debug_buffer(struct cudbg_buffer *dbg_buff,
  93                               struct cudbg_entity_hdr *entity_hdr)
  94 {
  95         u8 zero_buf[4] = {0};
  96         u8 padding, remain;
  97
  98         remain = (dbg_buff->offset - entity_hdr->start_offset) % 4;
  99         padding = 4 - remain;
 100         if (remain) {
 101                 memcpy(((u8 *)dbg_buff->data) + dbg_buff->offset, &zero_buf,
 102                        padding);
 103                 dbg_buff->offset += padding;
 104                 entity_hdr->num_pad = padding;
 105         }
 106         entity_hdr->size = dbg_buff->offset - entity_hdr->start_offset;
 107 }
 108
 109 struct cudbg_entity_hdr *cudbg_get_entity_hdr(void *outbuf, int i)
 110 {
 111         struct cudbg_hdr *cudbg_hdr = (struct cudbg_hdr *)outbuf;
 112
 113         return (struct cudbg_entity_hdr *)
 114                ((char *)outbuf + cudbg_hdr->hdr_len +
 115                 (sizeof(struct cudbg_entity_hdr) * (i - 1)));
 116 }
 117
 118 static int cudbg_read_vpd_reg(struct adapter *padap, u32 addr, u32 len,
 119                               void *dest)
 120 {
 121         int vaddr, rc;
 122
 123         vaddr = t4_eeprom_ptov(addr, padap->pf, EEPROMPFSIZE);
 124         if (vaddr < 0)
 125                 return vaddr;
 126
 127         rc = pci_read_vpd(padap->pdev, vaddr, len, dest);
 128         if (rc < 0)
 129                 return rc;
 130
 131         return 0;
 132 }
 133
 134 static int cudbg_mem_desc_cmp(const void *a, const void *b)
 135 {
 136         return ((const struct cudbg_mem_desc *)a)->base -
 137                ((const struct cudbg_mem_desc *)b)->base;
 138 }
 139
 140 int cudbg_fill_meminfo(struct adapter *padap,
 141                        struct cudbg_meminfo *meminfo_buff)
 142 {
 143         struct cudbg_mem_desc *md;
 144         u32 lo, hi, used, alloc;
 145         int n, i;
 146
 147         memset(meminfo_buff->avail, 0,
 148                ARRAY_SIZE(meminfo_buff->avail) *
 149                sizeof(struct cudbg_mem_desc));
 150         memset(meminfo_buff->mem, 0,
 151                (ARRAY_SIZE(cudbg_region) + 3) * sizeof(struct cudbg_mem_desc));
 152         md  = meminfo_buff->mem;
 153
 154         for (i = 0; i < ARRAY_SIZE(meminfo_buff->mem); i++) {
 155                 meminfo_buff->mem[i].limit = 0;
 156                 meminfo_buff->mem[i].idx = i;
 157         }
 158
 159         /* Find and sort the populated memory ranges */
 160         i = 0;
 161         lo = t4_read_reg(padap, MA_TARGET_MEM_ENABLE_A);
 162         if (lo & EDRAM0_ENABLE_F) {
 163                 hi = t4_read_reg(padap, MA_EDRAM0_BAR_A);
 164                 meminfo_buff->avail[i].base =
 165                         cudbg_mbytes_to_bytes(EDRAM0_BASE_G(hi));
 166                 meminfo_buff->avail[i].limit =
 167                         meminfo_buff->avail[i].base +
 168                         cudbg_mbytes_to_bytes(EDRAM0_SIZE_G(hi));
 169                 meminfo_buff->avail[i].idx = 0;
 170                 i++;
 171         }
 172
 173         if (lo & EDRAM1_ENABLE_F) {
 174                 hi =  t4_read_reg(padap, MA_EDRAM1_BAR_A);
 175                 meminfo_buff->avail[i].base =
 176                         cudbg_mbytes_to_bytes(EDRAM1_BASE_G(hi));
 177                 meminfo_buff->avail[i].limit =
 178                         meminfo_buff->avail[i].base +
 179                         cudbg_mbytes_to_bytes(EDRAM1_SIZE_G(hi));
 180                 meminfo_buff->avail[i].idx = 1;
 181                 i++;
 182         }
 183
 184         if (is_t5(padap->params.chip)) {
 185                 if (lo & EXT_MEM0_ENABLE_F) {
 186                         hi = t4_read_reg(padap, MA_EXT_MEMORY0_BAR_A);
 187                         meminfo_buff->avail[i].base =
 188                                 cudbg_mbytes_to_bytes(EXT_MEM_BASE_G(hi));
 189                         meminfo_buff->avail[i].limit =
 190                                 meminfo_buff->avail[i].base +
 191                                 cudbg_mbytes_to_bytes(EXT_MEM_SIZE_G(hi));
 192                         meminfo_buff->avail[i].idx = 3;
 193                         i++;
 194                 }
 195
 196                 if (lo & EXT_MEM1_ENABLE_F) {
 197                         hi = t4_read_reg(padap, MA_EXT_MEMORY1_BAR_A);
 198                         meminfo_buff->avail[i].base =
 199                                 cudbg_mbytes_to_bytes(EXT_MEM1_BASE_G(hi));
 200                         meminfo_buff->avail[i].limit =
 201                                 meminfo_buff->avail[i].base +
 202                                 cudbg_mbytes_to_bytes(EXT_MEM1_SIZE_G(hi));
 203                         meminfo_buff->avail[i].idx = 4;
 204                         i++;
 205                 }
 206         } else {
 207                 if (lo & EXT_MEM_ENABLE_F) {
 208                         hi = t4_read_reg(padap, MA_EXT_MEMORY_BAR_A);
 209                         meminfo_buff->avail[i].base =
 210                                 cudbg_mbytes_to_bytes(EXT_MEM_BASE_G(hi));
 211                         meminfo_buff->avail[i].limit =
 212                                 meminfo_buff->avail[i].base +
 213                                 cudbg_mbytes_to_bytes(EXT_MEM_SIZE_G(hi));
 214                         meminfo_buff->avail[i].idx = 2;
 215                         i++;
 216                 }
 217
 218                 if (lo & HMA_MUX_F) {
 219                         hi = t4_read_reg(padap, MA_EXT_MEMORY1_BAR_A);
 220                         meminfo_buff->avail[i].base =
 221                                 cudbg_mbytes_to_bytes(EXT_MEM1_BASE_G(hi));
 222                         meminfo_buff->avail[i].limit =
 223                                 meminfo_buff->avail[i].base +
 224                                 cudbg_mbytes_to_bytes(EXT_MEM1_SIZE_G(hi));
 225                         meminfo_buff->avail[i].idx = 5;
 226                         i++;
 227                 }
 228         }
 229
 230         if (!i) /* no memory available */
 231                 return CUDBG_STATUS_ENTITY_NOT_FOUND;
 232
 233         meminfo_buff->avail_c = i;
 234         sort(meminfo_buff->avail, i, sizeof(struct cudbg_mem_desc),
 235              cudbg_mem_desc_cmp, NULL);
 236         (md++)->base = t4_read_reg(padap, SGE_DBQ_CTXT_BADDR_A);
 237         (md++)->base = t4_read_reg(padap, SGE_IMSG_CTXT_BADDR_A);
 238         (md++)->base = t4_read_reg(padap, SGE_FLM_CACHE_BADDR_A);
 239         (md++)->base = t4_read_reg(padap, TP_CMM_TCB_BASE_A);
 240         (md++)->base = t4_read_reg(padap, TP_CMM_MM_BASE_A);
 241         (md++)->base = t4_read_reg(padap, TP_CMM_TIMER_BASE_A);
 242         (md++)->base = t4_read_reg(padap, TP_CMM_MM_RX_FLST_BASE_A);
 243         (md++)->base = t4_read_reg(padap, TP_CMM_MM_TX_FLST_BASE_A);
 244         (md++)->base = t4_read_reg(padap, TP_CMM_MM_PS_FLST_BASE_A);
 245
 246         /* the next few have explicit upper bounds */
 247         md->base = t4_read_reg(padap, TP_PMM_TX_BASE_A);
 248         md->limit = md->base - 1 +
 249                     t4_read_reg(padap, TP_PMM_TX_PAGE_SIZE_A) *
 250                     PMTXMAXPAGE_G(t4_read_reg(padap, TP_PMM_TX_MAX_PAGE_A));
 251         md++;
 252
 253         md->base = t4_read_reg(padap, TP_PMM_RX_BASE_A);
 254         md->limit = md->base - 1 +
 255                     t4_read_reg(padap, TP_PMM_RX_PAGE_SIZE_A) *
 256                     PMRXMAXPAGE_G(t4_read_reg(padap, TP_PMM_RX_MAX_PAGE_A));
 257         md++;
 258
 259         if (t4_read_reg(padap, LE_DB_CONFIG_A) & HASHEN_F) {
 260                 if (CHELSIO_CHIP_VERSION(padap->params.chip) <= CHELSIO_T5) {
 261                         hi = t4_read_reg(padap, LE_DB_TID_HASHBASE_A) / 4;
 262                         md->base = t4_read_reg(padap, LE_DB_HASH_TID_BASE_A);
 263                 } else {
 264                         hi = t4_read_reg(padap, LE_DB_HASH_TID_BASE_A);
 265                         md->base = t4_read_reg(padap,
 266                                                LE_DB_HASH_TBL_BASE_ADDR_A);
 267                 }
 268                 md->limit = 0;
 269         } else {
 270                 md->base = 0;
 271                 md->idx = ARRAY_SIZE(cudbg_region);  /* hide it */
 272         }
 273         md++;
 274
 275 #define ulp_region(reg) do { \
 276         md->base = t4_read_reg(padap, ULP_ ## reg ## _LLIMIT_A);\
 277         (md++)->limit = t4_read_reg(padap, ULP_ ## reg ## _ULIMIT_A);\
 278 } while (0)
 279
 280         ulp_region(RX_ISCSI);
 281         ulp_region(RX_TDDP);
 282         ulp_region(TX_TPT);
 283         ulp_region(RX_STAG);
 284         ulp_region(RX_RQ);
 285         ulp_region(RX_RQUDP);
 286         ulp_region(RX_PBL);
 287         ulp_region(TX_PBL);
 288 #undef ulp_region
 289         md->base = 0;
 290         md->idx = ARRAY_SIZE(cudbg_region);
 291         if (!is_t4(padap->params.chip)) {
 292                 u32 fifo_size = t4_read_reg(padap, SGE_DBVFIFO_SIZE_A);
 293                 u32 sge_ctrl = t4_read_reg(padap, SGE_CONTROL2_A);
 294                 u32 size = 0;
 295
 296                 if (is_t5(padap->params.chip)) {
 297                         if (sge_ctrl & VFIFO_ENABLE_F)
 298                                 size = DBVFIFO_SIZE_G(fifo_size);
 299                 } else {
 300                         size = T6_DBVFIFO_SIZE_G(fifo_size);
 301                 }
 302
 303                 if (size) {
 304                         md->base = BASEADDR_G(t4_read_reg(padap,
 305                                                           SGE_DBVFIFO_BADDR_A));
 306                         md->limit = md->base + (size << 2) - 1;
 307                 }
 308         }
 309
 310         md++;
 311
 312         md->base = t4_read_reg(padap, ULP_RX_CTX_BASE_A);
 313         md->limit = 0;
 314         md++;
 315         md->base = t4_read_reg(padap, ULP_TX_ERR_TABLE_BASE_A);
 316         md->limit = 0;
 317         md++;
 318
 319         md->base = padap->vres.ocq.start;
 320         if (padap->vres.ocq.size)
 321                 md->limit = md->base + padap->vres.ocq.size - 1;
 322         else
 323                 md->idx = ARRAY_SIZE(cudbg_region);  /* hide it */
 324         md++;
 325
 326         /* add any address-space holes, there can be up to 3 */
 327         for (n = 0; n < i - 1; n++)
 328                 if (meminfo_buff->avail[n].limit <
 329                     meminfo_buff->avail[n + 1].base)
 330                         (md++)->base = meminfo_buff->avail[n].limit;
 331
 332         if (meminfo_buff->avail[n].limit)
 333                 (md++)->base = meminfo_buff->avail[n].limit;
 334
 335         n = md - meminfo_buff->mem;
 336         meminfo_buff->mem_c = n;
 337
 338         sort(meminfo_buff->mem, n, sizeof(struct cudbg_mem_desc),
 339              cudbg_mem_desc_cmp, NULL);
 340
 341         lo = t4_read_reg(padap, CIM_SDRAM_BASE_ADDR_A);
 342         hi = t4_read_reg(padap, CIM_SDRAM_ADDR_SIZE_A) + lo - 1;
 343         meminfo_buff->up_ram_lo = lo;
 344         meminfo_buff->up_ram_hi = hi;
 345
 346         lo = t4_read_reg(padap, CIM_EXTMEM2_BASE_ADDR_A);
 347         hi = t4_read_reg(padap, CIM_EXTMEM2_ADDR_SIZE_A) + lo - 1;
 348         meminfo_buff->up_extmem2_lo = lo;
 349         meminfo_buff->up_extmem2_hi = hi;
 350
 351         lo = t4_read_reg(padap, TP_PMM_RX_MAX_PAGE_A);
 352         meminfo_buff->rx_pages_data[0] =  PMRXMAXPAGE_G(lo);
 353         meminfo_buff->rx_pages_data[1] =
 354                 t4_read_reg(padap, TP_PMM_RX_PAGE_SIZE_A) >> 10;
 355         meminfo_buff->rx_pages_data[2] = (lo & PMRXNUMCHN_F) ? 2 : 1;
 356
 357         lo = t4_read_reg(padap, TP_PMM_TX_MAX_PAGE_A);
 358         hi = t4_read_reg(padap, TP_PMM_TX_PAGE_SIZE_A);
 359         meminfo_buff->tx_pages_data[0] = PMTXMAXPAGE_G(lo);
 360         meminfo_buff->tx_pages_data[1] =
 361                 hi >= (1 << 20) ? (hi >> 20) : (hi >> 10);
 362         meminfo_buff->tx_pages_data[2] =
 363                 hi >= (1 << 20) ? 'M' : 'K';
 364         meminfo_buff->tx_pages_data[3] = 1 << PMTXNUMCHN_G(lo);
 365
 366         meminfo_buff->p_structs = t4_read_reg(padap, TP_CMM_MM_MAX_PSTRUCT_A);
 367
 368         for (i = 0; i < 4; i++) {
 369                 if (CHELSIO_CHIP_VERSION(padap->params.chip) > CHELSIO_T5)
 370                         lo = t4_read_reg(padap,
 371                                          MPS_RX_MAC_BG_PG_CNT0_A + i * 4);
 372                 else
 373                         lo = t4_read_reg(padap, MPS_RX_PG_RSV0_A + i * 4);
 374                 if (is_t5(padap->params.chip)) {
 375                         used = T5_USED_G(lo);
 376                         alloc = T5_ALLOC_G(lo);
 377                 } else {
 378                         used = USED_G(lo);
 379                         alloc = ALLOC_G(lo);
 380                 }
 381                 meminfo_buff->port_used[i] = used;
 382                 meminfo_buff->port_alloc[i] = alloc;
 383         }
 384
 385         for (i = 0; i < padap->params.arch.nchan; i++) {
 386                 if (CHELSIO_CHIP_VERSION(padap->params.chip) > CHELSIO_T5)
 387                         lo = t4_read_reg(padap,
 388                                          MPS_RX_LPBK_BG_PG_CNT0_A + i * 4);
 389                 else
 390                         lo = t4_read_reg(padap, MPS_RX_PG_RSV4_A + i * 4);
 391                 if (is_t5(padap->params.chip)) {
 392                         used = T5_USED_G(lo);
 393                         alloc = T5_ALLOC_G(lo);
 394                 } else {
 395                         used = USED_G(lo);
 396                         alloc = ALLOC_G(lo);
 397                 }
 398                 meminfo_buff->loopback_used[i] = used;
 399                 meminfo_buff->loopback_alloc[i] = alloc;
 400         }
 401
 402         return 0;
 403 }
 404
 405 int cudbg_collect_reg_dump(struct cudbg_init *pdbg_init,
 406                            struct cudbg_buffer *dbg_buff,
 407                            struct cudbg_error *cudbg_err)
 408 {
 409         struct adapter *padap = pdbg_init->adap;
 410         struct cudbg_buffer temp_buff = { 0 };
 411         u32 buf_size = 0;
 412         int rc = 0;
 413
 414         if (is_t4(padap->params.chip))
 415                 buf_size = T4_REGMAP_SIZE;
 416         else if (is_t5(padap->params.chip) || is_t6(padap->params.chip))
 417                 buf_size = T5_REGMAP_SIZE;
 418
 419         rc = cudbg_get_buff(pdbg_init, dbg_buff, buf_size, &temp_buff);
 420         if (rc)
 421                 return rc;
 422         t4_get_regs(padap, (void *)temp_buff.data, temp_buff.size);
 423         return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff);
 424 }
 425
 426 int cudbg_collect_fw_devlog(struct cudbg_init *pdbg_init,
 427                             struct cudbg_buffer *dbg_buff,
 428                             struct cudbg_error *cudbg_err)
 429 {
 430         struct adapter *padap = pdbg_init->adap;
 431         struct cudbg_buffer temp_buff = { 0 };
 432         struct devlog_params *dparams;
 433         int rc = 0;
 434
 435         rc = t4_init_devlog_params(padap);
 436         if (rc < 0) {
 437                 cudbg_err->sys_err = rc;
 438                 return rc;
 439         }
 440
 441         dparams = &padap->params.devlog;
 442         rc = cudbg_get_buff(pdbg_init, dbg_buff, dparams->size, &temp_buff);
 443         if (rc)
 444                 return rc;
 445
 446         /* Collect FW devlog */
 447         if (dparams->start != 0) {
 448                 spin_lock(&padap->win0_lock);
 449                 rc = t4_memory_rw(padap, padap->params.drv_memwin,
 450                                   dparams->memtype, dparams->start,
 451                                   dparams->size,
 452                                   (__be32 *)(char *)temp_buff.data,
 453                                   1);
 454                 spin_unlock(&padap->win0_lock);
 455                 if (rc) {
 456                         cudbg_err->sys_err = rc;
 457                         cudbg_put_buff(pdbg_init, &temp_buff);
 458                         return rc;
 459                 }
 460         }
 461         return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff);
 462 }
 463
 464 int cudbg_collect_cim_la(struct cudbg_init *pdbg_init,
 465                          struct cudbg_buffer *dbg_buff,
 466                          struct cudbg_error *cudbg_err)
 467 {
 468         struct adapter *padap = pdbg_init->adap;
 469         struct cudbg_buffer temp_buff = { 0 };
 470         int size, rc;
 471         u32 cfg = 0;
 472
 473         if (is_t6(padap->params.chip)) {
 474                 size = padap->params.cim_la_size / 10 + 1;
 475                 size *= 10 * sizeof(u32);
 476         } else {
 477                 size = padap->params.cim_la_size / 8;
 478                 size *= 8 * sizeof(u32);
 479         }
 480
 481         size += sizeof(cfg);
 482         rc = cudbg_get_buff(pdbg_init, dbg_buff, size, &temp_buff);
 483         if (rc)
 484                 return rc;
 485
 486         rc = t4_cim_read(padap, UP_UP_DBG_LA_CFG_A, 1, &cfg);
 487         if (rc) {
 488                 cudbg_err->sys_err = rc;
 489                 cudbg_put_buff(pdbg_init, &temp_buff);
 490                 return rc;
 491         }
 492
 493         memcpy((char *)temp_buff.data, &cfg, sizeof(cfg));
 494         rc = t4_cim_read_la(padap,
 495                             (u32 *)((char *)temp_buff.data + sizeof(cfg)),
 496                             NULL);
 497         if (rc < 0) {
 498                 cudbg_err->sys_err = rc;
 499                 cudbg_put_buff(pdbg_init, &temp_buff);
 500                 return rc;
 501         }
 502         return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff);
 503 }
 504
 505 int cudbg_collect_cim_ma_la(struct cudbg_init *pdbg_init,
 506                             struct cudbg_buffer *dbg_buff,
 507                             struct cudbg_error *cudbg_err)
 508 {
 509         struct adapter *padap = pdbg_init->adap;
 510         struct cudbg_buffer temp_buff = { 0 };
 511         int size, rc;
 512
 513         size = 2 * CIM_MALA_SIZE * 5 * sizeof(u32);
 514         rc = cudbg_get_buff(pdbg_init, dbg_buff, size, &temp_buff);
 515         if (rc)
 516                 return rc;
 517
 518         t4_cim_read_ma_la(padap,
 519                           (u32 *)temp_buff.data,
 520                           (u32 *)((char *)temp_buff.data +
 521                                   5 * CIM_MALA_SIZE));
 522         return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff);
 523 }
 524
 525 int cudbg_collect_cim_qcfg(struct cudbg_init *pdbg_init,
 526                            struct cudbg_buffer *dbg_buff,
 527                            struct cudbg_error *cudbg_err)
 528 {
 529         struct adapter *padap = pdbg_init->adap;
 530         struct cudbg_buffer temp_buff = { 0 };
 531         struct cudbg_cim_qcfg *cim_qcfg_data;
 532         int rc;
 533
 534         rc = cudbg_get_buff(pdbg_init, dbg_buff, sizeof(struct cudbg_cim_qcfg),
 535                             &temp_buff);
 536         if (rc)
 537                 return rc;
 538
 539         cim_qcfg_data = (struct cudbg_cim_qcfg *)temp_buff.data;
 540         cim_qcfg_data->chip = padap->params.chip;
 541         rc = t4_cim_read(padap, UP_IBQ_0_RDADDR_A,
 542                          ARRAY_SIZE(cim_qcfg_data->stat), cim_qcfg_data->stat);
 543         if (rc) {
 544                 cudbg_err->sys_err = rc;
 545                 cudbg_put_buff(pdbg_init, &temp_buff);
 546                 return rc;
 547         }
 548
 549         rc = t4_cim_read(padap, UP_OBQ_0_REALADDR_A,
 550                          ARRAY_SIZE(cim_qcfg_data->obq_wr),
 551                          cim_qcfg_data->obq_wr);
 552         if (rc) {
 553                 cudbg_err->sys_err = rc;
 554                 cudbg_put_buff(pdbg_init, &temp_buff);
 555                 return rc;
 556         }
 557
 558         t4_read_cimq_cfg(padap, cim_qcfg_data->base, cim_qcfg_data->size,
 559                          cim_qcfg_data->thres);
 560         return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff);
 561 }
 562
 563 static int cudbg_read_cim_ibq(struct cudbg_init *pdbg_init,
 564                               struct cudbg_buffer *dbg_buff,
 565                               struct cudbg_error *cudbg_err, int qid)
 566 {
 567         struct adapter *padap = pdbg_init->adap;
 568         struct cudbg_buffer temp_buff = { 0 };
 569         int no_of_read_words, rc = 0;
 570         u32 qsize;
 571
 572         /* collect CIM IBQ */
 573         qsize = CIM_IBQ_SIZE * 4 * sizeof(u32);
 574         rc = cudbg_get_buff(pdbg_init, dbg_buff, qsize, &temp_buff);
 575         if (rc)
 576                 return rc;
 577
 578         /* t4_read_cim_ibq will return no. of read words or error */
 579         no_of_read_words = t4_read_cim_ibq(padap, qid,
 580                                            (u32 *)temp_buff.data, qsize);
 581         /* no_of_read_words is less than or equal to 0 means error */
 582         if (no_of_read_words <= 0) {
 583                 if (!no_of_read_words)
 584                         rc = CUDBG_SYSTEM_ERROR;
 585                 else
 586                         rc = no_of_read_words;
 587                 cudbg_err->sys_err = rc;
 588                 cudbg_put_buff(pdbg_init, &temp_buff);
 589                 return rc;
 590         }
 591         return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff);
 592 }
 593
 594 int cudbg_collect_cim_ibq_tp0(struct cudbg_init *pdbg_init,
 595                               struct cudbg_buffer *dbg_buff,
 596                               struct cudbg_error *cudbg_err)
 597 {
 598         return cudbg_read_cim_ibq(pdbg_init, dbg_buff, cudbg_err, 0);
 599 }
 600
 601 int cudbg_collect_cim_ibq_tp1(struct cudbg_init *pdbg_init,
 602                               struct cudbg_buffer *dbg_buff,
 603                               struct cudbg_error *cudbg_err)
 604 {
 605         return cudbg_read_cim_ibq(pdbg_init, dbg_buff, cudbg_err, 1);
 606 }
 607
 608 int cudbg_collect_cim_ibq_ulp(struct cudbg_init *pdbg_init,
 609                               struct cudbg_buffer *dbg_buff,
 610                               struct cudbg_error *cudbg_err)
 611 {
 612         return cudbg_read_cim_ibq(pdbg_init, dbg_buff, cudbg_err, 2);
 613 }
 614
 615 int cudbg_collect_cim_ibq_sge0(struct cudbg_init *pdbg_init,
 616                                struct cudbg_buffer *dbg_buff,
 617                                struct cudbg_error *cudbg_err)
 618 {
 619         return cudbg_read_cim_ibq(pdbg_init, dbg_buff, cudbg_err, 3);
 620 }
 621
 622 int cudbg_collect_cim_ibq_sge1(struct cudbg_init *pdbg_init,
 623                                struct cudbg_buffer *dbg_buff,
 624                                struct cudbg_error *cudbg_err)
 625 {
 626         return cudbg_read_cim_ibq(pdbg_init, dbg_buff, cudbg_err, 4);
 627 }
 628
 629 int cudbg_collect_cim_ibq_ncsi(struct cudbg_init *pdbg_init,
 630                                struct cudbg_buffer *dbg_buff,
 631                                struct cudbg_error *cudbg_err)
 632 {
 633         return cudbg_read_cim_ibq(pdbg_init, dbg_buff, cudbg_err, 5);
 634 }
 635
 636 u32 cudbg_cim_obq_size(struct adapter *padap, int qid)
 637 {
 638         u32 value;
 639
 640         t4_write_reg(padap, CIM_QUEUE_CONFIG_REF_A, OBQSELECT_F |
 641                      QUENUMSELECT_V(qid));
 642         value = t4_read_reg(padap, CIM_QUEUE_CONFIG_CTRL_A);
 643         value = CIMQSIZE_G(value) * 64; /* size in number of words */
 644         return value * sizeof(u32);
 645 }
 646
 647 static int cudbg_read_cim_obq(struct cudbg_init *pdbg_init,
 648                               struct cudbg_buffer *dbg_buff,
 649                               struct cudbg_error *cudbg_err, int qid)
 650 {
 651         struct adapter *padap = pdbg_init->adap;
 652         struct cudbg_buffer temp_buff = { 0 };
 653         int no_of_read_words, rc = 0;
 654         u32 qsize;
 655
 656         /* collect CIM OBQ */
 657         qsize =  cudbg_cim_obq_size(padap, qid);
 658         rc = cudbg_get_buff(pdbg_init, dbg_buff, qsize, &temp_buff);
 659         if (rc)
 660                 return rc;
 661
 662         /* t4_read_cim_obq will return no. of read words or error */
 663         no_of_read_words = t4_read_cim_obq(padap, qid,
 664                                            (u32 *)temp_buff.data, qsize);
 665         /* no_of_read_words is less than or equal to 0 means error */
 666         if (no_of_read_words <= 0) {
 667                 if (!no_of_read_words)
 668                         rc = CUDBG_SYSTEM_ERROR;
 669                 else
 670                         rc = no_of_read_words;
 671                 cudbg_err->sys_err = rc;
 672                 cudbg_put_buff(pdbg_init, &temp_buff);
 673                 return rc;
 674         }
 675         return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff);
 676 }
 677
 678 int cudbg_collect_cim_obq_ulp0(struct cudbg_init *pdbg_init,
 679                                struct cudbg_buffer *dbg_buff,
 680                                struct cudbg_error *cudbg_err)
 681 {
 682         return cudbg_read_cim_obq(pdbg_init, dbg_buff, cudbg_err, 0);
 683 }
 684
 685 int cudbg_collect_cim_obq_ulp1(struct cudbg_init *pdbg_init,
 686                                struct cudbg_buffer *dbg_buff,
 687                                struct cudbg_error *cudbg_err)
 688 {
 689         return cudbg_read_cim_obq(pdbg_init, dbg_buff, cudbg_err, 1);
 690 }
 691
 692 int cudbg_collect_cim_obq_ulp2(struct cudbg_init *pdbg_init,
 693                                struct cudbg_buffer *dbg_buff,
 694                                struct cudbg_error *cudbg_err)
 695 {
 696         return cudbg_read_cim_obq(pdbg_init, dbg_buff, cudbg_err, 2);
 697 }
 698
 699 int cudbg_collect_cim_obq_ulp3(struct cudbg_init *pdbg_init,
 700                                struct cudbg_buffer *dbg_buff,
 701                                struct cudbg_error *cudbg_err)
 702 {
 703         return cudbg_read_cim_obq(pdbg_init, dbg_buff, cudbg_err, 3);
 704 }
 705
 706 int cudbg_collect_cim_obq_sge(struct cudbg_init *pdbg_init,
 707                               struct cudbg_buffer *dbg_buff,
 708                               struct cudbg_error *cudbg_err)
 709 {
 710         return cudbg_read_cim_obq(pdbg_init, dbg_buff, cudbg_err, 4);
 711 }
 712
 713 int cudbg_collect_cim_obq_ncsi(struct cudbg_init *pdbg_init,
 714                                struct cudbg_buffer *dbg_buff,
 715                                struct cudbg_error *cudbg_err)
 716 {
 717         return cudbg_read_cim_obq(pdbg_init, dbg_buff, cudbg_err, 5);
 718 }
 719
 720 int cudbg_collect_obq_sge_rx_q0(struct cudbg_init *pdbg_init,
 721                                 struct cudbg_buffer *dbg_buff,
 722                                 struct cudbg_error *cudbg_err)
 723 {
 724         return cudbg_read_cim_obq(pdbg_init, dbg_buff, cudbg_err, 6);
 725 }
 726
 727 int cudbg_collect_obq_sge_rx_q1(struct cudbg_init *pdbg_init,
 728                                 struct cudbg_buffer *dbg_buff,
 729                                 struct cudbg_error *cudbg_err)
 730 {
 731         return cudbg_read_cim_obq(pdbg_init, dbg_buff, cudbg_err, 7);
 732 }
 733
 734 static int cudbg_meminfo_get_mem_index(struct adapter *padap,
 735                                        struct cudbg_meminfo *mem_info,
 736                                        u8 mem_type, u8 *idx)
 737 {
 738         u8 i, flag;
 739
 740         switch (mem_type) {
 741         case MEM_EDC0:
 742                 flag = EDC0_FLAG;
 743                 break;
 744         case MEM_EDC1:
 745                 flag = EDC1_FLAG;
 746                 break;
 747         case MEM_MC0:
 748                 /* Some T5 cards have both MC0 and MC1. */
 749                 flag = is_t5(padap->params.chip) ? MC0_FLAG : MC_FLAG;
 750                 break;
 751         case MEM_MC1:
 752                 flag = MC1_FLAG;
 753                 break;
 754         case MEM_HMA:
 755                 flag = HMA_FLAG;
 756                 break;
 757         default:
 758                 return CUDBG_STATUS_ENTITY_NOT_FOUND;
 759         }
 760
 761         for (i = 0; i < mem_info->avail_c; i++) {
 762                 if (mem_info->avail[i].idx == flag) {
 763                         *idx = i;
 764                         return 0;
 765                 }
 766         }
 767
 768         return CUDBG_STATUS_ENTITY_NOT_FOUND;
 769 }
 770
 771 /* Fetch the @region_name's start and end from @meminfo. */
 772 static int cudbg_get_mem_region(struct adapter *padap,
 773                                 struct cudbg_meminfo *meminfo,
 774                                 u8 mem_type, const char *region_name,
 775                                 struct cudbg_mem_desc *mem_desc)
 776 {
 777         u8 mc, found = 0;
 778         u32 i, idx = 0;
 779         int rc;
 780
 781         rc = cudbg_meminfo_get_mem_index(padap, meminfo, mem_type, &mc);
 782         if (rc)
 783                 return rc;
 784
 785         for (i = 0; i < ARRAY_SIZE(cudbg_region); i++) {
 786                 if (!strcmp(cudbg_region[i], region_name)) {
 787                         found = 1;
 788                         idx = i;
 789                         break;
 790                 }
 791         }
 792         if (!found)
 793                 return -EINVAL;
 794
 795         found = 0;
 796         for (i = 0; i < meminfo->mem_c; i++) {
 797                 if (meminfo->mem[i].idx >= ARRAY_SIZE(cudbg_region))
 798                         continue; /* Skip holes */
 799
 800                 if (!(meminfo->mem[i].limit))
 801                         meminfo->mem[i].limit =
 802                                 i < meminfo->mem_c - 1 ?
 803                                 meminfo->mem[i + 1].base - 1 : ~0;
 804
 805                 if (meminfo->mem[i].idx == idx) {
 806                         /* Check if the region exists in @mem_type memory */
 807                         if (meminfo->mem[i].base < meminfo->avail[mc].base &&
 808                             meminfo->mem[i].limit < meminfo->avail[mc].base)
 809                                 return -EINVAL;
 810
 811                         if (meminfo->mem[i].base > meminfo->avail[mc].limit)
 812                                 return -EINVAL;
 813
 814                         memcpy(mem_desc, &meminfo->mem[i],
 815                                sizeof(struct cudbg_mem_desc));
 816                         found = 1;
 817                         break;
 818                 }
 819         }
 820         if (!found)
 821                 return -EINVAL;
 822
 823         return 0;
 824 }
 825
 826 /* Fetch and update the start and end of the requested memory region w.r.t 0
 827  * in the corresponding EDC/MC/HMA.
 828  */
 829 static int cudbg_get_mem_relative(struct adapter *padap,
 830                                   struct cudbg_meminfo *meminfo,
 831                                   u8 mem_type, u32 *out_base, u32 *out_end)
 832 {
 833         u8 mc_idx;
 834         int rc;
 835
 836         rc = cudbg_meminfo_get_mem_index(padap, meminfo, mem_type, &mc_idx);
 837         if (rc)
 838                 return rc;
 839
 840         if (*out_base < meminfo->avail[mc_idx].base)
 841                 *out_base = 0;
 842         else
 843                 *out_base -= meminfo->avail[mc_idx].base;
 844
 845         if (*out_end > meminfo->avail[mc_idx].limit)
 846                 *out_end = meminfo->avail[mc_idx].limit;
 847         else
 848                 *out_end -= meminfo->avail[mc_idx].base;
 849
 850         return 0;
 851 }
 852
 853 /* Get TX and RX Payload region */
 854 static int cudbg_get_payload_range(struct adapter *padap, u8 mem_type,
 855                                    const char *region_name,
 856                                    struct cudbg_region_info *payload)
 857 {
 858         struct cudbg_mem_desc mem_desc = { 0 };
 859         struct cudbg_meminfo meminfo;
 860         int rc;
 861
 862         rc = cudbg_fill_meminfo(padap, &meminfo);
 863         if (rc)
 864                 return rc;
 865
 866         rc = cudbg_get_mem_region(padap, &meminfo, mem_type, region_name,
 867                                   &mem_desc);
 868         if (rc) {
 869                 payload->exist = false;
 870                 return 0;
 871         }
 872
 873         payload->exist = true;
 874         payload->start = mem_desc.base;
 875         payload->end = mem_desc.limit;
 876
 877         return cudbg_get_mem_relative(padap, &meminfo, mem_type,
 878                                       &payload->start, &payload->end);
 879 }
 880
 881 static int cudbg_memory_read(struct cudbg_init *pdbg_init, int win,
 882                              int mtype, u32 addr, u32 len, void *hbuf)
 883 {
 884         u32 win_pf, memoffset, mem_aperture, mem_base;
 885         struct adapter *adap = pdbg_init->adap;
 886         u32 pos, offset, resid;
 887         u32 *res_buf;
 888         u64 *buf;
 889         int ret;
 890
 891         /* Argument sanity checks ...
 892          */
 893         if (addr & 0x3 || (uintptr_t)hbuf & 0x3)
 894                 return -EINVAL;
 895
 896         buf = (u64 *)hbuf;
 897
 898         /* Try to do 64-bit reads.  Residual will be handled later. */
 899         resid = len & 0x7;
 900         len -= resid;
 901
 902         ret = t4_memory_rw_init(adap, win, mtype, &memoffset, &mem_base,
 903                                 &mem_aperture);
 904         if (ret)
 905                 return ret;
 906
 907         addr = addr + memoffset;
 908         win_pf = is_t4(adap->params.chip) ? 0 : PFNUM_V(adap->pf);
 909
 910         pos = addr & ~(mem_aperture - 1);
 911         offset = addr - pos;
 912
 913         /* Set up initial PCI-E Memory Window to cover the start of our
 914          * transfer.
 915          */
 916         t4_memory_update_win(adap, win, pos | win_pf);
 917
 918         /* Transfer data from the adapter */
 919         while (len > 0) {
 920                 *buf++ = le64_to_cpu((__force __le64)
 921                                      t4_read_reg64(adap, mem_base + offset));
 922                 offset += sizeof(u64);
 923                 len -= sizeof(u64);
 924
 925                 /* If we've reached the end of our current window aperture,
 926                  * move the PCI-E Memory Window on to the next.
 927                  */
 928                 if (offset == mem_aperture) {
 929                         pos += mem_aperture;
 930                         offset = 0;
 931                         t4_memory_update_win(adap, win, pos | win_pf);
 932                 }
 933         }
 934
 935         res_buf = (u32 *)buf;
 936         /* Read residual in 32-bit multiples */
 937         while (resid > sizeof(u32)) {
 938                 *res_buf++ = le32_to_cpu((__force __le32)
 939                                          t4_read_reg(adap, mem_base + offset));
 940                 offset += sizeof(u32);
 941                 resid -= sizeof(u32);
 942
 943                 /* If we've reached the end of our current window aperture,
 944                  * move the PCI-E Memory Window on to the next.
 945                  */
 946                 if (offset == mem_aperture) {
 947                         pos += mem_aperture;
 948                         offset = 0;
 949                         t4_memory_update_win(adap, win, pos | win_pf);
 950                 }
 951         }
 952
 953         /* Transfer residual < 32-bits */
 954         if (resid)
 955                 t4_memory_rw_residual(adap, resid, mem_base + offset,
 956                                       (u8 *)res_buf, T4_MEMORY_READ);
 957
 958         return 0;
 959 }
 960
 961 #define CUDBG_YIELD_ITERATION 256
 962
 963 static int cudbg_read_fw_mem(struct cudbg_init *pdbg_init,
 964                              struct cudbg_buffer *dbg_buff, u8 mem_type,
 965                              unsigned long tot_len,
 966                              struct cudbg_error *cudbg_err)
 967 {
 968         static const char * const region_name[] = { "Tx payload:",
 969                                                     "Rx payload:" };
 970         unsigned long bytes, bytes_left, bytes_read = 0;
 971         struct adapter *padap = pdbg_init->adap;
 972         struct cudbg_buffer temp_buff = { 0 };
 973         struct cudbg_region_info payload[2];
 974         u32 yield_count = 0;
 975         int rc = 0;
 976         u8 i;
 977
 978         /* Get TX/RX Payload region range if they exist */
 979         memset(payload, 0, sizeof(payload));
 980         for (i = 0; i < ARRAY_SIZE(region_name); i++) {
 981                 rc = cudbg_get_payload_range(padap, mem_type, region_name[i],
 982                                              &payload[i]);
 983                 if (rc)
 984                         return rc;
 985
 986                 if (payload[i].exist) {
 987                         /* Align start and end to avoid wrap around */
 988                         payload[i].start = roundup(payload[i].start,
 989                                                    CUDBG_CHUNK_SIZE);
 990                         payload[i].end = rounddown(payload[i].end,
 991                                                    CUDBG_CHUNK_SIZE);
 992                 }
 993         }
 994
 995         bytes_left = tot_len;
 996         while (bytes_left > 0) {
 997                 /* As MC size is huge and read through PIO access, this
 998                  * loop will hold cpu for a longer time. OS may think that
 999                  * the process is hanged and will generate CPU stall traces.
1000                  * So yield the cpu regularly.
1001                  */
1002                 yield_count++;
1003                 if (!(yield_count % CUDBG_YIELD_ITERATION))
1004                         schedule();
1005
1006                 bytes = min_t(unsigned long, bytes_left,
1007                               (unsigned long)CUDBG_CHUNK_SIZE);
1008                 rc = cudbg_get_buff(pdbg_init, dbg_buff, bytes, &temp_buff);
1009                 if (rc)
1010                         return rc;
1011
1012                 for (i = 0; i < ARRAY_SIZE(payload); i++)
1013                         if (payload[i].exist &&
1014                             bytes_read >= payload[i].start &&
1015                             bytes_read + bytes <= payload[i].end)
1016                                 /* TX and RX Payload regions can't overlap */
1017                                 goto skip_read;
1018
1019                 spin_lock(&padap->win0_lock);
1020                 rc = cudbg_memory_read(pdbg_init, MEMWIN_NIC, mem_type,
1021                                        bytes_read, bytes, temp_buff.data);
1022                 spin_unlock(&padap->win0_lock);
1023                 if (rc) {
1024                         cudbg_err->sys_err = rc;
1025                         cudbg_put_buff(pdbg_init, &temp_buff);
1026                         return rc;
1027                 }
1028
1029 skip_read:
1030                 bytes_left -= bytes;
1031                 bytes_read += bytes;
1032                 rc = cudbg_write_and_release_buff(pdbg_init, &temp_buff,
1033                                                   dbg_buff);
1034                 if (rc) {
1035                         cudbg_put_buff(pdbg_init, &temp_buff);
1036                         return rc;
1037                 }
1038         }
1039         return rc;
1040 }
1041
1042 static void cudbg_t4_fwcache(struct cudbg_init *pdbg_init,
1043                              struct cudbg_error *cudbg_err)
1044 {
1045         struct adapter *padap = pdbg_init->adap;
1046         int rc;
1047
1048         if (is_fw_attached(pdbg_init)) {
1049                 /* Flush uP dcache before reading edcX/mcX  */
1050                 rc = t4_fwcache(padap, FW_PARAM_DEV_FWCACHE_FLUSH);
1051                 if (rc)
1052                         cudbg_err->sys_warn = rc;
1053         }
1054 }
1055
1056 static int cudbg_collect_mem_region(struct cudbg_init *pdbg_init,
1057                                     struct cudbg_buffer *dbg_buff,
1058                                     struct cudbg_error *cudbg_err,
1059                                     u8 mem_type)
1060 {
1061         struct adapter *padap = pdbg_init->adap;
1062         struct cudbg_meminfo mem_info;
1063         unsigned long size;
1064         u8 mc_idx;
1065         int rc;
1066
1067         memset(&mem_info, 0, sizeof(struct cudbg_meminfo));
1068         rc = cudbg_fill_meminfo(padap, &mem_info);
1069         if (rc)
1070                 return rc;
1071
1072         cudbg_t4_fwcache(pdbg_init, cudbg_err);
1073         rc = cudbg_meminfo_get_mem_index(padap, &mem_info, mem_type, &mc_idx);
1074         if (rc)
1075                 return rc;
1076
1077         size = mem_info.avail[mc_idx].limit - mem_info.avail[mc_idx].base;
1078         return cudbg_read_fw_mem(pdbg_init, dbg_buff, mem_type, size,
1079                                  cudbg_err);
1080 }
1081
1082 int cudbg_collect_edc0_meminfo(struct cudbg_init *pdbg_init,
1083                                struct cudbg_buffer *dbg_buff,
1084                                struct cudbg_error *cudbg_err)
1085 {
1086         return cudbg_collect_mem_region(pdbg_init, dbg_buff, cudbg_err,
1087                                         MEM_EDC0);
1088 }
1089
1090 int cudbg_collect_edc1_meminfo(struct cudbg_init *pdbg_init,
1091                                struct cudbg_buffer *dbg_buff,
1092                                struct cudbg_error *cudbg_err)
1093 {
1094         return cudbg_collect_mem_region(pdbg_init, dbg_buff, cudbg_err,
1095                                         MEM_EDC1);
1096 }
1097
1098 int cudbg_collect_mc0_meminfo(struct cudbg_init *pdbg_init,
1099                               struct cudbg_buffer *dbg_buff,
1100                               struct cudbg_error *cudbg_err)
1101 {
1102         return cudbg_collect_mem_region(pdbg_init, dbg_buff, cudbg_err,
1103                                         MEM_MC0);
1104 }
1105
1106 int cudbg_collect_mc1_meminfo(struct cudbg_init *pdbg_init,
1107                               struct cudbg_buffer *dbg_buff,
1108                               struct cudbg_error *cudbg_err)
1109 {
1110         return cudbg_collect_mem_region(pdbg_init, dbg_buff, cudbg_err,
1111                                         MEM_MC1);
1112 }
1113
1114 int cudbg_collect_hma_meminfo(struct cudbg_init *pdbg_init,
1115                               struct cudbg_buffer *dbg_buff,
1116                               struct cudbg_error *cudbg_err)
1117 {
1118         return cudbg_collect_mem_region(pdbg_init, dbg_buff, cudbg_err,
1119                                         MEM_HMA);
1120 }
1121
1122 int cudbg_collect_rss(struct cudbg_init *pdbg_init,
1123                       struct cudbg_buffer *dbg_buff,
1124                       struct cudbg_error *cudbg_err)
1125 {
1126         struct adapter *padap = pdbg_init->adap;
1127         struct cudbg_buffer temp_buff = { 0 };
1128         int rc, nentries;
1129
1130         nentries = t4_chip_rss_size(padap);
1131         rc = cudbg_get_buff(pdbg_init, dbg_buff, nentries * sizeof(u16),
1132                             &temp_buff);
1133         if (rc)
1134                 return rc;
1135
1136         rc = t4_read_rss(padap, (u16 *)temp_buff.data);
1137         if (rc) {
1138                 cudbg_err->sys_err = rc;
1139                 cudbg_put_buff(pdbg_init, &temp_buff);
1140                 return rc;
1141         }
1142         return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff);
1143 }
1144
1145 int cudbg_collect_rss_vf_config(struct cudbg_init *pdbg_init,
1146                                 struct cudbg_buffer *dbg_buff,
1147                                 struct cudbg_error *cudbg_err)
1148 {
1149         struct adapter *padap = pdbg_init->adap;
1150         struct cudbg_buffer temp_buff = { 0 };
1151         struct cudbg_rss_vf_conf *vfconf;
1152         int vf, rc, vf_count;
1153
1154         vf_count = padap->params.arch.vfcount;
1155         rc = cudbg_get_buff(pdbg_init, dbg_buff,
1156                             vf_count * sizeof(struct cudbg_rss_vf_conf),
1157                             &temp_buff);
1158         if (rc)
1159                 return rc;
1160
1161         vfconf = (struct cudbg_rss_vf_conf *)temp_buff.data;
1162         for (vf = 0; vf < vf_count; vf++)
1163                 t4_read_rss_vf_config(padap, vf, &vfconf[vf].rss_vf_vfl,
1164                                       &vfconf[vf].rss_vf_vfh, true);
1165         return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff);
1166 }
1167
1168 int cudbg_collect_path_mtu(struct cudbg_init *pdbg_init,
1169                            struct cudbg_buffer *dbg_buff,
1170                            struct cudbg_error *cudbg_err)
1171 {
1172         struct adapter *padap = pdbg_init->adap;
1173         struct cudbg_buffer temp_buff = { 0 };
1174         int rc;
1175
1176         rc = cudbg_get_buff(pdbg_init, dbg_buff, NMTUS * sizeof(u16),
1177                             &temp_buff);
1178         if (rc)
1179                 return rc;
1180
1181         t4_read_mtu_tbl(padap, (u16 *)temp_buff.data, NULL);
1182         return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff);
1183 }
1184
1185 int cudbg_collect_pm_stats(struct cudbg_init *pdbg_init,
1186                            struct cudbg_buffer *dbg_buff,
1187                            struct cudbg_error *cudbg_err)
1188 {
1189         struct adapter *padap = pdbg_init->adap;
1190         struct cudbg_buffer temp_buff = { 0 };
1191         struct cudbg_pm_stats *pm_stats_buff;
1192         int rc;
1193
1194         rc = cudbg_get_buff(pdbg_init, dbg_buff, sizeof(struct cudbg_pm_stats),
1195                             &temp_buff);
1196         if (rc)
1197                 return rc;
1198
1199         pm_stats_buff = (struct cudbg_pm_stats *)temp_buff.data;
1200         t4_pmtx_get_stats(padap, pm_stats_buff->tx_cnt, pm_stats_buff->tx_cyc);
1201         t4_pmrx_get_stats(padap, pm_stats_buff->rx_cnt, pm_stats_buff->rx_cyc);
1202         return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff);
1203 }
1204
1205 int cudbg_collect_hw_sched(struct cudbg_init *pdbg_init,
1206                            struct cudbg_buffer *dbg_buff,
1207                            struct cudbg_error *cudbg_err)
1208 {
1209         struct adapter *padap = pdbg_init->adap;
1210         struct cudbg_buffer temp_buff = { 0 };
1211         struct cudbg_hw_sched *hw_sched_buff;
1212         int i, rc = 0;
1213
1214         if (!padap->params.vpd.cclk)
1215                 return CUDBG_STATUS_CCLK_NOT_DEFINED;
1216
1217         rc = cudbg_get_buff(pdbg_init, dbg_buff, sizeof(struct cudbg_hw_sched),
1218                             &temp_buff);
1219         hw_sched_buff = (struct cudbg_hw_sched *)temp_buff.data;
1220         hw_sched_buff->map = t4_read_reg(padap, TP_TX_MOD_QUEUE_REQ_MAP_A);
1221         hw_sched_buff->mode = TIMERMODE_G(t4_read_reg(padap, TP_MOD_CONFIG_A));
1222         t4_read_pace_tbl(padap, hw_sched_buff->pace_tab);
1223         for (i = 0; i < NTX_SCHED; ++i)
1224                 t4_get_tx_sched(padap, i, &hw_sched_buff->kbps[i],
1225                                 &hw_sched_buff->ipg[i], true);
1226         return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff);
1227 }
1228
1229 int cudbg_collect_tp_indirect(struct cudbg_init *pdbg_init,
1230                               struct cudbg_buffer *dbg_buff,
1231                               struct cudbg_error *cudbg_err)
1232 {
1233         struct adapter *padap = pdbg_init->adap;
1234         struct cudbg_buffer temp_buff = { 0 };
1235         struct ireg_buf *ch_tp_pio;
1236         int i, rc, n = 0;
1237         u32 size;
1238
1239         if (is_t5(padap->params.chip))
1240                 n = sizeof(t5_tp_pio_array) +
1241                     sizeof(t5_tp_tm_pio_array) +
1242                     sizeof(t5_tp_mib_index_array);
1243         else
1244                 n = sizeof(t6_tp_pio_array) +
1245                     sizeof(t6_tp_tm_pio_array) +
1246                     sizeof(t6_tp_mib_index_array);
1247
1248         n = n / (IREG_NUM_ELEM * sizeof(u32));
1249         size = sizeof(struct ireg_buf) * n;
1250         rc = cudbg_get_buff(pdbg_init, dbg_buff, size, &temp_buff);
1251         if (rc)
1252                 return rc;
1253
1254         ch_tp_pio = (struct ireg_buf *)temp_buff.data;
1255
1256         /* TP_PIO */
1257         if (is_t5(padap->params.chip))
1258                 n = sizeof(t5_tp_pio_array) / (IREG_NUM_ELEM * sizeof(u32));
1259         else if (is_t6(padap->params.chip))
1260                 n = sizeof(t6_tp_pio_array) / (IREG_NUM_ELEM * sizeof(u32));
1261
1262         for (i = 0; i < n; i++) {
1263                 struct ireg_field *tp_pio = &ch_tp_pio->tp_pio;
1264                 u32 *buff = ch_tp_pio->outbuf;
1265
1266                 if (is_t5(padap->params.chip)) {
1267                         tp_pio->ireg_addr = t5_tp_pio_array[i][0];
1268                         tp_pio->ireg_data = t5_tp_pio_array[i][1];
1269                         tp_pio->ireg_local_offset = t5_tp_pio_array[i][2];
1270                         tp_pio->ireg_offset_range = t5_tp_pio_array[i][3];
1271                 } else if (is_t6(padap->params.chip)) {
1272                         tp_pio->ireg_addr = t6_tp_pio_array[i][0];
1273                         tp_pio->ireg_data = t6_tp_pio_array[i][1];
1274                         tp_pio->ireg_local_offset = t6_tp_pio_array[i][2];
1275                         tp_pio->ireg_offset_range = t6_tp_pio_array[i][3];
1276                 }
1277                 t4_tp_pio_read(padap, buff, tp_pio->ireg_offset_range,
1278                                tp_pio->ireg_local_offset, true);
1279                 ch_tp_pio++;
1280         }
1281
1282         /* TP_TM_PIO */
1283         if (is_t5(padap->params.chip))
1284                 n = sizeof(t5_tp_tm_pio_array) / (IREG_NUM_ELEM * sizeof(u32));
1285         else if (is_t6(padap->params.chip))
1286                 n = sizeof(t6_tp_tm_pio_array) / (IREG_NUM_ELEM * sizeof(u32));
1287
1288         for (i = 0; i < n; i++) {
1289                 struct ireg_field *tp_pio = &ch_tp_pio->tp_pio;
1290                 u32 *buff = ch_tp_pio->outbuf;
1291
1292                 if (is_t5(padap->params.chip)) {
1293                         tp_pio->ireg_addr = t5_tp_tm_pio_array[i][0];
1294                         tp_pio->ireg_data = t5_tp_tm_pio_array[i][1];
1295                         tp_pio->ireg_local_offset = t5_tp_tm_pio_array[i][2];
1296                         tp_pio->ireg_offset_range = t5_tp_tm_pio_array[i][3];
1297                 } else if (is_t6(padap->params.chip)) {
1298                         tp_pio->ireg_addr = t6_tp_tm_pio_array[i][0];
1299                         tp_pio->ireg_data = t6_tp_tm_pio_array[i][1];
1300                         tp_pio->ireg_local_offset = t6_tp_tm_pio_array[i][2];
1301                         tp_pio->ireg_offset_range = t6_tp_tm_pio_array[i][3];
1302                 }
1303                 t4_tp_tm_pio_read(padap, buff, tp_pio->ireg_offset_range,
1304                                   tp_pio->ireg_local_offset, true);
1305                 ch_tp_pio++;
1306         }
1307
1308         /* TP_MIB_INDEX */
1309         if (is_t5(padap->params.chip))
1310                 n = sizeof(t5_tp_mib_index_array) /
1311                     (IREG_NUM_ELEM * sizeof(u32));
1312         else if (is_t6(padap->params.chip))
1313                 n = sizeof(t6_tp_mib_index_array) /
1314                     (IREG_NUM_ELEM * sizeof(u32));
1315
1316         for (i = 0; i < n ; i++) {
1317                 struct ireg_field *tp_pio = &ch_tp_pio->tp_pio;
1318                 u32 *buff = ch_tp_pio->outbuf;
1319
1320                 if (is_t5(padap->params.chip)) {
1321                         tp_pio->ireg_addr = t5_tp_mib_index_array[i][0];
1322                         tp_pio->ireg_data = t5_tp_mib_index_array[i][1];
1323                         tp_pio->ireg_local_offset =
1324                                 t5_tp_mib_index_array[i][2];
1325                         tp_pio->ireg_offset_range =
1326                                 t5_tp_mib_index_array[i][3];
1327                 } else if (is_t6(padap->params.chip)) {
1328                         tp_pio->ireg_addr = t6_tp_mib_index_array[i][0];
1329                         tp_pio->ireg_data = t6_tp_mib_index_array[i][1];
1330                         tp_pio->ireg_local_offset =
1331                                 t6_tp_mib_index_array[i][2];
1332                         tp_pio->ireg_offset_range =
1333                                 t6_tp_mib_index_array[i][3];
1334                 }
1335                 t4_tp_mib_read(padap, buff, tp_pio->ireg_offset_range,
1336                                tp_pio->ireg_local_offset, true);
1337                 ch_tp_pio++;
1338         }
1339         return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff);
1340 }
1341
1342 int cudbg_collect_sge_indirect(struct cudbg_init *pdbg_init,
1343                                struct cudbg_buffer *dbg_buff,
1344                                struct cudbg_error *cudbg_err)
1345 {
1346         struct adapter *padap = pdbg_init->adap;
1347         struct cudbg_buffer temp_buff = { 0 };
1348         struct ireg_buf *ch_sge_dbg;
1349         int i, rc;
1350
1351         rc = cudbg_get_buff(pdbg_init, dbg_buff, sizeof(*ch_sge_dbg) * 2,
1352                             &temp_buff);
1353         if (rc)
1354                 return rc;
1355
1356         ch_sge_dbg = (struct ireg_buf *)temp_buff.data;
1357         for (i = 0; i < 2; i++) {
1358                 struct ireg_field *sge_pio = &ch_sge_dbg->tp_pio;
1359                 u32 *buff = ch_sge_dbg->outbuf;
1360
1361                 sge_pio->ireg_addr = t5_sge_dbg_index_array[i][0];
1362                 sge_pio->ireg_data = t5_sge_dbg_index_array[i][1];
1363                 sge_pio->ireg_local_offset = t5_sge_dbg_index_array[i][2];
1364                 sge_pio->ireg_offset_range = t5_sge_dbg_index_array[i][3];
1365                 t4_read_indirect(padap,
1366                                  sge_pio->ireg_addr,
1367                                  sge_pio->ireg_data,
1368                                  buff,
1369                                  sge_pio->ireg_offset_range,
1370                                  sge_pio->ireg_local_offset);
1371                 ch_sge_dbg++;
1372         }
1373         return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff);
1374 }
1375
1376 int cudbg_collect_ulprx_la(struct cudbg_init *pdbg_init,
1377                            struct cudbg_buffer *dbg_buff,
1378                            struct cudbg_error *cudbg_err)
1379 {
1380         struct adapter *padap = pdbg_init->adap;
1381         struct cudbg_buffer temp_buff = { 0 };
1382         struct cudbg_ulprx_la *ulprx_la_buff;
1383         int rc;
1384
1385         rc = cudbg_get_buff(pdbg_init, dbg_buff, sizeof(struct cudbg_ulprx_la),
1386                             &temp_buff);
1387         if (rc)
1388                 return rc;
1389
1390         ulprx_la_buff = (struct cudbg_ulprx_la *)temp_buff.data;
1391         t4_ulprx_read_la(padap, (u32 *)ulprx_la_buff->data);
1392         ulprx_la_buff->size = ULPRX_LA_SIZE;
1393         return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff);
1394 }
1395
1396 int cudbg_collect_tp_la(struct cudbg_init *pdbg_init,
1397                         struct cudbg_buffer *dbg_buff,
1398                         struct cudbg_error *cudbg_err)
1399 {
1400         struct adapter *padap = pdbg_init->adap;
1401         struct cudbg_buffer temp_buff = { 0 };
1402         struct cudbg_tp_la *tp_la_buff;
1403         int size, rc;
1404
1405         size = sizeof(struct cudbg_tp_la) + TPLA_SIZE *  sizeof(u64);
1406         rc = cudbg_get_buff(pdbg_init, dbg_buff, size, &temp_buff);
1407         if (rc)
1408                 return rc;
1409
1410         tp_la_buff = (struct cudbg_tp_la *)temp_buff.data;
1411         tp_la_buff->mode = DBGLAMODE_G(t4_read_reg(padap, TP_DBG_LA_CONFIG_A));
1412         t4_tp_read_la(padap, (u64 *)tp_la_buff->data, NULL);
1413         return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff);
1414 }
1415
1416 int cudbg_collect_meminfo(struct cudbg_init *pdbg_init,
1417                           struct cudbg_buffer *dbg_buff,
1418                           struct cudbg_error *cudbg_err)
1419 {
1420         struct adapter *padap = pdbg_init->adap;
1421         struct cudbg_buffer temp_buff = { 0 };
1422         struct cudbg_meminfo *meminfo_buff;
1423         int rc;
1424
1425         rc = cudbg_get_buff(pdbg_init, dbg_buff, sizeof(struct cudbg_meminfo),
1426                             &temp_buff);
1427         if (rc)
1428                 return rc;
1429
1430         meminfo_buff = (struct cudbg_meminfo *)temp_buff.data;
1431         rc = cudbg_fill_meminfo(padap, meminfo_buff);
1432         if (rc) {
1433                 cudbg_err->sys_err = rc;
1434                 cudbg_put_buff(pdbg_init, &temp_buff);
1435                 return rc;
1436         }
1437
1438         return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff);
1439 }
1440
1441 int cudbg_collect_cim_pif_la(struct cudbg_init *pdbg_init,
1442                              struct cudbg_buffer *dbg_buff,
1443                              struct cudbg_error *cudbg_err)
1444 {
1445         struct cudbg_cim_pif_la *cim_pif_la_buff;
1446         struct adapter *padap = pdbg_init->adap;
1447         struct cudbg_buffer temp_buff = { 0 };
1448         int size, rc;
1449
1450         size = sizeof(struct cudbg_cim_pif_la) +
1451                2 * CIM_PIFLA_SIZE * 6 * sizeof(u32);
1452         rc = cudbg_get_buff(pdbg_init, dbg_buff, size, &temp_buff);
1453         if (rc)
1454                 return rc;
1455
1456         cim_pif_la_buff = (struct cudbg_cim_pif_la *)temp_buff.data;
1457         cim_pif_la_buff->size = CIM_PIFLA_SIZE;
1458         t4_cim_read_pif_la(padap, (u32 *)cim_pif_la_buff->data,
1459                            (u32 *)cim_pif_la_buff->data + 6 * CIM_PIFLA_SIZE,
1460                            NULL, NULL);
1461         return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff);
1462 }
1463
1464 int cudbg_collect_clk_info(struct cudbg_init *pdbg_init,
1465                            struct cudbg_buffer *dbg_buff,
1466                            struct cudbg_error *cudbg_err)
1467 {
1468         struct adapter *padap = pdbg_init->adap;
1469         struct cudbg_buffer temp_buff = { 0 };
1470         struct cudbg_clk_info *clk_info_buff;
1471         u64 tp_tick_us;
1472         int rc;
1473
1474         if (!padap->params.vpd.cclk)
1475                 return CUDBG_STATUS_CCLK_NOT_DEFINED;
1476
1477         rc = cudbg_get_buff(pdbg_init, dbg_buff, sizeof(struct cudbg_clk_info),
1478                             &temp_buff);
1479         if (rc)
1480                 return rc;
1481
1482         clk_info_buff = (struct cudbg_clk_info *)temp_buff.data;
1483         clk_info_buff->cclk_ps = 1000000000 / padap->params.vpd.cclk; /* psec */
1484         clk_info_buff->res = t4_read_reg(padap, TP_TIMER_RESOLUTION_A);
1485         clk_info_buff->tre = TIMERRESOLUTION_G(clk_info_buff->res);
1486         clk_info_buff->dack_re = DELAYEDACKRESOLUTION_G(clk_info_buff->res);
1487         tp_tick_us = (clk_info_buff->cclk_ps << clk_info_buff->tre) / 1000000;
1488
1489         clk_info_buff->dack_timer =
1490                 (clk_info_buff->cclk_ps << clk_info_buff->dack_re) / 1000000 *
1491                 t4_read_reg(padap, TP_DACK_TIMER_A);
1492         clk_info_buff->retransmit_min =
1493                 tp_tick_us * t4_read_reg(padap, TP_RXT_MIN_A);
1494         clk_info_buff->retransmit_max =
1495                 tp_tick_us * t4_read_reg(padap, TP_RXT_MAX_A);
1496         clk_info_buff->persist_timer_min =
1497                 tp_tick_us * t4_read_reg(padap, TP_PERS_MIN_A);
1498         clk_info_buff->persist_timer_max =
1499                 tp_tick_us * t4_read_reg(padap, TP_PERS_MAX_A);
1500         clk_info_buff->keepalive_idle_timer =
1501                 tp_tick_us * t4_read_reg(padap, TP_KEEP_IDLE_A);
1502         clk_info_buff->keepalive_interval =
1503                 tp_tick_us * t4_read_reg(padap, TP_KEEP_INTVL_A);
1504         clk_info_buff->initial_srtt =
1505                 tp_tick_us * INITSRTT_G(t4_read_reg(padap, TP_INIT_SRTT_A));
1506         clk_info_buff->finwait2_timer =
1507                 tp_tick_us * t4_read_reg(padap, TP_FINWAIT2_TIMER_A);
1508
1509         return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff);
1510 }
1511
1512 int cudbg_collect_pcie_indirect(struct cudbg_init *pdbg_init,
1513                                 struct cudbg_buffer *dbg_buff,
1514                                 struct cudbg_error *cudbg_err)
1515 {
1516         struct adapter *padap = pdbg_init->adap;
1517         struct cudbg_buffer temp_buff = { 0 };
1518         struct ireg_buf *ch_pcie;
1519         int i, rc, n;
1520         u32 size;
1521
1522         n = sizeof(t5_pcie_pdbg_array) / (IREG_NUM_ELEM * sizeof(u32));
1523         size = sizeof(struct ireg_buf) * n * 2;
1524         rc = cudbg_get_buff(pdbg_init, dbg_buff, size, &temp_buff);
1525         if (rc)
1526                 return rc;
1527
1528         ch_pcie = (struct ireg_buf *)temp_buff.data;
1529         /* PCIE_PDBG */
1530         for (i = 0; i < n; i++) {
1531                 struct ireg_field *pcie_pio = &ch_pcie->tp_pio;
1532                 u32 *buff = ch_pcie->outbuf;
1533
1534                 pcie_pio->ireg_addr = t5_pcie_pdbg_array[i][0];
1535                 pcie_pio->ireg_data = t5_pcie_pdbg_array[i][1];
1536                 pcie_pio->ireg_local_offset = t5_pcie_pdbg_array[i][2];
1537                 pcie_pio->ireg_offset_range = t5_pcie_pdbg_array[i][3];
1538                 t4_read_indirect(padap,
1539                                  pcie_pio->ireg_addr,
1540                                  pcie_pio->ireg_data,
1541                                  buff,
1542                                  pcie_pio->ireg_offset_range,
1543                                  pcie_pio->ireg_local_offset);
1544                 ch_pcie++;
1545         }
1546
1547         /* PCIE_CDBG */
1548         n = sizeof(t5_pcie_cdbg_array) / (IREG_NUM_ELEM * sizeof(u32));
1549         for (i = 0; i < n; i++) {
1550                 struct ireg_field *pcie_pio = &ch_pcie->tp_pio;
1551                 u32 *buff = ch_pcie->outbuf;
1552
1553                 pcie_pio->ireg_addr = t5_pcie_cdbg_array[i][0];
1554                 pcie_pio->ireg_data = t5_pcie_cdbg_array[i][1];
1555                 pcie_pio->ireg_local_offset = t5_pcie_cdbg_array[i][2];
1556                 pcie_pio->ireg_offset_range = t5_pcie_cdbg_array[i][3];
1557                 t4_read_indirect(padap,
1558                                  pcie_pio->ireg_addr,
1559                                  pcie_pio->ireg_data,
1560                                  buff,
1561                                  pcie_pio->ireg_offset_range,
1562                                  pcie_pio->ireg_local_offset);
1563                 ch_pcie++;
1564         }
1565         return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff);
1566 }
1567
1568 int cudbg_collect_pm_indirect(struct cudbg_init *pdbg_init,
1569                               struct cudbg_buffer *dbg_buff,
1570                               struct cudbg_error *cudbg_err)
1571 {
1572         struct adapter *padap = pdbg_init->adap;
1573         struct cudbg_buffer temp_buff = { 0 };
1574         struct ireg_buf *ch_pm;
1575         int i, rc, n;
1576         u32 size;
1577
1578         n = sizeof(t5_pm_rx_array) / (IREG_NUM_ELEM * sizeof(u32));
1579         size = sizeof(struct ireg_buf) * n * 2;
1580         rc = cudbg_get_buff(pdbg_init, dbg_buff, size, &temp_buff);
1581         if (rc)
1582                 return rc;
1583
1584         ch_pm = (struct ireg_buf *)temp_buff.data;
1585         /* PM_RX */
1586         for (i = 0; i < n; i++) {
1587                 struct ireg_field *pm_pio = &ch_pm->tp_pio;
1588                 u32 *buff = ch_pm->outbuf;
1589
1590                 pm_pio->ireg_addr = t5_pm_rx_array[i][0];
1591                 pm_pio->ireg_data = t5_pm_rx_array[i][1];
1592                 pm_pio->ireg_local_offset = t5_pm_rx_array[i][2];
1593                 pm_pio->ireg_offset_range = t5_pm_rx_array[i][3];
1594                 t4_read_indirect(padap,
1595                                  pm_pio->ireg_addr,
1596                                  pm_pio->ireg_data,
1597                                  buff,
1598                                  pm_pio->ireg_offset_range,
1599                                  pm_pio->ireg_local_offset);
1600                 ch_pm++;
1601         }
1602
1603         /* PM_TX */
1604         n = sizeof(t5_pm_tx_array) / (IREG_NUM_ELEM * sizeof(u32));
1605         for (i = 0; i < n; i++) {
1606                 struct ireg_field *pm_pio = &ch_pm->tp_pio;
1607                 u32 *buff = ch_pm->outbuf;
1608
1609                 pm_pio->ireg_addr = t5_pm_tx_array[i][0];
1610                 pm_pio->ireg_data = t5_pm_tx_array[i][1];
1611                 pm_pio->ireg_local_offset = t5_pm_tx_array[i][2];
1612                 pm_pio->ireg_offset_range = t5_pm_tx_array[i][3];
1613                 t4_read_indirect(padap,
1614                                  pm_pio->ireg_addr,
1615                                  pm_pio->ireg_data,
1616                                  buff,
1617                                  pm_pio->ireg_offset_range,
1618                                  pm_pio->ireg_local_offset);
1619                 ch_pm++;
1620         }
1621         return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff);
1622 }
1623
1624 int cudbg_collect_tid(struct cudbg_init *pdbg_init,
1625                       struct cudbg_buffer *dbg_buff,
1626                       struct cudbg_error *cudbg_err)
1627 {
1628         struct adapter *padap = pdbg_init->adap;
1629         struct cudbg_tid_info_region_rev1 *tid1;
1630         struct cudbg_buffer temp_buff = { 0 };
1631         struct cudbg_tid_info_region *tid;
1632         u32 para[2], val[2];
1633         int rc;
1634
1635         rc = cudbg_get_buff(pdbg_init, dbg_buff,
1636                             sizeof(struct cudbg_tid_info_region_rev1),
1637                             &temp_buff);
1638         if (rc)
1639                 return rc;
1640
1641         tid1 = (struct cudbg_tid_info_region_rev1 *)temp_buff.data;
1642         tid = &tid1->tid;
1643         tid1->ver_hdr.signature = CUDBG_ENTITY_SIGNATURE;
1644         tid1->ver_hdr.revision = CUDBG_TID_INFO_REV;
1645         tid1->ver_hdr.size = sizeof(struct cudbg_tid_info_region_rev1) -
1646                              sizeof(struct cudbg_ver_hdr);
1647
1648         /* If firmware is not attached/alive, use backdoor register
1649          * access to collect dump.
1650          */
1651         if (!is_fw_attached(pdbg_init))
1652                 goto fill_tid;
1653
1654 #define FW_PARAM_PFVF_A(param) \
1655         (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_PFVF) | \
1656          FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_PFVF_##param) | \
1657          FW_PARAMS_PARAM_Y_V(0) | \
1658          FW_PARAMS_PARAM_Z_V(0))
1659
1660         para[0] = FW_PARAM_PFVF_A(ETHOFLD_START);
1661         para[1] = FW_PARAM_PFVF_A(ETHOFLD_END);
1662         rc = t4_query_params(padap, padap->mbox, padap->pf, 0, 2, para, val);
1663         if (rc <  0) {
1664                 cudbg_err->sys_err = rc;
1665                 cudbg_put_buff(pdbg_init, &temp_buff);
1666                 return rc;
1667         }
1668         tid->uotid_base = val[0];
1669         tid->nuotids = val[1] - val[0] + 1;
1670
1671         if (is_t5(padap->params.chip)) {
1672                 tid->sb = t4_read_reg(padap, LE_DB_SERVER_INDEX_A) / 4;
1673         } else if (is_t6(padap->params.chip)) {
1674                 tid1->tid_start =
1675                         t4_read_reg(padap, LE_DB_ACTIVE_TABLE_START_INDEX_A);
1676                 tid->sb = t4_read_reg(padap, LE_DB_SRVR_START_INDEX_A);
1677
1678                 para[0] = FW_PARAM_PFVF_A(HPFILTER_START);
1679                 para[1] = FW_PARAM_PFVF_A(HPFILTER_END);
1680                 rc = t4_query_params(padap, padap->mbox, padap->pf, 0, 2,
1681                                      para, val);
1682                 if (rc < 0) {
1683                         cudbg_err->sys_err = rc;
1684                         cudbg_put_buff(pdbg_init, &temp_buff);
1685                         return rc;
1686                 }
1687                 tid->hpftid_base = val[0];
1688                 tid->nhpftids = val[1] - val[0] + 1;
1689         }
1690
1691 #undef FW_PARAM_PFVF_A
1692
1693 fill_tid:
1694         tid->ntids = padap->tids.ntids;
1695         tid->nstids = padap->tids.nstids;
1696         tid->stid_base = padap->tids.stid_base;
1697         tid->hash_base = padap->tids.hash_base;
1698
1699         tid->natids = padap->tids.natids;
1700         tid->nftids = padap->tids.nftids;
1701         tid->ftid_base = padap->tids.ftid_base;
1702         tid->aftid_base = padap->tids.aftid_base;
1703         tid->aftid_end = padap->tids.aftid_end;
1704
1705         tid->sftid_base = padap->tids.sftid_base;
1706         tid->nsftids = padap->tids.nsftids;
1707
1708         tid->flags = padap->flags;
1709         tid->le_db_conf = t4_read_reg(padap, LE_DB_CONFIG_A);
1710         tid->ip_users = t4_read_reg(padap, LE_DB_ACT_CNT_IPV4_A);
1711         tid->ipv6_users = t4_read_reg(padap, LE_DB_ACT_CNT_IPV6_A);
1712
1713         return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff);
1714 }
1715
1716 int cudbg_collect_pcie_config(struct cudbg_init *pdbg_init,
1717                               struct cudbg_buffer *dbg_buff,
1718                               struct cudbg_error *cudbg_err)
1719 {
1720         struct adapter *padap = pdbg_init->adap;
1721         struct cudbg_buffer temp_buff = { 0 };
1722         u32 size, *value, j;
1723         int i, rc, n;
1724
1725         size = sizeof(u32) * CUDBG_NUM_PCIE_CONFIG_REGS;
1726         n = sizeof(t5_pcie_config_array) / (2 * sizeof(u32));
1727         rc = cudbg_get_buff(pdbg_init, dbg_buff, size, &temp_buff);
1728         if (rc)
1729                 return rc;
1730
1731         value = (u32 *)temp_buff.data;
1732         for (i = 0; i < n; i++) {
1733                 for (j = t5_pcie_config_array[i][0];
1734                      j <= t5_pcie_config_array[i][1]; j += 4) {
1735                         t4_hw_pci_read_cfg4(padap, j, value);
1736                         value++;
1737                 }
1738         }
1739         return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff);
1740 }
1741
1742 static int cudbg_sge_ctxt_check_valid(u32 *buf, int type)
1743 {
1744         int index, bit, bit_pos = 0;
1745
1746         switch (type) {
1747         case CTXT_EGRESS:
1748                 bit_pos = 176;
1749                 break;
1750         case CTXT_INGRESS:
1751                 bit_pos = 141;
1752                 break;
1753         case CTXT_FLM:
1754                 bit_pos = 89;
1755                 break;
1756         }
1757         index = bit_pos / 32;
1758         bit =  bit_pos % 32;
1759         return buf[index] & (1U << bit);
1760 }
1761
1762 static int cudbg_get_ctxt_region_info(struct adapter *padap,
1763                                       struct cudbg_region_info *ctx_info,
1764                                       u8 *mem_type)
1765 {
1766         struct cudbg_mem_desc mem_desc;
1767         struct cudbg_meminfo meminfo;
1768         u32 i, j, value, found;
1769         u8 flq;
1770         int rc;
1771
1772         rc = cudbg_fill_meminfo(padap, &meminfo);
1773         if (rc)
1774                 return rc;
1775
1776         /* Get EGRESS and INGRESS context region size */
1777         for (i = CTXT_EGRESS; i <= CTXT_INGRESS; i++) {
1778                 found = 0;
1779                 memset(&mem_desc, 0, sizeof(struct cudbg_mem_desc));
1780                 for (j = 0; j < ARRAY_SIZE(meminfo.avail); j++) {
1781                         rc = cudbg_get_mem_region(padap, &meminfo, j,
1782                                                   cudbg_region[i],
1783                                                   &mem_desc);
1784                         if (!rc) {
1785                                 found = 1;
1786                                 rc = cudbg_get_mem_relative(padap, &meminfo, j,
1787                                                             &mem_desc.base,
1788                                                             &mem_desc.limit);
1789                                 if (rc) {
1790                                         ctx_info[i].exist = false;
1791                                         break;
1792                                 }
1793                                 ctx_info[i].exist = true;
1794                                 ctx_info[i].start = mem_desc.base;
1795                                 ctx_info[i].end = mem_desc.limit;
1796                                 mem_type[i] = j;
1797                                 break;
1798                         }
1799                 }
1800                 if (!found)
1801                         ctx_info[i].exist = false;
1802         }
1803
1804         /* Get FLM and CNM max qid. */
1805         value = t4_read_reg(padap, SGE_FLM_CFG_A);
1806
1807         /* Get number of data freelist queues */
1808         flq = HDRSTARTFLQ_G(value);
1809         ctx_info[CTXT_FLM].exist = true;
1810         ctx_info[CTXT_FLM].end = (CUDBG_MAX_FL_QIDS >> flq) * SGE_CTXT_SIZE;
1811
1812         /* The number of CONM contexts are same as number of freelist
1813          * queues.
1814          */
1815         ctx_info[CTXT_CNM].exist = true;
1816         ctx_info[CTXT_CNM].end = ctx_info[CTXT_FLM].end;
1817
1818         return 0;
1819 }
1820
1821 int cudbg_dump_context_size(struct adapter *padap)
1822 {
1823         struct cudbg_region_info region_info[CTXT_CNM + 1] = { {0} };
1824         u8 mem_type[CTXT_INGRESS + 1] = { 0 };
1825         u32 i, size = 0;
1826         int rc;
1827
1828         /* Get max valid qid for each type of queue */
1829         rc = cudbg_get_ctxt_region_info(padap, region_info, mem_type);
1830         if (rc)
1831                 return rc;
1832
1833         for (i = 0; i < CTXT_CNM; i++) {
1834                 if (!region_info[i].exist) {
1835                         if (i == CTXT_EGRESS || i == CTXT_INGRESS)
1836                                 size += CUDBG_LOWMEM_MAX_CTXT_QIDS *
1837                                         SGE_CTXT_SIZE;
1838                         continue;
1839                 }
1840
1841                 size += (region_info[i].end - region_info[i].start + 1) /
1842                         SGE_CTXT_SIZE;
1843         }
1844         return size * sizeof(struct cudbg_ch_cntxt);
1845 }
1846
1847 static void cudbg_read_sge_ctxt(struct cudbg_init *pdbg_init, u32 cid,
1848                                 enum ctxt_type ctype, u32 *data)
1849 {
1850         struct adapter *padap = pdbg_init->adap;
1851         int rc = -1;
1852
1853         /* Under heavy traffic, the SGE Queue contexts registers will be
1854          * frequently accessed by firmware.
1855          *
1856          * To avoid conflicts with firmware, always ask firmware to fetch
1857          * the SGE Queue contexts via mailbox. On failure, fallback to
1858          * accessing hardware registers directly.
1859          */
1860         if (is_fw_attached(pdbg_init))
1861                 rc = t4_sge_ctxt_rd(padap, padap->mbox, cid, ctype, data);
1862         if (rc)
1863                 t4_sge_ctxt_rd_bd(padap, cid, ctype, data);
1864 }
1865
1866 static void cudbg_get_sge_ctxt_fw(struct cudbg_init *pdbg_init, u32 max_qid,
1867                                   u8 ctxt_type,
1868                                   struct cudbg_ch_cntxt **out_buff)
1869 {
1870         struct cudbg_ch_cntxt *buff = *out_buff;
1871         int rc;
1872         u32 j;
1873
1874         for (j = 0; j < max_qid; j++) {
1875                 cudbg_read_sge_ctxt(pdbg_init, j, ctxt_type, buff->data);
1876                 rc = cudbg_sge_ctxt_check_valid(buff->data, ctxt_type);
1877                 if (!rc)
1878                         continue;
1879
1880                 buff->cntxt_type = ctxt_type;
1881                 buff->cntxt_id = j;
1882                 buff++;
1883                 if (ctxt_type == CTXT_FLM) {
1884                         cudbg_read_sge_ctxt(pdbg_init, j, CTXT_CNM, buff->data);
1885                         buff->cntxt_type = CTXT_CNM;
1886                         buff->cntxt_id = j;
1887                         buff++;
1888                 }
1889         }
1890
1891         *out_buff = buff;
1892 }
1893
1894 int cudbg_collect_dump_context(struct cudbg_init *pdbg_init,
1895                                struct cudbg_buffer *dbg_buff,
1896                                struct cudbg_error *cudbg_err)
1897 {
1898         struct cudbg_region_info region_info[CTXT_CNM + 1] = { {0} };
1899         struct adapter *padap = pdbg_init->adap;
1900         u32 j, size, max_ctx_size, max_ctx_qid;
1901         u8 mem_type[CTXT_INGRESS + 1] = { 0 };
1902         struct cudbg_buffer temp_buff = { 0 };
1903         struct cudbg_ch_cntxt *buff;
1904         u64 *dst_off, *src_off;
1905         u8 *ctx_buf;
1906         u8 i, k;
1907         int rc;
1908
1909         /* Get max valid qid for each type of queue */
1910         rc = cudbg_get_ctxt_region_info(padap, region_info, mem_type);
1911         if (rc)
1912                 return rc;
1913
1914         rc = cudbg_dump_context_size(padap);
1915         if (rc <= 0)
1916                 return CUDBG_STATUS_ENTITY_NOT_FOUND;
1917
1918         size = rc;
1919         rc = cudbg_get_buff(pdbg_init, dbg_buff, size, &temp_buff);
1920         if (rc)
1921                 return rc;
1922
1923         /* Get buffer with enough space to read the biggest context
1924          * region in memory.
1925          */
1926         max_ctx_size = max(region_info[CTXT_EGRESS].end -
1927                            region_info[CTXT_EGRESS].start + 1,
1928                            region_info[CTXT_INGRESS].end -
1929                            region_info[CTXT_INGRESS].start + 1);
1930
1931         ctx_buf = kvzalloc(max_ctx_size, GFP_KERNEL);
1932         if (!ctx_buf) {
1933                 cudbg_put_buff(pdbg_init, &temp_buff);
1934                 return -ENOMEM;
1935         }
1936
1937         buff = (struct cudbg_ch_cntxt *)temp_buff.data;
1938
1939         /* Collect EGRESS and INGRESS context data.
1940          * In case of failures, fallback to collecting via FW or
1941          * backdoor access.
1942          */
1943         for (i = CTXT_EGRESS; i <= CTXT_INGRESS; i++) {
1944                 if (!region_info[i].exist) {
1945                         max_ctx_qid = CUDBG_LOWMEM_MAX_CTXT_QIDS;
1946                         cudbg_get_sge_ctxt_fw(pdbg_init, max_ctx_qid, i,
1947                                               &buff);
1948                         continue;
1949                 }
1950
1951                 max_ctx_size = region_info[i].end - region_info[i].start + 1;
1952                 max_ctx_qid = max_ctx_size / SGE_CTXT_SIZE;
1953
1954                 /* If firmware is not attached/alive, use backdoor register
1955                  * access to collect dump.
1956                  */
1957                 if (is_fw_attached(pdbg_init)) {
1958                         t4_sge_ctxt_flush(padap, padap->mbox, i);
1959
1960                         rc = t4_memory_rw(padap, MEMWIN_NIC, mem_type[i],
1961                                           region_info[i].start, max_ctx_size,
1962                                           (__be32 *)ctx_buf, 1);
1963                 }
1964
1965                 if (rc || !is_fw_attached(pdbg_init)) {
1966                         max_ctx_qid = CUDBG_LOWMEM_MAX_CTXT_QIDS;
1967                         cudbg_get_sge_ctxt_fw(pdbg_init, max_ctx_qid, i,
1968                                               &buff);
1969                         continue;
1970                 }
1971
1972                 for (j = 0; j < max_ctx_qid; j++) {
1973                         src_off = (u64 *)(ctx_buf + j * SGE_CTXT_SIZE);
1974                         dst_off = (u64 *)buff->data;
1975
1976                         /* The data is stored in 64-bit cpu order.  Convert it
1977                          * to big endian before parsing.
1978                          */
1979                         for (k = 0; k < SGE_CTXT_SIZE / sizeof(u64); k++)
1980                                 dst_off[k] = cpu_to_be64(src_off[k]);
1981
1982                         rc = cudbg_sge_ctxt_check_valid(buff->data, i);
1983                         if (!rc)
1984                                 continue;
1985
1986                         buff->cntxt_type = i;
1987                         buff->cntxt_id = j;
1988                         buff++;
1989                 }
1990         }
1991
1992         kvfree(ctx_buf);
1993
1994         /* Collect FREELIST and CONGESTION MANAGER contexts */
1995         max_ctx_size = region_info[CTXT_FLM].end -
1996                        region_info[CTXT_FLM].start + 1;
1997         max_ctx_qid = max_ctx_size / SGE_CTXT_SIZE;
1998         /* Since FLM and CONM are 1-to-1 mapped, the below function
1999          * will fetch both FLM and CONM contexts.
2000          */
2001         cudbg_get_sge_ctxt_fw(pdbg_init, max_ctx_qid, CTXT_FLM, &buff);
2002
2003         return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff);
2004 }
2005
2006 static inline void cudbg_tcamxy2valmask(u64 x, u64 y, u8 *addr, u64 *mask)
2007 {
2008         *mask = x | y;
2009         y = (__force u64)cpu_to_be64(y);
2010         memcpy(addr, (char *)&y + 2, ETH_ALEN);
2011 }
2012
2013 static void cudbg_mps_rpl_backdoor(struct adapter *padap,
2014                                    struct fw_ldst_mps_rplc *mps_rplc)
2015 {
2016         if (is_t5(padap->params.chip)) {
2017                 mps_rplc->rplc255_224 = htonl(t4_read_reg(padap,
2018                                                           MPS_VF_RPLCT_MAP3_A));
2019                 mps_rplc->rplc223_192 = htonl(t4_read_reg(padap,
2020                                                           MPS_VF_RPLCT_MAP2_A));
2021                 mps_rplc->rplc191_160 = htonl(t4_read_reg(padap,
2022                                                           MPS_VF_RPLCT_MAP1_A));
2023                 mps_rplc->rplc159_128 = htonl(t4_read_reg(padap,
2024                                                           MPS_VF_RPLCT_MAP0_A));
2025         } else {
2026                 mps_rplc->rplc255_224 = htonl(t4_read_reg(padap,
2027                                                           MPS_VF_RPLCT_MAP7_A));
2028                 mps_rplc->rplc223_192 = htonl(t4_read_reg(padap,
2029                                                           MPS_VF_RPLCT_MAP6_A));
2030                 mps_rplc->rplc191_160 = htonl(t4_read_reg(padap,
2031                                                           MPS_VF_RPLCT_MAP5_A));
2032                 mps_rplc->rplc159_128 = htonl(t4_read_reg(padap,
2033                                                           MPS_VF_RPLCT_MAP4_A));
2034         }
2035         mps_rplc->rplc127_96 = htonl(t4_read_reg(padap, MPS_VF_RPLCT_MAP3_A));
2036         mps_rplc->rplc95_64 = htonl(t4_read_reg(padap, MPS_VF_RPLCT_MAP2_A));
2037         mps_rplc->rplc63_32 = htonl(t4_read_reg(padap, MPS_VF_RPLCT_MAP1_A));
2038         mps_rplc->rplc31_0 = htonl(t4_read_reg(padap, MPS_VF_RPLCT_MAP0_A));
2039 }
2040
2041 static int cudbg_collect_tcam_index(struct cudbg_init *pdbg_init,
2042                                     struct cudbg_mps_tcam *tcam, u32 idx)
2043 {
2044         struct adapter *padap = pdbg_init->adap;
2045         u64 tcamy, tcamx, val;
2046         u32 ctl, data2;
2047         int rc = 0;
2048
2049         if (CHELSIO_CHIP_VERSION(padap->params.chip) >= CHELSIO_T6) {
2050                 /* CtlReqID   - 1: use Host Driver Requester ID
2051                  * CtlCmdType - 0: Read, 1: Write
2052                  * CtlTcamSel - 0: TCAM0, 1: TCAM1
2053                  * CtlXYBitSel- 0: Y bit, 1: X bit
2054                  */
2055
2056                 /* Read tcamy */
2057                 ctl = CTLREQID_V(1) | CTLCMDTYPE_V(0) | CTLXYBITSEL_V(0);
2058                 if (idx < 256)
2059                         ctl |= CTLTCAMINDEX_V(idx) | CTLTCAMSEL_V(0);
2060                 else
2061                         ctl |= CTLTCAMINDEX_V(idx - 256) | CTLTCAMSEL_V(1);
2062
2063                 t4_write_reg(padap, MPS_CLS_TCAM_DATA2_CTL_A, ctl);
2064                 val = t4_read_reg(padap, MPS_CLS_TCAM_RDATA1_REQ_ID1_A);
2065                 tcamy = DMACH_G(val) << 32;
2066                 tcamy |= t4_read_reg(padap, MPS_CLS_TCAM_RDATA0_REQ_ID1_A);
2067                 data2 = t4_read_reg(padap, MPS_CLS_TCAM_RDATA2_REQ_ID1_A);
2068                 tcam->lookup_type = DATALKPTYPE_G(data2);
2069
2070                 /* 0 - Outer header, 1 - Inner header
2071                  * [71:48] bit locations are overloaded for
2072                  * outer vs. inner lookup types.
2073                  */
2074                 if (tcam->lookup_type && tcam->lookup_type != DATALKPTYPE_M) {
2075                         /* Inner header VNI */
2076                         tcam->vniy = (data2 & DATAVIDH2_F) | DATAVIDH1_G(data2);
2077                         tcam->vniy = (tcam->vniy << 16) | VIDL_G(val);
2078                         tcam->dip_hit = data2 & DATADIPHIT_F;
2079                 } else {
2080                         tcam->vlan_vld = data2 & DATAVIDH2_F;
2081                         tcam->ivlan = VIDL_G(val);
2082                 }
2083
2084                 tcam->port_num = DATAPORTNUM_G(data2);
2085
2086                 /* Read tcamx. Change the control param */
2087                 ctl |= CTLXYBITSEL_V(1);
2088                 t4_write_reg(padap, MPS_CLS_TCAM_DATA2_CTL_A, ctl);
2089                 val = t4_read_reg(padap, MPS_CLS_TCAM_RDATA1_REQ_ID1_A);
2090                 tcamx = DMACH_G(val) << 32;
2091                 tcamx |= t4_read_reg(padap, MPS_CLS_TCAM_RDATA0_REQ_ID1_A);
2092                 data2 = t4_read_reg(padap, MPS_CLS_TCAM_RDATA2_REQ_ID1_A);
2093                 if (tcam->lookup_type && tcam->lookup_type != DATALKPTYPE_M) {
2094                         /* Inner header VNI mask */
2095                         tcam->vnix = (data2 & DATAVIDH2_F) | DATAVIDH1_G(data2);
2096                         tcam->vnix = (tcam->vnix << 16) | VIDL_G(val);
2097                 }
2098         } else {
2099                 tcamy = t4_read_reg64(padap, MPS_CLS_TCAM_Y_L(idx));
2100                 tcamx = t4_read_reg64(padap, MPS_CLS_TCAM_X_L(idx));
2101         }
2102
2103         /* If no entry, return */
2104         if (tcamx & tcamy)
2105                 return rc;
2106
2107         tcam->cls_lo = t4_read_reg(padap, MPS_CLS_SRAM_L(idx));
2108         tcam->cls_hi = t4_read_reg(padap, MPS_CLS_SRAM_H(idx));
2109
2110         if (is_t5(padap->params.chip))
2111                 tcam->repli = (tcam->cls_lo & REPLICATE_F);
2112         else if (is_t6(padap->params.chip))
2113                 tcam->repli = (tcam->cls_lo & T6_REPLICATE_F);
2114
2115         if (tcam->repli) {
2116                 struct fw_ldst_cmd ldst_cmd;
2117                 struct fw_ldst_mps_rplc mps_rplc;
2118
2119                 memset(&ldst_cmd, 0, sizeof(ldst_cmd));
2120                 ldst_cmd.op_to_addrspace =
2121                         htonl(FW_CMD_OP_V(FW_LDST_CMD) |
2122                               FW_CMD_REQUEST_F | FW_CMD_READ_F |
2123                               FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_MPS));
2124                 ldst_cmd.cycles_to_len16 = htonl(FW_LEN16(ldst_cmd));
2125                 ldst_cmd.u.mps.rplc.fid_idx =
2126                         htons(FW_LDST_CMD_FID_V(FW_LDST_MPS_RPLC) |
2127                               FW_LDST_CMD_IDX_V(idx));
2128
2129                 /* If firmware is not attached/alive, use backdoor register
2130                  * access to collect dump.
2131                  */
2132                 if (is_fw_attached(pdbg_init))
2133                         rc = t4_wr_mbox(padap, padap->mbox, &ldst_cmd,
2134                                         sizeof(ldst_cmd), &ldst_cmd);
2135
2136                 if (rc || !is_fw_attached(pdbg_init)) {
2137                         cudbg_mps_rpl_backdoor(padap, &mps_rplc);
2138                         /* Ignore error since we collected directly from
2139                          * reading registers.
2140                          */
2141                         rc = 0;
2142                 } else {
2143                         mps_rplc = ldst_cmd.u.mps.rplc;
2144                 }
2145
2146                 tcam->rplc[0] = ntohl(mps_rplc.rplc31_0);
2147                 tcam->rplc[1] = ntohl(mps_rplc.rplc63_32);
2148                 tcam->rplc[2] = ntohl(mps_rplc.rplc95_64);
2149                 tcam->rplc[3] = ntohl(mps_rplc.rplc127_96);
2150                 if (padap->params.arch.mps_rplc_size > CUDBG_MAX_RPLC_SIZE) {
2151                         tcam->rplc[4] = ntohl(mps_rplc.rplc159_128);
2152                         tcam->rplc[5] = ntohl(mps_rplc.rplc191_160);
2153                         tcam->rplc[6] = ntohl(mps_rplc.rplc223_192);
2154                         tcam->rplc[7] = ntohl(mps_rplc.rplc255_224);
2155                 }
2156         }
2157         cudbg_tcamxy2valmask(tcamx, tcamy, tcam->addr, &tcam->mask);
2158         tcam->idx = idx;
2159         tcam->rplc_size = padap->params.arch.mps_rplc_size;
2160         return rc;
2161 }
2162
2163 int cudbg_collect_mps_tcam(struct cudbg_init *pdbg_init,
2164                            struct cudbg_buffer *dbg_buff,
2165                            struct cudbg_error *cudbg_err)
2166 {
2167         struct adapter *padap = pdbg_init->adap;
2168         struct cudbg_buffer temp_buff = { 0 };
2169         u32 size = 0, i, n, total_size = 0;
2170         struct cudbg_mps_tcam *tcam;
2171         int rc;
2172
2173         n = padap->params.arch.mps_tcam_size;
2174         size = sizeof(struct cudbg_mps_tcam) * n;
2175         rc = cudbg_get_buff(pdbg_init, dbg_buff, size, &temp_buff);
2176         if (rc)
2177                 return rc;
2178
2179         tcam = (struct cudbg_mps_tcam *)temp_buff.data;
2180         for (i = 0; i < n; i++) {
2181                 rc = cudbg_collect_tcam_index(pdbg_init, tcam, i);
2182                 if (rc) {
2183                         cudbg_err->sys_err = rc;
2184                         cudbg_put_buff(pdbg_init, &temp_buff);
2185                         return rc;
2186                 }
2187                 total_size += sizeof(struct cudbg_mps_tcam);
2188                 tcam++;
2189         }
2190
2191         if (!total_size) {
2192                 rc = CUDBG_SYSTEM_ERROR;
2193                 cudbg_err->sys_err = rc;
2194                 cudbg_put_buff(pdbg_init, &temp_buff);
2195                 return rc;
2196         }
2197         return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff);
2198 }
2199
2200 int cudbg_collect_vpd_data(struct cudbg_init *pdbg_init,
2201                            struct cudbg_buffer *dbg_buff,
2202                            struct cudbg_error *cudbg_err)
2203 {
2204         struct adapter *padap = pdbg_init->adap;
2205         struct cudbg_buffer temp_buff = { 0 };
2206         char vpd_str[CUDBG_VPD_VER_LEN + 1];
2207         u32 scfg_vers, vpd_vers, fw_vers;
2208         struct cudbg_vpd_data *vpd_data;
2209         struct vpd_params vpd = { 0 };
2210         int rc, ret;
2211
2212         rc = t4_get_raw_vpd_params(padap, &vpd);
2213         if (rc)
2214                 return rc;
2215
2216         rc = t4_get_fw_version(padap, &fw_vers);
2217         if (rc)
2218                 return rc;
2219
2220         /* Serial Configuration Version is located beyond the PF's vpd size.
2221          * Temporarily give access to entire EEPROM to get it.
2222          */
2223         rc = pci_set_vpd_size(padap->pdev, EEPROMVSIZE);
2224         if (rc < 0)
2225                 return rc;
2226
2227         ret = cudbg_read_vpd_reg(padap, CUDBG_SCFG_VER_ADDR, CUDBG_SCFG_VER_LEN,
2228                                  &scfg_vers);
2229
2230         /* Restore back to original PF's vpd size */
2231         rc = pci_set_vpd_size(padap->pdev, CUDBG_VPD_PF_SIZE);
2232         if (rc < 0)
2233                 return rc;
2234
2235         if (ret)
2236                 return ret;
2237
2238         rc = cudbg_read_vpd_reg(padap, CUDBG_VPD_VER_ADDR, CUDBG_VPD_VER_LEN,
2239                                 vpd_str);
2240         if (rc)
2241                 return rc;
2242
2243         vpd_str[CUDBG_VPD_VER_LEN] = '\0';
2244         rc = kstrtouint(vpd_str, 0, &vpd_vers);
2245         if (rc)
2246                 return rc;
2247
2248         rc = cudbg_get_buff(pdbg_init, dbg_buff, sizeof(struct cudbg_vpd_data),
2249                             &temp_buff);
2250         if (rc)
2251                 return rc;
2252
2253         vpd_data = (struct cudbg_vpd_data *)temp_buff.data;
2254         memcpy(vpd_data->sn, vpd.sn, SERNUM_LEN + 1);
2255         memcpy(vpd_data->bn, vpd.pn, PN_LEN + 1);
2256         memcpy(vpd_data->na, vpd.na, MACADDR_LEN + 1);
2257         memcpy(vpd_data->mn, vpd.id, ID_LEN + 1);
2258         vpd_data->scfg_vers = scfg_vers;
2259         vpd_data->vpd_vers = vpd_vers;
2260         vpd_data->fw_major = FW_HDR_FW_VER_MAJOR_G(fw_vers);
2261         vpd_data->fw_minor = FW_HDR_FW_VER_MINOR_G(fw_vers);
2262         vpd_data->fw_micro = FW_HDR_FW_VER_MICRO_G(fw_vers);
2263         vpd_data->fw_build = FW_HDR_FW_VER_BUILD_G(fw_vers);
2264         return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff);
2265 }
2266
2267 static int cudbg_read_tid(struct cudbg_init *pdbg_init, u32 tid,
2268                           struct cudbg_tid_data *tid_data)
2269 {
2270         struct adapter *padap = pdbg_init->adap;
2271         int i, cmd_retry = 8;
2272         u32 val;
2273
2274         /* Fill REQ_DATA regs with 0's */
2275         for (i = 0; i < NUM_LE_DB_DBGI_REQ_DATA_INSTANCES; i++)
2276                 t4_write_reg(padap, LE_DB_DBGI_REQ_DATA_A + (i << 2), 0);
2277
2278         /* Write DBIG command */
2279         val = DBGICMD_V(4) | DBGITID_V(tid);
2280         t4_write_reg(padap, LE_DB_DBGI_REQ_TCAM_CMD_A, val);
2281         tid_data->dbig_cmd = val;
2282
2283         val = DBGICMDSTRT_F | DBGICMDMODE_V(1); /* LE mode */
2284         t4_write_reg(padap, LE_DB_DBGI_CONFIG_A, val);
2285         tid_data->dbig_conf = val;
2286
2287         /* Poll the DBGICMDBUSY bit */
2288         val = 1;
2289         while (val) {
2290                 val = t4_read_reg(padap, LE_DB_DBGI_CONFIG_A);
2291                 val = val & DBGICMDBUSY_F;
2292                 cmd_retry--;
2293                 if (!cmd_retry)
2294                         return CUDBG_SYSTEM_ERROR;
2295         }
2296
2297         /* Check RESP status */
2298         val = t4_read_reg(padap, LE_DB_DBGI_RSP_STATUS_A);
2299         tid_data->dbig_rsp_stat = val;
2300         if (!(val & 1))
2301                 return CUDBG_SYSTEM_ERROR;
2302
2303         /* Read RESP data */
2304         for (i = 0; i < NUM_LE_DB_DBGI_RSP_DATA_INSTANCES; i++)
2305                 tid_data->data[i] = t4_read_reg(padap,
2306                                                 LE_DB_DBGI_RSP_DATA_A +
2307                                                 (i << 2));
2308         tid_data->tid = tid;
2309         return 0;
2310 }
2311
2312 static int cudbg_get_le_type(u32 tid, struct cudbg_tcam tcam_region)
2313 {
2314         int type = LE_ET_UNKNOWN;
2315
2316         if (tid < tcam_region.server_start)
2317                 type = LE_ET_TCAM_CON;
2318         else if (tid < tcam_region.filter_start)
2319                 type = LE_ET_TCAM_SERVER;
2320         else if (tid < tcam_region.clip_start)
2321                 type = LE_ET_TCAM_FILTER;
2322         else if (tid < tcam_region.routing_start)
2323                 type = LE_ET_TCAM_CLIP;
2324         else if (tid < tcam_region.tid_hash_base)
2325                 type = LE_ET_TCAM_ROUTING;
2326         else if (tid < tcam_region.max_tid)
2327                 type = LE_ET_HASH_CON;
2328         else
2329                 type = LE_ET_INVALID_TID;
2330
2331         return type;
2332 }
2333
2334 static int cudbg_is_ipv6_entry(struct cudbg_tid_data *tid_data,
2335                                struct cudbg_tcam tcam_region)
2336 {
2337         int ipv6 = 0;
2338         int le_type;
2339
2340         le_type = cudbg_get_le_type(tid_data->tid, tcam_region);
2341         if (tid_data->tid & 1)
2342                 return 0;
2343
2344         if (le_type == LE_ET_HASH_CON) {
2345                 ipv6 = tid_data->data[16] & 0x8000;
2346         } else if (le_type == LE_ET_TCAM_CON) {
2347                 ipv6 = tid_data->data[16] & 0x8000;
2348                 if (ipv6)
2349                         ipv6 = tid_data->data[9] == 0x00C00000;
2350         } else {
2351                 ipv6 = 0;
2352         }
2353         return ipv6;
2354 }
2355
2356 void cudbg_fill_le_tcam_info(struct adapter *padap,
2357                              struct cudbg_tcam *tcam_region)
2358 {
2359         u32 value;
2360
2361         /* Get the LE regions */
2362         value = t4_read_reg(padap, LE_DB_TID_HASHBASE_A); /* hash base index */
2363         tcam_region->tid_hash_base = value;
2364
2365         /* Get routing table index */
2366         value = t4_read_reg(padap, LE_DB_ROUTING_TABLE_INDEX_A);
2367         tcam_region->routing_start = value;
2368
2369         /*Get clip table index */
2370         value = t4_read_reg(padap, LE_DB_CLIP_TABLE_INDEX_A);
2371         tcam_region->clip_start = value;
2372
2373         /* Get filter table index */
2374         value = t4_read_reg(padap, LE_DB_FILTER_TABLE_INDEX_A);
2375         tcam_region->filter_start = value;
2376
2377         /* Get server table index */
2378         value = t4_read_reg(padap, LE_DB_SERVER_INDEX_A);
2379         tcam_region->server_start = value;
2380
2381         /* Check whether hash is enabled and calculate the max tids */
2382         value = t4_read_reg(padap, LE_DB_CONFIG_A);
2383         if ((value >> HASHEN_S) & 1) {
2384                 value = t4_read_reg(padap, LE_DB_HASH_CONFIG_A);
2385                 if (CHELSIO_CHIP_VERSION(padap->params.chip) > CHELSIO_T5) {
2386                         tcam_region->max_tid = (value & 0xFFFFF) +
2387                                                tcam_region->tid_hash_base;
2388                 } else {
2389                         value = HASHTIDSIZE_G(value);
2390                         value = 1 << value;
2391                         tcam_region->max_tid = value +
2392                                                tcam_region->tid_hash_base;
2393                 }
2394         } else { /* hash not enabled */
2395                 tcam_region->max_tid = CUDBG_MAX_TCAM_TID;
2396         }
2397 }
2398
2399 int cudbg_collect_le_tcam(struct cudbg_init *pdbg_init,
2400                           struct cudbg_buffer *dbg_buff,
2401                           struct cudbg_error *cudbg_err)
2402 {
2403         struct adapter *padap = pdbg_init->adap;
2404         struct cudbg_buffer temp_buff = { 0 };
2405         struct cudbg_tcam tcam_region = { 0 };
2406         struct cudbg_tid_data *tid_data;
2407         u32 bytes = 0;
2408         int rc, size;
2409         u32 i;
2410
2411         cudbg_fill_le_tcam_info(padap, &tcam_region);
2412
2413         size = sizeof(struct cudbg_tid_data) * tcam_region.max_tid;
2414         size += sizeof(struct cudbg_tcam);
2415         rc = cudbg_get_buff(pdbg_init, dbg_buff, size, &temp_buff);
2416         if (rc)
2417                 return rc;
2418
2419         memcpy(temp_buff.data, &tcam_region, sizeof(struct cudbg_tcam));
2420         bytes = sizeof(struct cudbg_tcam);
2421         tid_data = (struct cudbg_tid_data *)(temp_buff.data + bytes);
2422         /* read all tid */
2423         for (i = 0; i < tcam_region.max_tid; ) {
2424                 rc = cudbg_read_tid(pdbg_init, i, tid_data);
2425                 if (rc) {
2426                         cudbg_err->sys_err = rc;
2427                         cudbg_put_buff(pdbg_init, &temp_buff);
2428                         return rc;
2429                 }
2430
2431                 /* ipv6 takes two tids */
2432                 cudbg_is_ipv6_entry(tid_data, tcam_region) ? i += 2 : i++;
2433
2434                 tid_data++;
2435                 bytes += sizeof(struct cudbg_tid_data);
2436         }
2437
2438         return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff);
2439 }
2440
2441 int cudbg_collect_cctrl(struct cudbg_init *pdbg_init,
2442                         struct cudbg_buffer *dbg_buff,
2443                         struct cudbg_error *cudbg_err)
2444 {
2445         struct adapter *padap = pdbg_init->adap;
2446         struct cudbg_buffer temp_buff = { 0 };
2447         u32 size;
2448         int rc;
2449
2450         size = sizeof(u16) * NMTUS * NCCTRL_WIN;
2451         rc = cudbg_get_buff(pdbg_init, dbg_buff, size, &temp_buff);
2452         if (rc)
2453                 return rc;
2454
2455         t4_read_cong_tbl(padap, (void *)temp_buff.data);
2456         return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff);
2457 }
2458
2459 int cudbg_collect_ma_indirect(struct cudbg_init *pdbg_init,
2460                               struct cudbg_buffer *dbg_buff,
2461                               struct cudbg_error *cudbg_err)
2462 {
2463         struct adapter *padap = pdbg_init->adap;
2464         struct cudbg_buffer temp_buff = { 0 };
2465         struct ireg_buf *ma_indr;
2466         int i, rc, n;
2467         u32 size, j;
2468
2469         if (CHELSIO_CHIP_VERSION(padap->params.chip) < CHELSIO_T6)
2470                 return CUDBG_STATUS_ENTITY_NOT_FOUND;
2471
2472         n = sizeof(t6_ma_ireg_array) / (IREG_NUM_ELEM * sizeof(u32));
2473         size = sizeof(struct ireg_buf) * n * 2;
2474         rc = cudbg_get_buff(pdbg_init, dbg_buff, size, &temp_buff);
2475         if (rc)
2476                 return rc;
2477
2478         ma_indr = (struct ireg_buf *)temp_buff.data;
2479         for (i = 0; i < n; i++) {
2480                 struct ireg_field *ma_fli = &ma_indr->tp_pio;
2481                 u32 *buff = ma_indr->outbuf;
2482
2483                 ma_fli->ireg_addr = t6_ma_ireg_array[i][0];
2484                 ma_fli->ireg_data = t6_ma_ireg_array[i][1];
2485                 ma_fli->ireg_local_offset = t6_ma_ireg_array[i][2];
2486                 ma_fli->ireg_offset_range = t6_ma_ireg_array[i][3];
2487                 t4_read_indirect(padap, ma_fli->ireg_addr, ma_fli->ireg_data,
2488                                  buff, ma_fli->ireg_offset_range,
2489                                  ma_fli->ireg_local_offset);
2490                 ma_indr++;
2491         }
2492
2493         n = sizeof(t6_ma_ireg_array2) / (IREG_NUM_ELEM * sizeof(u32));
2494         for (i = 0; i < n; i++) {
2495                 struct ireg_field *ma_fli = &ma_indr->tp_pio;
2496                 u32 *buff = ma_indr->outbuf;
2497
2498                 ma_fli->ireg_addr = t6_ma_ireg_array2[i][0];
2499                 ma_fli->ireg_data = t6_ma_ireg_array2[i][1];
2500                 ma_fli->ireg_local_offset = t6_ma_ireg_array2[i][2];
2501                 for (j = 0; j < t6_ma_ireg_array2[i][3]; j++) {
2502                         t4_read_indirect(padap, ma_fli->ireg_addr,
2503                                          ma_fli->ireg_data, buff, 1,
2504                                          ma_fli->ireg_local_offset);
2505                         buff++;
2506                         ma_fli->ireg_local_offset += 0x20;
2507                 }
2508                 ma_indr++;
2509         }
2510         return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff);
2511 }
2512
2513 int cudbg_collect_ulptx_la(struct cudbg_init *pdbg_init,
2514                            struct cudbg_buffer *dbg_buff,
2515                            struct cudbg_error *cudbg_err)
2516 {
2517         struct adapter *padap = pdbg_init->adap;
2518         struct cudbg_buffer temp_buff = { 0 };
2519         struct cudbg_ulptx_la *ulptx_la_buff;
2520         u32 i, j;
2521         int rc;
2522
2523         rc = cudbg_get_buff(pdbg_init, dbg_buff, sizeof(struct cudbg_ulptx_la),
2524                             &temp_buff);
2525         if (rc)
2526                 return rc;
2527
2528         ulptx_la_buff = (struct cudbg_ulptx_la *)temp_buff.data;
2529         for (i = 0; i < CUDBG_NUM_ULPTX; i++) {
2530                 ulptx_la_buff->rdptr[i] = t4_read_reg(padap,
2531                                                       ULP_TX_LA_RDPTR_0_A +
2532                                                       0x10 * i);
2533                 ulptx_la_buff->wrptr[i] = t4_read_reg(padap,
2534                                                       ULP_TX_LA_WRPTR_0_A +
2535                                                       0x10 * i);
2536                 ulptx_la_buff->rddata[i] = t4_read_reg(padap,
2537                                                        ULP_TX_LA_RDDATA_0_A +
2538                                                        0x10 * i);
2539                 for (j = 0; j < CUDBG_NUM_ULPTX_READ; j++)
2540                         ulptx_la_buff->rd_data[i][j] =
2541                                 t4_read_reg(padap,
2542                                             ULP_TX_LA_RDDATA_0_A + 0x10 * i);
2543         }
2544         return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff);
2545 }
2546
2547 int cudbg_collect_up_cim_indirect(struct cudbg_init *pdbg_init,
2548                                   struct cudbg_buffer *dbg_buff,
2549                                   struct cudbg_error *cudbg_err)
2550 {
2551         struct adapter *padap = pdbg_init->adap;
2552         struct cudbg_buffer temp_buff = { 0 };
2553         u32 local_offset, local_range;
2554         struct ireg_buf *up_cim;
2555         u32 size, j, iter;
2556         u32 instance = 0;
2557         int i, rc, n;
2558
2559         if (is_t5(padap->params.chip))
2560                 n = sizeof(t5_up_cim_reg_array) /
2561                     ((IREG_NUM_ELEM + 1) * sizeof(u32));
2562         else if (is_t6(padap->params.chip))
2563                 n = sizeof(t6_up_cim_reg_array) /
2564                     ((IREG_NUM_ELEM + 1) * sizeof(u32));
2565         else
2566                 return CUDBG_STATUS_NOT_IMPLEMENTED;
2567
2568         size = sizeof(struct ireg_buf) * n;
2569         rc = cudbg_get_buff(pdbg_init, dbg_buff, size, &temp_buff);
2570         if (rc)
2571                 return rc;
2572
2573         up_cim = (struct ireg_buf *)temp_buff.data;
2574         for (i = 0; i < n; i++) {
2575                 struct ireg_field *up_cim_reg = &up_cim->tp_pio;
2576                 u32 *buff = up_cim->outbuf;
2577
2578                 if (is_t5(padap->params.chip)) {
2579                         up_cim_reg->ireg_addr = t5_up_cim_reg_array[i][0];
2580                         up_cim_reg->ireg_data = t5_up_cim_reg_array[i][1];
2581                         up_cim_reg->ireg_local_offset =
2582                                                 t5_up_cim_reg_array[i][2];
2583                         up_cim_reg->ireg_offset_range =
2584                                                 t5_up_cim_reg_array[i][3];
2585                         instance = t5_up_cim_reg_array[i][4];
2586                 } else if (is_t6(padap->params.chip)) {
2587                         up_cim_reg->ireg_addr = t6_up_cim_reg_array[i][0];
2588                         up_cim_reg->ireg_data = t6_up_cim_reg_array[i][1];
2589                         up_cim_reg->ireg_local_offset =
2590                                                 t6_up_cim_reg_array[i][2];
2591                         up_cim_reg->ireg_offset_range =
2592                                                 t6_up_cim_reg_array[i][3];
2593                         instance = t6_up_cim_reg_array[i][4];
2594                 }
2595
2596                 switch (instance) {
2597                 case NUM_CIM_CTL_TSCH_CHANNEL_INSTANCES:
2598                         iter = up_cim_reg->ireg_offset_range;
2599                         local_offset = 0x120;
2600                         local_range = 1;
2601                         break;
2602                 case NUM_CIM_CTL_TSCH_CHANNEL_TSCH_CLASS_INSTANCES:
2603                         iter = up_cim_reg->ireg_offset_range;
2604                         local_offset = 0x10;
2605                         local_range = 1;
2606                         break;
2607                 default:
2608                         iter = 1;
2609                         local_offset = 0;
2610                         local_range = up_cim_reg->ireg_offset_range;
2611                         break;
2612                 }
2613
2614                 for (j = 0; j < iter; j++, buff++) {
2615                         rc = t4_cim_read(padap,
2616                                          up_cim_reg->ireg_local_offset +
2617                                          (j * local_offset), local_range, buff);
2618                         if (rc) {
2619                                 cudbg_put_buff(pdbg_init, &temp_buff);
2620                                 return rc;
2621                         }
2622                 }
2623                 up_cim++;
2624         }
2625         return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff);
2626 }
2627
2628 int cudbg_collect_pbt_tables(struct cudbg_init *pdbg_init,
2629                              struct cudbg_buffer *dbg_buff,
2630                              struct cudbg_error *cudbg_err)
2631 {
2632         struct adapter *padap = pdbg_init->adap;
2633         struct cudbg_buffer temp_buff = { 0 };
2634         struct cudbg_pbt_tables *pbt;
2635         int i, rc;
2636         u32 addr;
2637
2638         rc = cudbg_get_buff(pdbg_init, dbg_buff,
2639                             sizeof(struct cudbg_pbt_tables),
2640                             &temp_buff);
2641         if (rc)
2642                 return rc;
2643
2644         pbt = (struct cudbg_pbt_tables *)temp_buff.data;
2645         /* PBT dynamic entries */
2646         addr = CUDBG_CHAC_PBT_ADDR;
2647         for (i = 0; i < CUDBG_PBT_DYNAMIC_ENTRIES; i++) {
2648                 rc = t4_cim_read(padap, addr + (i * 4), 1,
2649                                  &pbt->pbt_dynamic[i]);
2650                 if (rc) {
2651                         cudbg_err->sys_err = rc;
2652                         cudbg_put_buff(pdbg_init, &temp_buff);
2653                         return rc;
2654                 }
2655         }
2656
2657         /* PBT static entries */
2658         /* static entries start when bit 6 is set */
2659         addr = CUDBG_CHAC_PBT_ADDR + (1 << 6);
2660         for (i = 0; i < CUDBG_PBT_STATIC_ENTRIES; i++) {
2661                 rc = t4_cim_read(padap, addr + (i * 4), 1,
2662                                  &pbt->pbt_static[i]);
2663                 if (rc) {
2664                         cudbg_err->sys_err = rc;
2665                         cudbg_put_buff(pdbg_init, &temp_buff);
2666                         return rc;
2667                 }
2668         }
2669
2670         /* LRF entries */
2671         addr = CUDBG_CHAC_PBT_LRF;
2672         for (i = 0; i < CUDBG_LRF_ENTRIES; i++) {
2673                 rc = t4_cim_read(padap, addr + (i * 4), 1,
2674                                  &pbt->lrf_table[i]);
2675                 if (rc) {
2676                         cudbg_err->sys_err = rc;
2677                         cudbg_put_buff(pdbg_init, &temp_buff);
2678                         return rc;
2679                 }
2680         }
2681
2682         /* PBT data entries */
2683         addr = CUDBG_CHAC_PBT_DATA;
2684         for (i = 0; i < CUDBG_PBT_DATA_ENTRIES; i++) {
2685                 rc = t4_cim_read(padap, addr + (i * 4), 1,
2686                                  &pbt->pbt_data[i]);
2687                 if (rc) {
2688                         cudbg_err->sys_err = rc;
2689                         cudbg_put_buff(pdbg_init, &temp_buff);
2690                         return rc;
2691                 }
2692         }
2693         return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff);
2694 }
2695
2696 int cudbg_collect_mbox_log(struct cudbg_init *pdbg_init,
2697                            struct cudbg_buffer *dbg_buff,
2698                            struct cudbg_error *cudbg_err)
2699 {
2700         struct adapter *padap = pdbg_init->adap;
2701         struct cudbg_mbox_log *mboxlog = NULL;
2702         struct cudbg_buffer temp_buff = { 0 };
2703         struct mbox_cmd_log *log = NULL;
2704         struct mbox_cmd *entry;
2705         unsigned int entry_idx;
2706         u16 mbox_cmds;
2707         int i, k, rc;
2708         u64 flit;
2709         u32 size;
2710
2711         log = padap->mbox_log;
2712         mbox_cmds = padap->mbox_log->size;
2713         size = sizeof(struct cudbg_mbox_log) * mbox_cmds;
2714         rc = cudbg_get_buff(pdbg_init, dbg_buff, size, &temp_buff);
2715         if (rc)
2716                 return rc;
2717
2718         mboxlog = (struct cudbg_mbox_log *)temp_buff.data;
2719         for (k = 0; k < mbox_cmds; k++) {
2720                 entry_idx = log->cursor + k;
2721                 if (entry_idx >= log->size)
2722                         entry_idx -= log->size;
2723
2724                 entry = mbox_cmd_log_entry(log, entry_idx);
2725                 /* skip over unused entries */
2726                 if (entry->timestamp == 0)
2727                         continue;
2728
2729                 memcpy(&mboxlog->entry, entry, sizeof(struct mbox_cmd));
2730                 for (i = 0; i < MBOX_LEN / 8; i++) {
2731                         flit = entry->cmd[i];
2732                         mboxlog->hi[i] = (u32)(flit >> 32);
2733                         mboxlog->lo[i] = (u32)flit;
2734                 }
2735                 mboxlog++;
2736         }
2737         return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff);
2738 }
2739
2740 int cudbg_collect_hma_indirect(struct cudbg_init *pdbg_init,
2741                                struct cudbg_buffer *dbg_buff,
2742                                struct cudbg_error *cudbg_err)
2743 {
2744         struct adapter *padap = pdbg_init->adap;
2745         struct cudbg_buffer temp_buff = { 0 };
2746         struct ireg_buf *hma_indr;
2747         int i, rc, n;
2748         u32 size;
2749
2750         if (CHELSIO_CHIP_VERSION(padap->params.chip) < CHELSIO_T6)
2751                 return CUDBG_STATUS_ENTITY_NOT_FOUND;
2752
2753         n = sizeof(t6_hma_ireg_array) / (IREG_NUM_ELEM * sizeof(u32));
2754         size = sizeof(struct ireg_buf) * n;
2755         rc = cudbg_get_buff(pdbg_init, dbg_buff, size, &temp_buff);
2756         if (rc)
2757                 return rc;
2758
2759         hma_indr = (struct ireg_buf *)temp_buff.data;
2760         for (i = 0; i < n; i++) {
2761                 struct ireg_field *hma_fli = &hma_indr->tp_pio;
2762                 u32 *buff = hma_indr->outbuf;
2763
2764                 hma_fli->ireg_addr = t6_hma_ireg_array[i][0];
2765                 hma_fli->ireg_data = t6_hma_ireg_array[i][1];
2766                 hma_fli->ireg_local_offset = t6_hma_ireg_array[i][2];
2767                 hma_fli->ireg_offset_range = t6_hma_ireg_array[i][3];
2768                 t4_read_indirect(padap, hma_fli->ireg_addr, hma_fli->ireg_data,
2769                                  buff, hma_fli->ireg_offset_range,
2770                                  hma_fli->ireg_local_offset);
2771                 hma_indr++;
2772         }
2773         return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff);
2774 }