drivers/net/ethernet/chelsio/cxgb4/cudbg_entity.h

   1 /*
   2  *  Copyright (C) 2017 Chelsio Communications.  All rights reserved.
   3  *
   4  *  This program is free software; you can redistribute it and/or modify it
   5  *  under the terms and conditions of the GNU General Public License,
   6  *  version 2, as published by the Free Software Foundation.
   7  *
   8  *  This program is distributed in the hope it will be useful, but WITHOUT
   9  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  10  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  11  *  more details.
  12  *
  13  *  The full GNU General Public License is included in this distribution in
  14  *  the file called "COPYING".
  15  *
  16  */
  17
  18 #ifndef __CUDBG_ENTITY_H__
  19 #define __CUDBG_ENTITY_H__
  20
  21 #define EDC0_FLAG 3
  22 #define EDC1_FLAG 4
  23
  24 #define CUDBG_ENTITY_SIGNATURE 0xCCEDB001
  25
  26 struct card_mem {
  27         u16 size_edc0;
  28         u16 size_edc1;
  29         u16 mem_flag;
  30 };
  31
  32 struct cudbg_mbox_log {
  33         struct mbox_cmd entry;
  34         u32 hi[MBOX_LEN / 8];
  35         u32 lo[MBOX_LEN / 8];
  36 };
  37
  38 struct cudbg_cim_qcfg {
  39         u8 chip;
  40         u16 base[CIM_NUM_IBQ + CIM_NUM_OBQ_T5];
  41         u16 size[CIM_NUM_IBQ + CIM_NUM_OBQ_T5];
  42         u16 thres[CIM_NUM_IBQ];
  43         u32 obq_wr[2 * CIM_NUM_OBQ_T5];
  44         u32 stat[4 * (CIM_NUM_IBQ + CIM_NUM_OBQ_T5)];
  45 };
  46
  47 struct cudbg_rss_vf_conf {
  48         u32 rss_vf_vfl;
  49         u32 rss_vf_vfh;
  50 };
  51
  52 struct cudbg_pm_stats {
  53         u32 tx_cnt[T6_PM_NSTATS];
  54         u32 rx_cnt[T6_PM_NSTATS];
  55         u64 tx_cyc[T6_PM_NSTATS];
  56         u64 rx_cyc[T6_PM_NSTATS];
  57 };
  58
  59 struct cudbg_hw_sched {
  60         u32 kbps[NTX_SCHED];
  61         u32 ipg[NTX_SCHED];
  62         u32 pace_tab[NTX_SCHED];
  63         u32 mode;
  64         u32 map;
  65 };
  66
  67 struct ireg_field {
  68         u32 ireg_addr;
  69         u32 ireg_data;
  70         u32 ireg_local_offset;
  71         u32 ireg_offset_range;
  72 };
  73
  74 struct ireg_buf {
  75         struct ireg_field tp_pio;
  76         u32 outbuf[32];
  77 };
  78
  79 struct cudbg_ulprx_la {
  80         u32 data[ULPRX_LA_SIZE * 8];
  81         u32 size;
  82 };
  83
  84 struct cudbg_tp_la {
  85         u32 size;
  86         u32 mode;
  87         u8 data[0];
  88 };
  89
  90 struct cudbg_cim_pif_la {
  91         int size;
  92         u8 data[0];
  93 };
  94
  95 struct cudbg_clk_info {
  96         u64 retransmit_min;
  97         u64 retransmit_max;
  98         u64 persist_timer_min;
  99         u64 persist_timer_max;
 100         u64 keepalive_idle_timer;
 101         u64 keepalive_interval;
 102         u64 initial_srtt;
 103         u64 finwait2_timer;
 104         u32 dack_timer;
 105         u32 res;
 106         u32 cclk_ps;
 107         u32 tre;
 108         u32 dack_re;
 109 };
 110
 111 struct cudbg_tid_info_region {
 112         u32 ntids;
 113         u32 nstids;
 114         u32 stid_base;
 115         u32 hash_base;
 116
 117         u32 natids;
 118         u32 nftids;
 119         u32 ftid_base;
 120         u32 aftid_base;
 121         u32 aftid_end;
 122
 123         u32 sftid_base;
 124         u32 nsftids;
 125
 126         u32 uotid_base;
 127         u32 nuotids;
 128
 129         u32 sb;
 130         u32 flags;
 131         u32 le_db_conf;
 132         u32 ip_users;
 133         u32 ipv6_users;
 134
 135         u32 hpftid_base;
 136         u32 nhpftids;
 137 };
 138
 139 #define CUDBG_TID_INFO_REV 1
 140
 141 struct cudbg_tid_info_region_rev1 {
 142         struct cudbg_ver_hdr ver_hdr;
 143         struct cudbg_tid_info_region tid;
 144         u32 tid_start;
 145         u32 reserved[16];
 146 };
 147
 148 #define CUDBG_MAX_FL_QIDS 1024
 149
 150 struct cudbg_ch_cntxt {
 151         u32 cntxt_type;
 152         u32 cntxt_id;
 153         u32 data[SGE_CTXT_SIZE / 4];
 154 };
 155
 156 #define CUDBG_MAX_RPLC_SIZE 128
 157
 158 struct cudbg_mps_tcam {
 159         u64 mask;
 160         u32 rplc[8];
 161         u32 idx;
 162         u32 cls_lo;
 163         u32 cls_hi;
 164         u32 rplc_size;
 165         u32 vniy;
 166         u32 vnix;
 167         u32 dip_hit;
 168         u32 vlan_vld;
 169         u32 repli;
 170         u16 ivlan;
 171         u8 addr[ETH_ALEN];
 172         u8 lookup_type;
 173         u8 port_num;
 174         u8 reserved[2];
 175 };
 176
 177 #define CUDBG_VPD_PF_SIZE 0x800
 178 #define CUDBG_SCFG_VER_ADDR 0x06
 179 #define CUDBG_SCFG_VER_LEN 4
 180 #define CUDBG_VPD_VER_ADDR 0x18c7
 181 #define CUDBG_VPD_VER_LEN 2
 182
 183 struct cudbg_vpd_data {
 184         u8 sn[SERNUM_LEN + 1];
 185         u8 bn[PN_LEN + 1];
 186         u8 na[MACADDR_LEN + 1];
 187         u8 mn[ID_LEN + 1];
 188         u16 fw_major;
 189         u16 fw_minor;
 190         u16 fw_micro;
 191         u16 fw_build;
 192         u32 scfg_vers;
 193         u32 vpd_vers;
 194 };
 195
 196 #define CUDBG_MAX_TCAM_TID 0x800
 197
 198 enum cudbg_le_entry_types {
 199         LE_ET_UNKNOWN = 0,
 200         LE_ET_TCAM_CON = 1,
 201         LE_ET_TCAM_SERVER = 2,
 202         LE_ET_TCAM_FILTER = 3,
 203         LE_ET_TCAM_CLIP = 4,
 204         LE_ET_TCAM_ROUTING = 5,
 205         LE_ET_HASH_CON = 6,
 206         LE_ET_INVALID_TID = 8,
 207 };
 208
 209 struct cudbg_tcam {
 210         u32 filter_start;
 211         u32 server_start;
 212         u32 clip_start;
 213         u32 routing_start;
 214         u32 tid_hash_base;
 215         u32 max_tid;
 216 };
 217
 218 struct cudbg_tid_data {
 219         u32 tid;
 220         u32 dbig_cmd;
 221         u32 dbig_conf;
 222         u32 dbig_rsp_stat;
 223         u32 data[NUM_LE_DB_DBGI_RSP_DATA_INSTANCES];
 224 };
 225
 226 #define CUDBG_NUM_ULPTX 11
 227 #define CUDBG_NUM_ULPTX_READ 512
 228
 229 struct cudbg_ulptx_la {
 230         u32 rdptr[CUDBG_NUM_ULPTX];
 231         u32 wrptr[CUDBG_NUM_ULPTX];
 232         u32 rddata[CUDBG_NUM_ULPTX];
 233         u32 rd_data[CUDBG_NUM_ULPTX][CUDBG_NUM_ULPTX_READ];
 234 };
 235
 236 #define CUDBG_CHAC_PBT_ADDR 0x2800
 237 #define CUDBG_CHAC_PBT_LRF  0x3000
 238 #define CUDBG_CHAC_PBT_DATA 0x3800
 239 #define CUDBG_PBT_DYNAMIC_ENTRIES 8
 240 #define CUDBG_PBT_STATIC_ENTRIES 16
 241 #define CUDBG_LRF_ENTRIES 8
 242 #define CUDBG_PBT_DATA_ENTRIES 512
 243
 244 struct cudbg_pbt_tables {
 245         u32 pbt_dynamic[CUDBG_PBT_DYNAMIC_ENTRIES];
 246         u32 pbt_static[CUDBG_PBT_STATIC_ENTRIES];
 247         u32 lrf_table[CUDBG_LRF_ENTRIES];
 248         u32 pbt_data[CUDBG_PBT_DATA_ENTRIES];
 249 };
 250
 251 #define IREG_NUM_ELEM 4
 252
 253 static const u32 t6_tp_pio_array[][IREG_NUM_ELEM] = {
 254         {0x7e40, 0x7e44, 0x020, 28}, /* t6_tp_pio_regs_20_to_3b */
 255         {0x7e40, 0x7e44, 0x040, 10}, /* t6_tp_pio_regs_40_to_49 */
 256         {0x7e40, 0x7e44, 0x050, 10}, /* t6_tp_pio_regs_50_to_59 */
 257         {0x7e40, 0x7e44, 0x060, 14}, /* t6_tp_pio_regs_60_to_6d */
 258         {0x7e40, 0x7e44, 0x06F, 1}, /* t6_tp_pio_regs_6f */
 259         {0x7e40, 0x7e44, 0x070, 6}, /* t6_tp_pio_regs_70_to_75 */
 260         {0x7e40, 0x7e44, 0x130, 18}, /* t6_tp_pio_regs_130_to_141 */
 261         {0x7e40, 0x7e44, 0x145, 19}, /* t6_tp_pio_regs_145_to_157 */
 262         {0x7e40, 0x7e44, 0x160, 1}, /* t6_tp_pio_regs_160 */
 263         {0x7e40, 0x7e44, 0x230, 25}, /* t6_tp_pio_regs_230_to_248 */
 264         {0x7e40, 0x7e44, 0x24a, 3}, /* t6_tp_pio_regs_24c */
 265         {0x7e40, 0x7e44, 0x8C0, 1} /* t6_tp_pio_regs_8c0 */
 266 };
 267
 268 static const u32 t5_tp_pio_array[][IREG_NUM_ELEM] = {
 269         {0x7e40, 0x7e44, 0x020, 28}, /* t5_tp_pio_regs_20_to_3b */
 270         {0x7e40, 0x7e44, 0x040, 19}, /* t5_tp_pio_regs_40_to_52 */
 271         {0x7e40, 0x7e44, 0x054, 2}, /* t5_tp_pio_regs_54_to_55 */
 272         {0x7e40, 0x7e44, 0x060, 13}, /* t5_tp_pio_regs_60_to_6c */
 273         {0x7e40, 0x7e44, 0x06F, 1}, /* t5_tp_pio_regs_6f */
 274         {0x7e40, 0x7e44, 0x120, 4}, /* t5_tp_pio_regs_120_to_123 */
 275         {0x7e40, 0x7e44, 0x12b, 2}, /* t5_tp_pio_regs_12b_to_12c */
 276         {0x7e40, 0x7e44, 0x12f, 21}, /* t5_tp_pio_regs_12f_to_143 */
 277         {0x7e40, 0x7e44, 0x145, 19}, /* t5_tp_pio_regs_145_to_157 */
 278         {0x7e40, 0x7e44, 0x230, 25}, /* t5_tp_pio_regs_230_to_248 */
 279         {0x7e40, 0x7e44, 0x8C0, 1} /* t5_tp_pio_regs_8c0 */
 280 };
 281
 282 static const u32 t6_tp_tm_pio_array[][IREG_NUM_ELEM] = {
 283         {0x7e18, 0x7e1c, 0x0, 12}
 284 };
 285
 286 static const u32 t5_tp_tm_pio_array[][IREG_NUM_ELEM] = {
 287         {0x7e18, 0x7e1c, 0x0, 12}
 288 };
 289
 290 static const u32 t6_tp_mib_index_array[6][IREG_NUM_ELEM] = {
 291         {0x7e50, 0x7e54, 0x0, 13},
 292         {0x7e50, 0x7e54, 0x10, 6},
 293         {0x7e50, 0x7e54, 0x18, 21},
 294         {0x7e50, 0x7e54, 0x30, 32},
 295         {0x7e50, 0x7e54, 0x50, 22},
 296         {0x7e50, 0x7e54, 0x68, 12}
 297 };
 298
 299 static const u32 t5_tp_mib_index_array[9][IREG_NUM_ELEM] = {
 300         {0x7e50, 0x7e54, 0x0, 13},
 301         {0x7e50, 0x7e54, 0x10, 6},
 302         {0x7e50, 0x7e54, 0x18, 8},
 303         {0x7e50, 0x7e54, 0x20, 13},
 304         {0x7e50, 0x7e54, 0x30, 16},
 305         {0x7e50, 0x7e54, 0x40, 16},
 306         {0x7e50, 0x7e54, 0x50, 16},
 307         {0x7e50, 0x7e54, 0x60, 6},
 308         {0x7e50, 0x7e54, 0x68, 4}
 309 };
 310
 311 static const u32 t5_sge_dbg_index_array[2][IREG_NUM_ELEM] = {
 312         {0x10cc, 0x10d0, 0x0, 16},
 313         {0x10cc, 0x10d4, 0x0, 16},
 314 };
 315
 316 static const u32 t5_pcie_pdbg_array[][IREG_NUM_ELEM] = {
 317         {0x5a04, 0x5a0c, 0x00, 0x20}, /* t5_pcie_pdbg_regs_00_to_20 */
 318         {0x5a04, 0x5a0c, 0x21, 0x20}, /* t5_pcie_pdbg_regs_21_to_40 */
 319         {0x5a04, 0x5a0c, 0x41, 0x10}, /* t5_pcie_pdbg_regs_41_to_50 */
 320 };
 321
 322 static const u32 t5_pcie_cdbg_array[][IREG_NUM_ELEM] = {
 323         {0x5a10, 0x5a18, 0x00, 0x20}, /* t5_pcie_cdbg_regs_00_to_20 */
 324         {0x5a10, 0x5a18, 0x21, 0x18}, /* t5_pcie_cdbg_regs_21_to_37 */
 325 };
 326
 327 static const u32 t5_pm_rx_array[][IREG_NUM_ELEM] = {
 328         {0x8FD0, 0x8FD4, 0x10000, 0x20}, /* t5_pm_rx_regs_10000_to_10020 */
 329         {0x8FD0, 0x8FD4, 0x10021, 0x0D}, /* t5_pm_rx_regs_10021_to_1002c */
 330 };
 331
 332 static const u32 t5_pm_tx_array[][IREG_NUM_ELEM] = {
 333         {0x8FF0, 0x8FF4, 0x10000, 0x20}, /* t5_pm_tx_regs_10000_to_10020 */
 334         {0x8FF0, 0x8FF4, 0x10021, 0x1D}, /* t5_pm_tx_regs_10021_to_1003c */
 335 };
 336
 337 static const u32 t6_ma_ireg_array[][IREG_NUM_ELEM] = {
 338         {0x78f8, 0x78fc, 0xa000, 23}, /* t6_ma_regs_a000_to_a016 */
 339         {0x78f8, 0x78fc, 0xa400, 30}, /* t6_ma_regs_a400_to_a41e */
 340         {0x78f8, 0x78fc, 0xa800, 20} /* t6_ma_regs_a800_to_a813 */
 341 };
 342
 343 static const u32 t6_ma_ireg_array2[][IREG_NUM_ELEM] = {
 344         {0x78f8, 0x78fc, 0xe400, 17}, /* t6_ma_regs_e400_to_e600 */
 345         {0x78f8, 0x78fc, 0xe640, 13} /* t6_ma_regs_e640_to_e7c0 */
 346 };
 347
 348 static const u32 t6_up_cim_reg_array[][IREG_NUM_ELEM] = {
 349         {0x7b50, 0x7b54, 0x2000, 0x20}, /* up_cim_2000_to_207c */
 350         {0x7b50, 0x7b54, 0x2080, 0x1d}, /* up_cim_2080_to_20fc */
 351         {0x7b50, 0x7b54, 0x00, 0x20}, /* up_cim_00_to_7c */
 352         {0x7b50, 0x7b54, 0x80, 0x20}, /* up_cim_80_to_fc */
 353         {0x7b50, 0x7b54, 0x100, 0x11}, /* up_cim_100_to_14c */
 354         {0x7b50, 0x7b54, 0x200, 0x10}, /* up_cim_200_to_23c */
 355         {0x7b50, 0x7b54, 0x240, 0x2}, /* up_cim_240_to_244 */
 356         {0x7b50, 0x7b54, 0x250, 0x2}, /* up_cim_250_to_254 */
 357         {0x7b50, 0x7b54, 0x260, 0x2}, /* up_cim_260_to_264 */
 358         {0x7b50, 0x7b54, 0x270, 0x2}, /* up_cim_270_to_274 */
 359         {0x7b50, 0x7b54, 0x280, 0x20}, /* up_cim_280_to_2fc */
 360         {0x7b50, 0x7b54, 0x300, 0x20}, /* up_cim_300_to_37c */
 361         {0x7b50, 0x7b54, 0x380, 0x14}, /* up_cim_380_to_3cc */
 362
 363 };
 364
 365 static const u32 t5_up_cim_reg_array[][IREG_NUM_ELEM] = {
 366         {0x7b50, 0x7b54, 0x2000, 0x20}, /* up_cim_2000_to_207c */
 367         {0x7b50, 0x7b54, 0x2080, 0x19}, /* up_cim_2080_to_20ec */
 368         {0x7b50, 0x7b54, 0x00, 0x20}, /* up_cim_00_to_7c */
 369         {0x7b50, 0x7b54, 0x80, 0x20}, /* up_cim_80_to_fc */
 370         {0x7b50, 0x7b54, 0x100, 0x11}, /* up_cim_100_to_14c */
 371         {0x7b50, 0x7b54, 0x200, 0x10}, /* up_cim_200_to_23c */
 372         {0x7b50, 0x7b54, 0x240, 0x2}, /* up_cim_240_to_244 */
 373         {0x7b50, 0x7b54, 0x250, 0x2}, /* up_cim_250_to_254 */
 374         {0x7b50, 0x7b54, 0x260, 0x2}, /* up_cim_260_to_264 */
 375         {0x7b50, 0x7b54, 0x270, 0x2}, /* up_cim_270_to_274 */
 376         {0x7b50, 0x7b54, 0x280, 0x20}, /* up_cim_280_to_2fc */
 377         {0x7b50, 0x7b54, 0x300, 0x20}, /* up_cim_300_to_37c */
 378         {0x7b50, 0x7b54, 0x380, 0x14}, /* up_cim_380_to_3cc */
 379 };
 380
 381 static const u32 t6_hma_ireg_array[][IREG_NUM_ELEM] = {
 382         {0x51320, 0x51324, 0xa000, 32} /* t6_hma_regs_a000_to_a01f */
 383 };
 384 #endif /* __CUDBG_ENTITY_H__ */