2 * Copyright (C) 2015 Cavium, Inc.
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of version 2 of the GNU General Public License
6 * as published by the Free Software Foundation.
10 #include <linux/netdevice.h>
12 #include <linux/etherdevice.h>
13 #include <linux/iommu.h>
20 #include "nicvf_queues.h"
22 static inline u64 nicvf_iova_to_phys(struct nicvf *nic, dma_addr_t dma_addr)
24 /* Translation is installed only when IOMMU is present */
25 if (nic->iommu_domain)
26 return iommu_iova_to_phys(nic->iommu_domain, dma_addr);
30 static void nicvf_get_page(struct nicvf *nic)
32 if (!nic->rb_pageref || !nic->rb_page)
35 page_ref_add(nic->rb_page, nic->rb_pageref);
39 /* Poll a register for a specific value */
40 static int nicvf_poll_reg(struct nicvf *nic, int qidx,
41 u64 reg, int bit_pos, int bits, int val)
47 bit_mask = (1ULL << bits) - 1;
48 bit_mask = (bit_mask << bit_pos);
51 reg_val = nicvf_queue_reg_read(nic, reg, qidx);
52 if (((reg_val & bit_mask) >> bit_pos) == val)
54 usleep_range(1000, 2000);
57 netdev_err(nic->netdev, "Poll on reg 0x%llx failed\n", reg);
61 /* Allocate memory for a queue's descriptors */
62 static int nicvf_alloc_q_desc_mem(struct nicvf *nic, struct q_desc_mem *dmem,
63 int q_len, int desc_size, int align_bytes)
66 dmem->size = (desc_size * q_len) + align_bytes;
67 /* Save address, need it while freeing */
68 dmem->unalign_base = dma_zalloc_coherent(&nic->pdev->dev, dmem->size,
69 &dmem->dma, GFP_KERNEL);
70 if (!dmem->unalign_base)
73 /* Align memory address for 'align_bytes' */
74 dmem->phys_base = NICVF_ALIGNED_ADDR((u64)dmem->dma, align_bytes);
75 dmem->base = dmem->unalign_base + (dmem->phys_base - dmem->dma);
79 /* Free queue's descriptor memory */
80 static void nicvf_free_q_desc_mem(struct nicvf *nic, struct q_desc_mem *dmem)
85 dma_free_coherent(&nic->pdev->dev, dmem->size,
86 dmem->unalign_base, dmem->dma);
87 dmem->unalign_base = NULL;
91 /* Allocate a new page or recycle one if possible
93 * We cannot optimize dma mapping here, since
94 * 1. It's only one RBDR ring for 8 Rx queues.
95 * 2. CQE_RX gives address of the buffer where pkt has been DMA'ed
96 * and not idx into RBDR ring, so can't refer to saved info.
97 * 3. There are multiple receive buffers per page
99 static struct pgcache *nicvf_alloc_page(struct nicvf *nic,
100 struct rbdr *rbdr, gfp_t gfp)
102 struct page *page = NULL;
103 struct pgcache *pgcache, *next;
105 /* Check if page is already allocated */
106 pgcache = &rbdr->pgcache[rbdr->pgidx];
107 page = pgcache->page;
108 /* Check if page can be recycled */
109 if (page && (page_ref_count(page) != 1))
113 page = alloc_pages(gfp | __GFP_COMP | __GFP_NOWARN, 0);
117 this_cpu_inc(nic->pnicvf->drv_stats->page_alloc);
119 /* Check for space */
120 if (rbdr->pgalloc >= rbdr->pgcnt) {
121 /* Page can still be used */
126 /* Save the page in page cache */
127 pgcache->page = page;
131 /* Take extra page reference for recycling */
132 page_ref_add(page, 1);
135 rbdr->pgidx &= (rbdr->pgcnt - 1);
137 /* Prefetch refcount of next page in page cache */
138 next = &rbdr->pgcache[rbdr->pgidx];
141 prefetch(&page->_refcount);
146 /* Allocate buffer for packet reception */
147 static inline int nicvf_alloc_rcv_buffer(struct nicvf *nic, struct rbdr *rbdr,
148 gfp_t gfp, u32 buf_len, u64 **rbuf)
150 struct pgcache *pgcache = NULL;
152 /* Check if request can be accomodated in previous allocated page */
154 ((nic->rb_page_offset + buf_len) <= PAGE_SIZE)) {
162 /* Get new page, either recycled or new one */
163 pgcache = nicvf_alloc_page(nic, rbdr, gfp);
164 if (!pgcache && !nic->rb_page) {
165 this_cpu_inc(nic->pnicvf->drv_stats->rcv_buffer_alloc_failures);
169 nic->rb_page_offset = 0;
170 /* Check if it's recycled */
172 nic->rb_page = pgcache->page;
174 /* HW will ensure data coherency, CPU sync not required */
175 *rbuf = (u64 *)((u64)dma_map_page_attrs(&nic->pdev->dev, nic->rb_page,
176 nic->rb_page_offset, buf_len,
178 DMA_ATTR_SKIP_CPU_SYNC));
179 if (dma_mapping_error(&nic->pdev->dev, (dma_addr_t)*rbuf)) {
180 if (!nic->rb_page_offset)
181 __free_pages(nic->rb_page, 0);
185 nic->rb_page_offset += buf_len;
190 /* Build skb around receive buffer */
191 static struct sk_buff *nicvf_rb_ptr_to_skb(struct nicvf *nic,
197 data = phys_to_virt(rb_ptr);
199 /* Now build an skb to give to stack */
200 skb = build_skb(data, RCV_FRAG_LEN);
202 put_page(virt_to_page(data));
210 /* Allocate RBDR ring and populate receive buffers */
211 static int nicvf_init_rbdr(struct nicvf *nic, struct rbdr *rbdr,
212 int ring_len, int buf_size)
216 struct rbdr_entry_t *desc;
219 err = nicvf_alloc_q_desc_mem(nic, &rbdr->dmem, ring_len,
220 sizeof(struct rbdr_entry_t),
221 NICVF_RCV_BUF_ALIGN_BYTES);
225 rbdr->desc = rbdr->dmem.base;
226 /* Buffer size has to be in multiples of 128 bytes */
227 rbdr->dma_size = buf_size;
229 rbdr->thresh = RBDR_THRESH;
233 /* Initialize page recycling stuff.
235 * Can't use single buffer per page especially with 64K pages.
236 * On embedded platforms i.e 81xx/83xx available memory itself
237 * is low and minimum ring size of RBDR is 8K, that takes away
240 rbdr->pgcnt = ring_len / (PAGE_SIZE / buf_size);
241 rbdr->pgcnt = roundup_pow_of_two(rbdr->pgcnt);
242 rbdr->pgcache = kzalloc(sizeof(*rbdr->pgcache) *
243 rbdr->pgcnt, GFP_KERNEL);
250 for (idx = 0; idx < ring_len; idx++) {
251 err = nicvf_alloc_rcv_buffer(nic, rbdr, GFP_KERNEL,
252 RCV_FRAG_LEN, &rbuf);
254 /* To free already allocated and mapped ones */
255 rbdr->tail = idx - 1;
259 desc = GET_RBDR_DESC(rbdr, idx);
260 desc->buf_addr = (u64)rbuf & ~(NICVF_RCV_BUF_ALIGN_BYTES - 1);
268 /* Free RBDR ring and its receive buffers */
269 static void nicvf_free_rbdr(struct nicvf *nic, struct rbdr *rbdr)
272 u64 buf_addr, phys_addr;
273 struct pgcache *pgcache;
274 struct rbdr_entry_t *desc;
279 rbdr->enable = false;
280 if (!rbdr->dmem.base)
286 /* Release page references */
287 while (head != tail) {
288 desc = GET_RBDR_DESC(rbdr, head);
289 buf_addr = desc->buf_addr;
290 phys_addr = nicvf_iova_to_phys(nic, buf_addr);
291 dma_unmap_page_attrs(&nic->pdev->dev, buf_addr, RCV_FRAG_LEN,
292 DMA_FROM_DEVICE, DMA_ATTR_SKIP_CPU_SYNC);
294 put_page(virt_to_page(phys_to_virt(phys_addr)));
296 head &= (rbdr->dmem.q_len - 1);
298 /* Release buffer of tail desc */
299 desc = GET_RBDR_DESC(rbdr, tail);
300 buf_addr = desc->buf_addr;
301 phys_addr = nicvf_iova_to_phys(nic, buf_addr);
302 dma_unmap_page_attrs(&nic->pdev->dev, buf_addr, RCV_FRAG_LEN,
303 DMA_FROM_DEVICE, DMA_ATTR_SKIP_CPU_SYNC);
305 put_page(virt_to_page(phys_to_virt(phys_addr)));
307 /* Sync page cache info */
310 /* Release additional page references held for recycling */
312 while (head < rbdr->pgcnt) {
313 pgcache = &rbdr->pgcache[head];
314 if (pgcache->page && page_ref_count(pgcache->page) != 0)
315 put_page(pgcache->page);
320 nicvf_free_q_desc_mem(nic, &rbdr->dmem);
323 /* Refill receive buffer descriptors with new buffers.
325 static void nicvf_refill_rbdr(struct nicvf *nic, gfp_t gfp)
327 struct queue_set *qs = nic->qs;
328 int rbdr_idx = qs->rbdr_cnt;
332 struct rbdr_entry_t *desc;
340 rbdr = &qs->rbdr[rbdr_idx];
341 /* Check if it's enabled */
345 /* Get no of desc's to be refilled */
346 qcount = nicvf_queue_reg_read(nic, NIC_QSET_RBDR_0_1_STATUS0, rbdr_idx);
348 /* Doorbell can be ringed with a max of ring size minus 1 */
349 if (qcount >= (qs->rbdr_len - 1))
352 refill_rb_cnt = qs->rbdr_len - qcount - 1;
354 /* Sync page cache info */
357 /* Start filling descs from tail */
358 tail = nicvf_queue_reg_read(nic, NIC_QSET_RBDR_0_1_TAIL, rbdr_idx) >> 3;
359 while (refill_rb_cnt) {
361 tail &= (rbdr->dmem.q_len - 1);
363 if (nicvf_alloc_rcv_buffer(nic, rbdr, gfp, RCV_FRAG_LEN, &rbuf))
366 desc = GET_RBDR_DESC(rbdr, tail);
367 desc->buf_addr = (u64)rbuf & ~(NICVF_RCV_BUF_ALIGN_BYTES - 1);
374 /* make sure all memory stores are done before ringing doorbell */
377 /* Check if buffer allocation failed */
379 nic->rb_alloc_fail = true;
381 nic->rb_alloc_fail = false;
384 nicvf_queue_reg_write(nic, NIC_QSET_RBDR_0_1_DOOR,
387 /* Re-enable RBDR interrupts only if buffer allocation is success */
388 if (!nic->rb_alloc_fail && rbdr->enable &&
389 netif_running(nic->pnicvf->netdev))
390 nicvf_enable_intr(nic, NICVF_INTR_RBDR, rbdr_idx);
396 /* Alloc rcv buffers in non-atomic mode for better success */
397 void nicvf_rbdr_work(struct work_struct *work)
399 struct nicvf *nic = container_of(work, struct nicvf, rbdr_work.work);
401 nicvf_refill_rbdr(nic, GFP_KERNEL);
402 if (nic->rb_alloc_fail)
403 schedule_delayed_work(&nic->rbdr_work, msecs_to_jiffies(10));
405 nic->rb_work_scheduled = false;
408 /* In Softirq context, alloc rcv buffers in atomic mode */
409 void nicvf_rbdr_task(unsigned long data)
411 struct nicvf *nic = (struct nicvf *)data;
413 nicvf_refill_rbdr(nic, GFP_ATOMIC);
414 if (nic->rb_alloc_fail) {
415 nic->rb_work_scheduled = true;
416 schedule_delayed_work(&nic->rbdr_work, msecs_to_jiffies(10));
420 /* Initialize completion queue */
421 static int nicvf_init_cmp_queue(struct nicvf *nic,
422 struct cmp_queue *cq, int q_len)
426 err = nicvf_alloc_q_desc_mem(nic, &cq->dmem, q_len, CMP_QUEUE_DESC_SIZE,
427 NICVF_CQ_BASE_ALIGN_BYTES);
431 cq->desc = cq->dmem.base;
432 cq->thresh = pass1_silicon(nic->pdev) ? 0 : CMP_QUEUE_CQE_THRESH;
433 nic->cq_coalesce_usecs = (CMP_QUEUE_TIMER_THRESH * 0.05) - 1;
438 static void nicvf_free_cmp_queue(struct nicvf *nic, struct cmp_queue *cq)
445 nicvf_free_q_desc_mem(nic, &cq->dmem);
448 /* Initialize transmit queue */
449 static int nicvf_init_snd_queue(struct nicvf *nic,
450 struct snd_queue *sq, int q_len)
454 err = nicvf_alloc_q_desc_mem(nic, &sq->dmem, q_len, SND_QUEUE_DESC_SIZE,
455 NICVF_SQ_BASE_ALIGN_BYTES);
459 sq->desc = sq->dmem.base;
460 sq->skbuff = kcalloc(q_len, sizeof(u64), GFP_KERNEL);
465 atomic_set(&sq->free_cnt, q_len - 1);
466 sq->thresh = SND_QUEUE_THRESH;
468 /* Preallocate memory for TSO segment's header */
469 sq->tso_hdrs = dma_alloc_coherent(&nic->pdev->dev,
470 q_len * TSO_HEADER_SIZE,
471 &sq->tso_hdrs_phys, GFP_KERNEL);
478 void nicvf_unmap_sndq_buffers(struct nicvf *nic, struct snd_queue *sq,
479 int hdr_sqe, u8 subdesc_cnt)
482 struct sq_gather_subdesc *gather;
484 /* Unmap DMA mapped skb data buffers */
485 for (idx = 0; idx < subdesc_cnt; idx++) {
487 hdr_sqe &= (sq->dmem.q_len - 1);
488 gather = (struct sq_gather_subdesc *)GET_SQ_DESC(sq, hdr_sqe);
489 /* HW will ensure data coherency, CPU sync not required */
490 dma_unmap_page_attrs(&nic->pdev->dev, gather->addr,
491 gather->size, DMA_TO_DEVICE,
492 DMA_ATTR_SKIP_CPU_SYNC);
496 static void nicvf_free_snd_queue(struct nicvf *nic, struct snd_queue *sq)
499 struct sq_hdr_subdesc *hdr;
500 struct sq_hdr_subdesc *tso_sqe;
508 dma_free_coherent(&nic->pdev->dev,
509 sq->dmem.q_len * TSO_HEADER_SIZE,
510 sq->tso_hdrs, sq->tso_hdrs_phys);
512 /* Free pending skbs in the queue */
514 while (sq->head != sq->tail) {
515 skb = (struct sk_buff *)sq->skbuff[sq->head];
518 hdr = (struct sq_hdr_subdesc *)GET_SQ_DESC(sq, sq->head);
519 /* Check for dummy descriptor used for HW TSO offload on 88xx */
520 if (hdr->dont_send) {
521 /* Get actual TSO descriptors and unmap them */
523 (struct sq_hdr_subdesc *)GET_SQ_DESC(sq, hdr->rsvd2);
524 nicvf_unmap_sndq_buffers(nic, sq, hdr->rsvd2,
525 tso_sqe->subdesc_cnt);
527 nicvf_unmap_sndq_buffers(nic, sq, sq->head,
530 dev_kfree_skb_any(skb);
533 sq->head &= (sq->dmem.q_len - 1);
536 nicvf_free_q_desc_mem(nic, &sq->dmem);
539 static void nicvf_reclaim_snd_queue(struct nicvf *nic,
540 struct queue_set *qs, int qidx)
542 /* Disable send queue */
543 nicvf_queue_reg_write(nic, NIC_QSET_SQ_0_7_CFG, qidx, 0);
544 /* Check if SQ is stopped */
545 if (nicvf_poll_reg(nic, qidx, NIC_QSET_SQ_0_7_STATUS, 21, 1, 0x01))
547 /* Reset send queue */
548 nicvf_queue_reg_write(nic, NIC_QSET_SQ_0_7_CFG, qidx, NICVF_SQ_RESET);
551 static void nicvf_reclaim_rcv_queue(struct nicvf *nic,
552 struct queue_set *qs, int qidx)
554 union nic_mbx mbx = {};
556 /* Make sure all packets in the pipeline are written back into mem */
557 mbx.msg.msg = NIC_MBOX_MSG_RQ_SW_SYNC;
558 nicvf_send_msg_to_pf(nic, &mbx);
561 static void nicvf_reclaim_cmp_queue(struct nicvf *nic,
562 struct queue_set *qs, int qidx)
564 /* Disable timer threshold (doesn't get reset upon CQ reset */
565 nicvf_queue_reg_write(nic, NIC_QSET_CQ_0_7_CFG2, qidx, 0);
566 /* Disable completion queue */
567 nicvf_queue_reg_write(nic, NIC_QSET_CQ_0_7_CFG, qidx, 0);
568 /* Reset completion queue */
569 nicvf_queue_reg_write(nic, NIC_QSET_CQ_0_7_CFG, qidx, NICVF_CQ_RESET);
572 static void nicvf_reclaim_rbdr(struct nicvf *nic,
573 struct rbdr *rbdr, int qidx)
578 /* Save head and tail pointers for feeing up buffers */
579 rbdr->head = nicvf_queue_reg_read(nic,
580 NIC_QSET_RBDR_0_1_HEAD,
582 rbdr->tail = nicvf_queue_reg_read(nic,
583 NIC_QSET_RBDR_0_1_TAIL,
586 /* If RBDR FIFO is in 'FAIL' state then do a reset first
589 fifo_state = nicvf_queue_reg_read(nic, NIC_QSET_RBDR_0_1_STATUS0, qidx);
590 if (((fifo_state >> 62) & 0x03) == 0x3)
591 nicvf_queue_reg_write(nic, NIC_QSET_RBDR_0_1_CFG,
592 qidx, NICVF_RBDR_RESET);
595 nicvf_queue_reg_write(nic, NIC_QSET_RBDR_0_1_CFG, qidx, 0);
596 if (nicvf_poll_reg(nic, qidx, NIC_QSET_RBDR_0_1_STATUS0, 62, 2, 0x00))
599 tmp = nicvf_queue_reg_read(nic,
600 NIC_QSET_RBDR_0_1_PREFETCH_STATUS,
602 if ((tmp & 0xFFFFFFFF) == ((tmp >> 32) & 0xFFFFFFFF))
604 usleep_range(1000, 2000);
607 netdev_err(nic->netdev,
608 "Failed polling on prefetch status\n");
612 nicvf_queue_reg_write(nic, NIC_QSET_RBDR_0_1_CFG,
613 qidx, NICVF_RBDR_RESET);
615 if (nicvf_poll_reg(nic, qidx, NIC_QSET_RBDR_0_1_STATUS0, 62, 2, 0x02))
617 nicvf_queue_reg_write(nic, NIC_QSET_RBDR_0_1_CFG, qidx, 0x00);
618 if (nicvf_poll_reg(nic, qidx, NIC_QSET_RBDR_0_1_STATUS0, 62, 2, 0x00))
622 void nicvf_config_vlan_stripping(struct nicvf *nic, netdev_features_t features)
627 rq_cfg = nicvf_queue_reg_read(nic, NIC_QSET_RQ_GEN_CFG, 0);
629 /* Enable first VLAN stripping */
630 if (features & NETIF_F_HW_VLAN_CTAG_RX)
631 rq_cfg |= (1ULL << 25);
633 rq_cfg &= ~(1ULL << 25);
634 nicvf_queue_reg_write(nic, NIC_QSET_RQ_GEN_CFG, 0, rq_cfg);
636 /* Configure Secondary Qsets, if any */
637 for (sqs = 0; sqs < nic->sqs_count; sqs++)
638 if (nic->snicvf[sqs])
639 nicvf_queue_reg_write(nic->snicvf[sqs],
640 NIC_QSET_RQ_GEN_CFG, 0, rq_cfg);
643 static void nicvf_reset_rcv_queue_stats(struct nicvf *nic)
645 union nic_mbx mbx = {};
647 /* Reset all RQ/SQ and VF stats */
648 mbx.reset_stat.msg = NIC_MBOX_MSG_RESET_STAT_COUNTER;
649 mbx.reset_stat.rx_stat_mask = 0x3FFF;
650 mbx.reset_stat.tx_stat_mask = 0x1F;
651 mbx.reset_stat.rq_stat_mask = 0xFFFF;
652 mbx.reset_stat.sq_stat_mask = 0xFFFF;
653 nicvf_send_msg_to_pf(nic, &mbx);
656 /* Configures receive queue */
657 static void nicvf_rcv_queue_config(struct nicvf *nic, struct queue_set *qs,
658 int qidx, bool enable)
660 union nic_mbx mbx = {};
661 struct rcv_queue *rq;
662 struct rq_cfg rq_cfg;
667 /* Disable receive queue */
668 nicvf_queue_reg_write(nic, NIC_QSET_RQ_0_7_CFG, qidx, 0);
671 nicvf_reclaim_rcv_queue(nic, qs, qidx);
675 rq->cq_qs = qs->vnic_id;
677 rq->start_rbdr_qs = qs->vnic_id;
678 rq->start_qs_rbdr_idx = qs->rbdr_cnt - 1;
679 rq->cont_rbdr_qs = qs->vnic_id;
680 rq->cont_qs_rbdr_idx = qs->rbdr_cnt - 1;
681 /* all writes of RBDR data to be loaded into L2 Cache as well*/
684 /* Send a mailbox msg to PF to config RQ */
685 mbx.rq.msg = NIC_MBOX_MSG_RQ_CFG;
686 mbx.rq.qs_num = qs->vnic_id;
687 mbx.rq.rq_num = qidx;
688 mbx.rq.cfg = (rq->caching << 26) | (rq->cq_qs << 19) |
689 (rq->cq_idx << 16) | (rq->cont_rbdr_qs << 9) |
690 (rq->cont_qs_rbdr_idx << 8) |
691 (rq->start_rbdr_qs << 1) | (rq->start_qs_rbdr_idx);
692 nicvf_send_msg_to_pf(nic, &mbx);
694 mbx.rq.msg = NIC_MBOX_MSG_RQ_BP_CFG;
695 mbx.rq.cfg = BIT_ULL(63) | BIT_ULL(62) |
696 (RQ_PASS_RBDR_LVL << 16) | (RQ_PASS_CQ_LVL << 8) |
698 nicvf_send_msg_to_pf(nic, &mbx);
701 * Enable CQ drop to reserve sufficient CQEs for all tx packets
703 mbx.rq.msg = NIC_MBOX_MSG_RQ_DROP_CFG;
704 mbx.rq.cfg = BIT_ULL(63) | BIT_ULL(62) |
705 (RQ_PASS_RBDR_LVL << 40) | (RQ_DROP_RBDR_LVL << 32) |
706 (RQ_PASS_CQ_LVL << 16) | (RQ_DROP_CQ_LVL << 8);
707 nicvf_send_msg_to_pf(nic, &mbx);
709 if (!nic->sqs_mode && (qidx == 0)) {
710 /* Enable checking L3/L4 length and TCP/UDP checksums
711 * Also allow IPv6 pkts with zero UDP checksum.
713 nicvf_queue_reg_write(nic, NIC_QSET_RQ_GEN_CFG, 0,
714 (BIT(24) | BIT(23) | BIT(21) | BIT(20)));
715 nicvf_config_vlan_stripping(nic, nic->netdev->features);
718 /* Enable Receive queue */
719 memset(&rq_cfg, 0, sizeof(struct rq_cfg));
722 nicvf_queue_reg_write(nic, NIC_QSET_RQ_0_7_CFG, qidx, *(u64 *)&rq_cfg);
725 /* Configures completion queue */
726 void nicvf_cmp_queue_config(struct nicvf *nic, struct queue_set *qs,
727 int qidx, bool enable)
729 struct cmp_queue *cq;
730 struct cq_cfg cq_cfg;
736 nicvf_reclaim_cmp_queue(nic, qs, qidx);
740 /* Reset completion queue */
741 nicvf_queue_reg_write(nic, NIC_QSET_CQ_0_7_CFG, qidx, NICVF_CQ_RESET);
746 spin_lock_init(&cq->lock);
747 /* Set completion queue base address */
748 nicvf_queue_reg_write(nic, NIC_QSET_CQ_0_7_BASE,
749 qidx, (u64)(cq->dmem.phys_base));
751 /* Enable Completion queue */
752 memset(&cq_cfg, 0, sizeof(struct cq_cfg));
756 cq_cfg.qsize = ilog2(qs->cq_len >> 10);
758 nicvf_queue_reg_write(nic, NIC_QSET_CQ_0_7_CFG, qidx, *(u64 *)&cq_cfg);
760 /* Set threshold value for interrupt generation */
761 nicvf_queue_reg_write(nic, NIC_QSET_CQ_0_7_THRESH, qidx, cq->thresh);
762 nicvf_queue_reg_write(nic, NIC_QSET_CQ_0_7_CFG2,
763 qidx, CMP_QUEUE_TIMER_THRESH);
766 /* Configures transmit queue */
767 static void nicvf_snd_queue_config(struct nicvf *nic, struct queue_set *qs,
768 int qidx, bool enable)
770 union nic_mbx mbx = {};
771 struct snd_queue *sq;
772 struct sq_cfg sq_cfg;
778 nicvf_reclaim_snd_queue(nic, qs, qidx);
782 /* Reset send queue */
783 nicvf_queue_reg_write(nic, NIC_QSET_SQ_0_7_CFG, qidx, NICVF_SQ_RESET);
785 sq->cq_qs = qs->vnic_id;
788 /* Send a mailbox msg to PF to config SQ */
789 mbx.sq.msg = NIC_MBOX_MSG_SQ_CFG;
790 mbx.sq.qs_num = qs->vnic_id;
791 mbx.sq.sq_num = qidx;
792 mbx.sq.sqs_mode = nic->sqs_mode;
793 mbx.sq.cfg = (sq->cq_qs << 3) | sq->cq_idx;
794 nicvf_send_msg_to_pf(nic, &mbx);
796 /* Set queue base address */
797 nicvf_queue_reg_write(nic, NIC_QSET_SQ_0_7_BASE,
798 qidx, (u64)(sq->dmem.phys_base));
800 /* Enable send queue & set queue size */
801 memset(&sq_cfg, 0, sizeof(struct sq_cfg));
805 sq_cfg.qsize = ilog2(qs->sq_len >> 10);
806 sq_cfg.tstmp_bgx_intf = 0;
807 /* CQ's level at which HW will stop processing SQEs to avoid
808 * transmitting a pkt with no space in CQ to post CQE_TX.
810 sq_cfg.cq_limit = (CMP_QUEUE_PIPELINE_RSVD * 256) / qs->cq_len;
811 nicvf_queue_reg_write(nic, NIC_QSET_SQ_0_7_CFG, qidx, *(u64 *)&sq_cfg);
813 /* Set threshold value for interrupt generation */
814 nicvf_queue_reg_write(nic, NIC_QSET_SQ_0_7_THRESH, qidx, sq->thresh);
816 /* Set queue:cpu affinity for better load distribution */
817 if (cpu_online(qidx)) {
818 cpumask_set_cpu(qidx, &sq->affinity_mask);
819 netif_set_xps_queue(nic->netdev,
820 &sq->affinity_mask, qidx);
824 /* Configures receive buffer descriptor ring */
825 static void nicvf_rbdr_config(struct nicvf *nic, struct queue_set *qs,
826 int qidx, bool enable)
829 struct rbdr_cfg rbdr_cfg;
831 rbdr = &qs->rbdr[qidx];
832 nicvf_reclaim_rbdr(nic, rbdr, qidx);
836 /* Set descriptor base address */
837 nicvf_queue_reg_write(nic, NIC_QSET_RBDR_0_1_BASE,
838 qidx, (u64)(rbdr->dmem.phys_base));
840 /* Enable RBDR & set queue size */
841 /* Buffer size should be in multiples of 128 bytes */
842 memset(&rbdr_cfg, 0, sizeof(struct rbdr_cfg));
846 rbdr_cfg.qsize = RBDR_SIZE;
847 rbdr_cfg.avg_con = 0;
848 rbdr_cfg.lines = rbdr->dma_size / 128;
849 nicvf_queue_reg_write(nic, NIC_QSET_RBDR_0_1_CFG,
850 qidx, *(u64 *)&rbdr_cfg);
853 nicvf_queue_reg_write(nic, NIC_QSET_RBDR_0_1_DOOR,
854 qidx, qs->rbdr_len - 1);
856 /* Set threshold value for interrupt generation */
857 nicvf_queue_reg_write(nic, NIC_QSET_RBDR_0_1_THRESH,
858 qidx, rbdr->thresh - 1);
861 /* Requests PF to assign and enable Qset */
862 void nicvf_qset_config(struct nicvf *nic, bool enable)
864 union nic_mbx mbx = {};
865 struct queue_set *qs = nic->qs;
866 struct qs_cfg *qs_cfg;
869 netdev_warn(nic->netdev,
870 "Qset is still not allocated, don't init queues\n");
875 qs->vnic_id = nic->vf_id;
877 /* Send a mailbox msg to PF to config Qset */
878 mbx.qs.msg = NIC_MBOX_MSG_QS_CFG;
879 mbx.qs.num = qs->vnic_id;
880 mbx.qs.sqs_count = nic->sqs_count;
883 qs_cfg = (struct qs_cfg *)&mbx.qs.cfg;
889 qs_cfg->vnic = qs->vnic_id;
891 nicvf_send_msg_to_pf(nic, &mbx);
894 static void nicvf_free_resources(struct nicvf *nic)
897 struct queue_set *qs = nic->qs;
899 /* Free receive buffer descriptor ring */
900 for (qidx = 0; qidx < qs->rbdr_cnt; qidx++)
901 nicvf_free_rbdr(nic, &qs->rbdr[qidx]);
903 /* Free completion queue */
904 for (qidx = 0; qidx < qs->cq_cnt; qidx++)
905 nicvf_free_cmp_queue(nic, &qs->cq[qidx]);
907 /* Free send queue */
908 for (qidx = 0; qidx < qs->sq_cnt; qidx++)
909 nicvf_free_snd_queue(nic, &qs->sq[qidx]);
912 static int nicvf_alloc_resources(struct nicvf *nic)
915 struct queue_set *qs = nic->qs;
917 /* Alloc receive buffer descriptor ring */
918 for (qidx = 0; qidx < qs->rbdr_cnt; qidx++) {
919 if (nicvf_init_rbdr(nic, &qs->rbdr[qidx], qs->rbdr_len,
924 /* Alloc send queue */
925 for (qidx = 0; qidx < qs->sq_cnt; qidx++) {
926 if (nicvf_init_snd_queue(nic, &qs->sq[qidx], qs->sq_len))
930 /* Alloc completion queue */
931 for (qidx = 0; qidx < qs->cq_cnt; qidx++) {
932 if (nicvf_init_cmp_queue(nic, &qs->cq[qidx], qs->cq_len))
938 nicvf_free_resources(nic);
942 int nicvf_set_qset_resources(struct nicvf *nic)
944 struct queue_set *qs;
946 qs = devm_kzalloc(&nic->pdev->dev, sizeof(*qs), GFP_KERNEL);
951 /* Set count of each queue */
952 qs->rbdr_cnt = DEFAULT_RBDR_CNT;
953 qs->rq_cnt = min_t(u8, MAX_RCV_QUEUES_PER_QS, num_online_cpus());
954 qs->sq_cnt = min_t(u8, MAX_SND_QUEUES_PER_QS, num_online_cpus());
955 qs->cq_cnt = max_t(u8, qs->rq_cnt, qs->sq_cnt);
957 /* Set queue lengths */
958 qs->rbdr_len = RCV_BUF_COUNT;
959 qs->sq_len = SND_QUEUE_LEN;
960 qs->cq_len = CMP_QUEUE_LEN;
962 nic->rx_queues = qs->rq_cnt;
963 nic->tx_queues = qs->sq_cnt;
968 int nicvf_config_data_transfer(struct nicvf *nic, bool enable)
970 bool disable = false;
971 struct queue_set *qs = nic->qs;
972 struct queue_set *pqs = nic->pnicvf->qs;
978 /* Take primary VF's queue lengths.
979 * This is needed to take queue lengths set from ethtool
980 * into consideration.
982 if (nic->sqs_mode && pqs) {
983 qs->cq_len = pqs->cq_len;
984 qs->sq_len = pqs->sq_len;
988 if (nicvf_alloc_resources(nic))
991 for (qidx = 0; qidx < qs->sq_cnt; qidx++)
992 nicvf_snd_queue_config(nic, qs, qidx, enable);
993 for (qidx = 0; qidx < qs->cq_cnt; qidx++)
994 nicvf_cmp_queue_config(nic, qs, qidx, enable);
995 for (qidx = 0; qidx < qs->rbdr_cnt; qidx++)
996 nicvf_rbdr_config(nic, qs, qidx, enable);
997 for (qidx = 0; qidx < qs->rq_cnt; qidx++)
998 nicvf_rcv_queue_config(nic, qs, qidx, enable);
1000 for (qidx = 0; qidx < qs->rq_cnt; qidx++)
1001 nicvf_rcv_queue_config(nic, qs, qidx, disable);
1002 for (qidx = 0; qidx < qs->rbdr_cnt; qidx++)
1003 nicvf_rbdr_config(nic, qs, qidx, disable);
1004 for (qidx = 0; qidx < qs->sq_cnt; qidx++)
1005 nicvf_snd_queue_config(nic, qs, qidx, disable);
1006 for (qidx = 0; qidx < qs->cq_cnt; qidx++)
1007 nicvf_cmp_queue_config(nic, qs, qidx, disable);
1009 nicvf_free_resources(nic);
1012 /* Reset RXQ's stats.
1013 * SQ's stats will get reset automatically once SQ is reset.
1015 nicvf_reset_rcv_queue_stats(nic);
1020 /* Get a free desc from SQ
1021 * returns descriptor ponter & descriptor number
1023 static inline int nicvf_get_sq_desc(struct snd_queue *sq, int desc_cnt)
1028 atomic_sub(desc_cnt, &sq->free_cnt);
1029 sq->tail += desc_cnt;
1030 sq->tail &= (sq->dmem.q_len - 1);
1035 /* Rollback to previous tail pointer when descriptors not used */
1036 static inline void nicvf_rollback_sq_desc(struct snd_queue *sq,
1037 int qentry, int desc_cnt)
1040 atomic_add(desc_cnt, &sq->free_cnt);
1043 /* Free descriptor back to SQ for future use */
1044 void nicvf_put_sq_desc(struct snd_queue *sq, int desc_cnt)
1046 atomic_add(desc_cnt, &sq->free_cnt);
1047 sq->head += desc_cnt;
1048 sq->head &= (sq->dmem.q_len - 1);
1051 static inline int nicvf_get_nxt_sqentry(struct snd_queue *sq, int qentry)
1054 qentry &= (sq->dmem.q_len - 1);
1058 void nicvf_sq_enable(struct nicvf *nic, struct snd_queue *sq, int qidx)
1062 sq_cfg = nicvf_queue_reg_read(nic, NIC_QSET_SQ_0_7_CFG, qidx);
1063 sq_cfg |= NICVF_SQ_EN;
1064 nicvf_queue_reg_write(nic, NIC_QSET_SQ_0_7_CFG, qidx, sq_cfg);
1065 /* Ring doorbell so that H/W restarts processing SQEs */
1066 nicvf_queue_reg_write(nic, NIC_QSET_SQ_0_7_DOOR, qidx, 0);
1069 void nicvf_sq_disable(struct nicvf *nic, int qidx)
1073 sq_cfg = nicvf_queue_reg_read(nic, NIC_QSET_SQ_0_7_CFG, qidx);
1074 sq_cfg &= ~NICVF_SQ_EN;
1075 nicvf_queue_reg_write(nic, NIC_QSET_SQ_0_7_CFG, qidx, sq_cfg);
1078 void nicvf_sq_free_used_descs(struct net_device *netdev, struct snd_queue *sq,
1082 struct sk_buff *skb;
1083 struct nicvf *nic = netdev_priv(netdev);
1084 struct sq_hdr_subdesc *hdr;
1086 head = nicvf_queue_reg_read(nic, NIC_QSET_SQ_0_7_HEAD, qidx) >> 4;
1087 tail = nicvf_queue_reg_read(nic, NIC_QSET_SQ_0_7_TAIL, qidx) >> 4;
1088 while (sq->head != head) {
1089 hdr = (struct sq_hdr_subdesc *)GET_SQ_DESC(sq, sq->head);
1090 if (hdr->subdesc_type != SQ_DESC_TYPE_HEADER) {
1091 nicvf_put_sq_desc(sq, 1);
1094 skb = (struct sk_buff *)sq->skbuff[sq->head];
1096 dev_kfree_skb_any(skb);
1097 atomic64_add(1, (atomic64_t *)&netdev->stats.tx_packets);
1098 atomic64_add(hdr->tot_len,
1099 (atomic64_t *)&netdev->stats.tx_bytes);
1100 nicvf_put_sq_desc(sq, hdr->subdesc_cnt + 1);
1104 /* Calculate no of SQ subdescriptors needed to transmit all
1105 * segments of this TSO packet.
1106 * Taken from 'Tilera network driver' with a minor modification.
1108 static int nicvf_tso_count_subdescs(struct sk_buff *skb)
1110 struct skb_shared_info *sh = skb_shinfo(skb);
1111 unsigned int sh_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
1112 unsigned int data_len = skb->len - sh_len;
1113 unsigned int p_len = sh->gso_size;
1114 long f_id = -1; /* id of the current fragment */
1115 long f_size = skb_headlen(skb) - sh_len; /* current fragment size */
1116 long f_used = 0; /* bytes used from the current fragment */
1117 long n; /* size of the current piece of payload */
1121 for (segment = 0; segment < sh->gso_segs; segment++) {
1122 unsigned int p_used = 0;
1124 /* One edesc for header and for each piece of the payload. */
1125 for (num_edescs++; p_used < p_len; num_edescs++) {
1126 /* Advance as needed. */
1127 while (f_used >= f_size) {
1129 f_size = skb_frag_size(&sh->frags[f_id]);
1133 /* Use bytes from the current fragment. */
1135 if (n > f_size - f_used)
1136 n = f_size - f_used;
1141 /* The last segment may be less than gso_size. */
1143 if (data_len < p_len)
1147 /* '+ gso_segs' for SQ_HDR_SUDESCs for each segment */
1148 return num_edescs + sh->gso_segs;
1151 #define POST_CQE_DESC_COUNT 2
1153 /* Get the number of SQ descriptors needed to xmit this skb */
1154 static int nicvf_sq_subdesc_required(struct nicvf *nic, struct sk_buff *skb)
1156 int subdesc_cnt = MIN_SQ_DESC_PER_PKT_XMIT;
1158 if (skb_shinfo(skb)->gso_size && !nic->hw_tso) {
1159 subdesc_cnt = nicvf_tso_count_subdescs(skb);
1163 /* Dummy descriptors to get TSO pkt completion notification */
1164 if (nic->t88 && nic->hw_tso && skb_shinfo(skb)->gso_size)
1165 subdesc_cnt += POST_CQE_DESC_COUNT;
1167 if (skb_shinfo(skb)->nr_frags)
1168 subdesc_cnt += skb_shinfo(skb)->nr_frags;
1173 /* Add SQ HEADER subdescriptor.
1174 * First subdescriptor for every send descriptor.
1177 nicvf_sq_add_hdr_subdesc(struct nicvf *nic, struct snd_queue *sq, int qentry,
1178 int subdesc_cnt, struct sk_buff *skb, int len)
1181 struct sq_hdr_subdesc *hdr;
1188 ip.hdr = skb_network_header(skb);
1189 hdr = (struct sq_hdr_subdesc *)GET_SQ_DESC(sq, qentry);
1190 memset(hdr, 0, SND_QUEUE_DESC_SIZE);
1191 hdr->subdesc_type = SQ_DESC_TYPE_HEADER;
1193 if (nic->t88 && nic->hw_tso && skb_shinfo(skb)->gso_size) {
1194 /* post_cqe = 0, to avoid HW posting a CQE for every TSO
1195 * segment transmitted on 88xx.
1197 hdr->subdesc_cnt = subdesc_cnt - POST_CQE_DESC_COUNT;
1199 sq->skbuff[qentry] = (u64)skb;
1200 /* Enable notification via CQE after processing SQE */
1202 /* No of subdescriptors following this */
1203 hdr->subdesc_cnt = subdesc_cnt;
1207 /* Offload checksum calculation to HW */
1208 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1209 hdr->csum_l3 = 1; /* Enable IP csum calculation */
1210 hdr->l3_offset = skb_network_offset(skb);
1211 hdr->l4_offset = skb_transport_offset(skb);
1213 proto = (ip.v4->version == 4) ? ip.v4->protocol :
1218 hdr->csum_l4 = SEND_L4_CSUM_TCP;
1221 hdr->csum_l4 = SEND_L4_CSUM_UDP;
1224 hdr->csum_l4 = SEND_L4_CSUM_SCTP;
1229 if (nic->hw_tso && skb_shinfo(skb)->gso_size) {
1231 hdr->tso_start = skb_transport_offset(skb) + tcp_hdrlen(skb);
1232 hdr->tso_max_paysize = skb_shinfo(skb)->gso_size;
1233 /* For non-tunneled pkts, point this to L2 ethertype */
1234 hdr->inner_l3_offset = skb_network_offset(skb) - 2;
1235 this_cpu_inc(nic->pnicvf->drv_stats->tx_tso);
1239 /* SQ GATHER subdescriptor
1240 * Must follow HDR descriptor
1242 static inline void nicvf_sq_add_gather_subdesc(struct snd_queue *sq, int qentry,
1245 struct sq_gather_subdesc *gather;
1247 qentry &= (sq->dmem.q_len - 1);
1248 gather = (struct sq_gather_subdesc *)GET_SQ_DESC(sq, qentry);
1250 memset(gather, 0, SND_QUEUE_DESC_SIZE);
1251 gather->subdesc_type = SQ_DESC_TYPE_GATHER;
1252 gather->ld_type = NIC_SEND_LD_TYPE_E_LDD;
1253 gather->size = size;
1254 gather->addr = data;
1257 /* Add HDR + IMMEDIATE subdescriptors right after descriptors of a TSO
1258 * packet so that a CQE is posted as a notifation for transmission of
1261 static inline void nicvf_sq_add_cqe_subdesc(struct snd_queue *sq, int qentry,
1262 int tso_sqe, struct sk_buff *skb)
1264 struct sq_imm_subdesc *imm;
1265 struct sq_hdr_subdesc *hdr;
1267 sq->skbuff[qentry] = (u64)skb;
1269 hdr = (struct sq_hdr_subdesc *)GET_SQ_DESC(sq, qentry);
1270 memset(hdr, 0, SND_QUEUE_DESC_SIZE);
1271 hdr->subdesc_type = SQ_DESC_TYPE_HEADER;
1272 /* Enable notification via CQE after processing SQE */
1274 /* There is no packet to transmit here */
1276 hdr->subdesc_cnt = POST_CQE_DESC_COUNT - 1;
1278 /* Actual TSO header SQE index, needed for cleanup */
1279 hdr->rsvd2 = tso_sqe;
1281 qentry = nicvf_get_nxt_sqentry(sq, qentry);
1282 imm = (struct sq_imm_subdesc *)GET_SQ_DESC(sq, qentry);
1283 memset(imm, 0, SND_QUEUE_DESC_SIZE);
1284 imm->subdesc_type = SQ_DESC_TYPE_IMMEDIATE;
1288 static inline void nicvf_sq_doorbell(struct nicvf *nic, struct sk_buff *skb,
1289 int sq_num, int desc_cnt)
1291 struct netdev_queue *txq;
1293 txq = netdev_get_tx_queue(nic->pnicvf->netdev,
1294 skb_get_queue_mapping(skb));
1296 netdev_tx_sent_queue(txq, skb->len);
1298 /* make sure all memory stores are done before ringing doorbell */
1301 /* Inform HW to xmit all TSO segments */
1302 nicvf_queue_reg_write(nic, NIC_QSET_SQ_0_7_DOOR,
1306 /* Segment a TSO packet into 'gso_size' segments and append
1307 * them to SQ for transfer
1309 static int nicvf_sq_append_tso(struct nicvf *nic, struct snd_queue *sq,
1310 int sq_num, int qentry, struct sk_buff *skb)
1313 int seg_subdescs = 0, desc_cnt = 0;
1314 int seg_len, total_len, data_left;
1315 int hdr_qentry = qentry;
1316 int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
1318 tso_start(skb, &tso);
1319 total_len = skb->len - hdr_len;
1320 while (total_len > 0) {
1323 /* Save Qentry for adding HDR_SUBDESC at the end */
1324 hdr_qentry = qentry;
1326 data_left = min_t(int, skb_shinfo(skb)->gso_size, total_len);
1327 total_len -= data_left;
1329 /* Add segment's header */
1330 qentry = nicvf_get_nxt_sqentry(sq, qentry);
1331 hdr = sq->tso_hdrs + qentry * TSO_HEADER_SIZE;
1332 tso_build_hdr(skb, hdr, &tso, data_left, total_len == 0);
1333 nicvf_sq_add_gather_subdesc(sq, qentry, hdr_len,
1335 qentry * TSO_HEADER_SIZE);
1336 /* HDR_SUDESC + GATHER */
1340 /* Add segment's payload fragments */
1341 while (data_left > 0) {
1344 size = min_t(int, tso.size, data_left);
1346 qentry = nicvf_get_nxt_sqentry(sq, qentry);
1347 nicvf_sq_add_gather_subdesc(sq, qentry, size,
1348 virt_to_phys(tso.data));
1353 tso_build_data(skb, &tso, size);
1355 nicvf_sq_add_hdr_subdesc(nic, sq, hdr_qentry,
1356 seg_subdescs - 1, skb, seg_len);
1357 sq->skbuff[hdr_qentry] = (u64)NULL;
1358 qentry = nicvf_get_nxt_sqentry(sq, qentry);
1360 desc_cnt += seg_subdescs;
1362 /* Save SKB in the last segment for freeing */
1363 sq->skbuff[hdr_qentry] = (u64)skb;
1365 nicvf_sq_doorbell(nic, skb, sq_num, desc_cnt);
1367 this_cpu_inc(nic->pnicvf->drv_stats->tx_tso);
1371 /* Append an skb to a SQ for packet transfer. */
1372 int nicvf_sq_append_skb(struct nicvf *nic, struct snd_queue *sq,
1373 struct sk_buff *skb, u8 sq_num)
1376 int subdesc_cnt, hdr_sqe = 0;
1380 subdesc_cnt = nicvf_sq_subdesc_required(nic, skb);
1381 if (subdesc_cnt > atomic_read(&sq->free_cnt))
1384 qentry = nicvf_get_sq_desc(sq, subdesc_cnt);
1386 /* Check if its a TSO packet */
1387 if (skb_shinfo(skb)->gso_size && !nic->hw_tso)
1388 return nicvf_sq_append_tso(nic, sq, sq_num, qentry, skb);
1390 /* Add SQ header subdesc */
1391 nicvf_sq_add_hdr_subdesc(nic, sq, qentry, subdesc_cnt - 1,
1395 /* Add SQ gather subdescs */
1396 qentry = nicvf_get_nxt_sqentry(sq, qentry);
1397 size = skb_is_nonlinear(skb) ? skb_headlen(skb) : skb->len;
1398 /* HW will ensure data coherency, CPU sync not required */
1399 dma_addr = dma_map_page_attrs(&nic->pdev->dev, virt_to_page(skb->data),
1400 offset_in_page(skb->data), size,
1401 DMA_TO_DEVICE, DMA_ATTR_SKIP_CPU_SYNC);
1402 if (dma_mapping_error(&nic->pdev->dev, dma_addr)) {
1403 nicvf_rollback_sq_desc(sq, qentry, subdesc_cnt);
1407 nicvf_sq_add_gather_subdesc(sq, qentry, size, dma_addr);
1409 /* Check for scattered buffer */
1410 if (!skb_is_nonlinear(skb))
1413 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1414 const struct skb_frag_struct *frag;
1416 frag = &skb_shinfo(skb)->frags[i];
1418 qentry = nicvf_get_nxt_sqentry(sq, qentry);
1419 size = skb_frag_size(frag);
1420 dma_addr = dma_map_page_attrs(&nic->pdev->dev,
1421 skb_frag_page(frag),
1422 frag->page_offset, size,
1424 DMA_ATTR_SKIP_CPU_SYNC);
1425 if (dma_mapping_error(&nic->pdev->dev, dma_addr)) {
1426 /* Free entire chain of mapped buffers
1427 * here 'i' = frags mapped + above mapped skb->data
1429 nicvf_unmap_sndq_buffers(nic, sq, hdr_sqe, i);
1430 nicvf_rollback_sq_desc(sq, qentry, subdesc_cnt);
1433 nicvf_sq_add_gather_subdesc(sq, qentry, size, dma_addr);
1437 if (nic->t88 && skb_shinfo(skb)->gso_size) {
1438 qentry = nicvf_get_nxt_sqentry(sq, qentry);
1439 nicvf_sq_add_cqe_subdesc(sq, qentry, hdr_sqe, skb);
1442 nicvf_sq_doorbell(nic, skb, sq_num, subdesc_cnt);
1447 /* Use original PCI dev for debug log */
1449 netdev_dbg(nic->netdev, "Not enough SQ descriptors to xmit pkt\n");
1453 static inline unsigned frag_num(unsigned i)
1456 return (i & ~3) + 3 - (i & 3);
1462 /* Returns SKB for a received packet */
1463 struct sk_buff *nicvf_get_rcv_skb(struct nicvf *nic, struct cqe_rx_t *cqe_rx)
1466 int payload_len = 0;
1467 struct sk_buff *skb = NULL;
1470 u16 *rb_lens = NULL;
1471 u64 *rb_ptrs = NULL;
1474 rb_lens = (void *)cqe_rx + (3 * sizeof(u64));
1475 /* Except 88xx pass1 on all other chips CQE_RX2_S is added to
1476 * CQE_RX at word6, hence buffer pointers move by word
1478 * Use existing 'hw_tso' flag which will be set for all chips
1479 * except 88xx pass1 instead of a additional cache line
1480 * access (or miss) by using pci dev's revision.
1483 rb_ptrs = (void *)cqe_rx + (6 * sizeof(u64));
1485 rb_ptrs = (void *)cqe_rx + (7 * sizeof(u64));
1487 for (frag = 0; frag < cqe_rx->rb_cnt; frag++) {
1488 payload_len = rb_lens[frag_num(frag)];
1489 phys_addr = nicvf_iova_to_phys(nic, *rb_ptrs);
1492 dev_kfree_skb_any(skb);
1497 /* First fragment */
1498 dma_unmap_page_attrs(&nic->pdev->dev,
1499 *rb_ptrs - cqe_rx->align_pad,
1500 RCV_FRAG_LEN, DMA_FROM_DEVICE,
1501 DMA_ATTR_SKIP_CPU_SYNC);
1502 skb = nicvf_rb_ptr_to_skb(nic,
1503 phys_addr - cqe_rx->align_pad,
1507 skb_reserve(skb, cqe_rx->align_pad);
1508 skb_put(skb, payload_len);
1511 dma_unmap_page_attrs(&nic->pdev->dev, *rb_ptrs,
1512 RCV_FRAG_LEN, DMA_FROM_DEVICE,
1513 DMA_ATTR_SKIP_CPU_SYNC);
1514 page = virt_to_page(phys_to_virt(phys_addr));
1515 offset = phys_to_virt(phys_addr) - page_address(page);
1516 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page,
1517 offset, payload_len, RCV_FRAG_LEN);
1519 /* Next buffer pointer */
1525 static u64 nicvf_int_type_to_mask(int int_type, int q_idx)
1531 reg_val = ((1ULL << q_idx) << NICVF_INTR_CQ_SHIFT);
1534 reg_val = ((1ULL << q_idx) << NICVF_INTR_SQ_SHIFT);
1536 case NICVF_INTR_RBDR:
1537 reg_val = ((1ULL << q_idx) << NICVF_INTR_RBDR_SHIFT);
1539 case NICVF_INTR_PKT_DROP:
1540 reg_val = (1ULL << NICVF_INTR_PKT_DROP_SHIFT);
1542 case NICVF_INTR_TCP_TIMER:
1543 reg_val = (1ULL << NICVF_INTR_TCP_TIMER_SHIFT);
1545 case NICVF_INTR_MBOX:
1546 reg_val = (1ULL << NICVF_INTR_MBOX_SHIFT);
1548 case NICVF_INTR_QS_ERR:
1549 reg_val = (1ULL << NICVF_INTR_QS_ERR_SHIFT);
1558 /* Enable interrupt */
1559 void nicvf_enable_intr(struct nicvf *nic, int int_type, int q_idx)
1561 u64 mask = nicvf_int_type_to_mask(int_type, q_idx);
1564 netdev_dbg(nic->netdev,
1565 "Failed to enable interrupt: unknown type\n");
1568 nicvf_reg_write(nic, NIC_VF_ENA_W1S,
1569 nicvf_reg_read(nic, NIC_VF_ENA_W1S) | mask);
1572 /* Disable interrupt */
1573 void nicvf_disable_intr(struct nicvf *nic, int int_type, int q_idx)
1575 u64 mask = nicvf_int_type_to_mask(int_type, q_idx);
1578 netdev_dbg(nic->netdev,
1579 "Failed to disable interrupt: unknown type\n");
1583 nicvf_reg_write(nic, NIC_VF_ENA_W1C, mask);
1586 /* Clear interrupt */
1587 void nicvf_clear_intr(struct nicvf *nic, int int_type, int q_idx)
1589 u64 mask = nicvf_int_type_to_mask(int_type, q_idx);
1592 netdev_dbg(nic->netdev,
1593 "Failed to clear interrupt: unknown type\n");
1597 nicvf_reg_write(nic, NIC_VF_INT, mask);
1600 /* Check if interrupt is enabled */
1601 int nicvf_is_intr_enabled(struct nicvf *nic, int int_type, int q_idx)
1603 u64 mask = nicvf_int_type_to_mask(int_type, q_idx);
1604 /* If interrupt type is unknown, we treat it disabled. */
1606 netdev_dbg(nic->netdev,
1607 "Failed to check interrupt enable: unknown type\n");
1611 return mask & nicvf_reg_read(nic, NIC_VF_ENA_W1S);
1614 void nicvf_update_rq_stats(struct nicvf *nic, int rq_idx)
1616 struct rcv_queue *rq;
1618 #define GET_RQ_STATS(reg) \
1619 nicvf_reg_read(nic, NIC_QSET_RQ_0_7_STAT_0_1 |\
1620 (rq_idx << NIC_Q_NUM_SHIFT) | (reg << 3))
1622 rq = &nic->qs->rq[rq_idx];
1623 rq->stats.bytes = GET_RQ_STATS(RQ_SQ_STATS_OCTS);
1624 rq->stats.pkts = GET_RQ_STATS(RQ_SQ_STATS_PKTS);
1627 void nicvf_update_sq_stats(struct nicvf *nic, int sq_idx)
1629 struct snd_queue *sq;
1631 #define GET_SQ_STATS(reg) \
1632 nicvf_reg_read(nic, NIC_QSET_SQ_0_7_STAT_0_1 |\
1633 (sq_idx << NIC_Q_NUM_SHIFT) | (reg << 3))
1635 sq = &nic->qs->sq[sq_idx];
1636 sq->stats.bytes = GET_SQ_STATS(RQ_SQ_STATS_OCTS);
1637 sq->stats.pkts = GET_SQ_STATS(RQ_SQ_STATS_PKTS);
1640 /* Check for errors in the receive cmp.queue entry */
1641 int nicvf_check_cqe_rx_errs(struct nicvf *nic, struct cqe_rx_t *cqe_rx)
1643 if (netif_msg_rx_err(nic))
1644 netdev_err(nic->netdev,
1645 "%s: RX error CQE err_level 0x%x err_opcode 0x%x\n",
1647 cqe_rx->err_level, cqe_rx->err_opcode);
1649 switch (cqe_rx->err_opcode) {
1650 case CQ_RX_ERROP_RE_PARTIAL:
1651 this_cpu_inc(nic->drv_stats->rx_bgx_truncated_pkts);
1653 case CQ_RX_ERROP_RE_JABBER:
1654 this_cpu_inc(nic->drv_stats->rx_jabber_errs);
1656 case CQ_RX_ERROP_RE_FCS:
1657 this_cpu_inc(nic->drv_stats->rx_fcs_errs);
1659 case CQ_RX_ERROP_RE_RX_CTL:
1660 this_cpu_inc(nic->drv_stats->rx_bgx_errs);
1662 case CQ_RX_ERROP_PREL2_ERR:
1663 this_cpu_inc(nic->drv_stats->rx_prel2_errs);
1665 case CQ_RX_ERROP_L2_MAL:
1666 this_cpu_inc(nic->drv_stats->rx_l2_hdr_malformed);
1668 case CQ_RX_ERROP_L2_OVERSIZE:
1669 this_cpu_inc(nic->drv_stats->rx_oversize);
1671 case CQ_RX_ERROP_L2_UNDERSIZE:
1672 this_cpu_inc(nic->drv_stats->rx_undersize);
1674 case CQ_RX_ERROP_L2_LENMISM:
1675 this_cpu_inc(nic->drv_stats->rx_l2_len_mismatch);
1677 case CQ_RX_ERROP_L2_PCLP:
1678 this_cpu_inc(nic->drv_stats->rx_l2_pclp);
1680 case CQ_RX_ERROP_IP_NOT:
1681 this_cpu_inc(nic->drv_stats->rx_ip_ver_errs);
1683 case CQ_RX_ERROP_IP_CSUM_ERR:
1684 this_cpu_inc(nic->drv_stats->rx_ip_csum_errs);
1686 case CQ_RX_ERROP_IP_MAL:
1687 this_cpu_inc(nic->drv_stats->rx_ip_hdr_malformed);
1689 case CQ_RX_ERROP_IP_MALD:
1690 this_cpu_inc(nic->drv_stats->rx_ip_payload_malformed);
1692 case CQ_RX_ERROP_IP_HOP:
1693 this_cpu_inc(nic->drv_stats->rx_ip_ttl_errs);
1695 case CQ_RX_ERROP_L3_PCLP:
1696 this_cpu_inc(nic->drv_stats->rx_l3_pclp);
1698 case CQ_RX_ERROP_L4_MAL:
1699 this_cpu_inc(nic->drv_stats->rx_l4_malformed);
1701 case CQ_RX_ERROP_L4_CHK:
1702 this_cpu_inc(nic->drv_stats->rx_l4_csum_errs);
1704 case CQ_RX_ERROP_UDP_LEN:
1705 this_cpu_inc(nic->drv_stats->rx_udp_len_errs);
1707 case CQ_RX_ERROP_L4_PORT:
1708 this_cpu_inc(nic->drv_stats->rx_l4_port_errs);
1710 case CQ_RX_ERROP_TCP_FLAG:
1711 this_cpu_inc(nic->drv_stats->rx_tcp_flag_errs);
1713 case CQ_RX_ERROP_TCP_OFFSET:
1714 this_cpu_inc(nic->drv_stats->rx_tcp_offset_errs);
1716 case CQ_RX_ERROP_L4_PCLP:
1717 this_cpu_inc(nic->drv_stats->rx_l4_pclp);
1719 case CQ_RX_ERROP_RBDR_TRUNC:
1720 this_cpu_inc(nic->drv_stats->rx_truncated_pkts);
1727 /* Check for errors in the send cmp.queue entry */
1728 int nicvf_check_cqe_tx_errs(struct nicvf *nic, struct cqe_send_t *cqe_tx)
1730 switch (cqe_tx->send_status) {
1731 case CQ_TX_ERROP_DESC_FAULT:
1732 this_cpu_inc(nic->drv_stats->tx_desc_fault);
1734 case CQ_TX_ERROP_HDR_CONS_ERR:
1735 this_cpu_inc(nic->drv_stats->tx_hdr_cons_err);
1737 case CQ_TX_ERROP_SUBDC_ERR:
1738 this_cpu_inc(nic->drv_stats->tx_subdesc_err);
1740 case CQ_TX_ERROP_MAX_SIZE_VIOL:
1741 this_cpu_inc(nic->drv_stats->tx_max_size_exceeded);
1743 case CQ_TX_ERROP_IMM_SIZE_OFLOW:
1744 this_cpu_inc(nic->drv_stats->tx_imm_size_oflow);
1746 case CQ_TX_ERROP_DATA_SEQUENCE_ERR:
1747 this_cpu_inc(nic->drv_stats->tx_data_seq_err);
1749 case CQ_TX_ERROP_MEM_SEQUENCE_ERR:
1750 this_cpu_inc(nic->drv_stats->tx_mem_seq_err);
1752 case CQ_TX_ERROP_LOCK_VIOL:
1753 this_cpu_inc(nic->drv_stats->tx_lock_viol);
1755 case CQ_TX_ERROP_DATA_FAULT:
1756 this_cpu_inc(nic->drv_stats->tx_data_fault);
1758 case CQ_TX_ERROP_TSTMP_CONFLICT:
1759 this_cpu_inc(nic->drv_stats->tx_tstmp_conflict);
1761 case CQ_TX_ERROP_TSTMP_TIMEOUT:
1762 this_cpu_inc(nic->drv_stats->tx_tstmp_timeout);
1764 case CQ_TX_ERROP_MEM_FAULT:
1765 this_cpu_inc(nic->drv_stats->tx_mem_fault);
1767 case CQ_TX_ERROP_CK_OVERLAP:
1768 this_cpu_inc(nic->drv_stats->tx_csum_overlap);
1770 case CQ_TX_ERROP_CK_OFLOW:
1771 this_cpu_inc(nic->drv_stats->tx_csum_overflow);