2 * Copyright (C) 2015 Cavium, Inc.
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of version 2 of the GNU General Public License
6 * as published by the Free Software Foundation.
10 #include <linux/netdevice.h>
12 #include <linux/etherdevice.h>
19 #include "nicvf_queues.h"
21 /* Poll a register for a specific value */
22 static int nicvf_poll_reg(struct nicvf *nic, int qidx,
23 u64 reg, int bit_pos, int bits, int val)
29 bit_mask = (1ULL << bits) - 1;
30 bit_mask = (bit_mask << bit_pos);
33 reg_val = nicvf_queue_reg_read(nic, reg, qidx);
34 if (((reg_val & bit_mask) >> bit_pos) == val)
36 usleep_range(1000, 2000);
39 netdev_err(nic->netdev, "Poll on reg 0x%llx failed\n", reg);
43 /* Allocate memory for a queue's descriptors */
44 static int nicvf_alloc_q_desc_mem(struct nicvf *nic, struct q_desc_mem *dmem,
45 int q_len, int desc_size, int align_bytes)
48 dmem->size = (desc_size * q_len) + align_bytes;
49 /* Save address, need it while freeing */
50 dmem->unalign_base = dma_zalloc_coherent(&nic->pdev->dev, dmem->size,
51 &dmem->dma, GFP_KERNEL);
52 if (!dmem->unalign_base)
55 /* Align memory address for 'align_bytes' */
56 dmem->phys_base = NICVF_ALIGNED_ADDR((u64)dmem->dma, align_bytes);
57 dmem->base = dmem->unalign_base + (dmem->phys_base - dmem->dma);
61 /* Free queue's descriptor memory */
62 static void nicvf_free_q_desc_mem(struct nicvf *nic, struct q_desc_mem *dmem)
67 dma_free_coherent(&nic->pdev->dev, dmem->size,
68 dmem->unalign_base, dmem->dma);
69 dmem->unalign_base = NULL;
73 /* Allocate buffer for packet reception
74 * HW returns memory address where packet is DMA'ed but not a pointer
75 * into RBDR ring, so save buffer address at the start of fragment and
76 * align the start address to a cache aligned address
78 static inline int nicvf_alloc_rcv_buffer(struct nicvf *nic, gfp_t gfp,
79 u32 buf_len, u64 **rbuf)
81 int order = (PAGE_SIZE <= 4096) ? PAGE_ALLOC_COSTLY_ORDER : 0;
83 /* Check if request can be accomodated in previous allocated page */
85 if ((nic->rb_page_offset + buf_len + buf_len) >
86 (PAGE_SIZE << order)) {
89 nic->rb_page_offset += buf_len;
90 get_page(nic->rb_page);
94 /* Allocate a new page */
96 nic->rb_page = alloc_pages(gfp | __GFP_COMP | __GFP_NOWARN,
99 nic->drv_stats.rcv_buffer_alloc_failures++;
102 nic->rb_page_offset = 0;
105 *rbuf = (u64 *)((u64)page_address(nic->rb_page) + nic->rb_page_offset);
110 /* Build skb around receive buffer */
111 static struct sk_buff *nicvf_rb_ptr_to_skb(struct nicvf *nic,
117 data = phys_to_virt(rb_ptr);
119 /* Now build an skb to give to stack */
120 skb = build_skb(data, RCV_FRAG_LEN);
122 put_page(virt_to_page(data));
130 /* Allocate RBDR ring and populate receive buffers */
131 static int nicvf_init_rbdr(struct nicvf *nic, struct rbdr *rbdr,
132 int ring_len, int buf_size)
136 struct rbdr_entry_t *desc;
139 err = nicvf_alloc_q_desc_mem(nic, &rbdr->dmem, ring_len,
140 sizeof(struct rbdr_entry_t),
141 NICVF_RCV_BUF_ALIGN_BYTES);
145 rbdr->desc = rbdr->dmem.base;
146 /* Buffer size has to be in multiples of 128 bytes */
147 rbdr->dma_size = buf_size;
149 rbdr->thresh = RBDR_THRESH;
152 for (idx = 0; idx < ring_len; idx++) {
153 err = nicvf_alloc_rcv_buffer(nic, GFP_KERNEL, RCV_FRAG_LEN,
158 desc = GET_RBDR_DESC(rbdr, idx);
159 desc->buf_addr = virt_to_phys(rbuf) >> NICVF_RCV_BUF_ALIGN;
164 /* Free RBDR ring and its receive buffers */
165 static void nicvf_free_rbdr(struct nicvf *nic, struct rbdr *rbdr)
169 struct rbdr_entry_t *desc;
174 rbdr->enable = false;
175 if (!rbdr->dmem.base)
182 while (head != tail) {
183 desc = GET_RBDR_DESC(rbdr, head);
184 buf_addr = desc->buf_addr << NICVF_RCV_BUF_ALIGN;
185 put_page(virt_to_page(phys_to_virt(buf_addr)));
187 head &= (rbdr->dmem.q_len - 1);
189 /* Free SKB of tail desc */
190 desc = GET_RBDR_DESC(rbdr, tail);
191 buf_addr = desc->buf_addr << NICVF_RCV_BUF_ALIGN;
192 put_page(virt_to_page(phys_to_virt(buf_addr)));
195 nicvf_free_q_desc_mem(nic, &rbdr->dmem);
198 /* Refill receive buffer descriptors with new buffers.
200 static void nicvf_refill_rbdr(struct nicvf *nic, gfp_t gfp)
202 struct queue_set *qs = nic->qs;
203 int rbdr_idx = qs->rbdr_cnt;
207 struct rbdr_entry_t *desc;
215 rbdr = &qs->rbdr[rbdr_idx];
216 /* Check if it's enabled */
220 /* Get no of desc's to be refilled */
221 qcount = nicvf_queue_reg_read(nic, NIC_QSET_RBDR_0_1_STATUS0, rbdr_idx);
223 /* Doorbell can be ringed with a max of ring size minus 1 */
224 if (qcount >= (qs->rbdr_len - 1))
227 refill_rb_cnt = qs->rbdr_len - qcount - 1;
229 /* Start filling descs from tail */
230 tail = nicvf_queue_reg_read(nic, NIC_QSET_RBDR_0_1_TAIL, rbdr_idx) >> 3;
231 while (refill_rb_cnt) {
233 tail &= (rbdr->dmem.q_len - 1);
235 if (nicvf_alloc_rcv_buffer(nic, gfp, RCV_FRAG_LEN, &rbuf))
238 desc = GET_RBDR_DESC(rbdr, tail);
239 desc->buf_addr = virt_to_phys(rbuf) >> NICVF_RCV_BUF_ALIGN;
244 /* make sure all memory stores are done before ringing doorbell */
247 /* Check if buffer allocation failed */
249 nic->rb_alloc_fail = true;
251 nic->rb_alloc_fail = false;
254 nicvf_queue_reg_write(nic, NIC_QSET_RBDR_0_1_DOOR,
257 /* Re-enable RBDR interrupts only if buffer allocation is success */
258 if (!nic->rb_alloc_fail && rbdr->enable)
259 nicvf_enable_intr(nic, NICVF_INTR_RBDR, rbdr_idx);
265 /* Alloc rcv buffers in non-atomic mode for better success */
266 void nicvf_rbdr_work(struct work_struct *work)
268 struct nicvf *nic = container_of(work, struct nicvf, rbdr_work.work);
270 nicvf_refill_rbdr(nic, GFP_KERNEL);
271 if (nic->rb_alloc_fail)
272 schedule_delayed_work(&nic->rbdr_work, msecs_to_jiffies(10));
274 nic->rb_work_scheduled = false;
277 /* In Softirq context, alloc rcv buffers in atomic mode */
278 void nicvf_rbdr_task(unsigned long data)
280 struct nicvf *nic = (struct nicvf *)data;
282 nicvf_refill_rbdr(nic, GFP_ATOMIC);
283 if (nic->rb_alloc_fail) {
284 nic->rb_work_scheduled = true;
285 schedule_delayed_work(&nic->rbdr_work, msecs_to_jiffies(10));
289 /* Initialize completion queue */
290 static int nicvf_init_cmp_queue(struct nicvf *nic,
291 struct cmp_queue *cq, int q_len)
295 err = nicvf_alloc_q_desc_mem(nic, &cq->dmem, q_len, CMP_QUEUE_DESC_SIZE,
296 NICVF_CQ_BASE_ALIGN_BYTES);
300 cq->desc = cq->dmem.base;
301 cq->thresh = pass1_silicon(nic->pdev) ? 0 : CMP_QUEUE_CQE_THRESH;
302 nic->cq_coalesce_usecs = (CMP_QUEUE_TIMER_THRESH * 0.05) - 1;
307 static void nicvf_free_cmp_queue(struct nicvf *nic, struct cmp_queue *cq)
314 nicvf_free_q_desc_mem(nic, &cq->dmem);
317 /* Initialize transmit queue */
318 static int nicvf_init_snd_queue(struct nicvf *nic,
319 struct snd_queue *sq, int q_len)
323 err = nicvf_alloc_q_desc_mem(nic, &sq->dmem, q_len, SND_QUEUE_DESC_SIZE,
324 NICVF_SQ_BASE_ALIGN_BYTES);
328 sq->desc = sq->dmem.base;
329 sq->skbuff = kcalloc(q_len, sizeof(u64), GFP_KERNEL);
334 atomic_set(&sq->free_cnt, q_len - 1);
335 sq->thresh = SND_QUEUE_THRESH;
337 /* Preallocate memory for TSO segment's header */
338 sq->tso_hdrs = dma_alloc_coherent(&nic->pdev->dev,
339 q_len * TSO_HEADER_SIZE,
340 &sq->tso_hdrs_phys, GFP_KERNEL);
347 static void nicvf_free_snd_queue(struct nicvf *nic, struct snd_queue *sq)
355 dma_free_coherent(&nic->pdev->dev,
356 sq->dmem.q_len * TSO_HEADER_SIZE,
357 sq->tso_hdrs, sq->tso_hdrs_phys);
360 nicvf_free_q_desc_mem(nic, &sq->dmem);
363 static void nicvf_reclaim_snd_queue(struct nicvf *nic,
364 struct queue_set *qs, int qidx)
366 /* Disable send queue */
367 nicvf_queue_reg_write(nic, NIC_QSET_SQ_0_7_CFG, qidx, 0);
368 /* Check if SQ is stopped */
369 if (nicvf_poll_reg(nic, qidx, NIC_QSET_SQ_0_7_STATUS, 21, 1, 0x01))
371 /* Reset send queue */
372 nicvf_queue_reg_write(nic, NIC_QSET_SQ_0_7_CFG, qidx, NICVF_SQ_RESET);
375 static void nicvf_reclaim_rcv_queue(struct nicvf *nic,
376 struct queue_set *qs, int qidx)
378 union nic_mbx mbx = {};
380 /* Make sure all packets in the pipeline are written back into mem */
381 mbx.msg.msg = NIC_MBOX_MSG_RQ_SW_SYNC;
382 nicvf_send_msg_to_pf(nic, &mbx);
385 static void nicvf_reclaim_cmp_queue(struct nicvf *nic,
386 struct queue_set *qs, int qidx)
388 /* Disable timer threshold (doesn't get reset upon CQ reset */
389 nicvf_queue_reg_write(nic, NIC_QSET_CQ_0_7_CFG2, qidx, 0);
390 /* Disable completion queue */
391 nicvf_queue_reg_write(nic, NIC_QSET_CQ_0_7_CFG, qidx, 0);
392 /* Reset completion queue */
393 nicvf_queue_reg_write(nic, NIC_QSET_CQ_0_7_CFG, qidx, NICVF_CQ_RESET);
396 static void nicvf_reclaim_rbdr(struct nicvf *nic,
397 struct rbdr *rbdr, int qidx)
402 /* Save head and tail pointers for feeing up buffers */
403 rbdr->head = nicvf_queue_reg_read(nic,
404 NIC_QSET_RBDR_0_1_HEAD,
406 rbdr->tail = nicvf_queue_reg_read(nic,
407 NIC_QSET_RBDR_0_1_TAIL,
410 /* If RBDR FIFO is in 'FAIL' state then do a reset first
413 fifo_state = nicvf_queue_reg_read(nic, NIC_QSET_RBDR_0_1_STATUS0, qidx);
414 if (((fifo_state >> 62) & 0x03) == 0x3)
415 nicvf_queue_reg_write(nic, NIC_QSET_RBDR_0_1_CFG,
416 qidx, NICVF_RBDR_RESET);
419 nicvf_queue_reg_write(nic, NIC_QSET_RBDR_0_1_CFG, qidx, 0);
420 if (nicvf_poll_reg(nic, qidx, NIC_QSET_RBDR_0_1_STATUS0, 62, 2, 0x00))
423 tmp = nicvf_queue_reg_read(nic,
424 NIC_QSET_RBDR_0_1_PREFETCH_STATUS,
426 if ((tmp & 0xFFFFFFFF) == ((tmp >> 32) & 0xFFFFFFFF))
428 usleep_range(1000, 2000);
431 netdev_err(nic->netdev,
432 "Failed polling on prefetch status\n");
436 nicvf_queue_reg_write(nic, NIC_QSET_RBDR_0_1_CFG,
437 qidx, NICVF_RBDR_RESET);
439 if (nicvf_poll_reg(nic, qidx, NIC_QSET_RBDR_0_1_STATUS0, 62, 2, 0x02))
441 nicvf_queue_reg_write(nic, NIC_QSET_RBDR_0_1_CFG, qidx, 0x00);
442 if (nicvf_poll_reg(nic, qidx, NIC_QSET_RBDR_0_1_STATUS0, 62, 2, 0x00))
446 void nicvf_config_vlan_stripping(struct nicvf *nic, netdev_features_t features)
451 rq_cfg = nicvf_queue_reg_read(nic, NIC_QSET_RQ_GEN_CFG, 0);
453 /* Enable first VLAN stripping */
454 if (features & NETIF_F_HW_VLAN_CTAG_RX)
455 rq_cfg |= (1ULL << 25);
457 rq_cfg &= ~(1ULL << 25);
458 nicvf_queue_reg_write(nic, NIC_QSET_RQ_GEN_CFG, 0, rq_cfg);
460 /* Configure Secondary Qsets, if any */
461 for (sqs = 0; sqs < nic->sqs_count; sqs++)
462 if (nic->snicvf[sqs])
463 nicvf_queue_reg_write(nic->snicvf[sqs],
464 NIC_QSET_RQ_GEN_CFG, 0, rq_cfg);
467 /* Configures receive queue */
468 static void nicvf_rcv_queue_config(struct nicvf *nic, struct queue_set *qs,
469 int qidx, bool enable)
471 union nic_mbx mbx = {};
472 struct rcv_queue *rq;
473 struct rq_cfg rq_cfg;
478 /* Disable receive queue */
479 nicvf_queue_reg_write(nic, NIC_QSET_RQ_0_7_CFG, qidx, 0);
482 nicvf_reclaim_rcv_queue(nic, qs, qidx);
486 rq->cq_qs = qs->vnic_id;
488 rq->start_rbdr_qs = qs->vnic_id;
489 rq->start_qs_rbdr_idx = qs->rbdr_cnt - 1;
490 rq->cont_rbdr_qs = qs->vnic_id;
491 rq->cont_qs_rbdr_idx = qs->rbdr_cnt - 1;
492 /* all writes of RBDR data to be loaded into L2 Cache as well*/
495 /* Send a mailbox msg to PF to config RQ */
496 mbx.rq.msg = NIC_MBOX_MSG_RQ_CFG;
497 mbx.rq.qs_num = qs->vnic_id;
498 mbx.rq.rq_num = qidx;
499 mbx.rq.cfg = (rq->caching << 26) | (rq->cq_qs << 19) |
500 (rq->cq_idx << 16) | (rq->cont_rbdr_qs << 9) |
501 (rq->cont_qs_rbdr_idx << 8) |
502 (rq->start_rbdr_qs << 1) | (rq->start_qs_rbdr_idx);
503 nicvf_send_msg_to_pf(nic, &mbx);
505 mbx.rq.msg = NIC_MBOX_MSG_RQ_BP_CFG;
506 mbx.rq.cfg = (1ULL << 63) | (1ULL << 62) | (qs->vnic_id << 0);
507 nicvf_send_msg_to_pf(nic, &mbx);
510 * Enable CQ drop to reserve sufficient CQEs for all tx packets
512 mbx.rq.msg = NIC_MBOX_MSG_RQ_DROP_CFG;
513 mbx.rq.cfg = (1ULL << 62) | (RQ_CQ_DROP << 8);
514 nicvf_send_msg_to_pf(nic, &mbx);
516 nicvf_queue_reg_write(nic, NIC_QSET_RQ_GEN_CFG, 0, 0x00);
518 nicvf_config_vlan_stripping(nic, nic->netdev->features);
520 /* Enable Receive queue */
523 nicvf_queue_reg_write(nic, NIC_QSET_RQ_0_7_CFG, qidx, *(u64 *)&rq_cfg);
526 /* Configures completion queue */
527 void nicvf_cmp_queue_config(struct nicvf *nic, struct queue_set *qs,
528 int qidx, bool enable)
530 struct cmp_queue *cq;
531 struct cq_cfg cq_cfg;
537 nicvf_reclaim_cmp_queue(nic, qs, qidx);
541 /* Reset completion queue */
542 nicvf_queue_reg_write(nic, NIC_QSET_CQ_0_7_CFG, qidx, NICVF_CQ_RESET);
547 spin_lock_init(&cq->lock);
548 /* Set completion queue base address */
549 nicvf_queue_reg_write(nic, NIC_QSET_CQ_0_7_BASE,
550 qidx, (u64)(cq->dmem.phys_base));
552 /* Enable Completion queue */
556 cq_cfg.qsize = CMP_QSIZE;
558 nicvf_queue_reg_write(nic, NIC_QSET_CQ_0_7_CFG, qidx, *(u64 *)&cq_cfg);
560 /* Set threshold value for interrupt generation */
561 nicvf_queue_reg_write(nic, NIC_QSET_CQ_0_7_THRESH, qidx, cq->thresh);
562 nicvf_queue_reg_write(nic, NIC_QSET_CQ_0_7_CFG2,
563 qidx, CMP_QUEUE_TIMER_THRESH);
566 /* Configures transmit queue */
567 static void nicvf_snd_queue_config(struct nicvf *nic, struct queue_set *qs,
568 int qidx, bool enable)
570 union nic_mbx mbx = {};
571 struct snd_queue *sq;
572 struct sq_cfg sq_cfg;
578 nicvf_reclaim_snd_queue(nic, qs, qidx);
582 /* Reset send queue */
583 nicvf_queue_reg_write(nic, NIC_QSET_SQ_0_7_CFG, qidx, NICVF_SQ_RESET);
585 sq->cq_qs = qs->vnic_id;
588 /* Send a mailbox msg to PF to config SQ */
589 mbx.sq.msg = NIC_MBOX_MSG_SQ_CFG;
590 mbx.sq.qs_num = qs->vnic_id;
591 mbx.sq.sq_num = qidx;
592 mbx.sq.sqs_mode = nic->sqs_mode;
593 mbx.sq.cfg = (sq->cq_qs << 3) | sq->cq_idx;
594 nicvf_send_msg_to_pf(nic, &mbx);
596 /* Set queue base address */
597 nicvf_queue_reg_write(nic, NIC_QSET_SQ_0_7_BASE,
598 qidx, (u64)(sq->dmem.phys_base));
600 /* Enable send queue & set queue size */
604 sq_cfg.qsize = SND_QSIZE;
605 sq_cfg.tstmp_bgx_intf = 0;
606 nicvf_queue_reg_write(nic, NIC_QSET_SQ_0_7_CFG, qidx, *(u64 *)&sq_cfg);
608 /* Set threshold value for interrupt generation */
609 nicvf_queue_reg_write(nic, NIC_QSET_SQ_0_7_THRESH, qidx, sq->thresh);
611 /* Set queue:cpu affinity for better load distribution */
612 if (cpu_online(qidx)) {
613 cpumask_set_cpu(qidx, &sq->affinity_mask);
614 netif_set_xps_queue(nic->netdev,
615 &sq->affinity_mask, qidx);
619 /* Configures receive buffer descriptor ring */
620 static void nicvf_rbdr_config(struct nicvf *nic, struct queue_set *qs,
621 int qidx, bool enable)
624 struct rbdr_cfg rbdr_cfg;
626 rbdr = &qs->rbdr[qidx];
627 nicvf_reclaim_rbdr(nic, rbdr, qidx);
631 /* Set descriptor base address */
632 nicvf_queue_reg_write(nic, NIC_QSET_RBDR_0_1_BASE,
633 qidx, (u64)(rbdr->dmem.phys_base));
635 /* Enable RBDR & set queue size */
636 /* Buffer size should be in multiples of 128 bytes */
640 rbdr_cfg.qsize = RBDR_SIZE;
641 rbdr_cfg.avg_con = 0;
642 rbdr_cfg.lines = rbdr->dma_size / 128;
643 nicvf_queue_reg_write(nic, NIC_QSET_RBDR_0_1_CFG,
644 qidx, *(u64 *)&rbdr_cfg);
647 nicvf_queue_reg_write(nic, NIC_QSET_RBDR_0_1_DOOR,
648 qidx, qs->rbdr_len - 1);
650 /* Set threshold value for interrupt generation */
651 nicvf_queue_reg_write(nic, NIC_QSET_RBDR_0_1_THRESH,
652 qidx, rbdr->thresh - 1);
655 /* Requests PF to assign and enable Qset */
656 void nicvf_qset_config(struct nicvf *nic, bool enable)
658 union nic_mbx mbx = {};
659 struct queue_set *qs = nic->qs;
660 struct qs_cfg *qs_cfg;
663 netdev_warn(nic->netdev,
664 "Qset is still not allocated, don't init queues\n");
669 qs->vnic_id = nic->vf_id;
671 /* Send a mailbox msg to PF to config Qset */
672 mbx.qs.msg = NIC_MBOX_MSG_QS_CFG;
673 mbx.qs.num = qs->vnic_id;
674 mbx.qs.sqs_count = nic->sqs_count;
677 qs_cfg = (struct qs_cfg *)&mbx.qs.cfg;
683 qs_cfg->vnic = qs->vnic_id;
685 nicvf_send_msg_to_pf(nic, &mbx);
688 static void nicvf_free_resources(struct nicvf *nic)
691 struct queue_set *qs = nic->qs;
693 /* Free receive buffer descriptor ring */
694 for (qidx = 0; qidx < qs->rbdr_cnt; qidx++)
695 nicvf_free_rbdr(nic, &qs->rbdr[qidx]);
697 /* Free completion queue */
698 for (qidx = 0; qidx < qs->cq_cnt; qidx++)
699 nicvf_free_cmp_queue(nic, &qs->cq[qidx]);
701 /* Free send queue */
702 for (qidx = 0; qidx < qs->sq_cnt; qidx++)
703 nicvf_free_snd_queue(nic, &qs->sq[qidx]);
706 static int nicvf_alloc_resources(struct nicvf *nic)
709 struct queue_set *qs = nic->qs;
711 /* Alloc receive buffer descriptor ring */
712 for (qidx = 0; qidx < qs->rbdr_cnt; qidx++) {
713 if (nicvf_init_rbdr(nic, &qs->rbdr[qidx], qs->rbdr_len,
718 /* Alloc send queue */
719 for (qidx = 0; qidx < qs->sq_cnt; qidx++) {
720 if (nicvf_init_snd_queue(nic, &qs->sq[qidx], qs->sq_len))
724 /* Alloc completion queue */
725 for (qidx = 0; qidx < qs->cq_cnt; qidx++) {
726 if (nicvf_init_cmp_queue(nic, &qs->cq[qidx], qs->cq_len))
732 nicvf_free_resources(nic);
736 int nicvf_set_qset_resources(struct nicvf *nic)
738 struct queue_set *qs;
740 qs = devm_kzalloc(&nic->pdev->dev, sizeof(*qs), GFP_KERNEL);
745 /* Set count of each queue */
746 qs->rbdr_cnt = RBDR_CNT;
747 qs->rq_cnt = RCV_QUEUE_CNT;
748 qs->sq_cnt = SND_QUEUE_CNT;
749 qs->cq_cnt = CMP_QUEUE_CNT;
751 /* Set queue lengths */
752 qs->rbdr_len = RCV_BUF_COUNT;
753 qs->sq_len = SND_QUEUE_LEN;
754 qs->cq_len = CMP_QUEUE_LEN;
756 nic->rx_queues = qs->rq_cnt;
757 nic->tx_queues = qs->sq_cnt;
762 int nicvf_config_data_transfer(struct nicvf *nic, bool enable)
764 bool disable = false;
765 struct queue_set *qs = nic->qs;
772 if (nicvf_alloc_resources(nic))
775 for (qidx = 0; qidx < qs->sq_cnt; qidx++)
776 nicvf_snd_queue_config(nic, qs, qidx, enable);
777 for (qidx = 0; qidx < qs->cq_cnt; qidx++)
778 nicvf_cmp_queue_config(nic, qs, qidx, enable);
779 for (qidx = 0; qidx < qs->rbdr_cnt; qidx++)
780 nicvf_rbdr_config(nic, qs, qidx, enable);
781 for (qidx = 0; qidx < qs->rq_cnt; qidx++)
782 nicvf_rcv_queue_config(nic, qs, qidx, enable);
784 for (qidx = 0; qidx < qs->rq_cnt; qidx++)
785 nicvf_rcv_queue_config(nic, qs, qidx, disable);
786 for (qidx = 0; qidx < qs->rbdr_cnt; qidx++)
787 nicvf_rbdr_config(nic, qs, qidx, disable);
788 for (qidx = 0; qidx < qs->sq_cnt; qidx++)
789 nicvf_snd_queue_config(nic, qs, qidx, disable);
790 for (qidx = 0; qidx < qs->cq_cnt; qidx++)
791 nicvf_cmp_queue_config(nic, qs, qidx, disable);
793 nicvf_free_resources(nic);
799 /* Get a free desc from SQ
800 * returns descriptor ponter & descriptor number
802 static inline int nicvf_get_sq_desc(struct snd_queue *sq, int desc_cnt)
807 atomic_sub(desc_cnt, &sq->free_cnt);
808 sq->tail += desc_cnt;
809 sq->tail &= (sq->dmem.q_len - 1);
814 /* Free descriptor back to SQ for future use */
815 void nicvf_put_sq_desc(struct snd_queue *sq, int desc_cnt)
817 atomic_add(desc_cnt, &sq->free_cnt);
818 sq->head += desc_cnt;
819 sq->head &= (sq->dmem.q_len - 1);
822 static inline int nicvf_get_nxt_sqentry(struct snd_queue *sq, int qentry)
825 qentry &= (sq->dmem.q_len - 1);
829 void nicvf_sq_enable(struct nicvf *nic, struct snd_queue *sq, int qidx)
833 sq_cfg = nicvf_queue_reg_read(nic, NIC_QSET_SQ_0_7_CFG, qidx);
834 sq_cfg |= NICVF_SQ_EN;
835 nicvf_queue_reg_write(nic, NIC_QSET_SQ_0_7_CFG, qidx, sq_cfg);
836 /* Ring doorbell so that H/W restarts processing SQEs */
837 nicvf_queue_reg_write(nic, NIC_QSET_SQ_0_7_DOOR, qidx, 0);
840 void nicvf_sq_disable(struct nicvf *nic, int qidx)
844 sq_cfg = nicvf_queue_reg_read(nic, NIC_QSET_SQ_0_7_CFG, qidx);
845 sq_cfg &= ~NICVF_SQ_EN;
846 nicvf_queue_reg_write(nic, NIC_QSET_SQ_0_7_CFG, qidx, sq_cfg);
849 void nicvf_sq_free_used_descs(struct net_device *netdev, struct snd_queue *sq,
854 struct nicvf *nic = netdev_priv(netdev);
855 struct sq_hdr_subdesc *hdr;
857 head = nicvf_queue_reg_read(nic, NIC_QSET_SQ_0_7_HEAD, qidx) >> 4;
858 tail = nicvf_queue_reg_read(nic, NIC_QSET_SQ_0_7_TAIL, qidx) >> 4;
859 while (sq->head != head) {
860 hdr = (struct sq_hdr_subdesc *)GET_SQ_DESC(sq, sq->head);
861 if (hdr->subdesc_type != SQ_DESC_TYPE_HEADER) {
862 nicvf_put_sq_desc(sq, 1);
865 skb = (struct sk_buff *)sq->skbuff[sq->head];
867 dev_kfree_skb_any(skb);
868 atomic64_add(1, (atomic64_t *)&netdev->stats.tx_packets);
869 atomic64_add(hdr->tot_len,
870 (atomic64_t *)&netdev->stats.tx_bytes);
871 nicvf_put_sq_desc(sq, hdr->subdesc_cnt + 1);
875 /* Calculate no of SQ subdescriptors needed to transmit all
876 * segments of this TSO packet.
877 * Taken from 'Tilera network driver' with a minor modification.
879 static int nicvf_tso_count_subdescs(struct sk_buff *skb)
881 struct skb_shared_info *sh = skb_shinfo(skb);
882 unsigned int sh_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
883 unsigned int data_len = skb->len - sh_len;
884 unsigned int p_len = sh->gso_size;
885 long f_id = -1; /* id of the current fragment */
886 long f_size = skb_headlen(skb) - sh_len; /* current fragment size */
887 long f_used = 0; /* bytes used from the current fragment */
888 long n; /* size of the current piece of payload */
892 for (segment = 0; segment < sh->gso_segs; segment++) {
893 unsigned int p_used = 0;
895 /* One edesc for header and for each piece of the payload. */
896 for (num_edescs++; p_used < p_len; num_edescs++) {
897 /* Advance as needed. */
898 while (f_used >= f_size) {
900 f_size = skb_frag_size(&sh->frags[f_id]);
904 /* Use bytes from the current fragment. */
906 if (n > f_size - f_used)
912 /* The last segment may be less than gso_size. */
914 if (data_len < p_len)
918 /* '+ gso_segs' for SQ_HDR_SUDESCs for each segment */
919 return num_edescs + sh->gso_segs;
922 /* Get the number of SQ descriptors needed to xmit this skb */
923 static int nicvf_sq_subdesc_required(struct nicvf *nic, struct sk_buff *skb)
925 int subdesc_cnt = MIN_SQ_DESC_PER_PKT_XMIT;
927 if (skb_shinfo(skb)->gso_size && !nic->hw_tso) {
928 subdesc_cnt = nicvf_tso_count_subdescs(skb);
932 if (skb_shinfo(skb)->nr_frags)
933 subdesc_cnt += skb_shinfo(skb)->nr_frags;
938 /* Add SQ HEADER subdescriptor.
939 * First subdescriptor for every send descriptor.
942 nicvf_sq_add_hdr_subdesc(struct nicvf *nic, struct snd_queue *sq, int qentry,
943 int subdesc_cnt, struct sk_buff *skb, int len)
946 struct sq_hdr_subdesc *hdr;
948 hdr = (struct sq_hdr_subdesc *)GET_SQ_DESC(sq, qentry);
949 sq->skbuff[qentry] = (u64)skb;
951 memset(hdr, 0, SND_QUEUE_DESC_SIZE);
952 hdr->subdesc_type = SQ_DESC_TYPE_HEADER;
953 /* Enable notification via CQE after processing SQE */
955 /* No of subdescriptors following this */
956 hdr->subdesc_cnt = subdesc_cnt;
959 /* Offload checksum calculation to HW */
960 if (skb->ip_summed == CHECKSUM_PARTIAL) {
961 hdr->csum_l3 = 1; /* Enable IP csum calculation */
962 hdr->l3_offset = skb_network_offset(skb);
963 hdr->l4_offset = skb_transport_offset(skb);
965 proto = ip_hdr(skb)->protocol;
968 hdr->csum_l4 = SEND_L4_CSUM_TCP;
971 hdr->csum_l4 = SEND_L4_CSUM_UDP;
974 hdr->csum_l4 = SEND_L4_CSUM_SCTP;
979 if (nic->hw_tso && skb_shinfo(skb)->gso_size) {
981 hdr->tso_start = skb_transport_offset(skb) + tcp_hdrlen(skb);
982 hdr->tso_max_paysize = skb_shinfo(skb)->gso_size;
983 /* For non-tunneled pkts, point this to L2 ethertype */
984 hdr->inner_l3_offset = skb_network_offset(skb) - 2;
985 nic->drv_stats.tx_tso++;
989 /* SQ GATHER subdescriptor
990 * Must follow HDR descriptor
992 static inline void nicvf_sq_add_gather_subdesc(struct snd_queue *sq, int qentry,
995 struct sq_gather_subdesc *gather;
997 qentry &= (sq->dmem.q_len - 1);
998 gather = (struct sq_gather_subdesc *)GET_SQ_DESC(sq, qentry);
1000 memset(gather, 0, SND_QUEUE_DESC_SIZE);
1001 gather->subdesc_type = SQ_DESC_TYPE_GATHER;
1002 gather->ld_type = NIC_SEND_LD_TYPE_E_LDD;
1003 gather->size = size;
1004 gather->addr = data;
1007 /* Segment a TSO packet into 'gso_size' segments and append
1008 * them to SQ for transfer
1010 static int nicvf_sq_append_tso(struct nicvf *nic, struct snd_queue *sq,
1011 int sq_num, int qentry, struct sk_buff *skb)
1014 int seg_subdescs = 0, desc_cnt = 0;
1015 int seg_len, total_len, data_left;
1016 int hdr_qentry = qentry;
1017 int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
1019 tso_start(skb, &tso);
1020 total_len = skb->len - hdr_len;
1021 while (total_len > 0) {
1024 /* Save Qentry for adding HDR_SUBDESC at the end */
1025 hdr_qentry = qentry;
1027 data_left = min_t(int, skb_shinfo(skb)->gso_size, total_len);
1028 total_len -= data_left;
1030 /* Add segment's header */
1031 qentry = nicvf_get_nxt_sqentry(sq, qentry);
1032 hdr = sq->tso_hdrs + qentry * TSO_HEADER_SIZE;
1033 tso_build_hdr(skb, hdr, &tso, data_left, total_len == 0);
1034 nicvf_sq_add_gather_subdesc(sq, qentry, hdr_len,
1036 qentry * TSO_HEADER_SIZE);
1037 /* HDR_SUDESC + GATHER */
1041 /* Add segment's payload fragments */
1042 while (data_left > 0) {
1045 size = min_t(int, tso.size, data_left);
1047 qentry = nicvf_get_nxt_sqentry(sq, qentry);
1048 nicvf_sq_add_gather_subdesc(sq, qentry, size,
1049 virt_to_phys(tso.data));
1054 tso_build_data(skb, &tso, size);
1056 nicvf_sq_add_hdr_subdesc(nic, sq, hdr_qentry,
1057 seg_subdescs - 1, skb, seg_len);
1058 sq->skbuff[hdr_qentry] = (u64)NULL;
1059 qentry = nicvf_get_nxt_sqentry(sq, qentry);
1061 desc_cnt += seg_subdescs;
1063 /* Save SKB in the last segment for freeing */
1064 sq->skbuff[hdr_qentry] = (u64)skb;
1066 /* make sure all memory stores are done before ringing doorbell */
1069 /* Inform HW to xmit all TSO segments */
1070 nicvf_queue_reg_write(nic, NIC_QSET_SQ_0_7_DOOR,
1072 nic->drv_stats.tx_tso++;
1076 /* Append an skb to a SQ for packet transfer. */
1077 int nicvf_sq_append_skb(struct nicvf *nic, struct sk_buff *skb)
1082 struct queue_set *qs;
1083 struct snd_queue *sq;
1085 sq_num = skb_get_queue_mapping(skb);
1086 if (sq_num >= MAX_SND_QUEUES_PER_QS) {
1087 /* Get secondary Qset's SQ structure */
1088 i = sq_num / MAX_SND_QUEUES_PER_QS;
1089 if (!nic->snicvf[i - 1]) {
1090 netdev_warn(nic->netdev,
1091 "Secondary Qset#%d's ptr not initialized\n",
1095 nic = (struct nicvf *)nic->snicvf[i - 1];
1096 sq_num = sq_num % MAX_SND_QUEUES_PER_QS;
1100 sq = &qs->sq[sq_num];
1102 subdesc_cnt = nicvf_sq_subdesc_required(nic, skb);
1103 if (subdesc_cnt > atomic_read(&sq->free_cnt))
1106 qentry = nicvf_get_sq_desc(sq, subdesc_cnt);
1108 /* Check if its a TSO packet */
1109 if (skb_shinfo(skb)->gso_size && !nic->hw_tso)
1110 return nicvf_sq_append_tso(nic, sq, sq_num, qentry, skb);
1112 /* Add SQ header subdesc */
1113 nicvf_sq_add_hdr_subdesc(nic, sq, qentry, subdesc_cnt - 1,
1116 /* Add SQ gather subdescs */
1117 qentry = nicvf_get_nxt_sqentry(sq, qentry);
1118 size = skb_is_nonlinear(skb) ? skb_headlen(skb) : skb->len;
1119 nicvf_sq_add_gather_subdesc(sq, qentry, size, virt_to_phys(skb->data));
1121 /* Check for scattered buffer */
1122 if (!skb_is_nonlinear(skb))
1125 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1126 const struct skb_frag_struct *frag;
1128 frag = &skb_shinfo(skb)->frags[i];
1130 qentry = nicvf_get_nxt_sqentry(sq, qentry);
1131 size = skb_frag_size(frag);
1132 nicvf_sq_add_gather_subdesc(sq, qentry, size,
1134 skb_frag_address(frag)));
1138 /* make sure all memory stores are done before ringing doorbell */
1141 /* Inform HW to xmit new packet */
1142 nicvf_queue_reg_write(nic, NIC_QSET_SQ_0_7_DOOR,
1143 sq_num, subdesc_cnt);
1147 /* Use original PCI dev for debug log */
1149 netdev_dbg(nic->netdev, "Not enough SQ descriptors to xmit pkt\n");
1153 static inline unsigned frag_num(unsigned i)
1156 return (i & ~3) + 3 - (i & 3);
1162 /* Returns SKB for a received packet */
1163 struct sk_buff *nicvf_get_rcv_skb(struct nicvf *nic, struct cqe_rx_t *cqe_rx)
1166 int payload_len = 0;
1167 struct sk_buff *skb = NULL;
1168 struct sk_buff *skb_frag = NULL;
1169 struct sk_buff *prev_frag = NULL;
1170 u16 *rb_lens = NULL;
1171 u64 *rb_ptrs = NULL;
1173 rb_lens = (void *)cqe_rx + (3 * sizeof(u64));
1174 rb_ptrs = (void *)cqe_rx + (6 * sizeof(u64));
1176 netdev_dbg(nic->netdev, "%s rb_cnt %d rb0_ptr %llx rb0_sz %d\n",
1177 __func__, cqe_rx->rb_cnt, cqe_rx->rb0_ptr, cqe_rx->rb0_sz);
1179 for (frag = 0; frag < cqe_rx->rb_cnt; frag++) {
1180 payload_len = rb_lens[frag_num(frag)];
1182 /* First fragment */
1183 skb = nicvf_rb_ptr_to_skb(nic,
1184 *rb_ptrs - cqe_rx->align_pad,
1188 skb_reserve(skb, cqe_rx->align_pad);
1189 skb_put(skb, payload_len);
1192 skb_frag = nicvf_rb_ptr_to_skb(nic, *rb_ptrs,
1199 if (!skb_shinfo(skb)->frag_list)
1200 skb_shinfo(skb)->frag_list = skb_frag;
1202 prev_frag->next = skb_frag;
1204 prev_frag = skb_frag;
1205 skb->len += payload_len;
1206 skb->data_len += payload_len;
1207 skb_frag->len = payload_len;
1209 /* Next buffer pointer */
1215 static u64 nicvf_int_type_to_mask(int int_type, int q_idx)
1221 reg_val = ((1ULL << q_idx) << NICVF_INTR_CQ_SHIFT);
1224 reg_val = ((1ULL << q_idx) << NICVF_INTR_SQ_SHIFT);
1226 case NICVF_INTR_RBDR:
1227 reg_val = ((1ULL << q_idx) << NICVF_INTR_RBDR_SHIFT);
1229 case NICVF_INTR_PKT_DROP:
1230 reg_val = (1ULL << NICVF_INTR_PKT_DROP_SHIFT);
1232 case NICVF_INTR_TCP_TIMER:
1233 reg_val = (1ULL << NICVF_INTR_TCP_TIMER_SHIFT);
1235 case NICVF_INTR_MBOX:
1236 reg_val = (1ULL << NICVF_INTR_MBOX_SHIFT);
1238 case NICVF_INTR_QS_ERR:
1239 reg_val = (1ULL << NICVF_INTR_QS_ERR_SHIFT);
1248 /* Enable interrupt */
1249 void nicvf_enable_intr(struct nicvf *nic, int int_type, int q_idx)
1251 u64 mask = nicvf_int_type_to_mask(int_type, q_idx);
1254 netdev_dbg(nic->netdev,
1255 "Failed to enable interrupt: unknown type\n");
1258 nicvf_reg_write(nic, NIC_VF_ENA_W1S,
1259 nicvf_reg_read(nic, NIC_VF_ENA_W1S) | mask);
1262 /* Disable interrupt */
1263 void nicvf_disable_intr(struct nicvf *nic, int int_type, int q_idx)
1265 u64 mask = nicvf_int_type_to_mask(int_type, q_idx);
1268 netdev_dbg(nic->netdev,
1269 "Failed to disable interrupt: unknown type\n");
1273 nicvf_reg_write(nic, NIC_VF_ENA_W1C, mask);
1276 /* Clear interrupt */
1277 void nicvf_clear_intr(struct nicvf *nic, int int_type, int q_idx)
1279 u64 mask = nicvf_int_type_to_mask(int_type, q_idx);
1282 netdev_dbg(nic->netdev,
1283 "Failed to clear interrupt: unknown type\n");
1287 nicvf_reg_write(nic, NIC_VF_INT, mask);
1290 /* Check if interrupt is enabled */
1291 int nicvf_is_intr_enabled(struct nicvf *nic, int int_type, int q_idx)
1293 u64 mask = nicvf_int_type_to_mask(int_type, q_idx);
1294 /* If interrupt type is unknown, we treat it disabled. */
1296 netdev_dbg(nic->netdev,
1297 "Failed to check interrupt enable: unknown type\n");
1301 return mask & nicvf_reg_read(nic, NIC_VF_ENA_W1S);
1304 void nicvf_update_rq_stats(struct nicvf *nic, int rq_idx)
1306 struct rcv_queue *rq;
1308 #define GET_RQ_STATS(reg) \
1309 nicvf_reg_read(nic, NIC_QSET_RQ_0_7_STAT_0_1 |\
1310 (rq_idx << NIC_Q_NUM_SHIFT) | (reg << 3))
1312 rq = &nic->qs->rq[rq_idx];
1313 rq->stats.bytes = GET_RQ_STATS(RQ_SQ_STATS_OCTS);
1314 rq->stats.pkts = GET_RQ_STATS(RQ_SQ_STATS_PKTS);
1317 void nicvf_update_sq_stats(struct nicvf *nic, int sq_idx)
1319 struct snd_queue *sq;
1321 #define GET_SQ_STATS(reg) \
1322 nicvf_reg_read(nic, NIC_QSET_SQ_0_7_STAT_0_1 |\
1323 (sq_idx << NIC_Q_NUM_SHIFT) | (reg << 3))
1325 sq = &nic->qs->sq[sq_idx];
1326 sq->stats.bytes = GET_SQ_STATS(RQ_SQ_STATS_OCTS);
1327 sq->stats.pkts = GET_SQ_STATS(RQ_SQ_STATS_PKTS);
1330 /* Check for errors in the receive cmp.queue entry */
1331 int nicvf_check_cqe_rx_errs(struct nicvf *nic, struct cqe_rx_t *cqe_rx)
1333 struct nicvf_hw_stats *stats = &nic->hw_stats;
1335 if (!cqe_rx->err_level && !cqe_rx->err_opcode)
1338 if (netif_msg_rx_err(nic))
1339 netdev_err(nic->netdev,
1340 "%s: RX error CQE err_level 0x%x err_opcode 0x%x\n",
1342 cqe_rx->err_level, cqe_rx->err_opcode);
1344 switch (cqe_rx->err_opcode) {
1345 case CQ_RX_ERROP_RE_PARTIAL:
1346 stats->rx_bgx_truncated_pkts++;
1348 case CQ_RX_ERROP_RE_JABBER:
1349 stats->rx_jabber_errs++;
1351 case CQ_RX_ERROP_RE_FCS:
1352 stats->rx_fcs_errs++;
1354 case CQ_RX_ERROP_RE_RX_CTL:
1355 stats->rx_bgx_errs++;
1357 case CQ_RX_ERROP_PREL2_ERR:
1358 stats->rx_prel2_errs++;
1360 case CQ_RX_ERROP_L2_MAL:
1361 stats->rx_l2_hdr_malformed++;
1363 case CQ_RX_ERROP_L2_OVERSIZE:
1364 stats->rx_oversize++;
1366 case CQ_RX_ERROP_L2_UNDERSIZE:
1367 stats->rx_undersize++;
1369 case CQ_RX_ERROP_L2_LENMISM:
1370 stats->rx_l2_len_mismatch++;
1372 case CQ_RX_ERROP_L2_PCLP:
1373 stats->rx_l2_pclp++;
1375 case CQ_RX_ERROP_IP_NOT:
1376 stats->rx_ip_ver_errs++;
1378 case CQ_RX_ERROP_IP_CSUM_ERR:
1379 stats->rx_ip_csum_errs++;
1381 case CQ_RX_ERROP_IP_MAL:
1382 stats->rx_ip_hdr_malformed++;
1384 case CQ_RX_ERROP_IP_MALD:
1385 stats->rx_ip_payload_malformed++;
1387 case CQ_RX_ERROP_IP_HOP:
1388 stats->rx_ip_ttl_errs++;
1390 case CQ_RX_ERROP_L3_PCLP:
1391 stats->rx_l3_pclp++;
1393 case CQ_RX_ERROP_L4_MAL:
1394 stats->rx_l4_malformed++;
1396 case CQ_RX_ERROP_L4_CHK:
1397 stats->rx_l4_csum_errs++;
1399 case CQ_RX_ERROP_UDP_LEN:
1400 stats->rx_udp_len_errs++;
1402 case CQ_RX_ERROP_L4_PORT:
1403 stats->rx_l4_port_errs++;
1405 case CQ_RX_ERROP_TCP_FLAG:
1406 stats->rx_tcp_flag_errs++;
1408 case CQ_RX_ERROP_TCP_OFFSET:
1409 stats->rx_tcp_offset_errs++;
1411 case CQ_RX_ERROP_L4_PCLP:
1412 stats->rx_l4_pclp++;
1414 case CQ_RX_ERROP_RBDR_TRUNC:
1415 stats->rx_truncated_pkts++;
1422 /* Check for errors in the send cmp.queue entry */
1423 int nicvf_check_cqe_tx_errs(struct nicvf *nic,
1424 struct cmp_queue *cq, struct cqe_send_t *cqe_tx)
1426 struct cmp_queue_stats *stats = &cq->stats;
1428 switch (cqe_tx->send_status) {
1429 case CQ_TX_ERROP_GOOD:
1432 case CQ_TX_ERROP_DESC_FAULT:
1433 stats->tx.desc_fault++;
1435 case CQ_TX_ERROP_HDR_CONS_ERR:
1436 stats->tx.hdr_cons_err++;
1438 case CQ_TX_ERROP_SUBDC_ERR:
1439 stats->tx.subdesc_err++;
1441 case CQ_TX_ERROP_IMM_SIZE_OFLOW:
1442 stats->tx.imm_size_oflow++;
1444 case CQ_TX_ERROP_DATA_SEQUENCE_ERR:
1445 stats->tx.data_seq_err++;
1447 case CQ_TX_ERROP_MEM_SEQUENCE_ERR:
1448 stats->tx.mem_seq_err++;
1450 case CQ_TX_ERROP_LOCK_VIOL:
1451 stats->tx.lock_viol++;
1453 case CQ_TX_ERROP_DATA_FAULT:
1454 stats->tx.data_fault++;
1456 case CQ_TX_ERROP_TSTMP_CONFLICT:
1457 stats->tx.tstmp_conflict++;
1459 case CQ_TX_ERROP_TSTMP_TIMEOUT:
1460 stats->tx.tstmp_timeout++;
1462 case CQ_TX_ERROP_MEM_FAULT:
1463 stats->tx.mem_fault++;
1465 case CQ_TX_ERROP_CK_OVERLAP:
1466 stats->tx.csum_overlap++;
1468 case CQ_TX_ERROP_CK_OFLOW:
1469 stats->tx.csum_overflow++;