2 * Copyright (C) 2015 Cavium, Inc.
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of version 2 of the GNU General Public License
6 * as published by the Free Software Foundation.
12 #include <linux/netdevice.h>
13 #include <linux/interrupt.h>
14 #include <linux/pci.h>
15 #include "thunder_bgx.h"
18 #define PCI_DEVICE_ID_THUNDER_NIC_PF 0xA01E
19 #define PCI_DEVICE_ID_THUNDER_PASS1_NIC_VF 0x0011
20 #define PCI_DEVICE_ID_THUNDER_NIC_VF 0xA034
21 #define PCI_DEVICE_ID_THUNDER_BGX 0xA026
23 /* Subsystem device IDs */
24 #define PCI_SUBSYS_DEVID_88XX_NIC_PF 0xA11E
25 #define PCI_SUBSYS_DEVID_81XX_NIC_PF 0xA21E
26 #define PCI_SUBSYS_DEVID_83XX_NIC_PF 0xA31E
28 #define PCI_SUBSYS_DEVID_88XX_PASS1_NIC_VF 0xA11E
29 #define PCI_SUBSYS_DEVID_88XX_NIC_VF 0xA134
30 #define PCI_SUBSYS_DEVID_81XX_NIC_VF 0xA234
31 #define PCI_SUBSYS_DEVID_83XX_NIC_VF 0xA334
35 #define PCI_CFG_REG_BAR_NUM 0
36 #define PCI_MSIX_REG_BAR_NUM 4
38 /* NIC SRIOV VF count */
39 #define MAX_NUM_VFS_SUPPORTED 128
40 #define DEFAULT_NUM_VF_ENABLED 8
42 #define NIC_TNS_BYPASS_MODE 0
43 #define NIC_TNS_MODE 1
46 #define NIC_SRIOV_ENABLED BIT(0)
48 /* Min/Max packet size */
49 #define NIC_HW_MIN_FRS 64
50 #define NIC_HW_MAX_FRS 9190 /* Excluding L2 header and FCS */
53 #define NIC_MAX_PKIND 16
55 /* Max when CPI_ALG is IP diffserv */
56 #define NIC_MAX_CPI_PER_LMAC 64
58 /* NIC VF Interrupts */
59 #define NICVF_INTR_CQ 0
60 #define NICVF_INTR_SQ 1
61 #define NICVF_INTR_RBDR 2
62 #define NICVF_INTR_PKT_DROP 3
63 #define NICVF_INTR_TCP_TIMER 4
64 #define NICVF_INTR_MBOX 5
65 #define NICVF_INTR_QS_ERR 6
67 #define NICVF_INTR_CQ_SHIFT 0
68 #define NICVF_INTR_SQ_SHIFT 8
69 #define NICVF_INTR_RBDR_SHIFT 16
70 #define NICVF_INTR_PKT_DROP_SHIFT 20
71 #define NICVF_INTR_TCP_TIMER_SHIFT 21
72 #define NICVF_INTR_MBOX_SHIFT 22
73 #define NICVF_INTR_QS_ERR_SHIFT 23
75 #define NICVF_INTR_CQ_MASK (0xFF << NICVF_INTR_CQ_SHIFT)
76 #define NICVF_INTR_SQ_MASK (0xFF << NICVF_INTR_SQ_SHIFT)
77 #define NICVF_INTR_RBDR_MASK (0x03 << NICVF_INTR_RBDR_SHIFT)
78 #define NICVF_INTR_PKT_DROP_MASK BIT(NICVF_INTR_PKT_DROP_SHIFT)
79 #define NICVF_INTR_TCP_TIMER_MASK BIT(NICVF_INTR_TCP_TIMER_SHIFT)
80 #define NICVF_INTR_MBOX_MASK BIT(NICVF_INTR_MBOX_SHIFT)
81 #define NICVF_INTR_QS_ERR_MASK BIT(NICVF_INTR_QS_ERR_SHIFT)
83 /* MSI-X interrupts */
84 #define NIC_PF_MSIX_VECTORS 10
85 #define NIC_VF_MSIX_VECTORS 20
87 #define NIC_PF_INTR_ID_ECC0_SBE 0
88 #define NIC_PF_INTR_ID_ECC0_DBE 1
89 #define NIC_PF_INTR_ID_ECC1_SBE 2
90 #define NIC_PF_INTR_ID_ECC1_DBE 3
91 #define NIC_PF_INTR_ID_ECC2_SBE 4
92 #define NIC_PF_INTR_ID_ECC2_DBE 5
93 #define NIC_PF_INTR_ID_ECC3_SBE 6
94 #define NIC_PF_INTR_ID_ECC3_DBE 7
95 #define NIC_PF_INTR_ID_MBOX0 8
96 #define NIC_PF_INTR_ID_MBOX1 9
98 /* Minimum FIFO level before all packets for the CQ are dropped
100 * This value ensures that once a packet has been "accepted"
101 * for reception it will not get dropped due to non-availability
102 * of CQ descriptor. An errata in HW mandates this value to be
105 #define NICPF_CQM_MIN_DROP_LEVEL 0x100
107 /* Global timer for CQ timer thresh interrupts
108 * Calculated for SCLK of 700Mhz
109 * value written should be a 1/16th of what is expected
111 * 1 tick per 0.025usec
113 #define NICPF_CLK_PER_INT_TICK 1
115 /* Time to wait before we decide that a SQ is stuck.
117 * Since both pkt rx and tx notifications are done with same CQ,
118 * when packets are being received at very high rate (eg: L2 forwarding)
119 * then freeing transmitted skbs will be delayed and watchdog
120 * will kick in, resetting interface. Hence keeping this value high.
122 #define NICVF_TX_TIMEOUT (50 * HZ)
124 struct nicvf_cq_poll {
126 u8 cq_idx; /* Completion queue index */
127 struct napi_struct napi;
130 #define NIC_MAX_RSS_HASH_BITS 8
131 #define NIC_MAX_RSS_IDR_TBL_SIZE (1 << NIC_MAX_RSS_HASH_BITS)
132 #define RSS_HASH_KEY_SIZE 5 /* 320 bit key */
134 struct nicvf_rss_info {
136 #define RSS_L2_EXTENDED_HASH_ENA BIT(0)
137 #define RSS_IP_HASH_ENA BIT(1)
138 #define RSS_TCP_HASH_ENA BIT(2)
139 #define RSS_TCP_SYN_DIS BIT(3)
140 #define RSS_UDP_HASH_ENA BIT(4)
141 #define RSS_L4_EXTENDED_HASH_ENA BIT(5)
142 #define RSS_ROCE_ENA BIT(6)
143 #define RSS_L3_BI_DIRECTION_ENA BIT(7)
144 #define RSS_L4_BI_DIRECTION_ENA BIT(8)
148 u8 ind_tbl[NIC_MAX_RSS_IDR_TBL_SIZE];
149 u64 key[RSS_HASH_KEY_SIZE];
150 } ____cacheline_aligned_in_smp;
158 enum rx_stats_reg_offset {
171 RX_DRP_L3BCAST = 0xc,
172 RX_DRP_L3MCAST = 0xd,
176 enum tx_stats_reg_offset {
185 struct nicvf_hw_stats {
193 u64 rx_drop_red_bytes;
195 u64 rx_drop_overrun_bytes;
198 u64 rx_drop_l3_bcast;
199 u64 rx_drop_l3_mcast;
211 struct nicvf_drv_stats {
213 u64 rx_bgx_truncated_pkts;
218 u64 rx_l2_hdr_malformed;
221 u64 rx_l2_len_mismatch;
225 u64 rx_ip_hdr_malformed;
226 u64 rx_ip_payload_malformed;
233 u64 rx_tcp_flag_errs;
234 u64 rx_tcp_offset_errs;
236 u64 rx_truncated_pkts;
242 u64 tx_max_size_exceeded;
243 u64 tx_imm_size_oflow;
248 u64 tx_tstmp_conflict;
249 u64 tx_tstmp_timeout;
252 u64 tx_csum_overflow;
254 /* driver debug stats */
260 u64 rcv_buffer_alloc_failures;
263 struct u64_stats_sync syncp;
268 struct xcast_addr_list {
274 struct delayed_work work;
276 struct xcast_addr_list *mc;
280 struct nicvf *pnicvf;
281 struct net_device *netdev;
282 struct pci_dev *pdev;
283 void __iomem *reg_base;
284 struct bpf_prog *xdp_prog;
285 #define MAX_QUEUES_PER_QSET 8
286 struct queue_set *qs;
294 /* Receive buffer alloc */
298 bool rb_work_scheduled;
299 struct page *rb_page;
300 struct delayed_work rbdr_work;
301 struct tasklet_struct rbdr_task;
305 #define MAX_SQS_PER_VF_SINGLE_NODE 5
306 #define MAX_SQS_PER_VF 11
307 struct nicvf *snicvf[MAX_SQS_PER_VF];
322 bool loopback_supported;
323 struct nicvf_rss_info rss_info;
324 struct nicvf_pfc pfc;
325 struct tasklet_struct qs_err_task;
326 struct work_struct reset_task;
327 struct nicvf_work rx_mode_work;
330 struct cavium_ptp *ptp_clock;
331 /* Inbound timestamping is on */
333 /* When the packet that requires timestamping is sent, hardware inserts
334 * two entries to the completion queue. First is the regular
335 * CQE_TYPE_SEND entry that signals that the packet was sent.
336 * The second is CQE_TYPE_SEND_PTP that contains the actual timestamp
338 * `ptp_skb` is initialized in the handler for the CQE_TYPE_SEND
339 * entry and is used and zeroed in the handler for the CQE_TYPE_SEND_PTP
341 * So `ptp_skb` is used to hold the pointer to the packet between
342 * the calls to CQE_TYPE_SEND and CQE_TYPE_SEND_PTP handlers.
344 struct sk_buff *ptp_skb;
345 /* `tx_ptp_skbs` is set when the hardware is sending a packet that
346 * requires timestamping. Cavium hardware can not process more than one
347 * such packet at once so this is set each time the driver submits
348 * a packet that requires timestamping to the send queue and clears
349 * each time it receives the entry on the completion queue saying
350 * that such packet was sent.
351 * So `tx_ptp_skbs` prevents driver from submitting more than one
352 * packet that requires timestamping to the hardware for transmitting.
354 atomic_t tx_ptp_skbs;
356 /* Interrupt coalescing settings */
357 u32 cq_coalesce_usecs;
361 struct nicvf_hw_stats hw_stats;
362 struct nicvf_drv_stats __percpu *drv_stats;
363 struct bgx_stats bgx_stats;
366 struct nicvf_cq_poll *napi[8];
370 char irq_name[NIC_VF_MSIX_VECTORS][IFNAMSIZ + 15];
371 bool irq_allocated[NIC_VF_MSIX_VECTORS];
372 cpumask_var_t affinity_mask[NIC_VF_MSIX_VECTORS];
374 /* VF <-> PF mailbox communication */
377 bool set_mac_pending;
378 } ____cacheline_aligned_in_smp;
380 /* PF <--> VF Mailbox communication
381 * Eight 64bit registers are shared between PF and VF.
382 * Separate set for each VF.
383 * Writing '1' into last register mbx7 means end of message.
386 /* PF <--> VF mailbox communication */
387 #define NIC_PF_VF_MAILBOX_SIZE 2
388 #define NIC_MBOX_MSG_TIMEOUT 2000 /* ms */
390 /* Mailbox message types */
391 #define NIC_MBOX_MSG_READY 0x01 /* Is PF ready to rcv msgs */
392 #define NIC_MBOX_MSG_ACK 0x02 /* ACK the message received */
393 #define NIC_MBOX_MSG_NACK 0x03 /* NACK the message received */
394 #define NIC_MBOX_MSG_QS_CFG 0x04 /* Configure Qset */
395 #define NIC_MBOX_MSG_RQ_CFG 0x05 /* Configure receive queue */
396 #define NIC_MBOX_MSG_SQ_CFG 0x06 /* Configure Send queue */
397 #define NIC_MBOX_MSG_RQ_DROP_CFG 0x07 /* Configure receive queue */
398 #define NIC_MBOX_MSG_SET_MAC 0x08 /* Add MAC ID to DMAC filter */
399 #define NIC_MBOX_MSG_SET_MAX_FRS 0x09 /* Set max frame size */
400 #define NIC_MBOX_MSG_CPI_CFG 0x0A /* Config CPI, RSSI */
401 #define NIC_MBOX_MSG_RSS_SIZE 0x0B /* Get RSS indir_tbl size */
402 #define NIC_MBOX_MSG_RSS_CFG 0x0C /* Config RSS table */
403 #define NIC_MBOX_MSG_RSS_CFG_CONT 0x0D /* RSS config continuation */
404 #define NIC_MBOX_MSG_RQ_BP_CFG 0x0E /* RQ backpressure config */
405 #define NIC_MBOX_MSG_RQ_SW_SYNC 0x0F /* Flush inflight pkts to RQ */
406 #define NIC_MBOX_MSG_BGX_STATS 0x10 /* Get stats from BGX */
407 #define NIC_MBOX_MSG_BGX_LINK_CHANGE 0x11 /* BGX:LMAC link status */
408 #define NIC_MBOX_MSG_ALLOC_SQS 0x12 /* Allocate secondary Qset */
409 #define NIC_MBOX_MSG_NICVF_PTR 0x13 /* Send nicvf ptr to PF */
410 #define NIC_MBOX_MSG_PNICVF_PTR 0x14 /* Get primary qset nicvf ptr */
411 #define NIC_MBOX_MSG_SNICVF_PTR 0x15 /* Send sqet nicvf ptr to PVF */
412 #define NIC_MBOX_MSG_LOOPBACK 0x16 /* Set interface in loopback */
413 #define NIC_MBOX_MSG_RESET_STAT_COUNTER 0x17 /* Reset statistics counters */
414 #define NIC_MBOX_MSG_PFC 0x18 /* Pause frame control */
415 #define NIC_MBOX_MSG_PTP_CFG 0x19 /* HW packet timestamp */
416 #define NIC_MBOX_MSG_CFG_DONE 0xF0 /* VF configuration done */
417 #define NIC_MBOX_MSG_SHUTDOWN 0xF1 /* VF is being shutdown */
418 #define NIC_MBOX_MSG_RESET_XCAST 0xF2 /* Reset DCAM filtering mode */
419 #define NIC_MBOX_MSG_ADD_MCAST 0xF3 /* Add MAC to DCAM filters */
420 #define NIC_MBOX_MSG_SET_XCAST 0xF4 /* Set MCAST/BCAST RX mode */
428 u8 loopback_supported:1;
429 u8 mac_addr[ETH_ALEN];
432 /* Qset configuration */
440 /* Receive queue configuration */
448 /* Send queue configuration */
457 /* Set VF's MAC address */
461 u8 mac_addr[ETH_ALEN];
464 /* Set Maximum frame size */
471 /* Set CPI algorithm type */
479 /* Get RSS table size */
486 /* Set RSS configuration */
493 #define RSS_IND_TBL_LEN_PER_MBX_MSG 8
494 u8 ind_tbl[RSS_IND_TBL_LEN_PER_MBX_MSG];
497 struct bgx_stats_msg {
505 /* Physical interface link status */
506 struct bgx_link_status {
514 /* Get Extra Qset IDs */
529 /* Set interface in loopback mode */
530 struct set_loopback {
536 /* Reset statistics counters */
537 struct reset_stat_cfg {
539 /* Bitmap to select NIC_PF_VNIC(vf_id)_RX_STAT(0..13) */
541 /* Bitmap to select NIC_PF_VNIC(vf_id)_TX_STAT(0..4) */
543 /* Bitmap to select NIC_PF_QS(0..127)_RQ(0..7)_STAT(0..1)
544 * bit14, bit15 NIC_PF_QS(vf_id)_RQ7_STAT(0..1)
545 * bit12, bit13 NIC_PF_QS(vf_id)_RQ6_STAT(0..1)
547 * bit2, bit3 NIC_PF_QS(vf_id)_RQ1_STAT(0..1)
548 * bit0, bit1 NIC_PF_QS(vf_id)_RQ0_STAT(0..1)
551 /* Bitmap to select NIC_PF_QS(0..127)_SQ(0..7)_STAT(0..1)
552 * bit14, bit15 NIC_PF_QS(vf_id)_SQ7_STAT(0..1)
553 * bit12, bit13 NIC_PF_QS(vf_id)_SQ6_STAT(0..1)
555 * bit2, bit3 NIC_PF_QS(vf_id)_SQ1_STAT(0..1)
556 * bit0, bit1 NIC_PF_QS(vf_id)_SQ0_STAT(0..1)
563 u8 get; /* Get or set PFC settings */
582 /* 128 bit shared memory between PF and each VF */
584 struct { u8 msg; } msg;
585 struct nic_cfg_msg nic_cfg;
586 struct qs_cfg_msg qs;
587 struct rq_cfg_msg rq;
588 struct sq_cfg_msg sq;
589 struct set_mac_msg mac;
590 struct set_frs_msg frs;
591 struct cpi_cfg_msg cpi_cfg;
592 struct rss_sz_msg rss_size;
593 struct rss_cfg_msg rss_cfg;
594 struct bgx_stats_msg bgx_stats;
595 struct bgx_link_status link_status;
596 struct sqs_alloc sqs_alloc;
597 struct nicvf_ptr nicvf;
598 struct set_loopback lbk;
599 struct reset_stat_cfg reset_stat;
605 #define NIC_NODE_ID_MASK 0x03
606 #define NIC_NODE_ID_SHIFT 44
608 static inline int nic_get_node_id(struct pci_dev *pdev)
610 u64 addr = pci_resource_start(pdev, PCI_CFG_REG_BAR_NUM);
611 return ((addr >> NIC_NODE_ID_SHIFT) & NIC_NODE_ID_MASK);
614 static inline bool pass1_silicon(struct pci_dev *pdev)
616 return (pdev->revision < 8) &&
617 (pdev->subsystem_device == PCI_SUBSYS_DEVID_88XX_NIC_PF);
620 static inline bool pass2_silicon(struct pci_dev *pdev)
622 return (pdev->revision >= 8) &&
623 (pdev->subsystem_device == PCI_SUBSYS_DEVID_88XX_NIC_PF);
626 int nicvf_set_real_num_queues(struct net_device *netdev,
627 int tx_queues, int rx_queues);
628 int nicvf_open(struct net_device *netdev);
629 int nicvf_stop(struct net_device *netdev);
630 int nicvf_send_msg_to_pf(struct nicvf *vf, union nic_mbx *mbx);
631 void nicvf_config_rss(struct nicvf *nic);
632 void nicvf_set_rss_key(struct nicvf *nic);
633 void nicvf_set_ethtool_ops(struct net_device *netdev);
634 void nicvf_update_stats(struct nicvf *nic);
635 void nicvf_update_lmac_stats(struct nicvf *nic);