1 /**********************************************************************
4 * Contact: support@cavium.com
5 * Please include "LiquidIO" in the subject.
7 * Copyright (c) 2003-2015 Cavium, Inc.
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
19 * This file may also be available under a different license from Cavium.
20 * Contact Cavium, Inc. for more information
21 **********************************************************************/
22 #include <linux/version.h>
23 #include <linux/types.h>
24 #include <linux/list.h>
25 #include <linux/interrupt.h>
26 #include <linux/pci.h>
27 #include <linux/kthread.h>
28 #include <linux/netdevice.h>
29 #include "octeon_config.h"
30 #include "liquidio_common.h"
31 #include "octeon_droq.h"
32 #include "octeon_iq.h"
33 #include "response_manager.h"
34 #include "octeon_device.h"
35 #include "octeon_nic.h"
36 #include "octeon_main.h"
37 #include "octeon_network.h"
38 #include "cn66xx_regs.h"
39 #include "cn66xx_device.h"
40 #include "cn68xx_regs.h"
41 #include "cn68xx_device.h"
42 #include "liquidio_image.h"
44 #define INCR_INSTRQUEUE_PKT_COUNT(octeon_dev_ptr, iq_no, field, count) \
45 (octeon_dev_ptr->instr_queue[iq_no]->stats.field += count)
47 struct iq_post_status {
52 static void check_db_timeout(struct work_struct *work);
53 static void __check_db_timeout(struct octeon_device *oct, unsigned long iq_no);
55 static void (*reqtype_free_fn[MAX_OCTEON_DEVICES][REQTYPE_LAST + 1]) (void *);
57 static inline int IQ_INSTR_MODE_64B(struct octeon_device *oct, int iq_no)
59 struct octeon_instr_queue *iq =
60 (struct octeon_instr_queue *)oct->instr_queue[iq_no];
64 #define IQ_INSTR_MODE_32B(oct, iq_no) (!IQ_INSTR_MODE_64B(oct, iq_no))
66 /* Define this to return the request status comaptible to old code */
67 /*#define OCTEON_USE_OLD_REQ_STATUS*/
69 /* Return 0 on success, 1 on failure */
70 int octeon_init_instr_queue(struct octeon_device *oct,
71 u32 iq_no, u32 num_descs)
73 struct octeon_instr_queue *iq;
74 struct octeon_iq_config *conf = NULL;
76 struct cavium_wq *db_wq;
78 if (OCTEON_CN6XXX(oct))
79 conf = &(CFG_GET_IQ_CFG(CHIP_FIELD(oct, cn6xxx, conf)));
82 dev_err(&oct->pci_dev->dev, "Unsupported Chip %x\n",
87 if (num_descs & (num_descs - 1)) {
88 dev_err(&oct->pci_dev->dev,
89 "Number of descriptors for instr queue %d not in power of 2.\n",
94 q_size = (u32)conf->instr_type * num_descs;
96 iq = oct->instr_queue[iq_no];
98 iq->base_addr = lio_dma_alloc(oct, q_size,
99 (dma_addr_t *)&iq->base_addr_dma);
100 if (!iq->base_addr) {
101 dev_err(&oct->pci_dev->dev, "Cannot allocate memory for instr queue %d\n",
106 iq->max_count = num_descs;
108 /* Initialize a list to holds requests that have been posted to Octeon
109 * but has yet to be fetched by octeon
111 iq->request_list = vmalloc(sizeof(*iq->request_list) * num_descs);
112 if (!iq->request_list) {
113 lio_dma_free(oct, q_size, iq->base_addr, iq->base_addr_dma);
114 dev_err(&oct->pci_dev->dev, "Alloc failed for IQ[%d] nr free list\n",
119 memset(iq->request_list, 0, sizeof(*iq->request_list) * num_descs);
121 dev_dbg(&oct->pci_dev->dev, "IQ[%d]: base: %p basedma: %llx count: %d\n",
122 iq_no, iq->base_addr, iq->base_addr_dma, iq->max_count);
125 iq->fill_threshold = (u32)conf->db_min;
127 iq->host_write_index = 0;
128 iq->octeon_read_index = 0;
130 iq->last_db_time = 0;
131 iq->do_auto_flush = 1;
132 iq->db_timeout = (u32)conf->db_timeout;
133 atomic_set(&iq->instr_pending, 0);
135 /* Initialize the spinlock for this instruction queue */
136 spin_lock_init(&iq->lock);
138 oct->io_qmask.iq |= (1 << iq_no);
140 /* Set the 32B/64B mode for each input queue */
141 oct->io_qmask.iq64B |= ((conf->instr_type == 64) << iq_no);
142 iq->iqcmd_64B = (conf->instr_type == 64);
144 oct->fn_list.setup_iq_regs(oct, iq_no);
146 oct->check_db_wq[iq_no].wq = create_workqueue("check_iq_db");
147 if (!oct->check_db_wq[iq_no].wq) {
148 lio_dma_free(oct, q_size, iq->base_addr, iq->base_addr_dma);
149 dev_err(&oct->pci_dev->dev, "check db wq create failed for iq %d\n",
154 db_wq = &oct->check_db_wq[iq_no];
156 INIT_DELAYED_WORK(&db_wq->wk.work, check_db_timeout);
157 db_wq->wk.ctxptr = oct;
158 db_wq->wk.ctxul = iq_no;
159 queue_delayed_work(db_wq->wq, &db_wq->wk.work, msecs_to_jiffies(1));
164 int octeon_delete_instr_queue(struct octeon_device *oct, u32 iq_no)
166 u64 desc_size = 0, q_size;
167 struct octeon_instr_queue *iq = oct->instr_queue[iq_no];
169 cancel_delayed_work_sync(&oct->check_db_wq[iq_no].wk.work);
170 flush_workqueue(oct->check_db_wq[iq_no].wq);
171 destroy_workqueue(oct->check_db_wq[iq_no].wq);
173 if (OCTEON_CN6XXX(oct))
175 CFG_GET_IQ_INSTR_TYPE(CHIP_FIELD(oct, cn6xxx, conf));
177 if (iq->request_list)
178 vfree(iq->request_list);
181 q_size = iq->max_count * desc_size;
182 lio_dma_free(oct, (u32)q_size, iq->base_addr,
189 /* Return 0 on success, 1 on failure */
190 int octeon_setup_iq(struct octeon_device *oct,
195 if (oct->instr_queue[iq_no]) {
196 dev_dbg(&oct->pci_dev->dev, "IQ is in use. Cannot create the IQ: %d again\n",
198 oct->instr_queue[iq_no]->app_ctx = app_ctx;
201 oct->instr_queue[iq_no] =
202 vmalloc(sizeof(struct octeon_instr_queue));
203 if (!oct->instr_queue[iq_no])
206 memset(oct->instr_queue[iq_no], 0,
207 sizeof(struct octeon_instr_queue));
209 oct->instr_queue[iq_no]->app_ctx = app_ctx;
210 if (octeon_init_instr_queue(oct, iq_no, num_descs)) {
211 vfree(oct->instr_queue[iq_no]);
212 oct->instr_queue[iq_no] = NULL;
217 oct->fn_list.enable_io_queues(oct);
221 int lio_wait_for_instr_fetch(struct octeon_device *oct)
223 int i, retry = 1000, pending, instr_cnt = 0;
228 /*for (i = 0; i < oct->num_iqs; i++) {*/
229 for (i = 0; i < MAX_OCTEON_INSTR_QUEUES; i++) {
230 if (!(oct->io_qmask.iq & (1UL << i)))
234 instr_queue[i]->instr_pending);
236 __check_db_timeout(oct, i);
237 instr_cnt += pending;
243 schedule_timeout_uninterruptible(1);
245 } while (retry-- && instr_cnt);
251 ring_doorbell(struct octeon_device *oct, struct octeon_instr_queue *iq)
253 if (atomic_read(&oct->status) == OCT_DEV_RUNNING) {
254 writel(iq->fill_cnt, iq->doorbell_reg);
255 /* make sure doorbell write goes through */
258 iq->last_db_time = jiffies;
263 static inline void __copy_cmd_into_iq(struct octeon_instr_queue *iq,
268 cmdsize = ((iq->iqcmd_64B) ? 64 : 32);
269 iqptr = iq->base_addr + (cmdsize * iq->host_write_index);
271 memcpy(iqptr, cmd, cmdsize);
275 __post_command(struct octeon_device *octeon_dev __attribute__((unused)),
276 struct octeon_instr_queue *iq,
277 u32 force_db __attribute__((unused)), u8 *cmd)
281 /* This ensures that the read index does not wrap around to the same
282 * position if queue gets full before Octeon could fetch any instr.
284 if (atomic_read(&iq->instr_pending) >= (s32)(iq->max_count - 1))
287 __copy_cmd_into_iq(iq, cmd);
289 /* "index" is returned, host_write_index is modified. */
290 index = iq->host_write_index;
291 INCR_INDEX_BY1(iq->host_write_index, iq->max_count);
294 /* Flush the command into memory. We need to be sure the data is in
295 * memory before indicating that the instruction is pending.
299 atomic_inc(&iq->instr_pending);
304 static inline struct iq_post_status
305 __post_command2(struct octeon_device *octeon_dev __attribute__((unused)),
306 struct octeon_instr_queue *iq,
307 u32 force_db __attribute__((unused)), u8 *cmd)
309 struct iq_post_status st;
311 st.status = IQ_SEND_OK;
313 /* This ensures that the read index does not wrap around to the same
314 * position if queue gets full before Octeon could fetch any instr.
316 if (atomic_read(&iq->instr_pending) >= (s32)(iq->max_count - 1)) {
317 st.status = IQ_SEND_FAILED;
322 if (atomic_read(&iq->instr_pending) >= (s32)(iq->max_count - 2))
323 st.status = IQ_SEND_STOP;
325 __copy_cmd_into_iq(iq, cmd);
327 /* "index" is returned, host_write_index is modified. */
328 st.index = iq->host_write_index;
329 INCR_INDEX_BY1(iq->host_write_index, iq->max_count);
332 /* Flush the command into memory. We need to be sure the data is in
333 * memory before indicating that the instruction is pending.
337 atomic_inc(&iq->instr_pending);
343 octeon_register_reqtype_free_fn(struct octeon_device *oct, int reqtype,
346 if (reqtype > REQTYPE_LAST) {
347 dev_err(&oct->pci_dev->dev, "%s: Invalid reqtype: %d\n",
352 reqtype_free_fn[oct->octeon_id][reqtype] = fn;
358 __add_to_request_list(struct octeon_instr_queue *iq,
359 int idx, void *buf, int reqtype)
361 iq->request_list[idx].buf = buf;
362 iq->request_list[idx].reqtype = reqtype;
366 lio_process_iq_request_list(struct octeon_device *oct,
367 struct octeon_instr_queue *iq)
371 u32 old = iq->flush_index;
373 unsigned pkts_compl = 0, bytes_compl = 0;
374 struct octeon_soft_command *sc;
375 struct octeon_instr_irh *irh;
377 while (old != iq->octeon_read_index) {
378 reqtype = iq->request_list[old].reqtype;
379 buf = iq->request_list[old].buf;
381 if (reqtype == REQTYPE_NONE)
384 octeon_update_tx_completion_counters(buf, reqtype, &pkts_compl,
388 case REQTYPE_NORESP_NET:
389 case REQTYPE_NORESP_NET_SG:
390 case REQTYPE_RESP_NET_SG:
391 reqtype_free_fn[oct->octeon_id][reqtype](buf);
393 case REQTYPE_RESP_NET:
394 case REQTYPE_SOFT_COMMAND:
397 irh = (struct octeon_instr_irh *)&sc->cmd.irh;
399 /* We're expecting a response from Octeon.
400 * It's up to lio_process_ordered_list() to
401 * process sc. Add sc to the ordered soft
402 * command response list because we expect
403 * a response from Octeon.
405 spin_lock_bh(&oct->response_list
406 [OCTEON_ORDERED_SC_LIST].lock);
407 atomic_inc(&oct->response_list
408 [OCTEON_ORDERED_SC_LIST].
410 list_add_tail(&sc->node, &oct->response_list
411 [OCTEON_ORDERED_SC_LIST].head);
412 spin_unlock_bh(&oct->response_list
413 [OCTEON_ORDERED_SC_LIST].lock);
416 sc->callback(oct, OCTEON_REQUEST_DONE,
422 dev_err(&oct->pci_dev->dev,
423 "%s Unknown reqtype: %d buf: %p at idx %d\n",
424 __func__, reqtype, buf, old);
427 iq->request_list[old].buf = NULL;
428 iq->request_list[old].reqtype = 0;
432 INCR_INDEX_BY1(old, iq->max_count);
435 octeon_report_tx_completion_to_bql(iq->app_ctx, pkts_compl,
437 iq->flush_index = old;
443 update_iq_indices(struct octeon_device *oct, struct octeon_instr_queue *iq)
445 u32 inst_processed = 0;
447 /* Calculate how many commands Octeon has read and move the read index
450 iq->octeon_read_index = oct->fn_list.update_iq_read_idx(oct, iq);
452 /* Move the NORESPONSE requests to the per-device completion list. */
453 if (iq->flush_index != iq->octeon_read_index)
454 inst_processed = lio_process_iq_request_list(oct, iq);
457 atomic_sub(inst_processed, &iq->instr_pending);
458 iq->stats.instr_processed += inst_processed;
462 octeon_flush_iq(struct octeon_device *oct, struct octeon_instr_queue *iq,
465 if (atomic_read(&iq->instr_pending) >= (s32)pending_thresh) {
466 spin_lock_bh(&iq->lock);
467 update_iq_indices(oct, iq);
468 spin_unlock_bh(&iq->lock);
472 static void __check_db_timeout(struct octeon_device *oct, unsigned long iq_no)
474 struct octeon_instr_queue *iq;
479 iq = oct->instr_queue[iq_no];
483 /* If jiffies - last_db_time < db_timeout do nothing */
484 next_time = iq->last_db_time + iq->db_timeout;
485 if (!time_after(jiffies, (unsigned long)next_time))
487 iq->last_db_time = jiffies;
489 /* Get the lock and prevent tasklets. This routine gets called from
490 * the poll thread. Instructions can now be posted in tasklet context
492 spin_lock_bh(&iq->lock);
493 if (iq->fill_cnt != 0)
494 ring_doorbell(oct, iq);
496 spin_unlock_bh(&iq->lock);
498 /* Flush the instruction queue */
499 if (iq->do_auto_flush)
500 octeon_flush_iq(oct, iq, 1);
503 /* Called by the Poll thread at regular intervals to check the instruction
504 * queue for commands to be posted and for commands that were fetched by Octeon.
506 static void check_db_timeout(struct work_struct *work)
508 struct cavium_wk *wk = (struct cavium_wk *)work;
509 struct octeon_device *oct = (struct octeon_device *)wk->ctxptr;
510 unsigned long iq_no = wk->ctxul;
511 struct cavium_wq *db_wq = &oct->check_db_wq[iq_no];
513 __check_db_timeout(oct, iq_no);
514 queue_delayed_work(db_wq->wq, &db_wq->wk.work, msecs_to_jiffies(1));
518 octeon_send_command(struct octeon_device *oct, u32 iq_no,
519 u32 force_db, void *cmd, void *buf,
520 u32 datasize, u32 reqtype)
522 struct iq_post_status st;
523 struct octeon_instr_queue *iq = oct->instr_queue[iq_no];
525 spin_lock_bh(&iq->lock);
527 st = __post_command2(oct, iq, force_db, cmd);
529 if (st.status != IQ_SEND_FAILED) {
530 octeon_report_sent_bytes_to_bql(buf, reqtype);
531 __add_to_request_list(iq, st.index, buf, reqtype);
532 INCR_INSTRQUEUE_PKT_COUNT(oct, iq_no, bytes_sent, datasize);
533 INCR_INSTRQUEUE_PKT_COUNT(oct, iq_no, instr_posted, 1);
535 if (iq->fill_cnt >= iq->fill_threshold || force_db)
536 ring_doorbell(oct, iq);
538 INCR_INSTRQUEUE_PKT_COUNT(oct, iq_no, instr_dropped, 1);
541 spin_unlock_bh(&iq->lock);
543 if (iq->do_auto_flush)
544 octeon_flush_iq(oct, iq, 2);
550 octeon_prepare_soft_command(struct octeon_device *oct,
551 struct octeon_soft_command *sc,
558 struct octeon_config *oct_cfg;
559 struct octeon_instr_ih *ih;
560 struct octeon_instr_irh *irh;
561 struct octeon_instr_rdp *rdp;
564 BUG_ON(subcode > 127);
566 oct_cfg = octeon_get_conf(oct);
568 ih = (struct octeon_instr_ih *)&sc->cmd.ih;
569 ih->tagtype = ATOMIC_TAG;
570 ih->tag = LIO_CONTROL;
572 ih->grp = CFG_GET_CTRL_Q_GRP(oct_cfg);
575 ih->dlengsz = sc->datasize;
579 irh = (struct octeon_instr_irh *)&sc->cmd.irh;
580 irh->opcode = opcode;
581 irh->subcode = subcode;
583 /* opcode/subcode specific parameters (ossp) */
584 irh->ossp = irh_ossp;
585 sc->cmd.ossp[0] = ossp0;
586 sc->cmd.ossp[1] = ossp1;
589 rdp = (struct octeon_instr_rdp *)&sc->cmd.rdp;
590 rdp->pcie_port = oct->pcie_port;
591 rdp->rlen = sc->rdatasize;
595 ih->fsz = 40; /* irh+ossp[0]+ossp[1]+rdp+rptr = 40 bytes */
599 ih->fsz = 24; /* irh + ossp[0] + ossp[1] = 24 bytes */
602 while (!(oct->io_qmask.iq & (1 << sc->iq_no)))
606 int octeon_send_soft_command(struct octeon_device *oct,
607 struct octeon_soft_command *sc)
609 struct octeon_instr_ih *ih;
610 struct octeon_instr_irh *irh;
611 struct octeon_instr_rdp *rdp;
613 ih = (struct octeon_instr_ih *)&sc->cmd.ih;
615 BUG_ON(!sc->dmadptr);
616 sc->cmd.dptr = sc->dmadptr;
619 irh = (struct octeon_instr_irh *)&sc->cmd.irh;
621 BUG_ON(!sc->dmarptr);
622 BUG_ON(!sc->status_word);
623 *sc->status_word = COMPLETION_WORD_INIT;
625 rdp = (struct octeon_instr_rdp *)&sc->cmd.rdp;
627 sc->cmd.rptr = sc->dmarptr;
631 sc->timeout = jiffies + sc->wait_time;
633 return octeon_send_command(oct, sc->iq_no, 1, &sc->cmd, sc,
634 (u32)ih->dlengsz, REQTYPE_SOFT_COMMAND);
637 int octeon_setup_sc_buffer_pool(struct octeon_device *oct)
641 struct octeon_soft_command *sc;
643 INIT_LIST_HEAD(&oct->sc_buf_pool.head);
644 spin_lock_init(&oct->sc_buf_pool.lock);
645 atomic_set(&oct->sc_buf_pool.alloc_buf_count, 0);
647 for (i = 0; i < MAX_SOFT_COMMAND_BUFFERS; i++) {
648 sc = (struct octeon_soft_command *)
650 SOFT_COMMAND_BUFFER_SIZE,
651 (dma_addr_t *)&dma_addr);
655 sc->dma_addr = dma_addr;
656 sc->size = SOFT_COMMAND_BUFFER_SIZE;
658 list_add_tail(&sc->node, &oct->sc_buf_pool.head);
664 int octeon_free_sc_buffer_pool(struct octeon_device *oct)
666 struct list_head *tmp, *tmp2;
667 struct octeon_soft_command *sc;
669 spin_lock(&oct->sc_buf_pool.lock);
671 list_for_each_safe(tmp, tmp2, &oct->sc_buf_pool.head) {
674 sc = (struct octeon_soft_command *)tmp;
676 lio_dma_free(oct, sc->size, sc, sc->dma_addr);
679 INIT_LIST_HEAD(&oct->sc_buf_pool.head);
681 spin_unlock(&oct->sc_buf_pool.lock);
686 struct octeon_soft_command *octeon_alloc_soft_command(struct octeon_device *oct,
693 u32 offset = sizeof(struct octeon_soft_command);
694 struct octeon_soft_command *sc = NULL;
695 struct list_head *tmp;
697 BUG_ON((offset + datasize + rdatasize + ctxsize) >
698 SOFT_COMMAND_BUFFER_SIZE);
700 spin_lock(&oct->sc_buf_pool.lock);
702 if (list_empty(&oct->sc_buf_pool.head)) {
703 spin_unlock(&oct->sc_buf_pool.lock);
707 list_for_each(tmp, &oct->sc_buf_pool.head)
712 atomic_inc(&oct->sc_buf_pool.alloc_buf_count);
714 spin_unlock(&oct->sc_buf_pool.lock);
716 sc = (struct octeon_soft_command *)tmp;
718 dma_addr = sc->dma_addr;
721 memset(sc, 0, sc->size);
723 sc->dma_addr = dma_addr;
727 sc->ctxptr = (u8 *)sc + offset;
728 sc->ctxsize = ctxsize;
731 /* Start data at 128 byte boundary */
732 offset = (offset + ctxsize + 127) & 0xffffff80;
735 sc->virtdptr = (u8 *)sc + offset;
736 sc->dmadptr = dma_addr + offset;
737 sc->datasize = datasize;
740 /* Start rdata at 128 byte boundary */
741 offset = (offset + datasize + 127) & 0xffffff80;
744 BUG_ON(rdatasize < 16);
745 sc->virtrptr = (u8 *)sc + offset;
746 sc->dmarptr = dma_addr + offset;
747 sc->rdatasize = rdatasize;
748 sc->status_word = (u64 *)((u8 *)(sc->virtrptr) + rdatasize - 8);
754 void octeon_free_soft_command(struct octeon_device *oct,
755 struct octeon_soft_command *sc)
757 spin_lock(&oct->sc_buf_pool.lock);
759 list_add_tail(&sc->node, &oct->sc_buf_pool.head);
761 atomic_dec(&oct->sc_buf_pool.alloc_buf_count);
763 spin_unlock(&oct->sc_buf_pool.lock);