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24 * \brief Host Driver: Implementation of Octeon input queues. "Input" is
25 * with respect to the Octeon device on the NIC. From this driver's
26 * point of view they are egress queues.
29 #ifndef __OCTEON_IQ_H__
30 #define __OCTEON_IQ_H__
32 #define IQ_STATUS_RUNNING 1
35 #define IQ_SEND_STOP 1
36 #define IQ_SEND_FAILED -1
38 /*------------------------- INSTRUCTION QUEUE --------------------------*/
42 #define REQTYPE_NONE 0
43 #define REQTYPE_NORESP_NET 1
44 #define REQTYPE_NORESP_NET_SG 2
45 #define REQTYPE_RESP_NET 3
46 #define REQTYPE_RESP_NET_SG 4
47 #define REQTYPE_SOFT_COMMAND 5
48 #define REQTYPE_LAST 5
50 struct octeon_request_list {
57 /** Input Queue statistics. Each input queue has four stats fields. */
59 u64 instr_posted; /**< Instructions posted to this queue. */
60 u64 instr_processed; /**< Instructions processed in this queue. */
61 u64 instr_dropped; /**< Instructions that could not be processed */
62 u64 bytes_sent; /**< Bytes sent through this queue. */
63 u64 sgentry_sent;/**< Gather entries sent through this queue. */
64 u64 tx_done;/**< Num of packets sent to network. */
65 u64 tx_iq_busy;/**< Numof times this iq was found to be full. */
66 u64 tx_dropped;/**< Numof pkts dropped dueto xmitpath errors. */
67 u64 tx_tot_bytes;/**< Total count of bytes sento to network. */
70 #define OCT_IQ_STATS_SIZE (sizeof(struct oct_iq_stats))
72 /** The instruction (input) queue.
73 * The input queue is used to post raw (instruction) mode data or packet
74 * data to Octeon device from the host. Each input queue (upto 4) for
75 * a Octeon device has one such structure to represent it.
77 struct octeon_instr_queue {
78 /** A spinlock to protect access to the input ring. */
81 /** Flag that indicates if the queue uses 64 byte commands. */
89 /* Controls the periodic flushing of iq */
94 /** Maximum no. of instructions in this queue. */
97 /** Index in input ring where the driver should write the next packet */
100 /** Index in input ring where Octeon is expected to read the next
103 u32 octeon_read_index;
105 /** This index aids in finding the window in the queue where Octeon
106 * has read the commands.
110 /** This field keeps track of the instructions pending in this queue. */
111 atomic_t instr_pending;
115 /** Pointer to the Virtual Base addr of the input ring. */
118 struct octeon_request_list *request_list;
120 /** Octeon doorbell register for the ring. */
121 void __iomem *doorbell_reg;
123 /** Octeon instruction count register for this ring. */
124 void __iomem *inst_cnt_reg;
126 /** Number of instructions pending to be posted to Octeon. */
129 /** The max. number of instructions that can be held pending by the
134 /** The last time that the doorbell was rung. */
137 /** The doorbell timeout. If the doorbell was not rung for this time and
138 * fill_cnt is non-zero, ring the doorbell again.
142 /** Statistics for this input queue. */
143 struct oct_iq_stats stats;
145 /** DMA mapped base address of the input descriptor ring. */
148 /** Application context */
152 /*---------------------- INSTRUCTION FORMAT ----------------------------*/
154 /** 32-byte instruction format.
155 * Format of instruction for a 32-byte mode input queue.
157 struct octeon_instr_32B {
158 /** Pointer where the input data is available. */
161 /** Instruction Header. */
164 /** Pointer where the response for a RAW mode packet will be written
169 /** Input Request Header. Additional info about the input. */
174 #define OCT_32B_INSTR_SIZE (sizeof(struct octeon_instr_32B))
176 /** 64-byte instruction format.
177 * Format of instruction for a 64-byte mode input queue.
179 struct octeon_instr_64B {
180 /** Pointer where the input data is available. */
183 /** Instruction Header. */
186 /** Input Request Header. */
189 /** opcode/subcode specific parameters */
192 /** Return Data Parameters */
195 /** Pointer where the response for a RAW mode packet will be written
204 #define OCT_64B_INSTR_SIZE (sizeof(struct octeon_instr_64B))
206 /** The size of each buffer in soft command buffer pool
208 #define SOFT_COMMAND_BUFFER_SIZE 1024
210 struct octeon_soft_command {
211 /** Soft command buffer info. */
212 struct list_head node;
216 /** Command and return status */
217 struct octeon_instr_64B cmd;
218 #define COMPLETION_WORD_INIT 0xffffffffffffffffULL
221 /** Data buffer info */
226 /** Return buffer info */
231 /** Context buffer info */
235 /** Time out and callback */
239 void (*callback)(struct octeon_device *, u32, void *);
243 /** Maximum number of buffers to allocate into soft command buffer pool
245 #define MAX_SOFT_COMMAND_BUFFERS 16
247 /** Head of a soft command buffer pool.
249 struct octeon_sc_buffer_pool {
250 /** List structure to add delete pending entries to */
251 struct list_head head;
253 /** A lock for this response list */
256 atomic_t alloc_buf_count;
259 int octeon_setup_sc_buffer_pool(struct octeon_device *oct);
260 int octeon_free_sc_buffer_pool(struct octeon_device *oct);
261 struct octeon_soft_command *
262 octeon_alloc_soft_command(struct octeon_device *oct,
263 u32 datasize, u32 rdatasize,
265 void octeon_free_soft_command(struct octeon_device *oct,
266 struct octeon_soft_command *sc);
269 * octeon_init_instr_queue()
270 * @param octeon_dev - pointer to the octeon device structure.
271 * @param iq_no - queue to be initialized (0 <= q_no <= 3).
273 * Called at driver init time for each input queue. iq_conf has the
274 * configuration parameters for the queue.
276 * @return Success: 0 Failure: 1
278 int octeon_init_instr_queue(struct octeon_device *octeon_dev, u32 iq_no,
282 * octeon_delete_instr_queue()
283 * @param octeon_dev - pointer to the octeon device structure.
284 * @param iq_no - queue to be deleted (0 <= q_no <= 3).
286 * Called at driver unload time for each input queue. Deletes all
287 * allocated resources for the input queue.
289 * @return Success: 0 Failure: 1
291 int octeon_delete_instr_queue(struct octeon_device *octeon_dev, u32 iq_no);
293 int lio_wait_for_instr_fetch(struct octeon_device *oct);
296 octeon_register_reqtype_free_fn(struct octeon_device *oct, int reqtype,
300 lio_process_iq_request_list(struct octeon_device *oct,
301 struct octeon_instr_queue *iq);
303 int octeon_send_command(struct octeon_device *oct, u32 iq_no,
304 u32 force_db, void *cmd, void *buf,
305 u32 datasize, u32 reqtype);
307 void octeon_prepare_soft_command(struct octeon_device *oct,
308 struct octeon_soft_command *sc,
309 u8 opcode, u8 subcode,
310 u32 irh_ossp, u64 ossp0,
313 int octeon_send_soft_command(struct octeon_device *oct,
314 struct octeon_soft_command *sc);
316 int octeon_setup_iq(struct octeon_device *oct, u32 iq_no,
317 u32 num_descs, void *app_ctx);
319 #endif /* __OCTEON_IQ_H__ */