1 // SPDX-License-Identifier: GPL-2.0-only
3 * Cadence MACB/GEM Ethernet Controller driver
5 * Copyright (C) 2004-2006 Atmel Corporation
8 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
10 #include <linux/clk-provider.h>
11 #include <linux/crc32.h>
12 #include <linux/module.h>
13 #include <linux/moduleparam.h>
14 #include <linux/kernel.h>
15 #include <linux/types.h>
16 #include <linux/circ_buf.h>
17 #include <linux/slab.h>
18 #include <linux/init.h>
20 #include <linux/gpio.h>
21 #include <linux/gpio/consumer.h>
22 #include <linux/interrupt.h>
23 #include <linux/netdevice.h>
24 #include <linux/etherdevice.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/platform_data/macb.h>
27 #include <linux/platform_device.h>
28 #include <linux/phylink.h>
30 #include <linux/of_device.h>
31 #include <linux/of_gpio.h>
32 #include <linux/of_mdio.h>
33 #include <linux/of_net.h>
35 #include <linux/udp.h>
36 #include <linux/tcp.h>
37 #include <linux/iopoll.h>
38 #include <linux/pm_runtime.h>
41 /* This structure is only used for MACB on SiFive FU540 devices */
42 struct sifive_fu540_macb_mgmt {
48 #define MACB_RX_BUFFER_SIZE 128
49 #define RX_BUFFER_MULTIPLE 64 /* bytes */
51 #define DEFAULT_RX_RING_SIZE 512 /* must be power of 2 */
52 #define MIN_RX_RING_SIZE 64
53 #define MAX_RX_RING_SIZE 8192
54 #define RX_RING_BYTES(bp) (macb_dma_desc_get_size(bp) \
57 #define DEFAULT_TX_RING_SIZE 512 /* must be power of 2 */
58 #define MIN_TX_RING_SIZE 64
59 #define MAX_TX_RING_SIZE 4096
60 #define TX_RING_BYTES(bp) (macb_dma_desc_get_size(bp) \
63 /* level of occupied TX descriptors under which we wake up TX process */
64 #define MACB_TX_WAKEUP_THRESH(bp) (3 * (bp)->tx_ring_size / 4)
66 #define MACB_RX_INT_FLAGS (MACB_BIT(RCOMP) | MACB_BIT(ISR_ROVR))
67 #define MACB_TX_ERR_FLAGS (MACB_BIT(ISR_TUND) \
70 #define MACB_TX_INT_FLAGS (MACB_TX_ERR_FLAGS | MACB_BIT(TCOMP) \
73 /* Max length of transmit frame must be a multiple of 8 bytes */
74 #define MACB_TX_LEN_ALIGN 8
75 #define MACB_MAX_TX_LEN ((unsigned int)((1 << MACB_TX_FRMLEN_SIZE) - 1) & ~((unsigned int)(MACB_TX_LEN_ALIGN - 1)))
76 /* Limit maximum TX length as per Cadence TSO errata. This is to avoid a
77 * false amba_error in TX path from the DMA assuming there is not enough
78 * space in the SRAM (16KB) even when there is.
80 #define GEM_MAX_TX_LEN (unsigned int)(0x3FC0)
82 #define GEM_MTU_MIN_SIZE ETH_MIN_MTU
83 #define MACB_NETIF_LSO NETIF_F_TSO
85 #define MACB_WOL_HAS_MAGIC_PACKET (0x1 << 0)
86 #define MACB_WOL_ENABLED (0x1 << 1)
88 /* Graceful stop timeouts in us. We should allow up to
89 * 1 frame time (10 Mbits/s, full-duplex, ignoring collisions)
91 #define MACB_HALT_TIMEOUT 1230
93 #define MACB_PM_TIMEOUT 100 /* ms */
95 #define MACB_MDIO_TIMEOUT 1000000 /* in usecs */
97 /* DMA buffer descriptor might be different size
98 * depends on hardware configuration:
100 * 1. dma address width 32 bits:
101 * word 1: 32 bit address of Data Buffer
104 * 2. dma address width 64 bits:
105 * word 1: 32 bit address of Data Buffer
107 * word 3: upper 32 bit address of Data Buffer
110 * 3. dma address width 32 bits with hardware timestamping:
111 * word 1: 32 bit address of Data Buffer
113 * word 3: timestamp word 1
114 * word 4: timestamp word 2
116 * 4. dma address width 64 bits with hardware timestamping:
117 * word 1: 32 bit address of Data Buffer
119 * word 3: upper 32 bit address of Data Buffer
121 * word 5: timestamp word 1
122 * word 6: timestamp word 2
124 static unsigned int macb_dma_desc_get_size(struct macb *bp)
127 unsigned int desc_size;
129 switch (bp->hw_dma_cap) {
131 desc_size = sizeof(struct macb_dma_desc)
132 + sizeof(struct macb_dma_desc_64);
135 desc_size = sizeof(struct macb_dma_desc)
136 + sizeof(struct macb_dma_desc_ptp);
138 case HW_DMA_CAP_64B_PTP:
139 desc_size = sizeof(struct macb_dma_desc)
140 + sizeof(struct macb_dma_desc_64)
141 + sizeof(struct macb_dma_desc_ptp);
144 desc_size = sizeof(struct macb_dma_desc);
148 return sizeof(struct macb_dma_desc);
151 static unsigned int macb_adj_dma_desc_idx(struct macb *bp, unsigned int desc_idx)
154 switch (bp->hw_dma_cap) {
159 case HW_DMA_CAP_64B_PTP:
169 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
170 static struct macb_dma_desc_64 *macb_64b_desc(struct macb *bp, struct macb_dma_desc *desc)
172 return (struct macb_dma_desc_64 *)((void *)desc
173 + sizeof(struct macb_dma_desc));
177 /* Ring buffer accessors */
178 static unsigned int macb_tx_ring_wrap(struct macb *bp, unsigned int index)
180 return index & (bp->tx_ring_size - 1);
183 static struct macb_dma_desc *macb_tx_desc(struct macb_queue *queue,
186 index = macb_tx_ring_wrap(queue->bp, index);
187 index = macb_adj_dma_desc_idx(queue->bp, index);
188 return &queue->tx_ring[index];
191 static struct macb_tx_skb *macb_tx_skb(struct macb_queue *queue,
194 return &queue->tx_skb[macb_tx_ring_wrap(queue->bp, index)];
197 static dma_addr_t macb_tx_dma(struct macb_queue *queue, unsigned int index)
201 offset = macb_tx_ring_wrap(queue->bp, index) *
202 macb_dma_desc_get_size(queue->bp);
204 return queue->tx_ring_dma + offset;
207 static unsigned int macb_rx_ring_wrap(struct macb *bp, unsigned int index)
209 return index & (bp->rx_ring_size - 1);
212 static struct macb_dma_desc *macb_rx_desc(struct macb_queue *queue, unsigned int index)
214 index = macb_rx_ring_wrap(queue->bp, index);
215 index = macb_adj_dma_desc_idx(queue->bp, index);
216 return &queue->rx_ring[index];
219 static void *macb_rx_buffer(struct macb_queue *queue, unsigned int index)
221 return queue->rx_buffers + queue->bp->rx_buffer_size *
222 macb_rx_ring_wrap(queue->bp, index);
226 static u32 hw_readl_native(struct macb *bp, int offset)
228 return __raw_readl(bp->regs + offset);
231 static void hw_writel_native(struct macb *bp, int offset, u32 value)
233 __raw_writel(value, bp->regs + offset);
236 static u32 hw_readl(struct macb *bp, int offset)
238 return readl_relaxed(bp->regs + offset);
241 static void hw_writel(struct macb *bp, int offset, u32 value)
243 writel_relaxed(value, bp->regs + offset);
246 /* Find the CPU endianness by using the loopback bit of NCR register. When the
247 * CPU is in big endian we need to program swapped mode for management
250 static bool hw_is_native_io(void __iomem *addr)
252 u32 value = MACB_BIT(LLB);
254 __raw_writel(value, addr + MACB_NCR);
255 value = __raw_readl(addr + MACB_NCR);
257 /* Write 0 back to disable everything */
258 __raw_writel(0, addr + MACB_NCR);
260 return value == MACB_BIT(LLB);
263 static bool hw_is_gem(void __iomem *addr, bool native_io)
268 id = __raw_readl(addr + MACB_MID);
270 id = readl_relaxed(addr + MACB_MID);
272 return MACB_BFEXT(IDNUM, id) >= 0x2;
275 static void macb_set_hwaddr(struct macb *bp)
280 bottom = cpu_to_le32(*((u32 *)bp->dev->dev_addr));
281 macb_or_gem_writel(bp, SA1B, bottom);
282 top = cpu_to_le16(*((u16 *)(bp->dev->dev_addr + 4)));
283 macb_or_gem_writel(bp, SA1T, top);
285 /* Clear unused address register sets */
286 macb_or_gem_writel(bp, SA2B, 0);
287 macb_or_gem_writel(bp, SA2T, 0);
288 macb_or_gem_writel(bp, SA3B, 0);
289 macb_or_gem_writel(bp, SA3T, 0);
290 macb_or_gem_writel(bp, SA4B, 0);
291 macb_or_gem_writel(bp, SA4T, 0);
294 static void macb_get_hwaddr(struct macb *bp)
301 /* Check all 4 address register for valid address */
302 for (i = 0; i < 4; i++) {
303 bottom = macb_or_gem_readl(bp, SA1B + i * 8);
304 top = macb_or_gem_readl(bp, SA1T + i * 8);
306 addr[0] = bottom & 0xff;
307 addr[1] = (bottom >> 8) & 0xff;
308 addr[2] = (bottom >> 16) & 0xff;
309 addr[3] = (bottom >> 24) & 0xff;
310 addr[4] = top & 0xff;
311 addr[5] = (top >> 8) & 0xff;
313 if (is_valid_ether_addr(addr)) {
314 memcpy(bp->dev->dev_addr, addr, sizeof(addr));
319 dev_info(&bp->pdev->dev, "invalid hw address, using random\n");
320 eth_hw_addr_random(bp->dev);
323 static int macb_mdio_wait_for_idle(struct macb *bp)
327 return readx_poll_timeout(MACB_READ_NSR, bp, val, val & MACB_BIT(IDLE),
328 1, MACB_MDIO_TIMEOUT);
331 static int macb_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
333 struct macb *bp = bus->priv;
336 status = pm_runtime_get_sync(&bp->pdev->dev);
340 status = macb_mdio_wait_for_idle(bp);
344 if (regnum & MII_ADDR_C45) {
345 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_C45_SOF)
346 | MACB_BF(RW, MACB_MAN_C45_ADDR)
347 | MACB_BF(PHYA, mii_id)
348 | MACB_BF(REGA, (regnum >> 16) & 0x1F)
349 | MACB_BF(DATA, regnum & 0xFFFF)
350 | MACB_BF(CODE, MACB_MAN_C45_CODE)));
352 status = macb_mdio_wait_for_idle(bp);
356 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_C45_SOF)
357 | MACB_BF(RW, MACB_MAN_C45_READ)
358 | MACB_BF(PHYA, mii_id)
359 | MACB_BF(REGA, (regnum >> 16) & 0x1F)
360 | MACB_BF(CODE, MACB_MAN_C45_CODE)));
362 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_C22_SOF)
363 | MACB_BF(RW, MACB_MAN_C22_READ)
364 | MACB_BF(PHYA, mii_id)
365 | MACB_BF(REGA, regnum)
366 | MACB_BF(CODE, MACB_MAN_C22_CODE)));
369 status = macb_mdio_wait_for_idle(bp);
373 status = MACB_BFEXT(DATA, macb_readl(bp, MAN));
376 pm_runtime_mark_last_busy(&bp->pdev->dev);
377 pm_runtime_put_autosuspend(&bp->pdev->dev);
382 static int macb_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
385 struct macb *bp = bus->priv;
388 status = pm_runtime_get_sync(&bp->pdev->dev);
392 status = macb_mdio_wait_for_idle(bp);
394 goto mdio_write_exit;
396 if (regnum & MII_ADDR_C45) {
397 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_C45_SOF)
398 | MACB_BF(RW, MACB_MAN_C45_ADDR)
399 | MACB_BF(PHYA, mii_id)
400 | MACB_BF(REGA, (regnum >> 16) & 0x1F)
401 | MACB_BF(DATA, regnum & 0xFFFF)
402 | MACB_BF(CODE, MACB_MAN_C45_CODE)));
404 status = macb_mdio_wait_for_idle(bp);
406 goto mdio_write_exit;
408 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_C45_SOF)
409 | MACB_BF(RW, MACB_MAN_C45_WRITE)
410 | MACB_BF(PHYA, mii_id)
411 | MACB_BF(REGA, (regnum >> 16) & 0x1F)
412 | MACB_BF(CODE, MACB_MAN_C45_CODE)
413 | MACB_BF(DATA, value)));
415 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_C22_SOF)
416 | MACB_BF(RW, MACB_MAN_C22_WRITE)
417 | MACB_BF(PHYA, mii_id)
418 | MACB_BF(REGA, regnum)
419 | MACB_BF(CODE, MACB_MAN_C22_CODE)
420 | MACB_BF(DATA, value)));
423 status = macb_mdio_wait_for_idle(bp);
425 goto mdio_write_exit;
428 pm_runtime_mark_last_busy(&bp->pdev->dev);
429 pm_runtime_put_autosuspend(&bp->pdev->dev);
434 static void macb_init_buffers(struct macb *bp)
436 struct macb_queue *queue;
439 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
440 queue_writel(queue, RBQP, lower_32_bits(queue->rx_ring_dma));
441 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
442 if (bp->hw_dma_cap & HW_DMA_CAP_64B)
443 queue_writel(queue, RBQPH,
444 upper_32_bits(queue->rx_ring_dma));
446 queue_writel(queue, TBQP, lower_32_bits(queue->tx_ring_dma));
447 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
448 if (bp->hw_dma_cap & HW_DMA_CAP_64B)
449 queue_writel(queue, TBQPH,
450 upper_32_bits(queue->tx_ring_dma));
456 * macb_set_tx_clk() - Set a clock to a new frequency
457 * @clk Pointer to the clock to change
458 * @rate New frequency in Hz
459 * @dev Pointer to the struct net_device
461 static void macb_set_tx_clk(struct clk *clk, int speed, struct net_device *dev)
463 long ferr, rate, rate_rounded;
482 rate_rounded = clk_round_rate(clk, rate);
483 if (rate_rounded < 0)
486 /* RGMII allows 50 ppm frequency error. Test and warn if this limit
489 ferr = abs(rate_rounded - rate);
490 ferr = DIV_ROUND_UP(ferr, rate / 100000);
492 netdev_warn(dev, "unable to generate target frequency: %ld Hz\n",
495 if (clk_set_rate(clk, rate_rounded))
496 netdev_err(dev, "adjusting tx_clk failed.\n");
499 static void macb_validate(struct phylink_config *config,
500 unsigned long *supported,
501 struct phylink_link_state *state)
503 struct net_device *ndev = to_net_dev(config->dev);
504 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
505 struct macb *bp = netdev_priv(ndev);
507 /* We only support MII, RMII, GMII, RGMII & SGMII. */
508 if (state->interface != PHY_INTERFACE_MODE_NA &&
509 state->interface != PHY_INTERFACE_MODE_MII &&
510 state->interface != PHY_INTERFACE_MODE_RMII &&
511 state->interface != PHY_INTERFACE_MODE_GMII &&
512 state->interface != PHY_INTERFACE_MODE_SGMII &&
513 !phy_interface_mode_is_rgmii(state->interface)) {
514 bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS);
518 if (!macb_is_gem(bp) &&
519 (state->interface == PHY_INTERFACE_MODE_GMII ||
520 phy_interface_mode_is_rgmii(state->interface))) {
521 bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS);
525 phylink_set_port_modes(mask);
526 phylink_set(mask, Autoneg);
527 phylink_set(mask, Asym_Pause);
529 phylink_set(mask, 10baseT_Half);
530 phylink_set(mask, 10baseT_Full);
531 phylink_set(mask, 100baseT_Half);
532 phylink_set(mask, 100baseT_Full);
534 if (bp->caps & MACB_CAPS_GIGABIT_MODE_AVAILABLE &&
535 (state->interface == PHY_INTERFACE_MODE_NA ||
536 state->interface == PHY_INTERFACE_MODE_GMII ||
537 state->interface == PHY_INTERFACE_MODE_SGMII ||
538 phy_interface_mode_is_rgmii(state->interface))) {
539 phylink_set(mask, 1000baseT_Full);
540 phylink_set(mask, 1000baseX_Full);
542 if (!(bp->caps & MACB_CAPS_NO_GIGABIT_HALF))
543 phylink_set(mask, 1000baseT_Half);
546 bitmap_and(supported, supported, mask, __ETHTOOL_LINK_MODE_MASK_NBITS);
547 bitmap_and(state->advertising, state->advertising, mask,
548 __ETHTOOL_LINK_MODE_MASK_NBITS);
551 static void macb_mac_pcs_get_state(struct phylink_config *config,
552 struct phylink_link_state *state)
557 static void macb_mac_an_restart(struct phylink_config *config)
562 static void macb_mac_config(struct phylink_config *config, unsigned int mode,
563 const struct phylink_link_state *state)
565 struct net_device *ndev = to_net_dev(config->dev);
566 struct macb *bp = netdev_priv(ndev);
570 spin_lock_irqsave(&bp->lock, flags);
572 old_ctrl = ctrl = macb_or_gem_readl(bp, NCFGR);
574 /* Clear all the bits we might set later */
575 ctrl &= ~(MACB_BIT(SPD) | MACB_BIT(FD) | MACB_BIT(PAE));
577 if (bp->caps & MACB_CAPS_MACB_IS_EMAC) {
578 if (state->interface == PHY_INTERFACE_MODE_RMII)
579 ctrl |= MACB_BIT(RM9200_RMII);
581 ctrl &= ~(GEM_BIT(GBE) | GEM_BIT(SGMIIEN) | GEM_BIT(PCSSEL));
583 /* We do not support MLO_PAUSE_RX yet */
584 if (state->pause & MLO_PAUSE_TX)
585 ctrl |= MACB_BIT(PAE);
587 if (state->interface == PHY_INTERFACE_MODE_SGMII)
588 ctrl |= GEM_BIT(SGMIIEN) | GEM_BIT(PCSSEL);
591 if (state->speed == SPEED_1000)
592 ctrl |= GEM_BIT(GBE);
593 else if (state->speed == SPEED_100)
594 ctrl |= MACB_BIT(SPD);
597 ctrl |= MACB_BIT(FD);
599 /* Apply the new configuration, if any */
601 macb_or_gem_writel(bp, NCFGR, ctrl);
603 bp->speed = state->speed;
605 spin_unlock_irqrestore(&bp->lock, flags);
608 static void macb_mac_link_down(struct phylink_config *config, unsigned int mode,
609 phy_interface_t interface)
611 struct net_device *ndev = to_net_dev(config->dev);
612 struct macb *bp = netdev_priv(ndev);
613 struct macb_queue *queue;
617 if (!(bp->caps & MACB_CAPS_MACB_IS_EMAC))
618 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue)
619 queue_writel(queue, IDR,
620 bp->rx_intr_mask | MACB_TX_INT_FLAGS | MACB_BIT(HRESP));
622 /* Disable Rx and Tx */
623 ctrl = macb_readl(bp, NCR) & ~(MACB_BIT(RE) | MACB_BIT(TE));
624 macb_writel(bp, NCR, ctrl);
626 netif_tx_stop_all_queues(ndev);
629 static void macb_mac_link_up(struct phylink_config *config, unsigned int mode,
630 phy_interface_t interface, struct phy_device *phy)
632 struct net_device *ndev = to_net_dev(config->dev);
633 struct macb *bp = netdev_priv(ndev);
634 struct macb_queue *queue;
637 if (!(bp->caps & MACB_CAPS_MACB_IS_EMAC)) {
638 macb_set_tx_clk(bp->tx_clk, bp->speed, ndev);
640 /* Initialize rings & buffers as clearing MACB_BIT(TE) in link down
641 * cleared the pipeline and control registers.
643 bp->macbgem_ops.mog_init_rings(bp);
644 macb_init_buffers(bp);
646 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue)
647 queue_writel(queue, IER,
648 bp->rx_intr_mask | MACB_TX_INT_FLAGS | MACB_BIT(HRESP));
651 /* Enable Rx and Tx */
652 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(RE) | MACB_BIT(TE));
654 netif_tx_wake_all_queues(ndev);
657 static const struct phylink_mac_ops macb_phylink_ops = {
658 .validate = macb_validate,
659 .mac_pcs_get_state = macb_mac_pcs_get_state,
660 .mac_an_restart = macb_mac_an_restart,
661 .mac_config = macb_mac_config,
662 .mac_link_down = macb_mac_link_down,
663 .mac_link_up = macb_mac_link_up,
666 static bool macb_phy_handle_exists(struct device_node *dn)
668 dn = of_parse_phandle(dn, "phy-handle", 0);
673 static int macb_phylink_connect(struct macb *bp)
675 struct device_node *dn = bp->pdev->dev.of_node;
676 struct net_device *dev = bp->dev;
677 struct phy_device *phydev;
681 ret = phylink_of_phy_connect(bp->phylink, dn, 0);
683 if (!dn || (ret && !macb_phy_handle_exists(dn))) {
684 phydev = phy_find_first(bp->mii_bus);
686 netdev_err(dev, "no PHY found\n");
690 /* attach the mac to the phy */
691 ret = phylink_connect_phy(bp->phylink, phydev);
695 netdev_err(dev, "Could not attach PHY (%d)\n", ret);
699 phylink_start(bp->phylink);
704 /* based on au1000_eth. c*/
705 static int macb_mii_probe(struct net_device *dev)
707 struct macb *bp = netdev_priv(dev);
709 bp->phylink_config.dev = &dev->dev;
710 bp->phylink_config.type = PHYLINK_NETDEV;
712 bp->phylink = phylink_create(&bp->phylink_config, bp->pdev->dev.fwnode,
713 bp->phy_interface, &macb_phylink_ops);
714 if (IS_ERR(bp->phylink)) {
715 netdev_err(dev, "Could not create a phylink instance (%ld)\n",
716 PTR_ERR(bp->phylink));
717 return PTR_ERR(bp->phylink);
723 static int macb_mdiobus_register(struct macb *bp)
725 struct device_node *child, *np = bp->pdev->dev.of_node;
727 /* Only create the PHY from the device tree if at least one PHY is
728 * described. Otherwise scan the entire MDIO bus. We do this to support
729 * old device tree that did not follow the best practices and did not
730 * describe their network PHYs.
732 for_each_available_child_of_node(np, child)
733 if (of_mdiobus_child_is_phy(child)) {
734 /* The loop increments the child refcount,
735 * decrement it before returning.
739 return of_mdiobus_register(bp->mii_bus, np);
742 return mdiobus_register(bp->mii_bus);
745 static int macb_mii_init(struct macb *bp)
749 /* Enable management port */
750 macb_writel(bp, NCR, MACB_BIT(MPE));
752 bp->mii_bus = mdiobus_alloc();
758 bp->mii_bus->name = "MACB_mii_bus";
759 bp->mii_bus->read = &macb_mdio_read;
760 bp->mii_bus->write = &macb_mdio_write;
761 snprintf(bp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
762 bp->pdev->name, bp->pdev->id);
763 bp->mii_bus->priv = bp;
764 bp->mii_bus->parent = &bp->pdev->dev;
766 dev_set_drvdata(&bp->dev->dev, bp->mii_bus);
768 err = macb_mdiobus_register(bp);
770 goto err_out_free_mdiobus;
772 err = macb_mii_probe(bp->dev);
774 goto err_out_unregister_bus;
778 err_out_unregister_bus:
779 mdiobus_unregister(bp->mii_bus);
780 err_out_free_mdiobus:
781 mdiobus_free(bp->mii_bus);
786 static void macb_update_stats(struct macb *bp)
788 u32 *p = &bp->hw_stats.macb.rx_pause_frames;
789 u32 *end = &bp->hw_stats.macb.tx_pause_frames + 1;
790 int offset = MACB_PFR;
792 WARN_ON((unsigned long)(end - p - 1) != (MACB_TPF - MACB_PFR) / 4);
794 for (; p < end; p++, offset += 4)
795 *p += bp->macb_reg_readl(bp, offset);
798 static int macb_halt_tx(struct macb *bp)
800 unsigned long halt_time, timeout;
803 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(THALT));
805 timeout = jiffies + usecs_to_jiffies(MACB_HALT_TIMEOUT);
808 status = macb_readl(bp, TSR);
809 if (!(status & MACB_BIT(TGO)))
813 } while (time_before(halt_time, timeout));
818 static void macb_tx_unmap(struct macb *bp, struct macb_tx_skb *tx_skb)
820 if (tx_skb->mapping) {
821 if (tx_skb->mapped_as_page)
822 dma_unmap_page(&bp->pdev->dev, tx_skb->mapping,
823 tx_skb->size, DMA_TO_DEVICE);
825 dma_unmap_single(&bp->pdev->dev, tx_skb->mapping,
826 tx_skb->size, DMA_TO_DEVICE);
831 dev_kfree_skb_any(tx_skb->skb);
836 static void macb_set_addr(struct macb *bp, struct macb_dma_desc *desc, dma_addr_t addr)
838 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
839 struct macb_dma_desc_64 *desc_64;
841 if (bp->hw_dma_cap & HW_DMA_CAP_64B) {
842 desc_64 = macb_64b_desc(bp, desc);
843 desc_64->addrh = upper_32_bits(addr);
844 /* The low bits of RX address contain the RX_USED bit, clearing
845 * of which allows packet RX. Make sure the high bits are also
846 * visible to HW at that point.
851 desc->addr = lower_32_bits(addr);
854 static dma_addr_t macb_get_addr(struct macb *bp, struct macb_dma_desc *desc)
857 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
858 struct macb_dma_desc_64 *desc_64;
860 if (bp->hw_dma_cap & HW_DMA_CAP_64B) {
861 desc_64 = macb_64b_desc(bp, desc);
862 addr = ((u64)(desc_64->addrh) << 32);
865 addr |= MACB_BF(RX_WADDR, MACB_BFEXT(RX_WADDR, desc->addr));
869 static void macb_tx_error_task(struct work_struct *work)
871 struct macb_queue *queue = container_of(work, struct macb_queue,
873 struct macb *bp = queue->bp;
874 struct macb_tx_skb *tx_skb;
875 struct macb_dma_desc *desc;
880 netdev_vdbg(bp->dev, "macb_tx_error_task: q = %u, t = %u, h = %u\n",
881 (unsigned int)(queue - bp->queues),
882 queue->tx_tail, queue->tx_head);
884 /* Prevent the queue IRQ handlers from running: each of them may call
885 * macb_tx_interrupt(), which in turn may call netif_wake_subqueue().
886 * As explained below, we have to halt the transmission before updating
887 * TBQP registers so we call netif_tx_stop_all_queues() to notify the
888 * network engine about the macb/gem being halted.
890 spin_lock_irqsave(&bp->lock, flags);
892 /* Make sure nobody is trying to queue up new packets */
893 netif_tx_stop_all_queues(bp->dev);
895 /* Stop transmission now
896 * (in case we have just queued new packets)
897 * macb/gem must be halted to write TBQP register
899 if (macb_halt_tx(bp))
900 /* Just complain for now, reinitializing TX path can be good */
901 netdev_err(bp->dev, "BUG: halt tx timed out\n");
903 /* Treat frames in TX queue including the ones that caused the error.
904 * Free transmit buffers in upper layer.
906 for (tail = queue->tx_tail; tail != queue->tx_head; tail++) {
909 desc = macb_tx_desc(queue, tail);
911 tx_skb = macb_tx_skb(queue, tail);
914 if (ctrl & MACB_BIT(TX_USED)) {
915 /* skb is set for the last buffer of the frame */
917 macb_tx_unmap(bp, tx_skb);
919 tx_skb = macb_tx_skb(queue, tail);
923 /* ctrl still refers to the first buffer descriptor
924 * since it's the only one written back by the hardware
926 if (!(ctrl & MACB_BIT(TX_BUF_EXHAUSTED))) {
927 netdev_vdbg(bp->dev, "txerr skb %u (data %p) TX complete\n",
928 macb_tx_ring_wrap(bp, tail),
930 bp->dev->stats.tx_packets++;
931 queue->stats.tx_packets++;
932 bp->dev->stats.tx_bytes += skb->len;
933 queue->stats.tx_bytes += skb->len;
936 /* "Buffers exhausted mid-frame" errors may only happen
937 * if the driver is buggy, so complain loudly about
938 * those. Statistics are updated by hardware.
940 if (ctrl & MACB_BIT(TX_BUF_EXHAUSTED))
942 "BUG: TX buffers exhausted mid-frame\n");
944 desc->ctrl = ctrl | MACB_BIT(TX_USED);
947 macb_tx_unmap(bp, tx_skb);
950 /* Set end of TX queue */
951 desc = macb_tx_desc(queue, 0);
952 macb_set_addr(bp, desc, 0);
953 desc->ctrl = MACB_BIT(TX_USED);
955 /* Make descriptor updates visible to hardware */
958 /* Reinitialize the TX desc queue */
959 queue_writel(queue, TBQP, lower_32_bits(queue->tx_ring_dma));
960 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
961 if (bp->hw_dma_cap & HW_DMA_CAP_64B)
962 queue_writel(queue, TBQPH, upper_32_bits(queue->tx_ring_dma));
964 /* Make TX ring reflect state of hardware */
968 /* Housework before enabling TX IRQ */
969 macb_writel(bp, TSR, macb_readl(bp, TSR));
970 queue_writel(queue, IER, MACB_TX_INT_FLAGS);
972 /* Now we are ready to start transmission again */
973 netif_tx_start_all_queues(bp->dev);
974 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(TSTART));
976 spin_unlock_irqrestore(&bp->lock, flags);
979 static void macb_tx_interrupt(struct macb_queue *queue)
984 struct macb *bp = queue->bp;
985 u16 queue_index = queue - bp->queues;
987 status = macb_readl(bp, TSR);
988 macb_writel(bp, TSR, status);
990 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
991 queue_writel(queue, ISR, MACB_BIT(TCOMP));
993 netdev_vdbg(bp->dev, "macb_tx_interrupt status = 0x%03lx\n",
994 (unsigned long)status);
996 head = queue->tx_head;
997 for (tail = queue->tx_tail; tail != head; tail++) {
998 struct macb_tx_skb *tx_skb;
1000 struct macb_dma_desc *desc;
1003 desc = macb_tx_desc(queue, tail);
1005 /* Make hw descriptor updates visible to CPU */
1010 /* TX_USED bit is only set by hardware on the very first buffer
1011 * descriptor of the transmitted frame.
1013 if (!(ctrl & MACB_BIT(TX_USED)))
1016 /* Process all buffers of the current transmitted frame */
1018 tx_skb = macb_tx_skb(queue, tail);
1021 /* First, update TX stats if needed */
1023 if (unlikely(skb_shinfo(skb)->tx_flags &
1025 gem_ptp_do_txstamp(queue, skb, desc) == 0) {
1026 /* skb now belongs to timestamp buffer
1027 * and will be removed later
1031 netdev_vdbg(bp->dev, "skb %u (data %p) TX complete\n",
1032 macb_tx_ring_wrap(bp, tail),
1034 bp->dev->stats.tx_packets++;
1035 queue->stats.tx_packets++;
1036 bp->dev->stats.tx_bytes += skb->len;
1037 queue->stats.tx_bytes += skb->len;
1040 /* Now we can safely release resources */
1041 macb_tx_unmap(bp, tx_skb);
1043 /* skb is set only for the last buffer of the frame.
1044 * WARNING: at this point skb has been freed by
1052 queue->tx_tail = tail;
1053 if (__netif_subqueue_stopped(bp->dev, queue_index) &&
1054 CIRC_CNT(queue->tx_head, queue->tx_tail,
1055 bp->tx_ring_size) <= MACB_TX_WAKEUP_THRESH(bp))
1056 netif_wake_subqueue(bp->dev, queue_index);
1059 static void gem_rx_refill(struct macb_queue *queue)
1062 struct sk_buff *skb;
1064 struct macb *bp = queue->bp;
1065 struct macb_dma_desc *desc;
1067 while (CIRC_SPACE(queue->rx_prepared_head, queue->rx_tail,
1068 bp->rx_ring_size) > 0) {
1069 entry = macb_rx_ring_wrap(bp, queue->rx_prepared_head);
1071 /* Make hw descriptor updates visible to CPU */
1074 queue->rx_prepared_head++;
1075 desc = macb_rx_desc(queue, entry);
1077 if (!queue->rx_skbuff[entry]) {
1078 /* allocate sk_buff for this free entry in ring */
1079 skb = netdev_alloc_skb(bp->dev, bp->rx_buffer_size);
1080 if (unlikely(!skb)) {
1082 "Unable to allocate sk_buff\n");
1086 /* now fill corresponding descriptor entry */
1087 paddr = dma_map_single(&bp->pdev->dev, skb->data,
1090 if (dma_mapping_error(&bp->pdev->dev, paddr)) {
1095 queue->rx_skbuff[entry] = skb;
1097 if (entry == bp->rx_ring_size - 1)
1098 paddr |= MACB_BIT(RX_WRAP);
1100 /* Setting addr clears RX_USED and allows reception,
1101 * make sure ctrl is cleared first to avoid a race.
1104 macb_set_addr(bp, desc, paddr);
1106 /* properly align Ethernet header */
1107 skb_reserve(skb, NET_IP_ALIGN);
1111 desc->addr &= ~MACB_BIT(RX_USED);
1115 /* Make descriptor updates visible to hardware */
1118 netdev_vdbg(bp->dev, "rx ring: queue: %p, prepared head %d, tail %d\n",
1119 queue, queue->rx_prepared_head, queue->rx_tail);
1122 /* Mark DMA descriptors from begin up to and not including end as unused */
1123 static void discard_partial_frame(struct macb_queue *queue, unsigned int begin,
1128 for (frag = begin; frag != end; frag++) {
1129 struct macb_dma_desc *desc = macb_rx_desc(queue, frag);
1131 desc->addr &= ~MACB_BIT(RX_USED);
1134 /* Make descriptor updates visible to hardware */
1137 /* When this happens, the hardware stats registers for
1138 * whatever caused this is updated, so we don't have to record
1143 static int gem_rx(struct macb_queue *queue, struct napi_struct *napi,
1146 struct macb *bp = queue->bp;
1149 struct sk_buff *skb;
1150 struct macb_dma_desc *desc;
1153 while (count < budget) {
1158 entry = macb_rx_ring_wrap(bp, queue->rx_tail);
1159 desc = macb_rx_desc(queue, entry);
1161 /* Make hw descriptor updates visible to CPU */
1164 rxused = (desc->addr & MACB_BIT(RX_USED)) ? true : false;
1165 addr = macb_get_addr(bp, desc);
1170 /* Ensure ctrl is at least as up-to-date as rxused */
1178 if (!(ctrl & MACB_BIT(RX_SOF) && ctrl & MACB_BIT(RX_EOF))) {
1180 "not whole frame pointed by descriptor\n");
1181 bp->dev->stats.rx_dropped++;
1182 queue->stats.rx_dropped++;
1185 skb = queue->rx_skbuff[entry];
1186 if (unlikely(!skb)) {
1188 "inconsistent Rx descriptor chain\n");
1189 bp->dev->stats.rx_dropped++;
1190 queue->stats.rx_dropped++;
1193 /* now everything is ready for receiving packet */
1194 queue->rx_skbuff[entry] = NULL;
1195 len = ctrl & bp->rx_frm_len_mask;
1197 netdev_vdbg(bp->dev, "gem_rx %u (len %u)\n", entry, len);
1200 dma_unmap_single(&bp->pdev->dev, addr,
1201 bp->rx_buffer_size, DMA_FROM_DEVICE);
1203 skb->protocol = eth_type_trans(skb, bp->dev);
1204 skb_checksum_none_assert(skb);
1205 if (bp->dev->features & NETIF_F_RXCSUM &&
1206 !(bp->dev->flags & IFF_PROMISC) &&
1207 GEM_BFEXT(RX_CSUM, ctrl) & GEM_RX_CSUM_CHECKED_MASK)
1208 skb->ip_summed = CHECKSUM_UNNECESSARY;
1210 bp->dev->stats.rx_packets++;
1211 queue->stats.rx_packets++;
1212 bp->dev->stats.rx_bytes += skb->len;
1213 queue->stats.rx_bytes += skb->len;
1215 gem_ptp_do_rxstamp(bp, skb, desc);
1217 #if defined(DEBUG) && defined(VERBOSE_DEBUG)
1218 netdev_vdbg(bp->dev, "received skb of length %u, csum: %08x\n",
1219 skb->len, skb->csum);
1220 print_hex_dump(KERN_DEBUG, " mac: ", DUMP_PREFIX_ADDRESS, 16, 1,
1221 skb_mac_header(skb), 16, true);
1222 print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_ADDRESS, 16, 1,
1223 skb->data, 32, true);
1226 napi_gro_receive(napi, skb);
1229 gem_rx_refill(queue);
1234 static int macb_rx_frame(struct macb_queue *queue, struct napi_struct *napi,
1235 unsigned int first_frag, unsigned int last_frag)
1239 unsigned int offset;
1240 struct sk_buff *skb;
1241 struct macb_dma_desc *desc;
1242 struct macb *bp = queue->bp;
1244 desc = macb_rx_desc(queue, last_frag);
1245 len = desc->ctrl & bp->rx_frm_len_mask;
1247 netdev_vdbg(bp->dev, "macb_rx_frame frags %u - %u (len %u)\n",
1248 macb_rx_ring_wrap(bp, first_frag),
1249 macb_rx_ring_wrap(bp, last_frag), len);
1251 /* The ethernet header starts NET_IP_ALIGN bytes into the
1252 * first buffer. Since the header is 14 bytes, this makes the
1253 * payload word-aligned.
1255 * Instead of calling skb_reserve(NET_IP_ALIGN), we just copy
1256 * the two padding bytes into the skb so that we avoid hitting
1257 * the slowpath in memcpy(), and pull them off afterwards.
1259 skb = netdev_alloc_skb(bp->dev, len + NET_IP_ALIGN);
1261 bp->dev->stats.rx_dropped++;
1262 for (frag = first_frag; ; frag++) {
1263 desc = macb_rx_desc(queue, frag);
1264 desc->addr &= ~MACB_BIT(RX_USED);
1265 if (frag == last_frag)
1269 /* Make descriptor updates visible to hardware */
1276 len += NET_IP_ALIGN;
1277 skb_checksum_none_assert(skb);
1280 for (frag = first_frag; ; frag++) {
1281 unsigned int frag_len = bp->rx_buffer_size;
1283 if (offset + frag_len > len) {
1284 if (unlikely(frag != last_frag)) {
1285 dev_kfree_skb_any(skb);
1288 frag_len = len - offset;
1290 skb_copy_to_linear_data_offset(skb, offset,
1291 macb_rx_buffer(queue, frag),
1293 offset += bp->rx_buffer_size;
1294 desc = macb_rx_desc(queue, frag);
1295 desc->addr &= ~MACB_BIT(RX_USED);
1297 if (frag == last_frag)
1301 /* Make descriptor updates visible to hardware */
1304 __skb_pull(skb, NET_IP_ALIGN);
1305 skb->protocol = eth_type_trans(skb, bp->dev);
1307 bp->dev->stats.rx_packets++;
1308 bp->dev->stats.rx_bytes += skb->len;
1309 netdev_vdbg(bp->dev, "received skb of length %u, csum: %08x\n",
1310 skb->len, skb->csum);
1311 napi_gro_receive(napi, skb);
1316 static inline void macb_init_rx_ring(struct macb_queue *queue)
1318 struct macb *bp = queue->bp;
1320 struct macb_dma_desc *desc = NULL;
1323 addr = queue->rx_buffers_dma;
1324 for (i = 0; i < bp->rx_ring_size; i++) {
1325 desc = macb_rx_desc(queue, i);
1326 macb_set_addr(bp, desc, addr);
1328 addr += bp->rx_buffer_size;
1330 desc->addr |= MACB_BIT(RX_WRAP);
1334 static int macb_rx(struct macb_queue *queue, struct napi_struct *napi,
1337 struct macb *bp = queue->bp;
1338 bool reset_rx_queue = false;
1341 int first_frag = -1;
1343 for (tail = queue->rx_tail; budget > 0; tail++) {
1344 struct macb_dma_desc *desc = macb_rx_desc(queue, tail);
1347 /* Make hw descriptor updates visible to CPU */
1350 if (!(desc->addr & MACB_BIT(RX_USED)))
1353 /* Ensure ctrl is at least as up-to-date as addr */
1358 if (ctrl & MACB_BIT(RX_SOF)) {
1359 if (first_frag != -1)
1360 discard_partial_frame(queue, first_frag, tail);
1364 if (ctrl & MACB_BIT(RX_EOF)) {
1367 if (unlikely(first_frag == -1)) {
1368 reset_rx_queue = true;
1372 dropped = macb_rx_frame(queue, napi, first_frag, tail);
1374 if (unlikely(dropped < 0)) {
1375 reset_rx_queue = true;
1385 if (unlikely(reset_rx_queue)) {
1386 unsigned long flags;
1389 netdev_err(bp->dev, "RX queue corruption: reset it\n");
1391 spin_lock_irqsave(&bp->lock, flags);
1393 ctrl = macb_readl(bp, NCR);
1394 macb_writel(bp, NCR, ctrl & ~MACB_BIT(RE));
1396 macb_init_rx_ring(queue);
1397 queue_writel(queue, RBQP, queue->rx_ring_dma);
1399 macb_writel(bp, NCR, ctrl | MACB_BIT(RE));
1401 spin_unlock_irqrestore(&bp->lock, flags);
1405 if (first_frag != -1)
1406 queue->rx_tail = first_frag;
1408 queue->rx_tail = tail;
1413 static int macb_poll(struct napi_struct *napi, int budget)
1415 struct macb_queue *queue = container_of(napi, struct macb_queue, napi);
1416 struct macb *bp = queue->bp;
1420 status = macb_readl(bp, RSR);
1421 macb_writel(bp, RSR, status);
1423 netdev_vdbg(bp->dev, "poll: status = %08lx, budget = %d\n",
1424 (unsigned long)status, budget);
1426 work_done = bp->macbgem_ops.mog_rx(queue, napi, budget);
1427 if (work_done < budget) {
1428 napi_complete_done(napi, work_done);
1430 /* Packets received while interrupts were disabled */
1431 status = macb_readl(bp, RSR);
1433 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1434 queue_writel(queue, ISR, MACB_BIT(RCOMP));
1435 napi_reschedule(napi);
1437 queue_writel(queue, IER, bp->rx_intr_mask);
1441 /* TODO: Handle errors */
1446 static void macb_hresp_error_task(unsigned long data)
1448 struct macb *bp = (struct macb *)data;
1449 struct net_device *dev = bp->dev;
1450 struct macb_queue *queue = bp->queues;
1454 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
1455 queue_writel(queue, IDR, bp->rx_intr_mask |
1459 ctrl = macb_readl(bp, NCR);
1460 ctrl &= ~(MACB_BIT(RE) | MACB_BIT(TE));
1461 macb_writel(bp, NCR, ctrl);
1463 netif_tx_stop_all_queues(dev);
1464 netif_carrier_off(dev);
1466 bp->macbgem_ops.mog_init_rings(bp);
1468 /* Initialize TX and RX buffers */
1469 macb_init_buffers(bp);
1471 /* Enable interrupts */
1472 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue)
1473 queue_writel(queue, IER,
1478 ctrl |= MACB_BIT(RE) | MACB_BIT(TE);
1479 macb_writel(bp, NCR, ctrl);
1481 netif_carrier_on(dev);
1482 netif_tx_start_all_queues(dev);
1485 static void macb_tx_restart(struct macb_queue *queue)
1487 unsigned int head = queue->tx_head;
1488 unsigned int tail = queue->tx_tail;
1489 struct macb *bp = queue->bp;
1491 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1492 queue_writel(queue, ISR, MACB_BIT(TXUBR));
1497 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(TSTART));
1500 static irqreturn_t macb_interrupt(int irq, void *dev_id)
1502 struct macb_queue *queue = dev_id;
1503 struct macb *bp = queue->bp;
1504 struct net_device *dev = bp->dev;
1507 status = queue_readl(queue, ISR);
1509 if (unlikely(!status))
1512 spin_lock(&bp->lock);
1515 /* close possible race with dev_close */
1516 if (unlikely(!netif_running(dev))) {
1517 queue_writel(queue, IDR, -1);
1518 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1519 queue_writel(queue, ISR, -1);
1523 netdev_vdbg(bp->dev, "queue = %u, isr = 0x%08lx\n",
1524 (unsigned int)(queue - bp->queues),
1525 (unsigned long)status);
1527 if (status & bp->rx_intr_mask) {
1528 /* There's no point taking any more interrupts
1529 * until we have processed the buffers. The
1530 * scheduling call may fail if the poll routine
1531 * is already scheduled, so disable interrupts
1534 queue_writel(queue, IDR, bp->rx_intr_mask);
1535 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1536 queue_writel(queue, ISR, MACB_BIT(RCOMP));
1538 if (napi_schedule_prep(&queue->napi)) {
1539 netdev_vdbg(bp->dev, "scheduling RX softirq\n");
1540 __napi_schedule(&queue->napi);
1544 if (unlikely(status & (MACB_TX_ERR_FLAGS))) {
1545 queue_writel(queue, IDR, MACB_TX_INT_FLAGS);
1546 schedule_work(&queue->tx_error_task);
1548 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1549 queue_writel(queue, ISR, MACB_TX_ERR_FLAGS);
1554 if (status & MACB_BIT(TCOMP))
1555 macb_tx_interrupt(queue);
1557 if (status & MACB_BIT(TXUBR))
1558 macb_tx_restart(queue);
1560 /* Link change detection isn't possible with RMII, so we'll
1561 * add that if/when we get our hands on a full-blown MII PHY.
1564 /* There is a hardware issue under heavy load where DMA can
1565 * stop, this causes endless "used buffer descriptor read"
1566 * interrupts but it can be cleared by re-enabling RX. See
1567 * the at91rm9200 manual, section 41.3.1 or the Zynq manual
1568 * section 16.7.4 for details. RXUBR is only enabled for
1569 * these two versions.
1571 if (status & MACB_BIT(RXUBR)) {
1572 ctrl = macb_readl(bp, NCR);
1573 macb_writel(bp, NCR, ctrl & ~MACB_BIT(RE));
1575 macb_writel(bp, NCR, ctrl | MACB_BIT(RE));
1577 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1578 queue_writel(queue, ISR, MACB_BIT(RXUBR));
1581 if (status & MACB_BIT(ISR_ROVR)) {
1582 /* We missed at least one packet */
1583 if (macb_is_gem(bp))
1584 bp->hw_stats.gem.rx_overruns++;
1586 bp->hw_stats.macb.rx_overruns++;
1588 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1589 queue_writel(queue, ISR, MACB_BIT(ISR_ROVR));
1592 if (status & MACB_BIT(HRESP)) {
1593 tasklet_schedule(&bp->hresp_err_tasklet);
1594 netdev_err(dev, "DMA bus error: HRESP not OK\n");
1596 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1597 queue_writel(queue, ISR, MACB_BIT(HRESP));
1599 status = queue_readl(queue, ISR);
1602 spin_unlock(&bp->lock);
1607 #ifdef CONFIG_NET_POLL_CONTROLLER
1608 /* Polling receive - used by netconsole and other diagnostic tools
1609 * to allow network i/o with interrupts disabled.
1611 static void macb_poll_controller(struct net_device *dev)
1613 struct macb *bp = netdev_priv(dev);
1614 struct macb_queue *queue;
1615 unsigned long flags;
1618 local_irq_save(flags);
1619 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue)
1620 macb_interrupt(dev->irq, queue);
1621 local_irq_restore(flags);
1625 static unsigned int macb_tx_map(struct macb *bp,
1626 struct macb_queue *queue,
1627 struct sk_buff *skb,
1628 unsigned int hdrlen)
1631 unsigned int len, entry, i, tx_head = queue->tx_head;
1632 struct macb_tx_skb *tx_skb = NULL;
1633 struct macb_dma_desc *desc;
1634 unsigned int offset, size, count = 0;
1635 unsigned int f, nr_frags = skb_shinfo(skb)->nr_frags;
1636 unsigned int eof = 1, mss_mfs = 0;
1637 u32 ctrl, lso_ctrl = 0, seq_ctrl = 0;
1640 if (skb_shinfo(skb)->gso_size != 0) {
1641 if (ip_hdr(skb)->protocol == IPPROTO_UDP)
1643 lso_ctrl = MACB_LSO_UFO_ENABLE;
1646 lso_ctrl = MACB_LSO_TSO_ENABLE;
1649 /* First, map non-paged data */
1650 len = skb_headlen(skb);
1652 /* first buffer length */
1657 entry = macb_tx_ring_wrap(bp, tx_head);
1658 tx_skb = &queue->tx_skb[entry];
1660 mapping = dma_map_single(&bp->pdev->dev,
1662 size, DMA_TO_DEVICE);
1663 if (dma_mapping_error(&bp->pdev->dev, mapping))
1666 /* Save info to properly release resources */
1668 tx_skb->mapping = mapping;
1669 tx_skb->size = size;
1670 tx_skb->mapped_as_page = false;
1677 size = min(len, bp->max_tx_length);
1680 /* Then, map paged data from fragments */
1681 for (f = 0; f < nr_frags; f++) {
1682 const skb_frag_t *frag = &skb_shinfo(skb)->frags[f];
1684 len = skb_frag_size(frag);
1687 size = min(len, bp->max_tx_length);
1688 entry = macb_tx_ring_wrap(bp, tx_head);
1689 tx_skb = &queue->tx_skb[entry];
1691 mapping = skb_frag_dma_map(&bp->pdev->dev, frag,
1692 offset, size, DMA_TO_DEVICE);
1693 if (dma_mapping_error(&bp->pdev->dev, mapping))
1696 /* Save info to properly release resources */
1698 tx_skb->mapping = mapping;
1699 tx_skb->size = size;
1700 tx_skb->mapped_as_page = true;
1709 /* Should never happen */
1710 if (unlikely(!tx_skb)) {
1711 netdev_err(bp->dev, "BUG! empty skb!\n");
1715 /* This is the last buffer of the frame: save socket buffer */
1718 /* Update TX ring: update buffer descriptors in reverse order
1719 * to avoid race condition
1722 /* Set 'TX_USED' bit in buffer descriptor at tx_head position
1723 * to set the end of TX queue
1726 entry = macb_tx_ring_wrap(bp, i);
1727 ctrl = MACB_BIT(TX_USED);
1728 desc = macb_tx_desc(queue, entry);
1732 if (lso_ctrl == MACB_LSO_UFO_ENABLE)
1733 /* include header and FCS in value given to h/w */
1734 mss_mfs = skb_shinfo(skb)->gso_size +
1735 skb_transport_offset(skb) +
1738 mss_mfs = skb_shinfo(skb)->gso_size;
1739 /* TCP Sequence Number Source Select
1740 * can be set only for TSO
1748 entry = macb_tx_ring_wrap(bp, i);
1749 tx_skb = &queue->tx_skb[entry];
1750 desc = macb_tx_desc(queue, entry);
1752 ctrl = (u32)tx_skb->size;
1754 ctrl |= MACB_BIT(TX_LAST);
1757 if (unlikely(entry == (bp->tx_ring_size - 1)))
1758 ctrl |= MACB_BIT(TX_WRAP);
1760 /* First descriptor is header descriptor */
1761 if (i == queue->tx_head) {
1762 ctrl |= MACB_BF(TX_LSO, lso_ctrl);
1763 ctrl |= MACB_BF(TX_TCP_SEQ_SRC, seq_ctrl);
1764 if ((bp->dev->features & NETIF_F_HW_CSUM) &&
1765 skb->ip_summed != CHECKSUM_PARTIAL && !lso_ctrl)
1766 ctrl |= MACB_BIT(TX_NOCRC);
1768 /* Only set MSS/MFS on payload descriptors
1769 * (second or later descriptor)
1771 ctrl |= MACB_BF(MSS_MFS, mss_mfs);
1773 /* Set TX buffer descriptor */
1774 macb_set_addr(bp, desc, tx_skb->mapping);
1775 /* desc->addr must be visible to hardware before clearing
1776 * 'TX_USED' bit in desc->ctrl.
1780 } while (i != queue->tx_head);
1782 queue->tx_head = tx_head;
1787 netdev_err(bp->dev, "TX DMA map failed\n");
1789 for (i = queue->tx_head; i != tx_head; i++) {
1790 tx_skb = macb_tx_skb(queue, i);
1792 macb_tx_unmap(bp, tx_skb);
1798 static netdev_features_t macb_features_check(struct sk_buff *skb,
1799 struct net_device *dev,
1800 netdev_features_t features)
1802 unsigned int nr_frags, f;
1803 unsigned int hdrlen;
1805 /* Validate LSO compatibility */
1807 /* there is only one buffer or protocol is not UDP */
1808 if (!skb_is_nonlinear(skb) || (ip_hdr(skb)->protocol != IPPROTO_UDP))
1811 /* length of header */
1812 hdrlen = skb_transport_offset(skb);
1815 * When software supplies two or more payload buffers all payload buffers
1816 * apart from the last must be a multiple of 8 bytes in size.
1818 if (!IS_ALIGNED(skb_headlen(skb) - hdrlen, MACB_TX_LEN_ALIGN))
1819 return features & ~MACB_NETIF_LSO;
1821 nr_frags = skb_shinfo(skb)->nr_frags;
1822 /* No need to check last fragment */
1824 for (f = 0; f < nr_frags; f++) {
1825 const skb_frag_t *frag = &skb_shinfo(skb)->frags[f];
1827 if (!IS_ALIGNED(skb_frag_size(frag), MACB_TX_LEN_ALIGN))
1828 return features & ~MACB_NETIF_LSO;
1833 static inline int macb_clear_csum(struct sk_buff *skb)
1835 /* no change for packets without checksum offloading */
1836 if (skb->ip_summed != CHECKSUM_PARTIAL)
1839 /* make sure we can modify the header */
1840 if (unlikely(skb_cow_head(skb, 0)))
1843 /* initialize checksum field
1844 * This is required - at least for Zynq, which otherwise calculates
1845 * wrong UDP header checksums for UDP packets with UDP data len <=2
1847 *(__sum16 *)(skb_checksum_start(skb) + skb->csum_offset) = 0;
1851 static int macb_pad_and_fcs(struct sk_buff **skb, struct net_device *ndev)
1853 bool cloned = skb_cloned(*skb) || skb_header_cloned(*skb);
1854 int padlen = ETH_ZLEN - (*skb)->len;
1855 int headroom = skb_headroom(*skb);
1856 int tailroom = skb_tailroom(*skb);
1857 struct sk_buff *nskb;
1860 if (!(ndev->features & NETIF_F_HW_CSUM) ||
1861 !((*skb)->ip_summed != CHECKSUM_PARTIAL) ||
1862 skb_shinfo(*skb)->gso_size) /* Not available for GSO */
1866 /* FCS could be appeded to tailroom. */
1867 if (tailroom >= ETH_FCS_LEN)
1869 /* FCS could be appeded by moving data to headroom. */
1870 else if (!cloned && headroom + tailroom >= ETH_FCS_LEN)
1872 /* No room for FCS, need to reallocate skb. */
1874 padlen = ETH_FCS_LEN;
1876 /* Add room for FCS. */
1877 padlen += ETH_FCS_LEN;
1880 if (!cloned && headroom + tailroom >= padlen) {
1881 (*skb)->data = memmove((*skb)->head, (*skb)->data, (*skb)->len);
1882 skb_set_tail_pointer(*skb, (*skb)->len);
1884 nskb = skb_copy_expand(*skb, 0, padlen, GFP_ATOMIC);
1888 dev_consume_skb_any(*skb);
1892 if (padlen > ETH_FCS_LEN)
1893 skb_put_zero(*skb, padlen - ETH_FCS_LEN);
1896 /* set FCS to packet */
1897 fcs = crc32_le(~0, (*skb)->data, (*skb)->len);
1900 skb_put_u8(*skb, fcs & 0xff);
1901 skb_put_u8(*skb, (fcs >> 8) & 0xff);
1902 skb_put_u8(*skb, (fcs >> 16) & 0xff);
1903 skb_put_u8(*skb, (fcs >> 24) & 0xff);
1908 static netdev_tx_t macb_start_xmit(struct sk_buff *skb, struct net_device *dev)
1910 u16 queue_index = skb_get_queue_mapping(skb);
1911 struct macb *bp = netdev_priv(dev);
1912 struct macb_queue *queue = &bp->queues[queue_index];
1913 unsigned long flags;
1914 unsigned int desc_cnt, nr_frags, frag_size, f;
1915 unsigned int hdrlen;
1916 bool is_lso, is_udp = 0;
1917 netdev_tx_t ret = NETDEV_TX_OK;
1919 if (macb_clear_csum(skb)) {
1920 dev_kfree_skb_any(skb);
1924 if (macb_pad_and_fcs(&skb, dev)) {
1925 dev_kfree_skb_any(skb);
1929 is_lso = (skb_shinfo(skb)->gso_size != 0);
1932 is_udp = !!(ip_hdr(skb)->protocol == IPPROTO_UDP);
1934 /* length of headers */
1936 /* only queue eth + ip headers separately for UDP */
1937 hdrlen = skb_transport_offset(skb);
1939 hdrlen = skb_transport_offset(skb) + tcp_hdrlen(skb);
1940 if (skb_headlen(skb) < hdrlen) {
1941 netdev_err(bp->dev, "Error - LSO headers fragmented!!!\n");
1942 /* if this is required, would need to copy to single buffer */
1943 return NETDEV_TX_BUSY;
1946 hdrlen = min(skb_headlen(skb), bp->max_tx_length);
1948 #if defined(DEBUG) && defined(VERBOSE_DEBUG)
1949 netdev_vdbg(bp->dev,
1950 "start_xmit: queue %hu len %u head %p data %p tail %p end %p\n",
1951 queue_index, skb->len, skb->head, skb->data,
1952 skb_tail_pointer(skb), skb_end_pointer(skb));
1953 print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_OFFSET, 16, 1,
1954 skb->data, 16, true);
1957 /* Count how many TX buffer descriptors are needed to send this
1958 * socket buffer: skb fragments of jumbo frames may need to be
1959 * split into many buffer descriptors.
1961 if (is_lso && (skb_headlen(skb) > hdrlen))
1962 /* extra header descriptor if also payload in first buffer */
1963 desc_cnt = DIV_ROUND_UP((skb_headlen(skb) - hdrlen), bp->max_tx_length) + 1;
1965 desc_cnt = DIV_ROUND_UP(skb_headlen(skb), bp->max_tx_length);
1966 nr_frags = skb_shinfo(skb)->nr_frags;
1967 for (f = 0; f < nr_frags; f++) {
1968 frag_size = skb_frag_size(&skb_shinfo(skb)->frags[f]);
1969 desc_cnt += DIV_ROUND_UP(frag_size, bp->max_tx_length);
1972 spin_lock_irqsave(&bp->lock, flags);
1974 /* This is a hard error, log it. */
1975 if (CIRC_SPACE(queue->tx_head, queue->tx_tail,
1976 bp->tx_ring_size) < desc_cnt) {
1977 netif_stop_subqueue(dev, queue_index);
1978 spin_unlock_irqrestore(&bp->lock, flags);
1979 netdev_dbg(bp->dev, "tx_head = %u, tx_tail = %u\n",
1980 queue->tx_head, queue->tx_tail);
1981 return NETDEV_TX_BUSY;
1984 /* Map socket buffer for DMA transfer */
1985 if (!macb_tx_map(bp, queue, skb, hdrlen)) {
1986 dev_kfree_skb_any(skb);
1990 /* Make newly initialized descriptor visible to hardware */
1992 skb_tx_timestamp(skb);
1994 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(TSTART));
1996 if (CIRC_SPACE(queue->tx_head, queue->tx_tail, bp->tx_ring_size) < 1)
1997 netif_stop_subqueue(dev, queue_index);
2000 spin_unlock_irqrestore(&bp->lock, flags);
2005 static void macb_init_rx_buffer_size(struct macb *bp, size_t size)
2007 if (!macb_is_gem(bp)) {
2008 bp->rx_buffer_size = MACB_RX_BUFFER_SIZE;
2010 bp->rx_buffer_size = size;
2012 if (bp->rx_buffer_size % RX_BUFFER_MULTIPLE) {
2014 "RX buffer must be multiple of %d bytes, expanding\n",
2015 RX_BUFFER_MULTIPLE);
2016 bp->rx_buffer_size =
2017 roundup(bp->rx_buffer_size, RX_BUFFER_MULTIPLE);
2021 netdev_dbg(bp->dev, "mtu [%u] rx_buffer_size [%zu]\n",
2022 bp->dev->mtu, bp->rx_buffer_size);
2025 static void gem_free_rx_buffers(struct macb *bp)
2027 struct sk_buff *skb;
2028 struct macb_dma_desc *desc;
2029 struct macb_queue *queue;
2034 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
2035 if (!queue->rx_skbuff)
2038 for (i = 0; i < bp->rx_ring_size; i++) {
2039 skb = queue->rx_skbuff[i];
2044 desc = macb_rx_desc(queue, i);
2045 addr = macb_get_addr(bp, desc);
2047 dma_unmap_single(&bp->pdev->dev, addr, bp->rx_buffer_size,
2049 dev_kfree_skb_any(skb);
2053 kfree(queue->rx_skbuff);
2054 queue->rx_skbuff = NULL;
2058 static void macb_free_rx_buffers(struct macb *bp)
2060 struct macb_queue *queue = &bp->queues[0];
2062 if (queue->rx_buffers) {
2063 dma_free_coherent(&bp->pdev->dev,
2064 bp->rx_ring_size * bp->rx_buffer_size,
2065 queue->rx_buffers, queue->rx_buffers_dma);
2066 queue->rx_buffers = NULL;
2070 static void macb_free_consistent(struct macb *bp)
2072 struct macb_queue *queue;
2076 bp->macbgem_ops.mog_free_rx_buffers(bp);
2078 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
2079 kfree(queue->tx_skb);
2080 queue->tx_skb = NULL;
2081 if (queue->tx_ring) {
2082 size = TX_RING_BYTES(bp) + bp->tx_bd_rd_prefetch;
2083 dma_free_coherent(&bp->pdev->dev, size,
2084 queue->tx_ring, queue->tx_ring_dma);
2085 queue->tx_ring = NULL;
2087 if (queue->rx_ring) {
2088 size = RX_RING_BYTES(bp) + bp->rx_bd_rd_prefetch;
2089 dma_free_coherent(&bp->pdev->dev, size,
2090 queue->rx_ring, queue->rx_ring_dma);
2091 queue->rx_ring = NULL;
2096 static int gem_alloc_rx_buffers(struct macb *bp)
2098 struct macb_queue *queue;
2102 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
2103 size = bp->rx_ring_size * sizeof(struct sk_buff *);
2104 queue->rx_skbuff = kzalloc(size, GFP_KERNEL);
2105 if (!queue->rx_skbuff)
2109 "Allocated %d RX struct sk_buff entries at %p\n",
2110 bp->rx_ring_size, queue->rx_skbuff);
2115 static int macb_alloc_rx_buffers(struct macb *bp)
2117 struct macb_queue *queue = &bp->queues[0];
2120 size = bp->rx_ring_size * bp->rx_buffer_size;
2121 queue->rx_buffers = dma_alloc_coherent(&bp->pdev->dev, size,
2122 &queue->rx_buffers_dma, GFP_KERNEL);
2123 if (!queue->rx_buffers)
2127 "Allocated RX buffers of %d bytes at %08lx (mapped %p)\n",
2128 size, (unsigned long)queue->rx_buffers_dma, queue->rx_buffers);
2132 static int macb_alloc_consistent(struct macb *bp)
2134 struct macb_queue *queue;
2138 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
2139 size = TX_RING_BYTES(bp) + bp->tx_bd_rd_prefetch;
2140 queue->tx_ring = dma_alloc_coherent(&bp->pdev->dev, size,
2141 &queue->tx_ring_dma,
2143 if (!queue->tx_ring)
2146 "Allocated TX ring for queue %u of %d bytes at %08lx (mapped %p)\n",
2147 q, size, (unsigned long)queue->tx_ring_dma,
2150 size = bp->tx_ring_size * sizeof(struct macb_tx_skb);
2151 queue->tx_skb = kmalloc(size, GFP_KERNEL);
2155 size = RX_RING_BYTES(bp) + bp->rx_bd_rd_prefetch;
2156 queue->rx_ring = dma_alloc_coherent(&bp->pdev->dev, size,
2157 &queue->rx_ring_dma, GFP_KERNEL);
2158 if (!queue->rx_ring)
2161 "Allocated RX ring of %d bytes at %08lx (mapped %p)\n",
2162 size, (unsigned long)queue->rx_ring_dma, queue->rx_ring);
2164 if (bp->macbgem_ops.mog_alloc_rx_buffers(bp))
2170 macb_free_consistent(bp);
2174 static void gem_init_rings(struct macb *bp)
2176 struct macb_queue *queue;
2177 struct macb_dma_desc *desc = NULL;
2181 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
2182 for (i = 0; i < bp->tx_ring_size; i++) {
2183 desc = macb_tx_desc(queue, i);
2184 macb_set_addr(bp, desc, 0);
2185 desc->ctrl = MACB_BIT(TX_USED);
2187 desc->ctrl |= MACB_BIT(TX_WRAP);
2192 queue->rx_prepared_head = 0;
2194 gem_rx_refill(queue);
2199 static void macb_init_rings(struct macb *bp)
2202 struct macb_dma_desc *desc = NULL;
2204 macb_init_rx_ring(&bp->queues[0]);
2206 for (i = 0; i < bp->tx_ring_size; i++) {
2207 desc = macb_tx_desc(&bp->queues[0], i);
2208 macb_set_addr(bp, desc, 0);
2209 desc->ctrl = MACB_BIT(TX_USED);
2211 bp->queues[0].tx_head = 0;
2212 bp->queues[0].tx_tail = 0;
2213 desc->ctrl |= MACB_BIT(TX_WRAP);
2216 static void macb_reset_hw(struct macb *bp)
2218 struct macb_queue *queue;
2220 u32 ctrl = macb_readl(bp, NCR);
2222 /* Disable RX and TX (XXX: Should we halt the transmission
2225 ctrl &= ~(MACB_BIT(RE) | MACB_BIT(TE));
2227 /* Clear the stats registers (XXX: Update stats first?) */
2228 ctrl |= MACB_BIT(CLRSTAT);
2230 macb_writel(bp, NCR, ctrl);
2232 /* Clear all status flags */
2233 macb_writel(bp, TSR, -1);
2234 macb_writel(bp, RSR, -1);
2236 /* Disable all interrupts */
2237 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
2238 queue_writel(queue, IDR, -1);
2239 queue_readl(queue, ISR);
2240 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
2241 queue_writel(queue, ISR, -1);
2245 static u32 gem_mdc_clk_div(struct macb *bp)
2248 unsigned long pclk_hz = clk_get_rate(bp->pclk);
2250 if (pclk_hz <= 20000000)
2251 config = GEM_BF(CLK, GEM_CLK_DIV8);
2252 else if (pclk_hz <= 40000000)
2253 config = GEM_BF(CLK, GEM_CLK_DIV16);
2254 else if (pclk_hz <= 80000000)
2255 config = GEM_BF(CLK, GEM_CLK_DIV32);
2256 else if (pclk_hz <= 120000000)
2257 config = GEM_BF(CLK, GEM_CLK_DIV48);
2258 else if (pclk_hz <= 160000000)
2259 config = GEM_BF(CLK, GEM_CLK_DIV64);
2261 config = GEM_BF(CLK, GEM_CLK_DIV96);
2266 static u32 macb_mdc_clk_div(struct macb *bp)
2269 unsigned long pclk_hz;
2271 if (macb_is_gem(bp))
2272 return gem_mdc_clk_div(bp);
2274 pclk_hz = clk_get_rate(bp->pclk);
2275 if (pclk_hz <= 20000000)
2276 config = MACB_BF(CLK, MACB_CLK_DIV8);
2277 else if (pclk_hz <= 40000000)
2278 config = MACB_BF(CLK, MACB_CLK_DIV16);
2279 else if (pclk_hz <= 80000000)
2280 config = MACB_BF(CLK, MACB_CLK_DIV32);
2282 config = MACB_BF(CLK, MACB_CLK_DIV64);
2287 /* Get the DMA bus width field of the network configuration register that we
2288 * should program. We find the width from decoding the design configuration
2289 * register to find the maximum supported data bus width.
2291 static u32 macb_dbw(struct macb *bp)
2293 if (!macb_is_gem(bp))
2296 switch (GEM_BFEXT(DBWDEF, gem_readl(bp, DCFG1))) {
2298 return GEM_BF(DBW, GEM_DBW128);
2300 return GEM_BF(DBW, GEM_DBW64);
2303 return GEM_BF(DBW, GEM_DBW32);
2307 /* Configure the receive DMA engine
2308 * - use the correct receive buffer size
2309 * - set best burst length for DMA operations
2310 * (if not supported by FIFO, it will fallback to default)
2311 * - set both rx/tx packet buffers to full memory size
2312 * These are configurable parameters for GEM.
2314 static void macb_configure_dma(struct macb *bp)
2316 struct macb_queue *queue;
2321 buffer_size = bp->rx_buffer_size / RX_BUFFER_MULTIPLE;
2322 if (macb_is_gem(bp)) {
2323 dmacfg = gem_readl(bp, DMACFG) & ~GEM_BF(RXBS, -1L);
2324 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
2326 queue_writel(queue, RBQS, buffer_size);
2328 dmacfg |= GEM_BF(RXBS, buffer_size);
2330 if (bp->dma_burst_length)
2331 dmacfg = GEM_BFINS(FBLDO, bp->dma_burst_length, dmacfg);
2332 dmacfg |= GEM_BIT(TXPBMS) | GEM_BF(RXBMS, -1L);
2333 dmacfg &= ~GEM_BIT(ENDIA_PKT);
2336 dmacfg &= ~GEM_BIT(ENDIA_DESC);
2338 dmacfg |= GEM_BIT(ENDIA_DESC); /* CPU in big endian */
2340 if (bp->dev->features & NETIF_F_HW_CSUM)
2341 dmacfg |= GEM_BIT(TXCOEN);
2343 dmacfg &= ~GEM_BIT(TXCOEN);
2345 dmacfg &= ~GEM_BIT(ADDR64);
2346 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
2347 if (bp->hw_dma_cap & HW_DMA_CAP_64B)
2348 dmacfg |= GEM_BIT(ADDR64);
2350 #ifdef CONFIG_MACB_USE_HWSTAMP
2351 if (bp->hw_dma_cap & HW_DMA_CAP_PTP)
2352 dmacfg |= GEM_BIT(RXEXT) | GEM_BIT(TXEXT);
2354 netdev_dbg(bp->dev, "Cadence configure DMA with 0x%08x\n",
2356 gem_writel(bp, DMACFG, dmacfg);
2360 static void macb_init_hw(struct macb *bp)
2365 macb_set_hwaddr(bp);
2367 config = macb_mdc_clk_div(bp);
2368 config |= MACB_BF(RBOF, NET_IP_ALIGN); /* Make eth data aligned */
2369 config |= MACB_BIT(DRFCS); /* Discard Rx FCS */
2370 if (bp->caps & MACB_CAPS_JUMBO)
2371 config |= MACB_BIT(JFRAME); /* Enable jumbo frames */
2373 config |= MACB_BIT(BIG); /* Receive oversized frames */
2374 if (bp->dev->flags & IFF_PROMISC)
2375 config |= MACB_BIT(CAF); /* Copy All Frames */
2376 else if (macb_is_gem(bp) && bp->dev->features & NETIF_F_RXCSUM)
2377 config |= GEM_BIT(RXCOEN);
2378 if (!(bp->dev->flags & IFF_BROADCAST))
2379 config |= MACB_BIT(NBC); /* No BroadCast */
2380 config |= macb_dbw(bp);
2381 macb_writel(bp, NCFGR, config);
2382 if ((bp->caps & MACB_CAPS_JUMBO) && bp->jumbo_max_len)
2383 gem_writel(bp, JML, bp->jumbo_max_len);
2384 bp->rx_frm_len_mask = MACB_RX_FRMLEN_MASK;
2385 if (bp->caps & MACB_CAPS_JUMBO)
2386 bp->rx_frm_len_mask = MACB_RX_JFRMLEN_MASK;
2388 macb_configure_dma(bp);
2391 /* The hash address register is 64 bits long and takes up two
2392 * locations in the memory map. The least significant bits are stored
2393 * in EMAC_HSL and the most significant bits in EMAC_HSH.
2395 * The unicast hash enable and the multicast hash enable bits in the
2396 * network configuration register enable the reception of hash matched
2397 * frames. The destination address is reduced to a 6 bit index into
2398 * the 64 bit hash register using the following hash function. The
2399 * hash function is an exclusive or of every sixth bit of the
2400 * destination address.
2402 * hi[5] = da[5] ^ da[11] ^ da[17] ^ da[23] ^ da[29] ^ da[35] ^ da[41] ^ da[47]
2403 * hi[4] = da[4] ^ da[10] ^ da[16] ^ da[22] ^ da[28] ^ da[34] ^ da[40] ^ da[46]
2404 * hi[3] = da[3] ^ da[09] ^ da[15] ^ da[21] ^ da[27] ^ da[33] ^ da[39] ^ da[45]
2405 * hi[2] = da[2] ^ da[08] ^ da[14] ^ da[20] ^ da[26] ^ da[32] ^ da[38] ^ da[44]
2406 * hi[1] = da[1] ^ da[07] ^ da[13] ^ da[19] ^ da[25] ^ da[31] ^ da[37] ^ da[43]
2407 * hi[0] = da[0] ^ da[06] ^ da[12] ^ da[18] ^ da[24] ^ da[30] ^ da[36] ^ da[42]
2409 * da[0] represents the least significant bit of the first byte
2410 * received, that is, the multicast/unicast indicator, and da[47]
2411 * represents the most significant bit of the last byte received. If
2412 * the hash index, hi[n], points to a bit that is set in the hash
2413 * register then the frame will be matched according to whether the
2414 * frame is multicast or unicast. A multicast match will be signalled
2415 * if the multicast hash enable bit is set, da[0] is 1 and the hash
2416 * index points to a bit set in the hash register. A unicast match
2417 * will be signalled if the unicast hash enable bit is set, da[0] is 0
2418 * and the hash index points to a bit set in the hash register. To
2419 * receive all multicast frames, the hash register should be set with
2420 * all ones and the multicast hash enable bit should be set in the
2421 * network configuration register.
2424 static inline int hash_bit_value(int bitnr, __u8 *addr)
2426 if (addr[bitnr / 8] & (1 << (bitnr % 8)))
2431 /* Return the hash index value for the specified address. */
2432 static int hash_get_index(__u8 *addr)
2437 for (j = 0; j < 6; j++) {
2438 for (i = 0, bitval = 0; i < 8; i++)
2439 bitval ^= hash_bit_value(i * 6 + j, addr);
2441 hash_index |= (bitval << j);
2447 /* Add multicast addresses to the internal multicast-hash table. */
2448 static void macb_sethashtable(struct net_device *dev)
2450 struct netdev_hw_addr *ha;
2451 unsigned long mc_filter[2];
2453 struct macb *bp = netdev_priv(dev);
2458 netdev_for_each_mc_addr(ha, dev) {
2459 bitnr = hash_get_index(ha->addr);
2460 mc_filter[bitnr >> 5] |= 1 << (bitnr & 31);
2463 macb_or_gem_writel(bp, HRB, mc_filter[0]);
2464 macb_or_gem_writel(bp, HRT, mc_filter[1]);
2467 /* Enable/Disable promiscuous and multicast modes. */
2468 static void macb_set_rx_mode(struct net_device *dev)
2471 struct macb *bp = netdev_priv(dev);
2473 cfg = macb_readl(bp, NCFGR);
2475 if (dev->flags & IFF_PROMISC) {
2476 /* Enable promiscuous mode */
2477 cfg |= MACB_BIT(CAF);
2479 /* Disable RX checksum offload */
2480 if (macb_is_gem(bp))
2481 cfg &= ~GEM_BIT(RXCOEN);
2483 /* Disable promiscuous mode */
2484 cfg &= ~MACB_BIT(CAF);
2486 /* Enable RX checksum offload only if requested */
2487 if (macb_is_gem(bp) && dev->features & NETIF_F_RXCSUM)
2488 cfg |= GEM_BIT(RXCOEN);
2491 if (dev->flags & IFF_ALLMULTI) {
2492 /* Enable all multicast mode */
2493 macb_or_gem_writel(bp, HRB, -1);
2494 macb_or_gem_writel(bp, HRT, -1);
2495 cfg |= MACB_BIT(NCFGR_MTI);
2496 } else if (!netdev_mc_empty(dev)) {
2497 /* Enable specific multicasts */
2498 macb_sethashtable(dev);
2499 cfg |= MACB_BIT(NCFGR_MTI);
2500 } else if (dev->flags & (~IFF_ALLMULTI)) {
2501 /* Disable all multicast mode */
2502 macb_or_gem_writel(bp, HRB, 0);
2503 macb_or_gem_writel(bp, HRT, 0);
2504 cfg &= ~MACB_BIT(NCFGR_MTI);
2507 macb_writel(bp, NCFGR, cfg);
2510 static int macb_open(struct net_device *dev)
2512 size_t bufsz = dev->mtu + ETH_HLEN + ETH_FCS_LEN + NET_IP_ALIGN;
2513 struct macb *bp = netdev_priv(dev);
2514 struct macb_queue *queue;
2518 netdev_dbg(bp->dev, "open\n");
2520 err = pm_runtime_get_sync(&bp->pdev->dev);
2524 /* RX buffers initialization */
2525 macb_init_rx_buffer_size(bp, bufsz);
2527 err = macb_alloc_consistent(bp);
2529 netdev_err(dev, "Unable to allocate DMA memory (error %d)\n",
2534 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue)
2535 napi_enable(&queue->napi);
2539 err = macb_phylink_connect(bp);
2543 netif_tx_start_all_queues(dev);
2546 bp->ptp_info->ptp_init(dev);
2550 pm_runtime_put_sync(&bp->pdev->dev);
2556 static int macb_close(struct net_device *dev)
2558 struct macb *bp = netdev_priv(dev);
2559 struct macb_queue *queue;
2560 unsigned long flags;
2563 netif_tx_stop_all_queues(dev);
2565 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue)
2566 napi_disable(&queue->napi);
2568 phylink_stop(bp->phylink);
2569 phylink_disconnect_phy(bp->phylink);
2571 spin_lock_irqsave(&bp->lock, flags);
2573 netif_carrier_off(dev);
2574 spin_unlock_irqrestore(&bp->lock, flags);
2576 macb_free_consistent(bp);
2579 bp->ptp_info->ptp_remove(dev);
2581 pm_runtime_put(&bp->pdev->dev);
2586 static int macb_change_mtu(struct net_device *dev, int new_mtu)
2588 if (netif_running(dev))
2596 static void gem_update_stats(struct macb *bp)
2598 struct macb_queue *queue;
2599 unsigned int i, q, idx;
2600 unsigned long *stat;
2602 u32 *p = &bp->hw_stats.gem.tx_octets_31_0;
2604 for (i = 0; i < GEM_STATS_LEN; ++i, ++p) {
2605 u32 offset = gem_statistics[i].offset;
2606 u64 val = bp->macb_reg_readl(bp, offset);
2608 bp->ethtool_stats[i] += val;
2611 if (offset == GEM_OCTTXL || offset == GEM_OCTRXL) {
2612 /* Add GEM_OCTTXH, GEM_OCTRXH */
2613 val = bp->macb_reg_readl(bp, offset + 4);
2614 bp->ethtool_stats[i] += ((u64)val) << 32;
2619 idx = GEM_STATS_LEN;
2620 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue)
2621 for (i = 0, stat = &queue->stats.first; i < QUEUE_STATS_LEN; ++i, ++stat)
2622 bp->ethtool_stats[idx++] = *stat;
2625 static struct net_device_stats *gem_get_stats(struct macb *bp)
2627 struct gem_stats *hwstat = &bp->hw_stats.gem;
2628 struct net_device_stats *nstat = &bp->dev->stats;
2630 gem_update_stats(bp);
2632 nstat->rx_errors = (hwstat->rx_frame_check_sequence_errors +
2633 hwstat->rx_alignment_errors +
2634 hwstat->rx_resource_errors +
2635 hwstat->rx_overruns +
2636 hwstat->rx_oversize_frames +
2637 hwstat->rx_jabbers +
2638 hwstat->rx_undersized_frames +
2639 hwstat->rx_length_field_frame_errors);
2640 nstat->tx_errors = (hwstat->tx_late_collisions +
2641 hwstat->tx_excessive_collisions +
2642 hwstat->tx_underrun +
2643 hwstat->tx_carrier_sense_errors);
2644 nstat->multicast = hwstat->rx_multicast_frames;
2645 nstat->collisions = (hwstat->tx_single_collision_frames +
2646 hwstat->tx_multiple_collision_frames +
2647 hwstat->tx_excessive_collisions);
2648 nstat->rx_length_errors = (hwstat->rx_oversize_frames +
2649 hwstat->rx_jabbers +
2650 hwstat->rx_undersized_frames +
2651 hwstat->rx_length_field_frame_errors);
2652 nstat->rx_over_errors = hwstat->rx_resource_errors;
2653 nstat->rx_crc_errors = hwstat->rx_frame_check_sequence_errors;
2654 nstat->rx_frame_errors = hwstat->rx_alignment_errors;
2655 nstat->rx_fifo_errors = hwstat->rx_overruns;
2656 nstat->tx_aborted_errors = hwstat->tx_excessive_collisions;
2657 nstat->tx_carrier_errors = hwstat->tx_carrier_sense_errors;
2658 nstat->tx_fifo_errors = hwstat->tx_underrun;
2663 static void gem_get_ethtool_stats(struct net_device *dev,
2664 struct ethtool_stats *stats, u64 *data)
2668 bp = netdev_priv(dev);
2669 gem_update_stats(bp);
2670 memcpy(data, &bp->ethtool_stats, sizeof(u64)
2671 * (GEM_STATS_LEN + QUEUE_STATS_LEN * MACB_MAX_QUEUES));
2674 static int gem_get_sset_count(struct net_device *dev, int sset)
2676 struct macb *bp = netdev_priv(dev);
2680 return GEM_STATS_LEN + bp->num_queues * QUEUE_STATS_LEN;
2686 static void gem_get_ethtool_strings(struct net_device *dev, u32 sset, u8 *p)
2688 char stat_string[ETH_GSTRING_LEN];
2689 struct macb *bp = netdev_priv(dev);
2690 struct macb_queue *queue;
2696 for (i = 0; i < GEM_STATS_LEN; i++, p += ETH_GSTRING_LEN)
2697 memcpy(p, gem_statistics[i].stat_string,
2700 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
2701 for (i = 0; i < QUEUE_STATS_LEN; i++, p += ETH_GSTRING_LEN) {
2702 snprintf(stat_string, ETH_GSTRING_LEN, "q%d_%s",
2703 q, queue_statistics[i].stat_string);
2704 memcpy(p, stat_string, ETH_GSTRING_LEN);
2711 static struct net_device_stats *macb_get_stats(struct net_device *dev)
2713 struct macb *bp = netdev_priv(dev);
2714 struct net_device_stats *nstat = &bp->dev->stats;
2715 struct macb_stats *hwstat = &bp->hw_stats.macb;
2717 if (macb_is_gem(bp))
2718 return gem_get_stats(bp);
2720 /* read stats from hardware */
2721 macb_update_stats(bp);
2723 /* Convert HW stats into netdevice stats */
2724 nstat->rx_errors = (hwstat->rx_fcs_errors +
2725 hwstat->rx_align_errors +
2726 hwstat->rx_resource_errors +
2727 hwstat->rx_overruns +
2728 hwstat->rx_oversize_pkts +
2729 hwstat->rx_jabbers +
2730 hwstat->rx_undersize_pkts +
2731 hwstat->rx_length_mismatch);
2732 nstat->tx_errors = (hwstat->tx_late_cols +
2733 hwstat->tx_excessive_cols +
2734 hwstat->tx_underruns +
2735 hwstat->tx_carrier_errors +
2736 hwstat->sqe_test_errors);
2737 nstat->collisions = (hwstat->tx_single_cols +
2738 hwstat->tx_multiple_cols +
2739 hwstat->tx_excessive_cols);
2740 nstat->rx_length_errors = (hwstat->rx_oversize_pkts +
2741 hwstat->rx_jabbers +
2742 hwstat->rx_undersize_pkts +
2743 hwstat->rx_length_mismatch);
2744 nstat->rx_over_errors = hwstat->rx_resource_errors +
2745 hwstat->rx_overruns;
2746 nstat->rx_crc_errors = hwstat->rx_fcs_errors;
2747 nstat->rx_frame_errors = hwstat->rx_align_errors;
2748 nstat->rx_fifo_errors = hwstat->rx_overruns;
2749 /* XXX: What does "missed" mean? */
2750 nstat->tx_aborted_errors = hwstat->tx_excessive_cols;
2751 nstat->tx_carrier_errors = hwstat->tx_carrier_errors;
2752 nstat->tx_fifo_errors = hwstat->tx_underruns;
2753 /* Don't know about heartbeat or window errors... */
2758 static int macb_get_regs_len(struct net_device *netdev)
2760 return MACB_GREGS_NBR * sizeof(u32);
2763 static void macb_get_regs(struct net_device *dev, struct ethtool_regs *regs,
2766 struct macb *bp = netdev_priv(dev);
2767 unsigned int tail, head;
2770 regs->version = (macb_readl(bp, MID) & ((1 << MACB_REV_SIZE) - 1))
2771 | MACB_GREGS_VERSION;
2773 tail = macb_tx_ring_wrap(bp, bp->queues[0].tx_tail);
2774 head = macb_tx_ring_wrap(bp, bp->queues[0].tx_head);
2776 regs_buff[0] = macb_readl(bp, NCR);
2777 regs_buff[1] = macb_or_gem_readl(bp, NCFGR);
2778 regs_buff[2] = macb_readl(bp, NSR);
2779 regs_buff[3] = macb_readl(bp, TSR);
2780 regs_buff[4] = macb_readl(bp, RBQP);
2781 regs_buff[5] = macb_readl(bp, TBQP);
2782 regs_buff[6] = macb_readl(bp, RSR);
2783 regs_buff[7] = macb_readl(bp, IMR);
2785 regs_buff[8] = tail;
2786 regs_buff[9] = head;
2787 regs_buff[10] = macb_tx_dma(&bp->queues[0], tail);
2788 regs_buff[11] = macb_tx_dma(&bp->queues[0], head);
2790 if (!(bp->caps & MACB_CAPS_USRIO_DISABLED))
2791 regs_buff[12] = macb_or_gem_readl(bp, USRIO);
2792 if (macb_is_gem(bp))
2793 regs_buff[13] = gem_readl(bp, DMACFG);
2796 static void macb_get_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
2798 struct macb *bp = netdev_priv(netdev);
2803 if (bp->wol & MACB_WOL_HAS_MAGIC_PACKET)
2804 phylink_ethtool_get_wol(bp->phylink, wol);
2807 static int macb_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
2809 struct macb *bp = netdev_priv(netdev);
2812 ret = phylink_ethtool_set_wol(bp->phylink, wol);
2816 if (!(bp->wol & MACB_WOL_HAS_MAGIC_PACKET) ||
2817 (wol->wolopts & ~WAKE_MAGIC))
2820 if (wol->wolopts & WAKE_MAGIC)
2821 bp->wol |= MACB_WOL_ENABLED;
2823 bp->wol &= ~MACB_WOL_ENABLED;
2825 device_set_wakeup_enable(&bp->pdev->dev, bp->wol & MACB_WOL_ENABLED);
2830 static int macb_get_link_ksettings(struct net_device *netdev,
2831 struct ethtool_link_ksettings *kset)
2833 struct macb *bp = netdev_priv(netdev);
2835 return phylink_ethtool_ksettings_get(bp->phylink, kset);
2838 static int macb_set_link_ksettings(struct net_device *netdev,
2839 const struct ethtool_link_ksettings *kset)
2841 struct macb *bp = netdev_priv(netdev);
2843 return phylink_ethtool_ksettings_set(bp->phylink, kset);
2846 static void macb_get_ringparam(struct net_device *netdev,
2847 struct ethtool_ringparam *ring)
2849 struct macb *bp = netdev_priv(netdev);
2851 ring->rx_max_pending = MAX_RX_RING_SIZE;
2852 ring->tx_max_pending = MAX_TX_RING_SIZE;
2854 ring->rx_pending = bp->rx_ring_size;
2855 ring->tx_pending = bp->tx_ring_size;
2858 static int macb_set_ringparam(struct net_device *netdev,
2859 struct ethtool_ringparam *ring)
2861 struct macb *bp = netdev_priv(netdev);
2862 u32 new_rx_size, new_tx_size;
2863 unsigned int reset = 0;
2865 if ((ring->rx_mini_pending) || (ring->rx_jumbo_pending))
2868 new_rx_size = clamp_t(u32, ring->rx_pending,
2869 MIN_RX_RING_SIZE, MAX_RX_RING_SIZE);
2870 new_rx_size = roundup_pow_of_two(new_rx_size);
2872 new_tx_size = clamp_t(u32, ring->tx_pending,
2873 MIN_TX_RING_SIZE, MAX_TX_RING_SIZE);
2874 new_tx_size = roundup_pow_of_two(new_tx_size);
2876 if ((new_tx_size == bp->tx_ring_size) &&
2877 (new_rx_size == bp->rx_ring_size)) {
2882 if (netif_running(bp->dev)) {
2884 macb_close(bp->dev);
2887 bp->rx_ring_size = new_rx_size;
2888 bp->tx_ring_size = new_tx_size;
2896 #ifdef CONFIG_MACB_USE_HWSTAMP
2897 static unsigned int gem_get_tsu_rate(struct macb *bp)
2899 struct clk *tsu_clk;
2900 unsigned int tsu_rate;
2902 tsu_clk = devm_clk_get(&bp->pdev->dev, "tsu_clk");
2903 if (!IS_ERR(tsu_clk))
2904 tsu_rate = clk_get_rate(tsu_clk);
2905 /* try pclk instead */
2906 else if (!IS_ERR(bp->pclk)) {
2908 tsu_rate = clk_get_rate(tsu_clk);
2914 static s32 gem_get_ptp_max_adj(void)
2919 static int gem_get_ts_info(struct net_device *dev,
2920 struct ethtool_ts_info *info)
2922 struct macb *bp = netdev_priv(dev);
2924 if ((bp->hw_dma_cap & HW_DMA_CAP_PTP) == 0) {
2925 ethtool_op_get_ts_info(dev, info);
2929 info->so_timestamping =
2930 SOF_TIMESTAMPING_TX_SOFTWARE |
2931 SOF_TIMESTAMPING_RX_SOFTWARE |
2932 SOF_TIMESTAMPING_SOFTWARE |
2933 SOF_TIMESTAMPING_TX_HARDWARE |
2934 SOF_TIMESTAMPING_RX_HARDWARE |
2935 SOF_TIMESTAMPING_RAW_HARDWARE;
2937 (1 << HWTSTAMP_TX_ONESTEP_SYNC) |
2938 (1 << HWTSTAMP_TX_OFF) |
2939 (1 << HWTSTAMP_TX_ON);
2941 (1 << HWTSTAMP_FILTER_NONE) |
2942 (1 << HWTSTAMP_FILTER_ALL);
2944 info->phc_index = bp->ptp_clock ? ptp_clock_index(bp->ptp_clock) : -1;
2949 static struct macb_ptp_info gem_ptp_info = {
2950 .ptp_init = gem_ptp_init,
2951 .ptp_remove = gem_ptp_remove,
2952 .get_ptp_max_adj = gem_get_ptp_max_adj,
2953 .get_tsu_rate = gem_get_tsu_rate,
2954 .get_ts_info = gem_get_ts_info,
2955 .get_hwtst = gem_get_hwtst,
2956 .set_hwtst = gem_set_hwtst,
2960 static int macb_get_ts_info(struct net_device *netdev,
2961 struct ethtool_ts_info *info)
2963 struct macb *bp = netdev_priv(netdev);
2966 return bp->ptp_info->get_ts_info(netdev, info);
2968 return ethtool_op_get_ts_info(netdev, info);
2971 static void gem_enable_flow_filters(struct macb *bp, bool enable)
2973 struct net_device *netdev = bp->dev;
2974 struct ethtool_rx_fs_item *item;
2978 if (!(netdev->features & NETIF_F_NTUPLE))
2981 num_t2_scr = GEM_BFEXT(T2SCR, gem_readl(bp, DCFG8));
2983 list_for_each_entry(item, &bp->rx_fs_list.list, list) {
2984 struct ethtool_rx_flow_spec *fs = &item->fs;
2985 struct ethtool_tcpip4_spec *tp4sp_m;
2987 if (fs->location >= num_t2_scr)
2990 t2_scr = gem_readl_n(bp, SCRT2, fs->location);
2992 /* enable/disable screener regs for the flow entry */
2993 t2_scr = GEM_BFINS(ETHTEN, enable, t2_scr);
2995 /* only enable fields with no masking */
2996 tp4sp_m = &(fs->m_u.tcp_ip4_spec);
2998 if (enable && (tp4sp_m->ip4src == 0xFFFFFFFF))
2999 t2_scr = GEM_BFINS(CMPAEN, 1, t2_scr);
3001 t2_scr = GEM_BFINS(CMPAEN, 0, t2_scr);
3003 if (enable && (tp4sp_m->ip4dst == 0xFFFFFFFF))
3004 t2_scr = GEM_BFINS(CMPBEN, 1, t2_scr);
3006 t2_scr = GEM_BFINS(CMPBEN, 0, t2_scr);
3008 if (enable && ((tp4sp_m->psrc == 0xFFFF) || (tp4sp_m->pdst == 0xFFFF)))
3009 t2_scr = GEM_BFINS(CMPCEN, 1, t2_scr);
3011 t2_scr = GEM_BFINS(CMPCEN, 0, t2_scr);
3013 gem_writel_n(bp, SCRT2, fs->location, t2_scr);
3017 static void gem_prog_cmp_regs(struct macb *bp, struct ethtool_rx_flow_spec *fs)
3019 struct ethtool_tcpip4_spec *tp4sp_v, *tp4sp_m;
3020 uint16_t index = fs->location;
3026 tp4sp_v = &(fs->h_u.tcp_ip4_spec);
3027 tp4sp_m = &(fs->m_u.tcp_ip4_spec);
3029 /* ignore field if any masking set */
3030 if (tp4sp_m->ip4src == 0xFFFFFFFF) {
3031 /* 1st compare reg - IP source address */
3034 w0 = tp4sp_v->ip4src;
3035 w1 = GEM_BFINS(T2DISMSK, 1, w1); /* 32-bit compare */
3036 w1 = GEM_BFINS(T2CMPOFST, GEM_T2COMPOFST_ETYPE, w1);
3037 w1 = GEM_BFINS(T2OFST, ETYPE_SRCIP_OFFSET, w1);
3038 gem_writel_n(bp, T2CMPW0, T2CMP_OFST(GEM_IP4SRC_CMP(index)), w0);
3039 gem_writel_n(bp, T2CMPW1, T2CMP_OFST(GEM_IP4SRC_CMP(index)), w1);
3043 /* ignore field if any masking set */
3044 if (tp4sp_m->ip4dst == 0xFFFFFFFF) {
3045 /* 2nd compare reg - IP destination address */
3048 w0 = tp4sp_v->ip4dst;
3049 w1 = GEM_BFINS(T2DISMSK, 1, w1); /* 32-bit compare */
3050 w1 = GEM_BFINS(T2CMPOFST, GEM_T2COMPOFST_ETYPE, w1);
3051 w1 = GEM_BFINS(T2OFST, ETYPE_DSTIP_OFFSET, w1);
3052 gem_writel_n(bp, T2CMPW0, T2CMP_OFST(GEM_IP4DST_CMP(index)), w0);
3053 gem_writel_n(bp, T2CMPW1, T2CMP_OFST(GEM_IP4DST_CMP(index)), w1);
3057 /* ignore both port fields if masking set in both */
3058 if ((tp4sp_m->psrc == 0xFFFF) || (tp4sp_m->pdst == 0xFFFF)) {
3059 /* 3rd compare reg - source port, destination port */
3062 w1 = GEM_BFINS(T2CMPOFST, GEM_T2COMPOFST_IPHDR, w1);
3063 if (tp4sp_m->psrc == tp4sp_m->pdst) {
3064 w0 = GEM_BFINS(T2MASK, tp4sp_v->psrc, w0);
3065 w0 = GEM_BFINS(T2CMP, tp4sp_v->pdst, w0);
3066 w1 = GEM_BFINS(T2DISMSK, 1, w1); /* 32-bit compare */
3067 w1 = GEM_BFINS(T2OFST, IPHDR_SRCPORT_OFFSET, w1);
3069 /* only one port definition */
3070 w1 = GEM_BFINS(T2DISMSK, 0, w1); /* 16-bit compare */
3071 w0 = GEM_BFINS(T2MASK, 0xFFFF, w0);
3072 if (tp4sp_m->psrc == 0xFFFF) { /* src port */
3073 w0 = GEM_BFINS(T2CMP, tp4sp_v->psrc, w0);
3074 w1 = GEM_BFINS(T2OFST, IPHDR_SRCPORT_OFFSET, w1);
3075 } else { /* dst port */
3076 w0 = GEM_BFINS(T2CMP, tp4sp_v->pdst, w0);
3077 w1 = GEM_BFINS(T2OFST, IPHDR_DSTPORT_OFFSET, w1);
3080 gem_writel_n(bp, T2CMPW0, T2CMP_OFST(GEM_PORT_CMP(index)), w0);
3081 gem_writel_n(bp, T2CMPW1, T2CMP_OFST(GEM_PORT_CMP(index)), w1);
3086 t2_scr = GEM_BFINS(QUEUE, (fs->ring_cookie) & 0xFF, t2_scr);
3087 t2_scr = GEM_BFINS(ETHT2IDX, SCRT2_ETHT, t2_scr);
3089 t2_scr = GEM_BFINS(CMPA, GEM_IP4SRC_CMP(index), t2_scr);
3091 t2_scr = GEM_BFINS(CMPB, GEM_IP4DST_CMP(index), t2_scr);
3093 t2_scr = GEM_BFINS(CMPC, GEM_PORT_CMP(index), t2_scr);
3094 gem_writel_n(bp, SCRT2, index, t2_scr);
3097 static int gem_add_flow_filter(struct net_device *netdev,
3098 struct ethtool_rxnfc *cmd)
3100 struct macb *bp = netdev_priv(netdev);
3101 struct ethtool_rx_flow_spec *fs = &cmd->fs;
3102 struct ethtool_rx_fs_item *item, *newfs;
3103 unsigned long flags;
3107 newfs = kmalloc(sizeof(*newfs), GFP_KERNEL);
3110 memcpy(&newfs->fs, fs, sizeof(newfs->fs));
3113 "Adding flow filter entry,type=%u,queue=%u,loc=%u,src=%08X,dst=%08X,ps=%u,pd=%u\n",
3114 fs->flow_type, (int)fs->ring_cookie, fs->location,
3115 htonl(fs->h_u.tcp_ip4_spec.ip4src),
3116 htonl(fs->h_u.tcp_ip4_spec.ip4dst),
3117 htons(fs->h_u.tcp_ip4_spec.psrc), htons(fs->h_u.tcp_ip4_spec.pdst));
3119 spin_lock_irqsave(&bp->rx_fs_lock, flags);
3121 /* find correct place to add in list */
3122 list_for_each_entry(item, &bp->rx_fs_list.list, list) {
3123 if (item->fs.location > newfs->fs.location) {
3124 list_add_tail(&newfs->list, &item->list);
3127 } else if (item->fs.location == fs->location) {
3128 netdev_err(netdev, "Rule not added: location %d not free!\n",
3135 list_add_tail(&newfs->list, &bp->rx_fs_list.list);
3137 gem_prog_cmp_regs(bp, fs);
3138 bp->rx_fs_list.count++;
3139 /* enable filtering if NTUPLE on */
3140 gem_enable_flow_filters(bp, 1);
3142 spin_unlock_irqrestore(&bp->rx_fs_lock, flags);
3146 spin_unlock_irqrestore(&bp->rx_fs_lock, flags);
3151 static int gem_del_flow_filter(struct net_device *netdev,
3152 struct ethtool_rxnfc *cmd)
3154 struct macb *bp = netdev_priv(netdev);
3155 struct ethtool_rx_fs_item *item;
3156 struct ethtool_rx_flow_spec *fs;
3157 unsigned long flags;
3159 spin_lock_irqsave(&bp->rx_fs_lock, flags);
3161 list_for_each_entry(item, &bp->rx_fs_list.list, list) {
3162 if (item->fs.location == cmd->fs.location) {
3163 /* disable screener regs for the flow entry */
3166 "Deleting flow filter entry,type=%u,queue=%u,loc=%u,src=%08X,dst=%08X,ps=%u,pd=%u\n",
3167 fs->flow_type, (int)fs->ring_cookie, fs->location,
3168 htonl(fs->h_u.tcp_ip4_spec.ip4src),
3169 htonl(fs->h_u.tcp_ip4_spec.ip4dst),
3170 htons(fs->h_u.tcp_ip4_spec.psrc),
3171 htons(fs->h_u.tcp_ip4_spec.pdst));
3173 gem_writel_n(bp, SCRT2, fs->location, 0);
3175 list_del(&item->list);
3176 bp->rx_fs_list.count--;
3177 spin_unlock_irqrestore(&bp->rx_fs_lock, flags);
3183 spin_unlock_irqrestore(&bp->rx_fs_lock, flags);
3187 static int gem_get_flow_entry(struct net_device *netdev,
3188 struct ethtool_rxnfc *cmd)
3190 struct macb *bp = netdev_priv(netdev);
3191 struct ethtool_rx_fs_item *item;
3193 list_for_each_entry(item, &bp->rx_fs_list.list, list) {
3194 if (item->fs.location == cmd->fs.location) {
3195 memcpy(&cmd->fs, &item->fs, sizeof(cmd->fs));
3202 static int gem_get_all_flow_entries(struct net_device *netdev,
3203 struct ethtool_rxnfc *cmd, u32 *rule_locs)
3205 struct macb *bp = netdev_priv(netdev);
3206 struct ethtool_rx_fs_item *item;
3209 list_for_each_entry(item, &bp->rx_fs_list.list, list) {
3210 if (cnt == cmd->rule_cnt)
3212 rule_locs[cnt] = item->fs.location;
3215 cmd->data = bp->max_tuples;
3216 cmd->rule_cnt = cnt;
3221 static int gem_get_rxnfc(struct net_device *netdev, struct ethtool_rxnfc *cmd,
3224 struct macb *bp = netdev_priv(netdev);
3228 case ETHTOOL_GRXRINGS:
3229 cmd->data = bp->num_queues;
3231 case ETHTOOL_GRXCLSRLCNT:
3232 cmd->rule_cnt = bp->rx_fs_list.count;
3234 case ETHTOOL_GRXCLSRULE:
3235 ret = gem_get_flow_entry(netdev, cmd);
3237 case ETHTOOL_GRXCLSRLALL:
3238 ret = gem_get_all_flow_entries(netdev, cmd, rule_locs);
3242 "Command parameter %d is not supported\n", cmd->cmd);
3249 static int gem_set_rxnfc(struct net_device *netdev, struct ethtool_rxnfc *cmd)
3251 struct macb *bp = netdev_priv(netdev);
3255 case ETHTOOL_SRXCLSRLINS:
3256 if ((cmd->fs.location >= bp->max_tuples)
3257 || (cmd->fs.ring_cookie >= bp->num_queues)) {
3261 ret = gem_add_flow_filter(netdev, cmd);
3263 case ETHTOOL_SRXCLSRLDEL:
3264 ret = gem_del_flow_filter(netdev, cmd);
3268 "Command parameter %d is not supported\n", cmd->cmd);
3275 static const struct ethtool_ops macb_ethtool_ops = {
3276 .get_regs_len = macb_get_regs_len,
3277 .get_regs = macb_get_regs,
3278 .get_link = ethtool_op_get_link,
3279 .get_ts_info = ethtool_op_get_ts_info,
3280 .get_wol = macb_get_wol,
3281 .set_wol = macb_set_wol,
3282 .get_link_ksettings = macb_get_link_ksettings,
3283 .set_link_ksettings = macb_set_link_ksettings,
3284 .get_ringparam = macb_get_ringparam,
3285 .set_ringparam = macb_set_ringparam,
3288 static const struct ethtool_ops gem_ethtool_ops = {
3289 .get_regs_len = macb_get_regs_len,
3290 .get_regs = macb_get_regs,
3291 .get_link = ethtool_op_get_link,
3292 .get_ts_info = macb_get_ts_info,
3293 .get_ethtool_stats = gem_get_ethtool_stats,
3294 .get_strings = gem_get_ethtool_strings,
3295 .get_sset_count = gem_get_sset_count,
3296 .get_link_ksettings = macb_get_link_ksettings,
3297 .set_link_ksettings = macb_set_link_ksettings,
3298 .get_ringparam = macb_get_ringparam,
3299 .set_ringparam = macb_set_ringparam,
3300 .get_rxnfc = gem_get_rxnfc,
3301 .set_rxnfc = gem_set_rxnfc,
3304 static int macb_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
3306 struct macb *bp = netdev_priv(dev);
3308 if (!netif_running(dev))
3314 return bp->ptp_info->set_hwtst(dev, rq, cmd);
3316 return bp->ptp_info->get_hwtst(dev, rq);
3320 return phylink_mii_ioctl(bp->phylink, rq, cmd);
3323 static inline void macb_set_txcsum_feature(struct macb *bp,
3324 netdev_features_t features)
3328 if (!macb_is_gem(bp))
3331 val = gem_readl(bp, DMACFG);
3332 if (features & NETIF_F_HW_CSUM)
3333 val |= GEM_BIT(TXCOEN);
3335 val &= ~GEM_BIT(TXCOEN);
3337 gem_writel(bp, DMACFG, val);
3340 static inline void macb_set_rxcsum_feature(struct macb *bp,
3341 netdev_features_t features)
3343 struct net_device *netdev = bp->dev;
3346 if (!macb_is_gem(bp))
3349 val = gem_readl(bp, NCFGR);
3350 if ((features & NETIF_F_RXCSUM) && !(netdev->flags & IFF_PROMISC))
3351 val |= GEM_BIT(RXCOEN);
3353 val &= ~GEM_BIT(RXCOEN);
3355 gem_writel(bp, NCFGR, val);
3358 static inline void macb_set_rxflow_feature(struct macb *bp,
3359 netdev_features_t features)
3361 if (!macb_is_gem(bp))
3364 gem_enable_flow_filters(bp, !!(features & NETIF_F_NTUPLE));
3367 static int macb_set_features(struct net_device *netdev,
3368 netdev_features_t features)
3370 struct macb *bp = netdev_priv(netdev);
3371 netdev_features_t changed = features ^ netdev->features;
3373 /* TX checksum offload */
3374 if (changed & NETIF_F_HW_CSUM)
3375 macb_set_txcsum_feature(bp, features);
3377 /* RX checksum offload */
3378 if (changed & NETIF_F_RXCSUM)
3379 macb_set_rxcsum_feature(bp, features);
3381 /* RX Flow Filters */
3382 if (changed & NETIF_F_NTUPLE)
3383 macb_set_rxflow_feature(bp, features);
3388 static void macb_restore_features(struct macb *bp)
3390 struct net_device *netdev = bp->dev;
3391 netdev_features_t features = netdev->features;
3393 /* TX checksum offload */
3394 macb_set_txcsum_feature(bp, features);
3396 /* RX checksum offload */
3397 macb_set_rxcsum_feature(bp, features);
3399 /* RX Flow Filters */
3400 macb_set_rxflow_feature(bp, features);
3403 static const struct net_device_ops macb_netdev_ops = {
3404 .ndo_open = macb_open,
3405 .ndo_stop = macb_close,
3406 .ndo_start_xmit = macb_start_xmit,
3407 .ndo_set_rx_mode = macb_set_rx_mode,
3408 .ndo_get_stats = macb_get_stats,
3409 .ndo_do_ioctl = macb_ioctl,
3410 .ndo_validate_addr = eth_validate_addr,
3411 .ndo_change_mtu = macb_change_mtu,
3412 .ndo_set_mac_address = eth_mac_addr,
3413 #ifdef CONFIG_NET_POLL_CONTROLLER
3414 .ndo_poll_controller = macb_poll_controller,
3416 .ndo_set_features = macb_set_features,
3417 .ndo_features_check = macb_features_check,
3420 /* Configure peripheral capabilities according to device tree
3421 * and integration options used
3423 static void macb_configure_caps(struct macb *bp,
3424 const struct macb_config *dt_conf)
3429 bp->caps = dt_conf->caps;
3431 if (hw_is_gem(bp->regs, bp->native_io)) {
3432 bp->caps |= MACB_CAPS_MACB_IS_GEM;
3434 dcfg = gem_readl(bp, DCFG1);
3435 if (GEM_BFEXT(IRQCOR, dcfg) == 0)
3436 bp->caps |= MACB_CAPS_ISR_CLEAR_ON_WRITE;
3437 dcfg = gem_readl(bp, DCFG2);
3438 if ((dcfg & (GEM_BIT(RX_PKT_BUFF) | GEM_BIT(TX_PKT_BUFF))) == 0)
3439 bp->caps |= MACB_CAPS_FIFO_MODE;
3440 #ifdef CONFIG_MACB_USE_HWSTAMP
3441 if (gem_has_ptp(bp)) {
3442 if (!GEM_BFEXT(TSU, gem_readl(bp, DCFG5)))
3443 dev_err(&bp->pdev->dev,
3444 "GEM doesn't support hardware ptp.\n");
3446 bp->hw_dma_cap |= HW_DMA_CAP_PTP;
3447 bp->ptp_info = &gem_ptp_info;
3453 dev_dbg(&bp->pdev->dev, "Cadence caps 0x%08x\n", bp->caps);
3456 static void macb_probe_queues(void __iomem *mem,
3458 unsigned int *queue_mask,
3459 unsigned int *num_queues)
3466 /* is it macb or gem ?
3468 * We need to read directly from the hardware here because
3469 * we are early in the probe process and don't have the
3470 * MACB_CAPS_MACB_IS_GEM flag positioned
3472 if (!hw_is_gem(mem, native_io))
3475 /* bit 0 is never set but queue 0 always exists */
3476 *queue_mask = readl_relaxed(mem + GEM_DCFG6) & 0xff;
3480 for (hw_q = 1; hw_q < MACB_MAX_QUEUES; ++hw_q)
3481 if (*queue_mask & (1 << hw_q))
3485 static int macb_clk_init(struct platform_device *pdev, struct clk **pclk,
3486 struct clk **hclk, struct clk **tx_clk,
3487 struct clk **rx_clk, struct clk **tsu_clk)
3489 struct macb_platform_data *pdata;
3492 pdata = dev_get_platdata(&pdev->dev);
3494 *pclk = pdata->pclk;
3495 *hclk = pdata->hclk;
3497 *pclk = devm_clk_get(&pdev->dev, "pclk");
3498 *hclk = devm_clk_get(&pdev->dev, "hclk");
3501 if (IS_ERR_OR_NULL(*pclk)) {
3502 err = PTR_ERR(*pclk);
3506 dev_err(&pdev->dev, "failed to get macb_clk (%d)\n", err);
3510 if (IS_ERR_OR_NULL(*hclk)) {
3511 err = PTR_ERR(*hclk);
3515 dev_err(&pdev->dev, "failed to get hclk (%d)\n", err);
3519 *tx_clk = devm_clk_get_optional(&pdev->dev, "tx_clk");
3520 if (IS_ERR(*tx_clk))
3521 return PTR_ERR(*tx_clk);
3523 *rx_clk = devm_clk_get_optional(&pdev->dev, "rx_clk");
3524 if (IS_ERR(*rx_clk))
3525 return PTR_ERR(*rx_clk);
3527 *tsu_clk = devm_clk_get_optional(&pdev->dev, "tsu_clk");
3528 if (IS_ERR(*tsu_clk))
3529 return PTR_ERR(*tsu_clk);
3531 err = clk_prepare_enable(*pclk);
3533 dev_err(&pdev->dev, "failed to enable pclk (%d)\n", err);
3537 err = clk_prepare_enable(*hclk);
3539 dev_err(&pdev->dev, "failed to enable hclk (%d)\n", err);
3540 goto err_disable_pclk;
3543 err = clk_prepare_enable(*tx_clk);
3545 dev_err(&pdev->dev, "failed to enable tx_clk (%d)\n", err);
3546 goto err_disable_hclk;
3549 err = clk_prepare_enable(*rx_clk);
3551 dev_err(&pdev->dev, "failed to enable rx_clk (%d)\n", err);
3552 goto err_disable_txclk;
3555 err = clk_prepare_enable(*tsu_clk);
3557 dev_err(&pdev->dev, "failed to enable tsu_clk (%d)\n", err);
3558 goto err_disable_rxclk;
3564 clk_disable_unprepare(*rx_clk);
3567 clk_disable_unprepare(*tx_clk);
3570 clk_disable_unprepare(*hclk);
3573 clk_disable_unprepare(*pclk);
3578 static int macb_init(struct platform_device *pdev)
3580 struct net_device *dev = platform_get_drvdata(pdev);
3581 unsigned int hw_q, q;
3582 struct macb *bp = netdev_priv(dev);
3583 struct macb_queue *queue;
3587 bp->tx_ring_size = DEFAULT_TX_RING_SIZE;
3588 bp->rx_ring_size = DEFAULT_RX_RING_SIZE;
3590 /* set the queue register mapping once for all: queue0 has a special
3591 * register mapping but we don't want to test the queue index then
3592 * compute the corresponding register offset at run time.
3594 for (hw_q = 0, q = 0; hw_q < MACB_MAX_QUEUES; ++hw_q) {
3595 if (!(bp->queue_mask & (1 << hw_q)))
3598 queue = &bp->queues[q];
3600 netif_napi_add(dev, &queue->napi, macb_poll, NAPI_POLL_WEIGHT);
3602 queue->ISR = GEM_ISR(hw_q - 1);
3603 queue->IER = GEM_IER(hw_q - 1);
3604 queue->IDR = GEM_IDR(hw_q - 1);
3605 queue->IMR = GEM_IMR(hw_q - 1);
3606 queue->TBQP = GEM_TBQP(hw_q - 1);
3607 queue->RBQP = GEM_RBQP(hw_q - 1);
3608 queue->RBQS = GEM_RBQS(hw_q - 1);
3609 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
3610 if (bp->hw_dma_cap & HW_DMA_CAP_64B) {
3611 queue->TBQPH = GEM_TBQPH(hw_q - 1);
3612 queue->RBQPH = GEM_RBQPH(hw_q - 1);
3616 /* queue0 uses legacy registers */
3617 queue->ISR = MACB_ISR;
3618 queue->IER = MACB_IER;
3619 queue->IDR = MACB_IDR;
3620 queue->IMR = MACB_IMR;
3621 queue->TBQP = MACB_TBQP;
3622 queue->RBQP = MACB_RBQP;
3623 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
3624 if (bp->hw_dma_cap & HW_DMA_CAP_64B) {
3625 queue->TBQPH = MACB_TBQPH;
3626 queue->RBQPH = MACB_RBQPH;
3631 /* get irq: here we use the linux queue index, not the hardware
3632 * queue index. the queue irq definitions in the device tree
3633 * must remove the optional gaps that could exist in the
3634 * hardware queue mask.
3636 queue->irq = platform_get_irq(pdev, q);
3637 err = devm_request_irq(&pdev->dev, queue->irq, macb_interrupt,
3638 IRQF_SHARED, dev->name, queue);
3641 "Unable to request IRQ %d (error %d)\n",
3646 INIT_WORK(&queue->tx_error_task, macb_tx_error_task);
3650 dev->netdev_ops = &macb_netdev_ops;
3652 /* setup appropriated routines according to adapter type */
3653 if (macb_is_gem(bp)) {
3654 bp->max_tx_length = GEM_MAX_TX_LEN;
3655 bp->macbgem_ops.mog_alloc_rx_buffers = gem_alloc_rx_buffers;
3656 bp->macbgem_ops.mog_free_rx_buffers = gem_free_rx_buffers;
3657 bp->macbgem_ops.mog_init_rings = gem_init_rings;
3658 bp->macbgem_ops.mog_rx = gem_rx;
3659 dev->ethtool_ops = &gem_ethtool_ops;
3661 bp->max_tx_length = MACB_MAX_TX_LEN;
3662 bp->macbgem_ops.mog_alloc_rx_buffers = macb_alloc_rx_buffers;
3663 bp->macbgem_ops.mog_free_rx_buffers = macb_free_rx_buffers;
3664 bp->macbgem_ops.mog_init_rings = macb_init_rings;
3665 bp->macbgem_ops.mog_rx = macb_rx;
3666 dev->ethtool_ops = &macb_ethtool_ops;
3670 dev->hw_features = NETIF_F_SG;
3672 /* Check LSO capability */
3673 if (GEM_BFEXT(PBUF_LSO, gem_readl(bp, DCFG6)))
3674 dev->hw_features |= MACB_NETIF_LSO;
3676 /* Checksum offload is only available on gem with packet buffer */
3677 if (macb_is_gem(bp) && !(bp->caps & MACB_CAPS_FIFO_MODE))
3678 dev->hw_features |= NETIF_F_HW_CSUM | NETIF_F_RXCSUM;
3679 if (bp->caps & MACB_CAPS_SG_DISABLED)
3680 dev->hw_features &= ~NETIF_F_SG;
3681 dev->features = dev->hw_features;
3683 /* Check RX Flow Filters support.
3684 * Max Rx flows set by availability of screeners & compare regs:
3685 * each 4-tuple define requires 1 T2 screener reg + 3 compare regs
3687 reg = gem_readl(bp, DCFG8);
3688 bp->max_tuples = min((GEM_BFEXT(SCR2CMP, reg) / 3),
3689 GEM_BFEXT(T2SCR, reg));
3690 if (bp->max_tuples > 0) {
3691 /* also needs one ethtype match to check IPv4 */
3692 if (GEM_BFEXT(SCR2ETH, reg) > 0) {
3693 /* program this reg now */
3695 reg = GEM_BFINS(ETHTCMP, (uint16_t)ETH_P_IP, reg);
3696 gem_writel_n(bp, ETHT, SCRT2_ETHT, reg);
3697 /* Filtering is supported in hw but don't enable it in kernel now */
3698 dev->hw_features |= NETIF_F_NTUPLE;
3699 /* init Rx flow definitions */
3700 INIT_LIST_HEAD(&bp->rx_fs_list.list);
3701 bp->rx_fs_list.count = 0;
3702 spin_lock_init(&bp->rx_fs_lock);
3707 if (!(bp->caps & MACB_CAPS_USRIO_DISABLED)) {
3709 if (bp->phy_interface == PHY_INTERFACE_MODE_RGMII)
3710 val = GEM_BIT(RGMII);
3711 else if (bp->phy_interface == PHY_INTERFACE_MODE_RMII &&
3712 (bp->caps & MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII))
3713 val = MACB_BIT(RMII);
3714 else if (!(bp->caps & MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII))
3715 val = MACB_BIT(MII);
3717 if (bp->caps & MACB_CAPS_USRIO_HAS_CLKEN)
3718 val |= MACB_BIT(CLKEN);
3720 macb_or_gem_writel(bp, USRIO, val);
3723 /* Set MII management clock divider */
3724 val = macb_mdc_clk_div(bp);
3725 val |= macb_dbw(bp);
3726 if (bp->phy_interface == PHY_INTERFACE_MODE_SGMII)
3727 val |= GEM_BIT(SGMIIEN) | GEM_BIT(PCSSEL);
3728 macb_writel(bp, NCFGR, val);
3733 #if defined(CONFIG_OF)
3734 /* 1518 rounded up */
3735 #define AT91ETHER_MAX_RBUFF_SZ 0x600
3736 /* max number of receive buffers */
3737 #define AT91ETHER_MAX_RX_DESCR 9
3739 static struct sifive_fu540_macb_mgmt *mgmt;
3741 /* Initialize and start the Receiver and Transmit subsystems */
3742 static int at91ether_start(struct net_device *dev)
3744 struct macb *lp = netdev_priv(dev);
3745 struct macb_queue *q = &lp->queues[0];
3746 struct macb_dma_desc *desc;
3751 q->rx_ring = dma_alloc_coherent(&lp->pdev->dev,
3752 (AT91ETHER_MAX_RX_DESCR *
3753 macb_dma_desc_get_size(lp)),
3754 &q->rx_ring_dma, GFP_KERNEL);
3758 q->rx_buffers = dma_alloc_coherent(&lp->pdev->dev,
3759 AT91ETHER_MAX_RX_DESCR *
3760 AT91ETHER_MAX_RBUFF_SZ,
3761 &q->rx_buffers_dma, GFP_KERNEL);
3762 if (!q->rx_buffers) {
3763 dma_free_coherent(&lp->pdev->dev,
3764 AT91ETHER_MAX_RX_DESCR *
3765 macb_dma_desc_get_size(lp),
3766 q->rx_ring, q->rx_ring_dma);
3771 addr = q->rx_buffers_dma;
3772 for (i = 0; i < AT91ETHER_MAX_RX_DESCR; i++) {
3773 desc = macb_rx_desc(q, i);
3774 macb_set_addr(lp, desc, addr);
3776 addr += AT91ETHER_MAX_RBUFF_SZ;
3779 /* Set the Wrap bit on the last descriptor */
3780 desc->addr |= MACB_BIT(RX_WRAP);
3782 /* Reset buffer index */
3785 /* Program address of descriptor list in Rx Buffer Queue register */
3786 macb_writel(lp, RBQP, q->rx_ring_dma);
3788 /* Enable Receive and Transmit */
3789 ctl = macb_readl(lp, NCR);
3790 macb_writel(lp, NCR, ctl | MACB_BIT(RE) | MACB_BIT(TE));
3795 /* Open the ethernet interface */
3796 static int at91ether_open(struct net_device *dev)
3798 struct macb *lp = netdev_priv(dev);
3802 ret = pm_runtime_get_sync(&lp->pdev->dev);
3806 /* Clear internal statistics */
3807 ctl = macb_readl(lp, NCR);
3808 macb_writel(lp, NCR, ctl | MACB_BIT(CLRSTAT));
3810 macb_set_hwaddr(lp);
3812 ret = at91ether_start(dev);
3816 /* Enable MAC interrupts */
3817 macb_writel(lp, IER, MACB_BIT(RCOMP) |
3819 MACB_BIT(ISR_TUND) |
3822 MACB_BIT(ISR_ROVR) |
3825 ret = macb_phylink_connect(lp);
3829 netif_start_queue(dev);
3834 /* Close the interface */
3835 static int at91ether_close(struct net_device *dev)
3837 struct macb *lp = netdev_priv(dev);
3838 struct macb_queue *q = &lp->queues[0];
3841 /* Disable Receiver and Transmitter */
3842 ctl = macb_readl(lp, NCR);
3843 macb_writel(lp, NCR, ctl & ~(MACB_BIT(TE) | MACB_BIT(RE)));
3845 /* Disable MAC interrupts */
3846 macb_writel(lp, IDR, MACB_BIT(RCOMP) |
3848 MACB_BIT(ISR_TUND) |
3851 MACB_BIT(ISR_ROVR) |
3854 netif_stop_queue(dev);
3856 phylink_stop(lp->phylink);
3857 phylink_disconnect_phy(lp->phylink);
3859 dma_free_coherent(&lp->pdev->dev,
3860 AT91ETHER_MAX_RX_DESCR *
3861 macb_dma_desc_get_size(lp),
3862 q->rx_ring, q->rx_ring_dma);
3865 dma_free_coherent(&lp->pdev->dev,
3866 AT91ETHER_MAX_RX_DESCR * AT91ETHER_MAX_RBUFF_SZ,
3867 q->rx_buffers, q->rx_buffers_dma);
3868 q->rx_buffers = NULL;
3870 return pm_runtime_put(&lp->pdev->dev);
3873 /* Transmit packet */
3874 static netdev_tx_t at91ether_start_xmit(struct sk_buff *skb,
3875 struct net_device *dev)
3877 struct macb *lp = netdev_priv(dev);
3879 if (macb_readl(lp, TSR) & MACB_BIT(RM9200_BNQ)) {
3880 netif_stop_queue(dev);
3882 /* Store packet information (to free when Tx completed) */
3884 lp->skb_length = skb->len;
3885 lp->skb_physaddr = dma_map_single(&lp->pdev->dev, skb->data,
3886 skb->len, DMA_TO_DEVICE);
3887 if (dma_mapping_error(&lp->pdev->dev, lp->skb_physaddr)) {
3888 dev_kfree_skb_any(skb);
3889 dev->stats.tx_dropped++;
3890 netdev_err(dev, "%s: DMA mapping error\n", __func__);
3891 return NETDEV_TX_OK;
3894 /* Set address of the data in the Transmit Address register */
3895 macb_writel(lp, TAR, lp->skb_physaddr);
3896 /* Set length of the packet in the Transmit Control register */
3897 macb_writel(lp, TCR, skb->len);
3900 netdev_err(dev, "%s called, but device is busy!\n", __func__);
3901 return NETDEV_TX_BUSY;
3904 return NETDEV_TX_OK;
3907 /* Extract received frame from buffer descriptors and sent to upper layers.
3908 * (Called from interrupt context)
3910 static void at91ether_rx(struct net_device *dev)
3912 struct macb *lp = netdev_priv(dev);
3913 struct macb_queue *q = &lp->queues[0];
3914 struct macb_dma_desc *desc;
3915 unsigned char *p_recv;
3916 struct sk_buff *skb;
3917 unsigned int pktlen;
3919 desc = macb_rx_desc(q, q->rx_tail);
3920 while (desc->addr & MACB_BIT(RX_USED)) {
3921 p_recv = q->rx_buffers + q->rx_tail * AT91ETHER_MAX_RBUFF_SZ;
3922 pktlen = MACB_BF(RX_FRMLEN, desc->ctrl);
3923 skb = netdev_alloc_skb(dev, pktlen + 2);
3925 skb_reserve(skb, 2);
3926 skb_put_data(skb, p_recv, pktlen);
3928 skb->protocol = eth_type_trans(skb, dev);
3929 dev->stats.rx_packets++;
3930 dev->stats.rx_bytes += pktlen;
3933 dev->stats.rx_dropped++;
3936 if (desc->ctrl & MACB_BIT(RX_MHASH_MATCH))
3937 dev->stats.multicast++;
3939 /* reset ownership bit */
3940 desc->addr &= ~MACB_BIT(RX_USED);
3942 /* wrap after last buffer */
3943 if (q->rx_tail == AT91ETHER_MAX_RX_DESCR - 1)
3948 desc = macb_rx_desc(q, q->rx_tail);
3952 /* MAC interrupt handler */
3953 static irqreturn_t at91ether_interrupt(int irq, void *dev_id)
3955 struct net_device *dev = dev_id;
3956 struct macb *lp = netdev_priv(dev);
3959 /* MAC Interrupt Status register indicates what interrupts are pending.
3960 * It is automatically cleared once read.
3962 intstatus = macb_readl(lp, ISR);
3964 /* Receive complete */
3965 if (intstatus & MACB_BIT(RCOMP))
3968 /* Transmit complete */
3969 if (intstatus & MACB_BIT(TCOMP)) {
3970 /* The TCOM bit is set even if the transmission failed */
3971 if (intstatus & (MACB_BIT(ISR_TUND) | MACB_BIT(ISR_RLE)))
3972 dev->stats.tx_errors++;
3975 dev_consume_skb_irq(lp->skb);
3977 dma_unmap_single(&lp->pdev->dev, lp->skb_physaddr,
3978 lp->skb_length, DMA_TO_DEVICE);
3979 dev->stats.tx_packets++;
3980 dev->stats.tx_bytes += lp->skb_length;
3982 netif_wake_queue(dev);
3985 /* Work-around for EMAC Errata section 41.3.1 */
3986 if (intstatus & MACB_BIT(RXUBR)) {
3987 ctl = macb_readl(lp, NCR);
3988 macb_writel(lp, NCR, ctl & ~MACB_BIT(RE));
3990 macb_writel(lp, NCR, ctl | MACB_BIT(RE));
3993 if (intstatus & MACB_BIT(ISR_ROVR))
3994 netdev_err(dev, "ROVR error\n");
3999 #ifdef CONFIG_NET_POLL_CONTROLLER
4000 static void at91ether_poll_controller(struct net_device *dev)
4002 unsigned long flags;
4004 local_irq_save(flags);
4005 at91ether_interrupt(dev->irq, dev);
4006 local_irq_restore(flags);
4010 static const struct net_device_ops at91ether_netdev_ops = {
4011 .ndo_open = at91ether_open,
4012 .ndo_stop = at91ether_close,
4013 .ndo_start_xmit = at91ether_start_xmit,
4014 .ndo_get_stats = macb_get_stats,
4015 .ndo_set_rx_mode = macb_set_rx_mode,
4016 .ndo_set_mac_address = eth_mac_addr,
4017 .ndo_do_ioctl = macb_ioctl,
4018 .ndo_validate_addr = eth_validate_addr,
4019 #ifdef CONFIG_NET_POLL_CONTROLLER
4020 .ndo_poll_controller = at91ether_poll_controller,
4024 static int at91ether_clk_init(struct platform_device *pdev, struct clk **pclk,
4025 struct clk **hclk, struct clk **tx_clk,
4026 struct clk **rx_clk, struct clk **tsu_clk)
4035 *pclk = devm_clk_get(&pdev->dev, "ether_clk");
4037 return PTR_ERR(*pclk);
4039 err = clk_prepare_enable(*pclk);
4041 dev_err(&pdev->dev, "failed to enable pclk (%d)\n", err);
4048 static int at91ether_init(struct platform_device *pdev)
4050 struct net_device *dev = platform_get_drvdata(pdev);
4051 struct macb *bp = netdev_priv(dev);
4054 bp->queues[0].bp = bp;
4056 dev->netdev_ops = &at91ether_netdev_ops;
4057 dev->ethtool_ops = &macb_ethtool_ops;
4059 err = devm_request_irq(&pdev->dev, dev->irq, at91ether_interrupt,
4064 macb_writel(bp, NCR, 0);
4066 macb_writel(bp, NCFGR, MACB_BF(CLK, MACB_CLK_DIV32) | MACB_BIT(BIG));
4071 static unsigned long fu540_macb_tx_recalc_rate(struct clk_hw *hw,
4072 unsigned long parent_rate)
4077 static long fu540_macb_tx_round_rate(struct clk_hw *hw, unsigned long rate,
4078 unsigned long *parent_rate)
4080 if (WARN_ON(rate < 2500000))
4082 else if (rate == 2500000)
4084 else if (WARN_ON(rate < 13750000))
4086 else if (WARN_ON(rate < 25000000))
4088 else if (rate == 25000000)
4090 else if (WARN_ON(rate < 75000000))
4092 else if (WARN_ON(rate < 125000000))
4094 else if (rate == 125000000)
4097 WARN_ON(rate > 125000000);
4102 static int fu540_macb_tx_set_rate(struct clk_hw *hw, unsigned long rate,
4103 unsigned long parent_rate)
4105 rate = fu540_macb_tx_round_rate(hw, rate, &parent_rate);
4106 if (rate != 125000000)
4107 iowrite32(1, mgmt->reg);
4109 iowrite32(0, mgmt->reg);
4115 static const struct clk_ops fu540_c000_ops = {
4116 .recalc_rate = fu540_macb_tx_recalc_rate,
4117 .round_rate = fu540_macb_tx_round_rate,
4118 .set_rate = fu540_macb_tx_set_rate,
4121 static int fu540_c000_clk_init(struct platform_device *pdev, struct clk **pclk,
4122 struct clk **hclk, struct clk **tx_clk,
4123 struct clk **rx_clk, struct clk **tsu_clk)
4125 struct clk_init_data init;
4128 err = macb_clk_init(pdev, pclk, hclk, tx_clk, rx_clk, tsu_clk);
4132 mgmt = devm_kzalloc(&pdev->dev, sizeof(*mgmt), GFP_KERNEL);
4136 init.name = "sifive-gemgxl-mgmt";
4137 init.ops = &fu540_c000_ops;
4139 init.num_parents = 0;
4142 mgmt->hw.init = &init;
4144 *tx_clk = devm_clk_register(&pdev->dev, &mgmt->hw);
4145 if (IS_ERR(*tx_clk))
4146 return PTR_ERR(*tx_clk);
4148 err = clk_prepare_enable(*tx_clk);
4150 dev_err(&pdev->dev, "failed to enable tx_clk (%u)\n", err);
4152 dev_info(&pdev->dev, "Registered clk switch '%s'\n", init.name);
4157 static int fu540_c000_init(struct platform_device *pdev)
4159 struct resource *res;
4161 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
4165 mgmt->reg = ioremap(res->start, resource_size(res));
4169 return macb_init(pdev);
4172 static const struct macb_config fu540_c000_config = {
4173 .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE | MACB_CAPS_JUMBO |
4174 MACB_CAPS_GEM_HAS_PTP,
4175 .dma_burst_length = 16,
4176 .clk_init = fu540_c000_clk_init,
4177 .init = fu540_c000_init,
4178 .jumbo_max_len = 10240,
4181 static const struct macb_config at91sam9260_config = {
4182 .caps = MACB_CAPS_USRIO_HAS_CLKEN | MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII,
4183 .clk_init = macb_clk_init,
4187 static const struct macb_config sama5d3macb_config = {
4188 .caps = MACB_CAPS_SG_DISABLED
4189 | MACB_CAPS_USRIO_HAS_CLKEN | MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII,
4190 .clk_init = macb_clk_init,
4194 static const struct macb_config pc302gem_config = {
4195 .caps = MACB_CAPS_SG_DISABLED | MACB_CAPS_GIGABIT_MODE_AVAILABLE,
4196 .dma_burst_length = 16,
4197 .clk_init = macb_clk_init,
4201 static const struct macb_config sama5d2_config = {
4202 .caps = MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII,
4203 .dma_burst_length = 16,
4204 .clk_init = macb_clk_init,
4208 static const struct macb_config sama5d3_config = {
4209 .caps = MACB_CAPS_SG_DISABLED | MACB_CAPS_GIGABIT_MODE_AVAILABLE
4210 | MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII | MACB_CAPS_JUMBO,
4211 .dma_burst_length = 16,
4212 .clk_init = macb_clk_init,
4214 .jumbo_max_len = 10240,
4217 static const struct macb_config sama5d4_config = {
4218 .caps = MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII,
4219 .dma_burst_length = 4,
4220 .clk_init = macb_clk_init,
4224 static const struct macb_config emac_config = {
4225 .caps = MACB_CAPS_NEEDS_RSTONUBR | MACB_CAPS_MACB_IS_EMAC,
4226 .clk_init = at91ether_clk_init,
4227 .init = at91ether_init,
4230 static const struct macb_config np4_config = {
4231 .caps = MACB_CAPS_USRIO_DISABLED,
4232 .clk_init = macb_clk_init,
4236 static const struct macb_config zynqmp_config = {
4237 .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE |
4239 MACB_CAPS_GEM_HAS_PTP | MACB_CAPS_BD_RD_PREFETCH,
4240 .dma_burst_length = 16,
4241 .clk_init = macb_clk_init,
4243 .jumbo_max_len = 10240,
4246 static const struct macb_config zynq_config = {
4247 .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE | MACB_CAPS_NO_GIGABIT_HALF |
4248 MACB_CAPS_NEEDS_RSTONUBR,
4249 .dma_burst_length = 16,
4250 .clk_init = macb_clk_init,
4254 static const struct of_device_id macb_dt_ids[] = {
4255 { .compatible = "cdns,at32ap7000-macb" },
4256 { .compatible = "cdns,at91sam9260-macb", .data = &at91sam9260_config },
4257 { .compatible = "cdns,macb" },
4258 { .compatible = "cdns,np4-macb", .data = &np4_config },
4259 { .compatible = "cdns,pc302-gem", .data = &pc302gem_config },
4260 { .compatible = "cdns,gem", .data = &pc302gem_config },
4261 { .compatible = "cdns,sam9x60-macb", .data = &at91sam9260_config },
4262 { .compatible = "atmel,sama5d2-gem", .data = &sama5d2_config },
4263 { .compatible = "atmel,sama5d3-gem", .data = &sama5d3_config },
4264 { .compatible = "atmel,sama5d3-macb", .data = &sama5d3macb_config },
4265 { .compatible = "atmel,sama5d4-gem", .data = &sama5d4_config },
4266 { .compatible = "cdns,at91rm9200-emac", .data = &emac_config },
4267 { .compatible = "cdns,emac", .data = &emac_config },
4268 { .compatible = "cdns,zynqmp-gem", .data = &zynqmp_config},
4269 { .compatible = "cdns,zynq-gem", .data = &zynq_config },
4270 { .compatible = "sifive,fu540-c000-gem", .data = &fu540_c000_config },
4273 MODULE_DEVICE_TABLE(of, macb_dt_ids);
4274 #endif /* CONFIG_OF */
4276 static const struct macb_config default_gem_config = {
4277 .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE |
4279 MACB_CAPS_GEM_HAS_PTP,
4280 .dma_burst_length = 16,
4281 .clk_init = macb_clk_init,
4283 .jumbo_max_len = 10240,
4286 static int macb_probe(struct platform_device *pdev)
4288 const struct macb_config *macb_config = &default_gem_config;
4289 int (*clk_init)(struct platform_device *, struct clk **,
4290 struct clk **, struct clk **, struct clk **,
4291 struct clk **) = macb_config->clk_init;
4292 int (*init)(struct platform_device *) = macb_config->init;
4293 struct device_node *np = pdev->dev.of_node;
4294 struct clk *pclk, *hclk = NULL, *tx_clk = NULL, *rx_clk = NULL;
4295 struct clk *tsu_clk = NULL;
4296 unsigned int queue_mask, num_queues;
4298 phy_interface_t interface;
4299 struct net_device *dev;
4300 struct resource *regs;
4306 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
4307 mem = devm_ioremap_resource(&pdev->dev, regs);
4309 return PTR_ERR(mem);
4312 const struct of_device_id *match;
4314 match = of_match_node(macb_dt_ids, np);
4315 if (match && match->data) {
4316 macb_config = match->data;
4317 clk_init = macb_config->clk_init;
4318 init = macb_config->init;
4322 err = clk_init(pdev, &pclk, &hclk, &tx_clk, &rx_clk, &tsu_clk);
4326 pm_runtime_set_autosuspend_delay(&pdev->dev, MACB_PM_TIMEOUT);
4327 pm_runtime_use_autosuspend(&pdev->dev);
4328 pm_runtime_get_noresume(&pdev->dev);
4329 pm_runtime_set_active(&pdev->dev);
4330 pm_runtime_enable(&pdev->dev);
4331 native_io = hw_is_native_io(mem);
4333 macb_probe_queues(mem, native_io, &queue_mask, &num_queues);
4334 dev = alloc_etherdev_mq(sizeof(*bp), num_queues);
4337 goto err_disable_clocks;
4340 dev->base_addr = regs->start;
4342 SET_NETDEV_DEV(dev, &pdev->dev);
4344 bp = netdev_priv(dev);
4348 bp->native_io = native_io;
4350 bp->macb_reg_readl = hw_readl_native;
4351 bp->macb_reg_writel = hw_writel_native;
4353 bp->macb_reg_readl = hw_readl;
4354 bp->macb_reg_writel = hw_writel;
4356 bp->num_queues = num_queues;
4357 bp->queue_mask = queue_mask;
4359 bp->dma_burst_length = macb_config->dma_burst_length;
4362 bp->tx_clk = tx_clk;
4363 bp->rx_clk = rx_clk;
4364 bp->tsu_clk = tsu_clk;
4366 bp->jumbo_max_len = macb_config->jumbo_max_len;
4369 if (of_get_property(np, "magic-packet", NULL))
4370 bp->wol |= MACB_WOL_HAS_MAGIC_PACKET;
4371 device_init_wakeup(&pdev->dev, bp->wol & MACB_WOL_HAS_MAGIC_PACKET);
4373 spin_lock_init(&bp->lock);
4375 /* setup capabilities */
4376 macb_configure_caps(bp, macb_config);
4378 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
4379 if (GEM_BFEXT(DAW64, gem_readl(bp, DCFG6))) {
4380 dma_set_mask(&pdev->dev, DMA_BIT_MASK(44));
4381 bp->hw_dma_cap |= HW_DMA_CAP_64B;
4384 platform_set_drvdata(pdev, dev);
4386 dev->irq = platform_get_irq(pdev, 0);
4389 goto err_out_free_netdev;
4392 /* MTU range: 68 - 1500 or 10240 */
4393 dev->min_mtu = GEM_MTU_MIN_SIZE;
4394 if (bp->caps & MACB_CAPS_JUMBO)
4395 dev->max_mtu = gem_readl(bp, JML) - ETH_HLEN - ETH_FCS_LEN;
4397 dev->max_mtu = ETH_DATA_LEN;
4399 if (bp->caps & MACB_CAPS_BD_RD_PREFETCH) {
4400 val = GEM_BFEXT(RXBD_RDBUFF, gem_readl(bp, DCFG10));
4402 bp->rx_bd_rd_prefetch = (2 << (val - 1)) *
4403 macb_dma_desc_get_size(bp);
4405 val = GEM_BFEXT(TXBD_RDBUFF, gem_readl(bp, DCFG10));
4407 bp->tx_bd_rd_prefetch = (2 << (val - 1)) *
4408 macb_dma_desc_get_size(bp);
4411 bp->rx_intr_mask = MACB_RX_INT_FLAGS;
4412 if (bp->caps & MACB_CAPS_NEEDS_RSTONUBR)
4413 bp->rx_intr_mask |= MACB_BIT(RXUBR);
4415 mac = of_get_mac_address(np);
4416 if (PTR_ERR(mac) == -EPROBE_DEFER) {
4417 err = -EPROBE_DEFER;
4418 goto err_out_free_netdev;
4419 } else if (!IS_ERR_OR_NULL(mac)) {
4420 ether_addr_copy(bp->dev->dev_addr, mac);
4422 macb_get_hwaddr(bp);
4425 err = of_get_phy_mode(np, &interface);
4427 /* not found in DT, MII by default */
4428 bp->phy_interface = PHY_INTERFACE_MODE_MII;
4430 bp->phy_interface = interface;
4432 bp->speed = SPEED_UNKNOWN;
4434 /* IP specific init */
4437 goto err_out_free_netdev;
4439 err = macb_mii_init(bp);
4441 goto err_out_free_netdev;
4443 netif_carrier_off(dev);
4445 err = register_netdev(dev);
4447 dev_err(&pdev->dev, "Cannot register net device, aborting.\n");
4448 goto err_out_unregister_mdio;
4451 tasklet_init(&bp->hresp_err_tasklet, macb_hresp_error_task,
4454 netdev_info(dev, "Cadence %s rev 0x%08x at 0x%08lx irq %d (%pM)\n",
4455 macb_is_gem(bp) ? "GEM" : "MACB", macb_readl(bp, MID),
4456 dev->base_addr, dev->irq, dev->dev_addr);
4458 pm_runtime_mark_last_busy(&bp->pdev->dev);
4459 pm_runtime_put_autosuspend(&bp->pdev->dev);
4463 err_out_unregister_mdio:
4464 mdiobus_unregister(bp->mii_bus);
4465 mdiobus_free(bp->mii_bus);
4467 err_out_free_netdev:
4471 clk_disable_unprepare(tx_clk);
4472 clk_disable_unprepare(hclk);
4473 clk_disable_unprepare(pclk);
4474 clk_disable_unprepare(rx_clk);
4475 clk_disable_unprepare(tsu_clk);
4476 pm_runtime_disable(&pdev->dev);
4477 pm_runtime_set_suspended(&pdev->dev);
4478 pm_runtime_dont_use_autosuspend(&pdev->dev);
4483 static int macb_remove(struct platform_device *pdev)
4485 struct net_device *dev;
4488 dev = platform_get_drvdata(pdev);
4491 bp = netdev_priv(dev);
4492 mdiobus_unregister(bp->mii_bus);
4493 mdiobus_free(bp->mii_bus);
4495 unregister_netdev(dev);
4496 tasklet_kill(&bp->hresp_err_tasklet);
4497 pm_runtime_disable(&pdev->dev);
4498 pm_runtime_dont_use_autosuspend(&pdev->dev);
4499 if (!pm_runtime_suspended(&pdev->dev)) {
4500 clk_disable_unprepare(bp->tx_clk);
4501 clk_disable_unprepare(bp->hclk);
4502 clk_disable_unprepare(bp->pclk);
4503 clk_disable_unprepare(bp->rx_clk);
4504 clk_disable_unprepare(bp->tsu_clk);
4505 pm_runtime_set_suspended(&pdev->dev);
4507 phylink_destroy(bp->phylink);
4514 static int __maybe_unused macb_suspend(struct device *dev)
4516 struct net_device *netdev = dev_get_drvdata(dev);
4517 struct macb *bp = netdev_priv(netdev);
4518 struct macb_queue *queue = bp->queues;
4519 unsigned long flags;
4522 if (!netif_running(netdev))
4525 if (bp->wol & MACB_WOL_ENABLED) {
4526 macb_writel(bp, IER, MACB_BIT(WOL));
4527 macb_writel(bp, WOL, MACB_BIT(MAG));
4528 enable_irq_wake(bp->queues[0].irq);
4529 netif_device_detach(netdev);
4531 netif_device_detach(netdev);
4532 for (q = 0, queue = bp->queues; q < bp->num_queues;
4534 napi_disable(&queue->napi);
4536 phylink_stop(bp->phylink);
4538 spin_lock_irqsave(&bp->lock, flags);
4540 spin_unlock_irqrestore(&bp->lock, flags);
4542 if (!(bp->caps & MACB_CAPS_USRIO_DISABLED))
4543 bp->pm_data.usrio = macb_or_gem_readl(bp, USRIO);
4545 if (netdev->hw_features & NETIF_F_NTUPLE)
4546 bp->pm_data.scrt2 = gem_readl_n(bp, ETHT, SCRT2_ETHT);
4549 netif_carrier_off(netdev);
4551 bp->ptp_info->ptp_remove(netdev);
4552 pm_runtime_force_suspend(dev);
4557 static int __maybe_unused macb_resume(struct device *dev)
4559 struct net_device *netdev = dev_get_drvdata(dev);
4560 struct macb *bp = netdev_priv(netdev);
4561 struct macb_queue *queue = bp->queues;
4564 if (!netif_running(netdev))
4567 pm_runtime_force_resume(dev);
4569 if (bp->wol & MACB_WOL_ENABLED) {
4570 macb_writel(bp, IDR, MACB_BIT(WOL));
4571 macb_writel(bp, WOL, 0);
4572 disable_irq_wake(bp->queues[0].irq);
4574 macb_writel(bp, NCR, MACB_BIT(MPE));
4576 if (netdev->hw_features & NETIF_F_NTUPLE)
4577 gem_writel_n(bp, ETHT, SCRT2_ETHT, bp->pm_data.scrt2);
4579 if (!(bp->caps & MACB_CAPS_USRIO_DISABLED))
4580 macb_or_gem_writel(bp, USRIO, bp->pm_data.usrio);
4582 for (q = 0, queue = bp->queues; q < bp->num_queues;
4584 napi_enable(&queue->napi);
4586 phylink_start(bp->phylink);
4591 macb_set_rx_mode(netdev);
4592 macb_restore_features(bp);
4593 netif_device_attach(netdev);
4595 bp->ptp_info->ptp_init(netdev);
4600 static int __maybe_unused macb_runtime_suspend(struct device *dev)
4602 struct net_device *netdev = dev_get_drvdata(dev);
4603 struct macb *bp = netdev_priv(netdev);
4605 if (!(device_may_wakeup(&bp->dev->dev))) {
4606 clk_disable_unprepare(bp->tx_clk);
4607 clk_disable_unprepare(bp->hclk);
4608 clk_disable_unprepare(bp->pclk);
4609 clk_disable_unprepare(bp->rx_clk);
4611 clk_disable_unprepare(bp->tsu_clk);
4616 static int __maybe_unused macb_runtime_resume(struct device *dev)
4618 struct net_device *netdev = dev_get_drvdata(dev);
4619 struct macb *bp = netdev_priv(netdev);
4621 if (!(device_may_wakeup(&bp->dev->dev))) {
4622 clk_prepare_enable(bp->pclk);
4623 clk_prepare_enable(bp->hclk);
4624 clk_prepare_enable(bp->tx_clk);
4625 clk_prepare_enable(bp->rx_clk);
4627 clk_prepare_enable(bp->tsu_clk);
4632 static const struct dev_pm_ops macb_pm_ops = {
4633 SET_SYSTEM_SLEEP_PM_OPS(macb_suspend, macb_resume)
4634 SET_RUNTIME_PM_OPS(macb_runtime_suspend, macb_runtime_resume, NULL)
4637 static struct platform_driver macb_driver = {
4638 .probe = macb_probe,
4639 .remove = macb_remove,
4642 .of_match_table = of_match_ptr(macb_dt_ids),
4647 module_platform_driver(macb_driver);
4649 MODULE_LICENSE("GPL");
4650 MODULE_DESCRIPTION("Cadence MACB/GEM Ethernet driver");
4651 MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
4652 MODULE_ALIAS("platform:macb");