2 * Cadence MACB/GEM Ethernet Controller driver
4 * Copyright (C) 2004-2006 Atmel Corporation
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
11 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
12 #include <linux/clk.h>
13 #include <linux/module.h>
14 #include <linux/moduleparam.h>
15 #include <linux/kernel.h>
16 #include <linux/types.h>
17 #include <linux/circ_buf.h>
18 #include <linux/slab.h>
19 #include <linux/init.h>
21 #include <linux/gpio.h>
22 #include <linux/interrupt.h>
23 #include <linux/netdevice.h>
24 #include <linux/etherdevice.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/platform_data/macb.h>
27 #include <linux/platform_device.h>
28 #include <linux/phy.h>
30 #include <linux/of_device.h>
31 #include <linux/of_mdio.h>
32 #include <linux/of_net.h>
33 #include <linux/pinctrl/consumer.h>
37 #define MACB_RX_BUFFER_SIZE 128
38 #define RX_BUFFER_MULTIPLE 64 /* bytes */
39 #define RX_RING_SIZE 512 /* must be power of 2 */
40 #define RX_RING_BYTES (sizeof(struct macb_dma_desc) * RX_RING_SIZE)
42 #define TX_RING_SIZE 128 /* must be power of 2 */
43 #define TX_RING_BYTES (sizeof(struct macb_dma_desc) * TX_RING_SIZE)
45 /* level of occupied TX descriptors under which we wake up TX process */
46 #define MACB_TX_WAKEUP_THRESH (3 * TX_RING_SIZE / 4)
48 #define MACB_RX_INT_FLAGS (MACB_BIT(RCOMP) | MACB_BIT(RXUBR) \
50 #define MACB_TX_ERR_FLAGS (MACB_BIT(ISR_TUND) \
53 #define MACB_TX_INT_FLAGS (MACB_TX_ERR_FLAGS | MACB_BIT(TCOMP))
56 * Graceful stop timeouts in us. We should allow up to
57 * 1 frame time (10 Mbits/s, full-duplex, ignoring collisions)
59 #define MACB_HALT_TIMEOUT 1230
61 /* Ring buffer accessors */
62 static unsigned int macb_tx_ring_wrap(unsigned int index)
64 return index & (TX_RING_SIZE - 1);
67 static struct macb_dma_desc *macb_tx_desc(struct macb *bp, unsigned int index)
69 return &bp->tx_ring[macb_tx_ring_wrap(index)];
72 static struct macb_tx_skb *macb_tx_skb(struct macb *bp, unsigned int index)
74 return &bp->tx_skb[macb_tx_ring_wrap(index)];
77 static dma_addr_t macb_tx_dma(struct macb *bp, unsigned int index)
81 offset = macb_tx_ring_wrap(index) * sizeof(struct macb_dma_desc);
83 return bp->tx_ring_dma + offset;
86 static unsigned int macb_rx_ring_wrap(unsigned int index)
88 return index & (RX_RING_SIZE - 1);
91 static struct macb_dma_desc *macb_rx_desc(struct macb *bp, unsigned int index)
93 return &bp->rx_ring[macb_rx_ring_wrap(index)];
96 static void *macb_rx_buffer(struct macb *bp, unsigned int index)
98 return bp->rx_buffers + bp->rx_buffer_size * macb_rx_ring_wrap(index);
101 void macb_set_hwaddr(struct macb *bp)
106 bottom = cpu_to_le32(*((u32 *)bp->dev->dev_addr));
107 macb_or_gem_writel(bp, SA1B, bottom);
108 top = cpu_to_le16(*((u16 *)(bp->dev->dev_addr + 4)));
109 macb_or_gem_writel(bp, SA1T, top);
111 /* Clear unused address register sets */
112 macb_or_gem_writel(bp, SA2B, 0);
113 macb_or_gem_writel(bp, SA2T, 0);
114 macb_or_gem_writel(bp, SA3B, 0);
115 macb_or_gem_writel(bp, SA3T, 0);
116 macb_or_gem_writel(bp, SA4B, 0);
117 macb_or_gem_writel(bp, SA4T, 0);
119 EXPORT_SYMBOL_GPL(macb_set_hwaddr);
121 void macb_get_hwaddr(struct macb *bp)
123 struct macb_platform_data *pdata;
129 pdata = dev_get_platdata(&bp->pdev->dev);
131 /* Check all 4 address register for vaild address */
132 for (i = 0; i < 4; i++) {
133 bottom = macb_or_gem_readl(bp, SA1B + i * 8);
134 top = macb_or_gem_readl(bp, SA1T + i * 8);
136 if (pdata && pdata->rev_eth_addr) {
137 addr[5] = bottom & 0xff;
138 addr[4] = (bottom >> 8) & 0xff;
139 addr[3] = (bottom >> 16) & 0xff;
140 addr[2] = (bottom >> 24) & 0xff;
141 addr[1] = top & 0xff;
142 addr[0] = (top & 0xff00) >> 8;
144 addr[0] = bottom & 0xff;
145 addr[1] = (bottom >> 8) & 0xff;
146 addr[2] = (bottom >> 16) & 0xff;
147 addr[3] = (bottom >> 24) & 0xff;
148 addr[4] = top & 0xff;
149 addr[5] = (top >> 8) & 0xff;
152 if (is_valid_ether_addr(addr)) {
153 memcpy(bp->dev->dev_addr, addr, sizeof(addr));
158 netdev_info(bp->dev, "invalid hw address, using random\n");
159 eth_hw_addr_random(bp->dev);
161 EXPORT_SYMBOL_GPL(macb_get_hwaddr);
163 static int macb_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
165 struct macb *bp = bus->priv;
168 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_SOF)
169 | MACB_BF(RW, MACB_MAN_READ)
170 | MACB_BF(PHYA, mii_id)
171 | MACB_BF(REGA, regnum)
172 | MACB_BF(CODE, MACB_MAN_CODE)));
174 /* wait for end of transfer */
175 while (!MACB_BFEXT(IDLE, macb_readl(bp, NSR)))
178 value = MACB_BFEXT(DATA, macb_readl(bp, MAN));
183 static int macb_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
186 struct macb *bp = bus->priv;
188 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_SOF)
189 | MACB_BF(RW, MACB_MAN_WRITE)
190 | MACB_BF(PHYA, mii_id)
191 | MACB_BF(REGA, regnum)
192 | MACB_BF(CODE, MACB_MAN_CODE)
193 | MACB_BF(DATA, value)));
195 /* wait for end of transfer */
196 while (!MACB_BFEXT(IDLE, macb_readl(bp, NSR)))
202 static int macb_mdio_reset(struct mii_bus *bus)
208 * macb_set_tx_clk() - Set a clock to a new frequency
209 * @clk Pointer to the clock to change
210 * @rate New frequency in Hz
211 * @dev Pointer to the struct net_device
213 static void macb_set_tx_clk(struct clk *clk, int speed, struct net_device *dev)
215 long ferr, rate, rate_rounded;
231 rate_rounded = clk_round_rate(clk, rate);
232 if (rate_rounded < 0)
235 /* RGMII allows 50 ppm frequency error. Test and warn if this limit
238 ferr = abs(rate_rounded - rate);
239 ferr = DIV_ROUND_UP(ferr, rate / 100000);
241 netdev_warn(dev, "unable to generate target frequency: %ld Hz\n",
244 if (clk_set_rate(clk, rate_rounded))
245 netdev_err(dev, "adjusting tx_clk failed.\n");
248 static void macb_handle_link_change(struct net_device *dev)
250 struct macb *bp = netdev_priv(dev);
251 struct phy_device *phydev = bp->phy_dev;
254 int status_change = 0;
256 spin_lock_irqsave(&bp->lock, flags);
259 if ((bp->speed != phydev->speed) ||
260 (bp->duplex != phydev->duplex)) {
263 reg = macb_readl(bp, NCFGR);
264 reg &= ~(MACB_BIT(SPD) | MACB_BIT(FD));
266 reg &= ~GEM_BIT(GBE);
270 if (phydev->speed == SPEED_100)
271 reg |= MACB_BIT(SPD);
272 if (phydev->speed == SPEED_1000)
275 macb_or_gem_writel(bp, NCFGR, reg);
277 bp->speed = phydev->speed;
278 bp->duplex = phydev->duplex;
283 if (phydev->link != bp->link) {
288 bp->link = phydev->link;
293 spin_unlock_irqrestore(&bp->lock, flags);
295 if (!IS_ERR(bp->tx_clk))
296 macb_set_tx_clk(bp->tx_clk, phydev->speed, dev);
300 netif_carrier_on(dev);
301 netdev_info(dev, "link up (%d/%s)\n",
303 phydev->duplex == DUPLEX_FULL ?
306 netif_carrier_off(dev);
307 netdev_info(dev, "link down\n");
312 /* based on au1000_eth. c*/
313 static int macb_mii_probe(struct net_device *dev)
315 struct macb *bp = netdev_priv(dev);
316 struct macb_platform_data *pdata;
317 struct phy_device *phydev;
321 phydev = phy_find_first(bp->mii_bus);
323 netdev_err(dev, "no PHY found\n");
327 pdata = dev_get_platdata(&bp->pdev->dev);
328 if (pdata && gpio_is_valid(pdata->phy_irq_pin)) {
329 ret = devm_gpio_request(&bp->pdev->dev, pdata->phy_irq_pin, "phy int");
331 phy_irq = gpio_to_irq(pdata->phy_irq_pin);
332 phydev->irq = (phy_irq < 0) ? PHY_POLL : phy_irq;
336 /* attach the mac to the phy */
337 ret = phy_connect_direct(dev, phydev, &macb_handle_link_change,
340 netdev_err(dev, "Could not attach to PHY\n");
344 /* mask with MAC supported features */
346 phydev->supported &= PHY_GBIT_FEATURES;
348 phydev->supported &= PHY_BASIC_FEATURES;
350 phydev->advertising = phydev->supported;
355 bp->phy_dev = phydev;
360 int macb_mii_init(struct macb *bp)
362 struct macb_platform_data *pdata;
363 struct device_node *np;
366 /* Enable management port */
367 macb_writel(bp, NCR, MACB_BIT(MPE));
369 bp->mii_bus = mdiobus_alloc();
370 if (bp->mii_bus == NULL) {
375 bp->mii_bus->name = "MACB_mii_bus";
376 bp->mii_bus->read = &macb_mdio_read;
377 bp->mii_bus->write = &macb_mdio_write;
378 bp->mii_bus->reset = &macb_mdio_reset;
379 snprintf(bp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
380 bp->pdev->name, bp->pdev->id);
381 bp->mii_bus->priv = bp;
382 bp->mii_bus->parent = &bp->dev->dev;
383 pdata = dev_get_platdata(&bp->pdev->dev);
385 bp->mii_bus->irq = kmalloc(sizeof(int)*PHY_MAX_ADDR, GFP_KERNEL);
386 if (!bp->mii_bus->irq) {
388 goto err_out_free_mdiobus;
391 dev_set_drvdata(&bp->dev->dev, bp->mii_bus);
393 np = bp->pdev->dev.of_node;
395 /* try dt phy registration */
396 err = of_mdiobus_register(bp->mii_bus, np);
398 /* fallback to standard phy registration if no phy were
399 found during dt phy registration */
400 if (!err && !phy_find_first(bp->mii_bus)) {
401 for (i = 0; i < PHY_MAX_ADDR; i++) {
402 struct phy_device *phydev;
404 phydev = mdiobus_scan(bp->mii_bus, i);
405 if (IS_ERR(phydev)) {
406 err = PTR_ERR(phydev);
412 goto err_out_unregister_bus;
415 for (i = 0; i < PHY_MAX_ADDR; i++)
416 bp->mii_bus->irq[i] = PHY_POLL;
419 bp->mii_bus->phy_mask = pdata->phy_mask;
421 err = mdiobus_register(bp->mii_bus);
425 goto err_out_free_mdio_irq;
427 err = macb_mii_probe(bp->dev);
429 goto err_out_unregister_bus;
433 err_out_unregister_bus:
434 mdiobus_unregister(bp->mii_bus);
435 err_out_free_mdio_irq:
436 kfree(bp->mii_bus->irq);
437 err_out_free_mdiobus:
438 mdiobus_free(bp->mii_bus);
442 EXPORT_SYMBOL_GPL(macb_mii_init);
444 static void macb_update_stats(struct macb *bp)
446 u32 __iomem *reg = bp->regs + MACB_PFR;
447 u32 *p = &bp->hw_stats.macb.rx_pause_frames;
448 u32 *end = &bp->hw_stats.macb.tx_pause_frames + 1;
450 WARN_ON((unsigned long)(end - p - 1) != (MACB_TPF - MACB_PFR) / 4);
452 for(; p < end; p++, reg++)
453 *p += __raw_readl(reg);
456 static int macb_halt_tx(struct macb *bp)
458 unsigned long halt_time, timeout;
461 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(THALT));
463 timeout = jiffies + usecs_to_jiffies(MACB_HALT_TIMEOUT);
466 status = macb_readl(bp, TSR);
467 if (!(status & MACB_BIT(TGO)))
470 usleep_range(10, 250);
471 } while (time_before(halt_time, timeout));
476 static void macb_tx_error_task(struct work_struct *work)
478 struct macb *bp = container_of(work, struct macb, tx_error_task);
479 struct macb_tx_skb *tx_skb;
483 netdev_vdbg(bp->dev, "macb_tx_error_task: t = %u, h = %u\n",
484 bp->tx_tail, bp->tx_head);
486 /* Make sure nobody is trying to queue up new packets */
487 netif_stop_queue(bp->dev);
490 * Stop transmission now
491 * (in case we have just queued new packets)
493 if (macb_halt_tx(bp))
494 /* Just complain for now, reinitializing TX path can be good */
495 netdev_err(bp->dev, "BUG: halt tx timed out\n");
497 /* No need for the lock here as nobody will interrupt us anymore */
500 * Treat frames in TX queue including the ones that caused the error.
501 * Free transmit buffers in upper layer.
503 for (tail = bp->tx_tail; tail != bp->tx_head; tail++) {
504 struct macb_dma_desc *desc;
507 desc = macb_tx_desc(bp, tail);
509 tx_skb = macb_tx_skb(bp, tail);
512 if (ctrl & MACB_BIT(TX_USED)) {
513 netdev_vdbg(bp->dev, "txerr skb %u (data %p) TX complete\n",
514 macb_tx_ring_wrap(tail), skb->data);
515 bp->stats.tx_packets++;
516 bp->stats.tx_bytes += skb->len;
519 * "Buffers exhausted mid-frame" errors may only happen
520 * if the driver is buggy, so complain loudly about those.
521 * Statistics are updated by hardware.
523 if (ctrl & MACB_BIT(TX_BUF_EXHAUSTED))
525 "BUG: TX buffers exhausted mid-frame\n");
527 desc->ctrl = ctrl | MACB_BIT(TX_USED);
530 dma_unmap_single(&bp->pdev->dev, tx_skb->mapping, skb->len,
536 /* Make descriptor updates visible to hardware */
539 /* Reinitialize the TX desc queue */
540 macb_writel(bp, TBQP, bp->tx_ring_dma);
541 /* Make TX ring reflect state of hardware */
542 bp->tx_head = bp->tx_tail = 0;
544 /* Now we are ready to start transmission again */
545 netif_wake_queue(bp->dev);
547 /* Housework before enabling TX IRQ */
548 macb_writel(bp, TSR, macb_readl(bp, TSR));
549 macb_writel(bp, IER, MACB_TX_INT_FLAGS);
552 static void macb_tx_interrupt(struct macb *bp)
558 status = macb_readl(bp, TSR);
559 macb_writel(bp, TSR, status);
561 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
562 macb_writel(bp, ISR, MACB_BIT(TCOMP));
564 netdev_vdbg(bp->dev, "macb_tx_interrupt status = 0x%03lx\n",
565 (unsigned long)status);
568 for (tail = bp->tx_tail; tail != head; tail++) {
569 struct macb_tx_skb *tx_skb;
571 struct macb_dma_desc *desc;
574 desc = macb_tx_desc(bp, tail);
576 /* Make hw descriptor updates visible to CPU */
581 if (!(ctrl & MACB_BIT(TX_USED)))
584 tx_skb = macb_tx_skb(bp, tail);
587 netdev_vdbg(bp->dev, "skb %u (data %p) TX complete\n",
588 macb_tx_ring_wrap(tail), skb->data);
589 dma_unmap_single(&bp->pdev->dev, tx_skb->mapping, skb->len,
591 bp->stats.tx_packets++;
592 bp->stats.tx_bytes += skb->len;
594 dev_kfree_skb_irq(skb);
598 if (netif_queue_stopped(bp->dev)
599 && CIRC_CNT(bp->tx_head, bp->tx_tail,
600 TX_RING_SIZE) <= MACB_TX_WAKEUP_THRESH)
601 netif_wake_queue(bp->dev);
604 static void gem_rx_refill(struct macb *bp)
608 struct macb_dma_desc *desc;
611 while (CIRC_SPACE(bp->rx_prepared_head, bp->rx_tail, RX_RING_SIZE) > 0) {
614 entry = macb_rx_ring_wrap(bp->rx_prepared_head);
615 desc = &bp->rx_ring[entry];
617 /* Make hw descriptor updates visible to CPU */
622 bp->rx_prepared_head++;
624 if ((addr & MACB_BIT(RX_USED)))
627 if (bp->rx_skbuff[entry] == NULL) {
628 /* allocate sk_buff for this free entry in ring */
629 skb = netdev_alloc_skb(bp->dev, bp->rx_buffer_size);
630 if (unlikely(skb == NULL)) {
632 "Unable to allocate sk_buff\n");
636 /* now fill corresponding descriptor entry */
637 paddr = dma_map_single(&bp->pdev->dev, skb->data,
638 bp->rx_buffer_size, DMA_FROM_DEVICE);
639 if (dma_mapping_error(&bp->pdev->dev, paddr)) {
644 bp->rx_skbuff[entry] = skb;
646 if (entry == RX_RING_SIZE - 1)
647 paddr |= MACB_BIT(RX_WRAP);
648 bp->rx_ring[entry].addr = paddr;
649 bp->rx_ring[entry].ctrl = 0;
651 /* properly align Ethernet header */
652 skb_reserve(skb, NET_IP_ALIGN);
656 /* Make descriptor updates visible to hardware */
659 netdev_vdbg(bp->dev, "rx ring: prepared head %d, tail %d\n",
660 bp->rx_prepared_head, bp->rx_tail);
663 /* Mark DMA descriptors from begin up to and not including end as unused */
664 static void discard_partial_frame(struct macb *bp, unsigned int begin,
669 for (frag = begin; frag != end; frag++) {
670 struct macb_dma_desc *desc = macb_rx_desc(bp, frag);
671 desc->addr &= ~MACB_BIT(RX_USED);
674 /* Make descriptor updates visible to hardware */
678 * When this happens, the hardware stats registers for
679 * whatever caused this is updated, so we don't have to record
684 static int gem_rx(struct macb *bp, int budget)
689 struct macb_dma_desc *desc;
692 while (count < budget) {
695 entry = macb_rx_ring_wrap(bp->rx_tail);
696 desc = &bp->rx_ring[entry];
698 /* Make hw descriptor updates visible to CPU */
704 if (!(addr & MACB_BIT(RX_USED)))
707 desc->addr &= ~MACB_BIT(RX_USED);
711 if (!(ctrl & MACB_BIT(RX_SOF) && ctrl & MACB_BIT(RX_EOF))) {
713 "not whole frame pointed by descriptor\n");
714 bp->stats.rx_dropped++;
717 skb = bp->rx_skbuff[entry];
718 if (unlikely(!skb)) {
720 "inconsistent Rx descriptor chain\n");
721 bp->stats.rx_dropped++;
724 /* now everything is ready for receiving packet */
725 bp->rx_skbuff[entry] = NULL;
726 len = MACB_BFEXT(RX_FRMLEN, ctrl);
728 netdev_vdbg(bp->dev, "gem_rx %u (len %u)\n", entry, len);
731 addr = MACB_BF(RX_WADDR, MACB_BFEXT(RX_WADDR, addr));
732 dma_unmap_single(&bp->pdev->dev, addr,
733 bp->rx_buffer_size, DMA_FROM_DEVICE);
735 skb->protocol = eth_type_trans(skb, bp->dev);
736 skb_checksum_none_assert(skb);
738 bp->stats.rx_packets++;
739 bp->stats.rx_bytes += skb->len;
741 #if defined(DEBUG) && defined(VERBOSE_DEBUG)
742 netdev_vdbg(bp->dev, "received skb of length %u, csum: %08x\n",
743 skb->len, skb->csum);
744 print_hex_dump(KERN_DEBUG, " mac: ", DUMP_PREFIX_ADDRESS, 16, 1,
745 skb->mac_header, 16, true);
746 print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_ADDRESS, 16, 1,
747 skb->data, 32, true);
750 netif_receive_skb(skb);
758 static int macb_rx_frame(struct macb *bp, unsigned int first_frag,
759 unsigned int last_frag)
765 struct macb_dma_desc *desc;
767 desc = macb_rx_desc(bp, last_frag);
768 len = MACB_BFEXT(RX_FRMLEN, desc->ctrl);
770 netdev_vdbg(bp->dev, "macb_rx_frame frags %u - %u (len %u)\n",
771 macb_rx_ring_wrap(first_frag),
772 macb_rx_ring_wrap(last_frag), len);
775 * The ethernet header starts NET_IP_ALIGN bytes into the
776 * first buffer. Since the header is 14 bytes, this makes the
777 * payload word-aligned.
779 * Instead of calling skb_reserve(NET_IP_ALIGN), we just copy
780 * the two padding bytes into the skb so that we avoid hitting
781 * the slowpath in memcpy(), and pull them off afterwards.
783 skb = netdev_alloc_skb(bp->dev, len + NET_IP_ALIGN);
785 bp->stats.rx_dropped++;
786 for (frag = first_frag; ; frag++) {
787 desc = macb_rx_desc(bp, frag);
788 desc->addr &= ~MACB_BIT(RX_USED);
789 if (frag == last_frag)
793 /* Make descriptor updates visible to hardware */
801 skb_checksum_none_assert(skb);
804 for (frag = first_frag; ; frag++) {
805 unsigned int frag_len = bp->rx_buffer_size;
807 if (offset + frag_len > len) {
808 BUG_ON(frag != last_frag);
809 frag_len = len - offset;
811 skb_copy_to_linear_data_offset(skb, offset,
812 macb_rx_buffer(bp, frag), frag_len);
813 offset += bp->rx_buffer_size;
814 desc = macb_rx_desc(bp, frag);
815 desc->addr &= ~MACB_BIT(RX_USED);
817 if (frag == last_frag)
821 /* Make descriptor updates visible to hardware */
824 __skb_pull(skb, NET_IP_ALIGN);
825 skb->protocol = eth_type_trans(skb, bp->dev);
827 bp->stats.rx_packets++;
828 bp->stats.rx_bytes += skb->len;
829 netdev_vdbg(bp->dev, "received skb of length %u, csum: %08x\n",
830 skb->len, skb->csum);
831 netif_receive_skb(skb);
836 static int macb_rx(struct macb *bp, int budget)
842 for (tail = bp->rx_tail; budget > 0; tail++) {
843 struct macb_dma_desc *desc = macb_rx_desc(bp, tail);
846 /* Make hw descriptor updates visible to CPU */
852 if (!(addr & MACB_BIT(RX_USED)))
855 if (ctrl & MACB_BIT(RX_SOF)) {
856 if (first_frag != -1)
857 discard_partial_frame(bp, first_frag, tail);
861 if (ctrl & MACB_BIT(RX_EOF)) {
863 BUG_ON(first_frag == -1);
865 dropped = macb_rx_frame(bp, first_frag, tail);
874 if (first_frag != -1)
875 bp->rx_tail = first_frag;
882 static int macb_poll(struct napi_struct *napi, int budget)
884 struct macb *bp = container_of(napi, struct macb, napi);
888 status = macb_readl(bp, RSR);
889 macb_writel(bp, RSR, status);
893 netdev_vdbg(bp->dev, "poll: status = %08lx, budget = %d\n",
894 (unsigned long)status, budget);
896 work_done = bp->macbgem_ops.mog_rx(bp, budget);
897 if (work_done < budget) {
901 * We've done what we can to clean the buffers. Make sure we
902 * get notified when new packets arrive.
904 macb_writel(bp, IER, MACB_RX_INT_FLAGS);
906 /* Packets received while interrupts were disabled */
907 status = macb_readl(bp, RSR);
908 if (unlikely(status))
909 napi_reschedule(napi);
912 /* TODO: Handle errors */
917 static irqreturn_t macb_interrupt(int irq, void *dev_id)
919 struct net_device *dev = dev_id;
920 struct macb *bp = netdev_priv(dev);
923 status = macb_readl(bp, ISR);
925 if (unlikely(!status))
928 spin_lock(&bp->lock);
931 /* close possible race with dev_close */
932 if (unlikely(!netif_running(dev))) {
933 macb_writel(bp, IDR, -1);
937 netdev_vdbg(bp->dev, "isr = 0x%08lx\n", (unsigned long)status);
939 if (status & MACB_RX_INT_FLAGS) {
941 * There's no point taking any more interrupts
942 * until we have processed the buffers. The
943 * scheduling call may fail if the poll routine
944 * is already scheduled, so disable interrupts
947 macb_writel(bp, IDR, MACB_RX_INT_FLAGS);
948 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
949 macb_writel(bp, ISR, MACB_BIT(RCOMP));
951 if (napi_schedule_prep(&bp->napi)) {
952 netdev_vdbg(bp->dev, "scheduling RX softirq\n");
953 __napi_schedule(&bp->napi);
957 if (unlikely(status & (MACB_TX_ERR_FLAGS))) {
958 macb_writel(bp, IDR, MACB_TX_INT_FLAGS);
959 schedule_work(&bp->tx_error_task);
963 if (status & MACB_BIT(TCOMP))
964 macb_tx_interrupt(bp);
967 * Link change detection isn't possible with RMII, so we'll
968 * add that if/when we get our hands on a full-blown MII PHY.
971 if (status & MACB_BIT(ISR_ROVR)) {
972 /* We missed at least one packet */
974 bp->hw_stats.gem.rx_overruns++;
976 bp->hw_stats.macb.rx_overruns++;
979 if (status & MACB_BIT(HRESP)) {
981 * TODO: Reset the hardware, and maybe move the
982 * netdev_err to a lower-priority context as well
985 netdev_err(dev, "DMA bus error: HRESP not OK\n");
988 status = macb_readl(bp, ISR);
991 spin_unlock(&bp->lock);
996 #ifdef CONFIG_NET_POLL_CONTROLLER
998 * Polling receive - used by netconsole and other diagnostic tools
999 * to allow network i/o with interrupts disabled.
1001 static void macb_poll_controller(struct net_device *dev)
1003 unsigned long flags;
1005 local_irq_save(flags);
1006 macb_interrupt(dev->irq, dev);
1007 local_irq_restore(flags);
1011 static int macb_start_xmit(struct sk_buff *skb, struct net_device *dev)
1013 struct macb *bp = netdev_priv(dev);
1015 unsigned int len, entry;
1016 struct macb_dma_desc *desc;
1017 struct macb_tx_skb *tx_skb;
1019 unsigned long flags;
1021 #if defined(DEBUG) && defined(VERBOSE_DEBUG)
1022 netdev_vdbg(bp->dev,
1023 "start_xmit: len %u head %p data %p tail %p end %p\n",
1024 skb->len, skb->head, skb->data,
1025 skb_tail_pointer(skb), skb_end_pointer(skb));
1026 print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_OFFSET, 16, 1,
1027 skb->data, 16, true);
1031 spin_lock_irqsave(&bp->lock, flags);
1033 /* This is a hard error, log it. */
1034 if (CIRC_SPACE(bp->tx_head, bp->tx_tail, TX_RING_SIZE) < 1) {
1035 netif_stop_queue(dev);
1036 spin_unlock_irqrestore(&bp->lock, flags);
1037 netdev_err(bp->dev, "BUG! Tx Ring full when queue awake!\n");
1038 netdev_dbg(bp->dev, "tx_head = %u, tx_tail = %u\n",
1039 bp->tx_head, bp->tx_tail);
1040 return NETDEV_TX_BUSY;
1043 entry = macb_tx_ring_wrap(bp->tx_head);
1044 netdev_vdbg(bp->dev, "Allocated ring entry %u\n", entry);
1045 mapping = dma_map_single(&bp->pdev->dev, skb->data,
1046 len, DMA_TO_DEVICE);
1047 if (dma_mapping_error(&bp->pdev->dev, mapping)) {
1048 dev_kfree_skb_any(skb);
1053 tx_skb = &bp->tx_skb[entry];
1055 tx_skb->mapping = mapping;
1056 netdev_vdbg(bp->dev, "Mapped skb data %p to DMA addr %08lx\n",
1057 skb->data, (unsigned long)mapping);
1059 ctrl = MACB_BF(TX_FRMLEN, len);
1060 ctrl |= MACB_BIT(TX_LAST);
1061 if (entry == (TX_RING_SIZE - 1))
1062 ctrl |= MACB_BIT(TX_WRAP);
1064 desc = &bp->tx_ring[entry];
1065 desc->addr = mapping;
1068 /* Make newly initialized descriptor visible to hardware */
1071 skb_tx_timestamp(skb);
1073 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(TSTART));
1075 if (CIRC_SPACE(bp->tx_head, bp->tx_tail, TX_RING_SIZE) < 1)
1076 netif_stop_queue(dev);
1079 spin_unlock_irqrestore(&bp->lock, flags);
1081 return NETDEV_TX_OK;
1084 static void macb_init_rx_buffer_size(struct macb *bp, size_t size)
1086 if (!macb_is_gem(bp)) {
1087 bp->rx_buffer_size = MACB_RX_BUFFER_SIZE;
1089 bp->rx_buffer_size = size;
1091 if (bp->rx_buffer_size % RX_BUFFER_MULTIPLE) {
1093 "RX buffer must be multiple of %d bytes, expanding\n",
1094 RX_BUFFER_MULTIPLE);
1095 bp->rx_buffer_size =
1096 roundup(bp->rx_buffer_size, RX_BUFFER_MULTIPLE);
1100 netdev_dbg(bp->dev, "mtu [%u] rx_buffer_size [%Zu]\n",
1101 bp->dev->mtu, bp->rx_buffer_size);
1104 static void gem_free_rx_buffers(struct macb *bp)
1106 struct sk_buff *skb;
1107 struct macb_dma_desc *desc;
1114 for (i = 0; i < RX_RING_SIZE; i++) {
1115 skb = bp->rx_skbuff[i];
1120 desc = &bp->rx_ring[i];
1121 addr = MACB_BF(RX_WADDR, MACB_BFEXT(RX_WADDR, desc->addr));
1122 dma_unmap_single(&bp->pdev->dev, addr, skb->len,
1124 dev_kfree_skb_any(skb);
1128 kfree(bp->rx_skbuff);
1129 bp->rx_skbuff = NULL;
1132 static void macb_free_rx_buffers(struct macb *bp)
1134 if (bp->rx_buffers) {
1135 dma_free_coherent(&bp->pdev->dev,
1136 RX_RING_SIZE * bp->rx_buffer_size,
1137 bp->rx_buffers, bp->rx_buffers_dma);
1138 bp->rx_buffers = NULL;
1142 static void macb_free_consistent(struct macb *bp)
1148 bp->macbgem_ops.mog_free_rx_buffers(bp);
1150 dma_free_coherent(&bp->pdev->dev, RX_RING_BYTES,
1151 bp->rx_ring, bp->rx_ring_dma);
1155 dma_free_coherent(&bp->pdev->dev, TX_RING_BYTES,
1156 bp->tx_ring, bp->tx_ring_dma);
1161 static int gem_alloc_rx_buffers(struct macb *bp)
1165 size = RX_RING_SIZE * sizeof(struct sk_buff *);
1166 bp->rx_skbuff = kzalloc(size, GFP_KERNEL);
1171 "Allocated %d RX struct sk_buff entries at %p\n",
1172 RX_RING_SIZE, bp->rx_skbuff);
1176 static int macb_alloc_rx_buffers(struct macb *bp)
1180 size = RX_RING_SIZE * bp->rx_buffer_size;
1181 bp->rx_buffers = dma_alloc_coherent(&bp->pdev->dev, size,
1182 &bp->rx_buffers_dma, GFP_KERNEL);
1183 if (!bp->rx_buffers)
1187 "Allocated RX buffers of %d bytes at %08lx (mapped %p)\n",
1188 size, (unsigned long)bp->rx_buffers_dma, bp->rx_buffers);
1192 static int macb_alloc_consistent(struct macb *bp)
1196 size = TX_RING_SIZE * sizeof(struct macb_tx_skb);
1197 bp->tx_skb = kmalloc(size, GFP_KERNEL);
1201 size = RX_RING_BYTES;
1202 bp->rx_ring = dma_alloc_coherent(&bp->pdev->dev, size,
1203 &bp->rx_ring_dma, GFP_KERNEL);
1207 "Allocated RX ring of %d bytes at %08lx (mapped %p)\n",
1208 size, (unsigned long)bp->rx_ring_dma, bp->rx_ring);
1210 size = TX_RING_BYTES;
1211 bp->tx_ring = dma_alloc_coherent(&bp->pdev->dev, size,
1212 &bp->tx_ring_dma, GFP_KERNEL);
1216 "Allocated TX ring of %d bytes at %08lx (mapped %p)\n",
1217 size, (unsigned long)bp->tx_ring_dma, bp->tx_ring);
1219 if (bp->macbgem_ops.mog_alloc_rx_buffers(bp))
1225 macb_free_consistent(bp);
1229 static void gem_init_rings(struct macb *bp)
1233 for (i = 0; i < TX_RING_SIZE; i++) {
1234 bp->tx_ring[i].addr = 0;
1235 bp->tx_ring[i].ctrl = MACB_BIT(TX_USED);
1237 bp->tx_ring[TX_RING_SIZE - 1].ctrl |= MACB_BIT(TX_WRAP);
1239 bp->rx_tail = bp->rx_prepared_head = bp->tx_head = bp->tx_tail = 0;
1244 static void macb_init_rings(struct macb *bp)
1249 addr = bp->rx_buffers_dma;
1250 for (i = 0; i < RX_RING_SIZE; i++) {
1251 bp->rx_ring[i].addr = addr;
1252 bp->rx_ring[i].ctrl = 0;
1253 addr += bp->rx_buffer_size;
1255 bp->rx_ring[RX_RING_SIZE - 1].addr |= MACB_BIT(RX_WRAP);
1257 for (i = 0; i < TX_RING_SIZE; i++) {
1258 bp->tx_ring[i].addr = 0;
1259 bp->tx_ring[i].ctrl = MACB_BIT(TX_USED);
1261 bp->tx_ring[TX_RING_SIZE - 1].ctrl |= MACB_BIT(TX_WRAP);
1263 bp->rx_tail = bp->tx_head = bp->tx_tail = 0;
1266 static void macb_reset_hw(struct macb *bp)
1269 * Disable RX and TX (XXX: Should we halt the transmission
1272 macb_writel(bp, NCR, 0);
1274 /* Clear the stats registers (XXX: Update stats first?) */
1275 macb_writel(bp, NCR, MACB_BIT(CLRSTAT));
1277 /* Clear all status flags */
1278 macb_writel(bp, TSR, -1);
1279 macb_writel(bp, RSR, -1);
1281 /* Disable all interrupts */
1282 macb_writel(bp, IDR, -1);
1283 macb_readl(bp, ISR);
1286 static u32 gem_mdc_clk_div(struct macb *bp)
1289 unsigned long pclk_hz = clk_get_rate(bp->pclk);
1291 if (pclk_hz <= 20000000)
1292 config = GEM_BF(CLK, GEM_CLK_DIV8);
1293 else if (pclk_hz <= 40000000)
1294 config = GEM_BF(CLK, GEM_CLK_DIV16);
1295 else if (pclk_hz <= 80000000)
1296 config = GEM_BF(CLK, GEM_CLK_DIV32);
1297 else if (pclk_hz <= 120000000)
1298 config = GEM_BF(CLK, GEM_CLK_DIV48);
1299 else if (pclk_hz <= 160000000)
1300 config = GEM_BF(CLK, GEM_CLK_DIV64);
1302 config = GEM_BF(CLK, GEM_CLK_DIV96);
1307 static u32 macb_mdc_clk_div(struct macb *bp)
1310 unsigned long pclk_hz;
1312 if (macb_is_gem(bp))
1313 return gem_mdc_clk_div(bp);
1315 pclk_hz = clk_get_rate(bp->pclk);
1316 if (pclk_hz <= 20000000)
1317 config = MACB_BF(CLK, MACB_CLK_DIV8);
1318 else if (pclk_hz <= 40000000)
1319 config = MACB_BF(CLK, MACB_CLK_DIV16);
1320 else if (pclk_hz <= 80000000)
1321 config = MACB_BF(CLK, MACB_CLK_DIV32);
1323 config = MACB_BF(CLK, MACB_CLK_DIV64);
1329 * Get the DMA bus width field of the network configuration register that we
1330 * should program. We find the width from decoding the design configuration
1331 * register to find the maximum supported data bus width.
1333 static u32 macb_dbw(struct macb *bp)
1335 if (!macb_is_gem(bp))
1338 switch (GEM_BFEXT(DBWDEF, gem_readl(bp, DCFG1))) {
1340 return GEM_BF(DBW, GEM_DBW128);
1342 return GEM_BF(DBW, GEM_DBW64);
1345 return GEM_BF(DBW, GEM_DBW32);
1350 * Configure the receive DMA engine
1351 * - use the correct receive buffer size
1352 * - set the possibility to use INCR16 bursts
1353 * (if not supported by FIFO, it will fallback to default)
1354 * - set both rx/tx packet buffers to full memory size
1355 * These are configurable parameters for GEM.
1357 static void macb_configure_dma(struct macb *bp)
1361 if (macb_is_gem(bp)) {
1362 dmacfg = gem_readl(bp, DMACFG) & ~GEM_BF(RXBS, -1L);
1363 dmacfg |= GEM_BF(RXBS, bp->rx_buffer_size / RX_BUFFER_MULTIPLE);
1364 dmacfg |= GEM_BF(FBLDO, 16);
1365 dmacfg |= GEM_BIT(TXPBMS) | GEM_BF(RXBMS, -1L);
1366 dmacfg &= ~GEM_BIT(ENDIA);
1367 gem_writel(bp, DMACFG, dmacfg);
1372 * Configure peripheral capacities according to integration options used
1374 static void macb_configure_caps(struct macb *bp)
1376 if (macb_is_gem(bp)) {
1377 if (GEM_BFEXT(IRQCOR, gem_readl(bp, DCFG1)) == 0)
1378 bp->caps |= MACB_CAPS_ISR_CLEAR_ON_WRITE;
1382 static void macb_init_hw(struct macb *bp)
1387 macb_set_hwaddr(bp);
1389 config = macb_mdc_clk_div(bp);
1390 config |= MACB_BF(RBOF, NET_IP_ALIGN); /* Make eth data aligned */
1391 config |= MACB_BIT(PAE); /* PAuse Enable */
1392 config |= MACB_BIT(DRFCS); /* Discard Rx FCS */
1393 config |= MACB_BIT(BIG); /* Receive oversized frames */
1394 if (bp->dev->flags & IFF_PROMISC)
1395 config |= MACB_BIT(CAF); /* Copy All Frames */
1396 if (!(bp->dev->flags & IFF_BROADCAST))
1397 config |= MACB_BIT(NBC); /* No BroadCast */
1398 config |= macb_dbw(bp);
1399 macb_writel(bp, NCFGR, config);
1400 bp->speed = SPEED_10;
1401 bp->duplex = DUPLEX_HALF;
1403 macb_configure_dma(bp);
1404 macb_configure_caps(bp);
1406 /* Initialize TX and RX buffers */
1407 macb_writel(bp, RBQP, bp->rx_ring_dma);
1408 macb_writel(bp, TBQP, bp->tx_ring_dma);
1410 /* Enable TX and RX */
1411 macb_writel(bp, NCR, MACB_BIT(RE) | MACB_BIT(TE) | MACB_BIT(MPE));
1413 /* Enable interrupts */
1414 macb_writel(bp, IER, (MACB_RX_INT_FLAGS
1416 | MACB_BIT(HRESP)));
1421 * The hash address register is 64 bits long and takes up two
1422 * locations in the memory map. The least significant bits are stored
1423 * in EMAC_HSL and the most significant bits in EMAC_HSH.
1425 * The unicast hash enable and the multicast hash enable bits in the
1426 * network configuration register enable the reception of hash matched
1427 * frames. The destination address is reduced to a 6 bit index into
1428 * the 64 bit hash register using the following hash function. The
1429 * hash function is an exclusive or of every sixth bit of the
1430 * destination address.
1432 * hi[5] = da[5] ^ da[11] ^ da[17] ^ da[23] ^ da[29] ^ da[35] ^ da[41] ^ da[47]
1433 * hi[4] = da[4] ^ da[10] ^ da[16] ^ da[22] ^ da[28] ^ da[34] ^ da[40] ^ da[46]
1434 * hi[3] = da[3] ^ da[09] ^ da[15] ^ da[21] ^ da[27] ^ da[33] ^ da[39] ^ da[45]
1435 * hi[2] = da[2] ^ da[08] ^ da[14] ^ da[20] ^ da[26] ^ da[32] ^ da[38] ^ da[44]
1436 * hi[1] = da[1] ^ da[07] ^ da[13] ^ da[19] ^ da[25] ^ da[31] ^ da[37] ^ da[43]
1437 * hi[0] = da[0] ^ da[06] ^ da[12] ^ da[18] ^ da[24] ^ da[30] ^ da[36] ^ da[42]
1439 * da[0] represents the least significant bit of the first byte
1440 * received, that is, the multicast/unicast indicator, and da[47]
1441 * represents the most significant bit of the last byte received. If
1442 * the hash index, hi[n], points to a bit that is set in the hash
1443 * register then the frame will be matched according to whether the
1444 * frame is multicast or unicast. A multicast match will be signalled
1445 * if the multicast hash enable bit is set, da[0] is 1 and the hash
1446 * index points to a bit set in the hash register. A unicast match
1447 * will be signalled if the unicast hash enable bit is set, da[0] is 0
1448 * and the hash index points to a bit set in the hash register. To
1449 * receive all multicast frames, the hash register should be set with
1450 * all ones and the multicast hash enable bit should be set in the
1451 * network configuration register.
1454 static inline int hash_bit_value(int bitnr, __u8 *addr)
1456 if (addr[bitnr / 8] & (1 << (bitnr % 8)))
1462 * Return the hash index value for the specified address.
1464 static int hash_get_index(__u8 *addr)
1469 for (j = 0; j < 6; j++) {
1470 for (i = 0, bitval = 0; i < 8; i++)
1471 bitval ^= hash_bit_value(i*6 + j, addr);
1473 hash_index |= (bitval << j);
1480 * Add multicast addresses to the internal multicast-hash table.
1482 static void macb_sethashtable(struct net_device *dev)
1484 struct netdev_hw_addr *ha;
1485 unsigned long mc_filter[2];
1487 struct macb *bp = netdev_priv(dev);
1489 mc_filter[0] = mc_filter[1] = 0;
1491 netdev_for_each_mc_addr(ha, dev) {
1492 bitnr = hash_get_index(ha->addr);
1493 mc_filter[bitnr >> 5] |= 1 << (bitnr & 31);
1496 macb_or_gem_writel(bp, HRB, mc_filter[0]);
1497 macb_or_gem_writel(bp, HRT, mc_filter[1]);
1501 * Enable/Disable promiscuous and multicast modes.
1503 void macb_set_rx_mode(struct net_device *dev)
1506 struct macb *bp = netdev_priv(dev);
1508 cfg = macb_readl(bp, NCFGR);
1510 if (dev->flags & IFF_PROMISC)
1511 /* Enable promiscuous mode */
1512 cfg |= MACB_BIT(CAF);
1513 else if (dev->flags & (~IFF_PROMISC))
1514 /* Disable promiscuous mode */
1515 cfg &= ~MACB_BIT(CAF);
1517 if (dev->flags & IFF_ALLMULTI) {
1518 /* Enable all multicast mode */
1519 macb_or_gem_writel(bp, HRB, -1);
1520 macb_or_gem_writel(bp, HRT, -1);
1521 cfg |= MACB_BIT(NCFGR_MTI);
1522 } else if (!netdev_mc_empty(dev)) {
1523 /* Enable specific multicasts */
1524 macb_sethashtable(dev);
1525 cfg |= MACB_BIT(NCFGR_MTI);
1526 } else if (dev->flags & (~IFF_ALLMULTI)) {
1527 /* Disable all multicast mode */
1528 macb_or_gem_writel(bp, HRB, 0);
1529 macb_or_gem_writel(bp, HRT, 0);
1530 cfg &= ~MACB_BIT(NCFGR_MTI);
1533 macb_writel(bp, NCFGR, cfg);
1535 EXPORT_SYMBOL_GPL(macb_set_rx_mode);
1537 static int macb_open(struct net_device *dev)
1539 struct macb *bp = netdev_priv(dev);
1540 size_t bufsz = dev->mtu + ETH_HLEN + ETH_FCS_LEN + NET_IP_ALIGN;
1543 netdev_dbg(bp->dev, "open\n");
1545 /* carrier starts down */
1546 netif_carrier_off(dev);
1548 /* if the phy is not yet register, retry later*/
1552 /* RX buffers initialization */
1553 macb_init_rx_buffer_size(bp, bufsz);
1555 err = macb_alloc_consistent(bp);
1557 netdev_err(dev, "Unable to allocate DMA memory (error %d)\n",
1562 napi_enable(&bp->napi);
1564 bp->macbgem_ops.mog_init_rings(bp);
1567 /* schedule a link state check */
1568 phy_start(bp->phy_dev);
1570 netif_start_queue(dev);
1575 static int macb_close(struct net_device *dev)
1577 struct macb *bp = netdev_priv(dev);
1578 unsigned long flags;
1580 netif_stop_queue(dev);
1581 napi_disable(&bp->napi);
1584 phy_stop(bp->phy_dev);
1586 spin_lock_irqsave(&bp->lock, flags);
1588 netif_carrier_off(dev);
1589 spin_unlock_irqrestore(&bp->lock, flags);
1591 macb_free_consistent(bp);
1596 static void gem_update_stats(struct macb *bp)
1598 u32 __iomem *reg = bp->regs + GEM_OTX;
1599 u32 *p = &bp->hw_stats.gem.tx_octets_31_0;
1600 u32 *end = &bp->hw_stats.gem.rx_udp_checksum_errors + 1;
1602 for (; p < end; p++, reg++)
1603 *p += __raw_readl(reg);
1606 static struct net_device_stats *gem_get_stats(struct macb *bp)
1608 struct gem_stats *hwstat = &bp->hw_stats.gem;
1609 struct net_device_stats *nstat = &bp->stats;
1611 gem_update_stats(bp);
1613 nstat->rx_errors = (hwstat->rx_frame_check_sequence_errors +
1614 hwstat->rx_alignment_errors +
1615 hwstat->rx_resource_errors +
1616 hwstat->rx_overruns +
1617 hwstat->rx_oversize_frames +
1618 hwstat->rx_jabbers +
1619 hwstat->rx_undersized_frames +
1620 hwstat->rx_length_field_frame_errors);
1621 nstat->tx_errors = (hwstat->tx_late_collisions +
1622 hwstat->tx_excessive_collisions +
1623 hwstat->tx_underrun +
1624 hwstat->tx_carrier_sense_errors);
1625 nstat->multicast = hwstat->rx_multicast_frames;
1626 nstat->collisions = (hwstat->tx_single_collision_frames +
1627 hwstat->tx_multiple_collision_frames +
1628 hwstat->tx_excessive_collisions);
1629 nstat->rx_length_errors = (hwstat->rx_oversize_frames +
1630 hwstat->rx_jabbers +
1631 hwstat->rx_undersized_frames +
1632 hwstat->rx_length_field_frame_errors);
1633 nstat->rx_over_errors = hwstat->rx_resource_errors;
1634 nstat->rx_crc_errors = hwstat->rx_frame_check_sequence_errors;
1635 nstat->rx_frame_errors = hwstat->rx_alignment_errors;
1636 nstat->rx_fifo_errors = hwstat->rx_overruns;
1637 nstat->tx_aborted_errors = hwstat->tx_excessive_collisions;
1638 nstat->tx_carrier_errors = hwstat->tx_carrier_sense_errors;
1639 nstat->tx_fifo_errors = hwstat->tx_underrun;
1644 struct net_device_stats *macb_get_stats(struct net_device *dev)
1646 struct macb *bp = netdev_priv(dev);
1647 struct net_device_stats *nstat = &bp->stats;
1648 struct macb_stats *hwstat = &bp->hw_stats.macb;
1650 if (macb_is_gem(bp))
1651 return gem_get_stats(bp);
1653 /* read stats from hardware */
1654 macb_update_stats(bp);
1656 /* Convert HW stats into netdevice stats */
1657 nstat->rx_errors = (hwstat->rx_fcs_errors +
1658 hwstat->rx_align_errors +
1659 hwstat->rx_resource_errors +
1660 hwstat->rx_overruns +
1661 hwstat->rx_oversize_pkts +
1662 hwstat->rx_jabbers +
1663 hwstat->rx_undersize_pkts +
1664 hwstat->sqe_test_errors +
1665 hwstat->rx_length_mismatch);
1666 nstat->tx_errors = (hwstat->tx_late_cols +
1667 hwstat->tx_excessive_cols +
1668 hwstat->tx_underruns +
1669 hwstat->tx_carrier_errors);
1670 nstat->collisions = (hwstat->tx_single_cols +
1671 hwstat->tx_multiple_cols +
1672 hwstat->tx_excessive_cols);
1673 nstat->rx_length_errors = (hwstat->rx_oversize_pkts +
1674 hwstat->rx_jabbers +
1675 hwstat->rx_undersize_pkts +
1676 hwstat->rx_length_mismatch);
1677 nstat->rx_over_errors = hwstat->rx_resource_errors +
1678 hwstat->rx_overruns;
1679 nstat->rx_crc_errors = hwstat->rx_fcs_errors;
1680 nstat->rx_frame_errors = hwstat->rx_align_errors;
1681 nstat->rx_fifo_errors = hwstat->rx_overruns;
1682 /* XXX: What does "missed" mean? */
1683 nstat->tx_aborted_errors = hwstat->tx_excessive_cols;
1684 nstat->tx_carrier_errors = hwstat->tx_carrier_errors;
1685 nstat->tx_fifo_errors = hwstat->tx_underruns;
1686 /* Don't know about heartbeat or window errors... */
1690 EXPORT_SYMBOL_GPL(macb_get_stats);
1692 static int macb_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1694 struct macb *bp = netdev_priv(dev);
1695 struct phy_device *phydev = bp->phy_dev;
1700 return phy_ethtool_gset(phydev, cmd);
1703 static int macb_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1705 struct macb *bp = netdev_priv(dev);
1706 struct phy_device *phydev = bp->phy_dev;
1711 return phy_ethtool_sset(phydev, cmd);
1714 static int macb_get_regs_len(struct net_device *netdev)
1716 return MACB_GREGS_NBR * sizeof(u32);
1719 static void macb_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1722 struct macb *bp = netdev_priv(dev);
1723 unsigned int tail, head;
1726 regs->version = (macb_readl(bp, MID) & ((1 << MACB_REV_SIZE) - 1))
1727 | MACB_GREGS_VERSION;
1729 tail = macb_tx_ring_wrap(bp->tx_tail);
1730 head = macb_tx_ring_wrap(bp->tx_head);
1732 regs_buff[0] = macb_readl(bp, NCR);
1733 regs_buff[1] = macb_or_gem_readl(bp, NCFGR);
1734 regs_buff[2] = macb_readl(bp, NSR);
1735 regs_buff[3] = macb_readl(bp, TSR);
1736 regs_buff[4] = macb_readl(bp, RBQP);
1737 regs_buff[5] = macb_readl(bp, TBQP);
1738 regs_buff[6] = macb_readl(bp, RSR);
1739 regs_buff[7] = macb_readl(bp, IMR);
1741 regs_buff[8] = tail;
1742 regs_buff[9] = head;
1743 regs_buff[10] = macb_tx_dma(bp, tail);
1744 regs_buff[11] = macb_tx_dma(bp, head);
1746 if (macb_is_gem(bp)) {
1747 regs_buff[12] = gem_readl(bp, USRIO);
1748 regs_buff[13] = gem_readl(bp, DMACFG);
1752 const struct ethtool_ops macb_ethtool_ops = {
1753 .get_settings = macb_get_settings,
1754 .set_settings = macb_set_settings,
1755 .get_regs_len = macb_get_regs_len,
1756 .get_regs = macb_get_regs,
1757 .get_link = ethtool_op_get_link,
1758 .get_ts_info = ethtool_op_get_ts_info,
1760 EXPORT_SYMBOL_GPL(macb_ethtool_ops);
1762 int macb_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1764 struct macb *bp = netdev_priv(dev);
1765 struct phy_device *phydev = bp->phy_dev;
1767 if (!netif_running(dev))
1773 return phy_mii_ioctl(phydev, rq, cmd);
1775 EXPORT_SYMBOL_GPL(macb_ioctl);
1777 static const struct net_device_ops macb_netdev_ops = {
1778 .ndo_open = macb_open,
1779 .ndo_stop = macb_close,
1780 .ndo_start_xmit = macb_start_xmit,
1781 .ndo_set_rx_mode = macb_set_rx_mode,
1782 .ndo_get_stats = macb_get_stats,
1783 .ndo_do_ioctl = macb_ioctl,
1784 .ndo_validate_addr = eth_validate_addr,
1785 .ndo_change_mtu = eth_change_mtu,
1786 .ndo_set_mac_address = eth_mac_addr,
1787 #ifdef CONFIG_NET_POLL_CONTROLLER
1788 .ndo_poll_controller = macb_poll_controller,
1792 #if defined(CONFIG_OF)
1793 static const struct of_device_id macb_dt_ids[] = {
1794 { .compatible = "cdns,at32ap7000-macb" },
1795 { .compatible = "cdns,at91sam9260-macb" },
1796 { .compatible = "cdns,macb" },
1797 { .compatible = "cdns,pc302-gem" },
1798 { .compatible = "cdns,gem" },
1801 MODULE_DEVICE_TABLE(of, macb_dt_ids);
1804 static int __init macb_probe(struct platform_device *pdev)
1806 struct macb_platform_data *pdata;
1807 struct resource *regs;
1808 struct net_device *dev;
1810 struct phy_device *phydev;
1813 struct pinctrl *pinctrl;
1816 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1818 dev_err(&pdev->dev, "no mmio resource defined\n");
1822 pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
1823 if (IS_ERR(pinctrl)) {
1824 err = PTR_ERR(pinctrl);
1825 if (err == -EPROBE_DEFER)
1828 dev_warn(&pdev->dev, "No pinctrl provided\n");
1832 dev = alloc_etherdev(sizeof(*bp));
1836 SET_NETDEV_DEV(dev, &pdev->dev);
1838 /* TODO: Actually, we have some interesting features... */
1841 bp = netdev_priv(dev);
1845 spin_lock_init(&bp->lock);
1846 INIT_WORK(&bp->tx_error_task, macb_tx_error_task);
1848 bp->pclk = devm_clk_get(&pdev->dev, "pclk");
1849 if (IS_ERR(bp->pclk)) {
1850 err = PTR_ERR(bp->pclk);
1851 dev_err(&pdev->dev, "failed to get macb_clk (%u)\n", err);
1852 goto err_out_free_dev;
1855 bp->hclk = devm_clk_get(&pdev->dev, "hclk");
1856 if (IS_ERR(bp->hclk)) {
1857 err = PTR_ERR(bp->hclk);
1858 dev_err(&pdev->dev, "failed to get hclk (%u)\n", err);
1859 goto err_out_free_dev;
1862 bp->tx_clk = devm_clk_get(&pdev->dev, "tx_clk");
1864 err = clk_prepare_enable(bp->pclk);
1866 dev_err(&pdev->dev, "failed to enable pclk (%u)\n", err);
1867 goto err_out_free_dev;
1870 err = clk_prepare_enable(bp->hclk);
1872 dev_err(&pdev->dev, "failed to enable hclk (%u)\n", err);
1873 goto err_out_disable_pclk;
1876 if (!IS_ERR(bp->tx_clk)) {
1877 err = clk_prepare_enable(bp->tx_clk);
1879 dev_err(&pdev->dev, "failed to enable tx_clk (%u)\n",
1881 goto err_out_disable_hclk;
1885 bp->regs = devm_ioremap(&pdev->dev, regs->start, resource_size(regs));
1887 dev_err(&pdev->dev, "failed to map registers, aborting.\n");
1889 goto err_out_disable_clocks;
1892 dev->irq = platform_get_irq(pdev, 0);
1893 err = devm_request_irq(&pdev->dev, dev->irq, macb_interrupt, 0,
1896 dev_err(&pdev->dev, "Unable to request IRQ %d (error %d)\n",
1898 goto err_out_disable_clocks;
1901 dev->netdev_ops = &macb_netdev_ops;
1902 netif_napi_add(dev, &bp->napi, macb_poll, 64);
1903 dev->ethtool_ops = &macb_ethtool_ops;
1905 dev->base_addr = regs->start;
1907 /* setup appropriated routines according to adapter type */
1908 if (macb_is_gem(bp)) {
1909 bp->macbgem_ops.mog_alloc_rx_buffers = gem_alloc_rx_buffers;
1910 bp->macbgem_ops.mog_free_rx_buffers = gem_free_rx_buffers;
1911 bp->macbgem_ops.mog_init_rings = gem_init_rings;
1912 bp->macbgem_ops.mog_rx = gem_rx;
1914 bp->macbgem_ops.mog_alloc_rx_buffers = macb_alloc_rx_buffers;
1915 bp->macbgem_ops.mog_free_rx_buffers = macb_free_rx_buffers;
1916 bp->macbgem_ops.mog_init_rings = macb_init_rings;
1917 bp->macbgem_ops.mog_rx = macb_rx;
1920 /* Set MII management clock divider */
1921 config = macb_mdc_clk_div(bp);
1922 config |= macb_dbw(bp);
1923 macb_writel(bp, NCFGR, config);
1925 mac = of_get_mac_address(pdev->dev.of_node);
1927 memcpy(bp->dev->dev_addr, mac, ETH_ALEN);
1929 macb_get_hwaddr(bp);
1931 err = of_get_phy_mode(pdev->dev.of_node);
1933 pdata = dev_get_platdata(&pdev->dev);
1934 if (pdata && pdata->is_rmii)
1935 bp->phy_interface = PHY_INTERFACE_MODE_RMII;
1937 bp->phy_interface = PHY_INTERFACE_MODE_MII;
1939 bp->phy_interface = err;
1942 if (bp->phy_interface == PHY_INTERFACE_MODE_RGMII)
1943 macb_or_gem_writel(bp, USRIO, GEM_BIT(RGMII));
1944 else if (bp->phy_interface == PHY_INTERFACE_MODE_RMII)
1945 #if defined(CONFIG_ARCH_AT91)
1946 macb_or_gem_writel(bp, USRIO, (MACB_BIT(RMII) |
1949 macb_or_gem_writel(bp, USRIO, 0);
1952 #if defined(CONFIG_ARCH_AT91)
1953 macb_or_gem_writel(bp, USRIO, MACB_BIT(CLKEN));
1955 macb_or_gem_writel(bp, USRIO, MACB_BIT(MII));
1958 err = register_netdev(dev);
1960 dev_err(&pdev->dev, "Cannot register net device, aborting.\n");
1961 goto err_out_disable_clocks;
1964 err = macb_mii_init(bp);
1966 goto err_out_unregister_netdev;
1968 platform_set_drvdata(pdev, dev);
1970 netif_carrier_off(dev);
1972 netdev_info(dev, "Cadence %s at 0x%08lx irq %d (%pM)\n",
1973 macb_is_gem(bp) ? "GEM" : "MACB", dev->base_addr,
1974 dev->irq, dev->dev_addr);
1976 phydev = bp->phy_dev;
1977 netdev_info(dev, "attached PHY driver [%s] (mii_bus:phy_addr=%s, irq=%d)\n",
1978 phydev->drv->name, dev_name(&phydev->dev), phydev->irq);
1982 err_out_unregister_netdev:
1983 unregister_netdev(dev);
1984 err_out_disable_clocks:
1985 if (!IS_ERR(bp->tx_clk))
1986 clk_disable_unprepare(bp->tx_clk);
1987 err_out_disable_hclk:
1988 clk_disable_unprepare(bp->hclk);
1989 err_out_disable_pclk:
1990 clk_disable_unprepare(bp->pclk);
1997 static int __exit macb_remove(struct platform_device *pdev)
1999 struct net_device *dev;
2002 dev = platform_get_drvdata(pdev);
2005 bp = netdev_priv(dev);
2007 phy_disconnect(bp->phy_dev);
2008 mdiobus_unregister(bp->mii_bus);
2009 kfree(bp->mii_bus->irq);
2010 mdiobus_free(bp->mii_bus);
2011 unregister_netdev(dev);
2012 if (!IS_ERR(bp->tx_clk))
2013 clk_disable_unprepare(bp->tx_clk);
2014 clk_disable_unprepare(bp->hclk);
2015 clk_disable_unprepare(bp->pclk);
2023 static int macb_suspend(struct device *dev)
2025 struct platform_device *pdev = to_platform_device(dev);
2026 struct net_device *netdev = platform_get_drvdata(pdev);
2027 struct macb *bp = netdev_priv(netdev);
2029 netif_carrier_off(netdev);
2030 netif_device_detach(netdev);
2032 if (!IS_ERR(bp->tx_clk))
2033 clk_disable_unprepare(bp->tx_clk);
2034 clk_disable_unprepare(bp->hclk);
2035 clk_disable_unprepare(bp->pclk);
2040 static int macb_resume(struct device *dev)
2042 struct platform_device *pdev = to_platform_device(dev);
2043 struct net_device *netdev = platform_get_drvdata(pdev);
2044 struct macb *bp = netdev_priv(netdev);
2046 clk_prepare_enable(bp->pclk);
2047 clk_prepare_enable(bp->hclk);
2048 if (!IS_ERR(bp->tx_clk))
2049 clk_prepare_enable(bp->tx_clk);
2051 netif_device_attach(netdev);
2057 static SIMPLE_DEV_PM_OPS(macb_pm_ops, macb_suspend, macb_resume);
2059 static struct platform_driver macb_driver = {
2060 .remove = __exit_p(macb_remove),
2063 .owner = THIS_MODULE,
2064 .of_match_table = of_match_ptr(macb_dt_ids),
2069 module_platform_driver_probe(macb_driver, macb_probe);
2071 MODULE_LICENSE("GPL");
2072 MODULE_DESCRIPTION("Cadence MACB/GEM Ethernet driver");
2073 MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
2074 MODULE_ALIAS("platform:macb");