2 * Linux network driver for Brocade Converged Network Adapter.
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License (GPL) Version 2 as
6 * published by the Free Software Foundation
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
11 * General Public License for more details.
14 * Copyright (c) 2005-2010 Brocade Communications Systems, Inc.
18 #include <linux/bitops.h>
19 #include <linux/netdevice.h>
20 #include <linux/skbuff.h>
21 #include <linux/etherdevice.h>
23 #include <linux/ethtool.h>
24 #include <linux/if_vlan.h>
25 #include <linux/if_ether.h>
27 #include <linux/prefetch.h>
28 #include <linux/module.h>
34 static DEFINE_MUTEX(bnad_fwimg_mutex);
39 static uint bnad_msix_disable;
40 module_param(bnad_msix_disable, uint, 0444);
41 MODULE_PARM_DESC(bnad_msix_disable, "Disable MSIX mode");
43 static uint bnad_ioc_auto_recover = 1;
44 module_param(bnad_ioc_auto_recover, uint, 0444);
45 MODULE_PARM_DESC(bnad_ioc_auto_recover, "Enable / Disable auto recovery");
47 static uint bna_debugfs_enable = 1;
48 module_param(bna_debugfs_enable, uint, S_IRUGO | S_IWUSR);
49 MODULE_PARM_DESC(bna_debugfs_enable, "Enables debugfs feature, default=1,"
50 " Range[false:0|true:1]");
55 u32 bnad_rxqs_per_cq = 2;
57 static struct mutex bnad_list_mutex;
58 static LIST_HEAD(bnad_list);
59 static const u8 bnad_bcast_addr[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
64 #define BNAD_TX_UNMAPQ_DEPTH (bnad->txq_depth * 2)
66 #define BNAD_RX_UNMAPQ_DEPTH (bnad->rxq_depth)
68 #define BNAD_GET_MBOX_IRQ(_bnad) \
69 (((_bnad)->cfg_flags & BNAD_CF_MSIX) ? \
70 ((_bnad)->msix_table[BNAD_MAILBOX_MSIX_INDEX].vector) : \
71 ((_bnad)->pcidev->irq))
73 #define BNAD_FILL_UNMAPQ_MEM_REQ(_res_info, _num, _depth) \
75 (_res_info)->res_type = BNA_RES_T_MEM; \
76 (_res_info)->res_u.mem_info.mem_type = BNA_MEM_T_KVA; \
77 (_res_info)->res_u.mem_info.num = (_num); \
78 (_res_info)->res_u.mem_info.len = \
79 sizeof(struct bnad_unmap_q) + \
80 (sizeof(struct bnad_skb_unmap) * ((_depth) - 1)); \
84 bnad_add_to_list(struct bnad *bnad)
86 mutex_lock(&bnad_list_mutex);
87 list_add_tail(&bnad->list_entry, &bnad_list);
89 mutex_unlock(&bnad_list_mutex);
93 bnad_remove_from_list(struct bnad *bnad)
95 mutex_lock(&bnad_list_mutex);
96 list_del(&bnad->list_entry);
97 mutex_unlock(&bnad_list_mutex);
101 * Reinitialize completions in CQ, once Rx is taken down
104 bnad_cq_cleanup(struct bnad *bnad, struct bna_ccb *ccb)
106 struct bna_cq_entry *cmpl, *next_cmpl;
107 unsigned int wi_range, wis = 0, ccb_prod = 0;
110 BNA_CQ_QPGE_PTR_GET(ccb_prod, ccb->sw_qpt, cmpl,
113 for (i = 0; i < ccb->q_depth; i++) {
115 if (likely(--wi_range))
116 next_cmpl = cmpl + 1;
118 BNA_QE_INDX_ADD(ccb_prod, wis, ccb->q_depth);
120 BNA_CQ_QPGE_PTR_GET(ccb_prod, ccb->sw_qpt,
121 next_cmpl, wi_range);
129 bnad_pci_unmap_skb(struct device *pdev, struct bnad_skb_unmap *array,
130 u32 index, u32 depth, struct sk_buff *skb, u32 frag)
133 array[index].skb = NULL;
135 dma_unmap_single(pdev, dma_unmap_addr(&array[index], dma_addr),
136 skb_headlen(skb), DMA_TO_DEVICE);
137 dma_unmap_addr_set(&array[index], dma_addr, 0);
138 BNA_QE_INDX_ADD(index, 1, depth);
140 for (j = 0; j < frag; j++) {
141 dma_unmap_page(pdev, dma_unmap_addr(&array[index], dma_addr),
142 skb_frag_size(&skb_shinfo(skb)->frags[j]),
144 dma_unmap_addr_set(&array[index], dma_addr, 0);
145 BNA_QE_INDX_ADD(index, 1, depth);
152 * Frees all pending Tx Bufs
153 * At this point no activity is expected on the Q,
154 * so DMA unmap & freeing is fine.
157 bnad_txq_cleanup(struct bnad *bnad,
161 struct bnad_unmap_q *unmap_q = tcb->unmap_q;
162 struct bnad_skb_unmap *unmap_array;
163 struct sk_buff *skb = NULL;
166 unmap_array = unmap_q->unmap_array;
168 for (q = 0; q < unmap_q->q_depth; q++) {
169 skb = unmap_array[q].skb;
174 unmap_cons = bnad_pci_unmap_skb(&bnad->pcidev->dev, unmap_array,
175 unmap_cons, unmap_q->q_depth, skb,
176 skb_shinfo(skb)->nr_frags);
178 dev_kfree_skb_any(skb);
182 /* Data Path Handlers */
185 * bnad_txcmpl_process : Frees the Tx bufs on Tx completion
186 * Can be called in a) Interrupt context
190 bnad_txcmpl_process(struct bnad *bnad,
193 u32 unmap_cons, sent_packets = 0, sent_bytes = 0;
194 u16 wis, updated_hw_cons;
195 struct bnad_unmap_q *unmap_q = tcb->unmap_q;
196 struct bnad_skb_unmap *unmap_array;
199 /* Just return if TX is stopped */
200 if (!test_bit(BNAD_TXQ_TX_STARTED, &tcb->flags))
203 updated_hw_cons = *(tcb->hw_consumer_index);
205 wis = BNA_Q_INDEX_CHANGE(tcb->consumer_index,
206 updated_hw_cons, tcb->q_depth);
208 BUG_ON(!(wis <= BNA_QE_IN_USE_CNT(tcb, tcb->q_depth)));
210 unmap_array = unmap_q->unmap_array;
211 unmap_cons = unmap_q->consumer_index;
213 prefetch(&unmap_array[unmap_cons + 1]);
215 skb = unmap_array[unmap_cons].skb;
218 sent_bytes += skb->len;
219 wis -= BNA_TXQ_WI_NEEDED(1 + skb_shinfo(skb)->nr_frags);
221 unmap_cons = bnad_pci_unmap_skb(&bnad->pcidev->dev, unmap_array,
222 unmap_cons, unmap_q->q_depth, skb,
223 skb_shinfo(skb)->nr_frags);
225 dev_kfree_skb_any(skb);
228 /* Update consumer pointers. */
229 tcb->consumer_index = updated_hw_cons;
230 unmap_q->consumer_index = unmap_cons;
232 tcb->txq->tx_packets += sent_packets;
233 tcb->txq->tx_bytes += sent_bytes;
239 bnad_tx_complete(struct bnad *bnad, struct bna_tcb *tcb)
241 struct net_device *netdev = bnad->netdev;
244 if (test_and_set_bit(BNAD_TXQ_FREE_SENT, &tcb->flags))
247 sent = bnad_txcmpl_process(bnad, tcb);
249 if (netif_queue_stopped(netdev) &&
250 netif_carrier_ok(netdev) &&
251 BNA_QE_FREE_CNT(tcb, tcb->q_depth) >=
252 BNAD_NETIF_WAKE_THRESHOLD) {
253 if (test_bit(BNAD_TXQ_TX_STARTED, &tcb->flags)) {
254 netif_wake_queue(netdev);
255 BNAD_UPDATE_CTR(bnad, netif_queue_wakeup);
260 if (likely(test_bit(BNAD_TXQ_TX_STARTED, &tcb->flags)))
261 bna_ib_ack(tcb->i_dbell, sent);
263 smp_mb__before_clear_bit();
264 clear_bit(BNAD_TXQ_FREE_SENT, &tcb->flags);
269 /* MSIX Tx Completion Handler */
271 bnad_msix_tx(int irq, void *data)
273 struct bna_tcb *tcb = (struct bna_tcb *)data;
274 struct bnad *bnad = tcb->bnad;
276 bnad_tx_complete(bnad, tcb);
282 bnad_rcb_cleanup(struct bnad *bnad, struct bna_rcb *rcb)
284 struct bnad_unmap_q *unmap_q = rcb->unmap_q;
286 rcb->producer_index = 0;
287 rcb->consumer_index = 0;
289 unmap_q->producer_index = 0;
290 unmap_q->consumer_index = 0;
294 bnad_rxq_cleanup(struct bnad *bnad, struct bna_rcb *rcb)
296 struct bnad_unmap_q *unmap_q;
297 struct bnad_skb_unmap *unmap_array;
301 unmap_q = rcb->unmap_q;
302 unmap_array = unmap_q->unmap_array;
303 for (unmap_cons = 0; unmap_cons < unmap_q->q_depth; unmap_cons++) {
304 skb = unmap_array[unmap_cons].skb;
307 unmap_array[unmap_cons].skb = NULL;
308 dma_unmap_single(&bnad->pcidev->dev,
309 dma_unmap_addr(&unmap_array[unmap_cons],
311 rcb->rxq->buffer_size,
315 bnad_rcb_cleanup(bnad, rcb);
319 bnad_rxq_post(struct bnad *bnad, struct bna_rcb *rcb)
321 u16 to_alloc, alloced, unmap_prod, wi_range;
322 struct bnad_unmap_q *unmap_q = rcb->unmap_q;
323 struct bnad_skb_unmap *unmap_array;
324 struct bna_rxq_entry *rxent;
330 BNA_QE_FREE_CNT(unmap_q, unmap_q->q_depth);
332 unmap_array = unmap_q->unmap_array;
333 unmap_prod = unmap_q->producer_index;
335 BNA_RXQ_QPGE_PTR_GET(unmap_prod, rcb->sw_qpt, rxent, wi_range);
339 BNA_RXQ_QPGE_PTR_GET(unmap_prod, rcb->sw_qpt, rxent,
341 skb = netdev_alloc_skb_ip_align(bnad->netdev,
342 rcb->rxq->buffer_size);
343 if (unlikely(!skb)) {
344 BNAD_UPDATE_CTR(bnad, rxbuf_alloc_failed);
345 rcb->rxq->rxbuf_alloc_failed++;
348 unmap_array[unmap_prod].skb = skb;
349 dma_addr = dma_map_single(&bnad->pcidev->dev, skb->data,
350 rcb->rxq->buffer_size,
352 dma_unmap_addr_set(&unmap_array[unmap_prod], dma_addr,
354 BNA_SET_DMA_ADDR(dma_addr, &rxent->host_addr);
355 BNA_QE_INDX_ADD(unmap_prod, 1, unmap_q->q_depth);
363 if (likely(alloced)) {
364 unmap_q->producer_index = unmap_prod;
365 rcb->producer_index = unmap_prod;
367 if (likely(test_bit(BNAD_RXQ_POST_OK, &rcb->flags)))
368 bna_rxq_prod_indx_doorbell(rcb);
373 bnad_refill_rxq(struct bnad *bnad, struct bna_rcb *rcb)
375 struct bnad_unmap_q *unmap_q = rcb->unmap_q;
377 if (!test_and_set_bit(BNAD_RXQ_REFILL, &rcb->flags)) {
378 if (BNA_QE_FREE_CNT(unmap_q, unmap_q->q_depth)
379 >> BNAD_RXQ_REFILL_THRESHOLD_SHIFT)
380 bnad_rxq_post(bnad, rcb);
381 smp_mb__before_clear_bit();
382 clear_bit(BNAD_RXQ_REFILL, &rcb->flags);
387 bnad_cq_process(struct bnad *bnad, struct bna_ccb *ccb, int budget)
389 struct bna_cq_entry *cmpl, *next_cmpl;
390 struct bna_rcb *rcb = NULL;
391 unsigned int wi_range, packets = 0, wis = 0;
392 struct bnad_unmap_q *unmap_q;
393 struct bnad_skb_unmap *unmap_array;
395 u32 flags, unmap_cons;
396 struct bna_pkt_rate *pkt_rt = &ccb->pkt_rate;
397 struct bnad_rx_ctrl *rx_ctrl = (struct bnad_rx_ctrl *)(ccb->ctrl);
399 if (!test_bit(BNAD_RXQ_STARTED, &ccb->rcb[0]->flags))
402 prefetch(bnad->netdev);
403 BNA_CQ_QPGE_PTR_GET(ccb->producer_index, ccb->sw_qpt, cmpl,
405 BUG_ON(!(wi_range <= ccb->q_depth));
406 while (cmpl->valid && packets < budget) {
408 BNA_UPDATE_PKT_CNT(pkt_rt, ntohs(cmpl->length));
410 if (bna_is_small_rxq(cmpl->rxq_id))
415 unmap_q = rcb->unmap_q;
416 unmap_array = unmap_q->unmap_array;
417 unmap_cons = unmap_q->consumer_index;
419 skb = unmap_array[unmap_cons].skb;
421 unmap_array[unmap_cons].skb = NULL;
422 dma_unmap_single(&bnad->pcidev->dev,
423 dma_unmap_addr(&unmap_array[unmap_cons],
425 rcb->rxq->buffer_size,
427 BNA_QE_INDX_ADD(unmap_q->consumer_index, 1, unmap_q->q_depth);
429 /* Should be more efficient ? Performance ? */
430 BNA_QE_INDX_ADD(rcb->consumer_index, 1, rcb->q_depth);
433 if (likely(--wi_range))
434 next_cmpl = cmpl + 1;
436 BNA_QE_INDX_ADD(ccb->producer_index, wis, ccb->q_depth);
438 BNA_CQ_QPGE_PTR_GET(ccb->producer_index, ccb->sw_qpt,
439 next_cmpl, wi_range);
440 BUG_ON(!(wi_range <= ccb->q_depth));
444 flags = ntohl(cmpl->flags);
447 (BNA_CQ_EF_MAC_ERROR | BNA_CQ_EF_FCS_ERROR |
448 BNA_CQ_EF_TOO_LONG))) {
449 dev_kfree_skb_any(skb);
450 rcb->rxq->rx_packets_with_error++;
454 skb_put(skb, ntohs(cmpl->length));
456 ((bnad->netdev->features & NETIF_F_RXCSUM) &&
457 (((flags & BNA_CQ_EF_IPV4) &&
458 (flags & BNA_CQ_EF_L3_CKSUM_OK)) ||
459 (flags & BNA_CQ_EF_IPV6)) &&
460 (flags & (BNA_CQ_EF_TCP | BNA_CQ_EF_UDP)) &&
461 (flags & BNA_CQ_EF_L4_CKSUM_OK)))
462 skb->ip_summed = CHECKSUM_UNNECESSARY;
464 skb_checksum_none_assert(skb);
466 rcb->rxq->rx_packets++;
467 rcb->rxq->rx_bytes += skb->len;
468 skb->protocol = eth_type_trans(skb, bnad->netdev);
470 if (flags & BNA_CQ_EF_VLAN)
471 __vlan_hwaccel_put_tag(skb, ntohs(cmpl->vlan_tag));
473 if (skb->ip_summed == CHECKSUM_UNNECESSARY)
474 napi_gro_receive(&rx_ctrl->napi, skb);
476 netif_receive_skb(skb);
483 BNA_QE_INDX_ADD(ccb->producer_index, wis, ccb->q_depth);
485 if (likely(test_bit(BNAD_RXQ_STARTED, &ccb->rcb[0]->flags)))
486 bna_ib_ack_disable_irq(ccb->i_dbell, packets);
488 bnad_refill_rxq(bnad, ccb->rcb[0]);
490 bnad_refill_rxq(bnad, ccb->rcb[1]);
492 clear_bit(BNAD_FP_IN_RX_PATH, &rx_ctrl->flags);
498 bnad_netif_rx_schedule_poll(struct bnad *bnad, struct bna_ccb *ccb)
500 struct bnad_rx_ctrl *rx_ctrl = (struct bnad_rx_ctrl *)(ccb->ctrl);
501 struct napi_struct *napi = &rx_ctrl->napi;
503 if (likely(napi_schedule_prep(napi))) {
504 __napi_schedule(napi);
505 rx_ctrl->rx_schedule++;
509 /* MSIX Rx Path Handler */
511 bnad_msix_rx(int irq, void *data)
513 struct bna_ccb *ccb = (struct bna_ccb *)data;
516 ((struct bnad_rx_ctrl *)(ccb->ctrl))->rx_intr_ctr++;
517 bnad_netif_rx_schedule_poll(ccb->bnad, ccb);
523 /* Interrupt handlers */
525 /* Mbox Interrupt Handlers */
527 bnad_msix_mbox_handler(int irq, void *data)
531 struct bnad *bnad = (struct bnad *)data;
533 spin_lock_irqsave(&bnad->bna_lock, flags);
534 if (unlikely(test_bit(BNAD_RF_MBOX_IRQ_DISABLED, &bnad->run_flags))) {
535 spin_unlock_irqrestore(&bnad->bna_lock, flags);
539 bna_intr_status_get(&bnad->bna, intr_status);
541 if (BNA_IS_MBOX_ERR_INTR(&bnad->bna, intr_status))
542 bna_mbox_handler(&bnad->bna, intr_status);
544 spin_unlock_irqrestore(&bnad->bna_lock, flags);
550 bnad_isr(int irq, void *data)
555 struct bnad *bnad = (struct bnad *)data;
556 struct bnad_rx_info *rx_info;
557 struct bnad_rx_ctrl *rx_ctrl;
558 struct bna_tcb *tcb = NULL;
560 spin_lock_irqsave(&bnad->bna_lock, flags);
561 if (unlikely(test_bit(BNAD_RF_MBOX_IRQ_DISABLED, &bnad->run_flags))) {
562 spin_unlock_irqrestore(&bnad->bna_lock, flags);
566 bna_intr_status_get(&bnad->bna, intr_status);
568 if (unlikely(!intr_status)) {
569 spin_unlock_irqrestore(&bnad->bna_lock, flags);
573 if (BNA_IS_MBOX_ERR_INTR(&bnad->bna, intr_status))
574 bna_mbox_handler(&bnad->bna, intr_status);
576 spin_unlock_irqrestore(&bnad->bna_lock, flags);
578 if (!BNA_IS_INTX_DATA_INTR(intr_status))
581 /* Process data interrupts */
583 for (i = 0; i < bnad->num_tx; i++) {
584 for (j = 0; j < bnad->num_txq_per_tx; j++) {
585 tcb = bnad->tx_info[i].tcb[j];
586 if (tcb && test_bit(BNAD_TXQ_TX_STARTED, &tcb->flags))
587 bnad_tx_complete(bnad, bnad->tx_info[i].tcb[j]);
591 for (i = 0; i < bnad->num_rx; i++) {
592 rx_info = &bnad->rx_info[i];
595 for (j = 0; j < bnad->num_rxp_per_rx; j++) {
596 rx_ctrl = &rx_info->rx_ctrl[j];
598 bnad_netif_rx_schedule_poll(bnad,
606 * Called in interrupt / callback context
607 * with bna_lock held, so cfg_flags access is OK
610 bnad_enable_mbox_irq(struct bnad *bnad)
612 clear_bit(BNAD_RF_MBOX_IRQ_DISABLED, &bnad->run_flags);
614 BNAD_UPDATE_CTR(bnad, mbox_intr_enabled);
618 * Called with bnad->bna_lock held b'cos of
619 * bnad->cfg_flags access.
622 bnad_disable_mbox_irq(struct bnad *bnad)
624 set_bit(BNAD_RF_MBOX_IRQ_DISABLED, &bnad->run_flags);
626 BNAD_UPDATE_CTR(bnad, mbox_intr_disabled);
630 bnad_set_netdev_perm_addr(struct bnad *bnad)
632 struct net_device *netdev = bnad->netdev;
634 memcpy(netdev->perm_addr, &bnad->perm_addr, netdev->addr_len);
635 if (is_zero_ether_addr(netdev->dev_addr))
636 memcpy(netdev->dev_addr, &bnad->perm_addr, netdev->addr_len);
639 /* Control Path Handlers */
643 bnad_cb_mbox_intr_enable(struct bnad *bnad)
645 bnad_enable_mbox_irq(bnad);
649 bnad_cb_mbox_intr_disable(struct bnad *bnad)
651 bnad_disable_mbox_irq(bnad);
655 bnad_cb_ioceth_ready(struct bnad *bnad)
657 bnad->bnad_completions.ioc_comp_status = BNA_CB_SUCCESS;
658 complete(&bnad->bnad_completions.ioc_comp);
662 bnad_cb_ioceth_failed(struct bnad *bnad)
664 bnad->bnad_completions.ioc_comp_status = BNA_CB_FAIL;
665 complete(&bnad->bnad_completions.ioc_comp);
669 bnad_cb_ioceth_disabled(struct bnad *bnad)
671 bnad->bnad_completions.ioc_comp_status = BNA_CB_SUCCESS;
672 complete(&bnad->bnad_completions.ioc_comp);
676 bnad_cb_enet_disabled(void *arg)
678 struct bnad *bnad = (struct bnad *)arg;
680 netif_carrier_off(bnad->netdev);
681 complete(&bnad->bnad_completions.enet_comp);
685 bnad_cb_ethport_link_status(struct bnad *bnad,
686 enum bna_link_status link_status)
688 bool link_up = false;
690 link_up = (link_status == BNA_LINK_UP) || (link_status == BNA_CEE_UP);
692 if (link_status == BNA_CEE_UP) {
693 if (!test_bit(BNAD_RF_CEE_RUNNING, &bnad->run_flags))
694 BNAD_UPDATE_CTR(bnad, cee_toggle);
695 set_bit(BNAD_RF_CEE_RUNNING, &bnad->run_flags);
697 if (test_bit(BNAD_RF_CEE_RUNNING, &bnad->run_flags))
698 BNAD_UPDATE_CTR(bnad, cee_toggle);
699 clear_bit(BNAD_RF_CEE_RUNNING, &bnad->run_flags);
703 if (!netif_carrier_ok(bnad->netdev)) {
705 printk(KERN_WARNING "bna: %s link up\n",
707 netif_carrier_on(bnad->netdev);
708 BNAD_UPDATE_CTR(bnad, link_toggle);
709 for (tx_id = 0; tx_id < bnad->num_tx; tx_id++) {
710 for (tcb_id = 0; tcb_id < bnad->num_txq_per_tx;
712 struct bna_tcb *tcb =
713 bnad->tx_info[tx_id].tcb[tcb_id];
720 if (test_bit(BNAD_TXQ_TX_STARTED,
724 * Transmit Schedule */
725 printk(KERN_INFO "bna: %s %d "
732 BNAD_UPDATE_CTR(bnad,
738 BNAD_UPDATE_CTR(bnad,
745 if (netif_carrier_ok(bnad->netdev)) {
746 printk(KERN_WARNING "bna: %s link down\n",
748 netif_carrier_off(bnad->netdev);
749 BNAD_UPDATE_CTR(bnad, link_toggle);
755 bnad_cb_tx_disabled(void *arg, struct bna_tx *tx)
757 struct bnad *bnad = (struct bnad *)arg;
759 complete(&bnad->bnad_completions.tx_comp);
763 bnad_cb_tcb_setup(struct bnad *bnad, struct bna_tcb *tcb)
765 struct bnad_tx_info *tx_info =
766 (struct bnad_tx_info *)tcb->txq->tx->priv;
767 struct bnad_unmap_q *unmap_q = tcb->unmap_q;
769 tx_info->tcb[tcb->id] = tcb;
770 unmap_q->producer_index = 0;
771 unmap_q->consumer_index = 0;
772 unmap_q->q_depth = BNAD_TX_UNMAPQ_DEPTH;
776 bnad_cb_tcb_destroy(struct bnad *bnad, struct bna_tcb *tcb)
778 struct bnad_tx_info *tx_info =
779 (struct bnad_tx_info *)tcb->txq->tx->priv;
781 tx_info->tcb[tcb->id] = NULL;
786 bnad_cb_rcb_setup(struct bnad *bnad, struct bna_rcb *rcb)
788 struct bnad_unmap_q *unmap_q = rcb->unmap_q;
790 unmap_q->producer_index = 0;
791 unmap_q->consumer_index = 0;
792 unmap_q->q_depth = BNAD_RX_UNMAPQ_DEPTH;
796 bnad_cb_ccb_setup(struct bnad *bnad, struct bna_ccb *ccb)
798 struct bnad_rx_info *rx_info =
799 (struct bnad_rx_info *)ccb->cq->rx->priv;
801 rx_info->rx_ctrl[ccb->id].ccb = ccb;
802 ccb->ctrl = &rx_info->rx_ctrl[ccb->id];
806 bnad_cb_ccb_destroy(struct bnad *bnad, struct bna_ccb *ccb)
808 struct bnad_rx_info *rx_info =
809 (struct bnad_rx_info *)ccb->cq->rx->priv;
811 rx_info->rx_ctrl[ccb->id].ccb = NULL;
815 bnad_cb_tx_stall(struct bnad *bnad, struct bna_tx *tx)
817 struct bnad_tx_info *tx_info =
818 (struct bnad_tx_info *)tx->priv;
823 for (i = 0; i < BNAD_MAX_TXQ_PER_TX; i++) {
824 tcb = tx_info->tcb[i];
828 clear_bit(BNAD_TXQ_TX_STARTED, &tcb->flags);
829 netif_stop_subqueue(bnad->netdev, txq_id);
830 printk(KERN_INFO "bna: %s %d TXQ_STOPPED\n",
831 bnad->netdev->name, txq_id);
836 bnad_cb_tx_resume(struct bnad *bnad, struct bna_tx *tx)
838 struct bnad_tx_info *tx_info = (struct bnad_tx_info *)tx->priv;
843 for (i = 0; i < BNAD_MAX_TXQ_PER_TX; i++) {
844 tcb = tx_info->tcb[i];
849 BUG_ON(test_bit(BNAD_TXQ_TX_STARTED, &tcb->flags));
850 set_bit(BNAD_TXQ_TX_STARTED, &tcb->flags);
851 BUG_ON(*(tcb->hw_consumer_index) != 0);
853 if (netif_carrier_ok(bnad->netdev)) {
854 printk(KERN_INFO "bna: %s %d TXQ_STARTED\n",
855 bnad->netdev->name, txq_id);
856 netif_wake_subqueue(bnad->netdev, txq_id);
857 BNAD_UPDATE_CTR(bnad, netif_queue_wakeup);
862 * Workaround for first ioceth enable failure & we
863 * get a 0 MAC address. We try to get the MAC address
866 if (is_zero_ether_addr(&bnad->perm_addr.mac[0])) {
867 bna_enet_perm_mac_get(&bnad->bna.enet, &bnad->perm_addr);
868 bnad_set_netdev_perm_addr(bnad);
873 * Free all TxQs buffers and then notify TX_E_CLEANUP_DONE to Tx fsm.
876 bnad_tx_cleanup(struct delayed_work *work)
878 struct bnad_tx_info *tx_info =
879 container_of(work, struct bnad_tx_info, tx_cleanup_work);
880 struct bnad *bnad = NULL;
881 struct bnad_unmap_q *unmap_q;
884 uint32_t i, pending = 0;
886 for (i = 0; i < BNAD_MAX_TXQ_PER_TX; i++) {
887 tcb = tx_info->tcb[i];
893 if (test_and_set_bit(BNAD_TXQ_FREE_SENT, &tcb->flags)) {
898 bnad_txq_cleanup(bnad, tcb);
900 unmap_q = tcb->unmap_q;
901 unmap_q->producer_index = 0;
902 unmap_q->consumer_index = 0;
904 smp_mb__before_clear_bit();
905 clear_bit(BNAD_TXQ_FREE_SENT, &tcb->flags);
909 queue_delayed_work(bnad->work_q, &tx_info->tx_cleanup_work,
910 msecs_to_jiffies(1));
914 spin_lock_irqsave(&bnad->bna_lock, flags);
915 bna_tx_cleanup_complete(tx_info->tx);
916 spin_unlock_irqrestore(&bnad->bna_lock, flags);
921 bnad_cb_tx_cleanup(struct bnad *bnad, struct bna_tx *tx)
923 struct bnad_tx_info *tx_info = (struct bnad_tx_info *)tx->priv;
927 for (i = 0; i < BNAD_MAX_TXQ_PER_TX; i++) {
928 tcb = tx_info->tcb[i];
933 queue_delayed_work(bnad->work_q, &tx_info->tx_cleanup_work, 0);
937 bnad_cb_rx_stall(struct bnad *bnad, struct bna_rx *rx)
939 struct bnad_rx_info *rx_info = (struct bnad_rx_info *)rx->priv;
941 struct bnad_rx_ctrl *rx_ctrl;
944 for (i = 0; i < BNAD_MAX_RXP_PER_RX; i++) {
945 rx_ctrl = &rx_info->rx_ctrl[i];
950 clear_bit(BNAD_RXQ_POST_OK, &ccb->rcb[0]->flags);
953 clear_bit(BNAD_RXQ_POST_OK, &ccb->rcb[1]->flags);
958 * Free all RxQs buffers and then notify RX_E_CLEANUP_DONE to Rx fsm.
961 bnad_rx_cleanup(void *work)
963 struct bnad_rx_info *rx_info =
964 container_of(work, struct bnad_rx_info, rx_cleanup_work);
965 struct bnad_rx_ctrl *rx_ctrl;
966 struct bnad *bnad = NULL;
970 for (i = 0; i < BNAD_MAX_RXP_PER_RX; i++) {
971 rx_ctrl = &rx_info->rx_ctrl[i];
976 bnad = rx_ctrl->ccb->bnad;
979 * Wait till the poll handler has exited
980 * and nothing can be scheduled anymore
982 napi_disable(&rx_ctrl->napi);
984 bnad_cq_cleanup(bnad, rx_ctrl->ccb);
985 bnad_rxq_cleanup(bnad, rx_ctrl->ccb->rcb[0]);
986 if (rx_ctrl->ccb->rcb[1])
987 bnad_rxq_cleanup(bnad, rx_ctrl->ccb->rcb[1]);
990 spin_lock_irqsave(&bnad->bna_lock, flags);
991 bna_rx_cleanup_complete(rx_info->rx);
992 spin_unlock_irqrestore(&bnad->bna_lock, flags);
996 bnad_cb_rx_cleanup(struct bnad *bnad, struct bna_rx *rx)
998 struct bnad_rx_info *rx_info = (struct bnad_rx_info *)rx->priv;
1000 struct bnad_rx_ctrl *rx_ctrl;
1003 for (i = 0; i < BNAD_MAX_RXP_PER_RX; i++) {
1004 rx_ctrl = &rx_info->rx_ctrl[i];
1009 clear_bit(BNAD_RXQ_STARTED, &ccb->rcb[0]->flags);
1012 clear_bit(BNAD_RXQ_STARTED, &ccb->rcb[1]->flags);
1015 queue_work(bnad->work_q, &rx_info->rx_cleanup_work);
1019 bnad_cb_rx_post(struct bnad *bnad, struct bna_rx *rx)
1021 struct bnad_rx_info *rx_info = (struct bnad_rx_info *)rx->priv;
1022 struct bna_ccb *ccb;
1023 struct bna_rcb *rcb;
1024 struct bnad_rx_ctrl *rx_ctrl;
1025 struct bnad_unmap_q *unmap_q;
1029 for (i = 0; i < BNAD_MAX_RXP_PER_RX; i++) {
1030 rx_ctrl = &rx_info->rx_ctrl[i];
1035 napi_enable(&rx_ctrl->napi);
1037 for (j = 0; j < BNAD_MAX_RXQ_PER_RXP; j++) {
1042 set_bit(BNAD_RXQ_STARTED, &rcb->flags);
1043 set_bit(BNAD_RXQ_POST_OK, &rcb->flags);
1044 unmap_q = rcb->unmap_q;
1046 /* Now allocate & post buffers for this RCB */
1047 /* !!Allocation in callback context */
1048 if (!test_and_set_bit(BNAD_RXQ_REFILL, &rcb->flags)) {
1049 if (BNA_QE_FREE_CNT(unmap_q, unmap_q->q_depth)
1050 >> BNAD_RXQ_REFILL_THRESHOLD_SHIFT)
1051 bnad_rxq_post(bnad, rcb);
1052 smp_mb__before_clear_bit();
1053 clear_bit(BNAD_RXQ_REFILL, &rcb->flags);
1060 bnad_cb_rx_disabled(void *arg, struct bna_rx *rx)
1062 struct bnad *bnad = (struct bnad *)arg;
1064 complete(&bnad->bnad_completions.rx_comp);
1068 bnad_cb_rx_mcast_add(struct bnad *bnad, struct bna_rx *rx)
1070 bnad->bnad_completions.mcast_comp_status = BNA_CB_SUCCESS;
1071 complete(&bnad->bnad_completions.mcast_comp);
1075 bnad_cb_stats_get(struct bnad *bnad, enum bna_cb_status status,
1076 struct bna_stats *stats)
1078 if (status == BNA_CB_SUCCESS)
1079 BNAD_UPDATE_CTR(bnad, hw_stats_updates);
1081 if (!netif_running(bnad->netdev) ||
1082 !test_bit(BNAD_RF_STATS_TIMER_RUNNING, &bnad->run_flags))
1085 mod_timer(&bnad->stats_timer,
1086 jiffies + msecs_to_jiffies(BNAD_STATS_TIMER_FREQ));
1090 bnad_cb_enet_mtu_set(struct bnad *bnad)
1092 bnad->bnad_completions.mtu_comp_status = BNA_CB_SUCCESS;
1093 complete(&bnad->bnad_completions.mtu_comp);
1097 bnad_cb_completion(void *arg, enum bfa_status status)
1099 struct bnad_iocmd_comp *iocmd_comp =
1100 (struct bnad_iocmd_comp *)arg;
1102 iocmd_comp->comp_status = (u32) status;
1103 complete(&iocmd_comp->comp);
1106 /* Resource allocation, free functions */
1109 bnad_mem_free(struct bnad *bnad,
1110 struct bna_mem_info *mem_info)
1115 if (mem_info->mdl == NULL)
1118 for (i = 0; i < mem_info->num; i++) {
1119 if (mem_info->mdl[i].kva != NULL) {
1120 if (mem_info->mem_type == BNA_MEM_T_DMA) {
1121 BNA_GET_DMA_ADDR(&(mem_info->mdl[i].dma),
1123 dma_free_coherent(&bnad->pcidev->dev,
1124 mem_info->mdl[i].len,
1125 mem_info->mdl[i].kva, dma_pa);
1127 kfree(mem_info->mdl[i].kva);
1130 kfree(mem_info->mdl);
1131 mem_info->mdl = NULL;
1135 bnad_mem_alloc(struct bnad *bnad,
1136 struct bna_mem_info *mem_info)
1141 if ((mem_info->num == 0) || (mem_info->len == 0)) {
1142 mem_info->mdl = NULL;
1146 mem_info->mdl = kcalloc(mem_info->num, sizeof(struct bna_mem_descr),
1148 if (mem_info->mdl == NULL)
1151 if (mem_info->mem_type == BNA_MEM_T_DMA) {
1152 for (i = 0; i < mem_info->num; i++) {
1153 mem_info->mdl[i].len = mem_info->len;
1154 mem_info->mdl[i].kva =
1155 dma_alloc_coherent(&bnad->pcidev->dev,
1156 mem_info->len, &dma_pa,
1159 if (mem_info->mdl[i].kva == NULL)
1162 BNA_SET_DMA_ADDR(dma_pa,
1163 &(mem_info->mdl[i].dma));
1166 for (i = 0; i < mem_info->num; i++) {
1167 mem_info->mdl[i].len = mem_info->len;
1168 mem_info->mdl[i].kva = kzalloc(mem_info->len,
1170 if (mem_info->mdl[i].kva == NULL)
1178 bnad_mem_free(bnad, mem_info);
1182 /* Free IRQ for Mailbox */
1184 bnad_mbox_irq_free(struct bnad *bnad)
1187 unsigned long flags;
1189 spin_lock_irqsave(&bnad->bna_lock, flags);
1190 bnad_disable_mbox_irq(bnad);
1191 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1193 irq = BNAD_GET_MBOX_IRQ(bnad);
1194 free_irq(irq, bnad);
1198 * Allocates IRQ for Mailbox, but keep it disabled
1199 * This will be enabled once we get the mbox enable callback
1203 bnad_mbox_irq_alloc(struct bnad *bnad)
1206 unsigned long irq_flags, flags;
1208 irq_handler_t irq_handler;
1210 spin_lock_irqsave(&bnad->bna_lock, flags);
1211 if (bnad->cfg_flags & BNAD_CF_MSIX) {
1212 irq_handler = (irq_handler_t)bnad_msix_mbox_handler;
1213 irq = bnad->msix_table[BNAD_MAILBOX_MSIX_INDEX].vector;
1216 irq_handler = (irq_handler_t)bnad_isr;
1217 irq = bnad->pcidev->irq;
1218 irq_flags = IRQF_SHARED;
1221 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1222 sprintf(bnad->mbox_irq_name, "%s", BNAD_NAME);
1225 * Set the Mbox IRQ disable flag, so that the IRQ handler
1226 * called from request_irq() for SHARED IRQs do not execute
1228 set_bit(BNAD_RF_MBOX_IRQ_DISABLED, &bnad->run_flags);
1230 BNAD_UPDATE_CTR(bnad, mbox_intr_disabled);
1232 err = request_irq(irq, irq_handler, irq_flags,
1233 bnad->mbox_irq_name, bnad);
1239 bnad_txrx_irq_free(struct bnad *bnad, struct bna_intr_info *intr_info)
1241 kfree(intr_info->idl);
1242 intr_info->idl = NULL;
1245 /* Allocates Interrupt Descriptor List for MSIX/INT-X vectors */
1247 bnad_txrx_irq_alloc(struct bnad *bnad, enum bnad_intr_source src,
1248 u32 txrx_id, struct bna_intr_info *intr_info)
1250 int i, vector_start = 0;
1252 unsigned long flags;
1254 spin_lock_irqsave(&bnad->bna_lock, flags);
1255 cfg_flags = bnad->cfg_flags;
1256 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1258 if (cfg_flags & BNAD_CF_MSIX) {
1259 intr_info->intr_type = BNA_INTR_T_MSIX;
1260 intr_info->idl = kcalloc(intr_info->num,
1261 sizeof(struct bna_intr_descr),
1263 if (!intr_info->idl)
1268 vector_start = BNAD_MAILBOX_MSIX_VECTORS + txrx_id;
1272 vector_start = BNAD_MAILBOX_MSIX_VECTORS +
1273 (bnad->num_tx * bnad->num_txq_per_tx) +
1281 for (i = 0; i < intr_info->num; i++)
1282 intr_info->idl[i].vector = vector_start + i;
1284 intr_info->intr_type = BNA_INTR_T_INTX;
1286 intr_info->idl = kcalloc(intr_info->num,
1287 sizeof(struct bna_intr_descr),
1289 if (!intr_info->idl)
1294 intr_info->idl[0].vector = BNAD_INTX_TX_IB_BITMASK;
1298 intr_info->idl[0].vector = BNAD_INTX_RX_IB_BITMASK;
1306 * NOTE: Should be called for MSIX only
1307 * Unregisters Tx MSIX vector(s) from the kernel
1310 bnad_tx_msix_unregister(struct bnad *bnad, struct bnad_tx_info *tx_info,
1316 for (i = 0; i < num_txqs; i++) {
1317 if (tx_info->tcb[i] == NULL)
1320 vector_num = tx_info->tcb[i]->intr_vector;
1321 free_irq(bnad->msix_table[vector_num].vector, tx_info->tcb[i]);
1326 * NOTE: Should be called for MSIX only
1327 * Registers Tx MSIX vector(s) and ISR(s), cookie with the kernel
1330 bnad_tx_msix_register(struct bnad *bnad, struct bnad_tx_info *tx_info,
1331 u32 tx_id, int num_txqs)
1337 for (i = 0; i < num_txqs; i++) {
1338 vector_num = tx_info->tcb[i]->intr_vector;
1339 sprintf(tx_info->tcb[i]->name, "%s TXQ %d", bnad->netdev->name,
1340 tx_id + tx_info->tcb[i]->id);
1341 err = request_irq(bnad->msix_table[vector_num].vector,
1342 (irq_handler_t)bnad_msix_tx, 0,
1343 tx_info->tcb[i]->name,
1353 bnad_tx_msix_unregister(bnad, tx_info, (i - 1));
1358 * NOTE: Should be called for MSIX only
1359 * Unregisters Rx MSIX vector(s) from the kernel
1362 bnad_rx_msix_unregister(struct bnad *bnad, struct bnad_rx_info *rx_info,
1368 for (i = 0; i < num_rxps; i++) {
1369 if (rx_info->rx_ctrl[i].ccb == NULL)
1372 vector_num = rx_info->rx_ctrl[i].ccb->intr_vector;
1373 free_irq(bnad->msix_table[vector_num].vector,
1374 rx_info->rx_ctrl[i].ccb);
1379 * NOTE: Should be called for MSIX only
1380 * Registers Tx MSIX vector(s) and ISR(s), cookie with the kernel
1383 bnad_rx_msix_register(struct bnad *bnad, struct bnad_rx_info *rx_info,
1384 u32 rx_id, int num_rxps)
1390 for (i = 0; i < num_rxps; i++) {
1391 vector_num = rx_info->rx_ctrl[i].ccb->intr_vector;
1392 sprintf(rx_info->rx_ctrl[i].ccb->name, "%s CQ %d",
1394 rx_id + rx_info->rx_ctrl[i].ccb->id);
1395 err = request_irq(bnad->msix_table[vector_num].vector,
1396 (irq_handler_t)bnad_msix_rx, 0,
1397 rx_info->rx_ctrl[i].ccb->name,
1398 rx_info->rx_ctrl[i].ccb);
1407 bnad_rx_msix_unregister(bnad, rx_info, (i - 1));
1411 /* Free Tx object Resources */
1413 bnad_tx_res_free(struct bnad *bnad, struct bna_res_info *res_info)
1417 for (i = 0; i < BNA_TX_RES_T_MAX; i++) {
1418 if (res_info[i].res_type == BNA_RES_T_MEM)
1419 bnad_mem_free(bnad, &res_info[i].res_u.mem_info);
1420 else if (res_info[i].res_type == BNA_RES_T_INTR)
1421 bnad_txrx_irq_free(bnad, &res_info[i].res_u.intr_info);
1425 /* Allocates memory and interrupt resources for Tx object */
1427 bnad_tx_res_alloc(struct bnad *bnad, struct bna_res_info *res_info,
1432 for (i = 0; i < BNA_TX_RES_T_MAX; i++) {
1433 if (res_info[i].res_type == BNA_RES_T_MEM)
1434 err = bnad_mem_alloc(bnad,
1435 &res_info[i].res_u.mem_info);
1436 else if (res_info[i].res_type == BNA_RES_T_INTR)
1437 err = bnad_txrx_irq_alloc(bnad, BNAD_INTR_TX, tx_id,
1438 &res_info[i].res_u.intr_info);
1445 bnad_tx_res_free(bnad, res_info);
1449 /* Free Rx object Resources */
1451 bnad_rx_res_free(struct bnad *bnad, struct bna_res_info *res_info)
1455 for (i = 0; i < BNA_RX_RES_T_MAX; i++) {
1456 if (res_info[i].res_type == BNA_RES_T_MEM)
1457 bnad_mem_free(bnad, &res_info[i].res_u.mem_info);
1458 else if (res_info[i].res_type == BNA_RES_T_INTR)
1459 bnad_txrx_irq_free(bnad, &res_info[i].res_u.intr_info);
1463 /* Allocates memory and interrupt resources for Rx object */
1465 bnad_rx_res_alloc(struct bnad *bnad, struct bna_res_info *res_info,
1470 /* All memory needs to be allocated before setup_ccbs */
1471 for (i = 0; i < BNA_RX_RES_T_MAX; i++) {
1472 if (res_info[i].res_type == BNA_RES_T_MEM)
1473 err = bnad_mem_alloc(bnad,
1474 &res_info[i].res_u.mem_info);
1475 else if (res_info[i].res_type == BNA_RES_T_INTR)
1476 err = bnad_txrx_irq_alloc(bnad, BNAD_INTR_RX, rx_id,
1477 &res_info[i].res_u.intr_info);
1484 bnad_rx_res_free(bnad, res_info);
1488 /* Timer callbacks */
1491 bnad_ioc_timeout(unsigned long data)
1493 struct bnad *bnad = (struct bnad *)data;
1494 unsigned long flags;
1496 spin_lock_irqsave(&bnad->bna_lock, flags);
1497 bfa_nw_ioc_timeout((void *) &bnad->bna.ioceth.ioc);
1498 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1502 bnad_ioc_hb_check(unsigned long data)
1504 struct bnad *bnad = (struct bnad *)data;
1505 unsigned long flags;
1507 spin_lock_irqsave(&bnad->bna_lock, flags);
1508 bfa_nw_ioc_hb_check((void *) &bnad->bna.ioceth.ioc);
1509 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1513 bnad_iocpf_timeout(unsigned long data)
1515 struct bnad *bnad = (struct bnad *)data;
1516 unsigned long flags;
1518 spin_lock_irqsave(&bnad->bna_lock, flags);
1519 bfa_nw_iocpf_timeout((void *) &bnad->bna.ioceth.ioc);
1520 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1524 bnad_iocpf_sem_timeout(unsigned long data)
1526 struct bnad *bnad = (struct bnad *)data;
1527 unsigned long flags;
1529 spin_lock_irqsave(&bnad->bna_lock, flags);
1530 bfa_nw_iocpf_sem_timeout((void *) &bnad->bna.ioceth.ioc);
1531 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1535 * All timer routines use bnad->bna_lock to protect against
1536 * the following race, which may occur in case of no locking:
1544 /* b) Dynamic Interrupt Moderation Timer */
1546 bnad_dim_timeout(unsigned long data)
1548 struct bnad *bnad = (struct bnad *)data;
1549 struct bnad_rx_info *rx_info;
1550 struct bnad_rx_ctrl *rx_ctrl;
1552 unsigned long flags;
1554 if (!netif_carrier_ok(bnad->netdev))
1557 spin_lock_irqsave(&bnad->bna_lock, flags);
1558 for (i = 0; i < bnad->num_rx; i++) {
1559 rx_info = &bnad->rx_info[i];
1562 for (j = 0; j < bnad->num_rxp_per_rx; j++) {
1563 rx_ctrl = &rx_info->rx_ctrl[j];
1566 bna_rx_dim_update(rx_ctrl->ccb);
1570 /* Check for BNAD_CF_DIM_ENABLED, does not eleminate a race */
1571 if (test_bit(BNAD_RF_DIM_TIMER_RUNNING, &bnad->run_flags))
1572 mod_timer(&bnad->dim_timer,
1573 jiffies + msecs_to_jiffies(BNAD_DIM_TIMER_FREQ));
1574 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1577 /* c) Statistics Timer */
1579 bnad_stats_timeout(unsigned long data)
1581 struct bnad *bnad = (struct bnad *)data;
1582 unsigned long flags;
1584 if (!netif_running(bnad->netdev) ||
1585 !test_bit(BNAD_RF_STATS_TIMER_RUNNING, &bnad->run_flags))
1588 spin_lock_irqsave(&bnad->bna_lock, flags);
1589 bna_hw_stats_get(&bnad->bna);
1590 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1594 * Set up timer for DIM
1595 * Called with bnad->bna_lock held
1598 bnad_dim_timer_start(struct bnad *bnad)
1600 if (bnad->cfg_flags & BNAD_CF_DIM_ENABLED &&
1601 !test_bit(BNAD_RF_DIM_TIMER_RUNNING, &bnad->run_flags)) {
1602 setup_timer(&bnad->dim_timer, bnad_dim_timeout,
1603 (unsigned long)bnad);
1604 set_bit(BNAD_RF_DIM_TIMER_RUNNING, &bnad->run_flags);
1605 mod_timer(&bnad->dim_timer,
1606 jiffies + msecs_to_jiffies(BNAD_DIM_TIMER_FREQ));
1611 * Set up timer for statistics
1612 * Called with mutex_lock(&bnad->conf_mutex) held
1615 bnad_stats_timer_start(struct bnad *bnad)
1617 unsigned long flags;
1619 spin_lock_irqsave(&bnad->bna_lock, flags);
1620 if (!test_and_set_bit(BNAD_RF_STATS_TIMER_RUNNING, &bnad->run_flags)) {
1621 setup_timer(&bnad->stats_timer, bnad_stats_timeout,
1622 (unsigned long)bnad);
1623 mod_timer(&bnad->stats_timer,
1624 jiffies + msecs_to_jiffies(BNAD_STATS_TIMER_FREQ));
1626 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1630 * Stops the stats timer
1631 * Called with mutex_lock(&bnad->conf_mutex) held
1634 bnad_stats_timer_stop(struct bnad *bnad)
1637 unsigned long flags;
1639 spin_lock_irqsave(&bnad->bna_lock, flags);
1640 if (test_and_clear_bit(BNAD_RF_STATS_TIMER_RUNNING, &bnad->run_flags))
1642 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1644 del_timer_sync(&bnad->stats_timer);
1650 bnad_netdev_mc_list_get(struct net_device *netdev, u8 *mc_list)
1652 int i = 1; /* Index 0 has broadcast address */
1653 struct netdev_hw_addr *mc_addr;
1655 netdev_for_each_mc_addr(mc_addr, netdev) {
1656 memcpy(&mc_list[i * ETH_ALEN], &mc_addr->addr[0],
1663 bnad_napi_poll_rx(struct napi_struct *napi, int budget)
1665 struct bnad_rx_ctrl *rx_ctrl =
1666 container_of(napi, struct bnad_rx_ctrl, napi);
1667 struct bnad *bnad = rx_ctrl->bnad;
1670 rx_ctrl->rx_poll_ctr++;
1672 if (!netif_carrier_ok(bnad->netdev))
1675 rcvd = bnad_cq_process(bnad, rx_ctrl->ccb, budget);
1680 napi_complete(napi);
1682 rx_ctrl->rx_complete++;
1685 bnad_enable_rx_irq_unsafe(rx_ctrl->ccb);
1690 #define BNAD_NAPI_POLL_QUOTA 64
1692 bnad_napi_add(struct bnad *bnad, u32 rx_id)
1694 struct bnad_rx_ctrl *rx_ctrl;
1697 /* Initialize & enable NAPI */
1698 for (i = 0; i < bnad->num_rxp_per_rx; i++) {
1699 rx_ctrl = &bnad->rx_info[rx_id].rx_ctrl[i];
1700 netif_napi_add(bnad->netdev, &rx_ctrl->napi,
1701 bnad_napi_poll_rx, BNAD_NAPI_POLL_QUOTA);
1706 bnad_napi_delete(struct bnad *bnad, u32 rx_id)
1710 /* First disable and then clean up */
1711 for (i = 0; i < bnad->num_rxp_per_rx; i++)
1712 netif_napi_del(&bnad->rx_info[rx_id].rx_ctrl[i].napi);
1715 /* Should be held with conf_lock held */
1717 bnad_destroy_tx(struct bnad *bnad, u32 tx_id)
1719 struct bnad_tx_info *tx_info = &bnad->tx_info[tx_id];
1720 struct bna_res_info *res_info = &bnad->tx_res_info[tx_id].res_info[0];
1721 unsigned long flags;
1726 init_completion(&bnad->bnad_completions.tx_comp);
1727 spin_lock_irqsave(&bnad->bna_lock, flags);
1728 bna_tx_disable(tx_info->tx, BNA_HARD_CLEANUP, bnad_cb_tx_disabled);
1729 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1730 wait_for_completion(&bnad->bnad_completions.tx_comp);
1732 if (tx_info->tcb[0]->intr_type == BNA_INTR_T_MSIX)
1733 bnad_tx_msix_unregister(bnad, tx_info,
1734 bnad->num_txq_per_tx);
1736 spin_lock_irqsave(&bnad->bna_lock, flags);
1737 bna_tx_destroy(tx_info->tx);
1738 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1743 bnad_tx_res_free(bnad, res_info);
1746 /* Should be held with conf_lock held */
1748 bnad_setup_tx(struct bnad *bnad, u32 tx_id)
1751 struct bnad_tx_info *tx_info = &bnad->tx_info[tx_id];
1752 struct bna_res_info *res_info = &bnad->tx_res_info[tx_id].res_info[0];
1753 struct bna_intr_info *intr_info =
1754 &res_info[BNA_TX_RES_INTR_T_TXCMPL].res_u.intr_info;
1755 struct bna_tx_config *tx_config = &bnad->tx_config[tx_id];
1756 static const struct bna_tx_event_cbfn tx_cbfn = {
1757 .tcb_setup_cbfn = bnad_cb_tcb_setup,
1758 .tcb_destroy_cbfn = bnad_cb_tcb_destroy,
1759 .tx_stall_cbfn = bnad_cb_tx_stall,
1760 .tx_resume_cbfn = bnad_cb_tx_resume,
1761 .tx_cleanup_cbfn = bnad_cb_tx_cleanup,
1765 unsigned long flags;
1767 tx_info->tx_id = tx_id;
1769 /* Initialize the Tx object configuration */
1770 tx_config->num_txq = bnad->num_txq_per_tx;
1771 tx_config->txq_depth = bnad->txq_depth;
1772 tx_config->tx_type = BNA_TX_T_REGULAR;
1773 tx_config->coalescing_timeo = bnad->tx_coalescing_timeo;
1775 /* Get BNA's resource requirement for one tx object */
1776 spin_lock_irqsave(&bnad->bna_lock, flags);
1777 bna_tx_res_req(bnad->num_txq_per_tx,
1778 bnad->txq_depth, res_info);
1779 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1781 /* Fill Unmap Q memory requirements */
1782 BNAD_FILL_UNMAPQ_MEM_REQ(
1783 &res_info[BNA_TX_RES_MEM_T_UNMAPQ],
1784 bnad->num_txq_per_tx,
1785 BNAD_TX_UNMAPQ_DEPTH);
1787 /* Allocate resources */
1788 err = bnad_tx_res_alloc(bnad, res_info, tx_id);
1792 /* Ask BNA to create one Tx object, supplying required resources */
1793 spin_lock_irqsave(&bnad->bna_lock, flags);
1794 tx = bna_tx_create(&bnad->bna, bnad, tx_config, &tx_cbfn, res_info,
1796 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1801 INIT_DELAYED_WORK(&tx_info->tx_cleanup_work,
1802 (work_func_t)bnad_tx_cleanup);
1804 /* Register ISR for the Tx object */
1805 if (intr_info->intr_type == BNA_INTR_T_MSIX) {
1806 err = bnad_tx_msix_register(bnad, tx_info,
1807 tx_id, bnad->num_txq_per_tx);
1812 spin_lock_irqsave(&bnad->bna_lock, flags);
1814 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1819 bnad_tx_res_free(bnad, res_info);
1823 /* Setup the rx config for bna_rx_create */
1824 /* bnad decides the configuration */
1826 bnad_init_rx_config(struct bnad *bnad, struct bna_rx_config *rx_config)
1828 rx_config->rx_type = BNA_RX_T_REGULAR;
1829 rx_config->num_paths = bnad->num_rxp_per_rx;
1830 rx_config->coalescing_timeo = bnad->rx_coalescing_timeo;
1832 if (bnad->num_rxp_per_rx > 1) {
1833 rx_config->rss_status = BNA_STATUS_T_ENABLED;
1834 rx_config->rss_config.hash_type =
1835 (BFI_ENET_RSS_IPV6 |
1836 BFI_ENET_RSS_IPV6_TCP |
1838 BFI_ENET_RSS_IPV4_TCP);
1839 rx_config->rss_config.hash_mask =
1840 bnad->num_rxp_per_rx - 1;
1841 get_random_bytes(rx_config->rss_config.toeplitz_hash_key,
1842 sizeof(rx_config->rss_config.toeplitz_hash_key));
1844 rx_config->rss_status = BNA_STATUS_T_DISABLED;
1845 memset(&rx_config->rss_config, 0,
1846 sizeof(rx_config->rss_config));
1848 rx_config->rxp_type = BNA_RXP_SLR;
1849 rx_config->q_depth = bnad->rxq_depth;
1851 rx_config->small_buff_size = BFI_SMALL_RXBUF_SIZE;
1853 rx_config->vlan_strip_status = BNA_STATUS_T_ENABLED;
1857 bnad_rx_ctrl_init(struct bnad *bnad, u32 rx_id)
1859 struct bnad_rx_info *rx_info = &bnad->rx_info[rx_id];
1862 for (i = 0; i < bnad->num_rxp_per_rx; i++)
1863 rx_info->rx_ctrl[i].bnad = bnad;
1866 /* Called with mutex_lock(&bnad->conf_mutex) held */
1868 bnad_destroy_rx(struct bnad *bnad, u32 rx_id)
1870 struct bnad_rx_info *rx_info = &bnad->rx_info[rx_id];
1871 struct bna_rx_config *rx_config = &bnad->rx_config[rx_id];
1872 struct bna_res_info *res_info = &bnad->rx_res_info[rx_id].res_info[0];
1873 unsigned long flags;
1880 spin_lock_irqsave(&bnad->bna_lock, flags);
1881 if (bnad->cfg_flags & BNAD_CF_DIM_ENABLED &&
1882 test_bit(BNAD_RF_DIM_TIMER_RUNNING, &bnad->run_flags)) {
1883 clear_bit(BNAD_RF_DIM_TIMER_RUNNING, &bnad->run_flags);
1886 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1888 del_timer_sync(&bnad->dim_timer);
1891 init_completion(&bnad->bnad_completions.rx_comp);
1892 spin_lock_irqsave(&bnad->bna_lock, flags);
1893 bna_rx_disable(rx_info->rx, BNA_HARD_CLEANUP, bnad_cb_rx_disabled);
1894 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1895 wait_for_completion(&bnad->bnad_completions.rx_comp);
1897 if (rx_info->rx_ctrl[0].ccb->intr_type == BNA_INTR_T_MSIX)
1898 bnad_rx_msix_unregister(bnad, rx_info, rx_config->num_paths);
1900 bnad_napi_delete(bnad, rx_id);
1902 spin_lock_irqsave(&bnad->bna_lock, flags);
1903 bna_rx_destroy(rx_info->rx);
1907 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1909 bnad_rx_res_free(bnad, res_info);
1912 /* Called with mutex_lock(&bnad->conf_mutex) held */
1914 bnad_setup_rx(struct bnad *bnad, u32 rx_id)
1917 struct bnad_rx_info *rx_info = &bnad->rx_info[rx_id];
1918 struct bna_res_info *res_info = &bnad->rx_res_info[rx_id].res_info[0];
1919 struct bna_intr_info *intr_info =
1920 &res_info[BNA_RX_RES_T_INTR].res_u.intr_info;
1921 struct bna_rx_config *rx_config = &bnad->rx_config[rx_id];
1922 static const struct bna_rx_event_cbfn rx_cbfn = {
1923 .rcb_setup_cbfn = bnad_cb_rcb_setup,
1924 .rcb_destroy_cbfn = NULL,
1925 .ccb_setup_cbfn = bnad_cb_ccb_setup,
1926 .ccb_destroy_cbfn = bnad_cb_ccb_destroy,
1927 .rx_stall_cbfn = bnad_cb_rx_stall,
1928 .rx_cleanup_cbfn = bnad_cb_rx_cleanup,
1929 .rx_post_cbfn = bnad_cb_rx_post,
1932 unsigned long flags;
1934 rx_info->rx_id = rx_id;
1936 /* Initialize the Rx object configuration */
1937 bnad_init_rx_config(bnad, rx_config);
1939 /* Get BNA's resource requirement for one Rx object */
1940 spin_lock_irqsave(&bnad->bna_lock, flags);
1941 bna_rx_res_req(rx_config, res_info);
1942 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1944 /* Fill Unmap Q memory requirements */
1945 BNAD_FILL_UNMAPQ_MEM_REQ(
1946 &res_info[BNA_RX_RES_MEM_T_UNMAPQ],
1947 rx_config->num_paths +
1948 ((rx_config->rxp_type == BNA_RXP_SINGLE) ? 0 :
1949 rx_config->num_paths), BNAD_RX_UNMAPQ_DEPTH);
1951 /* Allocate resource */
1952 err = bnad_rx_res_alloc(bnad, res_info, rx_id);
1956 bnad_rx_ctrl_init(bnad, rx_id);
1958 /* Ask BNA to create one Rx object, supplying required resources */
1959 spin_lock_irqsave(&bnad->bna_lock, flags);
1960 rx = bna_rx_create(&bnad->bna, bnad, rx_config, &rx_cbfn, res_info,
1964 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1968 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1970 INIT_WORK(&rx_info->rx_cleanup_work,
1971 (work_func_t)(bnad_rx_cleanup));
1974 * Init NAPI, so that state is set to NAPI_STATE_SCHED,
1975 * so that IRQ handler cannot schedule NAPI at this point.
1977 bnad_napi_add(bnad, rx_id);
1979 /* Register ISR for the Rx object */
1980 if (intr_info->intr_type == BNA_INTR_T_MSIX) {
1981 err = bnad_rx_msix_register(bnad, rx_info, rx_id,
1982 rx_config->num_paths);
1987 spin_lock_irqsave(&bnad->bna_lock, flags);
1989 /* Set up Dynamic Interrupt Moderation Vector */
1990 if (bnad->cfg_flags & BNAD_CF_DIM_ENABLED)
1991 bna_rx_dim_reconfig(&bnad->bna, bna_napi_dim_vector);
1993 /* Enable VLAN filtering only on the default Rx */
1994 bna_rx_vlanfilter_enable(rx);
1996 /* Start the DIM timer */
1997 bnad_dim_timer_start(bnad);
2001 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2006 bnad_destroy_rx(bnad, rx_id);
2010 /* Called with conf_lock & bnad->bna_lock held */
2012 bnad_tx_coalescing_timeo_set(struct bnad *bnad)
2014 struct bnad_tx_info *tx_info;
2016 tx_info = &bnad->tx_info[0];
2020 bna_tx_coalescing_timeo_set(tx_info->tx, bnad->tx_coalescing_timeo);
2023 /* Called with conf_lock & bnad->bna_lock held */
2025 bnad_rx_coalescing_timeo_set(struct bnad *bnad)
2027 struct bnad_rx_info *rx_info;
2030 for (i = 0; i < bnad->num_rx; i++) {
2031 rx_info = &bnad->rx_info[i];
2034 bna_rx_coalescing_timeo_set(rx_info->rx,
2035 bnad->rx_coalescing_timeo);
2040 * Called with bnad->bna_lock held
2043 bnad_mac_addr_set_locked(struct bnad *bnad, u8 *mac_addr)
2047 if (!is_valid_ether_addr(mac_addr))
2048 return -EADDRNOTAVAIL;
2050 /* If datapath is down, pretend everything went through */
2051 if (!bnad->rx_info[0].rx)
2054 ret = bna_rx_ucast_set(bnad->rx_info[0].rx, mac_addr, NULL);
2055 if (ret != BNA_CB_SUCCESS)
2056 return -EADDRNOTAVAIL;
2061 /* Should be called with conf_lock held */
2063 bnad_enable_default_bcast(struct bnad *bnad)
2065 struct bnad_rx_info *rx_info = &bnad->rx_info[0];
2067 unsigned long flags;
2069 init_completion(&bnad->bnad_completions.mcast_comp);
2071 spin_lock_irqsave(&bnad->bna_lock, flags);
2072 ret = bna_rx_mcast_add(rx_info->rx, (u8 *)bnad_bcast_addr,
2073 bnad_cb_rx_mcast_add);
2074 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2076 if (ret == BNA_CB_SUCCESS)
2077 wait_for_completion(&bnad->bnad_completions.mcast_comp);
2081 if (bnad->bnad_completions.mcast_comp_status != BNA_CB_SUCCESS)
2087 /* Called with mutex_lock(&bnad->conf_mutex) held */
2089 bnad_restore_vlans(struct bnad *bnad, u32 rx_id)
2092 unsigned long flags;
2094 for_each_set_bit(vid, bnad->active_vlans, VLAN_N_VID) {
2095 spin_lock_irqsave(&bnad->bna_lock, flags);
2096 bna_rx_vlan_add(bnad->rx_info[rx_id].rx, vid);
2097 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2101 /* Statistics utilities */
2103 bnad_netdev_qstats_fill(struct bnad *bnad, struct rtnl_link_stats64 *stats)
2107 for (i = 0; i < bnad->num_rx; i++) {
2108 for (j = 0; j < bnad->num_rxp_per_rx; j++) {
2109 if (bnad->rx_info[i].rx_ctrl[j].ccb) {
2110 stats->rx_packets += bnad->rx_info[i].
2111 rx_ctrl[j].ccb->rcb[0]->rxq->rx_packets;
2112 stats->rx_bytes += bnad->rx_info[i].
2113 rx_ctrl[j].ccb->rcb[0]->rxq->rx_bytes;
2114 if (bnad->rx_info[i].rx_ctrl[j].ccb->rcb[1] &&
2115 bnad->rx_info[i].rx_ctrl[j].ccb->
2117 stats->rx_packets +=
2118 bnad->rx_info[i].rx_ctrl[j].
2119 ccb->rcb[1]->rxq->rx_packets;
2121 bnad->rx_info[i].rx_ctrl[j].
2122 ccb->rcb[1]->rxq->rx_bytes;
2127 for (i = 0; i < bnad->num_tx; i++) {
2128 for (j = 0; j < bnad->num_txq_per_tx; j++) {
2129 if (bnad->tx_info[i].tcb[j]) {
2130 stats->tx_packets +=
2131 bnad->tx_info[i].tcb[j]->txq->tx_packets;
2133 bnad->tx_info[i].tcb[j]->txq->tx_bytes;
2140 * Must be called with the bna_lock held.
2143 bnad_netdev_hwstats_fill(struct bnad *bnad, struct rtnl_link_stats64 *stats)
2145 struct bfi_enet_stats_mac *mac_stats;
2149 mac_stats = &bnad->stats.bna_stats->hw_stats.mac_stats;
2151 mac_stats->rx_fcs_error + mac_stats->rx_alignment_error +
2152 mac_stats->rx_frame_length_error + mac_stats->rx_code_error +
2153 mac_stats->rx_undersize;
2154 stats->tx_errors = mac_stats->tx_fcs_error +
2155 mac_stats->tx_undersize;
2156 stats->rx_dropped = mac_stats->rx_drop;
2157 stats->tx_dropped = mac_stats->tx_drop;
2158 stats->multicast = mac_stats->rx_multicast;
2159 stats->collisions = mac_stats->tx_total_collision;
2161 stats->rx_length_errors = mac_stats->rx_frame_length_error;
2163 /* receive ring buffer overflow ?? */
2165 stats->rx_crc_errors = mac_stats->rx_fcs_error;
2166 stats->rx_frame_errors = mac_stats->rx_alignment_error;
2167 /* recv'r fifo overrun */
2168 bmap = bna_rx_rid_mask(&bnad->bna);
2169 for (i = 0; bmap; i++) {
2171 stats->rx_fifo_errors +=
2172 bnad->stats.bna_stats->
2173 hw_stats.rxf_stats[i].frame_drops;
2181 bnad_mbox_irq_sync(struct bnad *bnad)
2184 unsigned long flags;
2186 spin_lock_irqsave(&bnad->bna_lock, flags);
2187 if (bnad->cfg_flags & BNAD_CF_MSIX)
2188 irq = bnad->msix_table[BNAD_MAILBOX_MSIX_INDEX].vector;
2190 irq = bnad->pcidev->irq;
2191 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2193 synchronize_irq(irq);
2196 /* Utility used by bnad_start_xmit, for doing TSO */
2198 bnad_tso_prepare(struct bnad *bnad, struct sk_buff *skb)
2202 if (skb_header_cloned(skb)) {
2203 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
2205 BNAD_UPDATE_CTR(bnad, tso_err);
2211 * For TSO, the TCP checksum field is seeded with pseudo-header sum
2212 * excluding the length field.
2214 if (skb->protocol == htons(ETH_P_IP)) {
2215 struct iphdr *iph = ip_hdr(skb);
2217 /* Do we really need these? */
2221 tcp_hdr(skb)->check =
2222 ~csum_tcpudp_magic(iph->saddr, iph->daddr, 0,
2224 BNAD_UPDATE_CTR(bnad, tso4);
2226 struct ipv6hdr *ipv6h = ipv6_hdr(skb);
2228 ipv6h->payload_len = 0;
2229 tcp_hdr(skb)->check =
2230 ~csum_ipv6_magic(&ipv6h->saddr, &ipv6h->daddr, 0,
2232 BNAD_UPDATE_CTR(bnad, tso6);
2239 * Initialize Q numbers depending on Rx Paths
2240 * Called with bnad->bna_lock held, because of cfg_flags
2244 bnad_q_num_init(struct bnad *bnad)
2248 rxps = min((uint)num_online_cpus(),
2249 (uint)(BNAD_MAX_RX * BNAD_MAX_RXP_PER_RX));
2251 if (!(bnad->cfg_flags & BNAD_CF_MSIX))
2252 rxps = 1; /* INTx */
2256 bnad->num_rxp_per_rx = rxps;
2257 bnad->num_txq_per_tx = BNAD_TXQ_NUM;
2261 * Adjusts the Q numbers, given a number of msix vectors
2262 * Give preference to RSS as opposed to Tx priority Queues,
2263 * in such a case, just use 1 Tx Q
2264 * Called with bnad->bna_lock held b'cos of cfg_flags access
2267 bnad_q_num_adjust(struct bnad *bnad, int msix_vectors, int temp)
2269 bnad->num_txq_per_tx = 1;
2270 if ((msix_vectors >= (bnad->num_tx * bnad->num_txq_per_tx) +
2271 bnad_rxqs_per_cq + BNAD_MAILBOX_MSIX_VECTORS) &&
2272 (bnad->cfg_flags & BNAD_CF_MSIX)) {
2273 bnad->num_rxp_per_rx = msix_vectors -
2274 (bnad->num_tx * bnad->num_txq_per_tx) -
2275 BNAD_MAILBOX_MSIX_VECTORS;
2277 bnad->num_rxp_per_rx = 1;
2280 /* Enable / disable ioceth */
2282 bnad_ioceth_disable(struct bnad *bnad)
2284 unsigned long flags;
2287 spin_lock_irqsave(&bnad->bna_lock, flags);
2288 init_completion(&bnad->bnad_completions.ioc_comp);
2289 bna_ioceth_disable(&bnad->bna.ioceth, BNA_HARD_CLEANUP);
2290 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2292 wait_for_completion_timeout(&bnad->bnad_completions.ioc_comp,
2293 msecs_to_jiffies(BNAD_IOCETH_TIMEOUT));
2295 err = bnad->bnad_completions.ioc_comp_status;
2300 bnad_ioceth_enable(struct bnad *bnad)
2303 unsigned long flags;
2305 spin_lock_irqsave(&bnad->bna_lock, flags);
2306 init_completion(&bnad->bnad_completions.ioc_comp);
2307 bnad->bnad_completions.ioc_comp_status = BNA_CB_WAITING;
2308 bna_ioceth_enable(&bnad->bna.ioceth);
2309 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2311 wait_for_completion_timeout(&bnad->bnad_completions.ioc_comp,
2312 msecs_to_jiffies(BNAD_IOCETH_TIMEOUT));
2314 err = bnad->bnad_completions.ioc_comp_status;
2319 /* Free BNA resources */
2321 bnad_res_free(struct bnad *bnad, struct bna_res_info *res_info,
2326 for (i = 0; i < res_val_max; i++)
2327 bnad_mem_free(bnad, &res_info[i].res_u.mem_info);
2330 /* Allocates memory and interrupt resources for BNA */
2332 bnad_res_alloc(struct bnad *bnad, struct bna_res_info *res_info,
2337 for (i = 0; i < res_val_max; i++) {
2338 err = bnad_mem_alloc(bnad, &res_info[i].res_u.mem_info);
2345 bnad_res_free(bnad, res_info, res_val_max);
2349 /* Interrupt enable / disable */
2351 bnad_enable_msix(struct bnad *bnad)
2354 unsigned long flags;
2356 spin_lock_irqsave(&bnad->bna_lock, flags);
2357 if (!(bnad->cfg_flags & BNAD_CF_MSIX)) {
2358 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2361 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2363 if (bnad->msix_table)
2367 kcalloc(bnad->msix_num, sizeof(struct msix_entry), GFP_KERNEL);
2369 if (!bnad->msix_table)
2372 for (i = 0; i < bnad->msix_num; i++)
2373 bnad->msix_table[i].entry = i;
2375 ret = pci_enable_msix(bnad->pcidev, bnad->msix_table, bnad->msix_num);
2377 /* Not enough MSI-X vectors. */
2378 pr_warn("BNA: %d MSI-X vectors allocated < %d requested\n",
2379 ret, bnad->msix_num);
2381 spin_lock_irqsave(&bnad->bna_lock, flags);
2382 /* ret = #of vectors that we got */
2383 bnad_q_num_adjust(bnad, (ret - BNAD_MAILBOX_MSIX_VECTORS) / 2,
2384 (ret - BNAD_MAILBOX_MSIX_VECTORS) / 2);
2385 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2387 bnad->msix_num = BNAD_NUM_TXQ + BNAD_NUM_RXP +
2388 BNAD_MAILBOX_MSIX_VECTORS;
2390 if (bnad->msix_num > ret)
2393 /* Try once more with adjusted numbers */
2394 /* If this fails, fall back to INTx */
2395 ret = pci_enable_msix(bnad->pcidev, bnad->msix_table,
2403 pci_intx(bnad->pcidev, 0);
2408 pr_warn("BNA: MSI-X enable failed - operating in INTx mode\n");
2410 kfree(bnad->msix_table);
2411 bnad->msix_table = NULL;
2413 spin_lock_irqsave(&bnad->bna_lock, flags);
2414 bnad->cfg_flags &= ~BNAD_CF_MSIX;
2415 bnad_q_num_init(bnad);
2416 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2420 bnad_disable_msix(struct bnad *bnad)
2423 unsigned long flags;
2425 spin_lock_irqsave(&bnad->bna_lock, flags);
2426 cfg_flags = bnad->cfg_flags;
2427 if (bnad->cfg_flags & BNAD_CF_MSIX)
2428 bnad->cfg_flags &= ~BNAD_CF_MSIX;
2429 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2431 if (cfg_flags & BNAD_CF_MSIX) {
2432 pci_disable_msix(bnad->pcidev);
2433 kfree(bnad->msix_table);
2434 bnad->msix_table = NULL;
2438 /* Netdev entry points */
2440 bnad_open(struct net_device *netdev)
2443 struct bnad *bnad = netdev_priv(netdev);
2444 struct bna_pause_config pause_config;
2446 unsigned long flags;
2448 mutex_lock(&bnad->conf_mutex);
2451 err = bnad_setup_tx(bnad, 0);
2456 err = bnad_setup_rx(bnad, 0);
2461 pause_config.tx_pause = 0;
2462 pause_config.rx_pause = 0;
2464 mtu = ETH_HLEN + VLAN_HLEN + bnad->netdev->mtu + ETH_FCS_LEN;
2466 spin_lock_irqsave(&bnad->bna_lock, flags);
2467 bna_enet_mtu_set(&bnad->bna.enet, mtu, NULL);
2468 bna_enet_pause_config(&bnad->bna.enet, &pause_config, NULL);
2469 bna_enet_enable(&bnad->bna.enet);
2470 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2472 /* Enable broadcast */
2473 bnad_enable_default_bcast(bnad);
2475 /* Restore VLANs, if any */
2476 bnad_restore_vlans(bnad, 0);
2478 /* Set the UCAST address */
2479 spin_lock_irqsave(&bnad->bna_lock, flags);
2480 bnad_mac_addr_set_locked(bnad, netdev->dev_addr);
2481 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2483 /* Start the stats timer */
2484 bnad_stats_timer_start(bnad);
2486 mutex_unlock(&bnad->conf_mutex);
2491 bnad_destroy_tx(bnad, 0);
2494 mutex_unlock(&bnad->conf_mutex);
2499 bnad_stop(struct net_device *netdev)
2501 struct bnad *bnad = netdev_priv(netdev);
2502 unsigned long flags;
2504 mutex_lock(&bnad->conf_mutex);
2506 /* Stop the stats timer */
2507 bnad_stats_timer_stop(bnad);
2509 init_completion(&bnad->bnad_completions.enet_comp);
2511 spin_lock_irqsave(&bnad->bna_lock, flags);
2512 bna_enet_disable(&bnad->bna.enet, BNA_HARD_CLEANUP,
2513 bnad_cb_enet_disabled);
2514 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2516 wait_for_completion(&bnad->bnad_completions.enet_comp);
2518 bnad_destroy_tx(bnad, 0);
2519 bnad_destroy_rx(bnad, 0);
2521 /* Synchronize mailbox IRQ */
2522 bnad_mbox_irq_sync(bnad);
2524 mutex_unlock(&bnad->conf_mutex);
2531 * bnad_start_xmit : Netdev entry point for Transmit
2532 * Called under lock held by net_device
2535 bnad_start_xmit(struct sk_buff *skb, struct net_device *netdev)
2537 struct bnad *bnad = netdev_priv(netdev);
2539 struct bna_tcb *tcb = bnad->tx_info[0].tcb[txq_id];
2541 u16 txq_prod, vlan_tag = 0;
2542 u32 unmap_prod, wis, wis_used, wi_range;
2543 u32 vectors, vect_id, i, acked;
2548 struct bnad_unmap_q *unmap_q = tcb->unmap_q;
2549 dma_addr_t dma_addr;
2550 struct bna_txq_entry *txqent;
2553 if (unlikely(skb->len <= ETH_HLEN)) {
2555 BNAD_UPDATE_CTR(bnad, tx_skb_too_short);
2556 return NETDEV_TX_OK;
2558 if (unlikely(skb_headlen(skb) > BFI_TX_MAX_DATA_PER_VECTOR)) {
2560 BNAD_UPDATE_CTR(bnad, tx_skb_headlen_too_long);
2561 return NETDEV_TX_OK;
2563 if (unlikely(skb_headlen(skb) == 0)) {
2565 BNAD_UPDATE_CTR(bnad, tx_skb_headlen_zero);
2566 return NETDEV_TX_OK;
2570 * Takes care of the Tx that is scheduled between clearing the flag
2571 * and the netif_tx_stop_all_queues() call.
2573 if (unlikely(!test_bit(BNAD_TXQ_TX_STARTED, &tcb->flags))) {
2575 BNAD_UPDATE_CTR(bnad, tx_skb_stopping);
2576 return NETDEV_TX_OK;
2579 vectors = 1 + skb_shinfo(skb)->nr_frags;
2580 if (unlikely(vectors > BFI_TX_MAX_VECTORS_PER_PKT)) {
2582 BNAD_UPDATE_CTR(bnad, tx_skb_max_vectors);
2583 return NETDEV_TX_OK;
2585 wis = BNA_TXQ_WI_NEEDED(vectors); /* 4 vectors per work item */
2587 if (unlikely(wis > BNA_QE_FREE_CNT(tcb, tcb->q_depth) ||
2588 vectors > BNA_QE_FREE_CNT(unmap_q, unmap_q->q_depth))) {
2589 if ((u16) (*tcb->hw_consumer_index) !=
2590 tcb->consumer_index &&
2591 !test_and_set_bit(BNAD_TXQ_FREE_SENT, &tcb->flags)) {
2592 acked = bnad_txcmpl_process(bnad, tcb);
2593 if (likely(test_bit(BNAD_TXQ_TX_STARTED, &tcb->flags)))
2594 bna_ib_ack(tcb->i_dbell, acked);
2595 smp_mb__before_clear_bit();
2596 clear_bit(BNAD_TXQ_FREE_SENT, &tcb->flags);
2598 netif_stop_queue(netdev);
2599 BNAD_UPDATE_CTR(bnad, netif_queue_stop);
2604 * Check again to deal with race condition between
2605 * netif_stop_queue here, and netif_wake_queue in
2606 * interrupt handler which is not inside netif tx lock.
2609 (wis > BNA_QE_FREE_CNT(tcb, tcb->q_depth) ||
2610 vectors > BNA_QE_FREE_CNT(unmap_q, unmap_q->q_depth))) {
2611 BNAD_UPDATE_CTR(bnad, netif_queue_stop);
2612 return NETDEV_TX_BUSY;
2614 netif_wake_queue(netdev);
2615 BNAD_UPDATE_CTR(bnad, netif_queue_wakeup);
2619 unmap_prod = unmap_q->producer_index;
2622 txq_prod = tcb->producer_index;
2623 BNA_TXQ_QPGE_PTR_GET(txq_prod, tcb->sw_qpt, txqent, wi_range);
2624 txqent->hdr.wi.reserved = 0;
2625 txqent->hdr.wi.num_vectors = vectors;
2627 if (vlan_tx_tag_present(skb)) {
2628 vlan_tag = (u16) vlan_tx_tag_get(skb);
2629 flags |= (BNA_TXQ_WI_CF_INS_PRIO | BNA_TXQ_WI_CF_INS_VLAN);
2631 if (test_bit(BNAD_RF_CEE_RUNNING, &bnad->run_flags)) {
2633 (tcb->priority & 0x7) << 13 | (vlan_tag & 0x1fff);
2634 flags |= (BNA_TXQ_WI_CF_INS_PRIO | BNA_TXQ_WI_CF_INS_VLAN);
2637 txqent->hdr.wi.vlan_tag = htons(vlan_tag);
2639 if (skb_is_gso(skb)) {
2640 gso_size = skb_shinfo(skb)->gso_size;
2642 if (unlikely(gso_size > netdev->mtu)) {
2644 BNAD_UPDATE_CTR(bnad, tx_skb_mss_too_long);
2645 return NETDEV_TX_OK;
2647 if (unlikely((gso_size + skb_transport_offset(skb) +
2648 tcp_hdrlen(skb)) >= skb->len)) {
2649 txqent->hdr.wi.opcode =
2650 __constant_htons(BNA_TXQ_WI_SEND);
2651 txqent->hdr.wi.lso_mss = 0;
2652 BNAD_UPDATE_CTR(bnad, tx_skb_tso_too_short);
2654 txqent->hdr.wi.opcode =
2655 __constant_htons(BNA_TXQ_WI_SEND_LSO);
2656 txqent->hdr.wi.lso_mss = htons(gso_size);
2659 err = bnad_tso_prepare(bnad, skb);
2660 if (unlikely(err)) {
2662 BNAD_UPDATE_CTR(bnad, tx_skb_tso_prepare);
2663 return NETDEV_TX_OK;
2665 flags |= (BNA_TXQ_WI_CF_IP_CKSUM | BNA_TXQ_WI_CF_TCP_CKSUM);
2666 txqent->hdr.wi.l4_hdr_size_n_offset =
2667 htons(BNA_TXQ_WI_L4_HDR_N_OFFSET
2668 (tcp_hdrlen(skb) >> 2,
2669 skb_transport_offset(skb)));
2671 txqent->hdr.wi.opcode = __constant_htons(BNA_TXQ_WI_SEND);
2672 txqent->hdr.wi.lso_mss = 0;
2674 if (unlikely(skb->len > (netdev->mtu + ETH_HLEN))) {
2676 BNAD_UPDATE_CTR(bnad, tx_skb_non_tso_too_long);
2677 return NETDEV_TX_OK;
2680 if (skb->ip_summed == CHECKSUM_PARTIAL) {
2683 if (skb->protocol == __constant_htons(ETH_P_IP))
2684 proto = ip_hdr(skb)->protocol;
2685 else if (skb->protocol ==
2686 __constant_htons(ETH_P_IPV6)) {
2687 /* nexthdr may not be TCP immediately. */
2688 proto = ipv6_hdr(skb)->nexthdr;
2690 if (proto == IPPROTO_TCP) {
2691 flags |= BNA_TXQ_WI_CF_TCP_CKSUM;
2692 txqent->hdr.wi.l4_hdr_size_n_offset =
2693 htons(BNA_TXQ_WI_L4_HDR_N_OFFSET
2694 (0, skb_transport_offset(skb)));
2696 BNAD_UPDATE_CTR(bnad, tcpcsum_offload);
2698 if (unlikely(skb_headlen(skb) <
2699 skb_transport_offset(skb) + tcp_hdrlen(skb))) {
2701 BNAD_UPDATE_CTR(bnad, tx_skb_tcp_hdr);
2702 return NETDEV_TX_OK;
2705 } else if (proto == IPPROTO_UDP) {
2706 flags |= BNA_TXQ_WI_CF_UDP_CKSUM;
2707 txqent->hdr.wi.l4_hdr_size_n_offset =
2708 htons(BNA_TXQ_WI_L4_HDR_N_OFFSET
2709 (0, skb_transport_offset(skb)));
2711 BNAD_UPDATE_CTR(bnad, udpcsum_offload);
2712 if (unlikely(skb_headlen(skb) <
2713 skb_transport_offset(skb) +
2714 sizeof(struct udphdr))) {
2716 BNAD_UPDATE_CTR(bnad, tx_skb_udp_hdr);
2717 return NETDEV_TX_OK;
2721 BNAD_UPDATE_CTR(bnad, tx_skb_csum_err);
2722 return NETDEV_TX_OK;
2725 txqent->hdr.wi.l4_hdr_size_n_offset = 0;
2729 txqent->hdr.wi.flags = htons(flags);
2731 txqent->hdr.wi.frame_length = htonl(skb->len);
2733 unmap_q->unmap_array[unmap_prod].skb = skb;
2734 len = skb_headlen(skb);
2735 txqent->vector[0].length = htons(len);
2736 dma_addr = dma_map_single(&bnad->pcidev->dev, skb->data,
2737 skb_headlen(skb), DMA_TO_DEVICE);
2738 dma_unmap_addr_set(&unmap_q->unmap_array[unmap_prod], dma_addr,
2741 BNA_SET_DMA_ADDR(dma_addr, &txqent->vector[0].host_addr);
2742 BNA_QE_INDX_ADD(unmap_prod, 1, unmap_q->q_depth);
2747 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
2748 const struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[i];
2749 u16 size = skb_frag_size(frag);
2751 if (unlikely(size == 0)) {
2752 unmap_prod = unmap_q->producer_index;
2754 unmap_prod = bnad_pci_unmap_skb(&bnad->pcidev->dev,
2755 unmap_q->unmap_array,
2756 unmap_prod, unmap_q->q_depth, skb,
2759 BNAD_UPDATE_CTR(bnad, tx_skb_frag_zero);
2760 return NETDEV_TX_OK;
2765 if (++vect_id == BFI_TX_MAX_VECTORS_PER_WI) {
2770 BNA_QE_INDX_ADD(txq_prod, wis_used,
2773 BNA_TXQ_QPGE_PTR_GET(txq_prod, tcb->sw_qpt,
2777 txqent->hdr.wi_ext.opcode =
2778 __constant_htons(BNA_TXQ_WI_EXTENSION);
2781 BUG_ON(!(size <= BFI_TX_MAX_DATA_PER_VECTOR));
2782 txqent->vector[vect_id].length = htons(size);
2783 dma_addr = skb_frag_dma_map(&bnad->pcidev->dev, frag,
2784 0, size, DMA_TO_DEVICE);
2785 dma_unmap_addr_set(&unmap_q->unmap_array[unmap_prod], dma_addr,
2787 BNA_SET_DMA_ADDR(dma_addr, &txqent->vector[vect_id].host_addr);
2788 BNA_QE_INDX_ADD(unmap_prod, 1, unmap_q->q_depth);
2791 if (unlikely(len != skb->len)) {
2792 unmap_prod = unmap_q->producer_index;
2794 unmap_prod = bnad_pci_unmap_skb(&bnad->pcidev->dev,
2795 unmap_q->unmap_array, unmap_prod,
2796 unmap_q->q_depth, skb,
2797 skb_shinfo(skb)->nr_frags);
2799 BNAD_UPDATE_CTR(bnad, tx_skb_len_mismatch);
2800 return NETDEV_TX_OK;
2803 unmap_q->producer_index = unmap_prod;
2804 BNA_QE_INDX_ADD(txq_prod, wis_used, tcb->q_depth);
2805 tcb->producer_index = txq_prod;
2809 if (unlikely(!test_bit(BNAD_TXQ_TX_STARTED, &tcb->flags)))
2810 return NETDEV_TX_OK;
2812 bna_txq_prod_indx_doorbell(tcb);
2815 return NETDEV_TX_OK;
2819 * Used spin_lock to synchronize reading of stats structures, which
2820 * is written by BNA under the same lock.
2822 static struct rtnl_link_stats64 *
2823 bnad_get_stats64(struct net_device *netdev, struct rtnl_link_stats64 *stats)
2825 struct bnad *bnad = netdev_priv(netdev);
2826 unsigned long flags;
2828 spin_lock_irqsave(&bnad->bna_lock, flags);
2830 bnad_netdev_qstats_fill(bnad, stats);
2831 bnad_netdev_hwstats_fill(bnad, stats);
2833 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2839 bnad_set_rx_mode(struct net_device *netdev)
2841 struct bnad *bnad = netdev_priv(netdev);
2842 u32 new_mask, valid_mask;
2843 unsigned long flags;
2845 spin_lock_irqsave(&bnad->bna_lock, flags);
2847 new_mask = valid_mask = 0;
2849 if (netdev->flags & IFF_PROMISC) {
2850 if (!(bnad->cfg_flags & BNAD_CF_PROMISC)) {
2851 new_mask = BNAD_RXMODE_PROMISC_DEFAULT;
2852 valid_mask = BNAD_RXMODE_PROMISC_DEFAULT;
2853 bnad->cfg_flags |= BNAD_CF_PROMISC;
2856 if (bnad->cfg_flags & BNAD_CF_PROMISC) {
2857 new_mask = ~BNAD_RXMODE_PROMISC_DEFAULT;
2858 valid_mask = BNAD_RXMODE_PROMISC_DEFAULT;
2859 bnad->cfg_flags &= ~BNAD_CF_PROMISC;
2863 if (netdev->flags & IFF_ALLMULTI) {
2864 if (!(bnad->cfg_flags & BNAD_CF_ALLMULTI)) {
2865 new_mask |= BNA_RXMODE_ALLMULTI;
2866 valid_mask |= BNA_RXMODE_ALLMULTI;
2867 bnad->cfg_flags |= BNAD_CF_ALLMULTI;
2870 if (bnad->cfg_flags & BNAD_CF_ALLMULTI) {
2871 new_mask &= ~BNA_RXMODE_ALLMULTI;
2872 valid_mask |= BNA_RXMODE_ALLMULTI;
2873 bnad->cfg_flags &= ~BNAD_CF_ALLMULTI;
2877 if (bnad->rx_info[0].rx == NULL)
2880 bna_rx_mode_set(bnad->rx_info[0].rx, new_mask, valid_mask, NULL);
2882 if (!netdev_mc_empty(netdev)) {
2884 int mc_count = netdev_mc_count(netdev);
2886 /* Index 0 holds the broadcast address */
2888 kzalloc((mc_count + 1) * ETH_ALEN,
2893 memcpy(&mcaddr_list[0], &bnad_bcast_addr[0], ETH_ALEN);
2895 /* Copy rest of the MC addresses */
2896 bnad_netdev_mc_list_get(netdev, mcaddr_list);
2898 bna_rx_mcast_listset(bnad->rx_info[0].rx, mc_count + 1,
2901 /* Should we enable BNAD_CF_ALLMULTI for err != 0 ? */
2905 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2909 * bna_lock is used to sync writes to netdev->addr
2910 * conf_lock cannot be used since this call may be made
2911 * in a non-blocking context.
2914 bnad_set_mac_address(struct net_device *netdev, void *mac_addr)
2917 struct bnad *bnad = netdev_priv(netdev);
2918 struct sockaddr *sa = (struct sockaddr *)mac_addr;
2919 unsigned long flags;
2921 spin_lock_irqsave(&bnad->bna_lock, flags);
2923 err = bnad_mac_addr_set_locked(bnad, sa->sa_data);
2926 memcpy(netdev->dev_addr, sa->sa_data, netdev->addr_len);
2928 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2934 bnad_mtu_set(struct bnad *bnad, int mtu)
2936 unsigned long flags;
2938 init_completion(&bnad->bnad_completions.mtu_comp);
2940 spin_lock_irqsave(&bnad->bna_lock, flags);
2941 bna_enet_mtu_set(&bnad->bna.enet, mtu, bnad_cb_enet_mtu_set);
2942 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2944 wait_for_completion(&bnad->bnad_completions.mtu_comp);
2946 return bnad->bnad_completions.mtu_comp_status;
2950 bnad_change_mtu(struct net_device *netdev, int new_mtu)
2952 int err, mtu = netdev->mtu;
2953 struct bnad *bnad = netdev_priv(netdev);
2955 if (new_mtu + ETH_HLEN < ETH_ZLEN || new_mtu > BNAD_JUMBO_MTU)
2958 mutex_lock(&bnad->conf_mutex);
2960 netdev->mtu = new_mtu;
2962 mtu = ETH_HLEN + VLAN_HLEN + new_mtu + ETH_FCS_LEN;
2963 err = bnad_mtu_set(bnad, mtu);
2967 mutex_unlock(&bnad->conf_mutex);
2972 bnad_vlan_rx_add_vid(struct net_device *netdev,
2975 struct bnad *bnad = netdev_priv(netdev);
2976 unsigned long flags;
2978 if (!bnad->rx_info[0].rx)
2981 mutex_lock(&bnad->conf_mutex);
2983 spin_lock_irqsave(&bnad->bna_lock, flags);
2984 bna_rx_vlan_add(bnad->rx_info[0].rx, vid);
2985 set_bit(vid, bnad->active_vlans);
2986 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2988 mutex_unlock(&bnad->conf_mutex);
2994 bnad_vlan_rx_kill_vid(struct net_device *netdev,
2997 struct bnad *bnad = netdev_priv(netdev);
2998 unsigned long flags;
3000 if (!bnad->rx_info[0].rx)
3003 mutex_lock(&bnad->conf_mutex);
3005 spin_lock_irqsave(&bnad->bna_lock, flags);
3006 clear_bit(vid, bnad->active_vlans);
3007 bna_rx_vlan_del(bnad->rx_info[0].rx, vid);
3008 spin_unlock_irqrestore(&bnad->bna_lock, flags);
3010 mutex_unlock(&bnad->conf_mutex);
3015 #ifdef CONFIG_NET_POLL_CONTROLLER
3017 bnad_netpoll(struct net_device *netdev)
3019 struct bnad *bnad = netdev_priv(netdev);
3020 struct bnad_rx_info *rx_info;
3021 struct bnad_rx_ctrl *rx_ctrl;
3025 if (!(bnad->cfg_flags & BNAD_CF_MSIX)) {
3026 bna_intx_disable(&bnad->bna, curr_mask);
3027 bnad_isr(bnad->pcidev->irq, netdev);
3028 bna_intx_enable(&bnad->bna, curr_mask);
3031 * Tx processing may happen in sending context, so no need
3032 * to explicitly process completions here
3036 for (i = 0; i < bnad->num_rx; i++) {
3037 rx_info = &bnad->rx_info[i];
3040 for (j = 0; j < bnad->num_rxp_per_rx; j++) {
3041 rx_ctrl = &rx_info->rx_ctrl[j];
3043 bnad_netif_rx_schedule_poll(bnad,
3051 static const struct net_device_ops bnad_netdev_ops = {
3052 .ndo_open = bnad_open,
3053 .ndo_stop = bnad_stop,
3054 .ndo_start_xmit = bnad_start_xmit,
3055 .ndo_get_stats64 = bnad_get_stats64,
3056 .ndo_set_rx_mode = bnad_set_rx_mode,
3057 .ndo_validate_addr = eth_validate_addr,
3058 .ndo_set_mac_address = bnad_set_mac_address,
3059 .ndo_change_mtu = bnad_change_mtu,
3060 .ndo_vlan_rx_add_vid = bnad_vlan_rx_add_vid,
3061 .ndo_vlan_rx_kill_vid = bnad_vlan_rx_kill_vid,
3062 #ifdef CONFIG_NET_POLL_CONTROLLER
3063 .ndo_poll_controller = bnad_netpoll
3068 bnad_netdev_init(struct bnad *bnad, bool using_dac)
3070 struct net_device *netdev = bnad->netdev;
3072 netdev->hw_features = NETIF_F_SG | NETIF_F_RXCSUM |
3073 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
3074 NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_HW_VLAN_TX;
3076 netdev->vlan_features = NETIF_F_SG | NETIF_F_HIGHDMA |
3077 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
3078 NETIF_F_TSO | NETIF_F_TSO6;
3080 netdev->features |= netdev->hw_features |
3081 NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_FILTER;
3084 netdev->features |= NETIF_F_HIGHDMA;
3086 netdev->mem_start = bnad->mmio_start;
3087 netdev->mem_end = bnad->mmio_start + bnad->mmio_len - 1;
3089 netdev->netdev_ops = &bnad_netdev_ops;
3090 bnad_set_ethtool_ops(netdev);
3094 * 1. Initialize the bnad structure
3095 * 2. Setup netdev pointer in pci_dev
3096 * 3. Initialize no. of TxQ & CQs & MSIX vectors
3097 * 4. Initialize work queue.
3100 bnad_init(struct bnad *bnad,
3101 struct pci_dev *pdev, struct net_device *netdev)
3103 unsigned long flags;
3105 SET_NETDEV_DEV(netdev, &pdev->dev);
3106 pci_set_drvdata(pdev, netdev);
3108 bnad->netdev = netdev;
3109 bnad->pcidev = pdev;
3110 bnad->mmio_start = pci_resource_start(pdev, 0);
3111 bnad->mmio_len = pci_resource_len(pdev, 0);
3112 bnad->bar0 = ioremap_nocache(bnad->mmio_start, bnad->mmio_len);
3114 dev_err(&pdev->dev, "ioremap for bar0 failed\n");
3115 pci_set_drvdata(pdev, NULL);
3118 pr_info("bar0 mapped to %p, len %llu\n", bnad->bar0,
3119 (unsigned long long) bnad->mmio_len);
3121 spin_lock_irqsave(&bnad->bna_lock, flags);
3122 if (!bnad_msix_disable)
3123 bnad->cfg_flags = BNAD_CF_MSIX;
3125 bnad->cfg_flags |= BNAD_CF_DIM_ENABLED;
3127 bnad_q_num_init(bnad);
3128 spin_unlock_irqrestore(&bnad->bna_lock, flags);
3130 bnad->msix_num = (bnad->num_tx * bnad->num_txq_per_tx) +
3131 (bnad->num_rx * bnad->num_rxp_per_rx) +
3132 BNAD_MAILBOX_MSIX_VECTORS;
3134 bnad->txq_depth = BNAD_TXQ_DEPTH;
3135 bnad->rxq_depth = BNAD_RXQ_DEPTH;
3137 bnad->tx_coalescing_timeo = BFI_TX_COALESCING_TIMEO;
3138 bnad->rx_coalescing_timeo = BFI_RX_COALESCING_TIMEO;
3140 sprintf(bnad->wq_name, "%s_wq_%d", BNAD_NAME, bnad->id);
3141 bnad->work_q = create_singlethread_workqueue(bnad->wq_name);
3150 * Must be called after bnad_pci_uninit()
3151 * so that iounmap() and pci_set_drvdata(NULL)
3152 * happens only after PCI uninitialization.
3155 bnad_uninit(struct bnad *bnad)
3158 flush_workqueue(bnad->work_q);
3159 destroy_workqueue(bnad->work_q);
3160 bnad->work_q = NULL;
3164 iounmap(bnad->bar0);
3165 pci_set_drvdata(bnad->pcidev, NULL);
3170 a) Per ioceth mutes used for serializing configuration
3171 changes from OS interface
3172 b) spin lock used to protect bna state machine
3175 bnad_lock_init(struct bnad *bnad)
3177 spin_lock_init(&bnad->bna_lock);
3178 mutex_init(&bnad->conf_mutex);
3179 mutex_init(&bnad_list_mutex);
3183 bnad_lock_uninit(struct bnad *bnad)
3185 mutex_destroy(&bnad->conf_mutex);
3186 mutex_destroy(&bnad_list_mutex);
3189 /* PCI Initialization */
3191 bnad_pci_init(struct bnad *bnad,
3192 struct pci_dev *pdev, bool *using_dac)
3196 err = pci_enable_device(pdev);
3199 err = pci_request_regions(pdev, BNAD_NAME);
3201 goto disable_device;
3202 if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) &&
3203 !dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) {
3206 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
3208 err = dma_set_coherent_mask(&pdev->dev,
3211 goto release_regions;
3215 pci_set_master(pdev);
3219 pci_release_regions(pdev);
3221 pci_disable_device(pdev);
3227 bnad_pci_uninit(struct pci_dev *pdev)
3229 pci_release_regions(pdev);
3230 pci_disable_device(pdev);
3233 static int __devinit
3234 bnad_pci_probe(struct pci_dev *pdev,
3235 const struct pci_device_id *pcidev_id)
3241 struct net_device *netdev;
3242 struct bfa_pcidev pcidev_info;
3243 unsigned long flags;
3245 pr_info("bnad_pci_probe : (0x%p, 0x%p) PCI Func : (%d)\n",
3246 pdev, pcidev_id, PCI_FUNC(pdev->devfn));
3248 mutex_lock(&bnad_fwimg_mutex);
3249 if (!cna_get_firmware_buf(pdev)) {
3250 mutex_unlock(&bnad_fwimg_mutex);
3251 pr_warn("Failed to load Firmware Image!\n");
3254 mutex_unlock(&bnad_fwimg_mutex);
3257 * Allocates sizeof(struct net_device + struct bnad)
3258 * bnad = netdev->priv
3260 netdev = alloc_etherdev(sizeof(struct bnad));
3265 bnad = netdev_priv(netdev);
3266 bnad_lock_init(bnad);
3267 bnad_add_to_list(bnad);
3269 mutex_lock(&bnad->conf_mutex);
3271 * PCI initialization
3272 * Output : using_dac = 1 for 64 bit DMA
3273 * = 0 for 32 bit DMA
3275 err = bnad_pci_init(bnad, pdev, &using_dac);
3280 * Initialize bnad structure
3281 * Setup relation between pci_dev & netdev
3283 err = bnad_init(bnad, pdev, netdev);
3287 /* Initialize netdev structure, set up ethtool ops */
3288 bnad_netdev_init(bnad, using_dac);
3290 /* Set link to down state */
3291 netif_carrier_off(netdev);
3293 /* Setup the debugfs node for this bfad */
3294 if (bna_debugfs_enable)
3295 bnad_debugfs_init(bnad);
3297 /* Get resource requirement form bna */
3298 spin_lock_irqsave(&bnad->bna_lock, flags);
3299 bna_res_req(&bnad->res_info[0]);
3300 spin_unlock_irqrestore(&bnad->bna_lock, flags);
3302 /* Allocate resources from bna */
3303 err = bnad_res_alloc(bnad, &bnad->res_info[0], BNA_RES_T_MAX);
3309 /* Setup pcidev_info for bna_init() */
3310 pcidev_info.pci_slot = PCI_SLOT(bnad->pcidev->devfn);
3311 pcidev_info.pci_func = PCI_FUNC(bnad->pcidev->devfn);
3312 pcidev_info.device_id = bnad->pcidev->device;
3313 pcidev_info.pci_bar_kva = bnad->bar0;
3315 spin_lock_irqsave(&bnad->bna_lock, flags);
3316 bna_init(bna, bnad, &pcidev_info, &bnad->res_info[0]);
3317 spin_unlock_irqrestore(&bnad->bna_lock, flags);
3319 bnad->stats.bna_stats = &bna->stats;
3321 bnad_enable_msix(bnad);
3322 err = bnad_mbox_irq_alloc(bnad);
3328 setup_timer(&bnad->bna.ioceth.ioc.ioc_timer, bnad_ioc_timeout,
3329 ((unsigned long)bnad));
3330 setup_timer(&bnad->bna.ioceth.ioc.hb_timer, bnad_ioc_hb_check,
3331 ((unsigned long)bnad));
3332 setup_timer(&bnad->bna.ioceth.ioc.iocpf_timer, bnad_iocpf_timeout,
3333 ((unsigned long)bnad));
3334 setup_timer(&bnad->bna.ioceth.ioc.sem_timer, bnad_iocpf_sem_timeout,
3335 ((unsigned long)bnad));
3337 /* Now start the timer before calling IOC */
3338 mod_timer(&bnad->bna.ioceth.ioc.iocpf_timer,
3339 jiffies + msecs_to_jiffies(BNA_IOC_TIMER_FREQ));
3343 * If the call back comes with error, we bail out.
3344 * This is a catastrophic error.
3346 err = bnad_ioceth_enable(bnad);
3348 pr_err("BNA: Initialization failed err=%d\n",
3353 spin_lock_irqsave(&bnad->bna_lock, flags);
3354 if (bna_num_txq_set(bna, BNAD_NUM_TXQ + 1) ||
3355 bna_num_rxp_set(bna, BNAD_NUM_RXP + 1)) {
3356 bnad_q_num_adjust(bnad, bna_attr(bna)->num_txq - 1,
3357 bna_attr(bna)->num_rxp - 1);
3358 if (bna_num_txq_set(bna, BNAD_NUM_TXQ + 1) ||
3359 bna_num_rxp_set(bna, BNAD_NUM_RXP + 1))
3362 spin_unlock_irqrestore(&bnad->bna_lock, flags);
3364 goto disable_ioceth;
3366 spin_lock_irqsave(&bnad->bna_lock, flags);
3367 bna_mod_res_req(&bnad->bna, &bnad->mod_res_info[0]);
3368 spin_unlock_irqrestore(&bnad->bna_lock, flags);
3370 err = bnad_res_alloc(bnad, &bnad->mod_res_info[0], BNA_MOD_RES_T_MAX);
3373 goto disable_ioceth;
3376 spin_lock_irqsave(&bnad->bna_lock, flags);
3377 bna_mod_init(&bnad->bna, &bnad->mod_res_info[0]);
3378 spin_unlock_irqrestore(&bnad->bna_lock, flags);
3380 /* Get the burnt-in mac */
3381 spin_lock_irqsave(&bnad->bna_lock, flags);
3382 bna_enet_perm_mac_get(&bna->enet, &bnad->perm_addr);
3383 bnad_set_netdev_perm_addr(bnad);
3384 spin_unlock_irqrestore(&bnad->bna_lock, flags);
3386 mutex_unlock(&bnad->conf_mutex);
3388 /* Finally, reguister with net_device layer */
3389 err = register_netdev(netdev);
3391 pr_err("BNA : Registering with netdev failed\n");
3394 set_bit(BNAD_RF_NETDEV_REGISTERED, &bnad->run_flags);
3399 mutex_unlock(&bnad->conf_mutex);
3403 mutex_lock(&bnad->conf_mutex);
3404 bnad_res_free(bnad, &bnad->mod_res_info[0], BNA_MOD_RES_T_MAX);
3406 bnad_ioceth_disable(bnad);
3407 del_timer_sync(&bnad->bna.ioceth.ioc.ioc_timer);
3408 del_timer_sync(&bnad->bna.ioceth.ioc.sem_timer);
3409 del_timer_sync(&bnad->bna.ioceth.ioc.hb_timer);
3410 spin_lock_irqsave(&bnad->bna_lock, flags);
3412 spin_unlock_irqrestore(&bnad->bna_lock, flags);
3413 bnad_mbox_irq_free(bnad);
3414 bnad_disable_msix(bnad);
3416 bnad_res_free(bnad, &bnad->res_info[0], BNA_RES_T_MAX);
3418 /* Remove the debugfs node for this bnad */
3419 kfree(bnad->regdata);
3420 bnad_debugfs_uninit(bnad);
3423 bnad_pci_uninit(pdev);
3425 mutex_unlock(&bnad->conf_mutex);
3426 bnad_remove_from_list(bnad);
3427 bnad_lock_uninit(bnad);
3428 free_netdev(netdev);
3432 static void __devexit
3433 bnad_pci_remove(struct pci_dev *pdev)
3435 struct net_device *netdev = pci_get_drvdata(pdev);
3438 unsigned long flags;
3443 pr_info("%s bnad_pci_remove\n", netdev->name);
3444 bnad = netdev_priv(netdev);
3447 if (test_and_clear_bit(BNAD_RF_NETDEV_REGISTERED, &bnad->run_flags))
3448 unregister_netdev(netdev);
3450 mutex_lock(&bnad->conf_mutex);
3451 bnad_ioceth_disable(bnad);
3452 del_timer_sync(&bnad->bna.ioceth.ioc.ioc_timer);
3453 del_timer_sync(&bnad->bna.ioceth.ioc.sem_timer);
3454 del_timer_sync(&bnad->bna.ioceth.ioc.hb_timer);
3455 spin_lock_irqsave(&bnad->bna_lock, flags);
3457 spin_unlock_irqrestore(&bnad->bna_lock, flags);
3459 bnad_res_free(bnad, &bnad->mod_res_info[0], BNA_MOD_RES_T_MAX);
3460 bnad_res_free(bnad, &bnad->res_info[0], BNA_RES_T_MAX);
3461 bnad_mbox_irq_free(bnad);
3462 bnad_disable_msix(bnad);
3463 bnad_pci_uninit(pdev);
3464 mutex_unlock(&bnad->conf_mutex);
3465 bnad_remove_from_list(bnad);
3466 bnad_lock_uninit(bnad);
3467 /* Remove the debugfs node for this bnad */
3468 kfree(bnad->regdata);
3469 bnad_debugfs_uninit(bnad);
3471 free_netdev(netdev);
3474 static DEFINE_PCI_DEVICE_TABLE(bnad_pci_id_table) = {
3476 PCI_DEVICE(PCI_VENDOR_ID_BROCADE,
3477 PCI_DEVICE_ID_BROCADE_CT),
3478 .class = PCI_CLASS_NETWORK_ETHERNET << 8,
3479 .class_mask = 0xffff00
3482 PCI_DEVICE(PCI_VENDOR_ID_BROCADE,
3483 BFA_PCI_DEVICE_ID_CT2),
3484 .class = PCI_CLASS_NETWORK_ETHERNET << 8,
3485 .class_mask = 0xffff00
3490 MODULE_DEVICE_TABLE(pci, bnad_pci_id_table);
3492 static struct pci_driver bnad_pci_driver = {
3494 .id_table = bnad_pci_id_table,
3495 .probe = bnad_pci_probe,
3496 .remove = __devexit_p(bnad_pci_remove),
3500 bnad_module_init(void)
3504 pr_info("Brocade 10G Ethernet driver - version: %s\n",
3507 bfa_nw_ioc_auto_recover(bnad_ioc_auto_recover);
3509 err = pci_register_driver(&bnad_pci_driver);
3511 pr_err("bna : PCI registration failed in module init "
3520 bnad_module_exit(void)
3522 pci_unregister_driver(&bnad_pci_driver);
3523 release_firmware(bfi_fw);
3526 module_init(bnad_module_init);
3527 module_exit(bnad_module_exit);
3529 MODULE_AUTHOR("Brocade");
3530 MODULE_LICENSE("GPL");
3531 MODULE_DESCRIPTION("Brocade 10G PCIe Ethernet driver");
3532 MODULE_VERSION(BNAD_VERSION);
3533 MODULE_FIRMWARE(CNA_FW_FILE_CT);
3534 MODULE_FIRMWARE(CNA_FW_FILE_CT2);