2 * Linux network driver for QLogic BR-series Converged Network Adapter.
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License (GPL) Version 2 as
6 * published by the Free Software Foundation
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
11 * General Public License for more details.
14 * Copyright (c) 2005-2014 Brocade Communications Systems, Inc.
15 * Copyright (c) 2014-2015 QLogic Corporation
19 #include <linux/bitops.h>
20 #include <linux/netdevice.h>
21 #include <linux/skbuff.h>
22 #include <linux/etherdevice.h>
24 #include <linux/ethtool.h>
25 #include <linux/if_vlan.h>
26 #include <linux/if_ether.h>
28 #include <linux/prefetch.h>
29 #include <linux/module.h>
35 static DEFINE_MUTEX(bnad_fwimg_mutex);
40 static uint bnad_msix_disable;
41 module_param(bnad_msix_disable, uint, 0444);
42 MODULE_PARM_DESC(bnad_msix_disable, "Disable MSIX mode");
44 static uint bnad_ioc_auto_recover = 1;
45 module_param(bnad_ioc_auto_recover, uint, 0444);
46 MODULE_PARM_DESC(bnad_ioc_auto_recover, "Enable / Disable auto recovery");
48 static uint bna_debugfs_enable = 1;
49 module_param(bna_debugfs_enable, uint, S_IRUGO | S_IWUSR);
50 MODULE_PARM_DESC(bna_debugfs_enable, "Enables debugfs feature, default=1,"
51 " Range[false:0|true:1]");
56 static u32 bnad_rxqs_per_cq = 2;
58 static struct mutex bnad_list_mutex;
59 static LIST_HEAD(bnad_list);
60 static const u8 bnad_bcast_addr[] __aligned(2) =
61 { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
66 #define BNAD_GET_MBOX_IRQ(_bnad) \
67 (((_bnad)->cfg_flags & BNAD_CF_MSIX) ? \
68 ((_bnad)->msix_table[BNAD_MAILBOX_MSIX_INDEX].vector) : \
69 ((_bnad)->pcidev->irq))
71 #define BNAD_FILL_UNMAPQ_MEM_REQ(_res_info, _num, _size) \
73 (_res_info)->res_type = BNA_RES_T_MEM; \
74 (_res_info)->res_u.mem_info.mem_type = BNA_MEM_T_KVA; \
75 (_res_info)->res_u.mem_info.num = (_num); \
76 (_res_info)->res_u.mem_info.len = (_size); \
80 bnad_add_to_list(struct bnad *bnad)
82 mutex_lock(&bnad_list_mutex);
83 list_add_tail(&bnad->list_entry, &bnad_list);
85 mutex_unlock(&bnad_list_mutex);
89 bnad_remove_from_list(struct bnad *bnad)
91 mutex_lock(&bnad_list_mutex);
92 list_del(&bnad->list_entry);
93 mutex_unlock(&bnad_list_mutex);
97 * Reinitialize completions in CQ, once Rx is taken down
100 bnad_cq_cleanup(struct bnad *bnad, struct bna_ccb *ccb)
102 struct bna_cq_entry *cmpl;
105 for (i = 0; i < ccb->q_depth; i++) {
106 cmpl = &((struct bna_cq_entry *)ccb->sw_q)[i];
111 /* Tx Datapath functions */
114 /* Caller should ensure that the entry at unmap_q[index] is valid */
116 bnad_tx_buff_unmap(struct bnad *bnad,
117 struct bnad_tx_unmap *unmap_q,
118 u32 q_depth, u32 index)
120 struct bnad_tx_unmap *unmap;
124 unmap = &unmap_q[index];
125 nvecs = unmap->nvecs;
130 dma_unmap_single(&bnad->pcidev->dev,
131 dma_unmap_addr(&unmap->vectors[0], dma_addr),
132 skb_headlen(skb), DMA_TO_DEVICE);
133 dma_unmap_addr_set(&unmap->vectors[0], dma_addr, 0);
139 if (vector == BFI_TX_MAX_VECTORS_PER_WI) {
141 BNA_QE_INDX_INC(index, q_depth);
142 unmap = &unmap_q[index];
145 dma_unmap_page(&bnad->pcidev->dev,
146 dma_unmap_addr(&unmap->vectors[vector], dma_addr),
147 dma_unmap_len(&unmap->vectors[vector], dma_len),
149 dma_unmap_addr_set(&unmap->vectors[vector], dma_addr, 0);
153 BNA_QE_INDX_INC(index, q_depth);
159 * Frees all pending Tx Bufs
160 * At this point no activity is expected on the Q,
161 * so DMA unmap & freeing is fine.
164 bnad_txq_cleanup(struct bnad *bnad, struct bna_tcb *tcb)
166 struct bnad_tx_unmap *unmap_q = tcb->unmap_q;
170 for (i = 0; i < tcb->q_depth; i++) {
171 skb = unmap_q[i].skb;
174 bnad_tx_buff_unmap(bnad, unmap_q, tcb->q_depth, i);
176 dev_kfree_skb_any(skb);
181 * bnad_txcmpl_process : Frees the Tx bufs on Tx completion
182 * Can be called in a) Interrupt context
186 bnad_txcmpl_process(struct bnad *bnad, struct bna_tcb *tcb)
188 u32 sent_packets = 0, sent_bytes = 0;
189 u32 wis, unmap_wis, hw_cons, cons, q_depth;
190 struct bnad_tx_unmap *unmap_q = tcb->unmap_q;
191 struct bnad_tx_unmap *unmap;
194 /* Just return if TX is stopped */
195 if (!test_bit(BNAD_TXQ_TX_STARTED, &tcb->flags))
198 hw_cons = *(tcb->hw_consumer_index);
199 cons = tcb->consumer_index;
200 q_depth = tcb->q_depth;
202 wis = BNA_Q_INDEX_CHANGE(cons, hw_cons, q_depth);
203 BUG_ON(!(wis <= BNA_QE_IN_USE_CNT(tcb, tcb->q_depth)));
206 unmap = &unmap_q[cons];
211 sent_bytes += skb->len;
213 unmap_wis = BNA_TXQ_WI_NEEDED(unmap->nvecs);
216 cons = bnad_tx_buff_unmap(bnad, unmap_q, q_depth, cons);
217 dev_kfree_skb_any(skb);
220 /* Update consumer pointers. */
221 tcb->consumer_index = hw_cons;
223 tcb->txq->tx_packets += sent_packets;
224 tcb->txq->tx_bytes += sent_bytes;
230 bnad_tx_complete(struct bnad *bnad, struct bna_tcb *tcb)
232 struct net_device *netdev = bnad->netdev;
235 if (test_and_set_bit(BNAD_TXQ_FREE_SENT, &tcb->flags))
238 sent = bnad_txcmpl_process(bnad, tcb);
240 if (netif_queue_stopped(netdev) &&
241 netif_carrier_ok(netdev) &&
242 BNA_QE_FREE_CNT(tcb, tcb->q_depth) >=
243 BNAD_NETIF_WAKE_THRESHOLD) {
244 if (test_bit(BNAD_TXQ_TX_STARTED, &tcb->flags)) {
245 netif_wake_queue(netdev);
246 BNAD_UPDATE_CTR(bnad, netif_queue_wakeup);
251 if (likely(test_bit(BNAD_TXQ_TX_STARTED, &tcb->flags)))
252 bna_ib_ack(tcb->i_dbell, sent);
254 smp_mb__before_atomic();
255 clear_bit(BNAD_TXQ_FREE_SENT, &tcb->flags);
260 /* MSIX Tx Completion Handler */
262 bnad_msix_tx(int irq, void *data)
264 struct bna_tcb *tcb = (struct bna_tcb *)data;
265 struct bnad *bnad = tcb->bnad;
267 bnad_tx_complete(bnad, tcb);
273 bnad_rxq_alloc_uninit(struct bnad *bnad, struct bna_rcb *rcb)
275 struct bnad_rx_unmap_q *unmap_q = rcb->unmap_q;
277 unmap_q->reuse_pi = -1;
278 unmap_q->alloc_order = -1;
279 unmap_q->map_size = 0;
280 unmap_q->type = BNAD_RXBUF_NONE;
283 /* Default is page-based allocation. Multi-buffer support - TBD */
285 bnad_rxq_alloc_init(struct bnad *bnad, struct bna_rcb *rcb)
287 struct bnad_rx_unmap_q *unmap_q = rcb->unmap_q;
290 bnad_rxq_alloc_uninit(bnad, rcb);
292 order = get_order(rcb->rxq->buffer_size);
294 unmap_q->type = BNAD_RXBUF_PAGE;
296 if (bna_is_small_rxq(rcb->id)) {
297 unmap_q->alloc_order = 0;
298 unmap_q->map_size = rcb->rxq->buffer_size;
300 if (rcb->rxq->multi_buffer) {
301 unmap_q->alloc_order = 0;
302 unmap_q->map_size = rcb->rxq->buffer_size;
303 unmap_q->type = BNAD_RXBUF_MULTI_BUFF;
305 unmap_q->alloc_order = order;
307 (rcb->rxq->buffer_size > 2048) ?
308 PAGE_SIZE << order : 2048;
312 BUG_ON(((PAGE_SIZE << order) % unmap_q->map_size));
318 bnad_rxq_cleanup_page(struct bnad *bnad, struct bnad_rx_unmap *unmap)
323 dma_unmap_page(&bnad->pcidev->dev,
324 dma_unmap_addr(&unmap->vector, dma_addr),
325 unmap->vector.len, DMA_FROM_DEVICE);
326 put_page(unmap->page);
328 dma_unmap_addr_set(&unmap->vector, dma_addr, 0);
329 unmap->vector.len = 0;
333 bnad_rxq_cleanup_skb(struct bnad *bnad, struct bnad_rx_unmap *unmap)
338 dma_unmap_single(&bnad->pcidev->dev,
339 dma_unmap_addr(&unmap->vector, dma_addr),
340 unmap->vector.len, DMA_FROM_DEVICE);
341 dev_kfree_skb_any(unmap->skb);
343 dma_unmap_addr_set(&unmap->vector, dma_addr, 0);
344 unmap->vector.len = 0;
348 bnad_rxq_cleanup(struct bnad *bnad, struct bna_rcb *rcb)
350 struct bnad_rx_unmap_q *unmap_q = rcb->unmap_q;
353 for (i = 0; i < rcb->q_depth; i++) {
354 struct bnad_rx_unmap *unmap = &unmap_q->unmap[i];
356 if (BNAD_RXBUF_IS_SK_BUFF(unmap_q->type))
357 bnad_rxq_cleanup_skb(bnad, unmap);
359 bnad_rxq_cleanup_page(bnad, unmap);
361 bnad_rxq_alloc_uninit(bnad, rcb);
365 bnad_rxq_refill_page(struct bnad *bnad, struct bna_rcb *rcb, u32 nalloc)
367 u32 alloced, prod, q_depth;
368 struct bnad_rx_unmap_q *unmap_q = rcb->unmap_q;
369 struct bnad_rx_unmap *unmap, *prev;
370 struct bna_rxq_entry *rxent;
372 u32 page_offset, alloc_size;
375 prod = rcb->producer_index;
376 q_depth = rcb->q_depth;
378 alloc_size = PAGE_SIZE << unmap_q->alloc_order;
382 unmap = &unmap_q->unmap[prod];
384 if (unmap_q->reuse_pi < 0) {
385 page = alloc_pages(GFP_ATOMIC | __GFP_COMP,
386 unmap_q->alloc_order);
389 prev = &unmap_q->unmap[unmap_q->reuse_pi];
391 page_offset = prev->page_offset + unmap_q->map_size;
395 if (unlikely(!page)) {
396 BNAD_UPDATE_CTR(bnad, rxbuf_alloc_failed);
397 rcb->rxq->rxbuf_alloc_failed++;
401 dma_addr = dma_map_page(&bnad->pcidev->dev, page, page_offset,
402 unmap_q->map_size, DMA_FROM_DEVICE);
405 unmap->page_offset = page_offset;
406 dma_unmap_addr_set(&unmap->vector, dma_addr, dma_addr);
407 unmap->vector.len = unmap_q->map_size;
408 page_offset += unmap_q->map_size;
410 if (page_offset < alloc_size)
411 unmap_q->reuse_pi = prod;
413 unmap_q->reuse_pi = -1;
415 rxent = &((struct bna_rxq_entry *)rcb->sw_q)[prod];
416 BNA_SET_DMA_ADDR(dma_addr, &rxent->host_addr);
417 BNA_QE_INDX_INC(prod, q_depth);
422 if (likely(alloced)) {
423 rcb->producer_index = prod;
425 if (likely(test_bit(BNAD_RXQ_POST_OK, &rcb->flags)))
426 bna_rxq_prod_indx_doorbell(rcb);
433 bnad_rxq_refill_skb(struct bnad *bnad, struct bna_rcb *rcb, u32 nalloc)
435 u32 alloced, prod, q_depth, buff_sz;
436 struct bnad_rx_unmap_q *unmap_q = rcb->unmap_q;
437 struct bnad_rx_unmap *unmap;
438 struct bna_rxq_entry *rxent;
442 buff_sz = rcb->rxq->buffer_size;
443 prod = rcb->producer_index;
444 q_depth = rcb->q_depth;
448 unmap = &unmap_q->unmap[prod];
450 skb = netdev_alloc_skb_ip_align(bnad->netdev, buff_sz);
452 if (unlikely(!skb)) {
453 BNAD_UPDATE_CTR(bnad, rxbuf_alloc_failed);
454 rcb->rxq->rxbuf_alloc_failed++;
457 dma_addr = dma_map_single(&bnad->pcidev->dev, skb->data,
458 buff_sz, DMA_FROM_DEVICE);
461 dma_unmap_addr_set(&unmap->vector, dma_addr, dma_addr);
462 unmap->vector.len = buff_sz;
464 rxent = &((struct bna_rxq_entry *)rcb->sw_q)[prod];
465 BNA_SET_DMA_ADDR(dma_addr, &rxent->host_addr);
466 BNA_QE_INDX_INC(prod, q_depth);
471 if (likely(alloced)) {
472 rcb->producer_index = prod;
474 if (likely(test_bit(BNAD_RXQ_POST_OK, &rcb->flags)))
475 bna_rxq_prod_indx_doorbell(rcb);
482 bnad_rxq_post(struct bnad *bnad, struct bna_rcb *rcb)
484 struct bnad_rx_unmap_q *unmap_q = rcb->unmap_q;
487 to_alloc = BNA_QE_FREE_CNT(rcb, rcb->q_depth);
488 if (!(to_alloc >> BNAD_RXQ_REFILL_THRESHOLD_SHIFT))
491 if (BNAD_RXBUF_IS_SK_BUFF(unmap_q->type))
492 bnad_rxq_refill_skb(bnad, rcb, to_alloc);
494 bnad_rxq_refill_page(bnad, rcb, to_alloc);
497 #define flags_cksum_prot_mask (BNA_CQ_EF_IPV4 | BNA_CQ_EF_L3_CKSUM_OK | \
499 BNA_CQ_EF_TCP | BNA_CQ_EF_UDP | \
500 BNA_CQ_EF_L4_CKSUM_OK)
502 #define flags_tcp4 (BNA_CQ_EF_IPV4 | BNA_CQ_EF_L3_CKSUM_OK | \
503 BNA_CQ_EF_TCP | BNA_CQ_EF_L4_CKSUM_OK)
504 #define flags_tcp6 (BNA_CQ_EF_IPV6 | \
505 BNA_CQ_EF_TCP | BNA_CQ_EF_L4_CKSUM_OK)
506 #define flags_udp4 (BNA_CQ_EF_IPV4 | BNA_CQ_EF_L3_CKSUM_OK | \
507 BNA_CQ_EF_UDP | BNA_CQ_EF_L4_CKSUM_OK)
508 #define flags_udp6 (BNA_CQ_EF_IPV6 | \
509 BNA_CQ_EF_UDP | BNA_CQ_EF_L4_CKSUM_OK)
512 bnad_cq_drop_packet(struct bnad *bnad, struct bna_rcb *rcb,
513 u32 sop_ci, u32 nvecs)
515 struct bnad_rx_unmap_q *unmap_q;
516 struct bnad_rx_unmap *unmap;
519 unmap_q = rcb->unmap_q;
520 for (vec = 0, ci = sop_ci; vec < nvecs; vec++) {
521 unmap = &unmap_q->unmap[ci];
522 BNA_QE_INDX_INC(ci, rcb->q_depth);
524 if (BNAD_RXBUF_IS_SK_BUFF(unmap_q->type))
525 bnad_rxq_cleanup_skb(bnad, unmap);
527 bnad_rxq_cleanup_page(bnad, unmap);
532 bnad_cq_setup_skb_frags(struct bna_rcb *rcb, struct sk_buff *skb,
533 u32 sop_ci, u32 nvecs, u32 last_fraglen)
536 u32 ci, vec, len, totlen = 0;
537 struct bnad_rx_unmap_q *unmap_q;
538 struct bnad_rx_unmap *unmap;
540 unmap_q = rcb->unmap_q;
543 /* prefetch header */
544 prefetch(page_address(unmap_q->unmap[sop_ci].page) +
545 unmap_q->unmap[sop_ci].page_offset);
547 for (vec = 1, ci = sop_ci; vec <= nvecs; vec++) {
548 unmap = &unmap_q->unmap[ci];
549 BNA_QE_INDX_INC(ci, rcb->q_depth);
551 dma_unmap_page(&bnad->pcidev->dev,
552 dma_unmap_addr(&unmap->vector, dma_addr),
553 unmap->vector.len, DMA_FROM_DEVICE);
555 len = (vec == nvecs) ?
556 last_fraglen : unmap->vector.len;
557 skb->truesize += unmap->vector.len;
560 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
561 unmap->page, unmap->page_offset, len);
564 unmap->vector.len = 0;
568 skb->data_len += totlen;
572 bnad_cq_setup_skb(struct bnad *bnad, struct sk_buff *skb,
573 struct bnad_rx_unmap *unmap, u32 len)
577 dma_unmap_single(&bnad->pcidev->dev,
578 dma_unmap_addr(&unmap->vector, dma_addr),
579 unmap->vector.len, DMA_FROM_DEVICE);
582 skb->protocol = eth_type_trans(skb, bnad->netdev);
585 unmap->vector.len = 0;
589 bnad_cq_process(struct bnad *bnad, struct bna_ccb *ccb, int budget)
591 struct bna_cq_entry *cq, *cmpl, *next_cmpl;
592 struct bna_rcb *rcb = NULL;
593 struct bnad_rx_unmap_q *unmap_q;
594 struct bnad_rx_unmap *unmap = NULL;
595 struct sk_buff *skb = NULL;
596 struct bna_pkt_rate *pkt_rt = &ccb->pkt_rate;
597 struct bnad_rx_ctrl *rx_ctrl = ccb->ctrl;
598 u32 packets = 0, len = 0, totlen = 0;
599 u32 pi, vec, sop_ci = 0, nvecs = 0;
600 u32 flags, masked_flags;
602 prefetch(bnad->netdev);
606 while (packets < budget) {
607 cmpl = &cq[ccb->producer_index];
610 /* The 'valid' field is set by the adapter, only after writing
611 * the other fields of completion entry. Hence, do not load
612 * other fields of completion entry *before* the 'valid' is
613 * loaded. Adding the rmb() here prevents the compiler and/or
614 * CPU from reordering the reads which would potentially result
615 * in reading stale values in completion entry.
619 BNA_UPDATE_PKT_CNT(pkt_rt, ntohs(cmpl->length));
621 if (bna_is_small_rxq(cmpl->rxq_id))
626 unmap_q = rcb->unmap_q;
628 /* start of packet ci */
629 sop_ci = rcb->consumer_index;
631 if (BNAD_RXBUF_IS_SK_BUFF(unmap_q->type)) {
632 unmap = &unmap_q->unmap[sop_ci];
635 skb = napi_get_frags(&rx_ctrl->napi);
641 flags = ntohl(cmpl->flags);
642 len = ntohs(cmpl->length);
646 /* Check all the completions for this frame.
647 * busy-wait doesn't help much, break here.
649 if (BNAD_RXBUF_IS_MULTI_BUFF(unmap_q->type) &&
650 (flags & BNA_CQ_EF_EOP) == 0) {
651 pi = ccb->producer_index;
653 BNA_QE_INDX_INC(pi, ccb->q_depth);
656 if (!next_cmpl->valid)
658 /* The 'valid' field is set by the adapter, only
659 * after writing the other fields of completion
660 * entry. Hence, do not load other fields of
661 * completion entry *before* the 'valid' is
662 * loaded. Adding the rmb() here prevents the
663 * compiler and/or CPU from reordering the reads
664 * which would potentially result in reading
665 * stale values in completion entry.
669 len = ntohs(next_cmpl->length);
670 flags = ntohl(next_cmpl->flags);
674 } while ((flags & BNA_CQ_EF_EOP) == 0);
676 if (!next_cmpl->valid)
680 /* TODO: BNA_CQ_EF_LOCAL ? */
681 if (unlikely(flags & (BNA_CQ_EF_MAC_ERROR |
682 BNA_CQ_EF_FCS_ERROR |
683 BNA_CQ_EF_TOO_LONG))) {
684 bnad_cq_drop_packet(bnad, rcb, sop_ci, nvecs);
685 rcb->rxq->rx_packets_with_error++;
690 if (BNAD_RXBUF_IS_SK_BUFF(unmap_q->type))
691 bnad_cq_setup_skb(bnad, skb, unmap, len);
693 bnad_cq_setup_skb_frags(rcb, skb, sop_ci, nvecs, len);
696 rcb->rxq->rx_packets++;
697 rcb->rxq->rx_bytes += totlen;
698 ccb->bytes_per_intr += totlen;
700 masked_flags = flags & flags_cksum_prot_mask;
703 ((bnad->netdev->features & NETIF_F_RXCSUM) &&
704 ((masked_flags == flags_tcp4) ||
705 (masked_flags == flags_udp4) ||
706 (masked_flags == flags_tcp6) ||
707 (masked_flags == flags_udp6))))
708 skb->ip_summed = CHECKSUM_UNNECESSARY;
710 skb_checksum_none_assert(skb);
712 if ((flags & BNA_CQ_EF_VLAN) &&
713 (bnad->netdev->features & NETIF_F_HW_VLAN_CTAG_RX))
714 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), ntohs(cmpl->vlan_tag));
716 if (BNAD_RXBUF_IS_SK_BUFF(unmap_q->type))
717 netif_receive_skb(skb);
719 napi_gro_frags(&rx_ctrl->napi);
722 BNA_QE_INDX_ADD(rcb->consumer_index, nvecs, rcb->q_depth);
723 for (vec = 0; vec < nvecs; vec++) {
724 cmpl = &cq[ccb->producer_index];
726 BNA_QE_INDX_INC(ccb->producer_index, ccb->q_depth);
728 cmpl = &cq[ccb->producer_index];
731 napi_gro_flush(&rx_ctrl->napi, false);
732 if (likely(test_bit(BNAD_RXQ_STARTED, &ccb->rcb[0]->flags)))
733 bna_ib_ack_disable_irq(ccb->i_dbell, packets);
735 bnad_rxq_post(bnad, ccb->rcb[0]);
737 bnad_rxq_post(bnad, ccb->rcb[1]);
743 bnad_netif_rx_schedule_poll(struct bnad *bnad, struct bna_ccb *ccb)
745 struct bnad_rx_ctrl *rx_ctrl = (struct bnad_rx_ctrl *)(ccb->ctrl);
746 struct napi_struct *napi = &rx_ctrl->napi;
748 if (likely(napi_schedule_prep(napi))) {
749 __napi_schedule(napi);
750 rx_ctrl->rx_schedule++;
754 /* MSIX Rx Path Handler */
756 bnad_msix_rx(int irq, void *data)
758 struct bna_ccb *ccb = (struct bna_ccb *)data;
761 ((struct bnad_rx_ctrl *)(ccb->ctrl))->rx_intr_ctr++;
762 bnad_netif_rx_schedule_poll(ccb->bnad, ccb);
768 /* Interrupt handlers */
770 /* Mbox Interrupt Handlers */
772 bnad_msix_mbox_handler(int irq, void *data)
776 struct bnad *bnad = (struct bnad *)data;
778 spin_lock_irqsave(&bnad->bna_lock, flags);
779 if (unlikely(test_bit(BNAD_RF_MBOX_IRQ_DISABLED, &bnad->run_flags))) {
780 spin_unlock_irqrestore(&bnad->bna_lock, flags);
784 bna_intr_status_get(&bnad->bna, intr_status);
786 if (BNA_IS_MBOX_ERR_INTR(&bnad->bna, intr_status))
787 bna_mbox_handler(&bnad->bna, intr_status);
789 spin_unlock_irqrestore(&bnad->bna_lock, flags);
795 bnad_isr(int irq, void *data)
800 struct bnad *bnad = (struct bnad *)data;
801 struct bnad_rx_info *rx_info;
802 struct bnad_rx_ctrl *rx_ctrl;
803 struct bna_tcb *tcb = NULL;
805 spin_lock_irqsave(&bnad->bna_lock, flags);
806 if (unlikely(test_bit(BNAD_RF_MBOX_IRQ_DISABLED, &bnad->run_flags))) {
807 spin_unlock_irqrestore(&bnad->bna_lock, flags);
811 bna_intr_status_get(&bnad->bna, intr_status);
813 if (unlikely(!intr_status)) {
814 spin_unlock_irqrestore(&bnad->bna_lock, flags);
818 if (BNA_IS_MBOX_ERR_INTR(&bnad->bna, intr_status))
819 bna_mbox_handler(&bnad->bna, intr_status);
821 spin_unlock_irqrestore(&bnad->bna_lock, flags);
823 if (!BNA_IS_INTX_DATA_INTR(intr_status))
826 /* Process data interrupts */
828 for (i = 0; i < bnad->num_tx; i++) {
829 for (j = 0; j < bnad->num_txq_per_tx; j++) {
830 tcb = bnad->tx_info[i].tcb[j];
831 if (tcb && test_bit(BNAD_TXQ_TX_STARTED, &tcb->flags))
832 bnad_tx_complete(bnad, bnad->tx_info[i].tcb[j]);
836 for (i = 0; i < bnad->num_rx; i++) {
837 rx_info = &bnad->rx_info[i];
840 for (j = 0; j < bnad->num_rxp_per_rx; j++) {
841 rx_ctrl = &rx_info->rx_ctrl[j];
843 bnad_netif_rx_schedule_poll(bnad,
851 * Called in interrupt / callback context
852 * with bna_lock held, so cfg_flags access is OK
855 bnad_enable_mbox_irq(struct bnad *bnad)
857 clear_bit(BNAD_RF_MBOX_IRQ_DISABLED, &bnad->run_flags);
859 BNAD_UPDATE_CTR(bnad, mbox_intr_enabled);
863 * Called with bnad->bna_lock held b'cos of
864 * bnad->cfg_flags access.
867 bnad_disable_mbox_irq(struct bnad *bnad)
869 set_bit(BNAD_RF_MBOX_IRQ_DISABLED, &bnad->run_flags);
871 BNAD_UPDATE_CTR(bnad, mbox_intr_disabled);
875 bnad_set_netdev_perm_addr(struct bnad *bnad)
877 struct net_device *netdev = bnad->netdev;
879 ether_addr_copy(netdev->perm_addr, bnad->perm_addr);
880 if (is_zero_ether_addr(netdev->dev_addr))
881 ether_addr_copy(netdev->dev_addr, bnad->perm_addr);
884 /* Control Path Handlers */
888 bnad_cb_mbox_intr_enable(struct bnad *bnad)
890 bnad_enable_mbox_irq(bnad);
894 bnad_cb_mbox_intr_disable(struct bnad *bnad)
896 bnad_disable_mbox_irq(bnad);
900 bnad_cb_ioceth_ready(struct bnad *bnad)
902 bnad->bnad_completions.ioc_comp_status = BNA_CB_SUCCESS;
903 complete(&bnad->bnad_completions.ioc_comp);
907 bnad_cb_ioceth_failed(struct bnad *bnad)
909 bnad->bnad_completions.ioc_comp_status = BNA_CB_FAIL;
910 complete(&bnad->bnad_completions.ioc_comp);
914 bnad_cb_ioceth_disabled(struct bnad *bnad)
916 bnad->bnad_completions.ioc_comp_status = BNA_CB_SUCCESS;
917 complete(&bnad->bnad_completions.ioc_comp);
921 bnad_cb_enet_disabled(void *arg)
923 struct bnad *bnad = (struct bnad *)arg;
925 netif_carrier_off(bnad->netdev);
926 complete(&bnad->bnad_completions.enet_comp);
930 bnad_cb_ethport_link_status(struct bnad *bnad,
931 enum bna_link_status link_status)
933 bool link_up = false;
935 link_up = (link_status == BNA_LINK_UP) || (link_status == BNA_CEE_UP);
937 if (link_status == BNA_CEE_UP) {
938 if (!test_bit(BNAD_RF_CEE_RUNNING, &bnad->run_flags))
939 BNAD_UPDATE_CTR(bnad, cee_toggle);
940 set_bit(BNAD_RF_CEE_RUNNING, &bnad->run_flags);
942 if (test_bit(BNAD_RF_CEE_RUNNING, &bnad->run_flags))
943 BNAD_UPDATE_CTR(bnad, cee_toggle);
944 clear_bit(BNAD_RF_CEE_RUNNING, &bnad->run_flags);
948 if (!netif_carrier_ok(bnad->netdev)) {
950 printk(KERN_WARNING "bna: %s link up\n",
952 netif_carrier_on(bnad->netdev);
953 BNAD_UPDATE_CTR(bnad, link_toggle);
954 for (tx_id = 0; tx_id < bnad->num_tx; tx_id++) {
955 for (tcb_id = 0; tcb_id < bnad->num_txq_per_tx;
957 struct bna_tcb *tcb =
958 bnad->tx_info[tx_id].tcb[tcb_id];
965 if (test_bit(BNAD_TXQ_TX_STARTED,
969 * Transmit Schedule */
970 printk(KERN_INFO "bna: %s %d "
977 BNAD_UPDATE_CTR(bnad,
983 BNAD_UPDATE_CTR(bnad,
990 if (netif_carrier_ok(bnad->netdev)) {
991 printk(KERN_WARNING "bna: %s link down\n",
993 netif_carrier_off(bnad->netdev);
994 BNAD_UPDATE_CTR(bnad, link_toggle);
1000 bnad_cb_tx_disabled(void *arg, struct bna_tx *tx)
1002 struct bnad *bnad = (struct bnad *)arg;
1004 complete(&bnad->bnad_completions.tx_comp);
1008 bnad_cb_tcb_setup(struct bnad *bnad, struct bna_tcb *tcb)
1010 struct bnad_tx_info *tx_info =
1011 (struct bnad_tx_info *)tcb->txq->tx->priv;
1014 tx_info->tcb[tcb->id] = tcb;
1018 bnad_cb_tcb_destroy(struct bnad *bnad, struct bna_tcb *tcb)
1020 struct bnad_tx_info *tx_info =
1021 (struct bnad_tx_info *)tcb->txq->tx->priv;
1023 tx_info->tcb[tcb->id] = NULL;
1028 bnad_cb_ccb_setup(struct bnad *bnad, struct bna_ccb *ccb)
1030 struct bnad_rx_info *rx_info =
1031 (struct bnad_rx_info *)ccb->cq->rx->priv;
1033 rx_info->rx_ctrl[ccb->id].ccb = ccb;
1034 ccb->ctrl = &rx_info->rx_ctrl[ccb->id];
1038 bnad_cb_ccb_destroy(struct bnad *bnad, struct bna_ccb *ccb)
1040 struct bnad_rx_info *rx_info =
1041 (struct bnad_rx_info *)ccb->cq->rx->priv;
1043 rx_info->rx_ctrl[ccb->id].ccb = NULL;
1047 bnad_cb_tx_stall(struct bnad *bnad, struct bna_tx *tx)
1049 struct bnad_tx_info *tx_info =
1050 (struct bnad_tx_info *)tx->priv;
1051 struct bna_tcb *tcb;
1055 for (i = 0; i < BNAD_MAX_TXQ_PER_TX; i++) {
1056 tcb = tx_info->tcb[i];
1060 clear_bit(BNAD_TXQ_TX_STARTED, &tcb->flags);
1061 netif_stop_subqueue(bnad->netdev, txq_id);
1062 printk(KERN_INFO "bna: %s %d TXQ_STOPPED\n",
1063 bnad->netdev->name, txq_id);
1068 bnad_cb_tx_resume(struct bnad *bnad, struct bna_tx *tx)
1070 struct bnad_tx_info *tx_info = (struct bnad_tx_info *)tx->priv;
1071 struct bna_tcb *tcb;
1075 for (i = 0; i < BNAD_MAX_TXQ_PER_TX; i++) {
1076 tcb = tx_info->tcb[i];
1081 BUG_ON(test_bit(BNAD_TXQ_TX_STARTED, &tcb->flags));
1082 set_bit(BNAD_TXQ_TX_STARTED, &tcb->flags);
1083 BUG_ON(*(tcb->hw_consumer_index) != 0);
1085 if (netif_carrier_ok(bnad->netdev)) {
1086 printk(KERN_INFO "bna: %s %d TXQ_STARTED\n",
1087 bnad->netdev->name, txq_id);
1088 netif_wake_subqueue(bnad->netdev, txq_id);
1089 BNAD_UPDATE_CTR(bnad, netif_queue_wakeup);
1094 * Workaround for first ioceth enable failure & we
1095 * get a 0 MAC address. We try to get the MAC address
1098 if (is_zero_ether_addr(bnad->perm_addr)) {
1099 bna_enet_perm_mac_get(&bnad->bna.enet, bnad->perm_addr);
1100 bnad_set_netdev_perm_addr(bnad);
1105 * Free all TxQs buffers and then notify TX_E_CLEANUP_DONE to Tx fsm.
1108 bnad_tx_cleanup(struct delayed_work *work)
1110 struct bnad_tx_info *tx_info =
1111 container_of(work, struct bnad_tx_info, tx_cleanup_work);
1112 struct bnad *bnad = NULL;
1113 struct bna_tcb *tcb;
1114 unsigned long flags;
1117 for (i = 0; i < BNAD_MAX_TXQ_PER_TX; i++) {
1118 tcb = tx_info->tcb[i];
1124 if (test_and_set_bit(BNAD_TXQ_FREE_SENT, &tcb->flags)) {
1129 bnad_txq_cleanup(bnad, tcb);
1131 smp_mb__before_atomic();
1132 clear_bit(BNAD_TXQ_FREE_SENT, &tcb->flags);
1136 queue_delayed_work(bnad->work_q, &tx_info->tx_cleanup_work,
1137 msecs_to_jiffies(1));
1141 spin_lock_irqsave(&bnad->bna_lock, flags);
1142 bna_tx_cleanup_complete(tx_info->tx);
1143 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1147 bnad_cb_tx_cleanup(struct bnad *bnad, struct bna_tx *tx)
1149 struct bnad_tx_info *tx_info = (struct bnad_tx_info *)tx->priv;
1150 struct bna_tcb *tcb;
1153 for (i = 0; i < BNAD_MAX_TXQ_PER_TX; i++) {
1154 tcb = tx_info->tcb[i];
1159 queue_delayed_work(bnad->work_q, &tx_info->tx_cleanup_work, 0);
1163 bnad_cb_rx_stall(struct bnad *bnad, struct bna_rx *rx)
1165 struct bnad_rx_info *rx_info = (struct bnad_rx_info *)rx->priv;
1166 struct bna_ccb *ccb;
1167 struct bnad_rx_ctrl *rx_ctrl;
1170 for (i = 0; i < BNAD_MAX_RXP_PER_RX; i++) {
1171 rx_ctrl = &rx_info->rx_ctrl[i];
1176 clear_bit(BNAD_RXQ_POST_OK, &ccb->rcb[0]->flags);
1179 clear_bit(BNAD_RXQ_POST_OK, &ccb->rcb[1]->flags);
1184 * Free all RxQs buffers and then notify RX_E_CLEANUP_DONE to Rx fsm.
1187 bnad_rx_cleanup(void *work)
1189 struct bnad_rx_info *rx_info =
1190 container_of(work, struct bnad_rx_info, rx_cleanup_work);
1191 struct bnad_rx_ctrl *rx_ctrl;
1192 struct bnad *bnad = NULL;
1193 unsigned long flags;
1196 for (i = 0; i < BNAD_MAX_RXP_PER_RX; i++) {
1197 rx_ctrl = &rx_info->rx_ctrl[i];
1202 bnad = rx_ctrl->ccb->bnad;
1205 * Wait till the poll handler has exited
1206 * and nothing can be scheduled anymore
1208 napi_disable(&rx_ctrl->napi);
1210 bnad_cq_cleanup(bnad, rx_ctrl->ccb);
1211 bnad_rxq_cleanup(bnad, rx_ctrl->ccb->rcb[0]);
1212 if (rx_ctrl->ccb->rcb[1])
1213 bnad_rxq_cleanup(bnad, rx_ctrl->ccb->rcb[1]);
1216 spin_lock_irqsave(&bnad->bna_lock, flags);
1217 bna_rx_cleanup_complete(rx_info->rx);
1218 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1222 bnad_cb_rx_cleanup(struct bnad *bnad, struct bna_rx *rx)
1224 struct bnad_rx_info *rx_info = (struct bnad_rx_info *)rx->priv;
1225 struct bna_ccb *ccb;
1226 struct bnad_rx_ctrl *rx_ctrl;
1229 for (i = 0; i < BNAD_MAX_RXP_PER_RX; i++) {
1230 rx_ctrl = &rx_info->rx_ctrl[i];
1235 clear_bit(BNAD_RXQ_STARTED, &ccb->rcb[0]->flags);
1238 clear_bit(BNAD_RXQ_STARTED, &ccb->rcb[1]->flags);
1241 queue_work(bnad->work_q, &rx_info->rx_cleanup_work);
1245 bnad_cb_rx_post(struct bnad *bnad, struct bna_rx *rx)
1247 struct bnad_rx_info *rx_info = (struct bnad_rx_info *)rx->priv;
1248 struct bna_ccb *ccb;
1249 struct bna_rcb *rcb;
1250 struct bnad_rx_ctrl *rx_ctrl;
1253 for (i = 0; i < BNAD_MAX_RXP_PER_RX; i++) {
1254 rx_ctrl = &rx_info->rx_ctrl[i];
1259 napi_enable(&rx_ctrl->napi);
1261 for (j = 0; j < BNAD_MAX_RXQ_PER_RXP; j++) {
1266 bnad_rxq_alloc_init(bnad, rcb);
1267 set_bit(BNAD_RXQ_STARTED, &rcb->flags);
1268 set_bit(BNAD_RXQ_POST_OK, &rcb->flags);
1269 bnad_rxq_post(bnad, rcb);
1275 bnad_cb_rx_disabled(void *arg, struct bna_rx *rx)
1277 struct bnad *bnad = (struct bnad *)arg;
1279 complete(&bnad->bnad_completions.rx_comp);
1283 bnad_cb_rx_mcast_add(struct bnad *bnad, struct bna_rx *rx)
1285 bnad->bnad_completions.mcast_comp_status = BNA_CB_SUCCESS;
1286 complete(&bnad->bnad_completions.mcast_comp);
1290 bnad_cb_stats_get(struct bnad *bnad, enum bna_cb_status status,
1291 struct bna_stats *stats)
1293 if (status == BNA_CB_SUCCESS)
1294 BNAD_UPDATE_CTR(bnad, hw_stats_updates);
1296 if (!netif_running(bnad->netdev) ||
1297 !test_bit(BNAD_RF_STATS_TIMER_RUNNING, &bnad->run_flags))
1300 mod_timer(&bnad->stats_timer,
1301 jiffies + msecs_to_jiffies(BNAD_STATS_TIMER_FREQ));
1305 bnad_cb_enet_mtu_set(struct bnad *bnad)
1307 bnad->bnad_completions.mtu_comp_status = BNA_CB_SUCCESS;
1308 complete(&bnad->bnad_completions.mtu_comp);
1312 bnad_cb_completion(void *arg, enum bfa_status status)
1314 struct bnad_iocmd_comp *iocmd_comp =
1315 (struct bnad_iocmd_comp *)arg;
1317 iocmd_comp->comp_status = (u32) status;
1318 complete(&iocmd_comp->comp);
1321 /* Resource allocation, free functions */
1324 bnad_mem_free(struct bnad *bnad,
1325 struct bna_mem_info *mem_info)
1330 if (mem_info->mdl == NULL)
1333 for (i = 0; i < mem_info->num; i++) {
1334 if (mem_info->mdl[i].kva != NULL) {
1335 if (mem_info->mem_type == BNA_MEM_T_DMA) {
1336 BNA_GET_DMA_ADDR(&(mem_info->mdl[i].dma),
1338 dma_free_coherent(&bnad->pcidev->dev,
1339 mem_info->mdl[i].len,
1340 mem_info->mdl[i].kva, dma_pa);
1342 kfree(mem_info->mdl[i].kva);
1345 kfree(mem_info->mdl);
1346 mem_info->mdl = NULL;
1350 bnad_mem_alloc(struct bnad *bnad,
1351 struct bna_mem_info *mem_info)
1356 if ((mem_info->num == 0) || (mem_info->len == 0)) {
1357 mem_info->mdl = NULL;
1361 mem_info->mdl = kcalloc(mem_info->num, sizeof(struct bna_mem_descr),
1363 if (mem_info->mdl == NULL)
1366 if (mem_info->mem_type == BNA_MEM_T_DMA) {
1367 for (i = 0; i < mem_info->num; i++) {
1368 mem_info->mdl[i].len = mem_info->len;
1369 mem_info->mdl[i].kva =
1370 dma_alloc_coherent(&bnad->pcidev->dev,
1371 mem_info->len, &dma_pa,
1373 if (mem_info->mdl[i].kva == NULL)
1376 BNA_SET_DMA_ADDR(dma_pa,
1377 &(mem_info->mdl[i].dma));
1380 for (i = 0; i < mem_info->num; i++) {
1381 mem_info->mdl[i].len = mem_info->len;
1382 mem_info->mdl[i].kva = kzalloc(mem_info->len,
1384 if (mem_info->mdl[i].kva == NULL)
1392 bnad_mem_free(bnad, mem_info);
1396 /* Free IRQ for Mailbox */
1398 bnad_mbox_irq_free(struct bnad *bnad)
1401 unsigned long flags;
1403 spin_lock_irqsave(&bnad->bna_lock, flags);
1404 bnad_disable_mbox_irq(bnad);
1405 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1407 irq = BNAD_GET_MBOX_IRQ(bnad);
1408 free_irq(irq, bnad);
1412 * Allocates IRQ for Mailbox, but keep it disabled
1413 * This will be enabled once we get the mbox enable callback
1417 bnad_mbox_irq_alloc(struct bnad *bnad)
1420 unsigned long irq_flags, flags;
1422 irq_handler_t irq_handler;
1424 spin_lock_irqsave(&bnad->bna_lock, flags);
1425 if (bnad->cfg_flags & BNAD_CF_MSIX) {
1426 irq_handler = (irq_handler_t)bnad_msix_mbox_handler;
1427 irq = bnad->msix_table[BNAD_MAILBOX_MSIX_INDEX].vector;
1430 irq_handler = (irq_handler_t)bnad_isr;
1431 irq = bnad->pcidev->irq;
1432 irq_flags = IRQF_SHARED;
1435 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1436 sprintf(bnad->mbox_irq_name, "%s", BNAD_NAME);
1439 * Set the Mbox IRQ disable flag, so that the IRQ handler
1440 * called from request_irq() for SHARED IRQs do not execute
1442 set_bit(BNAD_RF_MBOX_IRQ_DISABLED, &bnad->run_flags);
1444 BNAD_UPDATE_CTR(bnad, mbox_intr_disabled);
1446 err = request_irq(irq, irq_handler, irq_flags,
1447 bnad->mbox_irq_name, bnad);
1453 bnad_txrx_irq_free(struct bnad *bnad, struct bna_intr_info *intr_info)
1455 kfree(intr_info->idl);
1456 intr_info->idl = NULL;
1459 /* Allocates Interrupt Descriptor List for MSIX/INT-X vectors */
1461 bnad_txrx_irq_alloc(struct bnad *bnad, enum bnad_intr_source src,
1462 u32 txrx_id, struct bna_intr_info *intr_info)
1464 int i, vector_start = 0;
1466 unsigned long flags;
1468 spin_lock_irqsave(&bnad->bna_lock, flags);
1469 cfg_flags = bnad->cfg_flags;
1470 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1472 if (cfg_flags & BNAD_CF_MSIX) {
1473 intr_info->intr_type = BNA_INTR_T_MSIX;
1474 intr_info->idl = kcalloc(intr_info->num,
1475 sizeof(struct bna_intr_descr),
1477 if (!intr_info->idl)
1482 vector_start = BNAD_MAILBOX_MSIX_VECTORS + txrx_id;
1486 vector_start = BNAD_MAILBOX_MSIX_VECTORS +
1487 (bnad->num_tx * bnad->num_txq_per_tx) +
1495 for (i = 0; i < intr_info->num; i++)
1496 intr_info->idl[i].vector = vector_start + i;
1498 intr_info->intr_type = BNA_INTR_T_INTX;
1500 intr_info->idl = kcalloc(intr_info->num,
1501 sizeof(struct bna_intr_descr),
1503 if (!intr_info->idl)
1508 intr_info->idl[0].vector = BNAD_INTX_TX_IB_BITMASK;
1512 intr_info->idl[0].vector = BNAD_INTX_RX_IB_BITMASK;
1519 /* NOTE: Should be called for MSIX only
1520 * Unregisters Tx MSIX vector(s) from the kernel
1523 bnad_tx_msix_unregister(struct bnad *bnad, struct bnad_tx_info *tx_info,
1529 for (i = 0; i < num_txqs; i++) {
1530 if (tx_info->tcb[i] == NULL)
1533 vector_num = tx_info->tcb[i]->intr_vector;
1534 free_irq(bnad->msix_table[vector_num].vector, tx_info->tcb[i]);
1538 /* NOTE: Should be called for MSIX only
1539 * Registers Tx MSIX vector(s) and ISR(s), cookie with the kernel
1542 bnad_tx_msix_register(struct bnad *bnad, struct bnad_tx_info *tx_info,
1543 u32 tx_id, int num_txqs)
1549 for (i = 0; i < num_txqs; i++) {
1550 vector_num = tx_info->tcb[i]->intr_vector;
1551 sprintf(tx_info->tcb[i]->name, "%s TXQ %d", bnad->netdev->name,
1552 tx_id + tx_info->tcb[i]->id);
1553 err = request_irq(bnad->msix_table[vector_num].vector,
1554 (irq_handler_t)bnad_msix_tx, 0,
1555 tx_info->tcb[i]->name,
1565 bnad_tx_msix_unregister(bnad, tx_info, (i - 1));
1569 /* NOTE: Should be called for MSIX only
1570 * Unregisters Rx MSIX vector(s) from the kernel
1573 bnad_rx_msix_unregister(struct bnad *bnad, struct bnad_rx_info *rx_info,
1579 for (i = 0; i < num_rxps; i++) {
1580 if (rx_info->rx_ctrl[i].ccb == NULL)
1583 vector_num = rx_info->rx_ctrl[i].ccb->intr_vector;
1584 free_irq(bnad->msix_table[vector_num].vector,
1585 rx_info->rx_ctrl[i].ccb);
1589 /* NOTE: Should be called for MSIX only
1590 * Registers Tx MSIX vector(s) and ISR(s), cookie with the kernel
1593 bnad_rx_msix_register(struct bnad *bnad, struct bnad_rx_info *rx_info,
1594 u32 rx_id, int num_rxps)
1600 for (i = 0; i < num_rxps; i++) {
1601 vector_num = rx_info->rx_ctrl[i].ccb->intr_vector;
1602 sprintf(rx_info->rx_ctrl[i].ccb->name, "%s CQ %d",
1604 rx_id + rx_info->rx_ctrl[i].ccb->id);
1605 err = request_irq(bnad->msix_table[vector_num].vector,
1606 (irq_handler_t)bnad_msix_rx, 0,
1607 rx_info->rx_ctrl[i].ccb->name,
1608 rx_info->rx_ctrl[i].ccb);
1617 bnad_rx_msix_unregister(bnad, rx_info, (i - 1));
1621 /* Free Tx object Resources */
1623 bnad_tx_res_free(struct bnad *bnad, struct bna_res_info *res_info)
1627 for (i = 0; i < BNA_TX_RES_T_MAX; i++) {
1628 if (res_info[i].res_type == BNA_RES_T_MEM)
1629 bnad_mem_free(bnad, &res_info[i].res_u.mem_info);
1630 else if (res_info[i].res_type == BNA_RES_T_INTR)
1631 bnad_txrx_irq_free(bnad, &res_info[i].res_u.intr_info);
1635 /* Allocates memory and interrupt resources for Tx object */
1637 bnad_tx_res_alloc(struct bnad *bnad, struct bna_res_info *res_info,
1642 for (i = 0; i < BNA_TX_RES_T_MAX; i++) {
1643 if (res_info[i].res_type == BNA_RES_T_MEM)
1644 err = bnad_mem_alloc(bnad,
1645 &res_info[i].res_u.mem_info);
1646 else if (res_info[i].res_type == BNA_RES_T_INTR)
1647 err = bnad_txrx_irq_alloc(bnad, BNAD_INTR_TX, tx_id,
1648 &res_info[i].res_u.intr_info);
1655 bnad_tx_res_free(bnad, res_info);
1659 /* Free Rx object Resources */
1661 bnad_rx_res_free(struct bnad *bnad, struct bna_res_info *res_info)
1665 for (i = 0; i < BNA_RX_RES_T_MAX; i++) {
1666 if (res_info[i].res_type == BNA_RES_T_MEM)
1667 bnad_mem_free(bnad, &res_info[i].res_u.mem_info);
1668 else if (res_info[i].res_type == BNA_RES_T_INTR)
1669 bnad_txrx_irq_free(bnad, &res_info[i].res_u.intr_info);
1673 /* Allocates memory and interrupt resources for Rx object */
1675 bnad_rx_res_alloc(struct bnad *bnad, struct bna_res_info *res_info,
1680 /* All memory needs to be allocated before setup_ccbs */
1681 for (i = 0; i < BNA_RX_RES_T_MAX; i++) {
1682 if (res_info[i].res_type == BNA_RES_T_MEM)
1683 err = bnad_mem_alloc(bnad,
1684 &res_info[i].res_u.mem_info);
1685 else if (res_info[i].res_type == BNA_RES_T_INTR)
1686 err = bnad_txrx_irq_alloc(bnad, BNAD_INTR_RX, rx_id,
1687 &res_info[i].res_u.intr_info);
1694 bnad_rx_res_free(bnad, res_info);
1698 /* Timer callbacks */
1701 bnad_ioc_timeout(unsigned long data)
1703 struct bnad *bnad = (struct bnad *)data;
1704 unsigned long flags;
1706 spin_lock_irqsave(&bnad->bna_lock, flags);
1707 bfa_nw_ioc_timeout((void *) &bnad->bna.ioceth.ioc);
1708 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1712 bnad_ioc_hb_check(unsigned long data)
1714 struct bnad *bnad = (struct bnad *)data;
1715 unsigned long flags;
1717 spin_lock_irqsave(&bnad->bna_lock, flags);
1718 bfa_nw_ioc_hb_check((void *) &bnad->bna.ioceth.ioc);
1719 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1723 bnad_iocpf_timeout(unsigned long data)
1725 struct bnad *bnad = (struct bnad *)data;
1726 unsigned long flags;
1728 spin_lock_irqsave(&bnad->bna_lock, flags);
1729 bfa_nw_iocpf_timeout((void *) &bnad->bna.ioceth.ioc);
1730 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1734 bnad_iocpf_sem_timeout(unsigned long data)
1736 struct bnad *bnad = (struct bnad *)data;
1737 unsigned long flags;
1739 spin_lock_irqsave(&bnad->bna_lock, flags);
1740 bfa_nw_iocpf_sem_timeout((void *) &bnad->bna.ioceth.ioc);
1741 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1745 * All timer routines use bnad->bna_lock to protect against
1746 * the following race, which may occur in case of no locking:
1754 /* b) Dynamic Interrupt Moderation Timer */
1756 bnad_dim_timeout(unsigned long data)
1758 struct bnad *bnad = (struct bnad *)data;
1759 struct bnad_rx_info *rx_info;
1760 struct bnad_rx_ctrl *rx_ctrl;
1762 unsigned long flags;
1764 if (!netif_carrier_ok(bnad->netdev))
1767 spin_lock_irqsave(&bnad->bna_lock, flags);
1768 for (i = 0; i < bnad->num_rx; i++) {
1769 rx_info = &bnad->rx_info[i];
1772 for (j = 0; j < bnad->num_rxp_per_rx; j++) {
1773 rx_ctrl = &rx_info->rx_ctrl[j];
1776 bna_rx_dim_update(rx_ctrl->ccb);
1780 /* Check for BNAD_CF_DIM_ENABLED, does not eleminate a race */
1781 if (test_bit(BNAD_RF_DIM_TIMER_RUNNING, &bnad->run_flags))
1782 mod_timer(&bnad->dim_timer,
1783 jiffies + msecs_to_jiffies(BNAD_DIM_TIMER_FREQ));
1784 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1787 /* c) Statistics Timer */
1789 bnad_stats_timeout(unsigned long data)
1791 struct bnad *bnad = (struct bnad *)data;
1792 unsigned long flags;
1794 if (!netif_running(bnad->netdev) ||
1795 !test_bit(BNAD_RF_STATS_TIMER_RUNNING, &bnad->run_flags))
1798 spin_lock_irqsave(&bnad->bna_lock, flags);
1799 bna_hw_stats_get(&bnad->bna);
1800 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1804 * Set up timer for DIM
1805 * Called with bnad->bna_lock held
1808 bnad_dim_timer_start(struct bnad *bnad)
1810 if (bnad->cfg_flags & BNAD_CF_DIM_ENABLED &&
1811 !test_bit(BNAD_RF_DIM_TIMER_RUNNING, &bnad->run_flags)) {
1812 setup_timer(&bnad->dim_timer, bnad_dim_timeout,
1813 (unsigned long)bnad);
1814 set_bit(BNAD_RF_DIM_TIMER_RUNNING, &bnad->run_flags);
1815 mod_timer(&bnad->dim_timer,
1816 jiffies + msecs_to_jiffies(BNAD_DIM_TIMER_FREQ));
1821 * Set up timer for statistics
1822 * Called with mutex_lock(&bnad->conf_mutex) held
1825 bnad_stats_timer_start(struct bnad *bnad)
1827 unsigned long flags;
1829 spin_lock_irqsave(&bnad->bna_lock, flags);
1830 if (!test_and_set_bit(BNAD_RF_STATS_TIMER_RUNNING, &bnad->run_flags)) {
1831 setup_timer(&bnad->stats_timer, bnad_stats_timeout,
1832 (unsigned long)bnad);
1833 mod_timer(&bnad->stats_timer,
1834 jiffies + msecs_to_jiffies(BNAD_STATS_TIMER_FREQ));
1836 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1840 * Stops the stats timer
1841 * Called with mutex_lock(&bnad->conf_mutex) held
1844 bnad_stats_timer_stop(struct bnad *bnad)
1847 unsigned long flags;
1849 spin_lock_irqsave(&bnad->bna_lock, flags);
1850 if (test_and_clear_bit(BNAD_RF_STATS_TIMER_RUNNING, &bnad->run_flags))
1852 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1854 del_timer_sync(&bnad->stats_timer);
1860 bnad_netdev_mc_list_get(struct net_device *netdev, u8 *mc_list)
1862 int i = 1; /* Index 0 has broadcast address */
1863 struct netdev_hw_addr *mc_addr;
1865 netdev_for_each_mc_addr(mc_addr, netdev) {
1866 ether_addr_copy(&mc_list[i * ETH_ALEN], &mc_addr->addr[0]);
1872 bnad_napi_poll_rx(struct napi_struct *napi, int budget)
1874 struct bnad_rx_ctrl *rx_ctrl =
1875 container_of(napi, struct bnad_rx_ctrl, napi);
1876 struct bnad *bnad = rx_ctrl->bnad;
1879 rx_ctrl->rx_poll_ctr++;
1881 if (!netif_carrier_ok(bnad->netdev))
1884 rcvd = bnad_cq_process(bnad, rx_ctrl->ccb, budget);
1889 napi_complete(napi);
1891 rx_ctrl->rx_complete++;
1894 bnad_enable_rx_irq_unsafe(rx_ctrl->ccb);
1899 #define BNAD_NAPI_POLL_QUOTA 64
1901 bnad_napi_add(struct bnad *bnad, u32 rx_id)
1903 struct bnad_rx_ctrl *rx_ctrl;
1906 /* Initialize & enable NAPI */
1907 for (i = 0; i < bnad->num_rxp_per_rx; i++) {
1908 rx_ctrl = &bnad->rx_info[rx_id].rx_ctrl[i];
1909 netif_napi_add(bnad->netdev, &rx_ctrl->napi,
1910 bnad_napi_poll_rx, BNAD_NAPI_POLL_QUOTA);
1915 bnad_napi_delete(struct bnad *bnad, u32 rx_id)
1919 /* First disable and then clean up */
1920 for (i = 0; i < bnad->num_rxp_per_rx; i++)
1921 netif_napi_del(&bnad->rx_info[rx_id].rx_ctrl[i].napi);
1924 /* Should be held with conf_lock held */
1926 bnad_destroy_tx(struct bnad *bnad, u32 tx_id)
1928 struct bnad_tx_info *tx_info = &bnad->tx_info[tx_id];
1929 struct bna_res_info *res_info = &bnad->tx_res_info[tx_id].res_info[0];
1930 unsigned long flags;
1935 init_completion(&bnad->bnad_completions.tx_comp);
1936 spin_lock_irqsave(&bnad->bna_lock, flags);
1937 bna_tx_disable(tx_info->tx, BNA_HARD_CLEANUP, bnad_cb_tx_disabled);
1938 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1939 wait_for_completion(&bnad->bnad_completions.tx_comp);
1941 if (tx_info->tcb[0]->intr_type == BNA_INTR_T_MSIX)
1942 bnad_tx_msix_unregister(bnad, tx_info,
1943 bnad->num_txq_per_tx);
1945 spin_lock_irqsave(&bnad->bna_lock, flags);
1946 bna_tx_destroy(tx_info->tx);
1947 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1952 bnad_tx_res_free(bnad, res_info);
1955 /* Should be held with conf_lock held */
1957 bnad_setup_tx(struct bnad *bnad, u32 tx_id)
1960 struct bnad_tx_info *tx_info = &bnad->tx_info[tx_id];
1961 struct bna_res_info *res_info = &bnad->tx_res_info[tx_id].res_info[0];
1962 struct bna_intr_info *intr_info =
1963 &res_info[BNA_TX_RES_INTR_T_TXCMPL].res_u.intr_info;
1964 struct bna_tx_config *tx_config = &bnad->tx_config[tx_id];
1965 static const struct bna_tx_event_cbfn tx_cbfn = {
1966 .tcb_setup_cbfn = bnad_cb_tcb_setup,
1967 .tcb_destroy_cbfn = bnad_cb_tcb_destroy,
1968 .tx_stall_cbfn = bnad_cb_tx_stall,
1969 .tx_resume_cbfn = bnad_cb_tx_resume,
1970 .tx_cleanup_cbfn = bnad_cb_tx_cleanup,
1974 unsigned long flags;
1976 tx_info->tx_id = tx_id;
1978 /* Initialize the Tx object configuration */
1979 tx_config->num_txq = bnad->num_txq_per_tx;
1980 tx_config->txq_depth = bnad->txq_depth;
1981 tx_config->tx_type = BNA_TX_T_REGULAR;
1982 tx_config->coalescing_timeo = bnad->tx_coalescing_timeo;
1984 /* Get BNA's resource requirement for one tx object */
1985 spin_lock_irqsave(&bnad->bna_lock, flags);
1986 bna_tx_res_req(bnad->num_txq_per_tx,
1987 bnad->txq_depth, res_info);
1988 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1990 /* Fill Unmap Q memory requirements */
1991 BNAD_FILL_UNMAPQ_MEM_REQ(&res_info[BNA_TX_RES_MEM_T_UNMAPQ],
1992 bnad->num_txq_per_tx, (sizeof(struct bnad_tx_unmap) *
1995 /* Allocate resources */
1996 err = bnad_tx_res_alloc(bnad, res_info, tx_id);
2000 /* Ask BNA to create one Tx object, supplying required resources */
2001 spin_lock_irqsave(&bnad->bna_lock, flags);
2002 tx = bna_tx_create(&bnad->bna, bnad, tx_config, &tx_cbfn, res_info,
2004 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2011 INIT_DELAYED_WORK(&tx_info->tx_cleanup_work,
2012 (work_func_t)bnad_tx_cleanup);
2014 /* Register ISR for the Tx object */
2015 if (intr_info->intr_type == BNA_INTR_T_MSIX) {
2016 err = bnad_tx_msix_register(bnad, tx_info,
2017 tx_id, bnad->num_txq_per_tx);
2022 spin_lock_irqsave(&bnad->bna_lock, flags);
2024 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2029 spin_lock_irqsave(&bnad->bna_lock, flags);
2030 bna_tx_destroy(tx_info->tx);
2031 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2035 bnad_tx_res_free(bnad, res_info);
2039 /* Setup the rx config for bna_rx_create */
2040 /* bnad decides the configuration */
2042 bnad_init_rx_config(struct bnad *bnad, struct bna_rx_config *rx_config)
2044 memset(rx_config, 0, sizeof(*rx_config));
2045 rx_config->rx_type = BNA_RX_T_REGULAR;
2046 rx_config->num_paths = bnad->num_rxp_per_rx;
2047 rx_config->coalescing_timeo = bnad->rx_coalescing_timeo;
2049 if (bnad->num_rxp_per_rx > 1) {
2050 rx_config->rss_status = BNA_STATUS_T_ENABLED;
2051 rx_config->rss_config.hash_type =
2052 (BFI_ENET_RSS_IPV6 |
2053 BFI_ENET_RSS_IPV6_TCP |
2055 BFI_ENET_RSS_IPV4_TCP);
2056 rx_config->rss_config.hash_mask =
2057 bnad->num_rxp_per_rx - 1;
2058 netdev_rss_key_fill(rx_config->rss_config.toeplitz_hash_key,
2059 sizeof(rx_config->rss_config.toeplitz_hash_key));
2061 rx_config->rss_status = BNA_STATUS_T_DISABLED;
2062 memset(&rx_config->rss_config, 0,
2063 sizeof(rx_config->rss_config));
2066 rx_config->frame_size = BNAD_FRAME_SIZE(bnad->netdev->mtu);
2067 rx_config->q0_multi_buf = BNA_STATUS_T_DISABLED;
2069 /* BNA_RXP_SINGLE - one data-buffer queue
2070 * BNA_RXP_SLR - one small-buffer and one large-buffer queues
2071 * BNA_RXP_HDS - one header-buffer and one data-buffer queues
2073 /* TODO: configurable param for queue type */
2074 rx_config->rxp_type = BNA_RXP_SLR;
2076 if (BNAD_PCI_DEV_IS_CAT2(bnad) &&
2077 rx_config->frame_size > 4096) {
2078 /* though size_routing_enable is set in SLR,
2079 * small packets may get routed to same rxq.
2080 * set buf_size to 2048 instead of PAGE_SIZE.
2082 rx_config->q0_buf_size = 2048;
2083 /* this should be in multiples of 2 */
2084 rx_config->q0_num_vecs = 4;
2085 rx_config->q0_depth = bnad->rxq_depth * rx_config->q0_num_vecs;
2086 rx_config->q0_multi_buf = BNA_STATUS_T_ENABLED;
2088 rx_config->q0_buf_size = rx_config->frame_size;
2089 rx_config->q0_num_vecs = 1;
2090 rx_config->q0_depth = bnad->rxq_depth;
2093 /* initialize for q1 for BNA_RXP_SLR/BNA_RXP_HDS */
2094 if (rx_config->rxp_type == BNA_RXP_SLR) {
2095 rx_config->q1_depth = bnad->rxq_depth;
2096 rx_config->q1_buf_size = BFI_SMALL_RXBUF_SIZE;
2099 rx_config->vlan_strip_status =
2100 (bnad->netdev->features & NETIF_F_HW_VLAN_CTAG_RX) ?
2101 BNA_STATUS_T_ENABLED : BNA_STATUS_T_DISABLED;
2105 bnad_rx_ctrl_init(struct bnad *bnad, u32 rx_id)
2107 struct bnad_rx_info *rx_info = &bnad->rx_info[rx_id];
2110 for (i = 0; i < bnad->num_rxp_per_rx; i++)
2111 rx_info->rx_ctrl[i].bnad = bnad;
2114 /* Called with mutex_lock(&bnad->conf_mutex) held */
2116 bnad_reinit_rx(struct bnad *bnad)
2118 struct net_device *netdev = bnad->netdev;
2119 u32 err = 0, current_err = 0;
2120 u32 rx_id = 0, count = 0;
2121 unsigned long flags;
2123 /* destroy and create new rx objects */
2124 for (rx_id = 0; rx_id < bnad->num_rx; rx_id++) {
2125 if (!bnad->rx_info[rx_id].rx)
2127 bnad_destroy_rx(bnad, rx_id);
2130 spin_lock_irqsave(&bnad->bna_lock, flags);
2131 bna_enet_mtu_set(&bnad->bna.enet,
2132 BNAD_FRAME_SIZE(bnad->netdev->mtu), NULL);
2133 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2135 for (rx_id = 0; rx_id < bnad->num_rx; rx_id++) {
2137 current_err = bnad_setup_rx(bnad, rx_id);
2138 if (current_err && !err) {
2140 pr_err("RXQ:%u setup failed\n", rx_id);
2144 /* restore rx configuration */
2145 if (bnad->rx_info[0].rx && !err) {
2146 bnad_restore_vlans(bnad, 0);
2147 bnad_enable_default_bcast(bnad);
2148 spin_lock_irqsave(&bnad->bna_lock, flags);
2149 bnad_mac_addr_set_locked(bnad, netdev->dev_addr);
2150 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2151 bnad_set_rx_mode(netdev);
2157 /* Called with bnad_conf_lock() held */
2159 bnad_destroy_rx(struct bnad *bnad, u32 rx_id)
2161 struct bnad_rx_info *rx_info = &bnad->rx_info[rx_id];
2162 struct bna_rx_config *rx_config = &bnad->rx_config[rx_id];
2163 struct bna_res_info *res_info = &bnad->rx_res_info[rx_id].res_info[0];
2164 unsigned long flags;
2171 spin_lock_irqsave(&bnad->bna_lock, flags);
2172 if (bnad->cfg_flags & BNAD_CF_DIM_ENABLED &&
2173 test_bit(BNAD_RF_DIM_TIMER_RUNNING, &bnad->run_flags)) {
2174 clear_bit(BNAD_RF_DIM_TIMER_RUNNING, &bnad->run_flags);
2177 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2179 del_timer_sync(&bnad->dim_timer);
2182 init_completion(&bnad->bnad_completions.rx_comp);
2183 spin_lock_irqsave(&bnad->bna_lock, flags);
2184 bna_rx_disable(rx_info->rx, BNA_HARD_CLEANUP, bnad_cb_rx_disabled);
2185 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2186 wait_for_completion(&bnad->bnad_completions.rx_comp);
2188 if (rx_info->rx_ctrl[0].ccb->intr_type == BNA_INTR_T_MSIX)
2189 bnad_rx_msix_unregister(bnad, rx_info, rx_config->num_paths);
2191 bnad_napi_delete(bnad, rx_id);
2193 spin_lock_irqsave(&bnad->bna_lock, flags);
2194 bna_rx_destroy(rx_info->rx);
2198 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2200 bnad_rx_res_free(bnad, res_info);
2203 /* Called with mutex_lock(&bnad->conf_mutex) held */
2205 bnad_setup_rx(struct bnad *bnad, u32 rx_id)
2208 struct bnad_rx_info *rx_info = &bnad->rx_info[rx_id];
2209 struct bna_res_info *res_info = &bnad->rx_res_info[rx_id].res_info[0];
2210 struct bna_intr_info *intr_info =
2211 &res_info[BNA_RX_RES_T_INTR].res_u.intr_info;
2212 struct bna_rx_config *rx_config = &bnad->rx_config[rx_id];
2213 static const struct bna_rx_event_cbfn rx_cbfn = {
2214 .rcb_setup_cbfn = NULL,
2215 .rcb_destroy_cbfn = NULL,
2216 .ccb_setup_cbfn = bnad_cb_ccb_setup,
2217 .ccb_destroy_cbfn = bnad_cb_ccb_destroy,
2218 .rx_stall_cbfn = bnad_cb_rx_stall,
2219 .rx_cleanup_cbfn = bnad_cb_rx_cleanup,
2220 .rx_post_cbfn = bnad_cb_rx_post,
2223 unsigned long flags;
2225 rx_info->rx_id = rx_id;
2227 /* Initialize the Rx object configuration */
2228 bnad_init_rx_config(bnad, rx_config);
2230 /* Get BNA's resource requirement for one Rx object */
2231 spin_lock_irqsave(&bnad->bna_lock, flags);
2232 bna_rx_res_req(rx_config, res_info);
2233 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2235 /* Fill Unmap Q memory requirements */
2236 BNAD_FILL_UNMAPQ_MEM_REQ(&res_info[BNA_RX_RES_MEM_T_UNMAPDQ],
2237 rx_config->num_paths,
2238 (rx_config->q0_depth *
2239 sizeof(struct bnad_rx_unmap)) +
2240 sizeof(struct bnad_rx_unmap_q));
2242 if (rx_config->rxp_type != BNA_RXP_SINGLE) {
2243 BNAD_FILL_UNMAPQ_MEM_REQ(&res_info[BNA_RX_RES_MEM_T_UNMAPHQ],
2244 rx_config->num_paths,
2245 (rx_config->q1_depth *
2246 sizeof(struct bnad_rx_unmap) +
2247 sizeof(struct bnad_rx_unmap_q)));
2249 /* Allocate resource */
2250 err = bnad_rx_res_alloc(bnad, res_info, rx_id);
2254 bnad_rx_ctrl_init(bnad, rx_id);
2256 /* Ask BNA to create one Rx object, supplying required resources */
2257 spin_lock_irqsave(&bnad->bna_lock, flags);
2258 rx = bna_rx_create(&bnad->bna, bnad, rx_config, &rx_cbfn, res_info,
2262 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2266 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2268 INIT_WORK(&rx_info->rx_cleanup_work,
2269 (work_func_t)(bnad_rx_cleanup));
2272 * Init NAPI, so that state is set to NAPI_STATE_SCHED,
2273 * so that IRQ handler cannot schedule NAPI at this point.
2275 bnad_napi_add(bnad, rx_id);
2277 /* Register ISR for the Rx object */
2278 if (intr_info->intr_type == BNA_INTR_T_MSIX) {
2279 err = bnad_rx_msix_register(bnad, rx_info, rx_id,
2280 rx_config->num_paths);
2285 spin_lock_irqsave(&bnad->bna_lock, flags);
2287 /* Set up Dynamic Interrupt Moderation Vector */
2288 if (bnad->cfg_flags & BNAD_CF_DIM_ENABLED)
2289 bna_rx_dim_reconfig(&bnad->bna, bna_napi_dim_vector);
2291 /* Enable VLAN filtering only on the default Rx */
2292 bna_rx_vlanfilter_enable(rx);
2294 /* Start the DIM timer */
2295 bnad_dim_timer_start(bnad);
2299 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2304 bnad_destroy_rx(bnad, rx_id);
2308 /* Called with conf_lock & bnad->bna_lock held */
2310 bnad_tx_coalescing_timeo_set(struct bnad *bnad)
2312 struct bnad_tx_info *tx_info;
2314 tx_info = &bnad->tx_info[0];
2318 bna_tx_coalescing_timeo_set(tx_info->tx, bnad->tx_coalescing_timeo);
2321 /* Called with conf_lock & bnad->bna_lock held */
2323 bnad_rx_coalescing_timeo_set(struct bnad *bnad)
2325 struct bnad_rx_info *rx_info;
2328 for (i = 0; i < bnad->num_rx; i++) {
2329 rx_info = &bnad->rx_info[i];
2332 bna_rx_coalescing_timeo_set(rx_info->rx,
2333 bnad->rx_coalescing_timeo);
2338 * Called with bnad->bna_lock held
2341 bnad_mac_addr_set_locked(struct bnad *bnad, u8 *mac_addr)
2345 if (!is_valid_ether_addr(mac_addr))
2346 return -EADDRNOTAVAIL;
2348 /* If datapath is down, pretend everything went through */
2349 if (!bnad->rx_info[0].rx)
2352 ret = bna_rx_ucast_set(bnad->rx_info[0].rx, mac_addr);
2353 if (ret != BNA_CB_SUCCESS)
2354 return -EADDRNOTAVAIL;
2359 /* Should be called with conf_lock held */
2361 bnad_enable_default_bcast(struct bnad *bnad)
2363 struct bnad_rx_info *rx_info = &bnad->rx_info[0];
2365 unsigned long flags;
2367 init_completion(&bnad->bnad_completions.mcast_comp);
2369 spin_lock_irqsave(&bnad->bna_lock, flags);
2370 ret = bna_rx_mcast_add(rx_info->rx, (u8 *)bnad_bcast_addr,
2371 bnad_cb_rx_mcast_add);
2372 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2374 if (ret == BNA_CB_SUCCESS)
2375 wait_for_completion(&bnad->bnad_completions.mcast_comp);
2379 if (bnad->bnad_completions.mcast_comp_status != BNA_CB_SUCCESS)
2385 /* Called with mutex_lock(&bnad->conf_mutex) held */
2387 bnad_restore_vlans(struct bnad *bnad, u32 rx_id)
2390 unsigned long flags;
2392 for_each_set_bit(vid, bnad->active_vlans, VLAN_N_VID) {
2393 spin_lock_irqsave(&bnad->bna_lock, flags);
2394 bna_rx_vlan_add(bnad->rx_info[rx_id].rx, vid);
2395 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2399 /* Statistics utilities */
2401 bnad_netdev_qstats_fill(struct bnad *bnad, struct rtnl_link_stats64 *stats)
2405 for (i = 0; i < bnad->num_rx; i++) {
2406 for (j = 0; j < bnad->num_rxp_per_rx; j++) {
2407 if (bnad->rx_info[i].rx_ctrl[j].ccb) {
2408 stats->rx_packets += bnad->rx_info[i].
2409 rx_ctrl[j].ccb->rcb[0]->rxq->rx_packets;
2410 stats->rx_bytes += bnad->rx_info[i].
2411 rx_ctrl[j].ccb->rcb[0]->rxq->rx_bytes;
2412 if (bnad->rx_info[i].rx_ctrl[j].ccb->rcb[1] &&
2413 bnad->rx_info[i].rx_ctrl[j].ccb->
2415 stats->rx_packets +=
2416 bnad->rx_info[i].rx_ctrl[j].
2417 ccb->rcb[1]->rxq->rx_packets;
2419 bnad->rx_info[i].rx_ctrl[j].
2420 ccb->rcb[1]->rxq->rx_bytes;
2425 for (i = 0; i < bnad->num_tx; i++) {
2426 for (j = 0; j < bnad->num_txq_per_tx; j++) {
2427 if (bnad->tx_info[i].tcb[j]) {
2428 stats->tx_packets +=
2429 bnad->tx_info[i].tcb[j]->txq->tx_packets;
2431 bnad->tx_info[i].tcb[j]->txq->tx_bytes;
2438 * Must be called with the bna_lock held.
2441 bnad_netdev_hwstats_fill(struct bnad *bnad, struct rtnl_link_stats64 *stats)
2443 struct bfi_enet_stats_mac *mac_stats;
2447 mac_stats = &bnad->stats.bna_stats->hw_stats.mac_stats;
2449 mac_stats->rx_fcs_error + mac_stats->rx_alignment_error +
2450 mac_stats->rx_frame_length_error + mac_stats->rx_code_error +
2451 mac_stats->rx_undersize;
2452 stats->tx_errors = mac_stats->tx_fcs_error +
2453 mac_stats->tx_undersize;
2454 stats->rx_dropped = mac_stats->rx_drop;
2455 stats->tx_dropped = mac_stats->tx_drop;
2456 stats->multicast = mac_stats->rx_multicast;
2457 stats->collisions = mac_stats->tx_total_collision;
2459 stats->rx_length_errors = mac_stats->rx_frame_length_error;
2461 /* receive ring buffer overflow ?? */
2463 stats->rx_crc_errors = mac_stats->rx_fcs_error;
2464 stats->rx_frame_errors = mac_stats->rx_alignment_error;
2465 /* recv'r fifo overrun */
2466 bmap = bna_rx_rid_mask(&bnad->bna);
2467 for (i = 0; bmap; i++) {
2469 stats->rx_fifo_errors +=
2470 bnad->stats.bna_stats->
2471 hw_stats.rxf_stats[i].frame_drops;
2479 bnad_mbox_irq_sync(struct bnad *bnad)
2482 unsigned long flags;
2484 spin_lock_irqsave(&bnad->bna_lock, flags);
2485 if (bnad->cfg_flags & BNAD_CF_MSIX)
2486 irq = bnad->msix_table[BNAD_MAILBOX_MSIX_INDEX].vector;
2488 irq = bnad->pcidev->irq;
2489 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2491 synchronize_irq(irq);
2494 /* Utility used by bnad_start_xmit, for doing TSO */
2496 bnad_tso_prepare(struct bnad *bnad, struct sk_buff *skb)
2500 err = skb_cow_head(skb, 0);
2502 BNAD_UPDATE_CTR(bnad, tso_err);
2507 * For TSO, the TCP checksum field is seeded with pseudo-header sum
2508 * excluding the length field.
2510 if (vlan_get_protocol(skb) == htons(ETH_P_IP)) {
2511 struct iphdr *iph = ip_hdr(skb);
2513 /* Do we really need these? */
2517 tcp_hdr(skb)->check =
2518 ~csum_tcpudp_magic(iph->saddr, iph->daddr, 0,
2520 BNAD_UPDATE_CTR(bnad, tso4);
2522 struct ipv6hdr *ipv6h = ipv6_hdr(skb);
2524 ipv6h->payload_len = 0;
2525 tcp_hdr(skb)->check =
2526 ~csum_ipv6_magic(&ipv6h->saddr, &ipv6h->daddr, 0,
2528 BNAD_UPDATE_CTR(bnad, tso6);
2535 * Initialize Q numbers depending on Rx Paths
2536 * Called with bnad->bna_lock held, because of cfg_flags
2540 bnad_q_num_init(struct bnad *bnad)
2544 rxps = min((uint)num_online_cpus(),
2545 (uint)(BNAD_MAX_RX * BNAD_MAX_RXP_PER_RX));
2547 if (!(bnad->cfg_flags & BNAD_CF_MSIX))
2548 rxps = 1; /* INTx */
2552 bnad->num_rxp_per_rx = rxps;
2553 bnad->num_txq_per_tx = BNAD_TXQ_NUM;
2557 * Adjusts the Q numbers, given a number of msix vectors
2558 * Give preference to RSS as opposed to Tx priority Queues,
2559 * in such a case, just use 1 Tx Q
2560 * Called with bnad->bna_lock held b'cos of cfg_flags access
2563 bnad_q_num_adjust(struct bnad *bnad, int msix_vectors, int temp)
2565 bnad->num_txq_per_tx = 1;
2566 if ((msix_vectors >= (bnad->num_tx * bnad->num_txq_per_tx) +
2567 bnad_rxqs_per_cq + BNAD_MAILBOX_MSIX_VECTORS) &&
2568 (bnad->cfg_flags & BNAD_CF_MSIX)) {
2569 bnad->num_rxp_per_rx = msix_vectors -
2570 (bnad->num_tx * bnad->num_txq_per_tx) -
2571 BNAD_MAILBOX_MSIX_VECTORS;
2573 bnad->num_rxp_per_rx = 1;
2576 /* Enable / disable ioceth */
2578 bnad_ioceth_disable(struct bnad *bnad)
2580 unsigned long flags;
2583 spin_lock_irqsave(&bnad->bna_lock, flags);
2584 init_completion(&bnad->bnad_completions.ioc_comp);
2585 bna_ioceth_disable(&bnad->bna.ioceth, BNA_HARD_CLEANUP);
2586 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2588 wait_for_completion_timeout(&bnad->bnad_completions.ioc_comp,
2589 msecs_to_jiffies(BNAD_IOCETH_TIMEOUT));
2591 err = bnad->bnad_completions.ioc_comp_status;
2596 bnad_ioceth_enable(struct bnad *bnad)
2599 unsigned long flags;
2601 spin_lock_irqsave(&bnad->bna_lock, flags);
2602 init_completion(&bnad->bnad_completions.ioc_comp);
2603 bnad->bnad_completions.ioc_comp_status = BNA_CB_WAITING;
2604 bna_ioceth_enable(&bnad->bna.ioceth);
2605 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2607 wait_for_completion_timeout(&bnad->bnad_completions.ioc_comp,
2608 msecs_to_jiffies(BNAD_IOCETH_TIMEOUT));
2610 err = bnad->bnad_completions.ioc_comp_status;
2615 /* Free BNA resources */
2617 bnad_res_free(struct bnad *bnad, struct bna_res_info *res_info,
2622 for (i = 0; i < res_val_max; i++)
2623 bnad_mem_free(bnad, &res_info[i].res_u.mem_info);
2626 /* Allocates memory and interrupt resources for BNA */
2628 bnad_res_alloc(struct bnad *bnad, struct bna_res_info *res_info,
2633 for (i = 0; i < res_val_max; i++) {
2634 err = bnad_mem_alloc(bnad, &res_info[i].res_u.mem_info);
2641 bnad_res_free(bnad, res_info, res_val_max);
2645 /* Interrupt enable / disable */
2647 bnad_enable_msix(struct bnad *bnad)
2650 unsigned long flags;
2652 spin_lock_irqsave(&bnad->bna_lock, flags);
2653 if (!(bnad->cfg_flags & BNAD_CF_MSIX)) {
2654 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2657 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2659 if (bnad->msix_table)
2663 kcalloc(bnad->msix_num, sizeof(struct msix_entry), GFP_KERNEL);
2665 if (!bnad->msix_table)
2668 for (i = 0; i < bnad->msix_num; i++)
2669 bnad->msix_table[i].entry = i;
2671 ret = pci_enable_msix_range(bnad->pcidev, bnad->msix_table,
2675 } else if (ret < bnad->msix_num) {
2676 pr_warn("BNA: %d MSI-X vectors allocated < %d requested\n",
2677 ret, bnad->msix_num);
2679 spin_lock_irqsave(&bnad->bna_lock, flags);
2680 /* ret = #of vectors that we got */
2681 bnad_q_num_adjust(bnad, (ret - BNAD_MAILBOX_MSIX_VECTORS) / 2,
2682 (ret - BNAD_MAILBOX_MSIX_VECTORS) / 2);
2683 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2685 bnad->msix_num = BNAD_NUM_TXQ + BNAD_NUM_RXP +
2686 BNAD_MAILBOX_MSIX_VECTORS;
2688 if (bnad->msix_num > ret) {
2689 pci_disable_msix(bnad->pcidev);
2694 pci_intx(bnad->pcidev, 0);
2699 pr_warn("BNA: MSI-X enable failed - operating in INTx mode\n");
2701 kfree(bnad->msix_table);
2702 bnad->msix_table = NULL;
2704 spin_lock_irqsave(&bnad->bna_lock, flags);
2705 bnad->cfg_flags &= ~BNAD_CF_MSIX;
2706 bnad_q_num_init(bnad);
2707 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2711 bnad_disable_msix(struct bnad *bnad)
2714 unsigned long flags;
2716 spin_lock_irqsave(&bnad->bna_lock, flags);
2717 cfg_flags = bnad->cfg_flags;
2718 if (bnad->cfg_flags & BNAD_CF_MSIX)
2719 bnad->cfg_flags &= ~BNAD_CF_MSIX;
2720 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2722 if (cfg_flags & BNAD_CF_MSIX) {
2723 pci_disable_msix(bnad->pcidev);
2724 kfree(bnad->msix_table);
2725 bnad->msix_table = NULL;
2729 /* Netdev entry points */
2731 bnad_open(struct net_device *netdev)
2734 struct bnad *bnad = netdev_priv(netdev);
2735 struct bna_pause_config pause_config;
2736 unsigned long flags;
2738 mutex_lock(&bnad->conf_mutex);
2741 err = bnad_setup_tx(bnad, 0);
2746 err = bnad_setup_rx(bnad, 0);
2751 pause_config.tx_pause = 0;
2752 pause_config.rx_pause = 0;
2754 spin_lock_irqsave(&bnad->bna_lock, flags);
2755 bna_enet_mtu_set(&bnad->bna.enet,
2756 BNAD_FRAME_SIZE(bnad->netdev->mtu), NULL);
2757 bna_enet_pause_config(&bnad->bna.enet, &pause_config);
2758 bna_enet_enable(&bnad->bna.enet);
2759 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2761 /* Enable broadcast */
2762 bnad_enable_default_bcast(bnad);
2764 /* Restore VLANs, if any */
2765 bnad_restore_vlans(bnad, 0);
2767 /* Set the UCAST address */
2768 spin_lock_irqsave(&bnad->bna_lock, flags);
2769 bnad_mac_addr_set_locked(bnad, netdev->dev_addr);
2770 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2772 /* Start the stats timer */
2773 bnad_stats_timer_start(bnad);
2775 mutex_unlock(&bnad->conf_mutex);
2780 bnad_destroy_tx(bnad, 0);
2783 mutex_unlock(&bnad->conf_mutex);
2788 bnad_stop(struct net_device *netdev)
2790 struct bnad *bnad = netdev_priv(netdev);
2791 unsigned long flags;
2793 mutex_lock(&bnad->conf_mutex);
2795 /* Stop the stats timer */
2796 bnad_stats_timer_stop(bnad);
2798 init_completion(&bnad->bnad_completions.enet_comp);
2800 spin_lock_irqsave(&bnad->bna_lock, flags);
2801 bna_enet_disable(&bnad->bna.enet, BNA_HARD_CLEANUP,
2802 bnad_cb_enet_disabled);
2803 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2805 wait_for_completion(&bnad->bnad_completions.enet_comp);
2807 bnad_destroy_tx(bnad, 0);
2808 bnad_destroy_rx(bnad, 0);
2810 /* Synchronize mailbox IRQ */
2811 bnad_mbox_irq_sync(bnad);
2813 mutex_unlock(&bnad->conf_mutex);
2819 /* Returns 0 for success */
2821 bnad_txq_wi_prepare(struct bnad *bnad, struct bna_tcb *tcb,
2822 struct sk_buff *skb, struct bna_txq_entry *txqent)
2828 if (skb_vlan_tag_present(skb)) {
2829 vlan_tag = (u16)skb_vlan_tag_get(skb);
2830 flags |= (BNA_TXQ_WI_CF_INS_PRIO | BNA_TXQ_WI_CF_INS_VLAN);
2832 if (test_bit(BNAD_RF_CEE_RUNNING, &bnad->run_flags)) {
2833 vlan_tag = ((tcb->priority & 0x7) << VLAN_PRIO_SHIFT)
2834 | (vlan_tag & 0x1fff);
2835 flags |= (BNA_TXQ_WI_CF_INS_PRIO | BNA_TXQ_WI_CF_INS_VLAN);
2837 txqent->hdr.wi.vlan_tag = htons(vlan_tag);
2839 if (skb_is_gso(skb)) {
2840 gso_size = skb_shinfo(skb)->gso_size;
2841 if (unlikely(gso_size > bnad->netdev->mtu)) {
2842 BNAD_UPDATE_CTR(bnad, tx_skb_mss_too_long);
2845 if (unlikely((gso_size + skb_transport_offset(skb) +
2846 tcp_hdrlen(skb)) >= skb->len)) {
2847 txqent->hdr.wi.opcode = htons(BNA_TXQ_WI_SEND);
2848 txqent->hdr.wi.lso_mss = 0;
2849 BNAD_UPDATE_CTR(bnad, tx_skb_tso_too_short);
2851 txqent->hdr.wi.opcode = htons(BNA_TXQ_WI_SEND_LSO);
2852 txqent->hdr.wi.lso_mss = htons(gso_size);
2855 if (bnad_tso_prepare(bnad, skb)) {
2856 BNAD_UPDATE_CTR(bnad, tx_skb_tso_prepare);
2860 flags |= (BNA_TXQ_WI_CF_IP_CKSUM | BNA_TXQ_WI_CF_TCP_CKSUM);
2861 txqent->hdr.wi.l4_hdr_size_n_offset =
2862 htons(BNA_TXQ_WI_L4_HDR_N_OFFSET(
2863 tcp_hdrlen(skb) >> 2, skb_transport_offset(skb)));
2865 txqent->hdr.wi.opcode = htons(BNA_TXQ_WI_SEND);
2866 txqent->hdr.wi.lso_mss = 0;
2868 if (unlikely(skb->len > (bnad->netdev->mtu + VLAN_ETH_HLEN))) {
2869 BNAD_UPDATE_CTR(bnad, tx_skb_non_tso_too_long);
2873 if (skb->ip_summed == CHECKSUM_PARTIAL) {
2874 __be16 net_proto = vlan_get_protocol(skb);
2877 if (net_proto == htons(ETH_P_IP))
2878 proto = ip_hdr(skb)->protocol;
2879 #ifdef NETIF_F_IPV6_CSUM
2880 else if (net_proto == htons(ETH_P_IPV6)) {
2881 /* nexthdr may not be TCP immediately. */
2882 proto = ipv6_hdr(skb)->nexthdr;
2885 if (proto == IPPROTO_TCP) {
2886 flags |= BNA_TXQ_WI_CF_TCP_CKSUM;
2887 txqent->hdr.wi.l4_hdr_size_n_offset =
2888 htons(BNA_TXQ_WI_L4_HDR_N_OFFSET
2889 (0, skb_transport_offset(skb)));
2891 BNAD_UPDATE_CTR(bnad, tcpcsum_offload);
2893 if (unlikely(skb_headlen(skb) <
2894 skb_transport_offset(skb) +
2896 BNAD_UPDATE_CTR(bnad, tx_skb_tcp_hdr);
2899 } else if (proto == IPPROTO_UDP) {
2900 flags |= BNA_TXQ_WI_CF_UDP_CKSUM;
2901 txqent->hdr.wi.l4_hdr_size_n_offset =
2902 htons(BNA_TXQ_WI_L4_HDR_N_OFFSET
2903 (0, skb_transport_offset(skb)));
2905 BNAD_UPDATE_CTR(bnad, udpcsum_offload);
2906 if (unlikely(skb_headlen(skb) <
2907 skb_transport_offset(skb) +
2908 sizeof(struct udphdr))) {
2909 BNAD_UPDATE_CTR(bnad, tx_skb_udp_hdr);
2914 BNAD_UPDATE_CTR(bnad, tx_skb_csum_err);
2918 txqent->hdr.wi.l4_hdr_size_n_offset = 0;
2921 txqent->hdr.wi.flags = htons(flags);
2922 txqent->hdr.wi.frame_length = htonl(skb->len);
2928 * bnad_start_xmit : Netdev entry point for Transmit
2929 * Called under lock held by net_device
2932 bnad_start_xmit(struct sk_buff *skb, struct net_device *netdev)
2934 struct bnad *bnad = netdev_priv(netdev);
2936 struct bna_tcb *tcb = NULL;
2937 struct bnad_tx_unmap *unmap_q, *unmap, *head_unmap;
2938 u32 prod, q_depth, vect_id;
2939 u32 wis, vectors, len;
2941 dma_addr_t dma_addr;
2942 struct bna_txq_entry *txqent;
2944 len = skb_headlen(skb);
2946 /* Sanity checks for the skb */
2948 if (unlikely(skb->len <= ETH_HLEN)) {
2949 dev_kfree_skb_any(skb);
2950 BNAD_UPDATE_CTR(bnad, tx_skb_too_short);
2951 return NETDEV_TX_OK;
2953 if (unlikely(len > BFI_TX_MAX_DATA_PER_VECTOR)) {
2954 dev_kfree_skb_any(skb);
2955 BNAD_UPDATE_CTR(bnad, tx_skb_headlen_zero);
2956 return NETDEV_TX_OK;
2958 if (unlikely(len == 0)) {
2959 dev_kfree_skb_any(skb);
2960 BNAD_UPDATE_CTR(bnad, tx_skb_headlen_zero);
2961 return NETDEV_TX_OK;
2964 tcb = bnad->tx_info[0].tcb[txq_id];
2967 * Takes care of the Tx that is scheduled between clearing the flag
2968 * and the netif_tx_stop_all_queues() call.
2970 if (unlikely(!tcb || !test_bit(BNAD_TXQ_TX_STARTED, &tcb->flags))) {
2971 dev_kfree_skb_any(skb);
2972 BNAD_UPDATE_CTR(bnad, tx_skb_stopping);
2973 return NETDEV_TX_OK;
2976 q_depth = tcb->q_depth;
2977 prod = tcb->producer_index;
2978 unmap_q = tcb->unmap_q;
2980 vectors = 1 + skb_shinfo(skb)->nr_frags;
2981 wis = BNA_TXQ_WI_NEEDED(vectors); /* 4 vectors per work item */
2983 if (unlikely(vectors > BFI_TX_MAX_VECTORS_PER_PKT)) {
2984 dev_kfree_skb_any(skb);
2985 BNAD_UPDATE_CTR(bnad, tx_skb_max_vectors);
2986 return NETDEV_TX_OK;
2989 /* Check for available TxQ resources */
2990 if (unlikely(wis > BNA_QE_FREE_CNT(tcb, q_depth))) {
2991 if ((*tcb->hw_consumer_index != tcb->consumer_index) &&
2992 !test_and_set_bit(BNAD_TXQ_FREE_SENT, &tcb->flags)) {
2994 sent = bnad_txcmpl_process(bnad, tcb);
2995 if (likely(test_bit(BNAD_TXQ_TX_STARTED, &tcb->flags)))
2996 bna_ib_ack(tcb->i_dbell, sent);
2997 smp_mb__before_atomic();
2998 clear_bit(BNAD_TXQ_FREE_SENT, &tcb->flags);
3000 netif_stop_queue(netdev);
3001 BNAD_UPDATE_CTR(bnad, netif_queue_stop);
3006 * Check again to deal with race condition between
3007 * netif_stop_queue here, and netif_wake_queue in
3008 * interrupt handler which is not inside netif tx lock.
3010 if (likely(wis > BNA_QE_FREE_CNT(tcb, q_depth))) {
3011 BNAD_UPDATE_CTR(bnad, netif_queue_stop);
3012 return NETDEV_TX_BUSY;
3014 netif_wake_queue(netdev);
3015 BNAD_UPDATE_CTR(bnad, netif_queue_wakeup);
3019 txqent = &((struct bna_txq_entry *)tcb->sw_q)[prod];
3020 head_unmap = &unmap_q[prod];
3022 /* Program the opcode, flags, frame_len, num_vectors in WI */
3023 if (bnad_txq_wi_prepare(bnad, tcb, skb, txqent)) {
3024 dev_kfree_skb_any(skb);
3025 return NETDEV_TX_OK;
3027 txqent->hdr.wi.reserved = 0;
3028 txqent->hdr.wi.num_vectors = vectors;
3030 head_unmap->skb = skb;
3031 head_unmap->nvecs = 0;
3033 /* Program the vectors */
3035 dma_addr = dma_map_single(&bnad->pcidev->dev, skb->data,
3036 len, DMA_TO_DEVICE);
3037 BNA_SET_DMA_ADDR(dma_addr, &txqent->vector[0].host_addr);
3038 txqent->vector[0].length = htons(len);
3039 dma_unmap_addr_set(&unmap->vectors[0], dma_addr, dma_addr);
3040 head_unmap->nvecs++;
3042 for (i = 0, vect_id = 0; i < vectors - 1; i++) {
3043 const struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[i];
3044 u32 size = skb_frag_size(frag);
3046 if (unlikely(size == 0)) {
3047 /* Undo the changes starting at tcb->producer_index */
3048 bnad_tx_buff_unmap(bnad, unmap_q, q_depth,
3049 tcb->producer_index);
3050 dev_kfree_skb_any(skb);
3051 BNAD_UPDATE_CTR(bnad, tx_skb_frag_zero);
3052 return NETDEV_TX_OK;
3058 if (vect_id == BFI_TX_MAX_VECTORS_PER_WI) {
3060 BNA_QE_INDX_INC(prod, q_depth);
3061 txqent = &((struct bna_txq_entry *)tcb->sw_q)[prod];
3062 txqent->hdr.wi_ext.opcode = htons(BNA_TXQ_WI_EXTENSION);
3063 unmap = &unmap_q[prod];
3066 dma_addr = skb_frag_dma_map(&bnad->pcidev->dev, frag,
3067 0, size, DMA_TO_DEVICE);
3068 dma_unmap_len_set(&unmap->vectors[vect_id], dma_len, size);
3069 BNA_SET_DMA_ADDR(dma_addr, &txqent->vector[vect_id].host_addr);
3070 txqent->vector[vect_id].length = htons(size);
3071 dma_unmap_addr_set(&unmap->vectors[vect_id], dma_addr,
3073 head_unmap->nvecs++;
3076 if (unlikely(len != skb->len)) {
3077 /* Undo the changes starting at tcb->producer_index */
3078 bnad_tx_buff_unmap(bnad, unmap_q, q_depth, tcb->producer_index);
3079 dev_kfree_skb_any(skb);
3080 BNAD_UPDATE_CTR(bnad, tx_skb_len_mismatch);
3081 return NETDEV_TX_OK;
3084 BNA_QE_INDX_INC(prod, q_depth);
3085 tcb->producer_index = prod;
3089 if (unlikely(!test_bit(BNAD_TXQ_TX_STARTED, &tcb->flags)))
3090 return NETDEV_TX_OK;
3092 skb_tx_timestamp(skb);
3094 bna_txq_prod_indx_doorbell(tcb);
3097 return NETDEV_TX_OK;
3101 * Used spin_lock to synchronize reading of stats structures, which
3102 * is written by BNA under the same lock.
3104 static struct rtnl_link_stats64 *
3105 bnad_get_stats64(struct net_device *netdev, struct rtnl_link_stats64 *stats)
3107 struct bnad *bnad = netdev_priv(netdev);
3108 unsigned long flags;
3110 spin_lock_irqsave(&bnad->bna_lock, flags);
3112 bnad_netdev_qstats_fill(bnad, stats);
3113 bnad_netdev_hwstats_fill(bnad, stats);
3115 spin_unlock_irqrestore(&bnad->bna_lock, flags);
3121 bnad_set_rx_ucast_fltr(struct bnad *bnad)
3123 struct net_device *netdev = bnad->netdev;
3124 int uc_count = netdev_uc_count(netdev);
3125 enum bna_cb_status ret;
3127 struct netdev_hw_addr *ha;
3130 if (netdev_uc_empty(bnad->netdev)) {
3131 bna_rx_ucast_listset(bnad->rx_info[0].rx, 0, NULL);
3135 if (uc_count > bna_attr(&bnad->bna)->num_ucmac)
3138 mac_list = kzalloc(uc_count * ETH_ALEN, GFP_ATOMIC);
3139 if (mac_list == NULL)
3143 netdev_for_each_uc_addr(ha, netdev) {
3144 ether_addr_copy(&mac_list[entry * ETH_ALEN], &ha->addr[0]);
3148 ret = bna_rx_ucast_listset(bnad->rx_info[0].rx, entry, mac_list);
3151 if (ret != BNA_CB_SUCCESS)
3156 /* ucast packets not in UCAM are routed to default function */
3158 bnad->cfg_flags |= BNAD_CF_DEFAULT;
3159 bna_rx_ucast_listset(bnad->rx_info[0].rx, 0, NULL);
3163 bnad_set_rx_mcast_fltr(struct bnad *bnad)
3165 struct net_device *netdev = bnad->netdev;
3166 int mc_count = netdev_mc_count(netdev);
3167 enum bna_cb_status ret;
3170 if (netdev->flags & IFF_ALLMULTI)
3173 if (netdev_mc_empty(netdev))
3176 if (mc_count > bna_attr(&bnad->bna)->num_mcmac)
3179 mac_list = kzalloc((mc_count + 1) * ETH_ALEN, GFP_ATOMIC);
3181 if (mac_list == NULL)
3184 ether_addr_copy(&mac_list[0], &bnad_bcast_addr[0]);
3186 /* copy rest of the MCAST addresses */
3187 bnad_netdev_mc_list_get(netdev, mac_list);
3188 ret = bna_rx_mcast_listset(bnad->rx_info[0].rx, mc_count + 1, mac_list);
3191 if (ret != BNA_CB_SUCCESS)
3197 bnad->cfg_flags |= BNAD_CF_ALLMULTI;
3198 bna_rx_mcast_delall(bnad->rx_info[0].rx);
3202 bnad_set_rx_mode(struct net_device *netdev)
3204 struct bnad *bnad = netdev_priv(netdev);
3205 enum bna_rxmode new_mode, mode_mask;
3206 unsigned long flags;
3208 spin_lock_irqsave(&bnad->bna_lock, flags);
3210 if (bnad->rx_info[0].rx == NULL) {
3211 spin_unlock_irqrestore(&bnad->bna_lock, flags);
3215 /* clear bnad flags to update it with new settings */
3216 bnad->cfg_flags &= ~(BNAD_CF_PROMISC | BNAD_CF_DEFAULT |
3220 if (netdev->flags & IFF_PROMISC) {
3221 new_mode |= BNAD_RXMODE_PROMISC_DEFAULT;
3222 bnad->cfg_flags |= BNAD_CF_PROMISC;
3224 bnad_set_rx_mcast_fltr(bnad);
3226 if (bnad->cfg_flags & BNAD_CF_ALLMULTI)
3227 new_mode |= BNA_RXMODE_ALLMULTI;
3229 bnad_set_rx_ucast_fltr(bnad);
3231 if (bnad->cfg_flags & BNAD_CF_DEFAULT)
3232 new_mode |= BNA_RXMODE_DEFAULT;
3235 mode_mask = BNA_RXMODE_PROMISC | BNA_RXMODE_DEFAULT |
3236 BNA_RXMODE_ALLMULTI;
3237 bna_rx_mode_set(bnad->rx_info[0].rx, new_mode, mode_mask);
3239 spin_unlock_irqrestore(&bnad->bna_lock, flags);
3243 * bna_lock is used to sync writes to netdev->addr
3244 * conf_lock cannot be used since this call may be made
3245 * in a non-blocking context.
3248 bnad_set_mac_address(struct net_device *netdev, void *addr)
3251 struct bnad *bnad = netdev_priv(netdev);
3252 struct sockaddr *sa = (struct sockaddr *)addr;
3253 unsigned long flags;
3255 spin_lock_irqsave(&bnad->bna_lock, flags);
3257 err = bnad_mac_addr_set_locked(bnad, sa->sa_data);
3259 ether_addr_copy(netdev->dev_addr, sa->sa_data);
3261 spin_unlock_irqrestore(&bnad->bna_lock, flags);
3267 bnad_mtu_set(struct bnad *bnad, int frame_size)
3269 unsigned long flags;
3271 init_completion(&bnad->bnad_completions.mtu_comp);
3273 spin_lock_irqsave(&bnad->bna_lock, flags);
3274 bna_enet_mtu_set(&bnad->bna.enet, frame_size, bnad_cb_enet_mtu_set);
3275 spin_unlock_irqrestore(&bnad->bna_lock, flags);
3277 wait_for_completion(&bnad->bnad_completions.mtu_comp);
3279 return bnad->bnad_completions.mtu_comp_status;
3283 bnad_change_mtu(struct net_device *netdev, int new_mtu)
3286 struct bnad *bnad = netdev_priv(netdev);
3287 u32 rx_count = 0, frame, new_frame;
3289 if (new_mtu + ETH_HLEN < ETH_ZLEN || new_mtu > BNAD_JUMBO_MTU)
3292 mutex_lock(&bnad->conf_mutex);
3295 netdev->mtu = new_mtu;
3297 frame = BNAD_FRAME_SIZE(mtu);
3298 new_frame = BNAD_FRAME_SIZE(new_mtu);
3300 /* check if multi-buffer needs to be enabled */
3301 if (BNAD_PCI_DEV_IS_CAT2(bnad) &&
3302 netif_running(bnad->netdev)) {
3303 /* only when transition is over 4K */
3304 if ((frame <= 4096 && new_frame > 4096) ||
3305 (frame > 4096 && new_frame <= 4096))
3306 rx_count = bnad_reinit_rx(bnad);
3309 /* rx_count > 0 - new rx created
3310 * - Linux set err = 0 and return
3312 err = bnad_mtu_set(bnad, new_frame);
3316 mutex_unlock(&bnad->conf_mutex);
3321 bnad_vlan_rx_add_vid(struct net_device *netdev, __be16 proto, u16 vid)
3323 struct bnad *bnad = netdev_priv(netdev);
3324 unsigned long flags;
3326 if (!bnad->rx_info[0].rx)
3329 mutex_lock(&bnad->conf_mutex);
3331 spin_lock_irqsave(&bnad->bna_lock, flags);
3332 bna_rx_vlan_add(bnad->rx_info[0].rx, vid);
3333 set_bit(vid, bnad->active_vlans);
3334 spin_unlock_irqrestore(&bnad->bna_lock, flags);
3336 mutex_unlock(&bnad->conf_mutex);
3342 bnad_vlan_rx_kill_vid(struct net_device *netdev, __be16 proto, u16 vid)
3344 struct bnad *bnad = netdev_priv(netdev);
3345 unsigned long flags;
3347 if (!bnad->rx_info[0].rx)
3350 mutex_lock(&bnad->conf_mutex);
3352 spin_lock_irqsave(&bnad->bna_lock, flags);
3353 clear_bit(vid, bnad->active_vlans);
3354 bna_rx_vlan_del(bnad->rx_info[0].rx, vid);
3355 spin_unlock_irqrestore(&bnad->bna_lock, flags);
3357 mutex_unlock(&bnad->conf_mutex);
3362 static int bnad_set_features(struct net_device *dev, netdev_features_t features)
3364 struct bnad *bnad = netdev_priv(dev);
3365 netdev_features_t changed = features ^ dev->features;
3367 if ((changed & NETIF_F_HW_VLAN_CTAG_RX) && netif_running(dev)) {
3368 unsigned long flags;
3370 spin_lock_irqsave(&bnad->bna_lock, flags);
3372 if (features & NETIF_F_HW_VLAN_CTAG_RX)
3373 bna_rx_vlan_strip_enable(bnad->rx_info[0].rx);
3375 bna_rx_vlan_strip_disable(bnad->rx_info[0].rx);
3377 spin_unlock_irqrestore(&bnad->bna_lock, flags);
3383 #ifdef CONFIG_NET_POLL_CONTROLLER
3385 bnad_netpoll(struct net_device *netdev)
3387 struct bnad *bnad = netdev_priv(netdev);
3388 struct bnad_rx_info *rx_info;
3389 struct bnad_rx_ctrl *rx_ctrl;
3393 if (!(bnad->cfg_flags & BNAD_CF_MSIX)) {
3394 bna_intx_disable(&bnad->bna, curr_mask);
3395 bnad_isr(bnad->pcidev->irq, netdev);
3396 bna_intx_enable(&bnad->bna, curr_mask);
3399 * Tx processing may happen in sending context, so no need
3400 * to explicitly process completions here
3404 for (i = 0; i < bnad->num_rx; i++) {
3405 rx_info = &bnad->rx_info[i];
3408 for (j = 0; j < bnad->num_rxp_per_rx; j++) {
3409 rx_ctrl = &rx_info->rx_ctrl[j];
3411 bnad_netif_rx_schedule_poll(bnad,
3419 static const struct net_device_ops bnad_netdev_ops = {
3420 .ndo_open = bnad_open,
3421 .ndo_stop = bnad_stop,
3422 .ndo_start_xmit = bnad_start_xmit,
3423 .ndo_get_stats64 = bnad_get_stats64,
3424 .ndo_set_rx_mode = bnad_set_rx_mode,
3425 .ndo_validate_addr = eth_validate_addr,
3426 .ndo_set_mac_address = bnad_set_mac_address,
3427 .ndo_change_mtu = bnad_change_mtu,
3428 .ndo_vlan_rx_add_vid = bnad_vlan_rx_add_vid,
3429 .ndo_vlan_rx_kill_vid = bnad_vlan_rx_kill_vid,
3430 .ndo_set_features = bnad_set_features,
3431 #ifdef CONFIG_NET_POLL_CONTROLLER
3432 .ndo_poll_controller = bnad_netpoll
3437 bnad_netdev_init(struct bnad *bnad, bool using_dac)
3439 struct net_device *netdev = bnad->netdev;
3441 netdev->hw_features = NETIF_F_SG | NETIF_F_RXCSUM |
3442 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
3443 NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_HW_VLAN_CTAG_TX |
3444 NETIF_F_HW_VLAN_CTAG_RX;
3446 netdev->vlan_features = NETIF_F_SG | NETIF_F_HIGHDMA |
3447 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
3448 NETIF_F_TSO | NETIF_F_TSO6;
3450 netdev->features |= netdev->hw_features | NETIF_F_HW_VLAN_CTAG_FILTER;
3453 netdev->features |= NETIF_F_HIGHDMA;
3455 netdev->mem_start = bnad->mmio_start;
3456 netdev->mem_end = bnad->mmio_start + bnad->mmio_len - 1;
3458 netdev->netdev_ops = &bnad_netdev_ops;
3459 bnad_set_ethtool_ops(netdev);
3463 * 1. Initialize the bnad structure
3464 * 2. Setup netdev pointer in pci_dev
3465 * 3. Initialize no. of TxQ & CQs & MSIX vectors
3466 * 4. Initialize work queue.
3469 bnad_init(struct bnad *bnad,
3470 struct pci_dev *pdev, struct net_device *netdev)
3472 unsigned long flags;
3474 SET_NETDEV_DEV(netdev, &pdev->dev);
3475 pci_set_drvdata(pdev, netdev);
3477 bnad->netdev = netdev;
3478 bnad->pcidev = pdev;
3479 bnad->mmio_start = pci_resource_start(pdev, 0);
3480 bnad->mmio_len = pci_resource_len(pdev, 0);
3481 bnad->bar0 = ioremap_nocache(bnad->mmio_start, bnad->mmio_len);
3483 dev_err(&pdev->dev, "ioremap for bar0 failed\n");
3486 pr_info("bar0 mapped to %p, len %llu\n", bnad->bar0,
3487 (unsigned long long) bnad->mmio_len);
3489 spin_lock_irqsave(&bnad->bna_lock, flags);
3490 if (!bnad_msix_disable)
3491 bnad->cfg_flags = BNAD_CF_MSIX;
3493 bnad->cfg_flags |= BNAD_CF_DIM_ENABLED;
3495 bnad_q_num_init(bnad);
3496 spin_unlock_irqrestore(&bnad->bna_lock, flags);
3498 bnad->msix_num = (bnad->num_tx * bnad->num_txq_per_tx) +
3499 (bnad->num_rx * bnad->num_rxp_per_rx) +
3500 BNAD_MAILBOX_MSIX_VECTORS;
3502 bnad->txq_depth = BNAD_TXQ_DEPTH;
3503 bnad->rxq_depth = BNAD_RXQ_DEPTH;
3505 bnad->tx_coalescing_timeo = BFI_TX_COALESCING_TIMEO;
3506 bnad->rx_coalescing_timeo = BFI_RX_COALESCING_TIMEO;
3508 sprintf(bnad->wq_name, "%s_wq_%d", BNAD_NAME, bnad->id);
3509 bnad->work_q = create_singlethread_workqueue(bnad->wq_name);
3510 if (!bnad->work_q) {
3511 iounmap(bnad->bar0);
3519 * Must be called after bnad_pci_uninit()
3520 * so that iounmap() and pci_set_drvdata(NULL)
3521 * happens only after PCI uninitialization.
3524 bnad_uninit(struct bnad *bnad)
3527 flush_workqueue(bnad->work_q);
3528 destroy_workqueue(bnad->work_q);
3529 bnad->work_q = NULL;
3533 iounmap(bnad->bar0);
3538 a) Per ioceth mutes used for serializing configuration
3539 changes from OS interface
3540 b) spin lock used to protect bna state machine
3543 bnad_lock_init(struct bnad *bnad)
3545 spin_lock_init(&bnad->bna_lock);
3546 mutex_init(&bnad->conf_mutex);
3547 mutex_init(&bnad_list_mutex);
3551 bnad_lock_uninit(struct bnad *bnad)
3553 mutex_destroy(&bnad->conf_mutex);
3554 mutex_destroy(&bnad_list_mutex);
3557 /* PCI Initialization */
3559 bnad_pci_init(struct bnad *bnad,
3560 struct pci_dev *pdev, bool *using_dac)
3564 err = pci_enable_device(pdev);
3567 err = pci_request_regions(pdev, BNAD_NAME);
3569 goto disable_device;
3570 if (!dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64))) {
3573 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
3575 goto release_regions;
3578 pci_set_master(pdev);
3582 pci_release_regions(pdev);
3584 pci_disable_device(pdev);
3590 bnad_pci_uninit(struct pci_dev *pdev)
3592 pci_release_regions(pdev);
3593 pci_disable_device(pdev);
3597 bnad_pci_probe(struct pci_dev *pdev,
3598 const struct pci_device_id *pcidev_id)
3604 struct net_device *netdev;
3605 struct bfa_pcidev pcidev_info;
3606 unsigned long flags;
3608 pr_info("bnad_pci_probe : (0x%p, 0x%p) PCI Func : (%d)\n",
3609 pdev, pcidev_id, PCI_FUNC(pdev->devfn));
3611 mutex_lock(&bnad_fwimg_mutex);
3612 if (!cna_get_firmware_buf(pdev)) {
3613 mutex_unlock(&bnad_fwimg_mutex);
3614 pr_warn("Failed to load Firmware Image!\n");
3617 mutex_unlock(&bnad_fwimg_mutex);
3620 * Allocates sizeof(struct net_device + struct bnad)
3621 * bnad = netdev->priv
3623 netdev = alloc_etherdev(sizeof(struct bnad));
3628 bnad = netdev_priv(netdev);
3629 bnad_lock_init(bnad);
3630 bnad_add_to_list(bnad);
3632 mutex_lock(&bnad->conf_mutex);
3634 * PCI initialization
3635 * Output : using_dac = 1 for 64 bit DMA
3636 * = 0 for 32 bit DMA
3639 err = bnad_pci_init(bnad, pdev, &using_dac);
3644 * Initialize bnad structure
3645 * Setup relation between pci_dev & netdev
3647 err = bnad_init(bnad, pdev, netdev);
3651 /* Initialize netdev structure, set up ethtool ops */
3652 bnad_netdev_init(bnad, using_dac);
3654 /* Set link to down state */
3655 netif_carrier_off(netdev);
3657 /* Setup the debugfs node for this bfad */
3658 if (bna_debugfs_enable)
3659 bnad_debugfs_init(bnad);
3661 /* Get resource requirement form bna */
3662 spin_lock_irqsave(&bnad->bna_lock, flags);
3663 bna_res_req(&bnad->res_info[0]);
3664 spin_unlock_irqrestore(&bnad->bna_lock, flags);
3666 /* Allocate resources from bna */
3667 err = bnad_res_alloc(bnad, &bnad->res_info[0], BNA_RES_T_MAX);
3673 /* Setup pcidev_info for bna_init() */
3674 pcidev_info.pci_slot = PCI_SLOT(bnad->pcidev->devfn);
3675 pcidev_info.pci_func = PCI_FUNC(bnad->pcidev->devfn);
3676 pcidev_info.device_id = bnad->pcidev->device;
3677 pcidev_info.pci_bar_kva = bnad->bar0;
3679 spin_lock_irqsave(&bnad->bna_lock, flags);
3680 bna_init(bna, bnad, &pcidev_info, &bnad->res_info[0]);
3681 spin_unlock_irqrestore(&bnad->bna_lock, flags);
3683 bnad->stats.bna_stats = &bna->stats;
3685 bnad_enable_msix(bnad);
3686 err = bnad_mbox_irq_alloc(bnad);
3691 setup_timer(&bnad->bna.ioceth.ioc.ioc_timer, bnad_ioc_timeout,
3692 ((unsigned long)bnad));
3693 setup_timer(&bnad->bna.ioceth.ioc.hb_timer, bnad_ioc_hb_check,
3694 ((unsigned long)bnad));
3695 setup_timer(&bnad->bna.ioceth.ioc.iocpf_timer, bnad_iocpf_timeout,
3696 ((unsigned long)bnad));
3697 setup_timer(&bnad->bna.ioceth.ioc.sem_timer, bnad_iocpf_sem_timeout,
3698 ((unsigned long)bnad));
3702 * If the call back comes with error, we bail out.
3703 * This is a catastrophic error.
3705 err = bnad_ioceth_enable(bnad);
3707 pr_err("BNA: Initialization failed err=%d\n",
3712 spin_lock_irqsave(&bnad->bna_lock, flags);
3713 if (bna_num_txq_set(bna, BNAD_NUM_TXQ + 1) ||
3714 bna_num_rxp_set(bna, BNAD_NUM_RXP + 1)) {
3715 bnad_q_num_adjust(bnad, bna_attr(bna)->num_txq - 1,
3716 bna_attr(bna)->num_rxp - 1);
3717 if (bna_num_txq_set(bna, BNAD_NUM_TXQ + 1) ||
3718 bna_num_rxp_set(bna, BNAD_NUM_RXP + 1))
3721 spin_unlock_irqrestore(&bnad->bna_lock, flags);
3723 goto disable_ioceth;
3725 spin_lock_irqsave(&bnad->bna_lock, flags);
3726 bna_mod_res_req(&bnad->bna, &bnad->mod_res_info[0]);
3727 spin_unlock_irqrestore(&bnad->bna_lock, flags);
3729 err = bnad_res_alloc(bnad, &bnad->mod_res_info[0], BNA_MOD_RES_T_MAX);
3732 goto disable_ioceth;
3735 spin_lock_irqsave(&bnad->bna_lock, flags);
3736 bna_mod_init(&bnad->bna, &bnad->mod_res_info[0]);
3737 spin_unlock_irqrestore(&bnad->bna_lock, flags);
3739 /* Get the burnt-in mac */
3740 spin_lock_irqsave(&bnad->bna_lock, flags);
3741 bna_enet_perm_mac_get(&bna->enet, bnad->perm_addr);
3742 bnad_set_netdev_perm_addr(bnad);
3743 spin_unlock_irqrestore(&bnad->bna_lock, flags);
3745 mutex_unlock(&bnad->conf_mutex);
3747 /* Finally, reguister with net_device layer */
3748 err = register_netdev(netdev);
3750 pr_err("BNA : Registering with netdev failed\n");
3753 set_bit(BNAD_RF_NETDEV_REGISTERED, &bnad->run_flags);
3758 mutex_unlock(&bnad->conf_mutex);
3762 mutex_lock(&bnad->conf_mutex);
3763 bnad_res_free(bnad, &bnad->mod_res_info[0], BNA_MOD_RES_T_MAX);
3765 bnad_ioceth_disable(bnad);
3766 del_timer_sync(&bnad->bna.ioceth.ioc.ioc_timer);
3767 del_timer_sync(&bnad->bna.ioceth.ioc.sem_timer);
3768 del_timer_sync(&bnad->bna.ioceth.ioc.hb_timer);
3769 spin_lock_irqsave(&bnad->bna_lock, flags);
3771 spin_unlock_irqrestore(&bnad->bna_lock, flags);
3772 bnad_mbox_irq_free(bnad);
3773 bnad_disable_msix(bnad);
3775 bnad_res_free(bnad, &bnad->res_info[0], BNA_RES_T_MAX);
3777 /* Remove the debugfs node for this bnad */
3778 kfree(bnad->regdata);
3779 bnad_debugfs_uninit(bnad);
3782 bnad_pci_uninit(pdev);
3784 mutex_unlock(&bnad->conf_mutex);
3785 bnad_remove_from_list(bnad);
3786 bnad_lock_uninit(bnad);
3787 free_netdev(netdev);
3792 bnad_pci_remove(struct pci_dev *pdev)
3794 struct net_device *netdev = pci_get_drvdata(pdev);
3797 unsigned long flags;
3802 pr_info("%s bnad_pci_remove\n", netdev->name);
3803 bnad = netdev_priv(netdev);
3806 if (test_and_clear_bit(BNAD_RF_NETDEV_REGISTERED, &bnad->run_flags))
3807 unregister_netdev(netdev);
3809 mutex_lock(&bnad->conf_mutex);
3810 bnad_ioceth_disable(bnad);
3811 del_timer_sync(&bnad->bna.ioceth.ioc.ioc_timer);
3812 del_timer_sync(&bnad->bna.ioceth.ioc.sem_timer);
3813 del_timer_sync(&bnad->bna.ioceth.ioc.hb_timer);
3814 spin_lock_irqsave(&bnad->bna_lock, flags);
3816 spin_unlock_irqrestore(&bnad->bna_lock, flags);
3818 bnad_res_free(bnad, &bnad->mod_res_info[0], BNA_MOD_RES_T_MAX);
3819 bnad_res_free(bnad, &bnad->res_info[0], BNA_RES_T_MAX);
3820 bnad_mbox_irq_free(bnad);
3821 bnad_disable_msix(bnad);
3822 bnad_pci_uninit(pdev);
3823 mutex_unlock(&bnad->conf_mutex);
3824 bnad_remove_from_list(bnad);
3825 bnad_lock_uninit(bnad);
3826 /* Remove the debugfs node for this bnad */
3827 kfree(bnad->regdata);
3828 bnad_debugfs_uninit(bnad);
3830 free_netdev(netdev);
3833 static const struct pci_device_id bnad_pci_id_table[] = {
3835 PCI_DEVICE(PCI_VENDOR_ID_BROCADE,
3836 PCI_DEVICE_ID_BROCADE_CT),
3837 .class = PCI_CLASS_NETWORK_ETHERNET << 8,
3838 .class_mask = 0xffff00
3841 PCI_DEVICE(PCI_VENDOR_ID_BROCADE,
3842 BFA_PCI_DEVICE_ID_CT2),
3843 .class = PCI_CLASS_NETWORK_ETHERNET << 8,
3844 .class_mask = 0xffff00
3849 MODULE_DEVICE_TABLE(pci, bnad_pci_id_table);
3851 static struct pci_driver bnad_pci_driver = {
3853 .id_table = bnad_pci_id_table,
3854 .probe = bnad_pci_probe,
3855 .remove = bnad_pci_remove,
3859 bnad_module_init(void)
3863 pr_info("QLogic BR-series 10G Ethernet driver - version: %s\n",
3866 bfa_nw_ioc_auto_recover(bnad_ioc_auto_recover);
3868 err = pci_register_driver(&bnad_pci_driver);
3870 pr_err("bna : PCI registration failed in module init "
3879 bnad_module_exit(void)
3881 pci_unregister_driver(&bnad_pci_driver);
3882 release_firmware(bfi_fw);
3885 module_init(bnad_module_init);
3886 module_exit(bnad_module_exit);
3888 MODULE_AUTHOR("Brocade");
3889 MODULE_LICENSE("GPL");
3890 MODULE_DESCRIPTION("QLogic BR-series 10G PCIe Ethernet driver");
3891 MODULE_VERSION(BNAD_VERSION);
3892 MODULE_FIRMWARE(CNA_FW_FILE_CT);
3893 MODULE_FIRMWARE(CNA_FW_FILE_CT2);