2 * tg3.c: Broadcom Tigon3 ethernet driver.
4 * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5 * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
6 * Copyright (C) 2004 Sun Microsystems Inc.
7 * Copyright (C) 2005-2011 Broadcom Corporation.
10 * Derived from proprietary unpublished source code,
11 * Copyright (C) 2000-2003 Broadcom Corporation.
13 * Permission is hereby granted for the distribution of this firmware
14 * data in hexadecimal or equivalent format, provided this copyright
15 * notice is accompanying it.
19 #include <linux/module.h>
20 #include <linux/moduleparam.h>
21 #include <linux/stringify.h>
22 #include <linux/kernel.h>
23 #include <linux/types.h>
24 #include <linux/compiler.h>
25 #include <linux/slab.h>
26 #include <linux/delay.h>
28 #include <linux/init.h>
29 #include <linux/interrupt.h>
30 #include <linux/ioport.h>
31 #include <linux/pci.h>
32 #include <linux/netdevice.h>
33 #include <linux/etherdevice.h>
34 #include <linux/skbuff.h>
35 #include <linux/ethtool.h>
36 #include <linux/mdio.h>
37 #include <linux/mii.h>
38 #include <linux/phy.h>
39 #include <linux/brcmphy.h>
40 #include <linux/if_vlan.h>
42 #include <linux/tcp.h>
43 #include <linux/workqueue.h>
44 #include <linux/prefetch.h>
45 #include <linux/dma-mapping.h>
46 #include <linux/firmware.h>
48 #include <net/checksum.h>
51 #include <asm/system.h>
53 #include <asm/byteorder.h>
54 #include <linux/uaccess.h>
57 #include <asm/idprom.h>
66 /* Functions & macros to verify TG3_FLAGS types */
68 static inline int _tg3_flag(enum TG3_FLAGS flag, unsigned long *bits)
70 return test_bit(flag, bits);
73 static inline void _tg3_flag_set(enum TG3_FLAGS flag, unsigned long *bits)
78 static inline void _tg3_flag_clear(enum TG3_FLAGS flag, unsigned long *bits)
80 clear_bit(flag, bits);
83 #define tg3_flag(tp, flag) \
84 _tg3_flag(TG3_FLAG_##flag, (tp)->tg3_flags)
85 #define tg3_flag_set(tp, flag) \
86 _tg3_flag_set(TG3_FLAG_##flag, (tp)->tg3_flags)
87 #define tg3_flag_clear(tp, flag) \
88 _tg3_flag_clear(TG3_FLAG_##flag, (tp)->tg3_flags)
90 #define DRV_MODULE_NAME "tg3"
92 #define TG3_MIN_NUM 121
93 #define DRV_MODULE_VERSION \
94 __stringify(TG3_MAJ_NUM) "." __stringify(TG3_MIN_NUM)
95 #define DRV_MODULE_RELDATE "November 2, 2011"
97 #define RESET_KIND_SHUTDOWN 0
98 #define RESET_KIND_INIT 1
99 #define RESET_KIND_SUSPEND 2
101 #define TG3_DEF_RX_MODE 0
102 #define TG3_DEF_TX_MODE 0
103 #define TG3_DEF_MSG_ENABLE \
113 #define TG3_GRC_LCLCTL_PWRSW_DELAY 100
115 /* length of time before we decide the hardware is borked,
116 * and dev->tx_timeout() should be called to fix the problem
119 #define TG3_TX_TIMEOUT (5 * HZ)
121 /* hardware minimum and maximum for a single frame's data payload */
122 #define TG3_MIN_MTU 60
123 #define TG3_MAX_MTU(tp) \
124 (tg3_flag(tp, JUMBO_CAPABLE) ? 9000 : 1500)
126 /* These numbers seem to be hard coded in the NIC firmware somehow.
127 * You can't change the ring sizes, but you can change where you place
128 * them in the NIC onboard memory.
130 #define TG3_RX_STD_RING_SIZE(tp) \
131 (tg3_flag(tp, LRG_PROD_RING_CAP) ? \
132 TG3_RX_STD_MAX_SIZE_5717 : TG3_RX_STD_MAX_SIZE_5700)
133 #define TG3_DEF_RX_RING_PENDING 200
134 #define TG3_RX_JMB_RING_SIZE(tp) \
135 (tg3_flag(tp, LRG_PROD_RING_CAP) ? \
136 TG3_RX_JMB_MAX_SIZE_5717 : TG3_RX_JMB_MAX_SIZE_5700)
137 #define TG3_DEF_RX_JUMBO_RING_PENDING 100
138 #define TG3_RSS_INDIR_TBL_SIZE 128
140 /* Do not place this n-ring entries value into the tp struct itself,
141 * we really want to expose these constants to GCC so that modulo et
142 * al. operations are done with shifts and masks instead of with
143 * hw multiply/modulo instructions. Another solution would be to
144 * replace things like '% foo' with '& (foo - 1)'.
147 #define TG3_TX_RING_SIZE 512
148 #define TG3_DEF_TX_RING_PENDING (TG3_TX_RING_SIZE - 1)
150 #define TG3_RX_STD_RING_BYTES(tp) \
151 (sizeof(struct tg3_rx_buffer_desc) * TG3_RX_STD_RING_SIZE(tp))
152 #define TG3_RX_JMB_RING_BYTES(tp) \
153 (sizeof(struct tg3_ext_rx_buffer_desc) * TG3_RX_JMB_RING_SIZE(tp))
154 #define TG3_RX_RCB_RING_BYTES(tp) \
155 (sizeof(struct tg3_rx_buffer_desc) * (tp->rx_ret_ring_mask + 1))
156 #define TG3_TX_RING_BYTES (sizeof(struct tg3_tx_buffer_desc) * \
158 #define NEXT_TX(N) (((N) + 1) & (TG3_TX_RING_SIZE - 1))
160 #define TG3_DMA_BYTE_ENAB 64
162 #define TG3_RX_STD_DMA_SZ 1536
163 #define TG3_RX_JMB_DMA_SZ 9046
165 #define TG3_RX_DMA_TO_MAP_SZ(x) ((x) + TG3_DMA_BYTE_ENAB)
167 #define TG3_RX_STD_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_STD_DMA_SZ)
168 #define TG3_RX_JMB_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ)
170 #define TG3_RX_STD_BUFF_RING_SIZE(tp) \
171 (sizeof(struct ring_info) * TG3_RX_STD_RING_SIZE(tp))
173 #define TG3_RX_JMB_BUFF_RING_SIZE(tp) \
174 (sizeof(struct ring_info) * TG3_RX_JMB_RING_SIZE(tp))
176 /* Due to a hardware bug, the 5701 can only DMA to memory addresses
177 * that are at least dword aligned when used in PCIX mode. The driver
178 * works around this bug by double copying the packet. This workaround
179 * is built into the normal double copy length check for efficiency.
181 * However, the double copy is only necessary on those architectures
182 * where unaligned memory accesses are inefficient. For those architectures
183 * where unaligned memory accesses incur little penalty, we can reintegrate
184 * the 5701 in the normal rx path. Doing so saves a device structure
185 * dereference by hardcoding the double copy threshold in place.
187 #define TG3_RX_COPY_THRESHOLD 256
188 #if NET_IP_ALIGN == 0 || defined(CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS)
189 #define TG3_RX_COPY_THRESH(tp) TG3_RX_COPY_THRESHOLD
191 #define TG3_RX_COPY_THRESH(tp) ((tp)->rx_copy_thresh)
194 #if (NET_IP_ALIGN != 0)
195 #define TG3_RX_OFFSET(tp) ((tp)->rx_offset)
197 #define TG3_RX_OFFSET(tp) 0
200 /* minimum number of free TX descriptors required to wake up TX process */
201 #define TG3_TX_WAKEUP_THRESH(tnapi) ((tnapi)->tx_pending / 4)
202 #define TG3_TX_BD_DMA_MAX 4096
204 #define TG3_RAW_IP_ALIGN 2
206 #define TG3_FW_UPDATE_TIMEOUT_SEC 5
208 #define FIRMWARE_TG3 "tigon/tg3.bin"
209 #define FIRMWARE_TG3TSO "tigon/tg3_tso.bin"
210 #define FIRMWARE_TG3TSO5 "tigon/tg3_tso5.bin"
212 static char version[] __devinitdata =
213 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")";
215 MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
216 MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
217 MODULE_LICENSE("GPL");
218 MODULE_VERSION(DRV_MODULE_VERSION);
219 MODULE_FIRMWARE(FIRMWARE_TG3);
220 MODULE_FIRMWARE(FIRMWARE_TG3TSO);
221 MODULE_FIRMWARE(FIRMWARE_TG3TSO5);
223 static int tg3_debug = -1; /* -1 == use TG3_DEF_MSG_ENABLE as value */
224 module_param(tg3_debug, int, 0);
225 MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
227 static DEFINE_PCI_DEVICE_TABLE(tg3_pci_tbl) = {
228 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
229 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
230 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
231 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
232 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
233 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
234 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
235 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
236 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
237 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
238 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
239 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
240 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
241 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
242 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
243 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
244 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
245 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
246 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
247 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
248 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
249 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
250 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
251 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
252 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
253 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
254 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
255 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
256 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
257 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
258 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
259 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
260 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
261 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
262 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
263 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
264 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
265 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
266 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
267 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
268 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
269 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
270 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
271 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
272 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
273 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
274 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
275 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
276 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
277 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
278 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
279 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
280 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
281 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
282 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
283 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)},
284 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)},
285 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_G)},
286 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_F)},
287 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)},
288 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)},
289 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790)},
290 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57788)},
291 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5717)},
292 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5718)},
293 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57781)},
294 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57785)},
295 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57761)},
296 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57765)},
297 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57791)},
298 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57795)},
299 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5719)},
300 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5720)},
301 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
302 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
303 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
304 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
305 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
306 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
307 {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
308 {PCI_DEVICE(0x10cf, 0x11a2)}, /* Fujitsu 1000base-SX with BCM5703SKHB */
312 MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
314 static const struct {
315 const char string[ETH_GSTRING_LEN];
316 } ethtool_stats_keys[] = {
319 { "rx_ucast_packets" },
320 { "rx_mcast_packets" },
321 { "rx_bcast_packets" },
323 { "rx_align_errors" },
324 { "rx_xon_pause_rcvd" },
325 { "rx_xoff_pause_rcvd" },
326 { "rx_mac_ctrl_rcvd" },
327 { "rx_xoff_entered" },
328 { "rx_frame_too_long_errors" },
330 { "rx_undersize_packets" },
331 { "rx_in_length_errors" },
332 { "rx_out_length_errors" },
333 { "rx_64_or_less_octet_packets" },
334 { "rx_65_to_127_octet_packets" },
335 { "rx_128_to_255_octet_packets" },
336 { "rx_256_to_511_octet_packets" },
337 { "rx_512_to_1023_octet_packets" },
338 { "rx_1024_to_1522_octet_packets" },
339 { "rx_1523_to_2047_octet_packets" },
340 { "rx_2048_to_4095_octet_packets" },
341 { "rx_4096_to_8191_octet_packets" },
342 { "rx_8192_to_9022_octet_packets" },
349 { "tx_flow_control" },
351 { "tx_single_collisions" },
352 { "tx_mult_collisions" },
354 { "tx_excessive_collisions" },
355 { "tx_late_collisions" },
356 { "tx_collide_2times" },
357 { "tx_collide_3times" },
358 { "tx_collide_4times" },
359 { "tx_collide_5times" },
360 { "tx_collide_6times" },
361 { "tx_collide_7times" },
362 { "tx_collide_8times" },
363 { "tx_collide_9times" },
364 { "tx_collide_10times" },
365 { "tx_collide_11times" },
366 { "tx_collide_12times" },
367 { "tx_collide_13times" },
368 { "tx_collide_14times" },
369 { "tx_collide_15times" },
370 { "tx_ucast_packets" },
371 { "tx_mcast_packets" },
372 { "tx_bcast_packets" },
373 { "tx_carrier_sense_errors" },
377 { "dma_writeq_full" },
378 { "dma_write_prioq_full" },
382 { "rx_threshold_hit" },
384 { "dma_readq_full" },
385 { "dma_read_prioq_full" },
386 { "tx_comp_queue_full" },
388 { "ring_set_send_prod_index" },
389 { "ring_status_update" },
391 { "nic_avoided_irqs" },
392 { "nic_tx_threshold_hit" },
394 { "mbuf_lwm_thresh_hit" },
397 #define TG3_NUM_STATS ARRAY_SIZE(ethtool_stats_keys)
400 static const struct {
401 const char string[ETH_GSTRING_LEN];
402 } ethtool_test_keys[] = {
403 { "nvram test (online) " },
404 { "link test (online) " },
405 { "register test (offline)" },
406 { "memory test (offline)" },
407 { "mac loopback test (offline)" },
408 { "phy loopback test (offline)" },
409 { "ext loopback test (offline)" },
410 { "interrupt test (offline)" },
413 #define TG3_NUM_TEST ARRAY_SIZE(ethtool_test_keys)
416 static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
418 writel(val, tp->regs + off);
421 static u32 tg3_read32(struct tg3 *tp, u32 off)
423 return readl(tp->regs + off);
426 static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
428 writel(val, tp->aperegs + off);
431 static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
433 return readl(tp->aperegs + off);
436 static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
440 spin_lock_irqsave(&tp->indirect_lock, flags);
441 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
442 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
443 spin_unlock_irqrestore(&tp->indirect_lock, flags);
446 static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
448 writel(val, tp->regs + off);
449 readl(tp->regs + off);
452 static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
457 spin_lock_irqsave(&tp->indirect_lock, flags);
458 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
459 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
460 spin_unlock_irqrestore(&tp->indirect_lock, flags);
464 static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
468 if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
469 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
470 TG3_64BIT_REG_LOW, val);
473 if (off == TG3_RX_STD_PROD_IDX_REG) {
474 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
475 TG3_64BIT_REG_LOW, val);
479 spin_lock_irqsave(&tp->indirect_lock, flags);
480 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
481 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
482 spin_unlock_irqrestore(&tp->indirect_lock, flags);
484 /* In indirect mode when disabling interrupts, we also need
485 * to clear the interrupt bit in the GRC local ctrl register.
487 if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
489 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
490 tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
494 static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
499 spin_lock_irqsave(&tp->indirect_lock, flags);
500 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
501 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
502 spin_unlock_irqrestore(&tp->indirect_lock, flags);
506 /* usec_wait specifies the wait time in usec when writing to certain registers
507 * where it is unsafe to read back the register without some delay.
508 * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
509 * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
511 static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
513 if (tg3_flag(tp, PCIX_TARGET_HWBUG) || tg3_flag(tp, ICH_WORKAROUND))
514 /* Non-posted methods */
515 tp->write32(tp, off, val);
518 tg3_write32(tp, off, val);
523 /* Wait again after the read for the posted method to guarantee that
524 * the wait time is met.
530 static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
532 tp->write32_mbox(tp, off, val);
533 if (!tg3_flag(tp, MBOX_WRITE_REORDER) && !tg3_flag(tp, ICH_WORKAROUND))
534 tp->read32_mbox(tp, off);
537 static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
539 void __iomem *mbox = tp->regs + off;
541 if (tg3_flag(tp, TXD_MBOX_HWBUG))
543 if (tg3_flag(tp, MBOX_WRITE_REORDER))
547 static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
549 return readl(tp->regs + off + GRCMBOX_BASE);
552 static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
554 writel(val, tp->regs + off + GRCMBOX_BASE);
557 #define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val)
558 #define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val))
559 #define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val)
560 #define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val)
561 #define tr32_mailbox(reg) tp->read32_mbox(tp, reg)
563 #define tw32(reg, val) tp->write32(tp, reg, val)
564 #define tw32_f(reg, val) _tw32_flush(tp, (reg), (val), 0)
565 #define tw32_wait_f(reg, val, us) _tw32_flush(tp, (reg), (val), (us))
566 #define tr32(reg) tp->read32(tp, reg)
568 static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
572 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 &&
573 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
576 spin_lock_irqsave(&tp->indirect_lock, flags);
577 if (tg3_flag(tp, SRAM_USE_CONFIG)) {
578 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
579 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
581 /* Always leave this as zero. */
582 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
584 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
585 tw32_f(TG3PCI_MEM_WIN_DATA, val);
587 /* Always leave this as zero. */
588 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
590 spin_unlock_irqrestore(&tp->indirect_lock, flags);
593 static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
597 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 &&
598 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
603 spin_lock_irqsave(&tp->indirect_lock, flags);
604 if (tg3_flag(tp, SRAM_USE_CONFIG)) {
605 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
606 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
608 /* Always leave this as zero. */
609 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
611 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
612 *val = tr32(TG3PCI_MEM_WIN_DATA);
614 /* Always leave this as zero. */
615 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
617 spin_unlock_irqrestore(&tp->indirect_lock, flags);
620 static void tg3_ape_lock_init(struct tg3 *tp)
625 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
626 regbase = TG3_APE_LOCK_GRANT;
628 regbase = TG3_APE_PER_LOCK_GRANT;
630 /* Make sure the driver hasn't any stale locks. */
631 for (i = TG3_APE_LOCK_PHY0; i <= TG3_APE_LOCK_GPIO; i++) {
633 case TG3_APE_LOCK_PHY0:
634 case TG3_APE_LOCK_PHY1:
635 case TG3_APE_LOCK_PHY2:
636 case TG3_APE_LOCK_PHY3:
637 bit = APE_LOCK_GRANT_DRIVER;
641 bit = APE_LOCK_GRANT_DRIVER;
643 bit = 1 << tp->pci_fn;
645 tg3_ape_write32(tp, regbase + 4 * i, bit);
650 static int tg3_ape_lock(struct tg3 *tp, int locknum)
654 u32 status, req, gnt, bit;
656 if (!tg3_flag(tp, ENABLE_APE))
660 case TG3_APE_LOCK_GPIO:
661 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
663 case TG3_APE_LOCK_GRC:
664 case TG3_APE_LOCK_MEM:
666 bit = APE_LOCK_REQ_DRIVER;
668 bit = 1 << tp->pci_fn;
674 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
675 req = TG3_APE_LOCK_REQ;
676 gnt = TG3_APE_LOCK_GRANT;
678 req = TG3_APE_PER_LOCK_REQ;
679 gnt = TG3_APE_PER_LOCK_GRANT;
684 tg3_ape_write32(tp, req + off, bit);
686 /* Wait for up to 1 millisecond to acquire lock. */
687 for (i = 0; i < 100; i++) {
688 status = tg3_ape_read32(tp, gnt + off);
695 /* Revoke the lock request. */
696 tg3_ape_write32(tp, gnt + off, bit);
703 static void tg3_ape_unlock(struct tg3 *tp, int locknum)
707 if (!tg3_flag(tp, ENABLE_APE))
711 case TG3_APE_LOCK_GPIO:
712 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
714 case TG3_APE_LOCK_GRC:
715 case TG3_APE_LOCK_MEM:
717 bit = APE_LOCK_GRANT_DRIVER;
719 bit = 1 << tp->pci_fn;
725 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
726 gnt = TG3_APE_LOCK_GRANT;
728 gnt = TG3_APE_PER_LOCK_GRANT;
730 tg3_ape_write32(tp, gnt + 4 * locknum, bit);
733 static void tg3_ape_send_event(struct tg3 *tp, u32 event)
738 /* NCSI does not support APE events */
739 if (tg3_flag(tp, APE_HAS_NCSI))
742 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
743 if (apedata != APE_SEG_SIG_MAGIC)
746 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
747 if (!(apedata & APE_FW_STATUS_READY))
750 /* Wait for up to 1 millisecond for APE to service previous event. */
751 for (i = 0; i < 10; i++) {
752 if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM))
755 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
757 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
758 tg3_ape_write32(tp, TG3_APE_EVENT_STATUS,
759 event | APE_EVENT_STATUS_EVENT_PENDING);
761 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
763 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
769 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
770 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
773 static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
778 if (!tg3_flag(tp, ENABLE_APE))
782 case RESET_KIND_INIT:
783 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
784 APE_HOST_SEG_SIG_MAGIC);
785 tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
786 APE_HOST_SEG_LEN_MAGIC);
787 apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
788 tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
789 tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
790 APE_HOST_DRIVER_ID_MAGIC(TG3_MAJ_NUM, TG3_MIN_NUM));
791 tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
792 APE_HOST_BEHAV_NO_PHYLOCK);
793 tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE,
794 TG3_APE_HOST_DRVR_STATE_START);
796 event = APE_EVENT_STATUS_STATE_START;
798 case RESET_KIND_SHUTDOWN:
799 /* With the interface we are currently using,
800 * APE does not track driver state. Wiping
801 * out the HOST SEGMENT SIGNATURE forces
802 * the APE to assume OS absent status.
804 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0);
806 if (device_may_wakeup(&tp->pdev->dev) &&
807 tg3_flag(tp, WOL_ENABLE)) {
808 tg3_ape_write32(tp, TG3_APE_HOST_WOL_SPEED,
809 TG3_APE_HOST_WOL_SPEED_AUTO);
810 apedata = TG3_APE_HOST_DRVR_STATE_WOL;
812 apedata = TG3_APE_HOST_DRVR_STATE_UNLOAD;
814 tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE, apedata);
816 event = APE_EVENT_STATUS_STATE_UNLOAD;
818 case RESET_KIND_SUSPEND:
819 event = APE_EVENT_STATUS_STATE_SUSPEND;
825 event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE;
827 tg3_ape_send_event(tp, event);
830 static void tg3_disable_ints(struct tg3 *tp)
834 tw32(TG3PCI_MISC_HOST_CTRL,
835 (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
836 for (i = 0; i < tp->irq_max; i++)
837 tw32_mailbox_f(tp->napi[i].int_mbox, 0x00000001);
840 static void tg3_enable_ints(struct tg3 *tp)
847 tw32(TG3PCI_MISC_HOST_CTRL,
848 (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
850 tp->coal_now = tp->coalesce_mode | HOSTCC_MODE_ENABLE;
851 for (i = 0; i < tp->irq_cnt; i++) {
852 struct tg3_napi *tnapi = &tp->napi[i];
854 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
855 if (tg3_flag(tp, 1SHOT_MSI))
856 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
858 tp->coal_now |= tnapi->coal_now;
861 /* Force an initial interrupt */
862 if (!tg3_flag(tp, TAGGED_STATUS) &&
863 (tp->napi[0].hw_status->status & SD_STATUS_UPDATED))
864 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
866 tw32(HOSTCC_MODE, tp->coal_now);
868 tp->coal_now &= ~(tp->napi[0].coal_now | tp->napi[1].coal_now);
871 static inline unsigned int tg3_has_work(struct tg3_napi *tnapi)
873 struct tg3 *tp = tnapi->tp;
874 struct tg3_hw_status *sblk = tnapi->hw_status;
875 unsigned int work_exists = 0;
877 /* check for phy events */
878 if (!(tg3_flag(tp, USE_LINKCHG_REG) || tg3_flag(tp, POLL_SERDES))) {
879 if (sblk->status & SD_STATUS_LINK_CHG)
882 /* check for RX/TX work to do */
883 if (sblk->idx[0].tx_consumer != tnapi->tx_cons ||
884 *(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
891 * similar to tg3_enable_ints, but it accurately determines whether there
892 * is new work pending and can return without flushing the PIO write
893 * which reenables interrupts
895 static void tg3_int_reenable(struct tg3_napi *tnapi)
897 struct tg3 *tp = tnapi->tp;
899 tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
902 /* When doing tagged status, this work check is unnecessary.
903 * The last_tag we write above tells the chip which piece of
904 * work we've completed.
906 if (!tg3_flag(tp, TAGGED_STATUS) && tg3_has_work(tnapi))
907 tw32(HOSTCC_MODE, tp->coalesce_mode |
908 HOSTCC_MODE_ENABLE | tnapi->coal_now);
911 static void tg3_switch_clocks(struct tg3 *tp)
916 if (tg3_flag(tp, CPMU_PRESENT) || tg3_flag(tp, 5780_CLASS))
919 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
921 orig_clock_ctrl = clock_ctrl;
922 clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
923 CLOCK_CTRL_CLKRUN_OENABLE |
925 tp->pci_clock_ctrl = clock_ctrl;
927 if (tg3_flag(tp, 5705_PLUS)) {
928 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
929 tw32_wait_f(TG3PCI_CLOCK_CTRL,
930 clock_ctrl | CLOCK_CTRL_625_CORE, 40);
932 } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
933 tw32_wait_f(TG3PCI_CLOCK_CTRL,
935 (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
937 tw32_wait_f(TG3PCI_CLOCK_CTRL,
938 clock_ctrl | (CLOCK_CTRL_ALTCLK),
941 tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
944 #define PHY_BUSY_LOOPS 5000
946 static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
952 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
954 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
960 frame_val = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
961 MI_COM_PHY_ADDR_MASK);
962 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
963 MI_COM_REG_ADDR_MASK);
964 frame_val |= (MI_COM_CMD_READ | MI_COM_START);
966 tw32_f(MAC_MI_COM, frame_val);
968 loops = PHY_BUSY_LOOPS;
971 frame_val = tr32(MAC_MI_COM);
973 if ((frame_val & MI_COM_BUSY) == 0) {
975 frame_val = tr32(MAC_MI_COM);
983 *val = frame_val & MI_COM_DATA_MASK;
987 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
988 tw32_f(MAC_MI_MODE, tp->mi_mode);
995 static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
1001 if ((tp->phy_flags & TG3_PHYFLG_IS_FET) &&
1002 (reg == MII_CTRL1000 || reg == MII_TG3_AUX_CTRL))
1005 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
1007 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
1011 frame_val = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
1012 MI_COM_PHY_ADDR_MASK);
1013 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
1014 MI_COM_REG_ADDR_MASK);
1015 frame_val |= (val & MI_COM_DATA_MASK);
1016 frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
1018 tw32_f(MAC_MI_COM, frame_val);
1020 loops = PHY_BUSY_LOOPS;
1021 while (loops != 0) {
1023 frame_val = tr32(MAC_MI_COM);
1024 if ((frame_val & MI_COM_BUSY) == 0) {
1026 frame_val = tr32(MAC_MI_COM);
1036 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
1037 tw32_f(MAC_MI_MODE, tp->mi_mode);
1044 static int tg3_phy_cl45_write(struct tg3 *tp, u32 devad, u32 addr, u32 val)
1048 err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad);
1052 err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr);
1056 err = tg3_writephy(tp, MII_TG3_MMD_CTRL,
1057 MII_TG3_MMD_CTRL_DATA_NOINC | devad);
1061 err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, val);
1067 static int tg3_phy_cl45_read(struct tg3 *tp, u32 devad, u32 addr, u32 *val)
1071 err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad);
1075 err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr);
1079 err = tg3_writephy(tp, MII_TG3_MMD_CTRL,
1080 MII_TG3_MMD_CTRL_DATA_NOINC | devad);
1084 err = tg3_readphy(tp, MII_TG3_MMD_ADDRESS, val);
1090 static int tg3_phydsp_read(struct tg3 *tp, u32 reg, u32 *val)
1094 err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1096 err = tg3_readphy(tp, MII_TG3_DSP_RW_PORT, val);
1101 static int tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
1105 err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1107 err = tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
1112 static int tg3_phy_auxctl_read(struct tg3 *tp, int reg, u32 *val)
1116 err = tg3_writephy(tp, MII_TG3_AUX_CTRL,
1117 (reg << MII_TG3_AUXCTL_MISC_RDSEL_SHIFT) |
1118 MII_TG3_AUXCTL_SHDWSEL_MISC);
1120 err = tg3_readphy(tp, MII_TG3_AUX_CTRL, val);
1125 static int tg3_phy_auxctl_write(struct tg3 *tp, int reg, u32 set)
1127 if (reg == MII_TG3_AUXCTL_SHDWSEL_MISC)
1128 set |= MII_TG3_AUXCTL_MISC_WREN;
1130 return tg3_writephy(tp, MII_TG3_AUX_CTRL, set | reg);
1133 #define TG3_PHY_AUXCTL_SMDSP_ENABLE(tp) \
1134 tg3_phy_auxctl_write((tp), MII_TG3_AUXCTL_SHDWSEL_AUXCTL, \
1135 MII_TG3_AUXCTL_ACTL_SMDSP_ENA | \
1136 MII_TG3_AUXCTL_ACTL_TX_6DB)
1138 #define TG3_PHY_AUXCTL_SMDSP_DISABLE(tp) \
1139 tg3_phy_auxctl_write((tp), MII_TG3_AUXCTL_SHDWSEL_AUXCTL, \
1140 MII_TG3_AUXCTL_ACTL_TX_6DB);
1142 static int tg3_bmcr_reset(struct tg3 *tp)
1147 /* OK, reset it, and poll the BMCR_RESET bit until it
1148 * clears or we time out.
1150 phy_control = BMCR_RESET;
1151 err = tg3_writephy(tp, MII_BMCR, phy_control);
1157 err = tg3_readphy(tp, MII_BMCR, &phy_control);
1161 if ((phy_control & BMCR_RESET) == 0) {
1173 static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
1175 struct tg3 *tp = bp->priv;
1178 spin_lock_bh(&tp->lock);
1180 if (tg3_readphy(tp, reg, &val))
1183 spin_unlock_bh(&tp->lock);
1188 static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
1190 struct tg3 *tp = bp->priv;
1193 spin_lock_bh(&tp->lock);
1195 if (tg3_writephy(tp, reg, val))
1198 spin_unlock_bh(&tp->lock);
1203 static int tg3_mdio_reset(struct mii_bus *bp)
1208 static void tg3_mdio_config_5785(struct tg3 *tp)
1211 struct phy_device *phydev;
1213 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1214 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
1215 case PHY_ID_BCM50610:
1216 case PHY_ID_BCM50610M:
1217 val = MAC_PHYCFG2_50610_LED_MODES;
1219 case PHY_ID_BCMAC131:
1220 val = MAC_PHYCFG2_AC131_LED_MODES;
1222 case PHY_ID_RTL8211C:
1223 val = MAC_PHYCFG2_RTL8211C_LED_MODES;
1225 case PHY_ID_RTL8201E:
1226 val = MAC_PHYCFG2_RTL8201E_LED_MODES;
1232 if (phydev->interface != PHY_INTERFACE_MODE_RGMII) {
1233 tw32(MAC_PHYCFG2, val);
1235 val = tr32(MAC_PHYCFG1);
1236 val &= ~(MAC_PHYCFG1_RGMII_INT |
1237 MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK);
1238 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT;
1239 tw32(MAC_PHYCFG1, val);
1244 if (!tg3_flag(tp, RGMII_INBAND_DISABLE))
1245 val |= MAC_PHYCFG2_EMODE_MASK_MASK |
1246 MAC_PHYCFG2_FMODE_MASK_MASK |
1247 MAC_PHYCFG2_GMODE_MASK_MASK |
1248 MAC_PHYCFG2_ACT_MASK_MASK |
1249 MAC_PHYCFG2_QUAL_MASK_MASK |
1250 MAC_PHYCFG2_INBAND_ENABLE;
1252 tw32(MAC_PHYCFG2, val);
1254 val = tr32(MAC_PHYCFG1);
1255 val &= ~(MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK |
1256 MAC_PHYCFG1_RGMII_EXT_RX_DEC | MAC_PHYCFG1_RGMII_SND_STAT_EN);
1257 if (!tg3_flag(tp, RGMII_INBAND_DISABLE)) {
1258 if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN))
1259 val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
1260 if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN))
1261 val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
1263 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT |
1264 MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV;
1265 tw32(MAC_PHYCFG1, val);
1267 val = tr32(MAC_EXT_RGMII_MODE);
1268 val &= ~(MAC_RGMII_MODE_RX_INT_B |
1269 MAC_RGMII_MODE_RX_QUALITY |
1270 MAC_RGMII_MODE_RX_ACTIVITY |
1271 MAC_RGMII_MODE_RX_ENG_DET |
1272 MAC_RGMII_MODE_TX_ENABLE |
1273 MAC_RGMII_MODE_TX_LOWPWR |
1274 MAC_RGMII_MODE_TX_RESET);
1275 if (!tg3_flag(tp, RGMII_INBAND_DISABLE)) {
1276 if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN))
1277 val |= MAC_RGMII_MODE_RX_INT_B |
1278 MAC_RGMII_MODE_RX_QUALITY |
1279 MAC_RGMII_MODE_RX_ACTIVITY |
1280 MAC_RGMII_MODE_RX_ENG_DET;
1281 if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN))
1282 val |= MAC_RGMII_MODE_TX_ENABLE |
1283 MAC_RGMII_MODE_TX_LOWPWR |
1284 MAC_RGMII_MODE_TX_RESET;
1286 tw32(MAC_EXT_RGMII_MODE, val);
1289 static void tg3_mdio_start(struct tg3 *tp)
1291 tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
1292 tw32_f(MAC_MI_MODE, tp->mi_mode);
1295 if (tg3_flag(tp, MDIOBUS_INITED) &&
1296 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1297 tg3_mdio_config_5785(tp);
1300 static int tg3_mdio_init(struct tg3 *tp)
1304 struct phy_device *phydev;
1306 if (tg3_flag(tp, 5717_PLUS)) {
1309 tp->phy_addr = tp->pci_fn + 1;
1311 if (tp->pci_chip_rev_id != CHIPREV_ID_5717_A0)
1312 is_serdes = tr32(SG_DIG_STATUS) & SG_DIG_IS_SERDES;
1314 is_serdes = tr32(TG3_CPMU_PHY_STRAP) &
1315 TG3_CPMU_PHY_STRAP_IS_SERDES;
1319 tp->phy_addr = TG3_PHY_MII_ADDR;
1323 if (!tg3_flag(tp, USE_PHYLIB) || tg3_flag(tp, MDIOBUS_INITED))
1326 tp->mdio_bus = mdiobus_alloc();
1327 if (tp->mdio_bus == NULL)
1330 tp->mdio_bus->name = "tg3 mdio bus";
1331 snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x",
1332 (tp->pdev->bus->number << 8) | tp->pdev->devfn);
1333 tp->mdio_bus->priv = tp;
1334 tp->mdio_bus->parent = &tp->pdev->dev;
1335 tp->mdio_bus->read = &tg3_mdio_read;
1336 tp->mdio_bus->write = &tg3_mdio_write;
1337 tp->mdio_bus->reset = &tg3_mdio_reset;
1338 tp->mdio_bus->phy_mask = ~(1 << TG3_PHY_MII_ADDR);
1339 tp->mdio_bus->irq = &tp->mdio_irq[0];
1341 for (i = 0; i < PHY_MAX_ADDR; i++)
1342 tp->mdio_bus->irq[i] = PHY_POLL;
1344 /* The bus registration will look for all the PHYs on the mdio bus.
1345 * Unfortunately, it does not ensure the PHY is powered up before
1346 * accessing the PHY ID registers. A chip reset is the
1347 * quickest way to bring the device back to an operational state..
1349 if (tg3_readphy(tp, MII_BMCR, ®) || (reg & BMCR_PDOWN))
1352 i = mdiobus_register(tp->mdio_bus);
1354 dev_warn(&tp->pdev->dev, "mdiobus_reg failed (0x%x)\n", i);
1355 mdiobus_free(tp->mdio_bus);
1359 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1361 if (!phydev || !phydev->drv) {
1362 dev_warn(&tp->pdev->dev, "No PHY devices\n");
1363 mdiobus_unregister(tp->mdio_bus);
1364 mdiobus_free(tp->mdio_bus);
1368 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
1369 case PHY_ID_BCM57780:
1370 phydev->interface = PHY_INTERFACE_MODE_GMII;
1371 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1373 case PHY_ID_BCM50610:
1374 case PHY_ID_BCM50610M:
1375 phydev->dev_flags |= PHY_BRCM_CLEAR_RGMII_MODE |
1376 PHY_BRCM_RX_REFCLK_UNUSED |
1377 PHY_BRCM_DIS_TXCRXC_NOENRGY |
1378 PHY_BRCM_AUTO_PWRDWN_ENABLE;
1379 if (tg3_flag(tp, RGMII_INBAND_DISABLE))
1380 phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
1381 if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN))
1382 phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
1383 if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN))
1384 phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
1386 case PHY_ID_RTL8211C:
1387 phydev->interface = PHY_INTERFACE_MODE_RGMII;
1389 case PHY_ID_RTL8201E:
1390 case PHY_ID_BCMAC131:
1391 phydev->interface = PHY_INTERFACE_MODE_MII;
1392 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1393 tp->phy_flags |= TG3_PHYFLG_IS_FET;
1397 tg3_flag_set(tp, MDIOBUS_INITED);
1399 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1400 tg3_mdio_config_5785(tp);
1405 static void tg3_mdio_fini(struct tg3 *tp)
1407 if (tg3_flag(tp, MDIOBUS_INITED)) {
1408 tg3_flag_clear(tp, MDIOBUS_INITED);
1409 mdiobus_unregister(tp->mdio_bus);
1410 mdiobus_free(tp->mdio_bus);
1414 /* tp->lock is held. */
1415 static inline void tg3_generate_fw_event(struct tg3 *tp)
1419 val = tr32(GRC_RX_CPU_EVENT);
1420 val |= GRC_RX_CPU_DRIVER_EVENT;
1421 tw32_f(GRC_RX_CPU_EVENT, val);
1423 tp->last_event_jiffies = jiffies;
1426 #define TG3_FW_EVENT_TIMEOUT_USEC 2500
1428 /* tp->lock is held. */
1429 static void tg3_wait_for_event_ack(struct tg3 *tp)
1432 unsigned int delay_cnt;
1435 /* If enough time has passed, no wait is necessary. */
1436 time_remain = (long)(tp->last_event_jiffies + 1 +
1437 usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) -
1439 if (time_remain < 0)
1442 /* Check if we can shorten the wait time. */
1443 delay_cnt = jiffies_to_usecs(time_remain);
1444 if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC)
1445 delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC;
1446 delay_cnt = (delay_cnt >> 3) + 1;
1448 for (i = 0; i < delay_cnt; i++) {
1449 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
1455 /* tp->lock is held. */
1456 static void tg3_ump_link_report(struct tg3 *tp)
1461 if (!tg3_flag(tp, 5780_CLASS) || !tg3_flag(tp, ENABLE_ASF))
1464 tg3_wait_for_event_ack(tp);
1466 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1468 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1471 if (!tg3_readphy(tp, MII_BMCR, ®))
1473 if (!tg3_readphy(tp, MII_BMSR, ®))
1474 val |= (reg & 0xffff);
1475 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, val);
1478 if (!tg3_readphy(tp, MII_ADVERTISE, ®))
1480 if (!tg3_readphy(tp, MII_LPA, ®))
1481 val |= (reg & 0xffff);
1482 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 4, val);
1485 if (!(tp->phy_flags & TG3_PHYFLG_MII_SERDES)) {
1486 if (!tg3_readphy(tp, MII_CTRL1000, ®))
1488 if (!tg3_readphy(tp, MII_STAT1000, ®))
1489 val |= (reg & 0xffff);
1491 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 8, val);
1493 if (!tg3_readphy(tp, MII_PHYADDR, ®))
1497 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 12, val);
1499 tg3_generate_fw_event(tp);
1502 /* tp->lock is held. */
1503 static void tg3_stop_fw(struct tg3 *tp)
1505 if (tg3_flag(tp, ENABLE_ASF) && !tg3_flag(tp, ENABLE_APE)) {
1506 /* Wait for RX cpu to ACK the previous event. */
1507 tg3_wait_for_event_ack(tp);
1509 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
1511 tg3_generate_fw_event(tp);
1513 /* Wait for RX cpu to ACK this event. */
1514 tg3_wait_for_event_ack(tp);
1518 /* tp->lock is held. */
1519 static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
1521 tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
1522 NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
1524 if (tg3_flag(tp, ASF_NEW_HANDSHAKE)) {
1526 case RESET_KIND_INIT:
1527 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1531 case RESET_KIND_SHUTDOWN:
1532 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1536 case RESET_KIND_SUSPEND:
1537 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1546 if (kind == RESET_KIND_INIT ||
1547 kind == RESET_KIND_SUSPEND)
1548 tg3_ape_driver_state_change(tp, kind);
1551 /* tp->lock is held. */
1552 static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
1554 if (tg3_flag(tp, ASF_NEW_HANDSHAKE)) {
1556 case RESET_KIND_INIT:
1557 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1558 DRV_STATE_START_DONE);
1561 case RESET_KIND_SHUTDOWN:
1562 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1563 DRV_STATE_UNLOAD_DONE);
1571 if (kind == RESET_KIND_SHUTDOWN)
1572 tg3_ape_driver_state_change(tp, kind);
1575 /* tp->lock is held. */
1576 static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
1578 if (tg3_flag(tp, ENABLE_ASF)) {
1580 case RESET_KIND_INIT:
1581 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1585 case RESET_KIND_SHUTDOWN:
1586 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1590 case RESET_KIND_SUSPEND:
1591 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1601 static int tg3_poll_fw(struct tg3 *tp)
1606 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1607 /* Wait up to 20ms for init done. */
1608 for (i = 0; i < 200; i++) {
1609 if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
1616 /* Wait for firmware initialization to complete. */
1617 for (i = 0; i < 100000; i++) {
1618 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
1619 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
1624 /* Chip might not be fitted with firmware. Some Sun onboard
1625 * parts are configured like that. So don't signal the timeout
1626 * of the above loop as an error, but do report the lack of
1627 * running firmware once.
1629 if (i >= 100000 && !tg3_flag(tp, NO_FWARE_REPORTED)) {
1630 tg3_flag_set(tp, NO_FWARE_REPORTED);
1632 netdev_info(tp->dev, "No firmware running\n");
1635 if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) {
1636 /* The 57765 A0 needs a little more
1637 * time to do some important work.
1645 static void tg3_link_report(struct tg3 *tp)
1647 if (!netif_carrier_ok(tp->dev)) {
1648 netif_info(tp, link, tp->dev, "Link is down\n");
1649 tg3_ump_link_report(tp);
1650 } else if (netif_msg_link(tp)) {
1651 netdev_info(tp->dev, "Link is up at %d Mbps, %s duplex\n",
1652 (tp->link_config.active_speed == SPEED_1000 ?
1654 (tp->link_config.active_speed == SPEED_100 ?
1656 (tp->link_config.active_duplex == DUPLEX_FULL ?
1659 netdev_info(tp->dev, "Flow control is %s for TX and %s for RX\n",
1660 (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ?
1662 (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ?
1665 if (tp->phy_flags & TG3_PHYFLG_EEE_CAP)
1666 netdev_info(tp->dev, "EEE is %s\n",
1667 tp->setlpicnt ? "enabled" : "disabled");
1669 tg3_ump_link_report(tp);
1673 static u16 tg3_advert_flowctrl_1000T(u8 flow_ctrl)
1677 if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1678 miireg = ADVERTISE_PAUSE_CAP;
1679 else if (flow_ctrl & FLOW_CTRL_TX)
1680 miireg = ADVERTISE_PAUSE_ASYM;
1681 else if (flow_ctrl & FLOW_CTRL_RX)
1682 miireg = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1689 static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1693 if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1694 miireg = ADVERTISE_1000XPAUSE;
1695 else if (flow_ctrl & FLOW_CTRL_TX)
1696 miireg = ADVERTISE_1000XPSE_ASYM;
1697 else if (flow_ctrl & FLOW_CTRL_RX)
1698 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1705 static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1709 if (lcladv & ADVERTISE_1000XPAUSE) {
1710 if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1711 if (rmtadv & LPA_1000XPAUSE)
1712 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1713 else if (rmtadv & LPA_1000XPAUSE_ASYM)
1716 if (rmtadv & LPA_1000XPAUSE)
1717 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1719 } else if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1720 if ((rmtadv & LPA_1000XPAUSE) && (rmtadv & LPA_1000XPAUSE_ASYM))
1727 static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
1731 u32 old_rx_mode = tp->rx_mode;
1732 u32 old_tx_mode = tp->tx_mode;
1734 if (tg3_flag(tp, USE_PHYLIB))
1735 autoneg = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]->autoneg;
1737 autoneg = tp->link_config.autoneg;
1739 if (autoneg == AUTONEG_ENABLE && tg3_flag(tp, PAUSE_AUTONEG)) {
1740 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
1741 flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
1743 flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
1745 flowctrl = tp->link_config.flowctrl;
1747 tp->link_config.active_flowctrl = flowctrl;
1749 if (flowctrl & FLOW_CTRL_RX)
1750 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1752 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1754 if (old_rx_mode != tp->rx_mode)
1755 tw32_f(MAC_RX_MODE, tp->rx_mode);
1757 if (flowctrl & FLOW_CTRL_TX)
1758 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1760 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1762 if (old_tx_mode != tp->tx_mode)
1763 tw32_f(MAC_TX_MODE, tp->tx_mode);
1766 static void tg3_adjust_link(struct net_device *dev)
1768 u8 oldflowctrl, linkmesg = 0;
1769 u32 mac_mode, lcl_adv, rmt_adv;
1770 struct tg3 *tp = netdev_priv(dev);
1771 struct phy_device *phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1773 spin_lock_bh(&tp->lock);
1775 mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
1776 MAC_MODE_HALF_DUPLEX);
1778 oldflowctrl = tp->link_config.active_flowctrl;
1784 if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
1785 mac_mode |= MAC_MODE_PORT_MODE_MII;
1786 else if (phydev->speed == SPEED_1000 ||
1787 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785)
1788 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1790 mac_mode |= MAC_MODE_PORT_MODE_MII;
1792 if (phydev->duplex == DUPLEX_HALF)
1793 mac_mode |= MAC_MODE_HALF_DUPLEX;
1795 lcl_adv = tg3_advert_flowctrl_1000T(
1796 tp->link_config.flowctrl);
1799 rmt_adv = LPA_PAUSE_CAP;
1800 if (phydev->asym_pause)
1801 rmt_adv |= LPA_PAUSE_ASYM;
1804 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1806 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1808 if (mac_mode != tp->mac_mode) {
1809 tp->mac_mode = mac_mode;
1810 tw32_f(MAC_MODE, tp->mac_mode);
1814 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
1815 if (phydev->speed == SPEED_10)
1817 MAC_MI_STAT_10MBPS_MODE |
1818 MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1820 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1823 if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
1824 tw32(MAC_TX_LENGTHS,
1825 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1826 (6 << TX_LENGTHS_IPG_SHIFT) |
1827 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
1829 tw32(MAC_TX_LENGTHS,
1830 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1831 (6 << TX_LENGTHS_IPG_SHIFT) |
1832 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
1834 if ((phydev->link && tp->link_config.active_speed == SPEED_INVALID) ||
1835 (!phydev->link && tp->link_config.active_speed != SPEED_INVALID) ||
1836 phydev->speed != tp->link_config.active_speed ||
1837 phydev->duplex != tp->link_config.active_duplex ||
1838 oldflowctrl != tp->link_config.active_flowctrl)
1841 tp->link_config.active_speed = phydev->speed;
1842 tp->link_config.active_duplex = phydev->duplex;
1844 spin_unlock_bh(&tp->lock);
1847 tg3_link_report(tp);
1850 static int tg3_phy_init(struct tg3 *tp)
1852 struct phy_device *phydev;
1854 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)
1857 /* Bring the PHY back to a known state. */
1860 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1862 /* Attach the MAC to the PHY. */
1863 phydev = phy_connect(tp->dev, dev_name(&phydev->dev), tg3_adjust_link,
1864 phydev->dev_flags, phydev->interface);
1865 if (IS_ERR(phydev)) {
1866 dev_err(&tp->pdev->dev, "Could not attach to PHY\n");
1867 return PTR_ERR(phydev);
1870 /* Mask with MAC supported features. */
1871 switch (phydev->interface) {
1872 case PHY_INTERFACE_MODE_GMII:
1873 case PHY_INTERFACE_MODE_RGMII:
1874 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
1875 phydev->supported &= (PHY_GBIT_FEATURES |
1877 SUPPORTED_Asym_Pause);
1881 case PHY_INTERFACE_MODE_MII:
1882 phydev->supported &= (PHY_BASIC_FEATURES |
1884 SUPPORTED_Asym_Pause);
1887 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1891 tp->phy_flags |= TG3_PHYFLG_IS_CONNECTED;
1893 phydev->advertising = phydev->supported;
1898 static void tg3_phy_start(struct tg3 *tp)
1900 struct phy_device *phydev;
1902 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
1905 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1907 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
1908 tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER;
1909 phydev->speed = tp->link_config.orig_speed;
1910 phydev->duplex = tp->link_config.orig_duplex;
1911 phydev->autoneg = tp->link_config.orig_autoneg;
1912 phydev->advertising = tp->link_config.orig_advertising;
1917 phy_start_aneg(phydev);
1920 static void tg3_phy_stop(struct tg3 *tp)
1922 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
1925 phy_stop(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1928 static void tg3_phy_fini(struct tg3 *tp)
1930 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
1931 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1932 tp->phy_flags &= ~TG3_PHYFLG_IS_CONNECTED;
1936 static int tg3_phy_set_extloopbk(struct tg3 *tp)
1941 if (tp->phy_flags & TG3_PHYFLG_IS_FET)
1944 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
1945 /* Cannot do read-modify-write on 5401 */
1946 err = tg3_phy_auxctl_write(tp,
1947 MII_TG3_AUXCTL_SHDWSEL_AUXCTL,
1948 MII_TG3_AUXCTL_ACTL_EXTLOOPBK |
1953 err = tg3_phy_auxctl_read(tp,
1954 MII_TG3_AUXCTL_SHDWSEL_AUXCTL, &val);
1958 val |= MII_TG3_AUXCTL_ACTL_EXTLOOPBK;
1959 err = tg3_phy_auxctl_write(tp,
1960 MII_TG3_AUXCTL_SHDWSEL_AUXCTL, val);
1966 static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable)
1970 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
1973 tg3_writephy(tp, MII_TG3_FET_TEST,
1974 phytest | MII_TG3_FET_SHADOW_EN);
1975 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXSTAT2, &phy)) {
1977 phy |= MII_TG3_FET_SHDW_AUXSTAT2_APD;
1979 phy &= ~MII_TG3_FET_SHDW_AUXSTAT2_APD;
1980 tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy);
1982 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
1986 static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable)
1990 if (!tg3_flag(tp, 5705_PLUS) ||
1991 (tg3_flag(tp, 5717_PLUS) &&
1992 (tp->phy_flags & TG3_PHYFLG_MII_SERDES)))
1995 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
1996 tg3_phy_fet_toggle_apd(tp, enable);
2000 reg = MII_TG3_MISC_SHDW_WREN |
2001 MII_TG3_MISC_SHDW_SCR5_SEL |
2002 MII_TG3_MISC_SHDW_SCR5_LPED |
2003 MII_TG3_MISC_SHDW_SCR5_DLPTLM |
2004 MII_TG3_MISC_SHDW_SCR5_SDTL |
2005 MII_TG3_MISC_SHDW_SCR5_C125OE;
2006 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 || !enable)
2007 reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD;
2009 tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
2012 reg = MII_TG3_MISC_SHDW_WREN |
2013 MII_TG3_MISC_SHDW_APD_SEL |
2014 MII_TG3_MISC_SHDW_APD_WKTM_84MS;
2016 reg |= MII_TG3_MISC_SHDW_APD_ENABLE;
2018 tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
2021 static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
2025 if (!tg3_flag(tp, 5705_PLUS) ||
2026 (tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
2029 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
2032 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) {
2033 u32 reg = MII_TG3_FET_SHDW_MISCCTRL;
2035 tg3_writephy(tp, MII_TG3_FET_TEST,
2036 ephy | MII_TG3_FET_SHADOW_EN);
2037 if (!tg3_readphy(tp, reg, &phy)) {
2039 phy |= MII_TG3_FET_SHDW_MISCCTRL_MDIX;
2041 phy &= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX;
2042 tg3_writephy(tp, reg, phy);
2044 tg3_writephy(tp, MII_TG3_FET_TEST, ephy);
2049 ret = tg3_phy_auxctl_read(tp,
2050 MII_TG3_AUXCTL_SHDWSEL_MISC, &phy);
2053 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
2055 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
2056 tg3_phy_auxctl_write(tp,
2057 MII_TG3_AUXCTL_SHDWSEL_MISC, phy);
2062 static void tg3_phy_set_wirespeed(struct tg3 *tp)
2067 if (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED)
2070 ret = tg3_phy_auxctl_read(tp, MII_TG3_AUXCTL_SHDWSEL_MISC, &val);
2072 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_MISC,
2073 val | MII_TG3_AUXCTL_MISC_WIRESPD_EN);
2076 static void tg3_phy_apply_otp(struct tg3 *tp)
2085 if (TG3_PHY_AUXCTL_SMDSP_ENABLE(tp))
2088 phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
2089 phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
2090 tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
2092 phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
2093 ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
2094 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
2096 phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
2097 phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
2098 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
2100 phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
2101 tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
2103 phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
2104 tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
2106 phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
2107 ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
2108 tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
2110 TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
2113 static void tg3_phy_eee_adjust(struct tg3 *tp, u32 current_link_up)
2117 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))
2122 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
2123 current_link_up == 1 &&
2124 tp->link_config.active_duplex == DUPLEX_FULL &&
2125 (tp->link_config.active_speed == SPEED_100 ||
2126 tp->link_config.active_speed == SPEED_1000)) {
2129 if (tp->link_config.active_speed == SPEED_1000)
2130 eeectl = TG3_CPMU_EEE_CTRL_EXIT_16_5_US;
2132 eeectl = TG3_CPMU_EEE_CTRL_EXIT_36_US;
2134 tw32(TG3_CPMU_EEE_CTRL, eeectl);
2136 tg3_phy_cl45_read(tp, MDIO_MMD_AN,
2137 TG3_CL45_D7_EEERES_STAT, &val);
2139 if (val == TG3_CL45_D7_EEERES_STAT_LP_1000T ||
2140 val == TG3_CL45_D7_EEERES_STAT_LP_100TX)
2144 if (!tp->setlpicnt) {
2145 if (current_link_up == 1 &&
2146 !TG3_PHY_AUXCTL_SMDSP_ENABLE(tp)) {
2147 tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, 0x0000);
2148 TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
2151 val = tr32(TG3_CPMU_EEE_MODE);
2152 tw32(TG3_CPMU_EEE_MODE, val & ~TG3_CPMU_EEEMD_LPI_ENABLE);
2156 static void tg3_phy_eee_enable(struct tg3 *tp)
2160 if (tp->link_config.active_speed == SPEED_1000 &&
2161 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
2162 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
2163 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) &&
2164 !TG3_PHY_AUXCTL_SMDSP_ENABLE(tp)) {
2165 val = MII_TG3_DSP_TAP26_ALNOKO |
2166 MII_TG3_DSP_TAP26_RMRXSTO;
2167 tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, val);
2168 TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
2171 val = tr32(TG3_CPMU_EEE_MODE);
2172 tw32(TG3_CPMU_EEE_MODE, val | TG3_CPMU_EEEMD_LPI_ENABLE);
2175 static int tg3_wait_macro_done(struct tg3 *tp)
2182 if (!tg3_readphy(tp, MII_TG3_DSP_CONTROL, &tmp32)) {
2183 if ((tmp32 & 0x1000) == 0)
2193 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
2195 static const u32 test_pat[4][6] = {
2196 { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
2197 { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
2198 { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
2199 { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
2203 for (chan = 0; chan < 4; chan++) {
2206 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
2207 (chan * 0x2000) | 0x0200);
2208 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
2210 for (i = 0; i < 6; i++)
2211 tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
2214 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
2215 if (tg3_wait_macro_done(tp)) {
2220 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
2221 (chan * 0x2000) | 0x0200);
2222 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0082);
2223 if (tg3_wait_macro_done(tp)) {
2228 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0802);
2229 if (tg3_wait_macro_done(tp)) {
2234 for (i = 0; i < 6; i += 2) {
2237 if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
2238 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
2239 tg3_wait_macro_done(tp)) {
2245 if (low != test_pat[chan][i] ||
2246 high != test_pat[chan][i+1]) {
2247 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
2248 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
2249 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
2259 static int tg3_phy_reset_chanpat(struct tg3 *tp)
2263 for (chan = 0; chan < 4; chan++) {
2266 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
2267 (chan * 0x2000) | 0x0200);
2268 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
2269 for (i = 0; i < 6; i++)
2270 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
2271 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
2272 if (tg3_wait_macro_done(tp))
2279 static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
2281 u32 reg32, phy9_orig;
2282 int retries, do_phy_reset, err;
2288 err = tg3_bmcr_reset(tp);
2294 /* Disable transmitter and interrupt. */
2295 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, ®32))
2299 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
2301 /* Set full-duplex, 1000 mbps. */
2302 tg3_writephy(tp, MII_BMCR,
2303 BMCR_FULLDPLX | BMCR_SPEED1000);
2305 /* Set to master mode. */
2306 if (tg3_readphy(tp, MII_CTRL1000, &phy9_orig))
2309 tg3_writephy(tp, MII_CTRL1000,
2310 CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER);
2312 err = TG3_PHY_AUXCTL_SMDSP_ENABLE(tp);
2316 /* Block the PHY control access. */
2317 tg3_phydsp_write(tp, 0x8005, 0x0800);
2319 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
2322 } while (--retries);
2324 err = tg3_phy_reset_chanpat(tp);
2328 tg3_phydsp_write(tp, 0x8005, 0x0000);
2330 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
2331 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0000);
2333 TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
2335 tg3_writephy(tp, MII_CTRL1000, phy9_orig);
2337 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, ®32)) {
2339 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
2346 /* This will reset the tigon3 PHY if there is no valid
2347 * link unless the FORCE argument is non-zero.
2349 static int tg3_phy_reset(struct tg3 *tp)
2354 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2355 val = tr32(GRC_MISC_CFG);
2356 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
2359 err = tg3_readphy(tp, MII_BMSR, &val);
2360 err |= tg3_readphy(tp, MII_BMSR, &val);
2364 if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
2365 netif_carrier_off(tp->dev);
2366 tg3_link_report(tp);
2369 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2370 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2371 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
2372 err = tg3_phy_reset_5703_4_5(tp);
2379 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
2380 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
2381 cpmuctrl = tr32(TG3_CPMU_CTRL);
2382 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
2384 cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
2387 err = tg3_bmcr_reset(tp);
2391 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
2392 val = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
2393 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, val);
2395 tw32(TG3_CPMU_CTRL, cpmuctrl);
2398 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
2399 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
2400 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2401 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
2402 CPMU_LSPD_1000MB_MACCLK_12_5) {
2403 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2405 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2409 if (tg3_flag(tp, 5717_PLUS) &&
2410 (tp->phy_flags & TG3_PHYFLG_MII_SERDES))
2413 tg3_phy_apply_otp(tp);
2415 if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
2416 tg3_phy_toggle_apd(tp, true);
2418 tg3_phy_toggle_apd(tp, false);
2421 if ((tp->phy_flags & TG3_PHYFLG_ADC_BUG) &&
2422 !TG3_PHY_AUXCTL_SMDSP_ENABLE(tp)) {
2423 tg3_phydsp_write(tp, 0x201f, 0x2aaa);
2424 tg3_phydsp_write(tp, 0x000a, 0x0323);
2425 TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
2428 if (tp->phy_flags & TG3_PHYFLG_5704_A0_BUG) {
2429 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
2430 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
2433 if (tp->phy_flags & TG3_PHYFLG_BER_BUG) {
2434 if (!TG3_PHY_AUXCTL_SMDSP_ENABLE(tp)) {
2435 tg3_phydsp_write(tp, 0x000a, 0x310b);
2436 tg3_phydsp_write(tp, 0x201f, 0x9506);
2437 tg3_phydsp_write(tp, 0x401f, 0x14e2);
2438 TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
2440 } else if (tp->phy_flags & TG3_PHYFLG_JITTER_BUG) {
2441 if (!TG3_PHY_AUXCTL_SMDSP_ENABLE(tp)) {
2442 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
2443 if (tp->phy_flags & TG3_PHYFLG_ADJUST_TRIM) {
2444 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
2445 tg3_writephy(tp, MII_TG3_TEST1,
2446 MII_TG3_TEST1_TRIM_EN | 0x4);
2448 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
2450 TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
2454 /* Set Extended packet length bit (bit 14) on all chips that */
2455 /* support jumbo frames */
2456 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
2457 /* Cannot do read-modify-write on 5401 */
2458 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, 0x4c20);
2459 } else if (tg3_flag(tp, JUMBO_CAPABLE)) {
2460 /* Set bit 14 with read-modify-write to preserve other bits */
2461 err = tg3_phy_auxctl_read(tp,
2462 MII_TG3_AUXCTL_SHDWSEL_AUXCTL, &val);
2464 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL,
2465 val | MII_TG3_AUXCTL_ACTL_EXTPKTLEN);
2468 /* Set phy register 0x10 bit 0 to high fifo elasticity to support
2469 * jumbo frames transmission.
2471 if (tg3_flag(tp, JUMBO_CAPABLE)) {
2472 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &val))
2473 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2474 val | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
2477 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2478 /* adjust output voltage */
2479 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12);
2482 tg3_phy_toggle_automdix(tp, 1);
2483 tg3_phy_set_wirespeed(tp);
2487 #define TG3_GPIO_MSG_DRVR_PRES 0x00000001
2488 #define TG3_GPIO_MSG_NEED_VAUX 0x00000002
2489 #define TG3_GPIO_MSG_MASK (TG3_GPIO_MSG_DRVR_PRES | \
2490 TG3_GPIO_MSG_NEED_VAUX)
2491 #define TG3_GPIO_MSG_ALL_DRVR_PRES_MASK \
2492 ((TG3_GPIO_MSG_DRVR_PRES << 0) | \
2493 (TG3_GPIO_MSG_DRVR_PRES << 4) | \
2494 (TG3_GPIO_MSG_DRVR_PRES << 8) | \
2495 (TG3_GPIO_MSG_DRVR_PRES << 12))
2497 #define TG3_GPIO_MSG_ALL_NEED_VAUX_MASK \
2498 ((TG3_GPIO_MSG_NEED_VAUX << 0) | \
2499 (TG3_GPIO_MSG_NEED_VAUX << 4) | \
2500 (TG3_GPIO_MSG_NEED_VAUX << 8) | \
2501 (TG3_GPIO_MSG_NEED_VAUX << 12))
2503 static inline u32 tg3_set_function_status(struct tg3 *tp, u32 newstat)
2507 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
2508 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
2509 status = tg3_ape_read32(tp, TG3_APE_GPIO_MSG);
2511 status = tr32(TG3_CPMU_DRV_STATUS);
2513 shift = TG3_APE_GPIO_MSG_SHIFT + 4 * tp->pci_fn;
2514 status &= ~(TG3_GPIO_MSG_MASK << shift);
2515 status |= (newstat << shift);
2517 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
2518 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
2519 tg3_ape_write32(tp, TG3_APE_GPIO_MSG, status);
2521 tw32(TG3_CPMU_DRV_STATUS, status);
2523 return status >> TG3_APE_GPIO_MSG_SHIFT;
2526 static inline int tg3_pwrsrc_switch_to_vmain(struct tg3 *tp)
2528 if (!tg3_flag(tp, IS_NIC))
2531 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
2532 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
2533 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) {
2534 if (tg3_ape_lock(tp, TG3_APE_LOCK_GPIO))
2537 tg3_set_function_status(tp, TG3_GPIO_MSG_DRVR_PRES);
2539 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl,
2540 TG3_GRC_LCLCTL_PWRSW_DELAY);
2542 tg3_ape_unlock(tp, TG3_APE_LOCK_GPIO);
2544 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl,
2545 TG3_GRC_LCLCTL_PWRSW_DELAY);
2551 static void tg3_pwrsrc_die_with_vmain(struct tg3 *tp)
2555 if (!tg3_flag(tp, IS_NIC) ||
2556 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2557 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)
2560 grc_local_ctrl = tp->grc_local_ctrl | GRC_LCLCTRL_GPIO_OE1;
2562 tw32_wait_f(GRC_LOCAL_CTRL,
2563 grc_local_ctrl | GRC_LCLCTRL_GPIO_OUTPUT1,
2564 TG3_GRC_LCLCTL_PWRSW_DELAY);
2566 tw32_wait_f(GRC_LOCAL_CTRL,
2568 TG3_GRC_LCLCTL_PWRSW_DELAY);
2570 tw32_wait_f(GRC_LOCAL_CTRL,
2571 grc_local_ctrl | GRC_LCLCTRL_GPIO_OUTPUT1,
2572 TG3_GRC_LCLCTL_PWRSW_DELAY);
2575 static void tg3_pwrsrc_switch_to_vaux(struct tg3 *tp)
2577 if (!tg3_flag(tp, IS_NIC))
2580 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2581 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2582 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2583 (GRC_LCLCTRL_GPIO_OE0 |
2584 GRC_LCLCTRL_GPIO_OE1 |
2585 GRC_LCLCTRL_GPIO_OE2 |
2586 GRC_LCLCTRL_GPIO_OUTPUT0 |
2587 GRC_LCLCTRL_GPIO_OUTPUT1),
2588 TG3_GRC_LCLCTL_PWRSW_DELAY);
2589 } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
2590 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
2591 /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
2592 u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
2593 GRC_LCLCTRL_GPIO_OE1 |
2594 GRC_LCLCTRL_GPIO_OE2 |
2595 GRC_LCLCTRL_GPIO_OUTPUT0 |
2596 GRC_LCLCTRL_GPIO_OUTPUT1 |
2598 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl,
2599 TG3_GRC_LCLCTL_PWRSW_DELAY);
2601 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
2602 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl,
2603 TG3_GRC_LCLCTL_PWRSW_DELAY);
2605 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
2606 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl,
2607 TG3_GRC_LCLCTL_PWRSW_DELAY);
2610 u32 grc_local_ctrl = 0;
2612 /* Workaround to prevent overdrawing Amps. */
2613 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
2614 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
2615 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2617 TG3_GRC_LCLCTL_PWRSW_DELAY);
2620 /* On 5753 and variants, GPIO2 cannot be used. */
2621 no_gpio2 = tp->nic_sram_data_cfg &
2622 NIC_SRAM_DATA_CFG_NO_GPIO2;
2624 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
2625 GRC_LCLCTRL_GPIO_OE1 |
2626 GRC_LCLCTRL_GPIO_OE2 |
2627 GRC_LCLCTRL_GPIO_OUTPUT1 |
2628 GRC_LCLCTRL_GPIO_OUTPUT2;
2630 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
2631 GRC_LCLCTRL_GPIO_OUTPUT2);
2633 tw32_wait_f(GRC_LOCAL_CTRL,
2634 tp->grc_local_ctrl | grc_local_ctrl,
2635 TG3_GRC_LCLCTL_PWRSW_DELAY);
2637 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
2639 tw32_wait_f(GRC_LOCAL_CTRL,
2640 tp->grc_local_ctrl | grc_local_ctrl,
2641 TG3_GRC_LCLCTL_PWRSW_DELAY);
2644 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
2645 tw32_wait_f(GRC_LOCAL_CTRL,
2646 tp->grc_local_ctrl | grc_local_ctrl,
2647 TG3_GRC_LCLCTL_PWRSW_DELAY);
2652 static void tg3_frob_aux_power_5717(struct tg3 *tp, bool wol_enable)
2656 /* Serialize power state transitions */
2657 if (tg3_ape_lock(tp, TG3_APE_LOCK_GPIO))
2660 if (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE) || wol_enable)
2661 msg = TG3_GPIO_MSG_NEED_VAUX;
2663 msg = tg3_set_function_status(tp, msg);
2665 if (msg & TG3_GPIO_MSG_ALL_DRVR_PRES_MASK)
2668 if (msg & TG3_GPIO_MSG_ALL_NEED_VAUX_MASK)
2669 tg3_pwrsrc_switch_to_vaux(tp);
2671 tg3_pwrsrc_die_with_vmain(tp);
2674 tg3_ape_unlock(tp, TG3_APE_LOCK_GPIO);
2677 static void tg3_frob_aux_power(struct tg3 *tp, bool include_wol)
2679 bool need_vaux = false;
2681 /* The GPIOs do something completely different on 57765. */
2682 if (!tg3_flag(tp, IS_NIC) ||
2683 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
2686 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
2687 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
2688 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) {
2689 tg3_frob_aux_power_5717(tp, include_wol ?
2690 tg3_flag(tp, WOL_ENABLE) != 0 : 0);
2694 if (tp->pdev_peer && tp->pdev_peer != tp->pdev) {
2695 struct net_device *dev_peer;
2697 dev_peer = pci_get_drvdata(tp->pdev_peer);
2699 /* remove_one() may have been run on the peer. */
2701 struct tg3 *tp_peer = netdev_priv(dev_peer);
2703 if (tg3_flag(tp_peer, INIT_COMPLETE))
2706 if ((include_wol && tg3_flag(tp_peer, WOL_ENABLE)) ||
2707 tg3_flag(tp_peer, ENABLE_ASF))
2712 if ((include_wol && tg3_flag(tp, WOL_ENABLE)) ||
2713 tg3_flag(tp, ENABLE_ASF))
2717 tg3_pwrsrc_switch_to_vaux(tp);
2719 tg3_pwrsrc_die_with_vmain(tp);
2722 static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
2724 if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
2726 else if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411) {
2727 if (speed != SPEED_10)
2729 } else if (speed == SPEED_10)
2735 static int tg3_setup_phy(struct tg3 *, int);
2736 static int tg3_halt_cpu(struct tg3 *, u32);
2738 static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
2742 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
2743 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2744 u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
2745 u32 serdes_cfg = tr32(MAC_SERDES_CFG);
2748 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
2749 tw32(SG_DIG_CTRL, sg_dig_ctrl);
2750 tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
2755 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2757 val = tr32(GRC_MISC_CFG);
2758 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
2761 } else if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
2763 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
2766 tg3_writephy(tp, MII_ADVERTISE, 0);
2767 tg3_writephy(tp, MII_BMCR,
2768 BMCR_ANENABLE | BMCR_ANRESTART);
2770 tg3_writephy(tp, MII_TG3_FET_TEST,
2771 phytest | MII_TG3_FET_SHADOW_EN);
2772 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXMODE4, &phy)) {
2773 phy |= MII_TG3_FET_SHDW_AUXMODE4_SBPD;
2775 MII_TG3_FET_SHDW_AUXMODE4,
2778 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
2781 } else if (do_low_power) {
2782 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2783 MII_TG3_EXT_CTRL_FORCE_LED_OFF);
2785 val = MII_TG3_AUXCTL_PCTL_100TX_LPWR |
2786 MII_TG3_AUXCTL_PCTL_SPR_ISOLATE |
2787 MII_TG3_AUXCTL_PCTL_VREG_11V;
2788 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_PWRCTL, val);
2791 /* The PHY should not be powered down on some chips because
2794 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2795 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2796 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
2797 (tp->phy_flags & TG3_PHYFLG_MII_SERDES)))
2800 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
2801 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
2802 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2803 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2804 val |= CPMU_LSPD_1000MB_MACCLK_12_5;
2805 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2808 tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
2811 /* tp->lock is held. */
2812 static int tg3_nvram_lock(struct tg3 *tp)
2814 if (tg3_flag(tp, NVRAM)) {
2817 if (tp->nvram_lock_cnt == 0) {
2818 tw32(NVRAM_SWARB, SWARB_REQ_SET1);
2819 for (i = 0; i < 8000; i++) {
2820 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
2825 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
2829 tp->nvram_lock_cnt++;
2834 /* tp->lock is held. */
2835 static void tg3_nvram_unlock(struct tg3 *tp)
2837 if (tg3_flag(tp, NVRAM)) {
2838 if (tp->nvram_lock_cnt > 0)
2839 tp->nvram_lock_cnt--;
2840 if (tp->nvram_lock_cnt == 0)
2841 tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
2845 /* tp->lock is held. */
2846 static void tg3_enable_nvram_access(struct tg3 *tp)
2848 if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM)) {
2849 u32 nvaccess = tr32(NVRAM_ACCESS);
2851 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
2855 /* tp->lock is held. */
2856 static void tg3_disable_nvram_access(struct tg3 *tp)
2858 if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM)) {
2859 u32 nvaccess = tr32(NVRAM_ACCESS);
2861 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
2865 static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
2866 u32 offset, u32 *val)
2871 if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0)
2874 tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
2875 EEPROM_ADDR_DEVID_MASK |
2877 tw32(GRC_EEPROM_ADDR,
2879 (0 << EEPROM_ADDR_DEVID_SHIFT) |
2880 ((offset << EEPROM_ADDR_ADDR_SHIFT) &
2881 EEPROM_ADDR_ADDR_MASK) |
2882 EEPROM_ADDR_READ | EEPROM_ADDR_START);
2884 for (i = 0; i < 1000; i++) {
2885 tmp = tr32(GRC_EEPROM_ADDR);
2887 if (tmp & EEPROM_ADDR_COMPLETE)
2891 if (!(tmp & EEPROM_ADDR_COMPLETE))
2894 tmp = tr32(GRC_EEPROM_DATA);
2897 * The data will always be opposite the native endian
2898 * format. Perform a blind byteswap to compensate.
2905 #define NVRAM_CMD_TIMEOUT 10000
2907 static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
2911 tw32(NVRAM_CMD, nvram_cmd);
2912 for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
2914 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
2920 if (i == NVRAM_CMD_TIMEOUT)
2926 static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
2928 if (tg3_flag(tp, NVRAM) &&
2929 tg3_flag(tp, NVRAM_BUFFERED) &&
2930 tg3_flag(tp, FLASH) &&
2931 !tg3_flag(tp, NO_NVRAM_ADDR_TRANS) &&
2932 (tp->nvram_jedecnum == JEDEC_ATMEL))
2934 addr = ((addr / tp->nvram_pagesize) <<
2935 ATMEL_AT45DB0X1B_PAGE_POS) +
2936 (addr % tp->nvram_pagesize);
2941 static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
2943 if (tg3_flag(tp, NVRAM) &&
2944 tg3_flag(tp, NVRAM_BUFFERED) &&
2945 tg3_flag(tp, FLASH) &&
2946 !tg3_flag(tp, NO_NVRAM_ADDR_TRANS) &&
2947 (tp->nvram_jedecnum == JEDEC_ATMEL))
2949 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
2950 tp->nvram_pagesize) +
2951 (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
2956 /* NOTE: Data read in from NVRAM is byteswapped according to
2957 * the byteswapping settings for all other register accesses.
2958 * tg3 devices are BE devices, so on a BE machine, the data
2959 * returned will be exactly as it is seen in NVRAM. On a LE
2960 * machine, the 32-bit value will be byteswapped.
2962 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
2966 if (!tg3_flag(tp, NVRAM))
2967 return tg3_nvram_read_using_eeprom(tp, offset, val);
2969 offset = tg3_nvram_phys_addr(tp, offset);
2971 if (offset > NVRAM_ADDR_MSK)
2974 ret = tg3_nvram_lock(tp);
2978 tg3_enable_nvram_access(tp);
2980 tw32(NVRAM_ADDR, offset);
2981 ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
2982 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
2985 *val = tr32(NVRAM_RDDATA);
2987 tg3_disable_nvram_access(tp);
2989 tg3_nvram_unlock(tp);
2994 /* Ensures NVRAM data is in bytestream format. */
2995 static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val)
2998 int res = tg3_nvram_read(tp, offset, &v);
3000 *val = cpu_to_be32(v);
3004 #define RX_CPU_SCRATCH_BASE 0x30000
3005 #define RX_CPU_SCRATCH_SIZE 0x04000
3006 #define TX_CPU_SCRATCH_BASE 0x34000
3007 #define TX_CPU_SCRATCH_SIZE 0x04000
3009 /* tp->lock is held. */
3010 static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
3014 BUG_ON(offset == TX_CPU_BASE && tg3_flag(tp, 5705_PLUS));
3016 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
3017 u32 val = tr32(GRC_VCPU_EXT_CTRL);
3019 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
3022 if (offset == RX_CPU_BASE) {
3023 for (i = 0; i < 10000; i++) {
3024 tw32(offset + CPU_STATE, 0xffffffff);
3025 tw32(offset + CPU_MODE, CPU_MODE_HALT);
3026 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
3030 tw32(offset + CPU_STATE, 0xffffffff);
3031 tw32_f(offset + CPU_MODE, CPU_MODE_HALT);
3034 for (i = 0; i < 10000; i++) {
3035 tw32(offset + CPU_STATE, 0xffffffff);
3036 tw32(offset + CPU_MODE, CPU_MODE_HALT);
3037 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
3043 netdev_err(tp->dev, "%s timed out, %s CPU\n",
3044 __func__, offset == RX_CPU_BASE ? "RX" : "TX");
3048 /* Clear firmware's nvram arbitration. */
3049 if (tg3_flag(tp, NVRAM))
3050 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
3055 unsigned int fw_base;
3056 unsigned int fw_len;
3057 const __be32 *fw_data;
3060 /* tp->lock is held. */
3061 static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base,
3062 u32 cpu_scratch_base, int cpu_scratch_size,
3063 struct fw_info *info)
3065 int err, lock_err, i;
3066 void (*write_op)(struct tg3 *, u32, u32);
3068 if (cpu_base == TX_CPU_BASE && tg3_flag(tp, 5705_PLUS)) {
3070 "%s: Trying to load TX cpu firmware which is 5705\n",
3075 if (tg3_flag(tp, 5705_PLUS))
3076 write_op = tg3_write_mem;
3078 write_op = tg3_write_indirect_reg32;
3080 /* It is possible that bootcode is still loading at this point.
3081 * Get the nvram lock first before halting the cpu.
3083 lock_err = tg3_nvram_lock(tp);
3084 err = tg3_halt_cpu(tp, cpu_base);
3086 tg3_nvram_unlock(tp);
3090 for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
3091 write_op(tp, cpu_scratch_base + i, 0);
3092 tw32(cpu_base + CPU_STATE, 0xffffffff);
3093 tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
3094 for (i = 0; i < (info->fw_len / sizeof(u32)); i++)
3095 write_op(tp, (cpu_scratch_base +
3096 (info->fw_base & 0xffff) +
3098 be32_to_cpu(info->fw_data[i]));
3106 /* tp->lock is held. */
3107 static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
3109 struct fw_info info;
3110 const __be32 *fw_data;
3113 fw_data = (void *)tp->fw->data;
3115 /* Firmware blob starts with version numbers, followed by
3116 start address and length. We are setting complete length.
3117 length = end_address_of_bss - start_address_of_text.
3118 Remainder is the blob to be loaded contiguously
3119 from start address. */
3121 info.fw_base = be32_to_cpu(fw_data[1]);
3122 info.fw_len = tp->fw->size - 12;
3123 info.fw_data = &fw_data[3];
3125 err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
3126 RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
3131 err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
3132 TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
3137 /* Now startup only the RX cpu. */
3138 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
3139 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
3141 for (i = 0; i < 5; i++) {
3142 if (tr32(RX_CPU_BASE + CPU_PC) == info.fw_base)
3144 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
3145 tw32(RX_CPU_BASE + CPU_MODE, CPU_MODE_HALT);
3146 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
3150 netdev_err(tp->dev, "%s fails to set RX CPU PC, is %08x "
3151 "should be %08x\n", __func__,
3152 tr32(RX_CPU_BASE + CPU_PC), info.fw_base);
3155 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
3156 tw32_f(RX_CPU_BASE + CPU_MODE, 0x00000000);
3161 /* tp->lock is held. */
3162 static int tg3_load_tso_firmware(struct tg3 *tp)
3164 struct fw_info info;
3165 const __be32 *fw_data;
3166 unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
3169 if (tg3_flag(tp, HW_TSO_1) ||
3170 tg3_flag(tp, HW_TSO_2) ||
3171 tg3_flag(tp, HW_TSO_3))
3174 fw_data = (void *)tp->fw->data;
3176 /* Firmware blob starts with version numbers, followed by
3177 start address and length. We are setting complete length.
3178 length = end_address_of_bss - start_address_of_text.
3179 Remainder is the blob to be loaded contiguously
3180 from start address. */
3182 info.fw_base = be32_to_cpu(fw_data[1]);
3183 cpu_scratch_size = tp->fw_len;
3184 info.fw_len = tp->fw->size - 12;
3185 info.fw_data = &fw_data[3];
3187 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
3188 cpu_base = RX_CPU_BASE;
3189 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
3191 cpu_base = TX_CPU_BASE;
3192 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
3193 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
3196 err = tg3_load_firmware_cpu(tp, cpu_base,
3197 cpu_scratch_base, cpu_scratch_size,
3202 /* Now startup the cpu. */
3203 tw32(cpu_base + CPU_STATE, 0xffffffff);
3204 tw32_f(cpu_base + CPU_PC, info.fw_base);
3206 for (i = 0; i < 5; i++) {
3207 if (tr32(cpu_base + CPU_PC) == info.fw_base)
3209 tw32(cpu_base + CPU_STATE, 0xffffffff);
3210 tw32(cpu_base + CPU_MODE, CPU_MODE_HALT);
3211 tw32_f(cpu_base + CPU_PC, info.fw_base);
3216 "%s fails to set CPU PC, is %08x should be %08x\n",
3217 __func__, tr32(cpu_base + CPU_PC), info.fw_base);
3220 tw32(cpu_base + CPU_STATE, 0xffffffff);
3221 tw32_f(cpu_base + CPU_MODE, 0x00000000);
3226 /* tp->lock is held. */
3227 static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1)
3229 u32 addr_high, addr_low;
3232 addr_high = ((tp->dev->dev_addr[0] << 8) |
3233 tp->dev->dev_addr[1]);
3234 addr_low = ((tp->dev->dev_addr[2] << 24) |
3235 (tp->dev->dev_addr[3] << 16) |
3236 (tp->dev->dev_addr[4] << 8) |
3237 (tp->dev->dev_addr[5] << 0));
3238 for (i = 0; i < 4; i++) {
3239 if (i == 1 && skip_mac_1)
3241 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
3242 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
3245 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
3246 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
3247 for (i = 0; i < 12; i++) {
3248 tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
3249 tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
3253 addr_high = (tp->dev->dev_addr[0] +
3254 tp->dev->dev_addr[1] +
3255 tp->dev->dev_addr[2] +
3256 tp->dev->dev_addr[3] +
3257 tp->dev->dev_addr[4] +
3258 tp->dev->dev_addr[5]) &
3259 TX_BACKOFF_SEED_MASK;
3260 tw32(MAC_TX_BACKOFF_SEED, addr_high);
3263 static void tg3_enable_register_access(struct tg3 *tp)
3266 * Make sure register accesses (indirect or otherwise) will function
3269 pci_write_config_dword(tp->pdev,
3270 TG3PCI_MISC_HOST_CTRL, tp->misc_host_ctrl);
3273 static int tg3_power_up(struct tg3 *tp)
3277 tg3_enable_register_access(tp);
3279 err = pci_set_power_state(tp->pdev, PCI_D0);
3281 /* Switch out of Vaux if it is a NIC */
3282 tg3_pwrsrc_switch_to_vmain(tp);
3284 netdev_err(tp->dev, "Transition to D0 failed\n");
3290 static int tg3_power_down_prepare(struct tg3 *tp)
3293 bool device_should_wake, do_low_power;
3295 tg3_enable_register_access(tp);
3297 /* Restore the CLKREQ setting. */
3298 if (tg3_flag(tp, CLKREQ_BUG)) {
3301 pci_read_config_word(tp->pdev,
3302 pci_pcie_cap(tp->pdev) + PCI_EXP_LNKCTL,
3304 lnkctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
3305 pci_write_config_word(tp->pdev,
3306 pci_pcie_cap(tp->pdev) + PCI_EXP_LNKCTL,
3310 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
3311 tw32(TG3PCI_MISC_HOST_CTRL,
3312 misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
3314 device_should_wake = device_may_wakeup(&tp->pdev->dev) &&
3315 tg3_flag(tp, WOL_ENABLE);
3317 if (tg3_flag(tp, USE_PHYLIB)) {
3318 do_low_power = false;
3319 if ((tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) &&
3320 !(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
3321 struct phy_device *phydev;
3322 u32 phyid, advertising;
3324 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
3326 tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER;
3328 tp->link_config.orig_speed = phydev->speed;
3329 tp->link_config.orig_duplex = phydev->duplex;
3330 tp->link_config.orig_autoneg = phydev->autoneg;
3331 tp->link_config.orig_advertising = phydev->advertising;
3333 advertising = ADVERTISED_TP |
3335 ADVERTISED_Autoneg |
3336 ADVERTISED_10baseT_Half;
3338 if (tg3_flag(tp, ENABLE_ASF) || device_should_wake) {
3339 if (tg3_flag(tp, WOL_SPEED_100MB))
3341 ADVERTISED_100baseT_Half |
3342 ADVERTISED_100baseT_Full |
3343 ADVERTISED_10baseT_Full;
3345 advertising |= ADVERTISED_10baseT_Full;
3348 phydev->advertising = advertising;
3350 phy_start_aneg(phydev);
3352 phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask;
3353 if (phyid != PHY_ID_BCMAC131) {
3354 phyid &= PHY_BCM_OUI_MASK;
3355 if (phyid == PHY_BCM_OUI_1 ||
3356 phyid == PHY_BCM_OUI_2 ||
3357 phyid == PHY_BCM_OUI_3)
3358 do_low_power = true;
3362 do_low_power = true;
3364 if (!(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
3365 tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER;
3366 tp->link_config.orig_speed = tp->link_config.speed;
3367 tp->link_config.orig_duplex = tp->link_config.duplex;
3368 tp->link_config.orig_autoneg = tp->link_config.autoneg;
3371 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
3372 tp->link_config.speed = SPEED_10;
3373 tp->link_config.duplex = DUPLEX_HALF;
3374 tp->link_config.autoneg = AUTONEG_ENABLE;
3375 tg3_setup_phy(tp, 0);
3379 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
3382 val = tr32(GRC_VCPU_EXT_CTRL);
3383 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
3384 } else if (!tg3_flag(tp, ENABLE_ASF)) {
3388 for (i = 0; i < 200; i++) {
3389 tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
3390 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
3395 if (tg3_flag(tp, WOL_CAP))
3396 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
3397 WOL_DRV_STATE_SHUTDOWN |
3401 if (device_should_wake) {
3404 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
3406 !(tp->phy_flags & TG3_PHYFLG_IS_FET)) {
3407 tg3_phy_auxctl_write(tp,
3408 MII_TG3_AUXCTL_SHDWSEL_PWRCTL,
3409 MII_TG3_AUXCTL_PCTL_WOL_EN |
3410 MII_TG3_AUXCTL_PCTL_100TX_LPWR |
3411 MII_TG3_AUXCTL_PCTL_CL_AB_TXDAC);
3415 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
3416 mac_mode = MAC_MODE_PORT_MODE_GMII;
3418 mac_mode = MAC_MODE_PORT_MODE_MII;
3420 mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
3421 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
3423 u32 speed = tg3_flag(tp, WOL_SPEED_100MB) ?
3424 SPEED_100 : SPEED_10;
3425 if (tg3_5700_link_polarity(tp, speed))
3426 mac_mode |= MAC_MODE_LINK_POLARITY;
3428 mac_mode &= ~MAC_MODE_LINK_POLARITY;
3431 mac_mode = MAC_MODE_PORT_MODE_TBI;
3434 if (!tg3_flag(tp, 5750_PLUS))
3435 tw32(MAC_LED_CTRL, tp->led_ctrl);
3437 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
3438 if ((tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, 5780_CLASS)) &&
3439 (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE)))
3440 mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL;
3442 if (tg3_flag(tp, ENABLE_APE))
3443 mac_mode |= MAC_MODE_APE_TX_EN |
3444 MAC_MODE_APE_RX_EN |
3445 MAC_MODE_TDE_ENABLE;
3447 tw32_f(MAC_MODE, mac_mode);
3450 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
3454 if (!tg3_flag(tp, WOL_SPEED_100MB) &&
3455 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
3456 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
3459 base_val = tp->pci_clock_ctrl;
3460 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
3461 CLOCK_CTRL_TXCLK_DISABLE);
3463 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
3464 CLOCK_CTRL_PWRDOWN_PLL133, 40);
3465 } else if (tg3_flag(tp, 5780_CLASS) ||
3466 tg3_flag(tp, CPMU_PRESENT) ||
3467 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
3469 } else if (!(tg3_flag(tp, 5750_PLUS) && tg3_flag(tp, ENABLE_ASF))) {
3470 u32 newbits1, newbits2;
3472 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
3473 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
3474 newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
3475 CLOCK_CTRL_TXCLK_DISABLE |
3477 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
3478 } else if (tg3_flag(tp, 5705_PLUS)) {
3479 newbits1 = CLOCK_CTRL_625_CORE;
3480 newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
3482 newbits1 = CLOCK_CTRL_ALTCLK;
3483 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
3486 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
3489 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
3492 if (!tg3_flag(tp, 5705_PLUS)) {
3495 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
3496 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
3497 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
3498 CLOCK_CTRL_TXCLK_DISABLE |
3499 CLOCK_CTRL_44MHZ_CORE);
3501 newbits3 = CLOCK_CTRL_44MHZ_CORE;
3504 tw32_wait_f(TG3PCI_CLOCK_CTRL,
3505 tp->pci_clock_ctrl | newbits3, 40);
3509 if (!(device_should_wake) && !tg3_flag(tp, ENABLE_ASF))
3510 tg3_power_down_phy(tp, do_low_power);
3512 tg3_frob_aux_power(tp, true);
3514 /* Workaround for unstable PLL clock */
3515 if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
3516 (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
3517 u32 val = tr32(0x7d00);
3519 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
3521 if (!tg3_flag(tp, ENABLE_ASF)) {
3524 err = tg3_nvram_lock(tp);
3525 tg3_halt_cpu(tp, RX_CPU_BASE);
3527 tg3_nvram_unlock(tp);
3531 tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
3536 static void tg3_power_down(struct tg3 *tp)
3538 tg3_power_down_prepare(tp);
3540 pci_wake_from_d3(tp->pdev, tg3_flag(tp, WOL_ENABLE));
3541 pci_set_power_state(tp->pdev, PCI_D3hot);
3544 static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
3546 switch (val & MII_TG3_AUX_STAT_SPDMASK) {
3547 case MII_TG3_AUX_STAT_10HALF:
3549 *duplex = DUPLEX_HALF;
3552 case MII_TG3_AUX_STAT_10FULL:
3554 *duplex = DUPLEX_FULL;
3557 case MII_TG3_AUX_STAT_100HALF:
3559 *duplex = DUPLEX_HALF;
3562 case MII_TG3_AUX_STAT_100FULL:
3564 *duplex = DUPLEX_FULL;
3567 case MII_TG3_AUX_STAT_1000HALF:
3568 *speed = SPEED_1000;
3569 *duplex = DUPLEX_HALF;
3572 case MII_TG3_AUX_STAT_1000FULL:
3573 *speed = SPEED_1000;
3574 *duplex = DUPLEX_FULL;
3578 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
3579 *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
3581 *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
3585 *speed = SPEED_INVALID;
3586 *duplex = DUPLEX_INVALID;
3591 static int tg3_phy_autoneg_cfg(struct tg3 *tp, u32 advertise, u32 flowctrl)
3596 new_adv = ADVERTISE_CSMA;
3597 if (advertise & ADVERTISED_10baseT_Half)
3598 new_adv |= ADVERTISE_10HALF;
3599 if (advertise & ADVERTISED_10baseT_Full)
3600 new_adv |= ADVERTISE_10FULL;
3601 if (advertise & ADVERTISED_100baseT_Half)
3602 new_adv |= ADVERTISE_100HALF;
3603 if (advertise & ADVERTISED_100baseT_Full)
3604 new_adv |= ADVERTISE_100FULL;
3606 new_adv |= tg3_advert_flowctrl_1000T(flowctrl);
3608 err = tg3_writephy(tp, MII_ADVERTISE, new_adv);
3612 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
3616 if (advertise & ADVERTISED_1000baseT_Half)
3617 new_adv |= ADVERTISE_1000HALF;
3618 if (advertise & ADVERTISED_1000baseT_Full)
3619 new_adv |= ADVERTISE_1000FULL;
3621 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
3622 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
3623 new_adv |= CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER;
3625 err = tg3_writephy(tp, MII_CTRL1000, new_adv);
3629 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))
3632 tw32(TG3_CPMU_EEE_MODE,
3633 tr32(TG3_CPMU_EEE_MODE) & ~TG3_CPMU_EEEMD_LPI_ENABLE);
3635 err = TG3_PHY_AUXCTL_SMDSP_ENABLE(tp);
3640 /* Advertise 100-BaseTX EEE ability */
3641 if (advertise & ADVERTISED_100baseT_Full)
3642 val |= MDIO_AN_EEE_ADV_100TX;
3643 /* Advertise 1000-BaseT EEE ability */
3644 if (advertise & ADVERTISED_1000baseT_Full)
3645 val |= MDIO_AN_EEE_ADV_1000T;
3646 err = tg3_phy_cl45_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val);
3650 switch (GET_ASIC_REV(tp->pci_chip_rev_id)) {
3652 case ASIC_REV_57765:
3654 /* If we advertised any eee advertisements above... */
3656 val = MII_TG3_DSP_TAP26_ALNOKO |
3657 MII_TG3_DSP_TAP26_RMRXSTO |
3658 MII_TG3_DSP_TAP26_OPCSINPT;
3659 tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, val);
3662 if (!tg3_phydsp_read(tp, MII_TG3_DSP_CH34TP2, &val))
3663 tg3_phydsp_write(tp, MII_TG3_DSP_CH34TP2, val |
3664 MII_TG3_DSP_CH34TP2_HIBW01);
3667 err2 = TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
3676 static void tg3_phy_copper_begin(struct tg3 *tp)
3681 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
3682 new_adv = ADVERTISED_10baseT_Half |
3683 ADVERTISED_10baseT_Full;
3684 if (tg3_flag(tp, WOL_SPEED_100MB))
3685 new_adv |= ADVERTISED_100baseT_Half |
3686 ADVERTISED_100baseT_Full;
3688 tg3_phy_autoneg_cfg(tp, new_adv,
3689 FLOW_CTRL_TX | FLOW_CTRL_RX);
3690 } else if (tp->link_config.speed == SPEED_INVALID) {
3691 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
3692 tp->link_config.advertising &=
3693 ~(ADVERTISED_1000baseT_Half |
3694 ADVERTISED_1000baseT_Full);
3696 tg3_phy_autoneg_cfg(tp, tp->link_config.advertising,
3697 tp->link_config.flowctrl);
3699 /* Asking for a specific link mode. */
3700 if (tp->link_config.speed == SPEED_1000) {
3701 if (tp->link_config.duplex == DUPLEX_FULL)
3702 new_adv = ADVERTISED_1000baseT_Full;
3704 new_adv = ADVERTISED_1000baseT_Half;
3705 } else if (tp->link_config.speed == SPEED_100) {
3706 if (tp->link_config.duplex == DUPLEX_FULL)
3707 new_adv = ADVERTISED_100baseT_Full;
3709 new_adv = ADVERTISED_100baseT_Half;
3711 if (tp->link_config.duplex == DUPLEX_FULL)
3712 new_adv = ADVERTISED_10baseT_Full;
3714 new_adv = ADVERTISED_10baseT_Half;
3717 tg3_phy_autoneg_cfg(tp, new_adv,
3718 tp->link_config.flowctrl);
3721 if (tp->link_config.autoneg == AUTONEG_DISABLE &&
3722 tp->link_config.speed != SPEED_INVALID) {
3723 u32 bmcr, orig_bmcr;
3725 tp->link_config.active_speed = tp->link_config.speed;
3726 tp->link_config.active_duplex = tp->link_config.duplex;
3729 switch (tp->link_config.speed) {
3735 bmcr |= BMCR_SPEED100;
3739 bmcr |= BMCR_SPEED1000;
3743 if (tp->link_config.duplex == DUPLEX_FULL)
3744 bmcr |= BMCR_FULLDPLX;
3746 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
3747 (bmcr != orig_bmcr)) {
3748 tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
3749 for (i = 0; i < 1500; i++) {
3753 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
3754 tg3_readphy(tp, MII_BMSR, &tmp))
3756 if (!(tmp & BMSR_LSTATUS)) {
3761 tg3_writephy(tp, MII_BMCR, bmcr);
3765 tg3_writephy(tp, MII_BMCR,
3766 BMCR_ANENABLE | BMCR_ANRESTART);
3770 static int tg3_init_5401phy_dsp(struct tg3 *tp)
3774 /* Turn off tap power management. */
3775 /* Set Extended packet length bit */
3776 err = tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, 0x4c20);
3778 err |= tg3_phydsp_write(tp, 0x0012, 0x1804);
3779 err |= tg3_phydsp_write(tp, 0x0013, 0x1204);
3780 err |= tg3_phydsp_write(tp, 0x8006, 0x0132);
3781 err |= tg3_phydsp_write(tp, 0x8006, 0x0232);
3782 err |= tg3_phydsp_write(tp, 0x201f, 0x0a20);
3789 static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
3791 u32 adv_reg, all_mask = 0;
3793 if (mask & ADVERTISED_10baseT_Half)
3794 all_mask |= ADVERTISE_10HALF;
3795 if (mask & ADVERTISED_10baseT_Full)
3796 all_mask |= ADVERTISE_10FULL;
3797 if (mask & ADVERTISED_100baseT_Half)
3798 all_mask |= ADVERTISE_100HALF;
3799 if (mask & ADVERTISED_100baseT_Full)
3800 all_mask |= ADVERTISE_100FULL;
3802 if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
3805 if ((adv_reg & ADVERTISE_ALL) != all_mask)
3808 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
3812 if (mask & ADVERTISED_1000baseT_Half)
3813 all_mask |= ADVERTISE_1000HALF;
3814 if (mask & ADVERTISED_1000baseT_Full)
3815 all_mask |= ADVERTISE_1000FULL;
3817 if (tg3_readphy(tp, MII_CTRL1000, &tg3_ctrl))
3820 tg3_ctrl &= (ADVERTISE_1000HALF | ADVERTISE_1000FULL);
3821 if (tg3_ctrl != all_mask)
3828 static int tg3_adv_1000T_flowctrl_ok(struct tg3 *tp, u32 *lcladv, u32 *rmtadv)
3832 if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
3835 curadv = *lcladv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
3836 reqadv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
3838 if (tp->link_config.active_duplex == DUPLEX_FULL) {
3839 if (curadv != reqadv)
3842 if (tg3_flag(tp, PAUSE_AUTONEG))
3843 tg3_readphy(tp, MII_LPA, rmtadv);
3845 /* Reprogram the advertisement register, even if it
3846 * does not affect the current link. If the link
3847 * gets renegotiated in the future, we can save an
3848 * additional renegotiation cycle by advertising
3849 * it correctly in the first place.
3851 if (curadv != reqadv) {
3852 *lcladv &= ~(ADVERTISE_PAUSE_CAP |
3853 ADVERTISE_PAUSE_ASYM);
3854 tg3_writephy(tp, MII_ADVERTISE, *lcladv | reqadv);
3861 static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
3863 int current_link_up;
3865 u32 lcl_adv, rmt_adv;
3873 (MAC_STATUS_SYNC_CHANGED |
3874 MAC_STATUS_CFG_CHANGED |
3875 MAC_STATUS_MI_COMPLETION |
3876 MAC_STATUS_LNKSTATE_CHANGED));
3879 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
3881 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
3885 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_PWRCTL, 0);
3887 /* Some third-party PHYs need to be reset on link going
3890 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
3891 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
3892 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
3893 netif_carrier_ok(tp->dev)) {
3894 tg3_readphy(tp, MII_BMSR, &bmsr);
3895 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3896 !(bmsr & BMSR_LSTATUS))
3902 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
3903 tg3_readphy(tp, MII_BMSR, &bmsr);
3904 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
3905 !tg3_flag(tp, INIT_COMPLETE))
3908 if (!(bmsr & BMSR_LSTATUS)) {
3909 err = tg3_init_5401phy_dsp(tp);
3913 tg3_readphy(tp, MII_BMSR, &bmsr);
3914 for (i = 0; i < 1000; i++) {
3916 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3917 (bmsr & BMSR_LSTATUS)) {
3923 if ((tp->phy_id & TG3_PHY_ID_REV_MASK) ==
3924 TG3_PHY_REV_BCM5401_B0 &&
3925 !(bmsr & BMSR_LSTATUS) &&
3926 tp->link_config.active_speed == SPEED_1000) {
3927 err = tg3_phy_reset(tp);
3929 err = tg3_init_5401phy_dsp(tp);
3934 } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
3935 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
3936 /* 5701 {A0,B0} CRC bug workaround */
3937 tg3_writephy(tp, 0x15, 0x0a75);
3938 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);
3939 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
3940 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);
3943 /* Clear pending interrupts... */
3944 tg3_readphy(tp, MII_TG3_ISTAT, &val);
3945 tg3_readphy(tp, MII_TG3_ISTAT, &val);
3947 if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT)
3948 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
3949 else if (!(tp->phy_flags & TG3_PHYFLG_IS_FET))
3950 tg3_writephy(tp, MII_TG3_IMASK, ~0);
3952 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
3953 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
3954 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
3955 tg3_writephy(tp, MII_TG3_EXT_CTRL,
3956 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
3958 tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
3961 current_link_up = 0;
3962 current_speed = SPEED_INVALID;
3963 current_duplex = DUPLEX_INVALID;
3965 if (tp->phy_flags & TG3_PHYFLG_CAPACITIVE_COUPLING) {
3966 err = tg3_phy_auxctl_read(tp,
3967 MII_TG3_AUXCTL_SHDWSEL_MISCTEST,
3969 if (!err && !(val & (1 << 10))) {
3970 tg3_phy_auxctl_write(tp,
3971 MII_TG3_AUXCTL_SHDWSEL_MISCTEST,
3978 for (i = 0; i < 100; i++) {
3979 tg3_readphy(tp, MII_BMSR, &bmsr);
3980 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3981 (bmsr & BMSR_LSTATUS))
3986 if (bmsr & BMSR_LSTATUS) {
3989 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
3990 for (i = 0; i < 2000; i++) {
3992 if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
3997 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
4002 for (i = 0; i < 200; i++) {
4003 tg3_readphy(tp, MII_BMCR, &bmcr);
4004 if (tg3_readphy(tp, MII_BMCR, &bmcr))
4006 if (bmcr && bmcr != 0x7fff)
4014 tp->link_config.active_speed = current_speed;
4015 tp->link_config.active_duplex = current_duplex;
4017 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
4018 if ((bmcr & BMCR_ANENABLE) &&
4019 tg3_copper_is_advertising_all(tp,
4020 tp->link_config.advertising)) {
4021 if (tg3_adv_1000T_flowctrl_ok(tp, &lcl_adv,
4023 current_link_up = 1;
4026 if (!(bmcr & BMCR_ANENABLE) &&
4027 tp->link_config.speed == current_speed &&
4028 tp->link_config.duplex == current_duplex &&
4029 tp->link_config.flowctrl ==
4030 tp->link_config.active_flowctrl) {
4031 current_link_up = 1;
4035 if (current_link_up == 1 &&
4036 tp->link_config.active_duplex == DUPLEX_FULL)
4037 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
4041 if (current_link_up == 0 || (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
4042 tg3_phy_copper_begin(tp);
4044 tg3_readphy(tp, MII_BMSR, &bmsr);
4045 if ((!tg3_readphy(tp, MII_BMSR, &bmsr) && (bmsr & BMSR_LSTATUS)) ||
4046 (tp->mac_mode & MAC_MODE_PORT_INT_LPBACK))
4047 current_link_up = 1;
4050 tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
4051 if (current_link_up == 1) {
4052 if (tp->link_config.active_speed == SPEED_100 ||
4053 tp->link_config.active_speed == SPEED_10)
4054 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
4056 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
4057 } else if (tp->phy_flags & TG3_PHYFLG_IS_FET)
4058 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
4060 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
4062 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
4063 if (tp->link_config.active_duplex == DUPLEX_HALF)
4064 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
4066 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
4067 if (current_link_up == 1 &&
4068 tg3_5700_link_polarity(tp, tp->link_config.active_speed))
4069 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
4071 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
4074 /* ??? Without this setting Netgear GA302T PHY does not
4075 * ??? send/receive packets...
4077 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411 &&
4078 tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
4079 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
4080 tw32_f(MAC_MI_MODE, tp->mi_mode);
4084 tw32_f(MAC_MODE, tp->mac_mode);
4087 tg3_phy_eee_adjust(tp, current_link_up);
4089 if (tg3_flag(tp, USE_LINKCHG_REG)) {
4090 /* Polled via timer. */
4091 tw32_f(MAC_EVENT, 0);
4093 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4097 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
4098 current_link_up == 1 &&
4099 tp->link_config.active_speed == SPEED_1000 &&
4100 (tg3_flag(tp, PCIX_MODE) || tg3_flag(tp, PCI_HIGH_SPEED))) {
4103 (MAC_STATUS_SYNC_CHANGED |
4104 MAC_STATUS_CFG_CHANGED));
4107 NIC_SRAM_FIRMWARE_MBOX,
4108 NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
4111 /* Prevent send BD corruption. */
4112 if (tg3_flag(tp, CLKREQ_BUG)) {
4113 u16 oldlnkctl, newlnkctl;
4115 pci_read_config_word(tp->pdev,
4116 pci_pcie_cap(tp->pdev) + PCI_EXP_LNKCTL,
4118 if (tp->link_config.active_speed == SPEED_100 ||
4119 tp->link_config.active_speed == SPEED_10)
4120 newlnkctl = oldlnkctl & ~PCI_EXP_LNKCTL_CLKREQ_EN;
4122 newlnkctl = oldlnkctl | PCI_EXP_LNKCTL_CLKREQ_EN;
4123 if (newlnkctl != oldlnkctl)
4124 pci_write_config_word(tp->pdev,
4125 pci_pcie_cap(tp->pdev) +
4126 PCI_EXP_LNKCTL, newlnkctl);
4129 if (current_link_up != netif_carrier_ok(tp->dev)) {
4130 if (current_link_up)
4131 netif_carrier_on(tp->dev);
4133 netif_carrier_off(tp->dev);
4134 tg3_link_report(tp);
4140 struct tg3_fiber_aneginfo {
4142 #define ANEG_STATE_UNKNOWN 0
4143 #define ANEG_STATE_AN_ENABLE 1
4144 #define ANEG_STATE_RESTART_INIT 2
4145 #define ANEG_STATE_RESTART 3
4146 #define ANEG_STATE_DISABLE_LINK_OK 4
4147 #define ANEG_STATE_ABILITY_DETECT_INIT 5
4148 #define ANEG_STATE_ABILITY_DETECT 6
4149 #define ANEG_STATE_ACK_DETECT_INIT 7
4150 #define ANEG_STATE_ACK_DETECT 8
4151 #define ANEG_STATE_COMPLETE_ACK_INIT 9
4152 #define ANEG_STATE_COMPLETE_ACK 10
4153 #define ANEG_STATE_IDLE_DETECT_INIT 11
4154 #define ANEG_STATE_IDLE_DETECT 12
4155 #define ANEG_STATE_LINK_OK 13
4156 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT 14
4157 #define ANEG_STATE_NEXT_PAGE_WAIT 15
4160 #define MR_AN_ENABLE 0x00000001
4161 #define MR_RESTART_AN 0x00000002
4162 #define MR_AN_COMPLETE 0x00000004
4163 #define MR_PAGE_RX 0x00000008
4164 #define MR_NP_LOADED 0x00000010
4165 #define MR_TOGGLE_TX 0x00000020
4166 #define MR_LP_ADV_FULL_DUPLEX 0x00000040
4167 #define MR_LP_ADV_HALF_DUPLEX 0x00000080
4168 #define MR_LP_ADV_SYM_PAUSE 0x00000100
4169 #define MR_LP_ADV_ASYM_PAUSE 0x00000200
4170 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
4171 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
4172 #define MR_LP_ADV_NEXT_PAGE 0x00001000
4173 #define MR_TOGGLE_RX 0x00002000
4174 #define MR_NP_RX 0x00004000
4176 #define MR_LINK_OK 0x80000000
4178 unsigned long link_time, cur_time;
4180 u32 ability_match_cfg;
4181 int ability_match_count;
4183 char ability_match, idle_match, ack_match;
4185 u32 txconfig, rxconfig;
4186 #define ANEG_CFG_NP 0x00000080
4187 #define ANEG_CFG_ACK 0x00000040
4188 #define ANEG_CFG_RF2 0x00000020
4189 #define ANEG_CFG_RF1 0x00000010
4190 #define ANEG_CFG_PS2 0x00000001
4191 #define ANEG_CFG_PS1 0x00008000
4192 #define ANEG_CFG_HD 0x00004000
4193 #define ANEG_CFG_FD 0x00002000
4194 #define ANEG_CFG_INVAL 0x00001f06
4199 #define ANEG_TIMER_ENAB 2
4200 #define ANEG_FAILED -1
4202 #define ANEG_STATE_SETTLE_TIME 10000
4204 static int tg3_fiber_aneg_smachine(struct tg3 *tp,
4205 struct tg3_fiber_aneginfo *ap)
4208 unsigned long delta;
4212 if (ap->state == ANEG_STATE_UNKNOWN) {
4216 ap->ability_match_cfg = 0;
4217 ap->ability_match_count = 0;
4218 ap->ability_match = 0;
4224 if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
4225 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
4227 if (rx_cfg_reg != ap->ability_match_cfg) {
4228 ap->ability_match_cfg = rx_cfg_reg;
4229 ap->ability_match = 0;
4230 ap->ability_match_count = 0;
4232 if (++ap->ability_match_count > 1) {
4233 ap->ability_match = 1;
4234 ap->ability_match_cfg = rx_cfg_reg;
4237 if (rx_cfg_reg & ANEG_CFG_ACK)
4245 ap->ability_match_cfg = 0;
4246 ap->ability_match_count = 0;
4247 ap->ability_match = 0;
4253 ap->rxconfig = rx_cfg_reg;
4256 switch (ap->state) {
4257 case ANEG_STATE_UNKNOWN:
4258 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
4259 ap->state = ANEG_STATE_AN_ENABLE;
4262 case ANEG_STATE_AN_ENABLE:
4263 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
4264 if (ap->flags & MR_AN_ENABLE) {
4267 ap->ability_match_cfg = 0;
4268 ap->ability_match_count = 0;
4269 ap->ability_match = 0;
4273 ap->state = ANEG_STATE_RESTART_INIT;
4275 ap->state = ANEG_STATE_DISABLE_LINK_OK;
4279 case ANEG_STATE_RESTART_INIT:
4280 ap->link_time = ap->cur_time;
4281 ap->flags &= ~(MR_NP_LOADED);
4283 tw32(MAC_TX_AUTO_NEG, 0);
4284 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
4285 tw32_f(MAC_MODE, tp->mac_mode);
4288 ret = ANEG_TIMER_ENAB;
4289 ap->state = ANEG_STATE_RESTART;
4292 case ANEG_STATE_RESTART:
4293 delta = ap->cur_time - ap->link_time;
4294 if (delta > ANEG_STATE_SETTLE_TIME)
4295 ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
4297 ret = ANEG_TIMER_ENAB;
4300 case ANEG_STATE_DISABLE_LINK_OK:
4304 case ANEG_STATE_ABILITY_DETECT_INIT:
4305 ap->flags &= ~(MR_TOGGLE_TX);
4306 ap->txconfig = ANEG_CFG_FD;
4307 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
4308 if (flowctrl & ADVERTISE_1000XPAUSE)
4309 ap->txconfig |= ANEG_CFG_PS1;
4310 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
4311 ap->txconfig |= ANEG_CFG_PS2;
4312 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
4313 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
4314 tw32_f(MAC_MODE, tp->mac_mode);
4317 ap->state = ANEG_STATE_ABILITY_DETECT;
4320 case ANEG_STATE_ABILITY_DETECT:
4321 if (ap->ability_match != 0 && ap->rxconfig != 0)
4322 ap->state = ANEG_STATE_ACK_DETECT_INIT;
4325 case ANEG_STATE_ACK_DETECT_INIT:
4326 ap->txconfig |= ANEG_CFG_ACK;
4327 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
4328 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
4329 tw32_f(MAC_MODE, tp->mac_mode);
4332 ap->state = ANEG_STATE_ACK_DETECT;
4335 case ANEG_STATE_ACK_DETECT:
4336 if (ap->ack_match != 0) {
4337 if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
4338 (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
4339 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
4341 ap->state = ANEG_STATE_AN_ENABLE;
4343 } else if (ap->ability_match != 0 &&
4344 ap->rxconfig == 0) {
4345 ap->state = ANEG_STATE_AN_ENABLE;
4349 case ANEG_STATE_COMPLETE_ACK_INIT:
4350 if (ap->rxconfig & ANEG_CFG_INVAL) {
4354 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
4355 MR_LP_ADV_HALF_DUPLEX |
4356 MR_LP_ADV_SYM_PAUSE |
4357 MR_LP_ADV_ASYM_PAUSE |
4358 MR_LP_ADV_REMOTE_FAULT1 |
4359 MR_LP_ADV_REMOTE_FAULT2 |
4360 MR_LP_ADV_NEXT_PAGE |
4363 if (ap->rxconfig & ANEG_CFG_FD)
4364 ap->flags |= MR_LP_ADV_FULL_DUPLEX;
4365 if (ap->rxconfig & ANEG_CFG_HD)
4366 ap->flags |= MR_LP_ADV_HALF_DUPLEX;
4367 if (ap->rxconfig & ANEG_CFG_PS1)
4368 ap->flags |= MR_LP_ADV_SYM_PAUSE;
4369 if (ap->rxconfig & ANEG_CFG_PS2)
4370 ap->flags |= MR_LP_ADV_ASYM_PAUSE;
4371 if (ap->rxconfig & ANEG_CFG_RF1)
4372 ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
4373 if (ap->rxconfig & ANEG_CFG_RF2)
4374 ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
4375 if (ap->rxconfig & ANEG_CFG_NP)
4376 ap->flags |= MR_LP_ADV_NEXT_PAGE;
4378 ap->link_time = ap->cur_time;
4380 ap->flags ^= (MR_TOGGLE_TX);
4381 if (ap->rxconfig & 0x0008)
4382 ap->flags |= MR_TOGGLE_RX;
4383 if (ap->rxconfig & ANEG_CFG_NP)
4384 ap->flags |= MR_NP_RX;
4385 ap->flags |= MR_PAGE_RX;
4387 ap->state = ANEG_STATE_COMPLETE_ACK;
4388 ret = ANEG_TIMER_ENAB;
4391 case ANEG_STATE_COMPLETE_ACK:
4392 if (ap->ability_match != 0 &&
4393 ap->rxconfig == 0) {
4394 ap->state = ANEG_STATE_AN_ENABLE;
4397 delta = ap->cur_time - ap->link_time;
4398 if (delta > ANEG_STATE_SETTLE_TIME) {
4399 if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
4400 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
4402 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
4403 !(ap->flags & MR_NP_RX)) {
4404 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
4412 case ANEG_STATE_IDLE_DETECT_INIT:
4413 ap->link_time = ap->cur_time;
4414 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
4415 tw32_f(MAC_MODE, tp->mac_mode);
4418 ap->state = ANEG_STATE_IDLE_DETECT;
4419 ret = ANEG_TIMER_ENAB;
4422 case ANEG_STATE_IDLE_DETECT:
4423 if (ap->ability_match != 0 &&
4424 ap->rxconfig == 0) {
4425 ap->state = ANEG_STATE_AN_ENABLE;
4428 delta = ap->cur_time - ap->link_time;
4429 if (delta > ANEG_STATE_SETTLE_TIME) {
4430 /* XXX another gem from the Broadcom driver :( */
4431 ap->state = ANEG_STATE_LINK_OK;
4435 case ANEG_STATE_LINK_OK:
4436 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
4440 case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
4441 /* ??? unimplemented */
4444 case ANEG_STATE_NEXT_PAGE_WAIT:
4445 /* ??? unimplemented */
4456 static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
4459 struct tg3_fiber_aneginfo aninfo;
4460 int status = ANEG_FAILED;
4464 tw32_f(MAC_TX_AUTO_NEG, 0);
4466 tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
4467 tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
4470 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
4473 memset(&aninfo, 0, sizeof(aninfo));
4474 aninfo.flags |= MR_AN_ENABLE;
4475 aninfo.state = ANEG_STATE_UNKNOWN;
4476 aninfo.cur_time = 0;
4478 while (++tick < 195000) {
4479 status = tg3_fiber_aneg_smachine(tp, &aninfo);
4480 if (status == ANEG_DONE || status == ANEG_FAILED)
4486 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
4487 tw32_f(MAC_MODE, tp->mac_mode);
4490 *txflags = aninfo.txconfig;
4491 *rxflags = aninfo.flags;
4493 if (status == ANEG_DONE &&
4494 (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
4495 MR_LP_ADV_FULL_DUPLEX)))
4501 static void tg3_init_bcm8002(struct tg3 *tp)
4503 u32 mac_status = tr32(MAC_STATUS);
4506 /* Reset when initting first time or we have a link. */
4507 if (tg3_flag(tp, INIT_COMPLETE) &&
4508 !(mac_status & MAC_STATUS_PCS_SYNCED))
4511 /* Set PLL lock range. */
4512 tg3_writephy(tp, 0x16, 0x8007);
4515 tg3_writephy(tp, MII_BMCR, BMCR_RESET);
4517 /* Wait for reset to complete. */
4518 /* XXX schedule_timeout() ... */
4519 for (i = 0; i < 500; i++)
4522 /* Config mode; select PMA/Ch 1 regs. */
4523 tg3_writephy(tp, 0x10, 0x8411);
4525 /* Enable auto-lock and comdet, select txclk for tx. */
4526 tg3_writephy(tp, 0x11, 0x0a10);
4528 tg3_writephy(tp, 0x18, 0x00a0);
4529 tg3_writephy(tp, 0x16, 0x41ff);
4531 /* Assert and deassert POR. */
4532 tg3_writephy(tp, 0x13, 0x0400);
4534 tg3_writephy(tp, 0x13, 0x0000);
4536 tg3_writephy(tp, 0x11, 0x0a50);
4538 tg3_writephy(tp, 0x11, 0x0a10);
4540 /* Wait for signal to stabilize */
4541 /* XXX schedule_timeout() ... */
4542 for (i = 0; i < 15000; i++)
4545 /* Deselect the channel register so we can read the PHYID
4548 tg3_writephy(tp, 0x10, 0x8011);
4551 static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
4554 u32 sg_dig_ctrl, sg_dig_status;
4555 u32 serdes_cfg, expected_sg_dig_ctrl;
4556 int workaround, port_a;
4557 int current_link_up;
4560 expected_sg_dig_ctrl = 0;
4563 current_link_up = 0;
4565 if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
4566 tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
4568 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
4571 /* preserve bits 0-11,13,14 for signal pre-emphasis */
4572 /* preserve bits 20-23 for voltage regulator */
4573 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
4576 sg_dig_ctrl = tr32(SG_DIG_CTRL);
4578 if (tp->link_config.autoneg != AUTONEG_ENABLE) {
4579 if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
4581 u32 val = serdes_cfg;
4587 tw32_f(MAC_SERDES_CFG, val);
4590 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
4592 if (mac_status & MAC_STATUS_PCS_SYNCED) {
4593 tg3_setup_flow_control(tp, 0, 0);
4594 current_link_up = 1;
4599 /* Want auto-negotiation. */
4600 expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
4602 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
4603 if (flowctrl & ADVERTISE_1000XPAUSE)
4604 expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
4605 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
4606 expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
4608 if (sg_dig_ctrl != expected_sg_dig_ctrl) {
4609 if ((tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT) &&
4610 tp->serdes_counter &&
4611 ((mac_status & (MAC_STATUS_PCS_SYNCED |
4612 MAC_STATUS_RCVD_CFG)) ==
4613 MAC_STATUS_PCS_SYNCED)) {
4614 tp->serdes_counter--;
4615 current_link_up = 1;
4620 tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
4621 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
4623 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
4625 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
4626 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4627 } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
4628 MAC_STATUS_SIGNAL_DET)) {
4629 sg_dig_status = tr32(SG_DIG_STATUS);
4630 mac_status = tr32(MAC_STATUS);
4632 if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
4633 (mac_status & MAC_STATUS_PCS_SYNCED)) {
4634 u32 local_adv = 0, remote_adv = 0;
4636 if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
4637 local_adv |= ADVERTISE_1000XPAUSE;
4638 if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
4639 local_adv |= ADVERTISE_1000XPSE_ASYM;
4641 if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
4642 remote_adv |= LPA_1000XPAUSE;
4643 if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
4644 remote_adv |= LPA_1000XPAUSE_ASYM;
4646 tg3_setup_flow_control(tp, local_adv, remote_adv);
4647 current_link_up = 1;
4648 tp->serdes_counter = 0;
4649 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4650 } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
4651 if (tp->serdes_counter)
4652 tp->serdes_counter--;
4655 u32 val = serdes_cfg;
4662 tw32_f(MAC_SERDES_CFG, val);
4665 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
4668 /* Link parallel detection - link is up */
4669 /* only if we have PCS_SYNC and not */
4670 /* receiving config code words */
4671 mac_status = tr32(MAC_STATUS);
4672 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
4673 !(mac_status & MAC_STATUS_RCVD_CFG)) {
4674 tg3_setup_flow_control(tp, 0, 0);
4675 current_link_up = 1;
4677 TG3_PHYFLG_PARALLEL_DETECT;
4678 tp->serdes_counter =
4679 SERDES_PARALLEL_DET_TIMEOUT;
4681 goto restart_autoneg;
4685 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
4686 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4690 return current_link_up;
4693 static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
4695 int current_link_up = 0;
4697 if (!(mac_status & MAC_STATUS_PCS_SYNCED))
4700 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
4701 u32 txflags, rxflags;
4704 if (fiber_autoneg(tp, &txflags, &rxflags)) {
4705 u32 local_adv = 0, remote_adv = 0;
4707 if (txflags & ANEG_CFG_PS1)
4708 local_adv |= ADVERTISE_1000XPAUSE;
4709 if (txflags & ANEG_CFG_PS2)
4710 local_adv |= ADVERTISE_1000XPSE_ASYM;
4712 if (rxflags & MR_LP_ADV_SYM_PAUSE)
4713 remote_adv |= LPA_1000XPAUSE;
4714 if (rxflags & MR_LP_ADV_ASYM_PAUSE)
4715 remote_adv |= LPA_1000XPAUSE_ASYM;
4717 tg3_setup_flow_control(tp, local_adv, remote_adv);
4719 current_link_up = 1;
4721 for (i = 0; i < 30; i++) {
4724 (MAC_STATUS_SYNC_CHANGED |
4725 MAC_STATUS_CFG_CHANGED));
4727 if ((tr32(MAC_STATUS) &
4728 (MAC_STATUS_SYNC_CHANGED |
4729 MAC_STATUS_CFG_CHANGED)) == 0)
4733 mac_status = tr32(MAC_STATUS);
4734 if (current_link_up == 0 &&
4735 (mac_status & MAC_STATUS_PCS_SYNCED) &&
4736 !(mac_status & MAC_STATUS_RCVD_CFG))
4737 current_link_up = 1;
4739 tg3_setup_flow_control(tp, 0, 0);
4741 /* Forcing 1000FD link up. */
4742 current_link_up = 1;
4744 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
4747 tw32_f(MAC_MODE, tp->mac_mode);
4752 return current_link_up;
4755 static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
4758 u16 orig_active_speed;
4759 u8 orig_active_duplex;
4761 int current_link_up;
4764 orig_pause_cfg = tp->link_config.active_flowctrl;
4765 orig_active_speed = tp->link_config.active_speed;
4766 orig_active_duplex = tp->link_config.active_duplex;
4768 if (!tg3_flag(tp, HW_AUTONEG) &&
4769 netif_carrier_ok(tp->dev) &&
4770 tg3_flag(tp, INIT_COMPLETE)) {
4771 mac_status = tr32(MAC_STATUS);
4772 mac_status &= (MAC_STATUS_PCS_SYNCED |
4773 MAC_STATUS_SIGNAL_DET |
4774 MAC_STATUS_CFG_CHANGED |
4775 MAC_STATUS_RCVD_CFG);
4776 if (mac_status == (MAC_STATUS_PCS_SYNCED |
4777 MAC_STATUS_SIGNAL_DET)) {
4778 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
4779 MAC_STATUS_CFG_CHANGED));
4784 tw32_f(MAC_TX_AUTO_NEG, 0);
4786 tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
4787 tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
4788 tw32_f(MAC_MODE, tp->mac_mode);
4791 if (tp->phy_id == TG3_PHY_ID_BCM8002)
4792 tg3_init_bcm8002(tp);
4794 /* Enable link change event even when serdes polling. */
4795 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4798 current_link_up = 0;
4799 mac_status = tr32(MAC_STATUS);
4801 if (tg3_flag(tp, HW_AUTONEG))
4802 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
4804 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
4806 tp->napi[0].hw_status->status =
4807 (SD_STATUS_UPDATED |
4808 (tp->napi[0].hw_status->status & ~SD_STATUS_LINK_CHG));
4810 for (i = 0; i < 100; i++) {
4811 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
4812 MAC_STATUS_CFG_CHANGED));
4814 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
4815 MAC_STATUS_CFG_CHANGED |
4816 MAC_STATUS_LNKSTATE_CHANGED)) == 0)
4820 mac_status = tr32(MAC_STATUS);
4821 if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
4822 current_link_up = 0;
4823 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
4824 tp->serdes_counter == 0) {
4825 tw32_f(MAC_MODE, (tp->mac_mode |
4826 MAC_MODE_SEND_CONFIGS));
4828 tw32_f(MAC_MODE, tp->mac_mode);
4832 if (current_link_up == 1) {
4833 tp->link_config.active_speed = SPEED_1000;
4834 tp->link_config.active_duplex = DUPLEX_FULL;
4835 tw32(MAC_LED_CTRL, (tp->led_ctrl |
4836 LED_CTRL_LNKLED_OVERRIDE |
4837 LED_CTRL_1000MBPS_ON));
4839 tp->link_config.active_speed = SPEED_INVALID;
4840 tp->link_config.active_duplex = DUPLEX_INVALID;
4841 tw32(MAC_LED_CTRL, (tp->led_ctrl |
4842 LED_CTRL_LNKLED_OVERRIDE |
4843 LED_CTRL_TRAFFIC_OVERRIDE));
4846 if (current_link_up != netif_carrier_ok(tp->dev)) {
4847 if (current_link_up)
4848 netif_carrier_on(tp->dev);
4850 netif_carrier_off(tp->dev);
4851 tg3_link_report(tp);
4853 u32 now_pause_cfg = tp->link_config.active_flowctrl;
4854 if (orig_pause_cfg != now_pause_cfg ||
4855 orig_active_speed != tp->link_config.active_speed ||
4856 orig_active_duplex != tp->link_config.active_duplex)
4857 tg3_link_report(tp);
4863 static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
4865 int current_link_up, err = 0;
4869 u32 local_adv, remote_adv;
4871 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
4872 tw32_f(MAC_MODE, tp->mac_mode);
4878 (MAC_STATUS_SYNC_CHANGED |
4879 MAC_STATUS_CFG_CHANGED |
4880 MAC_STATUS_MI_COMPLETION |
4881 MAC_STATUS_LNKSTATE_CHANGED));
4887 current_link_up = 0;
4888 current_speed = SPEED_INVALID;
4889 current_duplex = DUPLEX_INVALID;
4891 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4892 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4893 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
4894 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4895 bmsr |= BMSR_LSTATUS;
4897 bmsr &= ~BMSR_LSTATUS;
4900 err |= tg3_readphy(tp, MII_BMCR, &bmcr);
4902 if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
4903 (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) {
4904 /* do nothing, just check for link up at the end */
4905 } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
4908 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4909 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
4910 ADVERTISE_1000XPAUSE |
4911 ADVERTISE_1000XPSE_ASYM |
4914 new_adv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
4916 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
4917 new_adv |= ADVERTISE_1000XHALF;
4918 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
4919 new_adv |= ADVERTISE_1000XFULL;
4921 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
4922 tg3_writephy(tp, MII_ADVERTISE, new_adv);
4923 bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
4924 tg3_writephy(tp, MII_BMCR, bmcr);
4926 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4927 tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
4928 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4935 bmcr &= ~BMCR_SPEED1000;
4936 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
4938 if (tp->link_config.duplex == DUPLEX_FULL)
4939 new_bmcr |= BMCR_FULLDPLX;
4941 if (new_bmcr != bmcr) {
4942 /* BMCR_SPEED1000 is a reserved bit that needs
4943 * to be set on write.
4945 new_bmcr |= BMCR_SPEED1000;
4947 /* Force a linkdown */
4948 if (netif_carrier_ok(tp->dev)) {
4951 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4952 adv &= ~(ADVERTISE_1000XFULL |
4953 ADVERTISE_1000XHALF |
4955 tg3_writephy(tp, MII_ADVERTISE, adv);
4956 tg3_writephy(tp, MII_BMCR, bmcr |
4960 netif_carrier_off(tp->dev);
4962 tg3_writephy(tp, MII_BMCR, new_bmcr);
4964 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4965 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4966 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
4968 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4969 bmsr |= BMSR_LSTATUS;
4971 bmsr &= ~BMSR_LSTATUS;
4973 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4977 if (bmsr & BMSR_LSTATUS) {
4978 current_speed = SPEED_1000;
4979 current_link_up = 1;
4980 if (bmcr & BMCR_FULLDPLX)
4981 current_duplex = DUPLEX_FULL;
4983 current_duplex = DUPLEX_HALF;
4988 if (bmcr & BMCR_ANENABLE) {
4991 err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
4992 err |= tg3_readphy(tp, MII_LPA, &remote_adv);
4993 common = local_adv & remote_adv;
4994 if (common & (ADVERTISE_1000XHALF |
4995 ADVERTISE_1000XFULL)) {
4996 if (common & ADVERTISE_1000XFULL)
4997 current_duplex = DUPLEX_FULL;
4999 current_duplex = DUPLEX_HALF;
5000 } else if (!tg3_flag(tp, 5780_CLASS)) {
5001 /* Link is up via parallel detect */
5003 current_link_up = 0;
5008 if (current_link_up == 1 && current_duplex == DUPLEX_FULL)
5009 tg3_setup_flow_control(tp, local_adv, remote_adv);
5011 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
5012 if (tp->link_config.active_duplex == DUPLEX_HALF)
5013 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
5015 tw32_f(MAC_MODE, tp->mac_mode);
5018 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
5020 tp->link_config.active_speed = current_speed;
5021 tp->link_config.active_duplex = current_duplex;
5023 if (current_link_up != netif_carrier_ok(tp->dev)) {
5024 if (current_link_up)
5025 netif_carrier_on(tp->dev);
5027 netif_carrier_off(tp->dev);
5028 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
5030 tg3_link_report(tp);
5035 static void tg3_serdes_parallel_detect(struct tg3 *tp)
5037 if (tp->serdes_counter) {
5038 /* Give autoneg time to complete. */
5039 tp->serdes_counter--;
5043 if (!netif_carrier_ok(tp->dev) &&
5044 (tp->link_config.autoneg == AUTONEG_ENABLE)) {
5047 tg3_readphy(tp, MII_BMCR, &bmcr);
5048 if (bmcr & BMCR_ANENABLE) {
5051 /* Select shadow register 0x1f */
5052 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x7c00);
5053 tg3_readphy(tp, MII_TG3_MISC_SHDW, &phy1);
5055 /* Select expansion interrupt status register */
5056 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
5057 MII_TG3_DSP_EXP1_INT_STAT);
5058 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
5059 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
5061 if ((phy1 & 0x10) && !(phy2 & 0x20)) {
5062 /* We have signal detect and not receiving
5063 * config code words, link is up by parallel
5067 bmcr &= ~BMCR_ANENABLE;
5068 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
5069 tg3_writephy(tp, MII_BMCR, bmcr);
5070 tp->phy_flags |= TG3_PHYFLG_PARALLEL_DETECT;
5073 } else if (netif_carrier_ok(tp->dev) &&
5074 (tp->link_config.autoneg == AUTONEG_ENABLE) &&
5075 (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) {
5078 /* Select expansion interrupt status register */
5079 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
5080 MII_TG3_DSP_EXP1_INT_STAT);
5081 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
5085 /* Config code words received, turn on autoneg. */
5086 tg3_readphy(tp, MII_BMCR, &bmcr);
5087 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
5089 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
5095 static int tg3_setup_phy(struct tg3 *tp, int force_reset)
5100 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
5101 err = tg3_setup_fiber_phy(tp, force_reset);
5102 else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
5103 err = tg3_setup_fiber_mii_phy(tp, force_reset);
5105 err = tg3_setup_copper_phy(tp, force_reset);
5107 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
5110 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
5111 if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
5113 else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
5118 val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
5119 val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
5120 tw32(GRC_MISC_CFG, val);
5123 val = (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
5124 (6 << TX_LENGTHS_IPG_SHIFT);
5125 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720)
5126 val |= tr32(MAC_TX_LENGTHS) &
5127 (TX_LENGTHS_JMB_FRM_LEN_MSK |
5128 TX_LENGTHS_CNT_DWN_VAL_MSK);
5130 if (tp->link_config.active_speed == SPEED_1000 &&
5131 tp->link_config.active_duplex == DUPLEX_HALF)
5132 tw32(MAC_TX_LENGTHS, val |
5133 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT));
5135 tw32(MAC_TX_LENGTHS, val |
5136 (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
5138 if (!tg3_flag(tp, 5705_PLUS)) {
5139 if (netif_carrier_ok(tp->dev)) {
5140 tw32(HOSTCC_STAT_COAL_TICKS,
5141 tp->coal.stats_block_coalesce_usecs);
5143 tw32(HOSTCC_STAT_COAL_TICKS, 0);
5147 if (tg3_flag(tp, ASPM_WORKAROUND)) {
5148 val = tr32(PCIE_PWR_MGMT_THRESH);
5149 if (!netif_carrier_ok(tp->dev))
5150 val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
5153 val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
5154 tw32(PCIE_PWR_MGMT_THRESH, val);
5160 static inline int tg3_irq_sync(struct tg3 *tp)
5162 return tp->irq_sync;
5165 static inline void tg3_rd32_loop(struct tg3 *tp, u32 *dst, u32 off, u32 len)
5169 dst = (u32 *)((u8 *)dst + off);
5170 for (i = 0; i < len; i += sizeof(u32))
5171 *dst++ = tr32(off + i);
5174 static void tg3_dump_legacy_regs(struct tg3 *tp, u32 *regs)
5176 tg3_rd32_loop(tp, regs, TG3PCI_VENDOR, 0xb0);
5177 tg3_rd32_loop(tp, regs, MAILBOX_INTERRUPT_0, 0x200);
5178 tg3_rd32_loop(tp, regs, MAC_MODE, 0x4f0);
5179 tg3_rd32_loop(tp, regs, SNDDATAI_MODE, 0xe0);
5180 tg3_rd32_loop(tp, regs, SNDDATAC_MODE, 0x04);
5181 tg3_rd32_loop(tp, regs, SNDBDS_MODE, 0x80);
5182 tg3_rd32_loop(tp, regs, SNDBDI_MODE, 0x48);
5183 tg3_rd32_loop(tp, regs, SNDBDC_MODE, 0x04);
5184 tg3_rd32_loop(tp, regs, RCVLPC_MODE, 0x20);
5185 tg3_rd32_loop(tp, regs, RCVLPC_SELLST_BASE, 0x15c);
5186 tg3_rd32_loop(tp, regs, RCVDBDI_MODE, 0x0c);
5187 tg3_rd32_loop(tp, regs, RCVDBDI_JUMBO_BD, 0x3c);
5188 tg3_rd32_loop(tp, regs, RCVDBDI_BD_PROD_IDX_0, 0x44);
5189 tg3_rd32_loop(tp, regs, RCVDCC_MODE, 0x04);
5190 tg3_rd32_loop(tp, regs, RCVBDI_MODE, 0x20);
5191 tg3_rd32_loop(tp, regs, RCVCC_MODE, 0x14);
5192 tg3_rd32_loop(tp, regs, RCVLSC_MODE, 0x08);
5193 tg3_rd32_loop(tp, regs, MBFREE_MODE, 0x08);
5194 tg3_rd32_loop(tp, regs, HOSTCC_MODE, 0x100);
5196 if (tg3_flag(tp, SUPPORT_MSIX))
5197 tg3_rd32_loop(tp, regs, HOSTCC_RXCOL_TICKS_VEC1, 0x180);
5199 tg3_rd32_loop(tp, regs, MEMARB_MODE, 0x10);
5200 tg3_rd32_loop(tp, regs, BUFMGR_MODE, 0x58);
5201 tg3_rd32_loop(tp, regs, RDMAC_MODE, 0x08);
5202 tg3_rd32_loop(tp, regs, WDMAC_MODE, 0x08);
5203 tg3_rd32_loop(tp, regs, RX_CPU_MODE, 0x04);
5204 tg3_rd32_loop(tp, regs, RX_CPU_STATE, 0x04);
5205 tg3_rd32_loop(tp, regs, RX_CPU_PGMCTR, 0x04);
5206 tg3_rd32_loop(tp, regs, RX_CPU_HWBKPT, 0x04);
5208 if (!tg3_flag(tp, 5705_PLUS)) {
5209 tg3_rd32_loop(tp, regs, TX_CPU_MODE, 0x04);
5210 tg3_rd32_loop(tp, regs, TX_CPU_STATE, 0x04);
5211 tg3_rd32_loop(tp, regs, TX_CPU_PGMCTR, 0x04);
5214 tg3_rd32_loop(tp, regs, GRCMBOX_INTERRUPT_0, 0x110);
5215 tg3_rd32_loop(tp, regs, FTQ_RESET, 0x120);
5216 tg3_rd32_loop(tp, regs, MSGINT_MODE, 0x0c);
5217 tg3_rd32_loop(tp, regs, DMAC_MODE, 0x04);
5218 tg3_rd32_loop(tp, regs, GRC_MODE, 0x4c);
5220 if (tg3_flag(tp, NVRAM))
5221 tg3_rd32_loop(tp, regs, NVRAM_CMD, 0x24);
5224 static void tg3_dump_state(struct tg3 *tp)
5229 regs = kzalloc(TG3_REG_BLK_SIZE, GFP_ATOMIC);
5231 netdev_err(tp->dev, "Failed allocating register dump buffer\n");
5235 if (tg3_flag(tp, PCI_EXPRESS)) {
5236 /* Read up to but not including private PCI registers */
5237 for (i = 0; i < TG3_PCIE_TLDLPL_PORT; i += sizeof(u32))
5238 regs[i / sizeof(u32)] = tr32(i);
5240 tg3_dump_legacy_regs(tp, regs);
5242 for (i = 0; i < TG3_REG_BLK_SIZE / sizeof(u32); i += 4) {
5243 if (!regs[i + 0] && !regs[i + 1] &&
5244 !regs[i + 2] && !regs[i + 3])
5247 netdev_err(tp->dev, "0x%08x: 0x%08x, 0x%08x, 0x%08x, 0x%08x\n",
5249 regs[i + 0], regs[i + 1], regs[i + 2], regs[i + 3]);
5254 for (i = 0; i < tp->irq_cnt; i++) {
5255 struct tg3_napi *tnapi = &tp->napi[i];
5257 /* SW status block */
5259 "%d: Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
5261 tnapi->hw_status->status,
5262 tnapi->hw_status->status_tag,
5263 tnapi->hw_status->rx_jumbo_consumer,
5264 tnapi->hw_status->rx_consumer,
5265 tnapi->hw_status->rx_mini_consumer,
5266 tnapi->hw_status->idx[0].rx_producer,
5267 tnapi->hw_status->idx[0].tx_consumer);
5270 "%d: NAPI info [%08x:%08x:(%04x:%04x:%04x):%04x:(%04x:%04x:%04x:%04x)]\n",
5272 tnapi->last_tag, tnapi->last_irq_tag,
5273 tnapi->tx_prod, tnapi->tx_cons, tnapi->tx_pending,
5275 tnapi->prodring.rx_std_prod_idx,
5276 tnapi->prodring.rx_std_cons_idx,
5277 tnapi->prodring.rx_jmb_prod_idx,
5278 tnapi->prodring.rx_jmb_cons_idx);
5282 /* This is called whenever we suspect that the system chipset is re-
5283 * ordering the sequence of MMIO to the tx send mailbox. The symptom
5284 * is bogus tx completions. We try to recover by setting the
5285 * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
5288 static void tg3_tx_recover(struct tg3 *tp)
5290 BUG_ON(tg3_flag(tp, MBOX_WRITE_REORDER) ||
5291 tp->write32_tx_mbox == tg3_write_indirect_mbox);
5293 netdev_warn(tp->dev,
5294 "The system may be re-ordering memory-mapped I/O "
5295 "cycles to the network device, attempting to recover. "
5296 "Please report the problem to the driver maintainer "
5297 "and include system chipset information.\n");
5299 spin_lock(&tp->lock);
5300 tg3_flag_set(tp, TX_RECOVERY_PENDING);
5301 spin_unlock(&tp->lock);
5304 static inline u32 tg3_tx_avail(struct tg3_napi *tnapi)
5306 /* Tell compiler to fetch tx indices from memory. */
5308 return tnapi->tx_pending -
5309 ((tnapi->tx_prod - tnapi->tx_cons) & (TG3_TX_RING_SIZE - 1));
5312 /* Tigon3 never reports partial packet sends. So we do not
5313 * need special logic to handle SKBs that have not had all
5314 * of their frags sent yet, like SunGEM does.
5316 static void tg3_tx(struct tg3_napi *tnapi)
5318 struct tg3 *tp = tnapi->tp;
5319 u32 hw_idx = tnapi->hw_status->idx[0].tx_consumer;
5320 u32 sw_idx = tnapi->tx_cons;
5321 struct netdev_queue *txq;
5322 int index = tnapi - tp->napi;
5324 if (tg3_flag(tp, ENABLE_TSS))
5327 txq = netdev_get_tx_queue(tp->dev, index);
5329 while (sw_idx != hw_idx) {
5330 struct tg3_tx_ring_info *ri = &tnapi->tx_buffers[sw_idx];
5331 struct sk_buff *skb = ri->skb;
5334 if (unlikely(skb == NULL)) {
5339 pci_unmap_single(tp->pdev,
5340 dma_unmap_addr(ri, mapping),
5346 while (ri->fragmented) {
5347 ri->fragmented = false;
5348 sw_idx = NEXT_TX(sw_idx);
5349 ri = &tnapi->tx_buffers[sw_idx];
5352 sw_idx = NEXT_TX(sw_idx);
5354 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
5355 ri = &tnapi->tx_buffers[sw_idx];
5356 if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
5359 pci_unmap_page(tp->pdev,
5360 dma_unmap_addr(ri, mapping),
5361 skb_frag_size(&skb_shinfo(skb)->frags[i]),
5364 while (ri->fragmented) {
5365 ri->fragmented = false;
5366 sw_idx = NEXT_TX(sw_idx);
5367 ri = &tnapi->tx_buffers[sw_idx];
5370 sw_idx = NEXT_TX(sw_idx);
5375 if (unlikely(tx_bug)) {
5381 tnapi->tx_cons = sw_idx;
5383 /* Need to make the tx_cons update visible to tg3_start_xmit()
5384 * before checking for netif_queue_stopped(). Without the
5385 * memory barrier, there is a small possibility that tg3_start_xmit()
5386 * will miss it and cause the queue to be stopped forever.
5390 if (unlikely(netif_tx_queue_stopped(txq) &&
5391 (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))) {
5392 __netif_tx_lock(txq, smp_processor_id());
5393 if (netif_tx_queue_stopped(txq) &&
5394 (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))
5395 netif_tx_wake_queue(txq);
5396 __netif_tx_unlock(txq);
5400 static void tg3_rx_skb_free(struct tg3 *tp, struct ring_info *ri, u32 map_sz)
5405 pci_unmap_single(tp->pdev, dma_unmap_addr(ri, mapping),
5406 map_sz, PCI_DMA_FROMDEVICE);
5407 dev_kfree_skb_any(ri->skb);
5411 /* Returns size of skb allocated or < 0 on error.
5413 * We only need to fill in the address because the other members
5414 * of the RX descriptor are invariant, see tg3_init_rings.
5416 * Note the purposeful assymetry of cpu vs. chip accesses. For
5417 * posting buffers we only dirty the first cache line of the RX
5418 * descriptor (containing the address). Whereas for the RX status
5419 * buffers the cpu only reads the last cacheline of the RX descriptor
5420 * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
5422 static int tg3_alloc_rx_skb(struct tg3 *tp, struct tg3_rx_prodring_set *tpr,
5423 u32 opaque_key, u32 dest_idx_unmasked)
5425 struct tg3_rx_buffer_desc *desc;
5426 struct ring_info *map;
5427 struct sk_buff *skb;
5429 int skb_size, dest_idx;
5431 switch (opaque_key) {
5432 case RXD_OPAQUE_RING_STD:
5433 dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask;
5434 desc = &tpr->rx_std[dest_idx];
5435 map = &tpr->rx_std_buffers[dest_idx];
5436 skb_size = tp->rx_pkt_map_sz;
5439 case RXD_OPAQUE_RING_JUMBO:
5440 dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask;
5441 desc = &tpr->rx_jmb[dest_idx].std;
5442 map = &tpr->rx_jmb_buffers[dest_idx];
5443 skb_size = TG3_RX_JMB_MAP_SZ;
5450 /* Do not overwrite any of the map or rp information
5451 * until we are sure we can commit to a new buffer.
5453 * Callers depend upon this behavior and assume that
5454 * we leave everything unchanged if we fail.
5456 skb = netdev_alloc_skb(tp->dev, skb_size + TG3_RX_OFFSET(tp));
5460 skb_reserve(skb, TG3_RX_OFFSET(tp));
5462 mapping = pci_map_single(tp->pdev, skb->data, skb_size,
5463 PCI_DMA_FROMDEVICE);
5464 if (pci_dma_mapping_error(tp->pdev, mapping)) {
5470 dma_unmap_addr_set(map, mapping, mapping);
5472 desc->addr_hi = ((u64)mapping >> 32);
5473 desc->addr_lo = ((u64)mapping & 0xffffffff);
5478 /* We only need to move over in the address because the other
5479 * members of the RX descriptor are invariant. See notes above
5480 * tg3_alloc_rx_skb for full details.
5482 static void tg3_recycle_rx(struct tg3_napi *tnapi,
5483 struct tg3_rx_prodring_set *dpr,
5484 u32 opaque_key, int src_idx,
5485 u32 dest_idx_unmasked)
5487 struct tg3 *tp = tnapi->tp;
5488 struct tg3_rx_buffer_desc *src_desc, *dest_desc;
5489 struct ring_info *src_map, *dest_map;
5490 struct tg3_rx_prodring_set *spr = &tp->napi[0].prodring;
5493 switch (opaque_key) {
5494 case RXD_OPAQUE_RING_STD:
5495 dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask;
5496 dest_desc = &dpr->rx_std[dest_idx];
5497 dest_map = &dpr->rx_std_buffers[dest_idx];
5498 src_desc = &spr->rx_std[src_idx];
5499 src_map = &spr->rx_std_buffers[src_idx];
5502 case RXD_OPAQUE_RING_JUMBO:
5503 dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask;
5504 dest_desc = &dpr->rx_jmb[dest_idx].std;
5505 dest_map = &dpr->rx_jmb_buffers[dest_idx];
5506 src_desc = &spr->rx_jmb[src_idx].std;
5507 src_map = &spr->rx_jmb_buffers[src_idx];
5514 dest_map->skb = src_map->skb;
5515 dma_unmap_addr_set(dest_map, mapping,
5516 dma_unmap_addr(src_map, mapping));
5517 dest_desc->addr_hi = src_desc->addr_hi;
5518 dest_desc->addr_lo = src_desc->addr_lo;
5520 /* Ensure that the update to the skb happens after the physical
5521 * addresses have been transferred to the new BD location.
5525 src_map->skb = NULL;
5528 /* The RX ring scheme is composed of multiple rings which post fresh
5529 * buffers to the chip, and one special ring the chip uses to report
5530 * status back to the host.
5532 * The special ring reports the status of received packets to the
5533 * host. The chip does not write into the original descriptor the
5534 * RX buffer was obtained from. The chip simply takes the original
5535 * descriptor as provided by the host, updates the status and length
5536 * field, then writes this into the next status ring entry.
5538 * Each ring the host uses to post buffers to the chip is described
5539 * by a TG3_BDINFO entry in the chips SRAM area. When a packet arrives,
5540 * it is first placed into the on-chip ram. When the packet's length
5541 * is known, it walks down the TG3_BDINFO entries to select the ring.
5542 * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
5543 * which is within the range of the new packet's length is chosen.
5545 * The "separate ring for rx status" scheme may sound queer, but it makes
5546 * sense from a cache coherency perspective. If only the host writes
5547 * to the buffer post rings, and only the chip writes to the rx status
5548 * rings, then cache lines never move beyond shared-modified state.
5549 * If both the host and chip were to write into the same ring, cache line
5550 * eviction could occur since both entities want it in an exclusive state.
5552 static int tg3_rx(struct tg3_napi *tnapi, int budget)
5554 struct tg3 *tp = tnapi->tp;
5555 u32 work_mask, rx_std_posted = 0;
5556 u32 std_prod_idx, jmb_prod_idx;
5557 u32 sw_idx = tnapi->rx_rcb_ptr;
5560 struct tg3_rx_prodring_set *tpr = &tnapi->prodring;
5562 hw_idx = *(tnapi->rx_rcb_prod_idx);
5564 * We need to order the read of hw_idx and the read of
5565 * the opaque cookie.
5570 std_prod_idx = tpr->rx_std_prod_idx;
5571 jmb_prod_idx = tpr->rx_jmb_prod_idx;
5572 while (sw_idx != hw_idx && budget > 0) {
5573 struct ring_info *ri;
5574 struct tg3_rx_buffer_desc *desc = &tnapi->rx_rcb[sw_idx];
5576 struct sk_buff *skb;
5577 dma_addr_t dma_addr;
5578 u32 opaque_key, desc_idx, *post_ptr;
5580 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
5581 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
5582 if (opaque_key == RXD_OPAQUE_RING_STD) {
5583 ri = &tp->napi[0].prodring.rx_std_buffers[desc_idx];
5584 dma_addr = dma_unmap_addr(ri, mapping);
5586 post_ptr = &std_prod_idx;
5588 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
5589 ri = &tp->napi[0].prodring.rx_jmb_buffers[desc_idx];
5590 dma_addr = dma_unmap_addr(ri, mapping);
5592 post_ptr = &jmb_prod_idx;
5594 goto next_pkt_nopost;
5596 work_mask |= opaque_key;
5598 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
5599 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
5601 tg3_recycle_rx(tnapi, tpr, opaque_key,
5602 desc_idx, *post_ptr);
5604 /* Other statistics kept track of by card. */
5609 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) -
5612 if (len > TG3_RX_COPY_THRESH(tp)) {
5615 skb_size = tg3_alloc_rx_skb(tp, tpr, opaque_key,
5620 pci_unmap_single(tp->pdev, dma_addr, skb_size,
5621 PCI_DMA_FROMDEVICE);
5623 /* Ensure that the update to the skb happens
5624 * after the usage of the old DMA mapping.
5632 struct sk_buff *copy_skb;
5634 tg3_recycle_rx(tnapi, tpr, opaque_key,
5635 desc_idx, *post_ptr);
5637 copy_skb = netdev_alloc_skb(tp->dev, len +
5639 if (copy_skb == NULL)
5640 goto drop_it_no_recycle;
5642 skb_reserve(copy_skb, TG3_RAW_IP_ALIGN);
5643 skb_put(copy_skb, len);
5644 pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
5645 skb_copy_from_linear_data(skb, copy_skb->data, len);
5646 pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
5648 /* We'll reuse the original ring buffer. */
5652 if ((tp->dev->features & NETIF_F_RXCSUM) &&
5653 (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
5654 (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
5655 >> RXD_TCPCSUM_SHIFT) == 0xffff))
5656 skb->ip_summed = CHECKSUM_UNNECESSARY;
5658 skb_checksum_none_assert(skb);
5660 skb->protocol = eth_type_trans(skb, tp->dev);
5662 if (len > (tp->dev->mtu + ETH_HLEN) &&
5663 skb->protocol != htons(ETH_P_8021Q)) {
5665 goto drop_it_no_recycle;
5668 if (desc->type_flags & RXD_FLAG_VLAN &&
5669 !(tp->rx_mode & RX_MODE_KEEP_VLAN_TAG))
5670 __vlan_hwaccel_put_tag(skb,
5671 desc->err_vlan & RXD_VLAN_MASK);
5673 napi_gro_receive(&tnapi->napi, skb);
5681 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
5682 tpr->rx_std_prod_idx = std_prod_idx &
5683 tp->rx_std_ring_mask;
5684 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
5685 tpr->rx_std_prod_idx);
5686 work_mask &= ~RXD_OPAQUE_RING_STD;
5691 sw_idx &= tp->rx_ret_ring_mask;
5693 /* Refresh hw_idx to see if there is new work */
5694 if (sw_idx == hw_idx) {
5695 hw_idx = *(tnapi->rx_rcb_prod_idx);
5700 /* ACK the status ring. */
5701 tnapi->rx_rcb_ptr = sw_idx;
5702 tw32_rx_mbox(tnapi->consmbox, sw_idx);
5704 /* Refill RX ring(s). */
5705 if (!tg3_flag(tp, ENABLE_RSS)) {
5706 if (work_mask & RXD_OPAQUE_RING_STD) {
5707 tpr->rx_std_prod_idx = std_prod_idx &
5708 tp->rx_std_ring_mask;
5709 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
5710 tpr->rx_std_prod_idx);
5712 if (work_mask & RXD_OPAQUE_RING_JUMBO) {
5713 tpr->rx_jmb_prod_idx = jmb_prod_idx &
5714 tp->rx_jmb_ring_mask;
5715 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
5716 tpr->rx_jmb_prod_idx);
5719 } else if (work_mask) {
5720 /* rx_std_buffers[] and rx_jmb_buffers[] entries must be
5721 * updated before the producer indices can be updated.
5725 tpr->rx_std_prod_idx = std_prod_idx & tp->rx_std_ring_mask;
5726 tpr->rx_jmb_prod_idx = jmb_prod_idx & tp->rx_jmb_ring_mask;
5728 if (tnapi != &tp->napi[1])
5729 napi_schedule(&tp->napi[1].napi);
5735 static void tg3_poll_link(struct tg3 *tp)
5737 /* handle link change and other phy events */
5738 if (!(tg3_flag(tp, USE_LINKCHG_REG) || tg3_flag(tp, POLL_SERDES))) {
5739 struct tg3_hw_status *sblk = tp->napi[0].hw_status;
5741 if (sblk->status & SD_STATUS_LINK_CHG) {
5742 sblk->status = SD_STATUS_UPDATED |
5743 (sblk->status & ~SD_STATUS_LINK_CHG);
5744 spin_lock(&tp->lock);
5745 if (tg3_flag(tp, USE_PHYLIB)) {
5747 (MAC_STATUS_SYNC_CHANGED |
5748 MAC_STATUS_CFG_CHANGED |
5749 MAC_STATUS_MI_COMPLETION |
5750 MAC_STATUS_LNKSTATE_CHANGED));
5753 tg3_setup_phy(tp, 0);
5754 spin_unlock(&tp->lock);
5759 static int tg3_rx_prodring_xfer(struct tg3 *tp,
5760 struct tg3_rx_prodring_set *dpr,
5761 struct tg3_rx_prodring_set *spr)
5763 u32 si, di, cpycnt, src_prod_idx;
5767 src_prod_idx = spr->rx_std_prod_idx;
5769 /* Make sure updates to the rx_std_buffers[] entries and the
5770 * standard producer index are seen in the correct order.
5774 if (spr->rx_std_cons_idx == src_prod_idx)
5777 if (spr->rx_std_cons_idx < src_prod_idx)
5778 cpycnt = src_prod_idx - spr->rx_std_cons_idx;
5780 cpycnt = tp->rx_std_ring_mask + 1 -
5781 spr->rx_std_cons_idx;
5783 cpycnt = min(cpycnt,
5784 tp->rx_std_ring_mask + 1 - dpr->rx_std_prod_idx);
5786 si = spr->rx_std_cons_idx;
5787 di = dpr->rx_std_prod_idx;
5789 for (i = di; i < di + cpycnt; i++) {
5790 if (dpr->rx_std_buffers[i].skb) {
5800 /* Ensure that updates to the rx_std_buffers ring and the
5801 * shadowed hardware producer ring from tg3_recycle_skb() are
5802 * ordered correctly WRT the skb check above.
5806 memcpy(&dpr->rx_std_buffers[di],
5807 &spr->rx_std_buffers[si],
5808 cpycnt * sizeof(struct ring_info));
5810 for (i = 0; i < cpycnt; i++, di++, si++) {
5811 struct tg3_rx_buffer_desc *sbd, *dbd;
5812 sbd = &spr->rx_std[si];
5813 dbd = &dpr->rx_std[di];
5814 dbd->addr_hi = sbd->addr_hi;
5815 dbd->addr_lo = sbd->addr_lo;
5818 spr->rx_std_cons_idx = (spr->rx_std_cons_idx + cpycnt) &
5819 tp->rx_std_ring_mask;
5820 dpr->rx_std_prod_idx = (dpr->rx_std_prod_idx + cpycnt) &
5821 tp->rx_std_ring_mask;
5825 src_prod_idx = spr->rx_jmb_prod_idx;
5827 /* Make sure updates to the rx_jmb_buffers[] entries and
5828 * the jumbo producer index are seen in the correct order.
5832 if (spr->rx_jmb_cons_idx == src_prod_idx)
5835 if (spr->rx_jmb_cons_idx < src_prod_idx)
5836 cpycnt = src_prod_idx - spr->rx_jmb_cons_idx;
5838 cpycnt = tp->rx_jmb_ring_mask + 1 -
5839 spr->rx_jmb_cons_idx;
5841 cpycnt = min(cpycnt,
5842 tp->rx_jmb_ring_mask + 1 - dpr->rx_jmb_prod_idx);
5844 si = spr->rx_jmb_cons_idx;
5845 di = dpr->rx_jmb_prod_idx;
5847 for (i = di; i < di + cpycnt; i++) {
5848 if (dpr->rx_jmb_buffers[i].skb) {
5858 /* Ensure that updates to the rx_jmb_buffers ring and the
5859 * shadowed hardware producer ring from tg3_recycle_skb() are
5860 * ordered correctly WRT the skb check above.
5864 memcpy(&dpr->rx_jmb_buffers[di],
5865 &spr->rx_jmb_buffers[si],
5866 cpycnt * sizeof(struct ring_info));
5868 for (i = 0; i < cpycnt; i++, di++, si++) {
5869 struct tg3_rx_buffer_desc *sbd, *dbd;
5870 sbd = &spr->rx_jmb[si].std;
5871 dbd = &dpr->rx_jmb[di].std;
5872 dbd->addr_hi = sbd->addr_hi;
5873 dbd->addr_lo = sbd->addr_lo;
5876 spr->rx_jmb_cons_idx = (spr->rx_jmb_cons_idx + cpycnt) &
5877 tp->rx_jmb_ring_mask;
5878 dpr->rx_jmb_prod_idx = (dpr->rx_jmb_prod_idx + cpycnt) &
5879 tp->rx_jmb_ring_mask;
5885 static int tg3_poll_work(struct tg3_napi *tnapi, int work_done, int budget)
5887 struct tg3 *tp = tnapi->tp;
5889 /* run TX completion thread */
5890 if (tnapi->hw_status->idx[0].tx_consumer != tnapi->tx_cons) {
5892 if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING)))
5896 /* run RX thread, within the bounds set by NAPI.
5897 * All RX "locking" is done by ensuring outside
5898 * code synchronizes with tg3->napi.poll()
5900 if (*(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
5901 work_done += tg3_rx(tnapi, budget - work_done);
5903 if (tg3_flag(tp, ENABLE_RSS) && tnapi == &tp->napi[1]) {
5904 struct tg3_rx_prodring_set *dpr = &tp->napi[0].prodring;
5906 u32 std_prod_idx = dpr->rx_std_prod_idx;
5907 u32 jmb_prod_idx = dpr->rx_jmb_prod_idx;
5909 for (i = 1; i < tp->irq_cnt; i++)
5910 err |= tg3_rx_prodring_xfer(tp, dpr,
5911 &tp->napi[i].prodring);
5915 if (std_prod_idx != dpr->rx_std_prod_idx)
5916 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
5917 dpr->rx_std_prod_idx);
5919 if (jmb_prod_idx != dpr->rx_jmb_prod_idx)
5920 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
5921 dpr->rx_jmb_prod_idx);
5926 tw32_f(HOSTCC_MODE, tp->coal_now);
5932 static inline void tg3_reset_task_schedule(struct tg3 *tp)
5934 if (!test_and_set_bit(TG3_FLAG_RESET_TASK_PENDING, tp->tg3_flags))
5935 schedule_work(&tp->reset_task);
5938 static inline void tg3_reset_task_cancel(struct tg3 *tp)
5940 cancel_work_sync(&tp->reset_task);
5941 tg3_flag_clear(tp, RESET_TASK_PENDING);
5944 static int tg3_poll_msix(struct napi_struct *napi, int budget)
5946 struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
5947 struct tg3 *tp = tnapi->tp;
5949 struct tg3_hw_status *sblk = tnapi->hw_status;
5952 work_done = tg3_poll_work(tnapi, work_done, budget);
5954 if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING)))
5957 if (unlikely(work_done >= budget))
5960 /* tp->last_tag is used in tg3_int_reenable() below
5961 * to tell the hw how much work has been processed,
5962 * so we must read it before checking for more work.
5964 tnapi->last_tag = sblk->status_tag;
5965 tnapi->last_irq_tag = tnapi->last_tag;
5968 /* check for RX/TX work to do */
5969 if (likely(sblk->idx[0].tx_consumer == tnapi->tx_cons &&
5970 *(tnapi->rx_rcb_prod_idx) == tnapi->rx_rcb_ptr)) {
5971 napi_complete(napi);
5972 /* Reenable interrupts. */
5973 tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
5982 /* work_done is guaranteed to be less than budget. */
5983 napi_complete(napi);
5984 tg3_reset_task_schedule(tp);
5988 static void tg3_process_error(struct tg3 *tp)
5991 bool real_error = false;
5993 if (tg3_flag(tp, ERROR_PROCESSED))
5996 /* Check Flow Attention register */
5997 val = tr32(HOSTCC_FLOW_ATTN);
5998 if (val & ~HOSTCC_FLOW_ATTN_MBUF_LWM) {
5999 netdev_err(tp->dev, "FLOW Attention error. Resetting chip.\n");
6003 if (tr32(MSGINT_STATUS) & ~MSGINT_STATUS_MSI_REQ) {
6004 netdev_err(tp->dev, "MSI Status error. Resetting chip.\n");
6008 if (tr32(RDMAC_STATUS) || tr32(WDMAC_STATUS)) {
6009 netdev_err(tp->dev, "DMA Status error. Resetting chip.\n");
6018 tg3_flag_set(tp, ERROR_PROCESSED);
6019 tg3_reset_task_schedule(tp);
6022 static int tg3_poll(struct napi_struct *napi, int budget)
6024 struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
6025 struct tg3 *tp = tnapi->tp;
6027 struct tg3_hw_status *sblk = tnapi->hw_status;
6030 if (sblk->status & SD_STATUS_ERROR)
6031 tg3_process_error(tp);
6035 work_done = tg3_poll_work(tnapi, work_done, budget);
6037 if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING)))
6040 if (unlikely(work_done >= budget))
6043 if (tg3_flag(tp, TAGGED_STATUS)) {
6044 /* tp->last_tag is used in tg3_int_reenable() below
6045 * to tell the hw how much work has been processed,
6046 * so we must read it before checking for more work.
6048 tnapi->last_tag = sblk->status_tag;
6049 tnapi->last_irq_tag = tnapi->last_tag;
6052 sblk->status &= ~SD_STATUS_UPDATED;
6054 if (likely(!tg3_has_work(tnapi))) {
6055 napi_complete(napi);
6056 tg3_int_reenable(tnapi);
6064 /* work_done is guaranteed to be less than budget. */
6065 napi_complete(napi);
6066 tg3_reset_task_schedule(tp);
6070 static void tg3_napi_disable(struct tg3 *tp)
6074 for (i = tp->irq_cnt - 1; i >= 0; i--)
6075 napi_disable(&tp->napi[i].napi);
6078 static void tg3_napi_enable(struct tg3 *tp)
6082 for (i = 0; i < tp->irq_cnt; i++)
6083 napi_enable(&tp->napi[i].napi);
6086 static void tg3_napi_init(struct tg3 *tp)
6090 netif_napi_add(tp->dev, &tp->napi[0].napi, tg3_poll, 64);
6091 for (i = 1; i < tp->irq_cnt; i++)
6092 netif_napi_add(tp->dev, &tp->napi[i].napi, tg3_poll_msix, 64);
6095 static void tg3_napi_fini(struct tg3 *tp)
6099 for (i = 0; i < tp->irq_cnt; i++)
6100 netif_napi_del(&tp->napi[i].napi);
6103 static inline void tg3_netif_stop(struct tg3 *tp)
6105 tp->dev->trans_start = jiffies; /* prevent tx timeout */
6106 tg3_napi_disable(tp);
6107 netif_tx_disable(tp->dev);
6110 static inline void tg3_netif_start(struct tg3 *tp)
6112 /* NOTE: unconditional netif_tx_wake_all_queues is only
6113 * appropriate so long as all callers are assured to
6114 * have free tx slots (such as after tg3_init_hw)
6116 netif_tx_wake_all_queues(tp->dev);
6118 tg3_napi_enable(tp);
6119 tp->napi[0].hw_status->status |= SD_STATUS_UPDATED;
6120 tg3_enable_ints(tp);
6123 static void tg3_irq_quiesce(struct tg3 *tp)
6127 BUG_ON(tp->irq_sync);
6132 for (i = 0; i < tp->irq_cnt; i++)
6133 synchronize_irq(tp->napi[i].irq_vec);
6136 /* Fully shutdown all tg3 driver activity elsewhere in the system.
6137 * If irq_sync is non-zero, then the IRQ handler must be synchronized
6138 * with as well. Most of the time, this is not necessary except when
6139 * shutting down the device.
6141 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
6143 spin_lock_bh(&tp->lock);
6145 tg3_irq_quiesce(tp);
6148 static inline void tg3_full_unlock(struct tg3 *tp)
6150 spin_unlock_bh(&tp->lock);
6153 /* One-shot MSI handler - Chip automatically disables interrupt
6154 * after sending MSI so driver doesn't have to do it.
6156 static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
6158 struct tg3_napi *tnapi = dev_id;
6159 struct tg3 *tp = tnapi->tp;
6161 prefetch(tnapi->hw_status);
6163 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
6165 if (likely(!tg3_irq_sync(tp)))
6166 napi_schedule(&tnapi->napi);
6171 /* MSI ISR - No need to check for interrupt sharing and no need to
6172 * flush status block and interrupt mailbox. PCI ordering rules
6173 * guarantee that MSI will arrive after the status block.
6175 static irqreturn_t tg3_msi(int irq, void *dev_id)
6177 struct tg3_napi *tnapi = dev_id;
6178 struct tg3 *tp = tnapi->tp;
6180 prefetch(tnapi->hw_status);
6182 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
6184 * Writing any value to intr-mbox-0 clears PCI INTA# and
6185 * chip-internal interrupt pending events.
6186 * Writing non-zero to intr-mbox-0 additional tells the
6187 * NIC to stop sending us irqs, engaging "in-intr-handler"
6190 tw32_mailbox(tnapi->int_mbox, 0x00000001);
6191 if (likely(!tg3_irq_sync(tp)))
6192 napi_schedule(&tnapi->napi);
6194 return IRQ_RETVAL(1);
6197 static irqreturn_t tg3_interrupt(int irq, void *dev_id)
6199 struct tg3_napi *tnapi = dev_id;
6200 struct tg3 *tp = tnapi->tp;
6201 struct tg3_hw_status *sblk = tnapi->hw_status;
6202 unsigned int handled = 1;
6204 /* In INTx mode, it is possible for the interrupt to arrive at
6205 * the CPU before the status block posted prior to the interrupt.
6206 * Reading the PCI State register will confirm whether the
6207 * interrupt is ours and will flush the status block.
6209 if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
6210 if (tg3_flag(tp, CHIP_RESETTING) ||
6211 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
6218 * Writing any value to intr-mbox-0 clears PCI INTA# and
6219 * chip-internal interrupt pending events.
6220 * Writing non-zero to intr-mbox-0 additional tells the
6221 * NIC to stop sending us irqs, engaging "in-intr-handler"
6224 * Flush the mailbox to de-assert the IRQ immediately to prevent
6225 * spurious interrupts. The flush impacts performance but
6226 * excessive spurious interrupts can be worse in some cases.
6228 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
6229 if (tg3_irq_sync(tp))
6231 sblk->status &= ~SD_STATUS_UPDATED;
6232 if (likely(tg3_has_work(tnapi))) {
6233 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
6234 napi_schedule(&tnapi->napi);
6236 /* No work, shared interrupt perhaps? re-enable
6237 * interrupts, and flush that PCI write
6239 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
6243 return IRQ_RETVAL(handled);
6246 static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
6248 struct tg3_napi *tnapi = dev_id;
6249 struct tg3 *tp = tnapi->tp;
6250 struct tg3_hw_status *sblk = tnapi->hw_status;
6251 unsigned int handled = 1;
6253 /* In INTx mode, it is possible for the interrupt to arrive at
6254 * the CPU before the status block posted prior to the interrupt.
6255 * Reading the PCI State register will confirm whether the
6256 * interrupt is ours and will flush the status block.
6258 if (unlikely(sblk->status_tag == tnapi->last_irq_tag)) {
6259 if (tg3_flag(tp, CHIP_RESETTING) ||
6260 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
6267 * writing any value to intr-mbox-0 clears PCI INTA# and
6268 * chip-internal interrupt pending events.
6269 * writing non-zero to intr-mbox-0 additional tells the
6270 * NIC to stop sending us irqs, engaging "in-intr-handler"
6273 * Flush the mailbox to de-assert the IRQ immediately to prevent
6274 * spurious interrupts. The flush impacts performance but
6275 * excessive spurious interrupts can be worse in some cases.
6277 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
6280 * In a shared interrupt configuration, sometimes other devices'
6281 * interrupts will scream. We record the current status tag here
6282 * so that the above check can report that the screaming interrupts
6283 * are unhandled. Eventually they will be silenced.
6285 tnapi->last_irq_tag = sblk->status_tag;
6287 if (tg3_irq_sync(tp))
6290 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
6292 napi_schedule(&tnapi->napi);
6295 return IRQ_RETVAL(handled);
6298 /* ISR for interrupt test */
6299 static irqreturn_t tg3_test_isr(int irq, void *dev_id)
6301 struct tg3_napi *tnapi = dev_id;
6302 struct tg3 *tp = tnapi->tp;
6303 struct tg3_hw_status *sblk = tnapi->hw_status;
6305 if ((sblk->status & SD_STATUS_UPDATED) ||
6306 !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
6307 tg3_disable_ints(tp);
6308 return IRQ_RETVAL(1);
6310 return IRQ_RETVAL(0);
6313 static int tg3_init_hw(struct tg3 *, int);
6314 static int tg3_halt(struct tg3 *, int, int);
6316 /* Restart hardware after configuration changes, self-test, etc.
6317 * Invoked with tp->lock held.
6319 static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
6320 __releases(tp->lock)
6321 __acquires(tp->lock)
6325 err = tg3_init_hw(tp, reset_phy);
6328 "Failed to re-initialize device, aborting\n");
6329 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
6330 tg3_full_unlock(tp);
6331 del_timer_sync(&tp->timer);
6333 tg3_napi_enable(tp);
6335 tg3_full_lock(tp, 0);
6340 #ifdef CONFIG_NET_POLL_CONTROLLER
6341 static void tg3_poll_controller(struct net_device *dev)
6344 struct tg3 *tp = netdev_priv(dev);
6346 for (i = 0; i < tp->irq_cnt; i++)
6347 tg3_interrupt(tp->napi[i].irq_vec, &tp->napi[i]);
6351 static void tg3_reset_task(struct work_struct *work)
6353 struct tg3 *tp = container_of(work, struct tg3, reset_task);
6356 tg3_full_lock(tp, 0);
6358 if (!netif_running(tp->dev)) {
6359 tg3_flag_clear(tp, RESET_TASK_PENDING);
6360 tg3_full_unlock(tp);
6364 tg3_full_unlock(tp);
6370 tg3_full_lock(tp, 1);
6372 if (tg3_flag(tp, TX_RECOVERY_PENDING)) {
6373 tp->write32_tx_mbox = tg3_write32_tx_mbox;
6374 tp->write32_rx_mbox = tg3_write_flush_reg32;
6375 tg3_flag_set(tp, MBOX_WRITE_REORDER);
6376 tg3_flag_clear(tp, TX_RECOVERY_PENDING);
6379 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
6380 err = tg3_init_hw(tp, 1);
6384 tg3_netif_start(tp);
6387 tg3_full_unlock(tp);
6392 tg3_flag_clear(tp, RESET_TASK_PENDING);
6395 static void tg3_tx_timeout(struct net_device *dev)
6397 struct tg3 *tp = netdev_priv(dev);
6399 if (netif_msg_tx_err(tp)) {
6400 netdev_err(dev, "transmit timed out, resetting\n");
6404 tg3_reset_task_schedule(tp);
6407 /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
6408 static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
6410 u32 base = (u32) mapping & 0xffffffff;
6412 return (base > 0xffffdcc0) && (base + len + 8 < base);
6415 /* Test for DMA addresses > 40-bit */
6416 static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
6419 #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
6420 if (tg3_flag(tp, 40BIT_DMA_BUG))
6421 return ((u64) mapping + len) > DMA_BIT_MASK(40);
6428 static inline void tg3_tx_set_bd(struct tg3_tx_buffer_desc *txbd,
6429 dma_addr_t mapping, u32 len, u32 flags,
6432 txbd->addr_hi = ((u64) mapping >> 32);
6433 txbd->addr_lo = ((u64) mapping & 0xffffffff);
6434 txbd->len_flags = (len << TXD_LEN_SHIFT) | (flags & 0x0000ffff);
6435 txbd->vlan_tag = (mss << TXD_MSS_SHIFT) | (vlan << TXD_VLAN_TAG_SHIFT);
6438 static bool tg3_tx_frag_set(struct tg3_napi *tnapi, u32 *entry, u32 *budget,
6439 dma_addr_t map, u32 len, u32 flags,
6442 struct tg3 *tp = tnapi->tp;
6445 if (tg3_flag(tp, SHORT_DMA_BUG) && len <= 8)
6448 if (tg3_4g_overflow_test(map, len))
6451 if (tg3_40bit_overflow_test(tp, map, len))
6454 if (tg3_flag(tp, 4K_FIFO_LIMIT)) {
6455 u32 prvidx = *entry;
6456 u32 tmp_flag = flags & ~TXD_FLAG_END;
6457 while (len > TG3_TX_BD_DMA_MAX && *budget) {
6458 u32 frag_len = TG3_TX_BD_DMA_MAX;
6459 len -= TG3_TX_BD_DMA_MAX;
6461 /* Avoid the 8byte DMA problem */
6463 len += TG3_TX_BD_DMA_MAX / 2;
6464 frag_len = TG3_TX_BD_DMA_MAX / 2;
6467 tnapi->tx_buffers[*entry].fragmented = true;
6469 tg3_tx_set_bd(&tnapi->tx_ring[*entry], map,
6470 frag_len, tmp_flag, mss, vlan);
6473 *entry = NEXT_TX(*entry);
6480 tg3_tx_set_bd(&tnapi->tx_ring[*entry], map,
6481 len, flags, mss, vlan);
6483 *entry = NEXT_TX(*entry);
6486 tnapi->tx_buffers[prvidx].fragmented = false;
6490 tg3_tx_set_bd(&tnapi->tx_ring[*entry], map,
6491 len, flags, mss, vlan);
6492 *entry = NEXT_TX(*entry);
6498 static void tg3_tx_skb_unmap(struct tg3_napi *tnapi, u32 entry, int last)
6501 struct sk_buff *skb;
6502 struct tg3_tx_ring_info *txb = &tnapi->tx_buffers[entry];
6507 pci_unmap_single(tnapi->tp->pdev,
6508 dma_unmap_addr(txb, mapping),
6512 while (txb->fragmented) {
6513 txb->fragmented = false;
6514 entry = NEXT_TX(entry);
6515 txb = &tnapi->tx_buffers[entry];
6518 for (i = 0; i <= last; i++) {
6519 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
6521 entry = NEXT_TX(entry);
6522 txb = &tnapi->tx_buffers[entry];
6524 pci_unmap_page(tnapi->tp->pdev,
6525 dma_unmap_addr(txb, mapping),
6526 skb_frag_size(frag), PCI_DMA_TODEVICE);
6528 while (txb->fragmented) {
6529 txb->fragmented = false;
6530 entry = NEXT_TX(entry);
6531 txb = &tnapi->tx_buffers[entry];
6536 /* Workaround 4GB and 40-bit hardware DMA bugs. */
6537 static int tigon3_dma_hwbug_workaround(struct tg3_napi *tnapi,
6538 struct sk_buff **pskb,
6539 u32 *entry, u32 *budget,
6540 u32 base_flags, u32 mss, u32 vlan)
6542 struct tg3 *tp = tnapi->tp;
6543 struct sk_buff *new_skb, *skb = *pskb;
6544 dma_addr_t new_addr = 0;
6547 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
6548 new_skb = skb_copy(skb, GFP_ATOMIC);
6550 int more_headroom = 4 - ((unsigned long)skb->data & 3);
6552 new_skb = skb_copy_expand(skb,
6553 skb_headroom(skb) + more_headroom,
6554 skb_tailroom(skb), GFP_ATOMIC);
6560 /* New SKB is guaranteed to be linear. */
6561 new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
6563 /* Make sure the mapping succeeded */
6564 if (pci_dma_mapping_error(tp->pdev, new_addr)) {
6565 dev_kfree_skb(new_skb);
6568 u32 save_entry = *entry;
6570 base_flags |= TXD_FLAG_END;
6572 tnapi->tx_buffers[*entry].skb = new_skb;
6573 dma_unmap_addr_set(&tnapi->tx_buffers[*entry],
6576 if (tg3_tx_frag_set(tnapi, entry, budget, new_addr,
6577 new_skb->len, base_flags,
6579 tg3_tx_skb_unmap(tnapi, save_entry, -1);
6580 dev_kfree_skb(new_skb);
6591 static netdev_tx_t tg3_start_xmit(struct sk_buff *, struct net_device *);
6593 /* Use GSO to workaround a rare TSO bug that may be triggered when the
6594 * TSO header is greater than 80 bytes.
6596 static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
6598 struct sk_buff *segs, *nskb;
6599 u32 frag_cnt_est = skb_shinfo(skb)->gso_segs * 3;
6601 /* Estimate the number of fragments in the worst case */
6602 if (unlikely(tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)) {
6603 netif_stop_queue(tp->dev);
6605 /* netif_tx_stop_queue() must be done before checking
6606 * checking tx index in tg3_tx_avail() below, because in
6607 * tg3_tx(), we update tx index before checking for
6608 * netif_tx_queue_stopped().
6611 if (tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)
6612 return NETDEV_TX_BUSY;
6614 netif_wake_queue(tp->dev);
6617 segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
6619 goto tg3_tso_bug_end;
6625 tg3_start_xmit(nskb, tp->dev);
6631 return NETDEV_TX_OK;
6634 /* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
6635 * support TG3_FLAG_HW_TSO_1 or firmware TSO only.
6637 static netdev_tx_t tg3_start_xmit(struct sk_buff *skb, struct net_device *dev)
6639 struct tg3 *tp = netdev_priv(dev);
6640 u32 len, entry, base_flags, mss, vlan = 0;
6642 int i = -1, would_hit_hwbug;
6644 struct tg3_napi *tnapi;
6645 struct netdev_queue *txq;
6648 txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
6649 tnapi = &tp->napi[skb_get_queue_mapping(skb)];
6650 if (tg3_flag(tp, ENABLE_TSS))
6653 budget = tg3_tx_avail(tnapi);
6655 /* We are running in BH disabled context with netif_tx_lock
6656 * and TX reclaim runs via tp->napi.poll inside of a software
6657 * interrupt. Furthermore, IRQ processing runs lockless so we have
6658 * no IRQ context deadlocks to worry about either. Rejoice!
6660 if (unlikely(budget <= (skb_shinfo(skb)->nr_frags + 1))) {
6661 if (!netif_tx_queue_stopped(txq)) {
6662 netif_tx_stop_queue(txq);
6664 /* This is a hard error, log it. */
6666 "BUG! Tx Ring full when queue awake!\n");
6668 return NETDEV_TX_BUSY;
6671 entry = tnapi->tx_prod;
6673 if (skb->ip_summed == CHECKSUM_PARTIAL)
6674 base_flags |= TXD_FLAG_TCPUDP_CSUM;
6676 mss = skb_shinfo(skb)->gso_size;
6679 u32 tcp_opt_len, hdr_len;
6681 if (skb_header_cloned(skb) &&
6682 pskb_expand_head(skb, 0, 0, GFP_ATOMIC))
6686 tcp_opt_len = tcp_optlen(skb);
6688 if (skb_is_gso_v6(skb)) {
6689 hdr_len = skb_headlen(skb) - ETH_HLEN;
6693 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
6694 hdr_len = ip_tcp_len + tcp_opt_len;
6697 iph->tot_len = htons(mss + hdr_len);
6700 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
6701 tg3_flag(tp, TSO_BUG))
6702 return tg3_tso_bug(tp, skb);
6704 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
6705 TXD_FLAG_CPU_POST_DMA);
6707 if (tg3_flag(tp, HW_TSO_1) ||
6708 tg3_flag(tp, HW_TSO_2) ||
6709 tg3_flag(tp, HW_TSO_3)) {
6710 tcp_hdr(skb)->check = 0;
6711 base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
6713 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
6718 if (tg3_flag(tp, HW_TSO_3)) {
6719 mss |= (hdr_len & 0xc) << 12;
6721 base_flags |= 0x00000010;
6722 base_flags |= (hdr_len & 0x3e0) << 5;
6723 } else if (tg3_flag(tp, HW_TSO_2))
6724 mss |= hdr_len << 9;
6725 else if (tg3_flag(tp, HW_TSO_1) ||
6726 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
6727 if (tcp_opt_len || iph->ihl > 5) {
6730 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
6731 mss |= (tsflags << 11);
6734 if (tcp_opt_len || iph->ihl > 5) {
6737 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
6738 base_flags |= tsflags << 12;
6743 if (tg3_flag(tp, USE_JUMBO_BDFLAG) &&
6744 !mss && skb->len > VLAN_ETH_FRAME_LEN)
6745 base_flags |= TXD_FLAG_JMB_PKT;
6747 if (vlan_tx_tag_present(skb)) {
6748 base_flags |= TXD_FLAG_VLAN;
6749 vlan = vlan_tx_tag_get(skb);
6752 len = skb_headlen(skb);
6754 mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
6755 if (pci_dma_mapping_error(tp->pdev, mapping))
6759 tnapi->tx_buffers[entry].skb = skb;
6760 dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping);
6762 would_hit_hwbug = 0;
6764 if (tg3_flag(tp, 5701_DMA_BUG))
6765 would_hit_hwbug = 1;
6767 if (tg3_tx_frag_set(tnapi, &entry, &budget, mapping, len, base_flags |
6768 ((skb_shinfo(skb)->nr_frags == 0) ? TXD_FLAG_END : 0),
6770 would_hit_hwbug = 1;
6771 /* Now loop through additional data fragments, and queue them. */
6772 } else if (skb_shinfo(skb)->nr_frags > 0) {
6775 if (!tg3_flag(tp, HW_TSO_1) &&
6776 !tg3_flag(tp, HW_TSO_2) &&
6777 !tg3_flag(tp, HW_TSO_3))
6780 last = skb_shinfo(skb)->nr_frags - 1;
6781 for (i = 0; i <= last; i++) {
6782 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
6784 len = skb_frag_size(frag);
6785 mapping = skb_frag_dma_map(&tp->pdev->dev, frag, 0,
6786 len, DMA_TO_DEVICE);
6788 tnapi->tx_buffers[entry].skb = NULL;
6789 dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
6791 if (dma_mapping_error(&tp->pdev->dev, mapping))
6795 tg3_tx_frag_set(tnapi, &entry, &budget, mapping,
6797 ((i == last) ? TXD_FLAG_END : 0),
6799 would_hit_hwbug = 1;
6805 if (would_hit_hwbug) {
6806 tg3_tx_skb_unmap(tnapi, tnapi->tx_prod, i);
6808 /* If the workaround fails due to memory/mapping
6809 * failure, silently drop this packet.
6811 entry = tnapi->tx_prod;
6812 budget = tg3_tx_avail(tnapi);
6813 if (tigon3_dma_hwbug_workaround(tnapi, &skb, &entry, &budget,
6814 base_flags, mss, vlan))
6818 skb_tx_timestamp(skb);
6820 /* Packets are ready, update Tx producer idx local and on card. */
6821 tw32_tx_mbox(tnapi->prodmbox, entry);
6823 tnapi->tx_prod = entry;
6824 if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
6825 netif_tx_stop_queue(txq);
6827 /* netif_tx_stop_queue() must be done before checking
6828 * checking tx index in tg3_tx_avail() below, because in
6829 * tg3_tx(), we update tx index before checking for
6830 * netif_tx_queue_stopped().
6833 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
6834 netif_tx_wake_queue(txq);
6838 return NETDEV_TX_OK;
6841 tg3_tx_skb_unmap(tnapi, tnapi->tx_prod, --i);
6842 tnapi->tx_buffers[tnapi->tx_prod].skb = NULL;
6847 return NETDEV_TX_OK;
6850 static void tg3_mac_loopback(struct tg3 *tp, bool enable)
6853 tp->mac_mode &= ~(MAC_MODE_HALF_DUPLEX |
6854 MAC_MODE_PORT_MODE_MASK);
6856 tp->mac_mode |= MAC_MODE_PORT_INT_LPBACK;
6858 if (!tg3_flag(tp, 5705_PLUS))
6859 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
6861 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
6862 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
6864 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
6866 tp->mac_mode &= ~MAC_MODE_PORT_INT_LPBACK;
6868 if (tg3_flag(tp, 5705_PLUS) ||
6869 (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) ||
6870 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
6871 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
6874 tw32(MAC_MODE, tp->mac_mode);
6878 static int tg3_phy_lpbk_set(struct tg3 *tp, u32 speed, bool extlpbk)
6880 u32 val, bmcr, mac_mode, ptest = 0;
6882 tg3_phy_toggle_apd(tp, false);
6883 tg3_phy_toggle_automdix(tp, 0);
6885 if (extlpbk && tg3_phy_set_extloopbk(tp))
6888 bmcr = BMCR_FULLDPLX;
6893 bmcr |= BMCR_SPEED100;
6897 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
6899 bmcr |= BMCR_SPEED100;
6902 bmcr |= BMCR_SPEED1000;
6907 if (!(tp->phy_flags & TG3_PHYFLG_IS_FET)) {
6908 tg3_readphy(tp, MII_CTRL1000, &val);
6909 val |= CTL1000_AS_MASTER |
6910 CTL1000_ENABLE_MASTER;
6911 tg3_writephy(tp, MII_CTRL1000, val);
6913 ptest = MII_TG3_FET_PTEST_TRIM_SEL |
6914 MII_TG3_FET_PTEST_TRIM_2;
6915 tg3_writephy(tp, MII_TG3_FET_PTEST, ptest);
6918 bmcr |= BMCR_LOOPBACK;
6920 tg3_writephy(tp, MII_BMCR, bmcr);
6922 /* The write needs to be flushed for the FETs */
6923 if (tp->phy_flags & TG3_PHYFLG_IS_FET)
6924 tg3_readphy(tp, MII_BMCR, &bmcr);
6928 if ((tp->phy_flags & TG3_PHYFLG_IS_FET) &&
6929 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
6930 tg3_writephy(tp, MII_TG3_FET_PTEST, ptest |
6931 MII_TG3_FET_PTEST_FRC_TX_LINK |
6932 MII_TG3_FET_PTEST_FRC_TX_LOCK);
6934 /* The write needs to be flushed for the AC131 */
6935 tg3_readphy(tp, MII_TG3_FET_PTEST, &val);
6938 /* Reset to prevent losing 1st rx packet intermittently */
6939 if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
6940 tg3_flag(tp, 5780_CLASS)) {
6941 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
6943 tw32_f(MAC_RX_MODE, tp->rx_mode);
6946 mac_mode = tp->mac_mode &
6947 ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
6948 if (speed == SPEED_1000)
6949 mac_mode |= MAC_MODE_PORT_MODE_GMII;
6951 mac_mode |= MAC_MODE_PORT_MODE_MII;
6953 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
6954 u32 masked_phy_id = tp->phy_id & TG3_PHY_ID_MASK;
6956 if (masked_phy_id == TG3_PHY_ID_BCM5401)
6957 mac_mode &= ~MAC_MODE_LINK_POLARITY;
6958 else if (masked_phy_id == TG3_PHY_ID_BCM5411)
6959 mac_mode |= MAC_MODE_LINK_POLARITY;
6961 tg3_writephy(tp, MII_TG3_EXT_CTRL,
6962 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
6965 tw32(MAC_MODE, mac_mode);
6971 static void tg3_set_loopback(struct net_device *dev, netdev_features_t features)
6973 struct tg3 *tp = netdev_priv(dev);
6975 if (features & NETIF_F_LOOPBACK) {
6976 if (tp->mac_mode & MAC_MODE_PORT_INT_LPBACK)
6979 spin_lock_bh(&tp->lock);
6980 tg3_mac_loopback(tp, true);
6981 netif_carrier_on(tp->dev);
6982 spin_unlock_bh(&tp->lock);
6983 netdev_info(dev, "Internal MAC loopback mode enabled.\n");
6985 if (!(tp->mac_mode & MAC_MODE_PORT_INT_LPBACK))
6988 spin_lock_bh(&tp->lock);
6989 tg3_mac_loopback(tp, false);
6990 /* Force link status check */
6991 tg3_setup_phy(tp, 1);
6992 spin_unlock_bh(&tp->lock);
6993 netdev_info(dev, "Internal MAC loopback mode disabled.\n");
6997 static netdev_features_t tg3_fix_features(struct net_device *dev,
6998 netdev_features_t features)
7000 struct tg3 *tp = netdev_priv(dev);
7002 if (dev->mtu > ETH_DATA_LEN && tg3_flag(tp, 5780_CLASS))
7003 features &= ~NETIF_F_ALL_TSO;
7008 static int tg3_set_features(struct net_device *dev, netdev_features_t features)
7010 netdev_features_t changed = dev->features ^ features;
7012 if ((changed & NETIF_F_LOOPBACK) && netif_running(dev))
7013 tg3_set_loopback(dev, features);
7018 static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
7023 if (new_mtu > ETH_DATA_LEN) {
7024 if (tg3_flag(tp, 5780_CLASS)) {
7025 netdev_update_features(dev);
7026 tg3_flag_clear(tp, TSO_CAPABLE);
7028 tg3_flag_set(tp, JUMBO_RING_ENABLE);
7031 if (tg3_flag(tp, 5780_CLASS)) {
7032 tg3_flag_set(tp, TSO_CAPABLE);
7033 netdev_update_features(dev);
7035 tg3_flag_clear(tp, JUMBO_RING_ENABLE);
7039 static int tg3_change_mtu(struct net_device *dev, int new_mtu)
7041 struct tg3 *tp = netdev_priv(dev);
7044 if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
7047 if (!netif_running(dev)) {
7048 /* We'll just catch it later when the
7051 tg3_set_mtu(dev, tp, new_mtu);
7059 tg3_full_lock(tp, 1);
7061 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7063 tg3_set_mtu(dev, tp, new_mtu);
7065 err = tg3_restart_hw(tp, 0);
7068 tg3_netif_start(tp);
7070 tg3_full_unlock(tp);
7078 static void tg3_rx_prodring_free(struct tg3 *tp,
7079 struct tg3_rx_prodring_set *tpr)
7083 if (tpr != &tp->napi[0].prodring) {
7084 for (i = tpr->rx_std_cons_idx; i != tpr->rx_std_prod_idx;
7085 i = (i + 1) & tp->rx_std_ring_mask)
7086 tg3_rx_skb_free(tp, &tpr->rx_std_buffers[i],
7089 if (tg3_flag(tp, JUMBO_CAPABLE)) {
7090 for (i = tpr->rx_jmb_cons_idx;
7091 i != tpr->rx_jmb_prod_idx;
7092 i = (i + 1) & tp->rx_jmb_ring_mask) {
7093 tg3_rx_skb_free(tp, &tpr->rx_jmb_buffers[i],
7101 for (i = 0; i <= tp->rx_std_ring_mask; i++)
7102 tg3_rx_skb_free(tp, &tpr->rx_std_buffers[i],
7105 if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS)) {
7106 for (i = 0; i <= tp->rx_jmb_ring_mask; i++)
7107 tg3_rx_skb_free(tp, &tpr->rx_jmb_buffers[i],
7112 /* Initialize rx rings for packet processing.
7114 * The chip has been shut down and the driver detached from
7115 * the networking, so no interrupts or new tx packets will
7116 * end up in the driver. tp->{tx,}lock are held and thus
7119 static int tg3_rx_prodring_alloc(struct tg3 *tp,
7120 struct tg3_rx_prodring_set *tpr)
7122 u32 i, rx_pkt_dma_sz;
7124 tpr->rx_std_cons_idx = 0;
7125 tpr->rx_std_prod_idx = 0;
7126 tpr->rx_jmb_cons_idx = 0;
7127 tpr->rx_jmb_prod_idx = 0;
7129 if (tpr != &tp->napi[0].prodring) {
7130 memset(&tpr->rx_std_buffers[0], 0,
7131 TG3_RX_STD_BUFF_RING_SIZE(tp));
7132 if (tpr->rx_jmb_buffers)
7133 memset(&tpr->rx_jmb_buffers[0], 0,
7134 TG3_RX_JMB_BUFF_RING_SIZE(tp));
7138 /* Zero out all descriptors. */
7139 memset(tpr->rx_std, 0, TG3_RX_STD_RING_BYTES(tp));
7141 rx_pkt_dma_sz = TG3_RX_STD_DMA_SZ;
7142 if (tg3_flag(tp, 5780_CLASS) &&
7143 tp->dev->mtu > ETH_DATA_LEN)
7144 rx_pkt_dma_sz = TG3_RX_JMB_DMA_SZ;
7145 tp->rx_pkt_map_sz = TG3_RX_DMA_TO_MAP_SZ(rx_pkt_dma_sz);
7147 /* Initialize invariants of the rings, we only set this
7148 * stuff once. This works because the card does not
7149 * write into the rx buffer posting rings.
7151 for (i = 0; i <= tp->rx_std_ring_mask; i++) {
7152 struct tg3_rx_buffer_desc *rxd;
7154 rxd = &tpr->rx_std[i];
7155 rxd->idx_len = rx_pkt_dma_sz << RXD_LEN_SHIFT;
7156 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
7157 rxd->opaque = (RXD_OPAQUE_RING_STD |
7158 (i << RXD_OPAQUE_INDEX_SHIFT));
7161 /* Now allocate fresh SKBs for each rx ring. */
7162 for (i = 0; i < tp->rx_pending; i++) {
7163 if (tg3_alloc_rx_skb(tp, tpr, RXD_OPAQUE_RING_STD, i) < 0) {
7164 netdev_warn(tp->dev,
7165 "Using a smaller RX standard ring. Only "
7166 "%d out of %d buffers were allocated "
7167 "successfully\n", i, tp->rx_pending);
7175 if (!tg3_flag(tp, JUMBO_CAPABLE) || tg3_flag(tp, 5780_CLASS))
7178 memset(tpr->rx_jmb, 0, TG3_RX_JMB_RING_BYTES(tp));
7180 if (!tg3_flag(tp, JUMBO_RING_ENABLE))
7183 for (i = 0; i <= tp->rx_jmb_ring_mask; i++) {
7184 struct tg3_rx_buffer_desc *rxd;
7186 rxd = &tpr->rx_jmb[i].std;
7187 rxd->idx_len = TG3_RX_JMB_DMA_SZ << RXD_LEN_SHIFT;
7188 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
7190 rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
7191 (i << RXD_OPAQUE_INDEX_SHIFT));
7194 for (i = 0; i < tp->rx_jumbo_pending; i++) {
7195 if (tg3_alloc_rx_skb(tp, tpr, RXD_OPAQUE_RING_JUMBO, i) < 0) {
7196 netdev_warn(tp->dev,
7197 "Using a smaller RX jumbo ring. Only %d "
7198 "out of %d buffers were allocated "
7199 "successfully\n", i, tp->rx_jumbo_pending);
7202 tp->rx_jumbo_pending = i;
7211 tg3_rx_prodring_free(tp, tpr);
7215 static void tg3_rx_prodring_fini(struct tg3 *tp,
7216 struct tg3_rx_prodring_set *tpr)
7218 kfree(tpr->rx_std_buffers);
7219 tpr->rx_std_buffers = NULL;
7220 kfree(tpr->rx_jmb_buffers);
7221 tpr->rx_jmb_buffers = NULL;
7223 dma_free_coherent(&tp->pdev->dev, TG3_RX_STD_RING_BYTES(tp),
7224 tpr->rx_std, tpr->rx_std_mapping);
7228 dma_free_coherent(&tp->pdev->dev, TG3_RX_JMB_RING_BYTES(tp),
7229 tpr->rx_jmb, tpr->rx_jmb_mapping);
7234 static int tg3_rx_prodring_init(struct tg3 *tp,
7235 struct tg3_rx_prodring_set *tpr)
7237 tpr->rx_std_buffers = kzalloc(TG3_RX_STD_BUFF_RING_SIZE(tp),
7239 if (!tpr->rx_std_buffers)
7242 tpr->rx_std = dma_alloc_coherent(&tp->pdev->dev,
7243 TG3_RX_STD_RING_BYTES(tp),
7244 &tpr->rx_std_mapping,
7249 if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS)) {
7250 tpr->rx_jmb_buffers = kzalloc(TG3_RX_JMB_BUFF_RING_SIZE(tp),
7252 if (!tpr->rx_jmb_buffers)
7255 tpr->rx_jmb = dma_alloc_coherent(&tp->pdev->dev,
7256 TG3_RX_JMB_RING_BYTES(tp),
7257 &tpr->rx_jmb_mapping,
7266 tg3_rx_prodring_fini(tp, tpr);
7270 /* Free up pending packets in all rx/tx rings.
7272 * The chip has been shut down and the driver detached from
7273 * the networking, so no interrupts or new tx packets will
7274 * end up in the driver. tp->{tx,}lock is not held and we are not
7275 * in an interrupt context and thus may sleep.
7277 static void tg3_free_rings(struct tg3 *tp)
7281 for (j = 0; j < tp->irq_cnt; j++) {
7282 struct tg3_napi *tnapi = &tp->napi[j];
7284 tg3_rx_prodring_free(tp, &tnapi->prodring);
7286 if (!tnapi->tx_buffers)
7289 for (i = 0; i < TG3_TX_RING_SIZE; i++) {
7290 struct sk_buff *skb = tnapi->tx_buffers[i].skb;
7295 tg3_tx_skb_unmap(tnapi, i,
7296 skb_shinfo(skb)->nr_frags - 1);
7298 dev_kfree_skb_any(skb);
7303 /* Initialize tx/rx rings for packet processing.
7305 * The chip has been shut down and the driver detached from
7306 * the networking, so no interrupts or new tx packets will
7307 * end up in the driver. tp->{tx,}lock are held and thus
7310 static int tg3_init_rings(struct tg3 *tp)
7314 /* Free up all the SKBs. */
7317 for (i = 0; i < tp->irq_cnt; i++) {
7318 struct tg3_napi *tnapi = &tp->napi[i];
7320 tnapi->last_tag = 0;
7321 tnapi->last_irq_tag = 0;
7322 tnapi->hw_status->status = 0;
7323 tnapi->hw_status->status_tag = 0;
7324 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7329 memset(tnapi->tx_ring, 0, TG3_TX_RING_BYTES);
7331 tnapi->rx_rcb_ptr = 0;
7333 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
7335 if (tg3_rx_prodring_alloc(tp, &tnapi->prodring)) {
7345 * Must not be invoked with interrupt sources disabled and
7346 * the hardware shutdown down.
7348 static void tg3_free_consistent(struct tg3 *tp)
7352 for (i = 0; i < tp->irq_cnt; i++) {
7353 struct tg3_napi *tnapi = &tp->napi[i];
7355 if (tnapi->tx_ring) {
7356 dma_free_coherent(&tp->pdev->dev, TG3_TX_RING_BYTES,
7357 tnapi->tx_ring, tnapi->tx_desc_mapping);
7358 tnapi->tx_ring = NULL;
7361 kfree(tnapi->tx_buffers);
7362 tnapi->tx_buffers = NULL;
7364 if (tnapi->rx_rcb) {
7365 dma_free_coherent(&tp->pdev->dev,
7366 TG3_RX_RCB_RING_BYTES(tp),
7368 tnapi->rx_rcb_mapping);
7369 tnapi->rx_rcb = NULL;
7372 tg3_rx_prodring_fini(tp, &tnapi->prodring);
7374 if (tnapi->hw_status) {
7375 dma_free_coherent(&tp->pdev->dev, TG3_HW_STATUS_SIZE,
7377 tnapi->status_mapping);
7378 tnapi->hw_status = NULL;
7383 dma_free_coherent(&tp->pdev->dev, sizeof(struct tg3_hw_stats),
7384 tp->hw_stats, tp->stats_mapping);
7385 tp->hw_stats = NULL;
7390 * Must not be invoked with interrupt sources disabled and
7391 * the hardware shutdown down. Can sleep.
7393 static int tg3_alloc_consistent(struct tg3 *tp)
7397 tp->hw_stats = dma_alloc_coherent(&tp->pdev->dev,
7398 sizeof(struct tg3_hw_stats),
7404 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
7406 for (i = 0; i < tp->irq_cnt; i++) {
7407 struct tg3_napi *tnapi = &tp->napi[i];
7408 struct tg3_hw_status *sblk;
7410 tnapi->hw_status = dma_alloc_coherent(&tp->pdev->dev,
7412 &tnapi->status_mapping,
7414 if (!tnapi->hw_status)
7417 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7418 sblk = tnapi->hw_status;
7420 if (tg3_rx_prodring_init(tp, &tnapi->prodring))
7423 /* If multivector TSS is enabled, vector 0 does not handle
7424 * tx interrupts. Don't allocate any resources for it.
7426 if ((!i && !tg3_flag(tp, ENABLE_TSS)) ||
7427 (i && tg3_flag(tp, ENABLE_TSS))) {
7428 tnapi->tx_buffers = kzalloc(
7429 sizeof(struct tg3_tx_ring_info) *
7430 TG3_TX_RING_SIZE, GFP_KERNEL);
7431 if (!tnapi->tx_buffers)
7434 tnapi->tx_ring = dma_alloc_coherent(&tp->pdev->dev,
7436 &tnapi->tx_desc_mapping,
7438 if (!tnapi->tx_ring)
7443 * When RSS is enabled, the status block format changes
7444 * slightly. The "rx_jumbo_consumer", "reserved",
7445 * and "rx_mini_consumer" members get mapped to the
7446 * other three rx return ring producer indexes.
7450 tnapi->rx_rcb_prod_idx = &sblk->idx[0].rx_producer;
7453 tnapi->rx_rcb_prod_idx = &sblk->rx_jumbo_consumer;
7456 tnapi->rx_rcb_prod_idx = &sblk->reserved;
7459 tnapi->rx_rcb_prod_idx = &sblk->rx_mini_consumer;
7464 * If multivector RSS is enabled, vector 0 does not handle
7465 * rx or tx interrupts. Don't allocate any resources for it.
7467 if (!i && tg3_flag(tp, ENABLE_RSS))
7470 tnapi->rx_rcb = dma_alloc_coherent(&tp->pdev->dev,
7471 TG3_RX_RCB_RING_BYTES(tp),
7472 &tnapi->rx_rcb_mapping,
7477 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
7483 tg3_free_consistent(tp);
7487 #define MAX_WAIT_CNT 1000
7489 /* To stop a block, clear the enable bit and poll till it
7490 * clears. tp->lock is held.
7492 static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
7497 if (tg3_flag(tp, 5705_PLUS)) {
7504 /* We can't enable/disable these bits of the
7505 * 5705/5750, just say success.
7518 for (i = 0; i < MAX_WAIT_CNT; i++) {
7521 if ((val & enable_bit) == 0)
7525 if (i == MAX_WAIT_CNT && !silent) {
7526 dev_err(&tp->pdev->dev,
7527 "tg3_stop_block timed out, ofs=%lx enable_bit=%x\n",
7535 /* tp->lock is held. */
7536 static int tg3_abort_hw(struct tg3 *tp, int silent)
7540 tg3_disable_ints(tp);
7542 tp->rx_mode &= ~RX_MODE_ENABLE;
7543 tw32_f(MAC_RX_MODE, tp->rx_mode);
7546 err = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
7547 err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
7548 err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
7549 err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
7550 err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
7551 err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
7553 err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
7554 err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
7555 err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
7556 err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
7557 err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
7558 err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
7559 err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
7561 tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
7562 tw32_f(MAC_MODE, tp->mac_mode);
7565 tp->tx_mode &= ~TX_MODE_ENABLE;
7566 tw32_f(MAC_TX_MODE, tp->tx_mode);
7568 for (i = 0; i < MAX_WAIT_CNT; i++) {
7570 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
7573 if (i >= MAX_WAIT_CNT) {
7574 dev_err(&tp->pdev->dev,
7575 "%s timed out, TX_MODE_ENABLE will not clear "
7576 "MAC_TX_MODE=%08x\n", __func__, tr32(MAC_TX_MODE));
7580 err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
7581 err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
7582 err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
7584 tw32(FTQ_RESET, 0xffffffff);
7585 tw32(FTQ_RESET, 0x00000000);
7587 err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
7588 err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
7590 for (i = 0; i < tp->irq_cnt; i++) {
7591 struct tg3_napi *tnapi = &tp->napi[i];
7592 if (tnapi->hw_status)
7593 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7596 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
7601 /* Save PCI command register before chip reset */
7602 static void tg3_save_pci_state(struct tg3 *tp)
7604 pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd);
7607 /* Restore PCI state after chip reset */
7608 static void tg3_restore_pci_state(struct tg3 *tp)
7612 /* Re-enable indirect register accesses. */
7613 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
7614 tp->misc_host_ctrl);
7616 /* Set MAX PCI retry to zero. */
7617 val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
7618 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
7619 tg3_flag(tp, PCIX_MODE))
7620 val |= PCISTATE_RETRY_SAME_DMA;
7621 /* Allow reads and writes to the APE register and memory space. */
7622 if (tg3_flag(tp, ENABLE_APE))
7623 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
7624 PCISTATE_ALLOW_APE_SHMEM_WR |
7625 PCISTATE_ALLOW_APE_PSPACE_WR;
7626 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
7628 pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);
7630 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785) {
7631 if (tg3_flag(tp, PCI_EXPRESS))
7632 pcie_set_readrq(tp->pdev, tp->pcie_readrq);
7634 pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
7635 tp->pci_cacheline_sz);
7636 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
7641 /* Make sure PCI-X relaxed ordering bit is clear. */
7642 if (tg3_flag(tp, PCIX_MODE)) {
7645 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
7647 pcix_cmd &= ~PCI_X_CMD_ERO;
7648 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
7652 if (tg3_flag(tp, 5780_CLASS)) {
7654 /* Chip reset on 5780 will reset MSI enable bit,
7655 * so need to restore it.
7657 if (tg3_flag(tp, USING_MSI)) {
7660 pci_read_config_word(tp->pdev,
7661 tp->msi_cap + PCI_MSI_FLAGS,
7663 pci_write_config_word(tp->pdev,
7664 tp->msi_cap + PCI_MSI_FLAGS,
7665 ctrl | PCI_MSI_FLAGS_ENABLE);
7666 val = tr32(MSGINT_MODE);
7667 tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
7672 /* tp->lock is held. */
7673 static int tg3_chip_reset(struct tg3 *tp)
7676 void (*write_op)(struct tg3 *, u32, u32);
7681 tg3_ape_lock(tp, TG3_APE_LOCK_GRC);
7683 /* No matching tg3_nvram_unlock() after this because
7684 * chip reset below will undo the nvram lock.
7686 tp->nvram_lock_cnt = 0;
7688 /* GRC_MISC_CFG core clock reset will clear the memory
7689 * enable bit in PCI register 4 and the MSI enable bit
7690 * on some chips, so we save relevant registers here.
7692 tg3_save_pci_state(tp);
7694 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
7695 tg3_flag(tp, 5755_PLUS))
7696 tw32(GRC_FASTBOOT_PC, 0);
7699 * We must avoid the readl() that normally takes place.
7700 * It locks machines, causes machine checks, and other
7701 * fun things. So, temporarily disable the 5701
7702 * hardware workaround, while we do the reset.
7704 write_op = tp->write32;
7705 if (write_op == tg3_write_flush_reg32)
7706 tp->write32 = tg3_write32;
7708 /* Prevent the irq handler from reading or writing PCI registers
7709 * during chip reset when the memory enable bit in the PCI command
7710 * register may be cleared. The chip does not generate interrupt
7711 * at this time, but the irq handler may still be called due to irq
7712 * sharing or irqpoll.
7714 tg3_flag_set(tp, CHIP_RESETTING);
7715 for (i = 0; i < tp->irq_cnt; i++) {
7716 struct tg3_napi *tnapi = &tp->napi[i];
7717 if (tnapi->hw_status) {
7718 tnapi->hw_status->status = 0;
7719 tnapi->hw_status->status_tag = 0;
7721 tnapi->last_tag = 0;
7722 tnapi->last_irq_tag = 0;
7726 for (i = 0; i < tp->irq_cnt; i++)
7727 synchronize_irq(tp->napi[i].irq_vec);
7729 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
7730 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
7731 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
7735 val = GRC_MISC_CFG_CORECLK_RESET;
7737 if (tg3_flag(tp, PCI_EXPRESS)) {
7738 /* Force PCIe 1.0a mode */
7739 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
7740 !tg3_flag(tp, 57765_PLUS) &&
7741 tr32(TG3_PCIE_PHY_TSTCTL) ==
7742 (TG3_PCIE_PHY_TSTCTL_PCIE10 | TG3_PCIE_PHY_TSTCTL_PSCRAM))
7743 tw32(TG3_PCIE_PHY_TSTCTL, TG3_PCIE_PHY_TSTCTL_PSCRAM);
7745 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
7746 tw32(GRC_MISC_CFG, (1 << 29));
7751 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
7752 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
7753 tw32(GRC_VCPU_EXT_CTRL,
7754 tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
7757 /* Manage gphy power for all CPMU absent PCIe devices. */
7758 if (tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, CPMU_PRESENT))
7759 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
7761 tw32(GRC_MISC_CFG, val);
7763 /* restore 5701 hardware bug workaround write method */
7764 tp->write32 = write_op;
7766 /* Unfortunately, we have to delay before the PCI read back.
7767 * Some 575X chips even will not respond to a PCI cfg access
7768 * when the reset command is given to the chip.
7770 * How do these hardware designers expect things to work
7771 * properly if the PCI write is posted for a long period
7772 * of time? It is always necessary to have some method by
7773 * which a register read back can occur to push the write
7774 * out which does the reset.
7776 * For most tg3 variants the trick below was working.
7781 /* Flush PCI posted writes. The normal MMIO registers
7782 * are inaccessible at this time so this is the only
7783 * way to make this reliably (actually, this is no longer
7784 * the case, see above). I tried to use indirect
7785 * register read/write but this upset some 5701 variants.
7787 pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
7791 if (tg3_flag(tp, PCI_EXPRESS) && pci_pcie_cap(tp->pdev)) {
7794 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
7798 /* Wait for link training to complete. */
7799 for (i = 0; i < 5000; i++)
7802 pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
7803 pci_write_config_dword(tp->pdev, 0xc4,
7804 cfg_val | (1 << 15));
7807 /* Clear the "no snoop" and "relaxed ordering" bits. */
7808 pci_read_config_word(tp->pdev,
7809 pci_pcie_cap(tp->pdev) + PCI_EXP_DEVCTL,
7811 val16 &= ~(PCI_EXP_DEVCTL_RELAX_EN |
7812 PCI_EXP_DEVCTL_NOSNOOP_EN);
7814 * Older PCIe devices only support the 128 byte
7815 * MPS setting. Enforce the restriction.
7817 if (!tg3_flag(tp, CPMU_PRESENT))
7818 val16 &= ~PCI_EXP_DEVCTL_PAYLOAD;
7819 pci_write_config_word(tp->pdev,
7820 pci_pcie_cap(tp->pdev) + PCI_EXP_DEVCTL,
7823 pcie_set_readrq(tp->pdev, tp->pcie_readrq);
7825 /* Clear error status */
7826 pci_write_config_word(tp->pdev,
7827 pci_pcie_cap(tp->pdev) + PCI_EXP_DEVSTA,
7828 PCI_EXP_DEVSTA_CED |
7829 PCI_EXP_DEVSTA_NFED |
7830 PCI_EXP_DEVSTA_FED |
7831 PCI_EXP_DEVSTA_URD);
7834 tg3_restore_pci_state(tp);
7836 tg3_flag_clear(tp, CHIP_RESETTING);
7837 tg3_flag_clear(tp, ERROR_PROCESSED);
7840 if (tg3_flag(tp, 5780_CLASS))
7841 val = tr32(MEMARB_MODE);
7842 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
7844 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
7846 tw32(0x5000, 0x400);
7849 tw32(GRC_MODE, tp->grc_mode);
7851 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
7854 tw32(0xc4, val | (1 << 15));
7857 if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
7858 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
7859 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
7860 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
7861 tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
7862 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
7865 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
7866 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
7868 } else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) {
7869 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
7874 tw32_f(MAC_MODE, val);
7877 tg3_ape_unlock(tp, TG3_APE_LOCK_GRC);
7879 err = tg3_poll_fw(tp);
7885 if (tg3_flag(tp, PCI_EXPRESS) &&
7886 tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
7887 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
7888 !tg3_flag(tp, 57765_PLUS)) {
7891 tw32(0x7c00, val | (1 << 25));
7894 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) {
7895 val = tr32(TG3_CPMU_CLCK_ORIDE);
7896 tw32(TG3_CPMU_CLCK_ORIDE, val & ~CPMU_CLCK_ORIDE_MAC_ORIDE_EN);
7899 /* Reprobe ASF enable state. */
7900 tg3_flag_clear(tp, ENABLE_ASF);
7901 tg3_flag_clear(tp, ASF_NEW_HANDSHAKE);
7902 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
7903 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
7906 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
7907 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
7908 tg3_flag_set(tp, ENABLE_ASF);
7909 tp->last_event_jiffies = jiffies;
7910 if (tg3_flag(tp, 5750_PLUS))
7911 tg3_flag_set(tp, ASF_NEW_HANDSHAKE);
7918 /* tp->lock is held. */
7919 static int tg3_halt(struct tg3 *tp, int kind, int silent)
7925 tg3_write_sig_pre_reset(tp, kind);
7927 tg3_abort_hw(tp, silent);
7928 err = tg3_chip_reset(tp);
7930 __tg3_set_mac_addr(tp, 0);
7932 tg3_write_sig_legacy(tp, kind);
7933 tg3_write_sig_post_reset(tp, kind);
7941 static int tg3_set_mac_addr(struct net_device *dev, void *p)
7943 struct tg3 *tp = netdev_priv(dev);
7944 struct sockaddr *addr = p;
7945 int err = 0, skip_mac_1 = 0;
7947 if (!is_valid_ether_addr(addr->sa_data))
7950 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
7952 if (!netif_running(dev))
7955 if (tg3_flag(tp, ENABLE_ASF)) {
7956 u32 addr0_high, addr0_low, addr1_high, addr1_low;
7958 addr0_high = tr32(MAC_ADDR_0_HIGH);
7959 addr0_low = tr32(MAC_ADDR_0_LOW);
7960 addr1_high = tr32(MAC_ADDR_1_HIGH);
7961 addr1_low = tr32(MAC_ADDR_1_LOW);
7963 /* Skip MAC addr 1 if ASF is using it. */
7964 if ((addr0_high != addr1_high || addr0_low != addr1_low) &&
7965 !(addr1_high == 0 && addr1_low == 0))
7968 spin_lock_bh(&tp->lock);
7969 __tg3_set_mac_addr(tp, skip_mac_1);
7970 spin_unlock_bh(&tp->lock);
7975 /* tp->lock is held. */
7976 static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
7977 dma_addr_t mapping, u32 maxlen_flags,
7981 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
7982 ((u64) mapping >> 32));
7984 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
7985 ((u64) mapping & 0xffffffff));
7987 (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
7990 if (!tg3_flag(tp, 5705_PLUS))
7992 (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
7996 static void __tg3_set_rx_mode(struct net_device *);
7997 static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
8001 if (!tg3_flag(tp, ENABLE_TSS)) {
8002 tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
8003 tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
8004 tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
8006 tw32(HOSTCC_TXCOL_TICKS, 0);
8007 tw32(HOSTCC_TXMAX_FRAMES, 0);
8008 tw32(HOSTCC_TXCOAL_MAXF_INT, 0);
8011 if (!tg3_flag(tp, ENABLE_RSS)) {
8012 tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
8013 tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
8014 tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
8016 tw32(HOSTCC_RXCOL_TICKS, 0);
8017 tw32(HOSTCC_RXMAX_FRAMES, 0);
8018 tw32(HOSTCC_RXCOAL_MAXF_INT, 0);
8021 if (!tg3_flag(tp, 5705_PLUS)) {
8022 u32 val = ec->stats_block_coalesce_usecs;
8024 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
8025 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
8027 if (!netif_carrier_ok(tp->dev))
8030 tw32(HOSTCC_STAT_COAL_TICKS, val);
8033 for (i = 0; i < tp->irq_cnt - 1; i++) {
8036 reg = HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18;
8037 tw32(reg, ec->rx_coalesce_usecs);
8038 reg = HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18;
8039 tw32(reg, ec->rx_max_coalesced_frames);
8040 reg = HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18;
8041 tw32(reg, ec->rx_max_coalesced_frames_irq);
8043 if (tg3_flag(tp, ENABLE_TSS)) {
8044 reg = HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18;
8045 tw32(reg, ec->tx_coalesce_usecs);
8046 reg = HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18;
8047 tw32(reg, ec->tx_max_coalesced_frames);
8048 reg = HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18;
8049 tw32(reg, ec->tx_max_coalesced_frames_irq);
8053 for (; i < tp->irq_max - 1; i++) {
8054 tw32(HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18, 0);
8055 tw32(HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18, 0);
8056 tw32(HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
8058 if (tg3_flag(tp, ENABLE_TSS)) {
8059 tw32(HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18, 0);
8060 tw32(HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18, 0);
8061 tw32(HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
8066 /* tp->lock is held. */
8067 static void tg3_rings_reset(struct tg3 *tp)
8070 u32 stblk, txrcb, rxrcb, limit;
8071 struct tg3_napi *tnapi = &tp->napi[0];
8073 /* Disable all transmit rings but the first. */
8074 if (!tg3_flag(tp, 5705_PLUS))
8075 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 16;
8076 else if (tg3_flag(tp, 5717_PLUS))
8077 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 4;
8078 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
8079 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 2;
8081 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
8083 for (txrcb = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
8084 txrcb < limit; txrcb += TG3_BDINFO_SIZE)
8085 tg3_write_mem(tp, txrcb + TG3_BDINFO_MAXLEN_FLAGS,
8086 BDINFO_FLAGS_DISABLED);
8089 /* Disable all receive return rings but the first. */
8090 if (tg3_flag(tp, 5717_PLUS))
8091 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 17;
8092 else if (!tg3_flag(tp, 5705_PLUS))
8093 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 16;
8094 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
8095 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
8096 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 4;
8098 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
8100 for (rxrcb = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
8101 rxrcb < limit; rxrcb += TG3_BDINFO_SIZE)
8102 tg3_write_mem(tp, rxrcb + TG3_BDINFO_MAXLEN_FLAGS,
8103 BDINFO_FLAGS_DISABLED);
8105 /* Disable interrupts */
8106 tw32_mailbox_f(tp->napi[0].int_mbox, 1);
8107 tp->napi[0].chk_msi_cnt = 0;
8108 tp->napi[0].last_rx_cons = 0;
8109 tp->napi[0].last_tx_cons = 0;
8111 /* Zero mailbox registers. */
8112 if (tg3_flag(tp, SUPPORT_MSIX)) {
8113 for (i = 1; i < tp->irq_max; i++) {
8114 tp->napi[i].tx_prod = 0;
8115 tp->napi[i].tx_cons = 0;
8116 if (tg3_flag(tp, ENABLE_TSS))
8117 tw32_mailbox(tp->napi[i].prodmbox, 0);
8118 tw32_rx_mbox(tp->napi[i].consmbox, 0);
8119 tw32_mailbox_f(tp->napi[i].int_mbox, 1);
8120 tp->napi[i].chk_msi_cnt = 0;
8121 tp->napi[i].last_rx_cons = 0;
8122 tp->napi[i].last_tx_cons = 0;
8124 if (!tg3_flag(tp, ENABLE_TSS))
8125 tw32_mailbox(tp->napi[0].prodmbox, 0);
8127 tp->napi[0].tx_prod = 0;
8128 tp->napi[0].tx_cons = 0;
8129 tw32_mailbox(tp->napi[0].prodmbox, 0);
8130 tw32_rx_mbox(tp->napi[0].consmbox, 0);
8133 /* Make sure the NIC-based send BD rings are disabled. */
8134 if (!tg3_flag(tp, 5705_PLUS)) {
8135 u32 mbox = MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW;
8136 for (i = 0; i < 16; i++)
8137 tw32_tx_mbox(mbox + i * 8, 0);
8140 txrcb = NIC_SRAM_SEND_RCB;
8141 rxrcb = NIC_SRAM_RCV_RET_RCB;
8143 /* Clear status block in ram. */
8144 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
8146 /* Set status block DMA address */
8147 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
8148 ((u64) tnapi->status_mapping >> 32));
8149 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
8150 ((u64) tnapi->status_mapping & 0xffffffff));
8152 if (tnapi->tx_ring) {
8153 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
8154 (TG3_TX_RING_SIZE <<
8155 BDINFO_FLAGS_MAXLEN_SHIFT),
8156 NIC_SRAM_TX_BUFFER_DESC);
8157 txrcb += TG3_BDINFO_SIZE;
8160 if (tnapi->rx_rcb) {
8161 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
8162 (tp->rx_ret_ring_mask + 1) <<
8163 BDINFO_FLAGS_MAXLEN_SHIFT, 0);
8164 rxrcb += TG3_BDINFO_SIZE;
8167 stblk = HOSTCC_STATBLCK_RING1;
8169 for (i = 1, tnapi++; i < tp->irq_cnt; i++, tnapi++) {
8170 u64 mapping = (u64)tnapi->status_mapping;
8171 tw32(stblk + TG3_64BIT_REG_HIGH, mapping >> 32);
8172 tw32(stblk + TG3_64BIT_REG_LOW, mapping & 0xffffffff);
8174 /* Clear status block in ram. */
8175 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
8177 if (tnapi->tx_ring) {
8178 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
8179 (TG3_TX_RING_SIZE <<
8180 BDINFO_FLAGS_MAXLEN_SHIFT),
8181 NIC_SRAM_TX_BUFFER_DESC);
8182 txrcb += TG3_BDINFO_SIZE;
8185 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
8186 ((tp->rx_ret_ring_mask + 1) <<
8187 BDINFO_FLAGS_MAXLEN_SHIFT), 0);
8190 rxrcb += TG3_BDINFO_SIZE;
8194 static void tg3_setup_rxbd_thresholds(struct tg3 *tp)
8196 u32 val, bdcache_maxcnt, host_rep_thresh, nic_rep_thresh;
8198 if (!tg3_flag(tp, 5750_PLUS) ||
8199 tg3_flag(tp, 5780_CLASS) ||
8200 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
8201 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
8202 bdcache_maxcnt = TG3_SRAM_RX_STD_BDCACHE_SIZE_5700;
8203 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
8204 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
8205 bdcache_maxcnt = TG3_SRAM_RX_STD_BDCACHE_SIZE_5755;
8207 bdcache_maxcnt = TG3_SRAM_RX_STD_BDCACHE_SIZE_5906;
8209 nic_rep_thresh = min(bdcache_maxcnt / 2, tp->rx_std_max_post);
8210 host_rep_thresh = max_t(u32, tp->rx_pending / 8, 1);
8212 val = min(nic_rep_thresh, host_rep_thresh);
8213 tw32(RCVBDI_STD_THRESH, val);
8215 if (tg3_flag(tp, 57765_PLUS))
8216 tw32(STD_REPLENISH_LWM, bdcache_maxcnt);
8218 if (!tg3_flag(tp, JUMBO_CAPABLE) || tg3_flag(tp, 5780_CLASS))
8221 if (!tg3_flag(tp, 5705_PLUS))
8222 bdcache_maxcnt = TG3_SRAM_RX_JMB_BDCACHE_SIZE_5700;
8224 bdcache_maxcnt = TG3_SRAM_RX_JMB_BDCACHE_SIZE_5717;
8226 host_rep_thresh = max_t(u32, tp->rx_jumbo_pending / 8, 1);
8228 val = min(bdcache_maxcnt / 2, host_rep_thresh);
8229 tw32(RCVBDI_JUMBO_THRESH, val);
8231 if (tg3_flag(tp, 57765_PLUS))
8232 tw32(JMB_REPLENISH_LWM, bdcache_maxcnt);
8235 /* tp->lock is held. */
8236 static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
8238 u32 val, rdmac_mode;
8240 struct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring;
8242 tg3_disable_ints(tp);
8246 tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
8248 if (tg3_flag(tp, INIT_COMPLETE))
8249 tg3_abort_hw(tp, 1);
8251 /* Enable MAC control of LPI */
8252 if (tp->phy_flags & TG3_PHYFLG_EEE_CAP) {
8253 tw32_f(TG3_CPMU_EEE_LNKIDL_CTRL,
8254 TG3_CPMU_EEE_LNKIDL_PCIE_NL0 |
8255 TG3_CPMU_EEE_LNKIDL_UART_IDL);
8257 tw32_f(TG3_CPMU_EEE_CTRL,
8258 TG3_CPMU_EEE_CTRL_EXIT_20_1_US);
8260 val = TG3_CPMU_EEEMD_ERLY_L1_XIT_DET |
8261 TG3_CPMU_EEEMD_LPI_IN_TX |
8262 TG3_CPMU_EEEMD_LPI_IN_RX |
8263 TG3_CPMU_EEEMD_EEE_ENABLE;
8265 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717)
8266 val |= TG3_CPMU_EEEMD_SND_IDX_DET_EN;
8268 if (tg3_flag(tp, ENABLE_APE))
8269 val |= TG3_CPMU_EEEMD_APE_TX_DET_EN;
8271 tw32_f(TG3_CPMU_EEE_MODE, val);
8273 tw32_f(TG3_CPMU_EEE_DBTMR1,
8274 TG3_CPMU_DBTMR1_PCIEXIT_2047US |
8275 TG3_CPMU_DBTMR1_LNKIDLE_2047US);
8277 tw32_f(TG3_CPMU_EEE_DBTMR2,
8278 TG3_CPMU_DBTMR2_APE_TX_2047US |
8279 TG3_CPMU_DBTMR2_TXIDXEQ_2047US);
8285 err = tg3_chip_reset(tp);
8289 tg3_write_sig_legacy(tp, RESET_KIND_INIT);
8291 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
8292 val = tr32(TG3_CPMU_CTRL);
8293 val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE);
8294 tw32(TG3_CPMU_CTRL, val);
8296 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
8297 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
8298 val |= CPMU_LSPD_10MB_MACCLK_6_25;
8299 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
8301 val = tr32(TG3_CPMU_LNK_AWARE_PWRMD);
8302 val &= ~CPMU_LNK_AWARE_MACCLK_MASK;
8303 val |= CPMU_LNK_AWARE_MACCLK_6_25;
8304 tw32(TG3_CPMU_LNK_AWARE_PWRMD, val);
8306 val = tr32(TG3_CPMU_HST_ACC);
8307 val &= ~CPMU_HST_ACC_MACCLK_MASK;
8308 val |= CPMU_HST_ACC_MACCLK_6_25;
8309 tw32(TG3_CPMU_HST_ACC, val);
8312 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
8313 val = tr32(PCIE_PWR_MGMT_THRESH) & ~PCIE_PWR_MGMT_L1_THRESH_MSK;
8314 val |= PCIE_PWR_MGMT_EXT_ASPM_TMR_EN |
8315 PCIE_PWR_MGMT_L1_THRESH_4MS;
8316 tw32(PCIE_PWR_MGMT_THRESH, val);
8318 val = tr32(TG3_PCIE_EIDLE_DELAY) & ~TG3_PCIE_EIDLE_DELAY_MASK;
8319 tw32(TG3_PCIE_EIDLE_DELAY, val | TG3_PCIE_EIDLE_DELAY_13_CLKS);
8321 tw32(TG3_CORR_ERR_STAT, TG3_CORR_ERR_STAT_CLEAR);
8323 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
8324 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
8327 if (tg3_flag(tp, L1PLLPD_EN)) {
8328 u32 grc_mode = tr32(GRC_MODE);
8330 /* Access the lower 1K of PL PCIE block registers. */
8331 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
8332 tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
8334 val = tr32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1);
8335 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1,
8336 val | TG3_PCIE_PL_LO_PHYCTL1_L1PLLPD_EN);
8338 tw32(GRC_MODE, grc_mode);
8341 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
8342 if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) {
8343 u32 grc_mode = tr32(GRC_MODE);
8345 /* Access the lower 1K of PL PCIE block registers. */
8346 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
8347 tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
8349 val = tr32(TG3_PCIE_TLDLPL_PORT +
8350 TG3_PCIE_PL_LO_PHYCTL5);
8351 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL5,
8352 val | TG3_PCIE_PL_LO_PHYCTL5_DIS_L2CLKREQ);
8354 tw32(GRC_MODE, grc_mode);
8357 if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_57765_AX) {
8358 u32 grc_mode = tr32(GRC_MODE);
8360 /* Access the lower 1K of DL PCIE block registers. */
8361 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
8362 tw32(GRC_MODE, val | GRC_MODE_PCIE_DL_SEL);
8364 val = tr32(TG3_PCIE_TLDLPL_PORT +
8365 TG3_PCIE_DL_LO_FTSMAX);
8366 val &= ~TG3_PCIE_DL_LO_FTSMAX_MSK;
8367 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_DL_LO_FTSMAX,
8368 val | TG3_PCIE_DL_LO_FTSMAX_VAL);
8370 tw32(GRC_MODE, grc_mode);
8373 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
8374 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
8375 val |= CPMU_LSPD_10MB_MACCLK_6_25;
8376 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
8379 /* This works around an issue with Athlon chipsets on
8380 * B3 tigon3 silicon. This bit has no effect on any
8381 * other revision. But do not set this on PCI Express
8382 * chips and don't even touch the clocks if the CPMU is present.
8384 if (!tg3_flag(tp, CPMU_PRESENT)) {
8385 if (!tg3_flag(tp, PCI_EXPRESS))
8386 tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
8387 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
8390 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
8391 tg3_flag(tp, PCIX_MODE)) {
8392 val = tr32(TG3PCI_PCISTATE);
8393 val |= PCISTATE_RETRY_SAME_DMA;
8394 tw32(TG3PCI_PCISTATE, val);
8397 if (tg3_flag(tp, ENABLE_APE)) {
8398 /* Allow reads and writes to the
8399 * APE register and memory space.
8401 val = tr32(TG3PCI_PCISTATE);
8402 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
8403 PCISTATE_ALLOW_APE_SHMEM_WR |
8404 PCISTATE_ALLOW_APE_PSPACE_WR;
8405 tw32(TG3PCI_PCISTATE, val);
8408 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) {
8409 /* Enable some hw fixes. */
8410 val = tr32(TG3PCI_MSI_DATA);
8411 val |= (1 << 26) | (1 << 28) | (1 << 29);
8412 tw32(TG3PCI_MSI_DATA, val);
8415 /* Descriptor ring init may make accesses to the
8416 * NIC SRAM area to setup the TX descriptors, so we
8417 * can only do this after the hardware has been
8418 * successfully reset.
8420 err = tg3_init_rings(tp);
8424 if (tg3_flag(tp, 57765_PLUS)) {
8425 val = tr32(TG3PCI_DMA_RW_CTRL) &
8426 ~DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
8427 if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0)
8428 val &= ~DMA_RWCTRL_CRDRDR_RDMA_MRRS_MSK;
8429 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57765 &&
8430 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717)
8431 val |= DMA_RWCTRL_TAGGED_STAT_WA;
8432 tw32(TG3PCI_DMA_RW_CTRL, val | tp->dma_rwctrl);
8433 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 &&
8434 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761) {
8435 /* This value is determined during the probe time DMA
8436 * engine test, tg3_test_dma.
8438 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
8441 tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
8442 GRC_MODE_4X_NIC_SEND_RINGS |
8443 GRC_MODE_NO_TX_PHDR_CSUM |
8444 GRC_MODE_NO_RX_PHDR_CSUM);
8445 tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
8447 /* Pseudo-header checksum is done by hardware logic and not
8448 * the offload processers, so make the chip do the pseudo-
8449 * header checksums on receive. For transmit it is more
8450 * convenient to do the pseudo-header checksum in software
8451 * as Linux does that on transmit for us in all cases.
8453 tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
8457 (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
8459 /* Setup the timer prescalar register. Clock is always 66Mhz. */
8460 val = tr32(GRC_MISC_CFG);
8462 val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
8463 tw32(GRC_MISC_CFG, val);
8465 /* Initialize MBUF/DESC pool. */
8466 if (tg3_flag(tp, 5750_PLUS)) {
8468 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
8469 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
8470 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
8471 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
8473 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
8474 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
8475 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
8476 } else if (tg3_flag(tp, TSO_CAPABLE)) {
8479 fw_len = tp->fw_len;
8480 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
8481 tw32(BUFMGR_MB_POOL_ADDR,
8482 NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
8483 tw32(BUFMGR_MB_POOL_SIZE,
8484 NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
8487 if (tp->dev->mtu <= ETH_DATA_LEN) {
8488 tw32(BUFMGR_MB_RDMA_LOW_WATER,
8489 tp->bufmgr_config.mbuf_read_dma_low_water);
8490 tw32(BUFMGR_MB_MACRX_LOW_WATER,
8491 tp->bufmgr_config.mbuf_mac_rx_low_water);
8492 tw32(BUFMGR_MB_HIGH_WATER,
8493 tp->bufmgr_config.mbuf_high_water);
8495 tw32(BUFMGR_MB_RDMA_LOW_WATER,
8496 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
8497 tw32(BUFMGR_MB_MACRX_LOW_WATER,
8498 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
8499 tw32(BUFMGR_MB_HIGH_WATER,
8500 tp->bufmgr_config.mbuf_high_water_jumbo);
8502 tw32(BUFMGR_DMA_LOW_WATER,
8503 tp->bufmgr_config.dma_low_water);
8504 tw32(BUFMGR_DMA_HIGH_WATER,
8505 tp->bufmgr_config.dma_high_water);
8507 val = BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE;
8508 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
8509 val |= BUFMGR_MODE_NO_TX_UNDERRUN;
8510 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
8511 tp->pci_chip_rev_id == CHIPREV_ID_5719_A0 ||
8512 tp->pci_chip_rev_id == CHIPREV_ID_5720_A0)
8513 val |= BUFMGR_MODE_MBLOW_ATTN_ENAB;
8514 tw32(BUFMGR_MODE, val);
8515 for (i = 0; i < 2000; i++) {
8516 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
8521 netdev_err(tp->dev, "%s cannot enable BUFMGR\n", __func__);
8525 if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1)
8526 tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
8528 tg3_setup_rxbd_thresholds(tp);
8530 /* Initialize TG3_BDINFO's at:
8531 * RCVDBDI_STD_BD: standard eth size rx ring
8532 * RCVDBDI_JUMBO_BD: jumbo frame rx ring
8533 * RCVDBDI_MINI_BD: small frame rx ring (??? does not work)
8536 * TG3_BDINFO_HOST_ADDR: high/low parts of DMA address of ring
8537 * TG3_BDINFO_MAXLEN_FLAGS: (rx max buffer size << 16) |
8538 * ring attribute flags
8539 * TG3_BDINFO_NIC_ADDR: location of descriptors in nic SRAM
8541 * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
8542 * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
8544 * The size of each ring is fixed in the firmware, but the location is
8547 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
8548 ((u64) tpr->rx_std_mapping >> 32));
8549 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
8550 ((u64) tpr->rx_std_mapping & 0xffffffff));
8551 if (!tg3_flag(tp, 5717_PLUS))
8552 tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
8553 NIC_SRAM_RX_BUFFER_DESC);
8555 /* Disable the mini ring */
8556 if (!tg3_flag(tp, 5705_PLUS))
8557 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
8558 BDINFO_FLAGS_DISABLED);
8560 /* Program the jumbo buffer descriptor ring control
8561 * blocks on those devices that have them.
8563 if (tp->pci_chip_rev_id == CHIPREV_ID_5719_A0 ||
8564 (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS))) {
8566 if (tg3_flag(tp, JUMBO_RING_ENABLE)) {
8567 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
8568 ((u64) tpr->rx_jmb_mapping >> 32));
8569 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
8570 ((u64) tpr->rx_jmb_mapping & 0xffffffff));
8571 val = TG3_RX_JMB_RING_SIZE(tp) <<
8572 BDINFO_FLAGS_MAXLEN_SHIFT;
8573 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
8574 val | BDINFO_FLAGS_USE_EXT_RECV);
8575 if (!tg3_flag(tp, USE_JUMBO_BDFLAG) ||
8576 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
8577 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
8578 NIC_SRAM_RX_JUMBO_BUFFER_DESC);
8580 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
8581 BDINFO_FLAGS_DISABLED);
8584 if (tg3_flag(tp, 57765_PLUS)) {
8585 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
8586 val = TG3_RX_STD_MAX_SIZE_5700;
8588 val = TG3_RX_STD_MAX_SIZE_5717;
8589 val <<= BDINFO_FLAGS_MAXLEN_SHIFT;
8590 val |= (TG3_RX_STD_DMA_SZ << 2);
8592 val = TG3_RX_STD_DMA_SZ << BDINFO_FLAGS_MAXLEN_SHIFT;
8594 val = TG3_RX_STD_MAX_SIZE_5700 << BDINFO_FLAGS_MAXLEN_SHIFT;
8596 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS, val);
8598 tpr->rx_std_prod_idx = tp->rx_pending;
8599 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, tpr->rx_std_prod_idx);
8601 tpr->rx_jmb_prod_idx =
8602 tg3_flag(tp, JUMBO_RING_ENABLE) ? tp->rx_jumbo_pending : 0;
8603 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG, tpr->rx_jmb_prod_idx);
8605 tg3_rings_reset(tp);
8607 /* Initialize MAC address and backoff seed. */
8608 __tg3_set_mac_addr(tp, 0);
8610 /* MTU + ethernet header + FCS + optional VLAN tag */
8611 tw32(MAC_RX_MTU_SIZE,
8612 tp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN);
8614 /* The slot time is changed by tg3_setup_phy if we
8615 * run at gigabit with half duplex.
8617 val = (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
8618 (6 << TX_LENGTHS_IPG_SHIFT) |
8619 (32 << TX_LENGTHS_SLOT_TIME_SHIFT);
8621 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720)
8622 val |= tr32(MAC_TX_LENGTHS) &
8623 (TX_LENGTHS_JMB_FRM_LEN_MSK |
8624 TX_LENGTHS_CNT_DWN_VAL_MSK);
8626 tw32(MAC_TX_LENGTHS, val);
8628 /* Receive rules. */
8629 tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
8630 tw32(RCVLPC_CONFIG, 0x0181);
8632 /* Calculate RDMAC_MODE setting early, we need it to determine
8633 * the RCVLPC_STATE_ENABLE mask.
8635 rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
8636 RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
8637 RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
8638 RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
8639 RDMAC_MODE_LNGREAD_ENAB);
8641 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
8642 rdmac_mode |= RDMAC_MODE_MULT_DMA_RD_DIS;
8644 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
8645 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
8646 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
8647 rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB |
8648 RDMAC_MODE_MBUF_RBD_CRPT_ENAB |
8649 RDMAC_MODE_MBUF_SBD_CRPT_ENAB;
8651 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
8652 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) {
8653 if (tg3_flag(tp, TSO_CAPABLE) &&
8654 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
8655 rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
8656 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
8657 !tg3_flag(tp, IS_5788)) {
8658 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
8662 if (tg3_flag(tp, PCI_EXPRESS))
8663 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
8665 if (tg3_flag(tp, HW_TSO_1) ||
8666 tg3_flag(tp, HW_TSO_2) ||
8667 tg3_flag(tp, HW_TSO_3))
8668 rdmac_mode |= RDMAC_MODE_IPV4_LSO_EN;
8670 if (tg3_flag(tp, 57765_PLUS) ||
8671 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
8672 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
8673 rdmac_mode |= RDMAC_MODE_IPV6_LSO_EN;
8675 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720)
8676 rdmac_mode |= tr32(RDMAC_MODE) & RDMAC_MODE_H2BNC_VLAN_DET;
8678 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
8679 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
8680 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
8681 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
8682 tg3_flag(tp, 57765_PLUS)) {
8683 val = tr32(TG3_RDMA_RSRVCTRL_REG);
8684 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
8685 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) {
8686 val &= ~(TG3_RDMA_RSRVCTRL_TXMRGN_MASK |
8687 TG3_RDMA_RSRVCTRL_FIFO_LWM_MASK |
8688 TG3_RDMA_RSRVCTRL_FIFO_HWM_MASK);
8689 val |= TG3_RDMA_RSRVCTRL_TXMRGN_320B |
8690 TG3_RDMA_RSRVCTRL_FIFO_LWM_1_5K |
8691 TG3_RDMA_RSRVCTRL_FIFO_HWM_1_5K;
8693 tw32(TG3_RDMA_RSRVCTRL_REG,
8694 val | TG3_RDMA_RSRVCTRL_FIFO_OFLW_FIX);
8697 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
8698 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) {
8699 val = tr32(TG3_LSO_RD_DMA_CRPTEN_CTRL);
8700 tw32(TG3_LSO_RD_DMA_CRPTEN_CTRL, val |
8701 TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_BD_4K |
8702 TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_LSO_4K);
8705 /* Receive/send statistics. */
8706 if (tg3_flag(tp, 5750_PLUS)) {
8707 val = tr32(RCVLPC_STATS_ENABLE);
8708 val &= ~RCVLPC_STATSENAB_DACK_FIX;
8709 tw32(RCVLPC_STATS_ENABLE, val);
8710 } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
8711 tg3_flag(tp, TSO_CAPABLE)) {
8712 val = tr32(RCVLPC_STATS_ENABLE);
8713 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
8714 tw32(RCVLPC_STATS_ENABLE, val);
8716 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
8718 tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
8719 tw32(SNDDATAI_STATSENAB, 0xffffff);
8720 tw32(SNDDATAI_STATSCTRL,
8721 (SNDDATAI_SCTRL_ENABLE |
8722 SNDDATAI_SCTRL_FASTUPD));
8724 /* Setup host coalescing engine. */
8725 tw32(HOSTCC_MODE, 0);
8726 for (i = 0; i < 2000; i++) {
8727 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
8732 __tg3_set_coalesce(tp, &tp->coal);
8734 if (!tg3_flag(tp, 5705_PLUS)) {
8735 /* Status/statistics block address. See tg3_timer,
8736 * the tg3_periodic_fetch_stats call there, and
8737 * tg3_get_stats to see how this works for 5705/5750 chips.
8739 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
8740 ((u64) tp->stats_mapping >> 32));
8741 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
8742 ((u64) tp->stats_mapping & 0xffffffff));
8743 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
8745 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
8747 /* Clear statistics and status block memory areas */
8748 for (i = NIC_SRAM_STATS_BLK;
8749 i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
8751 tg3_write_mem(tp, i, 0);
8756 tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
8758 tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
8759 tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
8760 if (!tg3_flag(tp, 5705_PLUS))
8761 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
8763 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) {
8764 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
8765 /* reset to prevent losing 1st rx packet intermittently */
8766 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
8770 tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
8771 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE |
8772 MAC_MODE_FHDE_ENABLE;
8773 if (tg3_flag(tp, ENABLE_APE))
8774 tp->mac_mode |= MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
8775 if (!tg3_flag(tp, 5705_PLUS) &&
8776 !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
8777 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)
8778 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
8779 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
8782 /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
8783 * If TG3_FLAG_IS_NIC is zero, we should read the
8784 * register to preserve the GPIO settings for LOMs. The GPIOs,
8785 * whether used as inputs or outputs, are set by boot code after
8788 if (!tg3_flag(tp, IS_NIC)) {
8791 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
8792 GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
8793 GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
8795 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
8796 gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
8797 GRC_LCLCTRL_GPIO_OUTPUT3;
8799 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
8800 gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
8802 tp->grc_local_ctrl &= ~gpio_mask;
8803 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
8805 /* GPIO1 must be driven high for eeprom write protect */
8806 if (tg3_flag(tp, EEPROM_WRITE_PROT))
8807 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
8808 GRC_LCLCTRL_GPIO_OUTPUT1);
8810 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
8813 if (tg3_flag(tp, USING_MSIX) && tp->irq_cnt > 1) {
8814 val = tr32(MSGINT_MODE);
8815 val |= MSGINT_MODE_MULTIVEC_EN | MSGINT_MODE_ENABLE;
8816 if (!tg3_flag(tp, 1SHOT_MSI))
8817 val |= MSGINT_MODE_ONE_SHOT_DISABLE;
8818 tw32(MSGINT_MODE, val);
8821 if (!tg3_flag(tp, 5705_PLUS)) {
8822 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
8826 val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
8827 WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
8828 WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
8829 WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
8830 WDMAC_MODE_LNGREAD_ENAB);
8832 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
8833 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) {
8834 if (tg3_flag(tp, TSO_CAPABLE) &&
8835 (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
8836 tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
8838 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
8839 !tg3_flag(tp, IS_5788)) {
8840 val |= WDMAC_MODE_RX_ACCEL;
8844 /* Enable host coalescing bug fix */
8845 if (tg3_flag(tp, 5755_PLUS))
8846 val |= WDMAC_MODE_STATUS_TAG_FIX;
8848 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
8849 val |= WDMAC_MODE_BURST_ALL_DATA;
8851 tw32_f(WDMAC_MODE, val);
8854 if (tg3_flag(tp, PCIX_MODE)) {
8857 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
8859 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
8860 pcix_cmd &= ~PCI_X_CMD_MAX_READ;
8861 pcix_cmd |= PCI_X_CMD_READ_2K;
8862 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
8863 pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ);
8864 pcix_cmd |= PCI_X_CMD_READ_2K;
8866 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
8870 tw32_f(RDMAC_MODE, rdmac_mode);
8873 tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
8874 if (!tg3_flag(tp, 5705_PLUS))
8875 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
8877 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
8879 SNDDATAC_MODE_ENABLE | SNDDATAC_MODE_CDELAY);
8881 tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
8883 tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
8884 tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
8885 val = RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ;
8886 if (tg3_flag(tp, LRG_PROD_RING_CAP))
8887 val |= RCVDBDI_MODE_LRG_RING_SZ;
8888 tw32(RCVDBDI_MODE, val);
8889 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
8890 if (tg3_flag(tp, HW_TSO_1) ||
8891 tg3_flag(tp, HW_TSO_2) ||
8892 tg3_flag(tp, HW_TSO_3))
8893 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
8894 val = SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE;
8895 if (tg3_flag(tp, ENABLE_TSS))
8896 val |= SNDBDI_MODE_MULTI_TXQ_EN;
8897 tw32(SNDBDI_MODE, val);
8898 tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
8900 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
8901 err = tg3_load_5701_a0_firmware_fix(tp);
8906 if (tg3_flag(tp, TSO_CAPABLE)) {
8907 err = tg3_load_tso_firmware(tp);
8912 tp->tx_mode = TX_MODE_ENABLE;
8914 if (tg3_flag(tp, 5755_PLUS) ||
8915 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
8916 tp->tx_mode |= TX_MODE_MBUF_LOCKUP_FIX;
8918 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) {
8919 val = TX_MODE_JMB_FRM_LEN | TX_MODE_CNT_DN_MODE;
8920 tp->tx_mode &= ~val;
8921 tp->tx_mode |= tr32(MAC_TX_MODE) & val;
8924 tw32_f(MAC_TX_MODE, tp->tx_mode);
8927 if (tg3_flag(tp, ENABLE_RSS)) {
8929 u32 reg = MAC_RSS_INDIR_TBL_0;
8931 if (tp->irq_cnt == 2) {
8932 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i += 8) {
8939 while (i < TG3_RSS_INDIR_TBL_SIZE) {
8940 val = i % (tp->irq_cnt - 1);
8942 for (; i % 8; i++) {
8944 val |= (i % (tp->irq_cnt - 1));
8951 /* Setup the "secret" hash key. */
8952 tw32(MAC_RSS_HASH_KEY_0, 0x5f865437);
8953 tw32(MAC_RSS_HASH_KEY_1, 0xe4ac62cc);
8954 tw32(MAC_RSS_HASH_KEY_2, 0x50103a45);
8955 tw32(MAC_RSS_HASH_KEY_3, 0x36621985);
8956 tw32(MAC_RSS_HASH_KEY_4, 0xbf14c0e8);
8957 tw32(MAC_RSS_HASH_KEY_5, 0x1bc27a1e);
8958 tw32(MAC_RSS_HASH_KEY_6, 0x84f4b556);
8959 tw32(MAC_RSS_HASH_KEY_7, 0x094ea6fe);
8960 tw32(MAC_RSS_HASH_KEY_8, 0x7dda01e7);
8961 tw32(MAC_RSS_HASH_KEY_9, 0xc04d7481);
8964 tp->rx_mode = RX_MODE_ENABLE;
8965 if (tg3_flag(tp, 5755_PLUS))
8966 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
8968 if (tg3_flag(tp, ENABLE_RSS))
8969 tp->rx_mode |= RX_MODE_RSS_ENABLE |
8970 RX_MODE_RSS_ITBL_HASH_BITS_7 |
8971 RX_MODE_RSS_IPV6_HASH_EN |
8972 RX_MODE_RSS_TCP_IPV6_HASH_EN |
8973 RX_MODE_RSS_IPV4_HASH_EN |
8974 RX_MODE_RSS_TCP_IPV4_HASH_EN;
8976 tw32_f(MAC_RX_MODE, tp->rx_mode);
8979 tw32(MAC_LED_CTRL, tp->led_ctrl);
8981 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
8982 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
8983 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
8986 tw32_f(MAC_RX_MODE, tp->rx_mode);
8989 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
8990 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
8991 !(tp->phy_flags & TG3_PHYFLG_SERDES_PREEMPHASIS)) {
8992 /* Set drive transmission level to 1.2V */
8993 /* only if the signal pre-emphasis bit is not set */
8994 val = tr32(MAC_SERDES_CFG);
8997 tw32(MAC_SERDES_CFG, val);
8999 if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
9000 tw32(MAC_SERDES_CFG, 0x616000);
9003 /* Prevent chip from dropping frames when flow control
9006 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
9010 tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, val);
9012 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
9013 (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
9014 /* Use hardware link auto-negotiation */
9015 tg3_flag_set(tp, HW_AUTONEG);
9018 if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
9019 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
9022 tmp = tr32(SERDES_RX_CTRL);
9023 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
9024 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
9025 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
9026 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
9029 if (!tg3_flag(tp, USE_PHYLIB)) {
9030 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
9031 tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER;
9032 tp->link_config.speed = tp->link_config.orig_speed;
9033 tp->link_config.duplex = tp->link_config.orig_duplex;
9034 tp->link_config.autoneg = tp->link_config.orig_autoneg;
9037 err = tg3_setup_phy(tp, 0);
9041 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
9042 !(tp->phy_flags & TG3_PHYFLG_IS_FET)) {
9045 /* Clear CRC stats. */
9046 if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
9047 tg3_writephy(tp, MII_TG3_TEST1,
9048 tmp | MII_TG3_TEST1_CRC_EN);
9049 tg3_readphy(tp, MII_TG3_RXR_COUNTERS, &tmp);
9054 __tg3_set_rx_mode(tp->dev);
9056 /* Initialize receive rules. */
9057 tw32(MAC_RCV_RULE_0, 0xc2000000 & RCV_RULE_DISABLE_MASK);
9058 tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
9059 tw32(MAC_RCV_RULE_1, 0x86000004 & RCV_RULE_DISABLE_MASK);
9060 tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
9062 if (tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, 5780_CLASS))
9066 if (tg3_flag(tp, ENABLE_ASF))
9070 tw32(MAC_RCV_RULE_15, 0); tw32(MAC_RCV_VALUE_15, 0);
9072 tw32(MAC_RCV_RULE_14, 0); tw32(MAC_RCV_VALUE_14, 0);
9074 tw32(MAC_RCV_RULE_13, 0); tw32(MAC_RCV_VALUE_13, 0);
9076 tw32(MAC_RCV_RULE_12, 0); tw32(MAC_RCV_VALUE_12, 0);
9078 tw32(MAC_RCV_RULE_11, 0); tw32(MAC_RCV_VALUE_11, 0);
9080 tw32(MAC_RCV_RULE_10, 0); tw32(MAC_RCV_VALUE_10, 0);
9082 tw32(MAC_RCV_RULE_9, 0); tw32(MAC_RCV_VALUE_9, 0);
9084 tw32(MAC_RCV_RULE_8, 0); tw32(MAC_RCV_VALUE_8, 0);
9086 tw32(MAC_RCV_RULE_7, 0); tw32(MAC_RCV_VALUE_7, 0);
9088 tw32(MAC_RCV_RULE_6, 0); tw32(MAC_RCV_VALUE_6, 0);
9090 tw32(MAC_RCV_RULE_5, 0); tw32(MAC_RCV_VALUE_5, 0);
9092 tw32(MAC_RCV_RULE_4, 0); tw32(MAC_RCV_VALUE_4, 0);
9094 /* tw32(MAC_RCV_RULE_3, 0); tw32(MAC_RCV_VALUE_3, 0); */
9096 /* tw32(MAC_RCV_RULE_2, 0); tw32(MAC_RCV_VALUE_2, 0); */
9104 if (tg3_flag(tp, ENABLE_APE))
9105 /* Write our heartbeat update interval to APE. */
9106 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS,
9107 APE_HOST_HEARTBEAT_INT_DISABLE);
9109 tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
9114 /* Called at device open time to get the chip ready for
9115 * packet processing. Invoked with tp->lock held.
9117 static int tg3_init_hw(struct tg3 *tp, int reset_phy)
9119 tg3_switch_clocks(tp);
9121 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
9123 return tg3_reset_hw(tp, reset_phy);
9126 #define TG3_STAT_ADD32(PSTAT, REG) \
9127 do { u32 __val = tr32(REG); \
9128 (PSTAT)->low += __val; \
9129 if ((PSTAT)->low < __val) \
9130 (PSTAT)->high += 1; \
9133 static void tg3_periodic_fetch_stats(struct tg3 *tp)
9135 struct tg3_hw_stats *sp = tp->hw_stats;
9137 if (!netif_carrier_ok(tp->dev))
9140 TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
9141 TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
9142 TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
9143 TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
9144 TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
9145 TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
9146 TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
9147 TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
9148 TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
9149 TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
9150 TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
9151 TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
9152 TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
9154 TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
9155 TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
9156 TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
9157 TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
9158 TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
9159 TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
9160 TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
9161 TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
9162 TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
9163 TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
9164 TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
9165 TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
9166 TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
9167 TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
9169 TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
9170 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
9171 tp->pci_chip_rev_id != CHIPREV_ID_5719_A0 &&
9172 tp->pci_chip_rev_id != CHIPREV_ID_5720_A0) {
9173 TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
9175 u32 val = tr32(HOSTCC_FLOW_ATTN);
9176 val = (val & HOSTCC_FLOW_ATTN_MBUF_LWM) ? 1 : 0;
9178 tw32(HOSTCC_FLOW_ATTN, HOSTCC_FLOW_ATTN_MBUF_LWM);
9179 sp->rx_discards.low += val;
9180 if (sp->rx_discards.low < val)
9181 sp->rx_discards.high += 1;
9183 sp->mbuf_lwm_thresh_hit = sp->rx_discards;
9185 TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
9188 static void tg3_chk_missed_msi(struct tg3 *tp)
9192 for (i = 0; i < tp->irq_cnt; i++) {
9193 struct tg3_napi *tnapi = &tp->napi[i];
9195 if (tg3_has_work(tnapi)) {
9196 if (tnapi->last_rx_cons == tnapi->rx_rcb_ptr &&
9197 tnapi->last_tx_cons == tnapi->tx_cons) {
9198 if (tnapi->chk_msi_cnt < 1) {
9199 tnapi->chk_msi_cnt++;
9205 tnapi->chk_msi_cnt = 0;
9206 tnapi->last_rx_cons = tnapi->rx_rcb_ptr;
9207 tnapi->last_tx_cons = tnapi->tx_cons;
9211 static void tg3_timer(unsigned long __opaque)
9213 struct tg3 *tp = (struct tg3 *) __opaque;
9215 if (tp->irq_sync || tg3_flag(tp, RESET_TASK_PENDING))
9218 spin_lock(&tp->lock);
9220 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
9221 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
9222 tg3_chk_missed_msi(tp);
9224 if (!tg3_flag(tp, TAGGED_STATUS)) {
9225 /* All of this garbage is because when using non-tagged
9226 * IRQ status the mailbox/status_block protocol the chip
9227 * uses with the cpu is race prone.
9229 if (tp->napi[0].hw_status->status & SD_STATUS_UPDATED) {
9230 tw32(GRC_LOCAL_CTRL,
9231 tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
9233 tw32(HOSTCC_MODE, tp->coalesce_mode |
9234 HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW);
9237 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
9238 spin_unlock(&tp->lock);
9239 tg3_reset_task_schedule(tp);
9244 /* This part only runs once per second. */
9245 if (!--tp->timer_counter) {
9246 if (tg3_flag(tp, 5705_PLUS))
9247 tg3_periodic_fetch_stats(tp);
9249 if (tp->setlpicnt && !--tp->setlpicnt)
9250 tg3_phy_eee_enable(tp);
9252 if (tg3_flag(tp, USE_LINKCHG_REG)) {
9256 mac_stat = tr32(MAC_STATUS);
9259 if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) {
9260 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
9262 } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
9266 tg3_setup_phy(tp, 0);
9267 } else if (tg3_flag(tp, POLL_SERDES)) {
9268 u32 mac_stat = tr32(MAC_STATUS);
9271 if (netif_carrier_ok(tp->dev) &&
9272 (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
9275 if (!netif_carrier_ok(tp->dev) &&
9276 (mac_stat & (MAC_STATUS_PCS_SYNCED |
9277 MAC_STATUS_SIGNAL_DET))) {
9281 if (!tp->serdes_counter) {
9284 ~MAC_MODE_PORT_MODE_MASK));
9286 tw32_f(MAC_MODE, tp->mac_mode);
9289 tg3_setup_phy(tp, 0);
9291 } else if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
9292 tg3_flag(tp, 5780_CLASS)) {
9293 tg3_serdes_parallel_detect(tp);
9296 tp->timer_counter = tp->timer_multiplier;
9299 /* Heartbeat is only sent once every 2 seconds.
9301 * The heartbeat is to tell the ASF firmware that the host
9302 * driver is still alive. In the event that the OS crashes,
9303 * ASF needs to reset the hardware to free up the FIFO space
9304 * that may be filled with rx packets destined for the host.
9305 * If the FIFO is full, ASF will no longer function properly.
9307 * Unintended resets have been reported on real time kernels
9308 * where the timer doesn't run on time. Netpoll will also have
9311 * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
9312 * to check the ring condition when the heartbeat is expiring
9313 * before doing the reset. This will prevent most unintended
9316 if (!--tp->asf_counter) {
9317 if (tg3_flag(tp, ENABLE_ASF) && !tg3_flag(tp, ENABLE_APE)) {
9318 tg3_wait_for_event_ack(tp);
9320 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
9321 FWCMD_NICDRV_ALIVE3);
9322 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
9323 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX,
9324 TG3_FW_UPDATE_TIMEOUT_SEC);
9326 tg3_generate_fw_event(tp);
9328 tp->asf_counter = tp->asf_multiplier;
9331 spin_unlock(&tp->lock);
9334 tp->timer.expires = jiffies + tp->timer_offset;
9335 add_timer(&tp->timer);
9338 static int tg3_request_irq(struct tg3 *tp, int irq_num)
9341 unsigned long flags;
9343 struct tg3_napi *tnapi = &tp->napi[irq_num];
9345 if (tp->irq_cnt == 1)
9346 name = tp->dev->name;
9348 name = &tnapi->irq_lbl[0];
9349 snprintf(name, IFNAMSIZ, "%s-%d", tp->dev->name, irq_num);
9350 name[IFNAMSIZ-1] = 0;
9353 if (tg3_flag(tp, USING_MSI) || tg3_flag(tp, USING_MSIX)) {
9355 if (tg3_flag(tp, 1SHOT_MSI))
9360 if (tg3_flag(tp, TAGGED_STATUS))
9361 fn = tg3_interrupt_tagged;
9362 flags = IRQF_SHARED;
9365 return request_irq(tnapi->irq_vec, fn, flags, name, tnapi);
9368 static int tg3_test_interrupt(struct tg3 *tp)
9370 struct tg3_napi *tnapi = &tp->napi[0];
9371 struct net_device *dev = tp->dev;
9372 int err, i, intr_ok = 0;
9375 if (!netif_running(dev))
9378 tg3_disable_ints(tp);
9380 free_irq(tnapi->irq_vec, tnapi);
9383 * Turn off MSI one shot mode. Otherwise this test has no
9384 * observable way to know whether the interrupt was delivered.
9386 if (tg3_flag(tp, 57765_PLUS)) {
9387 val = tr32(MSGINT_MODE) | MSGINT_MODE_ONE_SHOT_DISABLE;
9388 tw32(MSGINT_MODE, val);
9391 err = request_irq(tnapi->irq_vec, tg3_test_isr,
9392 IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, tnapi);
9396 tnapi->hw_status->status &= ~SD_STATUS_UPDATED;
9397 tg3_enable_ints(tp);
9399 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
9402 for (i = 0; i < 5; i++) {
9403 u32 int_mbox, misc_host_ctrl;
9405 int_mbox = tr32_mailbox(tnapi->int_mbox);
9406 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
9408 if ((int_mbox != 0) ||
9409 (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
9414 if (tg3_flag(tp, 57765_PLUS) &&
9415 tnapi->hw_status->status_tag != tnapi->last_tag)
9416 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
9421 tg3_disable_ints(tp);
9423 free_irq(tnapi->irq_vec, tnapi);
9425 err = tg3_request_irq(tp, 0);
9431 /* Reenable MSI one shot mode. */
9432 if (tg3_flag(tp, 57765_PLUS) && tg3_flag(tp, 1SHOT_MSI)) {
9433 val = tr32(MSGINT_MODE) & ~MSGINT_MODE_ONE_SHOT_DISABLE;
9434 tw32(MSGINT_MODE, val);
9442 /* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
9443 * successfully restored
9445 static int tg3_test_msi(struct tg3 *tp)
9450 if (!tg3_flag(tp, USING_MSI))
9453 /* Turn off SERR reporting in case MSI terminates with Master
9456 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
9457 pci_write_config_word(tp->pdev, PCI_COMMAND,
9458 pci_cmd & ~PCI_COMMAND_SERR);
9460 err = tg3_test_interrupt(tp);
9462 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
9467 /* other failures */
9471 /* MSI test failed, go back to INTx mode */
9472 netdev_warn(tp->dev, "No interrupt was generated using MSI. Switching "
9473 "to INTx mode. Please report this failure to the PCI "
9474 "maintainer and include system chipset information\n");
9476 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
9478 pci_disable_msi(tp->pdev);
9480 tg3_flag_clear(tp, USING_MSI);
9481 tp->napi[0].irq_vec = tp->pdev->irq;
9483 err = tg3_request_irq(tp, 0);
9487 /* Need to reset the chip because the MSI cycle may have terminated
9488 * with Master Abort.
9490 tg3_full_lock(tp, 1);
9492 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9493 err = tg3_init_hw(tp, 1);
9495 tg3_full_unlock(tp);
9498 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
9503 static int tg3_request_firmware(struct tg3 *tp)
9505 const __be32 *fw_data;
9507 if (request_firmware(&tp->fw, tp->fw_needed, &tp->pdev->dev)) {
9508 netdev_err(tp->dev, "Failed to load firmware \"%s\"\n",
9513 fw_data = (void *)tp->fw->data;
9515 /* Firmware blob starts with version numbers, followed by
9516 * start address and _full_ length including BSS sections
9517 * (which must be longer than the actual data, of course
9520 tp->fw_len = be32_to_cpu(fw_data[2]); /* includes bss */
9521 if (tp->fw_len < (tp->fw->size - 12)) {
9522 netdev_err(tp->dev, "bogus length %d in \"%s\"\n",
9523 tp->fw_len, tp->fw_needed);
9524 release_firmware(tp->fw);
9529 /* We no longer need firmware; we have it. */
9530 tp->fw_needed = NULL;
9534 static bool tg3_enable_msix(struct tg3 *tp)
9536 int i, rc, cpus = num_online_cpus();
9537 struct msix_entry msix_ent[tp->irq_max];
9540 /* Just fallback to the simpler MSI mode. */
9544 * We want as many rx rings enabled as there are cpus.
9545 * The first MSIX vector only deals with link interrupts, etc,
9546 * so we add one to the number of vectors we are requesting.
9548 tp->irq_cnt = min_t(unsigned, cpus + 1, tp->irq_max);
9550 for (i = 0; i < tp->irq_max; i++) {
9551 msix_ent[i].entry = i;
9552 msix_ent[i].vector = 0;
9555 rc = pci_enable_msix(tp->pdev, msix_ent, tp->irq_cnt);
9558 } else if (rc != 0) {
9559 if (pci_enable_msix(tp->pdev, msix_ent, rc))
9561 netdev_notice(tp->dev, "Requested %d MSI-X vectors, received %d\n",
9566 for (i = 0; i < tp->irq_max; i++)
9567 tp->napi[i].irq_vec = msix_ent[i].vector;
9569 netif_set_real_num_tx_queues(tp->dev, 1);
9570 rc = tp->irq_cnt > 1 ? tp->irq_cnt - 1 : 1;
9571 if (netif_set_real_num_rx_queues(tp->dev, rc)) {
9572 pci_disable_msix(tp->pdev);
9576 if (tp->irq_cnt > 1) {
9577 tg3_flag_set(tp, ENABLE_RSS);
9579 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
9580 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) {
9581 tg3_flag_set(tp, ENABLE_TSS);
9582 netif_set_real_num_tx_queues(tp->dev, tp->irq_cnt - 1);
9589 static void tg3_ints_init(struct tg3 *tp)
9591 if ((tg3_flag(tp, SUPPORT_MSI) || tg3_flag(tp, SUPPORT_MSIX)) &&
9592 !tg3_flag(tp, TAGGED_STATUS)) {
9593 /* All MSI supporting chips should support tagged
9594 * status. Assert that this is the case.
9596 netdev_warn(tp->dev,
9597 "MSI without TAGGED_STATUS? Not using MSI\n");
9601 if (tg3_flag(tp, SUPPORT_MSIX) && tg3_enable_msix(tp))
9602 tg3_flag_set(tp, USING_MSIX);
9603 else if (tg3_flag(tp, SUPPORT_MSI) && pci_enable_msi(tp->pdev) == 0)
9604 tg3_flag_set(tp, USING_MSI);
9606 if (tg3_flag(tp, USING_MSI) || tg3_flag(tp, USING_MSIX)) {
9607 u32 msi_mode = tr32(MSGINT_MODE);
9608 if (tg3_flag(tp, USING_MSIX) && tp->irq_cnt > 1)
9609 msi_mode |= MSGINT_MODE_MULTIVEC_EN;
9610 if (!tg3_flag(tp, 1SHOT_MSI))
9611 msi_mode |= MSGINT_MODE_ONE_SHOT_DISABLE;
9612 tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
9615 if (!tg3_flag(tp, USING_MSIX)) {
9617 tp->napi[0].irq_vec = tp->pdev->irq;
9618 netif_set_real_num_tx_queues(tp->dev, 1);
9619 netif_set_real_num_rx_queues(tp->dev, 1);
9623 static void tg3_ints_fini(struct tg3 *tp)
9625 if (tg3_flag(tp, USING_MSIX))
9626 pci_disable_msix(tp->pdev);
9627 else if (tg3_flag(tp, USING_MSI))
9628 pci_disable_msi(tp->pdev);
9629 tg3_flag_clear(tp, USING_MSI);
9630 tg3_flag_clear(tp, USING_MSIX);
9631 tg3_flag_clear(tp, ENABLE_RSS);
9632 tg3_flag_clear(tp, ENABLE_TSS);
9635 static int tg3_open(struct net_device *dev)
9637 struct tg3 *tp = netdev_priv(dev);
9640 if (tp->fw_needed) {
9641 err = tg3_request_firmware(tp);
9642 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
9646 netdev_warn(tp->dev, "TSO capability disabled\n");
9647 tg3_flag_clear(tp, TSO_CAPABLE);
9648 } else if (!tg3_flag(tp, TSO_CAPABLE)) {
9649 netdev_notice(tp->dev, "TSO capability restored\n");
9650 tg3_flag_set(tp, TSO_CAPABLE);
9654 netif_carrier_off(tp->dev);
9656 err = tg3_power_up(tp);
9660 tg3_full_lock(tp, 0);
9662 tg3_disable_ints(tp);
9663 tg3_flag_clear(tp, INIT_COMPLETE);
9665 tg3_full_unlock(tp);
9668 * Setup interrupts first so we know how
9669 * many NAPI resources to allocate
9673 /* The placement of this call is tied
9674 * to the setup and use of Host TX descriptors.
9676 err = tg3_alloc_consistent(tp);
9682 tg3_napi_enable(tp);
9684 for (i = 0; i < tp->irq_cnt; i++) {
9685 struct tg3_napi *tnapi = &tp->napi[i];
9686 err = tg3_request_irq(tp, i);
9688 for (i--; i >= 0; i--) {
9689 tnapi = &tp->napi[i];
9690 free_irq(tnapi->irq_vec, tnapi);
9696 tg3_full_lock(tp, 0);
9698 err = tg3_init_hw(tp, 1);
9700 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9703 if (tg3_flag(tp, TAGGED_STATUS) &&
9704 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
9705 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57765)
9706 tp->timer_offset = HZ;
9708 tp->timer_offset = HZ / 10;
9710 BUG_ON(tp->timer_offset > HZ);
9711 tp->timer_counter = tp->timer_multiplier =
9712 (HZ / tp->timer_offset);
9713 tp->asf_counter = tp->asf_multiplier =
9714 ((HZ / tp->timer_offset) * 2);
9716 init_timer(&tp->timer);
9717 tp->timer.expires = jiffies + tp->timer_offset;
9718 tp->timer.data = (unsigned long) tp;
9719 tp->timer.function = tg3_timer;
9722 tg3_full_unlock(tp);
9727 if (tg3_flag(tp, USING_MSI)) {
9728 err = tg3_test_msi(tp);
9731 tg3_full_lock(tp, 0);
9732 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9734 tg3_full_unlock(tp);
9739 if (!tg3_flag(tp, 57765_PLUS) && tg3_flag(tp, USING_MSI)) {
9740 u32 val = tr32(PCIE_TRANSACTION_CFG);
9742 tw32(PCIE_TRANSACTION_CFG,
9743 val | PCIE_TRANS_CFG_1SHOT_MSI);
9749 tg3_full_lock(tp, 0);
9751 add_timer(&tp->timer);
9752 tg3_flag_set(tp, INIT_COMPLETE);
9753 tg3_enable_ints(tp);
9755 tg3_full_unlock(tp);
9757 netif_tx_start_all_queues(dev);
9760 * Reset loopback feature if it was turned on while the device was down
9761 * make sure that it's installed properly now.
9763 if (dev->features & NETIF_F_LOOPBACK)
9764 tg3_set_loopback(dev, dev->features);
9769 for (i = tp->irq_cnt - 1; i >= 0; i--) {
9770 struct tg3_napi *tnapi = &tp->napi[i];
9771 free_irq(tnapi->irq_vec, tnapi);
9775 tg3_napi_disable(tp);
9777 tg3_free_consistent(tp);
9781 tg3_frob_aux_power(tp, false);
9782 pci_set_power_state(tp->pdev, PCI_D3hot);
9786 static struct rtnl_link_stats64 *tg3_get_stats64(struct net_device *,
9787 struct rtnl_link_stats64 *);
9788 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *);
9790 static int tg3_close(struct net_device *dev)
9793 struct tg3 *tp = netdev_priv(dev);
9795 tg3_napi_disable(tp);
9796 tg3_reset_task_cancel(tp);
9798 netif_tx_stop_all_queues(dev);
9800 del_timer_sync(&tp->timer);
9804 tg3_full_lock(tp, 1);
9806 tg3_disable_ints(tp);
9808 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9810 tg3_flag_clear(tp, INIT_COMPLETE);
9812 tg3_full_unlock(tp);
9814 for (i = tp->irq_cnt - 1; i >= 0; i--) {
9815 struct tg3_napi *tnapi = &tp->napi[i];
9816 free_irq(tnapi->irq_vec, tnapi);
9821 tg3_get_stats64(tp->dev, &tp->net_stats_prev);
9823 memcpy(&tp->estats_prev, tg3_get_estats(tp),
9824 sizeof(tp->estats_prev));
9828 tg3_free_consistent(tp);
9832 netif_carrier_off(tp->dev);
9837 static inline u64 get_stat64(tg3_stat64_t *val)
9839 return ((u64)val->high << 32) | ((u64)val->low);
9842 static u64 calc_crc_errors(struct tg3 *tp)
9844 struct tg3_hw_stats *hw_stats = tp->hw_stats;
9846 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
9847 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
9848 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
9851 spin_lock_bh(&tp->lock);
9852 if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
9853 tg3_writephy(tp, MII_TG3_TEST1,
9854 val | MII_TG3_TEST1_CRC_EN);
9855 tg3_readphy(tp, MII_TG3_RXR_COUNTERS, &val);
9858 spin_unlock_bh(&tp->lock);
9860 tp->phy_crc_errors += val;
9862 return tp->phy_crc_errors;
9865 return get_stat64(&hw_stats->rx_fcs_errors);
9868 #define ESTAT_ADD(member) \
9869 estats->member = old_estats->member + \
9870 get_stat64(&hw_stats->member)
9872 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp)
9874 struct tg3_ethtool_stats *estats = &tp->estats;
9875 struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
9876 struct tg3_hw_stats *hw_stats = tp->hw_stats;
9881 ESTAT_ADD(rx_octets);
9882 ESTAT_ADD(rx_fragments);
9883 ESTAT_ADD(rx_ucast_packets);
9884 ESTAT_ADD(rx_mcast_packets);
9885 ESTAT_ADD(rx_bcast_packets);
9886 ESTAT_ADD(rx_fcs_errors);
9887 ESTAT_ADD(rx_align_errors);
9888 ESTAT_ADD(rx_xon_pause_rcvd);
9889 ESTAT_ADD(rx_xoff_pause_rcvd);
9890 ESTAT_ADD(rx_mac_ctrl_rcvd);
9891 ESTAT_ADD(rx_xoff_entered);
9892 ESTAT_ADD(rx_frame_too_long_errors);
9893 ESTAT_ADD(rx_jabbers);
9894 ESTAT_ADD(rx_undersize_packets);
9895 ESTAT_ADD(rx_in_length_errors);
9896 ESTAT_ADD(rx_out_length_errors);
9897 ESTAT_ADD(rx_64_or_less_octet_packets);
9898 ESTAT_ADD(rx_65_to_127_octet_packets);
9899 ESTAT_ADD(rx_128_to_255_octet_packets);
9900 ESTAT_ADD(rx_256_to_511_octet_packets);
9901 ESTAT_ADD(rx_512_to_1023_octet_packets);
9902 ESTAT_ADD(rx_1024_to_1522_octet_packets);
9903 ESTAT_ADD(rx_1523_to_2047_octet_packets);
9904 ESTAT_ADD(rx_2048_to_4095_octet_packets);
9905 ESTAT_ADD(rx_4096_to_8191_octet_packets);
9906 ESTAT_ADD(rx_8192_to_9022_octet_packets);
9908 ESTAT_ADD(tx_octets);
9909 ESTAT_ADD(tx_collisions);
9910 ESTAT_ADD(tx_xon_sent);
9911 ESTAT_ADD(tx_xoff_sent);
9912 ESTAT_ADD(tx_flow_control);
9913 ESTAT_ADD(tx_mac_errors);
9914 ESTAT_ADD(tx_single_collisions);
9915 ESTAT_ADD(tx_mult_collisions);
9916 ESTAT_ADD(tx_deferred);
9917 ESTAT_ADD(tx_excessive_collisions);
9918 ESTAT_ADD(tx_late_collisions);
9919 ESTAT_ADD(tx_collide_2times);
9920 ESTAT_ADD(tx_collide_3times);
9921 ESTAT_ADD(tx_collide_4times);
9922 ESTAT_ADD(tx_collide_5times);
9923 ESTAT_ADD(tx_collide_6times);
9924 ESTAT_ADD(tx_collide_7times);
9925 ESTAT_ADD(tx_collide_8times);
9926 ESTAT_ADD(tx_collide_9times);
9927 ESTAT_ADD(tx_collide_10times);
9928 ESTAT_ADD(tx_collide_11times);
9929 ESTAT_ADD(tx_collide_12times);
9930 ESTAT_ADD(tx_collide_13times);
9931 ESTAT_ADD(tx_collide_14times);
9932 ESTAT_ADD(tx_collide_15times);
9933 ESTAT_ADD(tx_ucast_packets);
9934 ESTAT_ADD(tx_mcast_packets);
9935 ESTAT_ADD(tx_bcast_packets);
9936 ESTAT_ADD(tx_carrier_sense_errors);
9937 ESTAT_ADD(tx_discards);
9938 ESTAT_ADD(tx_errors);
9940 ESTAT_ADD(dma_writeq_full);
9941 ESTAT_ADD(dma_write_prioq_full);
9942 ESTAT_ADD(rxbds_empty);
9943 ESTAT_ADD(rx_discards);
9944 ESTAT_ADD(rx_errors);
9945 ESTAT_ADD(rx_threshold_hit);
9947 ESTAT_ADD(dma_readq_full);
9948 ESTAT_ADD(dma_read_prioq_full);
9949 ESTAT_ADD(tx_comp_queue_full);
9951 ESTAT_ADD(ring_set_send_prod_index);
9952 ESTAT_ADD(ring_status_update);
9953 ESTAT_ADD(nic_irqs);
9954 ESTAT_ADD(nic_avoided_irqs);
9955 ESTAT_ADD(nic_tx_threshold_hit);
9957 ESTAT_ADD(mbuf_lwm_thresh_hit);
9962 static struct rtnl_link_stats64 *tg3_get_stats64(struct net_device *dev,
9963 struct rtnl_link_stats64 *stats)
9965 struct tg3 *tp = netdev_priv(dev);
9966 struct rtnl_link_stats64 *old_stats = &tp->net_stats_prev;
9967 struct tg3_hw_stats *hw_stats = tp->hw_stats;
9972 stats->rx_packets = old_stats->rx_packets +
9973 get_stat64(&hw_stats->rx_ucast_packets) +
9974 get_stat64(&hw_stats->rx_mcast_packets) +
9975 get_stat64(&hw_stats->rx_bcast_packets);
9977 stats->tx_packets = old_stats->tx_packets +
9978 get_stat64(&hw_stats->tx_ucast_packets) +
9979 get_stat64(&hw_stats->tx_mcast_packets) +
9980 get_stat64(&hw_stats->tx_bcast_packets);
9982 stats->rx_bytes = old_stats->rx_bytes +
9983 get_stat64(&hw_stats->rx_octets);
9984 stats->tx_bytes = old_stats->tx_bytes +
9985 get_stat64(&hw_stats->tx_octets);
9987 stats->rx_errors = old_stats->rx_errors +
9988 get_stat64(&hw_stats->rx_errors);
9989 stats->tx_errors = old_stats->tx_errors +
9990 get_stat64(&hw_stats->tx_errors) +
9991 get_stat64(&hw_stats->tx_mac_errors) +
9992 get_stat64(&hw_stats->tx_carrier_sense_errors) +
9993 get_stat64(&hw_stats->tx_discards);
9995 stats->multicast = old_stats->multicast +
9996 get_stat64(&hw_stats->rx_mcast_packets);
9997 stats->collisions = old_stats->collisions +
9998 get_stat64(&hw_stats->tx_collisions);
10000 stats->rx_length_errors = old_stats->rx_length_errors +
10001 get_stat64(&hw_stats->rx_frame_too_long_errors) +
10002 get_stat64(&hw_stats->rx_undersize_packets);
10004 stats->rx_over_errors = old_stats->rx_over_errors +
10005 get_stat64(&hw_stats->rxbds_empty);
10006 stats->rx_frame_errors = old_stats->rx_frame_errors +
10007 get_stat64(&hw_stats->rx_align_errors);
10008 stats->tx_aborted_errors = old_stats->tx_aborted_errors +
10009 get_stat64(&hw_stats->tx_discards);
10010 stats->tx_carrier_errors = old_stats->tx_carrier_errors +
10011 get_stat64(&hw_stats->tx_carrier_sense_errors);
10013 stats->rx_crc_errors = old_stats->rx_crc_errors +
10014 calc_crc_errors(tp);
10016 stats->rx_missed_errors = old_stats->rx_missed_errors +
10017 get_stat64(&hw_stats->rx_discards);
10019 stats->rx_dropped = tp->rx_dropped;
10020 stats->tx_dropped = tp->tx_dropped;
10025 static inline u32 calc_crc(unsigned char *buf, int len)
10033 for (j = 0; j < len; j++) {
10036 for (k = 0; k < 8; k++) {
10049 static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
10051 /* accept or reject all multicast frames */
10052 tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
10053 tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
10054 tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
10055 tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
10058 static void __tg3_set_rx_mode(struct net_device *dev)
10060 struct tg3 *tp = netdev_priv(dev);
10063 rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
10064 RX_MODE_KEEP_VLAN_TAG);
10066 #if !defined(CONFIG_VLAN_8021Q) && !defined(CONFIG_VLAN_8021Q_MODULE)
10067 /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
10070 if (!tg3_flag(tp, ENABLE_ASF))
10071 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
10074 if (dev->flags & IFF_PROMISC) {
10075 /* Promiscuous mode. */
10076 rx_mode |= RX_MODE_PROMISC;
10077 } else if (dev->flags & IFF_ALLMULTI) {
10078 /* Accept all multicast. */
10079 tg3_set_multi(tp, 1);
10080 } else if (netdev_mc_empty(dev)) {
10081 /* Reject all multicast. */
10082 tg3_set_multi(tp, 0);
10084 /* Accept one or more multicast(s). */
10085 struct netdev_hw_addr *ha;
10086 u32 mc_filter[4] = { 0, };
10091 netdev_for_each_mc_addr(ha, dev) {
10092 crc = calc_crc(ha->addr, ETH_ALEN);
10094 regidx = (bit & 0x60) >> 5;
10096 mc_filter[regidx] |= (1 << bit);
10099 tw32(MAC_HASH_REG_0, mc_filter[0]);
10100 tw32(MAC_HASH_REG_1, mc_filter[1]);
10101 tw32(MAC_HASH_REG_2, mc_filter[2]);
10102 tw32(MAC_HASH_REG_3, mc_filter[3]);
10105 if (rx_mode != tp->rx_mode) {
10106 tp->rx_mode = rx_mode;
10107 tw32_f(MAC_RX_MODE, rx_mode);
10112 static void tg3_set_rx_mode(struct net_device *dev)
10114 struct tg3 *tp = netdev_priv(dev);
10116 if (!netif_running(dev))
10119 tg3_full_lock(tp, 0);
10120 __tg3_set_rx_mode(dev);
10121 tg3_full_unlock(tp);
10124 static int tg3_get_regs_len(struct net_device *dev)
10126 return TG3_REG_BLK_SIZE;
10129 static void tg3_get_regs(struct net_device *dev,
10130 struct ethtool_regs *regs, void *_p)
10132 struct tg3 *tp = netdev_priv(dev);
10136 memset(_p, 0, TG3_REG_BLK_SIZE);
10138 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
10141 tg3_full_lock(tp, 0);
10143 tg3_dump_legacy_regs(tp, (u32 *)_p);
10145 tg3_full_unlock(tp);
10148 static int tg3_get_eeprom_len(struct net_device *dev)
10150 struct tg3 *tp = netdev_priv(dev);
10152 return tp->nvram_size;
10155 static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
10157 struct tg3 *tp = netdev_priv(dev);
10160 u32 i, offset, len, b_offset, b_count;
10163 if (tg3_flag(tp, NO_NVRAM))
10166 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
10169 offset = eeprom->offset;
10173 eeprom->magic = TG3_EEPROM_MAGIC;
10176 /* adjustments to start on required 4 byte boundary */
10177 b_offset = offset & 3;
10178 b_count = 4 - b_offset;
10179 if (b_count > len) {
10180 /* i.e. offset=1 len=2 */
10183 ret = tg3_nvram_read_be32(tp, offset-b_offset, &val);
10186 memcpy(data, ((char *)&val) + b_offset, b_count);
10189 eeprom->len += b_count;
10192 /* read bytes up to the last 4 byte boundary */
10193 pd = &data[eeprom->len];
10194 for (i = 0; i < (len - (len & 3)); i += 4) {
10195 ret = tg3_nvram_read_be32(tp, offset + i, &val);
10200 memcpy(pd + i, &val, 4);
10205 /* read last bytes not ending on 4 byte boundary */
10206 pd = &data[eeprom->len];
10208 b_offset = offset + len - b_count;
10209 ret = tg3_nvram_read_be32(tp, b_offset, &val);
10212 memcpy(pd, &val, b_count);
10213 eeprom->len += b_count;
10218 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf);
10220 static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
10222 struct tg3 *tp = netdev_priv(dev);
10224 u32 offset, len, b_offset, odd_len;
10228 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
10231 if (tg3_flag(tp, NO_NVRAM) ||
10232 eeprom->magic != TG3_EEPROM_MAGIC)
10235 offset = eeprom->offset;
10238 if ((b_offset = (offset & 3))) {
10239 /* adjustments to start on required 4 byte boundary */
10240 ret = tg3_nvram_read_be32(tp, offset-b_offset, &start);
10251 /* adjustments to end on required 4 byte boundary */
10253 len = (len + 3) & ~3;
10254 ret = tg3_nvram_read_be32(tp, offset+len-4, &end);
10260 if (b_offset || odd_len) {
10261 buf = kmalloc(len, GFP_KERNEL);
10265 memcpy(buf, &start, 4);
10267 memcpy(buf+len-4, &end, 4);
10268 memcpy(buf + b_offset, data, eeprom->len);
10271 ret = tg3_nvram_write_block(tp, offset, len, buf);
10279 static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
10281 struct tg3 *tp = netdev_priv(dev);
10283 if (tg3_flag(tp, USE_PHYLIB)) {
10284 struct phy_device *phydev;
10285 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
10287 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
10288 return phy_ethtool_gset(phydev, cmd);
10291 cmd->supported = (SUPPORTED_Autoneg);
10293 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
10294 cmd->supported |= (SUPPORTED_1000baseT_Half |
10295 SUPPORTED_1000baseT_Full);
10297 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
10298 cmd->supported |= (SUPPORTED_100baseT_Half |
10299 SUPPORTED_100baseT_Full |
10300 SUPPORTED_10baseT_Half |
10301 SUPPORTED_10baseT_Full |
10303 cmd->port = PORT_TP;
10305 cmd->supported |= SUPPORTED_FIBRE;
10306 cmd->port = PORT_FIBRE;
10309 cmd->advertising = tp->link_config.advertising;
10310 if (tg3_flag(tp, PAUSE_AUTONEG)) {
10311 if (tp->link_config.flowctrl & FLOW_CTRL_RX) {
10312 if (tp->link_config.flowctrl & FLOW_CTRL_TX) {
10313 cmd->advertising |= ADVERTISED_Pause;
10315 cmd->advertising |= ADVERTISED_Pause |
10316 ADVERTISED_Asym_Pause;
10318 } else if (tp->link_config.flowctrl & FLOW_CTRL_TX) {
10319 cmd->advertising |= ADVERTISED_Asym_Pause;
10322 if (netif_running(dev)) {
10323 ethtool_cmd_speed_set(cmd, tp->link_config.active_speed);
10324 cmd->duplex = tp->link_config.active_duplex;
10326 ethtool_cmd_speed_set(cmd, SPEED_INVALID);
10327 cmd->duplex = DUPLEX_INVALID;
10329 cmd->phy_address = tp->phy_addr;
10330 cmd->transceiver = XCVR_INTERNAL;
10331 cmd->autoneg = tp->link_config.autoneg;
10337 static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
10339 struct tg3 *tp = netdev_priv(dev);
10340 u32 speed = ethtool_cmd_speed(cmd);
10342 if (tg3_flag(tp, USE_PHYLIB)) {
10343 struct phy_device *phydev;
10344 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
10346 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
10347 return phy_ethtool_sset(phydev, cmd);
10350 if (cmd->autoneg != AUTONEG_ENABLE &&
10351 cmd->autoneg != AUTONEG_DISABLE)
10354 if (cmd->autoneg == AUTONEG_DISABLE &&
10355 cmd->duplex != DUPLEX_FULL &&
10356 cmd->duplex != DUPLEX_HALF)
10359 if (cmd->autoneg == AUTONEG_ENABLE) {
10360 u32 mask = ADVERTISED_Autoneg |
10362 ADVERTISED_Asym_Pause;
10364 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
10365 mask |= ADVERTISED_1000baseT_Half |
10366 ADVERTISED_1000baseT_Full;
10368 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
10369 mask |= ADVERTISED_100baseT_Half |
10370 ADVERTISED_100baseT_Full |
10371 ADVERTISED_10baseT_Half |
10372 ADVERTISED_10baseT_Full |
10375 mask |= ADVERTISED_FIBRE;
10377 if (cmd->advertising & ~mask)
10380 mask &= (ADVERTISED_1000baseT_Half |
10381 ADVERTISED_1000baseT_Full |
10382 ADVERTISED_100baseT_Half |
10383 ADVERTISED_100baseT_Full |
10384 ADVERTISED_10baseT_Half |
10385 ADVERTISED_10baseT_Full);
10387 cmd->advertising &= mask;
10389 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) {
10390 if (speed != SPEED_1000)
10393 if (cmd->duplex != DUPLEX_FULL)
10396 if (speed != SPEED_100 &&
10402 tg3_full_lock(tp, 0);
10404 tp->link_config.autoneg = cmd->autoneg;
10405 if (cmd->autoneg == AUTONEG_ENABLE) {
10406 tp->link_config.advertising = (cmd->advertising |
10407 ADVERTISED_Autoneg);
10408 tp->link_config.speed = SPEED_INVALID;
10409 tp->link_config.duplex = DUPLEX_INVALID;
10411 tp->link_config.advertising = 0;
10412 tp->link_config.speed = speed;
10413 tp->link_config.duplex = cmd->duplex;
10416 tp->link_config.orig_speed = tp->link_config.speed;
10417 tp->link_config.orig_duplex = tp->link_config.duplex;
10418 tp->link_config.orig_autoneg = tp->link_config.autoneg;
10420 if (netif_running(dev))
10421 tg3_setup_phy(tp, 1);
10423 tg3_full_unlock(tp);
10428 static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
10430 struct tg3 *tp = netdev_priv(dev);
10432 strlcpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver));
10433 strlcpy(info->version, DRV_MODULE_VERSION, sizeof(info->version));
10434 strlcpy(info->fw_version, tp->fw_ver, sizeof(info->fw_version));
10435 strlcpy(info->bus_info, pci_name(tp->pdev), sizeof(info->bus_info));
10438 static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
10440 struct tg3 *tp = netdev_priv(dev);
10442 if (tg3_flag(tp, WOL_CAP) && device_can_wakeup(&tp->pdev->dev))
10443 wol->supported = WAKE_MAGIC;
10445 wol->supported = 0;
10447 if (tg3_flag(tp, WOL_ENABLE) && device_can_wakeup(&tp->pdev->dev))
10448 wol->wolopts = WAKE_MAGIC;
10449 memset(&wol->sopass, 0, sizeof(wol->sopass));
10452 static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
10454 struct tg3 *tp = netdev_priv(dev);
10455 struct device *dp = &tp->pdev->dev;
10457 if (wol->wolopts & ~WAKE_MAGIC)
10459 if ((wol->wolopts & WAKE_MAGIC) &&
10460 !(tg3_flag(tp, WOL_CAP) && device_can_wakeup(dp)))
10463 device_set_wakeup_enable(dp, wol->wolopts & WAKE_MAGIC);
10465 spin_lock_bh(&tp->lock);
10466 if (device_may_wakeup(dp))
10467 tg3_flag_set(tp, WOL_ENABLE);
10469 tg3_flag_clear(tp, WOL_ENABLE);
10470 spin_unlock_bh(&tp->lock);
10475 static u32 tg3_get_msglevel(struct net_device *dev)
10477 struct tg3 *tp = netdev_priv(dev);
10478 return tp->msg_enable;
10481 static void tg3_set_msglevel(struct net_device *dev, u32 value)
10483 struct tg3 *tp = netdev_priv(dev);
10484 tp->msg_enable = value;
10487 static int tg3_nway_reset(struct net_device *dev)
10489 struct tg3 *tp = netdev_priv(dev);
10492 if (!netif_running(dev))
10495 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
10498 if (tg3_flag(tp, USE_PHYLIB)) {
10499 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
10501 r = phy_start_aneg(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
10505 spin_lock_bh(&tp->lock);
10507 tg3_readphy(tp, MII_BMCR, &bmcr);
10508 if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
10509 ((bmcr & BMCR_ANENABLE) ||
10510 (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT))) {
10511 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
10515 spin_unlock_bh(&tp->lock);
10521 static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
10523 struct tg3 *tp = netdev_priv(dev);
10525 ering->rx_max_pending = tp->rx_std_ring_mask;
10526 if (tg3_flag(tp, JUMBO_RING_ENABLE))
10527 ering->rx_jumbo_max_pending = tp->rx_jmb_ring_mask;
10529 ering->rx_jumbo_max_pending = 0;
10531 ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
10533 ering->rx_pending = tp->rx_pending;
10534 if (tg3_flag(tp, JUMBO_RING_ENABLE))
10535 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
10537 ering->rx_jumbo_pending = 0;
10539 ering->tx_pending = tp->napi[0].tx_pending;
10542 static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
10544 struct tg3 *tp = netdev_priv(dev);
10545 int i, irq_sync = 0, err = 0;
10547 if ((ering->rx_pending > tp->rx_std_ring_mask) ||
10548 (ering->rx_jumbo_pending > tp->rx_jmb_ring_mask) ||
10549 (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
10550 (ering->tx_pending <= MAX_SKB_FRAGS) ||
10551 (tg3_flag(tp, TSO_BUG) &&
10552 (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
10555 if (netif_running(dev)) {
10557 tg3_netif_stop(tp);
10561 tg3_full_lock(tp, irq_sync);
10563 tp->rx_pending = ering->rx_pending;
10565 if (tg3_flag(tp, MAX_RXPEND_64) &&
10566 tp->rx_pending > 63)
10567 tp->rx_pending = 63;
10568 tp->rx_jumbo_pending = ering->rx_jumbo_pending;
10570 for (i = 0; i < tp->irq_max; i++)
10571 tp->napi[i].tx_pending = ering->tx_pending;
10573 if (netif_running(dev)) {
10574 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10575 err = tg3_restart_hw(tp, 1);
10577 tg3_netif_start(tp);
10580 tg3_full_unlock(tp);
10582 if (irq_sync && !err)
10588 static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
10590 struct tg3 *tp = netdev_priv(dev);
10592 epause->autoneg = !!tg3_flag(tp, PAUSE_AUTONEG);
10594 if (tp->link_config.active_flowctrl & FLOW_CTRL_RX)
10595 epause->rx_pause = 1;
10597 epause->rx_pause = 0;
10599 if (tp->link_config.active_flowctrl & FLOW_CTRL_TX)
10600 epause->tx_pause = 1;
10602 epause->tx_pause = 0;
10605 static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
10607 struct tg3 *tp = netdev_priv(dev);
10610 if (tg3_flag(tp, USE_PHYLIB)) {
10612 struct phy_device *phydev;
10614 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
10616 if (!(phydev->supported & SUPPORTED_Pause) ||
10617 (!(phydev->supported & SUPPORTED_Asym_Pause) &&
10618 (epause->rx_pause != epause->tx_pause)))
10621 tp->link_config.flowctrl = 0;
10622 if (epause->rx_pause) {
10623 tp->link_config.flowctrl |= FLOW_CTRL_RX;
10625 if (epause->tx_pause) {
10626 tp->link_config.flowctrl |= FLOW_CTRL_TX;
10627 newadv = ADVERTISED_Pause;
10629 newadv = ADVERTISED_Pause |
10630 ADVERTISED_Asym_Pause;
10631 } else if (epause->tx_pause) {
10632 tp->link_config.flowctrl |= FLOW_CTRL_TX;
10633 newadv = ADVERTISED_Asym_Pause;
10637 if (epause->autoneg)
10638 tg3_flag_set(tp, PAUSE_AUTONEG);
10640 tg3_flag_clear(tp, PAUSE_AUTONEG);
10642 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
10643 u32 oldadv = phydev->advertising &
10644 (ADVERTISED_Pause | ADVERTISED_Asym_Pause);
10645 if (oldadv != newadv) {
10646 phydev->advertising &=
10647 ~(ADVERTISED_Pause |
10648 ADVERTISED_Asym_Pause);
10649 phydev->advertising |= newadv;
10650 if (phydev->autoneg) {
10652 * Always renegotiate the link to
10653 * inform our link partner of our
10654 * flow control settings, even if the
10655 * flow control is forced. Let
10656 * tg3_adjust_link() do the final
10657 * flow control setup.
10659 return phy_start_aneg(phydev);
10663 if (!epause->autoneg)
10664 tg3_setup_flow_control(tp, 0, 0);
10666 tp->link_config.orig_advertising &=
10667 ~(ADVERTISED_Pause |
10668 ADVERTISED_Asym_Pause);
10669 tp->link_config.orig_advertising |= newadv;
10674 if (netif_running(dev)) {
10675 tg3_netif_stop(tp);
10679 tg3_full_lock(tp, irq_sync);
10681 if (epause->autoneg)
10682 tg3_flag_set(tp, PAUSE_AUTONEG);
10684 tg3_flag_clear(tp, PAUSE_AUTONEG);
10685 if (epause->rx_pause)
10686 tp->link_config.flowctrl |= FLOW_CTRL_RX;
10688 tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
10689 if (epause->tx_pause)
10690 tp->link_config.flowctrl |= FLOW_CTRL_TX;
10692 tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
10694 if (netif_running(dev)) {
10695 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10696 err = tg3_restart_hw(tp, 1);
10698 tg3_netif_start(tp);
10701 tg3_full_unlock(tp);
10707 static int tg3_get_sset_count(struct net_device *dev, int sset)
10711 return TG3_NUM_TEST;
10713 return TG3_NUM_STATS;
10715 return -EOPNOTSUPP;
10719 static void tg3_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
10721 switch (stringset) {
10723 memcpy(buf, ðtool_stats_keys, sizeof(ethtool_stats_keys));
10726 memcpy(buf, ðtool_test_keys, sizeof(ethtool_test_keys));
10729 WARN_ON(1); /* we need a WARN() */
10734 static int tg3_set_phys_id(struct net_device *dev,
10735 enum ethtool_phys_id_state state)
10737 struct tg3 *tp = netdev_priv(dev);
10739 if (!netif_running(tp->dev))
10743 case ETHTOOL_ID_ACTIVE:
10744 return 1; /* cycle on/off once per second */
10746 case ETHTOOL_ID_ON:
10747 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
10748 LED_CTRL_1000MBPS_ON |
10749 LED_CTRL_100MBPS_ON |
10750 LED_CTRL_10MBPS_ON |
10751 LED_CTRL_TRAFFIC_OVERRIDE |
10752 LED_CTRL_TRAFFIC_BLINK |
10753 LED_CTRL_TRAFFIC_LED);
10756 case ETHTOOL_ID_OFF:
10757 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
10758 LED_CTRL_TRAFFIC_OVERRIDE);
10761 case ETHTOOL_ID_INACTIVE:
10762 tw32(MAC_LED_CTRL, tp->led_ctrl);
10769 static void tg3_get_ethtool_stats(struct net_device *dev,
10770 struct ethtool_stats *estats, u64 *tmp_stats)
10772 struct tg3 *tp = netdev_priv(dev);
10773 memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats));
10776 static __be32 *tg3_vpd_readblock(struct tg3 *tp, u32 *vpdlen)
10780 u32 offset = 0, len = 0;
10783 if (tg3_flag(tp, NO_NVRAM) || tg3_nvram_read(tp, 0, &magic))
10786 if (magic == TG3_EEPROM_MAGIC) {
10787 for (offset = TG3_NVM_DIR_START;
10788 offset < TG3_NVM_DIR_END;
10789 offset += TG3_NVM_DIRENT_SIZE) {
10790 if (tg3_nvram_read(tp, offset, &val))
10793 if ((val >> TG3_NVM_DIRTYPE_SHIFT) ==
10794 TG3_NVM_DIRTYPE_EXTVPD)
10798 if (offset != TG3_NVM_DIR_END) {
10799 len = (val & TG3_NVM_DIRTYPE_LENMSK) * 4;
10800 if (tg3_nvram_read(tp, offset + 4, &offset))
10803 offset = tg3_nvram_logical_addr(tp, offset);
10807 if (!offset || !len) {
10808 offset = TG3_NVM_VPD_OFF;
10809 len = TG3_NVM_VPD_LEN;
10812 buf = kmalloc(len, GFP_KERNEL);
10816 if (magic == TG3_EEPROM_MAGIC) {
10817 for (i = 0; i < len; i += 4) {
10818 /* The data is in little-endian format in NVRAM.
10819 * Use the big-endian read routines to preserve
10820 * the byte order as it exists in NVRAM.
10822 if (tg3_nvram_read_be32(tp, offset + i, &buf[i/4]))
10828 unsigned int pos = 0;
10830 ptr = (u8 *)&buf[0];
10831 for (i = 0; pos < len && i < 3; i++, pos += cnt, ptr += cnt) {
10832 cnt = pci_read_vpd(tp->pdev, pos,
10834 if (cnt == -ETIMEDOUT || cnt == -EINTR)
10852 #define NVRAM_TEST_SIZE 0x100
10853 #define NVRAM_SELFBOOT_FORMAT1_0_SIZE 0x14
10854 #define NVRAM_SELFBOOT_FORMAT1_2_SIZE 0x18
10855 #define NVRAM_SELFBOOT_FORMAT1_3_SIZE 0x1c
10856 #define NVRAM_SELFBOOT_FORMAT1_4_SIZE 0x20
10857 #define NVRAM_SELFBOOT_FORMAT1_5_SIZE 0x24
10858 #define NVRAM_SELFBOOT_FORMAT1_6_SIZE 0x50
10859 #define NVRAM_SELFBOOT_HW_SIZE 0x20
10860 #define NVRAM_SELFBOOT_DATA_SIZE 0x1c
10862 static int tg3_test_nvram(struct tg3 *tp)
10864 u32 csum, magic, len;
10866 int i, j, k, err = 0, size;
10868 if (tg3_flag(tp, NO_NVRAM))
10871 if (tg3_nvram_read(tp, 0, &magic) != 0)
10874 if (magic == TG3_EEPROM_MAGIC)
10875 size = NVRAM_TEST_SIZE;
10876 else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
10877 if ((magic & TG3_EEPROM_SB_FORMAT_MASK) ==
10878 TG3_EEPROM_SB_FORMAT_1) {
10879 switch (magic & TG3_EEPROM_SB_REVISION_MASK) {
10880 case TG3_EEPROM_SB_REVISION_0:
10881 size = NVRAM_SELFBOOT_FORMAT1_0_SIZE;
10883 case TG3_EEPROM_SB_REVISION_2:
10884 size = NVRAM_SELFBOOT_FORMAT1_2_SIZE;
10886 case TG3_EEPROM_SB_REVISION_3:
10887 size = NVRAM_SELFBOOT_FORMAT1_3_SIZE;
10889 case TG3_EEPROM_SB_REVISION_4:
10890 size = NVRAM_SELFBOOT_FORMAT1_4_SIZE;
10892 case TG3_EEPROM_SB_REVISION_5:
10893 size = NVRAM_SELFBOOT_FORMAT1_5_SIZE;
10895 case TG3_EEPROM_SB_REVISION_6:
10896 size = NVRAM_SELFBOOT_FORMAT1_6_SIZE;
10903 } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
10904 size = NVRAM_SELFBOOT_HW_SIZE;
10908 buf = kmalloc(size, GFP_KERNEL);
10913 for (i = 0, j = 0; i < size; i += 4, j++) {
10914 err = tg3_nvram_read_be32(tp, i, &buf[j]);
10921 /* Selfboot format */
10922 magic = be32_to_cpu(buf[0]);
10923 if ((magic & TG3_EEPROM_MAGIC_FW_MSK) ==
10924 TG3_EEPROM_MAGIC_FW) {
10925 u8 *buf8 = (u8 *) buf, csum8 = 0;
10927 if ((magic & TG3_EEPROM_SB_REVISION_MASK) ==
10928 TG3_EEPROM_SB_REVISION_2) {
10929 /* For rev 2, the csum doesn't include the MBA. */
10930 for (i = 0; i < TG3_EEPROM_SB_F1R2_MBA_OFF; i++)
10932 for (i = TG3_EEPROM_SB_F1R2_MBA_OFF + 4; i < size; i++)
10935 for (i = 0; i < size; i++)
10948 if ((magic & TG3_EEPROM_MAGIC_HW_MSK) ==
10949 TG3_EEPROM_MAGIC_HW) {
10950 u8 data[NVRAM_SELFBOOT_DATA_SIZE];
10951 u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
10952 u8 *buf8 = (u8 *) buf;
10954 /* Separate the parity bits and the data bytes. */
10955 for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
10956 if ((i == 0) || (i == 8)) {
10960 for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
10961 parity[k++] = buf8[i] & msk;
10963 } else if (i == 16) {
10967 for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
10968 parity[k++] = buf8[i] & msk;
10971 for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
10972 parity[k++] = buf8[i] & msk;
10975 data[j++] = buf8[i];
10979 for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
10980 u8 hw8 = hweight8(data[i]);
10982 if ((hw8 & 0x1) && parity[i])
10984 else if (!(hw8 & 0x1) && !parity[i])
10993 /* Bootstrap checksum at offset 0x10 */
10994 csum = calc_crc((unsigned char *) buf, 0x10);
10995 if (csum != le32_to_cpu(buf[0x10/4]))
10998 /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
10999 csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
11000 if (csum != le32_to_cpu(buf[0xfc/4]))
11005 buf = tg3_vpd_readblock(tp, &len);
11009 i = pci_vpd_find_tag((u8 *)buf, 0, len, PCI_VPD_LRDT_RO_DATA);
11011 j = pci_vpd_lrdt_size(&((u8 *)buf)[i]);
11015 if (i + PCI_VPD_LRDT_TAG_SIZE + j > len)
11018 i += PCI_VPD_LRDT_TAG_SIZE;
11019 j = pci_vpd_find_info_keyword((u8 *)buf, i, j,
11020 PCI_VPD_RO_KEYWORD_CHKSUM);
11024 j += PCI_VPD_INFO_FLD_HDR_SIZE;
11026 for (i = 0; i <= j; i++)
11027 csum8 += ((u8 *)buf)[i];
11041 #define TG3_SERDES_TIMEOUT_SEC 2
11042 #define TG3_COPPER_TIMEOUT_SEC 6
11044 static int tg3_test_link(struct tg3 *tp)
11048 if (!netif_running(tp->dev))
11051 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
11052 max = TG3_SERDES_TIMEOUT_SEC;
11054 max = TG3_COPPER_TIMEOUT_SEC;
11056 for (i = 0; i < max; i++) {
11057 if (netif_carrier_ok(tp->dev))
11060 if (msleep_interruptible(1000))
11067 /* Only test the commonly used registers */
11068 static int tg3_test_registers(struct tg3 *tp)
11070 int i, is_5705, is_5750;
11071 u32 offset, read_mask, write_mask, val, save_val, read_val;
11075 #define TG3_FL_5705 0x1
11076 #define TG3_FL_NOT_5705 0x2
11077 #define TG3_FL_NOT_5788 0x4
11078 #define TG3_FL_NOT_5750 0x8
11082 /* MAC Control Registers */
11083 { MAC_MODE, TG3_FL_NOT_5705,
11084 0x00000000, 0x00ef6f8c },
11085 { MAC_MODE, TG3_FL_5705,
11086 0x00000000, 0x01ef6b8c },
11087 { MAC_STATUS, TG3_FL_NOT_5705,
11088 0x03800107, 0x00000000 },
11089 { MAC_STATUS, TG3_FL_5705,
11090 0x03800100, 0x00000000 },
11091 { MAC_ADDR_0_HIGH, 0x0000,
11092 0x00000000, 0x0000ffff },
11093 { MAC_ADDR_0_LOW, 0x0000,
11094 0x00000000, 0xffffffff },
11095 { MAC_RX_MTU_SIZE, 0x0000,
11096 0x00000000, 0x0000ffff },
11097 { MAC_TX_MODE, 0x0000,
11098 0x00000000, 0x00000070 },
11099 { MAC_TX_LENGTHS, 0x0000,
11100 0x00000000, 0x00003fff },
11101 { MAC_RX_MODE, TG3_FL_NOT_5705,
11102 0x00000000, 0x000007fc },
11103 { MAC_RX_MODE, TG3_FL_5705,
11104 0x00000000, 0x000007dc },
11105 { MAC_HASH_REG_0, 0x0000,
11106 0x00000000, 0xffffffff },
11107 { MAC_HASH_REG_1, 0x0000,
11108 0x00000000, 0xffffffff },
11109 { MAC_HASH_REG_2, 0x0000,
11110 0x00000000, 0xffffffff },
11111 { MAC_HASH_REG_3, 0x0000,
11112 0x00000000, 0xffffffff },
11114 /* Receive Data and Receive BD Initiator Control Registers. */
11115 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
11116 0x00000000, 0xffffffff },
11117 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
11118 0x00000000, 0xffffffff },
11119 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
11120 0x00000000, 0x00000003 },
11121 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
11122 0x00000000, 0xffffffff },
11123 { RCVDBDI_STD_BD+0, 0x0000,
11124 0x00000000, 0xffffffff },
11125 { RCVDBDI_STD_BD+4, 0x0000,
11126 0x00000000, 0xffffffff },
11127 { RCVDBDI_STD_BD+8, 0x0000,
11128 0x00000000, 0xffff0002 },
11129 { RCVDBDI_STD_BD+0xc, 0x0000,
11130 0x00000000, 0xffffffff },
11132 /* Receive BD Initiator Control Registers. */
11133 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
11134 0x00000000, 0xffffffff },
11135 { RCVBDI_STD_THRESH, TG3_FL_5705,
11136 0x00000000, 0x000003ff },
11137 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
11138 0x00000000, 0xffffffff },
11140 /* Host Coalescing Control Registers. */
11141 { HOSTCC_MODE, TG3_FL_NOT_5705,
11142 0x00000000, 0x00000004 },
11143 { HOSTCC_MODE, TG3_FL_5705,
11144 0x00000000, 0x000000f6 },
11145 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
11146 0x00000000, 0xffffffff },
11147 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
11148 0x00000000, 0x000003ff },
11149 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
11150 0x00000000, 0xffffffff },
11151 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
11152 0x00000000, 0x000003ff },
11153 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
11154 0x00000000, 0xffffffff },
11155 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
11156 0x00000000, 0x000000ff },
11157 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
11158 0x00000000, 0xffffffff },
11159 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
11160 0x00000000, 0x000000ff },
11161 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
11162 0x00000000, 0xffffffff },
11163 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
11164 0x00000000, 0xffffffff },
11165 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
11166 0x00000000, 0xffffffff },
11167 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
11168 0x00000000, 0x000000ff },
11169 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
11170 0x00000000, 0xffffffff },
11171 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
11172 0x00000000, 0x000000ff },
11173 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
11174 0x00000000, 0xffffffff },
11175 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
11176 0x00000000, 0xffffffff },
11177 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
11178 0x00000000, 0xffffffff },
11179 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
11180 0x00000000, 0xffffffff },
11181 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
11182 0x00000000, 0xffffffff },
11183 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
11184 0xffffffff, 0x00000000 },
11185 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
11186 0xffffffff, 0x00000000 },
11188 /* Buffer Manager Control Registers. */
11189 { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
11190 0x00000000, 0x007fff80 },
11191 { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
11192 0x00000000, 0x007fffff },
11193 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
11194 0x00000000, 0x0000003f },
11195 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
11196 0x00000000, 0x000001ff },
11197 { BUFMGR_MB_HIGH_WATER, 0x0000,
11198 0x00000000, 0x000001ff },
11199 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
11200 0xffffffff, 0x00000000 },
11201 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
11202 0xffffffff, 0x00000000 },
11204 /* Mailbox Registers */
11205 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
11206 0x00000000, 0x000001ff },
11207 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
11208 0x00000000, 0x000001ff },
11209 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
11210 0x00000000, 0x000007ff },
11211 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
11212 0x00000000, 0x000001ff },
11214 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
11217 is_5705 = is_5750 = 0;
11218 if (tg3_flag(tp, 5705_PLUS)) {
11220 if (tg3_flag(tp, 5750_PLUS))
11224 for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
11225 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
11228 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
11231 if (tg3_flag(tp, IS_5788) &&
11232 (reg_tbl[i].flags & TG3_FL_NOT_5788))
11235 if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
11238 offset = (u32) reg_tbl[i].offset;
11239 read_mask = reg_tbl[i].read_mask;
11240 write_mask = reg_tbl[i].write_mask;
11242 /* Save the original register content */
11243 save_val = tr32(offset);
11245 /* Determine the read-only value. */
11246 read_val = save_val & read_mask;
11248 /* Write zero to the register, then make sure the read-only bits
11249 * are not changed and the read/write bits are all zeros.
11253 val = tr32(offset);
11255 /* Test the read-only and read/write bits. */
11256 if (((val & read_mask) != read_val) || (val & write_mask))
11259 /* Write ones to all the bits defined by RdMask and WrMask, then
11260 * make sure the read-only bits are not changed and the
11261 * read/write bits are all ones.
11263 tw32(offset, read_mask | write_mask);
11265 val = tr32(offset);
11267 /* Test the read-only bits. */
11268 if ((val & read_mask) != read_val)
11271 /* Test the read/write bits. */
11272 if ((val & write_mask) != write_mask)
11275 tw32(offset, save_val);
11281 if (netif_msg_hw(tp))
11282 netdev_err(tp->dev,
11283 "Register test failed at offset %x\n", offset);
11284 tw32(offset, save_val);
11288 static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
11290 static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
11294 for (i = 0; i < ARRAY_SIZE(test_pattern); i++) {
11295 for (j = 0; j < len; j += 4) {
11298 tg3_write_mem(tp, offset + j, test_pattern[i]);
11299 tg3_read_mem(tp, offset + j, &val);
11300 if (val != test_pattern[i])
11307 static int tg3_test_memory(struct tg3 *tp)
11309 static struct mem_entry {
11312 } mem_tbl_570x[] = {
11313 { 0x00000000, 0x00b50},
11314 { 0x00002000, 0x1c000},
11315 { 0xffffffff, 0x00000}
11316 }, mem_tbl_5705[] = {
11317 { 0x00000100, 0x0000c},
11318 { 0x00000200, 0x00008},
11319 { 0x00004000, 0x00800},
11320 { 0x00006000, 0x01000},
11321 { 0x00008000, 0x02000},
11322 { 0x00010000, 0x0e000},
11323 { 0xffffffff, 0x00000}
11324 }, mem_tbl_5755[] = {
11325 { 0x00000200, 0x00008},
11326 { 0x00004000, 0x00800},
11327 { 0x00006000, 0x00800},
11328 { 0x00008000, 0x02000},
11329 { 0x00010000, 0x0c000},
11330 { 0xffffffff, 0x00000}
11331 }, mem_tbl_5906[] = {
11332 { 0x00000200, 0x00008},
11333 { 0x00004000, 0x00400},
11334 { 0x00006000, 0x00400},
11335 { 0x00008000, 0x01000},
11336 { 0x00010000, 0x01000},
11337 { 0xffffffff, 0x00000}
11338 }, mem_tbl_5717[] = {
11339 { 0x00000200, 0x00008},
11340 { 0x00010000, 0x0a000},
11341 { 0x00020000, 0x13c00},
11342 { 0xffffffff, 0x00000}
11343 }, mem_tbl_57765[] = {
11344 { 0x00000200, 0x00008},
11345 { 0x00004000, 0x00800},
11346 { 0x00006000, 0x09800},
11347 { 0x00010000, 0x0a000},
11348 { 0xffffffff, 0x00000}
11350 struct mem_entry *mem_tbl;
11354 if (tg3_flag(tp, 5717_PLUS))
11355 mem_tbl = mem_tbl_5717;
11356 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
11357 mem_tbl = mem_tbl_57765;
11358 else if (tg3_flag(tp, 5755_PLUS))
11359 mem_tbl = mem_tbl_5755;
11360 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
11361 mem_tbl = mem_tbl_5906;
11362 else if (tg3_flag(tp, 5705_PLUS))
11363 mem_tbl = mem_tbl_5705;
11365 mem_tbl = mem_tbl_570x;
11367 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
11368 err = tg3_do_mem_test(tp, mem_tbl[i].offset, mem_tbl[i].len);
11376 #define TG3_TSO_MSS 500
11378 #define TG3_TSO_IP_HDR_LEN 20
11379 #define TG3_TSO_TCP_HDR_LEN 20
11380 #define TG3_TSO_TCP_OPT_LEN 12
11382 static const u8 tg3_tso_header[] = {
11384 0x45, 0x00, 0x00, 0x00,
11385 0x00, 0x00, 0x40, 0x00,
11386 0x40, 0x06, 0x00, 0x00,
11387 0x0a, 0x00, 0x00, 0x01,
11388 0x0a, 0x00, 0x00, 0x02,
11389 0x0d, 0x00, 0xe0, 0x00,
11390 0x00, 0x00, 0x01, 0x00,
11391 0x00, 0x00, 0x02, 0x00,
11392 0x80, 0x10, 0x10, 0x00,
11393 0x14, 0x09, 0x00, 0x00,
11394 0x01, 0x01, 0x08, 0x0a,
11395 0x11, 0x11, 0x11, 0x11,
11396 0x11, 0x11, 0x11, 0x11,
11399 static int tg3_run_loopback(struct tg3 *tp, u32 pktsz, bool tso_loopback)
11401 u32 rx_start_idx, rx_idx, tx_idx, opaque_key;
11402 u32 base_flags = 0, mss = 0, desc_idx, coal_now, data_off, val;
11404 struct sk_buff *skb, *rx_skb;
11407 int num_pkts, tx_len, rx_len, i, err;
11408 struct tg3_rx_buffer_desc *desc;
11409 struct tg3_napi *tnapi, *rnapi;
11410 struct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring;
11412 tnapi = &tp->napi[0];
11413 rnapi = &tp->napi[0];
11414 if (tp->irq_cnt > 1) {
11415 if (tg3_flag(tp, ENABLE_RSS))
11416 rnapi = &tp->napi[1];
11417 if (tg3_flag(tp, ENABLE_TSS))
11418 tnapi = &tp->napi[1];
11420 coal_now = tnapi->coal_now | rnapi->coal_now;
11425 skb = netdev_alloc_skb(tp->dev, tx_len);
11429 tx_data = skb_put(skb, tx_len);
11430 memcpy(tx_data, tp->dev->dev_addr, 6);
11431 memset(tx_data + 6, 0x0, 8);
11433 tw32(MAC_RX_MTU_SIZE, tx_len + ETH_FCS_LEN);
11435 if (tso_loopback) {
11436 struct iphdr *iph = (struct iphdr *)&tx_data[ETH_HLEN];
11438 u32 hdr_len = TG3_TSO_IP_HDR_LEN + TG3_TSO_TCP_HDR_LEN +
11439 TG3_TSO_TCP_OPT_LEN;
11441 memcpy(tx_data + ETH_ALEN * 2, tg3_tso_header,
11442 sizeof(tg3_tso_header));
11445 val = tx_len - ETH_ALEN * 2 - sizeof(tg3_tso_header);
11446 num_pkts = DIV_ROUND_UP(val, TG3_TSO_MSS);
11448 /* Set the total length field in the IP header */
11449 iph->tot_len = htons((u16)(mss + hdr_len));
11451 base_flags = (TXD_FLAG_CPU_PRE_DMA |
11452 TXD_FLAG_CPU_POST_DMA);
11454 if (tg3_flag(tp, HW_TSO_1) ||
11455 tg3_flag(tp, HW_TSO_2) ||
11456 tg3_flag(tp, HW_TSO_3)) {
11458 val = ETH_HLEN + TG3_TSO_IP_HDR_LEN;
11459 th = (struct tcphdr *)&tx_data[val];
11462 base_flags |= TXD_FLAG_TCPUDP_CSUM;
11464 if (tg3_flag(tp, HW_TSO_3)) {
11465 mss |= (hdr_len & 0xc) << 12;
11466 if (hdr_len & 0x10)
11467 base_flags |= 0x00000010;
11468 base_flags |= (hdr_len & 0x3e0) << 5;
11469 } else if (tg3_flag(tp, HW_TSO_2))
11470 mss |= hdr_len << 9;
11471 else if (tg3_flag(tp, HW_TSO_1) ||
11472 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
11473 mss |= (TG3_TSO_TCP_OPT_LEN << 9);
11475 base_flags |= (TG3_TSO_TCP_OPT_LEN << 10);
11478 data_off = ETH_ALEN * 2 + sizeof(tg3_tso_header);
11481 data_off = ETH_HLEN;
11484 for (i = data_off; i < tx_len; i++)
11485 tx_data[i] = (u8) (i & 0xff);
11487 map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
11488 if (pci_dma_mapping_error(tp->pdev, map)) {
11489 dev_kfree_skb(skb);
11493 val = tnapi->tx_prod;
11494 tnapi->tx_buffers[val].skb = skb;
11495 dma_unmap_addr_set(&tnapi->tx_buffers[val], mapping, map);
11497 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
11502 rx_start_idx = rnapi->hw_status->idx[0].rx_producer;
11504 budget = tg3_tx_avail(tnapi);
11505 if (tg3_tx_frag_set(tnapi, &val, &budget, map, tx_len,
11506 base_flags | TXD_FLAG_END, mss, 0)) {
11507 tnapi->tx_buffers[val].skb = NULL;
11508 dev_kfree_skb(skb);
11514 tw32_tx_mbox(tnapi->prodmbox, tnapi->tx_prod);
11515 tr32_mailbox(tnapi->prodmbox);
11519 /* 350 usec to allow enough time on some 10/100 Mbps devices. */
11520 for (i = 0; i < 35; i++) {
11521 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
11526 tx_idx = tnapi->hw_status->idx[0].tx_consumer;
11527 rx_idx = rnapi->hw_status->idx[0].rx_producer;
11528 if ((tx_idx == tnapi->tx_prod) &&
11529 (rx_idx == (rx_start_idx + num_pkts)))
11533 tg3_tx_skb_unmap(tnapi, tnapi->tx_prod - 1, -1);
11534 dev_kfree_skb(skb);
11536 if (tx_idx != tnapi->tx_prod)
11539 if (rx_idx != rx_start_idx + num_pkts)
11543 while (rx_idx != rx_start_idx) {
11544 desc = &rnapi->rx_rcb[rx_start_idx++];
11545 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
11546 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
11548 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
11549 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
11552 rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT)
11555 if (!tso_loopback) {
11556 if (rx_len != tx_len)
11559 if (pktsz <= TG3_RX_STD_DMA_SZ - ETH_FCS_LEN) {
11560 if (opaque_key != RXD_OPAQUE_RING_STD)
11563 if (opaque_key != RXD_OPAQUE_RING_JUMBO)
11566 } else if ((desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
11567 (desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
11568 >> RXD_TCPCSUM_SHIFT != 0xffff) {
11572 if (opaque_key == RXD_OPAQUE_RING_STD) {
11573 rx_skb = tpr->rx_std_buffers[desc_idx].skb;
11574 map = dma_unmap_addr(&tpr->rx_std_buffers[desc_idx],
11576 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
11577 rx_skb = tpr->rx_jmb_buffers[desc_idx].skb;
11578 map = dma_unmap_addr(&tpr->rx_jmb_buffers[desc_idx],
11583 pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len,
11584 PCI_DMA_FROMDEVICE);
11586 for (i = data_off; i < rx_len; i++, val++) {
11587 if (*(rx_skb->data + i) != (u8) (val & 0xff))
11594 /* tg3_free_rings will unmap and free the rx_skb */
11599 #define TG3_STD_LOOPBACK_FAILED 1
11600 #define TG3_JMB_LOOPBACK_FAILED 2
11601 #define TG3_TSO_LOOPBACK_FAILED 4
11602 #define TG3_LOOPBACK_FAILED \
11603 (TG3_STD_LOOPBACK_FAILED | \
11604 TG3_JMB_LOOPBACK_FAILED | \
11605 TG3_TSO_LOOPBACK_FAILED)
11607 static int tg3_test_loopback(struct tg3 *tp, u64 *data, bool do_extlpbk)
11612 eee_cap = tp->phy_flags & TG3_PHYFLG_EEE_CAP;
11613 tp->phy_flags &= ~TG3_PHYFLG_EEE_CAP;
11615 if (!netif_running(tp->dev)) {
11616 data[0] = TG3_LOOPBACK_FAILED;
11617 data[1] = TG3_LOOPBACK_FAILED;
11619 data[2] = TG3_LOOPBACK_FAILED;
11623 err = tg3_reset_hw(tp, 1);
11625 data[0] = TG3_LOOPBACK_FAILED;
11626 data[1] = TG3_LOOPBACK_FAILED;
11628 data[2] = TG3_LOOPBACK_FAILED;
11632 if (tg3_flag(tp, ENABLE_RSS)) {
11635 /* Reroute all rx packets to the 1st queue */
11636 for (i = MAC_RSS_INDIR_TBL_0;
11637 i < MAC_RSS_INDIR_TBL_0 + TG3_RSS_INDIR_TBL_SIZE; i += 4)
11641 /* HW errata - mac loopback fails in some cases on 5780.
11642 * Normal traffic and PHY loopback are not affected by
11643 * errata. Also, the MAC loopback test is deprecated for
11644 * all newer ASIC revisions.
11646 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5780 &&
11647 !tg3_flag(tp, CPMU_PRESENT)) {
11648 tg3_mac_loopback(tp, true);
11650 if (tg3_run_loopback(tp, ETH_FRAME_LEN, false))
11651 data[0] |= TG3_STD_LOOPBACK_FAILED;
11653 if (tg3_flag(tp, JUMBO_RING_ENABLE) &&
11654 tg3_run_loopback(tp, 9000 + ETH_HLEN, false))
11655 data[0] |= TG3_JMB_LOOPBACK_FAILED;
11657 tg3_mac_loopback(tp, false);
11660 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
11661 !tg3_flag(tp, USE_PHYLIB)) {
11664 tg3_phy_lpbk_set(tp, 0, false);
11666 /* Wait for link */
11667 for (i = 0; i < 100; i++) {
11668 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
11673 if (tg3_run_loopback(tp, ETH_FRAME_LEN, false))
11674 data[1] |= TG3_STD_LOOPBACK_FAILED;
11675 if (tg3_flag(tp, TSO_CAPABLE) &&
11676 tg3_run_loopback(tp, ETH_FRAME_LEN, true))
11677 data[1] |= TG3_TSO_LOOPBACK_FAILED;
11678 if (tg3_flag(tp, JUMBO_RING_ENABLE) &&
11679 tg3_run_loopback(tp, 9000 + ETH_HLEN, false))
11680 data[1] |= TG3_JMB_LOOPBACK_FAILED;
11683 tg3_phy_lpbk_set(tp, 0, true);
11685 /* All link indications report up, but the hardware
11686 * isn't really ready for about 20 msec. Double it
11691 if (tg3_run_loopback(tp, ETH_FRAME_LEN, false))
11692 data[2] |= TG3_STD_LOOPBACK_FAILED;
11693 if (tg3_flag(tp, TSO_CAPABLE) &&
11694 tg3_run_loopback(tp, ETH_FRAME_LEN, true))
11695 data[2] |= TG3_TSO_LOOPBACK_FAILED;
11696 if (tg3_flag(tp, JUMBO_RING_ENABLE) &&
11697 tg3_run_loopback(tp, 9000 + ETH_HLEN, false))
11698 data[2] |= TG3_JMB_LOOPBACK_FAILED;
11701 /* Re-enable gphy autopowerdown. */
11702 if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
11703 tg3_phy_toggle_apd(tp, true);
11706 err = (data[0] | data[1] | data[2]) ? -EIO : 0;
11709 tp->phy_flags |= eee_cap;
11714 static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
11717 struct tg3 *tp = netdev_priv(dev);
11718 bool doextlpbk = etest->flags & ETH_TEST_FL_EXTERNAL_LB;
11720 if ((tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) &&
11721 tg3_power_up(tp)) {
11722 etest->flags |= ETH_TEST_FL_FAILED;
11723 memset(data, 1, sizeof(u64) * TG3_NUM_TEST);
11727 memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
11729 if (tg3_test_nvram(tp) != 0) {
11730 etest->flags |= ETH_TEST_FL_FAILED;
11733 if (!doextlpbk && tg3_test_link(tp)) {
11734 etest->flags |= ETH_TEST_FL_FAILED;
11737 if (etest->flags & ETH_TEST_FL_OFFLINE) {
11738 int err, err2 = 0, irq_sync = 0;
11740 if (netif_running(dev)) {
11742 tg3_netif_stop(tp);
11746 tg3_full_lock(tp, irq_sync);
11748 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
11749 err = tg3_nvram_lock(tp);
11750 tg3_halt_cpu(tp, RX_CPU_BASE);
11751 if (!tg3_flag(tp, 5705_PLUS))
11752 tg3_halt_cpu(tp, TX_CPU_BASE);
11754 tg3_nvram_unlock(tp);
11756 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
11759 if (tg3_test_registers(tp) != 0) {
11760 etest->flags |= ETH_TEST_FL_FAILED;
11764 if (tg3_test_memory(tp) != 0) {
11765 etest->flags |= ETH_TEST_FL_FAILED;
11770 etest->flags |= ETH_TEST_FL_EXTERNAL_LB_DONE;
11772 if (tg3_test_loopback(tp, &data[4], doextlpbk))
11773 etest->flags |= ETH_TEST_FL_FAILED;
11775 tg3_full_unlock(tp);
11777 if (tg3_test_interrupt(tp) != 0) {
11778 etest->flags |= ETH_TEST_FL_FAILED;
11782 tg3_full_lock(tp, 0);
11784 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
11785 if (netif_running(dev)) {
11786 tg3_flag_set(tp, INIT_COMPLETE);
11787 err2 = tg3_restart_hw(tp, 1);
11789 tg3_netif_start(tp);
11792 tg3_full_unlock(tp);
11794 if (irq_sync && !err2)
11797 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
11798 tg3_power_down(tp);
11802 static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
11804 struct mii_ioctl_data *data = if_mii(ifr);
11805 struct tg3 *tp = netdev_priv(dev);
11808 if (tg3_flag(tp, USE_PHYLIB)) {
11809 struct phy_device *phydev;
11810 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
11812 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
11813 return phy_mii_ioctl(phydev, ifr, cmd);
11818 data->phy_id = tp->phy_addr;
11821 case SIOCGMIIREG: {
11824 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
11825 break; /* We have no PHY */
11827 if (!netif_running(dev))
11830 spin_lock_bh(&tp->lock);
11831 err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
11832 spin_unlock_bh(&tp->lock);
11834 data->val_out = mii_regval;
11840 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
11841 break; /* We have no PHY */
11843 if (!netif_running(dev))
11846 spin_lock_bh(&tp->lock);
11847 err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
11848 spin_unlock_bh(&tp->lock);
11856 return -EOPNOTSUPP;
11859 static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
11861 struct tg3 *tp = netdev_priv(dev);
11863 memcpy(ec, &tp->coal, sizeof(*ec));
11867 static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
11869 struct tg3 *tp = netdev_priv(dev);
11870 u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
11871 u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
11873 if (!tg3_flag(tp, 5705_PLUS)) {
11874 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
11875 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
11876 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
11877 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
11880 if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
11881 (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
11882 (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
11883 (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
11884 (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
11885 (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
11886 (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
11887 (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
11888 (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
11889 (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
11892 /* No rx interrupts will be generated if both are zero */
11893 if ((ec->rx_coalesce_usecs == 0) &&
11894 (ec->rx_max_coalesced_frames == 0))
11897 /* No tx interrupts will be generated if both are zero */
11898 if ((ec->tx_coalesce_usecs == 0) &&
11899 (ec->tx_max_coalesced_frames == 0))
11902 /* Only copy relevant parameters, ignore all others. */
11903 tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
11904 tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
11905 tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
11906 tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
11907 tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
11908 tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
11909 tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
11910 tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
11911 tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
11913 if (netif_running(dev)) {
11914 tg3_full_lock(tp, 0);
11915 __tg3_set_coalesce(tp, &tp->coal);
11916 tg3_full_unlock(tp);
11921 static const struct ethtool_ops tg3_ethtool_ops = {
11922 .get_settings = tg3_get_settings,
11923 .set_settings = tg3_set_settings,
11924 .get_drvinfo = tg3_get_drvinfo,
11925 .get_regs_len = tg3_get_regs_len,
11926 .get_regs = tg3_get_regs,
11927 .get_wol = tg3_get_wol,
11928 .set_wol = tg3_set_wol,
11929 .get_msglevel = tg3_get_msglevel,
11930 .set_msglevel = tg3_set_msglevel,
11931 .nway_reset = tg3_nway_reset,
11932 .get_link = ethtool_op_get_link,
11933 .get_eeprom_len = tg3_get_eeprom_len,
11934 .get_eeprom = tg3_get_eeprom,
11935 .set_eeprom = tg3_set_eeprom,
11936 .get_ringparam = tg3_get_ringparam,
11937 .set_ringparam = tg3_set_ringparam,
11938 .get_pauseparam = tg3_get_pauseparam,
11939 .set_pauseparam = tg3_set_pauseparam,
11940 .self_test = tg3_self_test,
11941 .get_strings = tg3_get_strings,
11942 .set_phys_id = tg3_set_phys_id,
11943 .get_ethtool_stats = tg3_get_ethtool_stats,
11944 .get_coalesce = tg3_get_coalesce,
11945 .set_coalesce = tg3_set_coalesce,
11946 .get_sset_count = tg3_get_sset_count,
11949 static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
11951 u32 cursize, val, magic;
11953 tp->nvram_size = EEPROM_CHIP_SIZE;
11955 if (tg3_nvram_read(tp, 0, &magic) != 0)
11958 if ((magic != TG3_EEPROM_MAGIC) &&
11959 ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
11960 ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
11964 * Size the chip by reading offsets at increasing powers of two.
11965 * When we encounter our validation signature, we know the addressing
11966 * has wrapped around, and thus have our chip size.
11970 while (cursize < tp->nvram_size) {
11971 if (tg3_nvram_read(tp, cursize, &val) != 0)
11980 tp->nvram_size = cursize;
11983 static void __devinit tg3_get_nvram_size(struct tg3 *tp)
11987 if (tg3_flag(tp, NO_NVRAM) || tg3_nvram_read(tp, 0, &val) != 0)
11990 /* Selfboot format */
11991 if (val != TG3_EEPROM_MAGIC) {
11992 tg3_get_eeprom_size(tp);
11996 if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
11998 /* This is confusing. We want to operate on the
11999 * 16-bit value at offset 0xf2. The tg3_nvram_read()
12000 * call will read from NVRAM and byteswap the data
12001 * according to the byteswapping settings for all
12002 * other register accesses. This ensures the data we
12003 * want will always reside in the lower 16-bits.
12004 * However, the data in NVRAM is in LE format, which
12005 * means the data from the NVRAM read will always be
12006 * opposite the endianness of the CPU. The 16-bit
12007 * byteswap then brings the data to CPU endianness.
12009 tp->nvram_size = swab16((u16)(val & 0x0000ffff)) * 1024;
12013 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
12016 static void __devinit tg3_get_nvram_info(struct tg3 *tp)
12020 nvcfg1 = tr32(NVRAM_CFG1);
12021 if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
12022 tg3_flag_set(tp, FLASH);
12024 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
12025 tw32(NVRAM_CFG1, nvcfg1);
12028 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
12029 tg3_flag(tp, 5780_CLASS)) {
12030 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
12031 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
12032 tp->nvram_jedecnum = JEDEC_ATMEL;
12033 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
12034 tg3_flag_set(tp, NVRAM_BUFFERED);
12036 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
12037 tp->nvram_jedecnum = JEDEC_ATMEL;
12038 tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
12040 case FLASH_VENDOR_ATMEL_EEPROM:
12041 tp->nvram_jedecnum = JEDEC_ATMEL;
12042 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
12043 tg3_flag_set(tp, NVRAM_BUFFERED);
12045 case FLASH_VENDOR_ST:
12046 tp->nvram_jedecnum = JEDEC_ST;
12047 tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
12048 tg3_flag_set(tp, NVRAM_BUFFERED);
12050 case FLASH_VENDOR_SAIFUN:
12051 tp->nvram_jedecnum = JEDEC_SAIFUN;
12052 tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
12054 case FLASH_VENDOR_SST_SMALL:
12055 case FLASH_VENDOR_SST_LARGE:
12056 tp->nvram_jedecnum = JEDEC_SST;
12057 tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
12061 tp->nvram_jedecnum = JEDEC_ATMEL;
12062 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
12063 tg3_flag_set(tp, NVRAM_BUFFERED);
12067 static void __devinit tg3_nvram_get_pagesize(struct tg3 *tp, u32 nvmcfg1)
12069 switch (nvmcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
12070 case FLASH_5752PAGE_SIZE_256:
12071 tp->nvram_pagesize = 256;
12073 case FLASH_5752PAGE_SIZE_512:
12074 tp->nvram_pagesize = 512;
12076 case FLASH_5752PAGE_SIZE_1K:
12077 tp->nvram_pagesize = 1024;
12079 case FLASH_5752PAGE_SIZE_2K:
12080 tp->nvram_pagesize = 2048;
12082 case FLASH_5752PAGE_SIZE_4K:
12083 tp->nvram_pagesize = 4096;
12085 case FLASH_5752PAGE_SIZE_264:
12086 tp->nvram_pagesize = 264;
12088 case FLASH_5752PAGE_SIZE_528:
12089 tp->nvram_pagesize = 528;
12094 static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
12098 nvcfg1 = tr32(NVRAM_CFG1);
12100 /* NVRAM protection for TPM */
12101 if (nvcfg1 & (1 << 27))
12102 tg3_flag_set(tp, PROTECTED_NVRAM);
12104 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
12105 case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
12106 case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
12107 tp->nvram_jedecnum = JEDEC_ATMEL;
12108 tg3_flag_set(tp, NVRAM_BUFFERED);
12110 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
12111 tp->nvram_jedecnum = JEDEC_ATMEL;
12112 tg3_flag_set(tp, NVRAM_BUFFERED);
12113 tg3_flag_set(tp, FLASH);
12115 case FLASH_5752VENDOR_ST_M45PE10:
12116 case FLASH_5752VENDOR_ST_M45PE20:
12117 case FLASH_5752VENDOR_ST_M45PE40:
12118 tp->nvram_jedecnum = JEDEC_ST;
12119 tg3_flag_set(tp, NVRAM_BUFFERED);
12120 tg3_flag_set(tp, FLASH);
12124 if (tg3_flag(tp, FLASH)) {
12125 tg3_nvram_get_pagesize(tp, nvcfg1);
12127 /* For eeprom, set pagesize to maximum eeprom size */
12128 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
12130 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
12131 tw32(NVRAM_CFG1, nvcfg1);
12135 static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp)
12137 u32 nvcfg1, protect = 0;
12139 nvcfg1 = tr32(NVRAM_CFG1);
12141 /* NVRAM protection for TPM */
12142 if (nvcfg1 & (1 << 27)) {
12143 tg3_flag_set(tp, PROTECTED_NVRAM);
12147 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
12149 case FLASH_5755VENDOR_ATMEL_FLASH_1:
12150 case FLASH_5755VENDOR_ATMEL_FLASH_2:
12151 case FLASH_5755VENDOR_ATMEL_FLASH_3:
12152 case FLASH_5755VENDOR_ATMEL_FLASH_5:
12153 tp->nvram_jedecnum = JEDEC_ATMEL;
12154 tg3_flag_set(tp, NVRAM_BUFFERED);
12155 tg3_flag_set(tp, FLASH);
12156 tp->nvram_pagesize = 264;
12157 if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 ||
12158 nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5)
12159 tp->nvram_size = (protect ? 0x3e200 :
12160 TG3_NVRAM_SIZE_512KB);
12161 else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2)
12162 tp->nvram_size = (protect ? 0x1f200 :
12163 TG3_NVRAM_SIZE_256KB);
12165 tp->nvram_size = (protect ? 0x1f200 :
12166 TG3_NVRAM_SIZE_128KB);
12168 case FLASH_5752VENDOR_ST_M45PE10:
12169 case FLASH_5752VENDOR_ST_M45PE20:
12170 case FLASH_5752VENDOR_ST_M45PE40:
12171 tp->nvram_jedecnum = JEDEC_ST;
12172 tg3_flag_set(tp, NVRAM_BUFFERED);
12173 tg3_flag_set(tp, FLASH);
12174 tp->nvram_pagesize = 256;
12175 if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10)
12176 tp->nvram_size = (protect ?
12177 TG3_NVRAM_SIZE_64KB :
12178 TG3_NVRAM_SIZE_128KB);
12179 else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20)
12180 tp->nvram_size = (protect ?
12181 TG3_NVRAM_SIZE_64KB :
12182 TG3_NVRAM_SIZE_256KB);
12184 tp->nvram_size = (protect ?
12185 TG3_NVRAM_SIZE_128KB :
12186 TG3_NVRAM_SIZE_512KB);
12191 static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp)
12195 nvcfg1 = tr32(NVRAM_CFG1);
12197 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
12198 case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
12199 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
12200 case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
12201 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
12202 tp->nvram_jedecnum = JEDEC_ATMEL;
12203 tg3_flag_set(tp, NVRAM_BUFFERED);
12204 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
12206 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
12207 tw32(NVRAM_CFG1, nvcfg1);
12209 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
12210 case FLASH_5755VENDOR_ATMEL_FLASH_1:
12211 case FLASH_5755VENDOR_ATMEL_FLASH_2:
12212 case FLASH_5755VENDOR_ATMEL_FLASH_3:
12213 tp->nvram_jedecnum = JEDEC_ATMEL;
12214 tg3_flag_set(tp, NVRAM_BUFFERED);
12215 tg3_flag_set(tp, FLASH);
12216 tp->nvram_pagesize = 264;
12218 case FLASH_5752VENDOR_ST_M45PE10:
12219 case FLASH_5752VENDOR_ST_M45PE20:
12220 case FLASH_5752VENDOR_ST_M45PE40:
12221 tp->nvram_jedecnum = JEDEC_ST;
12222 tg3_flag_set(tp, NVRAM_BUFFERED);
12223 tg3_flag_set(tp, FLASH);
12224 tp->nvram_pagesize = 256;
12229 static void __devinit tg3_get_5761_nvram_info(struct tg3 *tp)
12231 u32 nvcfg1, protect = 0;
12233 nvcfg1 = tr32(NVRAM_CFG1);
12235 /* NVRAM protection for TPM */
12236 if (nvcfg1 & (1 << 27)) {
12237 tg3_flag_set(tp, PROTECTED_NVRAM);
12241 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
12243 case FLASH_5761VENDOR_ATMEL_ADB021D:
12244 case FLASH_5761VENDOR_ATMEL_ADB041D:
12245 case FLASH_5761VENDOR_ATMEL_ADB081D:
12246 case FLASH_5761VENDOR_ATMEL_ADB161D:
12247 case FLASH_5761VENDOR_ATMEL_MDB021D:
12248 case FLASH_5761VENDOR_ATMEL_MDB041D:
12249 case FLASH_5761VENDOR_ATMEL_MDB081D:
12250 case FLASH_5761VENDOR_ATMEL_MDB161D:
12251 tp->nvram_jedecnum = JEDEC_ATMEL;
12252 tg3_flag_set(tp, NVRAM_BUFFERED);
12253 tg3_flag_set(tp, FLASH);
12254 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);
12255 tp->nvram_pagesize = 256;
12257 case FLASH_5761VENDOR_ST_A_M45PE20:
12258 case FLASH_5761VENDOR_ST_A_M45PE40:
12259 case FLASH_5761VENDOR_ST_A_M45PE80:
12260 case FLASH_5761VENDOR_ST_A_M45PE16:
12261 case FLASH_5761VENDOR_ST_M_M45PE20:
12262 case FLASH_5761VENDOR_ST_M_M45PE40:
12263 case FLASH_5761VENDOR_ST_M_M45PE80:
12264 case FLASH_5761VENDOR_ST_M_M45PE16:
12265 tp->nvram_jedecnum = JEDEC_ST;
12266 tg3_flag_set(tp, NVRAM_BUFFERED);
12267 tg3_flag_set(tp, FLASH);
12268 tp->nvram_pagesize = 256;
12273 tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT);
12276 case FLASH_5761VENDOR_ATMEL_ADB161D:
12277 case FLASH_5761VENDOR_ATMEL_MDB161D:
12278 case FLASH_5761VENDOR_ST_A_M45PE16:
12279 case FLASH_5761VENDOR_ST_M_M45PE16:
12280 tp->nvram_size = TG3_NVRAM_SIZE_2MB;
12282 case FLASH_5761VENDOR_ATMEL_ADB081D:
12283 case FLASH_5761VENDOR_ATMEL_MDB081D:
12284 case FLASH_5761VENDOR_ST_A_M45PE80:
12285 case FLASH_5761VENDOR_ST_M_M45PE80:
12286 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
12288 case FLASH_5761VENDOR_ATMEL_ADB041D:
12289 case FLASH_5761VENDOR_ATMEL_MDB041D:
12290 case FLASH_5761VENDOR_ST_A_M45PE40:
12291 case FLASH_5761VENDOR_ST_M_M45PE40:
12292 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
12294 case FLASH_5761VENDOR_ATMEL_ADB021D:
12295 case FLASH_5761VENDOR_ATMEL_MDB021D:
12296 case FLASH_5761VENDOR_ST_A_M45PE20:
12297 case FLASH_5761VENDOR_ST_M_M45PE20:
12298 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
12304 static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp)
12306 tp->nvram_jedecnum = JEDEC_ATMEL;
12307 tg3_flag_set(tp, NVRAM_BUFFERED);
12308 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
12311 static void __devinit tg3_get_57780_nvram_info(struct tg3 *tp)
12315 nvcfg1 = tr32(NVRAM_CFG1);
12317 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
12318 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
12319 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
12320 tp->nvram_jedecnum = JEDEC_ATMEL;
12321 tg3_flag_set(tp, NVRAM_BUFFERED);
12322 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
12324 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
12325 tw32(NVRAM_CFG1, nvcfg1);
12327 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
12328 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
12329 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
12330 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
12331 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
12332 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
12333 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
12334 tp->nvram_jedecnum = JEDEC_ATMEL;
12335 tg3_flag_set(tp, NVRAM_BUFFERED);
12336 tg3_flag_set(tp, FLASH);
12338 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
12339 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
12340 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
12341 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
12342 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
12344 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
12345 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
12346 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
12348 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
12349 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
12350 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
12354 case FLASH_5752VENDOR_ST_M45PE10:
12355 case FLASH_5752VENDOR_ST_M45PE20:
12356 case FLASH_5752VENDOR_ST_M45PE40:
12357 tp->nvram_jedecnum = JEDEC_ST;
12358 tg3_flag_set(tp, NVRAM_BUFFERED);
12359 tg3_flag_set(tp, FLASH);
12361 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
12362 case FLASH_5752VENDOR_ST_M45PE10:
12363 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
12365 case FLASH_5752VENDOR_ST_M45PE20:
12366 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
12368 case FLASH_5752VENDOR_ST_M45PE40:
12369 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
12374 tg3_flag_set(tp, NO_NVRAM);
12378 tg3_nvram_get_pagesize(tp, nvcfg1);
12379 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
12380 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);
12384 static void __devinit tg3_get_5717_nvram_info(struct tg3 *tp)
12388 nvcfg1 = tr32(NVRAM_CFG1);
12390 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
12391 case FLASH_5717VENDOR_ATMEL_EEPROM:
12392 case FLASH_5717VENDOR_MICRO_EEPROM:
12393 tp->nvram_jedecnum = JEDEC_ATMEL;
12394 tg3_flag_set(tp, NVRAM_BUFFERED);
12395 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
12397 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
12398 tw32(NVRAM_CFG1, nvcfg1);
12400 case FLASH_5717VENDOR_ATMEL_MDB011D:
12401 case FLASH_5717VENDOR_ATMEL_ADB011B:
12402 case FLASH_5717VENDOR_ATMEL_ADB011D:
12403 case FLASH_5717VENDOR_ATMEL_MDB021D:
12404 case FLASH_5717VENDOR_ATMEL_ADB021B:
12405 case FLASH_5717VENDOR_ATMEL_ADB021D:
12406 case FLASH_5717VENDOR_ATMEL_45USPT:
12407 tp->nvram_jedecnum = JEDEC_ATMEL;
12408 tg3_flag_set(tp, NVRAM_BUFFERED);
12409 tg3_flag_set(tp, FLASH);
12411 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
12412 case FLASH_5717VENDOR_ATMEL_MDB021D:
12413 /* Detect size with tg3_nvram_get_size() */
12415 case FLASH_5717VENDOR_ATMEL_ADB021B:
12416 case FLASH_5717VENDOR_ATMEL_ADB021D:
12417 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
12420 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
12424 case FLASH_5717VENDOR_ST_M_M25PE10:
12425 case FLASH_5717VENDOR_ST_A_M25PE10:
12426 case FLASH_5717VENDOR_ST_M_M45PE10:
12427 case FLASH_5717VENDOR_ST_A_M45PE10:
12428 case FLASH_5717VENDOR_ST_M_M25PE20:
12429 case FLASH_5717VENDOR_ST_A_M25PE20:
12430 case FLASH_5717VENDOR_ST_M_M45PE20:
12431 case FLASH_5717VENDOR_ST_A_M45PE20:
12432 case FLASH_5717VENDOR_ST_25USPT:
12433 case FLASH_5717VENDOR_ST_45USPT:
12434 tp->nvram_jedecnum = JEDEC_ST;
12435 tg3_flag_set(tp, NVRAM_BUFFERED);
12436 tg3_flag_set(tp, FLASH);
12438 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
12439 case FLASH_5717VENDOR_ST_M_M25PE20:
12440 case FLASH_5717VENDOR_ST_M_M45PE20:
12441 /* Detect size with tg3_nvram_get_size() */
12443 case FLASH_5717VENDOR_ST_A_M25PE20:
12444 case FLASH_5717VENDOR_ST_A_M45PE20:
12445 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
12448 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
12453 tg3_flag_set(tp, NO_NVRAM);
12457 tg3_nvram_get_pagesize(tp, nvcfg1);
12458 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
12459 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);
12462 static void __devinit tg3_get_5720_nvram_info(struct tg3 *tp)
12464 u32 nvcfg1, nvmpinstrp;
12466 nvcfg1 = tr32(NVRAM_CFG1);
12467 nvmpinstrp = nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK;
12469 switch (nvmpinstrp) {
12470 case FLASH_5720_EEPROM_HD:
12471 case FLASH_5720_EEPROM_LD:
12472 tp->nvram_jedecnum = JEDEC_ATMEL;
12473 tg3_flag_set(tp, NVRAM_BUFFERED);
12475 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
12476 tw32(NVRAM_CFG1, nvcfg1);
12477 if (nvmpinstrp == FLASH_5720_EEPROM_HD)
12478 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
12480 tp->nvram_pagesize = ATMEL_AT24C02_CHIP_SIZE;
12482 case FLASH_5720VENDOR_M_ATMEL_DB011D:
12483 case FLASH_5720VENDOR_A_ATMEL_DB011B:
12484 case FLASH_5720VENDOR_A_ATMEL_DB011D:
12485 case FLASH_5720VENDOR_M_ATMEL_DB021D:
12486 case FLASH_5720VENDOR_A_ATMEL_DB021B:
12487 case FLASH_5720VENDOR_A_ATMEL_DB021D:
12488 case FLASH_5720VENDOR_M_ATMEL_DB041D:
12489 case FLASH_5720VENDOR_A_ATMEL_DB041B:
12490 case FLASH_5720VENDOR_A_ATMEL_DB041D:
12491 case FLASH_5720VENDOR_M_ATMEL_DB081D:
12492 case FLASH_5720VENDOR_A_ATMEL_DB081D:
12493 case FLASH_5720VENDOR_ATMEL_45USPT:
12494 tp->nvram_jedecnum = JEDEC_ATMEL;
12495 tg3_flag_set(tp, NVRAM_BUFFERED);
12496 tg3_flag_set(tp, FLASH);
12498 switch (nvmpinstrp) {
12499 case FLASH_5720VENDOR_M_ATMEL_DB021D:
12500 case FLASH_5720VENDOR_A_ATMEL_DB021B:
12501 case FLASH_5720VENDOR_A_ATMEL_DB021D:
12502 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
12504 case FLASH_5720VENDOR_M_ATMEL_DB041D:
12505 case FLASH_5720VENDOR_A_ATMEL_DB041B:
12506 case FLASH_5720VENDOR_A_ATMEL_DB041D:
12507 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
12509 case FLASH_5720VENDOR_M_ATMEL_DB081D:
12510 case FLASH_5720VENDOR_A_ATMEL_DB081D:
12511 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
12514 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
12518 case FLASH_5720VENDOR_M_ST_M25PE10:
12519 case FLASH_5720VENDOR_M_ST_M45PE10:
12520 case FLASH_5720VENDOR_A_ST_M25PE10:
12521 case FLASH_5720VENDOR_A_ST_M45PE10:
12522 case FLASH_5720VENDOR_M_ST_M25PE20:
12523 case FLASH_5720VENDOR_M_ST_M45PE20:
12524 case FLASH_5720VENDOR_A_ST_M25PE20:
12525 case FLASH_5720VENDOR_A_ST_M45PE20:
12526 case FLASH_5720VENDOR_M_ST_M25PE40:
12527 case FLASH_5720VENDOR_M_ST_M45PE40:
12528 case FLASH_5720VENDOR_A_ST_M25PE40:
12529 case FLASH_5720VENDOR_A_ST_M45PE40:
12530 case FLASH_5720VENDOR_M_ST_M25PE80:
12531 case FLASH_5720VENDOR_M_ST_M45PE80:
12532 case FLASH_5720VENDOR_A_ST_M25PE80:
12533 case FLASH_5720VENDOR_A_ST_M45PE80:
12534 case FLASH_5720VENDOR_ST_25USPT:
12535 case FLASH_5720VENDOR_ST_45USPT:
12536 tp->nvram_jedecnum = JEDEC_ST;
12537 tg3_flag_set(tp, NVRAM_BUFFERED);
12538 tg3_flag_set(tp, FLASH);
12540 switch (nvmpinstrp) {
12541 case FLASH_5720VENDOR_M_ST_M25PE20:
12542 case FLASH_5720VENDOR_M_ST_M45PE20:
12543 case FLASH_5720VENDOR_A_ST_M25PE20:
12544 case FLASH_5720VENDOR_A_ST_M45PE20:
12545 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
12547 case FLASH_5720VENDOR_M_ST_M25PE40:
12548 case FLASH_5720VENDOR_M_ST_M45PE40:
12549 case FLASH_5720VENDOR_A_ST_M25PE40:
12550 case FLASH_5720VENDOR_A_ST_M45PE40:
12551 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
12553 case FLASH_5720VENDOR_M_ST_M25PE80:
12554 case FLASH_5720VENDOR_M_ST_M45PE80:
12555 case FLASH_5720VENDOR_A_ST_M25PE80:
12556 case FLASH_5720VENDOR_A_ST_M45PE80:
12557 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
12560 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
12565 tg3_flag_set(tp, NO_NVRAM);
12569 tg3_nvram_get_pagesize(tp, nvcfg1);
12570 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
12571 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);
12574 /* Chips other than 5700/5701 use the NVRAM for fetching info. */
12575 static void __devinit tg3_nvram_init(struct tg3 *tp)
12577 tw32_f(GRC_EEPROM_ADDR,
12578 (EEPROM_ADDR_FSM_RESET |
12579 (EEPROM_DEFAULT_CLOCK_PERIOD <<
12580 EEPROM_ADDR_CLKPERD_SHIFT)));
12584 /* Enable seeprom accesses. */
12585 tw32_f(GRC_LOCAL_CTRL,
12586 tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
12589 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
12590 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
12591 tg3_flag_set(tp, NVRAM);
12593 if (tg3_nvram_lock(tp)) {
12594 netdev_warn(tp->dev,
12595 "Cannot get nvram lock, %s failed\n",
12599 tg3_enable_nvram_access(tp);
12601 tp->nvram_size = 0;
12603 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
12604 tg3_get_5752_nvram_info(tp);
12605 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
12606 tg3_get_5755_nvram_info(tp);
12607 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
12608 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
12609 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
12610 tg3_get_5787_nvram_info(tp);
12611 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
12612 tg3_get_5761_nvram_info(tp);
12613 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12614 tg3_get_5906_nvram_info(tp);
12615 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
12616 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
12617 tg3_get_57780_nvram_info(tp);
12618 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
12619 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
12620 tg3_get_5717_nvram_info(tp);
12621 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720)
12622 tg3_get_5720_nvram_info(tp);
12624 tg3_get_nvram_info(tp);
12626 if (tp->nvram_size == 0)
12627 tg3_get_nvram_size(tp);
12629 tg3_disable_nvram_access(tp);
12630 tg3_nvram_unlock(tp);
12633 tg3_flag_clear(tp, NVRAM);
12634 tg3_flag_clear(tp, NVRAM_BUFFERED);
12636 tg3_get_eeprom_size(tp);
12640 static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
12641 u32 offset, u32 len, u8 *buf)
12646 for (i = 0; i < len; i += 4) {
12652 memcpy(&data, buf + i, 4);
12655 * The SEEPROM interface expects the data to always be opposite
12656 * the native endian format. We accomplish this by reversing
12657 * all the operations that would have been performed on the
12658 * data from a call to tg3_nvram_read_be32().
12660 tw32(GRC_EEPROM_DATA, swab32(be32_to_cpu(data)));
12662 val = tr32(GRC_EEPROM_ADDR);
12663 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
12665 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
12667 tw32(GRC_EEPROM_ADDR, val |
12668 (0 << EEPROM_ADDR_DEVID_SHIFT) |
12669 (addr & EEPROM_ADDR_ADDR_MASK) |
12670 EEPROM_ADDR_START |
12671 EEPROM_ADDR_WRITE);
12673 for (j = 0; j < 1000; j++) {
12674 val = tr32(GRC_EEPROM_ADDR);
12676 if (val & EEPROM_ADDR_COMPLETE)
12680 if (!(val & EEPROM_ADDR_COMPLETE)) {
12689 /* offset and length are dword aligned */
12690 static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
12694 u32 pagesize = tp->nvram_pagesize;
12695 u32 pagemask = pagesize - 1;
12699 tmp = kmalloc(pagesize, GFP_KERNEL);
12705 u32 phy_addr, page_off, size;
12707 phy_addr = offset & ~pagemask;
12709 for (j = 0; j < pagesize; j += 4) {
12710 ret = tg3_nvram_read_be32(tp, phy_addr + j,
12711 (__be32 *) (tmp + j));
12718 page_off = offset & pagemask;
12725 memcpy(tmp + page_off, buf, size);
12727 offset = offset + (pagesize - page_off);
12729 tg3_enable_nvram_access(tp);
12732 * Before we can erase the flash page, we need
12733 * to issue a special "write enable" command.
12735 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
12737 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
12740 /* Erase the target page */
12741 tw32(NVRAM_ADDR, phy_addr);
12743 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
12744 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
12746 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
12749 /* Issue another write enable to start the write. */
12750 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
12752 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
12755 for (j = 0; j < pagesize; j += 4) {
12758 data = *((__be32 *) (tmp + j));
12760 tw32(NVRAM_WRDATA, be32_to_cpu(data));
12762 tw32(NVRAM_ADDR, phy_addr + j);
12764 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
12768 nvram_cmd |= NVRAM_CMD_FIRST;
12769 else if (j == (pagesize - 4))
12770 nvram_cmd |= NVRAM_CMD_LAST;
12772 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
12779 nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
12780 tg3_nvram_exec_cmd(tp, nvram_cmd);
12787 /* offset and length are dword aligned */
12788 static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
12793 for (i = 0; i < len; i += 4, offset += 4) {
12794 u32 page_off, phy_addr, nvram_cmd;
12797 memcpy(&data, buf + i, 4);
12798 tw32(NVRAM_WRDATA, be32_to_cpu(data));
12800 page_off = offset % tp->nvram_pagesize;
12802 phy_addr = tg3_nvram_phys_addr(tp, offset);
12804 tw32(NVRAM_ADDR, phy_addr);
12806 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
12808 if (page_off == 0 || i == 0)
12809 nvram_cmd |= NVRAM_CMD_FIRST;
12810 if (page_off == (tp->nvram_pagesize - 4))
12811 nvram_cmd |= NVRAM_CMD_LAST;
12813 if (i == (len - 4))
12814 nvram_cmd |= NVRAM_CMD_LAST;
12816 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 &&
12817 !tg3_flag(tp, 5755_PLUS) &&
12818 (tp->nvram_jedecnum == JEDEC_ST) &&
12819 (nvram_cmd & NVRAM_CMD_FIRST)) {
12821 if ((ret = tg3_nvram_exec_cmd(tp,
12822 NVRAM_CMD_WREN | NVRAM_CMD_GO |
12827 if (!tg3_flag(tp, FLASH)) {
12828 /* We always do complete word writes to eeprom. */
12829 nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
12832 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
12838 /* offset and length are dword aligned */
12839 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
12843 if (tg3_flag(tp, EEPROM_WRITE_PROT)) {
12844 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
12845 ~GRC_LCLCTRL_GPIO_OUTPUT1);
12849 if (!tg3_flag(tp, NVRAM)) {
12850 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
12854 ret = tg3_nvram_lock(tp);
12858 tg3_enable_nvram_access(tp);
12859 if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM))
12860 tw32(NVRAM_WRITE1, 0x406);
12862 grc_mode = tr32(GRC_MODE);
12863 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
12865 if (tg3_flag(tp, NVRAM_BUFFERED) || !tg3_flag(tp, FLASH)) {
12866 ret = tg3_nvram_write_block_buffered(tp, offset, len,
12869 ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
12873 grc_mode = tr32(GRC_MODE);
12874 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
12876 tg3_disable_nvram_access(tp);
12877 tg3_nvram_unlock(tp);
12880 if (tg3_flag(tp, EEPROM_WRITE_PROT)) {
12881 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
12888 struct subsys_tbl_ent {
12889 u16 subsys_vendor, subsys_devid;
12893 static struct subsys_tbl_ent subsys_id_to_phy_id[] __devinitdata = {
12894 /* Broadcom boards. */
12895 { TG3PCI_SUBVENDOR_ID_BROADCOM,
12896 TG3PCI_SUBDEVICE_ID_BROADCOM_95700A6, TG3_PHY_ID_BCM5401 },
12897 { TG3PCI_SUBVENDOR_ID_BROADCOM,
12898 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A5, TG3_PHY_ID_BCM5701 },
12899 { TG3PCI_SUBVENDOR_ID_BROADCOM,
12900 TG3PCI_SUBDEVICE_ID_BROADCOM_95700T6, TG3_PHY_ID_BCM8002 },
12901 { TG3PCI_SUBVENDOR_ID_BROADCOM,
12902 TG3PCI_SUBDEVICE_ID_BROADCOM_95700A9, 0 },
12903 { TG3PCI_SUBVENDOR_ID_BROADCOM,
12904 TG3PCI_SUBDEVICE_ID_BROADCOM_95701T1, TG3_PHY_ID_BCM5701 },
12905 { TG3PCI_SUBVENDOR_ID_BROADCOM,
12906 TG3PCI_SUBDEVICE_ID_BROADCOM_95701T8, TG3_PHY_ID_BCM5701 },
12907 { TG3PCI_SUBVENDOR_ID_BROADCOM,
12908 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A7, 0 },
12909 { TG3PCI_SUBVENDOR_ID_BROADCOM,
12910 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A10, TG3_PHY_ID_BCM5701 },
12911 { TG3PCI_SUBVENDOR_ID_BROADCOM,
12912 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A12, TG3_PHY_ID_BCM5701 },
12913 { TG3PCI_SUBVENDOR_ID_BROADCOM,
12914 TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX1, TG3_PHY_ID_BCM5703 },
12915 { TG3PCI_SUBVENDOR_ID_BROADCOM,
12916 TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX2, TG3_PHY_ID_BCM5703 },
12919 { TG3PCI_SUBVENDOR_ID_3COM,
12920 TG3PCI_SUBDEVICE_ID_3COM_3C996T, TG3_PHY_ID_BCM5401 },
12921 { TG3PCI_SUBVENDOR_ID_3COM,
12922 TG3PCI_SUBDEVICE_ID_3COM_3C996BT, TG3_PHY_ID_BCM5701 },
12923 { TG3PCI_SUBVENDOR_ID_3COM,
12924 TG3PCI_SUBDEVICE_ID_3COM_3C996SX, 0 },
12925 { TG3PCI_SUBVENDOR_ID_3COM,
12926 TG3PCI_SUBDEVICE_ID_3COM_3C1000T, TG3_PHY_ID_BCM5701 },
12927 { TG3PCI_SUBVENDOR_ID_3COM,
12928 TG3PCI_SUBDEVICE_ID_3COM_3C940BR01, TG3_PHY_ID_BCM5701 },
12931 { TG3PCI_SUBVENDOR_ID_DELL,
12932 TG3PCI_SUBDEVICE_ID_DELL_VIPER, TG3_PHY_ID_BCM5401 },
12933 { TG3PCI_SUBVENDOR_ID_DELL,
12934 TG3PCI_SUBDEVICE_ID_DELL_JAGUAR, TG3_PHY_ID_BCM5401 },
12935 { TG3PCI_SUBVENDOR_ID_DELL,
12936 TG3PCI_SUBDEVICE_ID_DELL_MERLOT, TG3_PHY_ID_BCM5411 },
12937 { TG3PCI_SUBVENDOR_ID_DELL,
12938 TG3PCI_SUBDEVICE_ID_DELL_SLIM_MERLOT, TG3_PHY_ID_BCM5411 },
12940 /* Compaq boards. */
12941 { TG3PCI_SUBVENDOR_ID_COMPAQ,
12942 TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE, TG3_PHY_ID_BCM5701 },
12943 { TG3PCI_SUBVENDOR_ID_COMPAQ,
12944 TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE_2, TG3_PHY_ID_BCM5701 },
12945 { TG3PCI_SUBVENDOR_ID_COMPAQ,
12946 TG3PCI_SUBDEVICE_ID_COMPAQ_CHANGELING, 0 },
12947 { TG3PCI_SUBVENDOR_ID_COMPAQ,
12948 TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780, TG3_PHY_ID_BCM5701 },
12949 { TG3PCI_SUBVENDOR_ID_COMPAQ,
12950 TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780_2, TG3_PHY_ID_BCM5701 },
12953 { TG3PCI_SUBVENDOR_ID_IBM,
12954 TG3PCI_SUBDEVICE_ID_IBM_5703SAX2, 0 }
12957 static struct subsys_tbl_ent * __devinit tg3_lookup_by_subsys(struct tg3 *tp)
12961 for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
12962 if ((subsys_id_to_phy_id[i].subsys_vendor ==
12963 tp->pdev->subsystem_vendor) &&
12964 (subsys_id_to_phy_id[i].subsys_devid ==
12965 tp->pdev->subsystem_device))
12966 return &subsys_id_to_phy_id[i];
12971 static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
12975 tp->phy_id = TG3_PHY_ID_INVALID;
12976 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12978 /* Assume an onboard device and WOL capable by default. */
12979 tg3_flag_set(tp, EEPROM_WRITE_PROT);
12980 tg3_flag_set(tp, WOL_CAP);
12982 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
12983 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
12984 tg3_flag_clear(tp, EEPROM_WRITE_PROT);
12985 tg3_flag_set(tp, IS_NIC);
12987 val = tr32(VCPU_CFGSHDW);
12988 if (val & VCPU_CFGSHDW_ASPM_DBNC)
12989 tg3_flag_set(tp, ASPM_WORKAROUND);
12990 if ((val & VCPU_CFGSHDW_WOL_ENABLE) &&
12991 (val & VCPU_CFGSHDW_WOL_MAGPKT)) {
12992 tg3_flag_set(tp, WOL_ENABLE);
12993 device_set_wakeup_enable(&tp->pdev->dev, true);
12998 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
12999 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
13000 u32 nic_cfg, led_cfg;
13001 u32 nic_phy_id, ver, cfg2 = 0, cfg4 = 0, eeprom_phy_id;
13002 int eeprom_phy_serdes = 0;
13004 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
13005 tp->nic_sram_data_cfg = nic_cfg;
13007 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
13008 ver >>= NIC_SRAM_DATA_VER_SHIFT;
13009 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13010 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
13011 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703 &&
13012 (ver > 0) && (ver < 0x100))
13013 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
13015 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
13016 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4);
13018 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
13019 NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
13020 eeprom_phy_serdes = 1;
13022 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
13023 if (nic_phy_id != 0) {
13024 u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
13025 u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
13027 eeprom_phy_id = (id1 >> 16) << 10;
13028 eeprom_phy_id |= (id2 & 0xfc00) << 16;
13029 eeprom_phy_id |= (id2 & 0x03ff) << 0;
13033 tp->phy_id = eeprom_phy_id;
13034 if (eeprom_phy_serdes) {
13035 if (!tg3_flag(tp, 5705_PLUS))
13036 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
13038 tp->phy_flags |= TG3_PHYFLG_MII_SERDES;
13041 if (tg3_flag(tp, 5750_PLUS))
13042 led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
13043 SHASTA_EXT_LED_MODE_MASK);
13045 led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
13049 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
13050 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
13053 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
13054 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
13057 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
13058 tp->led_ctrl = LED_CTRL_MODE_MAC;
13060 /* Default to PHY_1_MODE if 0 (MAC_MODE) is
13061 * read on some older 5700/5701 bootcode.
13063 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
13065 GET_ASIC_REV(tp->pci_chip_rev_id) ==
13067 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
13071 case SHASTA_EXT_LED_SHARED:
13072 tp->led_ctrl = LED_CTRL_MODE_SHARED;
13073 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
13074 tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)
13075 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
13076 LED_CTRL_MODE_PHY_2);
13079 case SHASTA_EXT_LED_MAC:
13080 tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
13083 case SHASTA_EXT_LED_COMBO:
13084 tp->led_ctrl = LED_CTRL_MODE_COMBO;
13085 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)
13086 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
13087 LED_CTRL_MODE_PHY_2);
13092 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13093 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
13094 tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
13095 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
13097 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX)
13098 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
13100 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
13101 tg3_flag_set(tp, EEPROM_WRITE_PROT);
13102 if ((tp->pdev->subsystem_vendor ==
13103 PCI_VENDOR_ID_ARIMA) &&
13104 (tp->pdev->subsystem_device == 0x205a ||
13105 tp->pdev->subsystem_device == 0x2063))
13106 tg3_flag_clear(tp, EEPROM_WRITE_PROT);
13108 tg3_flag_clear(tp, EEPROM_WRITE_PROT);
13109 tg3_flag_set(tp, IS_NIC);
13112 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
13113 tg3_flag_set(tp, ENABLE_ASF);
13114 if (tg3_flag(tp, 5750_PLUS))
13115 tg3_flag_set(tp, ASF_NEW_HANDSHAKE);
13118 if ((nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE) &&
13119 tg3_flag(tp, 5750_PLUS))
13120 tg3_flag_set(tp, ENABLE_APE);
13122 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES &&
13123 !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL))
13124 tg3_flag_clear(tp, WOL_CAP);
13126 if (tg3_flag(tp, WOL_CAP) &&
13127 (nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE)) {
13128 tg3_flag_set(tp, WOL_ENABLE);
13129 device_set_wakeup_enable(&tp->pdev->dev, true);
13132 if (cfg2 & (1 << 17))
13133 tp->phy_flags |= TG3_PHYFLG_CAPACITIVE_COUPLING;
13135 /* serdes signal pre-emphasis in register 0x590 set by */
13136 /* bootcode if bit 18 is set */
13137 if (cfg2 & (1 << 18))
13138 tp->phy_flags |= TG3_PHYFLG_SERDES_PREEMPHASIS;
13140 if ((tg3_flag(tp, 57765_PLUS) ||
13141 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
13142 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX)) &&
13143 (cfg2 & NIC_SRAM_DATA_CFG_2_APD_EN))
13144 tp->phy_flags |= TG3_PHYFLG_ENABLE_APD;
13146 if (tg3_flag(tp, PCI_EXPRESS) &&
13147 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
13148 !tg3_flag(tp, 57765_PLUS)) {
13151 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3);
13152 if (cfg3 & NIC_SRAM_ASPM_DEBOUNCE)
13153 tg3_flag_set(tp, ASPM_WORKAROUND);
13156 if (cfg4 & NIC_SRAM_RGMII_INBAND_DISABLE)
13157 tg3_flag_set(tp, RGMII_INBAND_DISABLE);
13158 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_RX_EN)
13159 tg3_flag_set(tp, RGMII_EXT_IBND_RX_EN);
13160 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_TX_EN)
13161 tg3_flag_set(tp, RGMII_EXT_IBND_TX_EN);
13164 if (tg3_flag(tp, WOL_CAP))
13165 device_set_wakeup_enable(&tp->pdev->dev,
13166 tg3_flag(tp, WOL_ENABLE));
13168 device_set_wakeup_capable(&tp->pdev->dev, false);
13171 static int __devinit tg3_issue_otp_command(struct tg3 *tp, u32 cmd)
13176 tw32(OTP_CTRL, cmd | OTP_CTRL_OTP_CMD_START);
13177 tw32(OTP_CTRL, cmd);
13179 /* Wait for up to 1 ms for command to execute. */
13180 for (i = 0; i < 100; i++) {
13181 val = tr32(OTP_STATUS);
13182 if (val & OTP_STATUS_CMD_DONE)
13187 return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY;
13190 /* Read the gphy configuration from the OTP region of the chip. The gphy
13191 * configuration is a 32-bit value that straddles the alignment boundary.
13192 * We do two 32-bit reads and then shift and merge the results.
13194 static u32 __devinit tg3_read_otp_phycfg(struct tg3 *tp)
13196 u32 bhalf_otp, thalf_otp;
13198 tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC);
13200 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT))
13203 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1);
13205 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
13208 thalf_otp = tr32(OTP_READ_DATA);
13210 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2);
13212 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
13215 bhalf_otp = tr32(OTP_READ_DATA);
13217 return ((thalf_otp & 0x0000ffff) << 16) | (bhalf_otp >> 16);
13220 static void __devinit tg3_phy_init_link_config(struct tg3 *tp)
13222 u32 adv = ADVERTISED_Autoneg |
13225 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
13226 adv |= ADVERTISED_1000baseT_Half |
13227 ADVERTISED_1000baseT_Full;
13229 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
13230 adv |= ADVERTISED_100baseT_Half |
13231 ADVERTISED_100baseT_Full |
13232 ADVERTISED_10baseT_Half |
13233 ADVERTISED_10baseT_Full |
13236 adv |= ADVERTISED_FIBRE;
13238 tp->link_config.advertising = adv;
13239 tp->link_config.speed = SPEED_INVALID;
13240 tp->link_config.duplex = DUPLEX_INVALID;
13241 tp->link_config.autoneg = AUTONEG_ENABLE;
13242 tp->link_config.active_speed = SPEED_INVALID;
13243 tp->link_config.active_duplex = DUPLEX_INVALID;
13244 tp->link_config.orig_speed = SPEED_INVALID;
13245 tp->link_config.orig_duplex = DUPLEX_INVALID;
13246 tp->link_config.orig_autoneg = AUTONEG_INVALID;
13249 static int __devinit tg3_phy_probe(struct tg3 *tp)
13251 u32 hw_phy_id_1, hw_phy_id_2;
13252 u32 hw_phy_id, hw_phy_id_masked;
13255 /* flow control autonegotiation is default behavior */
13256 tg3_flag_set(tp, PAUSE_AUTONEG);
13257 tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
13259 if (tg3_flag(tp, USE_PHYLIB))
13260 return tg3_phy_init(tp);
13262 /* Reading the PHY ID register can conflict with ASF
13263 * firmware access to the PHY hardware.
13266 if (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE)) {
13267 hw_phy_id = hw_phy_id_masked = TG3_PHY_ID_INVALID;
13269 /* Now read the physical PHY_ID from the chip and verify
13270 * that it is sane. If it doesn't look good, we fall back
13271 * to either the hard-coded table based PHY_ID and failing
13272 * that the value found in the eeprom area.
13274 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
13275 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
13277 hw_phy_id = (hw_phy_id_1 & 0xffff) << 10;
13278 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
13279 hw_phy_id |= (hw_phy_id_2 & 0x03ff) << 0;
13281 hw_phy_id_masked = hw_phy_id & TG3_PHY_ID_MASK;
13284 if (!err && TG3_KNOWN_PHY_ID(hw_phy_id_masked)) {
13285 tp->phy_id = hw_phy_id;
13286 if (hw_phy_id_masked == TG3_PHY_ID_BCM8002)
13287 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
13289 tp->phy_flags &= ~TG3_PHYFLG_PHY_SERDES;
13291 if (tp->phy_id != TG3_PHY_ID_INVALID) {
13292 /* Do nothing, phy ID already set up in
13293 * tg3_get_eeprom_hw_cfg().
13296 struct subsys_tbl_ent *p;
13298 /* No eeprom signature? Try the hardcoded
13299 * subsys device table.
13301 p = tg3_lookup_by_subsys(tp);
13305 tp->phy_id = p->phy_id;
13307 tp->phy_id == TG3_PHY_ID_BCM8002)
13308 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
13312 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) &&
13313 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
13314 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720 ||
13315 (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 &&
13316 tp->pci_chip_rev_id != CHIPREV_ID_5717_A0) ||
13317 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
13318 tp->pci_chip_rev_id != CHIPREV_ID_57765_A0)))
13319 tp->phy_flags |= TG3_PHYFLG_EEE_CAP;
13321 tg3_phy_init_link_config(tp);
13323 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) &&
13324 !tg3_flag(tp, ENABLE_APE) &&
13325 !tg3_flag(tp, ENABLE_ASF)) {
13328 tg3_readphy(tp, MII_BMSR, &bmsr);
13329 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
13330 (bmsr & BMSR_LSTATUS))
13331 goto skip_phy_reset;
13333 err = tg3_phy_reset(tp);
13337 tg3_phy_set_wirespeed(tp);
13339 mask = (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
13340 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
13341 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full);
13342 if (!tg3_copper_is_advertising_all(tp, mask)) {
13343 tg3_phy_autoneg_cfg(tp, tp->link_config.advertising,
13344 tp->link_config.flowctrl);
13346 tg3_writephy(tp, MII_BMCR,
13347 BMCR_ANENABLE | BMCR_ANRESTART);
13352 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
13353 err = tg3_init_5401phy_dsp(tp);
13357 err = tg3_init_5401phy_dsp(tp);
13363 static void __devinit tg3_read_vpd(struct tg3 *tp)
13366 unsigned int block_end, rosize, len;
13370 vpd_data = (u8 *)tg3_vpd_readblock(tp, &vpdlen);
13374 i = pci_vpd_find_tag(vpd_data, 0, vpdlen, PCI_VPD_LRDT_RO_DATA);
13376 goto out_not_found;
13378 rosize = pci_vpd_lrdt_size(&vpd_data[i]);
13379 block_end = i + PCI_VPD_LRDT_TAG_SIZE + rosize;
13380 i += PCI_VPD_LRDT_TAG_SIZE;
13382 if (block_end > vpdlen)
13383 goto out_not_found;
13385 j = pci_vpd_find_info_keyword(vpd_data, i, rosize,
13386 PCI_VPD_RO_KEYWORD_MFR_ID);
13388 len = pci_vpd_info_field_size(&vpd_data[j]);
13390 j += PCI_VPD_INFO_FLD_HDR_SIZE;
13391 if (j + len > block_end || len != 4 ||
13392 memcmp(&vpd_data[j], "1028", 4))
13395 j = pci_vpd_find_info_keyword(vpd_data, i, rosize,
13396 PCI_VPD_RO_KEYWORD_VENDOR0);
13400 len = pci_vpd_info_field_size(&vpd_data[j]);
13402 j += PCI_VPD_INFO_FLD_HDR_SIZE;
13403 if (j + len > block_end)
13406 memcpy(tp->fw_ver, &vpd_data[j], len);
13407 strncat(tp->fw_ver, " bc ", vpdlen - len - 1);
13411 i = pci_vpd_find_info_keyword(vpd_data, i, rosize,
13412 PCI_VPD_RO_KEYWORD_PARTNO);
13414 goto out_not_found;
13416 len = pci_vpd_info_field_size(&vpd_data[i]);
13418 i += PCI_VPD_INFO_FLD_HDR_SIZE;
13419 if (len > TG3_BPN_SIZE ||
13420 (len + i) > vpdlen)
13421 goto out_not_found;
13423 memcpy(tp->board_part_number, &vpd_data[i], len);
13427 if (tp->board_part_number[0])
13431 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
13432 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717)
13433 strcpy(tp->board_part_number, "BCM5717");
13434 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718)
13435 strcpy(tp->board_part_number, "BCM5718");
13438 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
13439 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57780)
13440 strcpy(tp->board_part_number, "BCM57780");
13441 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57760)
13442 strcpy(tp->board_part_number, "BCM57760");
13443 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790)
13444 strcpy(tp->board_part_number, "BCM57790");
13445 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57788)
13446 strcpy(tp->board_part_number, "BCM57788");
13449 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
13450 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761)
13451 strcpy(tp->board_part_number, "BCM57761");
13452 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765)
13453 strcpy(tp->board_part_number, "BCM57765");
13454 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781)
13455 strcpy(tp->board_part_number, "BCM57781");
13456 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785)
13457 strcpy(tp->board_part_number, "BCM57785");
13458 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791)
13459 strcpy(tp->board_part_number, "BCM57791");
13460 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795)
13461 strcpy(tp->board_part_number, "BCM57795");
13464 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
13465 strcpy(tp->board_part_number, "BCM95906");
13468 strcpy(tp->board_part_number, "none");
13472 static int __devinit tg3_fw_img_is_valid(struct tg3 *tp, u32 offset)
13476 if (tg3_nvram_read(tp, offset, &val) ||
13477 (val & 0xfc000000) != 0x0c000000 ||
13478 tg3_nvram_read(tp, offset + 4, &val) ||
13485 static void __devinit tg3_read_bc_ver(struct tg3 *tp)
13487 u32 val, offset, start, ver_offset;
13489 bool newver = false;
13491 if (tg3_nvram_read(tp, 0xc, &offset) ||
13492 tg3_nvram_read(tp, 0x4, &start))
13495 offset = tg3_nvram_logical_addr(tp, offset);
13497 if (tg3_nvram_read(tp, offset, &val))
13500 if ((val & 0xfc000000) == 0x0c000000) {
13501 if (tg3_nvram_read(tp, offset + 4, &val))
13508 dst_off = strlen(tp->fw_ver);
13511 if (TG3_VER_SIZE - dst_off < 16 ||
13512 tg3_nvram_read(tp, offset + 8, &ver_offset))
13515 offset = offset + ver_offset - start;
13516 for (i = 0; i < 16; i += 4) {
13518 if (tg3_nvram_read_be32(tp, offset + i, &v))
13521 memcpy(tp->fw_ver + dst_off + i, &v, sizeof(v));
13526 if (tg3_nvram_read(tp, TG3_NVM_PTREV_BCVER, &ver_offset))
13529 major = (ver_offset & TG3_NVM_BCVER_MAJMSK) >>
13530 TG3_NVM_BCVER_MAJSFT;
13531 minor = ver_offset & TG3_NVM_BCVER_MINMSK;
13532 snprintf(&tp->fw_ver[dst_off], TG3_VER_SIZE - dst_off,
13533 "v%d.%02d", major, minor);
13537 static void __devinit tg3_read_hwsb_ver(struct tg3 *tp)
13539 u32 val, major, minor;
13541 /* Use native endian representation */
13542 if (tg3_nvram_read(tp, TG3_NVM_HWSB_CFG1, &val))
13545 major = (val & TG3_NVM_HWSB_CFG1_MAJMSK) >>
13546 TG3_NVM_HWSB_CFG1_MAJSFT;
13547 minor = (val & TG3_NVM_HWSB_CFG1_MINMSK) >>
13548 TG3_NVM_HWSB_CFG1_MINSFT;
13550 snprintf(&tp->fw_ver[0], 32, "sb v%d.%02d", major, minor);
13553 static void __devinit tg3_read_sb_ver(struct tg3 *tp, u32 val)
13555 u32 offset, major, minor, build;
13557 strncat(tp->fw_ver, "sb", TG3_VER_SIZE - strlen(tp->fw_ver) - 1);
13559 if ((val & TG3_EEPROM_SB_FORMAT_MASK) != TG3_EEPROM_SB_FORMAT_1)
13562 switch (val & TG3_EEPROM_SB_REVISION_MASK) {
13563 case TG3_EEPROM_SB_REVISION_0:
13564 offset = TG3_EEPROM_SB_F1R0_EDH_OFF;
13566 case TG3_EEPROM_SB_REVISION_2:
13567 offset = TG3_EEPROM_SB_F1R2_EDH_OFF;
13569 case TG3_EEPROM_SB_REVISION_3:
13570 offset = TG3_EEPROM_SB_F1R3_EDH_OFF;
13572 case TG3_EEPROM_SB_REVISION_4:
13573 offset = TG3_EEPROM_SB_F1R4_EDH_OFF;
13575 case TG3_EEPROM_SB_REVISION_5:
13576 offset = TG3_EEPROM_SB_F1R5_EDH_OFF;
13578 case TG3_EEPROM_SB_REVISION_6:
13579 offset = TG3_EEPROM_SB_F1R6_EDH_OFF;
13585 if (tg3_nvram_read(tp, offset, &val))
13588 build = (val & TG3_EEPROM_SB_EDH_BLD_MASK) >>
13589 TG3_EEPROM_SB_EDH_BLD_SHFT;
13590 major = (val & TG3_EEPROM_SB_EDH_MAJ_MASK) >>
13591 TG3_EEPROM_SB_EDH_MAJ_SHFT;
13592 minor = val & TG3_EEPROM_SB_EDH_MIN_MASK;
13594 if (minor > 99 || build > 26)
13597 offset = strlen(tp->fw_ver);
13598 snprintf(&tp->fw_ver[offset], TG3_VER_SIZE - offset,
13599 " v%d.%02d", major, minor);
13602 offset = strlen(tp->fw_ver);
13603 if (offset < TG3_VER_SIZE - 1)
13604 tp->fw_ver[offset] = 'a' + build - 1;
13608 static void __devinit tg3_read_mgmtfw_ver(struct tg3 *tp)
13610 u32 val, offset, start;
13613 for (offset = TG3_NVM_DIR_START;
13614 offset < TG3_NVM_DIR_END;
13615 offset += TG3_NVM_DIRENT_SIZE) {
13616 if (tg3_nvram_read(tp, offset, &val))
13619 if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI)
13623 if (offset == TG3_NVM_DIR_END)
13626 if (!tg3_flag(tp, 5705_PLUS))
13627 start = 0x08000000;
13628 else if (tg3_nvram_read(tp, offset - 4, &start))
13631 if (tg3_nvram_read(tp, offset + 4, &offset) ||
13632 !tg3_fw_img_is_valid(tp, offset) ||
13633 tg3_nvram_read(tp, offset + 8, &val))
13636 offset += val - start;
13638 vlen = strlen(tp->fw_ver);
13640 tp->fw_ver[vlen++] = ',';
13641 tp->fw_ver[vlen++] = ' ';
13643 for (i = 0; i < 4; i++) {
13645 if (tg3_nvram_read_be32(tp, offset, &v))
13648 offset += sizeof(v);
13650 if (vlen > TG3_VER_SIZE - sizeof(v)) {
13651 memcpy(&tp->fw_ver[vlen], &v, TG3_VER_SIZE - vlen);
13655 memcpy(&tp->fw_ver[vlen], &v, sizeof(v));
13660 static void __devinit tg3_read_dash_ver(struct tg3 *tp)
13666 if (!tg3_flag(tp, ENABLE_APE) || !tg3_flag(tp, ENABLE_ASF))
13669 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
13670 if (apedata != APE_SEG_SIG_MAGIC)
13673 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
13674 if (!(apedata & APE_FW_STATUS_READY))
13677 apedata = tg3_ape_read32(tp, TG3_APE_FW_VERSION);
13679 if (tg3_ape_read32(tp, TG3_APE_FW_FEATURES) & TG3_APE_FW_FEATURE_NCSI) {
13680 tg3_flag_set(tp, APE_HAS_NCSI);
13686 vlen = strlen(tp->fw_ver);
13688 snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " %s v%d.%d.%d.%d",
13690 (apedata & APE_FW_VERSION_MAJMSK) >> APE_FW_VERSION_MAJSFT,
13691 (apedata & APE_FW_VERSION_MINMSK) >> APE_FW_VERSION_MINSFT,
13692 (apedata & APE_FW_VERSION_REVMSK) >> APE_FW_VERSION_REVSFT,
13693 (apedata & APE_FW_VERSION_BLDMSK));
13696 static void __devinit tg3_read_fw_ver(struct tg3 *tp)
13699 bool vpd_vers = false;
13701 if (tp->fw_ver[0] != 0)
13704 if (tg3_flag(tp, NO_NVRAM)) {
13705 strcat(tp->fw_ver, "sb");
13709 if (tg3_nvram_read(tp, 0, &val))
13712 if (val == TG3_EEPROM_MAGIC)
13713 tg3_read_bc_ver(tp);
13714 else if ((val & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW)
13715 tg3_read_sb_ver(tp, val);
13716 else if ((val & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
13717 tg3_read_hwsb_ver(tp);
13724 if (tg3_flag(tp, ENABLE_APE)) {
13725 if (tg3_flag(tp, ENABLE_ASF))
13726 tg3_read_dash_ver(tp);
13727 } else if (tg3_flag(tp, ENABLE_ASF)) {
13728 tg3_read_mgmtfw_ver(tp);
13732 tp->fw_ver[TG3_VER_SIZE - 1] = 0;
13735 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *);
13737 static inline u32 tg3_rx_ret_ring_size(struct tg3 *tp)
13739 if (tg3_flag(tp, LRG_PROD_RING_CAP))
13740 return TG3_RX_RET_MAX_SIZE_5717;
13741 else if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS))
13742 return TG3_RX_RET_MAX_SIZE_5700;
13744 return TG3_RX_RET_MAX_SIZE_5705;
13747 static DEFINE_PCI_DEVICE_TABLE(tg3_write_reorder_chipsets) = {
13748 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C) },
13749 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE) },
13750 { PCI_DEVICE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8385_0) },
13754 static int __devinit tg3_get_invariants(struct tg3 *tp)
13757 u32 pci_state_reg, grc_misc_cfg;
13762 /* Force memory write invalidate off. If we leave it on,
13763 * then on 5700_BX chips we have to enable a workaround.
13764 * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
13765 * to match the cacheline size. The Broadcom driver have this
13766 * workaround but turns MWI off all the times so never uses
13767 * it. This seems to suggest that the workaround is insufficient.
13769 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
13770 pci_cmd &= ~PCI_COMMAND_INVALIDATE;
13771 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
13773 /* Important! -- Make sure register accesses are byteswapped
13774 * correctly. Also, for those chips that require it, make
13775 * sure that indirect register accesses are enabled before
13776 * the first operation.
13778 pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
13780 tp->misc_host_ctrl |= (misc_ctrl_reg &
13781 MISC_HOST_CTRL_CHIPREV);
13782 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
13783 tp->misc_host_ctrl);
13785 tp->pci_chip_rev_id = (misc_ctrl_reg >>
13786 MISC_HOST_CTRL_CHIPREV_SHIFT);
13787 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_USE_PROD_ID_REG) {
13788 u32 prod_id_asic_rev;
13790 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 ||
13791 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 ||
13792 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5719 ||
13793 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5720)
13794 pci_read_config_dword(tp->pdev,
13795 TG3PCI_GEN2_PRODID_ASICREV,
13796 &prod_id_asic_rev);
13797 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781 ||
13798 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785 ||
13799 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761 ||
13800 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765 ||
13801 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 ||
13802 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795)
13803 pci_read_config_dword(tp->pdev,
13804 TG3PCI_GEN15_PRODID_ASICREV,
13805 &prod_id_asic_rev);
13807 pci_read_config_dword(tp->pdev, TG3PCI_PRODID_ASICREV,
13808 &prod_id_asic_rev);
13810 tp->pci_chip_rev_id = prod_id_asic_rev;
13813 /* Wrong chip ID in 5752 A0. This code can be removed later
13814 * as A0 is not in production.
13816 if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
13817 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
13819 /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
13820 * we need to disable memory and use config. cycles
13821 * only to access all registers. The 5702/03 chips
13822 * can mistakenly decode the special cycles from the
13823 * ICH chipsets as memory write cycles, causing corruption
13824 * of register and memory space. Only certain ICH bridges
13825 * will drive special cycles with non-zero data during the
13826 * address phase which can fall within the 5703's address
13827 * range. This is not an ICH bug as the PCI spec allows
13828 * non-zero address during special cycles. However, only
13829 * these ICH bridges are known to drive non-zero addresses
13830 * during special cycles.
13832 * Since special cycles do not cross PCI bridges, we only
13833 * enable this workaround if the 5703 is on the secondary
13834 * bus of these ICH bridges.
13836 if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) ||
13837 (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) {
13838 static struct tg3_dev_id {
13842 } ich_chipsets[] = {
13843 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
13845 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
13847 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
13849 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
13853 struct tg3_dev_id *pci_id = &ich_chipsets[0];
13854 struct pci_dev *bridge = NULL;
13856 while (pci_id->vendor != 0) {
13857 bridge = pci_get_device(pci_id->vendor, pci_id->device,
13863 if (pci_id->rev != PCI_ANY_ID) {
13864 if (bridge->revision > pci_id->rev)
13867 if (bridge->subordinate &&
13868 (bridge->subordinate->number ==
13869 tp->pdev->bus->number)) {
13870 tg3_flag_set(tp, ICH_WORKAROUND);
13871 pci_dev_put(bridge);
13877 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
13878 static struct tg3_dev_id {
13881 } bridge_chipsets[] = {
13882 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0 },
13883 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1 },
13886 struct tg3_dev_id *pci_id = &bridge_chipsets[0];
13887 struct pci_dev *bridge = NULL;
13889 while (pci_id->vendor != 0) {
13890 bridge = pci_get_device(pci_id->vendor,
13897 if (bridge->subordinate &&
13898 (bridge->subordinate->number <=
13899 tp->pdev->bus->number) &&
13900 (bridge->subordinate->subordinate >=
13901 tp->pdev->bus->number)) {
13902 tg3_flag_set(tp, 5701_DMA_BUG);
13903 pci_dev_put(bridge);
13909 /* The EPB bridge inside 5714, 5715, and 5780 cannot support
13910 * DMA addresses > 40-bit. This bridge may have other additional
13911 * 57xx devices behind it in some 4-port NIC designs for example.
13912 * Any tg3 device found behind the bridge will also need the 40-bit
13915 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
13916 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
13917 tg3_flag_set(tp, 5780_CLASS);
13918 tg3_flag_set(tp, 40BIT_DMA_BUG);
13919 tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
13921 struct pci_dev *bridge = NULL;
13924 bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
13925 PCI_DEVICE_ID_SERVERWORKS_EPB,
13927 if (bridge && bridge->subordinate &&
13928 (bridge->subordinate->number <=
13929 tp->pdev->bus->number) &&
13930 (bridge->subordinate->subordinate >=
13931 tp->pdev->bus->number)) {
13932 tg3_flag_set(tp, 40BIT_DMA_BUG);
13933 pci_dev_put(bridge);
13939 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
13940 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)
13941 tp->pdev_peer = tg3_find_peer(tp);
13943 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13944 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
13945 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720)
13946 tg3_flag_set(tp, 5717_PLUS);
13948 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 ||
13949 tg3_flag(tp, 5717_PLUS))
13950 tg3_flag_set(tp, 57765_PLUS);
13952 /* Intentionally exclude ASIC_REV_5906 */
13953 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
13954 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
13955 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13956 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13957 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13958 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
13959 tg3_flag(tp, 57765_PLUS))
13960 tg3_flag_set(tp, 5755_PLUS);
13962 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
13963 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
13964 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
13965 tg3_flag(tp, 5755_PLUS) ||
13966 tg3_flag(tp, 5780_CLASS))
13967 tg3_flag_set(tp, 5750_PLUS);
13969 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
13970 tg3_flag(tp, 5750_PLUS))
13971 tg3_flag_set(tp, 5705_PLUS);
13973 /* Determine TSO capabilities */
13974 if (tp->pci_chip_rev_id == CHIPREV_ID_5719_A0)
13975 ; /* Do nothing. HW bug. */
13976 else if (tg3_flag(tp, 57765_PLUS))
13977 tg3_flag_set(tp, HW_TSO_3);
13978 else if (tg3_flag(tp, 5755_PLUS) ||
13979 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13980 tg3_flag_set(tp, HW_TSO_2);
13981 else if (tg3_flag(tp, 5750_PLUS)) {
13982 tg3_flag_set(tp, HW_TSO_1);
13983 tg3_flag_set(tp, TSO_BUG);
13984 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 &&
13985 tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2)
13986 tg3_flag_clear(tp, TSO_BUG);
13987 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13988 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
13989 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) {
13990 tg3_flag_set(tp, TSO_BUG);
13991 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)
13992 tp->fw_needed = FIRMWARE_TG3TSO5;
13994 tp->fw_needed = FIRMWARE_TG3TSO;
13997 /* Selectively allow TSO based on operating conditions */
13998 if (tg3_flag(tp, HW_TSO_1) ||
13999 tg3_flag(tp, HW_TSO_2) ||
14000 tg3_flag(tp, HW_TSO_3) ||
14001 (tp->fw_needed && !tg3_flag(tp, ENABLE_ASF)))
14002 tg3_flag_set(tp, TSO_CAPABLE);
14004 tg3_flag_clear(tp, TSO_CAPABLE);
14005 tg3_flag_clear(tp, TSO_BUG);
14006 tp->fw_needed = NULL;
14009 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0)
14010 tp->fw_needed = FIRMWARE_TG3;
14014 if (tg3_flag(tp, 5750_PLUS)) {
14015 tg3_flag_set(tp, SUPPORT_MSI);
14016 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX ||
14017 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX ||
14018 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 &&
14019 tp->pci_chip_rev_id <= CHIPREV_ID_5714_A2 &&
14020 tp->pdev_peer == tp->pdev))
14021 tg3_flag_clear(tp, SUPPORT_MSI);
14023 if (tg3_flag(tp, 5755_PLUS) ||
14024 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
14025 tg3_flag_set(tp, 1SHOT_MSI);
14028 if (tg3_flag(tp, 57765_PLUS)) {
14029 tg3_flag_set(tp, SUPPORT_MSIX);
14030 tp->irq_max = TG3_IRQ_MAX_VECS;
14034 if (tg3_flag(tp, 5755_PLUS))
14035 tg3_flag_set(tp, SHORT_DMA_BUG);
14037 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
14038 tg3_flag_set(tp, 4K_FIFO_LIMIT);
14040 if (tg3_flag(tp, 5717_PLUS))
14041 tg3_flag_set(tp, LRG_PROD_RING_CAP);
14043 if (tg3_flag(tp, 57765_PLUS) &&
14044 tp->pci_chip_rev_id != CHIPREV_ID_5719_A0)
14045 tg3_flag_set(tp, USE_JUMBO_BDFLAG);
14047 if (!tg3_flag(tp, 5705_PLUS) ||
14048 tg3_flag(tp, 5780_CLASS) ||
14049 tg3_flag(tp, USE_JUMBO_BDFLAG))
14050 tg3_flag_set(tp, JUMBO_CAPABLE);
14052 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
14055 if (pci_is_pcie(tp->pdev)) {
14058 tg3_flag_set(tp, PCI_EXPRESS);
14060 tp->pcie_readrq = 4096;
14061 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
14062 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720)
14063 tp->pcie_readrq = 2048;
14065 pcie_set_readrq(tp->pdev, tp->pcie_readrq);
14067 pci_read_config_word(tp->pdev,
14068 pci_pcie_cap(tp->pdev) + PCI_EXP_LNKCTL,
14070 if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN) {
14071 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
14073 tg3_flag_clear(tp, HW_TSO_2);
14074 tg3_flag_clear(tp, TSO_CAPABLE);
14076 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
14077 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
14078 tp->pci_chip_rev_id == CHIPREV_ID_57780_A0 ||
14079 tp->pci_chip_rev_id == CHIPREV_ID_57780_A1)
14080 tg3_flag_set(tp, CLKREQ_BUG);
14081 } else if (tp->pci_chip_rev_id == CHIPREV_ID_5717_A0) {
14082 tg3_flag_set(tp, L1PLLPD_EN);
14084 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
14085 /* BCM5785 devices are effectively PCIe devices, and should
14086 * follow PCIe codepaths, but do not have a PCIe capabilities
14089 tg3_flag_set(tp, PCI_EXPRESS);
14090 } else if (!tg3_flag(tp, 5705_PLUS) ||
14091 tg3_flag(tp, 5780_CLASS)) {
14092 tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX);
14093 if (!tp->pcix_cap) {
14094 dev_err(&tp->pdev->dev,
14095 "Cannot find PCI-X capability, aborting\n");
14099 if (!(pci_state_reg & PCISTATE_CONV_PCI_MODE))
14100 tg3_flag_set(tp, PCIX_MODE);
14103 /* If we have an AMD 762 or VIA K8T800 chipset, write
14104 * reordering to the mailbox registers done by the host
14105 * controller can cause major troubles. We read back from
14106 * every mailbox register write to force the writes to be
14107 * posted to the chip in order.
14109 if (pci_dev_present(tg3_write_reorder_chipsets) &&
14110 !tg3_flag(tp, PCI_EXPRESS))
14111 tg3_flag_set(tp, MBOX_WRITE_REORDER);
14113 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
14114 &tp->pci_cacheline_sz);
14115 pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER,
14116 &tp->pci_lat_timer);
14117 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
14118 tp->pci_lat_timer < 64) {
14119 tp->pci_lat_timer = 64;
14120 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
14121 tp->pci_lat_timer);
14124 /* Important! -- It is critical that the PCI-X hw workaround
14125 * situation is decided before the first MMIO register access.
14127 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
14128 /* 5700 BX chips need to have their TX producer index
14129 * mailboxes written twice to workaround a bug.
14131 tg3_flag_set(tp, TXD_MBOX_HWBUG);
14133 /* If we are in PCI-X mode, enable register write workaround.
14135 * The workaround is to use indirect register accesses
14136 * for all chip writes not to mailbox registers.
14138 if (tg3_flag(tp, PCIX_MODE)) {
14141 tg3_flag_set(tp, PCIX_TARGET_HWBUG);
14143 /* The chip can have it's power management PCI config
14144 * space registers clobbered due to this bug.
14145 * So explicitly force the chip into D0 here.
14147 pci_read_config_dword(tp->pdev,
14148 tp->pm_cap + PCI_PM_CTRL,
14150 pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
14151 pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
14152 pci_write_config_dword(tp->pdev,
14153 tp->pm_cap + PCI_PM_CTRL,
14156 /* Also, force SERR#/PERR# in PCI command. */
14157 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
14158 pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
14159 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
14163 if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
14164 tg3_flag_set(tp, PCI_HIGH_SPEED);
14165 if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
14166 tg3_flag_set(tp, PCI_32BIT);
14168 /* Chip-specific fixup from Broadcom driver */
14169 if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
14170 (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
14171 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
14172 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
14175 /* Default fast path register access methods */
14176 tp->read32 = tg3_read32;
14177 tp->write32 = tg3_write32;
14178 tp->read32_mbox = tg3_read32;
14179 tp->write32_mbox = tg3_write32;
14180 tp->write32_tx_mbox = tg3_write32;
14181 tp->write32_rx_mbox = tg3_write32;
14183 /* Various workaround register access methods */
14184 if (tg3_flag(tp, PCIX_TARGET_HWBUG))
14185 tp->write32 = tg3_write_indirect_reg32;
14186 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
14187 (tg3_flag(tp, PCI_EXPRESS) &&
14188 tp->pci_chip_rev_id == CHIPREV_ID_5750_A0)) {
14190 * Back to back register writes can cause problems on these
14191 * chips, the workaround is to read back all reg writes
14192 * except those to mailbox regs.
14194 * See tg3_write_indirect_reg32().
14196 tp->write32 = tg3_write_flush_reg32;
14199 if (tg3_flag(tp, TXD_MBOX_HWBUG) || tg3_flag(tp, MBOX_WRITE_REORDER)) {
14200 tp->write32_tx_mbox = tg3_write32_tx_mbox;
14201 if (tg3_flag(tp, MBOX_WRITE_REORDER))
14202 tp->write32_rx_mbox = tg3_write_flush_reg32;
14205 if (tg3_flag(tp, ICH_WORKAROUND)) {
14206 tp->read32 = tg3_read_indirect_reg32;
14207 tp->write32 = tg3_write_indirect_reg32;
14208 tp->read32_mbox = tg3_read_indirect_mbox;
14209 tp->write32_mbox = tg3_write_indirect_mbox;
14210 tp->write32_tx_mbox = tg3_write_indirect_mbox;
14211 tp->write32_rx_mbox = tg3_write_indirect_mbox;
14216 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
14217 pci_cmd &= ~PCI_COMMAND_MEMORY;
14218 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
14220 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
14221 tp->read32_mbox = tg3_read32_mbox_5906;
14222 tp->write32_mbox = tg3_write32_mbox_5906;
14223 tp->write32_tx_mbox = tg3_write32_mbox_5906;
14224 tp->write32_rx_mbox = tg3_write32_mbox_5906;
14227 if (tp->write32 == tg3_write_indirect_reg32 ||
14228 (tg3_flag(tp, PCIX_MODE) &&
14229 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
14230 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
14231 tg3_flag_set(tp, SRAM_USE_CONFIG);
14233 /* The memory arbiter has to be enabled in order for SRAM accesses
14234 * to succeed. Normally on powerup the tg3 chip firmware will make
14235 * sure it is enabled, but other entities such as system netboot
14236 * code might disable it.
14238 val = tr32(MEMARB_MODE);
14239 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
14241 tp->pci_fn = PCI_FUNC(tp->pdev->devfn) & 3;
14242 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
14243 tg3_flag(tp, 5780_CLASS)) {
14244 if (tg3_flag(tp, PCIX_MODE)) {
14245 pci_read_config_dword(tp->pdev,
14246 tp->pcix_cap + PCI_X_STATUS,
14248 tp->pci_fn = val & 0x7;
14250 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
14251 tg3_read_mem(tp, NIC_SRAM_CPMU_STATUS, &val);
14252 if ((val & NIC_SRAM_CPMUSTAT_SIG_MSK) ==
14253 NIC_SRAM_CPMUSTAT_SIG) {
14254 tp->pci_fn = val & TG3_CPMU_STATUS_FMSK_5717;
14255 tp->pci_fn = tp->pci_fn ? 1 : 0;
14257 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
14258 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) {
14259 tg3_read_mem(tp, NIC_SRAM_CPMU_STATUS, &val);
14260 if ((val & NIC_SRAM_CPMUSTAT_SIG_MSK) ==
14261 NIC_SRAM_CPMUSTAT_SIG) {
14262 tp->pci_fn = (val & TG3_CPMU_STATUS_FMSK_5719) >>
14263 TG3_CPMU_STATUS_FSHFT_5719;
14267 /* Get eeprom hw config before calling tg3_set_power_state().
14268 * In particular, the TG3_FLAG_IS_NIC flag must be
14269 * determined before calling tg3_set_power_state() so that
14270 * we know whether or not to switch out of Vaux power.
14271 * When the flag is set, it means that GPIO1 is used for eeprom
14272 * write protect and also implies that it is a LOM where GPIOs
14273 * are not used to switch power.
14275 tg3_get_eeprom_hw_cfg(tp);
14277 if (tg3_flag(tp, ENABLE_APE)) {
14278 /* Allow reads and writes to the
14279 * APE register and memory space.
14281 pci_state_reg |= PCISTATE_ALLOW_APE_CTLSPC_WR |
14282 PCISTATE_ALLOW_APE_SHMEM_WR |
14283 PCISTATE_ALLOW_APE_PSPACE_WR;
14284 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE,
14287 tg3_ape_lock_init(tp);
14290 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
14291 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
14292 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
14293 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
14294 tg3_flag(tp, 57765_PLUS))
14295 tg3_flag_set(tp, CPMU_PRESENT);
14297 /* Set up tp->grc_local_ctrl before calling
14298 * tg3_pwrsrc_switch_to_vmain(). GPIO1 driven high
14299 * will bring 5700's external PHY out of reset.
14300 * It is also used as eeprom write protect on LOMs.
14302 tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
14303 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
14304 tg3_flag(tp, EEPROM_WRITE_PROT))
14305 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
14306 GRC_LCLCTRL_GPIO_OUTPUT1);
14307 /* Unused GPIO3 must be driven as output on 5752 because there
14308 * are no pull-up resistors on unused GPIO pins.
14310 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
14311 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
14313 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
14314 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
14315 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
14316 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
14318 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
14319 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
14320 /* Turn off the debug UART. */
14321 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
14322 if (tg3_flag(tp, IS_NIC))
14323 /* Keep VMain power. */
14324 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
14325 GRC_LCLCTRL_GPIO_OUTPUT0;
14328 /* Switch out of Vaux if it is a NIC */
14329 tg3_pwrsrc_switch_to_vmain(tp);
14331 /* Derive initial jumbo mode from MTU assigned in
14332 * ether_setup() via the alloc_etherdev() call
14334 if (tp->dev->mtu > ETH_DATA_LEN && !tg3_flag(tp, 5780_CLASS))
14335 tg3_flag_set(tp, JUMBO_RING_ENABLE);
14337 /* Determine WakeOnLan speed to use. */
14338 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
14339 tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
14340 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
14341 tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
14342 tg3_flag_clear(tp, WOL_SPEED_100MB);
14344 tg3_flag_set(tp, WOL_SPEED_100MB);
14347 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
14348 tp->phy_flags |= TG3_PHYFLG_IS_FET;
14350 /* A few boards don't want Ethernet@WireSpeed phy feature */
14351 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
14352 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
14353 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
14354 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) ||
14355 (tp->phy_flags & TG3_PHYFLG_IS_FET) ||
14356 (tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
14357 tp->phy_flags |= TG3_PHYFLG_NO_ETH_WIRE_SPEED;
14359 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
14360 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
14361 tp->phy_flags |= TG3_PHYFLG_ADC_BUG;
14362 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
14363 tp->phy_flags |= TG3_PHYFLG_5704_A0_BUG;
14365 if (tg3_flag(tp, 5705_PLUS) &&
14366 !(tp->phy_flags & TG3_PHYFLG_IS_FET) &&
14367 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
14368 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57780 &&
14369 !tg3_flag(tp, 57765_PLUS)) {
14370 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
14371 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
14372 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
14373 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
14374 if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
14375 tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
14376 tp->phy_flags |= TG3_PHYFLG_JITTER_BUG;
14377 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
14378 tp->phy_flags |= TG3_PHYFLG_ADJUST_TRIM;
14380 tp->phy_flags |= TG3_PHYFLG_BER_BUG;
14383 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
14384 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
14385 tp->phy_otp = tg3_read_otp_phycfg(tp);
14386 if (tp->phy_otp == 0)
14387 tp->phy_otp = TG3_OTP_DEFAULT;
14390 if (tg3_flag(tp, CPMU_PRESENT))
14391 tp->mi_mode = MAC_MI_MODE_500KHZ_CONST;
14393 tp->mi_mode = MAC_MI_MODE_BASE;
14395 tp->coalesce_mode = 0;
14396 if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
14397 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
14398 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
14400 /* Set these bits to enable statistics workaround. */
14401 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
14402 tp->pci_chip_rev_id == CHIPREV_ID_5719_A0 ||
14403 tp->pci_chip_rev_id == CHIPREV_ID_5720_A0) {
14404 tp->coalesce_mode |= HOSTCC_MODE_ATTN;
14405 tp->grc_mode |= GRC_MODE_IRQ_ON_FLOW_ATTN;
14408 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
14409 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
14410 tg3_flag_set(tp, USE_PHYLIB);
14412 err = tg3_mdio_init(tp);
14416 /* Initialize data/descriptor byte/word swapping. */
14417 val = tr32(GRC_MODE);
14418 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720)
14419 val &= (GRC_MODE_BYTE_SWAP_B2HRX_DATA |
14420 GRC_MODE_WORD_SWAP_B2HRX_DATA |
14421 GRC_MODE_B2HRX_ENABLE |
14422 GRC_MODE_HTX2B_ENABLE |
14423 GRC_MODE_HOST_STACKUP);
14425 val &= GRC_MODE_HOST_STACKUP;
14427 tw32(GRC_MODE, val | tp->grc_mode);
14429 tg3_switch_clocks(tp);
14431 /* Clear this out for sanity. */
14432 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
14434 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
14436 if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
14437 !tg3_flag(tp, PCIX_TARGET_HWBUG)) {
14438 u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
14440 if (chiprevid == CHIPREV_ID_5701_A0 ||
14441 chiprevid == CHIPREV_ID_5701_B0 ||
14442 chiprevid == CHIPREV_ID_5701_B2 ||
14443 chiprevid == CHIPREV_ID_5701_B5) {
14444 void __iomem *sram_base;
14446 /* Write some dummy words into the SRAM status block
14447 * area, see if it reads back correctly. If the return
14448 * value is bad, force enable the PCIX workaround.
14450 sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
14452 writel(0x00000000, sram_base);
14453 writel(0x00000000, sram_base + 4);
14454 writel(0xffffffff, sram_base + 4);
14455 if (readl(sram_base) != 0x00000000)
14456 tg3_flag_set(tp, PCIX_TARGET_HWBUG);
14461 tg3_nvram_init(tp);
14463 grc_misc_cfg = tr32(GRC_MISC_CFG);
14464 grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
14466 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
14467 (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
14468 grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
14469 tg3_flag_set(tp, IS_5788);
14471 if (!tg3_flag(tp, IS_5788) &&
14472 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)
14473 tg3_flag_set(tp, TAGGED_STATUS);
14474 if (tg3_flag(tp, TAGGED_STATUS)) {
14475 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
14476 HOSTCC_MODE_CLRTICK_TXBD);
14478 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
14479 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
14480 tp->misc_host_ctrl);
14483 /* Preserve the APE MAC_MODE bits */
14484 if (tg3_flag(tp, ENABLE_APE))
14485 tp->mac_mode = MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
14489 /* these are limited to 10/100 only */
14490 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
14491 (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
14492 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
14493 tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
14494 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||
14495 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 ||
14496 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
14497 (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
14498 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
14499 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F ||
14500 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5787F)) ||
14501 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790 ||
14502 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 ||
14503 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795 ||
14504 (tp->phy_flags & TG3_PHYFLG_IS_FET))
14505 tp->phy_flags |= TG3_PHYFLG_10_100_ONLY;
14507 err = tg3_phy_probe(tp);
14509 dev_err(&tp->pdev->dev, "phy probe failed, err %d\n", err);
14510 /* ... but do not return immediately ... */
14515 tg3_read_fw_ver(tp);
14517 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
14518 tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT;
14520 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
14521 tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT;
14523 tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT;
14526 /* 5700 {AX,BX} chips have a broken status block link
14527 * change bit implementation, so we must use the
14528 * status register in those cases.
14530 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
14531 tg3_flag_set(tp, USE_LINKCHG_REG);
14533 tg3_flag_clear(tp, USE_LINKCHG_REG);
14535 /* The led_ctrl is set during tg3_phy_probe, here we might
14536 * have to force the link status polling mechanism based
14537 * upon subsystem IDs.
14539 if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
14540 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
14541 !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
14542 tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT;
14543 tg3_flag_set(tp, USE_LINKCHG_REG);
14546 /* For all SERDES we poll the MAC status register. */
14547 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
14548 tg3_flag_set(tp, POLL_SERDES);
14550 tg3_flag_clear(tp, POLL_SERDES);
14552 tp->rx_offset = NET_IP_ALIGN;
14553 tp->rx_copy_thresh = TG3_RX_COPY_THRESHOLD;
14554 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
14555 tg3_flag(tp, PCIX_MODE)) {
14557 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
14558 tp->rx_copy_thresh = ~(u16)0;
14562 tp->rx_std_ring_mask = TG3_RX_STD_RING_SIZE(tp) - 1;
14563 tp->rx_jmb_ring_mask = TG3_RX_JMB_RING_SIZE(tp) - 1;
14564 tp->rx_ret_ring_mask = tg3_rx_ret_ring_size(tp) - 1;
14566 tp->rx_std_max_post = tp->rx_std_ring_mask + 1;
14568 /* Increment the rx prod index on the rx std ring by at most
14569 * 8 for these chips to workaround hw errata.
14571 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
14572 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
14573 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
14574 tp->rx_std_max_post = 8;
14576 if (tg3_flag(tp, ASPM_WORKAROUND))
14577 tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) &
14578 PCIE_PWR_MGMT_L1_THRESH_MSK;
14583 #ifdef CONFIG_SPARC
14584 static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp)
14586 struct net_device *dev = tp->dev;
14587 struct pci_dev *pdev = tp->pdev;
14588 struct device_node *dp = pci_device_to_OF_node(pdev);
14589 const unsigned char *addr;
14592 addr = of_get_property(dp, "local-mac-address", &len);
14593 if (addr && len == 6) {
14594 memcpy(dev->dev_addr, addr, 6);
14595 memcpy(dev->perm_addr, dev->dev_addr, 6);
14601 static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp)
14603 struct net_device *dev = tp->dev;
14605 memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
14606 memcpy(dev->perm_addr, idprom->id_ethaddr, 6);
14611 static int __devinit tg3_get_device_address(struct tg3 *tp)
14613 struct net_device *dev = tp->dev;
14614 u32 hi, lo, mac_offset;
14617 #ifdef CONFIG_SPARC
14618 if (!tg3_get_macaddr_sparc(tp))
14623 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
14624 tg3_flag(tp, 5780_CLASS)) {
14625 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
14627 if (tg3_nvram_lock(tp))
14628 tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
14630 tg3_nvram_unlock(tp);
14631 } else if (tg3_flag(tp, 5717_PLUS)) {
14632 if (tp->pci_fn & 1)
14634 if (tp->pci_fn > 1)
14635 mac_offset += 0x18c;
14636 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
14639 /* First try to get it from MAC address mailbox. */
14640 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
14641 if ((hi >> 16) == 0x484b) {
14642 dev->dev_addr[0] = (hi >> 8) & 0xff;
14643 dev->dev_addr[1] = (hi >> 0) & 0xff;
14645 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
14646 dev->dev_addr[2] = (lo >> 24) & 0xff;
14647 dev->dev_addr[3] = (lo >> 16) & 0xff;
14648 dev->dev_addr[4] = (lo >> 8) & 0xff;
14649 dev->dev_addr[5] = (lo >> 0) & 0xff;
14651 /* Some old bootcode may report a 0 MAC address in SRAM */
14652 addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
14655 /* Next, try NVRAM. */
14656 if (!tg3_flag(tp, NO_NVRAM) &&
14657 !tg3_nvram_read_be32(tp, mac_offset + 0, &hi) &&
14658 !tg3_nvram_read_be32(tp, mac_offset + 4, &lo)) {
14659 memcpy(&dev->dev_addr[0], ((char *)&hi) + 2, 2);
14660 memcpy(&dev->dev_addr[2], (char *)&lo, sizeof(lo));
14662 /* Finally just fetch it out of the MAC control regs. */
14664 hi = tr32(MAC_ADDR_0_HIGH);
14665 lo = tr32(MAC_ADDR_0_LOW);
14667 dev->dev_addr[5] = lo & 0xff;
14668 dev->dev_addr[4] = (lo >> 8) & 0xff;
14669 dev->dev_addr[3] = (lo >> 16) & 0xff;
14670 dev->dev_addr[2] = (lo >> 24) & 0xff;
14671 dev->dev_addr[1] = hi & 0xff;
14672 dev->dev_addr[0] = (hi >> 8) & 0xff;
14676 if (!is_valid_ether_addr(&dev->dev_addr[0])) {
14677 #ifdef CONFIG_SPARC
14678 if (!tg3_get_default_macaddr_sparc(tp))
14683 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
14687 #define BOUNDARY_SINGLE_CACHELINE 1
14688 #define BOUNDARY_MULTI_CACHELINE 2
14690 static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
14692 int cacheline_size;
14696 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
14698 cacheline_size = 1024;
14700 cacheline_size = (int) byte * 4;
14702 /* On 5703 and later chips, the boundary bits have no
14705 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
14706 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
14707 !tg3_flag(tp, PCI_EXPRESS))
14710 #if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
14711 goal = BOUNDARY_MULTI_CACHELINE;
14713 #if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
14714 goal = BOUNDARY_SINGLE_CACHELINE;
14720 if (tg3_flag(tp, 57765_PLUS)) {
14721 val = goal ? 0 : DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
14728 /* PCI controllers on most RISC systems tend to disconnect
14729 * when a device tries to burst across a cache-line boundary.
14730 * Therefore, letting tg3 do so just wastes PCI bandwidth.
14732 * Unfortunately, for PCI-E there are only limited
14733 * write-side controls for this, and thus for reads
14734 * we will still get the disconnects. We'll also waste
14735 * these PCI cycles for both read and write for chips
14736 * other than 5700 and 5701 which do not implement the
14739 if (tg3_flag(tp, PCIX_MODE) && !tg3_flag(tp, PCI_EXPRESS)) {
14740 switch (cacheline_size) {
14745 if (goal == BOUNDARY_SINGLE_CACHELINE) {
14746 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
14747 DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
14749 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
14750 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
14755 val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
14756 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
14760 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
14761 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
14764 } else if (tg3_flag(tp, PCI_EXPRESS)) {
14765 switch (cacheline_size) {
14769 if (goal == BOUNDARY_SINGLE_CACHELINE) {
14770 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
14771 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
14777 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
14778 val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
14782 switch (cacheline_size) {
14784 if (goal == BOUNDARY_SINGLE_CACHELINE) {
14785 val |= (DMA_RWCTRL_READ_BNDRY_16 |
14786 DMA_RWCTRL_WRITE_BNDRY_16);
14791 if (goal == BOUNDARY_SINGLE_CACHELINE) {
14792 val |= (DMA_RWCTRL_READ_BNDRY_32 |
14793 DMA_RWCTRL_WRITE_BNDRY_32);
14798 if (goal == BOUNDARY_SINGLE_CACHELINE) {
14799 val |= (DMA_RWCTRL_READ_BNDRY_64 |
14800 DMA_RWCTRL_WRITE_BNDRY_64);
14805 if (goal == BOUNDARY_SINGLE_CACHELINE) {
14806 val |= (DMA_RWCTRL_READ_BNDRY_128 |
14807 DMA_RWCTRL_WRITE_BNDRY_128);
14812 val |= (DMA_RWCTRL_READ_BNDRY_256 |
14813 DMA_RWCTRL_WRITE_BNDRY_256);
14816 val |= (DMA_RWCTRL_READ_BNDRY_512 |
14817 DMA_RWCTRL_WRITE_BNDRY_512);
14821 val |= (DMA_RWCTRL_READ_BNDRY_1024 |
14822 DMA_RWCTRL_WRITE_BNDRY_1024);
14831 static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)
14833 struct tg3_internal_buffer_desc test_desc;
14834 u32 sram_dma_descs;
14837 sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
14839 tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
14840 tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
14841 tw32(RDMAC_STATUS, 0);
14842 tw32(WDMAC_STATUS, 0);
14844 tw32(BUFMGR_MODE, 0);
14845 tw32(FTQ_RESET, 0);
14847 test_desc.addr_hi = ((u64) buf_dma) >> 32;
14848 test_desc.addr_lo = buf_dma & 0xffffffff;
14849 test_desc.nic_mbuf = 0x00002100;
14850 test_desc.len = size;
14853 * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
14854 * the *second* time the tg3 driver was getting loaded after an
14857 * Broadcom tells me:
14858 * ...the DMA engine is connected to the GRC block and a DMA
14859 * reset may affect the GRC block in some unpredictable way...
14860 * The behavior of resets to individual blocks has not been tested.
14862 * Broadcom noted the GRC reset will also reset all sub-components.
14865 test_desc.cqid_sqid = (13 << 8) | 2;
14867 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
14870 test_desc.cqid_sqid = (16 << 8) | 7;
14872 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
14875 test_desc.flags = 0x00000005;
14877 for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
14880 val = *(((u32 *)&test_desc) + i);
14881 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
14882 sram_dma_descs + (i * sizeof(u32)));
14883 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
14885 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
14888 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
14890 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
14893 for (i = 0; i < 40; i++) {
14897 val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
14899 val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
14900 if ((val & 0xffff) == sram_dma_descs) {
14911 #define TEST_BUFFER_SIZE 0x2000
14913 static DEFINE_PCI_DEVICE_TABLE(tg3_dma_wait_state_chipsets) = {
14914 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
14918 static int __devinit tg3_test_dma(struct tg3 *tp)
14920 dma_addr_t buf_dma;
14921 u32 *buf, saved_dma_rwctrl;
14924 buf = dma_alloc_coherent(&tp->pdev->dev, TEST_BUFFER_SIZE,
14925 &buf_dma, GFP_KERNEL);
14931 tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
14932 (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
14934 tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
14936 if (tg3_flag(tp, 57765_PLUS))
14939 if (tg3_flag(tp, PCI_EXPRESS)) {
14940 /* DMA read watermark not used on PCIE */
14941 tp->dma_rwctrl |= 0x00180000;
14942 } else if (!tg3_flag(tp, PCIX_MODE)) {
14943 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
14944 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
14945 tp->dma_rwctrl |= 0x003f0000;
14947 tp->dma_rwctrl |= 0x003f000f;
14949 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
14950 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
14951 u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
14952 u32 read_water = 0x7;
14954 /* If the 5704 is behind the EPB bridge, we can
14955 * do the less restrictive ONE_DMA workaround for
14956 * better performance.
14958 if (tg3_flag(tp, 40BIT_DMA_BUG) &&
14959 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
14960 tp->dma_rwctrl |= 0x8000;
14961 else if (ccval == 0x6 || ccval == 0x7)
14962 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
14964 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703)
14966 /* Set bit 23 to enable PCIX hw bug fix */
14968 (read_water << DMA_RWCTRL_READ_WATER_SHIFT) |
14969 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
14971 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
14972 /* 5780 always in PCIX mode */
14973 tp->dma_rwctrl |= 0x00144000;
14974 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
14975 /* 5714 always in PCIX mode */
14976 tp->dma_rwctrl |= 0x00148000;
14978 tp->dma_rwctrl |= 0x001b000f;
14982 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
14983 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
14984 tp->dma_rwctrl &= 0xfffffff0;
14986 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
14987 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
14988 /* Remove this if it causes problems for some boards. */
14989 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
14991 /* On 5700/5701 chips, we need to set this bit.
14992 * Otherwise the chip will issue cacheline transactions
14993 * to streamable DMA memory with not all the byte
14994 * enables turned on. This is an error on several
14995 * RISC PCI controllers, in particular sparc64.
14997 * On 5703/5704 chips, this bit has been reassigned
14998 * a different meaning. In particular, it is used
14999 * on those chips to enable a PCI-X workaround.
15001 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
15004 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
15007 /* Unneeded, already done by tg3_get_invariants. */
15008 tg3_switch_clocks(tp);
15011 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
15012 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
15015 /* It is best to perform DMA test with maximum write burst size
15016 * to expose the 5700/5701 write DMA bug.
15018 saved_dma_rwctrl = tp->dma_rwctrl;
15019 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
15020 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
15025 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
15028 /* Send the buffer to the chip. */
15029 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
15031 dev_err(&tp->pdev->dev,
15032 "%s: Buffer write failed. err = %d\n",
15038 /* validate data reached card RAM correctly. */
15039 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
15041 tg3_read_mem(tp, 0x2100 + (i*4), &val);
15042 if (le32_to_cpu(val) != p[i]) {
15043 dev_err(&tp->pdev->dev,
15044 "%s: Buffer corrupted on device! "
15045 "(%d != %d)\n", __func__, val, i);
15046 /* ret = -ENODEV here? */
15051 /* Now read it back. */
15052 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
15054 dev_err(&tp->pdev->dev, "%s: Buffer read failed. "
15055 "err = %d\n", __func__, ret);
15060 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
15064 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
15065 DMA_RWCTRL_WRITE_BNDRY_16) {
15066 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
15067 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
15068 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
15071 dev_err(&tp->pdev->dev,
15072 "%s: Buffer corrupted on read back! "
15073 "(%d != %d)\n", __func__, p[i], i);
15079 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
15085 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
15086 DMA_RWCTRL_WRITE_BNDRY_16) {
15087 /* DMA test passed without adjusting DMA boundary,
15088 * now look for chipsets that are known to expose the
15089 * DMA bug without failing the test.
15091 if (pci_dev_present(tg3_dma_wait_state_chipsets)) {
15092 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
15093 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
15095 /* Safe to use the calculated DMA boundary. */
15096 tp->dma_rwctrl = saved_dma_rwctrl;
15099 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
15103 dma_free_coherent(&tp->pdev->dev, TEST_BUFFER_SIZE, buf, buf_dma);
15108 static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
15110 if (tg3_flag(tp, 57765_PLUS)) {
15111 tp->bufmgr_config.mbuf_read_dma_low_water =
15112 DEFAULT_MB_RDMA_LOW_WATER_5705;
15113 tp->bufmgr_config.mbuf_mac_rx_low_water =
15114 DEFAULT_MB_MACRX_LOW_WATER_57765;
15115 tp->bufmgr_config.mbuf_high_water =
15116 DEFAULT_MB_HIGH_WATER_57765;
15118 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
15119 DEFAULT_MB_RDMA_LOW_WATER_5705;
15120 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
15121 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_57765;
15122 tp->bufmgr_config.mbuf_high_water_jumbo =
15123 DEFAULT_MB_HIGH_WATER_JUMBO_57765;
15124 } else if (tg3_flag(tp, 5705_PLUS)) {
15125 tp->bufmgr_config.mbuf_read_dma_low_water =
15126 DEFAULT_MB_RDMA_LOW_WATER_5705;
15127 tp->bufmgr_config.mbuf_mac_rx_low_water =
15128 DEFAULT_MB_MACRX_LOW_WATER_5705;
15129 tp->bufmgr_config.mbuf_high_water =
15130 DEFAULT_MB_HIGH_WATER_5705;
15131 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
15132 tp->bufmgr_config.mbuf_mac_rx_low_water =
15133 DEFAULT_MB_MACRX_LOW_WATER_5906;
15134 tp->bufmgr_config.mbuf_high_water =
15135 DEFAULT_MB_HIGH_WATER_5906;
15138 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
15139 DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
15140 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
15141 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
15142 tp->bufmgr_config.mbuf_high_water_jumbo =
15143 DEFAULT_MB_HIGH_WATER_JUMBO_5780;
15145 tp->bufmgr_config.mbuf_read_dma_low_water =
15146 DEFAULT_MB_RDMA_LOW_WATER;
15147 tp->bufmgr_config.mbuf_mac_rx_low_water =
15148 DEFAULT_MB_MACRX_LOW_WATER;
15149 tp->bufmgr_config.mbuf_high_water =
15150 DEFAULT_MB_HIGH_WATER;
15152 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
15153 DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
15154 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
15155 DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
15156 tp->bufmgr_config.mbuf_high_water_jumbo =
15157 DEFAULT_MB_HIGH_WATER_JUMBO;
15160 tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
15161 tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
15164 static char * __devinit tg3_phy_string(struct tg3 *tp)
15166 switch (tp->phy_id & TG3_PHY_ID_MASK) {
15167 case TG3_PHY_ID_BCM5400: return "5400";
15168 case TG3_PHY_ID_BCM5401: return "5401";
15169 case TG3_PHY_ID_BCM5411: return "5411";
15170 case TG3_PHY_ID_BCM5701: return "5701";
15171 case TG3_PHY_ID_BCM5703: return "5703";
15172 case TG3_PHY_ID_BCM5704: return "5704";
15173 case TG3_PHY_ID_BCM5705: return "5705";
15174 case TG3_PHY_ID_BCM5750: return "5750";
15175 case TG3_PHY_ID_BCM5752: return "5752";
15176 case TG3_PHY_ID_BCM5714: return "5714";
15177 case TG3_PHY_ID_BCM5780: return "5780";
15178 case TG3_PHY_ID_BCM5755: return "5755";
15179 case TG3_PHY_ID_BCM5787: return "5787";
15180 case TG3_PHY_ID_BCM5784: return "5784";
15181 case TG3_PHY_ID_BCM5756: return "5722/5756";
15182 case TG3_PHY_ID_BCM5906: return "5906";
15183 case TG3_PHY_ID_BCM5761: return "5761";
15184 case TG3_PHY_ID_BCM5718C: return "5718C";
15185 case TG3_PHY_ID_BCM5718S: return "5718S";
15186 case TG3_PHY_ID_BCM57765: return "57765";
15187 case TG3_PHY_ID_BCM5719C: return "5719C";
15188 case TG3_PHY_ID_BCM5720C: return "5720C";
15189 case TG3_PHY_ID_BCM8002: return "8002/serdes";
15190 case 0: return "serdes";
15191 default: return "unknown";
15195 static char * __devinit tg3_bus_string(struct tg3 *tp, char *str)
15197 if (tg3_flag(tp, PCI_EXPRESS)) {
15198 strcpy(str, "PCI Express");
15200 } else if (tg3_flag(tp, PCIX_MODE)) {
15201 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
15203 strcpy(str, "PCIX:");
15205 if ((clock_ctrl == 7) ||
15206 ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
15207 GRC_MISC_CFG_BOARD_ID_5704CIOBE))
15208 strcat(str, "133MHz");
15209 else if (clock_ctrl == 0)
15210 strcat(str, "33MHz");
15211 else if (clock_ctrl == 2)
15212 strcat(str, "50MHz");
15213 else if (clock_ctrl == 4)
15214 strcat(str, "66MHz");
15215 else if (clock_ctrl == 6)
15216 strcat(str, "100MHz");
15218 strcpy(str, "PCI:");
15219 if (tg3_flag(tp, PCI_HIGH_SPEED))
15220 strcat(str, "66MHz");
15222 strcat(str, "33MHz");
15224 if (tg3_flag(tp, PCI_32BIT))
15225 strcat(str, ":32-bit");
15227 strcat(str, ":64-bit");
15231 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp)
15233 struct pci_dev *peer;
15234 unsigned int func, devnr = tp->pdev->devfn & ~7;
15236 for (func = 0; func < 8; func++) {
15237 peer = pci_get_slot(tp->pdev->bus, devnr | func);
15238 if (peer && peer != tp->pdev)
15242 /* 5704 can be configured in single-port mode, set peer to
15243 * tp->pdev in that case.
15251 * We don't need to keep the refcount elevated; there's no way
15252 * to remove one half of this device without removing the other
15259 static void __devinit tg3_init_coal(struct tg3 *tp)
15261 struct ethtool_coalesce *ec = &tp->coal;
15263 memset(ec, 0, sizeof(*ec));
15264 ec->cmd = ETHTOOL_GCOALESCE;
15265 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
15266 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
15267 ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
15268 ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
15269 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
15270 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
15271 ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
15272 ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
15273 ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
15275 if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
15276 HOSTCC_MODE_CLRTICK_TXBD)) {
15277 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
15278 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
15279 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
15280 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
15283 if (tg3_flag(tp, 5705_PLUS)) {
15284 ec->rx_coalesce_usecs_irq = 0;
15285 ec->tx_coalesce_usecs_irq = 0;
15286 ec->stats_block_coalesce_usecs = 0;
15290 static const struct net_device_ops tg3_netdev_ops = {
15291 .ndo_open = tg3_open,
15292 .ndo_stop = tg3_close,
15293 .ndo_start_xmit = tg3_start_xmit,
15294 .ndo_get_stats64 = tg3_get_stats64,
15295 .ndo_validate_addr = eth_validate_addr,
15296 .ndo_set_rx_mode = tg3_set_rx_mode,
15297 .ndo_set_mac_address = tg3_set_mac_addr,
15298 .ndo_do_ioctl = tg3_ioctl,
15299 .ndo_tx_timeout = tg3_tx_timeout,
15300 .ndo_change_mtu = tg3_change_mtu,
15301 .ndo_fix_features = tg3_fix_features,
15302 .ndo_set_features = tg3_set_features,
15303 #ifdef CONFIG_NET_POLL_CONTROLLER
15304 .ndo_poll_controller = tg3_poll_controller,
15308 static int __devinit tg3_init_one(struct pci_dev *pdev,
15309 const struct pci_device_id *ent)
15311 struct net_device *dev;
15313 int i, err, pm_cap;
15314 u32 sndmbx, rcvmbx, intmbx;
15316 u64 dma_mask, persist_dma_mask;
15317 netdev_features_t features = 0;
15319 printk_once(KERN_INFO "%s\n", version);
15321 err = pci_enable_device(pdev);
15323 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
15327 err = pci_request_regions(pdev, DRV_MODULE_NAME);
15329 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n");
15330 goto err_out_disable_pdev;
15333 pci_set_master(pdev);
15335 /* Find power-management capability. */
15336 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
15338 dev_err(&pdev->dev,
15339 "Cannot find Power Management capability, aborting\n");
15341 goto err_out_free_res;
15344 err = pci_set_power_state(pdev, PCI_D0);
15346 dev_err(&pdev->dev, "Transition to D0 failed, aborting\n");
15347 goto err_out_free_res;
15350 dev = alloc_etherdev_mq(sizeof(*tp), TG3_IRQ_MAX_VECS);
15352 dev_err(&pdev->dev, "Etherdev alloc failed, aborting\n");
15354 goto err_out_power_down;
15357 SET_NETDEV_DEV(dev, &pdev->dev);
15359 tp = netdev_priv(dev);
15362 tp->pm_cap = pm_cap;
15363 tp->rx_mode = TG3_DEF_RX_MODE;
15364 tp->tx_mode = TG3_DEF_TX_MODE;
15367 tp->msg_enable = tg3_debug;
15369 tp->msg_enable = TG3_DEF_MSG_ENABLE;
15371 /* The word/byte swap controls here control register access byte
15372 * swapping. DMA data byte swapping is controlled in the GRC_MODE
15375 tp->misc_host_ctrl =
15376 MISC_HOST_CTRL_MASK_PCI_INT |
15377 MISC_HOST_CTRL_WORD_SWAP |
15378 MISC_HOST_CTRL_INDIR_ACCESS |
15379 MISC_HOST_CTRL_PCISTATE_RW;
15381 /* The NONFRM (non-frame) byte/word swap controls take effect
15382 * on descriptor entries, anything which isn't packet data.
15384 * The StrongARM chips on the board (one for tx, one for rx)
15385 * are running in big-endian mode.
15387 tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
15388 GRC_MODE_WSWAP_NONFRM_DATA);
15389 #ifdef __BIG_ENDIAN
15390 tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
15392 spin_lock_init(&tp->lock);
15393 spin_lock_init(&tp->indirect_lock);
15394 INIT_WORK(&tp->reset_task, tg3_reset_task);
15396 tp->regs = pci_ioremap_bar(pdev, BAR_0);
15398 dev_err(&pdev->dev, "Cannot map device registers, aborting\n");
15400 goto err_out_free_dev;
15403 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
15404 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761E ||
15405 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S ||
15406 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761SE ||
15407 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 ||
15408 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 ||
15409 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5719 ||
15410 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5720) {
15411 tg3_flag_set(tp, ENABLE_APE);
15412 tp->aperegs = pci_ioremap_bar(pdev, BAR_2);
15413 if (!tp->aperegs) {
15414 dev_err(&pdev->dev,
15415 "Cannot map APE registers, aborting\n");
15417 goto err_out_iounmap;
15421 tp->rx_pending = TG3_DEF_RX_RING_PENDING;
15422 tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
15424 dev->ethtool_ops = &tg3_ethtool_ops;
15425 dev->watchdog_timeo = TG3_TX_TIMEOUT;
15426 dev->netdev_ops = &tg3_netdev_ops;
15427 dev->irq = pdev->irq;
15429 err = tg3_get_invariants(tp);
15431 dev_err(&pdev->dev,
15432 "Problem fetching invariants of chip, aborting\n");
15433 goto err_out_apeunmap;
15436 /* The EPB bridge inside 5714, 5715, and 5780 and any
15437 * device behind the EPB cannot support DMA addresses > 40-bit.
15438 * On 64-bit systems with IOMMU, use 40-bit dma_mask.
15439 * On 64-bit systems without IOMMU, use 64-bit dma_mask and
15440 * do DMA address check in tg3_start_xmit().
15442 if (tg3_flag(tp, IS_5788))
15443 persist_dma_mask = dma_mask = DMA_BIT_MASK(32);
15444 else if (tg3_flag(tp, 40BIT_DMA_BUG)) {
15445 persist_dma_mask = dma_mask = DMA_BIT_MASK(40);
15446 #ifdef CONFIG_HIGHMEM
15447 dma_mask = DMA_BIT_MASK(64);
15450 persist_dma_mask = dma_mask = DMA_BIT_MASK(64);
15452 /* Configure DMA attributes. */
15453 if (dma_mask > DMA_BIT_MASK(32)) {
15454 err = pci_set_dma_mask(pdev, dma_mask);
15456 features |= NETIF_F_HIGHDMA;
15457 err = pci_set_consistent_dma_mask(pdev,
15460 dev_err(&pdev->dev, "Unable to obtain 64 bit "
15461 "DMA for consistent allocations\n");
15462 goto err_out_apeunmap;
15466 if (err || dma_mask == DMA_BIT_MASK(32)) {
15467 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
15469 dev_err(&pdev->dev,
15470 "No usable DMA configuration, aborting\n");
15471 goto err_out_apeunmap;
15475 tg3_init_bufmgr_config(tp);
15477 features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
15479 /* 5700 B0 chips do not support checksumming correctly due
15480 * to hardware bugs.
15482 if (tp->pci_chip_rev_id != CHIPREV_ID_5700_B0) {
15483 features |= NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_RXCSUM;
15485 if (tg3_flag(tp, 5755_PLUS))
15486 features |= NETIF_F_IPV6_CSUM;
15489 /* TSO is on by default on chips that support hardware TSO.
15490 * Firmware TSO on older chips gives lower performance, so it
15491 * is off by default, but can be enabled using ethtool.
15493 if ((tg3_flag(tp, HW_TSO_1) ||
15494 tg3_flag(tp, HW_TSO_2) ||
15495 tg3_flag(tp, HW_TSO_3)) &&
15496 (features & NETIF_F_IP_CSUM))
15497 features |= NETIF_F_TSO;
15498 if (tg3_flag(tp, HW_TSO_2) || tg3_flag(tp, HW_TSO_3)) {
15499 if (features & NETIF_F_IPV6_CSUM)
15500 features |= NETIF_F_TSO6;
15501 if (tg3_flag(tp, HW_TSO_3) ||
15502 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
15503 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
15504 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
15505 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
15506 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
15507 features |= NETIF_F_TSO_ECN;
15510 dev->features |= features;
15511 dev->vlan_features |= features;
15514 * Add loopback capability only for a subset of devices that support
15515 * MAC-LOOPBACK. Eventually this need to be enhanced to allow INT-PHY
15516 * loopback for the remaining devices.
15518 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5780 &&
15519 !tg3_flag(tp, CPMU_PRESENT))
15520 /* Add the loopback capability */
15521 features |= NETIF_F_LOOPBACK;
15523 dev->hw_features |= features;
15525 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
15526 !tg3_flag(tp, TSO_CAPABLE) &&
15527 !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
15528 tg3_flag_set(tp, MAX_RXPEND_64);
15529 tp->rx_pending = 63;
15532 err = tg3_get_device_address(tp);
15534 dev_err(&pdev->dev,
15535 "Could not obtain valid ethernet address, aborting\n");
15536 goto err_out_apeunmap;
15540 * Reset chip in case UNDI or EFI driver did not shutdown
15541 * DMA self test will enable WDMAC and we'll see (spurious)
15542 * pending DMA on the PCI bus at that point.
15544 if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
15545 (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
15546 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
15547 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
15550 err = tg3_test_dma(tp);
15552 dev_err(&pdev->dev, "DMA engine test failed, aborting\n");
15553 goto err_out_apeunmap;
15556 intmbx = MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW;
15557 rcvmbx = MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW;
15558 sndmbx = MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW;
15559 for (i = 0; i < tp->irq_max; i++) {
15560 struct tg3_napi *tnapi = &tp->napi[i];
15563 tnapi->tx_pending = TG3_DEF_TX_RING_PENDING;
15565 tnapi->int_mbox = intmbx;
15571 tnapi->consmbox = rcvmbx;
15572 tnapi->prodmbox = sndmbx;
15575 tnapi->coal_now = HOSTCC_MODE_COAL_VEC1_NOW << (i - 1);
15577 tnapi->coal_now = HOSTCC_MODE_NOW;
15579 if (!tg3_flag(tp, SUPPORT_MSIX))
15583 * If we support MSIX, we'll be using RSS. If we're using
15584 * RSS, the first vector only handles link interrupts and the
15585 * remaining vectors handle rx and tx interrupts. Reuse the
15586 * mailbox values for the next iteration. The values we setup
15587 * above are still useful for the single vectored mode.
15602 pci_set_drvdata(pdev, dev);
15604 if (tg3_flag(tp, 5717_PLUS)) {
15605 /* Resume a low-power mode */
15606 tg3_frob_aux_power(tp, false);
15609 err = register_netdev(dev);
15611 dev_err(&pdev->dev, "Cannot register net device, aborting\n");
15612 goto err_out_apeunmap;
15615 netdev_info(dev, "Tigon3 [partno(%s) rev %04x] (%s) MAC address %pM\n",
15616 tp->board_part_number,
15617 tp->pci_chip_rev_id,
15618 tg3_bus_string(tp, str),
15621 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
15622 struct phy_device *phydev;
15623 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
15625 "attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
15626 phydev->drv->name, dev_name(&phydev->dev));
15630 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
15631 ethtype = "10/100Base-TX";
15632 else if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
15633 ethtype = "1000Base-SX";
15635 ethtype = "10/100/1000Base-T";
15637 netdev_info(dev, "attached PHY is %s (%s Ethernet) "
15638 "(WireSpeed[%d], EEE[%d])\n",
15639 tg3_phy_string(tp), ethtype,
15640 (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED) == 0,
15641 (tp->phy_flags & TG3_PHYFLG_EEE_CAP) != 0);
15644 netdev_info(dev, "RXcsums[%d] LinkChgREG[%d] MIirq[%d] ASF[%d] TSOcap[%d]\n",
15645 (dev->features & NETIF_F_RXCSUM) != 0,
15646 tg3_flag(tp, USE_LINKCHG_REG) != 0,
15647 (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) != 0,
15648 tg3_flag(tp, ENABLE_ASF) != 0,
15649 tg3_flag(tp, TSO_CAPABLE) != 0);
15650 netdev_info(dev, "dma_rwctrl[%08x] dma_mask[%d-bit]\n",
15652 pdev->dma_mask == DMA_BIT_MASK(32) ? 32 :
15653 ((u64)pdev->dma_mask) == DMA_BIT_MASK(40) ? 40 : 64);
15655 pci_save_state(pdev);
15661 iounmap(tp->aperegs);
15662 tp->aperegs = NULL;
15674 err_out_power_down:
15675 pci_set_power_state(pdev, PCI_D3hot);
15678 pci_release_regions(pdev);
15680 err_out_disable_pdev:
15681 pci_disable_device(pdev);
15682 pci_set_drvdata(pdev, NULL);
15686 static void __devexit tg3_remove_one(struct pci_dev *pdev)
15688 struct net_device *dev = pci_get_drvdata(pdev);
15691 struct tg3 *tp = netdev_priv(dev);
15694 release_firmware(tp->fw);
15696 tg3_reset_task_cancel(tp);
15698 if (tg3_flag(tp, USE_PHYLIB)) {
15703 unregister_netdev(dev);
15705 iounmap(tp->aperegs);
15706 tp->aperegs = NULL;
15713 pci_release_regions(pdev);
15714 pci_disable_device(pdev);
15715 pci_set_drvdata(pdev, NULL);
15719 #ifdef CONFIG_PM_SLEEP
15720 static int tg3_suspend(struct device *device)
15722 struct pci_dev *pdev = to_pci_dev(device);
15723 struct net_device *dev = pci_get_drvdata(pdev);
15724 struct tg3 *tp = netdev_priv(dev);
15727 if (!netif_running(dev))
15730 tg3_reset_task_cancel(tp);
15732 tg3_netif_stop(tp);
15734 del_timer_sync(&tp->timer);
15736 tg3_full_lock(tp, 1);
15737 tg3_disable_ints(tp);
15738 tg3_full_unlock(tp);
15740 netif_device_detach(dev);
15742 tg3_full_lock(tp, 0);
15743 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
15744 tg3_flag_clear(tp, INIT_COMPLETE);
15745 tg3_full_unlock(tp);
15747 err = tg3_power_down_prepare(tp);
15751 tg3_full_lock(tp, 0);
15753 tg3_flag_set(tp, INIT_COMPLETE);
15754 err2 = tg3_restart_hw(tp, 1);
15758 tp->timer.expires = jiffies + tp->timer_offset;
15759 add_timer(&tp->timer);
15761 netif_device_attach(dev);
15762 tg3_netif_start(tp);
15765 tg3_full_unlock(tp);
15774 static int tg3_resume(struct device *device)
15776 struct pci_dev *pdev = to_pci_dev(device);
15777 struct net_device *dev = pci_get_drvdata(pdev);
15778 struct tg3 *tp = netdev_priv(dev);
15781 if (!netif_running(dev))
15784 netif_device_attach(dev);
15786 tg3_full_lock(tp, 0);
15788 tg3_flag_set(tp, INIT_COMPLETE);
15789 err = tg3_restart_hw(tp, 1);
15793 tp->timer.expires = jiffies + tp->timer_offset;
15794 add_timer(&tp->timer);
15796 tg3_netif_start(tp);
15799 tg3_full_unlock(tp);
15807 static SIMPLE_DEV_PM_OPS(tg3_pm_ops, tg3_suspend, tg3_resume);
15808 #define TG3_PM_OPS (&tg3_pm_ops)
15812 #define TG3_PM_OPS NULL
15814 #endif /* CONFIG_PM_SLEEP */
15817 * tg3_io_error_detected - called when PCI error is detected
15818 * @pdev: Pointer to PCI device
15819 * @state: The current pci connection state
15821 * This function is called after a PCI bus error affecting
15822 * this device has been detected.
15824 static pci_ers_result_t tg3_io_error_detected(struct pci_dev *pdev,
15825 pci_channel_state_t state)
15827 struct net_device *netdev = pci_get_drvdata(pdev);
15828 struct tg3 *tp = netdev_priv(netdev);
15829 pci_ers_result_t err = PCI_ERS_RESULT_NEED_RESET;
15831 netdev_info(netdev, "PCI I/O error detected\n");
15835 if (!netif_running(netdev))
15840 tg3_netif_stop(tp);
15842 del_timer_sync(&tp->timer);
15844 /* Want to make sure that the reset task doesn't run */
15845 tg3_reset_task_cancel(tp);
15846 tg3_flag_clear(tp, TX_RECOVERY_PENDING);
15848 netif_device_detach(netdev);
15850 /* Clean up software state, even if MMIO is blocked */
15851 tg3_full_lock(tp, 0);
15852 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
15853 tg3_full_unlock(tp);
15856 if (state == pci_channel_io_perm_failure)
15857 err = PCI_ERS_RESULT_DISCONNECT;
15859 pci_disable_device(pdev);
15867 * tg3_io_slot_reset - called after the pci bus has been reset.
15868 * @pdev: Pointer to PCI device
15870 * Restart the card from scratch, as if from a cold-boot.
15871 * At this point, the card has exprienced a hard reset,
15872 * followed by fixups by BIOS, and has its config space
15873 * set up identically to what it was at cold boot.
15875 static pci_ers_result_t tg3_io_slot_reset(struct pci_dev *pdev)
15877 struct net_device *netdev = pci_get_drvdata(pdev);
15878 struct tg3 *tp = netdev_priv(netdev);
15879 pci_ers_result_t rc = PCI_ERS_RESULT_DISCONNECT;
15884 if (pci_enable_device(pdev)) {
15885 netdev_err(netdev, "Cannot re-enable PCI device after reset.\n");
15889 pci_set_master(pdev);
15890 pci_restore_state(pdev);
15891 pci_save_state(pdev);
15893 if (!netif_running(netdev)) {
15894 rc = PCI_ERS_RESULT_RECOVERED;
15898 err = tg3_power_up(tp);
15902 rc = PCI_ERS_RESULT_RECOVERED;
15911 * tg3_io_resume - called when traffic can start flowing again.
15912 * @pdev: Pointer to PCI device
15914 * This callback is called when the error recovery driver tells
15915 * us that its OK to resume normal operation.
15917 static void tg3_io_resume(struct pci_dev *pdev)
15919 struct net_device *netdev = pci_get_drvdata(pdev);
15920 struct tg3 *tp = netdev_priv(netdev);
15925 if (!netif_running(netdev))
15928 tg3_full_lock(tp, 0);
15929 tg3_flag_set(tp, INIT_COMPLETE);
15930 err = tg3_restart_hw(tp, 1);
15931 tg3_full_unlock(tp);
15933 netdev_err(netdev, "Cannot restart hardware after reset.\n");
15937 netif_device_attach(netdev);
15939 tp->timer.expires = jiffies + tp->timer_offset;
15940 add_timer(&tp->timer);
15942 tg3_netif_start(tp);
15950 static struct pci_error_handlers tg3_err_handler = {
15951 .error_detected = tg3_io_error_detected,
15952 .slot_reset = tg3_io_slot_reset,
15953 .resume = tg3_io_resume
15956 static struct pci_driver tg3_driver = {
15957 .name = DRV_MODULE_NAME,
15958 .id_table = tg3_pci_tbl,
15959 .probe = tg3_init_one,
15960 .remove = __devexit_p(tg3_remove_one),
15961 .err_handler = &tg3_err_handler,
15962 .driver.pm = TG3_PM_OPS,
15965 static int __init tg3_init(void)
15967 return pci_register_driver(&tg3_driver);
15970 static void __exit tg3_cleanup(void)
15972 pci_unregister_driver(&tg3_driver);
15975 module_init(tg3_init);
15976 module_exit(tg3_cleanup);