drivers/net/ethernet/broadcom/genet/bcmmii.c

   1 /*
   2  * Broadcom GENET MDIO routines
   3  *
   4  * Copyright (c) 2014-2017 Broadcom
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  */
  10
  11
  12 #include <linux/types.h>
  13 #include <linux/delay.h>
  14 #include <linux/wait.h>
  15 #include <linux/mii.h>
  16 #include <linux/ethtool.h>
  17 #include <linux/bitops.h>
  18 #include <linux/netdevice.h>
  19 #include <linux/platform_device.h>
  20 #include <linux/phy.h>
  21 #include <linux/phy_fixed.h>
  22 #include <linux/brcmphy.h>
  23 #include <linux/of.h>
  24 #include <linux/of_net.h>
  25 #include <linux/of_mdio.h>
  26 #include <linux/platform_data/bcmgenet.h>
  27
  28 #include "bcmgenet.h"
  29
  30 /* read a value from the MII */
  31 static int bcmgenet_mii_read(struct mii_bus *bus, int phy_id, int location)
  32 {
  33         int ret;
  34         struct net_device *dev = bus->priv;
  35         struct bcmgenet_priv *priv = netdev_priv(dev);
  36         u32 reg;
  37
  38         bcmgenet_umac_writel(priv, (MDIO_RD | (phy_id << MDIO_PMD_SHIFT) |
  39                              (location << MDIO_REG_SHIFT)), UMAC_MDIO_CMD);
  40         /* Start MDIO transaction*/
  41         reg = bcmgenet_umac_readl(priv, UMAC_MDIO_CMD);
  42         reg |= MDIO_START_BUSY;
  43         bcmgenet_umac_writel(priv, reg, UMAC_MDIO_CMD);
  44         wait_event_timeout(priv->wq,
  45                            !(bcmgenet_umac_readl(priv, UMAC_MDIO_CMD)
  46                            & MDIO_START_BUSY),
  47                            HZ / 100);
  48         ret = bcmgenet_umac_readl(priv, UMAC_MDIO_CMD);
  49
  50         /* Some broken devices are known not to release the line during
  51          * turn-around, e.g: Broadcom BCM53125 external switches, so check for
  52          * that condition here and ignore the MDIO controller read failure
  53          * indication.
  54          */
  55         if (!(bus->phy_ignore_ta_mask & 1 << phy_id) && (ret & MDIO_READ_FAIL))
  56                 return -EIO;
  57
  58         return ret & 0xffff;
  59 }
  60
  61 /* write a value to the MII */
  62 static int bcmgenet_mii_write(struct mii_bus *bus, int phy_id,
  63                               int location, u16 val)
  64 {
  65         struct net_device *dev = bus->priv;
  66         struct bcmgenet_priv *priv = netdev_priv(dev);
  67         u32 reg;
  68
  69         bcmgenet_umac_writel(priv, (MDIO_WR | (phy_id << MDIO_PMD_SHIFT) |
  70                              (location << MDIO_REG_SHIFT) | (0xffff & val)),
  71                              UMAC_MDIO_CMD);
  72         reg = bcmgenet_umac_readl(priv, UMAC_MDIO_CMD);
  73         reg |= MDIO_START_BUSY;
  74         bcmgenet_umac_writel(priv, reg, UMAC_MDIO_CMD);
  75         wait_event_timeout(priv->wq,
  76                            !(bcmgenet_umac_readl(priv, UMAC_MDIO_CMD) &
  77                            MDIO_START_BUSY),
  78                            HZ / 100);
  79
  80         return 0;
  81 }
  82
  83 /* setup netdev link state when PHY link status change and
  84  * update UMAC and RGMII block when link up
  85  */
  86 void bcmgenet_mii_setup(struct net_device *dev)
  87 {
  88         struct bcmgenet_priv *priv = netdev_priv(dev);
  89         struct phy_device *phydev = priv->phydev;
  90         u32 reg, cmd_bits = 0;
  91         bool status_changed = false;
  92
  93         if (priv->old_link != phydev->link) {
  94                 status_changed = true;
  95                 priv->old_link = phydev->link;
  96         }
  97
  98         if (phydev->link) {
  99                 /* check speed/duplex/pause changes */
 100                 if (priv->old_speed != phydev->speed) {
 101                         status_changed = true;
 102                         priv->old_speed = phydev->speed;
 103                 }
 104
 105                 if (priv->old_duplex != phydev->duplex) {
 106                         status_changed = true;
 107                         priv->old_duplex = phydev->duplex;
 108                 }
 109
 110                 if (priv->old_pause != phydev->pause) {
 111                         status_changed = true;
 112                         priv->old_pause = phydev->pause;
 113                 }
 114
 115                 /* done if nothing has changed */
 116                 if (!status_changed)
 117                         return;
 118
 119                 /* speed */
 120                 if (phydev->speed == SPEED_1000)
 121                         cmd_bits = UMAC_SPEED_1000;
 122                 else if (phydev->speed == SPEED_100)
 123                         cmd_bits = UMAC_SPEED_100;
 124                 else
 125                         cmd_bits = UMAC_SPEED_10;
 126                 cmd_bits <<= CMD_SPEED_SHIFT;
 127
 128                 /* duplex */
 129                 if (phydev->duplex != DUPLEX_FULL)
 130                         cmd_bits |= CMD_HD_EN;
 131
 132                 /* pause capability */
 133                 if (!phydev->pause)
 134                         cmd_bits |= CMD_RX_PAUSE_IGNORE | CMD_TX_PAUSE_IGNORE;
 135
 136                 /*
 137                  * Program UMAC and RGMII block based on established
 138                  * link speed, duplex, and pause. The speed set in
 139                  * umac->cmd tell RGMII block which clock to use for
 140                  * transmit -- 25MHz(100Mbps) or 125MHz(1Gbps).
 141                  * Receive clock is provided by the PHY.
 142                  */
 143                 reg = bcmgenet_ext_readl(priv, EXT_RGMII_OOB_CTRL);
 144                 reg &= ~OOB_DISABLE;
 145                 reg |= RGMII_LINK;
 146                 bcmgenet_ext_writel(priv, reg, EXT_RGMII_OOB_CTRL);
 147
 148                 reg = bcmgenet_umac_readl(priv, UMAC_CMD);
 149                 reg &= ~((CMD_SPEED_MASK << CMD_SPEED_SHIFT) |
 150                                CMD_HD_EN |
 151                                CMD_RX_PAUSE_IGNORE | CMD_TX_PAUSE_IGNORE);
 152                 reg |= cmd_bits;
 153                 bcmgenet_umac_writel(priv, reg, UMAC_CMD);
 154         } else {
 155                 /* done if nothing has changed */
 156                 if (!status_changed)
 157                         return;
 158
 159                 /* needed for MoCA fixed PHY to reflect correct link status */
 160                 netif_carrier_off(dev);
 161         }
 162
 163         phy_print_status(phydev);
 164 }
 165
 166
 167 static int bcmgenet_fixed_phy_link_update(struct net_device *dev,
 168                                           struct fixed_phy_status *status)
 169 {
 170         if (dev && dev->phydev && status)
 171                 status->link = dev->phydev->link;
 172
 173         return 0;
 174 }
 175
 176 /* Perform a voluntary PHY software reset, since the EPHY is very finicky about
 177  * not doing it and will start corrupting packets
 178  */
 179 void bcmgenet_mii_reset(struct net_device *dev)
 180 {
 181         struct bcmgenet_priv *priv = netdev_priv(dev);
 182
 183         if (GENET_IS_V4(priv))
 184                 return;
 185
 186         if (priv->phydev) {
 187                 phy_init_hw(priv->phydev);
 188                 phy_start_aneg(priv->phydev);
 189         }
 190 }
 191
 192 void bcmgenet_phy_power_set(struct net_device *dev, bool enable)
 193 {
 194         struct bcmgenet_priv *priv = netdev_priv(dev);
 195         u32 reg = 0;
 196
 197         /* EXT_GPHY_CTRL is only valid for GENETv4 and onward */
 198         if (GENET_IS_V4(priv)) {
 199                 reg = bcmgenet_ext_readl(priv, EXT_GPHY_CTRL);
 200                 if (enable) {
 201                         reg &= ~EXT_CK25_DIS;
 202                         bcmgenet_ext_writel(priv, reg, EXT_GPHY_CTRL);
 203                         mdelay(1);
 204
 205                         reg &= ~(EXT_CFG_IDDQ_BIAS | EXT_CFG_PWR_DOWN);
 206                         reg |= EXT_GPHY_RESET;
 207                         bcmgenet_ext_writel(priv, reg, EXT_GPHY_CTRL);
 208                         mdelay(1);
 209
 210                         reg &= ~EXT_GPHY_RESET;
 211                 } else {
 212                         reg |= EXT_CFG_IDDQ_BIAS | EXT_CFG_PWR_DOWN |
 213                                EXT_GPHY_RESET;
 214                         bcmgenet_ext_writel(priv, reg, EXT_GPHY_CTRL);
 215                         mdelay(1);
 216                         reg |= EXT_CK25_DIS;
 217                 }
 218                 bcmgenet_ext_writel(priv, reg, EXT_GPHY_CTRL);
 219                 udelay(60);
 220         } else {
 221                 mdelay(1);
 222         }
 223 }
 224
 225 static void bcmgenet_internal_phy_setup(struct net_device *dev)
 226 {
 227         struct bcmgenet_priv *priv = netdev_priv(dev);
 228         u32 reg;
 229
 230         /* Power up PHY */
 231         bcmgenet_phy_power_set(dev, true);
 232         if (!GENET_IS_V5(priv)) {
 233                 /* enable APD */
 234                 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
 235                 reg |= EXT_PWR_DN_EN_LD;
 236                 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
 237         }
 238         bcmgenet_mii_reset(dev);
 239 }
 240
 241 static void bcmgenet_moca_phy_setup(struct bcmgenet_priv *priv)
 242 {
 243         u32 reg;
 244
 245         if (!GENET_IS_V5(priv)) {
 246                 /* Speed settings are set in bcmgenet_mii_setup() */
 247                 reg = bcmgenet_sys_readl(priv, SYS_PORT_CTRL);
 248                 reg |= LED_ACT_SOURCE_MAC;
 249                 bcmgenet_sys_writel(priv, reg, SYS_PORT_CTRL);
 250         }
 251
 252         if (priv->hw_params->flags & GENET_HAS_MOCA_LINK_DET)
 253                 fixed_phy_set_link_update(priv->phydev,
 254                                           bcmgenet_fixed_phy_link_update);
 255 }
 256
 257 int bcmgenet_mii_config(struct net_device *dev)
 258 {
 259         struct bcmgenet_priv *priv = netdev_priv(dev);
 260         struct phy_device *phydev = priv->phydev;
 261         struct device *kdev = &priv->pdev->dev;
 262         const char *phy_name = NULL;
 263         u32 id_mode_dis = 0;
 264         u32 port_ctrl;
 265         u32 reg;
 266
 267         priv->ext_phy = !priv->internal_phy &&
 268                         (priv->phy_interface != PHY_INTERFACE_MODE_MOCA);
 269
 270         if (priv->internal_phy)
 271                 priv->phy_interface = PHY_INTERFACE_MODE_NA;
 272
 273         switch (priv->phy_interface) {
 274         case PHY_INTERFACE_MODE_NA:
 275         case PHY_INTERFACE_MODE_MOCA:
 276                 /* Irrespective of the actually configured PHY speed (100 or
 277                  * 1000) GENETv4 only has an internal GPHY so we will just end
 278                  * up masking the Gigabit features from what we support, not
 279                  * switching to the EPHY
 280                  */
 281                 if (GENET_IS_V4(priv))
 282                         port_ctrl = PORT_MODE_INT_GPHY;
 283                 else
 284                         port_ctrl = PORT_MODE_INT_EPHY;
 285
 286                 bcmgenet_sys_writel(priv, port_ctrl, SYS_PORT_CTRL);
 287
 288                 if (priv->internal_phy) {
 289                         phy_name = "internal PHY";
 290                         bcmgenet_internal_phy_setup(dev);
 291                 } else if (priv->phy_interface == PHY_INTERFACE_MODE_MOCA) {
 292                         phy_name = "MoCA";
 293                         bcmgenet_moca_phy_setup(priv);
 294                 }
 295                 break;
 296
 297         case PHY_INTERFACE_MODE_MII:
 298                 phy_name = "external MII";
 299                 phydev->supported &= PHY_BASIC_FEATURES;
 300                 bcmgenet_sys_writel(priv,
 301                                     PORT_MODE_EXT_EPHY, SYS_PORT_CTRL);
 302                 break;
 303
 304         case PHY_INTERFACE_MODE_REVMII:
 305                 phy_name = "external RvMII";
 306                 /* of_mdiobus_register took care of reading the 'max-speed'
 307                  * PHY property for us, effectively limiting the PHY supported
 308                  * capabilities, use that knowledge to also configure the
 309                  * Reverse MII interface correctly.
 310                  */
 311                 if ((priv->phydev->supported & PHY_BASIC_FEATURES) ==
 312                                 PHY_BASIC_FEATURES)
 313                         port_ctrl = PORT_MODE_EXT_RVMII_25;
 314                 else
 315                         port_ctrl = PORT_MODE_EXT_RVMII_50;
 316                 bcmgenet_sys_writel(priv, port_ctrl, SYS_PORT_CTRL);
 317                 break;
 318
 319         case PHY_INTERFACE_MODE_RGMII:
 320                 /* RGMII_NO_ID: TXC transitions at the same time as TXD
 321                  *              (requires PCB or receiver-side delay)
 322                  * RGMII:       Add 2ns delay on TXC (90 degree shift)
 323                  *
 324                  * ID is implicitly disabled for 100Mbps (RG)MII operation.
 325                  */
 326                 id_mode_dis = BIT(16);
 327                 /* fall through */
 328         case PHY_INTERFACE_MODE_RGMII_TXID:
 329                 if (id_mode_dis)
 330                         phy_name = "external RGMII (no delay)";
 331                 else
 332                         phy_name = "external RGMII (TX delay)";
 333                 bcmgenet_sys_writel(priv,
 334                                     PORT_MODE_EXT_GPHY, SYS_PORT_CTRL);
 335                 break;
 336         default:
 337                 dev_err(kdev, "unknown phy mode: %d\n", priv->phy_interface);
 338                 return -EINVAL;
 339         }
 340
 341         /* This is an external PHY (xMII), so we need to enable the RGMII
 342          * block for the interface to work
 343          */
 344         if (priv->ext_phy) {
 345                 reg = bcmgenet_ext_readl(priv, EXT_RGMII_OOB_CTRL);
 346                 reg |= RGMII_MODE_EN | id_mode_dis;
 347                 bcmgenet_ext_writel(priv, reg, EXT_RGMII_OOB_CTRL);
 348         }
 349
 350         dev_info_once(kdev, "configuring instance for %s\n", phy_name);
 351
 352         return 0;
 353 }
 354
 355 int bcmgenet_mii_probe(struct net_device *dev)
 356 {
 357         struct bcmgenet_priv *priv = netdev_priv(dev);
 358         struct device_node *dn = priv->pdev->dev.of_node;
 359         struct phy_device *phydev;
 360         u32 phy_flags;
 361         int ret;
 362
 363         /* Communicate the integrated PHY revision */
 364         phy_flags = priv->gphy_rev;
 365
 366         /* Initialize link state variables that bcmgenet_mii_setup() uses */
 367         priv->old_link = -1;
 368         priv->old_speed = -1;
 369         priv->old_duplex = -1;
 370         priv->old_pause = -1;
 371
 372         if (dn) {
 373                 phydev = of_phy_connect(dev, priv->phy_dn, bcmgenet_mii_setup,
 374                                         phy_flags, priv->phy_interface);
 375                 if (!phydev) {
 376                         pr_err("could not attach to PHY\n");
 377                         return -ENODEV;
 378                 }
 379         } else {
 380                 phydev = priv->phydev;
 381                 phydev->dev_flags = phy_flags;
 382
 383                 ret = phy_connect_direct(dev, phydev, bcmgenet_mii_setup,
 384                                          priv->phy_interface);
 385                 if (ret) {
 386                         pr_err("could not attach to PHY\n");
 387                         return -ENODEV;
 388                 }
 389         }
 390
 391         priv->phydev = phydev;
 392
 393         /* Configure port multiplexer based on what the probed PHY device since
 394          * reading the 'max-speed' property determines the maximum supported
 395          * PHY speed which is needed for bcmgenet_mii_config() to configure
 396          * things appropriately.
 397          */
 398         ret = bcmgenet_mii_config(dev);
 399         if (ret) {
 400                 phy_disconnect(priv->phydev);
 401                 return ret;
 402         }
 403
 404         phydev->advertising = phydev->supported;
 405
 406         /* The internal PHY has its link interrupts routed to the
 407          * Ethernet MAC ISRs
 408          */
 409         if (priv->internal_phy)
 410                 priv->phydev->irq = PHY_IGNORE_INTERRUPT;
 411
 412         return 0;
 413 }
 414
 415 /* Workaround for integrated BCM7xxx Gigabit PHYs which have a problem with
 416  * their internal MDIO management controller making them fail to successfully
 417  * be read from or written to for the first transaction.  We insert a dummy
 418  * BMSR read here to make sure that phy_get_device() and get_phy_id() can
 419  * correctly read the PHY MII_PHYSID1/2 registers and successfully register a
 420  * PHY device for this peripheral.
 421  *
 422  * Once the PHY driver is registered, we can workaround subsequent reads from
 423  * there (e.g: during system-wide power management).
 424  *
 425  * bus->reset is invoked before mdiobus_scan during mdiobus_register and is
 426  * therefore the right location to stick that workaround. Since we do not want
 427  * to read from non-existing PHYs, we either use bus->phy_mask or do a manual
 428  * Device Tree scan to limit the search area.
 429  */
 430 static int bcmgenet_mii_bus_reset(struct mii_bus *bus)
 431 {
 432         struct net_device *dev = bus->priv;
 433         struct bcmgenet_priv *priv = netdev_priv(dev);
 434         struct device_node *np = priv->mdio_dn;
 435         struct device_node *child = NULL;
 436         u32 read_mask = 0;
 437         int addr = 0;
 438
 439         if (!np) {
 440                 read_mask = 1 << priv->phy_addr;
 441         } else {
 442                 for_each_available_child_of_node(np, child) {
 443                         addr = of_mdio_parse_addr(&dev->dev, child);
 444                         if (addr < 0)
 445                                 continue;
 446
 447                         read_mask |= 1 << addr;
 448                 }
 449         }
 450
 451         for (addr = 0; addr < PHY_MAX_ADDR; addr++) {
 452                 if (read_mask & 1 << addr) {
 453                         dev_dbg(&dev->dev, "Workaround for PHY @ %d\n", addr);
 454                         mdiobus_read(bus, addr, MII_BMSR);
 455                 }
 456         }
 457
 458         return 0;
 459 }
 460
 461 static int bcmgenet_mii_alloc(struct bcmgenet_priv *priv)
 462 {
 463         struct mii_bus *bus;
 464
 465         if (priv->mii_bus)
 466                 return 0;
 467
 468         priv->mii_bus = mdiobus_alloc();
 469         if (!priv->mii_bus) {
 470                 pr_err("failed to allocate\n");
 471                 return -ENOMEM;
 472         }
 473
 474         bus = priv->mii_bus;
 475         bus->priv = priv->dev;
 476         bus->name = "bcmgenet MII bus";
 477         bus->parent = &priv->pdev->dev;
 478         bus->read = bcmgenet_mii_read;
 479         bus->write = bcmgenet_mii_write;
 480         bus->reset = bcmgenet_mii_bus_reset;
 481         snprintf(bus->id, MII_BUS_ID_SIZE, "%s-%d",
 482                  priv->pdev->name, priv->pdev->id);
 483
 484         return 0;
 485 }
 486
 487 static int bcmgenet_mii_of_init(struct bcmgenet_priv *priv)
 488 {
 489         struct device_node *dn = priv->pdev->dev.of_node;
 490         struct device *kdev = &priv->pdev->dev;
 491         const char *phy_mode_str = NULL;
 492         struct phy_device *phydev = NULL;
 493         char *compat;
 494         int phy_mode;
 495         int ret;
 496
 497         compat = kasprintf(GFP_KERNEL, "brcm,genet-mdio-v%d", priv->version);
 498         if (!compat)
 499                 return -ENOMEM;
 500
 501         priv->mdio_dn = of_find_compatible_node(dn, NULL, compat);
 502         kfree(compat);
 503         if (!priv->mdio_dn) {
 504                 dev_err(kdev, "unable to find MDIO bus node\n");
 505                 return -ENODEV;
 506         }
 507
 508         ret = of_mdiobus_register(priv->mii_bus, priv->mdio_dn);
 509         if (ret) {
 510                 dev_err(kdev, "failed to register MDIO bus\n");
 511                 return ret;
 512         }
 513
 514         /* Fetch the PHY phandle */
 515         priv->phy_dn = of_parse_phandle(dn, "phy-handle", 0);
 516
 517         /* In the case of a fixed PHY, the DT node associated
 518          * to the PHY is the Ethernet MAC DT node.
 519          */
 520         if (!priv->phy_dn && of_phy_is_fixed_link(dn)) {
 521                 ret = of_phy_register_fixed_link(dn);
 522                 if (ret)
 523                         return ret;
 524
 525                 priv->phy_dn = of_node_get(dn);
 526         }
 527
 528         /* Get the link mode */
 529         phy_mode = of_get_phy_mode(dn);
 530         priv->phy_interface = phy_mode;
 531
 532         /* We need to specifically look up whether this PHY interface is internal
 533          * or not *before* we even try to probe the PHY driver over MDIO as we
 534          * may have shut down the internal PHY for power saving purposes.
 535          */
 536         if (phy_mode < 0) {
 537                 ret = of_property_read_string(dn, "phy-mode", &phy_mode_str);
 538                 if (ret < 0) {
 539                         dev_err(kdev, "invalid PHY mode property\n");
 540                         return ret;
 541                 }
 542
 543                 priv->phy_interface = PHY_INTERFACE_MODE_NA;
 544                 if (!strcasecmp(phy_mode_str, "internal"))
 545                         priv->internal_phy = true;
 546         }
 547
 548         /* Make sure we initialize MoCA PHYs with a link down */
 549         if (phy_mode == PHY_INTERFACE_MODE_MOCA) {
 550                 phydev = of_phy_find_device(dn);
 551                 if (phydev) {
 552                         phydev->link = 0;
 553                         put_device(&phydev->mdio.dev);
 554                 }
 555         }
 556
 557         return 0;
 558 }
 559
 560 static int bcmgenet_mii_pd_init(struct bcmgenet_priv *priv)
 561 {
 562         struct device *kdev = &priv->pdev->dev;
 563         struct bcmgenet_platform_data *pd = kdev->platform_data;
 564         struct mii_bus *mdio = priv->mii_bus;
 565         struct phy_device *phydev;
 566         int ret;
 567
 568         if (pd->phy_interface != PHY_INTERFACE_MODE_MOCA && pd->mdio_enabled) {
 569                 /*
 570                  * Internal or external PHY with MDIO access
 571                  */
 572                 if (pd->phy_address >= 0 && pd->phy_address < PHY_MAX_ADDR)
 573                         mdio->phy_mask = ~(1 << pd->phy_address);
 574                 else
 575                         mdio->phy_mask = 0;
 576
 577                 ret = mdiobus_register(mdio);
 578                 if (ret) {
 579                         dev_err(kdev, "failed to register MDIO bus\n");
 580                         return ret;
 581                 }
 582
 583                 if (pd->phy_address >= 0 && pd->phy_address < PHY_MAX_ADDR)
 584                         phydev = mdiobus_get_phy(mdio, pd->phy_address);
 585                 else
 586                         phydev = phy_find_first(mdio);
 587
 588                 if (!phydev) {
 589                         dev_err(kdev, "failed to register PHY device\n");
 590                         mdiobus_unregister(mdio);
 591                         return -ENODEV;
 592                 }
 593         } else {
 594                 /*
 595                  * MoCA port or no MDIO access.
 596                  * Use fixed PHY to represent the link layer.
 597                  */
 598                 struct fixed_phy_status fphy_status = {
 599                         .link = 1,
 600                         .speed = pd->phy_speed,
 601                         .duplex = pd->phy_duplex,
 602                         .pause = 0,
 603                         .asym_pause = 0,
 604                 };
 605
 606                 phydev = fixed_phy_register(PHY_POLL, &fphy_status, -1, NULL);
 607                 if (!phydev || IS_ERR(phydev)) {
 608                         dev_err(kdev, "failed to register fixed PHY device\n");
 609                         return -ENODEV;
 610                 }
 611
 612                 /* Make sure we initialize MoCA PHYs with a link down */
 613                 phydev->link = 0;
 614
 615         }
 616
 617         priv->phydev = phydev;
 618         priv->phy_interface = pd->phy_interface;
 619
 620         return 0;
 621 }
 622
 623 static int bcmgenet_mii_bus_init(struct bcmgenet_priv *priv)
 624 {
 625         struct device_node *dn = priv->pdev->dev.of_node;
 626
 627         if (dn)
 628                 return bcmgenet_mii_of_init(priv);
 629         else
 630                 return bcmgenet_mii_pd_init(priv);
 631 }
 632
 633 int bcmgenet_mii_init(struct net_device *dev)
 634 {
 635         struct bcmgenet_priv *priv = netdev_priv(dev);
 636         struct device_node *dn = priv->pdev->dev.of_node;
 637         int ret;
 638
 639         ret = bcmgenet_mii_alloc(priv);
 640         if (ret)
 641                 return ret;
 642
 643         ret = bcmgenet_mii_bus_init(priv);
 644         if (ret)
 645                 goto out;
 646
 647         return 0;
 648
 649 out:
 650         if (of_phy_is_fixed_link(dn))
 651                 of_phy_deregister_fixed_link(dn);
 652         of_node_put(priv->phy_dn);
 653         mdiobus_unregister(priv->mii_bus);
 654         mdiobus_free(priv->mii_bus);
 655         return ret;
 656 }
 657
 658 void bcmgenet_mii_exit(struct net_device *dev)
 659 {
 660         struct bcmgenet_priv *priv = netdev_priv(dev);
 661         struct device_node *dn = priv->pdev->dev.of_node;
 662
 663         if (of_phy_is_fixed_link(dn))
 664                 of_phy_deregister_fixed_link(dn);
 665         of_node_put(priv->phy_dn);
 666         mdiobus_unregister(priv->mii_bus);
 667         mdiobus_free(priv->mii_bus);
 668 }