drivers/net/ethernet/broadcom/genet/bcmgenet.c

   1 /*
   2  * Broadcom GENET (Gigabit Ethernet) controller driver
   3  *
   4  * Copyright (c) 2014-2017 Broadcom
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  */
  10
  11 #define pr_fmt(fmt)                             "bcmgenet: " fmt
  12
  13 #include <linux/kernel.h>
  14 #include <linux/module.h>
  15 #include <linux/sched.h>
  16 #include <linux/types.h>
  17 #include <linux/fcntl.h>
  18 #include <linux/interrupt.h>
  19 #include <linux/string.h>
  20 #include <linux/if_ether.h>
  21 #include <linux/init.h>
  22 #include <linux/errno.h>
  23 #include <linux/delay.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/dma-mapping.h>
  26 #include <linux/pm.h>
  27 #include <linux/clk.h>
  28 #include <linux/of.h>
  29 #include <linux/of_address.h>
  30 #include <linux/of_irq.h>
  31 #include <linux/of_net.h>
  32 #include <linux/of_platform.h>
  33 #include <net/arp.h>
  34
  35 #include <linux/mii.h>
  36 #include <linux/ethtool.h>
  37 #include <linux/netdevice.h>
  38 #include <linux/inetdevice.h>
  39 #include <linux/etherdevice.h>
  40 #include <linux/skbuff.h>
  41 #include <linux/in.h>
  42 #include <linux/ip.h>
  43 #include <linux/ipv6.h>
  44 #include <linux/phy.h>
  45 #include <linux/platform_data/bcmgenet.h>
  46
  47 #include <asm/unaligned.h>
  48
  49 #include "bcmgenet.h"
  50
  51 /* Maximum number of hardware queues, downsized if needed */
  52 #define GENET_MAX_MQ_CNT        4
  53
  54 /* Default highest priority queue for multi queue support */
  55 #define GENET_Q0_PRIORITY       0
  56
  57 #define GENET_Q16_RX_BD_CNT     \
  58         (TOTAL_DESC - priv->hw_params->rx_queues * priv->hw_params->rx_bds_per_q)
  59 #define GENET_Q16_TX_BD_CNT     \
  60         (TOTAL_DESC - priv->hw_params->tx_queues * priv->hw_params->tx_bds_per_q)
  61
  62 #define RX_BUF_LENGTH           2048
  63 #define SKB_ALIGNMENT           32
  64
  65 /* Tx/Rx DMA register offset, skip 256 descriptors */
  66 #define WORDS_PER_BD(p)         (p->hw_params->words_per_bd)
  67 #define DMA_DESC_SIZE           (WORDS_PER_BD(priv) * sizeof(u32))
  68
  69 #define GENET_TDMA_REG_OFF      (priv->hw_params->tdma_offset + \
  70                                 TOTAL_DESC * DMA_DESC_SIZE)
  71
  72 #define GENET_RDMA_REG_OFF      (priv->hw_params->rdma_offset + \
  73                                 TOTAL_DESC * DMA_DESC_SIZE)
  74
  75 static inline void dmadesc_set_length_status(struct bcmgenet_priv *priv,
  76                                              void __iomem *d, u32 value)
  77 {
  78         __raw_writel(value, d + DMA_DESC_LENGTH_STATUS);
  79 }
  80
  81 static inline u32 dmadesc_get_length_status(struct bcmgenet_priv *priv,
  82                                             void __iomem *d)
  83 {
  84         return __raw_readl(d + DMA_DESC_LENGTH_STATUS);
  85 }
  86
  87 static inline void dmadesc_set_addr(struct bcmgenet_priv *priv,
  88                                     void __iomem *d,
  89                                     dma_addr_t addr)
  90 {
  91         __raw_writel(lower_32_bits(addr), d + DMA_DESC_ADDRESS_LO);
  92
  93         /* Register writes to GISB bus can take couple hundred nanoseconds
  94          * and are done for each packet, save these expensive writes unless
  95          * the platform is explicitly configured for 64-bits/LPAE.
  96          */
  97 #ifdef CONFIG_PHYS_ADDR_T_64BIT
  98         if (priv->hw_params->flags & GENET_HAS_40BITS)
  99                 __raw_writel(upper_32_bits(addr), d + DMA_DESC_ADDRESS_HI);
 100 #endif
 101 }
 102
 103 /* Combined address + length/status setter */
 104 static inline void dmadesc_set(struct bcmgenet_priv *priv,
 105                                void __iomem *d, dma_addr_t addr, u32 val)
 106 {
 107         dmadesc_set_addr(priv, d, addr);
 108         dmadesc_set_length_status(priv, d, val);
 109 }
 110
 111 static inline dma_addr_t dmadesc_get_addr(struct bcmgenet_priv *priv,
 112                                           void __iomem *d)
 113 {
 114         dma_addr_t addr;
 115
 116         addr = __raw_readl(d + DMA_DESC_ADDRESS_LO);
 117
 118         /* Register writes to GISB bus can take couple hundred nanoseconds
 119          * and are done for each packet, save these expensive writes unless
 120          * the platform is explicitly configured for 64-bits/LPAE.
 121          */
 122 #ifdef CONFIG_PHYS_ADDR_T_64BIT
 123         if (priv->hw_params->flags & GENET_HAS_40BITS)
 124                 addr |= (u64)__raw_readl(d + DMA_DESC_ADDRESS_HI) << 32;
 125 #endif
 126         return addr;
 127 }
 128
 129 #define GENET_VER_FMT   "%1d.%1d EPHY: 0x%04x"
 130
 131 #define GENET_MSG_DEFAULT       (NETIF_MSG_DRV | NETIF_MSG_PROBE | \
 132                                 NETIF_MSG_LINK)
 133
 134 static inline u32 bcmgenet_rbuf_ctrl_get(struct bcmgenet_priv *priv)
 135 {
 136         if (GENET_IS_V1(priv))
 137                 return bcmgenet_rbuf_readl(priv, RBUF_FLUSH_CTRL_V1);
 138         else
 139                 return bcmgenet_sys_readl(priv, SYS_RBUF_FLUSH_CTRL);
 140 }
 141
 142 static inline void bcmgenet_rbuf_ctrl_set(struct bcmgenet_priv *priv, u32 val)
 143 {
 144         if (GENET_IS_V1(priv))
 145                 bcmgenet_rbuf_writel(priv, val, RBUF_FLUSH_CTRL_V1);
 146         else
 147                 bcmgenet_sys_writel(priv, val, SYS_RBUF_FLUSH_CTRL);
 148 }
 149
 150 /* These macros are defined to deal with register map change
 151  * between GENET1.1 and GENET2. Only those currently being used
 152  * by driver are defined.
 153  */
 154 static inline u32 bcmgenet_tbuf_ctrl_get(struct bcmgenet_priv *priv)
 155 {
 156         if (GENET_IS_V1(priv))
 157                 return bcmgenet_rbuf_readl(priv, TBUF_CTRL_V1);
 158         else
 159                 return __raw_readl(priv->base +
 160                                 priv->hw_params->tbuf_offset + TBUF_CTRL);
 161 }
 162
 163 static inline void bcmgenet_tbuf_ctrl_set(struct bcmgenet_priv *priv, u32 val)
 164 {
 165         if (GENET_IS_V1(priv))
 166                 bcmgenet_rbuf_writel(priv, val, TBUF_CTRL_V1);
 167         else
 168                 __raw_writel(val, priv->base +
 169                                 priv->hw_params->tbuf_offset + TBUF_CTRL);
 170 }
 171
 172 static inline u32 bcmgenet_bp_mc_get(struct bcmgenet_priv *priv)
 173 {
 174         if (GENET_IS_V1(priv))
 175                 return bcmgenet_rbuf_readl(priv, TBUF_BP_MC_V1);
 176         else
 177                 return __raw_readl(priv->base +
 178                                 priv->hw_params->tbuf_offset + TBUF_BP_MC);
 179 }
 180
 181 static inline void bcmgenet_bp_mc_set(struct bcmgenet_priv *priv, u32 val)
 182 {
 183         if (GENET_IS_V1(priv))
 184                 bcmgenet_rbuf_writel(priv, val, TBUF_BP_MC_V1);
 185         else
 186                 __raw_writel(val, priv->base +
 187                                 priv->hw_params->tbuf_offset + TBUF_BP_MC);
 188 }
 189
 190 /* RX/TX DMA register accessors */
 191 enum dma_reg {
 192         DMA_RING_CFG = 0,
 193         DMA_CTRL,
 194         DMA_STATUS,
 195         DMA_SCB_BURST_SIZE,
 196         DMA_ARB_CTRL,
 197         DMA_PRIORITY_0,
 198         DMA_PRIORITY_1,
 199         DMA_PRIORITY_2,
 200         DMA_INDEX2RING_0,
 201         DMA_INDEX2RING_1,
 202         DMA_INDEX2RING_2,
 203         DMA_INDEX2RING_3,
 204         DMA_INDEX2RING_4,
 205         DMA_INDEX2RING_5,
 206         DMA_INDEX2RING_6,
 207         DMA_INDEX2RING_7,
 208         DMA_RING0_TIMEOUT,
 209         DMA_RING1_TIMEOUT,
 210         DMA_RING2_TIMEOUT,
 211         DMA_RING3_TIMEOUT,
 212         DMA_RING4_TIMEOUT,
 213         DMA_RING5_TIMEOUT,
 214         DMA_RING6_TIMEOUT,
 215         DMA_RING7_TIMEOUT,
 216         DMA_RING8_TIMEOUT,
 217         DMA_RING9_TIMEOUT,
 218         DMA_RING10_TIMEOUT,
 219         DMA_RING11_TIMEOUT,
 220         DMA_RING12_TIMEOUT,
 221         DMA_RING13_TIMEOUT,
 222         DMA_RING14_TIMEOUT,
 223         DMA_RING15_TIMEOUT,
 224         DMA_RING16_TIMEOUT,
 225 };
 226
 227 static const u8 bcmgenet_dma_regs_v3plus[] = {
 228         [DMA_RING_CFG]          = 0x00,
 229         [DMA_CTRL]              = 0x04,
 230         [DMA_STATUS]            = 0x08,
 231         [DMA_SCB_BURST_SIZE]    = 0x0C,
 232         [DMA_ARB_CTRL]          = 0x2C,
 233         [DMA_PRIORITY_0]        = 0x30,
 234         [DMA_PRIORITY_1]        = 0x34,
 235         [DMA_PRIORITY_2]        = 0x38,
 236         [DMA_RING0_TIMEOUT]     = 0x2C,
 237         [DMA_RING1_TIMEOUT]     = 0x30,
 238         [DMA_RING2_TIMEOUT]     = 0x34,
 239         [DMA_RING3_TIMEOUT]     = 0x38,
 240         [DMA_RING4_TIMEOUT]     = 0x3c,
 241         [DMA_RING5_TIMEOUT]     = 0x40,
 242         [DMA_RING6_TIMEOUT]     = 0x44,
 243         [DMA_RING7_TIMEOUT]     = 0x48,
 244         [DMA_RING8_TIMEOUT]     = 0x4c,
 245         [DMA_RING9_TIMEOUT]     = 0x50,
 246         [DMA_RING10_TIMEOUT]    = 0x54,
 247         [DMA_RING11_TIMEOUT]    = 0x58,
 248         [DMA_RING12_TIMEOUT]    = 0x5c,
 249         [DMA_RING13_TIMEOUT]    = 0x60,
 250         [DMA_RING14_TIMEOUT]    = 0x64,
 251         [DMA_RING15_TIMEOUT]    = 0x68,
 252         [DMA_RING16_TIMEOUT]    = 0x6C,
 253         [DMA_INDEX2RING_0]      = 0x70,
 254         [DMA_INDEX2RING_1]      = 0x74,
 255         [DMA_INDEX2RING_2]      = 0x78,
 256         [DMA_INDEX2RING_3]      = 0x7C,
 257         [DMA_INDEX2RING_4]      = 0x80,
 258         [DMA_INDEX2RING_5]      = 0x84,
 259         [DMA_INDEX2RING_6]      = 0x88,
 260         [DMA_INDEX2RING_7]      = 0x8C,
 261 };
 262
 263 static const u8 bcmgenet_dma_regs_v2[] = {
 264         [DMA_RING_CFG]          = 0x00,
 265         [DMA_CTRL]              = 0x04,
 266         [DMA_STATUS]            = 0x08,
 267         [DMA_SCB_BURST_SIZE]    = 0x0C,
 268         [DMA_ARB_CTRL]          = 0x30,
 269         [DMA_PRIORITY_0]        = 0x34,
 270         [DMA_PRIORITY_1]        = 0x38,
 271         [DMA_PRIORITY_2]        = 0x3C,
 272         [DMA_RING0_TIMEOUT]     = 0x2C,
 273         [DMA_RING1_TIMEOUT]     = 0x30,
 274         [DMA_RING2_TIMEOUT]     = 0x34,
 275         [DMA_RING3_TIMEOUT]     = 0x38,
 276         [DMA_RING4_TIMEOUT]     = 0x3c,
 277         [DMA_RING5_TIMEOUT]     = 0x40,
 278         [DMA_RING6_TIMEOUT]     = 0x44,
 279         [DMA_RING7_TIMEOUT]     = 0x48,
 280         [DMA_RING8_TIMEOUT]     = 0x4c,
 281         [DMA_RING9_TIMEOUT]     = 0x50,
 282         [DMA_RING10_TIMEOUT]    = 0x54,
 283         [DMA_RING11_TIMEOUT]    = 0x58,
 284         [DMA_RING12_TIMEOUT]    = 0x5c,
 285         [DMA_RING13_TIMEOUT]    = 0x60,
 286         [DMA_RING14_TIMEOUT]    = 0x64,
 287         [DMA_RING15_TIMEOUT]    = 0x68,
 288         [DMA_RING16_TIMEOUT]    = 0x6C,
 289 };
 290
 291 static const u8 bcmgenet_dma_regs_v1[] = {
 292         [DMA_CTRL]              = 0x00,
 293         [DMA_STATUS]            = 0x04,
 294         [DMA_SCB_BURST_SIZE]    = 0x0C,
 295         [DMA_ARB_CTRL]          = 0x30,
 296         [DMA_PRIORITY_0]        = 0x34,
 297         [DMA_PRIORITY_1]        = 0x38,
 298         [DMA_PRIORITY_2]        = 0x3C,
 299         [DMA_RING0_TIMEOUT]     = 0x2C,
 300         [DMA_RING1_TIMEOUT]     = 0x30,
 301         [DMA_RING2_TIMEOUT]     = 0x34,
 302         [DMA_RING3_TIMEOUT]     = 0x38,
 303         [DMA_RING4_TIMEOUT]     = 0x3c,
 304         [DMA_RING5_TIMEOUT]     = 0x40,
 305         [DMA_RING6_TIMEOUT]     = 0x44,
 306         [DMA_RING7_TIMEOUT]     = 0x48,
 307         [DMA_RING8_TIMEOUT]     = 0x4c,
 308         [DMA_RING9_TIMEOUT]     = 0x50,
 309         [DMA_RING10_TIMEOUT]    = 0x54,
 310         [DMA_RING11_TIMEOUT]    = 0x58,
 311         [DMA_RING12_TIMEOUT]    = 0x5c,
 312         [DMA_RING13_TIMEOUT]    = 0x60,
 313         [DMA_RING14_TIMEOUT]    = 0x64,
 314         [DMA_RING15_TIMEOUT]    = 0x68,
 315         [DMA_RING16_TIMEOUT]    = 0x6C,
 316 };
 317
 318 /* Set at runtime once bcmgenet version is known */
 319 static const u8 *bcmgenet_dma_regs;
 320
 321 static inline struct bcmgenet_priv *dev_to_priv(struct device *dev)
 322 {
 323         return netdev_priv(dev_get_drvdata(dev));
 324 }
 325
 326 static inline u32 bcmgenet_tdma_readl(struct bcmgenet_priv *priv,
 327                                       enum dma_reg r)
 328 {
 329         return __raw_readl(priv->base + GENET_TDMA_REG_OFF +
 330                         DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
 331 }
 332
 333 static inline void bcmgenet_tdma_writel(struct bcmgenet_priv *priv,
 334                                         u32 val, enum dma_reg r)
 335 {
 336         __raw_writel(val, priv->base + GENET_TDMA_REG_OFF +
 337                         DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
 338 }
 339
 340 static inline u32 bcmgenet_rdma_readl(struct bcmgenet_priv *priv,
 341                                       enum dma_reg r)
 342 {
 343         return __raw_readl(priv->base + GENET_RDMA_REG_OFF +
 344                         DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
 345 }
 346
 347 static inline void bcmgenet_rdma_writel(struct bcmgenet_priv *priv,
 348                                         u32 val, enum dma_reg r)
 349 {
 350         __raw_writel(val, priv->base + GENET_RDMA_REG_OFF +
 351                         DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
 352 }
 353
 354 /* RDMA/TDMA ring registers and accessors
 355  * we merge the common fields and just prefix with T/D the registers
 356  * having different meaning depending on the direction
 357  */
 358 enum dma_ring_reg {
 359         TDMA_READ_PTR = 0,
 360         RDMA_WRITE_PTR = TDMA_READ_PTR,
 361         TDMA_READ_PTR_HI,
 362         RDMA_WRITE_PTR_HI = TDMA_READ_PTR_HI,
 363         TDMA_CONS_INDEX,
 364         RDMA_PROD_INDEX = TDMA_CONS_INDEX,
 365         TDMA_PROD_INDEX,
 366         RDMA_CONS_INDEX = TDMA_PROD_INDEX,
 367         DMA_RING_BUF_SIZE,
 368         DMA_START_ADDR,
 369         DMA_START_ADDR_HI,
 370         DMA_END_ADDR,
 371         DMA_END_ADDR_HI,
 372         DMA_MBUF_DONE_THRESH,
 373         TDMA_FLOW_PERIOD,
 374         RDMA_XON_XOFF_THRESH = TDMA_FLOW_PERIOD,
 375         TDMA_WRITE_PTR,
 376         RDMA_READ_PTR = TDMA_WRITE_PTR,
 377         TDMA_WRITE_PTR_HI,
 378         RDMA_READ_PTR_HI = TDMA_WRITE_PTR_HI
 379 };
 380
 381 /* GENET v4 supports 40-bits pointer addressing
 382  * for obvious reasons the LO and HI word parts
 383  * are contiguous, but this offsets the other
 384  * registers.
 385  */
 386 static const u8 genet_dma_ring_regs_v4[] = {
 387         [TDMA_READ_PTR]                 = 0x00,
 388         [TDMA_READ_PTR_HI]              = 0x04,
 389         [TDMA_CONS_INDEX]               = 0x08,
 390         [TDMA_PROD_INDEX]               = 0x0C,
 391         [DMA_RING_BUF_SIZE]             = 0x10,
 392         [DMA_START_ADDR]                = 0x14,
 393         [DMA_START_ADDR_HI]             = 0x18,
 394         [DMA_END_ADDR]                  = 0x1C,
 395         [DMA_END_ADDR_HI]               = 0x20,
 396         [DMA_MBUF_DONE_THRESH]          = 0x24,
 397         [TDMA_FLOW_PERIOD]              = 0x28,
 398         [TDMA_WRITE_PTR]                = 0x2C,
 399         [TDMA_WRITE_PTR_HI]             = 0x30,
 400 };
 401
 402 static const u8 genet_dma_ring_regs_v123[] = {
 403         [TDMA_READ_PTR]                 = 0x00,
 404         [TDMA_CONS_INDEX]               = 0x04,
 405         [TDMA_PROD_INDEX]               = 0x08,
 406         [DMA_RING_BUF_SIZE]             = 0x0C,
 407         [DMA_START_ADDR]                = 0x10,
 408         [DMA_END_ADDR]                  = 0x14,
 409         [DMA_MBUF_DONE_THRESH]          = 0x18,
 410         [TDMA_FLOW_PERIOD]              = 0x1C,
 411         [TDMA_WRITE_PTR]                = 0x20,
 412 };
 413
 414 /* Set at runtime once GENET version is known */
 415 static const u8 *genet_dma_ring_regs;
 416
 417 static inline u32 bcmgenet_tdma_ring_readl(struct bcmgenet_priv *priv,
 418                                            unsigned int ring,
 419                                            enum dma_ring_reg r)
 420 {
 421         return __raw_readl(priv->base + GENET_TDMA_REG_OFF +
 422                         (DMA_RING_SIZE * ring) +
 423                         genet_dma_ring_regs[r]);
 424 }
 425
 426 static inline void bcmgenet_tdma_ring_writel(struct bcmgenet_priv *priv,
 427                                              unsigned int ring, u32 val,
 428                                              enum dma_ring_reg r)
 429 {
 430         __raw_writel(val, priv->base + GENET_TDMA_REG_OFF +
 431                         (DMA_RING_SIZE * ring) +
 432                         genet_dma_ring_regs[r]);
 433 }
 434
 435 static inline u32 bcmgenet_rdma_ring_readl(struct bcmgenet_priv *priv,
 436                                            unsigned int ring,
 437                                            enum dma_ring_reg r)
 438 {
 439         return __raw_readl(priv->base + GENET_RDMA_REG_OFF +
 440                         (DMA_RING_SIZE * ring) +
 441                         genet_dma_ring_regs[r]);
 442 }
 443
 444 static inline void bcmgenet_rdma_ring_writel(struct bcmgenet_priv *priv,
 445                                              unsigned int ring, u32 val,
 446                                              enum dma_ring_reg r)
 447 {
 448         __raw_writel(val, priv->base + GENET_RDMA_REG_OFF +
 449                         (DMA_RING_SIZE * ring) +
 450                         genet_dma_ring_regs[r]);
 451 }
 452
 453 static int bcmgenet_get_link_ksettings(struct net_device *dev,
 454                                        struct ethtool_link_ksettings *cmd)
 455 {
 456         struct bcmgenet_priv *priv = netdev_priv(dev);
 457
 458         if (!netif_running(dev))
 459                 return -EINVAL;
 460
 461         if (!priv->phydev)
 462                 return -ENODEV;
 463
 464         return phy_ethtool_ksettings_get(priv->phydev, cmd);
 465 }
 466
 467 static int bcmgenet_set_link_ksettings(struct net_device *dev,
 468                                        const struct ethtool_link_ksettings *cmd)
 469 {
 470         struct bcmgenet_priv *priv = netdev_priv(dev);
 471
 472         if (!netif_running(dev))
 473                 return -EINVAL;
 474
 475         if (!priv->phydev)
 476                 return -ENODEV;
 477
 478         return phy_ethtool_ksettings_set(priv->phydev, cmd);
 479 }
 480
 481 static int bcmgenet_set_rx_csum(struct net_device *dev,
 482                                 netdev_features_t wanted)
 483 {
 484         struct bcmgenet_priv *priv = netdev_priv(dev);
 485         u32 rbuf_chk_ctrl;
 486         bool rx_csum_en;
 487
 488         rx_csum_en = !!(wanted & NETIF_F_RXCSUM);
 489
 490         rbuf_chk_ctrl = bcmgenet_rbuf_readl(priv, RBUF_CHK_CTRL);
 491
 492         /* enable rx checksumming */
 493         if (rx_csum_en)
 494                 rbuf_chk_ctrl |= RBUF_RXCHK_EN;
 495         else
 496                 rbuf_chk_ctrl &= ~RBUF_RXCHK_EN;
 497         priv->desc_rxchk_en = rx_csum_en;
 498
 499         /* If UniMAC forwards CRC, we need to skip over it to get
 500          * a valid CHK bit to be set in the per-packet status word
 501         */
 502         if (rx_csum_en && priv->crc_fwd_en)
 503                 rbuf_chk_ctrl |= RBUF_SKIP_FCS;
 504         else
 505                 rbuf_chk_ctrl &= ~RBUF_SKIP_FCS;
 506
 507         bcmgenet_rbuf_writel(priv, rbuf_chk_ctrl, RBUF_CHK_CTRL);
 508
 509         return 0;
 510 }
 511
 512 static int bcmgenet_set_tx_csum(struct net_device *dev,
 513                                 netdev_features_t wanted)
 514 {
 515         struct bcmgenet_priv *priv = netdev_priv(dev);
 516         bool desc_64b_en;
 517         u32 tbuf_ctrl, rbuf_ctrl;
 518
 519         tbuf_ctrl = bcmgenet_tbuf_ctrl_get(priv);
 520         rbuf_ctrl = bcmgenet_rbuf_readl(priv, RBUF_CTRL);
 521
 522         desc_64b_en = !!(wanted & (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM));
 523
 524         /* enable 64 bytes descriptor in both directions (RBUF and TBUF) */
 525         if (desc_64b_en) {
 526                 tbuf_ctrl |= RBUF_64B_EN;
 527                 rbuf_ctrl |= RBUF_64B_EN;
 528         } else {
 529                 tbuf_ctrl &= ~RBUF_64B_EN;
 530                 rbuf_ctrl &= ~RBUF_64B_EN;
 531         }
 532         priv->desc_64b_en = desc_64b_en;
 533
 534         bcmgenet_tbuf_ctrl_set(priv, tbuf_ctrl);
 535         bcmgenet_rbuf_writel(priv, rbuf_ctrl, RBUF_CTRL);
 536
 537         return 0;
 538 }
 539
 540 static int bcmgenet_set_features(struct net_device *dev,
 541                                  netdev_features_t features)
 542 {
 543         netdev_features_t changed = features ^ dev->features;
 544         netdev_features_t wanted = dev->wanted_features;
 545         int ret = 0;
 546
 547         if (changed & (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM))
 548                 ret = bcmgenet_set_tx_csum(dev, wanted);
 549         if (changed & (NETIF_F_RXCSUM))
 550                 ret = bcmgenet_set_rx_csum(dev, wanted);
 551
 552         return ret;
 553 }
 554
 555 static u32 bcmgenet_get_msglevel(struct net_device *dev)
 556 {
 557         struct bcmgenet_priv *priv = netdev_priv(dev);
 558
 559         return priv->msg_enable;
 560 }
 561
 562 static void bcmgenet_set_msglevel(struct net_device *dev, u32 level)
 563 {
 564         struct bcmgenet_priv *priv = netdev_priv(dev);
 565
 566         priv->msg_enable = level;
 567 }
 568
 569 static int bcmgenet_get_coalesce(struct net_device *dev,
 570                                  struct ethtool_coalesce *ec)
 571 {
 572         struct bcmgenet_priv *priv = netdev_priv(dev);
 573
 574         ec->tx_max_coalesced_frames =
 575                 bcmgenet_tdma_ring_readl(priv, DESC_INDEX,
 576                                          DMA_MBUF_DONE_THRESH);
 577         ec->rx_max_coalesced_frames =
 578                 bcmgenet_rdma_ring_readl(priv, DESC_INDEX,
 579                                          DMA_MBUF_DONE_THRESH);
 580         ec->rx_coalesce_usecs =
 581                 bcmgenet_rdma_readl(priv, DMA_RING16_TIMEOUT) * 8192 / 1000;
 582
 583         return 0;
 584 }
 585
 586 static int bcmgenet_set_coalesce(struct net_device *dev,
 587                                  struct ethtool_coalesce *ec)
 588 {
 589         struct bcmgenet_priv *priv = netdev_priv(dev);
 590         unsigned int i;
 591         u32 reg;
 592
 593         /* Base system clock is 125Mhz, DMA timeout is this reference clock
 594          * divided by 1024, which yields roughly 8.192us, our maximum value
 595          * has to fit in the DMA_TIMEOUT_MASK (16 bits)
 596          */
 597         if (ec->tx_max_coalesced_frames > DMA_INTR_THRESHOLD_MASK ||
 598             ec->tx_max_coalesced_frames == 0 ||
 599             ec->rx_max_coalesced_frames > DMA_INTR_THRESHOLD_MASK ||
 600             ec->rx_coalesce_usecs > (DMA_TIMEOUT_MASK * 8) + 1)
 601                 return -EINVAL;
 602
 603         if (ec->rx_coalesce_usecs == 0 && ec->rx_max_coalesced_frames == 0)
 604                 return -EINVAL;
 605
 606         /* GENET TDMA hardware does not support a configurable timeout, but will
 607          * always generate an interrupt either after MBDONE packets have been
 608          * transmitted, or when the ring is empty.
 609          */
 610         if (ec->tx_coalesce_usecs || ec->tx_coalesce_usecs_high ||
 611             ec->tx_coalesce_usecs_irq || ec->tx_coalesce_usecs_low)
 612                 return -EOPNOTSUPP;
 613
 614         /* Program all TX queues with the same values, as there is no
 615          * ethtool knob to do coalescing on a per-queue basis
 616          */
 617         for (i = 0; i < priv->hw_params->tx_queues; i++)
 618                 bcmgenet_tdma_ring_writel(priv, i,
 619                                           ec->tx_max_coalesced_frames,
 620                                           DMA_MBUF_DONE_THRESH);
 621         bcmgenet_tdma_ring_writel(priv, DESC_INDEX,
 622                                   ec->tx_max_coalesced_frames,
 623                                   DMA_MBUF_DONE_THRESH);
 624
 625         for (i = 0; i < priv->hw_params->rx_queues; i++) {
 626                 bcmgenet_rdma_ring_writel(priv, i,
 627                                           ec->rx_max_coalesced_frames,
 628                                           DMA_MBUF_DONE_THRESH);
 629
 630                 reg = bcmgenet_rdma_readl(priv, DMA_RING0_TIMEOUT + i);
 631                 reg &= ~DMA_TIMEOUT_MASK;
 632                 reg |= DIV_ROUND_UP(ec->rx_coalesce_usecs * 1000, 8192);
 633                 bcmgenet_rdma_writel(priv, reg, DMA_RING0_TIMEOUT + i);
 634         }
 635
 636         bcmgenet_rdma_ring_writel(priv, DESC_INDEX,
 637                                   ec->rx_max_coalesced_frames,
 638                                   DMA_MBUF_DONE_THRESH);
 639
 640         reg = bcmgenet_rdma_readl(priv, DMA_RING16_TIMEOUT);
 641         reg &= ~DMA_TIMEOUT_MASK;
 642         reg |= DIV_ROUND_UP(ec->rx_coalesce_usecs * 1000, 8192);
 643         bcmgenet_rdma_writel(priv, reg, DMA_RING16_TIMEOUT);
 644
 645         return 0;
 646 }
 647
 648 /* standard ethtool support functions. */
 649 enum bcmgenet_stat_type {
 650         BCMGENET_STAT_NETDEV = -1,
 651         BCMGENET_STAT_MIB_RX,
 652         BCMGENET_STAT_MIB_TX,
 653         BCMGENET_STAT_RUNT,
 654         BCMGENET_STAT_MISC,
 655         BCMGENET_STAT_SOFT,
 656 };
 657
 658 struct bcmgenet_stats {
 659         char stat_string[ETH_GSTRING_LEN];
 660         int stat_sizeof;
 661         int stat_offset;
 662         enum bcmgenet_stat_type type;
 663         /* reg offset from UMAC base for misc counters */
 664         u16 reg_offset;
 665 };
 666
 667 #define STAT_NETDEV(m) { \
 668         .stat_string = __stringify(m), \
 669         .stat_sizeof = sizeof(((struct net_device_stats *)0)->m), \
 670         .stat_offset = offsetof(struct net_device_stats, m), \
 671         .type = BCMGENET_STAT_NETDEV, \
 672 }
 673
 674 #define STAT_GENET_MIB(str, m, _type) { \
 675         .stat_string = str, \
 676         .stat_sizeof = sizeof(((struct bcmgenet_priv *)0)->m), \
 677         .stat_offset = offsetof(struct bcmgenet_priv, m), \
 678         .type = _type, \
 679 }
 680
 681 #define STAT_GENET_MIB_RX(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_MIB_RX)
 682 #define STAT_GENET_MIB_TX(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_MIB_TX)
 683 #define STAT_GENET_RUNT(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_RUNT)
 684 #define STAT_GENET_SOFT_MIB(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_SOFT)
 685
 686 #define STAT_GENET_MISC(str, m, offset) { \
 687         .stat_string = str, \
 688         .stat_sizeof = sizeof(((struct bcmgenet_priv *)0)->m), \
 689         .stat_offset = offsetof(struct bcmgenet_priv, m), \
 690         .type = BCMGENET_STAT_MISC, \
 691         .reg_offset = offset, \
 692 }
 693
 694
 695 /* There is a 0xC gap between the end of RX and beginning of TX stats and then
 696  * between the end of TX stats and the beginning of the RX RUNT
 697  */
 698 #define BCMGENET_STAT_OFFSET    0xc
 699
 700 /* Hardware counters must be kept in sync because the order/offset
 701  * is important here (order in structure declaration = order in hardware)
 702  */
 703 static const struct bcmgenet_stats bcmgenet_gstrings_stats[] = {
 704         /* general stats */
 705         STAT_NETDEV(rx_packets),
 706         STAT_NETDEV(tx_packets),
 707         STAT_NETDEV(rx_bytes),
 708         STAT_NETDEV(tx_bytes),
 709         STAT_NETDEV(rx_errors),
 710         STAT_NETDEV(tx_errors),
 711         STAT_NETDEV(rx_dropped),
 712         STAT_NETDEV(tx_dropped),
 713         STAT_NETDEV(multicast),
 714         /* UniMAC RSV counters */
 715         STAT_GENET_MIB_RX("rx_64_octets", mib.rx.pkt_cnt.cnt_64),
 716         STAT_GENET_MIB_RX("rx_65_127_oct", mib.rx.pkt_cnt.cnt_127),
 717         STAT_GENET_MIB_RX("rx_128_255_oct", mib.rx.pkt_cnt.cnt_255),
 718         STAT_GENET_MIB_RX("rx_256_511_oct", mib.rx.pkt_cnt.cnt_511),
 719         STAT_GENET_MIB_RX("rx_512_1023_oct", mib.rx.pkt_cnt.cnt_1023),
 720         STAT_GENET_MIB_RX("rx_1024_1518_oct", mib.rx.pkt_cnt.cnt_1518),
 721         STAT_GENET_MIB_RX("rx_vlan_1519_1522_oct", mib.rx.pkt_cnt.cnt_mgv),
 722         STAT_GENET_MIB_RX("rx_1522_2047_oct", mib.rx.pkt_cnt.cnt_2047),
 723         STAT_GENET_MIB_RX("rx_2048_4095_oct", mib.rx.pkt_cnt.cnt_4095),
 724         STAT_GENET_MIB_RX("rx_4096_9216_oct", mib.rx.pkt_cnt.cnt_9216),
 725         STAT_GENET_MIB_RX("rx_pkts", mib.rx.pkt),
 726         STAT_GENET_MIB_RX("rx_bytes", mib.rx.bytes),
 727         STAT_GENET_MIB_RX("rx_multicast", mib.rx.mca),
 728         STAT_GENET_MIB_RX("rx_broadcast", mib.rx.bca),
 729         STAT_GENET_MIB_RX("rx_fcs", mib.rx.fcs),
 730         STAT_GENET_MIB_RX("rx_control", mib.rx.cf),
 731         STAT_GENET_MIB_RX("rx_pause", mib.rx.pf),
 732         STAT_GENET_MIB_RX("rx_unknown", mib.rx.uo),
 733         STAT_GENET_MIB_RX("rx_align", mib.rx.aln),
 734         STAT_GENET_MIB_RX("rx_outrange", mib.rx.flr),
 735         STAT_GENET_MIB_RX("rx_code", mib.rx.cde),
 736         STAT_GENET_MIB_RX("rx_carrier", mib.rx.fcr),
 737         STAT_GENET_MIB_RX("rx_oversize", mib.rx.ovr),
 738         STAT_GENET_MIB_RX("rx_jabber", mib.rx.jbr),
 739         STAT_GENET_MIB_RX("rx_mtu_err", mib.rx.mtue),
 740         STAT_GENET_MIB_RX("rx_good_pkts", mib.rx.pok),
 741         STAT_GENET_MIB_RX("rx_unicast", mib.rx.uc),
 742         STAT_GENET_MIB_RX("rx_ppp", mib.rx.ppp),
 743         STAT_GENET_MIB_RX("rx_crc", mib.rx.rcrc),
 744         /* UniMAC TSV counters */
 745         STAT_GENET_MIB_TX("tx_64_octets", mib.tx.pkt_cnt.cnt_64),
 746         STAT_GENET_MIB_TX("tx_65_127_oct", mib.tx.pkt_cnt.cnt_127),
 747         STAT_GENET_MIB_TX("tx_128_255_oct", mib.tx.pkt_cnt.cnt_255),
 748         STAT_GENET_MIB_TX("tx_256_511_oct", mib.tx.pkt_cnt.cnt_511),
 749         STAT_GENET_MIB_TX("tx_512_1023_oct", mib.tx.pkt_cnt.cnt_1023),
 750         STAT_GENET_MIB_TX("tx_1024_1518_oct", mib.tx.pkt_cnt.cnt_1518),
 751         STAT_GENET_MIB_TX("tx_vlan_1519_1522_oct", mib.tx.pkt_cnt.cnt_mgv),
 752         STAT_GENET_MIB_TX("tx_1522_2047_oct", mib.tx.pkt_cnt.cnt_2047),
 753         STAT_GENET_MIB_TX("tx_2048_4095_oct", mib.tx.pkt_cnt.cnt_4095),
 754         STAT_GENET_MIB_TX("tx_4096_9216_oct", mib.tx.pkt_cnt.cnt_9216),
 755         STAT_GENET_MIB_TX("tx_pkts", mib.tx.pkts),
 756         STAT_GENET_MIB_TX("tx_multicast", mib.tx.mca),
 757         STAT_GENET_MIB_TX("tx_broadcast", mib.tx.bca),
 758         STAT_GENET_MIB_TX("tx_pause", mib.tx.pf),
 759         STAT_GENET_MIB_TX("tx_control", mib.tx.cf),
 760         STAT_GENET_MIB_TX("tx_fcs_err", mib.tx.fcs),
 761         STAT_GENET_MIB_TX("tx_oversize", mib.tx.ovr),
 762         STAT_GENET_MIB_TX("tx_defer", mib.tx.drf),
 763         STAT_GENET_MIB_TX("tx_excess_defer", mib.tx.edf),
 764         STAT_GENET_MIB_TX("tx_single_col", mib.tx.scl),
 765         STAT_GENET_MIB_TX("tx_multi_col", mib.tx.mcl),
 766         STAT_GENET_MIB_TX("tx_late_col", mib.tx.lcl),
 767         STAT_GENET_MIB_TX("tx_excess_col", mib.tx.ecl),
 768         STAT_GENET_MIB_TX("tx_frags", mib.tx.frg),
 769         STAT_GENET_MIB_TX("tx_total_col", mib.tx.ncl),
 770         STAT_GENET_MIB_TX("tx_jabber", mib.tx.jbr),
 771         STAT_GENET_MIB_TX("tx_bytes", mib.tx.bytes),
 772         STAT_GENET_MIB_TX("tx_good_pkts", mib.tx.pok),
 773         STAT_GENET_MIB_TX("tx_unicast", mib.tx.uc),
 774         /* UniMAC RUNT counters */
 775         STAT_GENET_RUNT("rx_runt_pkts", mib.rx_runt_cnt),
 776         STAT_GENET_RUNT("rx_runt_valid_fcs", mib.rx_runt_fcs),
 777         STAT_GENET_RUNT("rx_runt_inval_fcs_align", mib.rx_runt_fcs_align),
 778         STAT_GENET_RUNT("rx_runt_bytes", mib.rx_runt_bytes),
 779         /* Misc UniMAC counters */
 780         STAT_GENET_MISC("rbuf_ovflow_cnt", mib.rbuf_ovflow_cnt,
 781                         UMAC_RBUF_OVFL_CNT),
 782         STAT_GENET_MISC("rbuf_err_cnt", mib.rbuf_err_cnt, UMAC_RBUF_ERR_CNT),
 783         STAT_GENET_MISC("mdf_err_cnt", mib.mdf_err_cnt, UMAC_MDF_ERR_CNT),
 784         STAT_GENET_SOFT_MIB("alloc_rx_buff_failed", mib.alloc_rx_buff_failed),
 785         STAT_GENET_SOFT_MIB("rx_dma_failed", mib.rx_dma_failed),
 786         STAT_GENET_SOFT_MIB("tx_dma_failed", mib.tx_dma_failed),
 787 };
 788
 789 #define BCMGENET_STATS_LEN      ARRAY_SIZE(bcmgenet_gstrings_stats)
 790
 791 static void bcmgenet_get_drvinfo(struct net_device *dev,
 792                                  struct ethtool_drvinfo *info)
 793 {
 794         strlcpy(info->driver, "bcmgenet", sizeof(info->driver));
 795         strlcpy(info->version, "v2.0", sizeof(info->version));
 796 }
 797
 798 static int bcmgenet_get_sset_count(struct net_device *dev, int string_set)
 799 {
 800         switch (string_set) {
 801         case ETH_SS_STATS:
 802                 return BCMGENET_STATS_LEN;
 803         default:
 804                 return -EOPNOTSUPP;
 805         }
 806 }
 807
 808 static void bcmgenet_get_strings(struct net_device *dev, u32 stringset,
 809                                  u8 *data)
 810 {
 811         int i;
 812
 813         switch (stringset) {
 814         case ETH_SS_STATS:
 815                 for (i = 0; i < BCMGENET_STATS_LEN; i++) {
 816                         memcpy(data + i * ETH_GSTRING_LEN,
 817                                bcmgenet_gstrings_stats[i].stat_string,
 818                                ETH_GSTRING_LEN);
 819                 }
 820                 break;
 821         }
 822 }
 823
 824 static void bcmgenet_update_mib_counters(struct bcmgenet_priv *priv)
 825 {
 826         int i, j = 0;
 827
 828         for (i = 0; i < BCMGENET_STATS_LEN; i++) {
 829                 const struct bcmgenet_stats *s;
 830                 u8 offset = 0;
 831                 u32 val = 0;
 832                 char *p;
 833
 834                 s = &bcmgenet_gstrings_stats[i];
 835                 switch (s->type) {
 836                 case BCMGENET_STAT_NETDEV:
 837                 case BCMGENET_STAT_SOFT:
 838                         continue;
 839                 case BCMGENET_STAT_MIB_RX:
 840                 case BCMGENET_STAT_MIB_TX:
 841                 case BCMGENET_STAT_RUNT:
 842                         if (s->type != BCMGENET_STAT_MIB_RX)
 843                                 offset = BCMGENET_STAT_OFFSET;
 844                         val = bcmgenet_umac_readl(priv,
 845                                                   UMAC_MIB_START + j + offset);
 846                         break;
 847                 case BCMGENET_STAT_MISC:
 848                         val = bcmgenet_umac_readl(priv, s->reg_offset);
 849                         /* clear if overflowed */
 850                         if (val == ~0)
 851                                 bcmgenet_umac_writel(priv, 0, s->reg_offset);
 852                         break;
 853                 }
 854
 855                 j += s->stat_sizeof;
 856                 p = (char *)priv + s->stat_offset;
 857                 *(u32 *)p = val;
 858         }
 859 }
 860
 861 static void bcmgenet_get_ethtool_stats(struct net_device *dev,
 862                                        struct ethtool_stats *stats,
 863                                        u64 *data)
 864 {
 865         struct bcmgenet_priv *priv = netdev_priv(dev);
 866         int i;
 867
 868         if (netif_running(dev))
 869                 bcmgenet_update_mib_counters(priv);
 870
 871         for (i = 0; i < BCMGENET_STATS_LEN; i++) {
 872                 const struct bcmgenet_stats *s;
 873                 char *p;
 874
 875                 s = &bcmgenet_gstrings_stats[i];
 876                 if (s->type == BCMGENET_STAT_NETDEV)
 877                         p = (char *)&dev->stats;
 878                 else
 879                         p = (char *)priv;
 880                 p += s->stat_offset;
 881                 if (sizeof(unsigned long) != sizeof(u32) &&
 882                     s->stat_sizeof == sizeof(unsigned long))
 883                         data[i] = *(unsigned long *)p;
 884                 else
 885                         data[i] = *(u32 *)p;
 886         }
 887 }
 888
 889 static void bcmgenet_eee_enable_set(struct net_device *dev, bool enable)
 890 {
 891         struct bcmgenet_priv *priv = netdev_priv(dev);
 892         u32 off = priv->hw_params->tbuf_offset + TBUF_ENERGY_CTRL;
 893         u32 reg;
 894
 895         if (enable && !priv->clk_eee_enabled) {
 896                 clk_prepare_enable(priv->clk_eee);
 897                 priv->clk_eee_enabled = true;
 898         }
 899
 900         reg = bcmgenet_umac_readl(priv, UMAC_EEE_CTRL);
 901         if (enable)
 902                 reg |= EEE_EN;
 903         else
 904                 reg &= ~EEE_EN;
 905         bcmgenet_umac_writel(priv, reg, UMAC_EEE_CTRL);
 906
 907         /* Enable EEE and switch to a 27Mhz clock automatically */
 908         reg = __raw_readl(priv->base + off);
 909         if (enable)
 910                 reg |= TBUF_EEE_EN | TBUF_PM_EN;
 911         else
 912                 reg &= ~(TBUF_EEE_EN | TBUF_PM_EN);
 913         __raw_writel(reg, priv->base + off);
 914
 915         /* Do the same for thing for RBUF */
 916         reg = bcmgenet_rbuf_readl(priv, RBUF_ENERGY_CTRL);
 917         if (enable)
 918                 reg |= RBUF_EEE_EN | RBUF_PM_EN;
 919         else
 920                 reg &= ~(RBUF_EEE_EN | RBUF_PM_EN);
 921         bcmgenet_rbuf_writel(priv, reg, RBUF_ENERGY_CTRL);
 922
 923         if (!enable && priv->clk_eee_enabled) {
 924                 clk_disable_unprepare(priv->clk_eee);
 925                 priv->clk_eee_enabled = false;
 926         }
 927
 928         priv->eee.eee_enabled = enable;
 929         priv->eee.eee_active = enable;
 930 }
 931
 932 static int bcmgenet_get_eee(struct net_device *dev, struct ethtool_eee *e)
 933 {
 934         struct bcmgenet_priv *priv = netdev_priv(dev);
 935         struct ethtool_eee *p = &priv->eee;
 936
 937         if (GENET_IS_V1(priv))
 938                 return -EOPNOTSUPP;
 939
 940         e->eee_enabled = p->eee_enabled;
 941         e->eee_active = p->eee_active;
 942         e->tx_lpi_timer = bcmgenet_umac_readl(priv, UMAC_EEE_LPI_TIMER);
 943
 944         return phy_ethtool_get_eee(priv->phydev, e);
 945 }
 946
 947 static int bcmgenet_set_eee(struct net_device *dev, struct ethtool_eee *e)
 948 {
 949         struct bcmgenet_priv *priv = netdev_priv(dev);
 950         struct ethtool_eee *p = &priv->eee;
 951         int ret = 0;
 952
 953         if (GENET_IS_V1(priv))
 954                 return -EOPNOTSUPP;
 955
 956         p->eee_enabled = e->eee_enabled;
 957
 958         if (!p->eee_enabled) {
 959                 bcmgenet_eee_enable_set(dev, false);
 960         } else {
 961                 ret = phy_init_eee(priv->phydev, 0);
 962                 if (ret) {
 963                         netif_err(priv, hw, dev, "EEE initialization failed\n");
 964                         return ret;
 965                 }
 966
 967                 bcmgenet_umac_writel(priv, e->tx_lpi_timer, UMAC_EEE_LPI_TIMER);
 968                 bcmgenet_eee_enable_set(dev, true);
 969         }
 970
 971         return phy_ethtool_set_eee(priv->phydev, e);
 972 }
 973
 974 /* standard ethtool support functions. */
 975 static const struct ethtool_ops bcmgenet_ethtool_ops = {
 976         .get_strings            = bcmgenet_get_strings,
 977         .get_sset_count         = bcmgenet_get_sset_count,
 978         .get_ethtool_stats      = bcmgenet_get_ethtool_stats,
 979         .get_drvinfo            = bcmgenet_get_drvinfo,
 980         .get_link               = ethtool_op_get_link,
 981         .get_msglevel           = bcmgenet_get_msglevel,
 982         .set_msglevel           = bcmgenet_set_msglevel,
 983         .get_wol                = bcmgenet_get_wol,
 984         .set_wol                = bcmgenet_set_wol,
 985         .get_eee                = bcmgenet_get_eee,
 986         .set_eee                = bcmgenet_set_eee,
 987         .nway_reset             = phy_ethtool_nway_reset,
 988         .get_coalesce           = bcmgenet_get_coalesce,
 989         .set_coalesce           = bcmgenet_set_coalesce,
 990         .get_link_ksettings     = bcmgenet_get_link_ksettings,
 991         .set_link_ksettings     = bcmgenet_set_link_ksettings,
 992 };
 993
 994 /* Power down the unimac, based on mode. */
 995 static int bcmgenet_power_down(struct bcmgenet_priv *priv,
 996                                 enum bcmgenet_power_mode mode)
 997 {
 998         int ret = 0;
 999         u32 reg;
1000
1001         switch (mode) {
1002         case GENET_POWER_CABLE_SENSE:
1003                 phy_detach(priv->phydev);
1004                 break;
1005
1006         case GENET_POWER_WOL_MAGIC:
1007                 ret = bcmgenet_wol_power_down_cfg(priv, mode);
1008                 break;
1009
1010         case GENET_POWER_PASSIVE:
1011                 /* Power down LED */
1012                 if (priv->hw_params->flags & GENET_HAS_EXT) {
1013                         reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
1014                         if (GENET_IS_V5(priv))
1015                                 reg |= EXT_PWR_DOWN_PHY_EN |
1016                                        EXT_PWR_DOWN_PHY_RD |
1017                                        EXT_PWR_DOWN_PHY_SD |
1018                                        EXT_PWR_DOWN_PHY_RX |
1019                                        EXT_PWR_DOWN_PHY_TX |
1020                                        EXT_IDDQ_GLBL_PWR;
1021                         else
1022                                 reg |= EXT_PWR_DOWN_PHY;
1023
1024                         reg |= (EXT_PWR_DOWN_DLL | EXT_PWR_DOWN_BIAS);
1025                         bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
1026
1027                         bcmgenet_phy_power_set(priv->dev, false);
1028                 }
1029                 break;
1030         default:
1031                 break;
1032         }
1033
1034         return 0;
1035 }
1036
1037 static void bcmgenet_power_up(struct bcmgenet_priv *priv,
1038                               enum bcmgenet_power_mode mode)
1039 {
1040         u32 reg;
1041
1042         if (!(priv->hw_params->flags & GENET_HAS_EXT))
1043                 return;
1044
1045         reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
1046
1047         switch (mode) {
1048         case GENET_POWER_PASSIVE:
1049                 reg &= ~(EXT_PWR_DOWN_DLL | EXT_PWR_DOWN_BIAS);
1050                 if (GENET_IS_V5(priv)) {
1051                         reg &= ~(EXT_PWR_DOWN_PHY_EN |
1052                                  EXT_PWR_DOWN_PHY_RD |
1053                                  EXT_PWR_DOWN_PHY_SD |
1054                                  EXT_PWR_DOWN_PHY_RX |
1055                                  EXT_PWR_DOWN_PHY_TX |
1056                                  EXT_IDDQ_GLBL_PWR);
1057                         reg |=   EXT_PHY_RESET;
1058                         bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
1059                         mdelay(1);
1060
1061                         reg &=  ~EXT_PHY_RESET;
1062                 } else {
1063                         reg &= ~EXT_PWR_DOWN_PHY;
1064                         reg |= EXT_PWR_DN_EN_LD;
1065                 }
1066                 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
1067                 bcmgenet_phy_power_set(priv->dev, true);
1068                 bcmgenet_mii_reset(priv->dev);
1069                 break;
1070
1071         case GENET_POWER_CABLE_SENSE:
1072                 /* enable APD */
1073                 if (!GENET_IS_V5(priv)) {
1074                         reg |= EXT_PWR_DN_EN_LD;
1075                         bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
1076                 }
1077                 break;
1078         case GENET_POWER_WOL_MAGIC:
1079                 bcmgenet_wol_power_up_cfg(priv, mode);
1080                 return;
1081         default:
1082                 break;
1083         }
1084 }
1085
1086 /* ioctl handle special commands that are not present in ethtool. */
1087 static int bcmgenet_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1088 {
1089         struct bcmgenet_priv *priv = netdev_priv(dev);
1090
1091         if (!netif_running(dev))
1092                 return -EINVAL;
1093
1094         if (!priv->phydev)
1095                 return -ENODEV;
1096
1097         return phy_mii_ioctl(priv->phydev, rq, cmd);
1098 }
1099
1100 static struct enet_cb *bcmgenet_get_txcb(struct bcmgenet_priv *priv,
1101                                          struct bcmgenet_tx_ring *ring)
1102 {
1103         struct enet_cb *tx_cb_ptr;
1104
1105         tx_cb_ptr = ring->cbs;
1106         tx_cb_ptr += ring->write_ptr - ring->cb_ptr;
1107
1108         /* Advancing local write pointer */
1109         if (ring->write_ptr == ring->end_ptr)
1110                 ring->write_ptr = ring->cb_ptr;
1111         else
1112                 ring->write_ptr++;
1113
1114         return tx_cb_ptr;
1115 }
1116
1117 /* Simple helper to free a control block's resources */
1118 static void bcmgenet_free_cb(struct enet_cb *cb)
1119 {
1120         dev_kfree_skb_any(cb->skb);
1121         cb->skb = NULL;
1122         dma_unmap_addr_set(cb, dma_addr, 0);
1123 }
1124
1125 static inline void bcmgenet_rx_ring16_int_disable(struct bcmgenet_rx_ring *ring)
1126 {
1127         bcmgenet_intrl2_0_writel(ring->priv, UMAC_IRQ_RXDMA_DONE,
1128                                  INTRL2_CPU_MASK_SET);
1129 }
1130
1131 static inline void bcmgenet_rx_ring16_int_enable(struct bcmgenet_rx_ring *ring)
1132 {
1133         bcmgenet_intrl2_0_writel(ring->priv, UMAC_IRQ_RXDMA_DONE,
1134                                  INTRL2_CPU_MASK_CLEAR);
1135 }
1136
1137 static inline void bcmgenet_rx_ring_int_disable(struct bcmgenet_rx_ring *ring)
1138 {
1139         bcmgenet_intrl2_1_writel(ring->priv,
1140                                  1 << (UMAC_IRQ1_RX_INTR_SHIFT + ring->index),
1141                                  INTRL2_CPU_MASK_SET);
1142 }
1143
1144 static inline void bcmgenet_rx_ring_int_enable(struct bcmgenet_rx_ring *ring)
1145 {
1146         bcmgenet_intrl2_1_writel(ring->priv,
1147                                  1 << (UMAC_IRQ1_RX_INTR_SHIFT + ring->index),
1148                                  INTRL2_CPU_MASK_CLEAR);
1149 }
1150
1151 static inline void bcmgenet_tx_ring16_int_disable(struct bcmgenet_tx_ring *ring)
1152 {
1153         bcmgenet_intrl2_0_writel(ring->priv, UMAC_IRQ_TXDMA_DONE,
1154                                  INTRL2_CPU_MASK_SET);
1155 }
1156
1157 static inline void bcmgenet_tx_ring16_int_enable(struct bcmgenet_tx_ring *ring)
1158 {
1159         bcmgenet_intrl2_0_writel(ring->priv, UMAC_IRQ_TXDMA_DONE,
1160                                  INTRL2_CPU_MASK_CLEAR);
1161 }
1162
1163 static inline void bcmgenet_tx_ring_int_enable(struct bcmgenet_tx_ring *ring)
1164 {
1165         bcmgenet_intrl2_1_writel(ring->priv, 1 << ring->index,
1166                                  INTRL2_CPU_MASK_CLEAR);
1167 }
1168
1169 static inline void bcmgenet_tx_ring_int_disable(struct bcmgenet_tx_ring *ring)
1170 {
1171         bcmgenet_intrl2_1_writel(ring->priv, 1 << ring->index,
1172                                  INTRL2_CPU_MASK_SET);
1173 }
1174
1175 /* Unlocked version of the reclaim routine */
1176 static unsigned int __bcmgenet_tx_reclaim(struct net_device *dev,
1177                                           struct bcmgenet_tx_ring *ring)
1178 {
1179         struct bcmgenet_priv *priv = netdev_priv(dev);
1180         struct device *kdev = &priv->pdev->dev;
1181         struct enet_cb *tx_cb_ptr;
1182         struct netdev_queue *txq;
1183         unsigned int pkts_compl = 0;
1184         unsigned int bytes_compl = 0;
1185         unsigned int c_index;
1186         unsigned int txbds_ready;
1187         unsigned int txbds_processed = 0;
1188
1189         /* Clear status before servicing to reduce spurious interrupts */
1190         if (ring->index == DESC_INDEX)
1191                 bcmgenet_intrl2_0_writel(priv, UMAC_IRQ_TXDMA_DONE,
1192                                          INTRL2_CPU_CLEAR);
1193         else
1194                 bcmgenet_intrl2_1_writel(priv, (1 << ring->index),
1195                                          INTRL2_CPU_CLEAR);
1196
1197         /* Compute how many buffers are transmitted since last xmit call */
1198         c_index = bcmgenet_tdma_ring_readl(priv, ring->index, TDMA_CONS_INDEX)
1199                 & DMA_C_INDEX_MASK;
1200         txbds_ready = (c_index - ring->c_index) & DMA_C_INDEX_MASK;
1201
1202         netif_dbg(priv, tx_done, dev,
1203                   "%s ring=%d old_c_index=%u c_index=%u txbds_ready=%u\n",
1204                   __func__, ring->index, ring->c_index, c_index, txbds_ready);
1205
1206         /* Reclaim transmitted buffers */
1207         while (txbds_processed < txbds_ready) {
1208                 tx_cb_ptr = &priv->tx_cbs[ring->clean_ptr];
1209                 if (tx_cb_ptr->skb) {
1210                         pkts_compl++;
1211                         bytes_compl += GENET_CB(tx_cb_ptr->skb)->bytes_sent;
1212                         dma_unmap_single(kdev,
1213                                          dma_unmap_addr(tx_cb_ptr, dma_addr),
1214                                          dma_unmap_len(tx_cb_ptr, dma_len),
1215                                          DMA_TO_DEVICE);
1216                         bcmgenet_free_cb(tx_cb_ptr);
1217                 } else if (dma_unmap_addr(tx_cb_ptr, dma_addr)) {
1218                         dma_unmap_page(kdev,
1219                                        dma_unmap_addr(tx_cb_ptr, dma_addr),
1220                                        dma_unmap_len(tx_cb_ptr, dma_len),
1221                                        DMA_TO_DEVICE);
1222                         dma_unmap_addr_set(tx_cb_ptr, dma_addr, 0);
1223                 }
1224
1225                 txbds_processed++;
1226                 if (likely(ring->clean_ptr < ring->end_ptr))
1227                         ring->clean_ptr++;
1228                 else
1229                         ring->clean_ptr = ring->cb_ptr;
1230         }
1231
1232         ring->free_bds += txbds_processed;
1233         ring->c_index = c_index;
1234
1235         dev->stats.tx_packets += pkts_compl;
1236         dev->stats.tx_bytes += bytes_compl;
1237
1238         txq = netdev_get_tx_queue(dev, ring->queue);
1239         netdev_tx_completed_queue(txq, pkts_compl, bytes_compl);
1240
1241         if (ring->free_bds > (MAX_SKB_FRAGS + 1)) {
1242                 if (netif_tx_queue_stopped(txq))
1243                         netif_tx_wake_queue(txq);
1244         }
1245
1246         return txbds_processed;
1247 }
1248
1249 static unsigned int bcmgenet_tx_reclaim(struct net_device *dev,
1250                                 struct bcmgenet_tx_ring *ring)
1251 {
1252         unsigned int released;
1253         unsigned long flags;
1254
1255         spin_lock_irqsave(&ring->lock, flags);
1256         released = __bcmgenet_tx_reclaim(dev, ring);
1257         spin_unlock_irqrestore(&ring->lock, flags);
1258
1259         return released;
1260 }
1261
1262 static int bcmgenet_tx_poll(struct napi_struct *napi, int budget)
1263 {
1264         struct bcmgenet_tx_ring *ring =
1265                 container_of(napi, struct bcmgenet_tx_ring, napi);
1266         unsigned int work_done = 0;
1267
1268         work_done = bcmgenet_tx_reclaim(ring->priv->dev, ring);
1269
1270         if (work_done == 0) {
1271                 napi_complete(napi);
1272                 ring->int_enable(ring);
1273
1274                 return 0;
1275         }
1276
1277         return budget;
1278 }
1279
1280 static void bcmgenet_tx_reclaim_all(struct net_device *dev)
1281 {
1282         struct bcmgenet_priv *priv = netdev_priv(dev);
1283         int i;
1284
1285         if (netif_is_multiqueue(dev)) {
1286                 for (i = 0; i < priv->hw_params->tx_queues; i++)
1287                         bcmgenet_tx_reclaim(dev, &priv->tx_rings[i]);
1288         }
1289
1290         bcmgenet_tx_reclaim(dev, &priv->tx_rings[DESC_INDEX]);
1291 }
1292
1293 /* Transmits a single SKB (either head of a fragment or a single SKB)
1294  * caller must hold priv->lock
1295  */
1296 static int bcmgenet_xmit_single(struct net_device *dev,
1297                                 struct sk_buff *skb,
1298                                 u16 dma_desc_flags,
1299                                 struct bcmgenet_tx_ring *ring)
1300 {
1301         struct bcmgenet_priv *priv = netdev_priv(dev);
1302         struct device *kdev = &priv->pdev->dev;
1303         struct enet_cb *tx_cb_ptr;
1304         unsigned int skb_len;
1305         dma_addr_t mapping;
1306         u32 length_status;
1307         int ret;
1308
1309         tx_cb_ptr = bcmgenet_get_txcb(priv, ring);
1310
1311         if (unlikely(!tx_cb_ptr))
1312                 BUG();
1313
1314         tx_cb_ptr->skb = skb;
1315
1316         skb_len = skb_headlen(skb);
1317
1318         mapping = dma_map_single(kdev, skb->data, skb_len, DMA_TO_DEVICE);
1319         ret = dma_mapping_error(kdev, mapping);
1320         if (ret) {
1321                 priv->mib.tx_dma_failed++;
1322                 netif_err(priv, tx_err, dev, "Tx DMA map failed\n");
1323                 dev_kfree_skb(skb);
1324                 return ret;
1325         }
1326
1327         dma_unmap_addr_set(tx_cb_ptr, dma_addr, mapping);
1328         dma_unmap_len_set(tx_cb_ptr, dma_len, skb_len);
1329         length_status = (skb_len << DMA_BUFLENGTH_SHIFT) | dma_desc_flags |
1330                         (priv->hw_params->qtag_mask << DMA_TX_QTAG_SHIFT) |
1331                         DMA_TX_APPEND_CRC;
1332
1333         if (skb->ip_summed == CHECKSUM_PARTIAL)
1334                 length_status |= DMA_TX_DO_CSUM;
1335
1336         dmadesc_set(priv, tx_cb_ptr->bd_addr, mapping, length_status);
1337
1338         return 0;
1339 }
1340
1341 /* Transmit a SKB fragment */
1342 static int bcmgenet_xmit_frag(struct net_device *dev,
1343                               skb_frag_t *frag,
1344                               u16 dma_desc_flags,
1345                               struct bcmgenet_tx_ring *ring)
1346 {
1347         struct bcmgenet_priv *priv = netdev_priv(dev);
1348         struct device *kdev = &priv->pdev->dev;
1349         struct enet_cb *tx_cb_ptr;
1350         unsigned int frag_size;
1351         dma_addr_t mapping;
1352         int ret;
1353
1354         tx_cb_ptr = bcmgenet_get_txcb(priv, ring);
1355
1356         if (unlikely(!tx_cb_ptr))
1357                 BUG();
1358
1359         tx_cb_ptr->skb = NULL;
1360
1361         frag_size = skb_frag_size(frag);
1362
1363         mapping = skb_frag_dma_map(kdev, frag, 0, frag_size, DMA_TO_DEVICE);
1364         ret = dma_mapping_error(kdev, mapping);
1365         if (ret) {
1366                 priv->mib.tx_dma_failed++;
1367                 netif_err(priv, tx_err, dev, "%s: Tx DMA map failed\n",
1368                           __func__);
1369                 return ret;
1370         }
1371
1372         dma_unmap_addr_set(tx_cb_ptr, dma_addr, mapping);
1373         dma_unmap_len_set(tx_cb_ptr, dma_len, frag_size);
1374
1375         dmadesc_set(priv, tx_cb_ptr->bd_addr, mapping,
1376                     (frag_size << DMA_BUFLENGTH_SHIFT) | dma_desc_flags |
1377                     (priv->hw_params->qtag_mask << DMA_TX_QTAG_SHIFT));
1378
1379         return 0;
1380 }
1381
1382 /* Reallocate the SKB to put enough headroom in front of it and insert
1383  * the transmit checksum offsets in the descriptors
1384  */
1385 static struct sk_buff *bcmgenet_put_tx_csum(struct net_device *dev,
1386                                             struct sk_buff *skb)
1387 {
1388         struct status_64 *status = NULL;
1389         struct sk_buff *new_skb;
1390         u16 offset;
1391         u8 ip_proto;
1392         u16 ip_ver;
1393         u32 tx_csum_info;
1394
1395         if (unlikely(skb_headroom(skb) < sizeof(*status))) {
1396                 /* If 64 byte status block enabled, must make sure skb has
1397                  * enough headroom for us to insert 64B status block.
1398                  */
1399                 new_skb = skb_realloc_headroom(skb, sizeof(*status));
1400                 dev_kfree_skb(skb);
1401                 if (!new_skb) {
1402                         dev->stats.tx_dropped++;
1403                         return NULL;
1404                 }
1405                 skb = new_skb;
1406         }
1407
1408         skb_push(skb, sizeof(*status));
1409         status = (struct status_64 *)skb->data;
1410
1411         if (skb->ip_summed  == CHECKSUM_PARTIAL) {
1412                 ip_ver = htons(skb->protocol);
1413                 switch (ip_ver) {
1414                 case ETH_P_IP:
1415                         ip_proto = ip_hdr(skb)->protocol;
1416                         break;
1417                 case ETH_P_IPV6:
1418                         ip_proto = ipv6_hdr(skb)->nexthdr;
1419                         break;
1420                 default:
1421                         return skb;
1422                 }
1423
1424                 offset = skb_checksum_start_offset(skb) - sizeof(*status);
1425                 tx_csum_info = (offset << STATUS_TX_CSUM_START_SHIFT) |
1426                                 (offset + skb->csum_offset);
1427
1428                 /* Set the length valid bit for TCP and UDP and just set
1429                  * the special UDP flag for IPv4, else just set to 0.
1430                  */
1431                 if (ip_proto == IPPROTO_TCP || ip_proto == IPPROTO_UDP) {
1432                         tx_csum_info |= STATUS_TX_CSUM_LV;
1433                         if (ip_proto == IPPROTO_UDP && ip_ver == ETH_P_IP)
1434                                 tx_csum_info |= STATUS_TX_CSUM_PROTO_UDP;
1435                 } else {
1436                         tx_csum_info = 0;
1437                 }
1438
1439                 status->tx_csum_info = tx_csum_info;
1440         }
1441
1442         return skb;
1443 }
1444
1445 static netdev_tx_t bcmgenet_xmit(struct sk_buff *skb, struct net_device *dev)
1446 {
1447         struct bcmgenet_priv *priv = netdev_priv(dev);
1448         struct bcmgenet_tx_ring *ring = NULL;
1449         struct netdev_queue *txq;
1450         unsigned long flags = 0;
1451         int nr_frags, index;
1452         u16 dma_desc_flags;
1453         int ret;
1454         int i;
1455
1456         index = skb_get_queue_mapping(skb);
1457         /* Mapping strategy:
1458          * queue_mapping = 0, unclassified, packet xmited through ring16
1459          * queue_mapping = 1, goes to ring 0. (highest priority queue
1460          * queue_mapping = 2, goes to ring 1.
1461          * queue_mapping = 3, goes to ring 2.
1462          * queue_mapping = 4, goes to ring 3.
1463          */
1464         if (index == 0)
1465                 index = DESC_INDEX;
1466         else
1467                 index -= 1;
1468
1469         ring = &priv->tx_rings[index];
1470         txq = netdev_get_tx_queue(dev, ring->queue);
1471
1472         nr_frags = skb_shinfo(skb)->nr_frags;
1473
1474         spin_lock_irqsave(&ring->lock, flags);
1475         if (ring->free_bds <= (nr_frags + 1)) {
1476                 if (!netif_tx_queue_stopped(txq)) {
1477                         netif_tx_stop_queue(txq);
1478                         netdev_err(dev,
1479                                    "%s: tx ring %d full when queue %d awake\n",
1480                                    __func__, index, ring->queue);
1481                 }
1482                 ret = NETDEV_TX_BUSY;
1483                 goto out;
1484         }
1485
1486         if (skb_padto(skb, ETH_ZLEN)) {
1487                 ret = NETDEV_TX_OK;
1488                 goto out;
1489         }
1490
1491         /* Retain how many bytes will be sent on the wire, without TSB inserted
1492          * by transmit checksum offload
1493          */
1494         GENET_CB(skb)->bytes_sent = skb->len;
1495
1496         /* set the SKB transmit checksum */
1497         if (priv->desc_64b_en) {
1498                 skb = bcmgenet_put_tx_csum(dev, skb);
1499                 if (!skb) {
1500                         ret = NETDEV_TX_OK;
1501                         goto out;
1502                 }
1503         }
1504
1505         dma_desc_flags = DMA_SOP;
1506         if (nr_frags == 0)
1507                 dma_desc_flags |= DMA_EOP;
1508
1509         /* Transmit single SKB or head of fragment list */
1510         ret = bcmgenet_xmit_single(dev, skb, dma_desc_flags, ring);
1511         if (ret) {
1512                 ret = NETDEV_TX_OK;
1513                 goto out;
1514         }
1515
1516         /* xmit fragment */
1517         for (i = 0; i < nr_frags; i++) {
1518                 ret = bcmgenet_xmit_frag(dev,
1519                                          &skb_shinfo(skb)->frags[i],
1520                                          (i == nr_frags - 1) ? DMA_EOP : 0,
1521                                          ring);
1522                 if (ret) {
1523                         ret = NETDEV_TX_OK;
1524                         goto out;
1525                 }
1526         }
1527
1528         skb_tx_timestamp(skb);
1529
1530         /* Decrement total BD count and advance our write pointer */
1531         ring->free_bds -= nr_frags + 1;
1532         ring->prod_index += nr_frags + 1;
1533         ring->prod_index &= DMA_P_INDEX_MASK;
1534
1535         netdev_tx_sent_queue(txq, GENET_CB(skb)->bytes_sent);
1536
1537         if (ring->free_bds <= (MAX_SKB_FRAGS + 1))
1538                 netif_tx_stop_queue(txq);
1539
1540         if (!skb->xmit_more || netif_xmit_stopped(txq))
1541                 /* Packets are ready, update producer index */
1542                 bcmgenet_tdma_ring_writel(priv, ring->index,
1543                                           ring->prod_index, TDMA_PROD_INDEX);
1544 out:
1545         spin_unlock_irqrestore(&ring->lock, flags);
1546
1547         return ret;
1548 }
1549
1550 static struct sk_buff *bcmgenet_rx_refill(struct bcmgenet_priv *priv,
1551                                           struct enet_cb *cb)
1552 {
1553         struct device *kdev = &priv->pdev->dev;
1554         struct sk_buff *skb;
1555         struct sk_buff *rx_skb;
1556         dma_addr_t mapping;
1557
1558         /* Allocate a new Rx skb */
1559         skb = netdev_alloc_skb(priv->dev, priv->rx_buf_len + SKB_ALIGNMENT);
1560         if (!skb) {
1561                 priv->mib.alloc_rx_buff_failed++;
1562                 netif_err(priv, rx_err, priv->dev,
1563                           "%s: Rx skb allocation failed\n", __func__);
1564                 return NULL;
1565         }
1566
1567         /* DMA-map the new Rx skb */
1568         mapping = dma_map_single(kdev, skb->data, priv->rx_buf_len,
1569                                  DMA_FROM_DEVICE);
1570         if (dma_mapping_error(kdev, mapping)) {
1571                 priv->mib.rx_dma_failed++;
1572                 dev_kfree_skb_any(skb);
1573                 netif_err(priv, rx_err, priv->dev,
1574                           "%s: Rx skb DMA mapping failed\n", __func__);
1575                 return NULL;
1576         }
1577
1578         /* Grab the current Rx skb from the ring and DMA-unmap it */
1579         rx_skb = cb->skb;
1580         if (likely(rx_skb))
1581                 dma_unmap_single(kdev, dma_unmap_addr(cb, dma_addr),
1582                                  priv->rx_buf_len, DMA_FROM_DEVICE);
1583
1584         /* Put the new Rx skb on the ring */
1585         cb->skb = skb;
1586         dma_unmap_addr_set(cb, dma_addr, mapping);
1587         dmadesc_set_addr(priv, cb->bd_addr, mapping);
1588
1589         /* Return the current Rx skb to caller */
1590         return rx_skb;
1591 }
1592
1593 /* bcmgenet_desc_rx - descriptor based rx process.
1594  * this could be called from bottom half, or from NAPI polling method.
1595  */
1596 static unsigned int bcmgenet_desc_rx(struct bcmgenet_rx_ring *ring,
1597                                      unsigned int budget)
1598 {
1599         struct bcmgenet_priv *priv = ring->priv;
1600         struct net_device *dev = priv->dev;
1601         struct enet_cb *cb;
1602         struct sk_buff *skb;
1603         u32 dma_length_status;
1604         unsigned long dma_flag;
1605         int len;
1606         unsigned int rxpktprocessed = 0, rxpkttoprocess;
1607         unsigned int p_index, mask;
1608         unsigned int discards;
1609         unsigned int chksum_ok = 0;
1610
1611         /* Clear status before servicing to reduce spurious interrupts */
1612         if (ring->index == DESC_INDEX) {
1613                 bcmgenet_intrl2_0_writel(priv, UMAC_IRQ_RXDMA_DONE,
1614                                          INTRL2_CPU_CLEAR);
1615         } else {
1616                 mask = 1 << (UMAC_IRQ1_RX_INTR_SHIFT + ring->index);
1617                 bcmgenet_intrl2_1_writel(priv,
1618                                          mask,
1619                                          INTRL2_CPU_CLEAR);
1620         }
1621
1622         p_index = bcmgenet_rdma_ring_readl(priv, ring->index, RDMA_PROD_INDEX);
1623
1624         discards = (p_index >> DMA_P_INDEX_DISCARD_CNT_SHIFT) &
1625                    DMA_P_INDEX_DISCARD_CNT_MASK;
1626         if (discards > ring->old_discards) {
1627                 discards = discards - ring->old_discards;
1628                 dev->stats.rx_missed_errors += discards;
1629                 dev->stats.rx_errors += discards;
1630                 ring->old_discards += discards;
1631
1632                 /* Clear HW register when we reach 75% of maximum 0xFFFF */
1633                 if (ring->old_discards >= 0xC000) {
1634                         ring->old_discards = 0;
1635                         bcmgenet_rdma_ring_writel(priv, ring->index, 0,
1636                                                   RDMA_PROD_INDEX);
1637                 }
1638         }
1639
1640         p_index &= DMA_P_INDEX_MASK;
1641         rxpkttoprocess = (p_index - ring->c_index) & DMA_C_INDEX_MASK;
1642
1643         netif_dbg(priv, rx_status, dev,
1644                   "RDMA: rxpkttoprocess=%d\n", rxpkttoprocess);
1645
1646         while ((rxpktprocessed < rxpkttoprocess) &&
1647                (rxpktprocessed < budget)) {
1648                 cb = &priv->rx_cbs[ring->read_ptr];
1649                 skb = bcmgenet_rx_refill(priv, cb);
1650
1651                 if (unlikely(!skb)) {
1652                         dev->stats.rx_dropped++;
1653                         goto next;
1654                 }
1655
1656                 if (!priv->desc_64b_en) {
1657                         dma_length_status =
1658                                 dmadesc_get_length_status(priv, cb->bd_addr);
1659                 } else {
1660                         struct status_64 *status;
1661
1662                         status = (struct status_64 *)skb->data;
1663                         dma_length_status = status->length_status;
1664                 }
1665
1666                 /* DMA flags and length are still valid no matter how
1667                  * we got the Receive Status Vector (64B RSB or register)
1668                  */
1669                 dma_flag = dma_length_status & 0xffff;
1670                 len = dma_length_status >> DMA_BUFLENGTH_SHIFT;
1671
1672                 netif_dbg(priv, rx_status, dev,
1673                           "%s:p_ind=%d c_ind=%d read_ptr=%d len_stat=0x%08x\n",
1674                           __func__, p_index, ring->c_index,
1675                           ring->read_ptr, dma_length_status);
1676
1677                 if (unlikely(!(dma_flag & DMA_EOP) || !(dma_flag & DMA_SOP))) {
1678                         netif_err(priv, rx_status, dev,
1679                                   "dropping fragmented packet!\n");
1680                         dev->stats.rx_errors++;
1681                         dev_kfree_skb_any(skb);
1682                         goto next;
1683                 }
1684
1685                 /* report errors */
1686                 if (unlikely(dma_flag & (DMA_RX_CRC_ERROR |
1687                                                 DMA_RX_OV |
1688                                                 DMA_RX_NO |
1689                                                 DMA_RX_LG |
1690                                                 DMA_RX_RXER))) {
1691                         netif_err(priv, rx_status, dev, "dma_flag=0x%x\n",
1692                                   (unsigned int)dma_flag);
1693                         if (dma_flag & DMA_RX_CRC_ERROR)
1694                                 dev->stats.rx_crc_errors++;
1695                         if (dma_flag & DMA_RX_OV)
1696                                 dev->stats.rx_over_errors++;
1697                         if (dma_flag & DMA_RX_NO)
1698                                 dev->stats.rx_frame_errors++;
1699                         if (dma_flag & DMA_RX_LG)
1700                                 dev->stats.rx_length_errors++;
1701                         dev->stats.rx_errors++;
1702                         dev_kfree_skb_any(skb);
1703                         goto next;
1704                 } /* error packet */
1705
1706                 chksum_ok = (dma_flag & priv->dma_rx_chk_bit) &&
1707                              priv->desc_rxchk_en;
1708
1709                 skb_put(skb, len);
1710                 if (priv->desc_64b_en) {
1711                         skb_pull(skb, 64);
1712                         len -= 64;
1713                 }
1714
1715                 if (likely(chksum_ok))
1716                         skb->ip_summed = CHECKSUM_UNNECESSARY;
1717
1718                 /* remove hardware 2bytes added for IP alignment */
1719                 skb_pull(skb, 2);
1720                 len -= 2;
1721
1722                 if (priv->crc_fwd_en) {
1723                         skb_trim(skb, len - ETH_FCS_LEN);
1724                         len -= ETH_FCS_LEN;
1725                 }
1726
1727                 /*Finish setting up the received SKB and send it to the kernel*/
1728                 skb->protocol = eth_type_trans(skb, priv->dev);
1729                 dev->stats.rx_packets++;
1730                 dev->stats.rx_bytes += len;
1731                 if (dma_flag & DMA_RX_MULT)
1732                         dev->stats.multicast++;
1733
1734                 /* Notify kernel */
1735                 napi_gro_receive(&ring->napi, skb);
1736                 netif_dbg(priv, rx_status, dev, "pushed up to kernel\n");
1737
1738 next:
1739                 rxpktprocessed++;
1740                 if (likely(ring->read_ptr < ring->end_ptr))
1741                         ring->read_ptr++;
1742                 else
1743                         ring->read_ptr = ring->cb_ptr;
1744
1745                 ring->c_index = (ring->c_index + 1) & DMA_C_INDEX_MASK;
1746                 bcmgenet_rdma_ring_writel(priv, ring->index, ring->c_index, RDMA_CONS_INDEX);
1747         }
1748
1749         return rxpktprocessed;
1750 }
1751
1752 /* Rx NAPI polling method */
1753 static int bcmgenet_rx_poll(struct napi_struct *napi, int budget)
1754 {
1755         struct bcmgenet_rx_ring *ring = container_of(napi,
1756                         struct bcmgenet_rx_ring, napi);
1757         unsigned int work_done;
1758
1759         work_done = bcmgenet_desc_rx(ring, budget);
1760
1761         if (work_done < budget) {
1762                 napi_complete_done(napi, work_done);
1763                 ring->int_enable(ring);
1764         }
1765
1766         return work_done;
1767 }
1768
1769 /* Assign skb to RX DMA descriptor. */
1770 static int bcmgenet_alloc_rx_buffers(struct bcmgenet_priv *priv,
1771                                      struct bcmgenet_rx_ring *ring)
1772 {
1773         struct enet_cb *cb;
1774         struct sk_buff *skb;
1775         int i;
1776
1777         netif_dbg(priv, hw, priv->dev, "%s\n", __func__);
1778
1779         /* loop here for each buffer needing assign */
1780         for (i = 0; i < ring->size; i++) {
1781                 cb = ring->cbs + i;
1782                 skb = bcmgenet_rx_refill(priv, cb);
1783                 if (skb)
1784                         dev_kfree_skb_any(skb);
1785                 if (!cb->skb)
1786                         return -ENOMEM;
1787         }
1788
1789         return 0;
1790 }
1791
1792 static void bcmgenet_free_rx_buffers(struct bcmgenet_priv *priv)
1793 {
1794         struct device *kdev = &priv->pdev->dev;
1795         struct enet_cb *cb;
1796         int i;
1797
1798         for (i = 0; i < priv->num_rx_bds; i++) {
1799                 cb = &priv->rx_cbs[i];
1800
1801                 if (dma_unmap_addr(cb, dma_addr)) {
1802                         dma_unmap_single(kdev,
1803                                          dma_unmap_addr(cb, dma_addr),
1804                                          priv->rx_buf_len, DMA_FROM_DEVICE);
1805                         dma_unmap_addr_set(cb, dma_addr, 0);
1806                 }
1807
1808                 if (cb->skb)
1809                         bcmgenet_free_cb(cb);
1810         }
1811 }
1812
1813 static void umac_enable_set(struct bcmgenet_priv *priv, u32 mask, bool enable)
1814 {
1815         u32 reg;
1816
1817         reg = bcmgenet_umac_readl(priv, UMAC_CMD);
1818         if (enable)
1819                 reg |= mask;
1820         else
1821                 reg &= ~mask;
1822         bcmgenet_umac_writel(priv, reg, UMAC_CMD);
1823
1824         /* UniMAC stops on a packet boundary, wait for a full-size packet
1825          * to be processed
1826          */
1827         if (enable == 0)
1828                 usleep_range(1000, 2000);
1829 }
1830
1831 static int reset_umac(struct bcmgenet_priv *priv)
1832 {
1833         struct device *kdev = &priv->pdev->dev;
1834         unsigned int timeout = 0;
1835         u32 reg;
1836
1837         /* 7358a0/7552a0: bad default in RBUF_FLUSH_CTRL.umac_sw_rst */
1838         bcmgenet_rbuf_ctrl_set(priv, 0);
1839         udelay(10);
1840
1841         /* disable MAC while updating its registers */
1842         bcmgenet_umac_writel(priv, 0, UMAC_CMD);
1843
1844         /* issue soft reset, wait for it to complete */
1845         bcmgenet_umac_writel(priv, CMD_SW_RESET, UMAC_CMD);
1846         while (timeout++ < 1000) {
1847                 reg = bcmgenet_umac_readl(priv, UMAC_CMD);
1848                 if (!(reg & CMD_SW_RESET))
1849                         return 0;
1850
1851                 udelay(1);
1852         }
1853
1854         if (timeout == 1000) {
1855                 dev_err(kdev,
1856                         "timeout waiting for MAC to come out of reset\n");
1857                 return -ETIMEDOUT;
1858         }
1859
1860         return 0;
1861 }
1862
1863 static void bcmgenet_intr_disable(struct bcmgenet_priv *priv)
1864 {
1865         /* Mask all interrupts.*/
1866         bcmgenet_intrl2_0_writel(priv, 0xFFFFFFFF, INTRL2_CPU_MASK_SET);
1867         bcmgenet_intrl2_0_writel(priv, 0xFFFFFFFF, INTRL2_CPU_CLEAR);
1868         bcmgenet_intrl2_1_writel(priv, 0xFFFFFFFF, INTRL2_CPU_MASK_SET);
1869         bcmgenet_intrl2_1_writel(priv, 0xFFFFFFFF, INTRL2_CPU_CLEAR);
1870 }
1871
1872 static void bcmgenet_link_intr_enable(struct bcmgenet_priv *priv)
1873 {
1874         u32 int0_enable = 0;
1875
1876         /* Monitor cable plug/unplugged event for internal PHY, external PHY
1877          * and MoCA PHY
1878          */
1879         if (priv->internal_phy) {
1880                 int0_enable |= UMAC_IRQ_LINK_EVENT;
1881         } else if (priv->ext_phy) {
1882                 int0_enable |= UMAC_IRQ_LINK_EVENT;
1883         } else if (priv->phy_interface == PHY_INTERFACE_MODE_MOCA) {
1884                 if (priv->hw_params->flags & GENET_HAS_MOCA_LINK_DET)
1885                         int0_enable |= UMAC_IRQ_LINK_EVENT;
1886         }
1887         bcmgenet_intrl2_0_writel(priv, int0_enable, INTRL2_CPU_MASK_CLEAR);
1888 }
1889
1890 static int init_umac(struct bcmgenet_priv *priv)
1891 {
1892         struct device *kdev = &priv->pdev->dev;
1893         int ret;
1894         u32 reg;
1895         u32 int0_enable = 0;
1896
1897         dev_dbg(&priv->pdev->dev, "bcmgenet: init_umac\n");
1898
1899         ret = reset_umac(priv);
1900         if (ret)
1901                 return ret;
1902
1903         bcmgenet_umac_writel(priv, 0, UMAC_CMD);
1904         /* clear tx/rx counter */
1905         bcmgenet_umac_writel(priv,
1906                              MIB_RESET_RX | MIB_RESET_TX | MIB_RESET_RUNT,
1907                              UMAC_MIB_CTRL);
1908         bcmgenet_umac_writel(priv, 0, UMAC_MIB_CTRL);
1909
1910         bcmgenet_umac_writel(priv, ENET_MAX_MTU_SIZE, UMAC_MAX_FRAME_LEN);
1911
1912         /* init rx registers, enable ip header optimization */
1913         reg = bcmgenet_rbuf_readl(priv, RBUF_CTRL);
1914         reg |= RBUF_ALIGN_2B;
1915         bcmgenet_rbuf_writel(priv, reg, RBUF_CTRL);
1916
1917         if (!GENET_IS_V1(priv) && !GENET_IS_V2(priv))
1918                 bcmgenet_rbuf_writel(priv, 1, RBUF_TBUF_SIZE_CTRL);
1919
1920         bcmgenet_intr_disable(priv);
1921
1922         /* Configure backpressure vectors for MoCA */
1923         if (priv->phy_interface == PHY_INTERFACE_MODE_MOCA) {
1924                 reg = bcmgenet_bp_mc_get(priv);
1925                 reg |= BIT(priv->hw_params->bp_in_en_shift);
1926
1927                 /* bp_mask: back pressure mask */
1928                 if (netif_is_multiqueue(priv->dev))
1929                         reg |= priv->hw_params->bp_in_mask;
1930                 else
1931                         reg &= ~priv->hw_params->bp_in_mask;
1932                 bcmgenet_bp_mc_set(priv, reg);
1933         }
1934
1935         /* Enable MDIO interrupts on GENET v3+ */
1936         if (priv->hw_params->flags & GENET_HAS_MDIO_INTR)
1937                 int0_enable |= (UMAC_IRQ_MDIO_DONE | UMAC_IRQ_MDIO_ERROR);
1938
1939         bcmgenet_intrl2_0_writel(priv, int0_enable, INTRL2_CPU_MASK_CLEAR);
1940
1941         dev_dbg(kdev, "done init umac\n");
1942
1943         return 0;
1944 }
1945
1946 /* Initialize a Tx ring along with corresponding hardware registers */
1947 static void bcmgenet_init_tx_ring(struct bcmgenet_priv *priv,
1948                                   unsigned int index, unsigned int size,
1949                                   unsigned int start_ptr, unsigned int end_ptr)
1950 {
1951         struct bcmgenet_tx_ring *ring = &priv->tx_rings[index];
1952         u32 words_per_bd = WORDS_PER_BD(priv);
1953         u32 flow_period_val = 0;
1954
1955         spin_lock_init(&ring->lock);
1956         ring->priv = priv;
1957         ring->index = index;
1958         if (index == DESC_INDEX) {
1959                 ring->queue = 0;
1960                 ring->int_enable = bcmgenet_tx_ring16_int_enable;
1961                 ring->int_disable = bcmgenet_tx_ring16_int_disable;
1962         } else {
1963                 ring->queue = index + 1;
1964                 ring->int_enable = bcmgenet_tx_ring_int_enable;
1965                 ring->int_disable = bcmgenet_tx_ring_int_disable;
1966         }
1967         ring->cbs = priv->tx_cbs + start_ptr;
1968         ring->size = size;
1969         ring->clean_ptr = start_ptr;
1970         ring->c_index = 0;
1971         ring->free_bds = size;
1972         ring->write_ptr = start_ptr;
1973         ring->cb_ptr = start_ptr;
1974         ring->end_ptr = end_ptr - 1;
1975         ring->prod_index = 0;
1976
1977         /* Set flow period for ring != 16 */
1978         if (index != DESC_INDEX)
1979                 flow_period_val = ENET_MAX_MTU_SIZE << 16;
1980
1981         bcmgenet_tdma_ring_writel(priv, index, 0, TDMA_PROD_INDEX);
1982         bcmgenet_tdma_ring_writel(priv, index, 0, TDMA_CONS_INDEX);
1983         bcmgenet_tdma_ring_writel(priv, index, 1, DMA_MBUF_DONE_THRESH);
1984         /* Disable rate control for now */
1985         bcmgenet_tdma_ring_writel(priv, index, flow_period_val,
1986                                   TDMA_FLOW_PERIOD);
1987         bcmgenet_tdma_ring_writel(priv, index,
1988                                   ((size << DMA_RING_SIZE_SHIFT) |
1989                                    RX_BUF_LENGTH), DMA_RING_BUF_SIZE);
1990
1991         /* Set start and end address, read and write pointers */
1992         bcmgenet_tdma_ring_writel(priv, index, start_ptr * words_per_bd,
1993                                   DMA_START_ADDR);
1994         bcmgenet_tdma_ring_writel(priv, index, start_ptr * words_per_bd,
1995                                   TDMA_READ_PTR);
1996         bcmgenet_tdma_ring_writel(priv, index, start_ptr * words_per_bd,
1997                                   TDMA_WRITE_PTR);
1998         bcmgenet_tdma_ring_writel(priv, index, end_ptr * words_per_bd - 1,
1999                                   DMA_END_ADDR);
2000 }
2001
2002 /* Initialize a RDMA ring */
2003 static int bcmgenet_init_rx_ring(struct bcmgenet_priv *priv,
2004                                  unsigned int index, unsigned int size,
2005                                  unsigned int start_ptr, unsigned int end_ptr)
2006 {
2007         struct bcmgenet_rx_ring *ring = &priv->rx_rings[index];
2008         u32 words_per_bd = WORDS_PER_BD(priv);
2009         int ret;
2010
2011         ring->priv = priv;
2012         ring->index = index;
2013         if (index == DESC_INDEX) {
2014                 ring->int_enable = bcmgenet_rx_ring16_int_enable;
2015                 ring->int_disable = bcmgenet_rx_ring16_int_disable;
2016         } else {
2017                 ring->int_enable = bcmgenet_rx_ring_int_enable;
2018                 ring->int_disable = bcmgenet_rx_ring_int_disable;
2019         }
2020         ring->cbs = priv->rx_cbs + start_ptr;
2021         ring->size = size;
2022         ring->c_index = 0;
2023         ring->read_ptr = start_ptr;
2024         ring->cb_ptr = start_ptr;
2025         ring->end_ptr = end_ptr - 1;
2026
2027         ret = bcmgenet_alloc_rx_buffers(priv, ring);
2028         if (ret)
2029                 return ret;
2030
2031         bcmgenet_rdma_ring_writel(priv, index, 0, RDMA_PROD_INDEX);
2032         bcmgenet_rdma_ring_writel(priv, index, 0, RDMA_CONS_INDEX);
2033         bcmgenet_rdma_ring_writel(priv, index, 1, DMA_MBUF_DONE_THRESH);
2034         bcmgenet_rdma_ring_writel(priv, index,
2035                                   ((size << DMA_RING_SIZE_SHIFT) |
2036                                    RX_BUF_LENGTH), DMA_RING_BUF_SIZE);
2037         bcmgenet_rdma_ring_writel(priv, index,
2038                                   (DMA_FC_THRESH_LO <<
2039                                    DMA_XOFF_THRESHOLD_SHIFT) |
2040                                    DMA_FC_THRESH_HI, RDMA_XON_XOFF_THRESH);
2041
2042         /* Set start and end address, read and write pointers */
2043         bcmgenet_rdma_ring_writel(priv, index, start_ptr * words_per_bd,
2044                                   DMA_START_ADDR);
2045         bcmgenet_rdma_ring_writel(priv, index, start_ptr * words_per_bd,
2046                                   RDMA_READ_PTR);
2047         bcmgenet_rdma_ring_writel(priv, index, start_ptr * words_per_bd,
2048                                   RDMA_WRITE_PTR);
2049         bcmgenet_rdma_ring_writel(priv, index, end_ptr * words_per_bd - 1,
2050                                   DMA_END_ADDR);
2051
2052         return ret;
2053 }
2054
2055 static void bcmgenet_init_tx_napi(struct bcmgenet_priv *priv)
2056 {
2057         unsigned int i;
2058         struct bcmgenet_tx_ring *ring;
2059
2060         for (i = 0; i < priv->hw_params->tx_queues; ++i) {
2061                 ring = &priv->tx_rings[i];
2062                 netif_tx_napi_add(priv->dev, &ring->napi, bcmgenet_tx_poll, 64);
2063         }
2064
2065         ring = &priv->tx_rings[DESC_INDEX];
2066         netif_tx_napi_add(priv->dev, &ring->napi, bcmgenet_tx_poll, 64);
2067 }
2068
2069 static void bcmgenet_enable_tx_napi(struct bcmgenet_priv *priv)
2070 {
2071         unsigned int i;
2072         u32 int0_enable = UMAC_IRQ_TXDMA_DONE;
2073         u32 int1_enable = 0;
2074         struct bcmgenet_tx_ring *ring;
2075
2076         for (i = 0; i < priv->hw_params->tx_queues; ++i) {
2077                 ring = &priv->tx_rings[i];
2078                 napi_enable(&ring->napi);
2079                 int1_enable |= (1 << i);
2080         }
2081
2082         ring = &priv->tx_rings[DESC_INDEX];
2083         napi_enable(&ring->napi);
2084
2085         bcmgenet_intrl2_0_writel(priv, int0_enable, INTRL2_CPU_MASK_CLEAR);
2086         bcmgenet_intrl2_1_writel(priv, int1_enable, INTRL2_CPU_MASK_CLEAR);
2087 }
2088
2089 static void bcmgenet_disable_tx_napi(struct bcmgenet_priv *priv)
2090 {
2091         unsigned int i;
2092         u32 int0_disable = UMAC_IRQ_TXDMA_DONE;
2093         u32 int1_disable = 0xffff;
2094         struct bcmgenet_tx_ring *ring;
2095
2096         bcmgenet_intrl2_0_writel(priv, int0_disable, INTRL2_CPU_MASK_SET);
2097         bcmgenet_intrl2_1_writel(priv, int1_disable, INTRL2_CPU_MASK_SET);
2098
2099         for (i = 0; i < priv->hw_params->tx_queues; ++i) {
2100                 ring = &priv->tx_rings[i];
2101                 napi_disable(&ring->napi);
2102         }
2103
2104         ring = &priv->tx_rings[DESC_INDEX];
2105         napi_disable(&ring->napi);
2106 }
2107
2108 static void bcmgenet_fini_tx_napi(struct bcmgenet_priv *priv)
2109 {
2110         unsigned int i;
2111         struct bcmgenet_tx_ring *ring;
2112
2113         for (i = 0; i < priv->hw_params->tx_queues; ++i) {
2114                 ring = &priv->tx_rings[i];
2115                 netif_napi_del(&ring->napi);
2116         }
2117
2118         ring = &priv->tx_rings[DESC_INDEX];
2119         netif_napi_del(&ring->napi);
2120 }
2121
2122 /* Initialize Tx queues
2123  *
2124  * Queues 0-3 are priority-based, each one has 32 descriptors,
2125  * with queue 0 being the highest priority queue.
2126  *
2127  * Queue 16 is the default Tx queue with
2128  * GENET_Q16_TX_BD_CNT = 256 - 4 * 32 = 128 descriptors.
2129  *
2130  * The transmit control block pool is then partitioned as follows:
2131  * - Tx queue 0 uses tx_cbs[0..31]
2132  * - Tx queue 1 uses tx_cbs[32..63]
2133  * - Tx queue 2 uses tx_cbs[64..95]
2134  * - Tx queue 3 uses tx_cbs[96..127]
2135  * - Tx queue 16 uses tx_cbs[128..255]
2136  */
2137 static void bcmgenet_init_tx_queues(struct net_device *dev)
2138 {
2139         struct bcmgenet_priv *priv = netdev_priv(dev);
2140         u32 i, dma_enable;
2141         u32 dma_ctrl, ring_cfg;
2142         u32 dma_priority[3] = {0, 0, 0};
2143
2144         dma_ctrl = bcmgenet_tdma_readl(priv, DMA_CTRL);
2145         dma_enable = dma_ctrl & DMA_EN;
2146         dma_ctrl &= ~DMA_EN;
2147         bcmgenet_tdma_writel(priv, dma_ctrl, DMA_CTRL);
2148
2149         dma_ctrl = 0;
2150         ring_cfg = 0;
2151
2152         /* Enable strict priority arbiter mode */
2153         bcmgenet_tdma_writel(priv, DMA_ARBITER_SP, DMA_ARB_CTRL);
2154
2155         /* Initialize Tx priority queues */
2156         for (i = 0; i < priv->hw_params->tx_queues; i++) {
2157                 bcmgenet_init_tx_ring(priv, i, priv->hw_params->tx_bds_per_q,
2158                                       i * priv->hw_params->tx_bds_per_q,
2159                                       (i + 1) * priv->hw_params->tx_bds_per_q);
2160                 ring_cfg |= (1 << i);
2161                 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT));
2162                 dma_priority[DMA_PRIO_REG_INDEX(i)] |=
2163                         ((GENET_Q0_PRIORITY + i) << DMA_PRIO_REG_SHIFT(i));
2164         }
2165
2166         /* Initialize Tx default queue 16 */
2167         bcmgenet_init_tx_ring(priv, DESC_INDEX, GENET_Q16_TX_BD_CNT,
2168                               priv->hw_params->tx_queues *
2169                               priv->hw_params->tx_bds_per_q,
2170                               TOTAL_DESC);
2171         ring_cfg |= (1 << DESC_INDEX);
2172         dma_ctrl |= (1 << (DESC_INDEX + DMA_RING_BUF_EN_SHIFT));
2173         dma_priority[DMA_PRIO_REG_INDEX(DESC_INDEX)] |=
2174                 ((GENET_Q0_PRIORITY + priv->hw_params->tx_queues) <<
2175                  DMA_PRIO_REG_SHIFT(DESC_INDEX));
2176
2177         /* Set Tx queue priorities */
2178         bcmgenet_tdma_writel(priv, dma_priority[0], DMA_PRIORITY_0);
2179         bcmgenet_tdma_writel(priv, dma_priority[1], DMA_PRIORITY_1);
2180         bcmgenet_tdma_writel(priv, dma_priority[2], DMA_PRIORITY_2);
2181
2182         /* Initialize Tx NAPI */
2183         bcmgenet_init_tx_napi(priv);
2184
2185         /* Enable Tx queues */
2186         bcmgenet_tdma_writel(priv, ring_cfg, DMA_RING_CFG);
2187
2188         /* Enable Tx DMA */
2189         if (dma_enable)
2190                 dma_ctrl |= DMA_EN;
2191         bcmgenet_tdma_writel(priv, dma_ctrl, DMA_CTRL);
2192 }
2193
2194 static void bcmgenet_init_rx_napi(struct bcmgenet_priv *priv)
2195 {
2196         unsigned int i;
2197         struct bcmgenet_rx_ring *ring;
2198
2199         for (i = 0; i < priv->hw_params->rx_queues; ++i) {
2200                 ring = &priv->rx_rings[i];
2201                 netif_napi_add(priv->dev, &ring->napi, bcmgenet_rx_poll, 64);
2202         }
2203
2204         ring = &priv->rx_rings[DESC_INDEX];
2205         netif_napi_add(priv->dev, &ring->napi, bcmgenet_rx_poll, 64);
2206 }
2207
2208 static void bcmgenet_enable_rx_napi(struct bcmgenet_priv *priv)
2209 {
2210         unsigned int i;
2211         u32 int0_enable = UMAC_IRQ_RXDMA_DONE;
2212         u32 int1_enable = 0;
2213         struct bcmgenet_rx_ring *ring;
2214
2215         for (i = 0; i < priv->hw_params->rx_queues; ++i) {
2216                 ring = &priv->rx_rings[i];
2217                 napi_enable(&ring->napi);
2218                 int1_enable |= (1 << (UMAC_IRQ1_RX_INTR_SHIFT + i));
2219         }
2220
2221         ring = &priv->rx_rings[DESC_INDEX];
2222         napi_enable(&ring->napi);
2223
2224         bcmgenet_intrl2_0_writel(priv, int0_enable, INTRL2_CPU_MASK_CLEAR);
2225         bcmgenet_intrl2_1_writel(priv, int1_enable, INTRL2_CPU_MASK_CLEAR);
2226 }
2227
2228 static void bcmgenet_disable_rx_napi(struct bcmgenet_priv *priv)
2229 {
2230         unsigned int i;
2231         u32 int0_disable = UMAC_IRQ_RXDMA_DONE;
2232         u32 int1_disable = 0xffff << UMAC_IRQ1_RX_INTR_SHIFT;
2233         struct bcmgenet_rx_ring *ring;
2234
2235         bcmgenet_intrl2_0_writel(priv, int0_disable, INTRL2_CPU_MASK_SET);
2236         bcmgenet_intrl2_1_writel(priv, int1_disable, INTRL2_CPU_MASK_SET);
2237
2238         for (i = 0; i < priv->hw_params->rx_queues; ++i) {
2239                 ring = &priv->rx_rings[i];
2240                 napi_disable(&ring->napi);
2241         }
2242
2243         ring = &priv->rx_rings[DESC_INDEX];
2244         napi_disable(&ring->napi);
2245 }
2246
2247 static void bcmgenet_fini_rx_napi(struct bcmgenet_priv *priv)
2248 {
2249         unsigned int i;
2250         struct bcmgenet_rx_ring *ring;
2251
2252         for (i = 0; i < priv->hw_params->rx_queues; ++i) {
2253                 ring = &priv->rx_rings[i];
2254                 netif_napi_del(&ring->napi);
2255         }
2256
2257         ring = &priv->rx_rings[DESC_INDEX];
2258         netif_napi_del(&ring->napi);
2259 }
2260
2261 /* Initialize Rx queues
2262  *
2263  * Queues 0-15 are priority queues. Hardware Filtering Block (HFB) can be
2264  * used to direct traffic to these queues.
2265  *
2266  * Queue 16 is the default Rx queue with GENET_Q16_RX_BD_CNT descriptors.
2267  */
2268 static int bcmgenet_init_rx_queues(struct net_device *dev)
2269 {
2270         struct bcmgenet_priv *priv = netdev_priv(dev);
2271         u32 i;
2272         u32 dma_enable;
2273         u32 dma_ctrl;
2274         u32 ring_cfg;
2275         int ret;
2276
2277         dma_ctrl = bcmgenet_rdma_readl(priv, DMA_CTRL);
2278         dma_enable = dma_ctrl & DMA_EN;
2279         dma_ctrl &= ~DMA_EN;
2280         bcmgenet_rdma_writel(priv, dma_ctrl, DMA_CTRL);
2281
2282         dma_ctrl = 0;
2283         ring_cfg = 0;
2284
2285         /* Initialize Rx priority queues */
2286         for (i = 0; i < priv->hw_params->rx_queues; i++) {
2287                 ret = bcmgenet_init_rx_ring(priv, i,
2288                                             priv->hw_params->rx_bds_per_q,
2289                                             i * priv->hw_params->rx_bds_per_q,
2290                                             (i + 1) *
2291                                             priv->hw_params->rx_bds_per_q);
2292                 if (ret)
2293                         return ret;
2294
2295                 ring_cfg |= (1 << i);
2296                 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT));
2297         }
2298
2299         /* Initialize Rx default queue 16 */
2300         ret = bcmgenet_init_rx_ring(priv, DESC_INDEX, GENET_Q16_RX_BD_CNT,
2301                                     priv->hw_params->rx_queues *
2302                                     priv->hw_params->rx_bds_per_q,
2303                                     TOTAL_DESC);
2304         if (ret)
2305                 return ret;
2306
2307         ring_cfg |= (1 << DESC_INDEX);
2308         dma_ctrl |= (1 << (DESC_INDEX + DMA_RING_BUF_EN_SHIFT));
2309
2310         /* Initialize Rx NAPI */
2311         bcmgenet_init_rx_napi(priv);
2312
2313         /* Enable rings */
2314         bcmgenet_rdma_writel(priv, ring_cfg, DMA_RING_CFG);
2315
2316         /* Configure ring as descriptor ring and re-enable DMA if enabled */
2317         if (dma_enable)
2318                 dma_ctrl |= DMA_EN;
2319         bcmgenet_rdma_writel(priv, dma_ctrl, DMA_CTRL);
2320
2321         return 0;
2322 }
2323
2324 static int bcmgenet_dma_teardown(struct bcmgenet_priv *priv)
2325 {
2326         int ret = 0;
2327         int timeout = 0;
2328         u32 reg;
2329         u32 dma_ctrl;
2330         int i;
2331
2332         /* Disable TDMA to stop add more frames in TX DMA */
2333         reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
2334         reg &= ~DMA_EN;
2335         bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
2336
2337         /* Check TDMA status register to confirm TDMA is disabled */
2338         while (timeout++ < DMA_TIMEOUT_VAL) {
2339                 reg = bcmgenet_tdma_readl(priv, DMA_STATUS);
2340                 if (reg & DMA_DISABLED)
2341                         break;
2342
2343                 udelay(1);
2344         }
2345
2346         if (timeout == DMA_TIMEOUT_VAL) {
2347                 netdev_warn(priv->dev, "Timed out while disabling TX DMA\n");
2348                 ret = -ETIMEDOUT;
2349         }
2350
2351         /* Wait 10ms for packet drain in both tx and rx dma */
2352         usleep_range(10000, 20000);
2353
2354         /* Disable RDMA */
2355         reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
2356         reg &= ~DMA_EN;
2357         bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
2358
2359         timeout = 0;
2360         /* Check RDMA status register to confirm RDMA is disabled */
2361         while (timeout++ < DMA_TIMEOUT_VAL) {
2362                 reg = bcmgenet_rdma_readl(priv, DMA_STATUS);
2363                 if (reg & DMA_DISABLED)
2364                         break;
2365
2366                 udelay(1);
2367         }
2368
2369         if (timeout == DMA_TIMEOUT_VAL) {
2370                 netdev_warn(priv->dev, "Timed out while disabling RX DMA\n");
2371                 ret = -ETIMEDOUT;
2372         }
2373
2374         dma_ctrl = 0;
2375         for (i = 0; i < priv->hw_params->rx_queues; i++)
2376                 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT));
2377         reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
2378         reg &= ~dma_ctrl;
2379         bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
2380
2381         dma_ctrl = 0;
2382         for (i = 0; i < priv->hw_params->tx_queues; i++)
2383                 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT));
2384         reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
2385         reg &= ~dma_ctrl;
2386         bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
2387
2388         return ret;
2389 }
2390
2391 static void bcmgenet_fini_dma(struct bcmgenet_priv *priv)
2392 {
2393         int i;
2394         struct netdev_queue *txq;
2395
2396         bcmgenet_fini_rx_napi(priv);
2397         bcmgenet_fini_tx_napi(priv);
2398
2399         /* disable DMA */
2400         bcmgenet_dma_teardown(priv);
2401
2402         for (i = 0; i < priv->num_tx_bds; i++) {
2403                 if (priv->tx_cbs[i].skb != NULL) {
2404                         dev_kfree_skb(priv->tx_cbs[i].skb);
2405                         priv->tx_cbs[i].skb = NULL;
2406                 }
2407         }
2408
2409         for (i = 0; i < priv->hw_params->tx_queues; i++) {
2410                 txq = netdev_get_tx_queue(priv->dev, priv->tx_rings[i].queue);
2411                 netdev_tx_reset_queue(txq);
2412         }
2413
2414         txq = netdev_get_tx_queue(priv->dev, priv->tx_rings[DESC_INDEX].queue);
2415         netdev_tx_reset_queue(txq);
2416
2417         bcmgenet_free_rx_buffers(priv);
2418         kfree(priv->rx_cbs);
2419         kfree(priv->tx_cbs);
2420 }
2421
2422 /* init_edma: Initialize DMA control register */
2423 static int bcmgenet_init_dma(struct bcmgenet_priv *priv)
2424 {
2425         int ret;
2426         unsigned int i;
2427         struct enet_cb *cb;
2428
2429         netif_dbg(priv, hw, priv->dev, "%s\n", __func__);
2430
2431         /* Initialize common Rx ring structures */
2432         priv->rx_bds = priv->base + priv->hw_params->rdma_offset;
2433         priv->num_rx_bds = TOTAL_DESC;
2434         priv->rx_cbs = kcalloc(priv->num_rx_bds, sizeof(struct enet_cb),
2435                                GFP_KERNEL);
2436         if (!priv->rx_cbs)
2437                 return -ENOMEM;
2438
2439         for (i = 0; i < priv->num_rx_bds; i++) {
2440                 cb = priv->rx_cbs + i;
2441                 cb->bd_addr = priv->rx_bds + i * DMA_DESC_SIZE;
2442         }
2443
2444         /* Initialize common TX ring structures */
2445         priv->tx_bds = priv->base + priv->hw_params->tdma_offset;
2446         priv->num_tx_bds = TOTAL_DESC;
2447         priv->tx_cbs = kcalloc(priv->num_tx_bds, sizeof(struct enet_cb),
2448                                GFP_KERNEL);
2449         if (!priv->tx_cbs) {
2450                 kfree(priv->rx_cbs);
2451                 return -ENOMEM;
2452         }
2453
2454         for (i = 0; i < priv->num_tx_bds; i++) {
2455                 cb = priv->tx_cbs + i;
2456                 cb->bd_addr = priv->tx_bds + i * DMA_DESC_SIZE;
2457         }
2458
2459         /* Init rDma */
2460         bcmgenet_rdma_writel(priv, DMA_MAX_BURST_LENGTH, DMA_SCB_BURST_SIZE);
2461
2462         /* Initialize Rx queues */
2463         ret = bcmgenet_init_rx_queues(priv->dev);
2464         if (ret) {
2465                 netdev_err(priv->dev, "failed to initialize Rx queues\n");
2466                 bcmgenet_free_rx_buffers(priv);
2467                 kfree(priv->rx_cbs);
2468                 kfree(priv->tx_cbs);
2469                 return ret;
2470         }
2471
2472         /* Init tDma */
2473         bcmgenet_tdma_writel(priv, DMA_MAX_BURST_LENGTH, DMA_SCB_BURST_SIZE);
2474
2475         /* Initialize Tx queues */
2476         bcmgenet_init_tx_queues(priv->dev);
2477
2478         return 0;
2479 }
2480
2481 /* Interrupt bottom half */
2482 static void bcmgenet_irq_task(struct work_struct *work)
2483 {
2484         struct bcmgenet_priv *priv = container_of(
2485                         work, struct bcmgenet_priv, bcmgenet_irq_work);
2486
2487         netif_dbg(priv, intr, priv->dev, "%s\n", __func__);
2488
2489         /* Link UP/DOWN event */
2490         if (priv->irq0_stat & UMAC_IRQ_LINK_EVENT) {
2491                 phy_mac_interrupt(priv->phydev,
2492                                   !!(priv->irq0_stat & UMAC_IRQ_LINK_UP));
2493                 priv->irq0_stat &= ~UMAC_IRQ_LINK_EVENT;
2494         }
2495 }
2496
2497 /* bcmgenet_isr1: handle Rx and Tx priority queues */
2498 static irqreturn_t bcmgenet_isr1(int irq, void *dev_id)
2499 {
2500         struct bcmgenet_priv *priv = dev_id;
2501         struct bcmgenet_rx_ring *rx_ring;
2502         struct bcmgenet_tx_ring *tx_ring;
2503         unsigned int index;
2504
2505         /* Save irq status for bottom-half processing. */
2506         priv->irq1_stat =
2507                 bcmgenet_intrl2_1_readl(priv, INTRL2_CPU_STAT) &
2508                 ~bcmgenet_intrl2_1_readl(priv, INTRL2_CPU_MASK_STATUS);
2509
2510         /* clear interrupts */
2511         bcmgenet_intrl2_1_writel(priv, priv->irq1_stat, INTRL2_CPU_CLEAR);
2512
2513         netif_dbg(priv, intr, priv->dev,
2514                   "%s: IRQ=0x%x\n", __func__, priv->irq1_stat);
2515
2516         /* Check Rx priority queue interrupts */
2517         for (index = 0; index < priv->hw_params->rx_queues; index++) {
2518                 if (!(priv->irq1_stat & BIT(UMAC_IRQ1_RX_INTR_SHIFT + index)))
2519                         continue;
2520
2521                 rx_ring = &priv->rx_rings[index];
2522
2523                 if (likely(napi_schedule_prep(&rx_ring->napi))) {
2524                         rx_ring->int_disable(rx_ring);
2525                         __napi_schedule_irqoff(&rx_ring->napi);
2526                 }
2527         }
2528
2529         /* Check Tx priority queue interrupts */
2530         for (index = 0; index < priv->hw_params->tx_queues; index++) {
2531                 if (!(priv->irq1_stat & BIT(index)))
2532                         continue;
2533
2534                 tx_ring = &priv->tx_rings[index];
2535
2536                 if (likely(napi_schedule_prep(&tx_ring->napi))) {
2537                         tx_ring->int_disable(tx_ring);
2538                         __napi_schedule_irqoff(&tx_ring->napi);
2539                 }
2540         }
2541
2542         return IRQ_HANDLED;
2543 }
2544
2545 /* bcmgenet_isr0: handle Rx and Tx default queues + other stuff */
2546 static irqreturn_t bcmgenet_isr0(int irq, void *dev_id)
2547 {
2548         struct bcmgenet_priv *priv = dev_id;
2549         struct bcmgenet_rx_ring *rx_ring;
2550         struct bcmgenet_tx_ring *tx_ring;
2551
2552         /* Save irq status for bottom-half processing. */
2553         priv->irq0_stat =
2554                 bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_STAT) &
2555                 ~bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_MASK_STATUS);
2556
2557         /* clear interrupts */
2558         bcmgenet_intrl2_0_writel(priv, priv->irq0_stat, INTRL2_CPU_CLEAR);
2559
2560         netif_dbg(priv, intr, priv->dev,
2561                   "IRQ=0x%x\n", priv->irq0_stat);
2562
2563         if (priv->irq0_stat & UMAC_IRQ_RXDMA_DONE) {
2564                 rx_ring = &priv->rx_rings[DESC_INDEX];
2565
2566                 if (likely(napi_schedule_prep(&rx_ring->napi))) {
2567                         rx_ring->int_disable(rx_ring);
2568                         __napi_schedule_irqoff(&rx_ring->napi);
2569                 }
2570         }
2571
2572         if (priv->irq0_stat & UMAC_IRQ_TXDMA_DONE) {
2573                 tx_ring = &priv->tx_rings[DESC_INDEX];
2574
2575                 if (likely(napi_schedule_prep(&tx_ring->napi))) {
2576                         tx_ring->int_disable(tx_ring);
2577                         __napi_schedule_irqoff(&tx_ring->napi);
2578                 }
2579         }
2580
2581         if (priv->irq0_stat & (UMAC_IRQ_PHY_DET_R |
2582                                 UMAC_IRQ_PHY_DET_F |
2583                                 UMAC_IRQ_LINK_EVENT |
2584                                 UMAC_IRQ_HFB_SM |
2585                                 UMAC_IRQ_HFB_MM)) {
2586                 /* all other interested interrupts handled in bottom half */
2587                 schedule_work(&priv->bcmgenet_irq_work);
2588         }
2589
2590         if ((priv->hw_params->flags & GENET_HAS_MDIO_INTR) &&
2591             priv->irq0_stat & (UMAC_IRQ_MDIO_DONE | UMAC_IRQ_MDIO_ERROR)) {
2592                 priv->irq0_stat &= ~(UMAC_IRQ_MDIO_DONE | UMAC_IRQ_MDIO_ERROR);
2593                 wake_up(&priv->wq);
2594         }
2595
2596         return IRQ_HANDLED;
2597 }
2598
2599 static irqreturn_t bcmgenet_wol_isr(int irq, void *dev_id)
2600 {
2601         struct bcmgenet_priv *priv = dev_id;
2602
2603         pm_wakeup_event(&priv->pdev->dev, 0);
2604
2605         return IRQ_HANDLED;
2606 }
2607
2608 #ifdef CONFIG_NET_POLL_CONTROLLER
2609 static void bcmgenet_poll_controller(struct net_device *dev)
2610 {
2611         struct bcmgenet_priv *priv = netdev_priv(dev);
2612
2613         /* Invoke the main RX/TX interrupt handler */
2614         disable_irq(priv->irq0);
2615         bcmgenet_isr0(priv->irq0, priv);
2616         enable_irq(priv->irq0);
2617
2618         /* And the interrupt handler for RX/TX priority queues */
2619         disable_irq(priv->irq1);
2620         bcmgenet_isr1(priv->irq1, priv);
2621         enable_irq(priv->irq1);
2622 }
2623 #endif
2624
2625 static void bcmgenet_umac_reset(struct bcmgenet_priv *priv)
2626 {
2627         u32 reg;
2628
2629         reg = bcmgenet_rbuf_ctrl_get(priv);
2630         reg |= BIT(1);
2631         bcmgenet_rbuf_ctrl_set(priv, reg);
2632         udelay(10);
2633
2634         reg &= ~BIT(1);
2635         bcmgenet_rbuf_ctrl_set(priv, reg);
2636         udelay(10);
2637 }
2638
2639 static void bcmgenet_set_hw_addr(struct bcmgenet_priv *priv,
2640                                  unsigned char *addr)
2641 {
2642         bcmgenet_umac_writel(priv, (addr[0] << 24) | (addr[1] << 16) |
2643                         (addr[2] << 8) | addr[3], UMAC_MAC0);
2644         bcmgenet_umac_writel(priv, (addr[4] << 8) | addr[5], UMAC_MAC1);
2645 }
2646
2647 /* Returns a reusable dma control register value */
2648 static u32 bcmgenet_dma_disable(struct bcmgenet_priv *priv)
2649 {
2650         u32 reg;
2651         u32 dma_ctrl;
2652
2653         /* disable DMA */
2654         dma_ctrl = 1 << (DESC_INDEX + DMA_RING_BUF_EN_SHIFT) | DMA_EN;
2655         reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
2656         reg &= ~dma_ctrl;
2657         bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
2658
2659         reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
2660         reg &= ~dma_ctrl;
2661         bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
2662
2663         bcmgenet_umac_writel(priv, 1, UMAC_TX_FLUSH);
2664         udelay(10);
2665         bcmgenet_umac_writel(priv, 0, UMAC_TX_FLUSH);
2666
2667         return dma_ctrl;
2668 }
2669
2670 static void bcmgenet_enable_dma(struct bcmgenet_priv *priv, u32 dma_ctrl)
2671 {
2672         u32 reg;
2673
2674         reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
2675         reg |= dma_ctrl;
2676         bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
2677
2678         reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
2679         reg |= dma_ctrl;
2680         bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
2681 }
2682
2683 /* bcmgenet_hfb_clear
2684  *
2685  * Clear Hardware Filter Block and disable all filtering.
2686  */
2687 static void bcmgenet_hfb_clear(struct bcmgenet_priv *priv)
2688 {
2689         u32 i;
2690
2691         bcmgenet_hfb_reg_writel(priv, 0x0, HFB_CTRL);
2692         bcmgenet_hfb_reg_writel(priv, 0x0, HFB_FLT_ENABLE_V3PLUS);
2693         bcmgenet_hfb_reg_writel(priv, 0x0, HFB_FLT_ENABLE_V3PLUS + 4);
2694
2695         for (i = DMA_INDEX2RING_0; i <= DMA_INDEX2RING_7; i++)
2696                 bcmgenet_rdma_writel(priv, 0x0, i);
2697
2698         for (i = 0; i < (priv->hw_params->hfb_filter_cnt / 4); i++)
2699                 bcmgenet_hfb_reg_writel(priv, 0x0,
2700                                         HFB_FLT_LEN_V3PLUS + i * sizeof(u32));
2701
2702         for (i = 0; i < priv->hw_params->hfb_filter_cnt *
2703                         priv->hw_params->hfb_filter_size; i++)
2704                 bcmgenet_hfb_writel(priv, 0x0, i * sizeof(u32));
2705 }
2706
2707 static void bcmgenet_hfb_init(struct bcmgenet_priv *priv)
2708 {
2709         if (GENET_IS_V1(priv) || GENET_IS_V2(priv))
2710                 return;
2711
2712         bcmgenet_hfb_clear(priv);
2713 }
2714
2715 static void bcmgenet_netif_start(struct net_device *dev)
2716 {
2717         struct bcmgenet_priv *priv = netdev_priv(dev);
2718
2719         /* Start the network engine */
2720         bcmgenet_enable_rx_napi(priv);
2721         bcmgenet_enable_tx_napi(priv);
2722
2723         umac_enable_set(priv, CMD_TX_EN | CMD_RX_EN, true);
2724
2725         netif_tx_start_all_queues(dev);
2726
2727         /* Monitor link interrupts now */
2728         bcmgenet_link_intr_enable(priv);
2729
2730         phy_start(priv->phydev);
2731 }
2732
2733 static int bcmgenet_open(struct net_device *dev)
2734 {
2735         struct bcmgenet_priv *priv = netdev_priv(dev);
2736         unsigned long dma_ctrl;
2737         u32 reg;
2738         int ret;
2739
2740         netif_dbg(priv, ifup, dev, "bcmgenet_open\n");
2741
2742         /* Turn on the clock */
2743         clk_prepare_enable(priv->clk);
2744
2745         /* If this is an internal GPHY, power it back on now, before UniMAC is
2746          * brought out of reset as absolutely no UniMAC activity is allowed
2747          */
2748         if (priv->internal_phy)
2749                 bcmgenet_power_up(priv, GENET_POWER_PASSIVE);
2750
2751         /* take MAC out of reset */
2752         bcmgenet_umac_reset(priv);
2753
2754         ret = init_umac(priv);
2755         if (ret)
2756                 goto err_clk_disable;
2757
2758         /* disable ethernet MAC while updating its registers */
2759         umac_enable_set(priv, CMD_TX_EN | CMD_RX_EN, false);
2760
2761         /* Make sure we reflect the value of CRC_CMD_FWD */
2762         reg = bcmgenet_umac_readl(priv, UMAC_CMD);
2763         priv->crc_fwd_en = !!(reg & CMD_CRC_FWD);
2764
2765         bcmgenet_set_hw_addr(priv, dev->dev_addr);
2766
2767         if (priv->internal_phy) {
2768                 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
2769                 reg |= EXT_ENERGY_DET_MASK;
2770                 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
2771         }
2772
2773         /* Disable RX/TX DMA and flush TX queues */
2774         dma_ctrl = bcmgenet_dma_disable(priv);
2775
2776         /* Reinitialize TDMA and RDMA and SW housekeeping */
2777         ret = bcmgenet_init_dma(priv);
2778         if (ret) {
2779                 netdev_err(dev, "failed to initialize DMA\n");
2780                 goto err_clk_disable;
2781         }
2782
2783         /* Always enable ring 16 - descriptor ring */
2784         bcmgenet_enable_dma(priv, dma_ctrl);
2785
2786         /* HFB init */
2787         bcmgenet_hfb_init(priv);
2788
2789         ret = request_irq(priv->irq0, bcmgenet_isr0, IRQF_SHARED,
2790                           dev->name, priv);
2791         if (ret < 0) {
2792                 netdev_err(dev, "can't request IRQ %d\n", priv->irq0);
2793                 goto err_fini_dma;
2794         }
2795
2796         ret = request_irq(priv->irq1, bcmgenet_isr1, IRQF_SHARED,
2797                           dev->name, priv);
2798         if (ret < 0) {
2799                 netdev_err(dev, "can't request IRQ %d\n", priv->irq1);
2800                 goto err_irq0;
2801         }
2802
2803         ret = bcmgenet_mii_probe(dev);
2804         if (ret) {
2805                 netdev_err(dev, "failed to connect to PHY\n");
2806                 goto err_irq1;
2807         }
2808
2809         bcmgenet_netif_start(dev);
2810
2811         return 0;
2812
2813 err_irq1:
2814         free_irq(priv->irq1, priv);
2815 err_irq0:
2816         free_irq(priv->irq0, priv);
2817 err_fini_dma:
2818         bcmgenet_fini_dma(priv);
2819 err_clk_disable:
2820         clk_disable_unprepare(priv->clk);
2821         return ret;
2822 }
2823
2824 static void bcmgenet_netif_stop(struct net_device *dev)
2825 {
2826         struct bcmgenet_priv *priv = netdev_priv(dev);
2827
2828         netif_tx_stop_all_queues(dev);
2829         phy_stop(priv->phydev);
2830         bcmgenet_intr_disable(priv);
2831         bcmgenet_disable_rx_napi(priv);
2832         bcmgenet_disable_tx_napi(priv);
2833
2834         /* Wait for pending work items to complete. Since interrupts are
2835          * disabled no new work will be scheduled.
2836          */
2837         cancel_work_sync(&priv->bcmgenet_irq_work);
2838
2839         priv->old_link = -1;
2840         priv->old_speed = -1;
2841         priv->old_duplex = -1;
2842         priv->old_pause = -1;
2843 }
2844
2845 static int bcmgenet_close(struct net_device *dev)
2846 {
2847         struct bcmgenet_priv *priv = netdev_priv(dev);
2848         int ret;
2849
2850         netif_dbg(priv, ifdown, dev, "bcmgenet_close\n");
2851
2852         bcmgenet_netif_stop(dev);
2853
2854         /* Really kill the PHY state machine and disconnect from it */
2855         phy_disconnect(priv->phydev);
2856
2857         /* Disable MAC receive */
2858         umac_enable_set(priv, CMD_RX_EN, false);
2859
2860         ret = bcmgenet_dma_teardown(priv);
2861         if (ret)
2862                 return ret;
2863
2864         /* Disable MAC transmit. TX DMA disabled must be done before this */
2865         umac_enable_set(priv, CMD_TX_EN, false);
2866
2867         /* tx reclaim */
2868         bcmgenet_tx_reclaim_all(dev);
2869         bcmgenet_fini_dma(priv);
2870
2871         free_irq(priv->irq0, priv);
2872         free_irq(priv->irq1, priv);
2873
2874         if (priv->internal_phy)
2875                 ret = bcmgenet_power_down(priv, GENET_POWER_PASSIVE);
2876
2877         clk_disable_unprepare(priv->clk);
2878
2879         return ret;
2880 }
2881
2882 static void bcmgenet_dump_tx_queue(struct bcmgenet_tx_ring *ring)
2883 {
2884         struct bcmgenet_priv *priv = ring->priv;
2885         u32 p_index, c_index, intsts, intmsk;
2886         struct netdev_queue *txq;
2887         unsigned int free_bds;
2888         unsigned long flags;
2889         bool txq_stopped;
2890
2891         if (!netif_msg_tx_err(priv))
2892                 return;
2893
2894         txq = netdev_get_tx_queue(priv->dev, ring->queue);
2895
2896         spin_lock_irqsave(&ring->lock, flags);
2897         if (ring->index == DESC_INDEX) {
2898                 intsts = ~bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_MASK_STATUS);
2899                 intmsk = UMAC_IRQ_TXDMA_DONE | UMAC_IRQ_TXDMA_MBDONE;
2900         } else {
2901                 intsts = ~bcmgenet_intrl2_1_readl(priv, INTRL2_CPU_MASK_STATUS);
2902                 intmsk = 1 << ring->index;
2903         }
2904         c_index = bcmgenet_tdma_ring_readl(priv, ring->index, TDMA_CONS_INDEX);
2905         p_index = bcmgenet_tdma_ring_readl(priv, ring->index, TDMA_PROD_INDEX);
2906         txq_stopped = netif_tx_queue_stopped(txq);
2907         free_bds = ring->free_bds;
2908         spin_unlock_irqrestore(&ring->lock, flags);
2909
2910         netif_err(priv, tx_err, priv->dev, "Ring %d queue %d status summary\n"
2911                   "TX queue status: %s, interrupts: %s\n"
2912                   "(sw)free_bds: %d (sw)size: %d\n"
2913                   "(sw)p_index: %d (hw)p_index: %d\n"
2914                   "(sw)c_index: %d (hw)c_index: %d\n"
2915                   "(sw)clean_p: %d (sw)write_p: %d\n"
2916                   "(sw)cb_ptr: %d (sw)end_ptr: %d\n",
2917                   ring->index, ring->queue,
2918                   txq_stopped ? "stopped" : "active",
2919                   intsts & intmsk ? "enabled" : "disabled",
2920                   free_bds, ring->size,
2921                   ring->prod_index, p_index & DMA_P_INDEX_MASK,
2922                   ring->c_index, c_index & DMA_C_INDEX_MASK,
2923                   ring->clean_ptr, ring->write_ptr,
2924                   ring->cb_ptr, ring->end_ptr);
2925 }
2926
2927 static void bcmgenet_timeout(struct net_device *dev)
2928 {
2929         struct bcmgenet_priv *priv = netdev_priv(dev);
2930         u32 int0_enable = 0;
2931         u32 int1_enable = 0;
2932         unsigned int q;
2933
2934         netif_dbg(priv, tx_err, dev, "bcmgenet_timeout\n");
2935
2936         for (q = 0; q < priv->hw_params->tx_queues; q++)
2937                 bcmgenet_dump_tx_queue(&priv->tx_rings[q]);
2938         bcmgenet_dump_tx_queue(&priv->tx_rings[DESC_INDEX]);
2939
2940         bcmgenet_tx_reclaim_all(dev);
2941
2942         for (q = 0; q < priv->hw_params->tx_queues; q++)
2943                 int1_enable |= (1 << q);
2944
2945         int0_enable = UMAC_IRQ_TXDMA_DONE;
2946
2947         /* Re-enable TX interrupts if disabled */
2948         bcmgenet_intrl2_0_writel(priv, int0_enable, INTRL2_CPU_MASK_CLEAR);
2949         bcmgenet_intrl2_1_writel(priv, int1_enable, INTRL2_CPU_MASK_CLEAR);
2950
2951         netif_trans_update(dev);
2952
2953         dev->stats.tx_errors++;
2954
2955         netif_tx_wake_all_queues(dev);
2956 }
2957
2958 #define MAX_MC_COUNT    16
2959
2960 static inline void bcmgenet_set_mdf_addr(struct bcmgenet_priv *priv,
2961                                          unsigned char *addr,
2962                                          int *i,
2963                                          int *mc)
2964 {
2965         u32 reg;
2966
2967         bcmgenet_umac_writel(priv, addr[0] << 8 | addr[1],
2968                              UMAC_MDF_ADDR + (*i * 4));
2969         bcmgenet_umac_writel(priv, addr[2] << 24 | addr[3] << 16 |
2970                              addr[4] << 8 | addr[5],
2971                              UMAC_MDF_ADDR + ((*i + 1) * 4));
2972         reg = bcmgenet_umac_readl(priv, UMAC_MDF_CTRL);
2973         reg |= (1 << (MAX_MC_COUNT - *mc));
2974         bcmgenet_umac_writel(priv, reg, UMAC_MDF_CTRL);
2975         *i += 2;
2976         (*mc)++;
2977 }
2978
2979 static void bcmgenet_set_rx_mode(struct net_device *dev)
2980 {
2981         struct bcmgenet_priv *priv = netdev_priv(dev);
2982         struct netdev_hw_addr *ha;
2983         int i, mc;
2984         u32 reg;
2985
2986         netif_dbg(priv, hw, dev, "%s: %08X\n", __func__, dev->flags);
2987
2988         /* Promiscuous mode */
2989         reg = bcmgenet_umac_readl(priv, UMAC_CMD);
2990         if (dev->flags & IFF_PROMISC) {
2991                 reg |= CMD_PROMISC;
2992                 bcmgenet_umac_writel(priv, reg, UMAC_CMD);
2993                 bcmgenet_umac_writel(priv, 0, UMAC_MDF_CTRL);
2994                 return;
2995         } else {
2996                 reg &= ~CMD_PROMISC;
2997                 bcmgenet_umac_writel(priv, reg, UMAC_CMD);
2998         }
2999
3000         /* UniMac doesn't support ALLMULTI */
3001         if (dev->flags & IFF_ALLMULTI) {
3002                 netdev_warn(dev, "ALLMULTI is not supported\n");
3003                 return;
3004         }
3005
3006         /* update MDF filter */
3007         i = 0;
3008         mc = 0;
3009         /* Broadcast */
3010         bcmgenet_set_mdf_addr(priv, dev->broadcast, &i, &mc);
3011         /* my own address.*/
3012         bcmgenet_set_mdf_addr(priv, dev->dev_addr, &i, &mc);
3013         /* Unicast list*/
3014         if (netdev_uc_count(dev) > (MAX_MC_COUNT - mc))
3015                 return;
3016
3017         if (!netdev_uc_empty(dev))
3018                 netdev_for_each_uc_addr(ha, dev)
3019                         bcmgenet_set_mdf_addr(priv, ha->addr, &i, &mc);
3020         /* Multicast */
3021         if (netdev_mc_empty(dev) || netdev_mc_count(dev) >= (MAX_MC_COUNT - mc))
3022                 return;
3023
3024         netdev_for_each_mc_addr(ha, dev)
3025                 bcmgenet_set_mdf_addr(priv, ha->addr, &i, &mc);
3026 }
3027
3028 /* Set the hardware MAC address. */
3029 static int bcmgenet_set_mac_addr(struct net_device *dev, void *p)
3030 {
3031         struct sockaddr *addr = p;
3032
3033         /* Setting the MAC address at the hardware level is not possible
3034          * without disabling the UniMAC RX/TX enable bits.
3035          */
3036         if (netif_running(dev))
3037                 return -EBUSY;
3038
3039         ether_addr_copy(dev->dev_addr, addr->sa_data);
3040
3041         return 0;
3042 }
3043
3044 static const struct net_device_ops bcmgenet_netdev_ops = {
3045         .ndo_open               = bcmgenet_open,
3046         .ndo_stop               = bcmgenet_close,
3047         .ndo_start_xmit         = bcmgenet_xmit,
3048         .ndo_tx_timeout         = bcmgenet_timeout,
3049         .ndo_set_rx_mode        = bcmgenet_set_rx_mode,
3050         .ndo_set_mac_address    = bcmgenet_set_mac_addr,
3051         .ndo_do_ioctl           = bcmgenet_ioctl,
3052         .ndo_set_features       = bcmgenet_set_features,
3053 #ifdef CONFIG_NET_POLL_CONTROLLER
3054         .ndo_poll_controller    = bcmgenet_poll_controller,
3055 #endif
3056 };
3057
3058 /* Array of GENET hardware parameters/characteristics */
3059 static struct bcmgenet_hw_params bcmgenet_hw_params[] = {
3060         [GENET_V1] = {
3061                 .tx_queues = 0,
3062                 .tx_bds_per_q = 0,
3063                 .rx_queues = 0,
3064                 .rx_bds_per_q = 0,
3065                 .bp_in_en_shift = 16,
3066                 .bp_in_mask = 0xffff,
3067                 .hfb_filter_cnt = 16,
3068                 .qtag_mask = 0x1F,
3069                 .hfb_offset = 0x1000,
3070                 .rdma_offset = 0x2000,
3071                 .tdma_offset = 0x3000,
3072                 .words_per_bd = 2,
3073         },
3074         [GENET_V2] = {
3075                 .tx_queues = 4,
3076                 .tx_bds_per_q = 32,
3077                 .rx_queues = 0,
3078                 .rx_bds_per_q = 0,
3079                 .bp_in_en_shift = 16,
3080                 .bp_in_mask = 0xffff,
3081                 .hfb_filter_cnt = 16,
3082                 .qtag_mask = 0x1F,
3083                 .tbuf_offset = 0x0600,
3084                 .hfb_offset = 0x1000,
3085                 .hfb_reg_offset = 0x2000,
3086                 .rdma_offset = 0x3000,
3087                 .tdma_offset = 0x4000,
3088                 .words_per_bd = 2,
3089                 .flags = GENET_HAS_EXT,
3090         },
3091         [GENET_V3] = {
3092                 .tx_queues = 4,
3093                 .tx_bds_per_q = 32,
3094                 .rx_queues = 0,
3095                 .rx_bds_per_q = 0,
3096                 .bp_in_en_shift = 17,
3097                 .bp_in_mask = 0x1ffff,
3098                 .hfb_filter_cnt = 48,
3099                 .hfb_filter_size = 128,
3100                 .qtag_mask = 0x3F,
3101                 .tbuf_offset = 0x0600,
3102                 .hfb_offset = 0x8000,
3103                 .hfb_reg_offset = 0xfc00,
3104                 .rdma_offset = 0x10000,
3105                 .tdma_offset = 0x11000,
3106                 .words_per_bd = 2,
3107                 .flags = GENET_HAS_EXT | GENET_HAS_MDIO_INTR |
3108                          GENET_HAS_MOCA_LINK_DET,
3109         },
3110         [GENET_V4] = {
3111                 .tx_queues = 4,
3112                 .tx_bds_per_q = 32,
3113                 .rx_queues = 0,
3114                 .rx_bds_per_q = 0,
3115                 .bp_in_en_shift = 17,
3116                 .bp_in_mask = 0x1ffff,
3117                 .hfb_filter_cnt = 48,
3118                 .hfb_filter_size = 128,
3119                 .qtag_mask = 0x3F,
3120                 .tbuf_offset = 0x0600,
3121                 .hfb_offset = 0x8000,
3122                 .hfb_reg_offset = 0xfc00,
3123                 .rdma_offset = 0x2000,
3124                 .tdma_offset = 0x4000,
3125                 .words_per_bd = 3,
3126                 .flags = GENET_HAS_40BITS | GENET_HAS_EXT |
3127                          GENET_HAS_MDIO_INTR | GENET_HAS_MOCA_LINK_DET,
3128         },
3129         [GENET_V5] = {
3130                 .tx_queues = 4,
3131                 .tx_bds_per_q = 32,
3132                 .rx_queues = 0,
3133                 .rx_bds_per_q = 0,
3134                 .bp_in_en_shift = 17,
3135                 .bp_in_mask = 0x1ffff,
3136                 .hfb_filter_cnt = 48,
3137                 .hfb_filter_size = 128,
3138                 .qtag_mask = 0x3F,
3139                 .tbuf_offset = 0x0600,
3140                 .hfb_offset = 0x8000,
3141                 .hfb_reg_offset = 0xfc00,
3142                 .rdma_offset = 0x2000,
3143                 .tdma_offset = 0x4000,
3144                 .words_per_bd = 3,
3145                 .flags = GENET_HAS_40BITS | GENET_HAS_EXT |
3146                          GENET_HAS_MDIO_INTR | GENET_HAS_MOCA_LINK_DET,
3147         },
3148 };
3149
3150 /* Infer hardware parameters from the detected GENET version */
3151 static void bcmgenet_set_hw_params(struct bcmgenet_priv *priv)
3152 {
3153         struct bcmgenet_hw_params *params;
3154         u32 reg;
3155         u8 major;
3156         u16 gphy_rev;
3157
3158         if (GENET_IS_V5(priv) || GENET_IS_V4(priv)) {
3159                 bcmgenet_dma_regs = bcmgenet_dma_regs_v3plus;
3160                 genet_dma_ring_regs = genet_dma_ring_regs_v4;
3161                 priv->dma_rx_chk_bit = DMA_RX_CHK_V3PLUS;
3162         } else if (GENET_IS_V3(priv)) {
3163                 bcmgenet_dma_regs = bcmgenet_dma_regs_v3plus;
3164                 genet_dma_ring_regs = genet_dma_ring_regs_v123;
3165                 priv->dma_rx_chk_bit = DMA_RX_CHK_V3PLUS;
3166         } else if (GENET_IS_V2(priv)) {
3167                 bcmgenet_dma_regs = bcmgenet_dma_regs_v2;
3168                 genet_dma_ring_regs = genet_dma_ring_regs_v123;
3169                 priv->dma_rx_chk_bit = DMA_RX_CHK_V12;
3170         } else if (GENET_IS_V1(priv)) {
3171                 bcmgenet_dma_regs = bcmgenet_dma_regs_v1;
3172                 genet_dma_ring_regs = genet_dma_ring_regs_v123;
3173                 priv->dma_rx_chk_bit = DMA_RX_CHK_V12;
3174         }
3175
3176         /* enum genet_version starts at 1 */
3177         priv->hw_params = &bcmgenet_hw_params[priv->version];
3178         params = priv->hw_params;
3179
3180         /* Read GENET HW version */
3181         reg = bcmgenet_sys_readl(priv, SYS_REV_CTRL);
3182         major = (reg >> 24 & 0x0f);
3183         if (major == 6)
3184                 major = 5;
3185         else if (major == 5)
3186                 major = 4;
3187         else if (major == 0)
3188                 major = 1;
3189         if (major != priv->version) {
3190                 dev_err(&priv->pdev->dev,
3191                         "GENET version mismatch, got: %d, configured for: %d\n",
3192                         major, priv->version);
3193         }
3194
3195         /* Print the GENET core version */
3196         dev_info(&priv->pdev->dev, "GENET " GENET_VER_FMT,
3197                  major, (reg >> 16) & 0x0f, reg & 0xffff);
3198
3199         /* Store the integrated PHY revision for the MDIO probing function
3200          * to pass this information to the PHY driver. The PHY driver expects
3201          * to find the PHY major revision in bits 15:8 while the GENET register
3202          * stores that information in bits 7:0, account for that.
3203          *
3204          * On newer chips, starting with PHY revision G0, a new scheme is
3205          * deployed similar to the Starfighter 2 switch with GPHY major
3206          * revision in bits 15:8 and patch level in bits 7:0. Major revision 0
3207          * is reserved as well as special value 0x01ff, we have a small
3208          * heuristic to check for the new GPHY revision and re-arrange things
3209          * so the GPHY driver is happy.
3210          */
3211         gphy_rev = reg & 0xffff;
3212
3213         if (GENET_IS_V5(priv)) {
3214                 /* The EPHY revision should come from the MDIO registers of
3215                  * the PHY not from GENET.
3216                  */
3217                 if (gphy_rev != 0) {
3218                         pr_warn("GENET is reporting EPHY revision: 0x%04x\n",
3219                                 gphy_rev);
3220                 }
3221         /* This is the good old scheme, just GPHY major, no minor nor patch */
3222         } else if ((gphy_rev & 0xf0) != 0) {
3223                 priv->gphy_rev = gphy_rev << 8;
3224         /* This is the new scheme, GPHY major rolls over with 0x10 = rev G0 */
3225         } else if ((gphy_rev & 0xff00) != 0) {
3226                 priv->gphy_rev = gphy_rev;
3227         /* This is reserved so should require special treatment */
3228         } else if (gphy_rev == 0 || gphy_rev == 0x01ff) {
3229                 pr_warn("Invalid GPHY revision detected: 0x%04x\n", gphy_rev);
3230                 return;
3231         }
3232
3233 #ifdef CONFIG_PHYS_ADDR_T_64BIT
3234         if (!(params->flags & GENET_HAS_40BITS))
3235                 pr_warn("GENET does not support 40-bits PA\n");
3236 #endif
3237
3238         pr_debug("Configuration for version: %d\n"
3239                 "TXq: %1d, TXqBDs: %1d, RXq: %1d, RXqBDs: %1d\n"
3240                 "BP << en: %2d, BP msk: 0x%05x\n"
3241                 "HFB count: %2d, QTAQ msk: 0x%05x\n"
3242                 "TBUF: 0x%04x, HFB: 0x%04x, HFBreg: 0x%04x\n"
3243                 "RDMA: 0x%05x, TDMA: 0x%05x\n"
3244                 "Words/BD: %d\n",
3245                 priv->version,
3246                 params->tx_queues, params->tx_bds_per_q,
3247                 params->rx_queues, params->rx_bds_per_q,
3248                 params->bp_in_en_shift, params->bp_in_mask,
3249                 params->hfb_filter_cnt, params->qtag_mask,
3250                 params->tbuf_offset, params->hfb_offset,
3251                 params->hfb_reg_offset,
3252                 params->rdma_offset, params->tdma_offset,
3253                 params->words_per_bd);
3254 }
3255
3256 static const struct of_device_id bcmgenet_match[] = {
3257         { .compatible = "brcm,genet-v1", .data = (void *)GENET_V1 },
3258         { .compatible = "brcm,genet-v2", .data = (void *)GENET_V2 },
3259         { .compatible = "brcm,genet-v3", .data = (void *)GENET_V3 },
3260         { .compatible = "brcm,genet-v4", .data = (void *)GENET_V4 },
3261         { .compatible = "brcm,genet-v5", .data = (void *)GENET_V5 },
3262         { },
3263 };
3264 MODULE_DEVICE_TABLE(of, bcmgenet_match);
3265
3266 static int bcmgenet_probe(struct platform_device *pdev)
3267 {
3268         struct bcmgenet_platform_data *pd = pdev->dev.platform_data;
3269         struct device_node *dn = pdev->dev.of_node;
3270         const struct of_device_id *of_id = NULL;
3271         struct bcmgenet_priv *priv;
3272         struct net_device *dev;
3273         const void *macaddr;
3274         struct resource *r;
3275         int err = -EIO;
3276
3277         /* Up to GENET_MAX_MQ_CNT + 1 TX queues and RX queues */
3278         dev = alloc_etherdev_mqs(sizeof(*priv), GENET_MAX_MQ_CNT + 1,
3279                                  GENET_MAX_MQ_CNT + 1);
3280         if (!dev) {
3281                 dev_err(&pdev->dev, "can't allocate net device\n");
3282                 return -ENOMEM;
3283         }
3284
3285         if (dn) {
3286                 of_id = of_match_node(bcmgenet_match, dn);
3287                 if (!of_id)
3288                         return -EINVAL;
3289         }
3290
3291         priv = netdev_priv(dev);
3292         priv->irq0 = platform_get_irq(pdev, 0);
3293         priv->irq1 = platform_get_irq(pdev, 1);
3294         priv->wol_irq = platform_get_irq(pdev, 2);
3295         if (!priv->irq0 || !priv->irq1) {
3296                 dev_err(&pdev->dev, "can't find IRQs\n");
3297                 err = -EINVAL;
3298                 goto err;
3299         }
3300
3301         if (dn) {
3302                 macaddr = of_get_mac_address(dn);
3303                 if (!macaddr) {
3304                         dev_err(&pdev->dev, "can't find MAC address\n");
3305                         err = -EINVAL;
3306                         goto err;
3307                 }
3308         } else {
3309                 macaddr = pd->mac_address;
3310         }
3311
3312         r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3313         priv->base = devm_ioremap_resource(&pdev->dev, r);
3314         if (IS_ERR(priv->base)) {
3315                 err = PTR_ERR(priv->base);
3316                 goto err;
3317         }
3318
3319         SET_NETDEV_DEV(dev, &pdev->dev);
3320         dev_set_drvdata(&pdev->dev, dev);
3321         ether_addr_copy(dev->dev_addr, macaddr);
3322         dev->watchdog_timeo = 2 * HZ;
3323         dev->ethtool_ops = &bcmgenet_ethtool_ops;
3324         dev->netdev_ops = &bcmgenet_netdev_ops;
3325
3326         priv->msg_enable = netif_msg_init(-1, GENET_MSG_DEFAULT);
3327
3328         /* Set hardware features */
3329         dev->hw_features |= NETIF_F_SG | NETIF_F_IP_CSUM |
3330                 NETIF_F_IPV6_CSUM | NETIF_F_RXCSUM;
3331
3332         /* Request the WOL interrupt and advertise suspend if available */
3333         priv->wol_irq_disabled = true;
3334         err = devm_request_irq(&pdev->dev, priv->wol_irq, bcmgenet_wol_isr, 0,
3335                                dev->name, priv);
3336         if (!err)
3337                 device_set_wakeup_capable(&pdev->dev, 1);
3338
3339         /* Set the needed headroom to account for any possible
3340          * features enabling/disabling at runtime
3341          */
3342         dev->needed_headroom += 64;
3343
3344         netdev_boot_setup_check(dev);
3345
3346         priv->dev = dev;
3347         priv->pdev = pdev;
3348         if (of_id)
3349                 priv->version = (enum bcmgenet_version)of_id->data;
3350         else
3351                 priv->version = pd->genet_version;
3352
3353         priv->clk = devm_clk_get(&priv->pdev->dev, "enet");
3354         if (IS_ERR(priv->clk)) {
3355                 dev_warn(&priv->pdev->dev, "failed to get enet clock\n");
3356                 priv->clk = NULL;
3357         }
3358
3359         clk_prepare_enable(priv->clk);
3360
3361         bcmgenet_set_hw_params(priv);
3362
3363         /* Mii wait queue */
3364         init_waitqueue_head(&priv->wq);
3365         /* Always use RX_BUF_LENGTH (2KB) buffer for all chips */
3366         priv->rx_buf_len = RX_BUF_LENGTH;
3367         INIT_WORK(&priv->bcmgenet_irq_work, bcmgenet_irq_task);
3368
3369         priv->clk_wol = devm_clk_get(&priv->pdev->dev, "enet-wol");
3370         if (IS_ERR(priv->clk_wol)) {
3371                 dev_warn(&priv->pdev->dev, "failed to get enet-wol clock\n");
3372                 priv->clk_wol = NULL;
3373         }
3374
3375         priv->clk_eee = devm_clk_get(&priv->pdev->dev, "enet-eee");
3376         if (IS_ERR(priv->clk_eee)) {
3377                 dev_warn(&priv->pdev->dev, "failed to get enet-eee clock\n");
3378                 priv->clk_eee = NULL;
3379         }
3380
3381         err = reset_umac(priv);
3382         if (err)
3383                 goto err_clk_disable;
3384
3385         err = bcmgenet_mii_init(dev);
3386         if (err)
3387                 goto err_clk_disable;
3388
3389         /* setup number of real queues  + 1 (GENET_V1 has 0 hardware queues
3390          * just the ring 16 descriptor based TX
3391          */
3392         netif_set_real_num_tx_queues(priv->dev, priv->hw_params->tx_queues + 1);
3393         netif_set_real_num_rx_queues(priv->dev, priv->hw_params->rx_queues + 1);
3394
3395         /* libphy will determine the link state */
3396         netif_carrier_off(dev);
3397
3398         /* Turn off the main clock, WOL clock is handled separately */
3399         clk_disable_unprepare(priv->clk);
3400
3401         err = register_netdev(dev);
3402         if (err)
3403                 goto err;
3404
3405         return err;
3406
3407 err_clk_disable:
3408         clk_disable_unprepare(priv->clk);
3409 err:
3410         free_netdev(dev);
3411         return err;
3412 }
3413
3414 static int bcmgenet_remove(struct platform_device *pdev)
3415 {
3416         struct bcmgenet_priv *priv = dev_to_priv(&pdev->dev);
3417
3418         dev_set_drvdata(&pdev->dev, NULL);
3419         unregister_netdev(priv->dev);
3420         bcmgenet_mii_exit(priv->dev);
3421         free_netdev(priv->dev);
3422
3423         return 0;
3424 }
3425
3426 #ifdef CONFIG_PM_SLEEP
3427 static int bcmgenet_suspend(struct device *d)
3428 {
3429         struct net_device *dev = dev_get_drvdata(d);
3430         struct bcmgenet_priv *priv = netdev_priv(dev);
3431         int ret;
3432
3433         if (!netif_running(dev))
3434                 return 0;
3435
3436         bcmgenet_netif_stop(dev);
3437
3438         phy_suspend(priv->phydev);
3439
3440         netif_device_detach(dev);
3441
3442         /* Disable MAC receive */
3443         umac_enable_set(priv, CMD_RX_EN, false);
3444
3445         ret = bcmgenet_dma_teardown(priv);
3446         if (ret)
3447                 return ret;
3448
3449         /* Disable MAC transmit. TX DMA disabled must be done before this */
3450         umac_enable_set(priv, CMD_TX_EN, false);
3451
3452         /* tx reclaim */
3453         bcmgenet_tx_reclaim_all(dev);
3454         bcmgenet_fini_dma(priv);
3455
3456         /* Prepare the device for Wake-on-LAN and switch to the slow clock */
3457         if (device_may_wakeup(d) && priv->wolopts) {
3458                 ret = bcmgenet_power_down(priv, GENET_POWER_WOL_MAGIC);
3459                 clk_prepare_enable(priv->clk_wol);
3460         } else if (priv->internal_phy) {
3461                 ret = bcmgenet_power_down(priv, GENET_POWER_PASSIVE);
3462         }
3463
3464         /* Turn off the clocks */
3465         clk_disable_unprepare(priv->clk);
3466
3467         return ret;
3468 }
3469
3470 static int bcmgenet_resume(struct device *d)
3471 {
3472         struct net_device *dev = dev_get_drvdata(d);
3473         struct bcmgenet_priv *priv = netdev_priv(dev);
3474         unsigned long dma_ctrl;
3475         int ret;
3476         u32 reg;
3477
3478         if (!netif_running(dev))
3479                 return 0;
3480
3481         /* Turn on the clock */
3482         ret = clk_prepare_enable(priv->clk);
3483         if (ret)
3484                 return ret;
3485
3486         /* If this is an internal GPHY, power it back on now, before UniMAC is
3487          * brought out of reset as absolutely no UniMAC activity is allowed
3488          */
3489         if (priv->internal_phy)
3490                 bcmgenet_power_up(priv, GENET_POWER_PASSIVE);
3491
3492         bcmgenet_umac_reset(priv);
3493
3494         ret = init_umac(priv);
3495         if (ret)
3496                 goto out_clk_disable;
3497
3498         /* From WOL-enabled suspend, switch to regular clock */
3499         if (priv->wolopts)
3500                 clk_disable_unprepare(priv->clk_wol);
3501
3502         phy_init_hw(priv->phydev);
3503         /* Speed settings must be restored */
3504         bcmgenet_mii_config(priv->dev);
3505
3506         /* disable ethernet MAC while updating its registers */
3507         umac_enable_set(priv, CMD_TX_EN | CMD_RX_EN, false);
3508
3509         bcmgenet_set_hw_addr(priv, dev->dev_addr);
3510
3511         if (priv->internal_phy) {
3512                 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
3513                 reg |= EXT_ENERGY_DET_MASK;
3514                 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
3515         }
3516
3517         if (priv->wolopts)
3518                 bcmgenet_power_up(priv, GENET_POWER_WOL_MAGIC);
3519
3520         /* Disable RX/TX DMA and flush TX queues */
3521         dma_ctrl = bcmgenet_dma_disable(priv);
3522
3523         /* Reinitialize TDMA and RDMA and SW housekeeping */
3524         ret = bcmgenet_init_dma(priv);
3525         if (ret) {
3526                 netdev_err(dev, "failed to initialize DMA\n");
3527                 goto out_clk_disable;
3528         }
3529
3530         /* Always enable ring 16 - descriptor ring */
3531         bcmgenet_enable_dma(priv, dma_ctrl);
3532
3533         netif_device_attach(dev);
3534
3535         phy_resume(priv->phydev);
3536
3537         if (priv->eee.eee_enabled)
3538                 bcmgenet_eee_enable_set(dev, true);
3539
3540         bcmgenet_netif_start(dev);
3541
3542         return 0;
3543
3544 out_clk_disable:
3545         clk_disable_unprepare(priv->clk);
3546         return ret;
3547 }
3548 #endif /* CONFIG_PM_SLEEP */
3549
3550 static SIMPLE_DEV_PM_OPS(bcmgenet_pm_ops, bcmgenet_suspend, bcmgenet_resume);
3551
3552 static struct platform_driver bcmgenet_driver = {
3553         .probe  = bcmgenet_probe,
3554         .remove = bcmgenet_remove,
3555         .driver = {
3556                 .name   = "bcmgenet",
3557                 .of_match_table = bcmgenet_match,
3558                 .pm     = &bcmgenet_pm_ops,
3559         },
3560 };
3561 module_platform_driver(bcmgenet_driver);
3562
3563 MODULE_AUTHOR("Broadcom Corporation");
3564 MODULE_DESCRIPTION("Broadcom GENET Ethernet controller driver");
3565 MODULE_ALIAS("platform:bcmgenet");
3566 MODULE_LICENSE("GPL");