drivers/net/ethernet/broadcom/genet/bcmgenet.c

   1 /*
   2  * Broadcom GENET (Gigabit Ethernet) controller driver
   3  *
   4  * Copyright (c) 2014 Broadcom Corporation
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  */
  10
  11 #define pr_fmt(fmt)                             "bcmgenet: " fmt
  12
  13 #include <linux/kernel.h>
  14 #include <linux/module.h>
  15 #include <linux/sched.h>
  16 #include <linux/types.h>
  17 #include <linux/fcntl.h>
  18 #include <linux/interrupt.h>
  19 #include <linux/string.h>
  20 #include <linux/if_ether.h>
  21 #include <linux/init.h>
  22 #include <linux/errno.h>
  23 #include <linux/delay.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/dma-mapping.h>
  26 #include <linux/pm.h>
  27 #include <linux/clk.h>
  28 #include <linux/of.h>
  29 #include <linux/of_address.h>
  30 #include <linux/of_irq.h>
  31 #include <linux/of_net.h>
  32 #include <linux/of_platform.h>
  33 #include <net/arp.h>
  34
  35 #include <linux/mii.h>
  36 #include <linux/ethtool.h>
  37 #include <linux/netdevice.h>
  38 #include <linux/inetdevice.h>
  39 #include <linux/etherdevice.h>
  40 #include <linux/skbuff.h>
  41 #include <linux/in.h>
  42 #include <linux/ip.h>
  43 #include <linux/ipv6.h>
  44 #include <linux/phy.h>
  45
  46 #include <asm/unaligned.h>
  47
  48 #include "bcmgenet.h"
  49
  50 /* Maximum number of hardware queues, downsized if needed */
  51 #define GENET_MAX_MQ_CNT        4
  52
  53 /* Default highest priority queue for multi queue support */
  54 #define GENET_Q0_PRIORITY       0
  55
  56 #define GENET_DEFAULT_BD_CNT    \
  57         (TOTAL_DESC - priv->hw_params->tx_queues * priv->hw_params->bds_cnt)
  58
  59 #define RX_BUF_LENGTH           2048
  60 #define SKB_ALIGNMENT           32
  61
  62 /* Tx/Rx DMA register offset, skip 256 descriptors */
  63 #define WORDS_PER_BD(p)         (p->hw_params->words_per_bd)
  64 #define DMA_DESC_SIZE           (WORDS_PER_BD(priv) * sizeof(u32))
  65
  66 #define GENET_TDMA_REG_OFF      (priv->hw_params->tdma_offset + \
  67                                 TOTAL_DESC * DMA_DESC_SIZE)
  68
  69 #define GENET_RDMA_REG_OFF      (priv->hw_params->rdma_offset + \
  70                                 TOTAL_DESC * DMA_DESC_SIZE)
  71
  72 static inline void dmadesc_set_length_status(struct bcmgenet_priv *priv,
  73                                              void __iomem *d, u32 value)
  74 {
  75         __raw_writel(value, d + DMA_DESC_LENGTH_STATUS);
  76 }
  77
  78 static inline u32 dmadesc_get_length_status(struct bcmgenet_priv *priv,
  79                                             void __iomem *d)
  80 {
  81         return __raw_readl(d + DMA_DESC_LENGTH_STATUS);
  82 }
  83
  84 static inline void dmadesc_set_addr(struct bcmgenet_priv *priv,
  85                                     void __iomem *d,
  86                                     dma_addr_t addr)
  87 {
  88         __raw_writel(lower_32_bits(addr), d + DMA_DESC_ADDRESS_LO);
  89
  90         /* Register writes to GISB bus can take couple hundred nanoseconds
  91          * and are done for each packet, save these expensive writes unless
  92          * the platform is explicitely configured for 64-bits/LPAE.
  93          */
  94 #ifdef CONFIG_PHYS_ADDR_T_64BIT
  95         if (priv->hw_params->flags & GENET_HAS_40BITS)
  96                 __raw_writel(upper_32_bits(addr), d + DMA_DESC_ADDRESS_HI);
  97 #endif
  98 }
  99
 100 /* Combined address + length/status setter */
 101 static inline void dmadesc_set(struct bcmgenet_priv *priv,
 102                                void __iomem *d, dma_addr_t addr, u32 val)
 103 {
 104         dmadesc_set_length_status(priv, d, val);
 105         dmadesc_set_addr(priv, d, addr);
 106 }
 107
 108 static inline dma_addr_t dmadesc_get_addr(struct bcmgenet_priv *priv,
 109                                           void __iomem *d)
 110 {
 111         dma_addr_t addr;
 112
 113         addr = __raw_readl(d + DMA_DESC_ADDRESS_LO);
 114
 115         /* Register writes to GISB bus can take couple hundred nanoseconds
 116          * and are done for each packet, save these expensive writes unless
 117          * the platform is explicitely configured for 64-bits/LPAE.
 118          */
 119 #ifdef CONFIG_PHYS_ADDR_T_64BIT
 120         if (priv->hw_params->flags & GENET_HAS_40BITS)
 121                 addr |= (u64)__raw_readl(d + DMA_DESC_ADDRESS_HI) << 32;
 122 #endif
 123         return addr;
 124 }
 125
 126 #define GENET_VER_FMT   "%1d.%1d EPHY: 0x%04x"
 127
 128 #define GENET_MSG_DEFAULT       (NETIF_MSG_DRV | NETIF_MSG_PROBE | \
 129                                 NETIF_MSG_LINK)
 130
 131 static inline u32 bcmgenet_rbuf_ctrl_get(struct bcmgenet_priv *priv)
 132 {
 133         if (GENET_IS_V1(priv))
 134                 return bcmgenet_rbuf_readl(priv, RBUF_FLUSH_CTRL_V1);
 135         else
 136                 return bcmgenet_sys_readl(priv, SYS_RBUF_FLUSH_CTRL);
 137 }
 138
 139 static inline void bcmgenet_rbuf_ctrl_set(struct bcmgenet_priv *priv, u32 val)
 140 {
 141         if (GENET_IS_V1(priv))
 142                 bcmgenet_rbuf_writel(priv, val, RBUF_FLUSH_CTRL_V1);
 143         else
 144                 bcmgenet_sys_writel(priv, val, SYS_RBUF_FLUSH_CTRL);
 145 }
 146
 147 /* These macros are defined to deal with register map change
 148  * between GENET1.1 and GENET2. Only those currently being used
 149  * by driver are defined.
 150  */
 151 static inline u32 bcmgenet_tbuf_ctrl_get(struct bcmgenet_priv *priv)
 152 {
 153         if (GENET_IS_V1(priv))
 154                 return bcmgenet_rbuf_readl(priv, TBUF_CTRL_V1);
 155         else
 156                 return __raw_readl(priv->base +
 157                                 priv->hw_params->tbuf_offset + TBUF_CTRL);
 158 }
 159
 160 static inline void bcmgenet_tbuf_ctrl_set(struct bcmgenet_priv *priv, u32 val)
 161 {
 162         if (GENET_IS_V1(priv))
 163                 bcmgenet_rbuf_writel(priv, val, TBUF_CTRL_V1);
 164         else
 165                 __raw_writel(val, priv->base +
 166                                 priv->hw_params->tbuf_offset + TBUF_CTRL);
 167 }
 168
 169 static inline u32 bcmgenet_bp_mc_get(struct bcmgenet_priv *priv)
 170 {
 171         if (GENET_IS_V1(priv))
 172                 return bcmgenet_rbuf_readl(priv, TBUF_BP_MC_V1);
 173         else
 174                 return __raw_readl(priv->base +
 175                                 priv->hw_params->tbuf_offset + TBUF_BP_MC);
 176 }
 177
 178 static inline void bcmgenet_bp_mc_set(struct bcmgenet_priv *priv, u32 val)
 179 {
 180         if (GENET_IS_V1(priv))
 181                 bcmgenet_rbuf_writel(priv, val, TBUF_BP_MC_V1);
 182         else
 183                 __raw_writel(val, priv->base +
 184                                 priv->hw_params->tbuf_offset + TBUF_BP_MC);
 185 }
 186
 187 /* RX/TX DMA register accessors */
 188 enum dma_reg {
 189         DMA_RING_CFG = 0,
 190         DMA_CTRL,
 191         DMA_STATUS,
 192         DMA_SCB_BURST_SIZE,
 193         DMA_ARB_CTRL,
 194         DMA_PRIORITY,
 195         DMA_RING_PRIORITY,
 196 };
 197
 198 static const u8 bcmgenet_dma_regs_v3plus[] = {
 199         [DMA_RING_CFG]          = 0x00,
 200         [DMA_CTRL]              = 0x04,
 201         [DMA_STATUS]            = 0x08,
 202         [DMA_SCB_BURST_SIZE]    = 0x0C,
 203         [DMA_ARB_CTRL]          = 0x2C,
 204         [DMA_PRIORITY]          = 0x30,
 205         [DMA_RING_PRIORITY]     = 0x38,
 206 };
 207
 208 static const u8 bcmgenet_dma_regs_v2[] = {
 209         [DMA_RING_CFG]          = 0x00,
 210         [DMA_CTRL]              = 0x04,
 211         [DMA_STATUS]            = 0x08,
 212         [DMA_SCB_BURST_SIZE]    = 0x0C,
 213         [DMA_ARB_CTRL]          = 0x30,
 214         [DMA_PRIORITY]          = 0x34,
 215         [DMA_RING_PRIORITY]     = 0x3C,
 216 };
 217
 218 static const u8 bcmgenet_dma_regs_v1[] = {
 219         [DMA_CTRL]              = 0x00,
 220         [DMA_STATUS]            = 0x04,
 221         [DMA_SCB_BURST_SIZE]    = 0x0C,
 222         [DMA_ARB_CTRL]          = 0x30,
 223         [DMA_PRIORITY]          = 0x34,
 224         [DMA_RING_PRIORITY]     = 0x3C,
 225 };
 226
 227 /* Set at runtime once bcmgenet version is known */
 228 static const u8 *bcmgenet_dma_regs;
 229
 230 static inline struct bcmgenet_priv *dev_to_priv(struct device *dev)
 231 {
 232         return netdev_priv(dev_get_drvdata(dev));
 233 }
 234
 235 static inline u32 bcmgenet_tdma_readl(struct bcmgenet_priv *priv,
 236                                       enum dma_reg r)
 237 {
 238         return __raw_readl(priv->base + GENET_TDMA_REG_OFF +
 239                         DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
 240 }
 241
 242 static inline void bcmgenet_tdma_writel(struct bcmgenet_priv *priv,
 243                                         u32 val, enum dma_reg r)
 244 {
 245         __raw_writel(val, priv->base + GENET_TDMA_REG_OFF +
 246                         DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
 247 }
 248
 249 static inline u32 bcmgenet_rdma_readl(struct bcmgenet_priv *priv,
 250                                       enum dma_reg r)
 251 {
 252         return __raw_readl(priv->base + GENET_RDMA_REG_OFF +
 253                         DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
 254 }
 255
 256 static inline void bcmgenet_rdma_writel(struct bcmgenet_priv *priv,
 257                                         u32 val, enum dma_reg r)
 258 {
 259         __raw_writel(val, priv->base + GENET_RDMA_REG_OFF +
 260                         DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
 261 }
 262
 263 /* RDMA/TDMA ring registers and accessors
 264  * we merge the common fields and just prefix with T/D the registers
 265  * having different meaning depending on the direction
 266  */
 267 enum dma_ring_reg {
 268         TDMA_READ_PTR = 0,
 269         RDMA_WRITE_PTR = TDMA_READ_PTR,
 270         TDMA_READ_PTR_HI,
 271         RDMA_WRITE_PTR_HI = TDMA_READ_PTR_HI,
 272         TDMA_CONS_INDEX,
 273         RDMA_PROD_INDEX = TDMA_CONS_INDEX,
 274         TDMA_PROD_INDEX,
 275         RDMA_CONS_INDEX = TDMA_PROD_INDEX,
 276         DMA_RING_BUF_SIZE,
 277         DMA_START_ADDR,
 278         DMA_START_ADDR_HI,
 279         DMA_END_ADDR,
 280         DMA_END_ADDR_HI,
 281         DMA_MBUF_DONE_THRESH,
 282         TDMA_FLOW_PERIOD,
 283         RDMA_XON_XOFF_THRESH = TDMA_FLOW_PERIOD,
 284         TDMA_WRITE_PTR,
 285         RDMA_READ_PTR = TDMA_WRITE_PTR,
 286         TDMA_WRITE_PTR_HI,
 287         RDMA_READ_PTR_HI = TDMA_WRITE_PTR_HI
 288 };
 289
 290 /* GENET v4 supports 40-bits pointer addressing
 291  * for obvious reasons the LO and HI word parts
 292  * are contiguous, but this offsets the other
 293  * registers.
 294  */
 295 static const u8 genet_dma_ring_regs_v4[] = {
 296         [TDMA_READ_PTR]                 = 0x00,
 297         [TDMA_READ_PTR_HI]              = 0x04,
 298         [TDMA_CONS_INDEX]               = 0x08,
 299         [TDMA_PROD_INDEX]               = 0x0C,
 300         [DMA_RING_BUF_SIZE]             = 0x10,
 301         [DMA_START_ADDR]                = 0x14,
 302         [DMA_START_ADDR_HI]             = 0x18,
 303         [DMA_END_ADDR]                  = 0x1C,
 304         [DMA_END_ADDR_HI]               = 0x20,
 305         [DMA_MBUF_DONE_THRESH]          = 0x24,
 306         [TDMA_FLOW_PERIOD]              = 0x28,
 307         [TDMA_WRITE_PTR]                = 0x2C,
 308         [TDMA_WRITE_PTR_HI]             = 0x30,
 309 };
 310
 311 static const u8 genet_dma_ring_regs_v123[] = {
 312         [TDMA_READ_PTR]                 = 0x00,
 313         [TDMA_CONS_INDEX]               = 0x04,
 314         [TDMA_PROD_INDEX]               = 0x08,
 315         [DMA_RING_BUF_SIZE]             = 0x0C,
 316         [DMA_START_ADDR]                = 0x10,
 317         [DMA_END_ADDR]                  = 0x14,
 318         [DMA_MBUF_DONE_THRESH]          = 0x18,
 319         [TDMA_FLOW_PERIOD]              = 0x1C,
 320         [TDMA_WRITE_PTR]                = 0x20,
 321 };
 322
 323 /* Set at runtime once GENET version is known */
 324 static const u8 *genet_dma_ring_regs;
 325
 326 static inline u32 bcmgenet_tdma_ring_readl(struct bcmgenet_priv *priv,
 327                                            unsigned int ring,
 328                                            enum dma_ring_reg r)
 329 {
 330         return __raw_readl(priv->base + GENET_TDMA_REG_OFF +
 331                         (DMA_RING_SIZE * ring) +
 332                         genet_dma_ring_regs[r]);
 333 }
 334
 335 static inline void bcmgenet_tdma_ring_writel(struct bcmgenet_priv *priv,
 336                                              unsigned int ring, u32 val,
 337                                              enum dma_ring_reg r)
 338 {
 339         __raw_writel(val, priv->base + GENET_TDMA_REG_OFF +
 340                         (DMA_RING_SIZE * ring) +
 341                         genet_dma_ring_regs[r]);
 342 }
 343
 344 static inline u32 bcmgenet_rdma_ring_readl(struct bcmgenet_priv *priv,
 345                                            unsigned int ring,
 346                                            enum dma_ring_reg r)
 347 {
 348         return __raw_readl(priv->base + GENET_RDMA_REG_OFF +
 349                         (DMA_RING_SIZE * ring) +
 350                         genet_dma_ring_regs[r]);
 351 }
 352
 353 static inline void bcmgenet_rdma_ring_writel(struct bcmgenet_priv *priv,
 354                                              unsigned int ring, u32 val,
 355                                              enum dma_ring_reg r)
 356 {
 357         __raw_writel(val, priv->base + GENET_RDMA_REG_OFF +
 358                         (DMA_RING_SIZE * ring) +
 359                         genet_dma_ring_regs[r]);
 360 }
 361
 362 static int bcmgenet_get_settings(struct net_device *dev,
 363                                  struct ethtool_cmd *cmd)
 364 {
 365         struct bcmgenet_priv *priv = netdev_priv(dev);
 366
 367         if (!netif_running(dev))
 368                 return -EINVAL;
 369
 370         if (!priv->phydev)
 371                 return -ENODEV;
 372
 373         return phy_ethtool_gset(priv->phydev, cmd);
 374 }
 375
 376 static int bcmgenet_set_settings(struct net_device *dev,
 377                                  struct ethtool_cmd *cmd)
 378 {
 379         struct bcmgenet_priv *priv = netdev_priv(dev);
 380
 381         if (!netif_running(dev))
 382                 return -EINVAL;
 383
 384         if (!priv->phydev)
 385                 return -ENODEV;
 386
 387         return phy_ethtool_sset(priv->phydev, cmd);
 388 }
 389
 390 static int bcmgenet_set_rx_csum(struct net_device *dev,
 391                                 netdev_features_t wanted)
 392 {
 393         struct bcmgenet_priv *priv = netdev_priv(dev);
 394         u32 rbuf_chk_ctrl;
 395         bool rx_csum_en;
 396
 397         rx_csum_en = !!(wanted & NETIF_F_RXCSUM);
 398
 399         rbuf_chk_ctrl = bcmgenet_rbuf_readl(priv, RBUF_CHK_CTRL);
 400
 401         /* enable rx checksumming */
 402         if (rx_csum_en)
 403                 rbuf_chk_ctrl |= RBUF_RXCHK_EN;
 404         else
 405                 rbuf_chk_ctrl &= ~RBUF_RXCHK_EN;
 406         priv->desc_rxchk_en = rx_csum_en;
 407
 408         /* If UniMAC forwards CRC, we need to skip over it to get
 409          * a valid CHK bit to be set in the per-packet status word
 410         */
 411         if (rx_csum_en && priv->crc_fwd_en)
 412                 rbuf_chk_ctrl |= RBUF_SKIP_FCS;
 413         else
 414                 rbuf_chk_ctrl &= ~RBUF_SKIP_FCS;
 415
 416         bcmgenet_rbuf_writel(priv, rbuf_chk_ctrl, RBUF_CHK_CTRL);
 417
 418         return 0;
 419 }
 420
 421 static int bcmgenet_set_tx_csum(struct net_device *dev,
 422                                 netdev_features_t wanted)
 423 {
 424         struct bcmgenet_priv *priv = netdev_priv(dev);
 425         bool desc_64b_en;
 426         u32 tbuf_ctrl, rbuf_ctrl;
 427
 428         tbuf_ctrl = bcmgenet_tbuf_ctrl_get(priv);
 429         rbuf_ctrl = bcmgenet_rbuf_readl(priv, RBUF_CTRL);
 430
 431         desc_64b_en = !!(wanted & (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM));
 432
 433         /* enable 64 bytes descriptor in both directions (RBUF and TBUF) */
 434         if (desc_64b_en) {
 435                 tbuf_ctrl |= RBUF_64B_EN;
 436                 rbuf_ctrl |= RBUF_64B_EN;
 437         } else {
 438                 tbuf_ctrl &= ~RBUF_64B_EN;
 439                 rbuf_ctrl &= ~RBUF_64B_EN;
 440         }
 441         priv->desc_64b_en = desc_64b_en;
 442
 443         bcmgenet_tbuf_ctrl_set(priv, tbuf_ctrl);
 444         bcmgenet_rbuf_writel(priv, rbuf_ctrl, RBUF_CTRL);
 445
 446         return 0;
 447 }
 448
 449 static int bcmgenet_set_features(struct net_device *dev,
 450                                  netdev_features_t features)
 451 {
 452         netdev_features_t changed = features ^ dev->features;
 453         netdev_features_t wanted = dev->wanted_features;
 454         int ret = 0;
 455
 456         if (changed & (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM))
 457                 ret = bcmgenet_set_tx_csum(dev, wanted);
 458         if (changed & (NETIF_F_RXCSUM))
 459                 ret = bcmgenet_set_rx_csum(dev, wanted);
 460
 461         return ret;
 462 }
 463
 464 static u32 bcmgenet_get_msglevel(struct net_device *dev)
 465 {
 466         struct bcmgenet_priv *priv = netdev_priv(dev);
 467
 468         return priv->msg_enable;
 469 }
 470
 471 static void bcmgenet_set_msglevel(struct net_device *dev, u32 level)
 472 {
 473         struct bcmgenet_priv *priv = netdev_priv(dev);
 474
 475         priv->msg_enable = level;
 476 }
 477
 478 /* standard ethtool support functions. */
 479 enum bcmgenet_stat_type {
 480         BCMGENET_STAT_NETDEV = -1,
 481         BCMGENET_STAT_MIB_RX,
 482         BCMGENET_STAT_MIB_TX,
 483         BCMGENET_STAT_RUNT,
 484         BCMGENET_STAT_MISC,
 485 };
 486
 487 struct bcmgenet_stats {
 488         char stat_string[ETH_GSTRING_LEN];
 489         int stat_sizeof;
 490         int stat_offset;
 491         enum bcmgenet_stat_type type;
 492         /* reg offset from UMAC base for misc counters */
 493         u16 reg_offset;
 494 };
 495
 496 #define STAT_NETDEV(m) { \
 497         .stat_string = __stringify(m), \
 498         .stat_sizeof = sizeof(((struct net_device_stats *)0)->m), \
 499         .stat_offset = offsetof(struct net_device_stats, m), \
 500         .type = BCMGENET_STAT_NETDEV, \
 501 }
 502
 503 #define STAT_GENET_MIB(str, m, _type) { \
 504         .stat_string = str, \
 505         .stat_sizeof = sizeof(((struct bcmgenet_priv *)0)->m), \
 506         .stat_offset = offsetof(struct bcmgenet_priv, m), \
 507         .type = _type, \
 508 }
 509
 510 #define STAT_GENET_MIB_RX(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_MIB_RX)
 511 #define STAT_GENET_MIB_TX(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_MIB_TX)
 512 #define STAT_GENET_RUNT(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_RUNT)
 513
 514 #define STAT_GENET_MISC(str, m, offset) { \
 515         .stat_string = str, \
 516         .stat_sizeof = sizeof(((struct bcmgenet_priv *)0)->m), \
 517         .stat_offset = offsetof(struct bcmgenet_priv, m), \
 518         .type = BCMGENET_STAT_MISC, \
 519         .reg_offset = offset, \
 520 }
 521
 522
 523 /* There is a 0xC gap between the end of RX and beginning of TX stats and then
 524  * between the end of TX stats and the beginning of the RX RUNT
 525  */
 526 #define BCMGENET_STAT_OFFSET    0xc
 527
 528 /* Hardware counters must be kept in sync because the order/offset
 529  * is important here (order in structure declaration = order in hardware)
 530  */
 531 static const struct bcmgenet_stats bcmgenet_gstrings_stats[] = {
 532         /* general stats */
 533         STAT_NETDEV(rx_packets),
 534         STAT_NETDEV(tx_packets),
 535         STAT_NETDEV(rx_bytes),
 536         STAT_NETDEV(tx_bytes),
 537         STAT_NETDEV(rx_errors),
 538         STAT_NETDEV(tx_errors),
 539         STAT_NETDEV(rx_dropped),
 540         STAT_NETDEV(tx_dropped),
 541         STAT_NETDEV(multicast),
 542         /* UniMAC RSV counters */
 543         STAT_GENET_MIB_RX("rx_64_octets", mib.rx.pkt_cnt.cnt_64),
 544         STAT_GENET_MIB_RX("rx_65_127_oct", mib.rx.pkt_cnt.cnt_127),
 545         STAT_GENET_MIB_RX("rx_128_255_oct", mib.rx.pkt_cnt.cnt_255),
 546         STAT_GENET_MIB_RX("rx_256_511_oct", mib.rx.pkt_cnt.cnt_511),
 547         STAT_GENET_MIB_RX("rx_512_1023_oct", mib.rx.pkt_cnt.cnt_1023),
 548         STAT_GENET_MIB_RX("rx_1024_1518_oct", mib.rx.pkt_cnt.cnt_1518),
 549         STAT_GENET_MIB_RX("rx_vlan_1519_1522_oct", mib.rx.pkt_cnt.cnt_mgv),
 550         STAT_GENET_MIB_RX("rx_1522_2047_oct", mib.rx.pkt_cnt.cnt_2047),
 551         STAT_GENET_MIB_RX("rx_2048_4095_oct", mib.rx.pkt_cnt.cnt_4095),
 552         STAT_GENET_MIB_RX("rx_4096_9216_oct", mib.rx.pkt_cnt.cnt_9216),
 553         STAT_GENET_MIB_RX("rx_pkts", mib.rx.pkt),
 554         STAT_GENET_MIB_RX("rx_bytes", mib.rx.bytes),
 555         STAT_GENET_MIB_RX("rx_multicast", mib.rx.mca),
 556         STAT_GENET_MIB_RX("rx_broadcast", mib.rx.bca),
 557         STAT_GENET_MIB_RX("rx_fcs", mib.rx.fcs),
 558         STAT_GENET_MIB_RX("rx_control", mib.rx.cf),
 559         STAT_GENET_MIB_RX("rx_pause", mib.rx.pf),
 560         STAT_GENET_MIB_RX("rx_unknown", mib.rx.uo),
 561         STAT_GENET_MIB_RX("rx_align", mib.rx.aln),
 562         STAT_GENET_MIB_RX("rx_outrange", mib.rx.flr),
 563         STAT_GENET_MIB_RX("rx_code", mib.rx.cde),
 564         STAT_GENET_MIB_RX("rx_carrier", mib.rx.fcr),
 565         STAT_GENET_MIB_RX("rx_oversize", mib.rx.ovr),
 566         STAT_GENET_MIB_RX("rx_jabber", mib.rx.jbr),
 567         STAT_GENET_MIB_RX("rx_mtu_err", mib.rx.mtue),
 568         STAT_GENET_MIB_RX("rx_good_pkts", mib.rx.pok),
 569         STAT_GENET_MIB_RX("rx_unicast", mib.rx.uc),
 570         STAT_GENET_MIB_RX("rx_ppp", mib.rx.ppp),
 571         STAT_GENET_MIB_RX("rx_crc", mib.rx.rcrc),
 572         /* UniMAC TSV counters */
 573         STAT_GENET_MIB_TX("tx_64_octets", mib.tx.pkt_cnt.cnt_64),
 574         STAT_GENET_MIB_TX("tx_65_127_oct", mib.tx.pkt_cnt.cnt_127),
 575         STAT_GENET_MIB_TX("tx_128_255_oct", mib.tx.pkt_cnt.cnt_255),
 576         STAT_GENET_MIB_TX("tx_256_511_oct", mib.tx.pkt_cnt.cnt_511),
 577         STAT_GENET_MIB_TX("tx_512_1023_oct", mib.tx.pkt_cnt.cnt_1023),
 578         STAT_GENET_MIB_TX("tx_1024_1518_oct", mib.tx.pkt_cnt.cnt_1518),
 579         STAT_GENET_MIB_TX("tx_vlan_1519_1522_oct", mib.tx.pkt_cnt.cnt_mgv),
 580         STAT_GENET_MIB_TX("tx_1522_2047_oct", mib.tx.pkt_cnt.cnt_2047),
 581         STAT_GENET_MIB_TX("tx_2048_4095_oct", mib.tx.pkt_cnt.cnt_4095),
 582         STAT_GENET_MIB_TX("tx_4096_9216_oct", mib.tx.pkt_cnt.cnt_9216),
 583         STAT_GENET_MIB_TX("tx_pkts", mib.tx.pkts),
 584         STAT_GENET_MIB_TX("tx_multicast", mib.tx.mca),
 585         STAT_GENET_MIB_TX("tx_broadcast", mib.tx.bca),
 586         STAT_GENET_MIB_TX("tx_pause", mib.tx.pf),
 587         STAT_GENET_MIB_TX("tx_control", mib.tx.cf),
 588         STAT_GENET_MIB_TX("tx_fcs_err", mib.tx.fcs),
 589         STAT_GENET_MIB_TX("tx_oversize", mib.tx.ovr),
 590         STAT_GENET_MIB_TX("tx_defer", mib.tx.drf),
 591         STAT_GENET_MIB_TX("tx_excess_defer", mib.tx.edf),
 592         STAT_GENET_MIB_TX("tx_single_col", mib.tx.scl),
 593         STAT_GENET_MIB_TX("tx_multi_col", mib.tx.mcl),
 594         STAT_GENET_MIB_TX("tx_late_col", mib.tx.lcl),
 595         STAT_GENET_MIB_TX("tx_excess_col", mib.tx.ecl),
 596         STAT_GENET_MIB_TX("tx_frags", mib.tx.frg),
 597         STAT_GENET_MIB_TX("tx_total_col", mib.tx.ncl),
 598         STAT_GENET_MIB_TX("tx_jabber", mib.tx.jbr),
 599         STAT_GENET_MIB_TX("tx_bytes", mib.tx.bytes),
 600         STAT_GENET_MIB_TX("tx_good_pkts", mib.tx.pok),
 601         STAT_GENET_MIB_TX("tx_unicast", mib.tx.uc),
 602         /* UniMAC RUNT counters */
 603         STAT_GENET_RUNT("rx_runt_pkts", mib.rx_runt_cnt),
 604         STAT_GENET_RUNT("rx_runt_valid_fcs", mib.rx_runt_fcs),
 605         STAT_GENET_RUNT("rx_runt_inval_fcs_align", mib.rx_runt_fcs_align),
 606         STAT_GENET_RUNT("rx_runt_bytes", mib.rx_runt_bytes),
 607         /* Misc UniMAC counters */
 608         STAT_GENET_MISC("rbuf_ovflow_cnt", mib.rbuf_ovflow_cnt,
 609                         UMAC_RBUF_OVFL_CNT),
 610         STAT_GENET_MISC("rbuf_err_cnt", mib.rbuf_err_cnt, UMAC_RBUF_ERR_CNT),
 611         STAT_GENET_MISC("mdf_err_cnt", mib.mdf_err_cnt, UMAC_MDF_ERR_CNT),
 612 };
 613
 614 #define BCMGENET_STATS_LEN      ARRAY_SIZE(bcmgenet_gstrings_stats)
 615
 616 static void bcmgenet_get_drvinfo(struct net_device *dev,
 617                                  struct ethtool_drvinfo *info)
 618 {
 619         strlcpy(info->driver, "bcmgenet", sizeof(info->driver));
 620         strlcpy(info->version, "v2.0", sizeof(info->version));
 621         info->n_stats = BCMGENET_STATS_LEN;
 622 }
 623
 624 static int bcmgenet_get_sset_count(struct net_device *dev, int string_set)
 625 {
 626         switch (string_set) {
 627         case ETH_SS_STATS:
 628                 return BCMGENET_STATS_LEN;
 629         default:
 630                 return -EOPNOTSUPP;
 631         }
 632 }
 633
 634 static void bcmgenet_get_strings(struct net_device *dev, u32 stringset,
 635                                  u8 *data)
 636 {
 637         int i;
 638
 639         switch (stringset) {
 640         case ETH_SS_STATS:
 641                 for (i = 0; i < BCMGENET_STATS_LEN; i++) {
 642                         memcpy(data + i * ETH_GSTRING_LEN,
 643                                bcmgenet_gstrings_stats[i].stat_string,
 644                                ETH_GSTRING_LEN);
 645                 }
 646                 break;
 647         }
 648 }
 649
 650 static void bcmgenet_update_mib_counters(struct bcmgenet_priv *priv)
 651 {
 652         int i, j = 0;
 653
 654         for (i = 0; i < BCMGENET_STATS_LEN; i++) {
 655                 const struct bcmgenet_stats *s;
 656                 u8 offset = 0;
 657                 u32 val = 0;
 658                 char *p;
 659
 660                 s = &bcmgenet_gstrings_stats[i];
 661                 switch (s->type) {
 662                 case BCMGENET_STAT_NETDEV:
 663                         continue;
 664                 case BCMGENET_STAT_MIB_RX:
 665                 case BCMGENET_STAT_MIB_TX:
 666                 case BCMGENET_STAT_RUNT:
 667                         if (s->type != BCMGENET_STAT_MIB_RX)
 668                                 offset = BCMGENET_STAT_OFFSET;
 669                         val = bcmgenet_umac_readl(priv,
 670                                                   UMAC_MIB_START + j + offset);
 671                         break;
 672                 case BCMGENET_STAT_MISC:
 673                         val = bcmgenet_umac_readl(priv, s->reg_offset);
 674                         /* clear if overflowed */
 675                         if (val == ~0)
 676                                 bcmgenet_umac_writel(priv, 0, s->reg_offset);
 677                         break;
 678                 }
 679
 680                 j += s->stat_sizeof;
 681                 p = (char *)priv + s->stat_offset;
 682                 *(u32 *)p = val;
 683         }
 684 }
 685
 686 static void bcmgenet_get_ethtool_stats(struct net_device *dev,
 687                                        struct ethtool_stats *stats,
 688                                        u64 *data)
 689 {
 690         struct bcmgenet_priv *priv = netdev_priv(dev);
 691         int i;
 692
 693         if (netif_running(dev))
 694                 bcmgenet_update_mib_counters(priv);
 695
 696         for (i = 0; i < BCMGENET_STATS_LEN; i++) {
 697                 const struct bcmgenet_stats *s;
 698                 char *p;
 699
 700                 s = &bcmgenet_gstrings_stats[i];
 701                 if (s->type == BCMGENET_STAT_NETDEV)
 702                         p = (char *)&dev->stats;
 703                 else
 704                         p = (char *)priv;
 705                 p += s->stat_offset;
 706                 data[i] = *(u32 *)p;
 707         }
 708 }
 709
 710 /* standard ethtool support functions. */
 711 static struct ethtool_ops bcmgenet_ethtool_ops = {
 712         .get_strings            = bcmgenet_get_strings,
 713         .get_sset_count         = bcmgenet_get_sset_count,
 714         .get_ethtool_stats      = bcmgenet_get_ethtool_stats,
 715         .get_settings           = bcmgenet_get_settings,
 716         .set_settings           = bcmgenet_set_settings,
 717         .get_drvinfo            = bcmgenet_get_drvinfo,
 718         .get_link               = ethtool_op_get_link,
 719         .get_msglevel           = bcmgenet_get_msglevel,
 720         .set_msglevel           = bcmgenet_set_msglevel,
 721         .get_wol                = bcmgenet_get_wol,
 722         .set_wol                = bcmgenet_set_wol,
 723 };
 724
 725 /* Power down the unimac, based on mode. */
 726 static void bcmgenet_power_down(struct bcmgenet_priv *priv,
 727                                 enum bcmgenet_power_mode mode)
 728 {
 729         u32 reg;
 730
 731         switch (mode) {
 732         case GENET_POWER_CABLE_SENSE:
 733                 phy_detach(priv->phydev);
 734                 break;
 735
 736         case GENET_POWER_WOL_MAGIC:
 737                 bcmgenet_wol_power_down_cfg(priv, mode);
 738                 break;
 739
 740         case GENET_POWER_PASSIVE:
 741                 /* Power down LED */
 742                 bcmgenet_mii_reset(priv->dev);
 743                 if (priv->hw_params->flags & GENET_HAS_EXT) {
 744                         reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
 745                         reg |= (EXT_PWR_DOWN_PHY |
 746                                 EXT_PWR_DOWN_DLL | EXT_PWR_DOWN_BIAS);
 747                         bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
 748                 }
 749                 break;
 750         default:
 751                 break;
 752         }
 753 }
 754
 755 static void bcmgenet_power_up(struct bcmgenet_priv *priv,
 756                               enum bcmgenet_power_mode mode)
 757 {
 758         u32 reg;
 759
 760         if (!(priv->hw_params->flags & GENET_HAS_EXT))
 761                 return;
 762
 763         reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
 764
 765         switch (mode) {
 766         case GENET_POWER_PASSIVE:
 767                 reg &= ~(EXT_PWR_DOWN_DLL | EXT_PWR_DOWN_PHY |
 768                                 EXT_PWR_DOWN_BIAS);
 769                 /* fallthrough */
 770         case GENET_POWER_CABLE_SENSE:
 771                 /* enable APD */
 772                 reg |= EXT_PWR_DN_EN_LD;
 773                 break;
 774         case GENET_POWER_WOL_MAGIC:
 775                 bcmgenet_wol_power_up_cfg(priv, mode);
 776                 return;
 777         default:
 778                 break;
 779         }
 780
 781         bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
 782         bcmgenet_mii_reset(priv->dev);
 783 }
 784
 785 /* ioctl handle special commands that are not present in ethtool. */
 786 static int bcmgenet_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
 787 {
 788         struct bcmgenet_priv *priv = netdev_priv(dev);
 789         int val = 0;
 790
 791         if (!netif_running(dev))
 792                 return -EINVAL;
 793
 794         switch (cmd) {
 795         case SIOCGMIIPHY:
 796         case SIOCGMIIREG:
 797         case SIOCSMIIREG:
 798                 if (!priv->phydev)
 799                         val = -ENODEV;
 800                 else
 801                         val = phy_mii_ioctl(priv->phydev, rq, cmd);
 802                 break;
 803
 804         default:
 805                 val = -EINVAL;
 806                 break;
 807         }
 808
 809         return val;
 810 }
 811
 812 static struct enet_cb *bcmgenet_get_txcb(struct bcmgenet_priv *priv,
 813                                          struct bcmgenet_tx_ring *ring)
 814 {
 815         struct enet_cb *tx_cb_ptr;
 816
 817         tx_cb_ptr = ring->cbs;
 818         tx_cb_ptr += ring->write_ptr - ring->cb_ptr;
 819         tx_cb_ptr->bd_addr = priv->tx_bds + ring->write_ptr * DMA_DESC_SIZE;
 820         /* Advancing local write pointer */
 821         if (ring->write_ptr == ring->end_ptr)
 822                 ring->write_ptr = ring->cb_ptr;
 823         else
 824                 ring->write_ptr++;
 825
 826         return tx_cb_ptr;
 827 }
 828
 829 /* Simple helper to free a control block's resources */
 830 static void bcmgenet_free_cb(struct enet_cb *cb)
 831 {
 832         dev_kfree_skb_any(cb->skb);
 833         cb->skb = NULL;
 834         dma_unmap_addr_set(cb, dma_addr, 0);
 835 }
 836
 837 static inline void bcmgenet_tx_ring16_int_disable(struct bcmgenet_priv *priv,
 838                                                   struct bcmgenet_tx_ring *ring)
 839 {
 840         bcmgenet_intrl2_0_writel(priv,
 841                                  UMAC_IRQ_TXDMA_BDONE | UMAC_IRQ_TXDMA_PDONE,
 842                                  INTRL2_CPU_MASK_SET);
 843 }
 844
 845 static inline void bcmgenet_tx_ring16_int_enable(struct bcmgenet_priv *priv,
 846                                                  struct bcmgenet_tx_ring *ring)
 847 {
 848         bcmgenet_intrl2_0_writel(priv,
 849                                  UMAC_IRQ_TXDMA_BDONE | UMAC_IRQ_TXDMA_PDONE,
 850                                  INTRL2_CPU_MASK_CLEAR);
 851 }
 852
 853 static inline void bcmgenet_tx_ring_int_enable(struct bcmgenet_priv *priv,
 854                                                struct bcmgenet_tx_ring *ring)
 855 {
 856         bcmgenet_intrl2_1_writel(priv, (1 << ring->index),
 857                                  INTRL2_CPU_MASK_CLEAR);
 858         priv->int1_mask &= ~(1 << ring->index);
 859 }
 860
 861 static inline void bcmgenet_tx_ring_int_disable(struct bcmgenet_priv *priv,
 862                                                 struct bcmgenet_tx_ring *ring)
 863 {
 864         bcmgenet_intrl2_1_writel(priv, (1 << ring->index),
 865                                  INTRL2_CPU_MASK_SET);
 866         priv->int1_mask |= (1 << ring->index);
 867 }
 868
 869 /* Unlocked version of the reclaim routine */
 870 static void __bcmgenet_tx_reclaim(struct net_device *dev,
 871                                   struct bcmgenet_tx_ring *ring)
 872 {
 873         struct bcmgenet_priv *priv = netdev_priv(dev);
 874         int last_tx_cn, last_c_index, num_tx_bds;
 875         struct enet_cb *tx_cb_ptr;
 876         struct netdev_queue *txq;
 877         unsigned int c_index;
 878
 879         /* Compute how many buffers are transmited since last xmit call */
 880         c_index = bcmgenet_tdma_ring_readl(priv, ring->index, TDMA_CONS_INDEX);
 881         txq = netdev_get_tx_queue(dev, ring->queue);
 882
 883         last_c_index = ring->c_index;
 884         num_tx_bds = ring->size;
 885
 886         c_index &= (num_tx_bds - 1);
 887
 888         if (c_index >= last_c_index)
 889                 last_tx_cn = c_index - last_c_index;
 890         else
 891                 last_tx_cn = num_tx_bds - last_c_index + c_index;
 892
 893         netif_dbg(priv, tx_done, dev,
 894                   "%s ring=%d index=%d last_tx_cn=%d last_index=%d\n",
 895                   __func__, ring->index,
 896                   c_index, last_tx_cn, last_c_index);
 897
 898         /* Reclaim transmitted buffers */
 899         while (last_tx_cn-- > 0) {
 900                 tx_cb_ptr = ring->cbs + last_c_index;
 901                 if (tx_cb_ptr->skb) {
 902                         dev->stats.tx_bytes += tx_cb_ptr->skb->len;
 903                         dma_unmap_single(&dev->dev,
 904                                          dma_unmap_addr(tx_cb_ptr, dma_addr),
 905                                          tx_cb_ptr->skb->len,
 906                                          DMA_TO_DEVICE);
 907                         bcmgenet_free_cb(tx_cb_ptr);
 908                 } else if (dma_unmap_addr(tx_cb_ptr, dma_addr)) {
 909                         dev->stats.tx_bytes +=
 910                                 dma_unmap_len(tx_cb_ptr, dma_len);
 911                         dma_unmap_page(&dev->dev,
 912                                        dma_unmap_addr(tx_cb_ptr, dma_addr),
 913                                        dma_unmap_len(tx_cb_ptr, dma_len),
 914                                        DMA_TO_DEVICE);
 915                         dma_unmap_addr_set(tx_cb_ptr, dma_addr, 0);
 916                 }
 917                 dev->stats.tx_packets++;
 918                 ring->free_bds += 1;
 919
 920                 last_c_index++;
 921                 last_c_index &= (num_tx_bds - 1);
 922         }
 923
 924         if (ring->free_bds > (MAX_SKB_FRAGS + 1))
 925                 ring->int_disable(priv, ring);
 926
 927         if (netif_tx_queue_stopped(txq))
 928                 netif_tx_wake_queue(txq);
 929
 930         ring->c_index = c_index;
 931 }
 932
 933 static void bcmgenet_tx_reclaim(struct net_device *dev,
 934                                 struct bcmgenet_tx_ring *ring)
 935 {
 936         unsigned long flags;
 937
 938         spin_lock_irqsave(&ring->lock, flags);
 939         __bcmgenet_tx_reclaim(dev, ring);
 940         spin_unlock_irqrestore(&ring->lock, flags);
 941 }
 942
 943 static void bcmgenet_tx_reclaim_all(struct net_device *dev)
 944 {
 945         struct bcmgenet_priv *priv = netdev_priv(dev);
 946         int i;
 947
 948         if (netif_is_multiqueue(dev)) {
 949                 for (i = 0; i < priv->hw_params->tx_queues; i++)
 950                         bcmgenet_tx_reclaim(dev, &priv->tx_rings[i]);
 951         }
 952
 953         bcmgenet_tx_reclaim(dev, &priv->tx_rings[DESC_INDEX]);
 954 }
 955
 956 /* Transmits a single SKB (either head of a fragment or a single SKB)
 957  * caller must hold priv->lock
 958  */
 959 static int bcmgenet_xmit_single(struct net_device *dev,
 960                                 struct sk_buff *skb,
 961                                 u16 dma_desc_flags,
 962                                 struct bcmgenet_tx_ring *ring)
 963 {
 964         struct bcmgenet_priv *priv = netdev_priv(dev);
 965         struct device *kdev = &priv->pdev->dev;
 966         struct enet_cb *tx_cb_ptr;
 967         unsigned int skb_len;
 968         dma_addr_t mapping;
 969         u32 length_status;
 970         int ret;
 971
 972         tx_cb_ptr = bcmgenet_get_txcb(priv, ring);
 973
 974         if (unlikely(!tx_cb_ptr))
 975                 BUG();
 976
 977         tx_cb_ptr->skb = skb;
 978
 979         skb_len = skb_headlen(skb) < ETH_ZLEN ? ETH_ZLEN : skb_headlen(skb);
 980
 981         mapping = dma_map_single(kdev, skb->data, skb_len, DMA_TO_DEVICE);
 982         ret = dma_mapping_error(kdev, mapping);
 983         if (ret) {
 984                 netif_err(priv, tx_err, dev, "Tx DMA map failed\n");
 985                 dev_kfree_skb(skb);
 986                 return ret;
 987         }
 988
 989         dma_unmap_addr_set(tx_cb_ptr, dma_addr, mapping);
 990         dma_unmap_len_set(tx_cb_ptr, dma_len, skb->len);
 991         length_status = (skb_len << DMA_BUFLENGTH_SHIFT) | dma_desc_flags |
 992                         (priv->hw_params->qtag_mask << DMA_TX_QTAG_SHIFT) |
 993                         DMA_TX_APPEND_CRC;
 994
 995         if (skb->ip_summed == CHECKSUM_PARTIAL)
 996                 length_status |= DMA_TX_DO_CSUM;
 997
 998         dmadesc_set(priv, tx_cb_ptr->bd_addr, mapping, length_status);
 999
1000         /* Decrement total BD count and advance our write pointer */
1001         ring->free_bds -= 1;
1002         ring->prod_index += 1;
1003         ring->prod_index &= DMA_P_INDEX_MASK;
1004
1005         return 0;
1006 }
1007
1008 /* Transmit a SKB fragement */
1009 static int bcmgenet_xmit_frag(struct net_device *dev,
1010                               skb_frag_t *frag,
1011                               u16 dma_desc_flags,
1012                               struct bcmgenet_tx_ring *ring)
1013 {
1014         struct bcmgenet_priv *priv = netdev_priv(dev);
1015         struct device *kdev = &priv->pdev->dev;
1016         struct enet_cb *tx_cb_ptr;
1017         dma_addr_t mapping;
1018         int ret;
1019
1020         tx_cb_ptr = bcmgenet_get_txcb(priv, ring);
1021
1022         if (unlikely(!tx_cb_ptr))
1023                 BUG();
1024         tx_cb_ptr->skb = NULL;
1025
1026         mapping = skb_frag_dma_map(kdev, frag, 0,
1027                                    skb_frag_size(frag), DMA_TO_DEVICE);
1028         ret = dma_mapping_error(kdev, mapping);
1029         if (ret) {
1030                 netif_err(priv, tx_err, dev, "%s: Tx DMA map failed\n",
1031                           __func__);
1032                 return ret;
1033         }
1034
1035         dma_unmap_addr_set(tx_cb_ptr, dma_addr, mapping);
1036         dma_unmap_len_set(tx_cb_ptr, dma_len, frag->size);
1037
1038         dmadesc_set(priv, tx_cb_ptr->bd_addr, mapping,
1039                     (frag->size << DMA_BUFLENGTH_SHIFT) | dma_desc_flags |
1040                     (priv->hw_params->qtag_mask << DMA_TX_QTAG_SHIFT));
1041
1042
1043         ring->free_bds -= 1;
1044         ring->prod_index += 1;
1045         ring->prod_index &= DMA_P_INDEX_MASK;
1046
1047         return 0;
1048 }
1049
1050 /* Reallocate the SKB to put enough headroom in front of it and insert
1051  * the transmit checksum offsets in the descriptors
1052  */
1053 static int bcmgenet_put_tx_csum(struct net_device *dev, struct sk_buff *skb)
1054 {
1055         struct status_64 *status = NULL;
1056         struct sk_buff *new_skb;
1057         u16 offset;
1058         u8 ip_proto;
1059         u16 ip_ver;
1060         u32 tx_csum_info;
1061
1062         if (unlikely(skb_headroom(skb) < sizeof(*status))) {
1063                 /* If 64 byte status block enabled, must make sure skb has
1064                  * enough headroom for us to insert 64B status block.
1065                  */
1066                 new_skb = skb_realloc_headroom(skb, sizeof(*status));
1067                 dev_kfree_skb(skb);
1068                 if (!new_skb) {
1069                         dev->stats.tx_errors++;
1070                         dev->stats.tx_dropped++;
1071                         return -ENOMEM;
1072                 }
1073                 skb = new_skb;
1074         }
1075
1076         skb_push(skb, sizeof(*status));
1077         status = (struct status_64 *)skb->data;
1078
1079         if (skb->ip_summed  == CHECKSUM_PARTIAL) {
1080                 ip_ver = htons(skb->protocol);
1081                 switch (ip_ver) {
1082                 case ETH_P_IP:
1083                         ip_proto = ip_hdr(skb)->protocol;
1084                         break;
1085                 case ETH_P_IPV6:
1086                         ip_proto = ipv6_hdr(skb)->nexthdr;
1087                         break;
1088                 default:
1089                         return 0;
1090                 }
1091
1092                 offset = skb_checksum_start_offset(skb) - sizeof(*status);
1093                 tx_csum_info = (offset << STATUS_TX_CSUM_START_SHIFT) |
1094                                 (offset + skb->csum_offset);
1095
1096                 /* Set the length valid bit for TCP and UDP and just set
1097                  * the special UDP flag for IPv4, else just set to 0.
1098                  */
1099                 if (ip_proto == IPPROTO_TCP || ip_proto == IPPROTO_UDP) {
1100                         tx_csum_info |= STATUS_TX_CSUM_LV;
1101                         if (ip_proto == IPPROTO_UDP && ip_ver == ETH_P_IP)
1102                                 tx_csum_info |= STATUS_TX_CSUM_PROTO_UDP;
1103                 } else {
1104                         tx_csum_info = 0;
1105                 }
1106
1107                 status->tx_csum_info = tx_csum_info;
1108         }
1109
1110         return 0;
1111 }
1112
1113 static netdev_tx_t bcmgenet_xmit(struct sk_buff *skb, struct net_device *dev)
1114 {
1115         struct bcmgenet_priv *priv = netdev_priv(dev);
1116         struct bcmgenet_tx_ring *ring = NULL;
1117         struct netdev_queue *txq;
1118         unsigned long flags = 0;
1119         int nr_frags, index;
1120         u16 dma_desc_flags;
1121         int ret;
1122         int i;
1123
1124         index = skb_get_queue_mapping(skb);
1125         /* Mapping strategy:
1126          * queue_mapping = 0, unclassified, packet xmited through ring16
1127          * queue_mapping = 1, goes to ring 0. (highest priority queue
1128          * queue_mapping = 2, goes to ring 1.
1129          * queue_mapping = 3, goes to ring 2.
1130          * queue_mapping = 4, goes to ring 3.
1131          */
1132         if (index == 0)
1133                 index = DESC_INDEX;
1134         else
1135                 index -= 1;
1136
1137         nr_frags = skb_shinfo(skb)->nr_frags;
1138         ring = &priv->tx_rings[index];
1139         txq = netdev_get_tx_queue(dev, ring->queue);
1140
1141         spin_lock_irqsave(&ring->lock, flags);
1142         if (ring->free_bds <= nr_frags + 1) {
1143                 netif_tx_stop_queue(txq);
1144                 netdev_err(dev, "%s: tx ring %d full when queue %d awake\n",
1145                            __func__, index, ring->queue);
1146                 ret = NETDEV_TX_BUSY;
1147                 goto out;
1148         }
1149
1150         if (skb_padto(skb, ETH_ZLEN)) {
1151                 ret = NETDEV_TX_OK;
1152                 goto out;
1153         }
1154
1155         /* set the SKB transmit checksum */
1156         if (priv->desc_64b_en) {
1157                 ret = bcmgenet_put_tx_csum(dev, skb);
1158                 if (ret) {
1159                         ret = NETDEV_TX_OK;
1160                         goto out;
1161                 }
1162         }
1163
1164         dma_desc_flags = DMA_SOP;
1165         if (nr_frags == 0)
1166                 dma_desc_flags |= DMA_EOP;
1167
1168         /* Transmit single SKB or head of fragment list */
1169         ret = bcmgenet_xmit_single(dev, skb, dma_desc_flags, ring);
1170         if (ret) {
1171                 ret = NETDEV_TX_OK;
1172                 goto out;
1173         }
1174
1175         /* xmit fragment */
1176         for (i = 0; i < nr_frags; i++) {
1177                 ret = bcmgenet_xmit_frag(dev,
1178                                          &skb_shinfo(skb)->frags[i],
1179                                          (i == nr_frags - 1) ? DMA_EOP : 0,
1180                                          ring);
1181                 if (ret) {
1182                         ret = NETDEV_TX_OK;
1183                         goto out;
1184                 }
1185         }
1186
1187         skb_tx_timestamp(skb);
1188
1189         /* we kept a software copy of how much we should advance the TDMA
1190          * producer index, now write it down to the hardware
1191          */
1192         bcmgenet_tdma_ring_writel(priv, ring->index,
1193                                   ring->prod_index, TDMA_PROD_INDEX);
1194
1195         if (ring->free_bds <= (MAX_SKB_FRAGS + 1)) {
1196                 netif_tx_stop_queue(txq);
1197                 ring->int_enable(priv, ring);
1198         }
1199
1200 out:
1201         spin_unlock_irqrestore(&ring->lock, flags);
1202
1203         return ret;
1204 }
1205
1206
1207 static int bcmgenet_rx_refill(struct bcmgenet_priv *priv, struct enet_cb *cb)
1208 {
1209         struct device *kdev = &priv->pdev->dev;
1210         struct sk_buff *skb;
1211         dma_addr_t mapping;
1212         int ret;
1213
1214         skb = netdev_alloc_skb(priv->dev, priv->rx_buf_len + SKB_ALIGNMENT);
1215         if (!skb)
1216                 return -ENOMEM;
1217
1218         /* a caller did not release this control block */
1219         WARN_ON(cb->skb != NULL);
1220         cb->skb = skb;
1221         mapping = dma_map_single(kdev, skb->data,
1222                                  priv->rx_buf_len, DMA_FROM_DEVICE);
1223         ret = dma_mapping_error(kdev, mapping);
1224         if (ret) {
1225                 bcmgenet_free_cb(cb);
1226                 netif_err(priv, rx_err, priv->dev,
1227                           "%s DMA map failed\n", __func__);
1228                 return ret;
1229         }
1230
1231         dma_unmap_addr_set(cb, dma_addr, mapping);
1232         /* assign packet, prepare descriptor, and advance pointer */
1233
1234         dmadesc_set_addr(priv, priv->rx_bd_assign_ptr, mapping);
1235
1236         /* turn on the newly assigned BD for DMA to use */
1237         priv->rx_bd_assign_index++;
1238         priv->rx_bd_assign_index &= (priv->num_rx_bds - 1);
1239
1240         priv->rx_bd_assign_ptr = priv->rx_bds +
1241                 (priv->rx_bd_assign_index * DMA_DESC_SIZE);
1242
1243         return 0;
1244 }
1245
1246 /* bcmgenet_desc_rx - descriptor based rx process.
1247  * this could be called from bottom half, or from NAPI polling method.
1248  */
1249 static unsigned int bcmgenet_desc_rx(struct bcmgenet_priv *priv,
1250                                      unsigned int budget)
1251 {
1252         struct net_device *dev = priv->dev;
1253         struct enet_cb *cb;
1254         struct sk_buff *skb;
1255         u32 dma_length_status;
1256         unsigned long dma_flag;
1257         int len, err;
1258         unsigned int rxpktprocessed = 0, rxpkttoprocess;
1259         unsigned int p_index;
1260         unsigned int chksum_ok = 0;
1261
1262         p_index = bcmgenet_rdma_ring_readl(priv, DESC_INDEX, RDMA_PROD_INDEX);
1263         p_index &= DMA_P_INDEX_MASK;
1264
1265         if (p_index < priv->rx_c_index)
1266                 rxpkttoprocess = (DMA_C_INDEX_MASK + 1) -
1267                         priv->rx_c_index + p_index;
1268         else
1269                 rxpkttoprocess = p_index - priv->rx_c_index;
1270
1271         netif_dbg(priv, rx_status, dev,
1272                   "RDMA: rxpkttoprocess=%d\n", rxpkttoprocess);
1273
1274         while ((rxpktprocessed < rxpkttoprocess) &&
1275                (rxpktprocessed < budget)) {
1276                 /* Unmap the packet contents such that we can use the
1277                  * RSV from the 64 bytes descriptor when enabled and save
1278                  * a 32-bits register read
1279                  */
1280                 cb = &priv->rx_cbs[priv->rx_read_ptr];
1281                 skb = cb->skb;
1282                 dma_unmap_single(&dev->dev, dma_unmap_addr(cb, dma_addr),
1283                                  priv->rx_buf_len, DMA_FROM_DEVICE);
1284
1285                 if (!priv->desc_64b_en) {
1286                         dma_length_status =
1287                                 dmadesc_get_length_status(priv,
1288                                                           priv->rx_bds +
1289                                                           (priv->rx_read_ptr *
1290                                                            DMA_DESC_SIZE));
1291                 } else {
1292                         struct status_64 *status;
1293
1294                         status = (struct status_64 *)skb->data;
1295                         dma_length_status = status->length_status;
1296                 }
1297
1298                 /* DMA flags and length are still valid no matter how
1299                  * we got the Receive Status Vector (64B RSB or register)
1300                  */
1301                 dma_flag = dma_length_status & 0xffff;
1302                 len = dma_length_status >> DMA_BUFLENGTH_SHIFT;
1303
1304                 netif_dbg(priv, rx_status, dev,
1305                           "%s:p_ind=%d c_ind=%d read_ptr=%d len_stat=0x%08x\n",
1306                           __func__, p_index, priv->rx_c_index,
1307                           priv->rx_read_ptr, dma_length_status);
1308
1309                 rxpktprocessed++;
1310
1311                 priv->rx_read_ptr++;
1312                 priv->rx_read_ptr &= (priv->num_rx_bds - 1);
1313
1314                 /* out of memory, just drop packets at the hardware level */
1315                 if (unlikely(!skb)) {
1316                         dev->stats.rx_dropped++;
1317                         dev->stats.rx_errors++;
1318                         goto refill;
1319                 }
1320
1321                 if (unlikely(!(dma_flag & DMA_EOP) || !(dma_flag & DMA_SOP))) {
1322                         netif_err(priv, rx_status, dev,
1323                                   "dropping fragmented packet!\n");
1324                         dev->stats.rx_dropped++;
1325                         dev->stats.rx_errors++;
1326                         dev_kfree_skb_any(cb->skb);
1327                         cb->skb = NULL;
1328                         goto refill;
1329                 }
1330                 /* report errors */
1331                 if (unlikely(dma_flag & (DMA_RX_CRC_ERROR |
1332                                                 DMA_RX_OV |
1333                                                 DMA_RX_NO |
1334                                                 DMA_RX_LG |
1335                                                 DMA_RX_RXER))) {
1336                         netif_err(priv, rx_status, dev, "dma_flag=0x%x\n",
1337                                   (unsigned int)dma_flag);
1338                         if (dma_flag & DMA_RX_CRC_ERROR)
1339                                 dev->stats.rx_crc_errors++;
1340                         if (dma_flag & DMA_RX_OV)
1341                                 dev->stats.rx_over_errors++;
1342                         if (dma_flag & DMA_RX_NO)
1343                                 dev->stats.rx_frame_errors++;
1344                         if (dma_flag & DMA_RX_LG)
1345                                 dev->stats.rx_length_errors++;
1346                         dev->stats.rx_dropped++;
1347                         dev->stats.rx_errors++;
1348
1349                         /* discard the packet and advance consumer index.*/
1350                         dev_kfree_skb_any(cb->skb);
1351                         cb->skb = NULL;
1352                         goto refill;
1353                 } /* error packet */
1354
1355                 chksum_ok = (dma_flag & priv->dma_rx_chk_bit) &&
1356                              priv->desc_rxchk_en;
1357
1358                 skb_put(skb, len);
1359                 if (priv->desc_64b_en) {
1360                         skb_pull(skb, 64);
1361                         len -= 64;
1362                 }
1363
1364                 if (likely(chksum_ok))
1365                         skb->ip_summed = CHECKSUM_UNNECESSARY;
1366
1367                 /* remove hardware 2bytes added for IP alignment */
1368                 skb_pull(skb, 2);
1369                 len -= 2;
1370
1371                 if (priv->crc_fwd_en) {
1372                         skb_trim(skb, len - ETH_FCS_LEN);
1373                         len -= ETH_FCS_LEN;
1374                 }
1375
1376                 /*Finish setting up the received SKB and send it to the kernel*/
1377                 skb->protocol = eth_type_trans(skb, priv->dev);
1378                 dev->stats.rx_packets++;
1379                 dev->stats.rx_bytes += len;
1380                 if (dma_flag & DMA_RX_MULT)
1381                         dev->stats.multicast++;
1382
1383                 /* Notify kernel */
1384                 napi_gro_receive(&priv->napi, skb);
1385                 cb->skb = NULL;
1386                 netif_dbg(priv, rx_status, dev, "pushed up to kernel\n");
1387
1388                 /* refill RX path on the current control block */
1389 refill:
1390                 err = bcmgenet_rx_refill(priv, cb);
1391                 if (err)
1392                         netif_err(priv, rx_err, dev, "Rx refill failed\n");
1393         }
1394
1395         return rxpktprocessed;
1396 }
1397
1398 /* Assign skb to RX DMA descriptor. */
1399 static int bcmgenet_alloc_rx_buffers(struct bcmgenet_priv *priv)
1400 {
1401         struct enet_cb *cb;
1402         int ret = 0;
1403         int i;
1404
1405         netif_dbg(priv, hw, priv->dev, "%s:\n", __func__);
1406
1407         /* loop here for each buffer needing assign */
1408         for (i = 0; i < priv->num_rx_bds; i++) {
1409                 cb = &priv->rx_cbs[priv->rx_bd_assign_index];
1410                 if (cb->skb)
1411                         continue;
1412
1413                 ret = bcmgenet_rx_refill(priv, cb);
1414                 if (ret)
1415                         break;
1416         }
1417
1418         return ret;
1419 }
1420
1421 static void bcmgenet_free_rx_buffers(struct bcmgenet_priv *priv)
1422 {
1423         struct enet_cb *cb;
1424         int i;
1425
1426         for (i = 0; i < priv->num_rx_bds; i++) {
1427                 cb = &priv->rx_cbs[i];
1428
1429                 if (dma_unmap_addr(cb, dma_addr)) {
1430                         dma_unmap_single(&priv->dev->dev,
1431                                          dma_unmap_addr(cb, dma_addr),
1432                                          priv->rx_buf_len, DMA_FROM_DEVICE);
1433                         dma_unmap_addr_set(cb, dma_addr, 0);
1434                 }
1435
1436                 if (cb->skb)
1437                         bcmgenet_free_cb(cb);
1438         }
1439 }
1440
1441 static void umac_enable_set(struct bcmgenet_priv *priv, u32 mask, bool enable)
1442 {
1443         u32 reg;
1444
1445         reg = bcmgenet_umac_readl(priv, UMAC_CMD);
1446         if (enable)
1447                 reg |= mask;
1448         else
1449                 reg &= ~mask;
1450         bcmgenet_umac_writel(priv, reg, UMAC_CMD);
1451
1452         /* UniMAC stops on a packet boundary, wait for a full-size packet
1453          * to be processed
1454          */
1455         if (enable == 0)
1456                 usleep_range(1000, 2000);
1457 }
1458
1459 static int reset_umac(struct bcmgenet_priv *priv)
1460 {
1461         struct device *kdev = &priv->pdev->dev;
1462         unsigned int timeout = 0;
1463         u32 reg;
1464
1465         /* 7358a0/7552a0: bad default in RBUF_FLUSH_CTRL.umac_sw_rst */
1466         bcmgenet_rbuf_ctrl_set(priv, 0);
1467         udelay(10);
1468
1469         /* disable MAC while updating its registers */
1470         bcmgenet_umac_writel(priv, 0, UMAC_CMD);
1471
1472         /* issue soft reset, wait for it to complete */
1473         bcmgenet_umac_writel(priv, CMD_SW_RESET, UMAC_CMD);
1474         while (timeout++ < 1000) {
1475                 reg = bcmgenet_umac_readl(priv, UMAC_CMD);
1476                 if (!(reg & CMD_SW_RESET))
1477                         return 0;
1478
1479                 udelay(1);
1480         }
1481
1482         if (timeout == 1000) {
1483                 dev_err(kdev,
1484                         "timeout waiting for MAC to come out of resetn\n");
1485                 return -ETIMEDOUT;
1486         }
1487
1488         return 0;
1489 }
1490
1491 static void bcmgenet_intr_disable(struct bcmgenet_priv *priv)
1492 {
1493         /* Mask all interrupts.*/
1494         bcmgenet_intrl2_0_writel(priv, 0xFFFFFFFF, INTRL2_CPU_MASK_SET);
1495         bcmgenet_intrl2_0_writel(priv, 0xFFFFFFFF, INTRL2_CPU_CLEAR);
1496         bcmgenet_intrl2_0_writel(priv, 0, INTRL2_CPU_MASK_CLEAR);
1497         bcmgenet_intrl2_1_writel(priv, 0xFFFFFFFF, INTRL2_CPU_MASK_SET);
1498         bcmgenet_intrl2_1_writel(priv, 0xFFFFFFFF, INTRL2_CPU_CLEAR);
1499         bcmgenet_intrl2_1_writel(priv, 0, INTRL2_CPU_MASK_CLEAR);
1500 }
1501
1502 static int init_umac(struct bcmgenet_priv *priv)
1503 {
1504         struct device *kdev = &priv->pdev->dev;
1505         int ret;
1506         u32 reg, cpu_mask_clear;
1507
1508         dev_dbg(&priv->pdev->dev, "bcmgenet: init_umac\n");
1509
1510         ret = reset_umac(priv);
1511         if (ret)
1512                 return ret;
1513
1514         bcmgenet_umac_writel(priv, 0, UMAC_CMD);
1515         /* clear tx/rx counter */
1516         bcmgenet_umac_writel(priv,
1517                              MIB_RESET_RX | MIB_RESET_TX | MIB_RESET_RUNT,
1518                              UMAC_MIB_CTRL);
1519         bcmgenet_umac_writel(priv, 0, UMAC_MIB_CTRL);
1520
1521         bcmgenet_umac_writel(priv, ENET_MAX_MTU_SIZE, UMAC_MAX_FRAME_LEN);
1522
1523         /* init rx registers, enable ip header optimization */
1524         reg = bcmgenet_rbuf_readl(priv, RBUF_CTRL);
1525         reg |= RBUF_ALIGN_2B;
1526         bcmgenet_rbuf_writel(priv, reg, RBUF_CTRL);
1527
1528         if (!GENET_IS_V1(priv) && !GENET_IS_V2(priv))
1529                 bcmgenet_rbuf_writel(priv, 1, RBUF_TBUF_SIZE_CTRL);
1530
1531         bcmgenet_intr_disable(priv);
1532
1533         cpu_mask_clear = UMAC_IRQ_RXDMA_BDONE;
1534
1535         dev_dbg(kdev, "%s:Enabling RXDMA_BDONE interrupt\n", __func__);
1536
1537         /* Monitor cable plug/unpluged event for internal PHY */
1538         if (phy_is_internal(priv->phydev)) {
1539                 cpu_mask_clear |= (UMAC_IRQ_LINK_DOWN | UMAC_IRQ_LINK_UP);
1540         } else if (priv->ext_phy) {
1541                 cpu_mask_clear |= (UMAC_IRQ_LINK_DOWN | UMAC_IRQ_LINK_UP);
1542         } else if (priv->phy_interface == PHY_INTERFACE_MODE_MOCA) {
1543                 reg = bcmgenet_bp_mc_get(priv);
1544                 reg |= BIT(priv->hw_params->bp_in_en_shift);
1545
1546                 /* bp_mask: back pressure mask */
1547                 if (netif_is_multiqueue(priv->dev))
1548                         reg |= priv->hw_params->bp_in_mask;
1549                 else
1550                         reg &= ~priv->hw_params->bp_in_mask;
1551                 bcmgenet_bp_mc_set(priv, reg);
1552         }
1553
1554         /* Enable MDIO interrupts on GENET v3+ */
1555         if (priv->hw_params->flags & GENET_HAS_MDIO_INTR)
1556                 cpu_mask_clear |= UMAC_IRQ_MDIO_DONE | UMAC_IRQ_MDIO_ERROR;
1557
1558         bcmgenet_intrl2_0_writel(priv, cpu_mask_clear, INTRL2_CPU_MASK_CLEAR);
1559
1560         /* Enable rx/tx engine.*/
1561         dev_dbg(kdev, "done init umac\n");
1562
1563         return 0;
1564 }
1565
1566 /* Initialize all house-keeping variables for a TX ring, along
1567  * with corresponding hardware registers
1568  */
1569 static void bcmgenet_init_tx_ring(struct bcmgenet_priv *priv,
1570                                   unsigned int index, unsigned int size,
1571                                   unsigned int write_ptr, unsigned int end_ptr)
1572 {
1573         struct bcmgenet_tx_ring *ring = &priv->tx_rings[index];
1574         u32 words_per_bd = WORDS_PER_BD(priv);
1575         u32 flow_period_val = 0;
1576         unsigned int first_bd;
1577
1578         spin_lock_init(&ring->lock);
1579         ring->index = index;
1580         if (index == DESC_INDEX) {
1581                 ring->queue = 0;
1582                 ring->int_enable = bcmgenet_tx_ring16_int_enable;
1583                 ring->int_disable = bcmgenet_tx_ring16_int_disable;
1584         } else {
1585                 ring->queue = index + 1;
1586                 ring->int_enable = bcmgenet_tx_ring_int_enable;
1587                 ring->int_disable = bcmgenet_tx_ring_int_disable;
1588         }
1589         ring->cbs = priv->tx_cbs + write_ptr;
1590         ring->size = size;
1591         ring->c_index = 0;
1592         ring->free_bds = size;
1593         ring->write_ptr = write_ptr;
1594         ring->cb_ptr = write_ptr;
1595         ring->end_ptr = end_ptr - 1;
1596         ring->prod_index = 0;
1597
1598         /* Set flow period for ring != 16 */
1599         if (index != DESC_INDEX)
1600                 flow_period_val = ENET_MAX_MTU_SIZE << 16;
1601
1602         bcmgenet_tdma_ring_writel(priv, index, 0, TDMA_PROD_INDEX);
1603         bcmgenet_tdma_ring_writel(priv, index, 0, TDMA_CONS_INDEX);
1604         bcmgenet_tdma_ring_writel(priv, index, 1, DMA_MBUF_DONE_THRESH);
1605         /* Disable rate control for now */
1606         bcmgenet_tdma_ring_writel(priv, index, flow_period_val,
1607                                   TDMA_FLOW_PERIOD);
1608         /* Unclassified traffic goes to ring 16 */
1609         bcmgenet_tdma_ring_writel(priv, index,
1610                                   ((size << DMA_RING_SIZE_SHIFT) |
1611                                    RX_BUF_LENGTH), DMA_RING_BUF_SIZE);
1612
1613         first_bd = write_ptr;
1614
1615         /* Set start and end address, read and write pointers */
1616         bcmgenet_tdma_ring_writel(priv, index, first_bd * words_per_bd,
1617                                   DMA_START_ADDR);
1618         bcmgenet_tdma_ring_writel(priv, index, first_bd * words_per_bd,
1619                                   TDMA_READ_PTR);
1620         bcmgenet_tdma_ring_writel(priv, index, first_bd,
1621                                   TDMA_WRITE_PTR);
1622         bcmgenet_tdma_ring_writel(priv, index, end_ptr * words_per_bd - 1,
1623                                   DMA_END_ADDR);
1624 }
1625
1626 /* Initialize a RDMA ring */
1627 static int bcmgenet_init_rx_ring(struct bcmgenet_priv *priv,
1628                                  unsigned int index, unsigned int size)
1629 {
1630         u32 words_per_bd = WORDS_PER_BD(priv);
1631         int ret;
1632
1633         priv->num_rx_bds = TOTAL_DESC;
1634         priv->rx_bds = priv->base + priv->hw_params->rdma_offset;
1635         priv->rx_bd_assign_ptr = priv->rx_bds;
1636         priv->rx_bd_assign_index = 0;
1637         priv->rx_c_index = 0;
1638         priv->rx_read_ptr = 0;
1639         priv->rx_cbs = kcalloc(priv->num_rx_bds, sizeof(struct enet_cb),
1640                                GFP_KERNEL);
1641         if (!priv->rx_cbs)
1642                 return -ENOMEM;
1643
1644         ret = bcmgenet_alloc_rx_buffers(priv);
1645         if (ret) {
1646                 kfree(priv->rx_cbs);
1647                 return ret;
1648         }
1649
1650         bcmgenet_rdma_ring_writel(priv, index, 0, RDMA_WRITE_PTR);
1651         bcmgenet_rdma_ring_writel(priv, index, 0, RDMA_PROD_INDEX);
1652         bcmgenet_rdma_ring_writel(priv, index, 0, RDMA_CONS_INDEX);
1653         bcmgenet_rdma_ring_writel(priv, index,
1654                                   ((size << DMA_RING_SIZE_SHIFT) |
1655                                    RX_BUF_LENGTH), DMA_RING_BUF_SIZE);
1656         bcmgenet_rdma_ring_writel(priv, index, 0, DMA_START_ADDR);
1657         bcmgenet_rdma_ring_writel(priv, index,
1658                                   words_per_bd * size - 1, DMA_END_ADDR);
1659         bcmgenet_rdma_ring_writel(priv, index,
1660                                   (DMA_FC_THRESH_LO <<
1661                                    DMA_XOFF_THRESHOLD_SHIFT) |
1662                                    DMA_FC_THRESH_HI, RDMA_XON_XOFF_THRESH);
1663         bcmgenet_rdma_ring_writel(priv, index, 0, RDMA_READ_PTR);
1664
1665         return ret;
1666 }
1667
1668 /* init multi xmit queues, only available for GENET2+
1669  * the queue is partitioned as follows:
1670  *
1671  * queue 0 - 3 is priority based, each one has 32 descriptors,
1672  * with queue 0 being the highest priority queue.
1673  *
1674  * queue 16 is the default tx queue with GENET_DEFAULT_BD_CNT
1675  * descriptors: 256 - (number of tx queues * bds per queues) = 128
1676  * descriptors.
1677  *
1678  * The transmit control block pool is then partitioned as following:
1679  * - tx_cbs[0...127] are for queue 16
1680  * - tx_ring_cbs[0] points to tx_cbs[128..159]
1681  * - tx_ring_cbs[1] points to tx_cbs[160..191]
1682  * - tx_ring_cbs[2] points to tx_cbs[192..223]
1683  * - tx_ring_cbs[3] points to tx_cbs[224..255]
1684  */
1685 static void bcmgenet_init_multiq(struct net_device *dev)
1686 {
1687         struct bcmgenet_priv *priv = netdev_priv(dev);
1688         unsigned int i, dma_enable;
1689         u32 reg, dma_ctrl, ring_cfg = 0, dma_priority = 0;
1690
1691         if (!netif_is_multiqueue(dev)) {
1692                 netdev_warn(dev, "called with non multi queue aware HW\n");
1693                 return;
1694         }
1695
1696         dma_ctrl = bcmgenet_tdma_readl(priv, DMA_CTRL);
1697         dma_enable = dma_ctrl & DMA_EN;
1698         dma_ctrl &= ~DMA_EN;
1699         bcmgenet_tdma_writel(priv, dma_ctrl, DMA_CTRL);
1700
1701         /* Enable strict priority arbiter mode */
1702         bcmgenet_tdma_writel(priv, DMA_ARBITER_SP, DMA_ARB_CTRL);
1703
1704         for (i = 0; i < priv->hw_params->tx_queues; i++) {
1705                 /* first 64 tx_cbs are reserved for default tx queue
1706                  * (ring 16)
1707                  */
1708                 bcmgenet_init_tx_ring(priv, i, priv->hw_params->bds_cnt,
1709                                       i * priv->hw_params->bds_cnt,
1710                                       (i + 1) * priv->hw_params->bds_cnt);
1711
1712                 /* Configure ring as decriptor ring and setup priority */
1713                 ring_cfg |= 1 << i;
1714                 dma_priority |= ((GENET_Q0_PRIORITY + i) <<
1715                                 (GENET_MAX_MQ_CNT + 1) * i);
1716                 dma_ctrl |= 1 << (i + DMA_RING_BUF_EN_SHIFT);
1717         }
1718
1719         /* Enable rings */
1720         reg = bcmgenet_tdma_readl(priv, DMA_RING_CFG);
1721         reg |= ring_cfg;
1722         bcmgenet_tdma_writel(priv, reg, DMA_RING_CFG);
1723
1724         /* Use configured rings priority and set ring #16 priority */
1725         reg = bcmgenet_tdma_readl(priv, DMA_RING_PRIORITY);
1726         reg |= ((GENET_Q0_PRIORITY + priv->hw_params->tx_queues) << 20);
1727         reg |= dma_priority;
1728         bcmgenet_tdma_writel(priv, reg, DMA_PRIORITY);
1729
1730         /* Configure ring as descriptor ring and re-enable DMA if enabled */
1731         reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
1732         reg |= dma_ctrl;
1733         if (dma_enable)
1734                 reg |= DMA_EN;
1735         bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
1736 }
1737
1738 static void bcmgenet_fini_dma(struct bcmgenet_priv *priv)
1739 {
1740         int i;
1741
1742         /* disable DMA */
1743         bcmgenet_rdma_writel(priv, 0, DMA_CTRL);
1744         bcmgenet_tdma_writel(priv, 0, DMA_CTRL);
1745
1746         for (i = 0; i < priv->num_tx_bds; i++) {
1747                 if (priv->tx_cbs[i].skb != NULL) {
1748                         dev_kfree_skb(priv->tx_cbs[i].skb);
1749                         priv->tx_cbs[i].skb = NULL;
1750                 }
1751         }
1752
1753         bcmgenet_free_rx_buffers(priv);
1754         kfree(priv->rx_cbs);
1755         kfree(priv->tx_cbs);
1756 }
1757
1758 /* init_edma: Initialize DMA control register */
1759 static int bcmgenet_init_dma(struct bcmgenet_priv *priv)
1760 {
1761         int ret;
1762
1763         netif_dbg(priv, hw, priv->dev, "bcmgenet: init_edma\n");
1764
1765         /* by default, enable ring 16 (descriptor based) */
1766         ret = bcmgenet_init_rx_ring(priv, DESC_INDEX, TOTAL_DESC);
1767         if (ret) {
1768                 netdev_err(priv->dev, "failed to initialize RX ring\n");
1769                 return ret;
1770         }
1771
1772         /* init rDma */
1773         bcmgenet_rdma_writel(priv, DMA_MAX_BURST_LENGTH, DMA_SCB_BURST_SIZE);
1774
1775         /* Init tDma */
1776         bcmgenet_tdma_writel(priv, DMA_MAX_BURST_LENGTH, DMA_SCB_BURST_SIZE);
1777
1778         /* Initialize commont TX ring structures */
1779         priv->tx_bds = priv->base + priv->hw_params->tdma_offset;
1780         priv->num_tx_bds = TOTAL_DESC;
1781         priv->tx_cbs = kcalloc(priv->num_tx_bds, sizeof(struct enet_cb),
1782                                GFP_KERNEL);
1783         if (!priv->tx_cbs) {
1784                 bcmgenet_fini_dma(priv);
1785                 return -ENOMEM;
1786         }
1787
1788         /* initialize multi xmit queue */
1789         bcmgenet_init_multiq(priv->dev);
1790
1791         /* initialize special ring 16 */
1792         bcmgenet_init_tx_ring(priv, DESC_INDEX, GENET_DEFAULT_BD_CNT,
1793                               priv->hw_params->tx_queues *
1794                               priv->hw_params->bds_cnt,
1795                               TOTAL_DESC);
1796
1797         return 0;
1798 }
1799
1800 /* NAPI polling method*/
1801 static int bcmgenet_poll(struct napi_struct *napi, int budget)
1802 {
1803         struct bcmgenet_priv *priv = container_of(napi,
1804                         struct bcmgenet_priv, napi);
1805         unsigned int work_done;
1806
1807         /* tx reclaim */
1808         bcmgenet_tx_reclaim(priv->dev, &priv->tx_rings[DESC_INDEX]);
1809
1810         work_done = bcmgenet_desc_rx(priv, budget);
1811
1812         /* Advancing our consumer index*/
1813         priv->rx_c_index += work_done;
1814         priv->rx_c_index &= DMA_C_INDEX_MASK;
1815         bcmgenet_rdma_ring_writel(priv, DESC_INDEX,
1816                                   priv->rx_c_index, RDMA_CONS_INDEX);
1817         if (work_done < budget) {
1818                 napi_complete(napi);
1819                 bcmgenet_intrl2_0_writel(priv, UMAC_IRQ_RXDMA_BDONE,
1820                                          INTRL2_CPU_MASK_CLEAR);
1821         }
1822
1823         return work_done;
1824 }
1825
1826 /* Interrupt bottom half */
1827 static void bcmgenet_irq_task(struct work_struct *work)
1828 {
1829         struct bcmgenet_priv *priv = container_of(
1830                         work, struct bcmgenet_priv, bcmgenet_irq_work);
1831
1832         netif_dbg(priv, intr, priv->dev, "%s\n", __func__);
1833
1834         if (priv->irq0_stat & UMAC_IRQ_MPD_R) {
1835                 priv->irq0_stat &= ~UMAC_IRQ_MPD_R;
1836                 netif_dbg(priv, wol, priv->dev,
1837                           "magic packet detected, waking up\n");
1838                 bcmgenet_power_up(priv, GENET_POWER_WOL_MAGIC);
1839         }
1840
1841         /* Link UP/DOWN event */
1842         if ((priv->hw_params->flags & GENET_HAS_MDIO_INTR) &&
1843             (priv->irq0_stat & (UMAC_IRQ_LINK_UP|UMAC_IRQ_LINK_DOWN))) {
1844                 phy_mac_interrupt(priv->phydev,
1845                                   priv->irq0_stat & UMAC_IRQ_LINK_UP);
1846                 priv->irq0_stat &= ~(UMAC_IRQ_LINK_UP|UMAC_IRQ_LINK_DOWN);
1847         }
1848 }
1849
1850 /* bcmgenet_isr1: interrupt handler for ring buffer. */
1851 static irqreturn_t bcmgenet_isr1(int irq, void *dev_id)
1852 {
1853         struct bcmgenet_priv *priv = dev_id;
1854         unsigned int index;
1855
1856         /* Save irq status for bottom-half processing. */
1857         priv->irq1_stat =
1858                 bcmgenet_intrl2_1_readl(priv, INTRL2_CPU_STAT) &
1859                 ~priv->int1_mask;
1860         /* clear inerrupts*/
1861         bcmgenet_intrl2_1_writel(priv, priv->irq1_stat, INTRL2_CPU_CLEAR);
1862
1863         netif_dbg(priv, intr, priv->dev,
1864                   "%s: IRQ=0x%x\n", __func__, priv->irq1_stat);
1865         /* Check the MBDONE interrupts.
1866          * packet is done, reclaim descriptors
1867          */
1868         if (priv->irq1_stat & 0x0000ffff) {
1869                 index = 0;
1870                 for (index = 0; index < 16; index++) {
1871                         if (priv->irq1_stat & (1 << index))
1872                                 bcmgenet_tx_reclaim(priv->dev,
1873                                                     &priv->tx_rings[index]);
1874                 }
1875         }
1876         return IRQ_HANDLED;
1877 }
1878
1879 /* bcmgenet_isr0: Handle various interrupts. */
1880 static irqreturn_t bcmgenet_isr0(int irq, void *dev_id)
1881 {
1882         struct bcmgenet_priv *priv = dev_id;
1883
1884         /* Save irq status for bottom-half processing. */
1885         priv->irq0_stat =
1886                 bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_STAT) &
1887                 ~bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_MASK_STATUS);
1888         /* clear inerrupts*/
1889         bcmgenet_intrl2_0_writel(priv, priv->irq0_stat, INTRL2_CPU_CLEAR);
1890
1891         netif_dbg(priv, intr, priv->dev,
1892                   "IRQ=0x%x\n", priv->irq0_stat);
1893
1894         if (priv->irq0_stat & (UMAC_IRQ_RXDMA_BDONE | UMAC_IRQ_RXDMA_PDONE)) {
1895                 /* We use NAPI(software interrupt throttling, if
1896                  * Rx Descriptor throttling is not used.
1897                  * Disable interrupt, will be enabled in the poll method.
1898                  */
1899                 if (likely(napi_schedule_prep(&priv->napi))) {
1900                         bcmgenet_intrl2_0_writel(priv, UMAC_IRQ_RXDMA_BDONE,
1901                                                  INTRL2_CPU_MASK_SET);
1902                         __napi_schedule(&priv->napi);
1903                 }
1904         }
1905         if (priv->irq0_stat &
1906                         (UMAC_IRQ_TXDMA_BDONE | UMAC_IRQ_TXDMA_PDONE)) {
1907                 /* Tx reclaim */
1908                 bcmgenet_tx_reclaim(priv->dev, &priv->tx_rings[DESC_INDEX]);
1909         }
1910         if (priv->irq0_stat & (UMAC_IRQ_PHY_DET_R |
1911                                 UMAC_IRQ_PHY_DET_F |
1912                                 UMAC_IRQ_LINK_UP |
1913                                 UMAC_IRQ_LINK_DOWN |
1914                                 UMAC_IRQ_HFB_SM |
1915                                 UMAC_IRQ_HFB_MM |
1916                                 UMAC_IRQ_MPD_R)) {
1917                 /* all other interested interrupts handled in bottom half */
1918                 schedule_work(&priv->bcmgenet_irq_work);
1919         }
1920
1921         if ((priv->hw_params->flags & GENET_HAS_MDIO_INTR) &&
1922             priv->irq0_stat & (UMAC_IRQ_MDIO_DONE | UMAC_IRQ_MDIO_ERROR)) {
1923                 priv->irq0_stat &= ~(UMAC_IRQ_MDIO_DONE | UMAC_IRQ_MDIO_ERROR);
1924                 wake_up(&priv->wq);
1925         }
1926
1927         return IRQ_HANDLED;
1928 }
1929
1930 static irqreturn_t bcmgenet_wol_isr(int irq, void *dev_id)
1931 {
1932         struct bcmgenet_priv *priv = dev_id;
1933
1934         pm_wakeup_event(&priv->pdev->dev, 0);
1935
1936         return IRQ_HANDLED;
1937 }
1938
1939 static void bcmgenet_umac_reset(struct bcmgenet_priv *priv)
1940 {
1941         u32 reg;
1942
1943         reg = bcmgenet_rbuf_ctrl_get(priv);
1944         reg |= BIT(1);
1945         bcmgenet_rbuf_ctrl_set(priv, reg);
1946         udelay(10);
1947
1948         reg &= ~BIT(1);
1949         bcmgenet_rbuf_ctrl_set(priv, reg);
1950         udelay(10);
1951 }
1952
1953 static void bcmgenet_set_hw_addr(struct bcmgenet_priv *priv,
1954                                  unsigned char *addr)
1955 {
1956         bcmgenet_umac_writel(priv, (addr[0] << 24) | (addr[1] << 16) |
1957                         (addr[2] << 8) | addr[3], UMAC_MAC0);
1958         bcmgenet_umac_writel(priv, (addr[4] << 8) | addr[5], UMAC_MAC1);
1959 }
1960
1961 static int bcmgenet_wol_resume(struct bcmgenet_priv *priv)
1962 {
1963         /* From WOL-enabled suspend, switch to regular clock */
1964         clk_disable_unprepare(priv->clk_wol);
1965
1966         phy_init_hw(priv->phydev);
1967         /* Speed settings must be restored */
1968         bcmgenet_mii_config(priv->dev);
1969
1970         return 0;
1971 }
1972
1973 /* Returns a reusable dma control register value */
1974 static u32 bcmgenet_dma_disable(struct bcmgenet_priv *priv)
1975 {
1976         u32 reg;
1977         u32 dma_ctrl;
1978
1979         /* disable DMA */
1980         dma_ctrl = 1 << (DESC_INDEX + DMA_RING_BUF_EN_SHIFT) | DMA_EN;
1981         reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
1982         reg &= ~dma_ctrl;
1983         bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
1984
1985         reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
1986         reg &= ~dma_ctrl;
1987         bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
1988
1989         bcmgenet_umac_writel(priv, 1, UMAC_TX_FLUSH);
1990         udelay(10);
1991         bcmgenet_umac_writel(priv, 0, UMAC_TX_FLUSH);
1992
1993         return dma_ctrl;
1994 }
1995
1996 static void bcmgenet_enable_dma(struct bcmgenet_priv *priv, u32 dma_ctrl)
1997 {
1998         u32 reg;
1999
2000         reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
2001         reg |= dma_ctrl;
2002         bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
2003
2004         reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
2005         reg |= dma_ctrl;
2006         bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
2007 }
2008
2009 static void bcmgenet_netif_start(struct net_device *dev)
2010 {
2011         struct bcmgenet_priv *priv = netdev_priv(dev);
2012
2013         /* Start the network engine */
2014         napi_enable(&priv->napi);
2015
2016         umac_enable_set(priv, CMD_TX_EN | CMD_RX_EN, true);
2017
2018         if (phy_is_internal(priv->phydev))
2019                 bcmgenet_power_up(priv, GENET_POWER_PASSIVE);
2020
2021         netif_tx_start_all_queues(dev);
2022
2023         phy_start(priv->phydev);
2024 }
2025
2026 static int bcmgenet_open(struct net_device *dev)
2027 {
2028         struct bcmgenet_priv *priv = netdev_priv(dev);
2029         unsigned long dma_ctrl;
2030         u32 reg;
2031         int ret;
2032
2033         netif_dbg(priv, ifup, dev, "bcmgenet_open\n");
2034
2035         /* Turn on the clock */
2036         if (!IS_ERR(priv->clk))
2037                 clk_prepare_enable(priv->clk);
2038
2039         /* take MAC out of reset */
2040         bcmgenet_umac_reset(priv);
2041
2042         ret = init_umac(priv);
2043         if (ret)
2044                 goto err_clk_disable;
2045
2046         /* disable ethernet MAC while updating its registers */
2047         umac_enable_set(priv, CMD_TX_EN | CMD_RX_EN, false);
2048
2049         /* Make sure we reflect the value of CRC_CMD_FWD */
2050         reg = bcmgenet_umac_readl(priv, UMAC_CMD);
2051         priv->crc_fwd_en = !!(reg & CMD_CRC_FWD);
2052
2053         bcmgenet_set_hw_addr(priv, dev->dev_addr);
2054
2055         if (phy_is_internal(priv->phydev)) {
2056                 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
2057                 reg |= EXT_ENERGY_DET_MASK;
2058                 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
2059         }
2060
2061         /* Disable RX/TX DMA and flush TX queues */
2062         dma_ctrl = bcmgenet_dma_disable(priv);
2063
2064         /* Reinitialize TDMA and RDMA and SW housekeeping */
2065         ret = bcmgenet_init_dma(priv);
2066         if (ret) {
2067                 netdev_err(dev, "failed to initialize DMA\n");
2068                 goto err_fini_dma;
2069         }
2070
2071         /* Always enable ring 16 - descriptor ring */
2072         bcmgenet_enable_dma(priv, dma_ctrl);
2073
2074         ret = request_irq(priv->irq0, bcmgenet_isr0, IRQF_SHARED,
2075                           dev->name, priv);
2076         if (ret < 0) {
2077                 netdev_err(dev, "can't request IRQ %d\n", priv->irq0);
2078                 goto err_fini_dma;
2079         }
2080
2081         ret = request_irq(priv->irq1, bcmgenet_isr1, IRQF_SHARED,
2082                           dev->name, priv);
2083         if (ret < 0) {
2084                 netdev_err(dev, "can't request IRQ %d\n", priv->irq1);
2085                 goto err_irq0;
2086         }
2087
2088         bcmgenet_netif_start(dev);
2089
2090         return 0;
2091
2092 err_irq0:
2093         free_irq(priv->irq0, dev);
2094 err_fini_dma:
2095         bcmgenet_fini_dma(priv);
2096 err_clk_disable:
2097         if (!IS_ERR(priv->clk))
2098                 clk_disable_unprepare(priv->clk);
2099         return ret;
2100 }
2101
2102 static int bcmgenet_dma_teardown(struct bcmgenet_priv *priv)
2103 {
2104         int ret = 0;
2105         int timeout = 0;
2106         u32 reg;
2107
2108         /* Disable TDMA to stop add more frames in TX DMA */
2109         reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
2110         reg &= ~DMA_EN;
2111         bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
2112
2113         /* Check TDMA status register to confirm TDMA is disabled */
2114         while (timeout++ < DMA_TIMEOUT_VAL) {
2115                 reg = bcmgenet_tdma_readl(priv, DMA_STATUS);
2116                 if (reg & DMA_DISABLED)
2117                         break;
2118
2119                 udelay(1);
2120         }
2121
2122         if (timeout == DMA_TIMEOUT_VAL) {
2123                 netdev_warn(priv->dev, "Timed out while disabling TX DMA\n");
2124                 ret = -ETIMEDOUT;
2125         }
2126
2127         /* Wait 10ms for packet drain in both tx and rx dma */
2128         usleep_range(10000, 20000);
2129
2130         /* Disable RDMA */
2131         reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
2132         reg &= ~DMA_EN;
2133         bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
2134
2135         timeout = 0;
2136         /* Check RDMA status register to confirm RDMA is disabled */
2137         while (timeout++ < DMA_TIMEOUT_VAL) {
2138                 reg = bcmgenet_rdma_readl(priv, DMA_STATUS);
2139                 if (reg & DMA_DISABLED)
2140                         break;
2141
2142                 udelay(1);
2143         }
2144
2145         if (timeout == DMA_TIMEOUT_VAL) {
2146                 netdev_warn(priv->dev, "Timed out while disabling RX DMA\n");
2147                 ret = -ETIMEDOUT;
2148         }
2149
2150         return ret;
2151 }
2152
2153 static void bcmgenet_netif_stop(struct net_device *dev)
2154 {
2155         struct bcmgenet_priv *priv = netdev_priv(dev);
2156
2157         netif_tx_stop_all_queues(dev);
2158         napi_disable(&priv->napi);
2159         phy_stop(priv->phydev);
2160
2161         bcmgenet_intr_disable(priv);
2162
2163         /* Wait for pending work items to complete. Since interrupts are
2164          * disabled no new work will be scheduled.
2165          */
2166         cancel_work_sync(&priv->bcmgenet_irq_work);
2167 }
2168
2169 static int bcmgenet_close(struct net_device *dev)
2170 {
2171         struct bcmgenet_priv *priv = netdev_priv(dev);
2172         int ret;
2173
2174         netif_dbg(priv, ifdown, dev, "bcmgenet_close\n");
2175
2176         bcmgenet_netif_stop(dev);
2177
2178         /* Disable MAC receive */
2179         umac_enable_set(priv, CMD_RX_EN, false);
2180
2181         ret = bcmgenet_dma_teardown(priv);
2182         if (ret)
2183                 return ret;
2184
2185         /* Disable MAC transmit. TX DMA disabled have to done before this */
2186         umac_enable_set(priv, CMD_TX_EN, false);
2187
2188         /* tx reclaim */
2189         bcmgenet_tx_reclaim_all(dev);
2190         bcmgenet_fini_dma(priv);
2191
2192         free_irq(priv->irq0, priv);
2193         free_irq(priv->irq1, priv);
2194
2195         if (phy_is_internal(priv->phydev))
2196                 bcmgenet_power_down(priv, GENET_POWER_PASSIVE);
2197
2198         if (!IS_ERR(priv->clk))
2199                 clk_disable_unprepare(priv->clk);
2200
2201         return 0;
2202 }
2203
2204 static void bcmgenet_timeout(struct net_device *dev)
2205 {
2206         struct bcmgenet_priv *priv = netdev_priv(dev);
2207
2208         netif_dbg(priv, tx_err, dev, "bcmgenet_timeout\n");
2209
2210         dev->trans_start = jiffies;
2211
2212         dev->stats.tx_errors++;
2213
2214         netif_tx_wake_all_queues(dev);
2215 }
2216
2217 #define MAX_MC_COUNT    16
2218
2219 static inline void bcmgenet_set_mdf_addr(struct bcmgenet_priv *priv,
2220                                          unsigned char *addr,
2221                                          int *i,
2222                                          int *mc)
2223 {
2224         u32 reg;
2225
2226         bcmgenet_umac_writel(priv, addr[0] << 8 | addr[1],
2227                              UMAC_MDF_ADDR + (*i * 4));
2228         bcmgenet_umac_writel(priv, addr[2] << 24 | addr[3] << 16 |
2229                              addr[4] << 8 | addr[5],
2230                              UMAC_MDF_ADDR + ((*i + 1) * 4));
2231         reg = bcmgenet_umac_readl(priv, UMAC_MDF_CTRL);
2232         reg |= (1 << (MAX_MC_COUNT - *mc));
2233         bcmgenet_umac_writel(priv, reg, UMAC_MDF_CTRL);
2234         *i += 2;
2235         (*mc)++;
2236 }
2237
2238 static void bcmgenet_set_rx_mode(struct net_device *dev)
2239 {
2240         struct bcmgenet_priv *priv = netdev_priv(dev);
2241         struct netdev_hw_addr *ha;
2242         int i, mc;
2243         u32 reg;
2244
2245         netif_dbg(priv, hw, dev, "%s: %08X\n", __func__, dev->flags);
2246
2247         /* Promiscous mode */
2248         reg = bcmgenet_umac_readl(priv, UMAC_CMD);
2249         if (dev->flags & IFF_PROMISC) {
2250                 reg |= CMD_PROMISC;
2251                 bcmgenet_umac_writel(priv, reg, UMAC_CMD);
2252                 bcmgenet_umac_writel(priv, 0, UMAC_MDF_CTRL);
2253                 return;
2254         } else {
2255                 reg &= ~CMD_PROMISC;
2256                 bcmgenet_umac_writel(priv, reg, UMAC_CMD);
2257         }
2258
2259         /* UniMac doesn't support ALLMULTI */
2260         if (dev->flags & IFF_ALLMULTI) {
2261                 netdev_warn(dev, "ALLMULTI is not supported\n");
2262                 return;
2263         }
2264
2265         /* update MDF filter */
2266         i = 0;
2267         mc = 0;
2268         /* Broadcast */
2269         bcmgenet_set_mdf_addr(priv, dev->broadcast, &i, &mc);
2270         /* my own address.*/
2271         bcmgenet_set_mdf_addr(priv, dev->dev_addr, &i, &mc);
2272         /* Unicast list*/
2273         if (netdev_uc_count(dev) > (MAX_MC_COUNT - mc))
2274                 return;
2275
2276         if (!netdev_uc_empty(dev))
2277                 netdev_for_each_uc_addr(ha, dev)
2278                         bcmgenet_set_mdf_addr(priv, ha->addr, &i, &mc);
2279         /* Multicast */
2280         if (netdev_mc_empty(dev) || netdev_mc_count(dev) >= (MAX_MC_COUNT - mc))
2281                 return;
2282
2283         netdev_for_each_mc_addr(ha, dev)
2284                 bcmgenet_set_mdf_addr(priv, ha->addr, &i, &mc);
2285 }
2286
2287 /* Set the hardware MAC address. */
2288 static int bcmgenet_set_mac_addr(struct net_device *dev, void *p)
2289 {
2290         struct sockaddr *addr = p;
2291
2292         /* Setting the MAC address at the hardware level is not possible
2293          * without disabling the UniMAC RX/TX enable bits.
2294          */
2295         if (netif_running(dev))
2296                 return -EBUSY;
2297
2298         ether_addr_copy(dev->dev_addr, addr->sa_data);
2299
2300         return 0;
2301 }
2302
2303 static const struct net_device_ops bcmgenet_netdev_ops = {
2304         .ndo_open               = bcmgenet_open,
2305         .ndo_stop               = bcmgenet_close,
2306         .ndo_start_xmit         = bcmgenet_xmit,
2307         .ndo_tx_timeout         = bcmgenet_timeout,
2308         .ndo_set_rx_mode        = bcmgenet_set_rx_mode,
2309         .ndo_set_mac_address    = bcmgenet_set_mac_addr,
2310         .ndo_do_ioctl           = bcmgenet_ioctl,
2311         .ndo_set_features       = bcmgenet_set_features,
2312 };
2313
2314 /* Array of GENET hardware parameters/characteristics */
2315 static struct bcmgenet_hw_params bcmgenet_hw_params[] = {
2316         [GENET_V1] = {
2317                 .tx_queues = 0,
2318                 .rx_queues = 0,
2319                 .bds_cnt = 0,
2320                 .bp_in_en_shift = 16,
2321                 .bp_in_mask = 0xffff,
2322                 .hfb_filter_cnt = 16,
2323                 .qtag_mask = 0x1F,
2324                 .hfb_offset = 0x1000,
2325                 .rdma_offset = 0x2000,
2326                 .tdma_offset = 0x3000,
2327                 .words_per_bd = 2,
2328         },
2329         [GENET_V2] = {
2330                 .tx_queues = 4,
2331                 .rx_queues = 4,
2332                 .bds_cnt = 32,
2333                 .bp_in_en_shift = 16,
2334                 .bp_in_mask = 0xffff,
2335                 .hfb_filter_cnt = 16,
2336                 .qtag_mask = 0x1F,
2337                 .tbuf_offset = 0x0600,
2338                 .hfb_offset = 0x1000,
2339                 .hfb_reg_offset = 0x2000,
2340                 .rdma_offset = 0x3000,
2341                 .tdma_offset = 0x4000,
2342                 .words_per_bd = 2,
2343                 .flags = GENET_HAS_EXT,
2344         },
2345         [GENET_V3] = {
2346                 .tx_queues = 4,
2347                 .rx_queues = 4,
2348                 .bds_cnt = 32,
2349                 .bp_in_en_shift = 17,
2350                 .bp_in_mask = 0x1ffff,
2351                 .hfb_filter_cnt = 48,
2352                 .qtag_mask = 0x3F,
2353                 .tbuf_offset = 0x0600,
2354                 .hfb_offset = 0x8000,
2355                 .hfb_reg_offset = 0xfc00,
2356                 .rdma_offset = 0x10000,
2357                 .tdma_offset = 0x11000,
2358                 .words_per_bd = 2,
2359                 .flags = GENET_HAS_EXT | GENET_HAS_MDIO_INTR,
2360         },
2361         [GENET_V4] = {
2362                 .tx_queues = 4,
2363                 .rx_queues = 4,
2364                 .bds_cnt = 32,
2365                 .bp_in_en_shift = 17,
2366                 .bp_in_mask = 0x1ffff,
2367                 .hfb_filter_cnt = 48,
2368                 .qtag_mask = 0x3F,
2369                 .tbuf_offset = 0x0600,
2370                 .hfb_offset = 0x8000,
2371                 .hfb_reg_offset = 0xfc00,
2372                 .rdma_offset = 0x2000,
2373                 .tdma_offset = 0x4000,
2374                 .words_per_bd = 3,
2375                 .flags = GENET_HAS_40BITS | GENET_HAS_EXT | GENET_HAS_MDIO_INTR,
2376         },
2377 };
2378
2379 /* Infer hardware parameters from the detected GENET version */
2380 static void bcmgenet_set_hw_params(struct bcmgenet_priv *priv)
2381 {
2382         struct bcmgenet_hw_params *params;
2383         u32 reg;
2384         u8 major;
2385
2386         if (GENET_IS_V4(priv)) {
2387                 bcmgenet_dma_regs = bcmgenet_dma_regs_v3plus;
2388                 genet_dma_ring_regs = genet_dma_ring_regs_v4;
2389                 priv->dma_rx_chk_bit = DMA_RX_CHK_V3PLUS;
2390                 priv->version = GENET_V4;
2391         } else if (GENET_IS_V3(priv)) {
2392                 bcmgenet_dma_regs = bcmgenet_dma_regs_v3plus;
2393                 genet_dma_ring_regs = genet_dma_ring_regs_v123;
2394                 priv->dma_rx_chk_bit = DMA_RX_CHK_V3PLUS;
2395                 priv->version = GENET_V3;
2396         } else if (GENET_IS_V2(priv)) {
2397                 bcmgenet_dma_regs = bcmgenet_dma_regs_v2;
2398                 genet_dma_ring_regs = genet_dma_ring_regs_v123;
2399                 priv->dma_rx_chk_bit = DMA_RX_CHK_V12;
2400                 priv->version = GENET_V2;
2401         } else if (GENET_IS_V1(priv)) {
2402                 bcmgenet_dma_regs = bcmgenet_dma_regs_v1;
2403                 genet_dma_ring_regs = genet_dma_ring_regs_v123;
2404                 priv->dma_rx_chk_bit = DMA_RX_CHK_V12;
2405                 priv->version = GENET_V1;
2406         }
2407
2408         /* enum genet_version starts at 1 */
2409         priv->hw_params = &bcmgenet_hw_params[priv->version];
2410         params = priv->hw_params;
2411
2412         /* Read GENET HW version */
2413         reg = bcmgenet_sys_readl(priv, SYS_REV_CTRL);
2414         major = (reg >> 24 & 0x0f);
2415         if (major == 5)
2416                 major = 4;
2417         else if (major == 0)
2418                 major = 1;
2419         if (major != priv->version) {
2420                 dev_err(&priv->pdev->dev,
2421                         "GENET version mismatch, got: %d, configured for: %d\n",
2422                         major, priv->version);
2423         }
2424
2425         /* Print the GENET core version */
2426         dev_info(&priv->pdev->dev, "GENET " GENET_VER_FMT,
2427                  major, (reg >> 16) & 0x0f, reg & 0xffff);
2428
2429 #ifdef CONFIG_PHYS_ADDR_T_64BIT
2430         if (!(params->flags & GENET_HAS_40BITS))
2431                 pr_warn("GENET does not support 40-bits PA\n");
2432 #endif
2433
2434         pr_debug("Configuration for version: %d\n"
2435                 "TXq: %1d, RXq: %1d, BDs: %1d\n"
2436                 "BP << en: %2d, BP msk: 0x%05x\n"
2437                 "HFB count: %2d, QTAQ msk: 0x%05x\n"
2438                 "TBUF: 0x%04x, HFB: 0x%04x, HFBreg: 0x%04x\n"
2439                 "RDMA: 0x%05x, TDMA: 0x%05x\n"
2440                 "Words/BD: %d\n",
2441                 priv->version,
2442                 params->tx_queues, params->rx_queues, params->bds_cnt,
2443                 params->bp_in_en_shift, params->bp_in_mask,
2444                 params->hfb_filter_cnt, params->qtag_mask,
2445                 params->tbuf_offset, params->hfb_offset,
2446                 params->hfb_reg_offset,
2447                 params->rdma_offset, params->tdma_offset,
2448                 params->words_per_bd);
2449 }
2450
2451 static const struct of_device_id bcmgenet_match[] = {
2452         { .compatible = "brcm,genet-v1", .data = (void *)GENET_V1 },
2453         { .compatible = "brcm,genet-v2", .data = (void *)GENET_V2 },
2454         { .compatible = "brcm,genet-v3", .data = (void *)GENET_V3 },
2455         { .compatible = "brcm,genet-v4", .data = (void *)GENET_V4 },
2456         { },
2457 };
2458
2459 static int bcmgenet_probe(struct platform_device *pdev)
2460 {
2461         struct device_node *dn = pdev->dev.of_node;
2462         const struct of_device_id *of_id;
2463         struct bcmgenet_priv *priv;
2464         struct net_device *dev;
2465         const void *macaddr;
2466         struct resource *r;
2467         int err = -EIO;
2468
2469         /* Up to GENET_MAX_MQ_CNT + 1 TX queues and a single RX queue */
2470         dev = alloc_etherdev_mqs(sizeof(*priv), GENET_MAX_MQ_CNT + 1, 1);
2471         if (!dev) {
2472                 dev_err(&pdev->dev, "can't allocate net device\n");
2473                 return -ENOMEM;
2474         }
2475
2476         of_id = of_match_node(bcmgenet_match, dn);
2477         if (!of_id)
2478                 return -EINVAL;
2479
2480         priv = netdev_priv(dev);
2481         priv->irq0 = platform_get_irq(pdev, 0);
2482         priv->irq1 = platform_get_irq(pdev, 1);
2483         priv->wol_irq = platform_get_irq(pdev, 2);
2484         if (!priv->irq0 || !priv->irq1) {
2485                 dev_err(&pdev->dev, "can't find IRQs\n");
2486                 err = -EINVAL;
2487                 goto err;
2488         }
2489
2490         macaddr = of_get_mac_address(dn);
2491         if (!macaddr) {
2492                 dev_err(&pdev->dev, "can't find MAC address\n");
2493                 err = -EINVAL;
2494                 goto err;
2495         }
2496
2497         r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2498         priv->base = devm_ioremap_resource(&pdev->dev, r);
2499         if (IS_ERR(priv->base)) {
2500                 err = PTR_ERR(priv->base);
2501                 goto err;
2502         }
2503
2504         SET_NETDEV_DEV(dev, &pdev->dev);
2505         dev_set_drvdata(&pdev->dev, dev);
2506         ether_addr_copy(dev->dev_addr, macaddr);
2507         dev->watchdog_timeo = 2 * HZ;
2508         dev->ethtool_ops = &bcmgenet_ethtool_ops;
2509         dev->netdev_ops = &bcmgenet_netdev_ops;
2510         netif_napi_add(dev, &priv->napi, bcmgenet_poll, 64);
2511
2512         priv->msg_enable = netif_msg_init(-1, GENET_MSG_DEFAULT);
2513
2514         /* Set hardware features */
2515         dev->hw_features |= NETIF_F_SG | NETIF_F_IP_CSUM |
2516                 NETIF_F_IPV6_CSUM | NETIF_F_RXCSUM;
2517
2518         /* Request the WOL interrupt and advertise suspend if available */
2519         priv->wol_irq_disabled = true;
2520         err = devm_request_irq(&pdev->dev, priv->wol_irq, bcmgenet_wol_isr, 0,
2521                                dev->name, priv);
2522         if (!err)
2523                 device_set_wakeup_capable(&pdev->dev, 1);
2524
2525         /* Set the needed headroom to account for any possible
2526          * features enabling/disabling at runtime
2527          */
2528         dev->needed_headroom += 64;
2529
2530         netdev_boot_setup_check(dev);
2531
2532         priv->dev = dev;
2533         priv->pdev = pdev;
2534         priv->version = (enum bcmgenet_version)of_id->data;
2535
2536         bcmgenet_set_hw_params(priv);
2537
2538         /* Mii wait queue */
2539         init_waitqueue_head(&priv->wq);
2540         /* Always use RX_BUF_LENGTH (2KB) buffer for all chips */
2541         priv->rx_buf_len = RX_BUF_LENGTH;
2542         INIT_WORK(&priv->bcmgenet_irq_work, bcmgenet_irq_task);
2543
2544         priv->clk = devm_clk_get(&priv->pdev->dev, "enet");
2545         if (IS_ERR(priv->clk))
2546                 dev_warn(&priv->pdev->dev, "failed to get enet clock\n");
2547
2548         priv->clk_wol = devm_clk_get(&priv->pdev->dev, "enet-wol");
2549         if (IS_ERR(priv->clk_wol))
2550                 dev_warn(&priv->pdev->dev, "failed to get enet-wol clock\n");
2551
2552         if (!IS_ERR(priv->clk))
2553                 clk_prepare_enable(priv->clk);
2554
2555         err = reset_umac(priv);
2556         if (err)
2557                 goto err_clk_disable;
2558
2559         err = bcmgenet_mii_init(dev);
2560         if (err)
2561                 goto err_clk_disable;
2562
2563         /* setup number of real queues  + 1 (GENET_V1 has 0 hardware queues
2564          * just the ring 16 descriptor based TX
2565          */
2566         netif_set_real_num_tx_queues(priv->dev, priv->hw_params->tx_queues + 1);
2567         netif_set_real_num_rx_queues(priv->dev, priv->hw_params->rx_queues + 1);
2568
2569         /* libphy will determine the link state */
2570         netif_carrier_off(dev);
2571
2572         /* Turn off the main clock, WOL clock is handled separately */
2573         if (!IS_ERR(priv->clk))
2574                 clk_disable_unprepare(priv->clk);
2575
2576         err = register_netdev(dev);
2577         if (err)
2578                 goto err;
2579
2580         return err;
2581
2582 err_clk_disable:
2583         if (!IS_ERR(priv->clk))
2584                 clk_disable_unprepare(priv->clk);
2585 err:
2586         free_netdev(dev);
2587         return err;
2588 }
2589
2590 static int bcmgenet_remove(struct platform_device *pdev)
2591 {
2592         struct bcmgenet_priv *priv = dev_to_priv(&pdev->dev);
2593
2594         dev_set_drvdata(&pdev->dev, NULL);
2595         unregister_netdev(priv->dev);
2596         bcmgenet_mii_exit(priv->dev);
2597         free_netdev(priv->dev);
2598
2599         return 0;
2600 }
2601
2602 #ifdef CONFIG_PM_SLEEP
2603 static int bcmgenet_suspend(struct device *d)
2604 {
2605         struct net_device *dev = dev_get_drvdata(d);
2606         struct bcmgenet_priv *priv = netdev_priv(dev);
2607         int ret;
2608
2609         if (!netif_running(dev))
2610                 return 0;
2611
2612         bcmgenet_netif_stop(dev);
2613
2614         netif_device_detach(dev);
2615
2616         /* Disable MAC receive */
2617         umac_enable_set(priv, CMD_RX_EN, false);
2618
2619         ret = bcmgenet_dma_teardown(priv);
2620         if (ret)
2621                 return ret;
2622
2623         /* Disable MAC transmit. TX DMA disabled have to done before this */
2624         umac_enable_set(priv, CMD_TX_EN, false);
2625
2626         /* tx reclaim */
2627         bcmgenet_tx_reclaim_all(dev);
2628         bcmgenet_fini_dma(priv);
2629
2630         /* Prepare the device for Wake-on-LAN and switch to the slow clock */
2631         if (device_may_wakeup(d) && priv->wolopts) {
2632                 bcmgenet_power_down(priv, GENET_POWER_WOL_MAGIC);
2633                 clk_prepare_enable(priv->clk_wol);
2634         }
2635
2636         /* Turn off the clocks */
2637         clk_disable_unprepare(priv->clk);
2638
2639         return 0;
2640 }
2641
2642 static int bcmgenet_resume(struct device *d)
2643 {
2644         struct net_device *dev = dev_get_drvdata(d);
2645         struct bcmgenet_priv *priv = netdev_priv(dev);
2646         unsigned long dma_ctrl;
2647         int ret;
2648         u32 reg;
2649
2650         if (!netif_running(dev))
2651                 return 0;
2652
2653         /* Turn on the clock */
2654         ret = clk_prepare_enable(priv->clk);
2655         if (ret)
2656                 return ret;
2657
2658         bcmgenet_umac_reset(priv);
2659
2660         ret = init_umac(priv);
2661         if (ret)
2662                 goto out_clk_disable;
2663
2664         if (priv->wolopts)
2665                 ret = bcmgenet_wol_resume(priv);
2666
2667         if (ret)
2668                 goto out_clk_disable;
2669
2670         /* disable ethernet MAC while updating its registers */
2671         umac_enable_set(priv, CMD_TX_EN | CMD_RX_EN, false);
2672
2673         bcmgenet_set_hw_addr(priv, dev->dev_addr);
2674
2675         if (phy_is_internal(priv->phydev)) {
2676                 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
2677                 reg |= EXT_ENERGY_DET_MASK;
2678                 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
2679         }
2680
2681         /* Disable RX/TX DMA and flush TX queues */
2682         dma_ctrl = bcmgenet_dma_disable(priv);
2683
2684         /* Reinitialize TDMA and RDMA and SW housekeeping */
2685         ret = bcmgenet_init_dma(priv);
2686         if (ret) {
2687                 netdev_err(dev, "failed to initialize DMA\n");
2688                 goto out_clk_disable;
2689         }
2690
2691         /* Always enable ring 16 - descriptor ring */
2692         bcmgenet_enable_dma(priv, dma_ctrl);
2693
2694         netif_device_attach(dev);
2695
2696         bcmgenet_netif_start(dev);
2697
2698         return 0;
2699
2700 out_clk_disable:
2701         clk_disable_unprepare(priv->clk);
2702         return ret;
2703 }
2704 #endif /* CONFIG_PM_SLEEP */
2705
2706 static SIMPLE_DEV_PM_OPS(bcmgenet_pm_ops, bcmgenet_suspend, bcmgenet_resume);
2707
2708 static struct platform_driver bcmgenet_driver = {
2709         .probe  = bcmgenet_probe,
2710         .remove = bcmgenet_remove,
2711         .driver = {
2712                 .name   = "bcmgenet",
2713                 .owner  = THIS_MODULE,
2714                 .of_match_table = bcmgenet_match,
2715                 .pm     = &bcmgenet_pm_ops,
2716         },
2717 };
2718 module_platform_driver(bcmgenet_driver);
2719
2720 MODULE_AUTHOR("Broadcom Corporation");
2721 MODULE_DESCRIPTION("Broadcom GENET Ethernet controller driver");
2722 MODULE_ALIAS("platform:bcmgenet");
2723 MODULE_LICENSE("GPL");