1 // SPDX-License-Identifier: GPL-2.0-only
3 * Broadcom GENET (Gigabit Ethernet) controller driver
5 * Copyright (c) 2014-2020 Broadcom
8 #define pr_fmt(fmt) "bcmgenet: " fmt
10 #include <linux/acpi.h>
11 #include <linux/kernel.h>
12 #include <linux/module.h>
13 #include <linux/sched.h>
14 #include <linux/types.h>
15 #include <linux/fcntl.h>
16 #include <linux/interrupt.h>
17 #include <linux/string.h>
18 #include <linux/if_ether.h>
19 #include <linux/init.h>
20 #include <linux/errno.h>
21 #include <linux/delay.h>
22 #include <linux/platform_device.h>
23 #include <linux/dma-mapping.h>
25 #include <linux/clk.h>
28 #include <linux/mii.h>
29 #include <linux/ethtool.h>
30 #include <linux/netdevice.h>
31 #include <linux/inetdevice.h>
32 #include <linux/etherdevice.h>
33 #include <linux/skbuff.h>
36 #include <linux/ipv6.h>
37 #include <linux/phy.h>
38 #include <linux/platform_data/bcmgenet.h>
40 #include <asm/unaligned.h>
44 /* Maximum number of hardware queues, downsized if needed */
45 #define GENET_MAX_MQ_CNT 4
47 /* Default highest priority queue for multi queue support */
48 #define GENET_Q0_PRIORITY 0
50 #define GENET_Q16_RX_BD_CNT \
51 (TOTAL_DESC - priv->hw_params->rx_queues * priv->hw_params->rx_bds_per_q)
52 #define GENET_Q16_TX_BD_CNT \
53 (TOTAL_DESC - priv->hw_params->tx_queues * priv->hw_params->tx_bds_per_q)
55 #define RX_BUF_LENGTH 2048
56 #define SKB_ALIGNMENT 32
58 /* Tx/Rx DMA register offset, skip 256 descriptors */
59 #define WORDS_PER_BD(p) (p->hw_params->words_per_bd)
60 #define DMA_DESC_SIZE (WORDS_PER_BD(priv) * sizeof(u32))
62 #define GENET_TDMA_REG_OFF (priv->hw_params->tdma_offset + \
63 TOTAL_DESC * DMA_DESC_SIZE)
65 #define GENET_RDMA_REG_OFF (priv->hw_params->rdma_offset + \
66 TOTAL_DESC * DMA_DESC_SIZE)
68 /* Forward declarations */
69 static void bcmgenet_set_rx_mode(struct net_device *dev);
71 static inline void bcmgenet_writel(u32 value, void __iomem *offset)
73 /* MIPS chips strapped for BE will automagically configure the
74 * peripheral registers for CPU-native byte order.
76 if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
77 __raw_writel(value, offset);
79 writel_relaxed(value, offset);
82 static inline u32 bcmgenet_readl(void __iomem *offset)
84 if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
85 return __raw_readl(offset);
87 return readl_relaxed(offset);
90 static inline void dmadesc_set_length_status(struct bcmgenet_priv *priv,
91 void __iomem *d, u32 value)
93 bcmgenet_writel(value, d + DMA_DESC_LENGTH_STATUS);
96 static inline void dmadesc_set_addr(struct bcmgenet_priv *priv,
100 bcmgenet_writel(lower_32_bits(addr), d + DMA_DESC_ADDRESS_LO);
102 /* Register writes to GISB bus can take couple hundred nanoseconds
103 * and are done for each packet, save these expensive writes unless
104 * the platform is explicitly configured for 64-bits/LPAE.
106 #ifdef CONFIG_PHYS_ADDR_T_64BIT
107 if (priv->hw_params->flags & GENET_HAS_40BITS)
108 bcmgenet_writel(upper_32_bits(addr), d + DMA_DESC_ADDRESS_HI);
112 /* Combined address + length/status setter */
113 static inline void dmadesc_set(struct bcmgenet_priv *priv,
114 void __iomem *d, dma_addr_t addr, u32 val)
116 dmadesc_set_addr(priv, d, addr);
117 dmadesc_set_length_status(priv, d, val);
120 static inline dma_addr_t dmadesc_get_addr(struct bcmgenet_priv *priv,
125 addr = bcmgenet_readl(d + DMA_DESC_ADDRESS_LO);
127 /* Register writes to GISB bus can take couple hundred nanoseconds
128 * and are done for each packet, save these expensive writes unless
129 * the platform is explicitly configured for 64-bits/LPAE.
131 #ifdef CONFIG_PHYS_ADDR_T_64BIT
132 if (priv->hw_params->flags & GENET_HAS_40BITS)
133 addr |= (u64)bcmgenet_readl(d + DMA_DESC_ADDRESS_HI) << 32;
138 #define GENET_VER_FMT "%1d.%1d EPHY: 0x%04x"
140 #define GENET_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | \
143 static inline u32 bcmgenet_rbuf_ctrl_get(struct bcmgenet_priv *priv)
145 if (GENET_IS_V1(priv))
146 return bcmgenet_rbuf_readl(priv, RBUF_FLUSH_CTRL_V1);
148 return bcmgenet_sys_readl(priv, SYS_RBUF_FLUSH_CTRL);
151 static inline void bcmgenet_rbuf_ctrl_set(struct bcmgenet_priv *priv, u32 val)
153 if (GENET_IS_V1(priv))
154 bcmgenet_rbuf_writel(priv, val, RBUF_FLUSH_CTRL_V1);
156 bcmgenet_sys_writel(priv, val, SYS_RBUF_FLUSH_CTRL);
159 /* These macros are defined to deal with register map change
160 * between GENET1.1 and GENET2. Only those currently being used
161 * by driver are defined.
163 static inline u32 bcmgenet_tbuf_ctrl_get(struct bcmgenet_priv *priv)
165 if (GENET_IS_V1(priv))
166 return bcmgenet_rbuf_readl(priv, TBUF_CTRL_V1);
168 return bcmgenet_readl(priv->base +
169 priv->hw_params->tbuf_offset + TBUF_CTRL);
172 static inline void bcmgenet_tbuf_ctrl_set(struct bcmgenet_priv *priv, u32 val)
174 if (GENET_IS_V1(priv))
175 bcmgenet_rbuf_writel(priv, val, TBUF_CTRL_V1);
177 bcmgenet_writel(val, priv->base +
178 priv->hw_params->tbuf_offset + TBUF_CTRL);
181 static inline u32 bcmgenet_bp_mc_get(struct bcmgenet_priv *priv)
183 if (GENET_IS_V1(priv))
184 return bcmgenet_rbuf_readl(priv, TBUF_BP_MC_V1);
186 return bcmgenet_readl(priv->base +
187 priv->hw_params->tbuf_offset + TBUF_BP_MC);
190 static inline void bcmgenet_bp_mc_set(struct bcmgenet_priv *priv, u32 val)
192 if (GENET_IS_V1(priv))
193 bcmgenet_rbuf_writel(priv, val, TBUF_BP_MC_V1);
195 bcmgenet_writel(val, priv->base +
196 priv->hw_params->tbuf_offset + TBUF_BP_MC);
199 /* RX/TX DMA register accessors */
236 static const u8 bcmgenet_dma_regs_v3plus[] = {
237 [DMA_RING_CFG] = 0x00,
240 [DMA_SCB_BURST_SIZE] = 0x0C,
241 [DMA_ARB_CTRL] = 0x2C,
242 [DMA_PRIORITY_0] = 0x30,
243 [DMA_PRIORITY_1] = 0x34,
244 [DMA_PRIORITY_2] = 0x38,
245 [DMA_RING0_TIMEOUT] = 0x2C,
246 [DMA_RING1_TIMEOUT] = 0x30,
247 [DMA_RING2_TIMEOUT] = 0x34,
248 [DMA_RING3_TIMEOUT] = 0x38,
249 [DMA_RING4_TIMEOUT] = 0x3c,
250 [DMA_RING5_TIMEOUT] = 0x40,
251 [DMA_RING6_TIMEOUT] = 0x44,
252 [DMA_RING7_TIMEOUT] = 0x48,
253 [DMA_RING8_TIMEOUT] = 0x4c,
254 [DMA_RING9_TIMEOUT] = 0x50,
255 [DMA_RING10_TIMEOUT] = 0x54,
256 [DMA_RING11_TIMEOUT] = 0x58,
257 [DMA_RING12_TIMEOUT] = 0x5c,
258 [DMA_RING13_TIMEOUT] = 0x60,
259 [DMA_RING14_TIMEOUT] = 0x64,
260 [DMA_RING15_TIMEOUT] = 0x68,
261 [DMA_RING16_TIMEOUT] = 0x6C,
262 [DMA_INDEX2RING_0] = 0x70,
263 [DMA_INDEX2RING_1] = 0x74,
264 [DMA_INDEX2RING_2] = 0x78,
265 [DMA_INDEX2RING_3] = 0x7C,
266 [DMA_INDEX2RING_4] = 0x80,
267 [DMA_INDEX2RING_5] = 0x84,
268 [DMA_INDEX2RING_6] = 0x88,
269 [DMA_INDEX2RING_7] = 0x8C,
272 static const u8 bcmgenet_dma_regs_v2[] = {
273 [DMA_RING_CFG] = 0x00,
276 [DMA_SCB_BURST_SIZE] = 0x0C,
277 [DMA_ARB_CTRL] = 0x30,
278 [DMA_PRIORITY_0] = 0x34,
279 [DMA_PRIORITY_1] = 0x38,
280 [DMA_PRIORITY_2] = 0x3C,
281 [DMA_RING0_TIMEOUT] = 0x2C,
282 [DMA_RING1_TIMEOUT] = 0x30,
283 [DMA_RING2_TIMEOUT] = 0x34,
284 [DMA_RING3_TIMEOUT] = 0x38,
285 [DMA_RING4_TIMEOUT] = 0x3c,
286 [DMA_RING5_TIMEOUT] = 0x40,
287 [DMA_RING6_TIMEOUT] = 0x44,
288 [DMA_RING7_TIMEOUT] = 0x48,
289 [DMA_RING8_TIMEOUT] = 0x4c,
290 [DMA_RING9_TIMEOUT] = 0x50,
291 [DMA_RING10_TIMEOUT] = 0x54,
292 [DMA_RING11_TIMEOUT] = 0x58,
293 [DMA_RING12_TIMEOUT] = 0x5c,
294 [DMA_RING13_TIMEOUT] = 0x60,
295 [DMA_RING14_TIMEOUT] = 0x64,
296 [DMA_RING15_TIMEOUT] = 0x68,
297 [DMA_RING16_TIMEOUT] = 0x6C,
300 static const u8 bcmgenet_dma_regs_v1[] = {
303 [DMA_SCB_BURST_SIZE] = 0x0C,
304 [DMA_ARB_CTRL] = 0x30,
305 [DMA_PRIORITY_0] = 0x34,
306 [DMA_PRIORITY_1] = 0x38,
307 [DMA_PRIORITY_2] = 0x3C,
308 [DMA_RING0_TIMEOUT] = 0x2C,
309 [DMA_RING1_TIMEOUT] = 0x30,
310 [DMA_RING2_TIMEOUT] = 0x34,
311 [DMA_RING3_TIMEOUT] = 0x38,
312 [DMA_RING4_TIMEOUT] = 0x3c,
313 [DMA_RING5_TIMEOUT] = 0x40,
314 [DMA_RING6_TIMEOUT] = 0x44,
315 [DMA_RING7_TIMEOUT] = 0x48,
316 [DMA_RING8_TIMEOUT] = 0x4c,
317 [DMA_RING9_TIMEOUT] = 0x50,
318 [DMA_RING10_TIMEOUT] = 0x54,
319 [DMA_RING11_TIMEOUT] = 0x58,
320 [DMA_RING12_TIMEOUT] = 0x5c,
321 [DMA_RING13_TIMEOUT] = 0x60,
322 [DMA_RING14_TIMEOUT] = 0x64,
323 [DMA_RING15_TIMEOUT] = 0x68,
324 [DMA_RING16_TIMEOUT] = 0x6C,
327 /* Set at runtime once bcmgenet version is known */
328 static const u8 *bcmgenet_dma_regs;
330 static inline struct bcmgenet_priv *dev_to_priv(struct device *dev)
332 return netdev_priv(dev_get_drvdata(dev));
335 static inline u32 bcmgenet_tdma_readl(struct bcmgenet_priv *priv,
338 return bcmgenet_readl(priv->base + GENET_TDMA_REG_OFF +
339 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
342 static inline void bcmgenet_tdma_writel(struct bcmgenet_priv *priv,
343 u32 val, enum dma_reg r)
345 bcmgenet_writel(val, priv->base + GENET_TDMA_REG_OFF +
346 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
349 static inline u32 bcmgenet_rdma_readl(struct bcmgenet_priv *priv,
352 return bcmgenet_readl(priv->base + GENET_RDMA_REG_OFF +
353 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
356 static inline void bcmgenet_rdma_writel(struct bcmgenet_priv *priv,
357 u32 val, enum dma_reg r)
359 bcmgenet_writel(val, priv->base + GENET_RDMA_REG_OFF +
360 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
363 /* RDMA/TDMA ring registers and accessors
364 * we merge the common fields and just prefix with T/D the registers
365 * having different meaning depending on the direction
369 RDMA_WRITE_PTR = TDMA_READ_PTR,
371 RDMA_WRITE_PTR_HI = TDMA_READ_PTR_HI,
373 RDMA_PROD_INDEX = TDMA_CONS_INDEX,
375 RDMA_CONS_INDEX = TDMA_PROD_INDEX,
381 DMA_MBUF_DONE_THRESH,
383 RDMA_XON_XOFF_THRESH = TDMA_FLOW_PERIOD,
385 RDMA_READ_PTR = TDMA_WRITE_PTR,
387 RDMA_READ_PTR_HI = TDMA_WRITE_PTR_HI
390 /* GENET v4 supports 40-bits pointer addressing
391 * for obvious reasons the LO and HI word parts
392 * are contiguous, but this offsets the other
395 static const u8 genet_dma_ring_regs_v4[] = {
396 [TDMA_READ_PTR] = 0x00,
397 [TDMA_READ_PTR_HI] = 0x04,
398 [TDMA_CONS_INDEX] = 0x08,
399 [TDMA_PROD_INDEX] = 0x0C,
400 [DMA_RING_BUF_SIZE] = 0x10,
401 [DMA_START_ADDR] = 0x14,
402 [DMA_START_ADDR_HI] = 0x18,
403 [DMA_END_ADDR] = 0x1C,
404 [DMA_END_ADDR_HI] = 0x20,
405 [DMA_MBUF_DONE_THRESH] = 0x24,
406 [TDMA_FLOW_PERIOD] = 0x28,
407 [TDMA_WRITE_PTR] = 0x2C,
408 [TDMA_WRITE_PTR_HI] = 0x30,
411 static const u8 genet_dma_ring_regs_v123[] = {
412 [TDMA_READ_PTR] = 0x00,
413 [TDMA_CONS_INDEX] = 0x04,
414 [TDMA_PROD_INDEX] = 0x08,
415 [DMA_RING_BUF_SIZE] = 0x0C,
416 [DMA_START_ADDR] = 0x10,
417 [DMA_END_ADDR] = 0x14,
418 [DMA_MBUF_DONE_THRESH] = 0x18,
419 [TDMA_FLOW_PERIOD] = 0x1C,
420 [TDMA_WRITE_PTR] = 0x20,
423 /* Set at runtime once GENET version is known */
424 static const u8 *genet_dma_ring_regs;
426 static inline u32 bcmgenet_tdma_ring_readl(struct bcmgenet_priv *priv,
430 return bcmgenet_readl(priv->base + GENET_TDMA_REG_OFF +
431 (DMA_RING_SIZE * ring) +
432 genet_dma_ring_regs[r]);
435 static inline void bcmgenet_tdma_ring_writel(struct bcmgenet_priv *priv,
436 unsigned int ring, u32 val,
439 bcmgenet_writel(val, priv->base + GENET_TDMA_REG_OFF +
440 (DMA_RING_SIZE * ring) +
441 genet_dma_ring_regs[r]);
444 static inline u32 bcmgenet_rdma_ring_readl(struct bcmgenet_priv *priv,
448 return bcmgenet_readl(priv->base + GENET_RDMA_REG_OFF +
449 (DMA_RING_SIZE * ring) +
450 genet_dma_ring_regs[r]);
453 static inline void bcmgenet_rdma_ring_writel(struct bcmgenet_priv *priv,
454 unsigned int ring, u32 val,
457 bcmgenet_writel(val, priv->base + GENET_RDMA_REG_OFF +
458 (DMA_RING_SIZE * ring) +
459 genet_dma_ring_regs[r]);
462 static void bcmgenet_hfb_enable_filter(struct bcmgenet_priv *priv, u32 f_index)
467 offset = HFB_FLT_ENABLE_V3PLUS + (f_index < 32) * sizeof(u32);
468 reg = bcmgenet_hfb_reg_readl(priv, offset);
469 reg |= (1 << (f_index % 32));
470 bcmgenet_hfb_reg_writel(priv, reg, offset);
471 reg = bcmgenet_hfb_reg_readl(priv, HFB_CTRL);
473 bcmgenet_hfb_reg_writel(priv, reg, HFB_CTRL);
476 static void bcmgenet_hfb_disable_filter(struct bcmgenet_priv *priv, u32 f_index)
478 u32 offset, reg, reg1;
480 offset = HFB_FLT_ENABLE_V3PLUS;
481 reg = bcmgenet_hfb_reg_readl(priv, offset);
482 reg1 = bcmgenet_hfb_reg_readl(priv, offset + sizeof(u32));
484 reg1 &= ~(1 << (f_index % 32));
485 bcmgenet_hfb_reg_writel(priv, reg1, offset + sizeof(u32));
487 reg &= ~(1 << (f_index % 32));
488 bcmgenet_hfb_reg_writel(priv, reg, offset);
491 reg = bcmgenet_hfb_reg_readl(priv, HFB_CTRL);
493 bcmgenet_hfb_reg_writel(priv, reg, HFB_CTRL);
497 static void bcmgenet_hfb_set_filter_rx_queue_mapping(struct bcmgenet_priv *priv,
498 u32 f_index, u32 rx_queue)
503 offset = f_index / 8;
504 reg = bcmgenet_rdma_readl(priv, DMA_INDEX2RING_0 + offset);
505 reg &= ~(0xF << (4 * (f_index % 8)));
506 reg |= ((rx_queue & 0xF) << (4 * (f_index % 8)));
507 bcmgenet_rdma_writel(priv, reg, DMA_INDEX2RING_0 + offset);
510 static void bcmgenet_hfb_set_filter_length(struct bcmgenet_priv *priv,
511 u32 f_index, u32 f_length)
516 offset = HFB_FLT_LEN_V3PLUS +
517 ((priv->hw_params->hfb_filter_cnt - 1 - f_index) / 4) *
519 reg = bcmgenet_hfb_reg_readl(priv, offset);
520 reg &= ~(0xFF << (8 * (f_index % 4)));
521 reg |= ((f_length & 0xFF) << (8 * (f_index % 4)));
522 bcmgenet_hfb_reg_writel(priv, reg, offset);
525 static int bcmgenet_hfb_validate_mask(void *mask, size_t size)
528 switch (*(unsigned char *)mask++) {
543 #define VALIDATE_MASK(x) \
544 bcmgenet_hfb_validate_mask(&(x), sizeof(x))
546 static int bcmgenet_hfb_insert_data(struct bcmgenet_priv *priv, u32 f_index,
547 u32 offset, void *val, void *mask,
552 index = f_index * priv->hw_params->hfb_filter_size + offset / 2;
553 tmp = bcmgenet_hfb_readl(priv, index * sizeof(u32));
558 tmp |= (*(unsigned char *)val++);
559 switch ((*(unsigned char *)mask++)) {
570 bcmgenet_hfb_writel(priv, tmp, index++ * sizeof(u32));
572 tmp = bcmgenet_hfb_readl(priv,
573 index * sizeof(u32));
576 tmp |= (*(unsigned char *)val++) << 8;
577 switch ((*(unsigned char *)mask++)) {
589 bcmgenet_hfb_writel(priv, tmp, index * sizeof(u32));
596 static void bcmgenet_hfb_create_rxnfc_filter(struct bcmgenet_priv *priv,
597 struct bcmgenet_rxnfc_rule *rule)
599 struct ethtool_rx_flow_spec *fs = &rule->fs;
600 u32 offset = 0, f_length = 0, f;
607 if (fs->flow_type & FLOW_MAC_EXT) {
608 bcmgenet_hfb_insert_data(priv, f, 0,
609 &fs->h_ext.h_dest, &fs->m_ext.h_dest,
610 sizeof(fs->h_ext.h_dest));
613 if (fs->flow_type & FLOW_EXT) {
614 if (fs->m_ext.vlan_etype ||
615 fs->m_ext.vlan_tci) {
616 bcmgenet_hfb_insert_data(priv, f, 12,
617 &fs->h_ext.vlan_etype,
618 &fs->m_ext.vlan_etype,
619 sizeof(fs->h_ext.vlan_etype));
620 bcmgenet_hfb_insert_data(priv, f, 14,
623 sizeof(fs->h_ext.vlan_tci));
625 f_length += DIV_ROUND_UP(VLAN_HLEN, 2);
629 switch (fs->flow_type & ~(FLOW_EXT | FLOW_MAC_EXT)) {
631 f_length += DIV_ROUND_UP(ETH_HLEN, 2);
632 bcmgenet_hfb_insert_data(priv, f, 0,
633 &fs->h_u.ether_spec.h_dest,
634 &fs->m_u.ether_spec.h_dest,
635 sizeof(fs->h_u.ether_spec.h_dest));
636 bcmgenet_hfb_insert_data(priv, f, ETH_ALEN,
637 &fs->h_u.ether_spec.h_source,
638 &fs->m_u.ether_spec.h_source,
639 sizeof(fs->h_u.ether_spec.h_source));
640 bcmgenet_hfb_insert_data(priv, f, (2 * ETH_ALEN) + offset,
641 &fs->h_u.ether_spec.h_proto,
642 &fs->m_u.ether_spec.h_proto,
643 sizeof(fs->h_u.ether_spec.h_proto));
646 f_length += DIV_ROUND_UP(ETH_HLEN + 20, 2);
647 /* Specify IP Ether Type */
648 val_16 = htons(ETH_P_IP);
650 bcmgenet_hfb_insert_data(priv, f, (2 * ETH_ALEN) + offset,
651 &val_16, &mask_16, sizeof(val_16));
652 bcmgenet_hfb_insert_data(priv, f, 15 + offset,
653 &fs->h_u.usr_ip4_spec.tos,
654 &fs->m_u.usr_ip4_spec.tos,
655 sizeof(fs->h_u.usr_ip4_spec.tos));
656 bcmgenet_hfb_insert_data(priv, f, 23 + offset,
657 &fs->h_u.usr_ip4_spec.proto,
658 &fs->m_u.usr_ip4_spec.proto,
659 sizeof(fs->h_u.usr_ip4_spec.proto));
660 bcmgenet_hfb_insert_data(priv, f, 26 + offset,
661 &fs->h_u.usr_ip4_spec.ip4src,
662 &fs->m_u.usr_ip4_spec.ip4src,
663 sizeof(fs->h_u.usr_ip4_spec.ip4src));
664 bcmgenet_hfb_insert_data(priv, f, 30 + offset,
665 &fs->h_u.usr_ip4_spec.ip4dst,
666 &fs->m_u.usr_ip4_spec.ip4dst,
667 sizeof(fs->h_u.usr_ip4_spec.ip4dst));
668 if (!fs->m_u.usr_ip4_spec.l4_4_bytes)
671 /* Only supports 20 byte IPv4 header */
674 bcmgenet_hfb_insert_data(priv, f, ETH_HLEN + offset,
677 size = sizeof(fs->h_u.usr_ip4_spec.l4_4_bytes);
678 bcmgenet_hfb_insert_data(priv, f,
679 ETH_HLEN + 20 + offset,
680 &fs->h_u.usr_ip4_spec.l4_4_bytes,
681 &fs->m_u.usr_ip4_spec.l4_4_bytes,
683 f_length += DIV_ROUND_UP(size, 2);
687 bcmgenet_hfb_set_filter_length(priv, f, 2 * f_length);
688 if (!fs->ring_cookie || fs->ring_cookie == RX_CLS_FLOW_WAKE) {
689 /* Ring 0 flows can be handled by the default Descriptor Ring
690 * We'll map them to ring 0, but don't enable the filter
692 bcmgenet_hfb_set_filter_rx_queue_mapping(priv, f, 0);
693 rule->state = BCMGENET_RXNFC_STATE_DISABLED;
695 /* Other Rx rings are direct mapped here */
696 bcmgenet_hfb_set_filter_rx_queue_mapping(priv, f,
698 bcmgenet_hfb_enable_filter(priv, f);
699 rule->state = BCMGENET_RXNFC_STATE_ENABLED;
703 /* bcmgenet_hfb_clear
705 * Clear Hardware Filter Block and disable all filtering.
707 static void bcmgenet_hfb_clear_filter(struct bcmgenet_priv *priv, u32 f_index)
711 base = f_index * priv->hw_params->hfb_filter_size;
712 for (i = 0; i < priv->hw_params->hfb_filter_size; i++)
713 bcmgenet_hfb_writel(priv, 0x0, (base + i) * sizeof(u32));
716 static void bcmgenet_hfb_clear(struct bcmgenet_priv *priv)
720 if (GENET_IS_V1(priv) || GENET_IS_V2(priv))
723 bcmgenet_hfb_reg_writel(priv, 0x0, HFB_CTRL);
724 bcmgenet_hfb_reg_writel(priv, 0x0, HFB_FLT_ENABLE_V3PLUS);
725 bcmgenet_hfb_reg_writel(priv, 0x0, HFB_FLT_ENABLE_V3PLUS + 4);
727 for (i = DMA_INDEX2RING_0; i <= DMA_INDEX2RING_7; i++)
728 bcmgenet_rdma_writel(priv, 0x0, i);
730 for (i = 0; i < (priv->hw_params->hfb_filter_cnt / 4); i++)
731 bcmgenet_hfb_reg_writel(priv, 0x0,
732 HFB_FLT_LEN_V3PLUS + i * sizeof(u32));
734 for (i = 0; i < priv->hw_params->hfb_filter_cnt; i++)
735 bcmgenet_hfb_clear_filter(priv, i);
738 static void bcmgenet_hfb_init(struct bcmgenet_priv *priv)
742 INIT_LIST_HEAD(&priv->rxnfc_list);
743 if (GENET_IS_V1(priv) || GENET_IS_V2(priv))
746 for (i = 0; i < MAX_NUM_OF_FS_RULES; i++) {
747 INIT_LIST_HEAD(&priv->rxnfc_rules[i].list);
748 priv->rxnfc_rules[i].state = BCMGENET_RXNFC_STATE_UNUSED;
751 bcmgenet_hfb_clear(priv);
754 static int bcmgenet_begin(struct net_device *dev)
756 struct bcmgenet_priv *priv = netdev_priv(dev);
758 /* Turn on the clock */
759 return clk_prepare_enable(priv->clk);
762 static void bcmgenet_complete(struct net_device *dev)
764 struct bcmgenet_priv *priv = netdev_priv(dev);
766 /* Turn off the clock */
767 clk_disable_unprepare(priv->clk);
770 static int bcmgenet_get_link_ksettings(struct net_device *dev,
771 struct ethtool_link_ksettings *cmd)
773 if (!netif_running(dev))
779 phy_ethtool_ksettings_get(dev->phydev, cmd);
784 static int bcmgenet_set_link_ksettings(struct net_device *dev,
785 const struct ethtool_link_ksettings *cmd)
787 if (!netif_running(dev))
793 return phy_ethtool_ksettings_set(dev->phydev, cmd);
796 static int bcmgenet_set_features(struct net_device *dev,
797 netdev_features_t features)
799 struct bcmgenet_priv *priv = netdev_priv(dev);
803 ret = clk_prepare_enable(priv->clk);
807 /* Make sure we reflect the value of CRC_CMD_FWD */
808 reg = bcmgenet_umac_readl(priv, UMAC_CMD);
809 priv->crc_fwd_en = !!(reg & CMD_CRC_FWD);
811 clk_disable_unprepare(priv->clk);
816 static u32 bcmgenet_get_msglevel(struct net_device *dev)
818 struct bcmgenet_priv *priv = netdev_priv(dev);
820 return priv->msg_enable;
823 static void bcmgenet_set_msglevel(struct net_device *dev, u32 level)
825 struct bcmgenet_priv *priv = netdev_priv(dev);
827 priv->msg_enable = level;
830 static int bcmgenet_get_coalesce(struct net_device *dev,
831 struct ethtool_coalesce *ec,
832 struct kernel_ethtool_coalesce *kernel_coal,
833 struct netlink_ext_ack *extack)
835 struct bcmgenet_priv *priv = netdev_priv(dev);
836 struct bcmgenet_rx_ring *ring;
839 ec->tx_max_coalesced_frames =
840 bcmgenet_tdma_ring_readl(priv, DESC_INDEX,
841 DMA_MBUF_DONE_THRESH);
842 ec->rx_max_coalesced_frames =
843 bcmgenet_rdma_ring_readl(priv, DESC_INDEX,
844 DMA_MBUF_DONE_THRESH);
845 ec->rx_coalesce_usecs =
846 bcmgenet_rdma_readl(priv, DMA_RING16_TIMEOUT) * 8192 / 1000;
848 for (i = 0; i < priv->hw_params->rx_queues; i++) {
849 ring = &priv->rx_rings[i];
850 ec->use_adaptive_rx_coalesce |= ring->dim.use_dim;
852 ring = &priv->rx_rings[DESC_INDEX];
853 ec->use_adaptive_rx_coalesce |= ring->dim.use_dim;
858 static void bcmgenet_set_rx_coalesce(struct bcmgenet_rx_ring *ring,
861 struct bcmgenet_priv *priv = ring->priv;
862 unsigned int i = ring->index;
865 bcmgenet_rdma_ring_writel(priv, i, pkts, DMA_MBUF_DONE_THRESH);
867 reg = bcmgenet_rdma_readl(priv, DMA_RING0_TIMEOUT + i);
868 reg &= ~DMA_TIMEOUT_MASK;
869 reg |= DIV_ROUND_UP(usecs * 1000, 8192);
870 bcmgenet_rdma_writel(priv, reg, DMA_RING0_TIMEOUT + i);
873 static void bcmgenet_set_ring_rx_coalesce(struct bcmgenet_rx_ring *ring,
874 struct ethtool_coalesce *ec)
876 struct dim_cq_moder moder;
879 ring->rx_coalesce_usecs = ec->rx_coalesce_usecs;
880 ring->rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
881 usecs = ring->rx_coalesce_usecs;
882 pkts = ring->rx_max_coalesced_frames;
884 if (ec->use_adaptive_rx_coalesce && !ring->dim.use_dim) {
885 moder = net_dim_get_def_rx_moderation(ring->dim.dim.mode);
890 ring->dim.use_dim = ec->use_adaptive_rx_coalesce;
891 bcmgenet_set_rx_coalesce(ring, usecs, pkts);
894 static int bcmgenet_set_coalesce(struct net_device *dev,
895 struct ethtool_coalesce *ec,
896 struct kernel_ethtool_coalesce *kernel_coal,
897 struct netlink_ext_ack *extack)
899 struct bcmgenet_priv *priv = netdev_priv(dev);
902 /* Base system clock is 125Mhz, DMA timeout is this reference clock
903 * divided by 1024, which yields roughly 8.192us, our maximum value
904 * has to fit in the DMA_TIMEOUT_MASK (16 bits)
906 if (ec->tx_max_coalesced_frames > DMA_INTR_THRESHOLD_MASK ||
907 ec->tx_max_coalesced_frames == 0 ||
908 ec->rx_max_coalesced_frames > DMA_INTR_THRESHOLD_MASK ||
909 ec->rx_coalesce_usecs > (DMA_TIMEOUT_MASK * 8) + 1)
912 if (ec->rx_coalesce_usecs == 0 && ec->rx_max_coalesced_frames == 0)
915 /* GENET TDMA hardware does not support a configurable timeout, but will
916 * always generate an interrupt either after MBDONE packets have been
917 * transmitted, or when the ring is empty.
920 /* Program all TX queues with the same values, as there is no
921 * ethtool knob to do coalescing on a per-queue basis
923 for (i = 0; i < priv->hw_params->tx_queues; i++)
924 bcmgenet_tdma_ring_writel(priv, i,
925 ec->tx_max_coalesced_frames,
926 DMA_MBUF_DONE_THRESH);
927 bcmgenet_tdma_ring_writel(priv, DESC_INDEX,
928 ec->tx_max_coalesced_frames,
929 DMA_MBUF_DONE_THRESH);
931 for (i = 0; i < priv->hw_params->rx_queues; i++)
932 bcmgenet_set_ring_rx_coalesce(&priv->rx_rings[i], ec);
933 bcmgenet_set_ring_rx_coalesce(&priv->rx_rings[DESC_INDEX], ec);
938 static void bcmgenet_get_pauseparam(struct net_device *dev,
939 struct ethtool_pauseparam *epause)
941 struct bcmgenet_priv *priv;
944 priv = netdev_priv(dev);
946 epause->autoneg = priv->autoneg_pause;
948 if (netif_carrier_ok(dev)) {
949 /* report active state when link is up */
950 umac_cmd = bcmgenet_umac_readl(priv, UMAC_CMD);
951 epause->tx_pause = !(umac_cmd & CMD_TX_PAUSE_IGNORE);
952 epause->rx_pause = !(umac_cmd & CMD_RX_PAUSE_IGNORE);
954 /* otherwise report stored settings */
955 epause->tx_pause = priv->tx_pause;
956 epause->rx_pause = priv->rx_pause;
960 static int bcmgenet_set_pauseparam(struct net_device *dev,
961 struct ethtool_pauseparam *epause)
963 struct bcmgenet_priv *priv = netdev_priv(dev);
968 if (!phy_validate_pause(dev->phydev, epause))
971 priv->autoneg_pause = !!epause->autoneg;
972 priv->tx_pause = !!epause->tx_pause;
973 priv->rx_pause = !!epause->rx_pause;
975 bcmgenet_phy_pause_set(dev, priv->rx_pause, priv->tx_pause);
980 /* standard ethtool support functions. */
981 enum bcmgenet_stat_type {
982 BCMGENET_STAT_NETDEV = -1,
983 BCMGENET_STAT_MIB_RX,
984 BCMGENET_STAT_MIB_TX,
990 struct bcmgenet_stats {
991 char stat_string[ETH_GSTRING_LEN];
994 enum bcmgenet_stat_type type;
995 /* reg offset from UMAC base for misc counters */
999 #define STAT_NETDEV(m) { \
1000 .stat_string = __stringify(m), \
1001 .stat_sizeof = sizeof(((struct net_device_stats *)0)->m), \
1002 .stat_offset = offsetof(struct net_device_stats, m), \
1003 .type = BCMGENET_STAT_NETDEV, \
1006 #define STAT_GENET_MIB(str, m, _type) { \
1007 .stat_string = str, \
1008 .stat_sizeof = sizeof(((struct bcmgenet_priv *)0)->m), \
1009 .stat_offset = offsetof(struct bcmgenet_priv, m), \
1013 #define STAT_GENET_MIB_RX(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_MIB_RX)
1014 #define STAT_GENET_MIB_TX(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_MIB_TX)
1015 #define STAT_GENET_RUNT(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_RUNT)
1016 #define STAT_GENET_SOFT_MIB(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_SOFT)
1018 #define STAT_GENET_MISC(str, m, offset) { \
1019 .stat_string = str, \
1020 .stat_sizeof = sizeof(((struct bcmgenet_priv *)0)->m), \
1021 .stat_offset = offsetof(struct bcmgenet_priv, m), \
1022 .type = BCMGENET_STAT_MISC, \
1023 .reg_offset = offset, \
1026 #define STAT_GENET_Q(num) \
1027 STAT_GENET_SOFT_MIB("txq" __stringify(num) "_packets", \
1028 tx_rings[num].packets), \
1029 STAT_GENET_SOFT_MIB("txq" __stringify(num) "_bytes", \
1030 tx_rings[num].bytes), \
1031 STAT_GENET_SOFT_MIB("rxq" __stringify(num) "_bytes", \
1032 rx_rings[num].bytes), \
1033 STAT_GENET_SOFT_MIB("rxq" __stringify(num) "_packets", \
1034 rx_rings[num].packets), \
1035 STAT_GENET_SOFT_MIB("rxq" __stringify(num) "_errors", \
1036 rx_rings[num].errors), \
1037 STAT_GENET_SOFT_MIB("rxq" __stringify(num) "_dropped", \
1038 rx_rings[num].dropped)
1040 /* There is a 0xC gap between the end of RX and beginning of TX stats and then
1041 * between the end of TX stats and the beginning of the RX RUNT
1043 #define BCMGENET_STAT_OFFSET 0xc
1045 /* Hardware counters must be kept in sync because the order/offset
1046 * is important here (order in structure declaration = order in hardware)
1048 static const struct bcmgenet_stats bcmgenet_gstrings_stats[] = {
1050 STAT_NETDEV(rx_packets),
1051 STAT_NETDEV(tx_packets),
1052 STAT_NETDEV(rx_bytes),
1053 STAT_NETDEV(tx_bytes),
1054 STAT_NETDEV(rx_errors),
1055 STAT_NETDEV(tx_errors),
1056 STAT_NETDEV(rx_dropped),
1057 STAT_NETDEV(tx_dropped),
1058 STAT_NETDEV(multicast),
1059 /* UniMAC RSV counters */
1060 STAT_GENET_MIB_RX("rx_64_octets", mib.rx.pkt_cnt.cnt_64),
1061 STAT_GENET_MIB_RX("rx_65_127_oct", mib.rx.pkt_cnt.cnt_127),
1062 STAT_GENET_MIB_RX("rx_128_255_oct", mib.rx.pkt_cnt.cnt_255),
1063 STAT_GENET_MIB_RX("rx_256_511_oct", mib.rx.pkt_cnt.cnt_511),
1064 STAT_GENET_MIB_RX("rx_512_1023_oct", mib.rx.pkt_cnt.cnt_1023),
1065 STAT_GENET_MIB_RX("rx_1024_1518_oct", mib.rx.pkt_cnt.cnt_1518),
1066 STAT_GENET_MIB_RX("rx_vlan_1519_1522_oct", mib.rx.pkt_cnt.cnt_mgv),
1067 STAT_GENET_MIB_RX("rx_1522_2047_oct", mib.rx.pkt_cnt.cnt_2047),
1068 STAT_GENET_MIB_RX("rx_2048_4095_oct", mib.rx.pkt_cnt.cnt_4095),
1069 STAT_GENET_MIB_RX("rx_4096_9216_oct", mib.rx.pkt_cnt.cnt_9216),
1070 STAT_GENET_MIB_RX("rx_pkts", mib.rx.pkt),
1071 STAT_GENET_MIB_RX("rx_bytes", mib.rx.bytes),
1072 STAT_GENET_MIB_RX("rx_multicast", mib.rx.mca),
1073 STAT_GENET_MIB_RX("rx_broadcast", mib.rx.bca),
1074 STAT_GENET_MIB_RX("rx_fcs", mib.rx.fcs),
1075 STAT_GENET_MIB_RX("rx_control", mib.rx.cf),
1076 STAT_GENET_MIB_RX("rx_pause", mib.rx.pf),
1077 STAT_GENET_MIB_RX("rx_unknown", mib.rx.uo),
1078 STAT_GENET_MIB_RX("rx_align", mib.rx.aln),
1079 STAT_GENET_MIB_RX("rx_outrange", mib.rx.flr),
1080 STAT_GENET_MIB_RX("rx_code", mib.rx.cde),
1081 STAT_GENET_MIB_RX("rx_carrier", mib.rx.fcr),
1082 STAT_GENET_MIB_RX("rx_oversize", mib.rx.ovr),
1083 STAT_GENET_MIB_RX("rx_jabber", mib.rx.jbr),
1084 STAT_GENET_MIB_RX("rx_mtu_err", mib.rx.mtue),
1085 STAT_GENET_MIB_RX("rx_good_pkts", mib.rx.pok),
1086 STAT_GENET_MIB_RX("rx_unicast", mib.rx.uc),
1087 STAT_GENET_MIB_RX("rx_ppp", mib.rx.ppp),
1088 STAT_GENET_MIB_RX("rx_crc", mib.rx.rcrc),
1089 /* UniMAC TSV counters */
1090 STAT_GENET_MIB_TX("tx_64_octets", mib.tx.pkt_cnt.cnt_64),
1091 STAT_GENET_MIB_TX("tx_65_127_oct", mib.tx.pkt_cnt.cnt_127),
1092 STAT_GENET_MIB_TX("tx_128_255_oct", mib.tx.pkt_cnt.cnt_255),
1093 STAT_GENET_MIB_TX("tx_256_511_oct", mib.tx.pkt_cnt.cnt_511),
1094 STAT_GENET_MIB_TX("tx_512_1023_oct", mib.tx.pkt_cnt.cnt_1023),
1095 STAT_GENET_MIB_TX("tx_1024_1518_oct", mib.tx.pkt_cnt.cnt_1518),
1096 STAT_GENET_MIB_TX("tx_vlan_1519_1522_oct", mib.tx.pkt_cnt.cnt_mgv),
1097 STAT_GENET_MIB_TX("tx_1522_2047_oct", mib.tx.pkt_cnt.cnt_2047),
1098 STAT_GENET_MIB_TX("tx_2048_4095_oct", mib.tx.pkt_cnt.cnt_4095),
1099 STAT_GENET_MIB_TX("tx_4096_9216_oct", mib.tx.pkt_cnt.cnt_9216),
1100 STAT_GENET_MIB_TX("tx_pkts", mib.tx.pkts),
1101 STAT_GENET_MIB_TX("tx_multicast", mib.tx.mca),
1102 STAT_GENET_MIB_TX("tx_broadcast", mib.tx.bca),
1103 STAT_GENET_MIB_TX("tx_pause", mib.tx.pf),
1104 STAT_GENET_MIB_TX("tx_control", mib.tx.cf),
1105 STAT_GENET_MIB_TX("tx_fcs_err", mib.tx.fcs),
1106 STAT_GENET_MIB_TX("tx_oversize", mib.tx.ovr),
1107 STAT_GENET_MIB_TX("tx_defer", mib.tx.drf),
1108 STAT_GENET_MIB_TX("tx_excess_defer", mib.tx.edf),
1109 STAT_GENET_MIB_TX("tx_single_col", mib.tx.scl),
1110 STAT_GENET_MIB_TX("tx_multi_col", mib.tx.mcl),
1111 STAT_GENET_MIB_TX("tx_late_col", mib.tx.lcl),
1112 STAT_GENET_MIB_TX("tx_excess_col", mib.tx.ecl),
1113 STAT_GENET_MIB_TX("tx_frags", mib.tx.frg),
1114 STAT_GENET_MIB_TX("tx_total_col", mib.tx.ncl),
1115 STAT_GENET_MIB_TX("tx_jabber", mib.tx.jbr),
1116 STAT_GENET_MIB_TX("tx_bytes", mib.tx.bytes),
1117 STAT_GENET_MIB_TX("tx_good_pkts", mib.tx.pok),
1118 STAT_GENET_MIB_TX("tx_unicast", mib.tx.uc),
1119 /* UniMAC RUNT counters */
1120 STAT_GENET_RUNT("rx_runt_pkts", mib.rx_runt_cnt),
1121 STAT_GENET_RUNT("rx_runt_valid_fcs", mib.rx_runt_fcs),
1122 STAT_GENET_RUNT("rx_runt_inval_fcs_align", mib.rx_runt_fcs_align),
1123 STAT_GENET_RUNT("rx_runt_bytes", mib.rx_runt_bytes),
1124 /* Misc UniMAC counters */
1125 STAT_GENET_MISC("rbuf_ovflow_cnt", mib.rbuf_ovflow_cnt,
1126 UMAC_RBUF_OVFL_CNT_V1),
1127 STAT_GENET_MISC("rbuf_err_cnt", mib.rbuf_err_cnt,
1128 UMAC_RBUF_ERR_CNT_V1),
1129 STAT_GENET_MISC("mdf_err_cnt", mib.mdf_err_cnt, UMAC_MDF_ERR_CNT),
1130 STAT_GENET_SOFT_MIB("alloc_rx_buff_failed", mib.alloc_rx_buff_failed),
1131 STAT_GENET_SOFT_MIB("rx_dma_failed", mib.rx_dma_failed),
1132 STAT_GENET_SOFT_MIB("tx_dma_failed", mib.tx_dma_failed),
1133 STAT_GENET_SOFT_MIB("tx_realloc_tsb", mib.tx_realloc_tsb),
1134 STAT_GENET_SOFT_MIB("tx_realloc_tsb_failed",
1135 mib.tx_realloc_tsb_failed),
1144 #define BCMGENET_STATS_LEN ARRAY_SIZE(bcmgenet_gstrings_stats)
1146 static void bcmgenet_get_drvinfo(struct net_device *dev,
1147 struct ethtool_drvinfo *info)
1149 strlcpy(info->driver, "bcmgenet", sizeof(info->driver));
1152 static int bcmgenet_get_sset_count(struct net_device *dev, int string_set)
1154 switch (string_set) {
1156 return BCMGENET_STATS_LEN;
1162 static void bcmgenet_get_strings(struct net_device *dev, u32 stringset,
1167 switch (stringset) {
1169 for (i = 0; i < BCMGENET_STATS_LEN; i++) {
1170 memcpy(data + i * ETH_GSTRING_LEN,
1171 bcmgenet_gstrings_stats[i].stat_string,
1178 static u32 bcmgenet_update_stat_misc(struct bcmgenet_priv *priv, u16 offset)
1184 case UMAC_RBUF_OVFL_CNT_V1:
1185 if (GENET_IS_V2(priv))
1186 new_offset = RBUF_OVFL_CNT_V2;
1188 new_offset = RBUF_OVFL_CNT_V3PLUS;
1190 val = bcmgenet_rbuf_readl(priv, new_offset);
1191 /* clear if overflowed */
1193 bcmgenet_rbuf_writel(priv, 0, new_offset);
1195 case UMAC_RBUF_ERR_CNT_V1:
1196 if (GENET_IS_V2(priv))
1197 new_offset = RBUF_ERR_CNT_V2;
1199 new_offset = RBUF_ERR_CNT_V3PLUS;
1201 val = bcmgenet_rbuf_readl(priv, new_offset);
1202 /* clear if overflowed */
1204 bcmgenet_rbuf_writel(priv, 0, new_offset);
1207 val = bcmgenet_umac_readl(priv, offset);
1208 /* clear if overflowed */
1210 bcmgenet_umac_writel(priv, 0, offset);
1217 static void bcmgenet_update_mib_counters(struct bcmgenet_priv *priv)
1221 for (i = 0; i < BCMGENET_STATS_LEN; i++) {
1222 const struct bcmgenet_stats *s;
1227 s = &bcmgenet_gstrings_stats[i];
1229 case BCMGENET_STAT_NETDEV:
1230 case BCMGENET_STAT_SOFT:
1232 case BCMGENET_STAT_RUNT:
1233 offset += BCMGENET_STAT_OFFSET;
1235 case BCMGENET_STAT_MIB_TX:
1236 offset += BCMGENET_STAT_OFFSET;
1238 case BCMGENET_STAT_MIB_RX:
1239 val = bcmgenet_umac_readl(priv,
1240 UMAC_MIB_START + j + offset);
1241 offset = 0; /* Reset Offset */
1243 case BCMGENET_STAT_MISC:
1244 if (GENET_IS_V1(priv)) {
1245 val = bcmgenet_umac_readl(priv, s->reg_offset);
1246 /* clear if overflowed */
1248 bcmgenet_umac_writel(priv, 0,
1251 val = bcmgenet_update_stat_misc(priv,
1257 j += s->stat_sizeof;
1258 p = (char *)priv + s->stat_offset;
1263 static void bcmgenet_get_ethtool_stats(struct net_device *dev,
1264 struct ethtool_stats *stats,
1267 struct bcmgenet_priv *priv = netdev_priv(dev);
1270 if (netif_running(dev))
1271 bcmgenet_update_mib_counters(priv);
1273 dev->netdev_ops->ndo_get_stats(dev);
1275 for (i = 0; i < BCMGENET_STATS_LEN; i++) {
1276 const struct bcmgenet_stats *s;
1279 s = &bcmgenet_gstrings_stats[i];
1280 if (s->type == BCMGENET_STAT_NETDEV)
1281 p = (char *)&dev->stats;
1284 p += s->stat_offset;
1285 if (sizeof(unsigned long) != sizeof(u32) &&
1286 s->stat_sizeof == sizeof(unsigned long))
1287 data[i] = *(unsigned long *)p;
1289 data[i] = *(u32 *)p;
1293 static void bcmgenet_eee_enable_set(struct net_device *dev, bool enable)
1295 struct bcmgenet_priv *priv = netdev_priv(dev);
1296 u32 off = priv->hw_params->tbuf_offset + TBUF_ENERGY_CTRL;
1299 if (enable && !priv->clk_eee_enabled) {
1300 clk_prepare_enable(priv->clk_eee);
1301 priv->clk_eee_enabled = true;
1304 reg = bcmgenet_umac_readl(priv, UMAC_EEE_CTRL);
1309 bcmgenet_umac_writel(priv, reg, UMAC_EEE_CTRL);
1311 /* Enable EEE and switch to a 27Mhz clock automatically */
1312 reg = bcmgenet_readl(priv->base + off);
1314 reg |= TBUF_EEE_EN | TBUF_PM_EN;
1316 reg &= ~(TBUF_EEE_EN | TBUF_PM_EN);
1317 bcmgenet_writel(reg, priv->base + off);
1319 /* Do the same for thing for RBUF */
1320 reg = bcmgenet_rbuf_readl(priv, RBUF_ENERGY_CTRL);
1322 reg |= RBUF_EEE_EN | RBUF_PM_EN;
1324 reg &= ~(RBUF_EEE_EN | RBUF_PM_EN);
1325 bcmgenet_rbuf_writel(priv, reg, RBUF_ENERGY_CTRL);
1327 if (!enable && priv->clk_eee_enabled) {
1328 clk_disable_unprepare(priv->clk_eee);
1329 priv->clk_eee_enabled = false;
1332 priv->eee.eee_enabled = enable;
1333 priv->eee.eee_active = enable;
1336 static int bcmgenet_get_eee(struct net_device *dev, struct ethtool_eee *e)
1338 struct bcmgenet_priv *priv = netdev_priv(dev);
1339 struct ethtool_eee *p = &priv->eee;
1341 if (GENET_IS_V1(priv))
1347 e->eee_enabled = p->eee_enabled;
1348 e->eee_active = p->eee_active;
1349 e->tx_lpi_timer = bcmgenet_umac_readl(priv, UMAC_EEE_LPI_TIMER);
1351 return phy_ethtool_get_eee(dev->phydev, e);
1354 static int bcmgenet_set_eee(struct net_device *dev, struct ethtool_eee *e)
1356 struct bcmgenet_priv *priv = netdev_priv(dev);
1357 struct ethtool_eee *p = &priv->eee;
1360 if (GENET_IS_V1(priv))
1366 p->eee_enabled = e->eee_enabled;
1368 if (!p->eee_enabled) {
1369 bcmgenet_eee_enable_set(dev, false);
1371 ret = phy_init_eee(dev->phydev, 0);
1373 netif_err(priv, hw, dev, "EEE initialization failed\n");
1377 bcmgenet_umac_writel(priv, e->tx_lpi_timer, UMAC_EEE_LPI_TIMER);
1378 bcmgenet_eee_enable_set(dev, true);
1381 return phy_ethtool_set_eee(dev->phydev, e);
1384 static int bcmgenet_validate_flow(struct net_device *dev,
1385 struct ethtool_rxnfc *cmd)
1387 struct ethtool_usrip4_spec *l4_mask;
1388 struct ethhdr *eth_mask;
1390 if (cmd->fs.location >= MAX_NUM_OF_FS_RULES) {
1391 netdev_err(dev, "rxnfc: Invalid location (%d)\n",
1396 switch (cmd->fs.flow_type & ~(FLOW_EXT | FLOW_MAC_EXT)) {
1398 l4_mask = &cmd->fs.m_u.usr_ip4_spec;
1399 /* don't allow mask which isn't valid */
1400 if (VALIDATE_MASK(l4_mask->ip4src) ||
1401 VALIDATE_MASK(l4_mask->ip4dst) ||
1402 VALIDATE_MASK(l4_mask->l4_4_bytes) ||
1403 VALIDATE_MASK(l4_mask->proto) ||
1404 VALIDATE_MASK(l4_mask->ip_ver) ||
1405 VALIDATE_MASK(l4_mask->tos)) {
1406 netdev_err(dev, "rxnfc: Unsupported mask\n");
1411 eth_mask = &cmd->fs.m_u.ether_spec;
1412 /* don't allow mask which isn't valid */
1413 if (VALIDATE_MASK(eth_mask->h_dest) ||
1414 VALIDATE_MASK(eth_mask->h_source) ||
1415 VALIDATE_MASK(eth_mask->h_proto)) {
1416 netdev_err(dev, "rxnfc: Unsupported mask\n");
1421 netdev_err(dev, "rxnfc: Unsupported flow type (0x%x)\n",
1426 if ((cmd->fs.flow_type & FLOW_EXT)) {
1427 /* don't allow mask which isn't valid */
1428 if (VALIDATE_MASK(cmd->fs.m_ext.vlan_etype) ||
1429 VALIDATE_MASK(cmd->fs.m_ext.vlan_tci)) {
1430 netdev_err(dev, "rxnfc: Unsupported mask\n");
1433 if (cmd->fs.m_ext.data[0] || cmd->fs.m_ext.data[1]) {
1434 netdev_err(dev, "rxnfc: user-def not supported\n");
1439 if ((cmd->fs.flow_type & FLOW_MAC_EXT)) {
1440 /* don't allow mask which isn't valid */
1441 if (VALIDATE_MASK(cmd->fs.m_ext.h_dest)) {
1442 netdev_err(dev, "rxnfc: Unsupported mask\n");
1450 static int bcmgenet_insert_flow(struct net_device *dev,
1451 struct ethtool_rxnfc *cmd)
1453 struct bcmgenet_priv *priv = netdev_priv(dev);
1454 struct bcmgenet_rxnfc_rule *loc_rule;
1457 if (priv->hw_params->hfb_filter_size < 128) {
1458 netdev_err(dev, "rxnfc: Not supported by this device\n");
1462 if (cmd->fs.ring_cookie > priv->hw_params->rx_queues &&
1463 cmd->fs.ring_cookie != RX_CLS_FLOW_WAKE) {
1464 netdev_err(dev, "rxnfc: Unsupported action (%llu)\n",
1465 cmd->fs.ring_cookie);
1469 err = bcmgenet_validate_flow(dev, cmd);
1473 loc_rule = &priv->rxnfc_rules[cmd->fs.location];
1474 if (loc_rule->state == BCMGENET_RXNFC_STATE_ENABLED)
1475 bcmgenet_hfb_disable_filter(priv, cmd->fs.location);
1476 if (loc_rule->state != BCMGENET_RXNFC_STATE_UNUSED) {
1477 list_del(&loc_rule->list);
1478 bcmgenet_hfb_clear_filter(priv, cmd->fs.location);
1480 loc_rule->state = BCMGENET_RXNFC_STATE_UNUSED;
1481 memcpy(&loc_rule->fs, &cmd->fs,
1482 sizeof(struct ethtool_rx_flow_spec));
1484 bcmgenet_hfb_create_rxnfc_filter(priv, loc_rule);
1486 list_add_tail(&loc_rule->list, &priv->rxnfc_list);
1491 static int bcmgenet_delete_flow(struct net_device *dev,
1492 struct ethtool_rxnfc *cmd)
1494 struct bcmgenet_priv *priv = netdev_priv(dev);
1495 struct bcmgenet_rxnfc_rule *rule;
1498 if (cmd->fs.location >= MAX_NUM_OF_FS_RULES)
1501 rule = &priv->rxnfc_rules[cmd->fs.location];
1502 if (rule->state == BCMGENET_RXNFC_STATE_UNUSED) {
1507 if (rule->state == BCMGENET_RXNFC_STATE_ENABLED)
1508 bcmgenet_hfb_disable_filter(priv, cmd->fs.location);
1509 if (rule->state != BCMGENET_RXNFC_STATE_UNUSED) {
1510 list_del(&rule->list);
1511 bcmgenet_hfb_clear_filter(priv, cmd->fs.location);
1513 rule->state = BCMGENET_RXNFC_STATE_UNUSED;
1514 memset(&rule->fs, 0, sizeof(struct ethtool_rx_flow_spec));
1520 static int bcmgenet_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd)
1522 struct bcmgenet_priv *priv = netdev_priv(dev);
1526 case ETHTOOL_SRXCLSRLINS:
1527 err = bcmgenet_insert_flow(dev, cmd);
1529 case ETHTOOL_SRXCLSRLDEL:
1530 err = bcmgenet_delete_flow(dev, cmd);
1533 netdev_warn(priv->dev, "Unsupported ethtool command. (%d)\n",
1541 static int bcmgenet_get_flow(struct net_device *dev, struct ethtool_rxnfc *cmd,
1544 struct bcmgenet_priv *priv = netdev_priv(dev);
1545 struct bcmgenet_rxnfc_rule *rule;
1548 if (loc < 0 || loc >= MAX_NUM_OF_FS_RULES)
1551 rule = &priv->rxnfc_rules[loc];
1552 if (rule->state == BCMGENET_RXNFC_STATE_UNUSED)
1555 memcpy(&cmd->fs, &rule->fs,
1556 sizeof(struct ethtool_rx_flow_spec));
1561 static int bcmgenet_get_num_flows(struct bcmgenet_priv *priv)
1563 struct list_head *pos;
1566 list_for_each(pos, &priv->rxnfc_list)
1572 static int bcmgenet_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd,
1575 struct bcmgenet_priv *priv = netdev_priv(dev);
1576 struct bcmgenet_rxnfc_rule *rule;
1581 case ETHTOOL_GRXRINGS:
1582 cmd->data = priv->hw_params->rx_queues ?: 1;
1584 case ETHTOOL_GRXCLSRLCNT:
1585 cmd->rule_cnt = bcmgenet_get_num_flows(priv);
1586 cmd->data = MAX_NUM_OF_FS_RULES;
1588 case ETHTOOL_GRXCLSRULE:
1589 err = bcmgenet_get_flow(dev, cmd, cmd->fs.location);
1591 case ETHTOOL_GRXCLSRLALL:
1592 list_for_each_entry(rule, &priv->rxnfc_list, list)
1593 if (i < cmd->rule_cnt)
1594 rule_locs[i++] = rule->fs.location;
1596 cmd->data = MAX_NUM_OF_FS_RULES;
1606 /* standard ethtool support functions. */
1607 static const struct ethtool_ops bcmgenet_ethtool_ops = {
1608 .supported_coalesce_params = ETHTOOL_COALESCE_RX_USECS |
1609 ETHTOOL_COALESCE_MAX_FRAMES |
1610 ETHTOOL_COALESCE_USE_ADAPTIVE_RX,
1611 .begin = bcmgenet_begin,
1612 .complete = bcmgenet_complete,
1613 .get_strings = bcmgenet_get_strings,
1614 .get_sset_count = bcmgenet_get_sset_count,
1615 .get_ethtool_stats = bcmgenet_get_ethtool_stats,
1616 .get_drvinfo = bcmgenet_get_drvinfo,
1617 .get_link = ethtool_op_get_link,
1618 .get_msglevel = bcmgenet_get_msglevel,
1619 .set_msglevel = bcmgenet_set_msglevel,
1620 .get_wol = bcmgenet_get_wol,
1621 .set_wol = bcmgenet_set_wol,
1622 .get_eee = bcmgenet_get_eee,
1623 .set_eee = bcmgenet_set_eee,
1624 .nway_reset = phy_ethtool_nway_reset,
1625 .get_coalesce = bcmgenet_get_coalesce,
1626 .set_coalesce = bcmgenet_set_coalesce,
1627 .get_link_ksettings = bcmgenet_get_link_ksettings,
1628 .set_link_ksettings = bcmgenet_set_link_ksettings,
1629 .get_ts_info = ethtool_op_get_ts_info,
1630 .get_rxnfc = bcmgenet_get_rxnfc,
1631 .set_rxnfc = bcmgenet_set_rxnfc,
1632 .get_pauseparam = bcmgenet_get_pauseparam,
1633 .set_pauseparam = bcmgenet_set_pauseparam,
1636 /* Power down the unimac, based on mode. */
1637 static int bcmgenet_power_down(struct bcmgenet_priv *priv,
1638 enum bcmgenet_power_mode mode)
1644 case GENET_POWER_CABLE_SENSE:
1645 phy_detach(priv->dev->phydev);
1648 case GENET_POWER_WOL_MAGIC:
1649 ret = bcmgenet_wol_power_down_cfg(priv, mode);
1652 case GENET_POWER_PASSIVE:
1653 /* Power down LED */
1654 if (priv->hw_params->flags & GENET_HAS_EXT) {
1655 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
1656 if (GENET_IS_V5(priv))
1657 reg |= EXT_PWR_DOWN_PHY_EN |
1658 EXT_PWR_DOWN_PHY_RD |
1659 EXT_PWR_DOWN_PHY_SD |
1660 EXT_PWR_DOWN_PHY_RX |
1661 EXT_PWR_DOWN_PHY_TX |
1664 reg |= EXT_PWR_DOWN_PHY;
1666 reg |= (EXT_PWR_DOWN_DLL | EXT_PWR_DOWN_BIAS);
1667 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
1669 bcmgenet_phy_power_set(priv->dev, false);
1679 static void bcmgenet_power_up(struct bcmgenet_priv *priv,
1680 enum bcmgenet_power_mode mode)
1684 if (!(priv->hw_params->flags & GENET_HAS_EXT))
1687 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
1690 case GENET_POWER_PASSIVE:
1691 reg &= ~(EXT_PWR_DOWN_DLL | EXT_PWR_DOWN_BIAS |
1692 EXT_ENERGY_DET_MASK);
1693 if (GENET_IS_V5(priv)) {
1694 reg &= ~(EXT_PWR_DOWN_PHY_EN |
1695 EXT_PWR_DOWN_PHY_RD |
1696 EXT_PWR_DOWN_PHY_SD |
1697 EXT_PWR_DOWN_PHY_RX |
1698 EXT_PWR_DOWN_PHY_TX |
1700 reg |= EXT_PHY_RESET;
1701 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
1704 reg &= ~EXT_PHY_RESET;
1706 reg &= ~EXT_PWR_DOWN_PHY;
1707 reg |= EXT_PWR_DN_EN_LD;
1709 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
1710 bcmgenet_phy_power_set(priv->dev, true);
1713 case GENET_POWER_CABLE_SENSE:
1715 if (!GENET_IS_V5(priv)) {
1716 reg |= EXT_PWR_DN_EN_LD;
1717 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
1720 case GENET_POWER_WOL_MAGIC:
1721 bcmgenet_wol_power_up_cfg(priv, mode);
1728 static struct enet_cb *bcmgenet_get_txcb(struct bcmgenet_priv *priv,
1729 struct bcmgenet_tx_ring *ring)
1731 struct enet_cb *tx_cb_ptr;
1733 tx_cb_ptr = ring->cbs;
1734 tx_cb_ptr += ring->write_ptr - ring->cb_ptr;
1736 /* Advancing local write pointer */
1737 if (ring->write_ptr == ring->end_ptr)
1738 ring->write_ptr = ring->cb_ptr;
1745 static struct enet_cb *bcmgenet_put_txcb(struct bcmgenet_priv *priv,
1746 struct bcmgenet_tx_ring *ring)
1748 struct enet_cb *tx_cb_ptr;
1750 tx_cb_ptr = ring->cbs;
1751 tx_cb_ptr += ring->write_ptr - ring->cb_ptr;
1753 /* Rewinding local write pointer */
1754 if (ring->write_ptr == ring->cb_ptr)
1755 ring->write_ptr = ring->end_ptr;
1762 static inline void bcmgenet_rx_ring16_int_disable(struct bcmgenet_rx_ring *ring)
1764 bcmgenet_intrl2_0_writel(ring->priv, UMAC_IRQ_RXDMA_DONE,
1765 INTRL2_CPU_MASK_SET);
1768 static inline void bcmgenet_rx_ring16_int_enable(struct bcmgenet_rx_ring *ring)
1770 bcmgenet_intrl2_0_writel(ring->priv, UMAC_IRQ_RXDMA_DONE,
1771 INTRL2_CPU_MASK_CLEAR);
1774 static inline void bcmgenet_rx_ring_int_disable(struct bcmgenet_rx_ring *ring)
1776 bcmgenet_intrl2_1_writel(ring->priv,
1777 1 << (UMAC_IRQ1_RX_INTR_SHIFT + ring->index),
1778 INTRL2_CPU_MASK_SET);
1781 static inline void bcmgenet_rx_ring_int_enable(struct bcmgenet_rx_ring *ring)
1783 bcmgenet_intrl2_1_writel(ring->priv,
1784 1 << (UMAC_IRQ1_RX_INTR_SHIFT + ring->index),
1785 INTRL2_CPU_MASK_CLEAR);
1788 static inline void bcmgenet_tx_ring16_int_disable(struct bcmgenet_tx_ring *ring)
1790 bcmgenet_intrl2_0_writel(ring->priv, UMAC_IRQ_TXDMA_DONE,
1791 INTRL2_CPU_MASK_SET);
1794 static inline void bcmgenet_tx_ring16_int_enable(struct bcmgenet_tx_ring *ring)
1796 bcmgenet_intrl2_0_writel(ring->priv, UMAC_IRQ_TXDMA_DONE,
1797 INTRL2_CPU_MASK_CLEAR);
1800 static inline void bcmgenet_tx_ring_int_enable(struct bcmgenet_tx_ring *ring)
1802 bcmgenet_intrl2_1_writel(ring->priv, 1 << ring->index,
1803 INTRL2_CPU_MASK_CLEAR);
1806 static inline void bcmgenet_tx_ring_int_disable(struct bcmgenet_tx_ring *ring)
1808 bcmgenet_intrl2_1_writel(ring->priv, 1 << ring->index,
1809 INTRL2_CPU_MASK_SET);
1812 /* Simple helper to free a transmit control block's resources
1813 * Returns an skb when the last transmit control block associated with the
1814 * skb is freed. The skb should be freed by the caller if necessary.
1816 static struct sk_buff *bcmgenet_free_tx_cb(struct device *dev,
1819 struct sk_buff *skb;
1825 if (cb == GENET_CB(skb)->first_cb)
1826 dma_unmap_single(dev, dma_unmap_addr(cb, dma_addr),
1827 dma_unmap_len(cb, dma_len),
1830 dma_unmap_page(dev, dma_unmap_addr(cb, dma_addr),
1831 dma_unmap_len(cb, dma_len),
1833 dma_unmap_addr_set(cb, dma_addr, 0);
1835 if (cb == GENET_CB(skb)->last_cb)
1838 } else if (dma_unmap_addr(cb, dma_addr)) {
1840 dma_unmap_addr(cb, dma_addr),
1841 dma_unmap_len(cb, dma_len),
1843 dma_unmap_addr_set(cb, dma_addr, 0);
1849 /* Simple helper to free a receive control block's resources */
1850 static struct sk_buff *bcmgenet_free_rx_cb(struct device *dev,
1853 struct sk_buff *skb;
1858 if (dma_unmap_addr(cb, dma_addr)) {
1859 dma_unmap_single(dev, dma_unmap_addr(cb, dma_addr),
1860 dma_unmap_len(cb, dma_len), DMA_FROM_DEVICE);
1861 dma_unmap_addr_set(cb, dma_addr, 0);
1867 /* Unlocked version of the reclaim routine */
1868 static unsigned int __bcmgenet_tx_reclaim(struct net_device *dev,
1869 struct bcmgenet_tx_ring *ring)
1871 struct bcmgenet_priv *priv = netdev_priv(dev);
1872 unsigned int txbds_processed = 0;
1873 unsigned int bytes_compl = 0;
1874 unsigned int pkts_compl = 0;
1875 unsigned int txbds_ready;
1876 unsigned int c_index;
1877 struct sk_buff *skb;
1879 /* Clear status before servicing to reduce spurious interrupts */
1880 if (ring->index == DESC_INDEX)
1881 bcmgenet_intrl2_0_writel(priv, UMAC_IRQ_TXDMA_DONE,
1884 bcmgenet_intrl2_1_writel(priv, (1 << ring->index),
1887 /* Compute how many buffers are transmitted since last xmit call */
1888 c_index = bcmgenet_tdma_ring_readl(priv, ring->index, TDMA_CONS_INDEX)
1890 txbds_ready = (c_index - ring->c_index) & DMA_C_INDEX_MASK;
1892 netif_dbg(priv, tx_done, dev,
1893 "%s ring=%d old_c_index=%u c_index=%u txbds_ready=%u\n",
1894 __func__, ring->index, ring->c_index, c_index, txbds_ready);
1896 /* Reclaim transmitted buffers */
1897 while (txbds_processed < txbds_ready) {
1898 skb = bcmgenet_free_tx_cb(&priv->pdev->dev,
1899 &priv->tx_cbs[ring->clean_ptr]);
1902 bytes_compl += GENET_CB(skb)->bytes_sent;
1903 dev_consume_skb_any(skb);
1907 if (likely(ring->clean_ptr < ring->end_ptr))
1910 ring->clean_ptr = ring->cb_ptr;
1913 ring->free_bds += txbds_processed;
1914 ring->c_index = c_index;
1916 ring->packets += pkts_compl;
1917 ring->bytes += bytes_compl;
1919 netdev_tx_completed_queue(netdev_get_tx_queue(dev, ring->queue),
1920 pkts_compl, bytes_compl);
1922 return txbds_processed;
1925 static unsigned int bcmgenet_tx_reclaim(struct net_device *dev,
1926 struct bcmgenet_tx_ring *ring)
1928 unsigned int released;
1930 spin_lock_bh(&ring->lock);
1931 released = __bcmgenet_tx_reclaim(dev, ring);
1932 spin_unlock_bh(&ring->lock);
1937 static int bcmgenet_tx_poll(struct napi_struct *napi, int budget)
1939 struct bcmgenet_tx_ring *ring =
1940 container_of(napi, struct bcmgenet_tx_ring, napi);
1941 unsigned int work_done = 0;
1942 struct netdev_queue *txq;
1944 spin_lock(&ring->lock);
1945 work_done = __bcmgenet_tx_reclaim(ring->priv->dev, ring);
1946 if (ring->free_bds > (MAX_SKB_FRAGS + 1)) {
1947 txq = netdev_get_tx_queue(ring->priv->dev, ring->queue);
1948 netif_tx_wake_queue(txq);
1950 spin_unlock(&ring->lock);
1952 if (work_done == 0) {
1953 napi_complete(napi);
1954 ring->int_enable(ring);
1962 static void bcmgenet_tx_reclaim_all(struct net_device *dev)
1964 struct bcmgenet_priv *priv = netdev_priv(dev);
1967 if (netif_is_multiqueue(dev)) {
1968 for (i = 0; i < priv->hw_params->tx_queues; i++)
1969 bcmgenet_tx_reclaim(dev, &priv->tx_rings[i]);
1972 bcmgenet_tx_reclaim(dev, &priv->tx_rings[DESC_INDEX]);
1975 /* Reallocate the SKB to put enough headroom in front of it and insert
1976 * the transmit checksum offsets in the descriptors
1978 static struct sk_buff *bcmgenet_add_tsb(struct net_device *dev,
1979 struct sk_buff *skb)
1981 struct bcmgenet_priv *priv = netdev_priv(dev);
1982 struct status_64 *status = NULL;
1983 struct sk_buff *new_skb;
1989 if (unlikely(skb_headroom(skb) < sizeof(*status))) {
1990 /* If 64 byte status block enabled, must make sure skb has
1991 * enough headroom for us to insert 64B status block.
1993 new_skb = skb_realloc_headroom(skb, sizeof(*status));
1995 dev_kfree_skb_any(skb);
1996 priv->mib.tx_realloc_tsb_failed++;
1997 dev->stats.tx_dropped++;
2000 dev_consume_skb_any(skb);
2002 priv->mib.tx_realloc_tsb++;
2005 skb_push(skb, sizeof(*status));
2006 status = (struct status_64 *)skb->data;
2008 if (skb->ip_summed == CHECKSUM_PARTIAL) {
2009 ip_ver = skb->protocol;
2011 case htons(ETH_P_IP):
2012 ip_proto = ip_hdr(skb)->protocol;
2014 case htons(ETH_P_IPV6):
2015 ip_proto = ipv6_hdr(skb)->nexthdr;
2018 /* don't use UDP flag */
2023 offset = skb_checksum_start_offset(skb) - sizeof(*status);
2024 tx_csum_info = (offset << STATUS_TX_CSUM_START_SHIFT) |
2025 (offset + skb->csum_offset) |
2028 /* Set the special UDP flag for UDP */
2029 if (ip_proto == IPPROTO_UDP)
2030 tx_csum_info |= STATUS_TX_CSUM_PROTO_UDP;
2032 status->tx_csum_info = tx_csum_info;
2038 static netdev_tx_t bcmgenet_xmit(struct sk_buff *skb, struct net_device *dev)
2040 struct bcmgenet_priv *priv = netdev_priv(dev);
2041 struct device *kdev = &priv->pdev->dev;
2042 struct bcmgenet_tx_ring *ring = NULL;
2043 struct enet_cb *tx_cb_ptr;
2044 struct netdev_queue *txq;
2045 int nr_frags, index;
2053 index = skb_get_queue_mapping(skb);
2054 /* Mapping strategy:
2055 * queue_mapping = 0, unclassified, packet xmited through ring16
2056 * queue_mapping = 1, goes to ring 0. (highest priority queue
2057 * queue_mapping = 2, goes to ring 1.
2058 * queue_mapping = 3, goes to ring 2.
2059 * queue_mapping = 4, goes to ring 3.
2066 ring = &priv->tx_rings[index];
2067 txq = netdev_get_tx_queue(dev, ring->queue);
2069 nr_frags = skb_shinfo(skb)->nr_frags;
2071 spin_lock(&ring->lock);
2072 if (ring->free_bds <= (nr_frags + 1)) {
2073 if (!netif_tx_queue_stopped(txq)) {
2074 netif_tx_stop_queue(txq);
2076 "%s: tx ring %d full when queue %d awake\n",
2077 __func__, index, ring->queue);
2079 ret = NETDEV_TX_BUSY;
2083 /* Retain how many bytes will be sent on the wire, without TSB inserted
2084 * by transmit checksum offload
2086 GENET_CB(skb)->bytes_sent = skb->len;
2088 /* add the Transmit Status Block */
2089 skb = bcmgenet_add_tsb(dev, skb);
2095 for (i = 0; i <= nr_frags; i++) {
2096 tx_cb_ptr = bcmgenet_get_txcb(priv, ring);
2101 /* Transmit single SKB or head of fragment list */
2102 GENET_CB(skb)->first_cb = tx_cb_ptr;
2103 size = skb_headlen(skb);
2104 mapping = dma_map_single(kdev, skb->data, size,
2108 frag = &skb_shinfo(skb)->frags[i - 1];
2109 size = skb_frag_size(frag);
2110 mapping = skb_frag_dma_map(kdev, frag, 0, size,
2114 ret = dma_mapping_error(kdev, mapping);
2116 priv->mib.tx_dma_failed++;
2117 netif_err(priv, tx_err, dev, "Tx DMA map failed\n");
2119 goto out_unmap_frags;
2121 dma_unmap_addr_set(tx_cb_ptr, dma_addr, mapping);
2122 dma_unmap_len_set(tx_cb_ptr, dma_len, size);
2124 tx_cb_ptr->skb = skb;
2126 len_stat = (size << DMA_BUFLENGTH_SHIFT) |
2127 (priv->hw_params->qtag_mask << DMA_TX_QTAG_SHIFT);
2129 /* Note: if we ever change from DMA_TX_APPEND_CRC below we
2130 * will need to restore software padding of "runt" packets
2133 len_stat |= DMA_TX_APPEND_CRC | DMA_SOP;
2134 if (skb->ip_summed == CHECKSUM_PARTIAL)
2135 len_stat |= DMA_TX_DO_CSUM;
2138 len_stat |= DMA_EOP;
2140 dmadesc_set(priv, tx_cb_ptr->bd_addr, mapping, len_stat);
2143 GENET_CB(skb)->last_cb = tx_cb_ptr;
2144 skb_tx_timestamp(skb);
2146 /* Decrement total BD count and advance our write pointer */
2147 ring->free_bds -= nr_frags + 1;
2148 ring->prod_index += nr_frags + 1;
2149 ring->prod_index &= DMA_P_INDEX_MASK;
2151 netdev_tx_sent_queue(txq, GENET_CB(skb)->bytes_sent);
2153 if (ring->free_bds <= (MAX_SKB_FRAGS + 1))
2154 netif_tx_stop_queue(txq);
2156 if (!netdev_xmit_more() || netif_xmit_stopped(txq))
2157 /* Packets are ready, update producer index */
2158 bcmgenet_tdma_ring_writel(priv, ring->index,
2159 ring->prod_index, TDMA_PROD_INDEX);
2161 spin_unlock(&ring->lock);
2166 /* Back up for failed control block mapping */
2167 bcmgenet_put_txcb(priv, ring);
2169 /* Unmap successfully mapped control blocks */
2171 tx_cb_ptr = bcmgenet_put_txcb(priv, ring);
2172 bcmgenet_free_tx_cb(kdev, tx_cb_ptr);
2179 static struct sk_buff *bcmgenet_rx_refill(struct bcmgenet_priv *priv,
2182 struct device *kdev = &priv->pdev->dev;
2183 struct sk_buff *skb;
2184 struct sk_buff *rx_skb;
2187 /* Allocate a new Rx skb */
2188 skb = __netdev_alloc_skb(priv->dev, priv->rx_buf_len + SKB_ALIGNMENT,
2189 GFP_ATOMIC | __GFP_NOWARN);
2191 priv->mib.alloc_rx_buff_failed++;
2192 netif_err(priv, rx_err, priv->dev,
2193 "%s: Rx skb allocation failed\n", __func__);
2197 /* DMA-map the new Rx skb */
2198 mapping = dma_map_single(kdev, skb->data, priv->rx_buf_len,
2200 if (dma_mapping_error(kdev, mapping)) {
2201 priv->mib.rx_dma_failed++;
2202 dev_kfree_skb_any(skb);
2203 netif_err(priv, rx_err, priv->dev,
2204 "%s: Rx skb DMA mapping failed\n", __func__);
2208 /* Grab the current Rx skb from the ring and DMA-unmap it */
2209 rx_skb = bcmgenet_free_rx_cb(kdev, cb);
2211 /* Put the new Rx skb on the ring */
2213 dma_unmap_addr_set(cb, dma_addr, mapping);
2214 dma_unmap_len_set(cb, dma_len, priv->rx_buf_len);
2215 dmadesc_set_addr(priv, cb->bd_addr, mapping);
2217 /* Return the current Rx skb to caller */
2221 /* bcmgenet_desc_rx - descriptor based rx process.
2222 * this could be called from bottom half, or from NAPI polling method.
2224 static unsigned int bcmgenet_desc_rx(struct bcmgenet_rx_ring *ring,
2225 unsigned int budget)
2227 struct bcmgenet_priv *priv = ring->priv;
2228 struct net_device *dev = priv->dev;
2230 struct sk_buff *skb;
2231 u32 dma_length_status;
2232 unsigned long dma_flag;
2234 unsigned int rxpktprocessed = 0, rxpkttoprocess;
2235 unsigned int bytes_processed = 0;
2236 unsigned int p_index, mask;
2237 unsigned int discards;
2239 /* Clear status before servicing to reduce spurious interrupts */
2240 if (ring->index == DESC_INDEX) {
2241 bcmgenet_intrl2_0_writel(priv, UMAC_IRQ_RXDMA_DONE,
2244 mask = 1 << (UMAC_IRQ1_RX_INTR_SHIFT + ring->index);
2245 bcmgenet_intrl2_1_writel(priv,
2250 p_index = bcmgenet_rdma_ring_readl(priv, ring->index, RDMA_PROD_INDEX);
2252 discards = (p_index >> DMA_P_INDEX_DISCARD_CNT_SHIFT) &
2253 DMA_P_INDEX_DISCARD_CNT_MASK;
2254 if (discards > ring->old_discards) {
2255 discards = discards - ring->old_discards;
2256 ring->errors += discards;
2257 ring->old_discards += discards;
2259 /* Clear HW register when we reach 75% of maximum 0xFFFF */
2260 if (ring->old_discards >= 0xC000) {
2261 ring->old_discards = 0;
2262 bcmgenet_rdma_ring_writel(priv, ring->index, 0,
2267 p_index &= DMA_P_INDEX_MASK;
2268 rxpkttoprocess = (p_index - ring->c_index) & DMA_C_INDEX_MASK;
2270 netif_dbg(priv, rx_status, dev,
2271 "RDMA: rxpkttoprocess=%d\n", rxpkttoprocess);
2273 while ((rxpktprocessed < rxpkttoprocess) &&
2274 (rxpktprocessed < budget)) {
2275 struct status_64 *status;
2278 cb = &priv->rx_cbs[ring->read_ptr];
2279 skb = bcmgenet_rx_refill(priv, cb);
2281 if (unlikely(!skb)) {
2286 status = (struct status_64 *)skb->data;
2287 dma_length_status = status->length_status;
2288 if (dev->features & NETIF_F_RXCSUM) {
2289 rx_csum = (__force __be16)(status->rx_csum & 0xffff);
2290 skb->csum = (__force __wsum)ntohs(rx_csum);
2291 skb->ip_summed = CHECKSUM_COMPLETE;
2294 /* DMA flags and length are still valid no matter how
2295 * we got the Receive Status Vector (64B RSB or register)
2297 dma_flag = dma_length_status & 0xffff;
2298 len = dma_length_status >> DMA_BUFLENGTH_SHIFT;
2300 netif_dbg(priv, rx_status, dev,
2301 "%s:p_ind=%d c_ind=%d read_ptr=%d len_stat=0x%08x\n",
2302 __func__, p_index, ring->c_index,
2303 ring->read_ptr, dma_length_status);
2305 if (unlikely(!(dma_flag & DMA_EOP) || !(dma_flag & DMA_SOP))) {
2306 netif_err(priv, rx_status, dev,
2307 "dropping fragmented packet!\n");
2309 dev_kfree_skb_any(skb);
2314 if (unlikely(dma_flag & (DMA_RX_CRC_ERROR |
2319 netif_err(priv, rx_status, dev, "dma_flag=0x%x\n",
2320 (unsigned int)dma_flag);
2321 if (dma_flag & DMA_RX_CRC_ERROR)
2322 dev->stats.rx_crc_errors++;
2323 if (dma_flag & DMA_RX_OV)
2324 dev->stats.rx_over_errors++;
2325 if (dma_flag & DMA_RX_NO)
2326 dev->stats.rx_frame_errors++;
2327 if (dma_flag & DMA_RX_LG)
2328 dev->stats.rx_length_errors++;
2329 dev->stats.rx_errors++;
2330 dev_kfree_skb_any(skb);
2332 } /* error packet */
2336 /* remove RSB and hardware 2bytes added for IP alignment */
2340 if (priv->crc_fwd_en) {
2341 skb_trim(skb, len - ETH_FCS_LEN);
2345 bytes_processed += len;
2347 /*Finish setting up the received SKB and send it to the kernel*/
2348 skb->protocol = eth_type_trans(skb, priv->dev);
2351 if (dma_flag & DMA_RX_MULT)
2352 dev->stats.multicast++;
2355 napi_gro_receive(&ring->napi, skb);
2356 netif_dbg(priv, rx_status, dev, "pushed up to kernel\n");
2360 if (likely(ring->read_ptr < ring->end_ptr))
2363 ring->read_ptr = ring->cb_ptr;
2365 ring->c_index = (ring->c_index + 1) & DMA_C_INDEX_MASK;
2366 bcmgenet_rdma_ring_writel(priv, ring->index, ring->c_index, RDMA_CONS_INDEX);
2369 ring->dim.bytes = bytes_processed;
2370 ring->dim.packets = rxpktprocessed;
2372 return rxpktprocessed;
2375 /* Rx NAPI polling method */
2376 static int bcmgenet_rx_poll(struct napi_struct *napi, int budget)
2378 struct bcmgenet_rx_ring *ring = container_of(napi,
2379 struct bcmgenet_rx_ring, napi);
2380 struct dim_sample dim_sample = {};
2381 unsigned int work_done;
2383 work_done = bcmgenet_desc_rx(ring, budget);
2385 if (work_done < budget) {
2386 napi_complete_done(napi, work_done);
2387 ring->int_enable(ring);
2390 if (ring->dim.use_dim) {
2391 dim_update_sample(ring->dim.event_ctr, ring->dim.packets,
2392 ring->dim.bytes, &dim_sample);
2393 net_dim(&ring->dim.dim, dim_sample);
2399 static void bcmgenet_dim_work(struct work_struct *work)
2401 struct dim *dim = container_of(work, struct dim, work);
2402 struct bcmgenet_net_dim *ndim =
2403 container_of(dim, struct bcmgenet_net_dim, dim);
2404 struct bcmgenet_rx_ring *ring =
2405 container_of(ndim, struct bcmgenet_rx_ring, dim);
2406 struct dim_cq_moder cur_profile =
2407 net_dim_get_rx_moderation(dim->mode, dim->profile_ix);
2409 bcmgenet_set_rx_coalesce(ring, cur_profile.usec, cur_profile.pkts);
2410 dim->state = DIM_START_MEASURE;
2413 /* Assign skb to RX DMA descriptor. */
2414 static int bcmgenet_alloc_rx_buffers(struct bcmgenet_priv *priv,
2415 struct bcmgenet_rx_ring *ring)
2418 struct sk_buff *skb;
2421 netif_dbg(priv, hw, priv->dev, "%s\n", __func__);
2423 /* loop here for each buffer needing assign */
2424 for (i = 0; i < ring->size; i++) {
2426 skb = bcmgenet_rx_refill(priv, cb);
2428 dev_consume_skb_any(skb);
2436 static void bcmgenet_free_rx_buffers(struct bcmgenet_priv *priv)
2438 struct sk_buff *skb;
2442 for (i = 0; i < priv->num_rx_bds; i++) {
2443 cb = &priv->rx_cbs[i];
2445 skb = bcmgenet_free_rx_cb(&priv->pdev->dev, cb);
2447 dev_consume_skb_any(skb);
2451 static void umac_enable_set(struct bcmgenet_priv *priv, u32 mask, bool enable)
2455 reg = bcmgenet_umac_readl(priv, UMAC_CMD);
2456 if (reg & CMD_SW_RESET)
2462 bcmgenet_umac_writel(priv, reg, UMAC_CMD);
2464 /* UniMAC stops on a packet boundary, wait for a full-size packet
2468 usleep_range(1000, 2000);
2471 static void reset_umac(struct bcmgenet_priv *priv)
2473 /* 7358a0/7552a0: bad default in RBUF_FLUSH_CTRL.umac_sw_rst */
2474 bcmgenet_rbuf_ctrl_set(priv, 0);
2477 /* issue soft reset and disable MAC while updating its registers */
2478 bcmgenet_umac_writel(priv, CMD_SW_RESET, UMAC_CMD);
2482 static void bcmgenet_intr_disable(struct bcmgenet_priv *priv)
2484 /* Mask all interrupts.*/
2485 bcmgenet_intrl2_0_writel(priv, 0xFFFFFFFF, INTRL2_CPU_MASK_SET);
2486 bcmgenet_intrl2_0_writel(priv, 0xFFFFFFFF, INTRL2_CPU_CLEAR);
2487 bcmgenet_intrl2_1_writel(priv, 0xFFFFFFFF, INTRL2_CPU_MASK_SET);
2488 bcmgenet_intrl2_1_writel(priv, 0xFFFFFFFF, INTRL2_CPU_CLEAR);
2491 static void bcmgenet_link_intr_enable(struct bcmgenet_priv *priv)
2493 u32 int0_enable = 0;
2495 /* Monitor cable plug/unplugged event for internal PHY, external PHY
2498 if (priv->internal_phy) {
2499 int0_enable |= UMAC_IRQ_LINK_EVENT;
2500 if (GENET_IS_V1(priv) || GENET_IS_V2(priv) || GENET_IS_V3(priv))
2501 int0_enable |= UMAC_IRQ_PHY_DET_R;
2502 } else if (priv->ext_phy) {
2503 int0_enable |= UMAC_IRQ_LINK_EVENT;
2504 } else if (priv->phy_interface == PHY_INTERFACE_MODE_MOCA) {
2505 if (priv->hw_params->flags & GENET_HAS_MOCA_LINK_DET)
2506 int0_enable |= UMAC_IRQ_LINK_EVENT;
2508 bcmgenet_intrl2_0_writel(priv, int0_enable, INTRL2_CPU_MASK_CLEAR);
2511 static void init_umac(struct bcmgenet_priv *priv)
2513 struct device *kdev = &priv->pdev->dev;
2515 u32 int0_enable = 0;
2517 dev_dbg(&priv->pdev->dev, "bcmgenet: init_umac\n");
2521 /* clear tx/rx counter */
2522 bcmgenet_umac_writel(priv,
2523 MIB_RESET_RX | MIB_RESET_TX | MIB_RESET_RUNT,
2525 bcmgenet_umac_writel(priv, 0, UMAC_MIB_CTRL);
2527 bcmgenet_umac_writel(priv, ENET_MAX_MTU_SIZE, UMAC_MAX_FRAME_LEN);
2529 /* init tx registers, enable TSB */
2530 reg = bcmgenet_tbuf_ctrl_get(priv);
2532 bcmgenet_tbuf_ctrl_set(priv, reg);
2534 /* init rx registers, enable ip header optimization and RSB */
2535 reg = bcmgenet_rbuf_readl(priv, RBUF_CTRL);
2536 reg |= RBUF_ALIGN_2B | RBUF_64B_EN;
2537 bcmgenet_rbuf_writel(priv, reg, RBUF_CTRL);
2539 /* enable rx checksumming */
2540 reg = bcmgenet_rbuf_readl(priv, RBUF_CHK_CTRL);
2541 reg |= RBUF_RXCHK_EN | RBUF_L3_PARSE_DIS;
2542 /* If UniMAC forwards CRC, we need to skip over it to get
2543 * a valid CHK bit to be set in the per-packet status word
2545 if (priv->crc_fwd_en)
2546 reg |= RBUF_SKIP_FCS;
2548 reg &= ~RBUF_SKIP_FCS;
2549 bcmgenet_rbuf_writel(priv, reg, RBUF_CHK_CTRL);
2551 if (!GENET_IS_V1(priv) && !GENET_IS_V2(priv))
2552 bcmgenet_rbuf_writel(priv, 1, RBUF_TBUF_SIZE_CTRL);
2554 bcmgenet_intr_disable(priv);
2556 /* Configure backpressure vectors for MoCA */
2557 if (priv->phy_interface == PHY_INTERFACE_MODE_MOCA) {
2558 reg = bcmgenet_bp_mc_get(priv);
2559 reg |= BIT(priv->hw_params->bp_in_en_shift);
2561 /* bp_mask: back pressure mask */
2562 if (netif_is_multiqueue(priv->dev))
2563 reg |= priv->hw_params->bp_in_mask;
2565 reg &= ~priv->hw_params->bp_in_mask;
2566 bcmgenet_bp_mc_set(priv, reg);
2569 /* Enable MDIO interrupts on GENET v3+ */
2570 if (priv->hw_params->flags & GENET_HAS_MDIO_INTR)
2571 int0_enable |= (UMAC_IRQ_MDIO_DONE | UMAC_IRQ_MDIO_ERROR);
2573 bcmgenet_intrl2_0_writel(priv, int0_enable, INTRL2_CPU_MASK_CLEAR);
2575 dev_dbg(kdev, "done init umac\n");
2578 static void bcmgenet_init_dim(struct bcmgenet_rx_ring *ring,
2579 void (*cb)(struct work_struct *work))
2581 struct bcmgenet_net_dim *dim = &ring->dim;
2583 INIT_WORK(&dim->dim.work, cb);
2584 dim->dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE;
2590 static void bcmgenet_init_rx_coalesce(struct bcmgenet_rx_ring *ring)
2592 struct bcmgenet_net_dim *dim = &ring->dim;
2593 struct dim_cq_moder moder;
2596 usecs = ring->rx_coalesce_usecs;
2597 pkts = ring->rx_max_coalesced_frames;
2599 /* If DIM was enabled, re-apply default parameters */
2601 moder = net_dim_get_def_rx_moderation(dim->dim.mode);
2606 bcmgenet_set_rx_coalesce(ring, usecs, pkts);
2609 /* Initialize a Tx ring along with corresponding hardware registers */
2610 static void bcmgenet_init_tx_ring(struct bcmgenet_priv *priv,
2611 unsigned int index, unsigned int size,
2612 unsigned int start_ptr, unsigned int end_ptr)
2614 struct bcmgenet_tx_ring *ring = &priv->tx_rings[index];
2615 u32 words_per_bd = WORDS_PER_BD(priv);
2616 u32 flow_period_val = 0;
2618 spin_lock_init(&ring->lock);
2620 ring->index = index;
2621 if (index == DESC_INDEX) {
2623 ring->int_enable = bcmgenet_tx_ring16_int_enable;
2624 ring->int_disable = bcmgenet_tx_ring16_int_disable;
2626 ring->queue = index + 1;
2627 ring->int_enable = bcmgenet_tx_ring_int_enable;
2628 ring->int_disable = bcmgenet_tx_ring_int_disable;
2630 ring->cbs = priv->tx_cbs + start_ptr;
2632 ring->clean_ptr = start_ptr;
2634 ring->free_bds = size;
2635 ring->write_ptr = start_ptr;
2636 ring->cb_ptr = start_ptr;
2637 ring->end_ptr = end_ptr - 1;
2638 ring->prod_index = 0;
2640 /* Set flow period for ring != 16 */
2641 if (index != DESC_INDEX)
2642 flow_period_val = ENET_MAX_MTU_SIZE << 16;
2644 bcmgenet_tdma_ring_writel(priv, index, 0, TDMA_PROD_INDEX);
2645 bcmgenet_tdma_ring_writel(priv, index, 0, TDMA_CONS_INDEX);
2646 bcmgenet_tdma_ring_writel(priv, index, 1, DMA_MBUF_DONE_THRESH);
2647 /* Disable rate control for now */
2648 bcmgenet_tdma_ring_writel(priv, index, flow_period_val,
2650 bcmgenet_tdma_ring_writel(priv, index,
2651 ((size << DMA_RING_SIZE_SHIFT) |
2652 RX_BUF_LENGTH), DMA_RING_BUF_SIZE);
2654 /* Set start and end address, read and write pointers */
2655 bcmgenet_tdma_ring_writel(priv, index, start_ptr * words_per_bd,
2657 bcmgenet_tdma_ring_writel(priv, index, start_ptr * words_per_bd,
2659 bcmgenet_tdma_ring_writel(priv, index, start_ptr * words_per_bd,
2661 bcmgenet_tdma_ring_writel(priv, index, end_ptr * words_per_bd - 1,
2664 /* Initialize Tx NAPI */
2665 netif_tx_napi_add(priv->dev, &ring->napi, bcmgenet_tx_poll,
2669 /* Initialize a RDMA ring */
2670 static int bcmgenet_init_rx_ring(struct bcmgenet_priv *priv,
2671 unsigned int index, unsigned int size,
2672 unsigned int start_ptr, unsigned int end_ptr)
2674 struct bcmgenet_rx_ring *ring = &priv->rx_rings[index];
2675 u32 words_per_bd = WORDS_PER_BD(priv);
2679 ring->index = index;
2680 if (index == DESC_INDEX) {
2681 ring->int_enable = bcmgenet_rx_ring16_int_enable;
2682 ring->int_disable = bcmgenet_rx_ring16_int_disable;
2684 ring->int_enable = bcmgenet_rx_ring_int_enable;
2685 ring->int_disable = bcmgenet_rx_ring_int_disable;
2687 ring->cbs = priv->rx_cbs + start_ptr;
2690 ring->read_ptr = start_ptr;
2691 ring->cb_ptr = start_ptr;
2692 ring->end_ptr = end_ptr - 1;
2694 ret = bcmgenet_alloc_rx_buffers(priv, ring);
2698 bcmgenet_init_dim(ring, bcmgenet_dim_work);
2699 bcmgenet_init_rx_coalesce(ring);
2701 /* Initialize Rx NAPI */
2702 netif_napi_add(priv->dev, &ring->napi, bcmgenet_rx_poll,
2705 bcmgenet_rdma_ring_writel(priv, index, 0, RDMA_PROD_INDEX);
2706 bcmgenet_rdma_ring_writel(priv, index, 0, RDMA_CONS_INDEX);
2707 bcmgenet_rdma_ring_writel(priv, index,
2708 ((size << DMA_RING_SIZE_SHIFT) |
2709 RX_BUF_LENGTH), DMA_RING_BUF_SIZE);
2710 bcmgenet_rdma_ring_writel(priv, index,
2711 (DMA_FC_THRESH_LO <<
2712 DMA_XOFF_THRESHOLD_SHIFT) |
2713 DMA_FC_THRESH_HI, RDMA_XON_XOFF_THRESH);
2715 /* Set start and end address, read and write pointers */
2716 bcmgenet_rdma_ring_writel(priv, index, start_ptr * words_per_bd,
2718 bcmgenet_rdma_ring_writel(priv, index, start_ptr * words_per_bd,
2720 bcmgenet_rdma_ring_writel(priv, index, start_ptr * words_per_bd,
2722 bcmgenet_rdma_ring_writel(priv, index, end_ptr * words_per_bd - 1,
2728 static void bcmgenet_enable_tx_napi(struct bcmgenet_priv *priv)
2731 struct bcmgenet_tx_ring *ring;
2733 for (i = 0; i < priv->hw_params->tx_queues; ++i) {
2734 ring = &priv->tx_rings[i];
2735 napi_enable(&ring->napi);
2736 ring->int_enable(ring);
2739 ring = &priv->tx_rings[DESC_INDEX];
2740 napi_enable(&ring->napi);
2741 ring->int_enable(ring);
2744 static void bcmgenet_disable_tx_napi(struct bcmgenet_priv *priv)
2747 struct bcmgenet_tx_ring *ring;
2749 for (i = 0; i < priv->hw_params->tx_queues; ++i) {
2750 ring = &priv->tx_rings[i];
2751 napi_disable(&ring->napi);
2754 ring = &priv->tx_rings[DESC_INDEX];
2755 napi_disable(&ring->napi);
2758 static void bcmgenet_fini_tx_napi(struct bcmgenet_priv *priv)
2761 struct bcmgenet_tx_ring *ring;
2763 for (i = 0; i < priv->hw_params->tx_queues; ++i) {
2764 ring = &priv->tx_rings[i];
2765 netif_napi_del(&ring->napi);
2768 ring = &priv->tx_rings[DESC_INDEX];
2769 netif_napi_del(&ring->napi);
2772 /* Initialize Tx queues
2774 * Queues 0-3 are priority-based, each one has 32 descriptors,
2775 * with queue 0 being the highest priority queue.
2777 * Queue 16 is the default Tx queue with
2778 * GENET_Q16_TX_BD_CNT = 256 - 4 * 32 = 128 descriptors.
2780 * The transmit control block pool is then partitioned as follows:
2781 * - Tx queue 0 uses tx_cbs[0..31]
2782 * - Tx queue 1 uses tx_cbs[32..63]
2783 * - Tx queue 2 uses tx_cbs[64..95]
2784 * - Tx queue 3 uses tx_cbs[96..127]
2785 * - Tx queue 16 uses tx_cbs[128..255]
2787 static void bcmgenet_init_tx_queues(struct net_device *dev)
2789 struct bcmgenet_priv *priv = netdev_priv(dev);
2791 u32 dma_ctrl, ring_cfg;
2792 u32 dma_priority[3] = {0, 0, 0};
2794 dma_ctrl = bcmgenet_tdma_readl(priv, DMA_CTRL);
2795 dma_enable = dma_ctrl & DMA_EN;
2796 dma_ctrl &= ~DMA_EN;
2797 bcmgenet_tdma_writel(priv, dma_ctrl, DMA_CTRL);
2802 /* Enable strict priority arbiter mode */
2803 bcmgenet_tdma_writel(priv, DMA_ARBITER_SP, DMA_ARB_CTRL);
2805 /* Initialize Tx priority queues */
2806 for (i = 0; i < priv->hw_params->tx_queues; i++) {
2807 bcmgenet_init_tx_ring(priv, i, priv->hw_params->tx_bds_per_q,
2808 i * priv->hw_params->tx_bds_per_q,
2809 (i + 1) * priv->hw_params->tx_bds_per_q);
2810 ring_cfg |= (1 << i);
2811 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT));
2812 dma_priority[DMA_PRIO_REG_INDEX(i)] |=
2813 ((GENET_Q0_PRIORITY + i) << DMA_PRIO_REG_SHIFT(i));
2816 /* Initialize Tx default queue 16 */
2817 bcmgenet_init_tx_ring(priv, DESC_INDEX, GENET_Q16_TX_BD_CNT,
2818 priv->hw_params->tx_queues *
2819 priv->hw_params->tx_bds_per_q,
2821 ring_cfg |= (1 << DESC_INDEX);
2822 dma_ctrl |= (1 << (DESC_INDEX + DMA_RING_BUF_EN_SHIFT));
2823 dma_priority[DMA_PRIO_REG_INDEX(DESC_INDEX)] |=
2824 ((GENET_Q0_PRIORITY + priv->hw_params->tx_queues) <<
2825 DMA_PRIO_REG_SHIFT(DESC_INDEX));
2827 /* Set Tx queue priorities */
2828 bcmgenet_tdma_writel(priv, dma_priority[0], DMA_PRIORITY_0);
2829 bcmgenet_tdma_writel(priv, dma_priority[1], DMA_PRIORITY_1);
2830 bcmgenet_tdma_writel(priv, dma_priority[2], DMA_PRIORITY_2);
2832 /* Enable Tx queues */
2833 bcmgenet_tdma_writel(priv, ring_cfg, DMA_RING_CFG);
2838 bcmgenet_tdma_writel(priv, dma_ctrl, DMA_CTRL);
2841 static void bcmgenet_enable_rx_napi(struct bcmgenet_priv *priv)
2844 struct bcmgenet_rx_ring *ring;
2846 for (i = 0; i < priv->hw_params->rx_queues; ++i) {
2847 ring = &priv->rx_rings[i];
2848 napi_enable(&ring->napi);
2849 ring->int_enable(ring);
2852 ring = &priv->rx_rings[DESC_INDEX];
2853 napi_enable(&ring->napi);
2854 ring->int_enable(ring);
2857 static void bcmgenet_disable_rx_napi(struct bcmgenet_priv *priv)
2860 struct bcmgenet_rx_ring *ring;
2862 for (i = 0; i < priv->hw_params->rx_queues; ++i) {
2863 ring = &priv->rx_rings[i];
2864 napi_disable(&ring->napi);
2865 cancel_work_sync(&ring->dim.dim.work);
2868 ring = &priv->rx_rings[DESC_INDEX];
2869 napi_disable(&ring->napi);
2870 cancel_work_sync(&ring->dim.dim.work);
2873 static void bcmgenet_fini_rx_napi(struct bcmgenet_priv *priv)
2876 struct bcmgenet_rx_ring *ring;
2878 for (i = 0; i < priv->hw_params->rx_queues; ++i) {
2879 ring = &priv->rx_rings[i];
2880 netif_napi_del(&ring->napi);
2883 ring = &priv->rx_rings[DESC_INDEX];
2884 netif_napi_del(&ring->napi);
2887 /* Initialize Rx queues
2889 * Queues 0-15 are priority queues. Hardware Filtering Block (HFB) can be
2890 * used to direct traffic to these queues.
2892 * Queue 16 is the default Rx queue with GENET_Q16_RX_BD_CNT descriptors.
2894 static int bcmgenet_init_rx_queues(struct net_device *dev)
2896 struct bcmgenet_priv *priv = netdev_priv(dev);
2903 dma_ctrl = bcmgenet_rdma_readl(priv, DMA_CTRL);
2904 dma_enable = dma_ctrl & DMA_EN;
2905 dma_ctrl &= ~DMA_EN;
2906 bcmgenet_rdma_writel(priv, dma_ctrl, DMA_CTRL);
2911 /* Initialize Rx priority queues */
2912 for (i = 0; i < priv->hw_params->rx_queues; i++) {
2913 ret = bcmgenet_init_rx_ring(priv, i,
2914 priv->hw_params->rx_bds_per_q,
2915 i * priv->hw_params->rx_bds_per_q,
2917 priv->hw_params->rx_bds_per_q);
2921 ring_cfg |= (1 << i);
2922 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT));
2925 /* Initialize Rx default queue 16 */
2926 ret = bcmgenet_init_rx_ring(priv, DESC_INDEX, GENET_Q16_RX_BD_CNT,
2927 priv->hw_params->rx_queues *
2928 priv->hw_params->rx_bds_per_q,
2933 ring_cfg |= (1 << DESC_INDEX);
2934 dma_ctrl |= (1 << (DESC_INDEX + DMA_RING_BUF_EN_SHIFT));
2937 bcmgenet_rdma_writel(priv, ring_cfg, DMA_RING_CFG);
2939 /* Configure ring as descriptor ring and re-enable DMA if enabled */
2942 bcmgenet_rdma_writel(priv, dma_ctrl, DMA_CTRL);
2947 static int bcmgenet_dma_teardown(struct bcmgenet_priv *priv)
2955 /* Disable TDMA to stop add more frames in TX DMA */
2956 reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
2958 bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
2960 /* Check TDMA status register to confirm TDMA is disabled */
2961 while (timeout++ < DMA_TIMEOUT_VAL) {
2962 reg = bcmgenet_tdma_readl(priv, DMA_STATUS);
2963 if (reg & DMA_DISABLED)
2969 if (timeout == DMA_TIMEOUT_VAL) {
2970 netdev_warn(priv->dev, "Timed out while disabling TX DMA\n");
2974 /* Wait 10ms for packet drain in both tx and rx dma */
2975 usleep_range(10000, 20000);
2978 reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
2980 bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
2983 /* Check RDMA status register to confirm RDMA is disabled */
2984 while (timeout++ < DMA_TIMEOUT_VAL) {
2985 reg = bcmgenet_rdma_readl(priv, DMA_STATUS);
2986 if (reg & DMA_DISABLED)
2992 if (timeout == DMA_TIMEOUT_VAL) {
2993 netdev_warn(priv->dev, "Timed out while disabling RX DMA\n");
2998 for (i = 0; i < priv->hw_params->rx_queues; i++)
2999 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT));
3000 reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
3002 bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
3005 for (i = 0; i < priv->hw_params->tx_queues; i++)
3006 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT));
3007 reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
3009 bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
3014 static void bcmgenet_fini_dma(struct bcmgenet_priv *priv)
3016 struct netdev_queue *txq;
3019 bcmgenet_fini_rx_napi(priv);
3020 bcmgenet_fini_tx_napi(priv);
3022 for (i = 0; i < priv->num_tx_bds; i++)
3023 dev_kfree_skb(bcmgenet_free_tx_cb(&priv->pdev->dev,
3026 for (i = 0; i < priv->hw_params->tx_queues; i++) {
3027 txq = netdev_get_tx_queue(priv->dev, priv->tx_rings[i].queue);
3028 netdev_tx_reset_queue(txq);
3031 txq = netdev_get_tx_queue(priv->dev, priv->tx_rings[DESC_INDEX].queue);
3032 netdev_tx_reset_queue(txq);
3034 bcmgenet_free_rx_buffers(priv);
3035 kfree(priv->rx_cbs);
3036 kfree(priv->tx_cbs);
3039 /* init_edma: Initialize DMA control register */
3040 static int bcmgenet_init_dma(struct bcmgenet_priv *priv)
3046 netif_dbg(priv, hw, priv->dev, "%s\n", __func__);
3048 /* Initialize common Rx ring structures */
3049 priv->rx_bds = priv->base + priv->hw_params->rdma_offset;
3050 priv->num_rx_bds = TOTAL_DESC;
3051 priv->rx_cbs = kcalloc(priv->num_rx_bds, sizeof(struct enet_cb),
3056 for (i = 0; i < priv->num_rx_bds; i++) {
3057 cb = priv->rx_cbs + i;
3058 cb->bd_addr = priv->rx_bds + i * DMA_DESC_SIZE;
3061 /* Initialize common TX ring structures */
3062 priv->tx_bds = priv->base + priv->hw_params->tdma_offset;
3063 priv->num_tx_bds = TOTAL_DESC;
3064 priv->tx_cbs = kcalloc(priv->num_tx_bds, sizeof(struct enet_cb),
3066 if (!priv->tx_cbs) {
3067 kfree(priv->rx_cbs);
3071 for (i = 0; i < priv->num_tx_bds; i++) {
3072 cb = priv->tx_cbs + i;
3073 cb->bd_addr = priv->tx_bds + i * DMA_DESC_SIZE;
3077 bcmgenet_rdma_writel(priv, priv->dma_max_burst_length,
3078 DMA_SCB_BURST_SIZE);
3080 /* Initialize Rx queues */
3081 ret = bcmgenet_init_rx_queues(priv->dev);
3083 netdev_err(priv->dev, "failed to initialize Rx queues\n");
3084 bcmgenet_free_rx_buffers(priv);
3085 kfree(priv->rx_cbs);
3086 kfree(priv->tx_cbs);
3091 bcmgenet_tdma_writel(priv, priv->dma_max_burst_length,
3092 DMA_SCB_BURST_SIZE);
3094 /* Initialize Tx queues */
3095 bcmgenet_init_tx_queues(priv->dev);
3100 /* Interrupt bottom half */
3101 static void bcmgenet_irq_task(struct work_struct *work)
3103 unsigned int status;
3104 struct bcmgenet_priv *priv = container_of(
3105 work, struct bcmgenet_priv, bcmgenet_irq_work);
3107 netif_dbg(priv, intr, priv->dev, "%s\n", __func__);
3109 spin_lock_irq(&priv->lock);
3110 status = priv->irq0_stat;
3111 priv->irq0_stat = 0;
3112 spin_unlock_irq(&priv->lock);
3114 if (status & UMAC_IRQ_PHY_DET_R &&
3115 priv->dev->phydev->autoneg != AUTONEG_ENABLE) {
3116 phy_init_hw(priv->dev->phydev);
3117 genphy_config_aneg(priv->dev->phydev);
3120 /* Link UP/DOWN event */
3121 if (status & UMAC_IRQ_LINK_EVENT)
3122 phy_mac_interrupt(priv->dev->phydev);
3126 /* bcmgenet_isr1: handle Rx and Tx priority queues */
3127 static irqreturn_t bcmgenet_isr1(int irq, void *dev_id)
3129 struct bcmgenet_priv *priv = dev_id;
3130 struct bcmgenet_rx_ring *rx_ring;
3131 struct bcmgenet_tx_ring *tx_ring;
3132 unsigned int index, status;
3134 /* Read irq status */
3135 status = bcmgenet_intrl2_1_readl(priv, INTRL2_CPU_STAT) &
3136 ~bcmgenet_intrl2_1_readl(priv, INTRL2_CPU_MASK_STATUS);
3138 /* clear interrupts */
3139 bcmgenet_intrl2_1_writel(priv, status, INTRL2_CPU_CLEAR);
3141 netif_dbg(priv, intr, priv->dev,
3142 "%s: IRQ=0x%x\n", __func__, status);
3144 /* Check Rx priority queue interrupts */
3145 for (index = 0; index < priv->hw_params->rx_queues; index++) {
3146 if (!(status & BIT(UMAC_IRQ1_RX_INTR_SHIFT + index)))
3149 rx_ring = &priv->rx_rings[index];
3150 rx_ring->dim.event_ctr++;
3152 if (likely(napi_schedule_prep(&rx_ring->napi))) {
3153 rx_ring->int_disable(rx_ring);
3154 __napi_schedule_irqoff(&rx_ring->napi);
3158 /* Check Tx priority queue interrupts */
3159 for (index = 0; index < priv->hw_params->tx_queues; index++) {
3160 if (!(status & BIT(index)))
3163 tx_ring = &priv->tx_rings[index];
3165 if (likely(napi_schedule_prep(&tx_ring->napi))) {
3166 tx_ring->int_disable(tx_ring);
3167 __napi_schedule_irqoff(&tx_ring->napi);
3174 /* bcmgenet_isr0: handle Rx and Tx default queues + other stuff */
3175 static irqreturn_t bcmgenet_isr0(int irq, void *dev_id)
3177 struct bcmgenet_priv *priv = dev_id;
3178 struct bcmgenet_rx_ring *rx_ring;
3179 struct bcmgenet_tx_ring *tx_ring;
3180 unsigned int status;
3181 unsigned long flags;
3183 /* Read irq status */
3184 status = bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_STAT) &
3185 ~bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_MASK_STATUS);
3187 /* clear interrupts */
3188 bcmgenet_intrl2_0_writel(priv, status, INTRL2_CPU_CLEAR);
3190 netif_dbg(priv, intr, priv->dev,
3191 "IRQ=0x%x\n", status);
3193 if (status & UMAC_IRQ_RXDMA_DONE) {
3194 rx_ring = &priv->rx_rings[DESC_INDEX];
3195 rx_ring->dim.event_ctr++;
3197 if (likely(napi_schedule_prep(&rx_ring->napi))) {
3198 rx_ring->int_disable(rx_ring);
3199 __napi_schedule_irqoff(&rx_ring->napi);
3203 if (status & UMAC_IRQ_TXDMA_DONE) {
3204 tx_ring = &priv->tx_rings[DESC_INDEX];
3206 if (likely(napi_schedule_prep(&tx_ring->napi))) {
3207 tx_ring->int_disable(tx_ring);
3208 __napi_schedule_irqoff(&tx_ring->napi);
3212 if ((priv->hw_params->flags & GENET_HAS_MDIO_INTR) &&
3213 status & (UMAC_IRQ_MDIO_DONE | UMAC_IRQ_MDIO_ERROR)) {
3217 /* all other interested interrupts handled in bottom half */
3218 status &= (UMAC_IRQ_LINK_EVENT | UMAC_IRQ_PHY_DET_R);
3220 /* Save irq status for bottom-half processing. */
3221 spin_lock_irqsave(&priv->lock, flags);
3222 priv->irq0_stat |= status;
3223 spin_unlock_irqrestore(&priv->lock, flags);
3225 schedule_work(&priv->bcmgenet_irq_work);
3231 static irqreturn_t bcmgenet_wol_isr(int irq, void *dev_id)
3233 /* Acknowledge the interrupt */
3237 #ifdef CONFIG_NET_POLL_CONTROLLER
3238 static void bcmgenet_poll_controller(struct net_device *dev)
3240 struct bcmgenet_priv *priv = netdev_priv(dev);
3242 /* Invoke the main RX/TX interrupt handler */
3243 disable_irq(priv->irq0);
3244 bcmgenet_isr0(priv->irq0, priv);
3245 enable_irq(priv->irq0);
3247 /* And the interrupt handler for RX/TX priority queues */
3248 disable_irq(priv->irq1);
3249 bcmgenet_isr1(priv->irq1, priv);
3250 enable_irq(priv->irq1);
3254 static void bcmgenet_umac_reset(struct bcmgenet_priv *priv)
3258 reg = bcmgenet_rbuf_ctrl_get(priv);
3260 bcmgenet_rbuf_ctrl_set(priv, reg);
3264 bcmgenet_rbuf_ctrl_set(priv, reg);
3268 static void bcmgenet_set_hw_addr(struct bcmgenet_priv *priv,
3269 unsigned char *addr)
3271 bcmgenet_umac_writel(priv, get_unaligned_be32(&addr[0]), UMAC_MAC0);
3272 bcmgenet_umac_writel(priv, get_unaligned_be16(&addr[4]), UMAC_MAC1);
3275 static void bcmgenet_get_hw_addr(struct bcmgenet_priv *priv,
3276 unsigned char *addr)
3280 addr_tmp = bcmgenet_umac_readl(priv, UMAC_MAC0);
3281 put_unaligned_be32(addr_tmp, &addr[0]);
3282 addr_tmp = bcmgenet_umac_readl(priv, UMAC_MAC1);
3283 put_unaligned_be16(addr_tmp, &addr[4]);
3286 /* Returns a reusable dma control register value */
3287 static u32 bcmgenet_dma_disable(struct bcmgenet_priv *priv)
3294 dma_ctrl = 1 << (DESC_INDEX + DMA_RING_BUF_EN_SHIFT) | DMA_EN;
3295 for (i = 0; i < priv->hw_params->tx_queues; i++)
3296 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT));
3297 reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
3299 bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
3301 dma_ctrl = 1 << (DESC_INDEX + DMA_RING_BUF_EN_SHIFT) | DMA_EN;
3302 for (i = 0; i < priv->hw_params->rx_queues; i++)
3303 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT));
3304 reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
3306 bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
3308 bcmgenet_umac_writel(priv, 1, UMAC_TX_FLUSH);
3310 bcmgenet_umac_writel(priv, 0, UMAC_TX_FLUSH);
3315 static void bcmgenet_enable_dma(struct bcmgenet_priv *priv, u32 dma_ctrl)
3319 reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
3321 bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
3323 reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
3325 bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
3328 static void bcmgenet_netif_start(struct net_device *dev)
3330 struct bcmgenet_priv *priv = netdev_priv(dev);
3332 /* Start the network engine */
3333 bcmgenet_set_rx_mode(dev);
3334 bcmgenet_enable_rx_napi(priv);
3336 umac_enable_set(priv, CMD_TX_EN | CMD_RX_EN, true);
3338 bcmgenet_enable_tx_napi(priv);
3340 /* Monitor link interrupts now */
3341 bcmgenet_link_intr_enable(priv);
3343 phy_start(dev->phydev);
3346 static int bcmgenet_open(struct net_device *dev)
3348 struct bcmgenet_priv *priv = netdev_priv(dev);
3349 unsigned long dma_ctrl;
3352 netif_dbg(priv, ifup, dev, "bcmgenet_open\n");
3354 /* Turn on the clock */
3355 clk_prepare_enable(priv->clk);
3357 /* If this is an internal GPHY, power it back on now, before UniMAC is
3358 * brought out of reset as absolutely no UniMAC activity is allowed
3360 if (priv->internal_phy)
3361 bcmgenet_power_up(priv, GENET_POWER_PASSIVE);
3363 /* take MAC out of reset */
3364 bcmgenet_umac_reset(priv);
3368 /* Apply features again in case we changed them while interface was
3371 bcmgenet_set_features(dev, dev->features);
3373 bcmgenet_set_hw_addr(priv, dev->dev_addr);
3375 /* Disable RX/TX DMA and flush TX queues */
3376 dma_ctrl = bcmgenet_dma_disable(priv);
3378 /* Reinitialize TDMA and RDMA and SW housekeeping */
3379 ret = bcmgenet_init_dma(priv);
3381 netdev_err(dev, "failed to initialize DMA\n");
3382 goto err_clk_disable;
3385 /* Always enable ring 16 - descriptor ring */
3386 bcmgenet_enable_dma(priv, dma_ctrl);
3389 bcmgenet_hfb_init(priv);
3391 ret = request_irq(priv->irq0, bcmgenet_isr0, IRQF_SHARED,
3394 netdev_err(dev, "can't request IRQ %d\n", priv->irq0);
3398 ret = request_irq(priv->irq1, bcmgenet_isr1, IRQF_SHARED,
3401 netdev_err(dev, "can't request IRQ %d\n", priv->irq1);
3405 ret = bcmgenet_mii_probe(dev);
3407 netdev_err(dev, "failed to connect to PHY\n");
3411 bcmgenet_phy_pause_set(dev, priv->rx_pause, priv->tx_pause);
3413 bcmgenet_netif_start(dev);
3415 netif_tx_start_all_queues(dev);
3420 free_irq(priv->irq1, priv);
3422 free_irq(priv->irq0, priv);
3424 bcmgenet_dma_teardown(priv);
3425 bcmgenet_fini_dma(priv);
3427 if (priv->internal_phy)
3428 bcmgenet_power_down(priv, GENET_POWER_PASSIVE);
3429 clk_disable_unprepare(priv->clk);
3433 static void bcmgenet_netif_stop(struct net_device *dev)
3435 struct bcmgenet_priv *priv = netdev_priv(dev);
3437 bcmgenet_disable_tx_napi(priv);
3438 netif_tx_disable(dev);
3440 /* Disable MAC receive */
3441 umac_enable_set(priv, CMD_RX_EN, false);
3443 bcmgenet_dma_teardown(priv);
3445 /* Disable MAC transmit. TX DMA disabled must be done before this */
3446 umac_enable_set(priv, CMD_TX_EN, false);
3448 phy_stop(dev->phydev);
3449 bcmgenet_disable_rx_napi(priv);
3450 bcmgenet_intr_disable(priv);
3452 /* Wait for pending work items to complete. Since interrupts are
3453 * disabled no new work will be scheduled.
3455 cancel_work_sync(&priv->bcmgenet_irq_work);
3458 bcmgenet_tx_reclaim_all(dev);
3459 bcmgenet_fini_dma(priv);
3462 static int bcmgenet_close(struct net_device *dev)
3464 struct bcmgenet_priv *priv = netdev_priv(dev);
3467 netif_dbg(priv, ifdown, dev, "bcmgenet_close\n");
3469 bcmgenet_netif_stop(dev);
3471 /* Really kill the PHY state machine and disconnect from it */
3472 phy_disconnect(dev->phydev);
3474 free_irq(priv->irq0, priv);
3475 free_irq(priv->irq1, priv);
3477 if (priv->internal_phy)
3478 ret = bcmgenet_power_down(priv, GENET_POWER_PASSIVE);
3480 clk_disable_unprepare(priv->clk);
3485 static void bcmgenet_dump_tx_queue(struct bcmgenet_tx_ring *ring)
3487 struct bcmgenet_priv *priv = ring->priv;
3488 u32 p_index, c_index, intsts, intmsk;
3489 struct netdev_queue *txq;
3490 unsigned int free_bds;
3493 if (!netif_msg_tx_err(priv))
3496 txq = netdev_get_tx_queue(priv->dev, ring->queue);
3498 spin_lock(&ring->lock);
3499 if (ring->index == DESC_INDEX) {
3500 intsts = ~bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_MASK_STATUS);
3501 intmsk = UMAC_IRQ_TXDMA_DONE | UMAC_IRQ_TXDMA_MBDONE;
3503 intsts = ~bcmgenet_intrl2_1_readl(priv, INTRL2_CPU_MASK_STATUS);
3504 intmsk = 1 << ring->index;
3506 c_index = bcmgenet_tdma_ring_readl(priv, ring->index, TDMA_CONS_INDEX);
3507 p_index = bcmgenet_tdma_ring_readl(priv, ring->index, TDMA_PROD_INDEX);
3508 txq_stopped = netif_tx_queue_stopped(txq);
3509 free_bds = ring->free_bds;
3510 spin_unlock(&ring->lock);
3512 netif_err(priv, tx_err, priv->dev, "Ring %d queue %d status summary\n"
3513 "TX queue status: %s, interrupts: %s\n"
3514 "(sw)free_bds: %d (sw)size: %d\n"
3515 "(sw)p_index: %d (hw)p_index: %d\n"
3516 "(sw)c_index: %d (hw)c_index: %d\n"
3517 "(sw)clean_p: %d (sw)write_p: %d\n"
3518 "(sw)cb_ptr: %d (sw)end_ptr: %d\n",
3519 ring->index, ring->queue,
3520 txq_stopped ? "stopped" : "active",
3521 intsts & intmsk ? "enabled" : "disabled",
3522 free_bds, ring->size,
3523 ring->prod_index, p_index & DMA_P_INDEX_MASK,
3524 ring->c_index, c_index & DMA_C_INDEX_MASK,
3525 ring->clean_ptr, ring->write_ptr,
3526 ring->cb_ptr, ring->end_ptr);
3529 static void bcmgenet_timeout(struct net_device *dev, unsigned int txqueue)
3531 struct bcmgenet_priv *priv = netdev_priv(dev);
3532 u32 int0_enable = 0;
3533 u32 int1_enable = 0;
3536 netif_dbg(priv, tx_err, dev, "bcmgenet_timeout\n");
3538 for (q = 0; q < priv->hw_params->tx_queues; q++)
3539 bcmgenet_dump_tx_queue(&priv->tx_rings[q]);
3540 bcmgenet_dump_tx_queue(&priv->tx_rings[DESC_INDEX]);
3542 bcmgenet_tx_reclaim_all(dev);
3544 for (q = 0; q < priv->hw_params->tx_queues; q++)
3545 int1_enable |= (1 << q);
3547 int0_enable = UMAC_IRQ_TXDMA_DONE;
3549 /* Re-enable TX interrupts if disabled */
3550 bcmgenet_intrl2_0_writel(priv, int0_enable, INTRL2_CPU_MASK_CLEAR);
3551 bcmgenet_intrl2_1_writel(priv, int1_enable, INTRL2_CPU_MASK_CLEAR);
3553 netif_trans_update(dev);
3555 dev->stats.tx_errors++;
3557 netif_tx_wake_all_queues(dev);
3560 #define MAX_MDF_FILTER 17
3562 static inline void bcmgenet_set_mdf_addr(struct bcmgenet_priv *priv,
3563 unsigned char *addr,
3566 bcmgenet_umac_writel(priv, addr[0] << 8 | addr[1],
3567 UMAC_MDF_ADDR + (*i * 4));
3568 bcmgenet_umac_writel(priv, addr[2] << 24 | addr[3] << 16 |
3569 addr[4] << 8 | addr[5],
3570 UMAC_MDF_ADDR + ((*i + 1) * 4));
3574 static void bcmgenet_set_rx_mode(struct net_device *dev)
3576 struct bcmgenet_priv *priv = netdev_priv(dev);
3577 struct netdev_hw_addr *ha;
3581 netif_dbg(priv, hw, dev, "%s: %08X\n", __func__, dev->flags);
3583 /* Number of filters needed */
3584 nfilter = netdev_uc_count(dev) + netdev_mc_count(dev) + 2;
3587 * Turn on promicuous mode for three scenarios
3588 * 1. IFF_PROMISC flag is set
3589 * 2. IFF_ALLMULTI flag is set
3590 * 3. The number of filters needed exceeds the number filters
3591 * supported by the hardware.
3593 reg = bcmgenet_umac_readl(priv, UMAC_CMD);
3594 if ((dev->flags & (IFF_PROMISC | IFF_ALLMULTI)) ||
3595 (nfilter > MAX_MDF_FILTER)) {
3597 bcmgenet_umac_writel(priv, reg, UMAC_CMD);
3598 bcmgenet_umac_writel(priv, 0, UMAC_MDF_CTRL);
3601 reg &= ~CMD_PROMISC;
3602 bcmgenet_umac_writel(priv, reg, UMAC_CMD);
3605 /* update MDF filter */
3608 bcmgenet_set_mdf_addr(priv, dev->broadcast, &i);
3609 /* my own address.*/
3610 bcmgenet_set_mdf_addr(priv, dev->dev_addr, &i);
3613 netdev_for_each_uc_addr(ha, dev)
3614 bcmgenet_set_mdf_addr(priv, ha->addr, &i);
3617 netdev_for_each_mc_addr(ha, dev)
3618 bcmgenet_set_mdf_addr(priv, ha->addr, &i);
3620 /* Enable filters */
3621 reg = GENMASK(MAX_MDF_FILTER - 1, MAX_MDF_FILTER - nfilter);
3622 bcmgenet_umac_writel(priv, reg, UMAC_MDF_CTRL);
3625 /* Set the hardware MAC address. */
3626 static int bcmgenet_set_mac_addr(struct net_device *dev, void *p)
3628 struct sockaddr *addr = p;
3630 /* Setting the MAC address at the hardware level is not possible
3631 * without disabling the UniMAC RX/TX enable bits.
3633 if (netif_running(dev))
3636 eth_hw_addr_set(dev, addr->sa_data);
3641 static struct net_device_stats *bcmgenet_get_stats(struct net_device *dev)
3643 struct bcmgenet_priv *priv = netdev_priv(dev);
3644 unsigned long tx_bytes = 0, tx_packets = 0;
3645 unsigned long rx_bytes = 0, rx_packets = 0;
3646 unsigned long rx_errors = 0, rx_dropped = 0;
3647 struct bcmgenet_tx_ring *tx_ring;
3648 struct bcmgenet_rx_ring *rx_ring;
3651 for (q = 0; q < priv->hw_params->tx_queues; q++) {
3652 tx_ring = &priv->tx_rings[q];
3653 tx_bytes += tx_ring->bytes;
3654 tx_packets += tx_ring->packets;
3656 tx_ring = &priv->tx_rings[DESC_INDEX];
3657 tx_bytes += tx_ring->bytes;
3658 tx_packets += tx_ring->packets;
3660 for (q = 0; q < priv->hw_params->rx_queues; q++) {
3661 rx_ring = &priv->rx_rings[q];
3663 rx_bytes += rx_ring->bytes;
3664 rx_packets += rx_ring->packets;
3665 rx_errors += rx_ring->errors;
3666 rx_dropped += rx_ring->dropped;
3668 rx_ring = &priv->rx_rings[DESC_INDEX];
3669 rx_bytes += rx_ring->bytes;
3670 rx_packets += rx_ring->packets;
3671 rx_errors += rx_ring->errors;
3672 rx_dropped += rx_ring->dropped;
3674 dev->stats.tx_bytes = tx_bytes;
3675 dev->stats.tx_packets = tx_packets;
3676 dev->stats.rx_bytes = rx_bytes;
3677 dev->stats.rx_packets = rx_packets;
3678 dev->stats.rx_errors = rx_errors;
3679 dev->stats.rx_missed_errors = rx_errors;
3680 dev->stats.rx_dropped = rx_dropped;
3684 static int bcmgenet_change_carrier(struct net_device *dev, bool new_carrier)
3686 struct bcmgenet_priv *priv = netdev_priv(dev);
3688 if (!dev->phydev || !phy_is_pseudo_fixed_link(dev->phydev) ||
3689 priv->phy_interface != PHY_INTERFACE_MODE_MOCA)
3693 netif_carrier_on(dev);
3695 netif_carrier_off(dev);
3700 static const struct net_device_ops bcmgenet_netdev_ops = {
3701 .ndo_open = bcmgenet_open,
3702 .ndo_stop = bcmgenet_close,
3703 .ndo_start_xmit = bcmgenet_xmit,
3704 .ndo_tx_timeout = bcmgenet_timeout,
3705 .ndo_set_rx_mode = bcmgenet_set_rx_mode,
3706 .ndo_set_mac_address = bcmgenet_set_mac_addr,
3707 .ndo_eth_ioctl = phy_do_ioctl_running,
3708 .ndo_set_features = bcmgenet_set_features,
3709 #ifdef CONFIG_NET_POLL_CONTROLLER
3710 .ndo_poll_controller = bcmgenet_poll_controller,
3712 .ndo_get_stats = bcmgenet_get_stats,
3713 .ndo_change_carrier = bcmgenet_change_carrier,
3716 /* Array of GENET hardware parameters/characteristics */
3717 static struct bcmgenet_hw_params bcmgenet_hw_params[] = {
3723 .bp_in_en_shift = 16,
3724 .bp_in_mask = 0xffff,
3725 .hfb_filter_cnt = 16,
3727 .hfb_offset = 0x1000,
3728 .rdma_offset = 0x2000,
3729 .tdma_offset = 0x3000,
3737 .bp_in_en_shift = 16,
3738 .bp_in_mask = 0xffff,
3739 .hfb_filter_cnt = 16,
3741 .tbuf_offset = 0x0600,
3742 .hfb_offset = 0x1000,
3743 .hfb_reg_offset = 0x2000,
3744 .rdma_offset = 0x3000,
3745 .tdma_offset = 0x4000,
3747 .flags = GENET_HAS_EXT,
3754 .bp_in_en_shift = 17,
3755 .bp_in_mask = 0x1ffff,
3756 .hfb_filter_cnt = 48,
3757 .hfb_filter_size = 128,
3759 .tbuf_offset = 0x0600,
3760 .hfb_offset = 0x8000,
3761 .hfb_reg_offset = 0xfc00,
3762 .rdma_offset = 0x10000,
3763 .tdma_offset = 0x11000,
3765 .flags = GENET_HAS_EXT | GENET_HAS_MDIO_INTR |
3766 GENET_HAS_MOCA_LINK_DET,
3773 .bp_in_en_shift = 17,
3774 .bp_in_mask = 0x1ffff,
3775 .hfb_filter_cnt = 48,
3776 .hfb_filter_size = 128,
3778 .tbuf_offset = 0x0600,
3779 .hfb_offset = 0x8000,
3780 .hfb_reg_offset = 0xfc00,
3781 .rdma_offset = 0x2000,
3782 .tdma_offset = 0x4000,
3784 .flags = GENET_HAS_40BITS | GENET_HAS_EXT |
3785 GENET_HAS_MDIO_INTR | GENET_HAS_MOCA_LINK_DET,
3792 .bp_in_en_shift = 17,
3793 .bp_in_mask = 0x1ffff,
3794 .hfb_filter_cnt = 48,
3795 .hfb_filter_size = 128,
3797 .tbuf_offset = 0x0600,
3798 .hfb_offset = 0x8000,
3799 .hfb_reg_offset = 0xfc00,
3800 .rdma_offset = 0x2000,
3801 .tdma_offset = 0x4000,
3803 .flags = GENET_HAS_40BITS | GENET_HAS_EXT |
3804 GENET_HAS_MDIO_INTR | GENET_HAS_MOCA_LINK_DET,
3808 /* Infer hardware parameters from the detected GENET version */
3809 static void bcmgenet_set_hw_params(struct bcmgenet_priv *priv)
3811 struct bcmgenet_hw_params *params;
3816 if (GENET_IS_V5(priv) || GENET_IS_V4(priv)) {
3817 bcmgenet_dma_regs = bcmgenet_dma_regs_v3plus;
3818 genet_dma_ring_regs = genet_dma_ring_regs_v4;
3819 } else if (GENET_IS_V3(priv)) {
3820 bcmgenet_dma_regs = bcmgenet_dma_regs_v3plus;
3821 genet_dma_ring_regs = genet_dma_ring_regs_v123;
3822 } else if (GENET_IS_V2(priv)) {
3823 bcmgenet_dma_regs = bcmgenet_dma_regs_v2;
3824 genet_dma_ring_regs = genet_dma_ring_regs_v123;
3825 } else if (GENET_IS_V1(priv)) {
3826 bcmgenet_dma_regs = bcmgenet_dma_regs_v1;
3827 genet_dma_ring_regs = genet_dma_ring_regs_v123;
3830 /* enum genet_version starts at 1 */
3831 priv->hw_params = &bcmgenet_hw_params[priv->version];
3832 params = priv->hw_params;
3834 /* Read GENET HW version */
3835 reg = bcmgenet_sys_readl(priv, SYS_REV_CTRL);
3836 major = (reg >> 24 & 0x0f);
3839 else if (major == 5)
3841 else if (major == 0)
3843 if (major != priv->version) {
3844 dev_err(&priv->pdev->dev,
3845 "GENET version mismatch, got: %d, configured for: %d\n",
3846 major, priv->version);
3849 /* Print the GENET core version */
3850 dev_info(&priv->pdev->dev, "GENET " GENET_VER_FMT,
3851 major, (reg >> 16) & 0x0f, reg & 0xffff);
3853 /* Store the integrated PHY revision for the MDIO probing function
3854 * to pass this information to the PHY driver. The PHY driver expects
3855 * to find the PHY major revision in bits 15:8 while the GENET register
3856 * stores that information in bits 7:0, account for that.
3858 * On newer chips, starting with PHY revision G0, a new scheme is
3859 * deployed similar to the Starfighter 2 switch with GPHY major
3860 * revision in bits 15:8 and patch level in bits 7:0. Major revision 0
3861 * is reserved as well as special value 0x01ff, we have a small
3862 * heuristic to check for the new GPHY revision and re-arrange things
3863 * so the GPHY driver is happy.
3865 gphy_rev = reg & 0xffff;
3867 if (GENET_IS_V5(priv)) {
3868 /* The EPHY revision should come from the MDIO registers of
3869 * the PHY not from GENET.
3871 if (gphy_rev != 0) {
3872 pr_warn("GENET is reporting EPHY revision: 0x%04x\n",
3875 /* This is reserved so should require special treatment */
3876 } else if (gphy_rev == 0 || gphy_rev == 0x01ff) {
3877 pr_warn("Invalid GPHY revision detected: 0x%04x\n", gphy_rev);
3879 /* This is the good old scheme, just GPHY major, no minor nor patch */
3880 } else if ((gphy_rev & 0xf0) != 0) {
3881 priv->gphy_rev = gphy_rev << 8;
3882 /* This is the new scheme, GPHY major rolls over with 0x10 = rev G0 */
3883 } else if ((gphy_rev & 0xff00) != 0) {
3884 priv->gphy_rev = gphy_rev;
3887 #ifdef CONFIG_PHYS_ADDR_T_64BIT
3888 if (!(params->flags & GENET_HAS_40BITS))
3889 pr_warn("GENET does not support 40-bits PA\n");
3892 pr_debug("Configuration for version: %d\n"
3893 "TXq: %1d, TXqBDs: %1d, RXq: %1d, RXqBDs: %1d\n"
3894 "BP << en: %2d, BP msk: 0x%05x\n"
3895 "HFB count: %2d, QTAQ msk: 0x%05x\n"
3896 "TBUF: 0x%04x, HFB: 0x%04x, HFBreg: 0x%04x\n"
3897 "RDMA: 0x%05x, TDMA: 0x%05x\n"
3900 params->tx_queues, params->tx_bds_per_q,
3901 params->rx_queues, params->rx_bds_per_q,
3902 params->bp_in_en_shift, params->bp_in_mask,
3903 params->hfb_filter_cnt, params->qtag_mask,
3904 params->tbuf_offset, params->hfb_offset,
3905 params->hfb_reg_offset,
3906 params->rdma_offset, params->tdma_offset,
3907 params->words_per_bd);
3910 struct bcmgenet_plat_data {
3911 enum bcmgenet_version version;
3912 u32 dma_max_burst_length;
3915 static const struct bcmgenet_plat_data v1_plat_data = {
3916 .version = GENET_V1,
3917 .dma_max_burst_length = DMA_MAX_BURST_LENGTH,
3920 static const struct bcmgenet_plat_data v2_plat_data = {
3921 .version = GENET_V2,
3922 .dma_max_burst_length = DMA_MAX_BURST_LENGTH,
3925 static const struct bcmgenet_plat_data v3_plat_data = {
3926 .version = GENET_V3,
3927 .dma_max_burst_length = DMA_MAX_BURST_LENGTH,
3930 static const struct bcmgenet_plat_data v4_plat_data = {
3931 .version = GENET_V4,
3932 .dma_max_burst_length = DMA_MAX_BURST_LENGTH,
3935 static const struct bcmgenet_plat_data v5_plat_data = {
3936 .version = GENET_V5,
3937 .dma_max_burst_length = DMA_MAX_BURST_LENGTH,
3940 static const struct bcmgenet_plat_data bcm2711_plat_data = {
3941 .version = GENET_V5,
3942 .dma_max_burst_length = 0x08,
3945 static const struct of_device_id bcmgenet_match[] = {
3946 { .compatible = "brcm,genet-v1", .data = &v1_plat_data },
3947 { .compatible = "brcm,genet-v2", .data = &v2_plat_data },
3948 { .compatible = "brcm,genet-v3", .data = &v3_plat_data },
3949 { .compatible = "brcm,genet-v4", .data = &v4_plat_data },
3950 { .compatible = "brcm,genet-v5", .data = &v5_plat_data },
3951 { .compatible = "brcm,bcm2711-genet-v5", .data = &bcm2711_plat_data },
3954 MODULE_DEVICE_TABLE(of, bcmgenet_match);
3956 static int bcmgenet_probe(struct platform_device *pdev)
3958 struct bcmgenet_platform_data *pd = pdev->dev.platform_data;
3959 const struct bcmgenet_plat_data *pdata;
3960 struct bcmgenet_priv *priv;
3961 struct net_device *dev;
3965 /* Up to GENET_MAX_MQ_CNT + 1 TX queues and RX queues */
3966 dev = alloc_etherdev_mqs(sizeof(*priv), GENET_MAX_MQ_CNT + 1,
3967 GENET_MAX_MQ_CNT + 1);
3969 dev_err(&pdev->dev, "can't allocate net device\n");
3973 priv = netdev_priv(dev);
3974 priv->irq0 = platform_get_irq(pdev, 0);
3975 if (priv->irq0 < 0) {
3979 priv->irq1 = platform_get_irq(pdev, 1);
3980 if (priv->irq1 < 0) {
3984 priv->wol_irq = platform_get_irq_optional(pdev, 2);
3986 priv->base = devm_platform_ioremap_resource(pdev, 0);
3987 if (IS_ERR(priv->base)) {
3988 err = PTR_ERR(priv->base);
3992 spin_lock_init(&priv->lock);
3994 /* Set default pause parameters */
3995 priv->autoneg_pause = 1;
3999 SET_NETDEV_DEV(dev, &pdev->dev);
4000 dev_set_drvdata(&pdev->dev, dev);
4001 dev->watchdog_timeo = 2 * HZ;
4002 dev->ethtool_ops = &bcmgenet_ethtool_ops;
4003 dev->netdev_ops = &bcmgenet_netdev_ops;
4005 priv->msg_enable = netif_msg_init(-1, GENET_MSG_DEFAULT);
4007 /* Set default features */
4008 dev->features |= NETIF_F_SG | NETIF_F_HIGHDMA | NETIF_F_HW_CSUM |
4010 dev->hw_features |= dev->features;
4011 dev->vlan_features |= dev->features;
4013 /* Request the WOL interrupt and advertise suspend if available */
4014 priv->wol_irq_disabled = true;
4015 err = devm_request_irq(&pdev->dev, priv->wol_irq, bcmgenet_wol_isr, 0,
4018 device_set_wakeup_capable(&pdev->dev, 1);
4020 /* Set the needed headroom to account for any possible
4021 * features enabling/disabling at runtime
4023 dev->needed_headroom += 64;
4028 pdata = device_get_match_data(&pdev->dev);
4030 priv->version = pdata->version;
4031 priv->dma_max_burst_length = pdata->dma_max_burst_length;
4033 priv->version = pd->genet_version;
4034 priv->dma_max_burst_length = DMA_MAX_BURST_LENGTH;
4037 priv->clk = devm_clk_get_optional(&priv->pdev->dev, "enet");
4038 if (IS_ERR(priv->clk)) {
4039 dev_dbg(&priv->pdev->dev, "failed to get enet clock\n");
4040 err = PTR_ERR(priv->clk);
4044 err = clk_prepare_enable(priv->clk);
4048 bcmgenet_set_hw_params(priv);
4051 if (priv->hw_params->flags & GENET_HAS_40BITS)
4052 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(40));
4054 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
4056 goto err_clk_disable;
4058 /* Mii wait queue */
4059 init_waitqueue_head(&priv->wq);
4060 /* Always use RX_BUF_LENGTH (2KB) buffer for all chips */
4061 priv->rx_buf_len = RX_BUF_LENGTH;
4062 INIT_WORK(&priv->bcmgenet_irq_work, bcmgenet_irq_task);
4064 priv->clk_wol = devm_clk_get_optional(&priv->pdev->dev, "enet-wol");
4065 if (IS_ERR(priv->clk_wol)) {
4066 dev_dbg(&priv->pdev->dev, "failed to get enet-wol clock\n");
4067 err = PTR_ERR(priv->clk_wol);
4068 goto err_clk_disable;
4071 priv->clk_eee = devm_clk_get_optional(&priv->pdev->dev, "enet-eee");
4072 if (IS_ERR(priv->clk_eee)) {
4073 dev_dbg(&priv->pdev->dev, "failed to get enet-eee clock\n");
4074 err = PTR_ERR(priv->clk_eee);
4075 goto err_clk_disable;
4078 /* If this is an internal GPHY, power it on now, before UniMAC is
4079 * brought out of reset as absolutely no UniMAC activity is allowed
4081 if (device_get_phy_mode(&pdev->dev) == PHY_INTERFACE_MODE_INTERNAL)
4082 bcmgenet_power_up(priv, GENET_POWER_PASSIVE);
4084 if (pd && !IS_ERR_OR_NULL(pd->mac_address))
4085 eth_hw_addr_set(dev, pd->mac_address);
4087 if (!device_get_mac_address(&pdev->dev, dev->dev_addr, ETH_ALEN))
4088 if (has_acpi_companion(&pdev->dev))
4089 bcmgenet_get_hw_addr(priv, dev->dev_addr);
4091 if (!is_valid_ether_addr(dev->dev_addr)) {
4092 dev_warn(&pdev->dev, "using random Ethernet MAC\n");
4093 eth_hw_addr_random(dev);
4098 err = bcmgenet_mii_init(dev);
4100 goto err_clk_disable;
4102 /* setup number of real queues + 1 (GENET_V1 has 0 hardware queues
4103 * just the ring 16 descriptor based TX
4105 netif_set_real_num_tx_queues(priv->dev, priv->hw_params->tx_queues + 1);
4106 netif_set_real_num_rx_queues(priv->dev, priv->hw_params->rx_queues + 1);
4108 /* Set default coalescing parameters */
4109 for (i = 0; i < priv->hw_params->rx_queues; i++)
4110 priv->rx_rings[i].rx_max_coalesced_frames = 1;
4111 priv->rx_rings[DESC_INDEX].rx_max_coalesced_frames = 1;
4113 /* libphy will determine the link state */
4114 netif_carrier_off(dev);
4116 /* Turn off the main clock, WOL clock is handled separately */
4117 clk_disable_unprepare(priv->clk);
4119 err = register_netdev(dev);
4121 bcmgenet_mii_exit(dev);
4128 clk_disable_unprepare(priv->clk);
4134 static int bcmgenet_remove(struct platform_device *pdev)
4136 struct bcmgenet_priv *priv = dev_to_priv(&pdev->dev);
4138 dev_set_drvdata(&pdev->dev, NULL);
4139 unregister_netdev(priv->dev);
4140 bcmgenet_mii_exit(priv->dev);
4141 free_netdev(priv->dev);
4146 static void bcmgenet_shutdown(struct platform_device *pdev)
4148 bcmgenet_remove(pdev);
4151 #ifdef CONFIG_PM_SLEEP
4152 static int bcmgenet_resume_noirq(struct device *d)
4154 struct net_device *dev = dev_get_drvdata(d);
4155 struct bcmgenet_priv *priv = netdev_priv(dev);
4159 if (!netif_running(dev))
4162 /* Turn on the clock */
4163 ret = clk_prepare_enable(priv->clk);
4167 if (device_may_wakeup(d) && priv->wolopts) {
4168 /* Account for Wake-on-LAN events and clear those events
4169 * (Some devices need more time between enabling the clocks
4170 * and the interrupt register reflecting the wake event so
4171 * read the register twice)
4173 reg = bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_STAT);
4174 reg = bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_STAT);
4175 if (reg & UMAC_IRQ_WAKE_EVENT)
4176 pm_wakeup_event(&priv->pdev->dev, 0);
4179 bcmgenet_intrl2_0_writel(priv, UMAC_IRQ_WAKE_EVENT, INTRL2_CPU_CLEAR);
4184 static int bcmgenet_resume(struct device *d)
4186 struct net_device *dev = dev_get_drvdata(d);
4187 struct bcmgenet_priv *priv = netdev_priv(dev);
4188 struct bcmgenet_rxnfc_rule *rule;
4189 unsigned long dma_ctrl;
4192 if (!netif_running(dev))
4195 /* From WOL-enabled suspend, switch to regular clock */
4196 if (device_may_wakeup(d) && priv->wolopts)
4197 bcmgenet_power_up(priv, GENET_POWER_WOL_MAGIC);
4199 /* If this is an internal GPHY, power it back on now, before UniMAC is
4200 * brought out of reset as absolutely no UniMAC activity is allowed
4202 if (priv->internal_phy)
4203 bcmgenet_power_up(priv, GENET_POWER_PASSIVE);
4205 bcmgenet_umac_reset(priv);
4209 phy_init_hw(dev->phydev);
4211 /* Speed settings must be restored */
4212 genphy_config_aneg(dev->phydev);
4213 bcmgenet_mii_config(priv->dev, false);
4215 /* Restore enabled features */
4216 bcmgenet_set_features(dev, dev->features);
4218 bcmgenet_set_hw_addr(priv, dev->dev_addr);
4220 /* Restore hardware filters */
4221 bcmgenet_hfb_clear(priv);
4222 list_for_each_entry(rule, &priv->rxnfc_list, list)
4223 if (rule->state != BCMGENET_RXNFC_STATE_UNUSED)
4224 bcmgenet_hfb_create_rxnfc_filter(priv, rule);
4226 /* Disable RX/TX DMA and flush TX queues */
4227 dma_ctrl = bcmgenet_dma_disable(priv);
4229 /* Reinitialize TDMA and RDMA and SW housekeeping */
4230 ret = bcmgenet_init_dma(priv);
4232 netdev_err(dev, "failed to initialize DMA\n");
4233 goto out_clk_disable;
4236 /* Always enable ring 16 - descriptor ring */
4237 bcmgenet_enable_dma(priv, dma_ctrl);
4239 if (!device_may_wakeup(d))
4240 phy_resume(dev->phydev);
4242 if (priv->eee.eee_enabled)
4243 bcmgenet_eee_enable_set(dev, true);
4245 bcmgenet_netif_start(dev);
4247 netif_device_attach(dev);
4252 if (priv->internal_phy)
4253 bcmgenet_power_down(priv, GENET_POWER_PASSIVE);
4254 clk_disable_unprepare(priv->clk);
4258 static int bcmgenet_suspend(struct device *d)
4260 struct net_device *dev = dev_get_drvdata(d);
4261 struct bcmgenet_priv *priv = netdev_priv(dev);
4263 if (!netif_running(dev))
4266 netif_device_detach(dev);
4268 bcmgenet_netif_stop(dev);
4270 if (!device_may_wakeup(d))
4271 phy_suspend(dev->phydev);
4273 /* Disable filtering */
4274 bcmgenet_hfb_reg_writel(priv, 0, HFB_CTRL);
4279 static int bcmgenet_suspend_noirq(struct device *d)
4281 struct net_device *dev = dev_get_drvdata(d);
4282 struct bcmgenet_priv *priv = netdev_priv(dev);
4285 if (!netif_running(dev))
4288 /* Prepare the device for Wake-on-LAN and switch to the slow clock */
4289 if (device_may_wakeup(d) && priv->wolopts)
4290 ret = bcmgenet_power_down(priv, GENET_POWER_WOL_MAGIC);
4291 else if (priv->internal_phy)
4292 ret = bcmgenet_power_down(priv, GENET_POWER_PASSIVE);
4294 /* Let the framework handle resumption and leave the clocks on */
4298 /* Turn off the clocks */
4299 clk_disable_unprepare(priv->clk);
4304 #define bcmgenet_suspend NULL
4305 #define bcmgenet_suspend_noirq NULL
4306 #define bcmgenet_resume NULL
4307 #define bcmgenet_resume_noirq NULL
4308 #endif /* CONFIG_PM_SLEEP */
4310 static const struct dev_pm_ops bcmgenet_pm_ops = {
4311 .suspend = bcmgenet_suspend,
4312 .suspend_noirq = bcmgenet_suspend_noirq,
4313 .resume = bcmgenet_resume,
4314 .resume_noirq = bcmgenet_resume_noirq,
4317 static const struct acpi_device_id genet_acpi_match[] = {
4318 { "BCM6E4E", (kernel_ulong_t)&bcm2711_plat_data },
4321 MODULE_DEVICE_TABLE(acpi, genet_acpi_match);
4323 static struct platform_driver bcmgenet_driver = {
4324 .probe = bcmgenet_probe,
4325 .remove = bcmgenet_remove,
4326 .shutdown = bcmgenet_shutdown,
4329 .of_match_table = bcmgenet_match,
4330 .pm = &bcmgenet_pm_ops,
4331 .acpi_match_table = genet_acpi_match,
4334 module_platform_driver(bcmgenet_driver);
4336 MODULE_AUTHOR("Broadcom Corporation");
4337 MODULE_DESCRIPTION("Broadcom GENET Ethernet controller driver");
4338 MODULE_ALIAS("platform:bcmgenet");
4339 MODULE_LICENSE("GPL");
4340 MODULE_SOFTDEP("pre: mdio-bcm-unimac");