1 /* Broadcom NetXtreme-C/E network driver.
3 * Copyright (c) 2014-2016 Broadcom Corporation
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
13 /* per-context HW statistics -- chip view */
18 __le64 rx_discard_pkts;
20 __le64 rx_ucast_bytes;
21 __le64 rx_mcast_bytes;
22 __le64 rx_bcast_bytes;
26 __le64 tx_discard_pkts;
28 __le64 tx_ucast_bytes;
29 __le64 tx_mcast_bytes;
30 __le64 tx_bcast_bytes;
37 /* Statistics Ejection Buffer Completion Record (16 bytes) */
40 #define EJECT_CMPL_TYPE_MASK 0x3fUL
41 #define EJECT_CMPL_TYPE_SFT 0
42 #define EJECT_CMPL_TYPE_STAT_EJECT (0x1aUL << 0)
46 #define EJECT_CMPL_V 0x1UL
50 /* HWRM Completion Record (16 bytes) */
53 #define HWRM_CMPL_TYPE_MASK 0x3fUL
54 #define HWRM_CMPL_TYPE_SFT 0
55 #define HWRM_CMPL_TYPE_HWRM_DONE (0x20UL << 0)
59 #define HWRM_CMPL_V 0x1UL
63 /* HWRM Forwarded Request (16 bytes) */
64 struct hwrm_fwd_req_cmpl {
66 #define HWRM_FWD_REQ_CMPL_TYPE_MASK 0x3fUL
67 #define HWRM_FWD_REQ_CMPL_TYPE_SFT 0
68 #define HWRM_FWD_REQ_CMPL_TYPE_HWRM_FWD_REQ (0x22UL << 0)
69 #define HWRM_FWD_REQ_CMPL_REQ_LEN_MASK 0xffc0UL
70 #define HWRM_FWD_REQ_CMPL_REQ_LEN_SFT 6
73 __le32 req_buf_addr_v[2];
74 #define HWRM_FWD_REQ_CMPL_V 0x1UL
75 #define HWRM_FWD_REQ_CMPL_REQ_BUF_ADDR_MASK 0xfffffffeUL
76 #define HWRM_FWD_REQ_CMPL_REQ_BUF_ADDR_SFT 1
79 /* HWRM Forwarded Response (16 bytes) */
80 struct hwrm_fwd_resp_cmpl {
82 #define HWRM_FWD_RESP_CMPL_TYPE_MASK 0x3fUL
83 #define HWRM_FWD_RESP_CMPL_TYPE_SFT 0
84 #define HWRM_FWD_RESP_CMPL_TYPE_HWRM_FWD_RESP (0x24UL << 0)
88 __le32 resp_buf_addr_v[2];
89 #define HWRM_FWD_RESP_CMPL_V 0x1UL
90 #define HWRM_FWD_RESP_CMPL_RESP_BUF_ADDR_MASK 0xfffffffeUL
91 #define HWRM_FWD_RESP_CMPL_RESP_BUF_ADDR_SFT 1
94 /* HWRM Asynchronous Event Completion Record (16 bytes) */
95 struct hwrm_async_event_cmpl {
97 #define HWRM_ASYNC_EVENT_CMPL_TYPE_MASK 0x3fUL
98 #define HWRM_ASYNC_EVENT_CMPL_TYPE_SFT 0
99 #define HWRM_ASYNC_EVENT_CMPL_TYPE_HWRM_ASYNC_EVENT (0x2eUL << 0)
101 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE (0x0UL << 0)
102 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_MTU_CHANGE (0x1UL << 0)
103 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CHANGE (0x2UL << 0)
104 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_DCB_CONFIG_CHANGE (0x3UL << 0)
105 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED (0x4UL << 0)
106 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_NOT_ALLOWED (0x5UL << 0)
107 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE (0x6UL << 0)
108 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_UNLOAD (0x10UL << 0)
109 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_LOAD (0x11UL << 0)
110 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD (0x20UL << 0)
111 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_LOAD (0x21UL << 0)
112 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_VF_FLR (0x30UL << 0)
113 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_VF_MAC_ADDR_CHANGE (0x31UL << 0)
114 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PF_VF_COMM_STATUS_CHANGE (0x32UL << 0)
115 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE (0x33UL << 0)
116 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR (0xffUL << 0)
119 #define HWRM_ASYNC_EVENT_CMPL_V 0x1UL
120 #define HWRM_ASYNC_EVENT_CMPL_OPAQUE_MASK 0xfeUL
121 #define HWRM_ASYNC_EVENT_CMPL_OPAQUE_SFT 1
127 /* HWRM Asynchronous Event Completion Record for link status change (16 bytes) */
128 struct hwrm_async_event_cmpl_link_status_change {
130 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_MASK 0x3fUL
131 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_SFT 0
132 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT (0x2eUL << 0)
134 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LINK_STATUS_CHANGE (0x0UL << 0)
137 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_V 0x1UL
138 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_OPAQUE_MASK 0xfeUL
139 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_OPAQUE_SFT 1
143 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE 0x1UL
144 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_DOWN (0x0UL << 0)
145 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_UP (0x1UL << 0)
146 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_LAST HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_UP
147 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_MASK 0xeUL
148 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_SFT 1
149 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_ID_MASK 0xffff0UL
150 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_ID_SFT 4
153 /* HWRM Asynchronous Event Completion Record for link MTU change (16 bytes) */
154 struct hwrm_async_event_cmpl_link_mtu_change {
156 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_MASK 0x3fUL
157 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_SFT 0
158 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_HWRM_ASYNC_EVENT (0x2eUL << 0)
160 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_ID_LINK_MTU_CHANGE (0x1UL << 0)
163 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_V 0x1UL
164 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_OPAQUE_MASK 0xfeUL
165 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_OPAQUE_SFT 1
169 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_DATA1_NEW_MTU_MASK 0xffffUL
170 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_DATA1_NEW_MTU_SFT 0
173 /* HWRM Asynchronous Event Completion Record for link speed change (16 bytes) */
174 struct hwrm_async_event_cmpl_link_speed_change {
176 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_MASK 0x3fUL
177 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_SFT 0
178 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_HWRM_ASYNC_EVENT (0x2eUL << 0)
180 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_ID_LINK_SPEED_CHANGE (0x2UL << 0)
183 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_V 0x1UL
184 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_OPAQUE_MASK 0xfeUL
185 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_OPAQUE_SFT 1
189 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_FORCE 0x1UL
190 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_MASK 0xfffeUL
191 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_SFT 1
192 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_100MB (0x1UL << 1)
193 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_1GB (0xaUL << 1)
194 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_2GB (0x14UL << 1)
195 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_2_5GB (0x19UL << 1)
196 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_10GB (0x64UL << 1)
197 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_20GB (0xc8UL << 1)
198 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_25GB (0xfaUL << 1)
199 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_40GB (0x190UL << 1)
200 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_50GB (0x1f4UL << 1)
201 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_100GB (0x3e8UL << 1)
202 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_10MB (0xffffUL << 1)
203 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_LAST HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_10MB
204 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_PORT_ID_MASK 0xffff0000UL
205 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_PORT_ID_SFT 16
208 /* HWRM Asynchronous Event Completion Record for DCB Config change (16 bytes) */
209 struct hwrm_async_event_cmpl_dcb_config_change {
211 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_MASK 0x3fUL
212 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_SFT 0
213 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_HWRM_ASYNC_EVENT (0x2eUL << 0)
215 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_ID_DCB_CONFIG_CHANGE (0x3UL << 0)
218 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_V 0x1UL
219 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_OPAQUE_MASK 0xfeUL
220 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_OPAQUE_SFT 1
224 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_PORT_ID_MASK 0xffffUL
225 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_PORT_ID_SFT 0
228 /* HWRM Asynchronous Event Completion Record for port connection not allowed (16 bytes) */
229 struct hwrm_async_event_cmpl_port_conn_not_allowed {
231 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_MASK 0x3fUL
232 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_SFT 0
233 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT (0x2eUL << 0)
235 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_PORT_CONN_NOT_ALLOWED (0x4UL << 0)
238 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_V 0x1UL
239 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_OPAQUE_MASK 0xfeUL
240 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_OPAQUE_SFT 1
244 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK 0xffffUL
245 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_SFT 0
246 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_MASK 0xff0000UL
247 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_SFT 16
248 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_NONE (0x0UL << 16)
249 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_DISABLETX (0x1UL << 16)
250 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_WARNINGMSG (0x2UL << 16)
251 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_PWRDOWN (0x3UL << 16)
252 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_LAST HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_PWRDOWN
255 /* HWRM Asynchronous Event Completion Record for link speed config not allowed (16 bytes) */
256 struct hwrm_async_event_cmpl_link_speed_cfg_not_allowed {
258 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_MASK 0x3fUL
259 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_SFT 0
260 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT (0x2eUL << 0)
262 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_ID_LINK_SPEED_CFG_NOT_ALLOWED (0x5UL << 0)
265 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_V 0x1UL
266 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_OPAQUE_MASK 0xfeUL
267 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_OPAQUE_SFT 1
271 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK 0xffffUL
272 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_DATA1_PORT_ID_SFT 0
275 /* HWRM Asynchronous Event Completion Record for link speed configuration change (16 bytes) */
276 struct hwrm_async_event_cmpl_link_speed_cfg_change {
278 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_MASK 0x3fUL
279 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_SFT 0
280 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT (0x2eUL << 0)
282 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LINK_SPEED_CFG_CHANGE (0x6UL << 0)
285 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_V 0x1UL
286 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_OPAQUE_MASK 0xfeUL
287 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_OPAQUE_SFT 1
291 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_PORT_ID_MASK 0xffffUL
292 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_PORT_ID_SFT 0
293 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_SUPPORTED_LINK_SPEEDS_CHANGE 0x10000UL
294 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_ILLEGAL_LINK_SPEED_CFG 0x20000UL
297 /* HWRM Asynchronous Event Completion Record for Function Driver Unload (16 bytes) */
298 struct hwrm_async_event_cmpl_func_drvr_unload {
300 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_MASK 0x3fUL
301 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_SFT 0
302 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_HWRM_ASYNC_EVENT (0x2eUL << 0)
304 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_ID_FUNC_DRVR_UNLOAD (0x10UL << 0)
307 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_V 0x1UL
308 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_OPAQUE_MASK 0xfeUL
309 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_OPAQUE_SFT 1
313 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_MASK 0xffffUL
314 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_SFT 0
317 /* HWRM Asynchronous Event Completion Record for Function Driver load (16 bytes) */
318 struct hwrm_async_event_cmpl_func_drvr_load {
320 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_MASK 0x3fUL
321 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_SFT 0
322 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_HWRM_ASYNC_EVENT (0x2eUL << 0)
324 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_ID_FUNC_DRVR_LOAD (0x11UL << 0)
327 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_V 0x1UL
328 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_OPAQUE_MASK 0xfeUL
329 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_OPAQUE_SFT 1
333 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_DATA1_FUNC_ID_MASK 0xffffUL
334 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_DATA1_FUNC_ID_SFT 0
337 /* HWRM Asynchronous Event Completion Record for PF Driver Unload (16 bytes) */
338 struct hwrm_async_event_cmpl_pf_drvr_unload {
340 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_MASK 0x3fUL
341 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_SFT 0
342 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_HWRM_ASYNC_EVENT (0x2eUL << 0)
344 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_ID_PF_DRVR_UNLOAD (0x20UL << 0)
347 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_V 0x1UL
348 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_OPAQUE_MASK 0xfeUL
349 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_OPAQUE_SFT 1
353 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_MASK 0xffffUL
354 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_SFT 0
355 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_PORT_MASK 0x70000UL
356 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_PORT_SFT 16
359 /* HWRM Asynchronous Event Completion Record for PF Driver load (16 bytes) */
360 struct hwrm_async_event_cmpl_pf_drvr_load {
362 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_MASK 0x3fUL
363 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_SFT 0
364 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_HWRM_ASYNC_EVENT (0x2eUL << 0)
366 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_ID_PF_DRVR_LOAD (0x21UL << 0)
369 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_V 0x1UL
370 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_OPAQUE_MASK 0xfeUL
371 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_OPAQUE_SFT 1
375 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_FUNC_ID_MASK 0xffffUL
376 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_FUNC_ID_SFT 0
377 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_PORT_MASK 0x70000UL
378 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_PORT_SFT 16
381 /* HWRM Asynchronous Event Completion Record for VF FLR (16 bytes) */
382 struct hwrm_async_event_cmpl_vf_flr {
384 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_TYPE_MASK 0x3fUL
385 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_TYPE_SFT 0
386 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_TYPE_HWRM_ASYNC_EVENT (0x2eUL << 0)
388 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_ID_VF_FLR (0x30UL << 0)
391 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_V 0x1UL
392 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_OPAQUE_MASK 0xfeUL
393 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_OPAQUE_SFT 1
397 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_DATA1_VF_ID_MASK 0xffffUL
398 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_DATA1_VF_ID_SFT 0
401 /* HWRM Asynchronous Event Completion Record for VF MAC Addr change (16 bytes) */
402 struct hwrm_async_event_cmpl_vf_mac_addr_change {
404 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_MASK 0x3fUL
405 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_SFT 0
406 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_HWRM_ASYNC_EVENT (0x2eUL << 0)
408 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_ID_VF_MAC_ADDR_CHANGE (0x31UL << 0)
411 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_V 0x1UL
412 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_OPAQUE_MASK 0xfeUL
413 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_OPAQUE_SFT 1
417 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_DATA1_VF_ID_MASK 0xffffUL
418 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_DATA1_VF_ID_SFT 0
421 /* HWRM Asynchronous Event Completion Record for PF-VF communication status change (16 bytes) */
422 struct hwrm_async_event_cmpl_pf_vf_comm_status_change {
424 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_MASK 0x3fUL
425 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_SFT 0
426 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT (0x2eUL << 0)
428 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_EVENT_ID_PF_VF_COMM_STATUS_CHANGE (0x32UL << 0)
431 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_V 0x1UL
432 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_OPAQUE_MASK 0xfeUL
433 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_OPAQUE_SFT 1
437 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_EVENT_DATA1_COMM_ESTABLISHED 0x1UL
440 /* HWRM Asynchronous Event Completion Record for VF configuration change (16 bytes) */
441 struct hwrm_async_event_cmpl_vf_cfg_change {
443 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_MASK 0x3fUL
444 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_SFT 0
445 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT (0x2eUL << 0)
447 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_VF_CFG_CHANGE (0x33UL << 0)
450 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_V 0x1UL
451 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_OPAQUE_MASK 0xfeUL
452 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_OPAQUE_SFT 1
456 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_MTU_CHANGE 0x1UL
457 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_MRU_CHANGE 0x2UL
458 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_DFLT_MAC_ADDR_CHANGE 0x4UL
459 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_DFLT_VLAN_CHANGE 0x8UL
462 /* HWRM Asynchronous Event Completion Record for HWRM Error (16 bytes) */
463 struct hwrm_async_event_cmpl_hwrm_error {
465 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_MASK 0x3fUL
466 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_SFT 0
467 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_HWRM_ASYNC_EVENT (0x2eUL << 0)
469 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_ID_HWRM_ERROR (0xffUL << 0)
471 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_MASK 0xffUL
472 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_SFT 0
473 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_WARNING (0x0UL << 0)
474 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_NONFATAL (0x1UL << 0)
475 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_FATAL (0x2UL << 0)
476 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_LAST HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_FATAL
478 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_V 0x1UL
479 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_OPAQUE_MASK 0xfeUL
480 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_OPAQUE_SFT 1
484 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA1_TIMESTAMP 0x1UL
487 /* HW Resource Manager Specification 1.2.2 */
488 #define HWRM_VERSION_MAJOR 1
489 #define HWRM_VERSION_MINOR 2
490 #define HWRM_VERSION_UPDATE 2
492 #define HWRM_VERSION_STR "1.2.2"
494 * Following is the signature for HWRM message field that indicates not
495 * applicable (All F's). Need to cast it the size of the field if needed.
497 #define HWRM_NA_SIGNATURE ((__le32)(-1))
498 #define HWRM_MAX_REQ_LEN (128) /* hwrm_func_buf_rgtr */
499 #define HWRM_MAX_RESP_LEN (176) /* hwrm_func_qstats */
500 #define HW_HASH_INDEX_SIZE 0x80 /* 7 bit indirection table index. */
501 #define HW_HASH_KEY_SIZE 40
502 #define HWRM_RESP_VALID_KEY 1 /* valid key for HWRM response */
503 /* Input (16 bytes) */
512 /* Output (8 bytes) */
520 /* Command numbering (8 bytes) */
523 #define HWRM_VER_GET (0x0UL)
524 #define HWRM_FUNC_BUF_UNRGTR (0xeUL)
525 #define HWRM_FUNC_VF_CFG (0xfUL)
526 #define RESERVED1 (0x10UL)
527 #define HWRM_FUNC_RESET (0x11UL)
528 #define HWRM_FUNC_GETFID (0x12UL)
529 #define HWRM_FUNC_VF_ALLOC (0x13UL)
530 #define HWRM_FUNC_VF_FREE (0x14UL)
531 #define HWRM_FUNC_QCAPS (0x15UL)
532 #define HWRM_FUNC_QCFG (0x16UL)
533 #define HWRM_FUNC_CFG (0x17UL)
534 #define HWRM_FUNC_QSTATS (0x18UL)
535 #define HWRM_FUNC_CLR_STATS (0x19UL)
536 #define HWRM_FUNC_DRV_UNRGTR (0x1aUL)
537 #define HWRM_FUNC_VF_RESC_FREE (0x1bUL)
538 #define HWRM_FUNC_VF_VNIC_IDS_QUERY (0x1cUL)
539 #define HWRM_FUNC_DRV_RGTR (0x1dUL)
540 #define HWRM_FUNC_DRV_QVER (0x1eUL)
541 #define HWRM_FUNC_BUF_RGTR (0x1fUL)
542 #define HWRM_PORT_PHY_CFG (0x20UL)
543 #define HWRM_PORT_MAC_CFG (0x21UL)
544 #define HWRM_PORT_TS_QUERY (0x22UL)
545 #define HWRM_PORT_QSTATS (0x23UL)
546 #define HWRM_PORT_LPBK_QSTATS (0x24UL)
547 #define HWRM_PORT_CLR_STATS (0x25UL)
548 #define HWRM_PORT_LPBK_CLR_STATS (0x26UL)
549 #define HWRM_PORT_PHY_QCFG (0x27UL)
550 #define HWRM_PORT_MAC_QCFG (0x28UL)
551 #define HWRM_PORT_BLINK_LED (0x29UL)
552 #define HWRM_PORT_PHY_QCAPS (0x2aUL)
553 #define HWRM_PORT_PHY_I2C_WRITE (0x2bUL)
554 #define HWRM_PORT_PHY_I2C_READ (0x2cUL)
555 #define HWRM_QUEUE_QPORTCFG (0x30UL)
556 #define HWRM_QUEUE_QCFG (0x31UL)
557 #define HWRM_QUEUE_CFG (0x32UL)
558 #define HWRM_QUEUE_BUFFERS_QCFG (0x33UL)
559 #define HWRM_QUEUE_BUFFERS_CFG (0x34UL)
560 #define HWRM_QUEUE_PFCENABLE_QCFG (0x35UL)
561 #define HWRM_QUEUE_PFCENABLE_CFG (0x36UL)
562 #define HWRM_QUEUE_PRI2COS_QCFG (0x37UL)
563 #define HWRM_QUEUE_PRI2COS_CFG (0x38UL)
564 #define HWRM_QUEUE_COS2BW_QCFG (0x39UL)
565 #define HWRM_QUEUE_COS2BW_CFG (0x3aUL)
566 #define HWRM_VNIC_ALLOC (0x40UL)
567 #define HWRM_VNIC_FREE (0x41UL)
568 #define HWRM_VNIC_CFG (0x42UL)
569 #define HWRM_VNIC_QCFG (0x43UL)
570 #define HWRM_VNIC_TPA_CFG (0x44UL)
571 #define HWRM_VNIC_TPA_QCFG (0x45UL)
572 #define HWRM_VNIC_RSS_CFG (0x46UL)
573 #define HWRM_VNIC_RSS_QCFG (0x47UL)
574 #define HWRM_VNIC_PLCMODES_CFG (0x48UL)
575 #define HWRM_VNIC_PLCMODES_QCFG (0x49UL)
576 #define HWRM_RING_ALLOC (0x50UL)
577 #define HWRM_RING_FREE (0x51UL)
578 #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS (0x52UL)
579 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS (0x53UL)
580 #define HWRM_RING_RESET (0x5eUL)
581 #define HWRM_RING_GRP_ALLOC (0x60UL)
582 #define HWRM_RING_GRP_FREE (0x61UL)
583 #define HWRM_VNIC_RSS_COS_LB_CTX_ALLOC (0x70UL)
584 #define HWRM_VNIC_RSS_COS_LB_CTX_FREE (0x71UL)
585 #define HWRM_CFA_L2_FILTER_ALLOC (0x90UL)
586 #define HWRM_CFA_L2_FILTER_FREE (0x91UL)
587 #define HWRM_CFA_L2_FILTER_CFG (0x92UL)
588 #define HWRM_CFA_L2_SET_RX_MASK (0x93UL)
589 #define RESERVED3 (0x94UL)
590 #define HWRM_CFA_TUNNEL_FILTER_ALLOC (0x95UL)
591 #define HWRM_CFA_TUNNEL_FILTER_FREE (0x96UL)
592 #define HWRM_CFA_ENCAP_RECORD_ALLOC (0x97UL)
593 #define HWRM_CFA_ENCAP_RECORD_FREE (0x98UL)
594 #define HWRM_CFA_NTUPLE_FILTER_ALLOC (0x99UL)
595 #define HWRM_CFA_NTUPLE_FILTER_FREE (0x9aUL)
596 #define HWRM_CFA_NTUPLE_FILTER_CFG (0x9bUL)
597 #define HWRM_CFA_EM_FLOW_ALLOC (0x9cUL)
598 #define HWRM_CFA_EM_FLOW_FREE (0x9dUL)
599 #define HWRM_CFA_EM_FLOW_CFG (0x9eUL)
600 #define HWRM_TUNNEL_DST_PORT_QUERY (0xa0UL)
601 #define HWRM_TUNNEL_DST_PORT_ALLOC (0xa1UL)
602 #define HWRM_TUNNEL_DST_PORT_FREE (0xa2UL)
603 #define HWRM_STAT_CTX_ALLOC (0xb0UL)
604 #define HWRM_STAT_CTX_FREE (0xb1UL)
605 #define HWRM_STAT_CTX_QUERY (0xb2UL)
606 #define HWRM_STAT_CTX_CLR_STATS (0xb3UL)
607 #define HWRM_FW_RESET (0xc0UL)
608 #define HWRM_FW_QSTATUS (0xc1UL)
609 #define HWRM_EXEC_FWD_RESP (0xd0UL)
610 #define HWRM_REJECT_FWD_RESP (0xd1UL)
611 #define HWRM_FWD_RESP (0xd2UL)
612 #define HWRM_FWD_ASYNC_EVENT_CMPL (0xd3UL)
613 #define HWRM_TEMP_MONITOR_QUERY (0xe0UL)
614 #define HWRM_DBG_READ_DIRECT (0xff10UL)
615 #define HWRM_DBG_READ_INDIRECT (0xff11UL)
616 #define HWRM_DBG_WRITE_DIRECT (0xff12UL)
617 #define HWRM_DBG_WRITE_INDIRECT (0xff13UL)
618 #define HWRM_DBG_DUMP (0xff14UL)
619 #define HWRM_NVM_MODIFY (0xfff4UL)
620 #define HWRM_NVM_VERIFY_UPDATE (0xfff5UL)
621 #define HWRM_NVM_GET_DEV_INFO (0xfff6UL)
622 #define HWRM_NVM_ERASE_DIR_ENTRY (0xfff7UL)
623 #define HWRM_NVM_MOD_DIR_ENTRY (0xfff8UL)
624 #define HWRM_NVM_FIND_DIR_ENTRY (0xfff9UL)
625 #define HWRM_NVM_GET_DIR_ENTRIES (0xfffaUL)
626 #define HWRM_NVM_GET_DIR_INFO (0xfffbUL)
627 #define HWRM_NVM_RAW_DUMP (0xfffcUL)
628 #define HWRM_NVM_READ (0xfffdUL)
629 #define HWRM_NVM_WRITE (0xfffeUL)
630 #define HWRM_NVM_RAW_WRITE_BLK (0xffffUL)
634 /* Return Codes (8 bytes) */
637 #define HWRM_ERR_CODE_SUCCESS (0x0UL)
638 #define HWRM_ERR_CODE_FAIL (0x1UL)
639 #define HWRM_ERR_CODE_INVALID_PARAMS (0x2UL)
640 #define HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED (0x3UL)
641 #define HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR (0x4UL)
642 #define HWRM_ERR_CODE_INVALID_FLAGS (0x5UL)
643 #define HWRM_ERR_CODE_INVALID_ENABLES (0x6UL)
644 #define HWRM_ERR_CODE_HWRM_ERROR (0xfUL)
645 #define HWRM_ERR_CODE_UNKNOWN_ERR (0xfffeUL)
646 #define HWRM_ERR_CODE_CMD_NOT_SUPPORTED (0xffffUL)
650 /* Output (16 bytes) */
651 struct hwrm_err_output {
662 /* Port Tx Statistics Formats (408 bytes) */
663 struct tx_port_stats {
664 __le64 tx_64b_frames;
665 __le64 tx_65b_127b_frames;
666 __le64 tx_128b_255b_frames;
667 __le64 tx_256b_511b_frames;
668 __le64 tx_512b_1023b_frames;
669 __le64 tx_1024b_1518_frames;
670 __le64 tx_good_vlan_frames;
671 __le64 tx_1519b_2047_frames;
672 __le64 tx_2048b_4095b_frames;
673 __le64 tx_4096b_9216b_frames;
674 __le64 tx_9217b_16383b_frames;
675 __le64 tx_good_frames;
676 __le64 tx_total_frames;
677 __le64 tx_ucast_frames;
678 __le64 tx_mcast_frames;
679 __le64 tx_bcast_frames;
680 __le64 tx_pause_frames;
681 __le64 tx_pfc_frames;
682 __le64 tx_jabber_frames;
683 __le64 tx_fcs_err_frames;
684 __le64 tx_control_frames;
685 __le64 tx_oversz_frames;
686 __le64 tx_single_dfrl_frames;
687 __le64 tx_multi_dfrl_frames;
688 __le64 tx_single_coll_frames;
689 __le64 tx_multi_coll_frames;
690 __le64 tx_late_coll_frames;
691 __le64 tx_excessive_coll_frames;
692 __le64 tx_frag_frames;
694 __le64 tx_tagged_frames;
695 __le64 tx_dbl_tagged_frames;
696 __le64 tx_runt_frames;
697 __le64 tx_fifo_underruns;
698 __le64 tx_pfc_ena_frames_pri0;
699 __le64 tx_pfc_ena_frames_pri1;
700 __le64 tx_pfc_ena_frames_pri2;
701 __le64 tx_pfc_ena_frames_pri3;
702 __le64 tx_pfc_ena_frames_pri4;
703 __le64 tx_pfc_ena_frames_pri5;
704 __le64 tx_pfc_ena_frames_pri6;
705 __le64 tx_pfc_ena_frames_pri7;
706 __le64 tx_eee_lpi_events;
707 __le64 tx_eee_lpi_duration;
708 __le64 tx_llfc_logical_msgs;
710 __le64 tx_total_collisions;
712 __le64 tx_xthol_frames;
713 __le64 tx_stat_discard;
714 __le64 tx_stat_error;
717 /* Port Rx Statistics Formats (528 bytes) */
718 struct rx_port_stats {
719 __le64 rx_64b_frames;
720 __le64 rx_65b_127b_frames;
721 __le64 rx_128b_255b_frames;
722 __le64 rx_256b_511b_frames;
723 __le64 rx_512b_1023b_frames;
724 __le64 rx_1024b_1518_frames;
725 __le64 rx_good_vlan_frames;
726 __le64 rx_1519b_2047b_frames;
727 __le64 rx_2048b_4095b_frames;
728 __le64 rx_4096b_9216b_frames;
729 __le64 rx_9217b_16383b_frames;
730 __le64 rx_total_frames;
731 __le64 rx_ucast_frames;
732 __le64 rx_mcast_frames;
733 __le64 rx_bcast_frames;
734 __le64 rx_fcs_err_frames;
735 __le64 rx_ctrl_frames;
736 __le64 rx_pause_frames;
737 __le64 rx_pfc_frames;
738 __le64 rx_unsupported_opcode_frames;
739 __le64 rx_unsupported_da_pausepfc_frames;
740 __le64 rx_wrong_sa_frames;
741 __le64 rx_align_err_frames;
742 __le64 rx_oor_len_frames;
743 __le64 rx_code_err_frames;
744 __le64 rx_false_carrier_frames;
745 __le64 rx_ovrsz_frames;
746 __le64 rx_jbr_frames;
747 __le64 rx_mtu_err_frames;
748 __le64 rx_match_crc_frames;
749 __le64 rx_promiscuous_frames;
750 __le64 rx_tagged_frames;
751 __le64 rx_double_tagged_frames;
752 __le64 rx_trunc_frames;
753 __le64 rx_good_frames;
754 __le64 rx_pfc_xon2xoff_frames_pri0;
755 __le64 rx_pfc_xon2xoff_frames_pri1;
756 __le64 rx_pfc_xon2xoff_frames_pri2;
757 __le64 rx_pfc_xon2xoff_frames_pri3;
758 __le64 rx_pfc_xon2xoff_frames_pri4;
759 __le64 rx_pfc_xon2xoff_frames_pri5;
760 __le64 rx_pfc_xon2xoff_frames_pri6;
761 __le64 rx_pfc_xon2xoff_frames_pri7;
762 __le64 rx_pfc_ena_frames_pri0;
763 __le64 rx_pfc_ena_frames_pri1;
764 __le64 rx_pfc_ena_frames_pri2;
765 __le64 rx_pfc_ena_frames_pri3;
766 __le64 rx_pfc_ena_frames_pri4;
767 __le64 rx_pfc_ena_frames_pri5;
768 __le64 rx_pfc_ena_frames_pri6;
769 __le64 rx_pfc_ena_frames_pri7;
770 __le64 rx_sch_crc_err_frames;
771 __le64 rx_undrsz_frames;
772 __le64 rx_frag_frames;
773 __le64 rx_eee_lpi_events;
774 __le64 rx_eee_lpi_duration;
775 __le64 rx_llfc_physical_msgs;
776 __le64 rx_llfc_logical_msgs;
777 __le64 rx_llfc_msgs_with_crc_err;
779 __le64 rx_hcfc_msgs_with_crc_err;
781 __le64 rx_runt_bytes;
782 __le64 rx_runt_frames;
783 __le64 rx_stat_discard;
788 /* Input (24 bytes) */
789 struct hwrm_ver_get_input {
801 /* Output (128 bytes) */
802 struct hwrm_ver_get_output {
828 char hwrm_fw_name[16];
829 char mgmt_fw_name[16];
830 char netctrl_fw_name[16];
832 char roce_fw_name[16];
837 u8 chip_platform_type;
838 #define VER_GET_RESP_CHIP_PLATFORM_TYPE_ASIC (0x0UL << 0)
839 #define VER_GET_RESP_CHIP_PLATFORM_TYPE_FPGA (0x1UL << 0)
840 #define VER_GET_RESP_CHIP_PLATFORM_TYPE_PALLADIUM (0x2UL << 0)
841 __le16 max_req_win_len;
843 __le16 def_req_timeout;
850 /* hwrm_func_reset */
851 /* Input (24 bytes) */
852 struct hwrm_func_reset_input {
859 #define FUNC_RESET_REQ_ENABLES_VF_ID_VALID 0x1UL
862 #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETALL (0x0UL << 0)
863 #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETME (0x1UL << 0)
864 #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETCHILDREN (0x2UL << 0)
865 #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETVF (0x3UL << 0)
869 /* Output (16 bytes) */
870 struct hwrm_func_reset_output {
882 /* hwrm_func_getfid */
883 /* Input (24 bytes) */
884 struct hwrm_func_getfid_input {
891 #define FUNC_GETFID_REQ_ENABLES_PCI_ID 0x1UL
896 /* Output (16 bytes) */
897 struct hwrm_func_getfid_output {
911 /* hwrm_func_vf_alloc */
912 /* Input (24 bytes) */
913 struct hwrm_func_vf_alloc_input {
920 #define FUNC_VF_ALLOC_REQ_ENABLES_FIRST_VF_ID 0x1UL
925 /* Output (16 bytes) */
926 struct hwrm_func_vf_alloc_output {
940 /* hwrm_func_vf_free */
941 /* Input (24 bytes) */
942 struct hwrm_func_vf_free_input {
949 #define FUNC_VF_FREE_REQ_ENABLES_FIRST_VF_ID 0x1UL
954 /* Output (16 bytes) */
955 struct hwrm_func_vf_free_output {
967 /* hwrm_func_vf_cfg */
968 /* Input (32 bytes) */
969 struct hwrm_func_vf_cfg_input {
976 #define FUNC_VF_CFG_REQ_ENABLES_MTU 0x1UL
977 #define FUNC_VF_CFG_REQ_ENABLES_GUEST_VLAN 0x2UL
978 #define FUNC_VF_CFG_REQ_ENABLES_ASYNC_EVENT_CR 0x4UL
979 #define FUNC_VF_CFG_REQ_ENABLES_DFLT_MAC_ADDR 0x8UL
982 __le16 async_event_cr;
986 /* Output (16 bytes) */
987 struct hwrm_func_vf_cfg_output {
999 /* hwrm_func_qcaps */
1000 /* Input (24 bytes) */
1001 struct hwrm_func_qcaps_input {
1011 /* Output (80 bytes) */
1012 struct hwrm_func_qcaps_output {
1020 #define FUNC_QCAPS_RESP_FLAGS_PUSH_MODE_SUPPORTED 0x1UL
1021 #define FUNC_QCAPS_RESP_FLAGS_GLOBAL_MSIX_AUTOMASKING 0x2UL
1022 #define FUNC_QCAPS_RESP_FLAGS_PTP_SUPPORTED 0x4UL
1024 __le16 max_rsscos_ctx;
1025 __le16 max_cmpl_rings;
1026 __le16 max_tx_rings;
1027 __le16 max_rx_rings;
1032 __le16 max_stat_ctx;
1033 __le32 max_encap_records;
1034 __le32 max_decap_records;
1035 __le32 max_tx_em_flows;
1036 __le32 max_tx_wm_flows;
1037 __le32 max_rx_em_flows;
1038 __le32 max_rx_wm_flows;
1039 __le32 max_mcast_filters;
1041 __le32 max_hw_ring_grps;
1048 /* hwrm_func_qcfg */
1049 /* Input (24 bytes) */
1050 struct hwrm_func_qcfg_input {
1060 /* Output (72 bytes) */
1061 struct hwrm_func_qcfg_output {
1073 __le16 alloc_rsscos_ctx;
1074 __le16 alloc_cmpl_rings;
1075 __le16 alloc_tx_rings;
1076 __le16 alloc_rx_rings;
1077 __le16 alloc_l2_ctx;
1082 u8 port_partition_type;
1083 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_SPF (0x0UL << 0)
1084 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_MPFS (0x1UL << 0)
1085 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_0 (0x2UL << 0)
1086 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_5 (0x3UL << 0)
1087 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR2_0 (0x4UL << 0)
1088 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_UNKNOWN (0xffUL << 0)
1090 __le16 dflt_vnic_id;
1096 #define FUNC_QCFG_RESP_EVB_MODE_NO_EVB (0x0UL << 0)
1097 #define FUNC_QCFG_RESP_EVB_MODE_VEB (0x1UL << 0)
1098 #define FUNC_QCFG_RESP_EVB_MODE_VEPA (0x2UL << 0)
1101 __le32 alloc_mcast_filters;
1102 __le32 alloc_hw_ring_grps;
1110 /* Input (88 bytes) */
1111 struct hwrm_func_cfg_input {
1121 #define FUNC_CFG_REQ_FLAGS_PROM_MODE 0x1UL
1122 #define FUNC_CFG_REQ_FLAGS_SRC_MAC_ADDR_CHECK 0x2UL
1123 #define FUNC_CFG_REQ_FLAGS_SRC_IP_ADDR_CHECK 0x4UL
1124 #define FUNC_CFG_REQ_FLAGS_VLAN_PRI_MATCH 0x8UL
1125 #define FUNC_CFG_REQ_FLAGS_DFLT_PRI_NOMATCH 0x10UL
1126 #define FUNC_CFG_REQ_FLAGS_DISABLE_PAUSE 0x20UL
1127 #define FUNC_CFG_REQ_FLAGS_DISABLE_STP 0x40UL
1128 #define FUNC_CFG_REQ_FLAGS_DISABLE_LLDP 0x80UL
1129 #define FUNC_CFG_REQ_FLAGS_DISABLE_PTPV2 0x100UL
1131 #define FUNC_CFG_REQ_ENABLES_MTU 0x1UL
1132 #define FUNC_CFG_REQ_ENABLES_MRU 0x2UL
1133 #define FUNC_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS 0x4UL
1134 #define FUNC_CFG_REQ_ENABLES_NUM_CMPL_RINGS 0x8UL
1135 #define FUNC_CFG_REQ_ENABLES_NUM_TX_RINGS 0x10UL
1136 #define FUNC_CFG_REQ_ENABLES_NUM_RX_RINGS 0x20UL
1137 #define FUNC_CFG_REQ_ENABLES_NUM_L2_CTXS 0x40UL
1138 #define FUNC_CFG_REQ_ENABLES_NUM_VNICS 0x80UL
1139 #define FUNC_CFG_REQ_ENABLES_NUM_STAT_CTXS 0x100UL
1140 #define FUNC_CFG_REQ_ENABLES_DFLT_MAC_ADDR 0x200UL
1141 #define FUNC_CFG_REQ_ENABLES_DFLT_VLAN 0x400UL
1142 #define FUNC_CFG_REQ_ENABLES_DFLT_IP_ADDR 0x800UL
1143 #define FUNC_CFG_REQ_ENABLES_MIN_BW 0x1000UL
1144 #define FUNC_CFG_REQ_ENABLES_MAX_BW 0x2000UL
1145 #define FUNC_CFG_REQ_ENABLES_ASYNC_EVENT_CR 0x4000UL
1146 #define FUNC_CFG_REQ_ENABLES_VLAN_ANTISPOOF_MODE 0x8000UL
1147 #define FUNC_CFG_REQ_ENABLES_ALLOWED_VLAN_PRIS 0x10000UL
1148 #define FUNC_CFG_REQ_ENABLES_EVB_MODE 0x20000UL
1149 #define FUNC_CFG_REQ_ENABLES_NUM_MCAST_FILTERS 0x40000UL
1150 #define FUNC_CFG_REQ_ENABLES_NUM_HW_RING_GRPS 0x80000UL
1153 __le16 num_rsscos_ctxs;
1154 __le16 num_cmpl_rings;
1155 __le16 num_tx_rings;
1156 __le16 num_rx_rings;
1159 __le16 num_stat_ctxs;
1160 __le16 num_hw_ring_grps;
1161 u8 dflt_mac_addr[6];
1163 __be32 dflt_ip_addr[4];
1166 __le16 async_event_cr;
1167 u8 vlan_antispoof_mode;
1168 #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_NOCHECK (0x0UL << 0)
1169 #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN (0x1UL << 0)
1170 #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_INSERT_IF_VLANDNE (0x2UL << 0)
1171 #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_INSERT_OR_OVERRIDE_VLAN (0x3UL << 0)
1172 u8 allowed_vlan_pris;
1174 #define FUNC_CFG_REQ_EVB_MODE_NO_EVB (0x0UL << 0)
1175 #define FUNC_CFG_REQ_EVB_MODE_VEB (0x1UL << 0)
1176 #define FUNC_CFG_REQ_EVB_MODE_VEPA (0x2UL << 0)
1178 __le16 num_mcast_filters;
1181 /* Output (16 bytes) */
1182 struct hwrm_func_cfg_output {
1194 /* hwrm_func_qstats */
1195 /* Input (24 bytes) */
1196 struct hwrm_func_qstats_input {
1206 /* Output (176 bytes) */
1207 struct hwrm_func_qstats_output {
1212 __le64 tx_ucast_pkts;
1213 __le64 tx_mcast_pkts;
1214 __le64 tx_bcast_pkts;
1216 __le64 tx_drop_pkts;
1217 __le64 tx_ucast_bytes;
1218 __le64 tx_mcast_bytes;
1219 __le64 tx_bcast_bytes;
1220 __le64 rx_ucast_pkts;
1221 __le64 rx_mcast_pkts;
1222 __le64 rx_bcast_pkts;
1224 __le64 rx_drop_pkts;
1225 __le64 rx_ucast_bytes;
1226 __le64 rx_mcast_bytes;
1227 __le64 rx_bcast_bytes;
1229 __le64 rx_agg_bytes;
1230 __le64 rx_agg_events;
1231 __le64 rx_agg_aborts;
1239 /* hwrm_func_clr_stats */
1240 /* Input (24 bytes) */
1241 struct hwrm_func_clr_stats_input {
1251 /* Output (16 bytes) */
1252 struct hwrm_func_clr_stats_output {
1264 /* hwrm_func_vf_resc_free */
1265 /* Input (24 bytes) */
1266 struct hwrm_func_vf_resc_free_input {
1276 /* Output (16 bytes) */
1277 struct hwrm_func_vf_resc_free_output {
1289 /* hwrm_func_vf_vnic_ids_query */
1290 /* Input (32 bytes) */
1291 struct hwrm_func_vf_vnic_ids_query_input {
1300 __le32 max_vnic_id_cnt;
1301 __le64 vnic_id_tbl_addr;
1304 /* Output (16 bytes) */
1305 struct hwrm_func_vf_vnic_ids_query_output {
1317 /* hwrm_func_drv_rgtr */
1318 /* Input (80 bytes) */
1319 struct hwrm_func_drv_rgtr_input {
1326 #define FUNC_DRV_RGTR_REQ_FLAGS_FWD_ALL_MODE 0x1UL
1327 #define FUNC_DRV_RGTR_REQ_FLAGS_FWD_NONE_MODE 0x2UL
1329 #define FUNC_DRV_RGTR_REQ_ENABLES_OS_TYPE 0x1UL
1330 #define FUNC_DRV_RGTR_REQ_ENABLES_VER 0x2UL
1331 #define FUNC_DRV_RGTR_REQ_ENABLES_TIMESTAMP 0x4UL
1332 #define FUNC_DRV_RGTR_REQ_ENABLES_VF_REQ_FWD 0x8UL
1333 #define FUNC_DRV_RGTR_REQ_ENABLES_ASYNC_EVENT_FWD 0x10UL
1335 #define FUNC_DRV_RGTR_REQ_OS_TYPE_UNKNOWN (0x0UL << 0)
1336 #define FUNC_DRV_RGTR_REQ_OS_TYPE_OTHER (0x1UL << 0)
1337 #define FUNC_DRV_RGTR_REQ_OS_TYPE_MSDOS (0xeUL << 0)
1338 #define FUNC_DRV_RGTR_REQ_OS_TYPE_WINDOWS (0x12UL << 0)
1339 #define FUNC_DRV_RGTR_REQ_OS_TYPE_SOLARIS (0x1dUL << 0)
1340 #define FUNC_DRV_RGTR_REQ_OS_TYPE_LINUX (0x24UL << 0)
1341 #define FUNC_DRV_RGTR_REQ_OS_TYPE_FREEBSD (0x2aUL << 0)
1342 #define FUNC_DRV_RGTR_REQ_OS_TYPE_ESXI (0x68UL << 0)
1343 #define FUNC_DRV_RGTR_REQ_OS_TYPE_WIN864 (0x73UL << 0)
1344 #define FUNC_DRV_RGTR_REQ_OS_TYPE_WIN2012R2 (0x74UL << 0)
1352 __le32 vf_req_fwd[8];
1353 __le32 async_event_fwd[8];
1356 /* Output (16 bytes) */
1357 struct hwrm_func_drv_rgtr_output {
1369 /* hwrm_func_drv_unrgtr */
1370 /* Input (24 bytes) */
1371 struct hwrm_func_drv_unrgtr_input {
1378 #define FUNC_DRV_UNRGTR_REQ_FLAGS_PREPARE_FOR_SHUTDOWN 0x1UL
1382 /* Output (16 bytes) */
1383 struct hwrm_func_drv_unrgtr_output {
1395 /* hwrm_func_buf_rgtr */
1396 /* Input (128 bytes) */
1397 struct hwrm_func_buf_rgtr_input {
1404 #define FUNC_BUF_RGTR_REQ_ENABLES_VF_ID 0x1UL
1405 #define FUNC_BUF_RGTR_REQ_ENABLES_ERR_BUF_ADDR 0x2UL
1407 __le16 req_buf_num_pages;
1408 __le16 req_buf_page_size;
1409 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_16B (0x4UL << 0)
1410 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_4K (0xcUL << 0)
1411 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_8K (0xdUL << 0)
1412 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_64K (0x10UL << 0)
1413 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_2M (0x16UL << 0)
1414 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_4M (0x17UL << 0)
1415 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_1G (0x1eUL << 0)
1417 __le16 resp_buf_len;
1420 __le64 req_buf_page_addr0;
1421 __le64 req_buf_page_addr1;
1422 __le64 req_buf_page_addr2;
1423 __le64 req_buf_page_addr3;
1424 __le64 req_buf_page_addr4;
1425 __le64 req_buf_page_addr5;
1426 __le64 req_buf_page_addr6;
1427 __le64 req_buf_page_addr7;
1428 __le64 req_buf_page_addr8;
1429 __le64 req_buf_page_addr9;
1430 __le64 error_buf_addr;
1431 __le64 resp_buf_addr;
1434 /* Output (16 bytes) */
1435 struct hwrm_func_buf_rgtr_output {
1447 /* hwrm_func_drv_qver */
1448 /* Input (24 bytes) */
1449 struct hwrm_func_drv_qver_input {
1460 /* Output (16 bytes) */
1461 struct hwrm_func_drv_qver_output {
1467 #define FUNC_DRV_QVER_RESP_OS_TYPE_UNKNOWN (0x0UL << 0)
1468 #define FUNC_DRV_QVER_RESP_OS_TYPE_OTHER (0x1UL << 0)
1469 #define FUNC_DRV_QVER_RESP_OS_TYPE_MSDOS (0xeUL << 0)
1470 #define FUNC_DRV_QVER_RESP_OS_TYPE_WINDOWS (0x12UL << 0)
1471 #define FUNC_DRV_QVER_RESP_OS_TYPE_SOLARIS (0x1dUL << 0)
1472 #define FUNC_DRV_QVER_RESP_OS_TYPE_LINUX (0x24UL << 0)
1473 #define FUNC_DRV_QVER_RESP_OS_TYPE_FREEBSD (0x2aUL << 0)
1474 #define FUNC_DRV_QVER_RESP_OS_TYPE_ESXI (0x68UL << 0)
1475 #define FUNC_DRV_QVER_RESP_OS_TYPE_WIN864 (0x73UL << 0)
1476 #define FUNC_DRV_QVER_RESP_OS_TYPE_WIN2012R2 (0x74UL << 0)
1485 /* hwrm_port_phy_cfg */
1486 /* Input (56 bytes) */
1487 struct hwrm_port_phy_cfg_input {
1494 #define PORT_PHY_CFG_REQ_FLAGS_RESET_PHY 0x1UL
1495 #define PORT_PHY_CFG_REQ_FLAGS_FORCE_LINK_DOWN 0x2UL
1496 #define PORT_PHY_CFG_REQ_FLAGS_FORCE 0x4UL
1497 #define PORT_PHY_CFG_REQ_FLAGS_RESTART_AUTONEG 0x8UL
1498 #define PORT_PHY_CFG_REQ_FLAGS_EEE_ENABLE 0x10UL
1499 #define PORT_PHY_CFG_REQ_FLAGS_EEE_DISABLE 0x20UL
1500 #define PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_ENABLE 0x40UL
1501 #define PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_DISABLE 0x80UL
1503 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_MODE 0x1UL
1504 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_DUPLEX 0x2UL
1505 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE 0x4UL
1506 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED 0x8UL
1507 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED_MASK 0x10UL
1508 #define PORT_PHY_CFG_REQ_ENABLES_WIRESPEED 0x20UL
1509 #define PORT_PHY_CFG_REQ_ENABLES_LPBK 0x40UL
1510 #define PORT_PHY_CFG_REQ_ENABLES_PREEMPHASIS 0x80UL
1511 #define PORT_PHY_CFG_REQ_ENABLES_FORCE_PAUSE 0x100UL
1512 #define PORT_PHY_CFG_REQ_ENABLES_EEE_LINK_SPEED_MASK 0x200UL
1513 #define PORT_PHY_CFG_REQ_ENABLES_TX_LPI_TIMER 0x400UL
1515 __le16 force_link_speed;
1516 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_100MB (0x1UL << 0)
1517 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_1GB (0xaUL << 0)
1518 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_2GB (0x14UL << 0)
1519 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_2_5GB (0x19UL << 0)
1520 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10GB (0x64UL << 0)
1521 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_20GB (0xc8UL << 0)
1522 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_25GB (0xfaUL << 0)
1523 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_40GB (0x190UL << 0)
1524 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_50GB (0x1f4UL << 0)
1525 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_100GB (0x3e8UL << 0)
1526 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10MB (0xffffUL << 0)
1528 #define PORT_PHY_CFG_REQ_AUTO_MODE_NONE (0x0UL << 0)
1529 #define PORT_PHY_CFG_REQ_AUTO_MODE_ALL_SPEEDS (0x1UL << 0)
1530 #define PORT_PHY_CFG_REQ_AUTO_MODE_ONE_SPEED (0x2UL << 0)
1531 #define PORT_PHY_CFG_REQ_AUTO_MODE_ONE_OR_BELOW (0x3UL << 0)
1532 #define PORT_PHY_CFG_REQ_AUTO_MODE_SPEED_MASK (0x4UL << 0)
1534 #define PORT_PHY_CFG_REQ_AUTO_DUPLEX_HALF (0x0UL << 0)
1535 #define PORT_PHY_CFG_REQ_AUTO_DUPLEX_FULL (0x1UL << 0)
1536 #define PORT_PHY_CFG_REQ_AUTO_DUPLEX_BOTH (0x2UL << 0)
1538 #define PORT_PHY_CFG_REQ_AUTO_PAUSE_TX 0x1UL
1539 #define PORT_PHY_CFG_REQ_AUTO_PAUSE_RX 0x2UL
1540 #define PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE 0x4UL
1542 __le16 auto_link_speed;
1543 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_100MB (0x1UL << 0)
1544 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_1GB (0xaUL << 0)
1545 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_2GB (0x14UL << 0)
1546 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_2_5GB (0x19UL << 0)
1547 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_10GB (0x64UL << 0)
1548 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_20GB (0xc8UL << 0)
1549 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_25GB (0xfaUL << 0)
1550 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_40GB (0x190UL << 0)
1551 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_50GB (0x1f4UL << 0)
1552 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_100GB (0x3e8UL << 0)
1553 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_10MB (0xffffUL << 0)
1554 __le16 auto_link_speed_mask;
1555 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_100MBHD 0x1UL
1556 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_100MB 0x2UL
1557 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_1GBHD 0x4UL
1558 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_1GB 0x8UL
1559 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_2GB 0x10UL
1560 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_2_5GB 0x20UL
1561 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_10GB 0x40UL
1562 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_20GB 0x80UL
1563 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_25GB 0x100UL
1564 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_40GB 0x200UL
1565 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_50GB 0x400UL
1566 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_100GB 0x800UL
1567 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_10MBHD 0x1000UL
1568 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_10MB 0x2000UL
1570 #define PORT_PHY_CFG_REQ_WIRESPEED_OFF (0x0UL << 0)
1571 #define PORT_PHY_CFG_REQ_WIRESPEED_ON (0x1UL << 0)
1573 #define PORT_PHY_CFG_REQ_LPBK_NONE (0x0UL << 0)
1574 #define PORT_PHY_CFG_REQ_LPBK_LOCAL (0x1UL << 0)
1575 #define PORT_PHY_CFG_REQ_LPBK_REMOTE (0x2UL << 0)
1577 #define PORT_PHY_CFG_REQ_FORCE_PAUSE_TX 0x1UL
1578 #define PORT_PHY_CFG_REQ_FORCE_PAUSE_RX 0x2UL
1581 __le16 eee_link_speed_mask;
1582 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD1 0x1UL
1583 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_100MB 0x2UL
1584 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD2 0x4UL
1585 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_1GB 0x8UL
1586 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD3 0x10UL
1587 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD4 0x20UL
1588 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_10GB 0x40UL
1591 __le32 tx_lpi_timer;
1593 #define PORT_PHY_CFG_REQ_TX_LPI_TIMER_MASK 0xffffffUL
1594 #define PORT_PHY_CFG_REQ_TX_LPI_TIMER_SFT 0
1597 /* Output (16 bytes) */
1598 struct hwrm_port_phy_cfg_output {
1610 /* hwrm_port_phy_qcfg */
1611 /* Input (24 bytes) */
1612 struct hwrm_port_phy_qcfg_input {
1622 /* Output (96 bytes) */
1623 struct hwrm_port_phy_qcfg_output {
1629 #define PORT_PHY_QCFG_RESP_LINK_NO_LINK (0x0UL << 0)
1630 #define PORT_PHY_QCFG_RESP_LINK_SIGNAL (0x1UL << 0)
1631 #define PORT_PHY_QCFG_RESP_LINK_LINK (0x2UL << 0)
1634 #define PORT_PHY_QCFG_RESP_LINK_SPEED_100MB (0x1UL << 0)
1635 #define PORT_PHY_QCFG_RESP_LINK_SPEED_1GB (0xaUL << 0)
1636 #define PORT_PHY_QCFG_RESP_LINK_SPEED_2GB (0x14UL << 0)
1637 #define PORT_PHY_QCFG_RESP_LINK_SPEED_2_5GB (0x19UL << 0)
1638 #define PORT_PHY_QCFG_RESP_LINK_SPEED_10GB (0x64UL << 0)
1639 #define PORT_PHY_QCFG_RESP_LINK_SPEED_20GB (0xc8UL << 0)
1640 #define PORT_PHY_QCFG_RESP_LINK_SPEED_25GB (0xfaUL << 0)
1641 #define PORT_PHY_QCFG_RESP_LINK_SPEED_40GB (0x190UL << 0)
1642 #define PORT_PHY_QCFG_RESP_LINK_SPEED_50GB (0x1f4UL << 0)
1643 #define PORT_PHY_QCFG_RESP_LINK_SPEED_100GB (0x3e8UL << 0)
1644 #define PORT_PHY_QCFG_RESP_LINK_SPEED_10MB (0xffffUL << 0)
1646 #define PORT_PHY_QCFG_RESP_DUPLEX_HALF (0x0UL << 0)
1647 #define PORT_PHY_QCFG_RESP_DUPLEX_FULL (0x1UL << 0)
1649 #define PORT_PHY_QCFG_RESP_PAUSE_TX 0x1UL
1650 #define PORT_PHY_QCFG_RESP_PAUSE_RX 0x2UL
1651 __le16 support_speeds;
1652 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100MBHD 0x1UL
1653 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100MB 0x2UL
1654 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_1GBHD 0x4UL
1655 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_1GB 0x8UL
1656 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2GB 0x10UL
1657 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2_5GB 0x20UL
1658 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10GB 0x40UL
1659 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_20GB 0x80UL
1660 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_25GB 0x100UL
1661 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_40GB 0x200UL
1662 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_50GB 0x400UL
1663 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100GB 0x800UL
1664 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10MBHD 0x1000UL
1665 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10MB 0x2000UL
1666 __le16 force_link_speed;
1667 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_100MB (0x1UL << 0)
1668 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_1GB (0xaUL << 0)
1669 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_2GB (0x14UL << 0)
1670 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_2_5GB (0x19UL << 0)
1671 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_10GB (0x64UL << 0)
1672 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_20GB (0xc8UL << 0)
1673 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_25GB (0xfaUL << 0)
1674 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_40GB (0x190UL << 0)
1675 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_50GB (0x1f4UL << 0)
1676 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_100GB (0x3e8UL << 0)
1677 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_10MB (0xffffUL << 0)
1679 #define PORT_PHY_QCFG_RESP_AUTO_MODE_NONE (0x0UL << 0)
1680 #define PORT_PHY_QCFG_RESP_AUTO_MODE_ALL_SPEEDS (0x1UL << 0)
1681 #define PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_SPEED (0x2UL << 0)
1682 #define PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_OR_BELOW (0x3UL << 0)
1683 #define PORT_PHY_QCFG_RESP_AUTO_MODE_SPEED_MASK (0x4UL << 0)
1685 #define PORT_PHY_QCFG_RESP_AUTO_PAUSE_TX 0x1UL
1686 #define PORT_PHY_QCFG_RESP_AUTO_PAUSE_RX 0x2UL
1687 #define PORT_PHY_QCFG_RESP_AUTO_PAUSE_AUTONEG_PAUSE 0x4UL
1688 __le16 auto_link_speed;
1689 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_100MB (0x1UL << 0)
1690 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_1GB (0xaUL << 0)
1691 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_2GB (0x14UL << 0)
1692 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_2_5GB (0x19UL << 0)
1693 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_10GB (0x64UL << 0)
1694 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_20GB (0xc8UL << 0)
1695 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_25GB (0xfaUL << 0)
1696 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_40GB (0x190UL << 0)
1697 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_50GB (0x1f4UL << 0)
1698 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_100GB (0x3e8UL << 0)
1699 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_10MB (0xffffUL << 0)
1700 __le16 auto_link_speed_mask;
1701 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_100MBHD 0x1UL
1702 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_100MB 0x2UL
1703 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_1GBHD 0x4UL
1704 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_1GB 0x8UL
1705 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_2GB 0x10UL
1706 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_2_5GB 0x20UL
1707 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_10GB 0x40UL
1708 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_20GB 0x80UL
1709 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_25GB 0x100UL
1710 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_40GB 0x200UL
1711 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_50GB 0x400UL
1712 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_100GB 0x800UL
1713 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_10MBHD 0x1000UL
1714 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_10MB 0x2000UL
1716 #define PORT_PHY_QCFG_RESP_WIRESPEED_OFF (0x0UL << 0)
1717 #define PORT_PHY_QCFG_RESP_WIRESPEED_ON (0x1UL << 0)
1719 #define PORT_PHY_QCFG_RESP_LPBK_NONE (0x0UL << 0)
1720 #define PORT_PHY_QCFG_RESP_LPBK_LOCAL (0x1UL << 0)
1721 #define PORT_PHY_QCFG_RESP_LPBK_REMOTE (0x2UL << 0)
1723 #define PORT_PHY_QCFG_RESP_FORCE_PAUSE_TX 0x1UL
1724 #define PORT_PHY_QCFG_RESP_FORCE_PAUSE_RX 0x2UL
1726 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_NONE (0x0UL << 0)
1727 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_DISABLETX (0x1UL << 0)
1728 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_WARNINGMSG (0x2UL << 0)
1729 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN (0x3UL << 0)
1730 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_NOTINSERTED (0x4UL << 0)
1731 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_NOTAPPLICABLE (0xffUL << 0)
1737 #define PORT_PHY_QCFG_RESP_PHY_TYPE_UNKNOWN (0x0UL << 0)
1738 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASECR (0x1UL << 0)
1739 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR4 (0x2UL << 0)
1740 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASELR (0x3UL << 0)
1741 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASESR (0x4UL << 0)
1742 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR2 (0x5UL << 0)
1743 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKX (0x6UL << 0)
1744 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR (0x7UL << 0)
1745 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASET (0x8UL << 0)
1746 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASETE (0x9UL << 0)
1747 #define PORT_PHY_QCFG_RESP_PHY_TYPE_SGMIIEXTPHY (0xaUL << 0)
1749 #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_UNKNOWN (0x0UL << 0)
1750 #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_TP (0x1UL << 0)
1751 #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_DAC (0x2UL << 0)
1752 #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_FIBRE (0x3UL << 0)
1754 #define PORT_PHY_QCFG_RESP_XCVR_PKG_TYPE_XCVR_INTERNAL (0x1UL << 0)
1755 #define PORT_PHY_QCFG_RESP_XCVR_PKG_TYPE_XCVR_EXTERNAL (0x2UL << 0)
1756 u8 eee_config_phy_addr;
1757 #define PORT_PHY_QCFG_RESP_PHY_ADDR_MASK 0x1fUL
1758 #define PORT_PHY_QCFG_RESP_PHY_ADDR_SFT 0
1759 #define PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ENABLED 0x20UL
1760 #define PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ACTIVE 0x40UL
1761 #define PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_TX_LPI 0x80UL
1762 #define PORT_PHY_QCFG_RESP_EEE_CONFIG_MASK 0xe0UL
1763 #define PORT_PHY_QCFG_RESP_EEE_CONFIG_SFT 5
1765 #define PORT_PHY_QCFG_RESP_PARALLEL_DETECT 0x1UL
1766 #define PORT_PHY_QCFG_RESP_RESERVED_MASK 0xfeUL
1767 #define PORT_PHY_QCFG_RESP_RESERVED_SFT 1
1768 __le16 link_partner_adv_speeds;
1769 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_100MBHD 0x1UL
1770 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_100MB 0x2UL
1771 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_1GBHD 0x4UL
1772 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_1GB 0x8UL
1773 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_2GB 0x10UL
1774 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_2_5GB 0x20UL
1775 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_10GB 0x40UL
1776 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_20GB 0x80UL
1777 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_25GB 0x100UL
1778 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_40GB 0x200UL
1779 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_50GB 0x400UL
1780 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_100GB 0x800UL
1781 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_10MBHD 0x1000UL
1782 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_10MB 0x2000UL
1783 u8 link_partner_adv_auto_mode;
1784 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_NONE (0x0UL << 0)
1785 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_ALL_SPEEDS (0x1UL << 0)
1786 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_ONE_SPEED (0x2UL << 0)
1787 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_ONE_OR_BELOW (0x3UL << 0)
1788 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_SPEED_MASK (0x4UL << 0)
1789 u8 link_partner_adv_pause;
1790 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_PAUSE_TX 0x1UL
1791 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_PAUSE_RX 0x2UL
1792 __le16 adv_eee_link_speed_mask;
1793 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD1 0x1UL
1794 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_100MB 0x2UL
1795 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD2 0x4UL
1796 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_1GB 0x8UL
1797 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD3 0x10UL
1798 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD4 0x20UL
1799 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_10GB 0x40UL
1800 __le16 link_partner_adv_eee_link_speed_mask;
1801 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD1 0x1UL
1802 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_100MB 0x2UL
1803 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD2 0x4UL
1804 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_1GB 0x8UL
1805 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD3 0x10UL
1806 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD4 0x20UL
1807 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_10GB 0x40UL
1808 __le32 xcvr_identifier_type_tx_lpi_timer;
1809 #define PORT_PHY_QCFG_RESP_TX_LPI_TIMER_MASK 0xffffffUL
1810 #define PORT_PHY_QCFG_RESP_TX_LPI_TIMER_SFT 0
1811 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_MASK 0xff000000UL
1812 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_SFT 24
1813 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_UNKNOWN (0x0UL << 24)
1814 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_SFP (0x3UL << 24)
1815 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFP (0xcUL << 24)
1816 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFPPLUS (0xdUL << 24)
1817 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFP28 (0x11UL << 24)
1819 char phy_vendor_name[16];
1820 char phy_vendor_partnumber[16];
1828 /* hwrm_port_mac_cfg */
1829 /* Input (40 bytes) */
1830 struct hwrm_port_mac_cfg_input {
1837 #define PORT_MAC_CFG_REQ_FLAGS_MATCH_LINK 0x1UL
1838 #define PORT_MAC_CFG_REQ_FLAGS_COS_ASSIGNMENT_ENABLE 0x2UL
1839 #define PORT_MAC_CFG_REQ_FLAGS_TUNNEL_PRI2COS_ENABLE 0x4UL
1840 #define PORT_MAC_CFG_REQ_FLAGS_IP_DSCP2COS_ENABLE 0x8UL
1841 #define PORT_MAC_CFG_REQ_FLAGS_PTP_RX_TS_CAPTURE_ENABLE 0x10UL
1842 #define PORT_MAC_CFG_REQ_FLAGS_PTP_RX_TS_CAPTURE_DISABLE 0x20UL
1843 #define PORT_MAC_CFG_REQ_FLAGS_PTP_TX_TS_CAPTURE_ENABLE 0x40UL
1844 #define PORT_MAC_CFG_REQ_FLAGS_PTP_TX_TS_CAPTURE_DISABLE 0x80UL
1846 #define PORT_MAC_CFG_REQ_ENABLES_IPG 0x1UL
1847 #define PORT_MAC_CFG_REQ_ENABLES_LPBK 0x2UL
1848 #define PORT_MAC_CFG_REQ_ENABLES_IVLAN_PRI2COS_MAP_PRI 0x4UL
1849 #define PORT_MAC_CFG_REQ_ENABLES_LCOS_MAP_PRI 0x8UL
1850 #define PORT_MAC_CFG_REQ_ENABLES_TUNNEL_PRI2COS_MAP_PRI 0x10UL
1851 #define PORT_MAC_CFG_REQ_ENABLES_DSCP2COS_MAP_PRI 0x20UL
1852 #define PORT_MAC_CFG_REQ_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE 0x40UL
1853 #define PORT_MAC_CFG_REQ_ENABLES_TX_TS_CAPTURE_PTP_MSG_TYPE 0x80UL
1857 #define PORT_MAC_CFG_REQ_LPBK_NONE (0x0UL << 0)
1858 #define PORT_MAC_CFG_REQ_LPBK_LOCAL (0x1UL << 0)
1859 #define PORT_MAC_CFG_REQ_LPBK_REMOTE (0x2UL << 0)
1860 u8 ivlan_pri2cos_map_pri;
1862 u8 tunnel_pri2cos_map_pri;
1863 u8 dscp2pri_map_pri;
1864 __le16 rx_ts_capture_ptp_msg_type;
1865 __le16 tx_ts_capture_ptp_msg_type;
1869 /* Output (16 bytes) */
1870 struct hwrm_port_mac_cfg_output {
1879 #define PORT_MAC_CFG_RESP_LPBK_NONE (0x0UL << 0)
1880 #define PORT_MAC_CFG_RESP_LPBK_LOCAL (0x1UL << 0)
1881 #define PORT_MAC_CFG_RESP_LPBK_REMOTE (0x2UL << 0)
1886 /* hwrm_port_qstats */
1887 /* Input (40 bytes) */
1888 struct hwrm_port_qstats_input {
1899 __le64 tx_stat_host_addr;
1900 __le64 rx_stat_host_addr;
1903 /* Output (16 bytes) */
1904 struct hwrm_port_qstats_output {
1909 __le16 tx_stat_size;
1910 __le16 rx_stat_size;
1917 /* hwrm_port_lpbk_qstats */
1918 /* Input (16 bytes) */
1919 struct hwrm_port_lpbk_qstats_input {
1927 /* Output (96 bytes) */
1928 struct hwrm_port_lpbk_qstats_output {
1933 __le64 lpbk_ucast_frames;
1934 __le64 lpbk_mcast_frames;
1935 __le64 lpbk_bcast_frames;
1936 __le64 lpbk_ucast_bytes;
1937 __le64 lpbk_mcast_bytes;
1938 __le64 lpbk_bcast_bytes;
1939 __le64 tx_stat_discard;
1940 __le64 tx_stat_error;
1941 __le64 rx_stat_discard;
1942 __le64 rx_stat_error;
1950 /* hwrm_port_clr_stats */
1951 /* Input (24 bytes) */
1952 struct hwrm_port_clr_stats_input {
1962 /* Output (16 bytes) */
1963 struct hwrm_port_clr_stats_output {
1975 /* hwrm_port_lpbk_clr_stats */
1976 /* Input (16 bytes) */
1977 struct hwrm_port_lpbk_clr_stats_input {
1985 /* Output (16 bytes) */
1986 struct hwrm_port_lpbk_clr_stats_output {
1998 /* hwrm_port_blink_led */
1999 /* Input (24 bytes) */
2000 struct hwrm_port_blink_led_input {
2010 /* Output (16 bytes) */
2011 struct hwrm_port_blink_led_output {
2023 /* hwrm_port_phy_qcaps */
2024 /* Input (24 bytes) */
2025 struct hwrm_port_phy_qcaps_input {
2035 /* Output (24 bytes) */
2036 struct hwrm_port_phy_qcaps_output {
2042 #define PORT_PHY_QCAPS_RESP_EEE_SUPPORTED 0x1UL
2043 #define PORT_PHY_QCAPS_RESP_RSVD1_MASK 0xfeUL
2044 #define PORT_PHY_QCAPS_RESP_RSVD1_SFT 1
2046 __le16 supported_speeds_force_mode;
2047 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_100MBHD 0x1UL
2048 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_100MB 0x2UL
2049 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_1GBHD 0x4UL
2050 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_1GB 0x8UL
2051 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_2GB 0x10UL
2052 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_2_5GB 0x20UL
2053 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_10GB 0x40UL
2054 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_20GB 0x80UL
2055 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_25GB 0x100UL
2056 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_40GB 0x200UL
2057 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_50GB 0x400UL
2058 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_100GB 0x800UL
2059 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_10MBHD 0x1000UL
2060 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_10MB 0x2000UL
2061 __le16 supported_speeds_auto_mode;
2062 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_100MBHD 0x1UL
2063 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_100MB 0x2UL
2064 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_1GBHD 0x4UL
2065 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_1GB 0x8UL
2066 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_2GB 0x10UL
2067 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_2_5GB 0x20UL
2068 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_10GB 0x40UL
2069 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_20GB 0x80UL
2070 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_25GB 0x100UL
2071 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_40GB 0x200UL
2072 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_50GB 0x400UL
2073 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_100GB 0x800UL
2074 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_10MBHD 0x1000UL
2075 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_10MB 0x2000UL
2076 __le16 supported_speeds_eee_mode;
2077 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD1 0x1UL
2078 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_100MB 0x2UL
2079 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD2 0x4UL
2080 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_1GB 0x8UL
2081 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD3 0x10UL
2082 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD4 0x20UL
2083 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_10GB 0x40UL
2084 __le32 tx_lpi_timer_low;
2085 #define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_LOW_MASK 0xffffffUL
2086 #define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_LOW_SFT 0
2087 #define PORT_PHY_QCAPS_RESP_RSVD2_MASK 0xff000000UL
2088 #define PORT_PHY_QCAPS_RESP_RSVD2_SFT 24
2089 __le32 valid_tx_lpi_timer_high;
2090 #define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_HIGH_MASK 0xffffffUL
2091 #define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_HIGH_SFT 0
2092 #define PORT_PHY_QCAPS_RESP_VALID_MASK 0xff000000UL
2093 #define PORT_PHY_QCAPS_RESP_VALID_SFT 24
2096 /* Input (24 bytes) */
2097 struct hwrm_queue_qportcfg_input {
2104 #define QUEUE_QPORTCFG_REQ_FLAGS_PATH 0x1UL
2105 #define QUEUE_QPORTCFG_REQ_FLAGS_PATH_TX (0x0UL << 0)
2106 #define QUEUE_QPORTCFG_REQ_FLAGS_PATH_RX (0x1UL << 0)
2107 #define QUEUE_QPORTCFG_REQ_FLAGS_PATH_LAST QUEUE_QPORTCFG_REQ_FLAGS_PATH_RX
2112 /* Output (32 bytes) */
2113 struct hwrm_queue_qportcfg_output {
2118 u8 max_configurable_queues;
2119 u8 max_configurable_lossless_queues;
2120 u8 queue_cfg_allowed;
2121 u8 queue_buffers_cfg_allowed;
2122 u8 queue_pfcenable_cfg_allowed;
2123 u8 queue_pri2cos_cfg_allowed;
2124 u8 queue_cos2bw_cfg_allowed;
2126 u8 queue_id0_service_profile;
2127 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSY (0x0UL << 0)
2128 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS (0x1UL << 0)
2129 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_UNKNOWN (0xffUL << 0)
2131 u8 queue_id1_service_profile;
2132 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSY (0x0UL << 0)
2133 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS (0x1UL << 0)
2134 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_UNKNOWN (0xffUL << 0)
2136 u8 queue_id2_service_profile;
2137 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSY (0x0UL << 0)
2138 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS (0x1UL << 0)
2139 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_UNKNOWN (0xffUL << 0)
2141 u8 queue_id3_service_profile;
2142 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSY (0x0UL << 0)
2143 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS (0x1UL << 0)
2144 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_UNKNOWN (0xffUL << 0)
2146 u8 queue_id4_service_profile;
2147 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSY (0x0UL << 0)
2148 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS (0x1UL << 0)
2149 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_UNKNOWN (0xffUL << 0)
2151 u8 queue_id5_service_profile;
2152 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSY (0x0UL << 0)
2153 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS (0x1UL << 0)
2154 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_UNKNOWN (0xffUL << 0)
2156 u8 queue_id6_service_profile;
2157 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSY (0x0UL << 0)
2158 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS (0x1UL << 0)
2159 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_UNKNOWN (0xffUL << 0)
2161 u8 queue_id7_service_profile;
2162 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSY (0x0UL << 0)
2163 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS (0x1UL << 0)
2164 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_UNKNOWN (0xffUL << 0)
2168 /* hwrm_queue_cfg */
2169 /* Input (40 bytes) */
2170 struct hwrm_queue_cfg_input {
2177 #define QUEUE_CFG_REQ_FLAGS_PATH 0x1UL
2178 #define QUEUE_CFG_REQ_FLAGS_PATH_TX (0x0UL << 0)
2179 #define QUEUE_CFG_REQ_FLAGS_PATH_RX (0x1UL << 0)
2180 #define QUEUE_CFG_REQ_FLAGS_PATH_LAST QUEUE_CFG_REQ_FLAGS_PATH_RX
2182 #define QUEUE_CFG_REQ_ENABLES_DFLT_LEN 0x1UL
2183 #define QUEUE_CFG_REQ_ENABLES_SERVICE_PROFILE 0x2UL
2187 #define QUEUE_CFG_REQ_SERVICE_PROFILE_LOSSY (0x0UL << 0)
2188 #define QUEUE_CFG_REQ_SERVICE_PROFILE_LOSSLESS (0x1UL << 0)
2189 #define QUEUE_CFG_REQ_SERVICE_PROFILE_UNKNOWN (0xffUL << 0)
2193 /* Output (16 bytes) */
2194 struct hwrm_queue_cfg_output {
2206 /* hwrm_queue_buffers_cfg */
2207 /* Input (56 bytes) */
2208 struct hwrm_queue_buffers_cfg_input {
2215 #define QUEUE_BUFFERS_CFG_REQ_FLAGS_PATH 0x1UL
2216 #define QUEUE_BUFFERS_CFG_REQ_FLAGS_PATH_TX (0x0UL << 0)
2217 #define QUEUE_BUFFERS_CFG_REQ_FLAGS_PATH_RX (0x1UL << 0)
2218 #define QUEUE_BUFFERS_CFG_REQ_FLAGS_PATH_LAST QUEUE_BUFFERS_CFG_REQ_FLAGS_PATH_RX
2220 #define QUEUE_BUFFERS_CFG_REQ_ENABLES_RESERVED 0x1UL
2221 #define QUEUE_BUFFERS_CFG_REQ_ENABLES_SHARED 0x2UL
2222 #define QUEUE_BUFFERS_CFG_REQ_ENABLES_XOFF 0x4UL
2223 #define QUEUE_BUFFERS_CFG_REQ_ENABLES_XON 0x8UL
2224 #define QUEUE_BUFFERS_CFG_REQ_ENABLES_FULL 0x10UL
2225 #define QUEUE_BUFFERS_CFG_REQ_ENABLES_NOTFULL 0x20UL
2226 #define QUEUE_BUFFERS_CFG_REQ_ENABLES_MAX 0x40UL
2237 /* Output (16 bytes) */
2238 struct hwrm_queue_buffers_cfg_output {
2250 /* hwrm_queue_pfcenable_cfg */
2251 /* Input (24 bytes) */
2252 struct hwrm_queue_pfcenable_cfg_input {
2259 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI0_PFC_ENABLED 0x1UL
2260 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI1_PFC_ENABLED 0x2UL
2261 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI2_PFC_ENABLED 0x4UL
2262 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI3_PFC_ENABLED 0x8UL
2263 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI4_PFC_ENABLED 0x10UL
2264 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI5_PFC_ENABLED 0x20UL
2265 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI6_PFC_ENABLED 0x40UL
2266 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI7_PFC_ENABLED 0x80UL
2271 /* Output (16 bytes) */
2272 struct hwrm_queue_pfcenable_cfg_output {
2284 /* hwrm_queue_pri2cos_cfg */
2285 /* Input (40 bytes) */
2286 struct hwrm_queue_pri2cos_cfg_input {
2293 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH 0x1UL
2294 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_TX (0x0UL << 0)
2295 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_RX (0x1UL << 0)
2296 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_LAST QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_RX
2297 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_IVLAN 0x2UL
2300 u8 pri0_cos_queue_id;
2301 u8 pri1_cos_queue_id;
2302 u8 pri2_cos_queue_id;
2303 u8 pri3_cos_queue_id;
2304 u8 pri4_cos_queue_id;
2305 u8 pri5_cos_queue_id;
2306 u8 pri6_cos_queue_id;
2307 u8 pri7_cos_queue_id;
2311 /* Output (16 bytes) */
2312 struct hwrm_queue_pri2cos_cfg_output {
2324 /* hwrm_queue_cos2bw_cfg */
2325 /* Input (128 bytes) */
2326 struct hwrm_queue_cos2bw_cfg_input {
2334 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID0_VALID 0x1UL
2335 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID1_VALID 0x2UL
2336 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID2_VALID 0x4UL
2337 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID3_VALID 0x8UL
2338 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID4_VALID 0x10UL
2339 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID5_VALID 0x20UL
2340 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID6_VALID 0x40UL
2341 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID7_VALID 0x80UL
2345 __le32 queue_id0_min_bw;
2346 __le32 queue_id0_max_bw;
2347 u8 queue_id0_tsa_assign;
2348 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_SP (0x0UL << 0)
2349 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_ETS (0x1UL << 0)
2350 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_RESERVED_FIRST (0x2UL << 0)
2351 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_RESERVED_LAST (0xffffUL << 0)
2352 u8 queue_id0_pri_lvl;
2353 u8 queue_id0_bw_weight;
2355 __le32 queue_id1_min_bw;
2356 __le32 queue_id1_max_bw;
2357 u8 queue_id1_tsa_assign;
2358 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_TSA_ASSIGN_SP (0x0UL << 0)
2359 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_TSA_ASSIGN_ETS (0x1UL << 0)
2360 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_TSA_ASSIGN_RESERVED_FIRST (0x2UL << 0)
2361 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_TSA_ASSIGN_RESERVED_LAST (0xffffUL << 0)
2362 u8 queue_id1_pri_lvl;
2363 u8 queue_id1_bw_weight;
2365 __le32 queue_id2_min_bw;
2366 __le32 queue_id2_max_bw;
2367 u8 queue_id2_tsa_assign;
2368 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_TSA_ASSIGN_SP (0x0UL << 0)
2369 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_TSA_ASSIGN_ETS (0x1UL << 0)
2370 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_TSA_ASSIGN_RESERVED_FIRST (0x2UL << 0)
2371 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_TSA_ASSIGN_RESERVED_LAST (0xffffUL << 0)
2372 u8 queue_id2_pri_lvl;
2373 u8 queue_id2_bw_weight;
2375 __le32 queue_id3_min_bw;
2376 __le32 queue_id3_max_bw;
2377 u8 queue_id3_tsa_assign;
2378 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_TSA_ASSIGN_SP (0x0UL << 0)
2379 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_TSA_ASSIGN_ETS (0x1UL << 0)
2380 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_TSA_ASSIGN_RESERVED_FIRST (0x2UL << 0)
2381 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_TSA_ASSIGN_RESERVED_LAST (0xffffUL << 0)
2382 u8 queue_id3_pri_lvl;
2383 u8 queue_id3_bw_weight;
2385 __le32 queue_id4_min_bw;
2386 __le32 queue_id4_max_bw;
2387 u8 queue_id4_tsa_assign;
2388 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_TSA_ASSIGN_SP (0x0UL << 0)
2389 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_TSA_ASSIGN_ETS (0x1UL << 0)
2390 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_TSA_ASSIGN_RESERVED_FIRST (0x2UL << 0)
2391 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_TSA_ASSIGN_RESERVED_LAST (0xffffUL << 0)
2392 u8 queue_id4_pri_lvl;
2393 u8 queue_id4_bw_weight;
2395 __le32 queue_id5_min_bw;
2396 __le32 queue_id5_max_bw;
2397 u8 queue_id5_tsa_assign;
2398 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_TSA_ASSIGN_SP (0x0UL << 0)
2399 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_TSA_ASSIGN_ETS (0x1UL << 0)
2400 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_TSA_ASSIGN_RESERVED_FIRST (0x2UL << 0)
2401 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_TSA_ASSIGN_RESERVED_LAST (0xffffUL << 0)
2402 u8 queue_id5_pri_lvl;
2403 u8 queue_id5_bw_weight;
2405 __le32 queue_id6_min_bw;
2406 __le32 queue_id6_max_bw;
2407 u8 queue_id6_tsa_assign;
2408 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_TSA_ASSIGN_SP (0x0UL << 0)
2409 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_TSA_ASSIGN_ETS (0x1UL << 0)
2410 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_TSA_ASSIGN_RESERVED_FIRST (0x2UL << 0)
2411 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_TSA_ASSIGN_RESERVED_LAST (0xffffUL << 0)
2412 u8 queue_id6_pri_lvl;
2413 u8 queue_id6_bw_weight;
2415 __le32 queue_id7_min_bw;
2416 __le32 queue_id7_max_bw;
2417 u8 queue_id7_tsa_assign;
2418 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_TSA_ASSIGN_SP (0x0UL << 0)
2419 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_TSA_ASSIGN_ETS (0x1UL << 0)
2420 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_TSA_ASSIGN_RESERVED_FIRST (0x2UL << 0)
2421 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_TSA_ASSIGN_RESERVED_LAST (0xffffUL << 0)
2422 u8 queue_id7_pri_lvl;
2423 u8 queue_id7_bw_weight;
2427 /* Output (16 bytes) */
2428 struct hwrm_queue_cos2bw_cfg_output {
2440 /* hwrm_vnic_alloc */
2441 /* Input (24 bytes) */
2442 struct hwrm_vnic_alloc_input {
2449 #define VNIC_ALLOC_REQ_FLAGS_DEFAULT 0x1UL
2453 /* Output (16 bytes) */
2454 struct hwrm_vnic_alloc_output {
2466 /* hwrm_vnic_free */
2467 /* Input (24 bytes) */
2468 struct hwrm_vnic_free_input {
2478 /* Output (16 bytes) */
2479 struct hwrm_vnic_free_output {
2492 /* Input (40 bytes) */
2493 struct hwrm_vnic_cfg_input {
2500 #define VNIC_CFG_REQ_FLAGS_DEFAULT 0x1UL
2501 #define VNIC_CFG_REQ_FLAGS_VLAN_STRIP_MODE 0x2UL
2502 #define VNIC_CFG_REQ_FLAGS_BD_STALL_MODE 0x4UL
2503 #define VNIC_CFG_REQ_FLAGS_ROCE_DUAL_VNIC_MODE 0x8UL
2504 #define VNIC_CFG_REQ_FLAGS_ROCE_ONLY_VNIC_MODE 0x10UL
2506 #define VNIC_CFG_REQ_ENABLES_DFLT_RING_GRP 0x1UL
2507 #define VNIC_CFG_REQ_ENABLES_RSS_RULE 0x2UL
2508 #define VNIC_CFG_REQ_ENABLES_COS_RULE 0x4UL
2509 #define VNIC_CFG_REQ_ENABLES_LB_RULE 0x8UL
2510 #define VNIC_CFG_REQ_ENABLES_MRU 0x10UL
2512 __le16 dflt_ring_grp;
2520 /* Output (16 bytes) */
2521 struct hwrm_vnic_cfg_output {
2533 /* hwrm_vnic_tpa_cfg */
2534 /* Input (40 bytes) */
2535 struct hwrm_vnic_tpa_cfg_input {
2542 #define VNIC_TPA_CFG_REQ_FLAGS_TPA 0x1UL
2543 #define VNIC_TPA_CFG_REQ_FLAGS_ENCAP_TPA 0x2UL
2544 #define VNIC_TPA_CFG_REQ_FLAGS_RSC_WND_UPDATE 0x4UL
2545 #define VNIC_TPA_CFG_REQ_FLAGS_GRO 0x8UL
2546 #define VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_ECN 0x10UL
2547 #define VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_SAME_GRE_SEQ 0x20UL
2548 #define VNIC_TPA_CFG_REQ_FLAGS_GRO_IPID_CHECK 0x40UL
2549 #define VNIC_TPA_CFG_REQ_FLAGS_GRO_TTL_CHECK 0x80UL
2551 #define VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_SEGS 0x1UL
2552 #define VNIC_TPA_CFG_REQ_ENABLES_MAX_AGGS 0x2UL
2553 #define VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_TIMER 0x4UL
2554 #define VNIC_TPA_CFG_REQ_ENABLES_MIN_AGG_LEN 0x8UL
2556 __le16 max_agg_segs;
2557 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_1 (0x0UL << 0)
2558 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_2 (0x1UL << 0)
2559 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_4 (0x2UL << 0)
2560 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_8 (0x3UL << 0)
2561 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_MAX (0x1fUL << 0)
2563 #define VNIC_TPA_CFG_REQ_MAX_AGGS_1 (0x0UL << 0)
2564 #define VNIC_TPA_CFG_REQ_MAX_AGGS_2 (0x1UL << 0)
2565 #define VNIC_TPA_CFG_REQ_MAX_AGGS_4 (0x2UL << 0)
2566 #define VNIC_TPA_CFG_REQ_MAX_AGGS_8 (0x3UL << 0)
2567 #define VNIC_TPA_CFG_REQ_MAX_AGGS_16 (0x4UL << 0)
2568 #define VNIC_TPA_CFG_REQ_MAX_AGGS_MAX (0x7UL << 0)
2571 __le32 max_agg_timer;
2575 /* Output (16 bytes) */
2576 struct hwrm_vnic_tpa_cfg_output {
2588 /* hwrm_vnic_rss_cfg */
2589 /* Input (48 bytes) */
2590 struct hwrm_vnic_rss_cfg_input {
2597 #define VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4 0x1UL
2598 #define VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4 0x2UL
2599 #define VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4 0x4UL
2600 #define VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6 0x8UL
2601 #define VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6 0x10UL
2602 #define VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6 0x20UL
2604 __le64 ring_grp_tbl_addr;
2605 __le64 hash_key_tbl_addr;
2610 /* Output (16 bytes) */
2611 struct hwrm_vnic_rss_cfg_output {
2623 /* hwrm_vnic_plcmodes_cfg */
2624 /* Input (40 bytes) */
2625 struct hwrm_vnic_plcmodes_cfg_input {
2632 #define VNIC_PLCMODES_CFG_REQ_FLAGS_REGULAR_PLACEMENT 0x1UL
2633 #define VNIC_PLCMODES_CFG_REQ_FLAGS_JUMBO_PLACEMENT 0x2UL
2634 #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV4 0x4UL
2635 #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV6 0x8UL
2636 #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_FCOE 0x10UL
2637 #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_ROCE 0x20UL
2639 #define VNIC_PLCMODES_CFG_REQ_ENABLES_JUMBO_THRESH_VALID 0x1UL
2640 #define VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_OFFSET_VALID 0x2UL
2641 #define VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_THRESHOLD_VALID 0x4UL
2643 __le16 jumbo_thresh;
2645 __le16 hds_threshold;
2649 /* Output (16 bytes) */
2650 struct hwrm_vnic_plcmodes_cfg_output {
2662 /* hwrm_vnic_rss_cos_lb_ctx_alloc */
2663 /* Input (16 bytes) */
2664 struct hwrm_vnic_rss_cos_lb_ctx_alloc_input {
2672 /* Output (16 bytes) */
2673 struct hwrm_vnic_rss_cos_lb_ctx_alloc_output {
2678 __le16 rss_cos_lb_ctx_id;
2687 /* hwrm_vnic_rss_cos_lb_ctx_free */
2688 /* Input (24 bytes) */
2689 struct hwrm_vnic_rss_cos_lb_ctx_free_input {
2695 __le16 rss_cos_lb_ctx_id;
2699 /* Output (16 bytes) */
2700 struct hwrm_vnic_rss_cos_lb_ctx_free_output {
2712 /* hwrm_ring_alloc */
2713 /* Input (80 bytes) */
2714 struct hwrm_ring_alloc_input {
2721 #define RING_ALLOC_REQ_ENABLES_RESERVED1 0x1UL
2722 #define RING_ALLOC_REQ_ENABLES_RESERVED2 0x2UL
2723 #define RING_ALLOC_REQ_ENABLES_RESERVED3 0x4UL
2724 #define RING_ALLOC_REQ_ENABLES_STAT_CTX_ID_VALID 0x8UL
2725 #define RING_ALLOC_REQ_ENABLES_RESERVED4 0x10UL
2726 #define RING_ALLOC_REQ_ENABLES_MAX_BW_VALID 0x20UL
2728 #define RING_ALLOC_REQ_RING_TYPE_CMPL (0x0UL << 0)
2729 #define RING_ALLOC_REQ_RING_TYPE_TX (0x1UL << 0)
2730 #define RING_ALLOC_REQ_RING_TYPE_RX (0x2UL << 0)
2733 __le64 page_tbl_addr;
2741 __le16 cmpl_ring_id;
2754 #define RING_ALLOC_REQ_INT_MODE_LEGACY (0x0UL << 0)
2755 #define RING_ALLOC_REQ_INT_MODE_RSVD (0x1UL << 0)
2756 #define RING_ALLOC_REQ_INT_MODE_MSIX (0x2UL << 0)
2757 #define RING_ALLOC_REQ_INT_MODE_POLL (0x3UL << 0)
2761 /* Output (16 bytes) */
2762 struct hwrm_ring_alloc_output {
2768 __le16 logical_ring_id;
2775 /* hwrm_ring_free */
2776 /* Input (24 bytes) */
2777 struct hwrm_ring_free_input {
2784 #define RING_FREE_REQ_RING_TYPE_CMPL (0x0UL << 0)
2785 #define RING_FREE_REQ_RING_TYPE_TX (0x1UL << 0)
2786 #define RING_FREE_REQ_RING_TYPE_RX (0x2UL << 0)
2792 /* Output (16 bytes) */
2793 struct hwrm_ring_free_output {
2805 /* hwrm_ring_cmpl_ring_qaggint_params */
2806 /* Input (24 bytes) */
2807 struct hwrm_ring_cmpl_ring_qaggint_params_input {
2817 /* Output (32 bytes) */
2818 struct hwrm_ring_cmpl_ring_qaggint_params_output {
2824 #define RING_CMPL_RING_QAGGINT_PARAMS_RESP_FLAGS_TIMER_RESET 0x1UL
2825 #define RING_CMPL_RING_QAGGINT_PARAMS_RESP_FLAGS_RING_IDLE 0x2UL
2826 __le16 num_cmpl_dma_aggr;
2827 __le16 num_cmpl_dma_aggr_during_int;
2828 __le16 cmpl_aggr_dma_tmr;
2829 __le16 cmpl_aggr_dma_tmr_during_int;
2830 __le16 int_lat_tmr_min;
2831 __le16 int_lat_tmr_max;
2832 __le16 num_cmpl_aggr_int;
2840 /* hwrm_ring_cmpl_ring_cfg_aggint_params */
2841 /* Input (40 bytes) */
2842 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input {
2850 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET 0x1UL
2851 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_RING_IDLE 0x2UL
2852 __le16 num_cmpl_dma_aggr;
2853 __le16 num_cmpl_dma_aggr_during_int;
2854 __le16 cmpl_aggr_dma_tmr;
2855 __le16 cmpl_aggr_dma_tmr_during_int;
2856 __le16 int_lat_tmr_min;
2857 __le16 int_lat_tmr_max;
2858 __le16 num_cmpl_aggr_int;
2862 /* Output (16 bytes) */
2863 struct hwrm_ring_cmpl_ring_cfg_aggint_params_output {
2875 /* hwrm_ring_reset */
2876 /* Input (24 bytes) */
2877 struct hwrm_ring_reset_input {
2884 #define RING_RESET_REQ_RING_TYPE_CMPL (0x0UL << 0)
2885 #define RING_RESET_REQ_RING_TYPE_TX (0x1UL << 0)
2886 #define RING_RESET_REQ_RING_TYPE_RX (0x2UL << 0)
2892 /* Output (16 bytes) */
2893 struct hwrm_ring_reset_output {
2905 /* hwrm_ring_grp_alloc */
2906 /* Input (24 bytes) */
2907 struct hwrm_ring_grp_alloc_input {
2919 /* Output (16 bytes) */
2920 struct hwrm_ring_grp_alloc_output {
2925 __le32 ring_group_id;
2932 /* hwrm_ring_grp_free */
2933 /* Input (24 bytes) */
2934 struct hwrm_ring_grp_free_input {
2940 __le32 ring_group_id;
2944 /* Output (16 bytes) */
2945 struct hwrm_ring_grp_free_output {
2957 /* hwrm_cfa_l2_filter_alloc */
2958 /* Input (96 bytes) */
2959 struct hwrm_cfa_l2_filter_alloc_input {
2966 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH 0x1UL
2967 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_TX (0x0UL << 0)
2968 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX (0x1UL << 0)
2969 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_LAST CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX
2970 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_LOOPBACK 0x2UL
2971 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_DROP 0x4UL
2972 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_OUTERMOST 0x8UL
2974 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR 0x1UL
2975 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR_MASK 0x2UL
2976 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_OVLAN 0x4UL
2977 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_OVLAN_MASK 0x8UL
2978 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_IVLAN 0x10UL
2979 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_IVLAN_MASK 0x20UL
2980 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_ADDR 0x40UL
2981 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_ADDR_MASK 0x80UL
2982 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_OVLAN 0x100UL
2983 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_OVLAN_MASK 0x200UL
2984 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_IVLAN 0x400UL
2985 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_IVLAN_MASK 0x800UL
2986 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_SRC_TYPE 0x1000UL
2987 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_SRC_ID 0x2000UL
2988 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE 0x4000UL
2989 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_DST_ID 0x8000UL
2990 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID 0x10000UL
2996 __le16 l2_ovlan_mask;
2998 __le16 l2_ivlan_mask;
3004 u8 t_l2_addr_mask[6];
3006 __le16 t_l2_ovlan_mask;
3008 __le16 t_l2_ivlan_mask;
3010 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_NPORT (0x0UL << 0)
3011 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_PF (0x1UL << 0)
3012 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_VF (0x2UL << 0)
3013 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_VNIC (0x3UL << 0)
3014 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_KONG (0x4UL << 0)
3015 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_APE (0x5UL << 0)
3016 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_BONO (0x6UL << 0)
3017 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_TANG (0x7UL << 0)
3021 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL (0x0UL << 0)
3022 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN (0x1UL << 0)
3023 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE (0x2UL << 0)
3024 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE (0x3UL << 0)
3025 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP (0x4UL << 0)
3026 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE (0x5UL << 0)
3027 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS (0x6UL << 0)
3028 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT (0x7UL << 0)
3029 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE (0x8UL << 0)
3030 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL (0xffUL << 0)
3033 __le16 mirror_vnic_id;
3035 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_NO_PREFER (0x0UL << 0)
3036 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_ABOVE_FILTER (0x1UL << 0)
3037 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_BELOW_FILTER (0x2UL << 0)
3038 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_MAX (0x3UL << 0)
3039 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_MIN (0x4UL << 0)
3042 __le64 l2_filter_id_hint;
3045 /* Output (24 bytes) */
3046 struct hwrm_cfa_l2_filter_alloc_output {
3051 __le64 l2_filter_id;
3059 /* hwrm_cfa_l2_filter_free */
3060 /* Input (24 bytes) */
3061 struct hwrm_cfa_l2_filter_free_input {
3067 __le64 l2_filter_id;
3070 /* Output (16 bytes) */
3071 struct hwrm_cfa_l2_filter_free_output {
3083 /* hwrm_cfa_l2_filter_cfg */
3084 /* Input (40 bytes) */
3085 struct hwrm_cfa_l2_filter_cfg_input {
3092 #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH 0x1UL
3093 #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_TX (0x0UL << 0)
3094 #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_RX (0x1UL << 0)
3095 #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_LAST CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_RX
3096 #define CFA_L2_FILTER_CFG_REQ_FLAGS_DROP 0x2UL
3098 #define CFA_L2_FILTER_CFG_REQ_ENABLES_DST_ID 0x1UL
3099 #define CFA_L2_FILTER_CFG_REQ_ENABLES_NEW_MIRROR_VNIC_ID 0x2UL
3100 __le64 l2_filter_id;
3102 __le32 new_mirror_vnic_id;
3105 /* Output (16 bytes) */
3106 struct hwrm_cfa_l2_filter_cfg_output {
3118 /* hwrm_cfa_l2_set_rx_mask */
3119 /* Input (40 bytes) */
3120 struct hwrm_cfa_l2_set_rx_mask_input {
3128 #define CFA_L2_SET_RX_MASK_REQ_MASK_RESERVED 0x1UL
3129 #define CFA_L2_SET_RX_MASK_REQ_MASK_MCAST 0x2UL
3130 #define CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST 0x4UL
3131 #define CFA_L2_SET_RX_MASK_REQ_MASK_BCAST 0x8UL
3132 #define CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS 0x10UL
3133 #define CFA_L2_SET_RX_MASK_REQ_MASK_OUTERMOST 0x20UL
3135 __le32 num_mc_entries;
3139 /* Output (16 bytes) */
3140 struct hwrm_cfa_l2_set_rx_mask_output {
3152 /* hwrm_cfa_tunnel_filter_alloc */
3153 /* Input (88 bytes) */
3154 struct hwrm_cfa_tunnel_filter_alloc_input {
3161 #define CFA_TUNNEL_FILTER_ALLOC_REQ_FLAGS_LOOPBACK 0x1UL
3163 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID 0x1UL
3164 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L2_ADDR 0x2UL
3165 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L2_IVLAN 0x4UL
3166 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L3_ADDR 0x8UL
3167 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L3_ADDR_TYPE 0x10UL
3168 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_T_L3_ADDR_TYPE 0x20UL
3169 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_T_L3_ADDR 0x40UL
3170 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE 0x80UL
3171 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_VNI 0x100UL
3172 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_DST_VNIC_ID 0x200UL
3173 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID 0x400UL
3174 __le64 l2_filter_id;
3178 __le32 t_l3_addr[4];
3182 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL (0x0UL << 0)
3183 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN (0x1UL << 0)
3184 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE (0x2UL << 0)
3185 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE (0x3UL << 0)
3186 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP (0x4UL << 0)
3187 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE (0x5UL << 0)
3188 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS (0x6UL << 0)
3189 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT (0x7UL << 0)
3190 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE (0x8UL << 0)
3191 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL (0xffUL << 0)
3195 __le32 mirror_vnic_id;
3198 /* Output (24 bytes) */
3199 struct hwrm_cfa_tunnel_filter_alloc_output {
3204 __le64 tunnel_filter_id;
3212 /* hwrm_cfa_tunnel_filter_free */
3213 /* Input (24 bytes) */
3214 struct hwrm_cfa_tunnel_filter_free_input {
3220 __le64 tunnel_filter_id;
3223 /* Output (16 bytes) */
3224 struct hwrm_cfa_tunnel_filter_free_output {
3236 /* hwrm_cfa_encap_record_alloc */
3237 /* Input (32 bytes) */
3238 struct hwrm_cfa_encap_record_alloc_input {
3245 #define CFA_ENCAP_RECORD_ALLOC_REQ_FLAGS_LOOPBACK 0x1UL
3247 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VXLAN (0x1UL << 0)
3248 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_NVGRE (0x2UL << 0)
3249 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_L2GRE (0x3UL << 0)
3250 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_IPIP (0x4UL << 0)
3251 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_GENEVE (0x5UL << 0)
3252 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_MPLS (0x6UL << 0)
3253 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VLAN (0x7UL << 0)
3254 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_IPGRE (0x8UL << 0)
3257 __le32 encap_data[16];
3260 /* Output (16 bytes) */
3261 struct hwrm_cfa_encap_record_alloc_output {
3266 __le32 encap_record_id;
3273 /* hwrm_cfa_encap_record_free */
3274 /* Input (24 bytes) */
3275 struct hwrm_cfa_encap_record_free_input {
3281 __le32 encap_record_id;
3285 /* Output (16 bytes) */
3286 struct hwrm_cfa_encap_record_free_output {
3298 /* hwrm_cfa_ntuple_filter_alloc */
3299 /* Input (128 bytes) */
3300 struct hwrm_cfa_ntuple_filter_alloc_input {
3307 #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_LOOPBACK 0x1UL
3308 #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_DROP 0x2UL
3310 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID 0x1UL
3311 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_ETHERTYPE 0x2UL
3312 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE 0x4UL
3313 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_MACADDR 0x8UL
3314 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IPADDR_TYPE 0x10UL
3315 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR 0x20UL
3316 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR_MASK 0x40UL
3317 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR 0x80UL
3318 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR_MASK 0x100UL
3319 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IP_PROTOCOL 0x200UL
3320 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT 0x400UL
3321 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT_MASK 0x800UL
3322 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT 0x1000UL
3323 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT_MASK 0x2000UL
3324 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_PRI_HINT 0x4000UL
3325 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_NTUPLE_FILTER_ID 0x8000UL
3326 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_ID 0x10000UL
3327 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID 0x20000UL
3328 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_MACADDR 0x40000UL
3329 __le64 l2_filter_id;
3333 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_UNKNOWN (0x0UL << 0)
3334 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV4 (0x4UL << 0)
3335 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6 (0x6UL << 0)
3337 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_UNKNOWN (0x0UL << 0)
3338 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_UDP (0x6UL << 0)
3339 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_TCP (0x11UL << 0)
3341 __le16 mirror_vnic_id;
3343 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL (0x0UL << 0)
3344 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN (0x1UL << 0)
3345 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE (0x2UL << 0)
3346 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE (0x3UL << 0)
3347 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP (0x4UL << 0)
3348 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE (0x5UL << 0)
3349 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS (0x6UL << 0)
3350 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT (0x7UL << 0)
3351 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE (0x8UL << 0)
3352 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL (0xffUL << 0)
3354 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_NO_PREFER (0x0UL << 0)
3355 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_ABOVE (0x1UL << 0)
3356 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_BELOW (0x2UL << 0)
3357 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_HIGHEST (0x3UL << 0)
3358 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_LOWEST (0x4UL << 0)
3359 __be32 src_ipaddr[4];
3360 __be32 src_ipaddr_mask[4];
3361 __be32 dst_ipaddr[4];
3362 __be32 dst_ipaddr_mask[4];
3364 __be16 src_port_mask;
3366 __be16 dst_port_mask;
3367 __le64 ntuple_filter_id_hint;
3370 /* Output (24 bytes) */
3371 struct hwrm_cfa_ntuple_filter_alloc_output {
3376 __le64 ntuple_filter_id;
3384 /* hwrm_cfa_ntuple_filter_free */
3385 /* Input (24 bytes) */
3386 struct hwrm_cfa_ntuple_filter_free_input {
3392 __le64 ntuple_filter_id;
3395 /* Output (16 bytes) */
3396 struct hwrm_cfa_ntuple_filter_free_output {
3408 /* hwrm_cfa_ntuple_filter_cfg */
3409 /* Input (40 bytes) */
3410 struct hwrm_cfa_ntuple_filter_cfg_input {
3417 #define CFA_NTUPLE_FILTER_CFG_REQ_ENABLES_NEW_DST_ID 0x1UL
3418 #define CFA_NTUPLE_FILTER_CFG_REQ_ENABLES_NEW_MIRROR_VNIC_ID 0x2UL
3420 __le64 ntuple_filter_id;
3422 __le32 new_mirror_vnic_id;
3425 /* Output (16 bytes) */
3426 struct hwrm_cfa_ntuple_filter_cfg_output {
3438 /* hwrm_tunnel_dst_port_query */
3439 /* Input (24 bytes) */
3440 struct hwrm_tunnel_dst_port_query_input {
3447 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_VXLAN (0x1UL << 0)
3448 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_GENEVE (0x5UL << 0)
3452 /* Output (16 bytes) */
3453 struct hwrm_tunnel_dst_port_query_output {
3458 __le16 tunnel_dst_port_id;
3459 __be16 tunnel_dst_port_val;
3466 /* hwrm_tunnel_dst_port_alloc */
3467 /* Input (24 bytes) */
3468 struct hwrm_tunnel_dst_port_alloc_input {
3475 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN (0x1UL << 0)
3476 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_GENEVE (0x5UL << 0)
3478 __be16 tunnel_dst_port_val;
3482 /* Output (16 bytes) */
3483 struct hwrm_tunnel_dst_port_alloc_output {
3488 __le16 tunnel_dst_port_id;
3497 /* hwrm_tunnel_dst_port_free */
3498 /* Input (24 bytes) */
3499 struct hwrm_tunnel_dst_port_free_input {
3506 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN (0x1UL << 0)
3507 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE (0x5UL << 0)
3509 __le16 tunnel_dst_port_id;
3513 /* Output (16 bytes) */
3514 struct hwrm_tunnel_dst_port_free_output {
3526 /* hwrm_stat_ctx_alloc */
3527 /* Input (32 bytes) */
3528 struct hwrm_stat_ctx_alloc_input {
3534 __le64 stats_dma_addr;
3535 __le32 update_period_ms;
3539 /* Output (16 bytes) */
3540 struct hwrm_stat_ctx_alloc_output {
3552 /* hwrm_stat_ctx_free */
3553 /* Input (24 bytes) */
3554 struct hwrm_stat_ctx_free_input {
3564 /* Output (16 bytes) */
3565 struct hwrm_stat_ctx_free_output {
3577 /* hwrm_stat_ctx_query */
3578 /* Input (24 bytes) */
3579 struct hwrm_stat_ctx_query_input {
3589 /* Output (176 bytes) */
3590 struct hwrm_stat_ctx_query_output {
3595 __le64 tx_ucast_pkts;
3596 __le64 tx_mcast_pkts;
3597 __le64 tx_bcast_pkts;
3599 __le64 tx_drop_pkts;
3600 __le64 tx_ucast_bytes;
3601 __le64 tx_mcast_bytes;
3602 __le64 tx_bcast_bytes;
3603 __le64 rx_ucast_pkts;
3604 __le64 rx_mcast_pkts;
3605 __le64 rx_bcast_pkts;
3607 __le64 rx_drop_pkts;
3608 __le64 rx_ucast_bytes;
3609 __le64 rx_mcast_bytes;
3610 __le64 rx_bcast_bytes;
3612 __le64 rx_agg_bytes;
3613 __le64 rx_agg_events;
3614 __le64 rx_agg_aborts;
3622 /* hwrm_stat_ctx_clr_stats */
3623 /* Input (24 bytes) */
3624 struct hwrm_stat_ctx_clr_stats_input {
3634 /* Output (16 bytes) */
3635 struct hwrm_stat_ctx_clr_stats_output {
3648 /* Input (24 bytes) */
3649 struct hwrm_fw_reset_input {
3655 u8 embedded_proc_type;
3656 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_BOOT (0x0UL << 0)
3657 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_MGMT (0x1UL << 0)
3658 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_NETCTRL (0x2UL << 0)
3659 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_ROCE (0x3UL << 0)
3660 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_RSVD (0x4UL << 0)
3662 #define FW_RESET_REQ_SELFRST_STATUS_SELFRSTNONE (0x0UL << 0)
3663 #define FW_RESET_REQ_SELFRST_STATUS_SELFRSTASAP (0x1UL << 0)
3664 #define FW_RESET_REQ_SELFRST_STATUS_SELFRSTPCIERST (0x2UL << 0)
3668 /* Output (16 bytes) */
3669 struct hwrm_fw_reset_output {
3675 #define FW_RESET_RESP_SELFRST_STATUS_SELFRSTNONE (0x0UL << 0)
3676 #define FW_RESET_RESP_SELFRST_STATUS_SELFRSTASAP (0x1UL << 0)
3677 #define FW_RESET_RESP_SELFRST_STATUS_SELFRSTPCIERST (0x2UL << 0)
3686 /* hwrm_fw_qstatus */
3687 /* Input (24 bytes) */
3688 struct hwrm_fw_qstatus_input {
3694 u8 embedded_proc_type;
3695 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_BOOT (0x0UL << 0)
3696 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_MGMT (0x1UL << 0)
3697 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_NETCTRL (0x2UL << 0)
3698 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_ROCE (0x3UL << 0)
3699 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_RSVD (0x4UL << 0)
3703 /* Output (16 bytes) */
3704 struct hwrm_fw_qstatus_output {
3710 #define FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTNONE (0x0UL << 0)
3711 #define FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTASAP (0x1UL << 0)
3712 #define FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTPCIERST (0x2UL << 0)
3721 /* hwrm_exec_fwd_resp */
3722 /* Input (128 bytes) */
3723 struct hwrm_exec_fwd_resp_input {
3729 __le32 encap_request[26];
3730 __le16 encap_resp_target_id;
3734 /* Output (16 bytes) */
3735 struct hwrm_exec_fwd_resp_output {
3747 /* hwrm_reject_fwd_resp */
3748 /* Input (128 bytes) */
3749 struct hwrm_reject_fwd_resp_input {
3755 __le32 encap_request[26];
3756 __le16 encap_resp_target_id;
3760 /* Output (16 bytes) */
3761 struct hwrm_reject_fwd_resp_output {
3774 /* Input (40 bytes) */
3775 struct hwrm_fwd_resp_input {
3781 __le16 encap_resp_target_id;
3782 __le16 encap_resp_cmpl_ring;
3783 __le16 encap_resp_len;
3786 __le64 encap_resp_addr;
3787 __le32 encap_resp[24];
3790 /* Output (16 bytes) */
3791 struct hwrm_fwd_resp_output {
3803 /* hwrm_fwd_async_event_cmpl */
3804 /* Input (32 bytes) */
3805 struct hwrm_fwd_async_event_cmpl_input {
3811 __le16 encap_async_event_target_id;
3816 __le32 encap_async_event_cmpl[4];
3819 /* Output (16 bytes) */
3820 struct hwrm_fwd_async_event_cmpl_output {
3832 /* hwrm_temp_monitor_query */
3833 /* Input (16 bytes) */
3834 struct hwrm_temp_monitor_query_input {
3842 /* Output (16 bytes) */
3843 struct hwrm_temp_monitor_query_output {
3857 /* hwrm_nvm_raw_write_blk */
3858 /* Input (32 bytes) */
3859 struct hwrm_nvm_raw_write_blk_input {
3865 __le64 host_src_addr;
3870 /* Output (16 bytes) */
3871 struct hwrm_nvm_raw_write_blk_output {
3884 /* Input (40 bytes) */
3885 struct hwrm_nvm_read_input {
3891 __le64 host_dest_addr;
3900 /* Output (16 bytes) */
3901 struct hwrm_nvm_read_output {
3913 /* hwrm_nvm_raw_dump */
3914 /* Input (32 bytes) */
3915 struct hwrm_nvm_raw_dump_input {
3921 __le64 host_dest_addr;
3926 /* Output (16 bytes) */
3927 struct hwrm_nvm_raw_dump_output {
3939 /* hwrm_nvm_get_dir_entries */
3940 /* Input (24 bytes) */
3941 struct hwrm_nvm_get_dir_entries_input {
3947 __le64 host_dest_addr;
3950 /* Output (16 bytes) */
3951 struct hwrm_nvm_get_dir_entries_output {
3963 /* hwrm_nvm_get_dir_info */
3964 /* Input (16 bytes) */
3965 struct hwrm_nvm_get_dir_info_input {
3973 /* Output (24 bytes) */
3974 struct hwrm_nvm_get_dir_info_output {
3980 __le32 entry_length;
3988 /* hwrm_nvm_write */
3989 /* Input (48 bytes) */
3990 struct hwrm_nvm_write_input {
3996 __le64 host_src_addr;
4001 __le32 dir_data_length;
4004 #define NVM_WRITE_REQ_FLAGS_KEEP_ORIG_ACTIVE_IMG 0x1UL
4005 __le32 dir_item_length;
4009 /* Output (16 bytes) */
4010 struct hwrm_nvm_write_output {
4015 __le32 dir_item_length;
4021 /* hwrm_nvm_modify */
4022 /* Input (40 bytes) */
4023 struct hwrm_nvm_modify_input {
4029 __le64 host_src_addr;
4038 /* Output (16 bytes) */
4039 struct hwrm_nvm_modify_output {
4051 /* hwrm_nvm_find_dir_entry */
4052 /* Input (32 bytes) */
4053 struct hwrm_nvm_find_dir_entry_input {
4060 #define NVM_FIND_DIR_ENTRY_REQ_ENABLES_DIR_IDX_VALID 0x1UL
4066 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_MASK 0x3UL
4067 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_SFT 0
4068 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_EQ (0x0UL << 0)
4069 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_GE (0x1UL << 0)
4070 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_GT (0x2UL << 0)
4074 /* Output (32 bytes) */
4075 struct hwrm_nvm_find_dir_entry_output {
4080 __le32 dir_item_length;
4081 __le32 dir_data_length;
4092 /* hwrm_nvm_erase_dir_entry */
4093 /* Input (24 bytes) */
4094 struct hwrm_nvm_erase_dir_entry_input {
4104 /* Output (16 bytes) */
4105 struct hwrm_nvm_erase_dir_entry_output {
4117 /* hwrm_nvm_get_dev_info */
4118 /* Input (16 bytes) */
4119 struct hwrm_nvm_get_dev_info_input {
4127 /* Output (32 bytes) */
4128 struct hwrm_nvm_get_dev_info_output {
4133 __le16 manufacturer_id;
4137 __le32 reserved_size;
4138 __le32 available_size;
4145 /* hwrm_nvm_mod_dir_entry */
4146 /* Input (32 bytes) */
4147 struct hwrm_nvm_mod_dir_entry_input {
4154 #define NVM_MOD_DIR_ENTRY_REQ_ENABLES_CHECKSUM 0x1UL
4162 /* Output (16 bytes) */
4163 struct hwrm_nvm_mod_dir_entry_output {
4175 /* hwrm_nvm_verify_update */
4176 /* Input (24 bytes) */
4177 struct hwrm_nvm_verify_update_input {
4189 /* Output (16 bytes) */
4190 struct hwrm_nvm_verify_update_output {