1 /* Broadcom NetXtreme-C/E network driver.
3 * Copyright (c) 2014-2016 Broadcom Corporation
4 * Copyright (c) 2016-2017 Broadcom Limited
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation.
11 #include <linux/bitops.h>
12 #include <linux/ctype.h>
13 #include <linux/stringify.h>
14 #include <linux/ethtool.h>
15 #include <linux/ethtool_netlink.h>
16 #include <linux/linkmode.h>
17 #include <linux/interrupt.h>
18 #include <linux/pci.h>
19 #include <linux/etherdevice.h>
20 #include <linux/crc32.h>
21 #include <linux/firmware.h>
22 #include <linux/utsname.h>
23 #include <linux/time.h>
24 #include <linux/ptp_clock_kernel.h>
25 #include <linux/net_tstamp.h>
26 #include <linux/timecounter.h>
27 #include <net/netlink.h>
30 #include "bnxt_hwrm.h"
34 #include "bnxt_ethtool.h"
35 #include "bnxt_nvm_defs.h" /* NVRAM content constant and structure defs */
36 #include "bnxt_fw_hdr.h" /* Firmware hdr constant and structure defs */
37 #include "bnxt_coredump.h"
39 #define BNXT_NVM_ERR_MSG(dev, extack, msg) \
42 NL_SET_ERR_MSG_MOD(extack, msg); \
43 netdev_err(dev, "%s\n", msg); \
46 static u32 bnxt_get_msglevel(struct net_device *dev)
48 struct bnxt *bp = netdev_priv(dev);
50 return bp->msg_enable;
53 static void bnxt_set_msglevel(struct net_device *dev, u32 value)
55 struct bnxt *bp = netdev_priv(dev);
57 bp->msg_enable = value;
60 static int bnxt_get_coalesce(struct net_device *dev,
61 struct ethtool_coalesce *coal,
62 struct kernel_ethtool_coalesce *kernel_coal,
63 struct netlink_ext_ack *extack)
65 struct bnxt *bp = netdev_priv(dev);
66 struct bnxt_coal *hw_coal;
69 memset(coal, 0, sizeof(*coal));
71 coal->use_adaptive_rx_coalesce = bp->flags & BNXT_FLAG_DIM;
73 hw_coal = &bp->rx_coal;
74 mult = hw_coal->bufs_per_record;
75 coal->rx_coalesce_usecs = hw_coal->coal_ticks;
76 coal->rx_max_coalesced_frames = hw_coal->coal_bufs / mult;
77 coal->rx_coalesce_usecs_irq = hw_coal->coal_ticks_irq;
78 coal->rx_max_coalesced_frames_irq = hw_coal->coal_bufs_irq / mult;
80 RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET)
81 kernel_coal->use_cqe_mode_rx = true;
83 hw_coal = &bp->tx_coal;
84 mult = hw_coal->bufs_per_record;
85 coal->tx_coalesce_usecs = hw_coal->coal_ticks;
86 coal->tx_max_coalesced_frames = hw_coal->coal_bufs / mult;
87 coal->tx_coalesce_usecs_irq = hw_coal->coal_ticks_irq;
88 coal->tx_max_coalesced_frames_irq = hw_coal->coal_bufs_irq / mult;
90 RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET)
91 kernel_coal->use_cqe_mode_tx = true;
93 coal->stats_block_coalesce_usecs = bp->stats_coal_ticks;
98 static int bnxt_set_coalesce(struct net_device *dev,
99 struct ethtool_coalesce *coal,
100 struct kernel_ethtool_coalesce *kernel_coal,
101 struct netlink_ext_ack *extack)
103 struct bnxt *bp = netdev_priv(dev);
104 bool update_stats = false;
105 struct bnxt_coal *hw_coal;
109 if (coal->use_adaptive_rx_coalesce) {
110 bp->flags |= BNXT_FLAG_DIM;
112 if (bp->flags & BNXT_FLAG_DIM) {
113 bp->flags &= ~(BNXT_FLAG_DIM);
118 if ((kernel_coal->use_cqe_mode_rx || kernel_coal->use_cqe_mode_tx) &&
119 !(bp->coal_cap.cmpl_params &
120 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_TIMER_RESET))
123 hw_coal = &bp->rx_coal;
124 mult = hw_coal->bufs_per_record;
125 hw_coal->coal_ticks = coal->rx_coalesce_usecs;
126 hw_coal->coal_bufs = coal->rx_max_coalesced_frames * mult;
127 hw_coal->coal_ticks_irq = coal->rx_coalesce_usecs_irq;
128 hw_coal->coal_bufs_irq = coal->rx_max_coalesced_frames_irq * mult;
130 ~RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET;
131 if (kernel_coal->use_cqe_mode_rx)
133 RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET;
135 hw_coal = &bp->tx_coal;
136 mult = hw_coal->bufs_per_record;
137 hw_coal->coal_ticks = coal->tx_coalesce_usecs;
138 hw_coal->coal_bufs = coal->tx_max_coalesced_frames * mult;
139 hw_coal->coal_ticks_irq = coal->tx_coalesce_usecs_irq;
140 hw_coal->coal_bufs_irq = coal->tx_max_coalesced_frames_irq * mult;
142 ~RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET;
143 if (kernel_coal->use_cqe_mode_tx)
145 RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET;
147 if (bp->stats_coal_ticks != coal->stats_block_coalesce_usecs) {
148 u32 stats_ticks = coal->stats_block_coalesce_usecs;
150 /* Allow 0, which means disable. */
152 stats_ticks = clamp_t(u32, stats_ticks,
153 BNXT_MIN_STATS_COAL_TICKS,
154 BNXT_MAX_STATS_COAL_TICKS);
155 stats_ticks = rounddown(stats_ticks, BNXT_MIN_STATS_COAL_TICKS);
156 bp->stats_coal_ticks = stats_ticks;
157 if (bp->stats_coal_ticks)
158 bp->current_interval =
159 bp->stats_coal_ticks * HZ / 1000000;
161 bp->current_interval = BNXT_TIMER_INTERVAL;
166 if (test_bit(BNXT_STATE_OPEN, &bp->state)) {
168 bnxt_close_nic(bp, true, false);
169 rc = bnxt_open_nic(bp, true, false);
171 rc = bnxt_hwrm_set_coal(bp);
178 static const char * const bnxt_ring_rx_stats_str[] = {
189 static const char * const bnxt_ring_tx_stats_str[] = {
200 static const char * const bnxt_ring_tpa_stats_str[] = {
207 static const char * const bnxt_ring_tpa2_stats_str[] = {
208 "rx_tpa_eligible_pkt",
209 "rx_tpa_eligible_bytes",
216 static const char * const bnxt_rx_sw_stats_str[] = {
222 static const char * const bnxt_cmn_sw_stats_str[] = {
226 #define BNXT_RX_STATS_ENTRY(counter) \
227 { BNXT_RX_STATS_OFFSET(counter), __stringify(counter) }
229 #define BNXT_TX_STATS_ENTRY(counter) \
230 { BNXT_TX_STATS_OFFSET(counter), __stringify(counter) }
232 #define BNXT_RX_STATS_EXT_ENTRY(counter) \
233 { BNXT_RX_STATS_EXT_OFFSET(counter), __stringify(counter) }
235 #define BNXT_TX_STATS_EXT_ENTRY(counter) \
236 { BNXT_TX_STATS_EXT_OFFSET(counter), __stringify(counter) }
238 #define BNXT_RX_STATS_EXT_PFC_ENTRY(n) \
239 BNXT_RX_STATS_EXT_ENTRY(pfc_pri##n##_rx_duration_us), \
240 BNXT_RX_STATS_EXT_ENTRY(pfc_pri##n##_rx_transitions)
242 #define BNXT_TX_STATS_EXT_PFC_ENTRY(n) \
243 BNXT_TX_STATS_EXT_ENTRY(pfc_pri##n##_tx_duration_us), \
244 BNXT_TX_STATS_EXT_ENTRY(pfc_pri##n##_tx_transitions)
246 #define BNXT_RX_STATS_EXT_PFC_ENTRIES \
247 BNXT_RX_STATS_EXT_PFC_ENTRY(0), \
248 BNXT_RX_STATS_EXT_PFC_ENTRY(1), \
249 BNXT_RX_STATS_EXT_PFC_ENTRY(2), \
250 BNXT_RX_STATS_EXT_PFC_ENTRY(3), \
251 BNXT_RX_STATS_EXT_PFC_ENTRY(4), \
252 BNXT_RX_STATS_EXT_PFC_ENTRY(5), \
253 BNXT_RX_STATS_EXT_PFC_ENTRY(6), \
254 BNXT_RX_STATS_EXT_PFC_ENTRY(7)
256 #define BNXT_TX_STATS_EXT_PFC_ENTRIES \
257 BNXT_TX_STATS_EXT_PFC_ENTRY(0), \
258 BNXT_TX_STATS_EXT_PFC_ENTRY(1), \
259 BNXT_TX_STATS_EXT_PFC_ENTRY(2), \
260 BNXT_TX_STATS_EXT_PFC_ENTRY(3), \
261 BNXT_TX_STATS_EXT_PFC_ENTRY(4), \
262 BNXT_TX_STATS_EXT_PFC_ENTRY(5), \
263 BNXT_TX_STATS_EXT_PFC_ENTRY(6), \
264 BNXT_TX_STATS_EXT_PFC_ENTRY(7)
266 #define BNXT_RX_STATS_EXT_COS_ENTRY(n) \
267 BNXT_RX_STATS_EXT_ENTRY(rx_bytes_cos##n), \
268 BNXT_RX_STATS_EXT_ENTRY(rx_packets_cos##n)
270 #define BNXT_TX_STATS_EXT_COS_ENTRY(n) \
271 BNXT_TX_STATS_EXT_ENTRY(tx_bytes_cos##n), \
272 BNXT_TX_STATS_EXT_ENTRY(tx_packets_cos##n)
274 #define BNXT_RX_STATS_EXT_COS_ENTRIES \
275 BNXT_RX_STATS_EXT_COS_ENTRY(0), \
276 BNXT_RX_STATS_EXT_COS_ENTRY(1), \
277 BNXT_RX_STATS_EXT_COS_ENTRY(2), \
278 BNXT_RX_STATS_EXT_COS_ENTRY(3), \
279 BNXT_RX_STATS_EXT_COS_ENTRY(4), \
280 BNXT_RX_STATS_EXT_COS_ENTRY(5), \
281 BNXT_RX_STATS_EXT_COS_ENTRY(6), \
282 BNXT_RX_STATS_EXT_COS_ENTRY(7) \
284 #define BNXT_TX_STATS_EXT_COS_ENTRIES \
285 BNXT_TX_STATS_EXT_COS_ENTRY(0), \
286 BNXT_TX_STATS_EXT_COS_ENTRY(1), \
287 BNXT_TX_STATS_EXT_COS_ENTRY(2), \
288 BNXT_TX_STATS_EXT_COS_ENTRY(3), \
289 BNXT_TX_STATS_EXT_COS_ENTRY(4), \
290 BNXT_TX_STATS_EXT_COS_ENTRY(5), \
291 BNXT_TX_STATS_EXT_COS_ENTRY(6), \
292 BNXT_TX_STATS_EXT_COS_ENTRY(7) \
294 #define BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(n) \
295 BNXT_RX_STATS_EXT_ENTRY(rx_discard_bytes_cos##n), \
296 BNXT_RX_STATS_EXT_ENTRY(rx_discard_packets_cos##n)
298 #define BNXT_RX_STATS_EXT_DISCARD_COS_ENTRIES \
299 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(0), \
300 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(1), \
301 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(2), \
302 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(3), \
303 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(4), \
304 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(5), \
305 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(6), \
306 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(7)
308 #define BNXT_RX_STATS_PRI_ENTRY(counter, n) \
309 { BNXT_RX_STATS_EXT_OFFSET(counter##_cos0), \
310 __stringify(counter##_pri##n) }
312 #define BNXT_TX_STATS_PRI_ENTRY(counter, n) \
313 { BNXT_TX_STATS_EXT_OFFSET(counter##_cos0), \
314 __stringify(counter##_pri##n) }
316 #define BNXT_RX_STATS_PRI_ENTRIES(counter) \
317 BNXT_RX_STATS_PRI_ENTRY(counter, 0), \
318 BNXT_RX_STATS_PRI_ENTRY(counter, 1), \
319 BNXT_RX_STATS_PRI_ENTRY(counter, 2), \
320 BNXT_RX_STATS_PRI_ENTRY(counter, 3), \
321 BNXT_RX_STATS_PRI_ENTRY(counter, 4), \
322 BNXT_RX_STATS_PRI_ENTRY(counter, 5), \
323 BNXT_RX_STATS_PRI_ENTRY(counter, 6), \
324 BNXT_RX_STATS_PRI_ENTRY(counter, 7)
326 #define BNXT_TX_STATS_PRI_ENTRIES(counter) \
327 BNXT_TX_STATS_PRI_ENTRY(counter, 0), \
328 BNXT_TX_STATS_PRI_ENTRY(counter, 1), \
329 BNXT_TX_STATS_PRI_ENTRY(counter, 2), \
330 BNXT_TX_STATS_PRI_ENTRY(counter, 3), \
331 BNXT_TX_STATS_PRI_ENTRY(counter, 4), \
332 BNXT_TX_STATS_PRI_ENTRY(counter, 5), \
333 BNXT_TX_STATS_PRI_ENTRY(counter, 6), \
334 BNXT_TX_STATS_PRI_ENTRY(counter, 7)
342 static const char *const bnxt_ring_err_stats_arr[] = {
343 "rx_total_l4_csum_errors",
345 "rx_total_buf_errors",
346 "rx_total_oom_discards",
347 "rx_total_netpoll_discards",
348 "rx_total_ring_discards",
350 "tx_total_ring_discards",
354 #define NUM_RING_RX_SW_STATS ARRAY_SIZE(bnxt_rx_sw_stats_str)
355 #define NUM_RING_CMN_SW_STATS ARRAY_SIZE(bnxt_cmn_sw_stats_str)
356 #define NUM_RING_RX_HW_STATS ARRAY_SIZE(bnxt_ring_rx_stats_str)
357 #define NUM_RING_TX_HW_STATS ARRAY_SIZE(bnxt_ring_tx_stats_str)
359 static const struct {
361 char string[ETH_GSTRING_LEN];
362 } bnxt_port_stats_arr[] = {
363 BNXT_RX_STATS_ENTRY(rx_64b_frames),
364 BNXT_RX_STATS_ENTRY(rx_65b_127b_frames),
365 BNXT_RX_STATS_ENTRY(rx_128b_255b_frames),
366 BNXT_RX_STATS_ENTRY(rx_256b_511b_frames),
367 BNXT_RX_STATS_ENTRY(rx_512b_1023b_frames),
368 BNXT_RX_STATS_ENTRY(rx_1024b_1518b_frames),
369 BNXT_RX_STATS_ENTRY(rx_good_vlan_frames),
370 BNXT_RX_STATS_ENTRY(rx_1519b_2047b_frames),
371 BNXT_RX_STATS_ENTRY(rx_2048b_4095b_frames),
372 BNXT_RX_STATS_ENTRY(rx_4096b_9216b_frames),
373 BNXT_RX_STATS_ENTRY(rx_9217b_16383b_frames),
374 BNXT_RX_STATS_ENTRY(rx_total_frames),
375 BNXT_RX_STATS_ENTRY(rx_ucast_frames),
376 BNXT_RX_STATS_ENTRY(rx_mcast_frames),
377 BNXT_RX_STATS_ENTRY(rx_bcast_frames),
378 BNXT_RX_STATS_ENTRY(rx_fcs_err_frames),
379 BNXT_RX_STATS_ENTRY(rx_ctrl_frames),
380 BNXT_RX_STATS_ENTRY(rx_pause_frames),
381 BNXT_RX_STATS_ENTRY(rx_pfc_frames),
382 BNXT_RX_STATS_ENTRY(rx_align_err_frames),
383 BNXT_RX_STATS_ENTRY(rx_ovrsz_frames),
384 BNXT_RX_STATS_ENTRY(rx_jbr_frames),
385 BNXT_RX_STATS_ENTRY(rx_mtu_err_frames),
386 BNXT_RX_STATS_ENTRY(rx_tagged_frames),
387 BNXT_RX_STATS_ENTRY(rx_double_tagged_frames),
388 BNXT_RX_STATS_ENTRY(rx_good_frames),
389 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri0),
390 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri1),
391 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri2),
392 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri3),
393 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri4),
394 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri5),
395 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri6),
396 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri7),
397 BNXT_RX_STATS_ENTRY(rx_undrsz_frames),
398 BNXT_RX_STATS_ENTRY(rx_eee_lpi_events),
399 BNXT_RX_STATS_ENTRY(rx_eee_lpi_duration),
400 BNXT_RX_STATS_ENTRY(rx_bytes),
401 BNXT_RX_STATS_ENTRY(rx_runt_bytes),
402 BNXT_RX_STATS_ENTRY(rx_runt_frames),
403 BNXT_RX_STATS_ENTRY(rx_stat_discard),
404 BNXT_RX_STATS_ENTRY(rx_stat_err),
406 BNXT_TX_STATS_ENTRY(tx_64b_frames),
407 BNXT_TX_STATS_ENTRY(tx_65b_127b_frames),
408 BNXT_TX_STATS_ENTRY(tx_128b_255b_frames),
409 BNXT_TX_STATS_ENTRY(tx_256b_511b_frames),
410 BNXT_TX_STATS_ENTRY(tx_512b_1023b_frames),
411 BNXT_TX_STATS_ENTRY(tx_1024b_1518b_frames),
412 BNXT_TX_STATS_ENTRY(tx_good_vlan_frames),
413 BNXT_TX_STATS_ENTRY(tx_1519b_2047b_frames),
414 BNXT_TX_STATS_ENTRY(tx_2048b_4095b_frames),
415 BNXT_TX_STATS_ENTRY(tx_4096b_9216b_frames),
416 BNXT_TX_STATS_ENTRY(tx_9217b_16383b_frames),
417 BNXT_TX_STATS_ENTRY(tx_good_frames),
418 BNXT_TX_STATS_ENTRY(tx_total_frames),
419 BNXT_TX_STATS_ENTRY(tx_ucast_frames),
420 BNXT_TX_STATS_ENTRY(tx_mcast_frames),
421 BNXT_TX_STATS_ENTRY(tx_bcast_frames),
422 BNXT_TX_STATS_ENTRY(tx_pause_frames),
423 BNXT_TX_STATS_ENTRY(tx_pfc_frames),
424 BNXT_TX_STATS_ENTRY(tx_jabber_frames),
425 BNXT_TX_STATS_ENTRY(tx_fcs_err_frames),
426 BNXT_TX_STATS_ENTRY(tx_err),
427 BNXT_TX_STATS_ENTRY(tx_fifo_underruns),
428 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri0),
429 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri1),
430 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri2),
431 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri3),
432 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri4),
433 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri5),
434 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri6),
435 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri7),
436 BNXT_TX_STATS_ENTRY(tx_eee_lpi_events),
437 BNXT_TX_STATS_ENTRY(tx_eee_lpi_duration),
438 BNXT_TX_STATS_ENTRY(tx_total_collisions),
439 BNXT_TX_STATS_ENTRY(tx_bytes),
440 BNXT_TX_STATS_ENTRY(tx_xthol_frames),
441 BNXT_TX_STATS_ENTRY(tx_stat_discard),
442 BNXT_TX_STATS_ENTRY(tx_stat_error),
445 static const struct {
447 char string[ETH_GSTRING_LEN];
448 } bnxt_port_stats_ext_arr[] = {
449 BNXT_RX_STATS_EXT_ENTRY(link_down_events),
450 BNXT_RX_STATS_EXT_ENTRY(continuous_pause_events),
451 BNXT_RX_STATS_EXT_ENTRY(resume_pause_events),
452 BNXT_RX_STATS_EXT_ENTRY(continuous_roce_pause_events),
453 BNXT_RX_STATS_EXT_ENTRY(resume_roce_pause_events),
454 BNXT_RX_STATS_EXT_COS_ENTRIES,
455 BNXT_RX_STATS_EXT_PFC_ENTRIES,
456 BNXT_RX_STATS_EXT_ENTRY(rx_bits),
457 BNXT_RX_STATS_EXT_ENTRY(rx_buffer_passed_threshold),
458 BNXT_RX_STATS_EXT_ENTRY(rx_pcs_symbol_err),
459 BNXT_RX_STATS_EXT_ENTRY(rx_corrected_bits),
460 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRIES,
461 BNXT_RX_STATS_EXT_ENTRY(rx_fec_corrected_blocks),
462 BNXT_RX_STATS_EXT_ENTRY(rx_fec_uncorrectable_blocks),
463 BNXT_RX_STATS_EXT_ENTRY(rx_filter_miss),
466 static const struct {
468 char string[ETH_GSTRING_LEN];
469 } bnxt_tx_port_stats_ext_arr[] = {
470 BNXT_TX_STATS_EXT_COS_ENTRIES,
471 BNXT_TX_STATS_EXT_PFC_ENTRIES,
474 static const struct {
476 char string[ETH_GSTRING_LEN];
477 } bnxt_rx_bytes_pri_arr[] = {
478 BNXT_RX_STATS_PRI_ENTRIES(rx_bytes),
481 static const struct {
483 char string[ETH_GSTRING_LEN];
484 } bnxt_rx_pkts_pri_arr[] = {
485 BNXT_RX_STATS_PRI_ENTRIES(rx_packets),
488 static const struct {
490 char string[ETH_GSTRING_LEN];
491 } bnxt_tx_bytes_pri_arr[] = {
492 BNXT_TX_STATS_PRI_ENTRIES(tx_bytes),
495 static const struct {
497 char string[ETH_GSTRING_LEN];
498 } bnxt_tx_pkts_pri_arr[] = {
499 BNXT_TX_STATS_PRI_ENTRIES(tx_packets),
502 #define BNXT_NUM_RING_ERR_STATS ARRAY_SIZE(bnxt_ring_err_stats_arr)
503 #define BNXT_NUM_PORT_STATS ARRAY_SIZE(bnxt_port_stats_arr)
504 #define BNXT_NUM_STATS_PRI \
505 (ARRAY_SIZE(bnxt_rx_bytes_pri_arr) + \
506 ARRAY_SIZE(bnxt_rx_pkts_pri_arr) + \
507 ARRAY_SIZE(bnxt_tx_bytes_pri_arr) + \
508 ARRAY_SIZE(bnxt_tx_pkts_pri_arr))
510 static int bnxt_get_num_tpa_ring_stats(struct bnxt *bp)
512 if (BNXT_SUPPORTS_TPA(bp)) {
513 if (bp->max_tpa_v2) {
514 if (BNXT_CHIP_P5(bp))
515 return BNXT_NUM_TPA_RING_STATS_P5;
516 return BNXT_NUM_TPA_RING_STATS_P7;
518 return BNXT_NUM_TPA_RING_STATS;
523 static int bnxt_get_num_ring_stats(struct bnxt *bp)
527 rx = NUM_RING_RX_HW_STATS + NUM_RING_RX_SW_STATS +
528 bnxt_get_num_tpa_ring_stats(bp);
529 tx = NUM_RING_TX_HW_STATS;
530 cmn = NUM_RING_CMN_SW_STATS;
531 return rx * bp->rx_nr_rings +
532 tx * (bp->tx_nr_rings_xdp + bp->tx_nr_rings_per_tc) +
533 cmn * bp->cp_nr_rings;
536 static int bnxt_get_num_stats(struct bnxt *bp)
538 int num_stats = bnxt_get_num_ring_stats(bp);
541 num_stats += BNXT_NUM_RING_ERR_STATS;
543 if (bp->flags & BNXT_FLAG_PORT_STATS)
544 num_stats += BNXT_NUM_PORT_STATS;
546 if (bp->flags & BNXT_FLAG_PORT_STATS_EXT) {
547 len = min_t(int, bp->fw_rx_stats_ext_size,
548 ARRAY_SIZE(bnxt_port_stats_ext_arr));
550 len = min_t(int, bp->fw_tx_stats_ext_size,
551 ARRAY_SIZE(bnxt_tx_port_stats_ext_arr));
553 if (bp->pri2cos_valid)
554 num_stats += BNXT_NUM_STATS_PRI;
560 static int bnxt_get_sset_count(struct net_device *dev, int sset)
562 struct bnxt *bp = netdev_priv(dev);
566 return bnxt_get_num_stats(bp);
570 return bp->num_tests;
576 static bool is_rx_ring(struct bnxt *bp, int ring_num)
578 return ring_num < bp->rx_nr_rings;
581 static bool is_tx_ring(struct bnxt *bp, int ring_num)
585 if (!(bp->flags & BNXT_FLAG_SHARED_RINGS))
586 tx_base = bp->rx_nr_rings;
588 if (ring_num >= tx_base && ring_num < (tx_base + bp->tx_nr_rings))
593 static void bnxt_get_ethtool_stats(struct net_device *dev,
594 struct ethtool_stats *stats, u64 *buf)
596 struct bnxt_total_ring_err_stats ring_err_stats = {0};
597 struct bnxt *bp = netdev_priv(dev);
603 j += bnxt_get_num_ring_stats(bp);
604 goto skip_ring_stats;
607 tpa_stats = bnxt_get_num_tpa_ring_stats(bp);
608 for (i = 0; i < bp->cp_nr_rings; i++) {
609 struct bnxt_napi *bnapi = bp->bnapi[i];
610 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
611 u64 *sw_stats = cpr->stats.sw_stats;
615 if (is_rx_ring(bp, i)) {
616 for (k = 0; k < NUM_RING_RX_HW_STATS; j++, k++)
617 buf[j] = sw_stats[k];
619 if (is_tx_ring(bp, i)) {
620 k = NUM_RING_RX_HW_STATS;
621 for (; k < NUM_RING_RX_HW_STATS + NUM_RING_TX_HW_STATS;
623 buf[j] = sw_stats[k];
625 if (!tpa_stats || !is_rx_ring(bp, i))
626 goto skip_tpa_ring_stats;
628 k = NUM_RING_RX_HW_STATS + NUM_RING_TX_HW_STATS;
629 for (; k < NUM_RING_RX_HW_STATS + NUM_RING_TX_HW_STATS +
631 buf[j] = sw_stats[k];
634 sw = (u64 *)&cpr->sw_stats.rx;
635 if (is_rx_ring(bp, i)) {
636 for (k = 0; k < NUM_RING_RX_SW_STATS; j++, k++)
640 sw = (u64 *)&cpr->sw_stats.cmn;
641 for (k = 0; k < NUM_RING_CMN_SW_STATS; j++, k++)
645 bnxt_get_ring_err_stats(bp, &ring_err_stats);
648 curr = &ring_err_stats.rx_total_l4_csum_errors;
649 prev = &bp->ring_err_stats_prev.rx_total_l4_csum_errors;
650 for (i = 0; i < BNXT_NUM_RING_ERR_STATS; i++, j++, curr++, prev++)
651 buf[j] = *curr + *prev;
653 if (bp->flags & BNXT_FLAG_PORT_STATS) {
654 u64 *port_stats = bp->port_stats.sw_stats;
656 for (i = 0; i < BNXT_NUM_PORT_STATS; i++, j++)
657 buf[j] = *(port_stats + bnxt_port_stats_arr[i].offset);
659 if (bp->flags & BNXT_FLAG_PORT_STATS_EXT) {
660 u64 *rx_port_stats_ext = bp->rx_port_stats_ext.sw_stats;
661 u64 *tx_port_stats_ext = bp->tx_port_stats_ext.sw_stats;
664 len = min_t(u32, bp->fw_rx_stats_ext_size,
665 ARRAY_SIZE(bnxt_port_stats_ext_arr));
666 for (i = 0; i < len; i++, j++) {
667 buf[j] = *(rx_port_stats_ext +
668 bnxt_port_stats_ext_arr[i].offset);
670 len = min_t(u32, bp->fw_tx_stats_ext_size,
671 ARRAY_SIZE(bnxt_tx_port_stats_ext_arr));
672 for (i = 0; i < len; i++, j++) {
673 buf[j] = *(tx_port_stats_ext +
674 bnxt_tx_port_stats_ext_arr[i].offset);
676 if (bp->pri2cos_valid) {
677 for (i = 0; i < 8; i++, j++) {
678 long n = bnxt_rx_bytes_pri_arr[i].base_off +
681 buf[j] = *(rx_port_stats_ext + n);
683 for (i = 0; i < 8; i++, j++) {
684 long n = bnxt_rx_pkts_pri_arr[i].base_off +
687 buf[j] = *(rx_port_stats_ext + n);
689 for (i = 0; i < 8; i++, j++) {
690 long n = bnxt_tx_bytes_pri_arr[i].base_off +
693 buf[j] = *(tx_port_stats_ext + n);
695 for (i = 0; i < 8; i++, j++) {
696 long n = bnxt_tx_pkts_pri_arr[i].base_off +
699 buf[j] = *(tx_port_stats_ext + n);
705 static void bnxt_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
707 struct bnxt *bp = netdev_priv(dev);
708 static const char * const *str;
713 for (i = 0; i < bp->cp_nr_rings; i++) {
714 if (is_rx_ring(bp, i)) {
715 num_str = NUM_RING_RX_HW_STATS;
716 for (j = 0; j < num_str; j++) {
717 sprintf(buf, "[%d]: %s", i,
718 bnxt_ring_rx_stats_str[j]);
719 buf += ETH_GSTRING_LEN;
722 if (is_tx_ring(bp, i)) {
723 num_str = NUM_RING_TX_HW_STATS;
724 for (j = 0; j < num_str; j++) {
725 sprintf(buf, "[%d]: %s", i,
726 bnxt_ring_tx_stats_str[j]);
727 buf += ETH_GSTRING_LEN;
730 num_str = bnxt_get_num_tpa_ring_stats(bp);
731 if (!num_str || !is_rx_ring(bp, i))
735 str = bnxt_ring_tpa2_stats_str;
737 str = bnxt_ring_tpa_stats_str;
739 for (j = 0; j < num_str; j++) {
740 sprintf(buf, "[%d]: %s", i, str[j]);
741 buf += ETH_GSTRING_LEN;
744 if (is_rx_ring(bp, i)) {
745 num_str = NUM_RING_RX_SW_STATS;
746 for (j = 0; j < num_str; j++) {
747 sprintf(buf, "[%d]: %s", i,
748 bnxt_rx_sw_stats_str[j]);
749 buf += ETH_GSTRING_LEN;
752 num_str = NUM_RING_CMN_SW_STATS;
753 for (j = 0; j < num_str; j++) {
754 sprintf(buf, "[%d]: %s", i,
755 bnxt_cmn_sw_stats_str[j]);
756 buf += ETH_GSTRING_LEN;
759 for (i = 0; i < BNXT_NUM_RING_ERR_STATS; i++) {
760 strscpy(buf, bnxt_ring_err_stats_arr[i], ETH_GSTRING_LEN);
761 buf += ETH_GSTRING_LEN;
764 if (bp->flags & BNXT_FLAG_PORT_STATS) {
765 for (i = 0; i < BNXT_NUM_PORT_STATS; i++) {
766 strcpy(buf, bnxt_port_stats_arr[i].string);
767 buf += ETH_GSTRING_LEN;
770 if (bp->flags & BNXT_FLAG_PORT_STATS_EXT) {
773 len = min_t(u32, bp->fw_rx_stats_ext_size,
774 ARRAY_SIZE(bnxt_port_stats_ext_arr));
775 for (i = 0; i < len; i++) {
776 strcpy(buf, bnxt_port_stats_ext_arr[i].string);
777 buf += ETH_GSTRING_LEN;
779 len = min_t(u32, bp->fw_tx_stats_ext_size,
780 ARRAY_SIZE(bnxt_tx_port_stats_ext_arr));
781 for (i = 0; i < len; i++) {
783 bnxt_tx_port_stats_ext_arr[i].string);
784 buf += ETH_GSTRING_LEN;
786 if (bp->pri2cos_valid) {
787 for (i = 0; i < 8; i++) {
789 bnxt_rx_bytes_pri_arr[i].string);
790 buf += ETH_GSTRING_LEN;
792 for (i = 0; i < 8; i++) {
794 bnxt_rx_pkts_pri_arr[i].string);
795 buf += ETH_GSTRING_LEN;
797 for (i = 0; i < 8; i++) {
799 bnxt_tx_bytes_pri_arr[i].string);
800 buf += ETH_GSTRING_LEN;
802 for (i = 0; i < 8; i++) {
804 bnxt_tx_pkts_pri_arr[i].string);
805 buf += ETH_GSTRING_LEN;
812 memcpy(buf, bp->test_info->string,
813 bp->num_tests * ETH_GSTRING_LEN);
816 netdev_err(bp->dev, "bnxt_get_strings invalid request %x\n",
822 static void bnxt_get_ringparam(struct net_device *dev,
823 struct ethtool_ringparam *ering,
824 struct kernel_ethtool_ringparam *kernel_ering,
825 struct netlink_ext_ack *extack)
827 struct bnxt *bp = netdev_priv(dev);
829 if (bp->flags & BNXT_FLAG_AGG_RINGS) {
830 ering->rx_max_pending = BNXT_MAX_RX_DESC_CNT_JUM_ENA;
831 ering->rx_jumbo_max_pending = BNXT_MAX_RX_JUM_DESC_CNT;
832 kernel_ering->tcp_data_split = ETHTOOL_TCP_DATA_SPLIT_ENABLED;
834 ering->rx_max_pending = BNXT_MAX_RX_DESC_CNT;
835 ering->rx_jumbo_max_pending = 0;
836 kernel_ering->tcp_data_split = ETHTOOL_TCP_DATA_SPLIT_DISABLED;
838 ering->tx_max_pending = BNXT_MAX_TX_DESC_CNT;
840 ering->rx_pending = bp->rx_ring_size;
841 ering->rx_jumbo_pending = bp->rx_agg_ring_size;
842 ering->tx_pending = bp->tx_ring_size;
845 static int bnxt_set_ringparam(struct net_device *dev,
846 struct ethtool_ringparam *ering,
847 struct kernel_ethtool_ringparam *kernel_ering,
848 struct netlink_ext_ack *extack)
850 struct bnxt *bp = netdev_priv(dev);
852 if ((ering->rx_pending > BNXT_MAX_RX_DESC_CNT) ||
853 (ering->tx_pending > BNXT_MAX_TX_DESC_CNT) ||
854 (ering->tx_pending < BNXT_MIN_TX_DESC_CNT))
857 if (netif_running(dev))
858 bnxt_close_nic(bp, false, false);
860 bp->rx_ring_size = ering->rx_pending;
861 bp->tx_ring_size = ering->tx_pending;
862 bnxt_set_ring_params(bp);
864 if (netif_running(dev))
865 return bnxt_open_nic(bp, false, false);
870 static void bnxt_get_channels(struct net_device *dev,
871 struct ethtool_channels *channel)
873 struct bnxt *bp = netdev_priv(dev);
874 struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
875 int max_rx_rings, max_tx_rings, tcs;
876 int max_tx_sch_inputs, tx_grps;
878 /* Get the most up-to-date max_tx_sch_inputs. */
879 if (netif_running(dev) && BNXT_NEW_RM(bp))
880 bnxt_hwrm_func_resc_qcaps(bp, false);
881 max_tx_sch_inputs = hw_resc->max_tx_sch_inputs;
883 bnxt_get_max_rings(bp, &max_rx_rings, &max_tx_rings, true);
884 if (max_tx_sch_inputs)
885 max_tx_rings = min_t(int, max_tx_rings, max_tx_sch_inputs);
888 tx_grps = max(tcs, 1);
889 if (bp->tx_nr_rings_xdp)
891 max_tx_rings /= tx_grps;
892 channel->max_combined = min_t(int, max_rx_rings, max_tx_rings);
894 if (bnxt_get_max_rings(bp, &max_rx_rings, &max_tx_rings, false)) {
898 if (max_tx_sch_inputs)
899 max_tx_rings = min_t(int, max_tx_rings, max_tx_sch_inputs);
904 channel->max_rx = max_rx_rings;
905 channel->max_tx = max_tx_rings;
906 channel->max_other = 0;
907 if (bp->flags & BNXT_FLAG_SHARED_RINGS) {
908 channel->combined_count = bp->rx_nr_rings;
909 if (BNXT_CHIP_TYPE_NITRO_A0(bp))
910 channel->combined_count--;
912 if (!BNXT_CHIP_TYPE_NITRO_A0(bp)) {
913 channel->rx_count = bp->rx_nr_rings;
914 channel->tx_count = bp->tx_nr_rings_per_tc;
919 static int bnxt_set_channels(struct net_device *dev,
920 struct ethtool_channels *channel)
922 struct bnxt *bp = netdev_priv(dev);
923 int req_tx_rings, req_rx_rings, tcs;
929 if (channel->other_count)
932 if (!channel->combined_count &&
933 (!channel->rx_count || !channel->tx_count))
936 if (channel->combined_count &&
937 (channel->rx_count || channel->tx_count))
940 if (BNXT_CHIP_TYPE_NITRO_A0(bp) && (channel->rx_count ||
944 if (channel->combined_count)
949 req_tx_rings = sh ? channel->combined_count : channel->tx_count;
950 req_rx_rings = sh ? channel->combined_count : channel->rx_count;
951 if (bp->tx_nr_rings_xdp) {
953 netdev_err(dev, "Only combined mode supported when XDP is enabled.\n");
956 tx_xdp = req_rx_rings;
958 rc = bnxt_check_rings(bp, req_tx_rings, req_rx_rings, sh, tcs, tx_xdp);
960 netdev_warn(dev, "Unable to allocate the requested rings\n");
964 if (bnxt_get_nr_rss_ctxs(bp, req_rx_rings) !=
965 bnxt_get_nr_rss_ctxs(bp, bp->rx_nr_rings) &&
966 netif_is_rxfh_configured(dev)) {
967 netdev_warn(dev, "RSS table size change required, RSS table entries must be default to proceed\n");
971 if (netif_running(dev)) {
973 /* TODO CHIMP_FW: Send message to all VF's
977 bnxt_close_nic(bp, true, false);
981 bp->flags |= BNXT_FLAG_SHARED_RINGS;
982 bp->rx_nr_rings = channel->combined_count;
983 bp->tx_nr_rings_per_tc = channel->combined_count;
985 bp->flags &= ~BNXT_FLAG_SHARED_RINGS;
986 bp->rx_nr_rings = channel->rx_count;
987 bp->tx_nr_rings_per_tc = channel->tx_count;
989 bp->tx_nr_rings_xdp = tx_xdp;
990 bp->tx_nr_rings = bp->tx_nr_rings_per_tc + tx_xdp;
992 bp->tx_nr_rings = bp->tx_nr_rings_per_tc * tcs + tx_xdp;
994 tx_cp = bnxt_num_tx_to_cp(bp, bp->tx_nr_rings);
995 bp->cp_nr_rings = sh ? max_t(int, tx_cp, bp->rx_nr_rings) :
996 tx_cp + bp->rx_nr_rings;
998 /* After changing number of rx channels, update NTUPLE feature. */
999 netdev_update_features(dev);
1000 if (netif_running(dev)) {
1001 rc = bnxt_open_nic(bp, true, false);
1002 if ((!rc) && BNXT_PF(bp)) {
1003 /* TODO CHIMP_FW: Send message to all VF's
1008 rc = bnxt_reserve_rings(bp, true);
1014 static u32 bnxt_get_all_fltr_ids_rcu(struct bnxt *bp, struct hlist_head tbl[],
1015 int tbl_size, u32 *ids, u32 start,
1022 for (i = 0; i < tbl_size; i++) {
1023 struct hlist_head *head;
1024 struct bnxt_filter_base *fltr;
1027 hlist_for_each_entry_rcu(fltr, head, hash) {
1029 test_bit(BNXT_FLTR_FW_DELETED, &fltr->state))
1031 ids[j++] = fltr->sw_id;
1039 static struct bnxt_filter_base *bnxt_get_one_fltr_rcu(struct bnxt *bp,
1040 struct hlist_head tbl[],
1041 int tbl_size, u32 id)
1045 for (i = 0; i < tbl_size; i++) {
1046 struct hlist_head *head;
1047 struct bnxt_filter_base *fltr;
1050 hlist_for_each_entry_rcu(fltr, head, hash) {
1051 if (fltr->flags && fltr->sw_id == id)
1058 static int bnxt_grxclsrlall(struct bnxt *bp, struct ethtool_rxnfc *cmd,
1061 cmd->data = bp->ntp_fltr_count;
1063 cmd->rule_cnt = bnxt_get_all_fltr_ids_rcu(bp, bp->ntp_fltr_hash_tbl,
1064 BNXT_NTP_FLTR_HASH_SIZE,
1065 rule_locs, 0, cmd->rule_cnt);
1071 static int bnxt_grxclsrule(struct bnxt *bp, struct ethtool_rxnfc *cmd)
1073 struct ethtool_rx_flow_spec *fs =
1074 (struct ethtool_rx_flow_spec *)&cmd->fs;
1075 struct bnxt_filter_base *fltr_base;
1076 struct bnxt_ntuple_filter *fltr;
1077 struct flow_keys *fkeys;
1080 if (fs->location >= BNXT_NTP_FLTR_MAX_FLTR)
1084 fltr_base = bnxt_get_one_fltr_rcu(bp, bp->ntp_fltr_hash_tbl,
1085 BNXT_NTP_FLTR_HASH_SIZE,
1091 fltr = container_of(fltr_base, struct bnxt_ntuple_filter, base);
1093 fkeys = &fltr->fkeys;
1094 if (fkeys->basic.n_proto == htons(ETH_P_IP)) {
1095 if (fkeys->basic.ip_proto == IPPROTO_TCP)
1096 fs->flow_type = TCP_V4_FLOW;
1097 else if (fkeys->basic.ip_proto == IPPROTO_UDP)
1098 fs->flow_type = UDP_V4_FLOW;
1102 if (fltr->ntuple_flags & BNXT_NTUPLE_MATCH_SRC_IP) {
1103 fs->h_u.tcp_ip4_spec.ip4src = fkeys->addrs.v4addrs.src;
1104 fs->m_u.tcp_ip4_spec.ip4src = cpu_to_be32(~0);
1106 if (fltr->ntuple_flags & BNXT_NTUPLE_MATCH_DST_IP) {
1107 fs->h_u.tcp_ip4_spec.ip4dst = fkeys->addrs.v4addrs.dst;
1108 fs->m_u.tcp_ip4_spec.ip4dst = cpu_to_be32(~0);
1110 if (fltr->ntuple_flags & BNXT_NTUPLE_MATCH_SRC_PORT) {
1111 fs->h_u.tcp_ip4_spec.psrc = fkeys->ports.src;
1112 fs->m_u.tcp_ip4_spec.psrc = cpu_to_be16(~0);
1114 if (fltr->ntuple_flags & BNXT_NTUPLE_MATCH_DST_PORT) {
1115 fs->h_u.tcp_ip4_spec.pdst = fkeys->ports.dst;
1116 fs->m_u.tcp_ip4_spec.pdst = cpu_to_be16(~0);
1119 if (fkeys->basic.ip_proto == IPPROTO_TCP)
1120 fs->flow_type = TCP_V6_FLOW;
1121 else if (fkeys->basic.ip_proto == IPPROTO_UDP)
1122 fs->flow_type = UDP_V6_FLOW;
1126 if (fltr->ntuple_flags & BNXT_NTUPLE_MATCH_SRC_IP) {
1127 *(struct in6_addr *)&fs->h_u.tcp_ip6_spec.ip6src[0] =
1128 fkeys->addrs.v6addrs.src;
1129 bnxt_fill_ipv6_mask(fs->m_u.tcp_ip6_spec.ip6src);
1131 if (fltr->ntuple_flags & BNXT_NTUPLE_MATCH_DST_IP) {
1132 *(struct in6_addr *)&fs->h_u.tcp_ip6_spec.ip6dst[0] =
1133 fkeys->addrs.v6addrs.dst;
1134 bnxt_fill_ipv6_mask(fs->m_u.tcp_ip6_spec.ip6dst);
1136 if (fltr->ntuple_flags & BNXT_NTUPLE_MATCH_SRC_PORT) {
1137 fs->h_u.tcp_ip6_spec.psrc = fkeys->ports.src;
1138 fs->m_u.tcp_ip6_spec.psrc = cpu_to_be16(~0);
1140 if (fltr->ntuple_flags & BNXT_NTUPLE_MATCH_DST_PORT) {
1141 fs->h_u.tcp_ip6_spec.pdst = fkeys->ports.dst;
1142 fs->m_u.tcp_ip6_spec.pdst = cpu_to_be16(~0);
1146 fs->ring_cookie = fltr->base.rxq;
1155 #define IPV4_ALL_MASK ((__force __be32)~0)
1156 #define L4_PORT_ALL_MASK ((__force __be16)~0)
1158 static bool ipv6_mask_is_full(__be32 mask[4])
1160 return (mask[0] & mask[1] & mask[2] & mask[3]) == IPV4_ALL_MASK;
1163 static bool ipv6_mask_is_zero(__be32 mask[4])
1165 return !(mask[0] | mask[1] | mask[2] | mask[3]);
1168 static int bnxt_add_ntuple_cls_rule(struct bnxt *bp,
1169 struct ethtool_rx_flow_spec *fs)
1171 u8 vf = ethtool_get_flow_spec_ring_vf(fs->ring_cookie);
1172 u32 ring = ethtool_get_flow_spec_ring(fs->ring_cookie);
1173 struct bnxt_ntuple_filter *new_fltr, *fltr;
1174 struct bnxt_l2_filter *l2_fltr;
1175 u32 flow_type = fs->flow_type;
1176 struct flow_keys *fkeys;
1183 if ((flow_type & (FLOW_MAC_EXT | FLOW_EXT)) || vf)
1186 new_fltr = kzalloc(sizeof(*new_fltr), GFP_KERNEL);
1190 l2_fltr = bp->vnic_info[0].l2_filters[0];
1191 atomic_inc(&l2_fltr->refcnt);
1192 new_fltr->l2_fltr = l2_fltr;
1193 fkeys = &new_fltr->fkeys;
1196 switch (flow_type) {
1199 struct ethtool_tcpip4_spec *ip_spec = &fs->h_u.tcp_ip4_spec;
1200 struct ethtool_tcpip4_spec *ip_mask = &fs->m_u.tcp_ip4_spec;
1202 fkeys->basic.ip_proto = IPPROTO_TCP;
1203 if (flow_type == UDP_V4_FLOW)
1204 fkeys->basic.ip_proto = IPPROTO_UDP;
1205 fkeys->basic.n_proto = htons(ETH_P_IP);
1207 if (ip_mask->ip4src == IPV4_ALL_MASK) {
1208 fkeys->addrs.v4addrs.src = ip_spec->ip4src;
1209 new_fltr->ntuple_flags |= BNXT_NTUPLE_MATCH_SRC_IP;
1210 } else if (ip_mask->ip4src) {
1213 if (ip_mask->ip4dst == IPV4_ALL_MASK) {
1214 fkeys->addrs.v4addrs.dst = ip_spec->ip4dst;
1215 new_fltr->ntuple_flags |= BNXT_NTUPLE_MATCH_DST_IP;
1216 } else if (ip_mask->ip4dst) {
1220 if (ip_mask->psrc == L4_PORT_ALL_MASK) {
1221 fkeys->ports.src = ip_spec->psrc;
1222 new_fltr->ntuple_flags |= BNXT_NTUPLE_MATCH_SRC_PORT;
1223 } else if (ip_mask->psrc) {
1226 if (ip_mask->pdst == L4_PORT_ALL_MASK) {
1227 fkeys->ports.dst = ip_spec->pdst;
1228 new_fltr->ntuple_flags |= BNXT_NTUPLE_MATCH_DST_PORT;
1229 } else if (ip_mask->pdst) {
1236 struct ethtool_tcpip6_spec *ip_spec = &fs->h_u.tcp_ip6_spec;
1237 struct ethtool_tcpip6_spec *ip_mask = &fs->m_u.tcp_ip6_spec;
1239 fkeys->basic.ip_proto = IPPROTO_TCP;
1240 if (flow_type == UDP_V6_FLOW)
1241 fkeys->basic.ip_proto = IPPROTO_UDP;
1242 fkeys->basic.n_proto = htons(ETH_P_IPV6);
1244 if (ipv6_mask_is_full(ip_mask->ip6src)) {
1245 fkeys->addrs.v6addrs.src =
1246 *(struct in6_addr *)&ip_spec->ip6src;
1247 new_fltr->ntuple_flags |= BNXT_NTUPLE_MATCH_SRC_IP;
1248 } else if (!ipv6_mask_is_zero(ip_mask->ip6src)) {
1251 if (ipv6_mask_is_full(ip_mask->ip6dst)) {
1252 fkeys->addrs.v6addrs.dst =
1253 *(struct in6_addr *)&ip_spec->ip6dst;
1254 new_fltr->ntuple_flags |= BNXT_NTUPLE_MATCH_DST_IP;
1255 } else if (!ipv6_mask_is_zero(ip_mask->ip6dst)) {
1259 if (ip_mask->psrc == L4_PORT_ALL_MASK) {
1260 fkeys->ports.src = ip_spec->psrc;
1261 new_fltr->ntuple_flags |= BNXT_NTUPLE_MATCH_SRC_PORT;
1262 } else if (ip_mask->psrc) {
1265 if (ip_mask->pdst == L4_PORT_ALL_MASK) {
1266 fkeys->ports.dst = ip_spec->pdst;
1267 new_fltr->ntuple_flags |= BNXT_NTUPLE_MATCH_DST_PORT;
1268 } else if (ip_mask->pdst) {
1277 if (!new_fltr->ntuple_flags)
1280 idx = bnxt_get_ntp_filter_idx(bp, fkeys, NULL);
1282 fltr = bnxt_lookup_ntp_filter_from_idx(bp, new_fltr, idx);
1290 new_fltr->base.rxq = ring;
1291 new_fltr->base.flags = BNXT_ACT_NO_AGING;
1292 __set_bit(BNXT_FLTR_VALID, &new_fltr->base.state);
1293 rc = bnxt_insert_ntp_filter(bp, new_fltr, idx);
1295 rc = bnxt_hwrm_cfa_ntuple_filter_alloc(bp, new_fltr);
1297 bnxt_del_ntp_filter(bp, new_fltr);
1300 fs->location = new_fltr->base.sw_id;
1305 atomic_dec(&l2_fltr->refcnt);
1310 static int bnxt_srxclsrlins(struct bnxt *bp, struct ethtool_rxnfc *cmd)
1312 struct ethtool_rx_flow_spec *fs = &cmd->fs;
1313 u32 ring, flow_type;
1317 if (!netif_running(bp->dev))
1319 if (!(bp->flags & BNXT_FLAG_RFS))
1321 if (fs->location != RX_CLS_LOC_ANY)
1324 ring = ethtool_get_flow_spec_ring(fs->ring_cookie);
1325 vf = ethtool_get_flow_spec_ring_vf(fs->ring_cookie);
1326 if (BNXT_VF(bp) && vf)
1328 if (BNXT_PF(bp) && vf > bp->pf.active_vfs)
1330 if (!vf && ring >= bp->rx_nr_rings)
1333 flow_type = fs->flow_type;
1334 if (flow_type & (FLOW_MAC_EXT | FLOW_RSS))
1336 flow_type &= ~FLOW_EXT;
1337 if (flow_type == ETHER_FLOW)
1340 rc = bnxt_add_ntuple_cls_rule(bp, fs);
1344 static int bnxt_srxclsrldel(struct bnxt *bp, struct ethtool_rxnfc *cmd)
1346 struct ethtool_rx_flow_spec *fs = &cmd->fs;
1347 struct bnxt_filter_base *fltr_base;
1348 struct bnxt_ntuple_filter *fltr;
1351 fltr_base = bnxt_get_one_fltr_rcu(bp, bp->ntp_fltr_hash_tbl,
1352 BNXT_NTP_FLTR_HASH_SIZE,
1359 fltr = container_of(fltr_base, struct bnxt_ntuple_filter, base);
1360 if (!(fltr->base.flags & BNXT_ACT_NO_AGING)) {
1365 bnxt_hwrm_cfa_ntuple_filter_free(bp, fltr);
1366 bnxt_del_ntp_filter(bp, fltr);
1370 static u64 get_ethtool_ipv4_rss(struct bnxt *bp)
1372 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4)
1373 return RXH_IP_SRC | RXH_IP_DST;
1377 static u64 get_ethtool_ipv6_rss(struct bnxt *bp)
1379 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6)
1380 return RXH_IP_SRC | RXH_IP_DST;
1384 static int bnxt_grxfh(struct bnxt *bp, struct ethtool_rxnfc *cmd)
1387 switch (cmd->flow_type) {
1389 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4)
1390 cmd->data |= RXH_IP_SRC | RXH_IP_DST |
1391 RXH_L4_B_0_1 | RXH_L4_B_2_3;
1392 cmd->data |= get_ethtool_ipv4_rss(bp);
1395 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4)
1396 cmd->data |= RXH_IP_SRC | RXH_IP_DST |
1397 RXH_L4_B_0_1 | RXH_L4_B_2_3;
1400 case AH_ESP_V4_FLOW:
1404 cmd->data |= get_ethtool_ipv4_rss(bp);
1408 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6)
1409 cmd->data |= RXH_IP_SRC | RXH_IP_DST |
1410 RXH_L4_B_0_1 | RXH_L4_B_2_3;
1411 cmd->data |= get_ethtool_ipv6_rss(bp);
1414 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6)
1415 cmd->data |= RXH_IP_SRC | RXH_IP_DST |
1416 RXH_L4_B_0_1 | RXH_L4_B_2_3;
1419 case AH_ESP_V6_FLOW:
1423 cmd->data |= get_ethtool_ipv6_rss(bp);
1429 #define RXH_4TUPLE (RXH_IP_SRC | RXH_IP_DST | RXH_L4_B_0_1 | RXH_L4_B_2_3)
1430 #define RXH_2TUPLE (RXH_IP_SRC | RXH_IP_DST)
1432 static int bnxt_srxfh(struct bnxt *bp, struct ethtool_rxnfc *cmd)
1434 u32 rss_hash_cfg = bp->rss_hash_cfg;
1437 if (cmd->data == RXH_4TUPLE)
1439 else if (cmd->data == RXH_2TUPLE)
1441 else if (!cmd->data)
1446 if (cmd->flow_type == TCP_V4_FLOW) {
1447 rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4;
1449 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4;
1450 } else if (cmd->flow_type == UDP_V4_FLOW) {
1451 if (tuple == 4 && !(bp->rss_cap & BNXT_RSS_CAP_UDP_RSS_CAP))
1453 rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4;
1455 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4;
1456 } else if (cmd->flow_type == TCP_V6_FLOW) {
1457 rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6;
1459 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6;
1460 } else if (cmd->flow_type == UDP_V6_FLOW) {
1461 if (tuple == 4 && !(bp->rss_cap & BNXT_RSS_CAP_UDP_RSS_CAP))
1463 rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6;
1465 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6;
1466 } else if (tuple == 4) {
1470 switch (cmd->flow_type) {
1474 case AH_ESP_V4_FLOW:
1479 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4;
1481 rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4;
1487 case AH_ESP_V6_FLOW:
1492 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6;
1494 rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6;
1498 if (bp->rss_hash_cfg == rss_hash_cfg)
1501 if (bp->rss_cap & BNXT_RSS_CAP_RSS_HASH_TYPE_DELTA)
1502 bp->rss_hash_delta = bp->rss_hash_cfg ^ rss_hash_cfg;
1503 bp->rss_hash_cfg = rss_hash_cfg;
1504 if (netif_running(bp->dev)) {
1505 bnxt_close_nic(bp, false, false);
1506 rc = bnxt_open_nic(bp, false, false);
1511 static int bnxt_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd,
1514 struct bnxt *bp = netdev_priv(dev);
1518 case ETHTOOL_GRXRINGS:
1519 cmd->data = bp->rx_nr_rings;
1522 case ETHTOOL_GRXCLSRLCNT:
1523 cmd->rule_cnt = bp->ntp_fltr_count;
1524 cmd->data = BNXT_NTP_FLTR_MAX_FLTR | RX_CLS_LOC_SPECIAL;
1527 case ETHTOOL_GRXCLSRLALL:
1528 rc = bnxt_grxclsrlall(bp, cmd, (u32 *)rule_locs);
1531 case ETHTOOL_GRXCLSRULE:
1532 rc = bnxt_grxclsrule(bp, cmd);
1536 rc = bnxt_grxfh(bp, cmd);
1547 static int bnxt_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd)
1549 struct bnxt *bp = netdev_priv(dev);
1554 rc = bnxt_srxfh(bp, cmd);
1557 case ETHTOOL_SRXCLSRLINS:
1558 rc = bnxt_srxclsrlins(bp, cmd);
1561 case ETHTOOL_SRXCLSRLDEL:
1562 rc = bnxt_srxclsrldel(bp, cmd);
1572 u32 bnxt_get_rxfh_indir_size(struct net_device *dev)
1574 struct bnxt *bp = netdev_priv(dev);
1576 if (bp->flags & BNXT_FLAG_CHIP_P5_PLUS)
1577 return bnxt_get_nr_rss_ctxs(bp, bp->rx_nr_rings) *
1578 BNXT_RSS_TABLE_ENTRIES_P5;
1579 return HW_HASH_INDEX_SIZE;
1582 static u32 bnxt_get_rxfh_key_size(struct net_device *dev)
1584 return HW_HASH_KEY_SIZE;
1587 static int bnxt_get_rxfh(struct net_device *dev,
1588 struct ethtool_rxfh_param *rxfh)
1590 struct bnxt *bp = netdev_priv(dev);
1591 struct bnxt_vnic_info *vnic;
1594 rxfh->hfunc = ETH_RSS_HASH_TOP;
1599 vnic = &bp->vnic_info[0];
1600 if (rxfh->indir && bp->rss_indir_tbl) {
1601 tbl_size = bnxt_get_rxfh_indir_size(dev);
1602 for (i = 0; i < tbl_size; i++)
1603 rxfh->indir[i] = bp->rss_indir_tbl[i];
1606 if (rxfh->key && vnic->rss_hash_key)
1607 memcpy(rxfh->key, vnic->rss_hash_key, HW_HASH_KEY_SIZE);
1612 static int bnxt_set_rxfh(struct net_device *dev,
1613 struct ethtool_rxfh_param *rxfh,
1614 struct netlink_ext_ack *extack)
1616 struct bnxt *bp = netdev_priv(dev);
1619 if (rxfh->hfunc && rxfh->hfunc != ETH_RSS_HASH_TOP)
1626 u32 i, pad, tbl_size = bnxt_get_rxfh_indir_size(dev);
1628 for (i = 0; i < tbl_size; i++)
1629 bp->rss_indir_tbl[i] = rxfh->indir[i];
1630 pad = bp->rss_indir_tbl_entries - tbl_size;
1632 memset(&bp->rss_indir_tbl[i], 0, pad * sizeof(u16));
1635 if (netif_running(bp->dev)) {
1636 bnxt_close_nic(bp, false, false);
1637 rc = bnxt_open_nic(bp, false, false);
1642 static void bnxt_get_drvinfo(struct net_device *dev,
1643 struct ethtool_drvinfo *info)
1645 struct bnxt *bp = netdev_priv(dev);
1647 strscpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver));
1648 strscpy(info->fw_version, bp->fw_ver_str, sizeof(info->fw_version));
1649 strscpy(info->bus_info, pci_name(bp->pdev), sizeof(info->bus_info));
1650 info->n_stats = bnxt_get_num_stats(bp);
1651 info->testinfo_len = bp->num_tests;
1652 /* TODO CHIMP_FW: eeprom dump details */
1653 info->eedump_len = 0;
1654 /* TODO CHIMP FW: reg dump details */
1655 info->regdump_len = 0;
1658 static int bnxt_get_regs_len(struct net_device *dev)
1660 struct bnxt *bp = netdev_priv(dev);
1666 reg_len = BNXT_PXP_REG_LEN;
1668 if (bp->fw_cap & BNXT_FW_CAP_PCIE_STATS_SUPPORTED)
1669 reg_len += sizeof(struct pcie_ctx_hw_stats);
1674 static void bnxt_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1677 struct pcie_ctx_hw_stats *hw_pcie_stats;
1678 struct hwrm_pcie_qstats_input *req;
1679 struct bnxt *bp = netdev_priv(dev);
1680 dma_addr_t hw_pcie_stats_addr;
1684 bnxt_dbg_hwrm_rd_reg(bp, 0, BNXT_PXP_REG_LEN / 4, _p);
1686 if (!(bp->fw_cap & BNXT_FW_CAP_PCIE_STATS_SUPPORTED))
1689 if (hwrm_req_init(bp, req, HWRM_PCIE_QSTATS))
1692 hw_pcie_stats = hwrm_req_dma_slice(bp, req, sizeof(*hw_pcie_stats),
1693 &hw_pcie_stats_addr);
1694 if (!hw_pcie_stats) {
1695 hwrm_req_drop(bp, req);
1700 hwrm_req_hold(bp, req); /* hold on to slice */
1701 req->pcie_stat_size = cpu_to_le16(sizeof(*hw_pcie_stats));
1702 req->pcie_stat_host_addr = cpu_to_le64(hw_pcie_stats_addr);
1703 rc = hwrm_req_send(bp, req);
1705 __le64 *src = (__le64 *)hw_pcie_stats;
1706 u64 *dst = (u64 *)(_p + BNXT_PXP_REG_LEN);
1709 for (i = 0; i < sizeof(*hw_pcie_stats) / sizeof(__le64); i++)
1710 dst[i] = le64_to_cpu(src[i]);
1712 hwrm_req_drop(bp, req);
1715 static void bnxt_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1717 struct bnxt *bp = netdev_priv(dev);
1721 memset(&wol->sopass, 0, sizeof(wol->sopass));
1722 if (bp->flags & BNXT_FLAG_WOL_CAP) {
1723 wol->supported = WAKE_MAGIC;
1725 wol->wolopts = WAKE_MAGIC;
1729 static int bnxt_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1731 struct bnxt *bp = netdev_priv(dev);
1733 if (wol->wolopts & ~WAKE_MAGIC)
1736 if (wol->wolopts & WAKE_MAGIC) {
1737 if (!(bp->flags & BNXT_FLAG_WOL_CAP))
1740 if (bnxt_hwrm_alloc_wol_fltr(bp))
1746 if (bnxt_hwrm_free_wol_fltr(bp))
1754 u32 _bnxt_fw_to_ethtool_adv_spds(u16 fw_speeds, u8 fw_pause)
1758 /* TODO: support 25GB, 40GB, 50GB with different cable type */
1759 /* set the advertised speeds */
1760 if (fw_speeds & BNXT_LINK_SPEED_MSK_100MB)
1761 speed_mask |= ADVERTISED_100baseT_Full;
1762 if (fw_speeds & BNXT_LINK_SPEED_MSK_1GB)
1763 speed_mask |= ADVERTISED_1000baseT_Full;
1764 if (fw_speeds & BNXT_LINK_SPEED_MSK_2_5GB)
1765 speed_mask |= ADVERTISED_2500baseX_Full;
1766 if (fw_speeds & BNXT_LINK_SPEED_MSK_10GB)
1767 speed_mask |= ADVERTISED_10000baseT_Full;
1768 if (fw_speeds & BNXT_LINK_SPEED_MSK_40GB)
1769 speed_mask |= ADVERTISED_40000baseCR4_Full;
1771 if ((fw_pause & BNXT_LINK_PAUSE_BOTH) == BNXT_LINK_PAUSE_BOTH)
1772 speed_mask |= ADVERTISED_Pause;
1773 else if (fw_pause & BNXT_LINK_PAUSE_TX)
1774 speed_mask |= ADVERTISED_Asym_Pause;
1775 else if (fw_pause & BNXT_LINK_PAUSE_RX)
1776 speed_mask |= ADVERTISED_Pause | ADVERTISED_Asym_Pause;
1781 enum bnxt_media_type {
1782 BNXT_MEDIA_UNKNOWN = 0,
1786 BNXT_MEDIA_LR_ER_FR,
1793 static const enum bnxt_media_type bnxt_phy_types[] = {
1794 [PORT_PHY_QCFG_RESP_PHY_TYPE_BASECR] = BNXT_MEDIA_CR,
1795 [PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR4] = BNXT_MEDIA_KR,
1796 [PORT_PHY_QCFG_RESP_PHY_TYPE_BASELR] = BNXT_MEDIA_LR_ER_FR,
1797 [PORT_PHY_QCFG_RESP_PHY_TYPE_BASESR] = BNXT_MEDIA_SR,
1798 [PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR2] = BNXT_MEDIA_KR,
1799 [PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKX] = BNXT_MEDIA_KX,
1800 [PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR] = BNXT_MEDIA_KR,
1801 [PORT_PHY_QCFG_RESP_PHY_TYPE_BASET] = BNXT_MEDIA_TP,
1802 [PORT_PHY_QCFG_RESP_PHY_TYPE_BASETE] = BNXT_MEDIA_TP,
1803 [PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASECR_CA_L] = BNXT_MEDIA_CR,
1804 [PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASECR_CA_S] = BNXT_MEDIA_CR,
1805 [PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASECR_CA_N] = BNXT_MEDIA_CR,
1806 [PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASESR] = BNXT_MEDIA_SR,
1807 [PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASECR4] = BNXT_MEDIA_CR,
1808 [PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASESR4] = BNXT_MEDIA_SR,
1809 [PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASELR4] = BNXT_MEDIA_LR_ER_FR,
1810 [PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASEER4] = BNXT_MEDIA_LR_ER_FR,
1811 [PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASESR10] = BNXT_MEDIA_SR,
1812 [PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASECR4] = BNXT_MEDIA_CR,
1813 [PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASESR4] = BNXT_MEDIA_SR,
1814 [PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASELR4] = BNXT_MEDIA_LR_ER_FR,
1815 [PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASEER4] = BNXT_MEDIA_LR_ER_FR,
1816 [PORT_PHY_QCFG_RESP_PHY_TYPE_40G_ACTIVE_CABLE] = BNXT_MEDIA_SR,
1817 [PORT_PHY_QCFG_RESP_PHY_TYPE_1G_BASET] = BNXT_MEDIA_TP,
1818 [PORT_PHY_QCFG_RESP_PHY_TYPE_1G_BASESX] = BNXT_MEDIA_X,
1819 [PORT_PHY_QCFG_RESP_PHY_TYPE_1G_BASECX] = BNXT_MEDIA_X,
1820 [PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASECR4] = BNXT_MEDIA_CR,
1821 [PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASESR4] = BNXT_MEDIA_SR,
1822 [PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASELR4] = BNXT_MEDIA_LR_ER_FR,
1823 [PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASEER4] = BNXT_MEDIA_LR_ER_FR,
1824 [PORT_PHY_QCFG_RESP_PHY_TYPE_50G_BASECR] = BNXT_MEDIA_CR,
1825 [PORT_PHY_QCFG_RESP_PHY_TYPE_50G_BASESR] = BNXT_MEDIA_SR,
1826 [PORT_PHY_QCFG_RESP_PHY_TYPE_50G_BASELR] = BNXT_MEDIA_LR_ER_FR,
1827 [PORT_PHY_QCFG_RESP_PHY_TYPE_50G_BASEER] = BNXT_MEDIA_LR_ER_FR,
1828 [PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASECR2] = BNXT_MEDIA_CR,
1829 [PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASESR2] = BNXT_MEDIA_SR,
1830 [PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASELR2] = BNXT_MEDIA_LR_ER_FR,
1831 [PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASEER2] = BNXT_MEDIA_LR_ER_FR,
1832 [PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASECR] = BNXT_MEDIA_CR,
1833 [PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASESR] = BNXT_MEDIA_SR,
1834 [PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASELR] = BNXT_MEDIA_LR_ER_FR,
1835 [PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASEER] = BNXT_MEDIA_LR_ER_FR,
1836 [PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASECR2] = BNXT_MEDIA_CR,
1837 [PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASESR2] = BNXT_MEDIA_SR,
1838 [PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASELR2] = BNXT_MEDIA_LR_ER_FR,
1839 [PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASEER2] = BNXT_MEDIA_LR_ER_FR,
1840 [PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASECR8] = BNXT_MEDIA_CR,
1841 [PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASESR8] = BNXT_MEDIA_SR,
1842 [PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASELR8] = BNXT_MEDIA_LR_ER_FR,
1843 [PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASEER8] = BNXT_MEDIA_LR_ER_FR,
1844 [PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASECR4] = BNXT_MEDIA_CR,
1845 [PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASESR4] = BNXT_MEDIA_SR,
1846 [PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASELR4] = BNXT_MEDIA_LR_ER_FR,
1847 [PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASEER4] = BNXT_MEDIA_LR_ER_FR,
1850 static enum bnxt_media_type
1851 bnxt_get_media(struct bnxt_link_info *link_info)
1853 switch (link_info->media_type) {
1854 case PORT_PHY_QCFG_RESP_MEDIA_TYPE_TP:
1855 return BNXT_MEDIA_TP;
1856 case PORT_PHY_QCFG_RESP_MEDIA_TYPE_DAC:
1857 return BNXT_MEDIA_CR;
1859 if (link_info->phy_type < ARRAY_SIZE(bnxt_phy_types))
1860 return bnxt_phy_types[link_info->phy_type];
1861 return BNXT_MEDIA_UNKNOWN;
1865 enum bnxt_link_speed_indices {
1866 BNXT_LINK_SPEED_UNKNOWN = 0,
1867 BNXT_LINK_SPEED_100MB_IDX,
1868 BNXT_LINK_SPEED_1GB_IDX,
1869 BNXT_LINK_SPEED_10GB_IDX,
1870 BNXT_LINK_SPEED_25GB_IDX,
1871 BNXT_LINK_SPEED_40GB_IDX,
1872 BNXT_LINK_SPEED_50GB_IDX,
1873 BNXT_LINK_SPEED_100GB_IDX,
1874 BNXT_LINK_SPEED_200GB_IDX,
1875 BNXT_LINK_SPEED_400GB_IDX,
1876 __BNXT_LINK_SPEED_END
1879 static enum bnxt_link_speed_indices bnxt_fw_speed_idx(u16 speed)
1882 case BNXT_LINK_SPEED_100MB: return BNXT_LINK_SPEED_100MB_IDX;
1883 case BNXT_LINK_SPEED_1GB: return BNXT_LINK_SPEED_1GB_IDX;
1884 case BNXT_LINK_SPEED_10GB: return BNXT_LINK_SPEED_10GB_IDX;
1885 case BNXT_LINK_SPEED_25GB: return BNXT_LINK_SPEED_25GB_IDX;
1886 case BNXT_LINK_SPEED_40GB: return BNXT_LINK_SPEED_40GB_IDX;
1887 case BNXT_LINK_SPEED_50GB:
1888 case BNXT_LINK_SPEED_50GB_PAM4:
1889 return BNXT_LINK_SPEED_50GB_IDX;
1890 case BNXT_LINK_SPEED_100GB:
1891 case BNXT_LINK_SPEED_100GB_PAM4:
1892 case BNXT_LINK_SPEED_100GB_PAM4_112:
1893 return BNXT_LINK_SPEED_100GB_IDX;
1894 case BNXT_LINK_SPEED_200GB:
1895 case BNXT_LINK_SPEED_200GB_PAM4:
1896 case BNXT_LINK_SPEED_200GB_PAM4_112:
1897 return BNXT_LINK_SPEED_200GB_IDX;
1898 case BNXT_LINK_SPEED_400GB:
1899 case BNXT_LINK_SPEED_400GB_PAM4:
1900 case BNXT_LINK_SPEED_400GB_PAM4_112:
1901 return BNXT_LINK_SPEED_400GB_IDX;
1902 default: return BNXT_LINK_SPEED_UNKNOWN;
1906 static const enum ethtool_link_mode_bit_indices
1907 bnxt_link_modes[__BNXT_LINK_SPEED_END][BNXT_SIG_MODE_MAX][__BNXT_MEDIA_END] = {
1908 [BNXT_LINK_SPEED_100MB_IDX] = {
1910 [BNXT_MEDIA_TP] = ETHTOOL_LINK_MODE_100baseT_Full_BIT,
1913 [BNXT_LINK_SPEED_1GB_IDX] = {
1915 [BNXT_MEDIA_TP] = ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
1916 /* historically baseT, but DAC is more correctly baseX */
1917 [BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_1000baseX_Full_BIT,
1918 [BNXT_MEDIA_KX] = ETHTOOL_LINK_MODE_1000baseKX_Full_BIT,
1919 [BNXT_MEDIA_X] = ETHTOOL_LINK_MODE_1000baseX_Full_BIT,
1920 [BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_1000baseKX_Full_BIT,
1923 [BNXT_LINK_SPEED_10GB_IDX] = {
1925 [BNXT_MEDIA_TP] = ETHTOOL_LINK_MODE_10000baseT_Full_BIT,
1926 [BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_10000baseCR_Full_BIT,
1927 [BNXT_MEDIA_SR] = ETHTOOL_LINK_MODE_10000baseSR_Full_BIT,
1928 [BNXT_MEDIA_LR_ER_FR] = ETHTOOL_LINK_MODE_10000baseLR_Full_BIT,
1929 [BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_10000baseKR_Full_BIT,
1930 [BNXT_MEDIA_KX] = ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT,
1933 [BNXT_LINK_SPEED_25GB_IDX] = {
1935 [BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_25000baseCR_Full_BIT,
1936 [BNXT_MEDIA_SR] = ETHTOOL_LINK_MODE_25000baseSR_Full_BIT,
1937 [BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_25000baseKR_Full_BIT,
1940 [BNXT_LINK_SPEED_40GB_IDX] = {
1942 [BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT,
1943 [BNXT_MEDIA_SR] = ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT,
1944 [BNXT_MEDIA_LR_ER_FR] = ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT,
1945 [BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT,
1948 [BNXT_LINK_SPEED_50GB_IDX] = {
1949 [BNXT_SIG_MODE_NRZ] = {
1950 [BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT,
1951 [BNXT_MEDIA_SR] = ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT,
1952 [BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT,
1954 [BNXT_SIG_MODE_PAM4] = {
1955 [BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_50000baseCR_Full_BIT,
1956 [BNXT_MEDIA_SR] = ETHTOOL_LINK_MODE_50000baseSR_Full_BIT,
1957 [BNXT_MEDIA_LR_ER_FR] = ETHTOOL_LINK_MODE_50000baseLR_ER_FR_Full_BIT,
1958 [BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_50000baseKR_Full_BIT,
1961 [BNXT_LINK_SPEED_100GB_IDX] = {
1962 [BNXT_SIG_MODE_NRZ] = {
1963 [BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT,
1964 [BNXT_MEDIA_SR] = ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT,
1965 [BNXT_MEDIA_LR_ER_FR] = ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT,
1966 [BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT,
1968 [BNXT_SIG_MODE_PAM4] = {
1969 [BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_100000baseCR2_Full_BIT,
1970 [BNXT_MEDIA_SR] = ETHTOOL_LINK_MODE_100000baseSR2_Full_BIT,
1971 [BNXT_MEDIA_LR_ER_FR] = ETHTOOL_LINK_MODE_100000baseLR2_ER2_FR2_Full_BIT,
1972 [BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_100000baseKR2_Full_BIT,
1974 [BNXT_SIG_MODE_PAM4_112] = {
1975 [BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_100000baseCR_Full_BIT,
1976 [BNXT_MEDIA_SR] = ETHTOOL_LINK_MODE_100000baseSR_Full_BIT,
1977 [BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_100000baseKR_Full_BIT,
1978 [BNXT_MEDIA_LR_ER_FR] = ETHTOOL_LINK_MODE_100000baseLR_ER_FR_Full_BIT,
1981 [BNXT_LINK_SPEED_200GB_IDX] = {
1982 [BNXT_SIG_MODE_PAM4] = {
1983 [BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_200000baseCR4_Full_BIT,
1984 [BNXT_MEDIA_SR] = ETHTOOL_LINK_MODE_200000baseSR4_Full_BIT,
1985 [BNXT_MEDIA_LR_ER_FR] = ETHTOOL_LINK_MODE_200000baseLR4_ER4_FR4_Full_BIT,
1986 [BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_200000baseKR4_Full_BIT,
1988 [BNXT_SIG_MODE_PAM4_112] = {
1989 [BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_200000baseCR2_Full_BIT,
1990 [BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_200000baseKR2_Full_BIT,
1991 [BNXT_MEDIA_SR] = ETHTOOL_LINK_MODE_200000baseSR2_Full_BIT,
1992 [BNXT_MEDIA_LR_ER_FR] = ETHTOOL_LINK_MODE_200000baseLR2_ER2_FR2_Full_BIT,
1995 [BNXT_LINK_SPEED_400GB_IDX] = {
1996 [BNXT_SIG_MODE_PAM4] = {
1997 [BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_400000baseCR8_Full_BIT,
1998 [BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_400000baseKR8_Full_BIT,
1999 [BNXT_MEDIA_SR] = ETHTOOL_LINK_MODE_400000baseSR8_Full_BIT,
2000 [BNXT_MEDIA_LR_ER_FR] = ETHTOOL_LINK_MODE_400000baseLR8_ER8_FR8_Full_BIT,
2002 [BNXT_SIG_MODE_PAM4_112] = {
2003 [BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_400000baseCR4_Full_BIT,
2004 [BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_400000baseKR4_Full_BIT,
2005 [BNXT_MEDIA_SR] = ETHTOOL_LINK_MODE_400000baseSR4_Full_BIT,
2006 [BNXT_MEDIA_LR_ER_FR] = ETHTOOL_LINK_MODE_400000baseLR4_ER4_FR4_Full_BIT,
2011 #define BNXT_LINK_MODE_UNKNOWN -1
2013 static enum ethtool_link_mode_bit_indices
2014 bnxt_get_link_mode(struct bnxt_link_info *link_info)
2016 enum ethtool_link_mode_bit_indices link_mode;
2017 enum bnxt_link_speed_indices speed;
2018 enum bnxt_media_type media;
2021 if (link_info->phy_link_status != BNXT_LINK_LINK)
2022 return BNXT_LINK_MODE_UNKNOWN;
2024 media = bnxt_get_media(link_info);
2025 if (BNXT_AUTO_MODE(link_info->auto_mode)) {
2026 speed = bnxt_fw_speed_idx(link_info->link_speed);
2027 sig_mode = link_info->active_fec_sig_mode &
2028 PORT_PHY_QCFG_RESP_SIGNAL_MODE_MASK;
2030 speed = bnxt_fw_speed_idx(link_info->req_link_speed);
2031 sig_mode = link_info->req_signal_mode;
2033 if (sig_mode >= BNXT_SIG_MODE_MAX)
2034 return BNXT_LINK_MODE_UNKNOWN;
2036 /* Note ETHTOOL_LINK_MODE_10baseT_Half_BIT == 0 is a legal Linux
2037 * link mode, but since no such devices exist, the zeroes in the
2038 * map can be conveniently used to represent unknown link modes.
2040 link_mode = bnxt_link_modes[speed][sig_mode][media];
2042 return BNXT_LINK_MODE_UNKNOWN;
2044 switch (link_mode) {
2045 case ETHTOOL_LINK_MODE_100baseT_Full_BIT:
2046 if (~link_info->duplex & BNXT_LINK_DUPLEX_FULL)
2047 link_mode = ETHTOOL_LINK_MODE_100baseT_Half_BIT;
2049 case ETHTOOL_LINK_MODE_1000baseT_Full_BIT:
2050 if (~link_info->duplex & BNXT_LINK_DUPLEX_FULL)
2051 link_mode = ETHTOOL_LINK_MODE_1000baseT_Half_BIT;
2060 static void bnxt_get_ethtool_modes(struct bnxt_link_info *link_info,
2061 struct ethtool_link_ksettings *lk_ksettings)
2063 struct bnxt *bp = container_of(link_info, struct bnxt, link_info);
2065 if (!(bp->phy_flags & BNXT_PHY_FL_NO_PAUSE)) {
2066 linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT,
2067 lk_ksettings->link_modes.supported);
2068 linkmode_set_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT,
2069 lk_ksettings->link_modes.supported);
2072 if (link_info->support_auto_speeds || link_info->support_auto_speeds2 ||
2073 link_info->support_pam4_auto_speeds)
2074 linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT,
2075 lk_ksettings->link_modes.supported);
2077 if (~link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL)
2080 if (link_info->auto_pause_setting & BNXT_LINK_PAUSE_RX)
2081 linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT,
2082 lk_ksettings->link_modes.advertising);
2083 if (hweight8(link_info->auto_pause_setting & BNXT_LINK_PAUSE_BOTH) == 1)
2084 linkmode_set_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT,
2085 lk_ksettings->link_modes.advertising);
2086 if (link_info->lp_pause & BNXT_LINK_PAUSE_RX)
2087 linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT,
2088 lk_ksettings->link_modes.lp_advertising);
2089 if (hweight8(link_info->lp_pause & BNXT_LINK_PAUSE_BOTH) == 1)
2090 linkmode_set_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT,
2091 lk_ksettings->link_modes.lp_advertising);
2094 static const u16 bnxt_nrz_speed_masks[] = {
2095 [BNXT_LINK_SPEED_100MB_IDX] = BNXT_LINK_SPEED_MSK_100MB,
2096 [BNXT_LINK_SPEED_1GB_IDX] = BNXT_LINK_SPEED_MSK_1GB,
2097 [BNXT_LINK_SPEED_10GB_IDX] = BNXT_LINK_SPEED_MSK_10GB,
2098 [BNXT_LINK_SPEED_25GB_IDX] = BNXT_LINK_SPEED_MSK_25GB,
2099 [BNXT_LINK_SPEED_40GB_IDX] = BNXT_LINK_SPEED_MSK_40GB,
2100 [BNXT_LINK_SPEED_50GB_IDX] = BNXT_LINK_SPEED_MSK_50GB,
2101 [BNXT_LINK_SPEED_100GB_IDX] = BNXT_LINK_SPEED_MSK_100GB,
2102 [__BNXT_LINK_SPEED_END - 1] = 0 /* make any legal speed a valid index */
2105 static const u16 bnxt_pam4_speed_masks[] = {
2106 [BNXT_LINK_SPEED_50GB_IDX] = BNXT_LINK_PAM4_SPEED_MSK_50GB,
2107 [BNXT_LINK_SPEED_100GB_IDX] = BNXT_LINK_PAM4_SPEED_MSK_100GB,
2108 [BNXT_LINK_SPEED_200GB_IDX] = BNXT_LINK_PAM4_SPEED_MSK_200GB,
2109 [__BNXT_LINK_SPEED_END - 1] = 0 /* make any legal speed a valid index */
2112 static const u16 bnxt_nrz_speeds2_masks[] = {
2113 [BNXT_LINK_SPEED_1GB_IDX] = BNXT_LINK_SPEEDS2_MSK_1GB,
2114 [BNXT_LINK_SPEED_10GB_IDX] = BNXT_LINK_SPEEDS2_MSK_10GB,
2115 [BNXT_LINK_SPEED_25GB_IDX] = BNXT_LINK_SPEEDS2_MSK_25GB,
2116 [BNXT_LINK_SPEED_40GB_IDX] = BNXT_LINK_SPEEDS2_MSK_40GB,
2117 [BNXT_LINK_SPEED_50GB_IDX] = BNXT_LINK_SPEEDS2_MSK_50GB,
2118 [BNXT_LINK_SPEED_100GB_IDX] = BNXT_LINK_SPEEDS2_MSK_100GB,
2119 [__BNXT_LINK_SPEED_END - 1] = 0 /* make any legal speed a valid index */
2122 static const u16 bnxt_pam4_speeds2_masks[] = {
2123 [BNXT_LINK_SPEED_50GB_IDX] = BNXT_LINK_SPEEDS2_MSK_50GB_PAM4,
2124 [BNXT_LINK_SPEED_100GB_IDX] = BNXT_LINK_SPEEDS2_MSK_100GB_PAM4,
2125 [BNXT_LINK_SPEED_200GB_IDX] = BNXT_LINK_SPEEDS2_MSK_200GB_PAM4,
2126 [BNXT_LINK_SPEED_400GB_IDX] = BNXT_LINK_SPEEDS2_MSK_400GB_PAM4,
2129 static const u16 bnxt_pam4_112_speeds2_masks[] = {
2130 [BNXT_LINK_SPEED_100GB_IDX] = BNXT_LINK_SPEEDS2_MSK_100GB_PAM4_112,
2131 [BNXT_LINK_SPEED_200GB_IDX] = BNXT_LINK_SPEEDS2_MSK_200GB_PAM4_112,
2132 [BNXT_LINK_SPEED_400GB_IDX] = BNXT_LINK_SPEEDS2_MSK_400GB_PAM4_112,
2135 static enum bnxt_link_speed_indices
2136 bnxt_encoding_speed_idx(u8 sig_mode, u16 phy_flags, u16 speed_msk)
2142 case BNXT_SIG_MODE_NRZ:
2143 if (phy_flags & BNXT_PHY_FL_SPEEDS2) {
2144 speeds = bnxt_nrz_speeds2_masks;
2145 len = ARRAY_SIZE(bnxt_nrz_speeds2_masks);
2147 speeds = bnxt_nrz_speed_masks;
2148 len = ARRAY_SIZE(bnxt_nrz_speed_masks);
2151 case BNXT_SIG_MODE_PAM4:
2152 if (phy_flags & BNXT_PHY_FL_SPEEDS2) {
2153 speeds = bnxt_pam4_speeds2_masks;
2154 len = ARRAY_SIZE(bnxt_pam4_speeds2_masks);
2156 speeds = bnxt_pam4_speed_masks;
2157 len = ARRAY_SIZE(bnxt_pam4_speed_masks);
2160 case BNXT_SIG_MODE_PAM4_112:
2161 speeds = bnxt_pam4_112_speeds2_masks;
2162 len = ARRAY_SIZE(bnxt_pam4_112_speeds2_masks);
2165 return BNXT_LINK_SPEED_UNKNOWN;
2168 for (idx = 0; idx < len; idx++) {
2169 if (speeds[idx] == speed_msk)
2173 return BNXT_LINK_SPEED_UNKNOWN;
2176 #define BNXT_FW_SPEED_MSK_BITS 16
2179 __bnxt_get_ethtool_speeds(unsigned long fw_mask, enum bnxt_media_type media,
2180 u8 sig_mode, u16 phy_flags, unsigned long *et_mask)
2182 enum ethtool_link_mode_bit_indices link_mode;
2183 enum bnxt_link_speed_indices speed;
2186 for_each_set_bit(bit, &fw_mask, BNXT_FW_SPEED_MSK_BITS) {
2187 speed = bnxt_encoding_speed_idx(sig_mode, phy_flags, 1 << bit);
2191 link_mode = bnxt_link_modes[speed][sig_mode][media];
2195 linkmode_set_bit(link_mode, et_mask);
2200 bnxt_get_ethtool_speeds(unsigned long fw_mask, enum bnxt_media_type media,
2201 u8 sig_mode, u16 phy_flags, unsigned long *et_mask)
2204 __bnxt_get_ethtool_speeds(fw_mask, media, sig_mode, phy_flags,
2209 /* list speeds for all media if unknown */
2210 for (media = 1; media < __BNXT_MEDIA_END; media++)
2211 __bnxt_get_ethtool_speeds(fw_mask, media, sig_mode, phy_flags,
2216 bnxt_get_all_ethtool_support_speeds(struct bnxt_link_info *link_info,
2217 enum bnxt_media_type media,
2218 struct ethtool_link_ksettings *lk_ksettings)
2220 struct bnxt *bp = container_of(link_info, struct bnxt, link_info);
2221 u16 sp_nrz, sp_pam4, sp_pam4_112 = 0;
2222 u16 phy_flags = bp->phy_flags;
2224 if (phy_flags & BNXT_PHY_FL_SPEEDS2) {
2225 sp_nrz = link_info->support_speeds2;
2226 sp_pam4 = link_info->support_speeds2;
2227 sp_pam4_112 = link_info->support_speeds2;
2229 sp_nrz = link_info->support_speeds;
2230 sp_pam4 = link_info->support_pam4_speeds;
2232 bnxt_get_ethtool_speeds(sp_nrz, media, BNXT_SIG_MODE_NRZ, phy_flags,
2233 lk_ksettings->link_modes.supported);
2234 bnxt_get_ethtool_speeds(sp_pam4, media, BNXT_SIG_MODE_PAM4, phy_flags,
2235 lk_ksettings->link_modes.supported);
2236 bnxt_get_ethtool_speeds(sp_pam4_112, media, BNXT_SIG_MODE_PAM4_112,
2237 phy_flags, lk_ksettings->link_modes.supported);
2241 bnxt_get_all_ethtool_adv_speeds(struct bnxt_link_info *link_info,
2242 enum bnxt_media_type media,
2243 struct ethtool_link_ksettings *lk_ksettings)
2245 struct bnxt *bp = container_of(link_info, struct bnxt, link_info);
2246 u16 sp_nrz, sp_pam4, sp_pam4_112 = 0;
2247 u16 phy_flags = bp->phy_flags;
2249 sp_nrz = link_info->advertising;
2250 if (phy_flags & BNXT_PHY_FL_SPEEDS2) {
2251 sp_pam4 = link_info->advertising;
2252 sp_pam4_112 = link_info->advertising;
2254 sp_pam4 = link_info->advertising_pam4;
2256 bnxt_get_ethtool_speeds(sp_nrz, media, BNXT_SIG_MODE_NRZ, phy_flags,
2257 lk_ksettings->link_modes.advertising);
2258 bnxt_get_ethtool_speeds(sp_pam4, media, BNXT_SIG_MODE_PAM4, phy_flags,
2259 lk_ksettings->link_modes.advertising);
2260 bnxt_get_ethtool_speeds(sp_pam4_112, media, BNXT_SIG_MODE_PAM4_112,
2261 phy_flags, lk_ksettings->link_modes.advertising);
2265 bnxt_get_all_ethtool_lp_speeds(struct bnxt_link_info *link_info,
2266 enum bnxt_media_type media,
2267 struct ethtool_link_ksettings *lk_ksettings)
2269 struct bnxt *bp = container_of(link_info, struct bnxt, link_info);
2270 u16 phy_flags = bp->phy_flags;
2272 bnxt_get_ethtool_speeds(link_info->lp_auto_link_speeds, media,
2273 BNXT_SIG_MODE_NRZ, phy_flags,
2274 lk_ksettings->link_modes.lp_advertising);
2275 bnxt_get_ethtool_speeds(link_info->lp_auto_pam4_link_speeds, media,
2276 BNXT_SIG_MODE_PAM4, phy_flags,
2277 lk_ksettings->link_modes.lp_advertising);
2280 static void bnxt_update_speed(u32 *delta, bool installed_media, u16 *speeds,
2281 u16 speed_msk, const unsigned long *et_mask,
2282 enum ethtool_link_mode_bit_indices mode)
2284 bool mode_desired = linkmode_test_bit(mode, et_mask);
2289 /* enabled speeds for installed media should override */
2290 if (installed_media && mode_desired) {
2291 *speeds |= speed_msk;
2292 *delta |= speed_msk;
2296 /* many to one mapping, only allow one change per fw_speed bit */
2297 if (!(*delta & speed_msk) && (mode_desired == !(*speeds & speed_msk))) {
2298 *speeds ^= speed_msk;
2299 *delta |= speed_msk;
2303 static void bnxt_set_ethtool_speeds(struct bnxt_link_info *link_info,
2304 const unsigned long *et_mask)
2306 struct bnxt *bp = container_of(link_info, struct bnxt, link_info);
2307 u16 const *sp_msks, *sp_pam4_msks, *sp_pam4_112_msks;
2308 enum bnxt_media_type media = bnxt_get_media(link_info);
2309 u16 *adv, *adv_pam4, *adv_pam4_112 = NULL;
2310 u32 delta_pam4_112 = 0;
2315 adv = &link_info->advertising;
2316 if (bp->phy_flags & BNXT_PHY_FL_SPEEDS2) {
2317 adv_pam4 = &link_info->advertising;
2318 adv_pam4_112 = &link_info->advertising;
2319 sp_msks = bnxt_nrz_speeds2_masks;
2320 sp_pam4_msks = bnxt_pam4_speeds2_masks;
2321 sp_pam4_112_msks = bnxt_pam4_112_speeds2_masks;
2323 adv_pam4 = &link_info->advertising_pam4;
2324 sp_msks = bnxt_nrz_speed_masks;
2325 sp_pam4_msks = bnxt_pam4_speed_masks;
2327 for (i = 1; i < __BNXT_LINK_SPEED_END; i++) {
2328 /* accept any legal media from user */
2329 for (m = 1; m < __BNXT_MEDIA_END; m++) {
2330 bnxt_update_speed(&delta_nrz, m == media,
2331 adv, sp_msks[i], et_mask,
2332 bnxt_link_modes[i][BNXT_SIG_MODE_NRZ][m]);
2333 bnxt_update_speed(&delta_pam4, m == media,
2334 adv_pam4, sp_pam4_msks[i], et_mask,
2335 bnxt_link_modes[i][BNXT_SIG_MODE_PAM4][m]);
2339 bnxt_update_speed(&delta_pam4_112, m == media,
2340 adv_pam4_112, sp_pam4_112_msks[i], et_mask,
2341 bnxt_link_modes[i][BNXT_SIG_MODE_PAM4_112][m]);
2346 static void bnxt_fw_to_ethtool_advertised_fec(struct bnxt_link_info *link_info,
2347 struct ethtool_link_ksettings *lk_ksettings)
2349 u16 fec_cfg = link_info->fec_cfg;
2351 if ((fec_cfg & BNXT_FEC_NONE) || !(fec_cfg & BNXT_FEC_AUTONEG)) {
2352 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_NONE_BIT,
2353 lk_ksettings->link_modes.advertising);
2356 if (fec_cfg & BNXT_FEC_ENC_BASE_R)
2357 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_BASER_BIT,
2358 lk_ksettings->link_modes.advertising);
2359 if (fec_cfg & BNXT_FEC_ENC_RS)
2360 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_RS_BIT,
2361 lk_ksettings->link_modes.advertising);
2362 if (fec_cfg & BNXT_FEC_ENC_LLRS)
2363 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_LLRS_BIT,
2364 lk_ksettings->link_modes.advertising);
2367 static void bnxt_fw_to_ethtool_support_fec(struct bnxt_link_info *link_info,
2368 struct ethtool_link_ksettings *lk_ksettings)
2370 u16 fec_cfg = link_info->fec_cfg;
2372 if (fec_cfg & BNXT_FEC_NONE) {
2373 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_NONE_BIT,
2374 lk_ksettings->link_modes.supported);
2377 if (fec_cfg & BNXT_FEC_ENC_BASE_R_CAP)
2378 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_BASER_BIT,
2379 lk_ksettings->link_modes.supported);
2380 if (fec_cfg & BNXT_FEC_ENC_RS_CAP)
2381 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_RS_BIT,
2382 lk_ksettings->link_modes.supported);
2383 if (fec_cfg & BNXT_FEC_ENC_LLRS_CAP)
2384 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_LLRS_BIT,
2385 lk_ksettings->link_modes.supported);
2388 u32 bnxt_fw_to_ethtool_speed(u16 fw_link_speed)
2390 switch (fw_link_speed) {
2391 case BNXT_LINK_SPEED_100MB:
2393 case BNXT_LINK_SPEED_1GB:
2395 case BNXT_LINK_SPEED_2_5GB:
2397 case BNXT_LINK_SPEED_10GB:
2399 case BNXT_LINK_SPEED_20GB:
2401 case BNXT_LINK_SPEED_25GB:
2403 case BNXT_LINK_SPEED_40GB:
2405 case BNXT_LINK_SPEED_50GB:
2406 case BNXT_LINK_SPEED_50GB_PAM4:
2408 case BNXT_LINK_SPEED_100GB:
2409 case BNXT_LINK_SPEED_100GB_PAM4:
2410 case BNXT_LINK_SPEED_100GB_PAM4_112:
2411 return SPEED_100000;
2412 case BNXT_LINK_SPEED_200GB:
2413 case BNXT_LINK_SPEED_200GB_PAM4:
2414 case BNXT_LINK_SPEED_200GB_PAM4_112:
2415 return SPEED_200000;
2416 case BNXT_LINK_SPEED_400GB:
2417 case BNXT_LINK_SPEED_400GB_PAM4:
2418 case BNXT_LINK_SPEED_400GB_PAM4_112:
2419 return SPEED_400000;
2421 return SPEED_UNKNOWN;
2425 static void bnxt_get_default_speeds(struct ethtool_link_ksettings *lk_ksettings,
2426 struct bnxt_link_info *link_info)
2428 struct ethtool_link_settings *base = &lk_ksettings->base;
2430 if (link_info->link_state == BNXT_LINK_STATE_UP) {
2431 base->speed = bnxt_fw_to_ethtool_speed(link_info->link_speed);
2432 base->duplex = DUPLEX_HALF;
2433 if (link_info->duplex & BNXT_LINK_DUPLEX_FULL)
2434 base->duplex = DUPLEX_FULL;
2435 lk_ksettings->lanes = link_info->active_lanes;
2436 } else if (!link_info->autoneg) {
2437 base->speed = bnxt_fw_to_ethtool_speed(link_info->req_link_speed);
2438 base->duplex = DUPLEX_HALF;
2439 if (link_info->req_duplex == BNXT_LINK_DUPLEX_FULL)
2440 base->duplex = DUPLEX_FULL;
2444 static int bnxt_get_link_ksettings(struct net_device *dev,
2445 struct ethtool_link_ksettings *lk_ksettings)
2447 struct ethtool_link_settings *base = &lk_ksettings->base;
2448 enum ethtool_link_mode_bit_indices link_mode;
2449 struct bnxt *bp = netdev_priv(dev);
2450 struct bnxt_link_info *link_info;
2451 enum bnxt_media_type media;
2453 ethtool_link_ksettings_zero_link_mode(lk_ksettings, lp_advertising);
2454 ethtool_link_ksettings_zero_link_mode(lk_ksettings, advertising);
2455 ethtool_link_ksettings_zero_link_mode(lk_ksettings, supported);
2456 base->duplex = DUPLEX_UNKNOWN;
2457 base->speed = SPEED_UNKNOWN;
2458 link_info = &bp->link_info;
2460 mutex_lock(&bp->link_lock);
2461 bnxt_get_ethtool_modes(link_info, lk_ksettings);
2462 media = bnxt_get_media(link_info);
2463 bnxt_get_all_ethtool_support_speeds(link_info, media, lk_ksettings);
2464 bnxt_fw_to_ethtool_support_fec(link_info, lk_ksettings);
2465 link_mode = bnxt_get_link_mode(link_info);
2466 if (link_mode != BNXT_LINK_MODE_UNKNOWN)
2467 ethtool_params_from_link_mode(lk_ksettings, link_mode);
2469 bnxt_get_default_speeds(lk_ksettings, link_info);
2471 if (link_info->autoneg) {
2472 bnxt_fw_to_ethtool_advertised_fec(link_info, lk_ksettings);
2473 linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT,
2474 lk_ksettings->link_modes.advertising);
2475 base->autoneg = AUTONEG_ENABLE;
2476 bnxt_get_all_ethtool_adv_speeds(link_info, media, lk_ksettings);
2477 if (link_info->phy_link_status == BNXT_LINK_LINK)
2478 bnxt_get_all_ethtool_lp_speeds(link_info, media,
2481 base->autoneg = AUTONEG_DISABLE;
2484 base->port = PORT_NONE;
2485 if (link_info->media_type == PORT_PHY_QCFG_RESP_MEDIA_TYPE_TP) {
2486 base->port = PORT_TP;
2487 linkmode_set_bit(ETHTOOL_LINK_MODE_TP_BIT,
2488 lk_ksettings->link_modes.supported);
2489 linkmode_set_bit(ETHTOOL_LINK_MODE_TP_BIT,
2490 lk_ksettings->link_modes.advertising);
2492 linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT,
2493 lk_ksettings->link_modes.supported);
2494 linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT,
2495 lk_ksettings->link_modes.advertising);
2497 if (link_info->media_type == PORT_PHY_QCFG_RESP_MEDIA_TYPE_DAC)
2498 base->port = PORT_DA;
2500 base->port = PORT_FIBRE;
2502 base->phy_address = link_info->phy_addr;
2503 mutex_unlock(&bp->link_lock);
2509 bnxt_force_link_speed(struct net_device *dev, u32 ethtool_speed, u32 lanes)
2511 struct bnxt *bp = netdev_priv(dev);
2512 struct bnxt_link_info *link_info = &bp->link_info;
2513 u16 support_pam4_spds = link_info->support_pam4_speeds;
2514 u16 support_spds2 = link_info->support_speeds2;
2515 u16 support_spds = link_info->support_speeds;
2516 u8 sig_mode = BNXT_SIG_MODE_NRZ;
2517 u32 lanes_needed = 1;
2520 switch (ethtool_speed) {
2522 if (support_spds & BNXT_LINK_SPEED_MSK_100MB)
2523 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_100MB;
2526 if ((support_spds & BNXT_LINK_SPEED_MSK_1GB) ||
2527 (support_spds2 & BNXT_LINK_SPEEDS2_MSK_1GB))
2528 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_1GB;
2531 if (support_spds & BNXT_LINK_SPEED_MSK_2_5GB)
2532 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_2_5GB;
2535 if ((support_spds & BNXT_LINK_SPEED_MSK_10GB) ||
2536 (support_spds2 & BNXT_LINK_SPEEDS2_MSK_10GB))
2537 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10GB;
2540 if (support_spds & BNXT_LINK_SPEED_MSK_20GB) {
2541 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_20GB;
2546 if ((support_spds & BNXT_LINK_SPEED_MSK_25GB) ||
2547 (support_spds2 & BNXT_LINK_SPEEDS2_MSK_25GB))
2548 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_25GB;
2551 if ((support_spds & BNXT_LINK_SPEED_MSK_40GB) ||
2552 (support_spds2 & BNXT_LINK_SPEEDS2_MSK_40GB)) {
2553 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_40GB;
2558 if (((support_spds & BNXT_LINK_SPEED_MSK_50GB) ||
2559 (support_spds2 & BNXT_LINK_SPEEDS2_MSK_50GB)) &&
2561 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_50GB;
2563 } else if (support_pam4_spds & BNXT_LINK_PAM4_SPEED_MSK_50GB) {
2564 fw_speed = PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_50GB;
2565 sig_mode = BNXT_SIG_MODE_PAM4;
2566 } else if (support_spds2 & BNXT_LINK_SPEEDS2_MSK_50GB_PAM4) {
2567 fw_speed = BNXT_LINK_SPEED_50GB_PAM4;
2568 sig_mode = BNXT_SIG_MODE_PAM4;
2572 if (((support_spds & BNXT_LINK_SPEED_MSK_100GB) ||
2573 (support_spds2 & BNXT_LINK_SPEEDS2_MSK_100GB)) &&
2574 lanes != 2 && lanes != 1) {
2575 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_100GB;
2577 } else if (support_pam4_spds & BNXT_LINK_PAM4_SPEED_MSK_100GB) {
2578 fw_speed = PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_100GB;
2579 sig_mode = BNXT_SIG_MODE_PAM4;
2581 } else if ((support_spds2 & BNXT_LINK_SPEEDS2_MSK_100GB_PAM4) &&
2583 fw_speed = BNXT_LINK_SPEED_100GB_PAM4;
2584 sig_mode = BNXT_SIG_MODE_PAM4;
2586 } else if (support_spds2 & BNXT_LINK_SPEEDS2_MSK_100GB_PAM4_112) {
2587 fw_speed = BNXT_LINK_SPEED_100GB_PAM4_112;
2588 sig_mode = BNXT_SIG_MODE_PAM4_112;
2592 if (support_pam4_spds & BNXT_LINK_PAM4_SPEED_MSK_200GB) {
2593 fw_speed = PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_200GB;
2594 sig_mode = BNXT_SIG_MODE_PAM4;
2596 } else if ((support_spds2 & BNXT_LINK_SPEEDS2_MSK_200GB_PAM4) &&
2598 fw_speed = BNXT_LINK_SPEED_200GB_PAM4;
2599 sig_mode = BNXT_SIG_MODE_PAM4;
2601 } else if (support_spds2 & BNXT_LINK_SPEEDS2_MSK_200GB_PAM4_112) {
2602 fw_speed = BNXT_LINK_SPEED_200GB_PAM4_112;
2603 sig_mode = BNXT_SIG_MODE_PAM4_112;
2608 if ((support_spds2 & BNXT_LINK_SPEEDS2_MSK_400GB_PAM4) &&
2610 fw_speed = BNXT_LINK_SPEED_400GB_PAM4;
2611 sig_mode = BNXT_SIG_MODE_PAM4;
2613 } else if (support_spds2 & BNXT_LINK_SPEEDS2_MSK_400GB_PAM4_112) {
2614 fw_speed = BNXT_LINK_SPEED_400GB_PAM4_112;
2615 sig_mode = BNXT_SIG_MODE_PAM4_112;
2622 netdev_err(dev, "unsupported speed!\n");
2626 if (lanes && lanes != lanes_needed) {
2627 netdev_err(dev, "unsupported number of lanes for speed\n");
2631 if (link_info->req_link_speed == fw_speed &&
2632 link_info->req_signal_mode == sig_mode &&
2633 link_info->autoneg == 0)
2636 link_info->req_link_speed = fw_speed;
2637 link_info->req_signal_mode = sig_mode;
2638 link_info->req_duplex = BNXT_LINK_DUPLEX_FULL;
2639 link_info->autoneg = 0;
2640 link_info->advertising = 0;
2641 link_info->advertising_pam4 = 0;
2646 u16 bnxt_get_fw_auto_link_speeds(u32 advertising)
2648 u16 fw_speed_mask = 0;
2650 /* only support autoneg at speed 100, 1000, and 10000 */
2651 if (advertising & (ADVERTISED_100baseT_Full |
2652 ADVERTISED_100baseT_Half)) {
2653 fw_speed_mask |= BNXT_LINK_SPEED_MSK_100MB;
2655 if (advertising & (ADVERTISED_1000baseT_Full |
2656 ADVERTISED_1000baseT_Half)) {
2657 fw_speed_mask |= BNXT_LINK_SPEED_MSK_1GB;
2659 if (advertising & ADVERTISED_10000baseT_Full)
2660 fw_speed_mask |= BNXT_LINK_SPEED_MSK_10GB;
2662 if (advertising & ADVERTISED_40000baseCR4_Full)
2663 fw_speed_mask |= BNXT_LINK_SPEED_MSK_40GB;
2665 return fw_speed_mask;
2668 static int bnxt_set_link_ksettings(struct net_device *dev,
2669 const struct ethtool_link_ksettings *lk_ksettings)
2671 struct bnxt *bp = netdev_priv(dev);
2672 struct bnxt_link_info *link_info = &bp->link_info;
2673 const struct ethtool_link_settings *base = &lk_ksettings->base;
2674 bool set_pause = false;
2675 u32 speed, lanes = 0;
2678 if (!BNXT_PHY_CFG_ABLE(bp))
2681 mutex_lock(&bp->link_lock);
2682 if (base->autoneg == AUTONEG_ENABLE) {
2683 bnxt_set_ethtool_speeds(link_info,
2684 lk_ksettings->link_modes.advertising);
2685 link_info->autoneg |= BNXT_AUTONEG_SPEED;
2686 if (!link_info->advertising && !link_info->advertising_pam4) {
2687 link_info->advertising = link_info->support_auto_speeds;
2688 link_info->advertising_pam4 =
2689 link_info->support_pam4_auto_speeds;
2691 /* any change to autoneg will cause link change, therefore the
2692 * driver should put back the original pause setting in autoneg
2694 if (!(bp->phy_flags & BNXT_PHY_FL_NO_PAUSE))
2697 u8 phy_type = link_info->phy_type;
2699 if (phy_type == PORT_PHY_QCFG_RESP_PHY_TYPE_BASET ||
2700 phy_type == PORT_PHY_QCFG_RESP_PHY_TYPE_BASETE ||
2701 link_info->media_type == PORT_PHY_QCFG_RESP_MEDIA_TYPE_TP) {
2702 netdev_err(dev, "10GBase-T devices must autoneg\n");
2704 goto set_setting_exit;
2706 if (base->duplex == DUPLEX_HALF) {
2707 netdev_err(dev, "HALF DUPLEX is not supported!\n");
2709 goto set_setting_exit;
2711 speed = base->speed;
2712 lanes = lk_ksettings->lanes;
2713 rc = bnxt_force_link_speed(dev, speed, lanes);
2715 if (rc == -EALREADY)
2717 goto set_setting_exit;
2721 if (netif_running(dev))
2722 rc = bnxt_hwrm_set_link_setting(bp, set_pause, false);
2725 mutex_unlock(&bp->link_lock);
2729 static int bnxt_get_fecparam(struct net_device *dev,
2730 struct ethtool_fecparam *fec)
2732 struct bnxt *bp = netdev_priv(dev);
2733 struct bnxt_link_info *link_info;
2737 link_info = &bp->link_info;
2738 fec_cfg = link_info->fec_cfg;
2739 active_fec = link_info->active_fec_sig_mode &
2740 PORT_PHY_QCFG_RESP_ACTIVE_FEC_MASK;
2741 if (fec_cfg & BNXT_FEC_NONE) {
2742 fec->fec = ETHTOOL_FEC_NONE;
2743 fec->active_fec = ETHTOOL_FEC_NONE;
2746 if (fec_cfg & BNXT_FEC_AUTONEG)
2747 fec->fec |= ETHTOOL_FEC_AUTO;
2748 if (fec_cfg & BNXT_FEC_ENC_BASE_R)
2749 fec->fec |= ETHTOOL_FEC_BASER;
2750 if (fec_cfg & BNXT_FEC_ENC_RS)
2751 fec->fec |= ETHTOOL_FEC_RS;
2752 if (fec_cfg & BNXT_FEC_ENC_LLRS)
2753 fec->fec |= ETHTOOL_FEC_LLRS;
2755 switch (active_fec) {
2756 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_CLAUSE74_ACTIVE:
2757 fec->active_fec |= ETHTOOL_FEC_BASER;
2759 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_CLAUSE91_ACTIVE:
2760 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS544_1XN_ACTIVE:
2761 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS544_IEEE_ACTIVE:
2762 fec->active_fec |= ETHTOOL_FEC_RS;
2764 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS272_1XN_ACTIVE:
2765 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS272_IEEE_ACTIVE:
2766 fec->active_fec |= ETHTOOL_FEC_LLRS;
2768 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_NONE_ACTIVE:
2769 fec->active_fec |= ETHTOOL_FEC_OFF;
2775 static void bnxt_get_fec_stats(struct net_device *dev,
2776 struct ethtool_fec_stats *fec_stats)
2778 struct bnxt *bp = netdev_priv(dev);
2781 if (BNXT_VF(bp) || !(bp->flags & BNXT_FLAG_PORT_STATS_EXT))
2784 rx = bp->rx_port_stats_ext.sw_stats;
2785 fec_stats->corrected_bits.total =
2786 *(rx + BNXT_RX_STATS_EXT_OFFSET(rx_corrected_bits));
2788 if (bp->fw_rx_stats_ext_size <= BNXT_RX_STATS_EXT_NUM_LEGACY)
2791 fec_stats->corrected_blocks.total =
2792 *(rx + BNXT_RX_STATS_EXT_OFFSET(rx_fec_corrected_blocks));
2793 fec_stats->uncorrectable_blocks.total =
2794 *(rx + BNXT_RX_STATS_EXT_OFFSET(rx_fec_uncorrectable_blocks));
2797 static u32 bnxt_ethtool_forced_fec_to_fw(struct bnxt_link_info *link_info,
2800 u32 fw_fec = PORT_PHY_CFG_REQ_FLAGS_FEC_AUTONEG_DISABLE;
2802 if (fec & ETHTOOL_FEC_BASER)
2803 fw_fec |= BNXT_FEC_BASE_R_ON(link_info);
2804 else if (fec & ETHTOOL_FEC_RS)
2805 fw_fec |= BNXT_FEC_RS_ON(link_info);
2806 else if (fec & ETHTOOL_FEC_LLRS)
2807 fw_fec |= BNXT_FEC_LLRS_ON;
2811 static int bnxt_set_fecparam(struct net_device *dev,
2812 struct ethtool_fecparam *fecparam)
2814 struct hwrm_port_phy_cfg_input *req;
2815 struct bnxt *bp = netdev_priv(dev);
2816 struct bnxt_link_info *link_info;
2817 u32 new_cfg, fec = fecparam->fec;
2821 link_info = &bp->link_info;
2822 fec_cfg = link_info->fec_cfg;
2823 if (fec_cfg & BNXT_FEC_NONE)
2826 if (fec & ETHTOOL_FEC_OFF) {
2827 new_cfg = PORT_PHY_CFG_REQ_FLAGS_FEC_AUTONEG_DISABLE |
2828 BNXT_FEC_ALL_OFF(link_info);
2831 if (((fec & ETHTOOL_FEC_AUTO) && !(fec_cfg & BNXT_FEC_AUTONEG_CAP)) ||
2832 ((fec & ETHTOOL_FEC_RS) && !(fec_cfg & BNXT_FEC_ENC_RS_CAP)) ||
2833 ((fec & ETHTOOL_FEC_LLRS) && !(fec_cfg & BNXT_FEC_ENC_LLRS_CAP)) ||
2834 ((fec & ETHTOOL_FEC_BASER) && !(fec_cfg & BNXT_FEC_ENC_BASE_R_CAP)))
2837 if (fec & ETHTOOL_FEC_AUTO) {
2838 if (!link_info->autoneg)
2840 new_cfg = PORT_PHY_CFG_REQ_FLAGS_FEC_AUTONEG_ENABLE;
2842 new_cfg = bnxt_ethtool_forced_fec_to_fw(link_info, fec);
2846 rc = hwrm_req_init(bp, req, HWRM_PORT_PHY_CFG);
2849 req->flags = cpu_to_le32(new_cfg | PORT_PHY_CFG_REQ_FLAGS_RESET_PHY);
2850 rc = hwrm_req_send(bp, req);
2851 /* update current settings */
2853 mutex_lock(&bp->link_lock);
2854 bnxt_update_link(bp, false);
2855 mutex_unlock(&bp->link_lock);
2860 static void bnxt_get_pauseparam(struct net_device *dev,
2861 struct ethtool_pauseparam *epause)
2863 struct bnxt *bp = netdev_priv(dev);
2864 struct bnxt_link_info *link_info = &bp->link_info;
2868 epause->autoneg = !!(link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL);
2869 epause->rx_pause = !!(link_info->req_flow_ctrl & BNXT_LINK_PAUSE_RX);
2870 epause->tx_pause = !!(link_info->req_flow_ctrl & BNXT_LINK_PAUSE_TX);
2873 static void bnxt_get_pause_stats(struct net_device *dev,
2874 struct ethtool_pause_stats *epstat)
2876 struct bnxt *bp = netdev_priv(dev);
2879 if (BNXT_VF(bp) || !(bp->flags & BNXT_FLAG_PORT_STATS))
2882 rx = bp->port_stats.sw_stats;
2883 tx = bp->port_stats.sw_stats + BNXT_TX_PORT_STATS_BYTE_OFFSET / 8;
2885 epstat->rx_pause_frames = BNXT_GET_RX_PORT_STATS64(rx, rx_pause_frames);
2886 epstat->tx_pause_frames = BNXT_GET_TX_PORT_STATS64(tx, tx_pause_frames);
2889 static int bnxt_set_pauseparam(struct net_device *dev,
2890 struct ethtool_pauseparam *epause)
2893 struct bnxt *bp = netdev_priv(dev);
2894 struct bnxt_link_info *link_info = &bp->link_info;
2896 if (!BNXT_PHY_CFG_ABLE(bp) || (bp->phy_flags & BNXT_PHY_FL_NO_PAUSE))
2899 mutex_lock(&bp->link_lock);
2900 if (epause->autoneg) {
2901 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) {
2906 link_info->autoneg |= BNXT_AUTONEG_FLOW_CTRL;
2907 link_info->req_flow_ctrl = 0;
2909 /* when transition from auto pause to force pause,
2910 * force a link change
2912 if (link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL)
2913 link_info->force_link_chng = true;
2914 link_info->autoneg &= ~BNXT_AUTONEG_FLOW_CTRL;
2915 link_info->req_flow_ctrl = 0;
2917 if (epause->rx_pause)
2918 link_info->req_flow_ctrl |= BNXT_LINK_PAUSE_RX;
2920 if (epause->tx_pause)
2921 link_info->req_flow_ctrl |= BNXT_LINK_PAUSE_TX;
2923 if (netif_running(dev))
2924 rc = bnxt_hwrm_set_pause(bp);
2927 mutex_unlock(&bp->link_lock);
2931 static u32 bnxt_get_link(struct net_device *dev)
2933 struct bnxt *bp = netdev_priv(dev);
2935 /* TODO: handle MF, VF, driver close case */
2936 return BNXT_LINK_IS_UP(bp);
2939 int bnxt_hwrm_nvm_get_dev_info(struct bnxt *bp,
2940 struct hwrm_nvm_get_dev_info_output *nvm_dev_info)
2942 struct hwrm_nvm_get_dev_info_output *resp;
2943 struct hwrm_nvm_get_dev_info_input *req;
2949 rc = hwrm_req_init(bp, req, HWRM_NVM_GET_DEV_INFO);
2953 resp = hwrm_req_hold(bp, req);
2954 rc = hwrm_req_send(bp, req);
2956 memcpy(nvm_dev_info, resp, sizeof(*resp));
2957 hwrm_req_drop(bp, req);
2961 static void bnxt_print_admin_err(struct bnxt *bp)
2963 netdev_info(bp->dev, "PF does not have admin privileges to flash or reset the device\n");
2966 int bnxt_find_nvram_item(struct net_device *dev, u16 type, u16 ordinal,
2967 u16 ext, u16 *index, u32 *item_length,
2970 int bnxt_flash_nvram(struct net_device *dev, u16 dir_type,
2971 u16 dir_ordinal, u16 dir_ext, u16 dir_attr,
2972 u32 dir_item_len, const u8 *data,
2975 struct bnxt *bp = netdev_priv(dev);
2976 struct hwrm_nvm_write_input *req;
2979 rc = hwrm_req_init(bp, req, HWRM_NVM_WRITE);
2983 if (data_len && data) {
2984 dma_addr_t dma_handle;
2987 kmem = hwrm_req_dma_slice(bp, req, data_len, &dma_handle);
2989 hwrm_req_drop(bp, req);
2993 req->dir_data_length = cpu_to_le32(data_len);
2995 memcpy(kmem, data, data_len);
2996 req->host_src_addr = cpu_to_le64(dma_handle);
2999 hwrm_req_timeout(bp, req, bp->hwrm_cmd_max_timeout);
3000 req->dir_type = cpu_to_le16(dir_type);
3001 req->dir_ordinal = cpu_to_le16(dir_ordinal);
3002 req->dir_ext = cpu_to_le16(dir_ext);
3003 req->dir_attr = cpu_to_le16(dir_attr);
3004 req->dir_item_length = cpu_to_le32(dir_item_len);
3005 rc = hwrm_req_send(bp, req);
3008 bnxt_print_admin_err(bp);
3012 int bnxt_hwrm_firmware_reset(struct net_device *dev, u8 proc_type,
3013 u8 self_reset, u8 flags)
3015 struct bnxt *bp = netdev_priv(dev);
3016 struct hwrm_fw_reset_input *req;
3019 if (!bnxt_hwrm_reset_permitted(bp)) {
3020 netdev_warn(bp->dev, "Reset denied by firmware, it may be inhibited by remote driver");
3024 rc = hwrm_req_init(bp, req, HWRM_FW_RESET);
3028 req->embedded_proc_type = proc_type;
3029 req->selfrst_status = self_reset;
3032 if (proc_type == FW_RESET_REQ_EMBEDDED_PROC_TYPE_AP) {
3033 rc = hwrm_req_send_silent(bp, req);
3035 rc = hwrm_req_send(bp, req);
3037 bnxt_print_admin_err(bp);
3042 static int bnxt_firmware_reset(struct net_device *dev,
3043 enum bnxt_nvm_directory_type dir_type)
3045 u8 self_reset = FW_RESET_REQ_SELFRST_STATUS_SELFRSTNONE;
3046 u8 proc_type, flags = 0;
3048 /* TODO: Address self-reset of APE/KONG/BONO/TANG or ungraceful reset */
3049 /* (e.g. when firmware isn't already running) */
3051 case BNX_DIR_TYPE_CHIMP_PATCH:
3052 case BNX_DIR_TYPE_BOOTCODE:
3053 case BNX_DIR_TYPE_BOOTCODE_2:
3054 proc_type = FW_RESET_REQ_EMBEDDED_PROC_TYPE_BOOT;
3055 /* Self-reset ChiMP upon next PCIe reset: */
3056 self_reset = FW_RESET_REQ_SELFRST_STATUS_SELFRSTPCIERST;
3058 case BNX_DIR_TYPE_APE_FW:
3059 case BNX_DIR_TYPE_APE_PATCH:
3060 proc_type = FW_RESET_REQ_EMBEDDED_PROC_TYPE_MGMT;
3061 /* Self-reset APE upon next PCIe reset: */
3062 self_reset = FW_RESET_REQ_SELFRST_STATUS_SELFRSTPCIERST;
3064 case BNX_DIR_TYPE_KONG_FW:
3065 case BNX_DIR_TYPE_KONG_PATCH:
3066 proc_type = FW_RESET_REQ_EMBEDDED_PROC_TYPE_NETCTRL;
3068 case BNX_DIR_TYPE_BONO_FW:
3069 case BNX_DIR_TYPE_BONO_PATCH:
3070 proc_type = FW_RESET_REQ_EMBEDDED_PROC_TYPE_ROCE;
3076 return bnxt_hwrm_firmware_reset(dev, proc_type, self_reset, flags);
3079 static int bnxt_firmware_reset_chip(struct net_device *dev)
3081 struct bnxt *bp = netdev_priv(dev);
3084 if (bp->fw_cap & BNXT_FW_CAP_HOT_RESET)
3085 flags = FW_RESET_REQ_FLAGS_RESET_GRACEFUL;
3087 return bnxt_hwrm_firmware_reset(dev,
3088 FW_RESET_REQ_EMBEDDED_PROC_TYPE_CHIP,
3089 FW_RESET_REQ_SELFRST_STATUS_SELFRSTASAP,
3093 static int bnxt_firmware_reset_ap(struct net_device *dev)
3095 return bnxt_hwrm_firmware_reset(dev, FW_RESET_REQ_EMBEDDED_PROC_TYPE_AP,
3096 FW_RESET_REQ_SELFRST_STATUS_SELFRSTNONE,
3100 static int bnxt_flash_firmware(struct net_device *dev,
3109 struct bnxt_fw_header *header = (struct bnxt_fw_header *)fw_data;
3112 case BNX_DIR_TYPE_BOOTCODE:
3113 case BNX_DIR_TYPE_BOOTCODE_2:
3114 code_type = CODE_BOOT;
3116 case BNX_DIR_TYPE_CHIMP_PATCH:
3117 code_type = CODE_CHIMP_PATCH;
3119 case BNX_DIR_TYPE_APE_FW:
3120 code_type = CODE_MCTP_PASSTHRU;
3122 case BNX_DIR_TYPE_APE_PATCH:
3123 code_type = CODE_APE_PATCH;
3125 case BNX_DIR_TYPE_KONG_FW:
3126 code_type = CODE_KONG_FW;
3128 case BNX_DIR_TYPE_KONG_PATCH:
3129 code_type = CODE_KONG_PATCH;
3131 case BNX_DIR_TYPE_BONO_FW:
3132 code_type = CODE_BONO_FW;
3134 case BNX_DIR_TYPE_BONO_PATCH:
3135 code_type = CODE_BONO_PATCH;
3138 netdev_err(dev, "Unsupported directory entry type: %u\n",
3142 if (fw_size < sizeof(struct bnxt_fw_header)) {
3143 netdev_err(dev, "Invalid firmware file size: %u\n",
3144 (unsigned int)fw_size);
3147 if (header->signature != cpu_to_le32(BNXT_FIRMWARE_BIN_SIGNATURE)) {
3148 netdev_err(dev, "Invalid firmware signature: %08X\n",
3149 le32_to_cpu(header->signature));
3152 if (header->code_type != code_type) {
3153 netdev_err(dev, "Expected firmware type: %d, read: %d\n",
3154 code_type, header->code_type);
3157 if (header->device != DEVICE_CUMULUS_FAMILY) {
3158 netdev_err(dev, "Expected firmware device family %d, read: %d\n",
3159 DEVICE_CUMULUS_FAMILY, header->device);
3162 /* Confirm the CRC32 checksum of the file: */
3163 stored_crc = le32_to_cpu(*(__le32 *)(fw_data + fw_size -
3164 sizeof(stored_crc)));
3165 calculated_crc = ~crc32(~0, fw_data, fw_size - sizeof(stored_crc));
3166 if (calculated_crc != stored_crc) {
3167 netdev_err(dev, "Firmware file CRC32 checksum (%08lX) does not match calculated checksum (%08lX)\n",
3168 (unsigned long)stored_crc,
3169 (unsigned long)calculated_crc);
3172 rc = bnxt_flash_nvram(dev, dir_type, BNX_DIR_ORDINAL_FIRST,
3173 0, 0, 0, fw_data, fw_size);
3174 if (rc == 0) /* Firmware update successful */
3175 rc = bnxt_firmware_reset(dev, dir_type);
3180 static int bnxt_flash_microcode(struct net_device *dev,
3185 struct bnxt_ucode_trailer *trailer;
3190 if (fw_size < sizeof(struct bnxt_ucode_trailer)) {
3191 netdev_err(dev, "Invalid microcode file size: %u\n",
3192 (unsigned int)fw_size);
3195 trailer = (struct bnxt_ucode_trailer *)(fw_data + (fw_size -
3197 if (trailer->sig != cpu_to_le32(BNXT_UCODE_TRAILER_SIGNATURE)) {
3198 netdev_err(dev, "Invalid microcode trailer signature: %08X\n",
3199 le32_to_cpu(trailer->sig));
3202 if (le16_to_cpu(trailer->dir_type) != dir_type) {
3203 netdev_err(dev, "Expected microcode type: %d, read: %d\n",
3204 dir_type, le16_to_cpu(trailer->dir_type));
3207 if (le16_to_cpu(trailer->trailer_length) <
3208 sizeof(struct bnxt_ucode_trailer)) {
3209 netdev_err(dev, "Invalid microcode trailer length: %d\n",
3210 le16_to_cpu(trailer->trailer_length));
3214 /* Confirm the CRC32 checksum of the file: */
3215 stored_crc = le32_to_cpu(*(__le32 *)(fw_data + fw_size -
3216 sizeof(stored_crc)));
3217 calculated_crc = ~crc32(~0, fw_data, fw_size - sizeof(stored_crc));
3218 if (calculated_crc != stored_crc) {
3220 "CRC32 (%08lX) does not match calculated: %08lX\n",
3221 (unsigned long)stored_crc,
3222 (unsigned long)calculated_crc);
3225 rc = bnxt_flash_nvram(dev, dir_type, BNX_DIR_ORDINAL_FIRST,
3226 0, 0, 0, fw_data, fw_size);
3231 static bool bnxt_dir_type_is_ape_bin_format(u16 dir_type)
3234 case BNX_DIR_TYPE_CHIMP_PATCH:
3235 case BNX_DIR_TYPE_BOOTCODE:
3236 case BNX_DIR_TYPE_BOOTCODE_2:
3237 case BNX_DIR_TYPE_APE_FW:
3238 case BNX_DIR_TYPE_APE_PATCH:
3239 case BNX_DIR_TYPE_KONG_FW:
3240 case BNX_DIR_TYPE_KONG_PATCH:
3241 case BNX_DIR_TYPE_BONO_FW:
3242 case BNX_DIR_TYPE_BONO_PATCH:
3249 static bool bnxt_dir_type_is_other_exec_format(u16 dir_type)
3252 case BNX_DIR_TYPE_AVS:
3253 case BNX_DIR_TYPE_EXP_ROM_MBA:
3254 case BNX_DIR_TYPE_PCIE:
3255 case BNX_DIR_TYPE_TSCF_UCODE:
3256 case BNX_DIR_TYPE_EXT_PHY:
3257 case BNX_DIR_TYPE_CCM:
3258 case BNX_DIR_TYPE_ISCSI_BOOT:
3259 case BNX_DIR_TYPE_ISCSI_BOOT_IPV6:
3260 case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6:
3267 static bool bnxt_dir_type_is_executable(u16 dir_type)
3269 return bnxt_dir_type_is_ape_bin_format(dir_type) ||
3270 bnxt_dir_type_is_other_exec_format(dir_type);
3273 static int bnxt_flash_firmware_from_file(struct net_device *dev,
3275 const char *filename)
3277 const struct firmware *fw;
3280 rc = request_firmware(&fw, filename, &dev->dev);
3282 netdev_err(dev, "Error %d requesting firmware file: %s\n",
3286 if (bnxt_dir_type_is_ape_bin_format(dir_type))
3287 rc = bnxt_flash_firmware(dev, dir_type, fw->data, fw->size);
3288 else if (bnxt_dir_type_is_other_exec_format(dir_type))
3289 rc = bnxt_flash_microcode(dev, dir_type, fw->data, fw->size);
3291 rc = bnxt_flash_nvram(dev, dir_type, BNX_DIR_ORDINAL_FIRST,
3292 0, 0, 0, fw->data, fw->size);
3293 release_firmware(fw);
3297 #define MSG_INTEGRITY_ERR "PKG install error : Data integrity on NVM"
3298 #define MSG_INVALID_PKG "PKG install error : Invalid package"
3299 #define MSG_AUTHENTICATION_ERR "PKG install error : Authentication error"
3300 #define MSG_INVALID_DEV "PKG install error : Invalid device"
3301 #define MSG_INTERNAL_ERR "PKG install error : Internal error"
3302 #define MSG_NO_PKG_UPDATE_AREA_ERR "PKG update area not created in nvram"
3303 #define MSG_NO_SPACE_ERR "PKG insufficient update area in nvram"
3304 #define MSG_RESIZE_UPDATE_ERR "Resize UPDATE entry error"
3305 #define MSG_ANTI_ROLLBACK_ERR "HWRM_NVM_INSTALL_UPDATE failure due to Anti-rollback detected"
3306 #define MSG_GENERIC_FAILURE_ERR "HWRM_NVM_INSTALL_UPDATE failure"
3308 static int nvm_update_err_to_stderr(struct net_device *dev, u8 result,
3309 struct netlink_ext_ack *extack)
3312 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_TYPE_PARAMETER:
3313 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_INDEX_PARAMETER:
3314 case NVM_INSTALL_UPDATE_RESP_RESULT_INSTALL_DATA_ERROR:
3315 case NVM_INSTALL_UPDATE_RESP_RESULT_INSTALL_CHECKSUM_ERROR:
3316 case NVM_INSTALL_UPDATE_RESP_RESULT_ITEM_NOT_FOUND:
3317 case NVM_INSTALL_UPDATE_RESP_RESULT_ITEM_LOCKED:
3318 BNXT_NVM_ERR_MSG(dev, extack, MSG_INTEGRITY_ERR);
3320 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_PREREQUISITE:
3321 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_FILE_HEADER:
3322 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_SIGNATURE:
3323 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_PROP_STREAM:
3324 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_PROP_LENGTH:
3325 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_MANIFEST:
3326 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_TRAILER:
3327 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_CHECKSUM:
3328 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_ITEM_CHECKSUM:
3329 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_DATA_LENGTH:
3330 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_DIRECTIVE:
3331 case NVM_INSTALL_UPDATE_RESP_RESULT_DUPLICATE_ITEM:
3332 case NVM_INSTALL_UPDATE_RESP_RESULT_ZERO_LENGTH_ITEM:
3333 BNXT_NVM_ERR_MSG(dev, extack, MSG_INVALID_PKG);
3335 case NVM_INSTALL_UPDATE_RESP_RESULT_INSTALL_AUTHENTICATION_ERROR:
3336 BNXT_NVM_ERR_MSG(dev, extack, MSG_AUTHENTICATION_ERR);
3338 case NVM_INSTALL_UPDATE_RESP_RESULT_UNSUPPORTED_CHIP_REV:
3339 case NVM_INSTALL_UPDATE_RESP_RESULT_UNSUPPORTED_DEVICE_ID:
3340 case NVM_INSTALL_UPDATE_RESP_RESULT_UNSUPPORTED_SUBSYS_VENDOR:
3341 case NVM_INSTALL_UPDATE_RESP_RESULT_UNSUPPORTED_SUBSYS_ID:
3342 case NVM_INSTALL_UPDATE_RESP_RESULT_UNSUPPORTED_PLATFORM:
3343 BNXT_NVM_ERR_MSG(dev, extack, MSG_INVALID_DEV);
3346 BNXT_NVM_ERR_MSG(dev, extack, MSG_INTERNAL_ERR);
3351 #define BNXT_PKG_DMA_SIZE 0x40000
3352 #define BNXT_NVM_MORE_FLAG (cpu_to_le16(NVM_MODIFY_REQ_FLAGS_BATCH_MODE))
3353 #define BNXT_NVM_LAST_FLAG (cpu_to_le16(NVM_MODIFY_REQ_FLAGS_BATCH_LAST))
3355 static int bnxt_resize_update_entry(struct net_device *dev, size_t fw_size,
3356 struct netlink_ext_ack *extack)
3361 rc = bnxt_find_nvram_item(dev, BNX_DIR_TYPE_UPDATE,
3362 BNX_DIR_ORDINAL_FIRST, BNX_DIR_EXT_NONE, NULL,
3365 BNXT_NVM_ERR_MSG(dev, extack, MSG_NO_PKG_UPDATE_AREA_ERR);
3369 if (fw_size > item_len) {
3370 rc = bnxt_flash_nvram(dev, BNX_DIR_TYPE_UPDATE,
3371 BNX_DIR_ORDINAL_FIRST, 0, 1,
3372 round_up(fw_size, 4096), NULL, 0);
3374 BNXT_NVM_ERR_MSG(dev, extack, MSG_RESIZE_UPDATE_ERR);
3381 int bnxt_flash_package_from_fw_obj(struct net_device *dev, const struct firmware *fw,
3382 u32 install_type, struct netlink_ext_ack *extack)
3384 struct hwrm_nvm_install_update_input *install;
3385 struct hwrm_nvm_install_update_output *resp;
3386 struct hwrm_nvm_modify_input *modify;
3387 struct bnxt *bp = netdev_priv(dev);
3388 bool defrag_attempted = false;
3389 dma_addr_t dma_handle;
3397 /* resize before flashing larger image than available space */
3398 rc = bnxt_resize_update_entry(dev, fw->size, extack);
3402 bnxt_hwrm_fw_set_time(bp);
3404 rc = hwrm_req_init(bp, modify, HWRM_NVM_MODIFY);
3408 /* Try allocating a large DMA buffer first. Older fw will
3409 * cause excessive NVRAM erases when using small blocks.
3411 modify_len = roundup_pow_of_two(fw->size);
3412 modify_len = min_t(u32, modify_len, BNXT_PKG_DMA_SIZE);
3414 kmem = hwrm_req_dma_slice(bp, modify, modify_len, &dma_handle);
3415 if (!kmem && modify_len > PAGE_SIZE)
3421 hwrm_req_drop(bp, modify);
3425 rc = hwrm_req_init(bp, install, HWRM_NVM_INSTALL_UPDATE);
3427 hwrm_req_drop(bp, modify);
3431 hwrm_req_timeout(bp, modify, bp->hwrm_cmd_max_timeout);
3432 hwrm_req_timeout(bp, install, bp->hwrm_cmd_max_timeout);
3434 hwrm_req_hold(bp, modify);
3435 modify->host_src_addr = cpu_to_le64(dma_handle);
3437 resp = hwrm_req_hold(bp, install);
3438 if ((install_type & 0xffff) == 0)
3439 install_type >>= 16;
3440 install->install_type = cpu_to_le32(install_type);
3443 u32 copied = 0, len = modify_len;
3445 rc = bnxt_find_nvram_item(dev, BNX_DIR_TYPE_UPDATE,
3446 BNX_DIR_ORDINAL_FIRST,
3448 &index, &item_len, NULL);
3450 BNXT_NVM_ERR_MSG(dev, extack, MSG_NO_PKG_UPDATE_AREA_ERR);
3453 if (fw->size > item_len) {
3454 BNXT_NVM_ERR_MSG(dev, extack, MSG_NO_SPACE_ERR);
3459 modify->dir_idx = cpu_to_le16(index);
3461 if (fw->size > modify_len)
3462 modify->flags = BNXT_NVM_MORE_FLAG;
3463 while (copied < fw->size) {
3464 u32 balance = fw->size - copied;
3466 if (balance <= modify_len) {
3469 modify->flags |= BNXT_NVM_LAST_FLAG;
3471 memcpy(kmem, fw->data + copied, len);
3472 modify->len = cpu_to_le32(len);
3473 modify->offset = cpu_to_le32(copied);
3474 rc = hwrm_req_send(bp, modify);
3480 rc = hwrm_req_send_silent(bp, install);
3484 if (defrag_attempted) {
3485 /* We have tried to defragment already in the previous
3486 * iteration. Return with the result for INSTALL_UPDATE
3491 cmd_err = ((struct hwrm_err_output *)resp)->cmd_err;
3494 case NVM_INSTALL_UPDATE_CMD_ERR_CODE_ANTI_ROLLBACK:
3495 BNXT_NVM_ERR_MSG(dev, extack, MSG_ANTI_ROLLBACK_ERR);
3498 case NVM_INSTALL_UPDATE_CMD_ERR_CODE_FRAG_ERR:
3500 cpu_to_le16(NVM_INSTALL_UPDATE_REQ_FLAGS_ALLOWED_TO_DEFRAG);
3502 rc = hwrm_req_send_silent(bp, install);
3506 cmd_err = ((struct hwrm_err_output *)resp)->cmd_err;
3508 if (cmd_err == NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_SPACE) {
3509 /* FW has cleared NVM area, driver will create
3510 * UPDATE directory and try the flash again
3512 defrag_attempted = true;
3514 rc = bnxt_flash_nvram(bp->dev,
3515 BNX_DIR_TYPE_UPDATE,
3516 BNX_DIR_ORDINAL_FIRST,
3517 0, 0, item_len, NULL, 0);
3523 BNXT_NVM_ERR_MSG(dev, extack, MSG_GENERIC_FAILURE_ERR);
3525 } while (defrag_attempted && !rc);
3528 hwrm_req_drop(bp, modify);
3529 hwrm_req_drop(bp, install);
3532 netdev_err(dev, "PKG install error = %d, problem_item = %d\n",
3533 (s8)resp->result, (int)resp->problem_item);
3534 rc = nvm_update_err_to_stderr(dev, resp->result, extack);
3537 bnxt_print_admin_err(bp);
3541 static int bnxt_flash_package_from_file(struct net_device *dev, const char *filename,
3542 u32 install_type, struct netlink_ext_ack *extack)
3544 const struct firmware *fw;
3547 rc = request_firmware(&fw, filename, &dev->dev);
3549 netdev_err(dev, "PKG error %d requesting file: %s\n",
3554 rc = bnxt_flash_package_from_fw_obj(dev, fw, install_type, extack);
3556 release_firmware(fw);
3561 static int bnxt_flash_device(struct net_device *dev,
3562 struct ethtool_flash *flash)
3564 if (!BNXT_PF((struct bnxt *)netdev_priv(dev))) {
3565 netdev_err(dev, "flashdev not supported from a virtual function\n");
3569 if (flash->region == ETHTOOL_FLASH_ALL_REGIONS ||
3570 flash->region > 0xffff)
3571 return bnxt_flash_package_from_file(dev, flash->data,
3572 flash->region, NULL);
3574 return bnxt_flash_firmware_from_file(dev, flash->region, flash->data);
3577 static int nvm_get_dir_info(struct net_device *dev, u32 *entries, u32 *length)
3579 struct hwrm_nvm_get_dir_info_output *output;
3580 struct hwrm_nvm_get_dir_info_input *req;
3581 struct bnxt *bp = netdev_priv(dev);
3584 rc = hwrm_req_init(bp, req, HWRM_NVM_GET_DIR_INFO);
3588 output = hwrm_req_hold(bp, req);
3589 rc = hwrm_req_send(bp, req);
3591 *entries = le32_to_cpu(output->entries);
3592 *length = le32_to_cpu(output->entry_length);
3594 hwrm_req_drop(bp, req);
3598 static int bnxt_get_eeprom_len(struct net_device *dev)
3600 struct bnxt *bp = netdev_priv(dev);
3605 /* The -1 return value allows the entire 32-bit range of offsets to be
3606 * passed via the ethtool command-line utility.
3611 static int bnxt_get_nvram_directory(struct net_device *dev, u32 len, u8 *data)
3613 struct bnxt *bp = netdev_priv(dev);
3619 dma_addr_t dma_handle;
3620 struct hwrm_nvm_get_dir_entries_input *req;
3622 rc = nvm_get_dir_info(dev, &dir_entries, &entry_length);
3626 if (!dir_entries || !entry_length)
3629 /* Insert 2 bytes of directory info (count and size of entries) */
3633 *data++ = dir_entries;
3634 *data++ = entry_length;
3636 memset(data, 0xff, len);
3638 rc = hwrm_req_init(bp, req, HWRM_NVM_GET_DIR_ENTRIES);
3642 buflen = mul_u32_u32(dir_entries, entry_length);
3643 buf = hwrm_req_dma_slice(bp, req, buflen, &dma_handle);
3645 hwrm_req_drop(bp, req);
3648 req->host_dest_addr = cpu_to_le64(dma_handle);
3650 hwrm_req_hold(bp, req); /* hold the slice */
3651 rc = hwrm_req_send(bp, req);
3653 memcpy(data, buf, len > buflen ? buflen : len);
3654 hwrm_req_drop(bp, req);
3658 int bnxt_get_nvram_item(struct net_device *dev, u32 index, u32 offset,
3659 u32 length, u8 *data)
3661 struct bnxt *bp = netdev_priv(dev);
3664 dma_addr_t dma_handle;
3665 struct hwrm_nvm_read_input *req;
3670 rc = hwrm_req_init(bp, req, HWRM_NVM_READ);
3674 buf = hwrm_req_dma_slice(bp, req, length, &dma_handle);
3676 hwrm_req_drop(bp, req);
3680 req->host_dest_addr = cpu_to_le64(dma_handle);
3681 req->dir_idx = cpu_to_le16(index);
3682 req->offset = cpu_to_le32(offset);
3683 req->len = cpu_to_le32(length);
3685 hwrm_req_hold(bp, req); /* hold the slice */
3686 rc = hwrm_req_send(bp, req);
3688 memcpy(data, buf, length);
3689 hwrm_req_drop(bp, req);
3693 int bnxt_find_nvram_item(struct net_device *dev, u16 type, u16 ordinal,
3694 u16 ext, u16 *index, u32 *item_length,
3697 struct hwrm_nvm_find_dir_entry_output *output;
3698 struct hwrm_nvm_find_dir_entry_input *req;
3699 struct bnxt *bp = netdev_priv(dev);
3702 rc = hwrm_req_init(bp, req, HWRM_NVM_FIND_DIR_ENTRY);
3708 req->dir_type = cpu_to_le16(type);
3709 req->dir_ordinal = cpu_to_le16(ordinal);
3710 req->dir_ext = cpu_to_le16(ext);
3711 req->opt_ordinal = NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_EQ;
3712 output = hwrm_req_hold(bp, req);
3713 rc = hwrm_req_send_silent(bp, req);
3716 *index = le16_to_cpu(output->dir_idx);
3718 *item_length = le32_to_cpu(output->dir_item_length);
3720 *data_length = le32_to_cpu(output->dir_data_length);
3722 hwrm_req_drop(bp, req);
3726 static char *bnxt_parse_pkglog(int desired_field, u8 *data, size_t datalen)
3728 char *retval = NULL;
3735 /* null-terminate the log data (removing last '\n'): */
3736 data[datalen - 1] = 0;
3737 for (p = data; *p != 0; p++) {
3740 while (*p != 0 && *p != '\n') {
3742 while (*p != 0 && *p != '\t' && *p != '\n')
3744 if (field == desired_field)
3759 int bnxt_get_pkginfo(struct net_device *dev, char *ver, int size)
3761 struct bnxt *bp = netdev_priv(dev);
3768 rc = bnxt_find_nvram_item(dev, BNX_DIR_TYPE_PKG_LOG,
3769 BNX_DIR_ORDINAL_FIRST, BNX_DIR_EXT_NONE,
3770 &index, NULL, &pkglen);
3774 pkgbuf = kzalloc(pkglen, GFP_KERNEL);
3776 dev_err(&bp->pdev->dev, "Unable to allocate memory for pkg version, length = %u\n",
3781 rc = bnxt_get_nvram_item(dev, index, 0, pkglen, pkgbuf);
3785 pkgver = bnxt_parse_pkglog(BNX_PKG_LOG_FIELD_IDX_PKG_VERSION, pkgbuf,
3787 if (pkgver && *pkgver != 0 && isdigit(*pkgver))
3788 strscpy(ver, pkgver, size);
3798 static void bnxt_get_pkgver(struct net_device *dev)
3800 struct bnxt *bp = netdev_priv(dev);
3801 char buf[FW_VER_STR_LEN];
3804 if (!bnxt_get_pkginfo(dev, buf, sizeof(buf))) {
3805 len = strlen(bp->fw_ver_str);
3806 snprintf(bp->fw_ver_str + len, FW_VER_STR_LEN - len - 1,
3811 static int bnxt_get_eeprom(struct net_device *dev,
3812 struct ethtool_eeprom *eeprom,
3818 if (eeprom->offset == 0) /* special offset value to get directory */
3819 return bnxt_get_nvram_directory(dev, eeprom->len, data);
3821 index = eeprom->offset >> 24;
3822 offset = eeprom->offset & 0xffffff;
3825 netdev_err(dev, "unsupported index value: %d\n", index);
3829 return bnxt_get_nvram_item(dev, index - 1, offset, eeprom->len, data);
3832 static int bnxt_erase_nvram_directory(struct net_device *dev, u8 index)
3834 struct hwrm_nvm_erase_dir_entry_input *req;
3835 struct bnxt *bp = netdev_priv(dev);
3838 rc = hwrm_req_init(bp, req, HWRM_NVM_ERASE_DIR_ENTRY);
3842 req->dir_idx = cpu_to_le16(index);
3843 return hwrm_req_send(bp, req);
3846 static int bnxt_set_eeprom(struct net_device *dev,
3847 struct ethtool_eeprom *eeprom,
3850 struct bnxt *bp = netdev_priv(dev);
3852 u16 type, ext, ordinal, attr;
3855 netdev_err(dev, "NVM write not supported from a virtual function\n");
3859 type = eeprom->magic >> 16;
3861 if (type == 0xffff) { /* special value for directory operations */
3862 index = eeprom->magic & 0xff;
3863 dir_op = eeprom->magic >> 8;
3867 case 0x0e: /* erase */
3868 if (eeprom->offset != ~eeprom->magic)
3870 return bnxt_erase_nvram_directory(dev, index - 1);
3876 /* Create or re-write an NVM item: */
3877 if (bnxt_dir_type_is_executable(type))
3879 ext = eeprom->magic & 0xffff;
3880 ordinal = eeprom->offset >> 16;
3881 attr = eeprom->offset & 0xffff;
3883 return bnxt_flash_nvram(dev, type, ordinal, ext, attr, 0, data,
3887 static int bnxt_set_eee(struct net_device *dev, struct ethtool_keee *edata)
3889 struct bnxt *bp = netdev_priv(dev);
3890 struct ethtool_keee *eee = &bp->eee;
3891 struct bnxt_link_info *link_info = &bp->link_info;
3895 if (!BNXT_PHY_CFG_ABLE(bp))
3898 if (!(bp->phy_flags & BNXT_PHY_FL_EEE_CAP))
3901 mutex_lock(&bp->link_lock);
3902 advertising = _bnxt_fw_to_ethtool_adv_spds(link_info->advertising, 0);
3903 if (!edata->eee_enabled)
3906 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) {
3907 netdev_warn(dev, "EEE requires autoneg\n");
3911 if (edata->tx_lpi_enabled) {
3912 if (bp->lpi_tmr_hi && (edata->tx_lpi_timer > bp->lpi_tmr_hi ||
3913 edata->tx_lpi_timer < bp->lpi_tmr_lo)) {
3914 netdev_warn(dev, "Valid LPI timer range is %d and %d microsecs\n",
3915 bp->lpi_tmr_lo, bp->lpi_tmr_hi);
3918 } else if (!bp->lpi_tmr_hi) {
3919 edata->tx_lpi_timer = eee->tx_lpi_timer;
3922 if (!edata->advertised) {
3923 edata->advertised = advertising & eee->supported;
3924 } else if (edata->advertised & ~advertising) {
3925 netdev_warn(dev, "EEE advertised %x must be a subset of autoneg advertised speeds %x\n",
3926 edata->advertised, advertising);
3931 eee->advertised = edata->advertised;
3932 eee->tx_lpi_enabled = edata->tx_lpi_enabled;
3933 eee->tx_lpi_timer = edata->tx_lpi_timer;
3935 eee->eee_enabled = edata->eee_enabled;
3937 if (netif_running(dev))
3938 rc = bnxt_hwrm_set_link_setting(bp, false, true);
3941 mutex_unlock(&bp->link_lock);
3945 static int bnxt_get_eee(struct net_device *dev, struct ethtool_keee *edata)
3947 struct bnxt *bp = netdev_priv(dev);
3949 if (!(bp->phy_flags & BNXT_PHY_FL_EEE_CAP))
3953 if (!bp->eee.eee_enabled) {
3954 /* Preserve tx_lpi_timer so that the last value will be used
3955 * by default when it is re-enabled.
3957 edata->advertised = 0;
3958 edata->tx_lpi_enabled = 0;
3961 if (!bp->eee.eee_active)
3962 edata->lp_advertised = 0;
3967 static int bnxt_read_sfp_module_eeprom_info(struct bnxt *bp, u16 i2c_addr,
3968 u16 page_number, u8 bank,
3969 u16 start_addr, u16 data_length,
3972 struct hwrm_port_phy_i2c_read_output *output;
3973 struct hwrm_port_phy_i2c_read_input *req;
3974 int rc, byte_offset = 0;
3976 rc = hwrm_req_init(bp, req, HWRM_PORT_PHY_I2C_READ);
3980 output = hwrm_req_hold(bp, req);
3981 req->i2c_slave_addr = i2c_addr;
3982 req->page_number = cpu_to_le16(page_number);
3983 req->port_id = cpu_to_le16(bp->pf.port_id);
3987 xfer_size = min_t(u16, data_length, BNXT_MAX_PHY_I2C_RESP_SIZE);
3988 data_length -= xfer_size;
3989 req->page_offset = cpu_to_le16(start_addr + byte_offset);
3990 req->data_length = xfer_size;
3992 cpu_to_le32((start_addr + byte_offset ?
3993 PORT_PHY_I2C_READ_REQ_ENABLES_PAGE_OFFSET :
3996 PORT_PHY_I2C_READ_REQ_ENABLES_BANK_NUMBER :
3998 rc = hwrm_req_send(bp, req);
4000 memcpy(buf + byte_offset, output->data, xfer_size);
4001 byte_offset += xfer_size;
4002 } while (!rc && data_length > 0);
4003 hwrm_req_drop(bp, req);
4008 static int bnxt_get_module_info(struct net_device *dev,
4009 struct ethtool_modinfo *modinfo)
4011 u8 data[SFF_DIAG_SUPPORT_OFFSET + 1];
4012 struct bnxt *bp = netdev_priv(dev);
4015 /* No point in going further if phy status indicates
4016 * module is not inserted or if it is powered down or
4017 * if it is of type 10GBase-T
4019 if (bp->link_info.module_status >
4020 PORT_PHY_QCFG_RESP_MODULE_STATUS_WARNINGMSG)
4023 /* This feature is not supported in older firmware versions */
4024 if (bp->hwrm_spec_code < 0x10202)
4027 rc = bnxt_read_sfp_module_eeprom_info(bp, I2C_DEV_ADDR_A0, 0, 0, 0,
4028 SFF_DIAG_SUPPORT_OFFSET + 1,
4031 u8 module_id = data[0];
4032 u8 diag_supported = data[SFF_DIAG_SUPPORT_OFFSET];
4034 switch (module_id) {
4035 case SFF_MODULE_ID_SFP:
4036 modinfo->type = ETH_MODULE_SFF_8472;
4037 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN;
4038 if (!diag_supported)
4039 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN;
4041 case SFF_MODULE_ID_QSFP:
4042 case SFF_MODULE_ID_QSFP_PLUS:
4043 modinfo->type = ETH_MODULE_SFF_8436;
4044 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN;
4046 case SFF_MODULE_ID_QSFP28:
4047 modinfo->type = ETH_MODULE_SFF_8636;
4048 modinfo->eeprom_len = ETH_MODULE_SFF_8636_LEN;
4058 static int bnxt_get_module_eeprom(struct net_device *dev,
4059 struct ethtool_eeprom *eeprom,
4062 struct bnxt *bp = netdev_priv(dev);
4063 u16 start = eeprom->offset, length = eeprom->len;
4066 memset(data, 0, eeprom->len);
4068 /* Read A0 portion of the EEPROM */
4069 if (start < ETH_MODULE_SFF_8436_LEN) {
4070 if (start + eeprom->len > ETH_MODULE_SFF_8436_LEN)
4071 length = ETH_MODULE_SFF_8436_LEN - start;
4072 rc = bnxt_read_sfp_module_eeprom_info(bp, I2C_DEV_ADDR_A0, 0, 0,
4073 start, length, data);
4078 length = eeprom->len - length;
4081 /* Read A2 portion of the EEPROM */
4083 start -= ETH_MODULE_SFF_8436_LEN;
4084 rc = bnxt_read_sfp_module_eeprom_info(bp, I2C_DEV_ADDR_A2, 0, 0,
4085 start, length, data);
4090 static int bnxt_get_module_status(struct bnxt *bp, struct netlink_ext_ack *extack)
4092 if (bp->link_info.module_status <=
4093 PORT_PHY_QCFG_RESP_MODULE_STATUS_WARNINGMSG)
4096 switch (bp->link_info.module_status) {
4097 case PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN:
4098 NL_SET_ERR_MSG_MOD(extack, "Transceiver module is powering down");
4100 case PORT_PHY_QCFG_RESP_MODULE_STATUS_NOTINSERTED:
4101 NL_SET_ERR_MSG_MOD(extack, "Transceiver module not inserted");
4103 case PORT_PHY_QCFG_RESP_MODULE_STATUS_CURRENTFAULT:
4104 NL_SET_ERR_MSG_MOD(extack, "Transceiver module disabled due to current fault");
4107 NL_SET_ERR_MSG_MOD(extack, "Unknown error");
4113 static int bnxt_get_module_eeprom_by_page(struct net_device *dev,
4114 const struct ethtool_module_eeprom *page_data,
4115 struct netlink_ext_ack *extack)
4117 struct bnxt *bp = netdev_priv(dev);
4120 rc = bnxt_get_module_status(bp, extack);
4124 if (bp->hwrm_spec_code < 0x10202) {
4125 NL_SET_ERR_MSG_MOD(extack, "Firmware version too old");
4129 if (page_data->bank && !(bp->phy_flags & BNXT_PHY_FL_BANK_SEL)) {
4130 NL_SET_ERR_MSG_MOD(extack, "Firmware not capable for bank selection");
4134 rc = bnxt_read_sfp_module_eeprom_info(bp, page_data->i2c_address << 1,
4135 page_data->page, page_data->bank,
4140 NL_SET_ERR_MSG_MOD(extack, "Module`s eeprom read failed");
4143 return page_data->length;
4146 static int bnxt_nway_reset(struct net_device *dev)
4150 struct bnxt *bp = netdev_priv(dev);
4151 struct bnxt_link_info *link_info = &bp->link_info;
4153 if (!BNXT_PHY_CFG_ABLE(bp))
4156 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED))
4159 if (netif_running(dev))
4160 rc = bnxt_hwrm_set_link_setting(bp, true, false);
4165 static int bnxt_set_phys_id(struct net_device *dev,
4166 enum ethtool_phys_id_state state)
4168 struct hwrm_port_led_cfg_input *req;
4169 struct bnxt *bp = netdev_priv(dev);
4170 struct bnxt_pf_info *pf = &bp->pf;
4171 struct bnxt_led_cfg *led_cfg;
4176 if (!bp->num_leds || BNXT_VF(bp))
4179 if (state == ETHTOOL_ID_ACTIVE) {
4180 led_state = PORT_LED_CFG_REQ_LED0_STATE_BLINKALT;
4181 duration = cpu_to_le16(500);
4182 } else if (state == ETHTOOL_ID_INACTIVE) {
4183 led_state = PORT_LED_CFG_REQ_LED1_STATE_DEFAULT;
4184 duration = cpu_to_le16(0);
4188 rc = hwrm_req_init(bp, req, HWRM_PORT_LED_CFG);
4192 req->port_id = cpu_to_le16(pf->port_id);
4193 req->num_leds = bp->num_leds;
4194 led_cfg = (struct bnxt_led_cfg *)&req->led0_id;
4195 for (i = 0; i < bp->num_leds; i++, led_cfg++) {
4196 req->enables |= BNXT_LED_DFLT_ENABLES(i);
4197 led_cfg->led_id = bp->leds[i].led_id;
4198 led_cfg->led_state = led_state;
4199 led_cfg->led_blink_on = duration;
4200 led_cfg->led_blink_off = duration;
4201 led_cfg->led_group_id = bp->leds[i].led_group_id;
4203 return hwrm_req_send(bp, req);
4206 static int bnxt_hwrm_selftest_irq(struct bnxt *bp, u16 cmpl_ring)
4208 struct hwrm_selftest_irq_input *req;
4211 rc = hwrm_req_init(bp, req, HWRM_SELFTEST_IRQ);
4215 req->cmpl_ring = cpu_to_le16(cmpl_ring);
4216 return hwrm_req_send(bp, req);
4219 static int bnxt_test_irq(struct bnxt *bp)
4223 for (i = 0; i < bp->cp_nr_rings; i++) {
4224 u16 cmpl_ring = bp->grp_info[i].cp_fw_ring_id;
4227 rc = bnxt_hwrm_selftest_irq(bp, cmpl_ring);
4234 static int bnxt_hwrm_mac_loopback(struct bnxt *bp, bool enable)
4236 struct hwrm_port_mac_cfg_input *req;
4239 rc = hwrm_req_init(bp, req, HWRM_PORT_MAC_CFG);
4243 req->enables = cpu_to_le32(PORT_MAC_CFG_REQ_ENABLES_LPBK);
4245 req->lpbk = PORT_MAC_CFG_REQ_LPBK_LOCAL;
4247 req->lpbk = PORT_MAC_CFG_REQ_LPBK_NONE;
4248 return hwrm_req_send(bp, req);
4251 static int bnxt_query_force_speeds(struct bnxt *bp, u16 *force_speeds)
4253 struct hwrm_port_phy_qcaps_output *resp;
4254 struct hwrm_port_phy_qcaps_input *req;
4257 rc = hwrm_req_init(bp, req, HWRM_PORT_PHY_QCAPS);
4261 resp = hwrm_req_hold(bp, req);
4262 rc = hwrm_req_send(bp, req);
4264 *force_speeds = le16_to_cpu(resp->supported_speeds_force_mode);
4266 hwrm_req_drop(bp, req);
4270 static int bnxt_disable_an_for_lpbk(struct bnxt *bp,
4271 struct hwrm_port_phy_cfg_input *req)
4273 struct bnxt_link_info *link_info = &bp->link_info;
4278 if (!link_info->autoneg ||
4279 (bp->phy_flags & BNXT_PHY_FL_AN_PHY_LPBK))
4282 rc = bnxt_query_force_speeds(bp, &fw_advertising);
4286 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_1GB;
4287 if (BNXT_LINK_IS_UP(bp))
4288 fw_speed = bp->link_info.link_speed;
4289 else if (fw_advertising & BNXT_LINK_SPEED_MSK_10GB)
4290 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10GB;
4291 else if (fw_advertising & BNXT_LINK_SPEED_MSK_25GB)
4292 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_25GB;
4293 else if (fw_advertising & BNXT_LINK_SPEED_MSK_40GB)
4294 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_40GB;
4295 else if (fw_advertising & BNXT_LINK_SPEED_MSK_50GB)
4296 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_50GB;
4298 req->force_link_speed = cpu_to_le16(fw_speed);
4299 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_FORCE |
4300 PORT_PHY_CFG_REQ_FLAGS_RESET_PHY);
4301 rc = hwrm_req_send(bp, req);
4303 req->force_link_speed = cpu_to_le16(0);
4307 static int bnxt_hwrm_phy_loopback(struct bnxt *bp, bool enable, bool ext)
4309 struct hwrm_port_phy_cfg_input *req;
4312 rc = hwrm_req_init(bp, req, HWRM_PORT_PHY_CFG);
4316 /* prevent bnxt_disable_an_for_lpbk() from consuming the request */
4317 hwrm_req_hold(bp, req);
4320 bnxt_disable_an_for_lpbk(bp, req);
4322 req->lpbk = PORT_PHY_CFG_REQ_LPBK_EXTERNAL;
4324 req->lpbk = PORT_PHY_CFG_REQ_LPBK_LOCAL;
4326 req->lpbk = PORT_PHY_CFG_REQ_LPBK_NONE;
4328 req->enables = cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_LPBK);
4329 rc = hwrm_req_send(bp, req);
4330 hwrm_req_drop(bp, req);
4334 static int bnxt_rx_loopback(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
4335 u32 raw_cons, int pkt_size)
4337 struct bnxt_napi *bnapi = cpr->bnapi;
4338 struct bnxt_rx_ring_info *rxr;
4339 struct bnxt_sw_rx_bd *rx_buf;
4340 struct rx_cmp *rxcmp;
4346 rxr = bnapi->rx_ring;
4347 cp_cons = RING_CMP(raw_cons);
4348 rxcmp = (struct rx_cmp *)
4349 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
4350 cons = rxcmp->rx_cmp_opaque;
4351 rx_buf = &rxr->rx_buf_ring[cons];
4352 data = rx_buf->data_ptr;
4353 len = le32_to_cpu(rxcmp->rx_cmp_len_flags_type) >> RX_CMP_LEN_SHIFT;
4354 if (len != pkt_size)
4357 if (!ether_addr_equal(data + i, bnapi->bp->dev->dev_addr))
4360 for ( ; i < pkt_size; i++) {
4361 if (data[i] != (u8)(i & 0xff))
4367 static int bnxt_poll_loopback(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
4370 struct tx_cmp *txcmp;
4376 raw_cons = cpr->cp_raw_cons;
4377 for (i = 0; i < 200; i++) {
4378 cons = RING_CMP(raw_cons);
4379 txcmp = &cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)];
4381 if (!TX_CMP_VALID(txcmp, raw_cons)) {
4386 /* The valid test of the entry must be done first before
4387 * reading any further.
4390 if (TX_CMP_TYPE(txcmp) == CMP_TYPE_RX_L2_CMP ||
4391 TX_CMP_TYPE(txcmp) == CMP_TYPE_RX_L2_V3_CMP) {
4392 rc = bnxt_rx_loopback(bp, cpr, raw_cons, pkt_size);
4393 raw_cons = NEXT_RAW_CMP(raw_cons);
4394 raw_cons = NEXT_RAW_CMP(raw_cons);
4397 raw_cons = NEXT_RAW_CMP(raw_cons);
4399 cpr->cp_raw_cons = raw_cons;
4403 static int bnxt_run_loopback(struct bnxt *bp)
4405 struct bnxt_tx_ring_info *txr = &bp->tx_ring[0];
4406 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[0];
4407 struct bnxt_cp_ring_info *cpr;
4408 int pkt_size, i = 0;
4409 struct sk_buff *skb;
4414 cpr = &rxr->bnapi->cp_ring;
4415 if (bp->flags & BNXT_FLAG_CHIP_P5_PLUS)
4417 pkt_size = min(bp->dev->mtu + ETH_HLEN, bp->rx_copy_thresh);
4418 skb = netdev_alloc_skb(bp->dev, pkt_size);
4421 data = skb_put(skb, pkt_size);
4422 ether_addr_copy(&data[i], bp->dev->dev_addr);
4424 ether_addr_copy(&data[i], bp->dev->dev_addr);
4426 for ( ; i < pkt_size; i++)
4427 data[i] = (u8)(i & 0xff);
4429 map = dma_map_single(&bp->pdev->dev, skb->data, pkt_size,
4431 if (dma_mapping_error(&bp->pdev->dev, map)) {
4435 bnxt_xmit_bd(bp, txr, map, pkt_size, NULL);
4437 /* Sync BD data before updating doorbell */
4440 bnxt_db_write(bp, &txr->tx_db, txr->tx_prod);
4441 rc = bnxt_poll_loopback(bp, cpr, pkt_size);
4443 dma_unmap_single(&bp->pdev->dev, map, pkt_size, DMA_TO_DEVICE);
4448 static int bnxt_run_fw_tests(struct bnxt *bp, u8 test_mask, u8 *test_results)
4450 struct hwrm_selftest_exec_output *resp;
4451 struct hwrm_selftest_exec_input *req;
4454 rc = hwrm_req_init(bp, req, HWRM_SELFTEST_EXEC);
4458 hwrm_req_timeout(bp, req, bp->test_info->timeout);
4459 req->flags = test_mask;
4461 resp = hwrm_req_hold(bp, req);
4462 rc = hwrm_req_send(bp, req);
4463 *test_results = resp->test_success;
4464 hwrm_req_drop(bp, req);
4468 #define BNXT_DRV_TESTS 4
4469 #define BNXT_MACLPBK_TEST_IDX (bp->num_tests - BNXT_DRV_TESTS)
4470 #define BNXT_PHYLPBK_TEST_IDX (BNXT_MACLPBK_TEST_IDX + 1)
4471 #define BNXT_EXTLPBK_TEST_IDX (BNXT_MACLPBK_TEST_IDX + 2)
4472 #define BNXT_IRQ_TEST_IDX (BNXT_MACLPBK_TEST_IDX + 3)
4474 static void bnxt_self_test(struct net_device *dev, struct ethtool_test *etest,
4477 struct bnxt *bp = netdev_priv(dev);
4478 bool do_ext_lpbk = false;
4479 bool offline = false;
4480 u8 test_results = 0;
4484 if (!bp->num_tests || !BNXT_PF(bp))
4486 memset(buf, 0, sizeof(u64) * bp->num_tests);
4487 if (!netif_running(dev)) {
4488 etest->flags |= ETH_TEST_FL_FAILED;
4492 if ((etest->flags & ETH_TEST_FL_EXTERNAL_LB) &&
4493 (bp->phy_flags & BNXT_PHY_FL_EXT_LPBK))
4496 if (etest->flags & ETH_TEST_FL_OFFLINE) {
4497 if (bp->pf.active_vfs || !BNXT_SINGLE_PF(bp)) {
4498 etest->flags |= ETH_TEST_FL_FAILED;
4499 netdev_warn(dev, "Offline tests cannot be run with active VFs or on shared PF\n");
4505 for (i = 0; i < bp->num_tests - BNXT_DRV_TESTS; i++) {
4506 u8 bit_val = 1 << i;
4508 if (!(bp->test_info->offline_mask & bit_val))
4509 test_mask |= bit_val;
4511 test_mask |= bit_val;
4514 bnxt_run_fw_tests(bp, test_mask, &test_results);
4517 bnxt_close_nic(bp, true, false);
4518 bnxt_run_fw_tests(bp, test_mask, &test_results);
4520 buf[BNXT_MACLPBK_TEST_IDX] = 1;
4521 bnxt_hwrm_mac_loopback(bp, true);
4523 rc = bnxt_half_open_nic(bp);
4525 bnxt_hwrm_mac_loopback(bp, false);
4526 etest->flags |= ETH_TEST_FL_FAILED;
4527 bnxt_ulp_start(bp, rc);
4530 if (bnxt_run_loopback(bp))
4531 etest->flags |= ETH_TEST_FL_FAILED;
4533 buf[BNXT_MACLPBK_TEST_IDX] = 0;
4535 bnxt_hwrm_mac_loopback(bp, false);
4536 bnxt_hwrm_phy_loopback(bp, true, false);
4538 if (bnxt_run_loopback(bp)) {
4539 buf[BNXT_PHYLPBK_TEST_IDX] = 1;
4540 etest->flags |= ETH_TEST_FL_FAILED;
4543 etest->flags |= ETH_TEST_FL_EXTERNAL_LB_DONE;
4544 bnxt_hwrm_phy_loopback(bp, true, true);
4546 if (bnxt_run_loopback(bp)) {
4547 buf[BNXT_EXTLPBK_TEST_IDX] = 1;
4548 etest->flags |= ETH_TEST_FL_FAILED;
4551 bnxt_hwrm_phy_loopback(bp, false, false);
4552 bnxt_half_close_nic(bp);
4553 rc = bnxt_open_nic(bp, true, true);
4554 bnxt_ulp_start(bp, rc);
4556 if (rc || bnxt_test_irq(bp)) {
4557 buf[BNXT_IRQ_TEST_IDX] = 1;
4558 etest->flags |= ETH_TEST_FL_FAILED;
4560 for (i = 0; i < bp->num_tests - BNXT_DRV_TESTS; i++) {
4561 u8 bit_val = 1 << i;
4563 if ((test_mask & bit_val) && !(test_results & bit_val)) {
4565 etest->flags |= ETH_TEST_FL_FAILED;
4570 static int bnxt_reset(struct net_device *dev, u32 *flags)
4572 struct bnxt *bp = netdev_priv(dev);
4573 bool reload = false;
4580 netdev_err(dev, "Reset is not supported from a VF\n");
4584 if (pci_vfs_assigned(bp->pdev) &&
4585 !(bp->fw_cap & BNXT_FW_CAP_HOT_RESET)) {
4587 "Reset not allowed when VFs are assigned to VMs\n");
4591 if ((req & BNXT_FW_RESET_CHIP) == BNXT_FW_RESET_CHIP) {
4592 /* This feature is not supported in older firmware versions */
4593 if (bp->hwrm_spec_code >= 0x10803) {
4594 if (!bnxt_firmware_reset_chip(dev)) {
4595 netdev_info(dev, "Firmware reset request successful.\n");
4596 if (!(bp->fw_cap & BNXT_FW_CAP_HOT_RESET))
4598 *flags &= ~BNXT_FW_RESET_CHIP;
4600 } else if (req == BNXT_FW_RESET_CHIP) {
4601 return -EOPNOTSUPP; /* only request, fail hard */
4605 if (!BNXT_CHIP_P4_PLUS(bp) && (req & BNXT_FW_RESET_AP)) {
4606 /* This feature is not supported in older firmware versions */
4607 if (bp->hwrm_spec_code >= 0x10803) {
4608 if (!bnxt_firmware_reset_ap(dev)) {
4609 netdev_info(dev, "Reset application processor successful.\n");
4611 *flags &= ~BNXT_FW_RESET_AP;
4613 } else if (req == BNXT_FW_RESET_AP) {
4614 return -EOPNOTSUPP; /* only request, fail hard */
4619 netdev_info(dev, "Reload driver to complete reset\n");
4624 static int bnxt_set_dump(struct net_device *dev, struct ethtool_dump *dump)
4626 struct bnxt *bp = netdev_priv(dev);
4628 if (dump->flag > BNXT_DUMP_CRASH) {
4629 netdev_info(dev, "Supports only Live(0) and Crash(1) dumps.\n");
4633 if (!IS_ENABLED(CONFIG_TEE_BNXT_FW) && dump->flag == BNXT_DUMP_CRASH) {
4634 netdev_info(dev, "Cannot collect crash dump as TEE_BNXT_FW config option is not enabled.\n");
4638 bp->dump_flag = dump->flag;
4642 static int bnxt_get_dump_flag(struct net_device *dev, struct ethtool_dump *dump)
4644 struct bnxt *bp = netdev_priv(dev);
4646 if (bp->hwrm_spec_code < 0x10801)
4649 dump->version = bp->ver_resp.hwrm_fw_maj_8b << 24 |
4650 bp->ver_resp.hwrm_fw_min_8b << 16 |
4651 bp->ver_resp.hwrm_fw_bld_8b << 8 |
4652 bp->ver_resp.hwrm_fw_rsvd_8b;
4654 dump->flag = bp->dump_flag;
4655 dump->len = bnxt_get_coredump_length(bp, bp->dump_flag);
4659 static int bnxt_get_dump_data(struct net_device *dev, struct ethtool_dump *dump,
4662 struct bnxt *bp = netdev_priv(dev);
4664 if (bp->hwrm_spec_code < 0x10801)
4667 memset(buf, 0, dump->len);
4669 dump->flag = bp->dump_flag;
4670 return bnxt_get_coredump(bp, dump->flag, buf, &dump->len);
4673 static int bnxt_get_ts_info(struct net_device *dev,
4674 struct ethtool_ts_info *info)
4676 struct bnxt *bp = netdev_priv(dev);
4677 struct bnxt_ptp_cfg *ptp;
4680 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE |
4681 SOF_TIMESTAMPING_RX_SOFTWARE |
4682 SOF_TIMESTAMPING_SOFTWARE;
4684 info->phc_index = -1;
4688 info->so_timestamping |= SOF_TIMESTAMPING_TX_HARDWARE |
4689 SOF_TIMESTAMPING_RX_HARDWARE |
4690 SOF_TIMESTAMPING_RAW_HARDWARE;
4692 info->phc_index = ptp_clock_index(ptp->ptp_clock);
4694 info->tx_types = (1 << HWTSTAMP_TX_OFF) | (1 << HWTSTAMP_TX_ON);
4696 info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) |
4697 (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) |
4698 (1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT);
4700 if (bp->fw_cap & BNXT_FW_CAP_RX_ALL_PKT_TS)
4701 info->rx_filters |= (1 << HWTSTAMP_FILTER_ALL);
4705 void bnxt_ethtool_init(struct bnxt *bp)
4707 struct hwrm_selftest_qlist_output *resp;
4708 struct hwrm_selftest_qlist_input *req;
4709 struct bnxt_test_info *test_info;
4710 struct net_device *dev = bp->dev;
4713 if (!(bp->fw_cap & BNXT_FW_CAP_PKG_VER))
4714 bnxt_get_pkgver(dev);
4717 if (bp->hwrm_spec_code < 0x10704 || !BNXT_PF(bp))
4720 test_info = bp->test_info;
4722 test_info = kzalloc(sizeof(*bp->test_info), GFP_KERNEL);
4725 bp->test_info = test_info;
4728 if (hwrm_req_init(bp, req, HWRM_SELFTEST_QLIST))
4731 resp = hwrm_req_hold(bp, req);
4732 rc = hwrm_req_send_silent(bp, req);
4734 goto ethtool_init_exit;
4736 bp->num_tests = resp->num_tests + BNXT_DRV_TESTS;
4737 if (bp->num_tests > BNXT_MAX_TEST)
4738 bp->num_tests = BNXT_MAX_TEST;
4740 test_info->offline_mask = resp->offline_tests;
4741 test_info->timeout = le16_to_cpu(resp->test_timeout);
4742 if (!test_info->timeout)
4743 test_info->timeout = HWRM_CMD_TIMEOUT;
4744 for (i = 0; i < bp->num_tests; i++) {
4745 char *str = test_info->string[i];
4746 char *fw_str = resp->test_name[i];
4748 if (i == BNXT_MACLPBK_TEST_IDX) {
4749 strcpy(str, "Mac loopback test (offline)");
4750 } else if (i == BNXT_PHYLPBK_TEST_IDX) {
4751 strcpy(str, "Phy loopback test (offline)");
4752 } else if (i == BNXT_EXTLPBK_TEST_IDX) {
4753 strcpy(str, "Ext loopback test (offline)");
4754 } else if (i == BNXT_IRQ_TEST_IDX) {
4755 strcpy(str, "Interrupt_test (offline)");
4757 snprintf(str, ETH_GSTRING_LEN, "%s test (%s)",
4758 fw_str, test_info->offline_mask & (1 << i) ?
4759 "offline" : "online");
4764 hwrm_req_drop(bp, req);
4767 static void bnxt_get_eth_phy_stats(struct net_device *dev,
4768 struct ethtool_eth_phy_stats *phy_stats)
4770 struct bnxt *bp = netdev_priv(dev);
4773 if (BNXT_VF(bp) || !(bp->flags & BNXT_FLAG_PORT_STATS_EXT))
4776 rx = bp->rx_port_stats_ext.sw_stats;
4777 phy_stats->SymbolErrorDuringCarrier =
4778 *(rx + BNXT_RX_STATS_EXT_OFFSET(rx_pcs_symbol_err));
4781 static void bnxt_get_eth_mac_stats(struct net_device *dev,
4782 struct ethtool_eth_mac_stats *mac_stats)
4784 struct bnxt *bp = netdev_priv(dev);
4787 if (BNXT_VF(bp) || !(bp->flags & BNXT_FLAG_PORT_STATS))
4790 rx = bp->port_stats.sw_stats;
4791 tx = bp->port_stats.sw_stats + BNXT_TX_PORT_STATS_BYTE_OFFSET / 8;
4793 mac_stats->FramesReceivedOK =
4794 BNXT_GET_RX_PORT_STATS64(rx, rx_good_frames);
4795 mac_stats->FramesTransmittedOK =
4796 BNXT_GET_TX_PORT_STATS64(tx, tx_good_frames);
4797 mac_stats->FrameCheckSequenceErrors =
4798 BNXT_GET_RX_PORT_STATS64(rx, rx_fcs_err_frames);
4799 mac_stats->AlignmentErrors =
4800 BNXT_GET_RX_PORT_STATS64(rx, rx_align_err_frames);
4801 mac_stats->OutOfRangeLengthField =
4802 BNXT_GET_RX_PORT_STATS64(rx, rx_oor_len_frames);
4805 static void bnxt_get_eth_ctrl_stats(struct net_device *dev,
4806 struct ethtool_eth_ctrl_stats *ctrl_stats)
4808 struct bnxt *bp = netdev_priv(dev);
4811 if (BNXT_VF(bp) || !(bp->flags & BNXT_FLAG_PORT_STATS))
4814 rx = bp->port_stats.sw_stats;
4815 ctrl_stats->MACControlFramesReceived =
4816 BNXT_GET_RX_PORT_STATS64(rx, rx_ctrl_frames);
4819 static const struct ethtool_rmon_hist_range bnxt_rmon_ranges[] = {
4833 static void bnxt_get_rmon_stats(struct net_device *dev,
4834 struct ethtool_rmon_stats *rmon_stats,
4835 const struct ethtool_rmon_hist_range **ranges)
4837 struct bnxt *bp = netdev_priv(dev);
4840 if (BNXT_VF(bp) || !(bp->flags & BNXT_FLAG_PORT_STATS))
4843 rx = bp->port_stats.sw_stats;
4844 tx = bp->port_stats.sw_stats + BNXT_TX_PORT_STATS_BYTE_OFFSET / 8;
4846 rmon_stats->jabbers =
4847 BNXT_GET_RX_PORT_STATS64(rx, rx_jbr_frames);
4848 rmon_stats->oversize_pkts =
4849 BNXT_GET_RX_PORT_STATS64(rx, rx_ovrsz_frames);
4850 rmon_stats->undersize_pkts =
4851 BNXT_GET_RX_PORT_STATS64(rx, rx_undrsz_frames);
4853 rmon_stats->hist[0] = BNXT_GET_RX_PORT_STATS64(rx, rx_64b_frames);
4854 rmon_stats->hist[1] = BNXT_GET_RX_PORT_STATS64(rx, rx_65b_127b_frames);
4855 rmon_stats->hist[2] = BNXT_GET_RX_PORT_STATS64(rx, rx_128b_255b_frames);
4856 rmon_stats->hist[3] = BNXT_GET_RX_PORT_STATS64(rx, rx_256b_511b_frames);
4857 rmon_stats->hist[4] =
4858 BNXT_GET_RX_PORT_STATS64(rx, rx_512b_1023b_frames);
4859 rmon_stats->hist[5] =
4860 BNXT_GET_RX_PORT_STATS64(rx, rx_1024b_1518b_frames);
4861 rmon_stats->hist[6] =
4862 BNXT_GET_RX_PORT_STATS64(rx, rx_1519b_2047b_frames);
4863 rmon_stats->hist[7] =
4864 BNXT_GET_RX_PORT_STATS64(rx, rx_2048b_4095b_frames);
4865 rmon_stats->hist[8] =
4866 BNXT_GET_RX_PORT_STATS64(rx, rx_4096b_9216b_frames);
4867 rmon_stats->hist[9] =
4868 BNXT_GET_RX_PORT_STATS64(rx, rx_9217b_16383b_frames);
4870 rmon_stats->hist_tx[0] =
4871 BNXT_GET_TX_PORT_STATS64(tx, tx_64b_frames);
4872 rmon_stats->hist_tx[1] =
4873 BNXT_GET_TX_PORT_STATS64(tx, tx_65b_127b_frames);
4874 rmon_stats->hist_tx[2] =
4875 BNXT_GET_TX_PORT_STATS64(tx, tx_128b_255b_frames);
4876 rmon_stats->hist_tx[3] =
4877 BNXT_GET_TX_PORT_STATS64(tx, tx_256b_511b_frames);
4878 rmon_stats->hist_tx[4] =
4879 BNXT_GET_TX_PORT_STATS64(tx, tx_512b_1023b_frames);
4880 rmon_stats->hist_tx[5] =
4881 BNXT_GET_TX_PORT_STATS64(tx, tx_1024b_1518b_frames);
4882 rmon_stats->hist_tx[6] =
4883 BNXT_GET_TX_PORT_STATS64(tx, tx_1519b_2047b_frames);
4884 rmon_stats->hist_tx[7] =
4885 BNXT_GET_TX_PORT_STATS64(tx, tx_2048b_4095b_frames);
4886 rmon_stats->hist_tx[8] =
4887 BNXT_GET_TX_PORT_STATS64(tx, tx_4096b_9216b_frames);
4888 rmon_stats->hist_tx[9] =
4889 BNXT_GET_TX_PORT_STATS64(tx, tx_9217b_16383b_frames);
4891 *ranges = bnxt_rmon_ranges;
4894 static void bnxt_get_link_ext_stats(struct net_device *dev,
4895 struct ethtool_link_ext_stats *stats)
4897 struct bnxt *bp = netdev_priv(dev);
4900 if (BNXT_VF(bp) || !(bp->flags & BNXT_FLAG_PORT_STATS_EXT))
4903 rx = bp->rx_port_stats_ext.sw_stats;
4904 stats->link_down_events =
4905 *(rx + BNXT_RX_STATS_EXT_OFFSET(link_down_events));
4908 void bnxt_ethtool_free(struct bnxt *bp)
4910 kfree(bp->test_info);
4911 bp->test_info = NULL;
4914 const struct ethtool_ops bnxt_ethtool_ops = {
4915 .cap_link_lanes_supported = 1,
4916 .supported_coalesce_params = ETHTOOL_COALESCE_USECS |
4917 ETHTOOL_COALESCE_MAX_FRAMES |
4918 ETHTOOL_COALESCE_USECS_IRQ |
4919 ETHTOOL_COALESCE_MAX_FRAMES_IRQ |
4920 ETHTOOL_COALESCE_STATS_BLOCK_USECS |
4921 ETHTOOL_COALESCE_USE_ADAPTIVE_RX |
4922 ETHTOOL_COALESCE_USE_CQE,
4923 .get_link_ksettings = bnxt_get_link_ksettings,
4924 .set_link_ksettings = bnxt_set_link_ksettings,
4925 .get_fec_stats = bnxt_get_fec_stats,
4926 .get_fecparam = bnxt_get_fecparam,
4927 .set_fecparam = bnxt_set_fecparam,
4928 .get_pause_stats = bnxt_get_pause_stats,
4929 .get_pauseparam = bnxt_get_pauseparam,
4930 .set_pauseparam = bnxt_set_pauseparam,
4931 .get_drvinfo = bnxt_get_drvinfo,
4932 .get_regs_len = bnxt_get_regs_len,
4933 .get_regs = bnxt_get_regs,
4934 .get_wol = bnxt_get_wol,
4935 .set_wol = bnxt_set_wol,
4936 .get_coalesce = bnxt_get_coalesce,
4937 .set_coalesce = bnxt_set_coalesce,
4938 .get_msglevel = bnxt_get_msglevel,
4939 .set_msglevel = bnxt_set_msglevel,
4940 .get_sset_count = bnxt_get_sset_count,
4941 .get_strings = bnxt_get_strings,
4942 .get_ethtool_stats = bnxt_get_ethtool_stats,
4943 .set_ringparam = bnxt_set_ringparam,
4944 .get_ringparam = bnxt_get_ringparam,
4945 .get_channels = bnxt_get_channels,
4946 .set_channels = bnxt_set_channels,
4947 .get_rxnfc = bnxt_get_rxnfc,
4948 .set_rxnfc = bnxt_set_rxnfc,
4949 .get_rxfh_indir_size = bnxt_get_rxfh_indir_size,
4950 .get_rxfh_key_size = bnxt_get_rxfh_key_size,
4951 .get_rxfh = bnxt_get_rxfh,
4952 .set_rxfh = bnxt_set_rxfh,
4953 .flash_device = bnxt_flash_device,
4954 .get_eeprom_len = bnxt_get_eeprom_len,
4955 .get_eeprom = bnxt_get_eeprom,
4956 .set_eeprom = bnxt_set_eeprom,
4957 .get_link = bnxt_get_link,
4958 .get_link_ext_stats = bnxt_get_link_ext_stats,
4959 .get_eee = bnxt_get_eee,
4960 .set_eee = bnxt_set_eee,
4961 .get_module_info = bnxt_get_module_info,
4962 .get_module_eeprom = bnxt_get_module_eeprom,
4963 .get_module_eeprom_by_page = bnxt_get_module_eeprom_by_page,
4964 .nway_reset = bnxt_nway_reset,
4965 .set_phys_id = bnxt_set_phys_id,
4966 .self_test = bnxt_self_test,
4967 .get_ts_info = bnxt_get_ts_info,
4968 .reset = bnxt_reset,
4969 .set_dump = bnxt_set_dump,
4970 .get_dump_flag = bnxt_get_dump_flag,
4971 .get_dump_data = bnxt_get_dump_data,
4972 .get_eth_phy_stats = bnxt_get_eth_phy_stats,
4973 .get_eth_mac_stats = bnxt_get_eth_mac_stats,
4974 .get_eth_ctrl_stats = bnxt_get_eth_ctrl_stats,
4975 .get_rmon_stats = bnxt_get_rmon_stats,