1 /* Broadcom NetXtreme-C/E network driver.
3 * Copyright (c) 2014-2015 Broadcom Corporation
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
13 #define DRV_MODULE_NAME "bnxt_en"
14 #define DRV_MODULE_VERSION "1.0.0"
21 __le32 tx_bd_len_flags_type;
22 #define TX_BD_TYPE (0x3f << 0)
23 #define TX_BD_TYPE_SHORT_TX_BD (0x00 << 0)
24 #define TX_BD_TYPE_LONG_TX_BD (0x10 << 0)
25 #define TX_BD_FLAGS_PACKET_END (1 << 6)
26 #define TX_BD_FLAGS_NO_CMPL (1 << 7)
27 #define TX_BD_FLAGS_BD_CNT (0x1f << 8)
28 #define TX_BD_FLAGS_BD_CNT_SHIFT 8
29 #define TX_BD_FLAGS_LHINT (3 << 13)
30 #define TX_BD_FLAGS_LHINT_SHIFT 13
31 #define TX_BD_FLAGS_LHINT_512_AND_SMALLER (0 << 13)
32 #define TX_BD_FLAGS_LHINT_512_TO_1023 (1 << 13)
33 #define TX_BD_FLAGS_LHINT_1024_TO_2047 (2 << 13)
34 #define TX_BD_FLAGS_LHINT_2048_AND_LARGER (3 << 13)
35 #define TX_BD_FLAGS_COAL_NOW (1 << 15)
36 #define TX_BD_LEN (0xffff << 16)
37 #define TX_BD_LEN_SHIFT 16
44 __le32 tx_bd_hsize_lflags;
45 #define TX_BD_FLAGS_TCP_UDP_CHKSUM (1 << 0)
46 #define TX_BD_FLAGS_IP_CKSUM (1 << 1)
47 #define TX_BD_FLAGS_NO_CRC (1 << 2)
48 #define TX_BD_FLAGS_STAMP (1 << 3)
49 #define TX_BD_FLAGS_T_IP_CHKSUM (1 << 4)
50 #define TX_BD_FLAGS_LSO (1 << 5)
51 #define TX_BD_FLAGS_IPID_FMT (1 << 6)
52 #define TX_BD_FLAGS_T_IPID (1 << 7)
53 #define TX_BD_HSIZE (0xff << 16)
54 #define TX_BD_HSIZE_SHIFT 16
57 __le32 tx_bd_cfa_action;
58 #define TX_BD_CFA_ACTION (0xffff << 16)
59 #define TX_BD_CFA_ACTION_SHIFT 16
61 __le32 tx_bd_cfa_meta;
62 #define TX_BD_CFA_META_MASK 0xfffffff
63 #define TX_BD_CFA_META_VID_MASK 0xfff
64 #define TX_BD_CFA_META_PRI_MASK (0xf << 12)
65 #define TX_BD_CFA_META_PRI_SHIFT 12
66 #define TX_BD_CFA_META_TPID_MASK (3 << 16)
67 #define TX_BD_CFA_META_TPID_SHIFT 16
68 #define TX_BD_CFA_META_KEY (0xf << 28)
69 #define TX_BD_CFA_META_KEY_SHIFT 28
70 #define TX_BD_CFA_META_KEY_VLAN (1 << 28)
74 __le32 rx_bd_len_flags_type;
75 #define RX_BD_TYPE (0x3f << 0)
76 #define RX_BD_TYPE_RX_PACKET_BD 0x4
77 #define RX_BD_TYPE_RX_BUFFER_BD 0x5
78 #define RX_BD_TYPE_RX_AGG_BD 0x6
79 #define RX_BD_TYPE_16B_BD_SIZE (0 << 4)
80 #define RX_BD_TYPE_32B_BD_SIZE (1 << 4)
81 #define RX_BD_TYPE_48B_BD_SIZE (2 << 4)
82 #define RX_BD_TYPE_64B_BD_SIZE (3 << 4)
83 #define RX_BD_FLAGS_SOP (1 << 6)
84 #define RX_BD_FLAGS_EOP (1 << 7)
85 #define RX_BD_FLAGS_BUFFERS (3 << 8)
86 #define RX_BD_FLAGS_1_BUFFER_PACKET (0 << 8)
87 #define RX_BD_FLAGS_2_BUFFER_PACKET (1 << 8)
88 #define RX_BD_FLAGS_3_BUFFER_PACKET (2 << 8)
89 #define RX_BD_FLAGS_4_BUFFER_PACKET (3 << 8)
90 #define RX_BD_LEN (0xffff << 16)
91 #define RX_BD_LEN_SHIFT 16
98 __le32 tx_cmp_flags_type;
99 #define CMP_TYPE (0x3f << 0)
100 #define CMP_TYPE_TX_L2_CMP 0
101 #define CMP_TYPE_RX_L2_CMP 17
102 #define CMP_TYPE_RX_AGG_CMP 18
103 #define CMP_TYPE_RX_L2_TPA_START_CMP 19
104 #define CMP_TYPE_RX_L2_TPA_END_CMP 21
105 #define CMP_TYPE_STATUS_CMP 32
106 #define CMP_TYPE_REMOTE_DRIVER_REQ 34
107 #define CMP_TYPE_REMOTE_DRIVER_RESP 36
108 #define CMP_TYPE_ERROR_STATUS 48
109 #define CMPL_BASE_TYPE_STAT_EJECT (0x1aUL << 0)
110 #define CMPL_BASE_TYPE_HWRM_DONE (0x20UL << 0)
111 #define CMPL_BASE_TYPE_HWRM_FWD_REQ (0x22UL << 0)
112 #define CMPL_BASE_TYPE_HWRM_FWD_RESP (0x24UL << 0)
113 #define CMPL_BASE_TYPE_HWRM_ASYNC_EVENT (0x2eUL << 0)
115 #define TX_CMP_FLAGS_ERROR (1 << 6)
116 #define TX_CMP_FLAGS_PUSH (1 << 7)
119 __le32 tx_cmp_errors_v;
120 #define TX_CMP_V (1 << 0)
121 #define TX_CMP_ERRORS_BUFFER_ERROR (7 << 1)
122 #define TX_CMP_ERRORS_BUFFER_ERROR_NO_ERROR 0
123 #define TX_CMP_ERRORS_BUFFER_ERROR_BAD_FORMAT 2
124 #define TX_CMP_ERRORS_BUFFER_ERROR_INVALID_STAG 4
125 #define TX_CMP_ERRORS_BUFFER_ERROR_STAG_BOUNDS 5
126 #define TX_CMP_ERRORS_ZERO_LENGTH_PKT (1 << 4)
127 #define TX_CMP_ERRORS_EXCESSIVE_BD_LEN (1 << 5)
128 #define TX_CMP_ERRORS_DMA_ERROR (1 << 6)
129 #define TX_CMP_ERRORS_HINT_TOO_SHORT (1 << 7)
131 __le32 tx_cmp_unsed_3;
135 __le32 rx_cmp_len_flags_type;
136 #define RX_CMP_CMP_TYPE (0x3f << 0)
137 #define RX_CMP_FLAGS_ERROR (1 << 6)
138 #define RX_CMP_FLAGS_PLACEMENT (7 << 7)
139 #define RX_CMP_FLAGS_RSS_VALID (1 << 10)
140 #define RX_CMP_FLAGS_UNUSED (1 << 11)
141 #define RX_CMP_FLAGS_ITYPES_SHIFT 12
142 #define RX_CMP_FLAGS_ITYPE_UNKNOWN (0 << 12)
143 #define RX_CMP_FLAGS_ITYPE_IP (1 << 12)
144 #define RX_CMP_FLAGS_ITYPE_TCP (2 << 12)
145 #define RX_CMP_FLAGS_ITYPE_UDP (3 << 12)
146 #define RX_CMP_FLAGS_ITYPE_FCOE (4 << 12)
147 #define RX_CMP_FLAGS_ITYPE_ROCE (5 << 12)
148 #define RX_CMP_FLAGS_ITYPE_PTP_WO_TS (8 << 12)
149 #define RX_CMP_FLAGS_ITYPE_PTP_W_TS (9 << 12)
150 #define RX_CMP_LEN (0xffff << 16)
151 #define RX_CMP_LEN_SHIFT 16
154 __le32 rx_cmp_misc_v1;
155 #define RX_CMP_V1 (1 << 0)
156 #define RX_CMP_AGG_BUFS (0x1f << 1)
157 #define RX_CMP_AGG_BUFS_SHIFT 1
158 #define RX_CMP_RSS_HASH_TYPE (0x7f << 9)
159 #define RX_CMP_RSS_HASH_TYPE_SHIFT 9
160 #define RX_CMP_PAYLOAD_OFFSET (0xff << 16)
161 #define RX_CMP_PAYLOAD_OFFSET_SHIFT 16
163 __le32 rx_cmp_rss_hash;
166 #define RX_CMP_HASH_VALID(rxcmp) \
167 ((rxcmp)->rx_cmp_len_flags_type & cpu_to_le32(RX_CMP_FLAGS_RSS_VALID))
169 #define RSS_PROFILE_ID_MASK 0x1f
171 #define RX_CMP_HASH_TYPE(rxcmp) \
172 (((le32_to_cpu((rxcmp)->rx_cmp_misc_v1) & RX_CMP_RSS_HASH_TYPE) >>\
173 RX_CMP_RSS_HASH_TYPE_SHIFT) & RSS_PROFILE_ID_MASK)
176 __le32 rx_cmp_flags2;
177 #define RX_CMP_FLAGS2_IP_CS_CALC 0x1
178 #define RX_CMP_FLAGS2_L4_CS_CALC (0x1 << 1)
179 #define RX_CMP_FLAGS2_T_IP_CS_CALC (0x1 << 2)
180 #define RX_CMP_FLAGS2_T_L4_CS_CALC (0x1 << 3)
181 #define RX_CMP_FLAGS2_META_FORMAT_VLAN (0x1 << 4)
182 __le32 rx_cmp_meta_data;
183 #define RX_CMP_FLAGS2_METADATA_VID_MASK 0xfff
184 #define RX_CMP_FLAGS2_METADATA_TPID_MASK 0xffff0000
185 #define RX_CMP_FLAGS2_METADATA_TPID_SFT 16
186 __le32 rx_cmp_cfa_code_errors_v2;
187 #define RX_CMP_V (1 << 0)
188 #define RX_CMPL_ERRORS_MASK (0x7fff << 1)
189 #define RX_CMPL_ERRORS_SFT 1
190 #define RX_CMPL_ERRORS_BUFFER_ERROR_MASK (0x7 << 1)
191 #define RX_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER (0x0 << 1)
192 #define RX_CMPL_ERRORS_BUFFER_ERROR_DID_NOT_FIT (0x1 << 1)
193 #define RX_CMPL_ERRORS_BUFFER_ERROR_NOT_ON_CHIP (0x2 << 1)
194 #define RX_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT (0x3 << 1)
195 #define RX_CMPL_ERRORS_IP_CS_ERROR (0x1 << 4)
196 #define RX_CMPL_ERRORS_L4_CS_ERROR (0x1 << 5)
197 #define RX_CMPL_ERRORS_T_IP_CS_ERROR (0x1 << 6)
198 #define RX_CMPL_ERRORS_T_L4_CS_ERROR (0x1 << 7)
199 #define RX_CMPL_ERRORS_CRC_ERROR (0x1 << 8)
200 #define RX_CMPL_ERRORS_T_PKT_ERROR_MASK (0x7 << 9)
201 #define RX_CMPL_ERRORS_T_PKT_ERROR_NO_ERROR (0x0 << 9)
202 #define RX_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_VERSION (0x1 << 9)
203 #define RX_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_HDR_LEN (0x2 << 9)
204 #define RX_CMPL_ERRORS_T_PKT_ERROR_TUNNEL_TOTAL_ERROR (0x3 << 9)
205 #define RX_CMPL_ERRORS_T_PKT_ERROR_T_IP_TOTAL_ERROR (0x4 << 9)
206 #define RX_CMPL_ERRORS_T_PKT_ERROR_T_UDP_TOTAL_ERROR (0x5 << 9)
207 #define RX_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL (0x6 << 9)
208 #define RX_CMPL_ERRORS_PKT_ERROR_MASK (0xf << 12)
209 #define RX_CMPL_ERRORS_PKT_ERROR_NO_ERROR (0x0 << 12)
210 #define RX_CMPL_ERRORS_PKT_ERROR_L3_BAD_VERSION (0x1 << 12)
211 #define RX_CMPL_ERRORS_PKT_ERROR_L3_BAD_HDR_LEN (0x2 << 12)
212 #define RX_CMPL_ERRORS_PKT_ERROR_L3_BAD_TTL (0x3 << 12)
213 #define RX_CMPL_ERRORS_PKT_ERROR_IP_TOTAL_ERROR (0x4 << 12)
214 #define RX_CMPL_ERRORS_PKT_ERROR_UDP_TOTAL_ERROR (0x5 << 12)
215 #define RX_CMPL_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN (0x6 << 12)
216 #define RX_CMPL_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN_TOO_SMALL (0x7 << 12)
217 #define RX_CMPL_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN (0x8 << 12)
219 #define RX_CMPL_CFA_CODE_MASK (0xffff << 16)
220 #define RX_CMPL_CFA_CODE_SFT 16
222 __le32 rx_cmp_unused3;
225 #define RX_CMP_L2_ERRORS \
226 cpu_to_le32(RX_CMPL_ERRORS_BUFFER_ERROR_MASK | RX_CMPL_ERRORS_CRC_ERROR)
228 #define RX_CMP_L4_CS_BITS \
229 (cpu_to_le32(RX_CMP_FLAGS2_L4_CS_CALC | RX_CMP_FLAGS2_T_L4_CS_CALC))
231 #define RX_CMP_L4_CS_ERR_BITS \
232 (cpu_to_le32(RX_CMPL_ERRORS_L4_CS_ERROR | RX_CMPL_ERRORS_T_L4_CS_ERROR))
234 #define RX_CMP_L4_CS_OK(rxcmp1) \
235 (((rxcmp1)->rx_cmp_flags2 & RX_CMP_L4_CS_BITS) && \
236 !((rxcmp1)->rx_cmp_cfa_code_errors_v2 & RX_CMP_L4_CS_ERR_BITS))
238 #define RX_CMP_ENCAP(rxcmp1) \
239 ((le32_to_cpu((rxcmp1)->rx_cmp_flags2) & \
240 RX_CMP_FLAGS2_T_L4_CS_CALC) >> 3)
243 __le32 rx_agg_cmp_len_flags_type;
244 #define RX_AGG_CMP_TYPE (0x3f << 0)
245 #define RX_AGG_CMP_LEN (0xffff << 16)
246 #define RX_AGG_CMP_LEN_SHIFT 16
247 u32 rx_agg_cmp_opaque;
249 #define RX_AGG_CMP_V (1 << 0)
250 __le32 rx_agg_cmp_unused;
253 struct rx_tpa_start_cmp {
254 __le32 rx_tpa_start_cmp_len_flags_type;
255 #define RX_TPA_START_CMP_TYPE (0x3f << 0)
256 #define RX_TPA_START_CMP_FLAGS (0x3ff << 6)
257 #define RX_TPA_START_CMP_FLAGS_SHIFT 6
258 #define RX_TPA_START_CMP_FLAGS_PLACEMENT (0x7 << 7)
259 #define RX_TPA_START_CMP_FLAGS_PLACEMENT_SHIFT 7
260 #define RX_TPA_START_CMP_FLAGS_PLACEMENT_JUMBO (0x1 << 7)
261 #define RX_TPA_START_CMP_FLAGS_PLACEMENT_HDS (0x2 << 7)
262 #define RX_TPA_START_CMP_FLAGS_PLACEMENT_GRO_JUMBO (0x5 << 7)
263 #define RX_TPA_START_CMP_FLAGS_PLACEMENT_GRO_HDS (0x6 << 7)
264 #define RX_TPA_START_CMP_FLAGS_RSS_VALID (0x1 << 10)
265 #define RX_TPA_START_CMP_FLAGS_ITYPES (0xf << 12)
266 #define RX_TPA_START_CMP_FLAGS_ITYPES_SHIFT 12
267 #define RX_TPA_START_CMP_FLAGS_ITYPE_TCP (0x2 << 12)
268 #define RX_TPA_START_CMP_LEN (0xffff << 16)
269 #define RX_TPA_START_CMP_LEN_SHIFT 16
271 u32 rx_tpa_start_cmp_opaque;
272 __le32 rx_tpa_start_cmp_misc_v1;
273 #define RX_TPA_START_CMP_V1 (0x1 << 0)
274 #define RX_TPA_START_CMP_RSS_HASH_TYPE (0x7f << 9)
275 #define RX_TPA_START_CMP_RSS_HASH_TYPE_SHIFT 9
276 #define RX_TPA_START_CMP_AGG_ID (0x7f << 25)
277 #define RX_TPA_START_CMP_AGG_ID_SHIFT 25
279 __le32 rx_tpa_start_cmp_rss_hash;
282 #define TPA_START_HASH_VALID(rx_tpa_start) \
283 ((rx_tpa_start)->rx_tpa_start_cmp_len_flags_type & \
284 cpu_to_le32(RX_TPA_START_CMP_FLAGS_RSS_VALID))
286 #define TPA_START_HASH_TYPE(rx_tpa_start) \
287 (((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_misc_v1) & \
288 RX_TPA_START_CMP_RSS_HASH_TYPE) >> \
289 RX_TPA_START_CMP_RSS_HASH_TYPE_SHIFT) & RSS_PROFILE_ID_MASK)
291 #define TPA_START_AGG_ID(rx_tpa_start) \
292 ((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_misc_v1) & \
293 RX_TPA_START_CMP_AGG_ID) >> RX_TPA_START_CMP_AGG_ID_SHIFT)
295 struct rx_tpa_start_cmp_ext {
296 __le32 rx_tpa_start_cmp_flags2;
297 #define RX_TPA_START_CMP_FLAGS2_IP_CS_CALC (0x1 << 0)
298 #define RX_TPA_START_CMP_FLAGS2_L4_CS_CALC (0x1 << 1)
299 #define RX_TPA_START_CMP_FLAGS2_T_IP_CS_CALC (0x1 << 2)
300 #define RX_TPA_START_CMP_FLAGS2_T_L4_CS_CALC (0x1 << 3)
302 __le32 rx_tpa_start_cmp_metadata;
303 __le32 rx_tpa_start_cmp_cfa_code_v2;
304 #define RX_TPA_START_CMP_V2 (0x1 << 0)
305 #define RX_TPA_START_CMP_CFA_CODE (0xffff << 16)
306 #define RX_TPA_START_CMPL_CFA_CODE_SHIFT 16
307 __le32 rx_tpa_start_cmp_unused5;
310 struct rx_tpa_end_cmp {
311 __le32 rx_tpa_end_cmp_len_flags_type;
312 #define RX_TPA_END_CMP_TYPE (0x3f << 0)
313 #define RX_TPA_END_CMP_FLAGS (0x3ff << 6)
314 #define RX_TPA_END_CMP_FLAGS_SHIFT 6
315 #define RX_TPA_END_CMP_FLAGS_PLACEMENT (0x7 << 7)
316 #define RX_TPA_END_CMP_FLAGS_PLACEMENT_SHIFT 7
317 #define RX_TPA_END_CMP_FLAGS_PLACEMENT_JUMBO (0x1 << 7)
318 #define RX_TPA_END_CMP_FLAGS_PLACEMENT_HDS (0x2 << 7)
319 #define RX_TPA_END_CMP_FLAGS_PLACEMENT_GRO_JUMBO (0x5 << 7)
320 #define RX_TPA_END_CMP_FLAGS_PLACEMENT_GRO_HDS (0x6 << 7)
321 #define RX_TPA_END_CMP_FLAGS_RSS_VALID (0x1 << 10)
322 #define RX_TPA_END_CMP_FLAGS_ITYPES (0xf << 12)
323 #define RX_TPA_END_CMP_FLAGS_ITYPES_SHIFT 12
324 #define RX_TPA_END_CMP_FLAGS_ITYPE_TCP (0x2 << 12)
325 #define RX_TPA_END_CMP_LEN (0xffff << 16)
326 #define RX_TPA_END_CMP_LEN_SHIFT 16
328 u32 rx_tpa_end_cmp_opaque;
329 __le32 rx_tpa_end_cmp_misc_v1;
330 #define RX_TPA_END_CMP_V1 (0x1 << 0)
331 #define RX_TPA_END_CMP_AGG_BUFS (0x3f << 1)
332 #define RX_TPA_END_CMP_AGG_BUFS_SHIFT 1
333 #define RX_TPA_END_CMP_TPA_SEGS (0xff << 8)
334 #define RX_TPA_END_CMP_TPA_SEGS_SHIFT 8
335 #define RX_TPA_END_CMP_PAYLOAD_OFFSET (0xff << 16)
336 #define RX_TPA_END_CMP_PAYLOAD_OFFSET_SHIFT 16
337 #define RX_TPA_END_CMP_AGG_ID (0x7f << 25)
338 #define RX_TPA_END_CMP_AGG_ID_SHIFT 25
340 __le32 rx_tpa_end_cmp_tsdelta;
341 #define RX_TPA_END_GRO_TS (0x1 << 31)
344 #define TPA_END_AGG_ID(rx_tpa_end) \
345 ((le32_to_cpu((rx_tpa_end)->rx_tpa_end_cmp_misc_v1) & \
346 RX_TPA_END_CMP_AGG_ID) >> RX_TPA_END_CMP_AGG_ID_SHIFT)
348 #define TPA_END_TPA_SEGS(rx_tpa_end) \
349 ((le32_to_cpu((rx_tpa_end)->rx_tpa_end_cmp_misc_v1) & \
350 RX_TPA_END_CMP_TPA_SEGS) >> RX_TPA_END_CMP_TPA_SEGS_SHIFT)
352 #define RX_TPA_END_CMP_FLAGS_PLACEMENT_ANY_GRO \
353 cpu_to_le32(RX_TPA_END_CMP_FLAGS_PLACEMENT_GRO_JUMBO & \
354 RX_TPA_END_CMP_FLAGS_PLACEMENT_GRO_HDS)
356 #define TPA_END_GRO(rx_tpa_end) \
357 ((rx_tpa_end)->rx_tpa_end_cmp_len_flags_type & \
358 RX_TPA_END_CMP_FLAGS_PLACEMENT_ANY_GRO)
360 #define TPA_END_GRO_TS(rx_tpa_end) \
361 ((rx_tpa_end)->rx_tpa_end_cmp_tsdelta & cpu_to_le32(RX_TPA_END_GRO_TS))
363 struct rx_tpa_end_cmp_ext {
364 __le32 rx_tpa_end_cmp_dup_acks;
365 #define RX_TPA_END_CMP_TPA_DUP_ACKS (0xf << 0)
367 __le32 rx_tpa_end_cmp_seg_len;
368 #define RX_TPA_END_CMP_TPA_SEG_LEN (0xffff << 0)
370 __le32 rx_tpa_end_cmp_errors_v2;
371 #define RX_TPA_END_CMP_V2 (0x1 << 0)
372 #define RX_TPA_END_CMP_ERRORS (0x7fff << 1)
373 #define RX_TPA_END_CMPL_ERRORS_SHIFT 1
375 u32 rx_tpa_end_cmp_start_opaque;
378 #define DB_IDX_MASK 0xffffff
379 #define DB_IDX_VALID (0x1 << 26)
380 #define DB_IRQ_DIS (0x1 << 27)
381 #define DB_KEY_TX (0x0 << 28)
382 #define DB_KEY_RX (0x1 << 28)
383 #define DB_KEY_CP (0x2 << 28)
384 #define DB_KEY_ST (0x3 << 28)
385 #define DB_KEY_TX_PUSH (0x4 << 28)
386 #define DB_LONG_TX_PUSH (0x2 << 24)
388 #define INVALID_HW_RING_ID ((u16)-1)
390 #define BNXT_RSS_HASH_TYPE_FLAG_IPV4 0x01
391 #define BNXT_RSS_HASH_TYPE_FLAG_TCP_IPV4 0x02
392 #define BNXT_RSS_HASH_TYPE_FLAG_IPV6 0x04
393 #define BNXT_RSS_HASH_TYPE_FLAG_TCP_IPV6 0x08
395 /* The hardware supports certain page sizes. Use the supported page sizes
396 * to allocate the rings.
398 #if (PAGE_SHIFT < 12)
399 #define BNXT_PAGE_SHIFT 12
400 #elif (PAGE_SHIFT <= 13)
401 #define BNXT_PAGE_SHIFT PAGE_SHIFT
402 #elif (PAGE_SHIFT < 16)
403 #define BNXT_PAGE_SHIFT 13
405 #define BNXT_PAGE_SHIFT 16
408 #define BNXT_PAGE_SIZE (1 << BNXT_PAGE_SHIFT)
410 #define BNXT_MIN_PKT_SIZE 45
412 #define BNXT_NUM_TESTS(bp) 0
414 #define BNXT_DEFAULT_RX_RING_SIZE 1023
415 #define BNXT_DEFAULT_TX_RING_SIZE 512
419 #define MAX_RX_PAGES 8
420 #define MAX_RX_AGG_PAGES 32
421 #define MAX_TX_PAGES 8
422 #define MAX_CP_PAGES 64
424 #define RX_DESC_CNT (BNXT_PAGE_SIZE / sizeof(struct rx_bd))
425 #define TX_DESC_CNT (BNXT_PAGE_SIZE / sizeof(struct tx_bd))
426 #define CP_DESC_CNT (BNXT_PAGE_SIZE / sizeof(struct tx_cmp))
428 #define SW_RXBD_RING_SIZE (sizeof(struct bnxt_sw_rx_bd) * RX_DESC_CNT)
429 #define HW_RXBD_RING_SIZE (sizeof(struct rx_bd) * RX_DESC_CNT)
431 #define SW_RXBD_AGG_RING_SIZE (sizeof(struct bnxt_sw_rx_agg_bd) * RX_DESC_CNT)
433 #define SW_TXBD_RING_SIZE (sizeof(struct bnxt_sw_tx_bd) * TX_DESC_CNT)
434 #define HW_TXBD_RING_SIZE (sizeof(struct tx_bd) * TX_DESC_CNT)
436 #define HW_CMPD_RING_SIZE (sizeof(struct tx_cmp) * CP_DESC_CNT)
438 #define BNXT_MAX_RX_DESC_CNT (RX_DESC_CNT * MAX_RX_PAGES - 1)
439 #define BNXT_MAX_RX_JUM_DESC_CNT (RX_DESC_CNT * MAX_RX_AGG_PAGES - 1)
440 #define BNXT_MAX_TX_DESC_CNT (TX_DESC_CNT * MAX_TX_PAGES - 1)
442 #define RX_RING(x) (((x) & ~(RX_DESC_CNT - 1)) >> (BNXT_PAGE_SHIFT - 4))
443 #define RX_IDX(x) ((x) & (RX_DESC_CNT - 1))
445 #define TX_RING(x) (((x) & ~(TX_DESC_CNT - 1)) >> (BNXT_PAGE_SHIFT - 4))
446 #define TX_IDX(x) ((x) & (TX_DESC_CNT - 1))
448 #define CP_RING(x) (((x) & ~(CP_DESC_CNT - 1)) >> (BNXT_PAGE_SHIFT - 4))
449 #define CP_IDX(x) ((x) & (CP_DESC_CNT - 1))
451 #define TX_CMP_VALID(txcmp, raw_cons) \
452 (!!((txcmp)->tx_cmp_errors_v & cpu_to_le32(TX_CMP_V)) == \
453 !((raw_cons) & bp->cp_bit))
455 #define RX_CMP_VALID(rxcmp1, raw_cons) \
456 (!!((rxcmp1)->rx_cmp_cfa_code_errors_v2 & cpu_to_le32(RX_CMP_V)) ==\
457 !((raw_cons) & bp->cp_bit))
459 #define RX_AGG_CMP_VALID(agg, raw_cons) \
460 (!!((agg)->rx_agg_cmp_v & cpu_to_le32(RX_AGG_CMP_V)) == \
461 !((raw_cons) & bp->cp_bit))
463 #define TX_CMP_TYPE(txcmp) \
464 (le32_to_cpu((txcmp)->tx_cmp_flags_type) & CMP_TYPE)
466 #define RX_CMP_TYPE(rxcmp) \
467 (le32_to_cpu((rxcmp)->rx_cmp_len_flags_type) & RX_CMP_CMP_TYPE)
469 #define NEXT_RX(idx) (((idx) + 1) & bp->rx_ring_mask)
471 #define NEXT_RX_AGG(idx) (((idx) + 1) & bp->rx_agg_ring_mask)
473 #define NEXT_TX(idx) (((idx) + 1) & bp->tx_ring_mask)
475 #define ADV_RAW_CMP(idx, n) ((idx) + (n))
476 #define NEXT_RAW_CMP(idx) ADV_RAW_CMP(idx, 1)
477 #define RING_CMP(idx) ((idx) & bp->cp_ring_mask)
478 #define NEXT_CMP(idx) RING_CMP(ADV_RAW_CMP(idx, 1))
480 #define HWRM_CMD_TIMEOUT 500
481 #define HWRM_RESET_TIMEOUT ((HWRM_CMD_TIMEOUT) * 4)
482 #define HWRM_RESP_ERR_CODE_MASK 0xffff
483 #define HWRM_RESP_LEN_MASK 0xffff0000
484 #define HWRM_RESP_LEN_SFT 16
485 #define HWRM_RESP_VALID_MASK 0xff000000
486 #define BNXT_HWRM_REQ_MAX_SIZE 128
487 #define BNXT_HWRM_REQS_PER_PAGE (BNXT_PAGE_SIZE / \
488 BNXT_HWRM_REQ_MAX_SIZE)
490 struct bnxt_sw_tx_bd {
492 DEFINE_DMA_UNMAP_ADDR(mapping);
495 unsigned short nr_frags;
498 struct bnxt_sw_rx_bd {
500 DEFINE_DMA_UNMAP_ADDR(mapping);
503 struct bnxt_sw_rx_agg_bd {
508 struct bnxt_ring_struct {
515 dma_addr_t pg_tbl_map;
520 u16 fw_ring_id; /* Ring id filled by Chimp FW */
527 struct tx_bd_ext txbd2;
530 struct bnxt_tx_ring_info {
531 struct bnxt_napi *bnapi;
534 void __iomem *tx_doorbell;
536 struct tx_bd *tx_desc_ring[MAX_TX_PAGES];
537 struct bnxt_sw_tx_bd *tx_buf_ring;
539 dma_addr_t tx_desc_mapping[MAX_TX_PAGES];
541 struct tx_push_bd *tx_push;
542 dma_addr_t tx_push_mapping;
544 #define BNXT_DEV_STATE_CLOSING 0x1
547 struct bnxt_ring_struct tx_ring_struct;
550 struct bnxt_tpa_info {
554 unsigned short gso_type;
557 enum pkt_hash_types hash_type;
561 struct bnxt_rx_ring_info {
562 struct bnxt_napi *bnapi;
566 void __iomem *rx_doorbell;
567 void __iomem *rx_agg_doorbell;
569 struct rx_bd *rx_desc_ring[MAX_RX_PAGES];
570 struct bnxt_sw_rx_bd *rx_buf_ring;
572 struct rx_bd *rx_agg_desc_ring[MAX_RX_AGG_PAGES];
573 struct bnxt_sw_rx_agg_bd *rx_agg_ring;
575 unsigned long *rx_agg_bmap;
576 u16 rx_agg_bmap_size;
578 dma_addr_t rx_desc_mapping[MAX_RX_PAGES];
579 dma_addr_t rx_agg_desc_mapping[MAX_RX_AGG_PAGES];
581 struct bnxt_tpa_info *rx_tpa;
583 struct bnxt_ring_struct rx_ring_struct;
584 struct bnxt_ring_struct rx_agg_ring_struct;
587 struct bnxt_cp_ring_info {
589 void __iomem *cp_doorbell;
591 struct tx_cmp *cp_desc_ring[MAX_CP_PAGES];
593 dma_addr_t cp_desc_mapping[MAX_CP_PAGES];
595 struct ctx_hw_stats *hw_stats;
596 dma_addr_t hw_stats_map;
598 u64 rx_l4_csum_errors;
600 struct bnxt_ring_struct cp_ring_struct;
604 struct napi_struct napi;
608 struct bnxt_cp_ring_info cp_ring;
609 struct bnxt_rx_ring_info *rx_ring;
610 struct bnxt_tx_ring_info *tx_ring;
612 #ifdef CONFIG_NET_RX_BUSY_POLL
617 #ifdef CONFIG_NET_RX_BUSY_POLL
618 enum bnxt_poll_state_t {
627 irq_handler_t handler;
630 char name[IFNAMSIZ + 2];
633 #define HWRM_RING_ALLOC_TX 0x1
634 #define HWRM_RING_ALLOC_RX 0x2
635 #define HWRM_RING_ALLOC_AGG 0x4
636 #define HWRM_RING_ALLOC_CMPL 0x8
638 #define INVALID_STATS_CTX_ID -1
640 struct hwrm_cmd_req_hdr {
641 #define HWRM_CMPL_RING_MASK 0xffff0000
642 #define HWRM_CMPL_RING_SFT 16
643 __le32 cmpl_ring_req_type;
644 #define HWRM_SEQ_ID_MASK 0xffff
645 #define HWRM_SEQ_ID_INVALID -1
646 #define HWRM_RESP_LEN_OFFSET 4
647 #define HWRM_TARGET_FID_MASK 0xffff0000
648 #define HWRM_TARGET_FID_SFT 16
649 __le32 target_id_seq_id;
653 struct bnxt_ring_grp_info {
661 struct bnxt_vnic_info {
662 u16 fw_vnic_id; /* returned by Chimp during alloc */
663 u16 fw_rss_cos_lb_ctx;
665 #define BNXT_MAX_UC_ADDRS 4
666 __le64 fw_l2_filter_id[BNXT_MAX_UC_ADDRS];
667 /* index 0 always dev_addr */
673 dma_addr_t rss_table_dma_addr;
675 dma_addr_t rss_hash_key_dma_addr;
682 dma_addr_t mc_list_mapping;
683 #define BNXT_MAX_MC_ADDRS 16
686 #define BNXT_VNIC_RSS_FLAG 1
687 #define BNXT_VNIC_RFS_FLAG 2
688 #define BNXT_VNIC_MCAST_FLAG 4
689 #define BNXT_VNIC_UCAST_FLAG 8
692 #if defined(CONFIG_BNXT_SRIOV)
693 struct bnxt_vf_info {
695 u8 mac_addr[ETH_ALEN];
700 u16 max_hw_ring_grps;
707 #define BNXT_VF_QOS 0x1
708 #define BNXT_VF_SPOOFCHK 0x2
709 #define BNXT_VF_LINK_FORCED 0x4
710 #define BNXT_VF_LINK_UP 0x8
711 u32 func_flags; /* func cfg flags */
714 void *hwrm_cmd_req_addr;
715 dma_addr_t hwrm_cmd_req_dma_addr;
719 struct bnxt_pf_info {
720 #define BNXT_FIRST_PF_FID 1
721 #define BNXT_FIRST_VF_FID 128
724 u8 mac_addr[ETH_ALEN];
727 u16 max_tx_rings; /* HW assigned max tx rings for this PF */
728 u16 max_rx_rings; /* HW assigned max rx rings for this PF */
729 u16 max_hw_ring_grps;
737 u32 max_encap_records;
738 u32 max_decap_records;
743 unsigned long *vf_event_bmap;
744 u16 hwrm_cmd_req_pages;
745 void *hwrm_cmd_req_addr[4];
746 dma_addr_t hwrm_cmd_req_dma_addr[4];
747 struct bnxt_vf_info *vf;
750 struct bnxt_ntuple_filter {
751 struct hlist_node hash;
752 u8 src_mac_addr[ETH_ALEN];
753 struct flow_keys fkeys;
759 #define BNXT_FLTR_VALID 0
760 #define BNXT_FLTR_UPDATE 1
763 #define BNXT_ALL_COPPER_ETHTOOL_SPEED \
764 (ADVERTISED_100baseT_Full | ADVERTISED_1000baseT_Full | \
765 ADVERTISED_10000baseT_Full)
767 struct bnxt_link_info {
772 #define BNXT_LINK_NO_LINK PORT_PHY_QCFG_RESP_LINK_NO_LINK
773 #define BNXT_LINK_SIGNAL PORT_PHY_QCFG_RESP_LINK_SIGNAL
774 #define BNXT_LINK_LINK PORT_PHY_QCFG_RESP_LINK_LINK
779 #define BNXT_LINK_DUPLEX_HALF PORT_PHY_QCFG_RESP_DUPLEX_HALF
780 #define BNXT_LINK_DUPLEX_FULL PORT_PHY_QCFG_RESP_DUPLEX_FULL
782 #define BNXT_LINK_PAUSE_TX PORT_PHY_QCFG_RESP_PAUSE_TX
783 #define BNXT_LINK_PAUSE_RX PORT_PHY_QCFG_RESP_PAUSE_RX
784 #define BNXT_LINK_PAUSE_BOTH (PORT_PHY_QCFG_RESP_PAUSE_RX | \
785 PORT_PHY_QCFG_RESP_PAUSE_TX)
786 u8 auto_pause_setting;
787 u8 force_pause_setting;
790 #define BNXT_AUTO_MODE(mode) ((mode) > BNXT_LINK_AUTO_NONE && \
791 (mode) <= BNXT_LINK_AUTO_MSK)
792 #define BNXT_LINK_AUTO_NONE PORT_PHY_QCFG_RESP_AUTO_MODE_NONE
793 #define BNXT_LINK_AUTO_ALLSPDS PORT_PHY_QCFG_RESP_AUTO_MODE_ALL_SPEEDS
794 #define BNXT_LINK_AUTO_ONESPD PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_SPEED
795 #define BNXT_LINK_AUTO_ONEORBELOW PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_OR_BELOW
796 #define BNXT_LINK_AUTO_MSK PORT_PHY_QCFG_RESP_AUTO_MODE_MASK
797 #define PHY_VER_LEN 3
798 u8 phy_ver[PHY_VER_LEN];
800 #define BNXT_LINK_SPEED_100MB PORT_PHY_QCFG_RESP_LINK_SPEED_100MB
801 #define BNXT_LINK_SPEED_1GB PORT_PHY_QCFG_RESP_LINK_SPEED_1GB
802 #define BNXT_LINK_SPEED_2GB PORT_PHY_QCFG_RESP_LINK_SPEED_2GB
803 #define BNXT_LINK_SPEED_2_5GB PORT_PHY_QCFG_RESP_LINK_SPEED_2_5GB
804 #define BNXT_LINK_SPEED_10GB PORT_PHY_QCFG_RESP_LINK_SPEED_10GB
805 #define BNXT_LINK_SPEED_20GB PORT_PHY_QCFG_RESP_LINK_SPEED_20GB
806 #define BNXT_LINK_SPEED_25GB PORT_PHY_QCFG_RESP_LINK_SPEED_25GB
807 #define BNXT_LINK_SPEED_40GB PORT_PHY_QCFG_RESP_LINK_SPEED_40GB
808 #define BNXT_LINK_SPEED_50GB PORT_PHY_QCFG_RESP_LINK_SPEED_50GB
810 u16 auto_link_speeds;
811 #define BNXT_LINK_SPEED_MSK_100MB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100MB
812 #define BNXT_LINK_SPEED_MSK_1GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_1GB
813 #define BNXT_LINK_SPEED_MSK_2GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2GB
814 #define BNXT_LINK_SPEED_MSK_10GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10GB
815 #define BNXT_LINK_SPEED_MSK_2_5GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2_5GB
816 #define BNXT_LINK_SPEED_MSK_20GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_20GB
817 #define BNXT_LINK_SPEED_MSK_25GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_25GB
818 #define BNXT_LINK_SPEED_MSK_40GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_40GB
819 #define BNXT_LINK_SPEED_MSK_50GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_50GB
821 u16 force_link_speed;
824 /* copy of requested setting from ethtool cmd */
826 #define BNXT_AUTONEG_SPEED 1
827 #define BNXT_AUTONEG_FLOW_CTRL 2
832 bool force_link_chng;
833 /* a copy of phy_qcfg output used to report link
836 struct hwrm_port_phy_qcfg_output phy_qcfg_resp;
839 #define BNXT_MAX_QUEUE 8
841 struct bnxt_queue_info {
846 #define BNXT_GRCPF_REG_WINDOW_BASE_OUT 0x400
847 #define BNXT_CAG_REG_LEGACY_INT_STATUS 0x4014
848 #define BNXT_CAG_REG_BASE 0x300000
857 struct net_device *dev;
858 struct pci_dev *pdev;
863 #define BNXT_FLAG_DCB_ENABLED 0x1
864 #define BNXT_FLAG_VF 0x2
865 #define BNXT_FLAG_LRO 0x4
867 #define BNXT_FLAG_GRO 0x8
869 /* Cannot support hardware GRO if CONFIG_INET is not set */
870 #define BNXT_FLAG_GRO 0x0
872 #define BNXT_FLAG_TPA (BNXT_FLAG_LRO | BNXT_FLAG_GRO)
873 #define BNXT_FLAG_JUMBO 0x10
874 #define BNXT_FLAG_STRIP_VLAN 0x20
875 #define BNXT_FLAG_AGG_RINGS (BNXT_FLAG_JUMBO | BNXT_FLAG_GRO | \
877 #define BNXT_FLAG_USING_MSIX 0x40
878 #define BNXT_FLAG_MSIX_CAP 0x80
879 #define BNXT_FLAG_RFS 0x100
880 #define BNXT_FLAG_SHARED_RINGS 0x200
882 #define BNXT_FLAG_ALL_CONFIG_FEATS (BNXT_FLAG_TPA | \
884 BNXT_FLAG_STRIP_VLAN)
886 #define BNXT_PF(bp) (!((bp)->flags & BNXT_FLAG_VF))
887 #define BNXT_VF(bp) ((bp)->flags & BNXT_FLAG_VF)
889 struct bnxt_napi **bnapi;
891 struct bnxt_rx_ring_info *rx_ring;
892 struct bnxt_tx_ring_info *tx_ring;
895 u32 rx_buf_use_size; /* useable size */
897 u32 rx_agg_ring_size;
900 u32 rx_agg_ring_mask;
910 int tx_nr_rings_per_tc;
924 /* grp_info indexed by completion ring index */
925 struct bnxt_ring_grp_info *grp_info;
926 struct bnxt_vnic_info *vnic_info;
930 struct bnxt_queue_info q_info[BNXT_MAX_QUEUE];
932 unsigned int current_interval;
933 #define BNXT_TIMER_INTERVAL (HZ / 2)
935 struct timer_list timer;
938 #define BNXT_STATE_OPEN 0
939 #define BNXT_STATE_IN_SP_TASK 1
941 struct bnxt_irq *irq_tbl;
942 u8 mac_addr[ETH_ALEN];
947 u32 hwrm_intr_seq_id;
948 void *hwrm_cmd_resp_addr;
949 dma_addr_t hwrm_cmd_resp_dma_addr;
950 void *hwrm_dbg_resp_addr;
951 dma_addr_t hwrm_dbg_resp_dma_addr;
952 #define HWRM_DBG_REG_BUF_SIZE 128
953 struct mutex hwrm_cmd_lock; /* serialize hwrm messages */
954 struct hwrm_ver_get_output ver_resp;
955 #define FW_VER_STR_LEN 32
956 #define BC_HWRM_STR_LEN 21
957 #define PHY_VER_STR_LEN (FW_VER_STR_LEN - BC_HWRM_STR_LEN)
958 char fw_ver_str[FW_VER_STR_LEN];
961 __le16 vxlan_fw_dst_port_id;
963 __le16 nge_fw_dst_port_id;
969 #define BNXT_USEC_TO_COAL_TIMER(x) ((x) * 25 / 2)
970 #define BNXT_COAL_TIMER_TO_USEC(x) ((x) * 2 / 25)
972 struct work_struct sp_task;
973 unsigned long sp_event;
974 #define BNXT_RX_MASK_SP_EVENT 0
975 #define BNXT_RX_NTP_FLTR_SP_EVENT 1
976 #define BNXT_LINK_CHNG_SP_EVENT 2
977 #define BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT 3
978 #define BNXT_VXLAN_ADD_PORT_SP_EVENT 4
979 #define BNXT_VXLAN_DEL_PORT_SP_EVENT 5
980 #define BNXT_RESET_TASK_SP_EVENT 6
981 #define BNXT_RST_RING_SP_EVENT 7
983 struct bnxt_pf_info pf;
984 #ifdef CONFIG_BNXT_SRIOV
986 struct bnxt_vf_info vf;
987 wait_queue_head_t sriov_cfg_wait;
989 #define BNXT_SRIOV_CFG_WAIT_TMO msecs_to_jiffies(10000)
992 #define BNXT_NTP_FLTR_MAX_FLTR 4096
993 #define BNXT_NTP_FLTR_HASH_SIZE 512
994 #define BNXT_NTP_FLTR_HASH_MASK (BNXT_NTP_FLTR_HASH_SIZE - 1)
995 struct hlist_head ntp_fltr_hash_tbl[BNXT_NTP_FLTR_HASH_SIZE];
996 spinlock_t ntp_fltr_lock; /* for hash table add, del */
998 unsigned long *ntp_fltr_bmap;
1001 struct bnxt_link_info link_info;
1004 #ifdef CONFIG_NET_RX_BUSY_POLL
1005 static inline void bnxt_enable_poll(struct bnxt_napi *bnapi)
1007 atomic_set(&bnapi->poll_state, BNXT_STATE_IDLE);
1010 /* called from the NAPI poll routine to get ownership of a bnapi */
1011 static inline bool bnxt_lock_napi(struct bnxt_napi *bnapi)
1013 int rc = atomic_cmpxchg(&bnapi->poll_state, BNXT_STATE_IDLE,
1016 return rc == BNXT_STATE_IDLE;
1019 static inline void bnxt_unlock_napi(struct bnxt_napi *bnapi)
1021 atomic_set(&bnapi->poll_state, BNXT_STATE_IDLE);
1024 /* called from the busy poll routine to get ownership of a bnapi */
1025 static inline bool bnxt_lock_poll(struct bnxt_napi *bnapi)
1027 int rc = atomic_cmpxchg(&bnapi->poll_state, BNXT_STATE_IDLE,
1030 return rc == BNXT_STATE_IDLE;
1033 static inline void bnxt_unlock_poll(struct bnxt_napi *bnapi)
1035 atomic_set(&bnapi->poll_state, BNXT_STATE_IDLE);
1038 static inline bool bnxt_busy_polling(struct bnxt_napi *bnapi)
1040 return atomic_read(&bnapi->poll_state) == BNXT_STATE_POLL;
1043 static inline void bnxt_disable_poll(struct bnxt_napi *bnapi)
1048 old = atomic_cmpxchg(&bnapi->poll_state, BNXT_STATE_IDLE,
1049 BNXT_STATE_DISABLE);
1050 if (old == BNXT_STATE_IDLE)
1052 usleep_range(500, 5000);
1058 static inline void bnxt_enable_poll(struct bnxt_napi *bnapi)
1062 static inline bool bnxt_lock_napi(struct bnxt_napi *bnapi)
1067 static inline void bnxt_unlock_napi(struct bnxt_napi *bnapi)
1071 static inline bool bnxt_lock_poll(struct bnxt_napi *bnapi)
1076 static inline void bnxt_unlock_poll(struct bnxt_napi *bnapi)
1080 static inline bool bnxt_busy_polling(struct bnxt_napi *bnapi)
1085 static inline void bnxt_disable_poll(struct bnxt_napi *bnapi)
1091 void bnxt_set_ring_params(struct bnxt *);
1092 void bnxt_hwrm_cmd_hdr_init(struct bnxt *, void *, u16, u16, u16);
1093 int _hwrm_send_message(struct bnxt *, void *, u32, int);
1094 int hwrm_send_message(struct bnxt *, void *, u32, int);
1095 int bnxt_hwrm_set_coal(struct bnxt *);
1096 int bnxt_hwrm_func_qcaps(struct bnxt *);
1097 int bnxt_hwrm_set_pause(struct bnxt *);
1098 int bnxt_hwrm_set_link_setting(struct bnxt *, bool);
1099 int bnxt_open_nic(struct bnxt *, bool, bool);
1100 int bnxt_close_nic(struct bnxt *, bool, bool);
1101 int bnxt_get_max_rings(struct bnxt *, int *, int *, bool);