1 /* Broadcom NetXtreme-C/E network driver.
3 * Copyright (c) 2014-2016 Broadcom Corporation
4 * Copyright (c) 2016-2018 Broadcom Limited
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation.
14 #define DRV_MODULE_NAME "bnxt_en"
16 /* DO NOT CHANGE DRV_VER_* defines
20 #define DRV_VER_MIN 10
23 #include <linux/ethtool.h>
24 #include <linux/interrupt.h>
25 #include <linux/rhashtable.h>
26 #include <linux/crash_dump.h>
27 #include <linux/auxiliary_bus.h>
28 #include <net/devlink.h>
29 #include <net/dst_metadata.h>
31 #include <linux/dim.h>
32 #include <linux/io-64-nonatomic-lo-hi.h>
33 #ifdef CONFIG_TEE_BNXT_FW
34 #include <linux/firmware/broadcom/tee_bnxt_fw.h>
37 extern struct list_head bnxt_block_cb_list;
42 __le32 tx_bd_len_flags_type;
43 #define TX_BD_TYPE (0x3f << 0)
44 #define TX_BD_TYPE_SHORT_TX_BD (0x00 << 0)
45 #define TX_BD_TYPE_LONG_TX_BD (0x10 << 0)
46 #define TX_BD_FLAGS_PACKET_END (1 << 6)
47 #define TX_BD_FLAGS_NO_CMPL (1 << 7)
48 #define TX_BD_FLAGS_BD_CNT (0x1f << 8)
49 #define TX_BD_FLAGS_BD_CNT_SHIFT 8
50 #define TX_BD_FLAGS_LHINT (3 << 13)
51 #define TX_BD_FLAGS_LHINT_SHIFT 13
52 #define TX_BD_FLAGS_LHINT_512_AND_SMALLER (0 << 13)
53 #define TX_BD_FLAGS_LHINT_512_TO_1023 (1 << 13)
54 #define TX_BD_FLAGS_LHINT_1024_TO_2047 (2 << 13)
55 #define TX_BD_FLAGS_LHINT_2048_AND_LARGER (3 << 13)
56 #define TX_BD_FLAGS_COAL_NOW (1 << 15)
57 #define TX_BD_LEN (0xffff << 16)
58 #define TX_BD_LEN_SHIFT 16
64 #define TX_OPAQUE_IDX_MASK 0x0000ffff
65 #define TX_OPAQUE_BDS_MASK 0x00ff0000
66 #define TX_OPAQUE_BDS_SHIFT 16
67 #define TX_OPAQUE_RING_MASK 0xff000000
68 #define TX_OPAQUE_RING_SHIFT 24
70 #define SET_TX_OPAQUE(bp, txr, idx, bds) \
71 (((txr)->tx_napi_idx << TX_OPAQUE_RING_SHIFT) | \
72 ((bds) << TX_OPAQUE_BDS_SHIFT) | ((idx) & (bp)->tx_ring_mask))
74 #define TX_OPAQUE_IDX(opq) ((opq) & TX_OPAQUE_IDX_MASK)
75 #define TX_OPAQUE_RING(opq) (((opq) & TX_OPAQUE_RING_MASK) >> \
77 #define TX_OPAQUE_BDS(opq) (((opq) & TX_OPAQUE_BDS_MASK) >> \
79 #define TX_OPAQUE_PROD(bp, opq) ((TX_OPAQUE_IDX(opq) + TX_OPAQUE_BDS(opq)) &\
83 __le32 tx_bd_hsize_lflags;
84 #define TX_BD_FLAGS_TCP_UDP_CHKSUM (1 << 0)
85 #define TX_BD_FLAGS_IP_CKSUM (1 << 1)
86 #define TX_BD_FLAGS_NO_CRC (1 << 2)
87 #define TX_BD_FLAGS_STAMP (1 << 3)
88 #define TX_BD_FLAGS_T_IP_CHKSUM (1 << 4)
89 #define TX_BD_FLAGS_LSO (1 << 5)
90 #define TX_BD_FLAGS_IPID_FMT (1 << 6)
91 #define TX_BD_FLAGS_T_IPID (1 << 7)
92 #define TX_BD_HSIZE (0xff << 16)
93 #define TX_BD_HSIZE_SHIFT 16
96 __le32 tx_bd_cfa_action;
97 #define TX_BD_CFA_ACTION (0xffff << 16)
98 #define TX_BD_CFA_ACTION_SHIFT 16
100 __le32 tx_bd_cfa_meta;
101 #define TX_BD_CFA_META_MASK 0xfffffff
102 #define TX_BD_CFA_META_VID_MASK 0xfff
103 #define TX_BD_CFA_META_PRI_MASK (0xf << 12)
104 #define TX_BD_CFA_META_PRI_SHIFT 12
105 #define TX_BD_CFA_META_TPID_MASK (3 << 16)
106 #define TX_BD_CFA_META_TPID_SHIFT 16
107 #define TX_BD_CFA_META_KEY (0xf << 28)
108 #define TX_BD_CFA_META_KEY_SHIFT 28
109 #define TX_BD_CFA_META_KEY_VLAN (1 << 28)
112 #define BNXT_TX_PTP_IS_SET(lflags) ((lflags) & cpu_to_le32(TX_BD_FLAGS_STAMP))
115 __le32 rx_bd_len_flags_type;
116 #define RX_BD_TYPE (0x3f << 0)
117 #define RX_BD_TYPE_RX_PACKET_BD 0x4
118 #define RX_BD_TYPE_RX_BUFFER_BD 0x5
119 #define RX_BD_TYPE_RX_AGG_BD 0x6
120 #define RX_BD_TYPE_16B_BD_SIZE (0 << 4)
121 #define RX_BD_TYPE_32B_BD_SIZE (1 << 4)
122 #define RX_BD_TYPE_48B_BD_SIZE (2 << 4)
123 #define RX_BD_TYPE_64B_BD_SIZE (3 << 4)
124 #define RX_BD_FLAGS_SOP (1 << 6)
125 #define RX_BD_FLAGS_EOP (1 << 7)
126 #define RX_BD_FLAGS_BUFFERS (3 << 8)
127 #define RX_BD_FLAGS_1_BUFFER_PACKET (0 << 8)
128 #define RX_BD_FLAGS_2_BUFFER_PACKET (1 << 8)
129 #define RX_BD_FLAGS_3_BUFFER_PACKET (2 << 8)
130 #define RX_BD_FLAGS_4_BUFFER_PACKET (3 << 8)
131 #define RX_BD_LEN (0xffff << 16)
132 #define RX_BD_LEN_SHIFT 16
139 __le32 tx_cmp_flags_type;
140 #define CMP_TYPE (0x3f << 0)
141 #define CMP_TYPE_TX_L2_CMP 0
142 #define CMP_TYPE_TX_L2_COAL_CMP 2
143 #define CMP_TYPE_TX_L2_PKT_TS_CMP 4
144 #define CMP_TYPE_RX_L2_CMP 17
145 #define CMP_TYPE_RX_AGG_CMP 18
146 #define CMP_TYPE_RX_L2_TPA_START_CMP 19
147 #define CMP_TYPE_RX_L2_TPA_END_CMP 21
148 #define CMP_TYPE_RX_TPA_AGG_CMP 22
149 #define CMP_TYPE_RX_L2_V3_CMP 23
150 #define CMP_TYPE_RX_L2_TPA_START_V3_CMP 25
151 #define CMP_TYPE_STATUS_CMP 32
152 #define CMP_TYPE_REMOTE_DRIVER_REQ 34
153 #define CMP_TYPE_REMOTE_DRIVER_RESP 36
154 #define CMP_TYPE_ERROR_STATUS 48
155 #define CMPL_BASE_TYPE_STAT_EJECT 0x1aUL
156 #define CMPL_BASE_TYPE_HWRM_DONE 0x20UL
157 #define CMPL_BASE_TYPE_HWRM_FWD_REQ 0x22UL
158 #define CMPL_BASE_TYPE_HWRM_FWD_RESP 0x24UL
159 #define CMPL_BASE_TYPE_HWRM_ASYNC_EVENT 0x2eUL
161 #define TX_CMP_FLAGS_ERROR (1 << 6)
162 #define TX_CMP_FLAGS_PUSH (1 << 7)
165 __le32 tx_cmp_errors_v;
166 #define TX_CMP_V (1 << 0)
167 #define TX_CMP_ERRORS_BUFFER_ERROR (7 << 1)
168 #define TX_CMP_ERRORS_BUFFER_ERROR_NO_ERROR 0
169 #define TX_CMP_ERRORS_BUFFER_ERROR_BAD_FORMAT 2
170 #define TX_CMP_ERRORS_BUFFER_ERROR_INVALID_STAG 4
171 #define TX_CMP_ERRORS_BUFFER_ERROR_STAG_BOUNDS 5
172 #define TX_CMP_ERRORS_ZERO_LENGTH_PKT (1 << 4)
173 #define TX_CMP_ERRORS_EXCESSIVE_BD_LEN (1 << 5)
174 #define TX_CMP_ERRORS_DMA_ERROR (1 << 6)
175 #define TX_CMP_ERRORS_HINT_TOO_SHORT (1 << 7)
178 #define TX_CMP_SQ_CONS_IDX_MASK 0x00ffffff
181 #define TX_CMP_SQ_CONS_IDX(txcmp) \
182 (le32_to_cpu((txcmp)->sq_cons_idx) & TX_CMP_SQ_CONS_IDX_MASK)
185 __le32 rx_cmp_len_flags_type;
186 #define RX_CMP_CMP_TYPE (0x3f << 0)
187 #define RX_CMP_FLAGS_ERROR (1 << 6)
188 #define RX_CMP_FLAGS_PLACEMENT (7 << 7)
189 #define RX_CMP_FLAGS_RSS_VALID (1 << 10)
190 #define RX_CMP_FLAGS_PKT_METADATA_PRESENT (1 << 11)
191 #define RX_CMP_FLAGS_ITYPES_SHIFT 12
192 #define RX_CMP_FLAGS_ITYPES_MASK 0xf000
193 #define RX_CMP_FLAGS_ITYPE_UNKNOWN (0 << 12)
194 #define RX_CMP_FLAGS_ITYPE_IP (1 << 12)
195 #define RX_CMP_FLAGS_ITYPE_TCP (2 << 12)
196 #define RX_CMP_FLAGS_ITYPE_UDP (3 << 12)
197 #define RX_CMP_FLAGS_ITYPE_FCOE (4 << 12)
198 #define RX_CMP_FLAGS_ITYPE_ROCE (5 << 12)
199 #define RX_CMP_FLAGS_ITYPE_PTP_WO_TS (8 << 12)
200 #define RX_CMP_FLAGS_ITYPE_PTP_W_TS (9 << 12)
201 #define RX_CMP_LEN (0xffff << 16)
202 #define RX_CMP_LEN_SHIFT 16
205 __le32 rx_cmp_misc_v1;
206 #define RX_CMP_V1 (1 << 0)
207 #define RX_CMP_AGG_BUFS (0x1f << 1)
208 #define RX_CMP_AGG_BUFS_SHIFT 1
209 #define RX_CMP_RSS_HASH_TYPE (0x7f << 9)
210 #define RX_CMP_RSS_HASH_TYPE_SHIFT 9
211 #define RX_CMP_V3_RSS_EXT_OP_LEGACY (0xf << 12)
212 #define RX_CMP_V3_RSS_EXT_OP_LEGACY_SHIFT 12
213 #define RX_CMP_V3_RSS_EXT_OP_NEW (0xf << 8)
214 #define RX_CMP_V3_RSS_EXT_OP_NEW_SHIFT 8
215 #define RX_CMP_PAYLOAD_OFFSET (0xff << 16)
216 #define RX_CMP_PAYLOAD_OFFSET_SHIFT 16
217 #define RX_CMP_SUB_NS_TS (0xf << 16)
218 #define RX_CMP_SUB_NS_TS_SHIFT 16
219 #define RX_CMP_METADATA1 (0xf << 28)
220 #define RX_CMP_METADATA1_SHIFT 28
221 #define RX_CMP_METADATA1_TPID_SEL (0x7 << 28)
222 #define RX_CMP_METADATA1_TPID_8021Q (0x1 << 28)
223 #define RX_CMP_METADATA1_TPID_8021AD (0x0 << 28)
224 #define RX_CMP_METADATA1_VALID (0x8 << 28)
226 __le32 rx_cmp_rss_hash;
229 #define BNXT_PTP_RX_TS_VALID(flags) \
230 (((flags) & RX_CMP_FLAGS_ITYPES_MASK) == RX_CMP_FLAGS_ITYPE_PTP_W_TS)
232 #define BNXT_ALL_RX_TS_VALID(flags) \
233 !((flags) & RX_CMP_FLAGS_PKT_METADATA_PRESENT)
235 #define RX_CMP_HASH_VALID(rxcmp) \
236 ((rxcmp)->rx_cmp_len_flags_type & cpu_to_le32(RX_CMP_FLAGS_RSS_VALID))
238 #define RSS_PROFILE_ID_MASK 0x1f
240 #define RX_CMP_HASH_TYPE(rxcmp) \
241 (((le32_to_cpu((rxcmp)->rx_cmp_misc_v1) & RX_CMP_RSS_HASH_TYPE) >>\
242 RX_CMP_RSS_HASH_TYPE_SHIFT) & RSS_PROFILE_ID_MASK)
244 #define RX_CMP_V3_HASH_TYPE_LEGACY(rxcmp) \
245 ((le32_to_cpu((rxcmp)->rx_cmp_misc_v1) & RX_CMP_V3_RSS_EXT_OP_LEGACY) >>\
246 RX_CMP_V3_RSS_EXT_OP_LEGACY_SHIFT)
248 #define RX_CMP_V3_HASH_TYPE_NEW(rxcmp) \
249 ((le32_to_cpu((rxcmp)->rx_cmp_misc_v1) & RX_CMP_V3_RSS_EXT_OP_NEW) >>\
250 RX_CMP_V3_RSS_EXT_OP_NEW_SHIFT)
252 #define RX_CMP_V3_HASH_TYPE(bp, rxcmp) \
253 (((bp)->rss_cap & BNXT_RSS_CAP_RSS_TCAM) ? \
254 RX_CMP_V3_HASH_TYPE_NEW(rxcmp) : \
255 RX_CMP_V3_HASH_TYPE_LEGACY(rxcmp))
257 #define EXT_OP_INNER_4 0x0
258 #define EXT_OP_OUTER_4 0x2
259 #define EXT_OP_INNFL_3 0x8
260 #define EXT_OP_OUTFL_3 0xa
262 #define RX_CMP_VLAN_VALID(rxcmp) \
263 ((rxcmp)->rx_cmp_misc_v1 & cpu_to_le32(RX_CMP_METADATA1_VALID))
265 #define RX_CMP_VLAN_TPID_SEL(rxcmp) \
266 (le32_to_cpu((rxcmp)->rx_cmp_misc_v1) & RX_CMP_METADATA1_TPID_SEL)
269 __le32 rx_cmp_flags2;
270 #define RX_CMP_FLAGS2_IP_CS_CALC 0x1
271 #define RX_CMP_FLAGS2_L4_CS_CALC (0x1 << 1)
272 #define RX_CMP_FLAGS2_T_IP_CS_CALC (0x1 << 2)
273 #define RX_CMP_FLAGS2_T_L4_CS_CALC (0x1 << 3)
274 #define RX_CMP_FLAGS2_META_FORMAT_VLAN (0x1 << 4)
275 __le32 rx_cmp_meta_data;
276 #define RX_CMP_FLAGS2_METADATA_TCI_MASK 0xffff
277 #define RX_CMP_FLAGS2_METADATA_VID_MASK 0xfff
278 #define RX_CMP_FLAGS2_METADATA_TPID_MASK 0xffff0000
279 #define RX_CMP_FLAGS2_METADATA_TPID_SFT 16
280 __le32 rx_cmp_cfa_code_errors_v2;
281 #define RX_CMP_V (1 << 0)
282 #define RX_CMPL_ERRORS_MASK (0x7fff << 1)
283 #define RX_CMPL_ERRORS_SFT 1
284 #define RX_CMPL_ERRORS_BUFFER_ERROR_MASK (0x7 << 1)
285 #define RX_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER (0x0 << 1)
286 #define RX_CMPL_ERRORS_BUFFER_ERROR_DID_NOT_FIT (0x1 << 1)
287 #define RX_CMPL_ERRORS_BUFFER_ERROR_NOT_ON_CHIP (0x2 << 1)
288 #define RX_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT (0x3 << 1)
289 #define RX_CMPL_ERRORS_IP_CS_ERROR (0x1 << 4)
290 #define RX_CMPL_ERRORS_L4_CS_ERROR (0x1 << 5)
291 #define RX_CMPL_ERRORS_T_IP_CS_ERROR (0x1 << 6)
292 #define RX_CMPL_ERRORS_T_L4_CS_ERROR (0x1 << 7)
293 #define RX_CMPL_ERRORS_CRC_ERROR (0x1 << 8)
294 #define RX_CMPL_ERRORS_T_PKT_ERROR_MASK (0x7 << 9)
295 #define RX_CMPL_ERRORS_T_PKT_ERROR_NO_ERROR (0x0 << 9)
296 #define RX_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_VERSION (0x1 << 9)
297 #define RX_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_HDR_LEN (0x2 << 9)
298 #define RX_CMPL_ERRORS_T_PKT_ERROR_TUNNEL_TOTAL_ERROR (0x3 << 9)
299 #define RX_CMPL_ERRORS_T_PKT_ERROR_T_IP_TOTAL_ERROR (0x4 << 9)
300 #define RX_CMPL_ERRORS_T_PKT_ERROR_T_UDP_TOTAL_ERROR (0x5 << 9)
301 #define RX_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL (0x6 << 9)
302 #define RX_CMPL_ERRORS_PKT_ERROR_MASK (0xf << 12)
303 #define RX_CMPL_ERRORS_PKT_ERROR_NO_ERROR (0x0 << 12)
304 #define RX_CMPL_ERRORS_PKT_ERROR_L3_BAD_VERSION (0x1 << 12)
305 #define RX_CMPL_ERRORS_PKT_ERROR_L3_BAD_HDR_LEN (0x2 << 12)
306 #define RX_CMPL_ERRORS_PKT_ERROR_L3_BAD_TTL (0x3 << 12)
307 #define RX_CMPL_ERRORS_PKT_ERROR_IP_TOTAL_ERROR (0x4 << 12)
308 #define RX_CMPL_ERRORS_PKT_ERROR_UDP_TOTAL_ERROR (0x5 << 12)
309 #define RX_CMPL_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN (0x6 << 12)
310 #define RX_CMPL_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN_TOO_SMALL (0x7 << 12)
311 #define RX_CMPL_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN (0x8 << 12)
313 #define RX_CMPL_CFA_CODE_MASK (0xffff << 16)
314 #define RX_CMPL_CFA_CODE_SFT 16
315 #define RX_CMPL_METADATA0_TCI_MASK (0xffff << 16)
316 #define RX_CMPL_METADATA0_VID_MASK (0x0fff << 16)
317 #define RX_CMPL_METADATA0_SFT 16
319 __le32 rx_cmp_timestamp;
322 #define RX_CMP_L2_ERRORS \
323 cpu_to_le32(RX_CMPL_ERRORS_BUFFER_ERROR_MASK | RX_CMPL_ERRORS_CRC_ERROR)
325 #define RX_CMP_L4_CS_BITS \
326 (cpu_to_le32(RX_CMP_FLAGS2_L4_CS_CALC | RX_CMP_FLAGS2_T_L4_CS_CALC))
328 #define RX_CMP_L4_CS_ERR_BITS \
329 (cpu_to_le32(RX_CMPL_ERRORS_L4_CS_ERROR | RX_CMPL_ERRORS_T_L4_CS_ERROR))
331 #define RX_CMP_L4_CS_OK(rxcmp1) \
332 (((rxcmp1)->rx_cmp_flags2 & RX_CMP_L4_CS_BITS) && \
333 !((rxcmp1)->rx_cmp_cfa_code_errors_v2 & RX_CMP_L4_CS_ERR_BITS))
335 #define RX_CMP_ENCAP(rxcmp1) \
336 ((le32_to_cpu((rxcmp1)->rx_cmp_flags2) & \
337 RX_CMP_FLAGS2_T_L4_CS_CALC) >> 3)
339 #define RX_CMP_CFA_CODE(rxcmpl1) \
340 ((le32_to_cpu((rxcmpl1)->rx_cmp_cfa_code_errors_v2) & \
341 RX_CMPL_CFA_CODE_MASK) >> RX_CMPL_CFA_CODE_SFT)
343 #define RX_CMP_METADATA0_TCI(rxcmp1) \
344 ((le32_to_cpu((rxcmp1)->rx_cmp_cfa_code_errors_v2) & \
345 RX_CMPL_METADATA0_TCI_MASK) >> RX_CMPL_METADATA0_SFT)
348 __le32 rx_agg_cmp_len_flags_type;
349 #define RX_AGG_CMP_TYPE (0x3f << 0)
350 #define RX_AGG_CMP_LEN (0xffff << 16)
351 #define RX_AGG_CMP_LEN_SHIFT 16
352 u32 rx_agg_cmp_opaque;
354 #define RX_AGG_CMP_V (1 << 0)
355 #define RX_AGG_CMP_AGG_ID (0xffff << 16)
356 #define RX_AGG_CMP_AGG_ID_SHIFT 16
357 __le32 rx_agg_cmp_unused;
360 #define TPA_AGG_AGG_ID(rx_agg) \
361 ((le32_to_cpu((rx_agg)->rx_agg_cmp_v) & \
362 RX_AGG_CMP_AGG_ID) >> RX_AGG_CMP_AGG_ID_SHIFT)
364 struct rx_tpa_start_cmp {
365 __le32 rx_tpa_start_cmp_len_flags_type;
366 #define RX_TPA_START_CMP_TYPE (0x3f << 0)
367 #define RX_TPA_START_CMP_FLAGS (0x3ff << 6)
368 #define RX_TPA_START_CMP_FLAGS_SHIFT 6
369 #define RX_TPA_START_CMP_FLAGS_ERROR (0x1 << 6)
370 #define RX_TPA_START_CMP_FLAGS_PLACEMENT (0x7 << 7)
371 #define RX_TPA_START_CMP_FLAGS_PLACEMENT_SHIFT 7
372 #define RX_TPA_START_CMP_FLAGS_PLACEMENT_JUMBO (0x1 << 7)
373 #define RX_TPA_START_CMP_FLAGS_PLACEMENT_HDS (0x2 << 7)
374 #define RX_TPA_START_CMP_FLAGS_PLACEMENT_GRO_JUMBO (0x5 << 7)
375 #define RX_TPA_START_CMP_FLAGS_PLACEMENT_GRO_HDS (0x6 << 7)
376 #define RX_TPA_START_CMP_FLAGS_RSS_VALID (0x1 << 10)
377 #define RX_TPA_START_CMP_FLAGS_TIMESTAMP (0x1 << 11)
378 #define RX_TPA_START_CMP_FLAGS_ITYPES (0xf << 12)
379 #define RX_TPA_START_CMP_FLAGS_ITYPES_SHIFT 12
380 #define RX_TPA_START_CMP_FLAGS_ITYPE_TCP (0x2 << 12)
381 #define RX_TPA_START_CMP_LEN (0xffff << 16)
382 #define RX_TPA_START_CMP_LEN_SHIFT 16
384 u32 rx_tpa_start_cmp_opaque;
385 __le32 rx_tpa_start_cmp_misc_v1;
386 #define RX_TPA_START_CMP_V1 (0x1 << 0)
387 #define RX_TPA_START_CMP_RSS_HASH_TYPE (0x7f << 9)
388 #define RX_TPA_START_CMP_RSS_HASH_TYPE_SHIFT 9
389 #define RX_TPA_START_CMP_V3_RSS_HASH_TYPE (0x1ff << 7)
390 #define RX_TPA_START_CMP_V3_RSS_HASH_TYPE_SHIFT 7
391 #define RX_TPA_START_CMP_AGG_ID (0x7f << 25)
392 #define RX_TPA_START_CMP_AGG_ID_SHIFT 25
393 #define RX_TPA_START_CMP_AGG_ID_P5 (0xffff << 16)
394 #define RX_TPA_START_CMP_AGG_ID_SHIFT_P5 16
395 #define RX_TPA_START_CMP_METADATA1 (0xf << 28)
396 #define RX_TPA_START_CMP_METADATA1_SHIFT 28
397 #define RX_TPA_START_METADATA1_TPID_SEL (0x7 << 28)
398 #define RX_TPA_START_METADATA1_TPID_8021Q (0x1 << 28)
399 #define RX_TPA_START_METADATA1_TPID_8021AD (0x0 << 28)
400 #define RX_TPA_START_METADATA1_VALID (0x8 << 28)
402 __le32 rx_tpa_start_cmp_rss_hash;
405 #define TPA_START_HASH_VALID(rx_tpa_start) \
406 ((rx_tpa_start)->rx_tpa_start_cmp_len_flags_type & \
407 cpu_to_le32(RX_TPA_START_CMP_FLAGS_RSS_VALID))
409 #define TPA_START_HASH_TYPE(rx_tpa_start) \
410 (((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_misc_v1) & \
411 RX_TPA_START_CMP_RSS_HASH_TYPE) >> \
412 RX_TPA_START_CMP_RSS_HASH_TYPE_SHIFT) & RSS_PROFILE_ID_MASK)
414 #define TPA_START_V3_HASH_TYPE(rx_tpa_start) \
415 (((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_misc_v1) & \
416 RX_TPA_START_CMP_V3_RSS_HASH_TYPE) >> \
417 RX_TPA_START_CMP_V3_RSS_HASH_TYPE_SHIFT) & RSS_PROFILE_ID_MASK)
419 #define TPA_START_AGG_ID(rx_tpa_start) \
420 ((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_misc_v1) & \
421 RX_TPA_START_CMP_AGG_ID) >> RX_TPA_START_CMP_AGG_ID_SHIFT)
423 #define TPA_START_AGG_ID_P5(rx_tpa_start) \
424 ((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_misc_v1) & \
425 RX_TPA_START_CMP_AGG_ID_P5) >> RX_TPA_START_CMP_AGG_ID_SHIFT_P5)
427 #define TPA_START_ERROR(rx_tpa_start) \
428 ((rx_tpa_start)->rx_tpa_start_cmp_len_flags_type & \
429 cpu_to_le32(RX_TPA_START_CMP_FLAGS_ERROR))
431 #define TPA_START_VLAN_VALID(rx_tpa_start) \
432 ((rx_tpa_start)->rx_tpa_start_cmp_misc_v1 & \
433 cpu_to_le32(RX_TPA_START_METADATA1_VALID))
435 #define TPA_START_VLAN_TPID_SEL(rx_tpa_start) \
436 (le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_misc_v1) & \
437 RX_TPA_START_METADATA1_TPID_SEL)
439 struct rx_tpa_start_cmp_ext {
440 __le32 rx_tpa_start_cmp_flags2;
441 #define RX_TPA_START_CMP_FLAGS2_IP_CS_CALC (0x1 << 0)
442 #define RX_TPA_START_CMP_FLAGS2_L4_CS_CALC (0x1 << 1)
443 #define RX_TPA_START_CMP_FLAGS2_T_IP_CS_CALC (0x1 << 2)
444 #define RX_TPA_START_CMP_FLAGS2_T_L4_CS_CALC (0x1 << 3)
445 #define RX_TPA_START_CMP_FLAGS2_IP_TYPE (0x1 << 8)
446 #define RX_TPA_START_CMP_FLAGS2_CSUM_CMPL_VALID (0x1 << 9)
447 #define RX_TPA_START_CMP_FLAGS2_EXT_META_FORMAT (0x3 << 10)
448 #define RX_TPA_START_CMP_FLAGS2_EXT_META_FORMAT_SHIFT 10
449 #define RX_TPA_START_CMP_V3_FLAGS2_T_IP_TYPE (0x1 << 10)
450 #define RX_TPA_START_CMP_V3_FLAGS2_AGG_GRO (0x1 << 11)
451 #define RX_TPA_START_CMP_FLAGS2_CSUM_CMPL (0xffff << 16)
452 #define RX_TPA_START_CMP_FLAGS2_CSUM_CMPL_SHIFT 16
454 __le32 rx_tpa_start_cmp_metadata;
455 __le32 rx_tpa_start_cmp_cfa_code_v2;
456 #define RX_TPA_START_CMP_V2 (0x1 << 0)
457 #define RX_TPA_START_CMP_ERRORS_BUFFER_ERROR_MASK (0x7 << 1)
458 #define RX_TPA_START_CMP_ERRORS_BUFFER_ERROR_SHIFT 1
459 #define RX_TPA_START_CMP_ERRORS_BUFFER_ERROR_NO_BUFFER (0x0 << 1)
460 #define RX_TPA_START_CMP_ERRORS_BUFFER_ERROR_BAD_FORMAT (0x3 << 1)
461 #define RX_TPA_START_CMP_ERRORS_BUFFER_ERROR_FLUSH (0x5 << 1)
462 #define RX_TPA_START_CMP_CFA_CODE (0xffff << 16)
463 #define RX_TPA_START_CMPL_CFA_CODE_SHIFT 16
464 #define RX_TPA_START_CMP_METADATA0_TCI_MASK (0xffff << 16)
465 #define RX_TPA_START_CMP_METADATA0_VID_MASK (0x0fff << 16)
466 #define RX_TPA_START_CMP_METADATA0_SFT 16
467 __le32 rx_tpa_start_cmp_hdr_info;
470 #define TPA_START_CFA_CODE(rx_tpa_start) \
471 ((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_cfa_code_v2) & \
472 RX_TPA_START_CMP_CFA_CODE) >> RX_TPA_START_CMPL_CFA_CODE_SHIFT)
474 #define TPA_START_IS_IPV6(rx_tpa_start) \
475 (!!((rx_tpa_start)->rx_tpa_start_cmp_flags2 & \
476 cpu_to_le32(RX_TPA_START_CMP_FLAGS2_IP_TYPE)))
478 #define TPA_START_ERROR_CODE(rx_tpa_start) \
479 ((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_cfa_code_v2) & \
480 RX_TPA_START_CMP_ERRORS_BUFFER_ERROR_MASK) >> \
481 RX_TPA_START_CMP_ERRORS_BUFFER_ERROR_SHIFT)
483 #define TPA_START_METADATA0_TCI(rx_tpa_start) \
484 ((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_cfa_code_v2) & \
485 RX_TPA_START_CMP_METADATA0_TCI_MASK) >> \
486 RX_TPA_START_CMP_METADATA0_SFT)
488 struct rx_tpa_end_cmp {
489 __le32 rx_tpa_end_cmp_len_flags_type;
490 #define RX_TPA_END_CMP_TYPE (0x3f << 0)
491 #define RX_TPA_END_CMP_FLAGS (0x3ff << 6)
492 #define RX_TPA_END_CMP_FLAGS_SHIFT 6
493 #define RX_TPA_END_CMP_FLAGS_PLACEMENT (0x7 << 7)
494 #define RX_TPA_END_CMP_FLAGS_PLACEMENT_SHIFT 7
495 #define RX_TPA_END_CMP_FLAGS_PLACEMENT_JUMBO (0x1 << 7)
496 #define RX_TPA_END_CMP_FLAGS_PLACEMENT_HDS (0x2 << 7)
497 #define RX_TPA_END_CMP_FLAGS_PLACEMENT_GRO_JUMBO (0x5 << 7)
498 #define RX_TPA_END_CMP_FLAGS_PLACEMENT_GRO_HDS (0x6 << 7)
499 #define RX_TPA_END_CMP_FLAGS_RSS_VALID (0x1 << 10)
500 #define RX_TPA_END_CMP_FLAGS_ITYPES (0xf << 12)
501 #define RX_TPA_END_CMP_FLAGS_ITYPES_SHIFT 12
502 #define RX_TPA_END_CMP_FLAGS_ITYPE_TCP (0x2 << 12)
503 #define RX_TPA_END_CMP_LEN (0xffff << 16)
504 #define RX_TPA_END_CMP_LEN_SHIFT 16
506 u32 rx_tpa_end_cmp_opaque;
507 __le32 rx_tpa_end_cmp_misc_v1;
508 #define RX_TPA_END_CMP_V1 (0x1 << 0)
509 #define RX_TPA_END_CMP_AGG_BUFS (0x3f << 1)
510 #define RX_TPA_END_CMP_AGG_BUFS_SHIFT 1
511 #define RX_TPA_END_CMP_TPA_SEGS (0xff << 8)
512 #define RX_TPA_END_CMP_TPA_SEGS_SHIFT 8
513 #define RX_TPA_END_CMP_PAYLOAD_OFFSET (0xff << 16)
514 #define RX_TPA_END_CMP_PAYLOAD_OFFSET_SHIFT 16
515 #define RX_TPA_END_CMP_AGG_ID (0x7f << 25)
516 #define RX_TPA_END_CMP_AGG_ID_SHIFT 25
517 #define RX_TPA_END_CMP_AGG_ID_P5 (0xffff << 16)
518 #define RX_TPA_END_CMP_AGG_ID_SHIFT_P5 16
520 __le32 rx_tpa_end_cmp_tsdelta;
521 #define RX_TPA_END_GRO_TS (0x1 << 31)
524 #define TPA_END_AGG_ID(rx_tpa_end) \
525 ((le32_to_cpu((rx_tpa_end)->rx_tpa_end_cmp_misc_v1) & \
526 RX_TPA_END_CMP_AGG_ID) >> RX_TPA_END_CMP_AGG_ID_SHIFT)
528 #define TPA_END_AGG_ID_P5(rx_tpa_end) \
529 ((le32_to_cpu((rx_tpa_end)->rx_tpa_end_cmp_misc_v1) & \
530 RX_TPA_END_CMP_AGG_ID_P5) >> RX_TPA_END_CMP_AGG_ID_SHIFT_P5)
532 #define TPA_END_PAYLOAD_OFF(rx_tpa_end) \
533 ((le32_to_cpu((rx_tpa_end)->rx_tpa_end_cmp_misc_v1) & \
534 RX_TPA_END_CMP_PAYLOAD_OFFSET) >> RX_TPA_END_CMP_PAYLOAD_OFFSET_SHIFT)
536 #define TPA_END_AGG_BUFS(rx_tpa_end) \
537 ((le32_to_cpu((rx_tpa_end)->rx_tpa_end_cmp_misc_v1) & \
538 RX_TPA_END_CMP_AGG_BUFS) >> RX_TPA_END_CMP_AGG_BUFS_SHIFT)
540 #define TPA_END_TPA_SEGS(rx_tpa_end) \
541 ((le32_to_cpu((rx_tpa_end)->rx_tpa_end_cmp_misc_v1) & \
542 RX_TPA_END_CMP_TPA_SEGS) >> RX_TPA_END_CMP_TPA_SEGS_SHIFT)
544 #define RX_TPA_END_CMP_FLAGS_PLACEMENT_ANY_GRO \
545 cpu_to_le32(RX_TPA_END_CMP_FLAGS_PLACEMENT_GRO_JUMBO & \
546 RX_TPA_END_CMP_FLAGS_PLACEMENT_GRO_HDS)
548 #define TPA_END_GRO(rx_tpa_end) \
549 ((rx_tpa_end)->rx_tpa_end_cmp_len_flags_type & \
550 RX_TPA_END_CMP_FLAGS_PLACEMENT_ANY_GRO)
552 #define TPA_END_GRO_TS(rx_tpa_end) \
553 (!!((rx_tpa_end)->rx_tpa_end_cmp_tsdelta & \
554 cpu_to_le32(RX_TPA_END_GRO_TS)))
556 struct rx_tpa_end_cmp_ext {
557 __le32 rx_tpa_end_cmp_dup_acks;
558 #define RX_TPA_END_CMP_TPA_DUP_ACKS (0xf << 0)
559 #define RX_TPA_END_CMP_PAYLOAD_OFFSET_P5 (0xff << 16)
560 #define RX_TPA_END_CMP_PAYLOAD_OFFSET_SHIFT_P5 16
561 #define RX_TPA_END_CMP_AGG_BUFS_P5 (0xff << 24)
562 #define RX_TPA_END_CMP_AGG_BUFS_SHIFT_P5 24
564 __le32 rx_tpa_end_cmp_seg_len;
565 #define RX_TPA_END_CMP_TPA_SEG_LEN (0xffff << 0)
567 __le32 rx_tpa_end_cmp_errors_v2;
568 #define RX_TPA_END_CMP_V2 (0x1 << 0)
569 #define RX_TPA_END_CMP_ERRORS (0x3 << 1)
570 #define RX_TPA_END_CMP_ERRORS_P5 (0x7 << 1)
571 #define RX_TPA_END_CMPL_ERRORS_SHIFT 1
572 #define RX_TPA_END_CMP_ERRORS_BUFFER_ERROR_NO_BUFFER (0x0 << 1)
573 #define RX_TPA_END_CMP_ERRORS_BUFFER_ERROR_NOT_ON_CHIP (0x2 << 1)
574 #define RX_TPA_END_CMP_ERRORS_BUFFER_ERROR_BAD_FORMAT (0x3 << 1)
575 #define RX_TPA_END_CMP_ERRORS_BUFFER_ERROR_RSV_ERROR (0x4 << 1)
576 #define RX_TPA_END_CMP_ERRORS_BUFFER_ERROR_FLUSH (0x5 << 1)
578 u32 rx_tpa_end_cmp_start_opaque;
581 #define TPA_END_ERRORS(rx_tpa_end_ext) \
582 ((rx_tpa_end_ext)->rx_tpa_end_cmp_errors_v2 & \
583 cpu_to_le32(RX_TPA_END_CMP_ERRORS))
585 #define TPA_END_PAYLOAD_OFF_P5(rx_tpa_end_ext) \
586 ((le32_to_cpu((rx_tpa_end_ext)->rx_tpa_end_cmp_dup_acks) & \
587 RX_TPA_END_CMP_PAYLOAD_OFFSET_P5) >> \
588 RX_TPA_END_CMP_PAYLOAD_OFFSET_SHIFT_P5)
590 #define TPA_END_AGG_BUFS_P5(rx_tpa_end_ext) \
591 ((le32_to_cpu((rx_tpa_end_ext)->rx_tpa_end_cmp_dup_acks) & \
592 RX_TPA_END_CMP_AGG_BUFS_P5) >> RX_TPA_END_CMP_AGG_BUFS_SHIFT_P5)
594 #define EVENT_DATA1_RESET_NOTIFY_FATAL(data1) \
596 ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_MASK) ==\
597 ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_FATAL)
599 #define EVENT_DATA1_RESET_NOTIFY_FW_ACTIVATION(data1) \
601 ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_MASK) ==\
602 ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_ACTIVATION)
604 #define EVENT_DATA2_RESET_NOTIFY_FW_STATUS_CODE(data2) \
606 ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA2_FW_STATUS_CODE_MASK)
608 #define EVENT_DATA1_RECOVERY_MASTER_FUNC(data1) \
610 ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_MASTER_FUNC)
612 #define EVENT_DATA1_RECOVERY_ENABLED(data1) \
614 ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_RECOVERY_ENABLED)
616 #define BNXT_EVENT_ERROR_REPORT_TYPE(data1) \
618 ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_MASK) >>\
619 ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_SFT)
621 #define BNXT_EVENT_INVALID_SIGNAL_DATA(data2) \
623 ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA2_PIN_ID_MASK) >>\
624 ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA2_PIN_ID_SFT)
628 #define NQ_CN_TYPE_MASK 0x3fUL
629 #define NQ_CN_TYPE_SFT 0
630 #define NQ_CN_TYPE_CQ_NOTIFICATION 0x30UL
631 #define NQ_CN_TYPE_LAST NQ_CN_TYPE_CQ_NOTIFICATION
632 #define NQ_CN_TOGGLE_MASK 0xc0UL
633 #define NQ_CN_TOGGLE_SFT 6
635 __le32 cq_handle_low;
637 #define NQ_CN_V 0x1UL
638 __le32 cq_handle_high;
641 #define BNXT_NQ_HDL_IDX_MASK 0x00ffffff
642 #define BNXT_NQ_HDL_TYPE_MASK 0xff000000
643 #define BNXT_NQ_HDL_TYPE_SHIFT 24
644 #define BNXT_NQ_HDL_TYPE_RX 0x00
645 #define BNXT_NQ_HDL_TYPE_TX 0x01
647 #define BNXT_NQ_HDL_IDX(hdl) ((hdl) & BNXT_NQ_HDL_IDX_MASK)
648 #define BNXT_NQ_HDL_TYPE(hdl) (((hdl) & BNXT_NQ_HDL_TYPE_MASK) >> \
649 BNXT_NQ_HDL_TYPE_SHIFT)
651 #define BNXT_SET_NQ_HDL(cpr) \
652 (((cpr)->cp_ring_type << BNXT_NQ_HDL_TYPE_SHIFT) | (cpr)->cp_idx)
654 #define NQE_CN_TYPE(type) ((type) & NQ_CN_TYPE_MASK)
655 #define NQE_CN_TOGGLE(type) (((type) & NQ_CN_TOGGLE_MASK) >> \
658 #define DB_IDX_MASK 0xffffff
659 #define DB_IDX_VALID (0x1 << 26)
660 #define DB_IRQ_DIS (0x1 << 27)
661 #define DB_KEY_TX (0x0 << 28)
662 #define DB_KEY_RX (0x1 << 28)
663 #define DB_KEY_CP (0x2 << 28)
664 #define DB_KEY_ST (0x3 << 28)
665 #define DB_KEY_TX_PUSH (0x4 << 28)
666 #define DB_LONG_TX_PUSH (0x2 << 24)
668 #define BNXT_MIN_ROCE_CP_RINGS 2
669 #define BNXT_MIN_ROCE_STAT_CTXS 1
671 /* 64-bit doorbell */
672 #define DBR_INDEX_MASK 0x0000000000ffffffULL
673 #define DBR_EPOCH_MASK 0x01000000UL
674 #define DBR_EPOCH_SFT 24
675 #define DBR_TOGGLE_MASK 0x06000000UL
676 #define DBR_TOGGLE_SFT 25
677 #define DBR_XID_MASK 0x000fffff00000000ULL
678 #define DBR_XID_SFT 32
679 #define DBR_PATH_L2 (0x1ULL << 56)
680 #define DBR_VALID (0x1ULL << 58)
681 #define DBR_TYPE_SQ (0x0ULL << 60)
682 #define DBR_TYPE_RQ (0x1ULL << 60)
683 #define DBR_TYPE_SRQ (0x2ULL << 60)
684 #define DBR_TYPE_SRQ_ARM (0x3ULL << 60)
685 #define DBR_TYPE_CQ (0x4ULL << 60)
686 #define DBR_TYPE_CQ_ARMSE (0x5ULL << 60)
687 #define DBR_TYPE_CQ_ARMALL (0x6ULL << 60)
688 #define DBR_TYPE_CQ_ARMENA (0x7ULL << 60)
689 #define DBR_TYPE_SRQ_ARMENA (0x8ULL << 60)
690 #define DBR_TYPE_CQ_CUTOFF_ACK (0x9ULL << 60)
691 #define DBR_TYPE_NQ (0xaULL << 60)
692 #define DBR_TYPE_NQ_ARM (0xbULL << 60)
693 #define DBR_TYPE_NQ_MASK (0xeULL << 60)
694 #define DBR_TYPE_NULL (0xfULL << 60)
696 #define DB_PF_OFFSET_P5 0x10000
697 #define DB_VF_OFFSET_P5 0x4000
699 #define INVALID_HW_RING_ID ((u16)-1)
701 /* The hardware supports certain page sizes. Use the supported page sizes
702 * to allocate the rings.
704 #if (PAGE_SHIFT < 12)
705 #define BNXT_PAGE_SHIFT 12
706 #elif (PAGE_SHIFT <= 13)
707 #define BNXT_PAGE_SHIFT PAGE_SHIFT
708 #elif (PAGE_SHIFT < 16)
709 #define BNXT_PAGE_SHIFT 13
711 #define BNXT_PAGE_SHIFT 16
714 #define BNXT_PAGE_SIZE (1 << BNXT_PAGE_SHIFT)
716 /* The RXBD length is 16-bit so we can only support page sizes < 64K */
717 #if (PAGE_SHIFT > 15)
718 #define BNXT_RX_PAGE_SHIFT 15
720 #define BNXT_RX_PAGE_SHIFT PAGE_SHIFT
723 #define BNXT_RX_PAGE_SIZE (1 << BNXT_RX_PAGE_SHIFT)
725 #define BNXT_MAX_MTU 9500
727 /* First RX buffer page in XDP multi-buf mode
729 * +-------------------------------------------------------------------------+
730 * | XDP_PACKET_HEADROOM | bp->rx_buf_use_size | skb_shared_info|
731 * | (bp->rx_dma_offset) | | |
732 * +-------------------------------------------------------------------------+
734 #define BNXT_MAX_PAGE_MODE_MTU_SBUF \
735 ((unsigned int)PAGE_SIZE - VLAN_ETH_HLEN - NET_IP_ALIGN - \
737 #define BNXT_MAX_PAGE_MODE_MTU \
738 (BNXT_MAX_PAGE_MODE_MTU_SBUF - \
739 SKB_DATA_ALIGN((unsigned int)sizeof(struct skb_shared_info)))
741 #define BNXT_MIN_PKT_SIZE 52
743 #define BNXT_DEFAULT_RX_RING_SIZE 511
744 #define BNXT_DEFAULT_TX_RING_SIZE 511
747 #define MAX_TPA_P5 256
748 #define MAX_TPA_P5_MASK (MAX_TPA_P5 - 1)
749 #define MAX_TPA_SEGS_P5 0x3f
751 #if (BNXT_PAGE_SHIFT == 16)
752 #define MAX_RX_PAGES_AGG_ENA 1
753 #define MAX_RX_PAGES 4
754 #define MAX_RX_AGG_PAGES 4
755 #define MAX_TX_PAGES 1
756 #define MAX_CP_PAGES 16
758 #define MAX_RX_PAGES_AGG_ENA 8
759 #define MAX_RX_PAGES 32
760 #define MAX_RX_AGG_PAGES 32
761 #define MAX_TX_PAGES 8
762 #define MAX_CP_PAGES 128
765 #define RX_DESC_CNT (BNXT_PAGE_SIZE / sizeof(struct rx_bd))
766 #define TX_DESC_CNT (BNXT_PAGE_SIZE / sizeof(struct tx_bd))
767 #define CP_DESC_CNT (BNXT_PAGE_SIZE / sizeof(struct tx_cmp))
769 #define SW_RXBD_RING_SIZE (sizeof(struct bnxt_sw_rx_bd) * RX_DESC_CNT)
770 #define HW_RXBD_RING_SIZE (sizeof(struct rx_bd) * RX_DESC_CNT)
772 #define SW_RXBD_AGG_RING_SIZE (sizeof(struct bnxt_sw_rx_agg_bd) * RX_DESC_CNT)
774 #define SW_TXBD_RING_SIZE (sizeof(struct bnxt_sw_tx_bd) * TX_DESC_CNT)
775 #define HW_TXBD_RING_SIZE (sizeof(struct tx_bd) * TX_DESC_CNT)
777 #define HW_CMPD_RING_SIZE (sizeof(struct tx_cmp) * CP_DESC_CNT)
779 #define BNXT_MAX_RX_DESC_CNT (RX_DESC_CNT * MAX_RX_PAGES - 1)
780 #define BNXT_MAX_RX_DESC_CNT_JUM_ENA (RX_DESC_CNT * MAX_RX_PAGES_AGG_ENA - 1)
781 #define BNXT_MAX_RX_JUM_DESC_CNT (RX_DESC_CNT * MAX_RX_AGG_PAGES - 1)
782 #define BNXT_MAX_TX_DESC_CNT (TX_DESC_CNT * MAX_TX_PAGES - 1)
784 /* Minimum TX BDs for a TX packet with MAX_SKB_FRAGS + 1. We need one extra
785 * BD because the first TX BD is always a long BD.
787 #define BNXT_MIN_TX_DESC_CNT (MAX_SKB_FRAGS + 2)
789 #define RX_RING(bp, x) (((x) & (bp)->rx_ring_mask) >> (BNXT_PAGE_SHIFT - 4))
790 #define RX_AGG_RING(bp, x) (((x) & (bp)->rx_agg_ring_mask) >> \
791 (BNXT_PAGE_SHIFT - 4))
792 #define RX_IDX(x) ((x) & (RX_DESC_CNT - 1))
794 #define TX_RING(bp, x) (((x) & (bp)->tx_ring_mask) >> (BNXT_PAGE_SHIFT - 4))
795 #define TX_IDX(x) ((x) & (TX_DESC_CNT - 1))
797 #define CP_RING(x) (((x) & ~(CP_DESC_CNT - 1)) >> (BNXT_PAGE_SHIFT - 4))
798 #define CP_IDX(x) ((x) & (CP_DESC_CNT - 1))
800 #define TX_CMP_VALID(txcmp, raw_cons) \
801 (!!((txcmp)->tx_cmp_errors_v & cpu_to_le32(TX_CMP_V)) == \
802 !((raw_cons) & bp->cp_bit))
804 #define RX_CMP_VALID(rxcmp1, raw_cons) \
805 (!!((rxcmp1)->rx_cmp_cfa_code_errors_v2 & cpu_to_le32(RX_CMP_V)) ==\
806 !((raw_cons) & bp->cp_bit))
808 #define RX_AGG_CMP_VALID(agg, raw_cons) \
809 (!!((agg)->rx_agg_cmp_v & cpu_to_le32(RX_AGG_CMP_V)) == \
810 !((raw_cons) & bp->cp_bit))
812 #define NQ_CMP_VALID(nqcmp, raw_cons) \
813 (!!((nqcmp)->v & cpu_to_le32(NQ_CN_V)) == !((raw_cons) & bp->cp_bit))
815 #define TX_CMP_TYPE(txcmp) \
816 (le32_to_cpu((txcmp)->tx_cmp_flags_type) & CMP_TYPE)
818 #define RX_CMP_TYPE(rxcmp) \
819 (le32_to_cpu((rxcmp)->rx_cmp_len_flags_type) & RX_CMP_CMP_TYPE)
821 #define RING_RX(bp, idx) ((idx) & (bp)->rx_ring_mask)
822 #define NEXT_RX(idx) ((idx) + 1)
824 #define RING_RX_AGG(bp, idx) ((idx) & (bp)->rx_agg_ring_mask)
825 #define NEXT_RX_AGG(idx) ((idx) + 1)
827 #define RING_TX(bp, idx) ((idx) & (bp)->tx_ring_mask)
828 #define NEXT_TX(idx) ((idx) + 1)
830 #define ADV_RAW_CMP(idx, n) ((idx) + (n))
831 #define NEXT_RAW_CMP(idx) ADV_RAW_CMP(idx, 1)
832 #define RING_CMP(idx) ((idx) & bp->cp_ring_mask)
833 #define NEXT_CMP(idx) RING_CMP(ADV_RAW_CMP(idx, 1))
835 #define DFLT_HWRM_CMD_TIMEOUT 500
837 #define BNXT_RX_EVENT 1
838 #define BNXT_AGG_EVENT 2
839 #define BNXT_TX_EVENT 4
840 #define BNXT_REDIRECT_EVENT 8
841 #define BNXT_TX_CMP_EVENT 0x10
843 struct bnxt_sw_tx_bd {
846 struct xdp_frame *xdpf;
848 DEFINE_DMA_UNMAP_ADDR(mapping);
849 DEFINE_DMA_UNMAP_LEN(len);
854 unsigned short nr_frags;
858 struct bnxt_sw_rx_bd {
864 struct bnxt_sw_rx_agg_bd {
870 struct bnxt_ring_mem_info {
874 #define BNXT_RMEM_VALID_PTE_FLAG 1
875 #define BNXT_RMEM_RING_PTE_FLAG 2
876 #define BNXT_RMEM_USE_FULL_PAGE_FLAG 4
879 struct bnxt_ctx_mem_type *ctx_mem;
885 dma_addr_t pg_tbl_map;
891 struct bnxt_ring_struct {
892 struct bnxt_ring_mem_info ring_mem;
894 u16 fw_ring_id; /* Ring id filled by Chimp FW */
897 u16 map_idx; /* Used by cmpl rings */
905 __le32 tx_bd_len_flags_type;
907 struct tx_bd_ext txbd2;
910 struct tx_push_buffer {
911 struct tx_push_bd push_bd;
915 struct bnxt_db_info {
916 void __iomem *doorbell;
926 #define DB_EPOCH(db, idx) (((idx) & (db)->db_epoch_mask) << \
927 ((db)->db_epoch_shift))
929 #define DB_TOGGLE(tgl) ((tgl) << DBR_TOGGLE_SFT)
931 #define DB_RING_IDX(db, idx) (((idx) & (db)->db_ring_mask) | \
934 struct bnxt_tx_ring_info {
935 struct bnxt_napi *bnapi;
936 struct bnxt_cp_ring_info *tx_cpr;
943 struct bnxt_db_info tx_db;
945 struct tx_bd *tx_desc_ring[MAX_TX_PAGES];
946 struct bnxt_sw_tx_bd *tx_buf_ring;
948 dma_addr_t tx_desc_mapping[MAX_TX_PAGES];
950 struct tx_push_buffer *tx_push;
951 dma_addr_t tx_push_mapping;
954 #define BNXT_DEV_STATE_CLOSING 0x1
957 struct bnxt_ring_struct tx_ring_struct;
958 /* Synchronize simultaneous xdp_xmit on same ring */
959 spinlock_t xdp_tx_lock;
962 #define BNXT_LEGACY_COAL_CMPL_PARAMS \
963 (RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_INT_LAT_TMR_MIN | \
964 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_INT_LAT_TMR_MAX | \
965 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_TIMER_RESET | \
966 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_RING_IDLE | \
967 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_DMA_AGGR | \
968 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_DMA_AGGR_DURING_INT | \
969 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_CMPL_AGGR_DMA_TMR | \
970 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_CMPL_AGGR_DMA_TMR_DURING_INT | \
971 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_AGGR_INT)
973 #define BNXT_COAL_CMPL_ENABLES \
974 (RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_DMA_AGGR | \
975 RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_CMPL_AGGR_DMA_TMR | \
976 RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_INT_LAT_TMR_MAX | \
977 RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_AGGR_INT)
979 #define BNXT_COAL_CMPL_MIN_TMR_ENABLE \
980 RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_INT_LAT_TMR_MIN
982 #define BNXT_COAL_CMPL_AGGR_TMR_DURING_INT_ENABLE \
983 RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_DMA_AGGR_DURING_INT
985 struct bnxt_coal_cap {
988 u16 num_cmpl_dma_aggr_max;
989 u16 num_cmpl_dma_aggr_during_int_max;
990 u16 cmpl_aggr_dma_tmr_max;
991 u16 cmpl_aggr_dma_tmr_during_int_max;
992 u16 int_lat_tmr_min_max;
993 u16 int_lat_tmr_max_max;
994 u16 num_cmpl_aggr_int_max;
1003 /* RING_IDLE enabled when coal ticks < idle_thresh */
1010 struct bnxt_tpa_info {
1015 unsigned short gso_type;
1018 enum pkt_hash_types hash_type;
1022 #define BNXT_TPA_L4_SIZE(hdr_info) \
1023 (((hdr_info) & 0xf8000000) ? ((hdr_info) >> 27) : 32)
1025 #define BNXT_TPA_INNER_L3_OFF(hdr_info) \
1026 (((hdr_info) >> 18) & 0x1ff)
1028 #define BNXT_TPA_INNER_L2_OFF(hdr_info) \
1029 (((hdr_info) >> 9) & 0x1ff)
1031 #define BNXT_TPA_OUTER_L3_OFF(hdr_info) \
1032 ((hdr_info) & 0x1ff)
1034 u16 cfa_code; /* cfa_code in TPA start compl */
1037 u8 cfa_code_valid:1;
1038 struct rx_agg_cmp *agg_arr;
1041 #define BNXT_AGG_IDX_BMAP_SIZE (MAX_TPA_P5 / BITS_PER_LONG)
1043 struct bnxt_tpa_idx_map {
1044 u16 agg_id_tbl[1024];
1045 unsigned long agg_idx_bmap[BNXT_AGG_IDX_BMAP_SIZE];
1048 struct bnxt_rx_ring_info {
1049 struct bnxt_napi *bnapi;
1050 struct bnxt_cp_ring_info *rx_cpr;
1055 struct bnxt_db_info rx_db;
1056 struct bnxt_db_info rx_agg_db;
1058 struct bpf_prog *xdp_prog;
1060 struct rx_bd *rx_desc_ring[MAX_RX_PAGES];
1061 struct bnxt_sw_rx_bd *rx_buf_ring;
1063 struct rx_bd *rx_agg_desc_ring[MAX_RX_AGG_PAGES];
1064 struct bnxt_sw_rx_agg_bd *rx_agg_ring;
1066 unsigned long *rx_agg_bmap;
1067 u16 rx_agg_bmap_size;
1069 dma_addr_t rx_desc_mapping[MAX_RX_PAGES];
1070 dma_addr_t rx_agg_desc_mapping[MAX_RX_AGG_PAGES];
1072 struct bnxt_tpa_info *rx_tpa;
1073 struct bnxt_tpa_idx_map *rx_tpa_idx_map;
1075 struct bnxt_ring_struct rx_ring_struct;
1076 struct bnxt_ring_struct rx_agg_ring_struct;
1077 struct xdp_rxq_info xdp_rxq;
1078 struct page_pool *page_pool;
1081 struct bnxt_rx_sw_stats {
1082 u64 rx_l4_csum_errors;
1085 u64 rx_oom_discards;
1086 u64 rx_netpoll_discards;
1089 struct bnxt_tx_sw_stats {
1093 struct bnxt_cmn_sw_stats {
1097 struct bnxt_sw_stats {
1098 struct bnxt_rx_sw_stats rx;
1099 struct bnxt_tx_sw_stats tx;
1100 struct bnxt_cmn_sw_stats cmn;
1103 struct bnxt_total_ring_err_stats {
1104 u64 rx_total_l4_csum_errors;
1105 u64 rx_total_resets;
1106 u64 rx_total_buf_errors;
1107 u64 rx_total_oom_discards;
1108 u64 rx_total_netpoll_discards;
1109 u64 rx_total_ring_discards;
1110 u64 tx_total_resets;
1111 u64 tx_total_ring_discards;
1112 u64 total_missed_irqs;
1115 struct bnxt_stats_mem {
1119 dma_addr_t hw_stats_map;
1123 struct bnxt_cp_ring_info {
1124 struct bnxt_napi *bnapi;
1126 struct bnxt_db_info cp_db;
1130 u8 had_nqe_notify:1;
1136 u32 last_cp_raw_cons;
1138 struct bnxt_coal rx_ring_coal;
1146 struct tx_cmp **cp_desc_ring;
1147 struct nqe_cn **nq_desc_ring;
1150 dma_addr_t *cp_desc_mapping;
1152 struct bnxt_stats_mem stats;
1153 u32 hw_stats_ctx_id;
1155 struct bnxt_sw_stats sw_stats;
1157 struct bnxt_ring_struct cp_ring_struct;
1160 struct bnxt_cp_ring_info *cp_ring_arr;
1163 #define BNXT_MAX_QUEUE 8
1164 #define BNXT_MAX_TXR_PER_NAPI BNXT_MAX_QUEUE
1166 #define bnxt_for_each_napi_tx(iter, bnapi, txr) \
1167 for (iter = 0, txr = (bnapi)->tx_ring[0]; txr; \
1168 txr = (iter < BNXT_MAX_TXR_PER_NAPI - 1) ? \
1169 (bnapi)->tx_ring[++iter] : NULL)
1172 struct napi_struct napi;
1176 struct bnxt_cp_ring_info cp_ring;
1177 struct bnxt_rx_ring_info *rx_ring;
1178 struct bnxt_tx_ring_info *tx_ring[BNXT_MAX_TXR_PER_NAPI];
1180 void (*tx_int)(struct bnxt *, struct bnxt_napi *,
1186 #define BNXT_NAPI_FLAG_XDP 0x1
1192 irq_handler_t handler;
1193 unsigned int vector;
1196 char name[IFNAMSIZ + 2];
1197 cpumask_var_t cpu_mask;
1200 #define HWRM_RING_ALLOC_TX 0x1
1201 #define HWRM_RING_ALLOC_RX 0x2
1202 #define HWRM_RING_ALLOC_AGG 0x4
1203 #define HWRM_RING_ALLOC_CMPL 0x8
1204 #define HWRM_RING_ALLOC_NQ 0x10
1206 #define INVALID_STATS_CTX_ID -1
1208 struct bnxt_ring_grp_info {
1216 struct bnxt_vnic_info {
1217 u16 fw_vnic_id; /* returned by Chimp during alloc */
1218 #define BNXT_MAX_CTX_PER_VNIC 8
1219 u16 fw_rss_cos_lb_ctx[BNXT_MAX_CTX_PER_VNIC];
1221 #define BNXT_MAX_UC_ADDRS 4
1222 struct bnxt_l2_filter *l2_filters[BNXT_MAX_UC_ADDRS];
1223 /* index 0 always dev_addr */
1224 u16 uc_filter_count;
1228 dma_addr_t rss_table_dma_addr;
1230 dma_addr_t rss_hash_key_dma_addr;
1233 #define BNXT_RSS_TABLE_ENTRIES_P5 64
1234 #define BNXT_RSS_TABLE_SIZE_P5 (BNXT_RSS_TABLE_ENTRIES_P5 * 4)
1235 #define BNXT_RSS_TABLE_MAX_TBL_P5 8
1236 #define BNXT_MAX_RSS_TABLE_SIZE_P5 \
1237 (BNXT_RSS_TABLE_SIZE_P5 * BNXT_RSS_TABLE_MAX_TBL_P5)
1238 #define BNXT_MAX_RSS_TABLE_ENTRIES_P5 \
1239 (BNXT_RSS_TABLE_ENTRIES_P5 * BNXT_RSS_TABLE_MAX_TBL_P5)
1246 dma_addr_t mc_list_mapping;
1247 #define BNXT_MAX_MC_ADDRS 16
1250 #define BNXT_VNIC_RSS_FLAG 1
1251 #define BNXT_VNIC_RFS_FLAG 2
1252 #define BNXT_VNIC_MCAST_FLAG 4
1253 #define BNXT_VNIC_UCAST_FLAG 8
1254 #define BNXT_VNIC_RFS_NEW_RSS_FLAG 0x10
1257 struct bnxt_hw_resc {
1258 u16 min_rsscos_ctxs;
1259 u16 max_rsscos_ctxs;
1266 u16 max_tx_sch_inputs;
1270 u16 min_hw_ring_grps;
1271 u16 max_hw_ring_grps;
1272 u16 resv_hw_ring_grps;
1286 #if defined(CONFIG_BNXT_SRIOV)
1287 struct bnxt_vf_info {
1289 u8 mac_addr[ETH_ALEN]; /* PF assigned MAC Address */
1290 u8 vf_mac_addr[ETH_ALEN]; /* VF assigned MAC address, only
1294 u16 func_qcfg_flags;
1296 #define BNXT_VF_QOS 0x1
1297 #define BNXT_VF_SPOOFCHK 0x2
1298 #define BNXT_VF_LINK_FORCED 0x4
1299 #define BNXT_VF_LINK_UP 0x8
1300 #define BNXT_VF_TRUST 0x10
1303 void *hwrm_cmd_req_addr;
1304 dma_addr_t hwrm_cmd_req_dma_addr;
1308 struct bnxt_pf_info {
1309 #define BNXT_FIRST_PF_FID 1
1310 #define BNXT_FIRST_VF_FID 128
1313 u8 mac_addr[ETH_ALEN];
1318 u32 max_encap_records;
1319 u32 max_decap_records;
1320 u32 max_tx_em_flows;
1321 u32 max_tx_wm_flows;
1322 u32 max_rx_em_flows;
1323 u32 max_rx_wm_flows;
1324 unsigned long *vf_event_bmap;
1325 u16 hwrm_cmd_req_pages;
1326 u8 vf_resv_strategy;
1327 #define BNXT_VF_RESV_STRATEGY_MAXIMAL 0
1328 #define BNXT_VF_RESV_STRATEGY_MINIMAL 1
1329 #define BNXT_VF_RESV_STRATEGY_MINIMAL_STATIC 2
1330 void *hwrm_cmd_req_addr[4];
1331 dma_addr_t hwrm_cmd_req_dma_addr[4];
1332 struct bnxt_vf_info *vf;
1335 struct bnxt_filter_base {
1336 struct hlist_node hash;
1339 #define BNXT_FLTR_TYPE_NTUPLE 1
1340 #define BNXT_FLTR_TYPE_L2 2
1342 #define BNXT_ACT_DROP 1
1343 #define BNXT_ACT_RING_DST 2
1344 #define BNXT_ACT_FUNC_DST 4
1349 unsigned long state;
1350 #define BNXT_FLTR_VALID 0
1351 #define BNXT_FLTR_INSERTED 1
1353 struct rcu_head rcu;
1356 struct bnxt_ntuple_filter {
1357 struct bnxt_filter_base base;
1358 struct flow_keys fkeys;
1359 struct bnxt_l2_filter *l2_fltr;
1363 struct bnxt_l2_key {
1366 u8 dst_mac_addr[ETH_ALEN];
1373 struct bnxt_ipv4_tuple {
1374 struct flow_dissector_key_ipv4_addrs v4addrs;
1375 struct flow_dissector_key_ports ports;
1378 struct bnxt_ipv6_tuple {
1379 struct flow_dissector_key_ipv6_addrs v6addrs;
1380 struct flow_dissector_key_ports ports;
1383 #define BNXT_L2_KEY_SIZE (sizeof(struct bnxt_l2_key) / 4)
1385 struct bnxt_l2_filter {
1386 struct bnxt_filter_base base;
1387 struct bnxt_l2_key l2_key;
1391 struct bnxt_link_info {
1397 #define BNXT_LINK_NO_LINK PORT_PHY_QCFG_RESP_LINK_NO_LINK
1398 #define BNXT_LINK_SIGNAL PORT_PHY_QCFG_RESP_LINK_SIGNAL
1399 #define BNXT_LINK_LINK PORT_PHY_QCFG_RESP_LINK_LINK
1402 #define BNXT_PHY_STATE_ENABLED 0
1403 #define BNXT_PHY_STATE_DISABLED 1
1406 #define BNXT_LINK_STATE_UNKNOWN 0
1407 #define BNXT_LINK_STATE_DOWN 1
1408 #define BNXT_LINK_STATE_UP 2
1409 #define BNXT_LINK_IS_UP(bp) ((bp)->link_info.link_state == BNXT_LINK_STATE_UP)
1412 #define BNXT_LINK_DUPLEX_HALF PORT_PHY_QCFG_RESP_DUPLEX_STATE_HALF
1413 #define BNXT_LINK_DUPLEX_FULL PORT_PHY_QCFG_RESP_DUPLEX_STATE_FULL
1415 #define BNXT_LINK_PAUSE_TX PORT_PHY_QCFG_RESP_PAUSE_TX
1416 #define BNXT_LINK_PAUSE_RX PORT_PHY_QCFG_RESP_PAUSE_RX
1417 #define BNXT_LINK_PAUSE_BOTH (PORT_PHY_QCFG_RESP_PAUSE_RX | \
1418 PORT_PHY_QCFG_RESP_PAUSE_TX)
1420 u8 auto_pause_setting;
1421 u8 force_pause_setting;
1424 #define BNXT_AUTO_MODE(mode) ((mode) > BNXT_LINK_AUTO_NONE && \
1425 (mode) <= BNXT_LINK_AUTO_MSK)
1426 #define BNXT_LINK_AUTO_NONE PORT_PHY_QCFG_RESP_AUTO_MODE_NONE
1427 #define BNXT_LINK_AUTO_ALLSPDS PORT_PHY_QCFG_RESP_AUTO_MODE_ALL_SPEEDS
1428 #define BNXT_LINK_AUTO_ONESPD PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_SPEED
1429 #define BNXT_LINK_AUTO_ONEORBELOW PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_OR_BELOW
1430 #define BNXT_LINK_AUTO_MSK PORT_PHY_QCFG_RESP_AUTO_MODE_SPEED_MASK
1431 #define PHY_VER_LEN 3
1432 u8 phy_ver[PHY_VER_LEN];
1434 #define BNXT_LINK_SPEED_100MB PORT_PHY_QCFG_RESP_LINK_SPEED_100MB
1435 #define BNXT_LINK_SPEED_1GB PORT_PHY_QCFG_RESP_LINK_SPEED_1GB
1436 #define BNXT_LINK_SPEED_2GB PORT_PHY_QCFG_RESP_LINK_SPEED_2GB
1437 #define BNXT_LINK_SPEED_2_5GB PORT_PHY_QCFG_RESP_LINK_SPEED_2_5GB
1438 #define BNXT_LINK_SPEED_10GB PORT_PHY_QCFG_RESP_LINK_SPEED_10GB
1439 #define BNXT_LINK_SPEED_20GB PORT_PHY_QCFG_RESP_LINK_SPEED_20GB
1440 #define BNXT_LINK_SPEED_25GB PORT_PHY_QCFG_RESP_LINK_SPEED_25GB
1441 #define BNXT_LINK_SPEED_40GB PORT_PHY_QCFG_RESP_LINK_SPEED_40GB
1442 #define BNXT_LINK_SPEED_50GB PORT_PHY_QCFG_RESP_LINK_SPEED_50GB
1443 #define BNXT_LINK_SPEED_100GB PORT_PHY_QCFG_RESP_LINK_SPEED_100GB
1444 #define BNXT_LINK_SPEED_200GB PORT_PHY_QCFG_RESP_LINK_SPEED_200GB
1445 #define BNXT_LINK_SPEED_400GB PORT_PHY_QCFG_RESP_LINK_SPEED_400GB
1447 u16 support_pam4_speeds;
1448 u16 support_speeds2;
1450 u16 auto_link_speeds; /* fw adv setting */
1451 #define BNXT_LINK_SPEED_MSK_100MB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100MB
1452 #define BNXT_LINK_SPEED_MSK_1GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_1GB
1453 #define BNXT_LINK_SPEED_MSK_2GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2GB
1454 #define BNXT_LINK_SPEED_MSK_10GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10GB
1455 #define BNXT_LINK_SPEED_MSK_2_5GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2_5GB
1456 #define BNXT_LINK_SPEED_MSK_20GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_20GB
1457 #define BNXT_LINK_SPEED_MSK_25GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_25GB
1458 #define BNXT_LINK_SPEED_MSK_40GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_40GB
1459 #define BNXT_LINK_SPEED_MSK_50GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_50GB
1460 #define BNXT_LINK_SPEED_MSK_100GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100GB
1461 u16 auto_pam4_link_speeds;
1462 #define BNXT_LINK_PAM4_SPEED_MSK_50GB PORT_PHY_QCFG_RESP_SUPPORT_PAM4_SPEEDS_50G
1463 #define BNXT_LINK_PAM4_SPEED_MSK_100GB PORT_PHY_QCFG_RESP_SUPPORT_PAM4_SPEEDS_100G
1464 #define BNXT_LINK_PAM4_SPEED_MSK_200GB PORT_PHY_QCFG_RESP_SUPPORT_PAM4_SPEEDS_200G
1465 u16 auto_link_speeds2;
1466 #define BNXT_LINK_SPEEDS2_MSK_1GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_1GB
1467 #define BNXT_LINK_SPEEDS2_MSK_10GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_10GB
1468 #define BNXT_LINK_SPEEDS2_MSK_25GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_25GB
1469 #define BNXT_LINK_SPEEDS2_MSK_40GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_40GB
1470 #define BNXT_LINK_SPEEDS2_MSK_50GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_50GB
1471 #define BNXT_LINK_SPEEDS2_MSK_100GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_100GB
1472 #define BNXT_LINK_SPEEDS2_MSK_50GB_PAM4 \
1473 PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_50GB_PAM4_56
1474 #define BNXT_LINK_SPEEDS2_MSK_100GB_PAM4 \
1475 PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_100GB_PAM4_56
1476 #define BNXT_LINK_SPEEDS2_MSK_200GB_PAM4 \
1477 PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_200GB_PAM4_56
1478 #define BNXT_LINK_SPEEDS2_MSK_400GB_PAM4 \
1479 PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_400GB_PAM4_56
1480 #define BNXT_LINK_SPEEDS2_MSK_100GB_PAM4_112 \
1481 PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_100GB_PAM4_112
1482 #define BNXT_LINK_SPEEDS2_MSK_200GB_PAM4_112 \
1483 PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_200GB_PAM4_112
1484 #define BNXT_LINK_SPEEDS2_MSK_400GB_PAM4_112 \
1485 PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_400GB_PAM4_112
1487 u16 support_auto_speeds;
1488 u16 support_pam4_auto_speeds;
1489 u16 support_auto_speeds2;
1491 u16 lp_auto_link_speeds;
1492 u16 lp_auto_pam4_link_speeds;
1493 u16 force_link_speed;
1494 u16 force_pam4_link_speed;
1495 u16 force_link_speed2;
1496 #define BNXT_LINK_SPEED_50GB_PAM4 \
1497 PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_50GB_PAM4_56
1498 #define BNXT_LINK_SPEED_100GB_PAM4 \
1499 PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_100GB_PAM4_56
1500 #define BNXT_LINK_SPEED_200GB_PAM4 \
1501 PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_200GB_PAM4_56
1502 #define BNXT_LINK_SPEED_400GB_PAM4 \
1503 PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_400GB_PAM4_56
1504 #define BNXT_LINK_SPEED_100GB_PAM4_112 \
1505 PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_100GB_PAM4_112
1506 #define BNXT_LINK_SPEED_200GB_PAM4_112 \
1507 PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_200GB_PAM4_112
1508 #define BNXT_LINK_SPEED_400GB_PAM4_112 \
1509 PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_400GB_PAM4_112
1513 u8 active_fec_sig_mode;
1515 #define BNXT_FEC_NONE PORT_PHY_QCFG_RESP_FEC_CFG_FEC_NONE_SUPPORTED
1516 #define BNXT_FEC_AUTONEG_CAP PORT_PHY_QCFG_RESP_FEC_CFG_FEC_AUTONEG_SUPPORTED
1517 #define BNXT_FEC_AUTONEG PORT_PHY_QCFG_RESP_FEC_CFG_FEC_AUTONEG_ENABLED
1518 #define BNXT_FEC_ENC_BASE_R_CAP \
1519 PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE74_SUPPORTED
1520 #define BNXT_FEC_ENC_BASE_R PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE74_ENABLED
1521 #define BNXT_FEC_ENC_RS_CAP \
1522 PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE91_SUPPORTED
1523 #define BNXT_FEC_ENC_LLRS_CAP \
1524 (PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS272_1XN_SUPPORTED | \
1525 PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS272_IEEE_SUPPORTED)
1526 #define BNXT_FEC_ENC_RS \
1527 (PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE91_ENABLED | \
1528 PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS544_1XN_ENABLED | \
1529 PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS544_IEEE_ENABLED)
1530 #define BNXT_FEC_ENC_LLRS \
1531 (PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS272_1XN_ENABLED | \
1532 PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS272_IEEE_ENABLED)
1534 /* copy of requested setting from ethtool cmd */
1536 #define BNXT_AUTONEG_SPEED 1
1537 #define BNXT_AUTONEG_FLOW_CTRL 2
1539 #define BNXT_SIG_MODE_NRZ PORT_PHY_QCFG_RESP_SIGNAL_MODE_NRZ
1540 #define BNXT_SIG_MODE_PAM4 PORT_PHY_QCFG_RESP_SIGNAL_MODE_PAM4
1541 #define BNXT_SIG_MODE_PAM4_112 PORT_PHY_QCFG_RESP_SIGNAL_MODE_PAM4_112
1542 #define BNXT_SIG_MODE_MAX (PORT_PHY_QCFG_RESP_SIGNAL_MODE_LAST + 1)
1546 u16 advertising; /* user adv setting */
1547 u16 advertising_pam4;
1548 bool force_link_chng;
1551 unsigned long phy_retry_expires;
1553 /* a copy of phy_qcfg output used to report link
1556 struct hwrm_port_phy_qcfg_output phy_qcfg_resp;
1559 #define BNXT_FEC_RS544_ON \
1560 (PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_1XN_ENABLE | \
1561 PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_IEEE_ENABLE)
1563 #define BNXT_FEC_RS544_OFF \
1564 (PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_1XN_DISABLE | \
1565 PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_IEEE_DISABLE)
1567 #define BNXT_FEC_RS272_ON \
1568 (PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_1XN_ENABLE | \
1569 PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_IEEE_ENABLE)
1571 #define BNXT_FEC_RS272_OFF \
1572 (PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_1XN_DISABLE | \
1573 PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_IEEE_DISABLE)
1575 #define BNXT_PAM4_SUPPORTED(link_info) \
1576 ((link_info)->support_pam4_speeds)
1578 #define BNXT_FEC_RS_ON(link_info) \
1579 (PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE91_ENABLE | \
1580 PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE74_DISABLE | \
1581 (BNXT_PAM4_SUPPORTED(link_info) ? \
1582 (BNXT_FEC_RS544_ON | BNXT_FEC_RS272_OFF) : 0))
1584 #define BNXT_FEC_LLRS_ON \
1585 (PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE91_ENABLE | \
1586 PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE74_DISABLE | \
1587 BNXT_FEC_RS272_ON | BNXT_FEC_RS544_OFF)
1589 #define BNXT_FEC_RS_OFF(link_info) \
1590 (PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE91_DISABLE | \
1591 (BNXT_PAM4_SUPPORTED(link_info) ? \
1592 (BNXT_FEC_RS544_OFF | BNXT_FEC_RS272_OFF) : 0))
1594 #define BNXT_FEC_BASE_R_ON(link_info) \
1595 (PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE74_ENABLE | \
1596 BNXT_FEC_RS_OFF(link_info))
1598 #define BNXT_FEC_ALL_OFF(link_info) \
1599 (PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE74_DISABLE | \
1600 BNXT_FEC_RS_OFF(link_info))
1602 struct bnxt_queue_info {
1607 #define BNXT_MAX_LED 4
1609 struct bnxt_led_info {
1614 __le16 led_state_caps;
1615 #define BNXT_LED_ALT_BLINK_CAP(x) ((x) & \
1616 cpu_to_le16(PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_BLINK_ALT_SUPPORTED))
1618 __le16 led_color_caps;
1621 #define BNXT_MAX_TEST 8
1623 struct bnxt_test_info {
1626 char string[BNXT_MAX_TEST][ETH_GSTRING_LEN];
1629 #define CHIMP_REG_VIEW_ADDR \
1630 ((bp->flags & BNXT_FLAG_CHIP_P5_PLUS) ? 0x80000000 : 0xb1000000)
1632 #define BNXT_GRCPF_REG_CHIMP_COMM 0x0
1633 #define BNXT_GRCPF_REG_CHIMP_COMM_TRIGGER 0x100
1634 #define BNXT_GRCPF_REG_WINDOW_BASE_OUT 0x400
1635 #define BNXT_CAG_REG_LEGACY_INT_STATUS 0x4014
1636 #define BNXT_CAG_REG_BASE 0x300000
1638 #define BNXT_GRC_REG_STATUS_P5 0x520
1640 #define BNXT_GRCPF_REG_KONG_COMM 0xA00
1641 #define BNXT_GRCPF_REG_KONG_COMM_TRIGGER 0xB00
1643 #define BNXT_GRC_REG_CHIP_NUM 0x48
1644 #define BNXT_GRC_REG_BASE 0x260000
1646 #define BNXT_TS_REG_TIMESYNC_TS0_LOWER 0x640180c
1647 #define BNXT_TS_REG_TIMESYNC_TS0_UPPER 0x6401810
1649 #define BNXT_GRC_BASE_MASK 0xfffff000
1650 #define BNXT_GRC_OFFSET_MASK 0x00000ffc
1652 struct bnxt_tc_flow_stats {
1657 #ifdef CONFIG_BNXT_FLOWER_OFFLOAD
1658 struct bnxt_flower_indr_block_cb_priv {
1659 struct net_device *tunnel_netdev;
1661 struct list_head list;
1665 struct bnxt_tc_info {
1668 /* hash table to store TC offloaded flows */
1669 struct rhashtable flow_table;
1670 struct rhashtable_params flow_ht_params;
1672 /* hash table to store L2 keys of TC flows */
1673 struct rhashtable l2_table;
1674 struct rhashtable_params l2_ht_params;
1675 /* hash table to store L2 keys for TC tunnel decap */
1676 struct rhashtable decap_l2_table;
1677 struct rhashtable_params decap_l2_ht_params;
1678 /* hash table to store tunnel decap entries */
1679 struct rhashtable decap_table;
1680 struct rhashtable_params decap_ht_params;
1681 /* hash table to store tunnel encap entries */
1682 struct rhashtable encap_table;
1683 struct rhashtable_params encap_ht_params;
1685 /* lock to atomically add/del an l2 node when a flow is
1690 /* Fields used for batching stats query */
1691 struct rhashtable_iter iter;
1692 #define BNXT_FLOW_STATS_BATCH_MAX 10
1693 struct bnxt_tc_stats_batch {
1695 struct bnxt_tc_flow_stats hw_stats;
1696 } stats_batch[BNXT_FLOW_STATS_BATCH_MAX];
1698 /* Stat counter mask (width) */
1703 struct bnxt_vf_rep_stats {
1709 struct bnxt_vf_rep {
1711 struct net_device *dev;
1712 struct metadata_dst *dst;
1717 struct bnxt_vf_rep_stats rx_stats;
1718 struct bnxt_vf_rep_stats tx_stats;
1721 #define PTU_PTE_VALID 0x1UL
1722 #define PTU_PTE_LAST 0x2UL
1723 #define PTU_PTE_NEXT_TO_LAST 0x4UL
1725 #define MAX_CTX_PAGES (BNXT_PAGE_SIZE / 8)
1726 #define MAX_CTX_TOTAL_PAGES (MAX_CTX_PAGES * MAX_CTX_PAGES)
1728 struct bnxt_ctx_pg_info {
1731 void *ctx_pg_arr[MAX_CTX_PAGES];
1732 dma_addr_t ctx_dma_arr[MAX_CTX_PAGES];
1733 struct bnxt_ring_mem_info ring_mem;
1734 struct bnxt_ctx_pg_info **ctx_pg_tbl;
1737 #define BNXT_MAX_TQM_SP_RINGS 1
1738 #define BNXT_MAX_TQM_FP_RINGS 8
1739 #define BNXT_MAX_TQM_RINGS \
1740 (BNXT_MAX_TQM_SP_RINGS + BNXT_MAX_TQM_FP_RINGS)
1742 #define BNXT_BACKING_STORE_CFG_LEGACY_LEN 256
1744 #define BNXT_SET_CTX_PAGE_ATTR(attr) \
1746 if (BNXT_PAGE_SIZE == 0x2000) \
1747 attr = FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_8K; \
1748 else if (BNXT_PAGE_SIZE == 0x10000) \
1749 attr = FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_64K; \
1751 attr = FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_4K; \
1754 struct bnxt_ctx_mem_type {
1758 #define BNXT_CTX_MEM_TYPE_VALID FUNC_BACKING_STORE_QCAPS_V2_RESP_FLAGS_TYPE_VALID
1763 #define BNXT_CTX_INIT_INVALID_OFFSET 0xffff
1768 #define BNXT_MAX_SPLIT_ENTRY 4
1773 u32 qp_fast_qpmd_entries;
1779 u32 mrav_av_entries;
1780 u32 mrav_num_entries_units;
1782 u32 split[BNXT_MAX_SPLIT_ENTRY];
1784 struct bnxt_ctx_pg_info *pg_info;
1787 #define BNXT_CTX_MRAV_AV_SPLIT_ENTRY 0
1789 #define BNXT_CTX_QP FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_QP
1790 #define BNXT_CTX_SRQ FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_SRQ
1791 #define BNXT_CTX_CQ FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_CQ
1792 #define BNXT_CTX_VNIC FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_VNIC
1793 #define BNXT_CTX_STAT FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_STAT
1794 #define BNXT_CTX_STQM FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_SP_TQM_RING
1795 #define BNXT_CTX_FTQM FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_FP_TQM_RING
1796 #define BNXT_CTX_MRAV FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_MRAV
1797 #define BNXT_CTX_TIM FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_TIM
1798 #define BNXT_CTX_TKC FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_TKC
1799 #define BNXT_CTX_RKC FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_RKC
1800 #define BNXT_CTX_MTQM FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_MP_TQM_RING
1801 #define BNXT_CTX_SQDBS FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_SQ_DB_SHADOW
1802 #define BNXT_CTX_RQDBS FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_RQ_DB_SHADOW
1803 #define BNXT_CTX_SRQDBS FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_SRQ_DB_SHADOW
1804 #define BNXT_CTX_CQDBS FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_CQ_DB_SHADOW
1805 #define BNXT_CTX_QTKC FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_QUIC_TKC
1806 #define BNXT_CTX_QRKC FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_QUIC_RKC
1807 #define BNXT_CTX_TBLSC FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_TBL_SCOPE
1808 #define BNXT_CTX_XPAR FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_XID_PARTITION
1810 #define BNXT_CTX_MAX (BNXT_CTX_TIM + 1)
1811 #define BNXT_CTX_L2_MAX (BNXT_CTX_FTQM + 1)
1812 #define BNXT_CTX_V2_MAX (BNXT_CTX_XPAR + 1)
1813 #define BNXT_CTX_INV ((u16)-1)
1815 struct bnxt_ctx_mem_info {
1816 u8 tqm_fp_rings_count;
1819 #define BNXT_CTX_FLAG_INITED 0x01
1820 struct bnxt_ctx_mem_type ctx_arr[BNXT_CTX_V2_MAX];
1823 enum bnxt_health_severity {
1824 SEVERITY_NORMAL = 0,
1826 SEVERITY_RECOVERABLE,
1830 enum bnxt_health_remedy {
1831 REMEDY_DEVLINK_RECOVER,
1832 REMEDY_POWER_CYCLE_DEVICE,
1833 REMEDY_POWER_CYCLE_HOST,
1838 struct bnxt_fw_health {
1841 u32 master_func_wait_dsecs;
1842 u32 normal_func_wait_dsecs;
1843 u32 post_reset_wait_dsecs;
1844 u32 post_reset_max_wait_dsecs;
1847 #define BNXT_FW_HEALTH_REG 0
1848 #define BNXT_FW_HEARTBEAT_REG 1
1849 #define BNXT_FW_RESET_CNT_REG 2
1850 #define BNXT_FW_RESET_INPROG_REG 3
1851 u32 fw_reset_inprog_reg_mask;
1852 u32 last_fw_heartbeat;
1853 u32 last_fw_reset_cnt;
1856 u8 status_reliable:1;
1857 u8 resets_reliable:1;
1860 u8 fw_reset_seq_cnt;
1861 u32 fw_reset_seq_regs[16];
1862 u32 fw_reset_seq_vals[16];
1863 u32 fw_reset_seq_delay_msec[16];
1866 struct devlink_health_reporter *fw_reporter;
1867 /* Protects severity and remedy */
1869 enum bnxt_health_severity severity;
1870 enum bnxt_health_remedy remedy;
1878 #define BNXT_FW_HEALTH_REG_TYPE_MASK 3
1879 #define BNXT_FW_HEALTH_REG_TYPE_CFG 0
1880 #define BNXT_FW_HEALTH_REG_TYPE_GRC 1
1881 #define BNXT_FW_HEALTH_REG_TYPE_BAR0 2
1882 #define BNXT_FW_HEALTH_REG_TYPE_BAR1 3
1884 #define BNXT_FW_HEALTH_REG_TYPE(reg) ((reg) & BNXT_FW_HEALTH_REG_TYPE_MASK)
1885 #define BNXT_FW_HEALTH_REG_OFF(reg) ((reg) & ~BNXT_FW_HEALTH_REG_TYPE_MASK)
1887 #define BNXT_FW_HEALTH_WIN_BASE 0x3000
1888 #define BNXT_FW_HEALTH_WIN_MAP_OFF 8
1890 #define BNXT_FW_HEALTH_WIN_OFF(reg) (BNXT_FW_HEALTH_WIN_BASE + \
1891 ((reg) & BNXT_GRC_OFFSET_MASK))
1893 #define BNXT_FW_STATUS_HEALTH_MSK 0xffff
1894 #define BNXT_FW_STATUS_HEALTHY 0x8000
1895 #define BNXT_FW_STATUS_SHUTDOWN 0x100000
1896 #define BNXT_FW_STATUS_RECOVERING 0x400000
1898 #define BNXT_FW_IS_HEALTHY(sts) (((sts) & BNXT_FW_STATUS_HEALTH_MSK) ==\
1899 BNXT_FW_STATUS_HEALTHY)
1901 #define BNXT_FW_IS_BOOTING(sts) (((sts) & BNXT_FW_STATUS_HEALTH_MSK) < \
1902 BNXT_FW_STATUS_HEALTHY)
1904 #define BNXT_FW_IS_ERR(sts) (((sts) & BNXT_FW_STATUS_HEALTH_MSK) > \
1905 BNXT_FW_STATUS_HEALTHY)
1907 #define BNXT_FW_IS_RECOVERING(sts) (BNXT_FW_IS_ERR(sts) && \
1908 ((sts) & BNXT_FW_STATUS_RECOVERING))
1910 #define BNXT_FW_RETRY 5
1911 #define BNXT_FW_IF_RETRY 10
1912 #define BNXT_FW_SLOT_RESET_RETRY 4
1914 struct bnxt_aux_priv {
1915 struct auxiliary_device aux_dev;
1916 struct bnxt_en_dev *edev;
1969 NETXTREME_E_P5_VF_HV,
1979 #define CHIP_NUM_57301 0x16c8
1980 #define CHIP_NUM_57302 0x16c9
1981 #define CHIP_NUM_57304 0x16ca
1982 #define CHIP_NUM_58700 0x16cd
1983 #define CHIP_NUM_57402 0x16d0
1984 #define CHIP_NUM_57404 0x16d1
1985 #define CHIP_NUM_57406 0x16d2
1986 #define CHIP_NUM_57407 0x16d5
1988 #define CHIP_NUM_57311 0x16ce
1989 #define CHIP_NUM_57312 0x16cf
1990 #define CHIP_NUM_57314 0x16df
1991 #define CHIP_NUM_57317 0x16e0
1992 #define CHIP_NUM_57412 0x16d6
1993 #define CHIP_NUM_57414 0x16d7
1994 #define CHIP_NUM_57416 0x16d8
1995 #define CHIP_NUM_57417 0x16d9
1996 #define CHIP_NUM_57412L 0x16da
1997 #define CHIP_NUM_57414L 0x16db
1999 #define CHIP_NUM_5745X 0xd730
2000 #define CHIP_NUM_57452 0xc452
2001 #define CHIP_NUM_57454 0xc454
2003 #define CHIP_NUM_57508 0x1750
2004 #define CHIP_NUM_57504 0x1751
2005 #define CHIP_NUM_57502 0x1752
2007 #define CHIP_NUM_57608 0x1760
2009 #define CHIP_NUM_58802 0xd802
2010 #define CHIP_NUM_58804 0xd804
2011 #define CHIP_NUM_58808 0xd808
2015 #define BNXT_CHIP_NUM_5730X(chip_num) \
2016 ((chip_num) >= CHIP_NUM_57301 && \
2017 (chip_num) <= CHIP_NUM_57304)
2019 #define BNXT_CHIP_NUM_5740X(chip_num) \
2020 (((chip_num) >= CHIP_NUM_57402 && \
2021 (chip_num) <= CHIP_NUM_57406) || \
2022 (chip_num) == CHIP_NUM_57407)
2024 #define BNXT_CHIP_NUM_5731X(chip_num) \
2025 ((chip_num) == CHIP_NUM_57311 || \
2026 (chip_num) == CHIP_NUM_57312 || \
2027 (chip_num) == CHIP_NUM_57314 || \
2028 (chip_num) == CHIP_NUM_57317)
2030 #define BNXT_CHIP_NUM_5741X(chip_num) \
2031 ((chip_num) >= CHIP_NUM_57412 && \
2032 (chip_num) <= CHIP_NUM_57414L)
2034 #define BNXT_CHIP_NUM_58700(chip_num) \
2035 ((chip_num) == CHIP_NUM_58700)
2037 #define BNXT_CHIP_NUM_5745X(chip_num) \
2038 ((chip_num) == CHIP_NUM_5745X || \
2039 (chip_num) == CHIP_NUM_57452 || \
2040 (chip_num) == CHIP_NUM_57454)
2043 #define BNXT_CHIP_NUM_57X0X(chip_num) \
2044 (BNXT_CHIP_NUM_5730X(chip_num) || BNXT_CHIP_NUM_5740X(chip_num))
2046 #define BNXT_CHIP_NUM_57X1X(chip_num) \
2047 (BNXT_CHIP_NUM_5731X(chip_num) || BNXT_CHIP_NUM_5741X(chip_num))
2049 #define BNXT_CHIP_NUM_588XX(chip_num) \
2050 ((chip_num) == CHIP_NUM_58802 || \
2051 (chip_num) == CHIP_NUM_58804 || \
2052 (chip_num) == CHIP_NUM_58808)
2054 #define BNXT_VPD_FLD_LEN 32
2055 char board_partno[BNXT_VPD_FLD_LEN];
2056 char board_serialno[BNXT_VPD_FLD_LEN];
2058 struct net_device *dev;
2059 struct pci_dev *pdev;
2064 #define BNXT_FLAG_CHIP_P5_PLUS 0x1
2065 #define BNXT_FLAG_VF 0x2
2066 #define BNXT_FLAG_LRO 0x4
2068 #define BNXT_FLAG_GRO 0x8
2070 /* Cannot support hardware GRO if CONFIG_INET is not set */
2071 #define BNXT_FLAG_GRO 0x0
2073 #define BNXT_FLAG_TPA (BNXT_FLAG_LRO | BNXT_FLAG_GRO)
2074 #define BNXT_FLAG_JUMBO 0x10
2075 #define BNXT_FLAG_STRIP_VLAN 0x20
2076 #define BNXT_FLAG_AGG_RINGS (BNXT_FLAG_JUMBO | BNXT_FLAG_GRO | \
2078 #define BNXT_FLAG_USING_MSIX 0x40
2079 #define BNXT_FLAG_MSIX_CAP 0x80
2080 #define BNXT_FLAG_RFS 0x100
2081 #define BNXT_FLAG_SHARED_RINGS 0x200
2082 #define BNXT_FLAG_PORT_STATS 0x400
2083 #define BNXT_FLAG_WOL_CAP 0x4000
2084 #define BNXT_FLAG_ROCEV1_CAP 0x8000
2085 #define BNXT_FLAG_ROCEV2_CAP 0x10000
2086 #define BNXT_FLAG_ROCE_CAP (BNXT_FLAG_ROCEV1_CAP | \
2087 BNXT_FLAG_ROCEV2_CAP)
2088 #define BNXT_FLAG_NO_AGG_RINGS 0x20000
2089 #define BNXT_FLAG_RX_PAGE_MODE 0x40000
2090 #define BNXT_FLAG_CHIP_P7 0x80000
2091 #define BNXT_FLAG_MULTI_HOST 0x100000
2092 #define BNXT_FLAG_DSN_VALID 0x200000
2093 #define BNXT_FLAG_DOUBLE_DB 0x400000
2094 #define BNXT_FLAG_UDP_GSO_CAP 0x800000
2095 #define BNXT_FLAG_CHIP_NITRO_A0 0x1000000
2096 #define BNXT_FLAG_DIM 0x2000000
2097 #define BNXT_FLAG_ROCE_MIRROR_CAP 0x4000000
2098 #define BNXT_FLAG_TX_COAL_CMPL 0x8000000
2099 #define BNXT_FLAG_PORT_STATS_EXT 0x10000000
2101 #define BNXT_FLAG_ALL_CONFIG_FEATS (BNXT_FLAG_TPA | \
2103 BNXT_FLAG_STRIP_VLAN)
2105 #define BNXT_PF(bp) (!((bp)->flags & BNXT_FLAG_VF))
2106 #define BNXT_VF(bp) ((bp)->flags & BNXT_FLAG_VF)
2107 #define BNXT_NPAR(bp) ((bp)->port_partition_type)
2108 #define BNXT_MH(bp) ((bp)->flags & BNXT_FLAG_MULTI_HOST)
2109 #define BNXT_SINGLE_PF(bp) (BNXT_PF(bp) && !BNXT_NPAR(bp) && !BNXT_MH(bp))
2110 #define BNXT_SH_PORT_CFG_OK(bp) (BNXT_PF(bp) && \
2111 ((bp)->phy_flags & BNXT_PHY_FL_SHARED_PORT_CFG))
2112 #define BNXT_PHY_CFG_ABLE(bp) ((BNXT_SINGLE_PF(bp) || \
2113 BNXT_SH_PORT_CFG_OK(bp)) && \
2114 (bp)->link_info.phy_state == BNXT_PHY_STATE_ENABLED)
2115 #define BNXT_CHIP_TYPE_NITRO_A0(bp) ((bp)->flags & BNXT_FLAG_CHIP_NITRO_A0)
2116 #define BNXT_RX_PAGE_MODE(bp) ((bp)->flags & BNXT_FLAG_RX_PAGE_MODE)
2117 #define BNXT_SUPPORTS_TPA(bp) (!BNXT_CHIP_TYPE_NITRO_A0(bp) && \
2118 (!((bp)->flags & BNXT_FLAG_CHIP_P5_PLUS) ||\
2119 (bp)->max_tpa_v2) && !is_kdump_kernel())
2120 #define BNXT_RX_JUMBO_MODE(bp) ((bp)->flags & BNXT_FLAG_JUMBO)
2122 #define BNXT_CHIP_P7(bp) \
2123 ((bp)->chip_num == CHIP_NUM_57608)
2125 #define BNXT_CHIP_P5(bp) \
2126 ((bp)->chip_num == CHIP_NUM_57508 || \
2127 (bp)->chip_num == CHIP_NUM_57504 || \
2128 (bp)->chip_num == CHIP_NUM_57502)
2130 /* Chip class phase 5 */
2131 #define BNXT_CHIP_P5_PLUS(bp) \
2132 (BNXT_CHIP_P5(bp) || BNXT_CHIP_P7(bp))
2134 /* Chip class phase 4.x */
2135 #define BNXT_CHIP_P4(bp) \
2136 (BNXT_CHIP_NUM_57X1X((bp)->chip_num) || \
2137 BNXT_CHIP_NUM_5745X((bp)->chip_num) || \
2138 BNXT_CHIP_NUM_588XX((bp)->chip_num) || \
2139 (BNXT_CHIP_NUM_58700((bp)->chip_num) && \
2140 !BNXT_CHIP_TYPE_NITRO_A0(bp)))
2142 #define BNXT_CHIP_P4_PLUS(bp) \
2143 (BNXT_CHIP_P4(bp) || BNXT_CHIP_P5_PLUS(bp))
2145 struct bnxt_aux_priv *aux_priv;
2146 struct bnxt_en_dev *edev;
2148 struct bnxt_napi **bnapi;
2150 struct bnxt_rx_ring_info *rx_ring;
2151 struct bnxt_tx_ring_info *tx_ring;
2154 struct sk_buff * (*gro_func)(struct bnxt_tpa_info *, int, int,
2157 struct sk_buff * (*rx_skb_func)(struct bnxt *,
2158 struct bnxt_rx_ring_info *,
2159 u16, void *, u8 *, dma_addr_t,
2165 u32 rx_buf_use_size; /* useable size */
2168 enum dma_data_direction rx_dir;
2170 u32 rx_agg_ring_size;
2173 u32 rx_agg_ring_mask;
2175 int rx_agg_nr_pages;
2183 int tx_nr_rings_per_tc;
2184 int tx_nr_rings_xdp;
2196 /* grp_info indexed by completion ring index */
2197 struct bnxt_ring_grp_info *grp_info;
2198 struct bnxt_vnic_info *vnic_info;
2201 u16 rss_indir_tbl_entries;
2205 #define BNXT_RSS_CAP_RSS_HASH_TYPE_DELTA BIT(0)
2206 #define BNXT_RSS_CAP_UDP_RSS_CAP BIT(1)
2207 #define BNXT_RSS_CAP_NEW_RSS_CAP BIT(2)
2208 #define BNXT_RSS_CAP_RSS_TCAM BIT(3)
2212 u8 max_lltc; /* lossless TCs */
2213 struct bnxt_queue_info q_info[BNXT_MAX_QUEUE];
2214 u8 tc_to_qidx[BNXT_MAX_QUEUE];
2215 u8 q_ids[BNXT_MAX_QUEUE];
2218 unsigned int current_interval;
2219 #define BNXT_TIMER_INTERVAL HZ
2221 struct timer_list timer;
2223 unsigned long state;
2224 #define BNXT_STATE_OPEN 0
2225 #define BNXT_STATE_IN_SP_TASK 1
2226 #define BNXT_STATE_READ_STATS 2
2227 #define BNXT_STATE_FW_RESET_DET 3
2228 #define BNXT_STATE_IN_FW_RESET 4
2229 #define BNXT_STATE_ABORT_ERR 5
2230 #define BNXT_STATE_FW_FATAL_COND 6
2231 #define BNXT_STATE_DRV_REGISTERED 7
2232 #define BNXT_STATE_PCI_CHANNEL_IO_FROZEN 8
2233 #define BNXT_STATE_NAPI_DISABLED 9
2234 #define BNXT_STATE_L2_FILTER_RETRY 10
2235 #define BNXT_STATE_FW_ACTIVATE 11
2236 #define BNXT_STATE_RECOVER 12
2237 #define BNXT_STATE_FW_NON_FATAL_COND 13
2238 #define BNXT_STATE_FW_ACTIVATE_RESET 14
2239 #define BNXT_STATE_HALF_OPEN 15 /* For offline ethtool tests */
2241 #define BNXT_NO_FW_ACCESS(bp) \
2242 (test_bit(BNXT_STATE_FW_FATAL_COND, &(bp)->state) || \
2243 pci_channel_offline((bp)->pdev))
2245 struct bnxt_irq *irq_tbl;
2247 u8 mac_addr[ETH_ALEN];
2249 #ifdef CONFIG_BNXT_DCB
2250 struct ieee_pfc *ieee_pfc;
2251 struct ieee_ets *ieee_ets;
2255 #endif /* CONFIG_BNXT_DCB */
2260 #define BNXT_FW_CAP_SHORT_CMD BIT_ULL(0)
2261 #define BNXT_FW_CAP_LLDP_AGENT BIT_ULL(1)
2262 #define BNXT_FW_CAP_DCBX_AGENT BIT_ULL(2)
2263 #define BNXT_FW_CAP_NEW_RM BIT_ULL(3)
2264 #define BNXT_FW_CAP_IF_CHANGE BIT_ULL(4)
2265 #define BNXT_FW_CAP_KONG_MB_CHNL BIT_ULL(7)
2266 #define BNXT_FW_CAP_OVS_64BIT_HANDLE BIT_ULL(10)
2267 #define BNXT_FW_CAP_TRUSTED_VF BIT_ULL(11)
2268 #define BNXT_FW_CAP_ERROR_RECOVERY BIT_ULL(13)
2269 #define BNXT_FW_CAP_PKG_VER BIT_ULL(14)
2270 #define BNXT_FW_CAP_CFA_ADV_FLOW BIT_ULL(15)
2271 #define BNXT_FW_CAP_CFA_RFS_RING_TBL_IDX_V2 BIT_ULL(16)
2272 #define BNXT_FW_CAP_PCIE_STATS_SUPPORTED BIT_ULL(17)
2273 #define BNXT_FW_CAP_EXT_STATS_SUPPORTED BIT_ULL(18)
2274 #define BNXT_FW_CAP_ERR_RECOVER_RELOAD BIT_ULL(20)
2275 #define BNXT_FW_CAP_HOT_RESET BIT_ULL(21)
2276 #define BNXT_FW_CAP_PTP_RTC BIT_ULL(22)
2277 #define BNXT_FW_CAP_RX_ALL_PKT_TS BIT_ULL(23)
2278 #define BNXT_FW_CAP_VLAN_RX_STRIP BIT_ULL(24)
2279 #define BNXT_FW_CAP_VLAN_TX_INSERT BIT_ULL(25)
2280 #define BNXT_FW_CAP_EXT_HW_STATS_SUPPORTED BIT_ULL(26)
2281 #define BNXT_FW_CAP_LIVEPATCH BIT_ULL(27)
2282 #define BNXT_FW_CAP_PTP_PPS BIT_ULL(28)
2283 #define BNXT_FW_CAP_HOT_RESET_IF BIT_ULL(29)
2284 #define BNXT_FW_CAP_RING_MONITOR BIT_ULL(30)
2285 #define BNXT_FW_CAP_DBG_QCAPS BIT_ULL(31)
2286 #define BNXT_FW_CAP_PTP BIT_ULL(32)
2287 #define BNXT_FW_CAP_THRESHOLD_TEMP_SUPPORTED BIT_ULL(33)
2288 #define BNXT_FW_CAP_DFLT_VLAN_TPID_PCP BIT_ULL(34)
2289 #define BNXT_FW_CAP_PRE_RESV_VNICS BIT_ULL(35)
2290 #define BNXT_FW_CAP_BACKING_STORE_V2 BIT_ULL(36)
2291 #define BNXT_FW_CAP_VNIC_TUNNEL_TPA BIT_ULL(37)
2295 #define BNXT_NEW_RM(bp) ((bp)->fw_cap & BNXT_FW_CAP_NEW_RM)
2296 #define BNXT_PTP_USE_RTC(bp) (!BNXT_MH(bp) && \
2297 ((bp)->fw_cap & BNXT_FW_CAP_PTP_RTC))
2300 u16 hwrm_cmd_kong_seq;
2301 struct dma_pool *hwrm_dma_pool;
2302 struct hlist_head hwrm_pending_list;
2304 struct rtnl_link_stats64 net_stats_prev;
2305 struct bnxt_stats_mem port_stats;
2306 struct bnxt_stats_mem rx_port_stats_ext;
2307 struct bnxt_stats_mem tx_port_stats_ext;
2308 u16 fw_rx_stats_ext_size;
2309 u16 fw_tx_stats_ext_size;
2310 u16 hw_ring_stats_size;
2314 struct bnxt_total_ring_err_stats ring_err_stats_prev;
2316 u16 hwrm_max_req_len;
2317 u16 hwrm_max_ext_req_len;
2318 unsigned int hwrm_cmd_timeout;
2319 unsigned int hwrm_cmd_max_timeout;
2320 struct mutex hwrm_cmd_lock; /* serialize hwrm messages */
2321 struct hwrm_ver_get_output ver_resp;
2322 #define FW_VER_STR_LEN 32
2323 #define BC_HWRM_STR_LEN 21
2324 #define PHY_VER_STR_LEN (FW_VER_STR_LEN - BC_HWRM_STR_LEN)
2325 char fw_ver_str[FW_VER_STR_LEN];
2326 char hwrm_ver_supp[FW_VER_STR_LEN];
2327 char nvm_cfg_ver[FW_VER_STR_LEN];
2329 #define BNXT_FW_VER_CODE(maj, min, bld, rsv) \
2330 ((u64)(maj) << 48 | (u64)(min) << 32 | (u64)(bld) << 16 | (rsv))
2331 #define BNXT_FW_MAJ(bp) ((bp)->fw_ver_code >> 48)
2332 #define BNXT_FW_BLD(bp) (((bp)->fw_ver_code >> 16) & 0xffff)
2334 u16 vxlan_fw_dst_port_id;
2335 u16 nge_fw_dst_port_id;
2336 u16 vxlan_gpe_fw_dst_port_id;
2339 __be16 vxlan_gpe_port;
2340 u8 port_partition_type;
2344 struct bnxt_coal_cap coal_cap;
2345 struct bnxt_coal rx_coal;
2346 struct bnxt_coal tx_coal;
2348 u32 stats_coal_ticks;
2349 #define BNXT_DEF_STATS_COAL_TICKS 1000000
2350 #define BNXT_MIN_STATS_COAL_TICKS 250000
2351 #define BNXT_MAX_STATS_COAL_TICKS 1000000
2353 struct work_struct sp_task;
2354 unsigned long sp_event;
2355 #define BNXT_RX_MASK_SP_EVENT 0
2356 #define BNXT_RX_NTP_FLTR_SP_EVENT 1
2357 #define BNXT_LINK_CHNG_SP_EVENT 2
2358 #define BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT 3
2359 #define BNXT_RESET_TASK_SP_EVENT 6
2360 #define BNXT_RST_RING_SP_EVENT 7
2361 #define BNXT_HWRM_PF_UNLOAD_SP_EVENT 8
2362 #define BNXT_PERIODIC_STATS_SP_EVENT 9
2363 #define BNXT_HWRM_PORT_MODULE_SP_EVENT 10
2364 #define BNXT_RESET_TASK_SILENT_SP_EVENT 11
2365 #define BNXT_LINK_SPEED_CHNG_SP_EVENT 14
2366 #define BNXT_FLOW_STATS_SP_EVENT 15
2367 #define BNXT_UPDATE_PHY_SP_EVENT 16
2368 #define BNXT_RING_COAL_NOW_SP_EVENT 17
2369 #define BNXT_FW_RESET_NOTIFY_SP_EVENT 18
2370 #define BNXT_FW_EXCEPTION_SP_EVENT 19
2371 #define BNXT_LINK_CFG_CHANGE_SP_EVENT 21
2372 #define BNXT_THERMAL_THRESHOLD_SP_EVENT 22
2373 #define BNXT_FW_ECHO_REQUEST_SP_EVENT 23
2375 struct delayed_work fw_reset_task;
2377 #define BNXT_FW_RESET_STATE_POLL_VF 1
2378 #define BNXT_FW_RESET_STATE_RESET_FW 2
2379 #define BNXT_FW_RESET_STATE_ENABLE_DEV 3
2380 #define BNXT_FW_RESET_STATE_POLL_FW 4
2381 #define BNXT_FW_RESET_STATE_OPENING 5
2382 #define BNXT_FW_RESET_STATE_POLL_FW_DOWN 6
2384 u16 fw_reset_min_dsecs;
2385 #define BNXT_DFLT_FW_RST_MIN_DSECS 20
2386 u16 fw_reset_max_dsecs;
2387 #define BNXT_DFLT_FW_RST_MAX_DSECS 60
2388 unsigned long fw_reset_timestamp;
2390 struct bnxt_fw_health *fw_health;
2392 struct bnxt_hw_resc hw_resc;
2393 struct bnxt_pf_info pf;
2394 struct bnxt_ctx_mem_info *ctx;
2395 #ifdef CONFIG_BNXT_SRIOV
2397 struct bnxt_vf_info vf;
2398 wait_queue_head_t sriov_cfg_wait;
2400 #define BNXT_SRIOV_CFG_WAIT_TMO msecs_to_jiffies(10000)
2403 #if BITS_PER_LONG == 32
2404 /* ensure atomic 64-bit doorbell writes on 32-bit systems. */
2407 int db_offset; /* db_offset within db_size */
2410 #define BNXT_NTP_FLTR_MAX_FLTR 4096
2411 #define BNXT_MAX_FLTR (BNXT_NTP_FLTR_MAX_FLTR + BNXT_L2_FLTR_MAX_FLTR)
2412 #define BNXT_NTP_FLTR_HASH_SIZE 512
2413 #define BNXT_NTP_FLTR_HASH_MASK (BNXT_NTP_FLTR_HASH_SIZE - 1)
2414 struct hlist_head ntp_fltr_hash_tbl[BNXT_NTP_FLTR_HASH_SIZE];
2415 spinlock_t ntp_fltr_lock; /* for hash table add, del */
2417 unsigned long *ntp_fltr_bmap;
2420 #define BNXT_L2_FLTR_MAX_FLTR 1024
2421 #define BNXT_L2_FLTR_HASH_SIZE 32
2422 #define BNXT_L2_FLTR_HASH_MASK (BNXT_L2_FLTR_HASH_SIZE - 1)
2423 struct hlist_head l2_fltr_hash_tbl[BNXT_L2_FLTR_HASH_SIZE];
2426 u64 toeplitz_prefix;
2428 /* To protect link related settings during link changes and
2429 * ethtool settings changes.
2431 struct mutex link_lock;
2432 struct bnxt_link_info link_info;
2433 struct ethtool_eee eee;
2437 /* copied from flags and flags2 in hwrm_port_phy_qcaps_output */
2439 #define BNXT_PHY_FL_EEE_CAP PORT_PHY_QCAPS_RESP_FLAGS_EEE_SUPPORTED
2440 #define BNXT_PHY_FL_EXT_LPBK PORT_PHY_QCAPS_RESP_FLAGS_EXTERNAL_LPBK_SUPPORTED
2441 #define BNXT_PHY_FL_AN_PHY_LPBK PORT_PHY_QCAPS_RESP_FLAGS_AUTONEG_LPBK_SUPPORTED
2442 #define BNXT_PHY_FL_SHARED_PORT_CFG PORT_PHY_QCAPS_RESP_FLAGS_SHARED_PHY_CFG_SUPPORTED
2443 #define BNXT_PHY_FL_PORT_STATS_NO_RESET PORT_PHY_QCAPS_RESP_FLAGS_CUMULATIVE_COUNTERS_ON_RESET
2444 #define BNXT_PHY_FL_NO_PHY_LPBK PORT_PHY_QCAPS_RESP_FLAGS_LOCAL_LPBK_NOT_SUPPORTED
2445 #define BNXT_PHY_FL_FW_MANAGED_LKDN PORT_PHY_QCAPS_RESP_FLAGS_FW_MANAGED_LINK_DOWN
2446 #define BNXT_PHY_FL_NO_FCS PORT_PHY_QCAPS_RESP_FLAGS_NO_FCS
2447 #define BNXT_PHY_FL_NO_PAUSE (PORT_PHY_QCAPS_RESP_FLAGS2_PAUSE_UNSUPPORTED << 8)
2448 #define BNXT_PHY_FL_NO_PFC (PORT_PHY_QCAPS_RESP_FLAGS2_PFC_UNSUPPORTED << 8)
2449 #define BNXT_PHY_FL_BANK_SEL (PORT_PHY_QCAPS_RESP_FLAGS2_BANK_ADDR_SUPPORTED << 8)
2450 #define BNXT_PHY_FL_SPEEDS2 (PORT_PHY_QCAPS_RESP_FLAGS2_SPEEDS2_SUPPORTED << 8)
2453 struct bnxt_test_info *test_info;
2459 struct bnxt_led_info leds[BNXT_MAX_LED];
2461 #define BNXT_DUMP_LIVE 0
2462 #define BNXT_DUMP_CRASH 1
2464 struct bpf_prog *xdp_prog;
2466 struct bnxt_ptp_cfg *ptp_cfg;
2467 u8 ptp_all_rx_tstamp;
2469 /* devlink interface and vf-rep structs */
2471 struct devlink_port dl_port;
2472 enum devlink_eswitch_mode eswitch_mode;
2473 struct bnxt_vf_rep **vf_reps; /* array of vf-rep ptrs */
2474 u16 *cfa_code_map; /* cfa_code -> vf_idx map */
2476 struct bnxt_tc_info *tc_info;
2477 struct list_head tc_indr_block_list;
2478 struct dentry *debugfs_pdev;
2479 #ifdef CONFIG_BNXT_HWMON
2480 struct device *hwmon_dev;
2481 u8 warn_thresh_temp;
2482 u8 crit_thresh_temp;
2483 u8 fatal_thresh_temp;
2484 u8 shutdown_thresh_temp;
2486 u32 thermal_threshold_type;
2487 enum board_idx board_idx;
2490 #define BNXT_NUM_RX_RING_STATS 8
2491 #define BNXT_NUM_TX_RING_STATS 8
2492 #define BNXT_NUM_TPA_RING_STATS 4
2493 #define BNXT_NUM_TPA_RING_STATS_P5 5
2494 #define BNXT_NUM_TPA_RING_STATS_P7 6
2496 #define BNXT_RING_STATS_SIZE_P5 \
2497 ((BNXT_NUM_RX_RING_STATS + BNXT_NUM_TX_RING_STATS + \
2498 BNXT_NUM_TPA_RING_STATS_P5) * 8)
2500 #define BNXT_RING_STATS_SIZE_P7 \
2501 ((BNXT_NUM_RX_RING_STATS + BNXT_NUM_TX_RING_STATS + \
2502 BNXT_NUM_TPA_RING_STATS_P7) * 8)
2504 #define BNXT_GET_RING_STATS64(sw, counter) \
2505 (*((sw) + offsetof(struct ctx_hw_stats, counter) / 8))
2507 #define BNXT_GET_RX_PORT_STATS64(sw, counter) \
2508 (*((sw) + offsetof(struct rx_port_stats, counter) / 8))
2510 #define BNXT_GET_TX_PORT_STATS64(sw, counter) \
2511 (*((sw) + offsetof(struct tx_port_stats, counter) / 8))
2513 #define BNXT_PORT_STATS_SIZE \
2514 (sizeof(struct rx_port_stats) + sizeof(struct tx_port_stats) + 1024)
2516 #define BNXT_TX_PORT_STATS_BYTE_OFFSET \
2517 (sizeof(struct rx_port_stats) + 512)
2519 #define BNXT_RX_STATS_OFFSET(counter) \
2520 (offsetof(struct rx_port_stats, counter) / 8)
2522 #define BNXT_TX_STATS_OFFSET(counter) \
2523 ((offsetof(struct tx_port_stats, counter) + \
2524 BNXT_TX_PORT_STATS_BYTE_OFFSET) / 8)
2526 #define BNXT_RX_STATS_EXT_OFFSET(counter) \
2527 (offsetof(struct rx_port_stats_ext, counter) / 8)
2529 #define BNXT_RX_STATS_EXT_NUM_LEGACY \
2530 BNXT_RX_STATS_EXT_OFFSET(rx_fec_corrected_blocks)
2532 #define BNXT_TX_STATS_EXT_OFFSET(counter) \
2533 (offsetof(struct tx_port_stats_ext, counter) / 8)
2535 #define BNXT_HW_FEATURE_VLAN_ALL_RX \
2536 (NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_STAG_RX)
2537 #define BNXT_HW_FEATURE_VLAN_ALL_TX \
2538 (NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_STAG_TX)
2540 #define I2C_DEV_ADDR_A0 0xa0
2541 #define I2C_DEV_ADDR_A2 0xa2
2542 #define SFF_DIAG_SUPPORT_OFFSET 0x5c
2543 #define SFF_MODULE_ID_SFP 0x3
2544 #define SFF_MODULE_ID_QSFP 0xc
2545 #define SFF_MODULE_ID_QSFP_PLUS 0xd
2546 #define SFF_MODULE_ID_QSFP28 0x11
2547 #define BNXT_MAX_PHY_I2C_RESP_SIZE 64
2549 static inline u32 bnxt_tx_avail(struct bnxt *bp,
2550 const struct bnxt_tx_ring_info *txr)
2552 u32 used = READ_ONCE(txr->tx_prod) - READ_ONCE(txr->tx_cons);
2554 return bp->tx_ring_size - (used & bp->tx_ring_mask);
2557 static inline void bnxt_writeq(struct bnxt *bp, u64 val,
2558 volatile void __iomem *addr)
2560 #if BITS_PER_LONG == 32
2561 spin_lock(&bp->db_lock);
2562 lo_hi_writeq(val, addr);
2563 spin_unlock(&bp->db_lock);
2569 static inline void bnxt_writeq_relaxed(struct bnxt *bp, u64 val,
2570 volatile void __iomem *addr)
2572 #if BITS_PER_LONG == 32
2573 spin_lock(&bp->db_lock);
2574 lo_hi_writeq_relaxed(val, addr);
2575 spin_unlock(&bp->db_lock);
2577 writeq_relaxed(val, addr);
2581 /* For TX and RX ring doorbells with no ordering guarantee*/
2582 static inline void bnxt_db_write_relaxed(struct bnxt *bp,
2583 struct bnxt_db_info *db, u32 idx)
2585 if (bp->flags & BNXT_FLAG_CHIP_P5_PLUS) {
2586 bnxt_writeq_relaxed(bp, db->db_key64 | DB_RING_IDX(db, idx),
2589 u32 db_val = db->db_key32 | DB_RING_IDX(db, idx);
2591 writel_relaxed(db_val, db->doorbell);
2592 if (bp->flags & BNXT_FLAG_DOUBLE_DB)
2593 writel_relaxed(db_val, db->doorbell);
2597 /* For TX and RX ring doorbells */
2598 static inline void bnxt_db_write(struct bnxt *bp, struct bnxt_db_info *db,
2601 if (bp->flags & BNXT_FLAG_CHIP_P5_PLUS) {
2602 bnxt_writeq(bp, db->db_key64 | DB_RING_IDX(db, idx),
2605 u32 db_val = db->db_key32 | DB_RING_IDX(db, idx);
2607 writel(db_val, db->doorbell);
2608 if (bp->flags & BNXT_FLAG_DOUBLE_DB)
2609 writel(db_val, db->doorbell);
2613 /* Must hold rtnl_lock */
2614 static inline bool bnxt_sriov_cfg(struct bnxt *bp)
2616 #if defined(CONFIG_BNXT_SRIOV)
2617 return BNXT_PF(bp) && (bp->pf.active_vfs || bp->sriov_cfg);
2623 extern const u16 bnxt_lhint_arr[];
2625 int bnxt_alloc_rx_data(struct bnxt *bp, struct bnxt_rx_ring_info *rxr,
2626 u16 prod, gfp_t gfp);
2627 void bnxt_reuse_rx_data(struct bnxt_rx_ring_info *rxr, u16 cons, void *data);
2628 u32 bnxt_fw_health_readl(struct bnxt *bp, int reg_idx);
2629 void bnxt_set_tpa_flags(struct bnxt *bp);
2630 void bnxt_set_ring_params(struct bnxt *);
2631 int bnxt_set_rx_skb_mode(struct bnxt *bp, bool page_mode);
2632 int bnxt_hwrm_func_drv_rgtr(struct bnxt *bp, unsigned long *bmap,
2633 int bmap_size, bool async_only);
2634 int bnxt_hwrm_func_drv_unrgtr(struct bnxt *bp);
2635 void bnxt_del_l2_filter(struct bnxt *bp, struct bnxt_l2_filter *fltr);
2636 int bnxt_hwrm_l2_filter_free(struct bnxt *bp, struct bnxt_l2_filter *fltr);
2637 int bnxt_hwrm_l2_filter_alloc(struct bnxt *bp, struct bnxt_l2_filter *fltr);
2638 int bnxt_get_nr_rss_ctxs(struct bnxt *bp, int rx_rings);
2639 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, u16 vnic_id);
2640 int __bnxt_hwrm_get_tx_rings(struct bnxt *bp, u16 fid, int *tx_rings);
2641 int bnxt_nq_rings_in_use(struct bnxt *bp);
2642 int bnxt_hwrm_set_coal(struct bnxt *);
2643 void bnxt_free_ctx_mem(struct bnxt *bp);
2644 int bnxt_num_tx_to_cp(struct bnxt *bp, int tx);
2645 unsigned int bnxt_get_max_func_stat_ctxs(struct bnxt *bp);
2646 unsigned int bnxt_get_avail_stat_ctxs_for_en(struct bnxt *bp);
2647 unsigned int bnxt_get_max_func_cp_rings(struct bnxt *bp);
2648 unsigned int bnxt_get_avail_cp_rings_for_en(struct bnxt *bp);
2649 int bnxt_get_avail_msix(struct bnxt *bp, int num);
2650 int bnxt_reserve_rings(struct bnxt *bp, bool irq_re_init);
2651 void bnxt_tx_disable(struct bnxt *bp);
2652 void bnxt_tx_enable(struct bnxt *bp);
2653 void bnxt_sched_reset_txr(struct bnxt *bp, struct bnxt_tx_ring_info *txr,
2655 void bnxt_report_link(struct bnxt *bp);
2656 int bnxt_update_link(struct bnxt *bp, bool chng_link_state);
2657 int bnxt_hwrm_set_pause(struct bnxt *);
2658 int bnxt_hwrm_set_link_setting(struct bnxt *, bool, bool);
2659 int bnxt_cancel_reservations(struct bnxt *bp, bool fw_reset);
2660 int bnxt_hwrm_alloc_wol_fltr(struct bnxt *bp);
2661 int bnxt_hwrm_free_wol_fltr(struct bnxt *bp);
2662 int bnxt_hwrm_func_resc_qcaps(struct bnxt *bp, bool all);
2663 int bnxt_hwrm_func_qcaps(struct bnxt *bp);
2664 int bnxt_hwrm_fw_set_time(struct bnxt *);
2665 int bnxt_open_nic(struct bnxt *, bool, bool);
2666 int bnxt_half_open_nic(struct bnxt *bp);
2667 void bnxt_half_close_nic(struct bnxt *bp);
2668 void bnxt_reenable_sriov(struct bnxt *bp);
2669 void bnxt_close_nic(struct bnxt *, bool, bool);
2670 void bnxt_get_ring_err_stats(struct bnxt *bp,
2671 struct bnxt_total_ring_err_stats *stats);
2672 int bnxt_dbg_hwrm_rd_reg(struct bnxt *bp, u32 reg_off, u16 num_words,
2674 void bnxt_fw_exception(struct bnxt *bp);
2675 void bnxt_fw_reset(struct bnxt *bp);
2676 int bnxt_check_rings(struct bnxt *bp, int tx, int rx, bool sh, int tcs,
2678 int bnxt_fw_init_one(struct bnxt *bp);
2679 bool bnxt_hwrm_reset_permitted(struct bnxt *bp);
2680 int bnxt_setup_mq_tc(struct net_device *dev, u8 tc);
2681 struct bnxt_ntuple_filter *bnxt_lookup_ntp_filter_from_idx(struct bnxt *bp,
2682 struct bnxt_ntuple_filter *fltr, u32 idx);
2683 u32 bnxt_get_ntp_filter_idx(struct bnxt *bp, struct flow_keys *fkeys,
2684 const struct sk_buff *skb);
2685 int bnxt_insert_ntp_filter(struct bnxt *bp, struct bnxt_ntuple_filter *fltr,
2687 int bnxt_get_max_rings(struct bnxt *, int *, int *, bool);
2688 int bnxt_restore_pf_fw_resources(struct bnxt *bp);
2689 int bnxt_get_port_parent_id(struct net_device *dev,
2690 struct netdev_phys_item_id *ppid);
2691 void bnxt_dim_work(struct work_struct *work);
2692 int bnxt_hwrm_set_ring_coal(struct bnxt *bp, struct bnxt_napi *bnapi);
2693 void bnxt_print_device_info(struct bnxt *bp);