1 /* Broadcom NetXtreme-C/E network driver.
3 * Copyright (c) 2014-2016 Broadcom Corporation
4 * Copyright (c) 2016-2019 Broadcom Limited
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation.
11 #include <linux/module.h>
13 #include <linux/stringify.h>
14 #include <linux/kernel.h>
15 #include <linux/timer.h>
16 #include <linux/errno.h>
17 #include <linux/ioport.h>
18 #include <linux/slab.h>
19 #include <linux/vmalloc.h>
20 #include <linux/interrupt.h>
21 #include <linux/pci.h>
22 #include <linux/netdevice.h>
23 #include <linux/etherdevice.h>
24 #include <linux/skbuff.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/bitops.h>
28 #include <linux/irq.h>
29 #include <linux/delay.h>
30 #include <asm/byteorder.h>
32 #include <linux/time.h>
33 #include <linux/mii.h>
34 #include <linux/mdio.h>
36 #include <linux/if_vlan.h>
37 #include <linux/if_bridge.h>
38 #include <linux/rtc.h>
39 #include <linux/bpf.h>
43 #include <net/checksum.h>
44 #include <net/ip6_checksum.h>
45 #include <net/udp_tunnel.h>
46 #include <linux/workqueue.h>
47 #include <linux/prefetch.h>
48 #include <linux/cache.h>
49 #include <linux/log2.h>
50 #include <linux/aer.h>
51 #include <linux/bitmap.h>
52 #include <linux/cpu_rmap.h>
53 #include <linux/cpumask.h>
54 #include <net/pkt_cls.h>
55 #include <linux/hwmon.h>
56 #include <linux/hwmon-sysfs.h>
57 #include <net/page_pool.h>
62 #include "bnxt_sriov.h"
63 #include "bnxt_ethtool.h"
68 #include "bnxt_devlink.h"
69 #include "bnxt_debugfs.h"
71 #define BNXT_TX_TIMEOUT (5 * HZ)
73 static const char version[] =
74 "Broadcom NetXtreme-C/E driver " DRV_MODULE_NAME " v" DRV_MODULE_VERSION "\n";
76 MODULE_LICENSE("GPL");
77 MODULE_DESCRIPTION("Broadcom BCM573xx network driver");
78 MODULE_VERSION(DRV_MODULE_VERSION);
80 #define BNXT_RX_OFFSET (NET_SKB_PAD + NET_IP_ALIGN)
81 #define BNXT_RX_DMA_OFFSET NET_SKB_PAD
82 #define BNXT_RX_COPY_THRESH 256
84 #define BNXT_TX_PUSH_THRESH 164
128 /* indexed by enum above */
129 static const struct {
132 [BCM57301] = { "Broadcom BCM57301 NetXtreme-C 10Gb Ethernet" },
133 [BCM57302] = { "Broadcom BCM57302 NetXtreme-C 10Gb/25Gb Ethernet" },
134 [BCM57304] = { "Broadcom BCM57304 NetXtreme-C 10Gb/25Gb/40Gb/50Gb Ethernet" },
135 [BCM57417_NPAR] = { "Broadcom BCM57417 NetXtreme-E Ethernet Partition" },
136 [BCM58700] = { "Broadcom BCM58700 Nitro 1Gb/2.5Gb/10Gb Ethernet" },
137 [BCM57311] = { "Broadcom BCM57311 NetXtreme-C 10Gb Ethernet" },
138 [BCM57312] = { "Broadcom BCM57312 NetXtreme-C 10Gb/25Gb Ethernet" },
139 [BCM57402] = { "Broadcom BCM57402 NetXtreme-E 10Gb Ethernet" },
140 [BCM57404] = { "Broadcom BCM57404 NetXtreme-E 10Gb/25Gb Ethernet" },
141 [BCM57406] = { "Broadcom BCM57406 NetXtreme-E 10GBase-T Ethernet" },
142 [BCM57402_NPAR] = { "Broadcom BCM57402 NetXtreme-E Ethernet Partition" },
143 [BCM57407] = { "Broadcom BCM57407 NetXtreme-E 10GBase-T Ethernet" },
144 [BCM57412] = { "Broadcom BCM57412 NetXtreme-E 10Gb Ethernet" },
145 [BCM57414] = { "Broadcom BCM57414 NetXtreme-E 10Gb/25Gb Ethernet" },
146 [BCM57416] = { "Broadcom BCM57416 NetXtreme-E 10GBase-T Ethernet" },
147 [BCM57417] = { "Broadcom BCM57417 NetXtreme-E 10GBase-T Ethernet" },
148 [BCM57412_NPAR] = { "Broadcom BCM57412 NetXtreme-E Ethernet Partition" },
149 [BCM57314] = { "Broadcom BCM57314 NetXtreme-C 10Gb/25Gb/40Gb/50Gb Ethernet" },
150 [BCM57417_SFP] = { "Broadcom BCM57417 NetXtreme-E 10Gb/25Gb Ethernet" },
151 [BCM57416_SFP] = { "Broadcom BCM57416 NetXtreme-E 10Gb Ethernet" },
152 [BCM57404_NPAR] = { "Broadcom BCM57404 NetXtreme-E Ethernet Partition" },
153 [BCM57406_NPAR] = { "Broadcom BCM57406 NetXtreme-E Ethernet Partition" },
154 [BCM57407_SFP] = { "Broadcom BCM57407 NetXtreme-E 25Gb Ethernet" },
155 [BCM57407_NPAR] = { "Broadcom BCM57407 NetXtreme-E Ethernet Partition" },
156 [BCM57414_NPAR] = { "Broadcom BCM57414 NetXtreme-E Ethernet Partition" },
157 [BCM57416_NPAR] = { "Broadcom BCM57416 NetXtreme-E Ethernet Partition" },
158 [BCM57452] = { "Broadcom BCM57452 NetXtreme-E 10Gb/25Gb/40Gb/50Gb Ethernet" },
159 [BCM57454] = { "Broadcom BCM57454 NetXtreme-E 10Gb/25Gb/40Gb/50Gb/100Gb Ethernet" },
160 [BCM5745x_NPAR] = { "Broadcom BCM5745x NetXtreme-E Ethernet Partition" },
161 [BCM57508] = { "Broadcom BCM57508 NetXtreme-E 10Gb/25Gb/50Gb/100Gb/200Gb Ethernet" },
162 [BCM57504] = { "Broadcom BCM57504 NetXtreme-E 10Gb/25Gb/50Gb/100Gb/200Gb Ethernet" },
163 [BCM57502] = { "Broadcom BCM57502 NetXtreme-E 10Gb/25Gb/50Gb Ethernet" },
164 [BCM58802] = { "Broadcom BCM58802 NetXtreme-S 10Gb/25Gb/40Gb/50Gb Ethernet" },
165 [BCM58804] = { "Broadcom BCM58804 NetXtreme-S 10Gb/25Gb/40Gb/50Gb/100Gb Ethernet" },
166 [BCM58808] = { "Broadcom BCM58808 NetXtreme-S 10Gb/25Gb/40Gb/50Gb/100Gb Ethernet" },
167 [NETXTREME_E_VF] = { "Broadcom NetXtreme-E Ethernet Virtual Function" },
168 [NETXTREME_C_VF] = { "Broadcom NetXtreme-C Ethernet Virtual Function" },
169 [NETXTREME_S_VF] = { "Broadcom NetXtreme-S Ethernet Virtual Function" },
170 [NETXTREME_E_P5_VF] = { "Broadcom BCM5750X NetXtreme-E Ethernet Virtual Function" },
173 static const struct pci_device_id bnxt_pci_tbl[] = {
174 { PCI_VDEVICE(BROADCOM, 0x1604), .driver_data = BCM5745x_NPAR },
175 { PCI_VDEVICE(BROADCOM, 0x1605), .driver_data = BCM5745x_NPAR },
176 { PCI_VDEVICE(BROADCOM, 0x1614), .driver_data = BCM57454 },
177 { PCI_VDEVICE(BROADCOM, 0x16c0), .driver_data = BCM57417_NPAR },
178 { PCI_VDEVICE(BROADCOM, 0x16c8), .driver_data = BCM57301 },
179 { PCI_VDEVICE(BROADCOM, 0x16c9), .driver_data = BCM57302 },
180 { PCI_VDEVICE(BROADCOM, 0x16ca), .driver_data = BCM57304 },
181 { PCI_VDEVICE(BROADCOM, 0x16cc), .driver_data = BCM57417_NPAR },
182 { PCI_VDEVICE(BROADCOM, 0x16cd), .driver_data = BCM58700 },
183 { PCI_VDEVICE(BROADCOM, 0x16ce), .driver_data = BCM57311 },
184 { PCI_VDEVICE(BROADCOM, 0x16cf), .driver_data = BCM57312 },
185 { PCI_VDEVICE(BROADCOM, 0x16d0), .driver_data = BCM57402 },
186 { PCI_VDEVICE(BROADCOM, 0x16d1), .driver_data = BCM57404 },
187 { PCI_VDEVICE(BROADCOM, 0x16d2), .driver_data = BCM57406 },
188 { PCI_VDEVICE(BROADCOM, 0x16d4), .driver_data = BCM57402_NPAR },
189 { PCI_VDEVICE(BROADCOM, 0x16d5), .driver_data = BCM57407 },
190 { PCI_VDEVICE(BROADCOM, 0x16d6), .driver_data = BCM57412 },
191 { PCI_VDEVICE(BROADCOM, 0x16d7), .driver_data = BCM57414 },
192 { PCI_VDEVICE(BROADCOM, 0x16d8), .driver_data = BCM57416 },
193 { PCI_VDEVICE(BROADCOM, 0x16d9), .driver_data = BCM57417 },
194 { PCI_VDEVICE(BROADCOM, 0x16de), .driver_data = BCM57412_NPAR },
195 { PCI_VDEVICE(BROADCOM, 0x16df), .driver_data = BCM57314 },
196 { PCI_VDEVICE(BROADCOM, 0x16e2), .driver_data = BCM57417_SFP },
197 { PCI_VDEVICE(BROADCOM, 0x16e3), .driver_data = BCM57416_SFP },
198 { PCI_VDEVICE(BROADCOM, 0x16e7), .driver_data = BCM57404_NPAR },
199 { PCI_VDEVICE(BROADCOM, 0x16e8), .driver_data = BCM57406_NPAR },
200 { PCI_VDEVICE(BROADCOM, 0x16e9), .driver_data = BCM57407_SFP },
201 { PCI_VDEVICE(BROADCOM, 0x16ea), .driver_data = BCM57407_NPAR },
202 { PCI_VDEVICE(BROADCOM, 0x16eb), .driver_data = BCM57412_NPAR },
203 { PCI_VDEVICE(BROADCOM, 0x16ec), .driver_data = BCM57414_NPAR },
204 { PCI_VDEVICE(BROADCOM, 0x16ed), .driver_data = BCM57414_NPAR },
205 { PCI_VDEVICE(BROADCOM, 0x16ee), .driver_data = BCM57416_NPAR },
206 { PCI_VDEVICE(BROADCOM, 0x16ef), .driver_data = BCM57416_NPAR },
207 { PCI_VDEVICE(BROADCOM, 0x16f0), .driver_data = BCM58808 },
208 { PCI_VDEVICE(BROADCOM, 0x16f1), .driver_data = BCM57452 },
209 { PCI_VDEVICE(BROADCOM, 0x1750), .driver_data = BCM57508 },
210 { PCI_VDEVICE(BROADCOM, 0x1751), .driver_data = BCM57504 },
211 { PCI_VDEVICE(BROADCOM, 0x1752), .driver_data = BCM57502 },
212 { PCI_VDEVICE(BROADCOM, 0xd802), .driver_data = BCM58802 },
213 { PCI_VDEVICE(BROADCOM, 0xd804), .driver_data = BCM58804 },
214 #ifdef CONFIG_BNXT_SRIOV
215 { PCI_VDEVICE(BROADCOM, 0x1606), .driver_data = NETXTREME_E_VF },
216 { PCI_VDEVICE(BROADCOM, 0x1609), .driver_data = NETXTREME_E_VF },
217 { PCI_VDEVICE(BROADCOM, 0x16c1), .driver_data = NETXTREME_E_VF },
218 { PCI_VDEVICE(BROADCOM, 0x16cb), .driver_data = NETXTREME_C_VF },
219 { PCI_VDEVICE(BROADCOM, 0x16d3), .driver_data = NETXTREME_E_VF },
220 { PCI_VDEVICE(BROADCOM, 0x16dc), .driver_data = NETXTREME_E_VF },
221 { PCI_VDEVICE(BROADCOM, 0x16e1), .driver_data = NETXTREME_C_VF },
222 { PCI_VDEVICE(BROADCOM, 0x16e5), .driver_data = NETXTREME_C_VF },
223 { PCI_VDEVICE(BROADCOM, 0x1806), .driver_data = NETXTREME_E_P5_VF },
224 { PCI_VDEVICE(BROADCOM, 0x1807), .driver_data = NETXTREME_E_P5_VF },
225 { PCI_VDEVICE(BROADCOM, 0xd800), .driver_data = NETXTREME_S_VF },
230 MODULE_DEVICE_TABLE(pci, bnxt_pci_tbl);
232 static const u16 bnxt_vf_req_snif[] = {
236 HWRM_CFA_L2_FILTER_ALLOC,
239 static const u16 bnxt_async_events_arr[] = {
240 ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE,
241 ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD,
242 ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED,
243 ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE,
244 ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE,
247 static struct workqueue_struct *bnxt_pf_wq;
249 static bool bnxt_vf_pciid(enum board_idx idx)
251 return (idx == NETXTREME_C_VF || idx == NETXTREME_E_VF ||
252 idx == NETXTREME_S_VF || idx == NETXTREME_E_P5_VF);
255 #define DB_CP_REARM_FLAGS (DB_KEY_CP | DB_IDX_VALID)
256 #define DB_CP_FLAGS (DB_KEY_CP | DB_IDX_VALID | DB_IRQ_DIS)
257 #define DB_CP_IRQ_DIS_FLAGS (DB_KEY_CP | DB_IRQ_DIS)
259 #define BNXT_CP_DB_IRQ_DIS(db) \
260 writel(DB_CP_IRQ_DIS_FLAGS, db)
262 #define BNXT_DB_CQ(db, idx) \
263 writel(DB_CP_FLAGS | RING_CMP(idx), (db)->doorbell)
265 #define BNXT_DB_NQ_P5(db, idx) \
266 writeq((db)->db_key64 | DBR_TYPE_NQ | RING_CMP(idx), (db)->doorbell)
268 #define BNXT_DB_CQ_ARM(db, idx) \
269 writel(DB_CP_REARM_FLAGS | RING_CMP(idx), (db)->doorbell)
271 #define BNXT_DB_NQ_ARM_P5(db, idx) \
272 writeq((db)->db_key64 | DBR_TYPE_NQ_ARM | RING_CMP(idx), (db)->doorbell)
274 static void bnxt_db_nq(struct bnxt *bp, struct bnxt_db_info *db, u32 idx)
276 if (bp->flags & BNXT_FLAG_CHIP_P5)
277 BNXT_DB_NQ_P5(db, idx);
282 static void bnxt_db_nq_arm(struct bnxt *bp, struct bnxt_db_info *db, u32 idx)
284 if (bp->flags & BNXT_FLAG_CHIP_P5)
285 BNXT_DB_NQ_ARM_P5(db, idx);
287 BNXT_DB_CQ_ARM(db, idx);
290 static void bnxt_db_cq(struct bnxt *bp, struct bnxt_db_info *db, u32 idx)
292 if (bp->flags & BNXT_FLAG_CHIP_P5)
293 writeq(db->db_key64 | DBR_TYPE_CQ_ARMALL | RING_CMP(idx),
299 const u16 bnxt_lhint_arr[] = {
300 TX_BD_FLAGS_LHINT_512_AND_SMALLER,
301 TX_BD_FLAGS_LHINT_512_TO_1023,
302 TX_BD_FLAGS_LHINT_1024_TO_2047,
303 TX_BD_FLAGS_LHINT_1024_TO_2047,
304 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
305 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
306 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
307 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
308 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
309 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
310 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
311 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
312 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
313 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
314 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
315 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
316 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
317 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
318 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
321 static u16 bnxt_xmit_get_cfa_action(struct sk_buff *skb)
323 struct metadata_dst *md_dst = skb_metadata_dst(skb);
325 if (!md_dst || md_dst->type != METADATA_HW_PORT_MUX)
328 return md_dst->u.port_info.port_id;
331 static netdev_tx_t bnxt_start_xmit(struct sk_buff *skb, struct net_device *dev)
333 struct bnxt *bp = netdev_priv(dev);
335 struct tx_bd_ext *txbd1;
336 struct netdev_queue *txq;
339 unsigned int length, pad = 0;
340 u32 len, free_size, vlan_tag_flags, cfa_action, flags;
342 struct pci_dev *pdev = bp->pdev;
343 struct bnxt_tx_ring_info *txr;
344 struct bnxt_sw_tx_bd *tx_buf;
346 i = skb_get_queue_mapping(skb);
347 if (unlikely(i >= bp->tx_nr_rings)) {
348 dev_kfree_skb_any(skb);
352 txq = netdev_get_tx_queue(dev, i);
353 txr = &bp->tx_ring[bp->tx_ring_map[i]];
356 free_size = bnxt_tx_avail(bp, txr);
357 if (unlikely(free_size < skb_shinfo(skb)->nr_frags + 2)) {
358 netif_tx_stop_queue(txq);
359 return NETDEV_TX_BUSY;
363 len = skb_headlen(skb);
364 last_frag = skb_shinfo(skb)->nr_frags;
366 txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
368 txbd->tx_bd_opaque = prod;
370 tx_buf = &txr->tx_buf_ring[prod];
372 tx_buf->nr_frags = last_frag;
375 cfa_action = bnxt_xmit_get_cfa_action(skb);
376 if (skb_vlan_tag_present(skb)) {
377 vlan_tag_flags = TX_BD_CFA_META_KEY_VLAN |
378 skb_vlan_tag_get(skb);
379 /* Currently supports 8021Q, 8021AD vlan offloads
380 * QINQ1, QINQ2, QINQ3 vlan headers are deprecated
382 if (skb->vlan_proto == htons(ETH_P_8021Q))
383 vlan_tag_flags |= 1 << TX_BD_CFA_META_TPID_SHIFT;
386 if (free_size == bp->tx_ring_size && length <= bp->tx_push_thresh) {
387 struct tx_push_buffer *tx_push_buf = txr->tx_push;
388 struct tx_push_bd *tx_push = &tx_push_buf->push_bd;
389 struct tx_bd_ext *tx_push1 = &tx_push->txbd2;
390 void __iomem *db = txr->tx_db.doorbell;
391 void *pdata = tx_push_buf->data;
395 /* Set COAL_NOW to be ready quickly for the next push */
396 tx_push->tx_bd_len_flags_type =
397 cpu_to_le32((length << TX_BD_LEN_SHIFT) |
398 TX_BD_TYPE_LONG_TX_BD |
399 TX_BD_FLAGS_LHINT_512_AND_SMALLER |
400 TX_BD_FLAGS_COAL_NOW |
401 TX_BD_FLAGS_PACKET_END |
402 (2 << TX_BD_FLAGS_BD_CNT_SHIFT));
404 if (skb->ip_summed == CHECKSUM_PARTIAL)
405 tx_push1->tx_bd_hsize_lflags =
406 cpu_to_le32(TX_BD_FLAGS_TCP_UDP_CHKSUM);
408 tx_push1->tx_bd_hsize_lflags = 0;
410 tx_push1->tx_bd_cfa_meta = cpu_to_le32(vlan_tag_flags);
411 tx_push1->tx_bd_cfa_action =
412 cpu_to_le32(cfa_action << TX_BD_CFA_ACTION_SHIFT);
414 end = pdata + length;
415 end = PTR_ALIGN(end, 8) - 1;
418 skb_copy_from_linear_data(skb, pdata, len);
420 for (j = 0; j < last_frag; j++) {
421 skb_frag_t *frag = &skb_shinfo(skb)->frags[j];
424 fptr = skb_frag_address_safe(frag);
428 memcpy(pdata, fptr, skb_frag_size(frag));
429 pdata += skb_frag_size(frag);
432 txbd->tx_bd_len_flags_type = tx_push->tx_bd_len_flags_type;
433 txbd->tx_bd_haddr = txr->data_mapping;
434 prod = NEXT_TX(prod);
435 txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
436 memcpy(txbd, tx_push1, sizeof(*txbd));
437 prod = NEXT_TX(prod);
439 cpu_to_le32(DB_KEY_TX_PUSH | DB_LONG_TX_PUSH | prod);
443 netdev_tx_sent_queue(txq, skb->len);
444 wmb(); /* Sync is_push and byte queue before pushing data */
446 push_len = (length + sizeof(*tx_push) + 7) / 8;
448 __iowrite64_copy(db, tx_push_buf, 16);
449 __iowrite32_copy(db + 4, tx_push_buf + 1,
450 (push_len - 16) << 1);
452 __iowrite64_copy(db, tx_push_buf, push_len);
459 if (length < BNXT_MIN_PKT_SIZE) {
460 pad = BNXT_MIN_PKT_SIZE - length;
461 if (skb_pad(skb, pad)) {
462 /* SKB already freed. */
466 length = BNXT_MIN_PKT_SIZE;
469 mapping = dma_map_single(&pdev->dev, skb->data, len, DMA_TO_DEVICE);
471 if (unlikely(dma_mapping_error(&pdev->dev, mapping))) {
472 dev_kfree_skb_any(skb);
477 dma_unmap_addr_set(tx_buf, mapping, mapping);
478 flags = (len << TX_BD_LEN_SHIFT) | TX_BD_TYPE_LONG_TX_BD |
479 ((last_frag + 2) << TX_BD_FLAGS_BD_CNT_SHIFT);
481 txbd->tx_bd_haddr = cpu_to_le64(mapping);
483 prod = NEXT_TX(prod);
484 txbd1 = (struct tx_bd_ext *)
485 &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
487 txbd1->tx_bd_hsize_lflags = 0;
488 if (skb_is_gso(skb)) {
491 if (skb->encapsulation)
492 hdr_len = skb_inner_network_offset(skb) +
493 skb_inner_network_header_len(skb) +
494 inner_tcp_hdrlen(skb);
496 hdr_len = skb_transport_offset(skb) +
499 txbd1->tx_bd_hsize_lflags = cpu_to_le32(TX_BD_FLAGS_LSO |
501 (hdr_len << (TX_BD_HSIZE_SHIFT - 1)));
502 length = skb_shinfo(skb)->gso_size;
503 txbd1->tx_bd_mss = cpu_to_le32(length);
505 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
506 txbd1->tx_bd_hsize_lflags =
507 cpu_to_le32(TX_BD_FLAGS_TCP_UDP_CHKSUM);
508 txbd1->tx_bd_mss = 0;
512 if (unlikely(length >= ARRAY_SIZE(bnxt_lhint_arr))) {
513 dev_warn_ratelimited(&pdev->dev, "Dropped oversize %d bytes TX packet.\n",
518 flags |= bnxt_lhint_arr[length];
519 txbd->tx_bd_len_flags_type = cpu_to_le32(flags);
521 txbd1->tx_bd_cfa_meta = cpu_to_le32(vlan_tag_flags);
522 txbd1->tx_bd_cfa_action =
523 cpu_to_le32(cfa_action << TX_BD_CFA_ACTION_SHIFT);
524 for (i = 0; i < last_frag; i++) {
525 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
527 prod = NEXT_TX(prod);
528 txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
530 len = skb_frag_size(frag);
531 mapping = skb_frag_dma_map(&pdev->dev, frag, 0, len,
534 if (unlikely(dma_mapping_error(&pdev->dev, mapping)))
537 tx_buf = &txr->tx_buf_ring[prod];
538 dma_unmap_addr_set(tx_buf, mapping, mapping);
540 txbd->tx_bd_haddr = cpu_to_le64(mapping);
542 flags = len << TX_BD_LEN_SHIFT;
543 txbd->tx_bd_len_flags_type = cpu_to_le32(flags);
547 txbd->tx_bd_len_flags_type =
548 cpu_to_le32(((len + pad) << TX_BD_LEN_SHIFT) | flags |
549 TX_BD_FLAGS_PACKET_END);
551 netdev_tx_sent_queue(txq, skb->len);
553 /* Sync BD data before updating doorbell */
556 prod = NEXT_TX(prod);
559 if (!netdev_xmit_more() || netif_xmit_stopped(txq))
560 bnxt_db_write(bp, &txr->tx_db, prod);
564 if (unlikely(bnxt_tx_avail(bp, txr) <= MAX_SKB_FRAGS + 1)) {
565 if (netdev_xmit_more() && !tx_buf->is_push)
566 bnxt_db_write(bp, &txr->tx_db, prod);
568 netif_tx_stop_queue(txq);
570 /* netif_tx_stop_queue() must be done before checking
571 * tx index in bnxt_tx_avail() below, because in
572 * bnxt_tx_int(), we update tx index before checking for
573 * netif_tx_queue_stopped().
576 if (bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh)
577 netif_tx_wake_queue(txq);
584 /* start back at beginning and unmap skb */
586 tx_buf = &txr->tx_buf_ring[prod];
588 dma_unmap_single(&pdev->dev, dma_unmap_addr(tx_buf, mapping),
589 skb_headlen(skb), PCI_DMA_TODEVICE);
590 prod = NEXT_TX(prod);
592 /* unmap remaining mapped pages */
593 for (i = 0; i < last_frag; i++) {
594 prod = NEXT_TX(prod);
595 tx_buf = &txr->tx_buf_ring[prod];
596 dma_unmap_page(&pdev->dev, dma_unmap_addr(tx_buf, mapping),
597 skb_frag_size(&skb_shinfo(skb)->frags[i]),
601 dev_kfree_skb_any(skb);
605 static void bnxt_tx_int(struct bnxt *bp, struct bnxt_napi *bnapi, int nr_pkts)
607 struct bnxt_tx_ring_info *txr = bnapi->tx_ring;
608 struct netdev_queue *txq = netdev_get_tx_queue(bp->dev, txr->txq_index);
609 u16 cons = txr->tx_cons;
610 struct pci_dev *pdev = bp->pdev;
612 unsigned int tx_bytes = 0;
614 for (i = 0; i < nr_pkts; i++) {
615 struct bnxt_sw_tx_bd *tx_buf;
619 tx_buf = &txr->tx_buf_ring[cons];
620 cons = NEXT_TX(cons);
624 if (tx_buf->is_push) {
629 dma_unmap_single(&pdev->dev, dma_unmap_addr(tx_buf, mapping),
630 skb_headlen(skb), PCI_DMA_TODEVICE);
631 last = tx_buf->nr_frags;
633 for (j = 0; j < last; j++) {
634 cons = NEXT_TX(cons);
635 tx_buf = &txr->tx_buf_ring[cons];
638 dma_unmap_addr(tx_buf, mapping),
639 skb_frag_size(&skb_shinfo(skb)->frags[j]),
644 cons = NEXT_TX(cons);
646 tx_bytes += skb->len;
647 dev_kfree_skb_any(skb);
650 netdev_tx_completed_queue(txq, nr_pkts, tx_bytes);
653 /* Need to make the tx_cons update visible to bnxt_start_xmit()
654 * before checking for netif_tx_queue_stopped(). Without the
655 * memory barrier, there is a small possibility that bnxt_start_xmit()
656 * will miss it and cause the queue to be stopped forever.
660 if (unlikely(netif_tx_queue_stopped(txq)) &&
661 (bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh)) {
662 __netif_tx_lock(txq, smp_processor_id());
663 if (netif_tx_queue_stopped(txq) &&
664 bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh &&
665 txr->dev_state != BNXT_DEV_STATE_CLOSING)
666 netif_tx_wake_queue(txq);
667 __netif_tx_unlock(txq);
671 static struct page *__bnxt_alloc_rx_page(struct bnxt *bp, dma_addr_t *mapping,
672 struct bnxt_rx_ring_info *rxr,
675 struct device *dev = &bp->pdev->dev;
678 page = page_pool_dev_alloc_pages(rxr->page_pool);
682 *mapping = dma_map_page_attrs(dev, page, 0, PAGE_SIZE, bp->rx_dir,
683 DMA_ATTR_WEAK_ORDERING);
684 if (dma_mapping_error(dev, *mapping)) {
685 page_pool_recycle_direct(rxr->page_pool, page);
688 *mapping += bp->rx_dma_offset;
692 static inline u8 *__bnxt_alloc_rx_data(struct bnxt *bp, dma_addr_t *mapping,
696 struct pci_dev *pdev = bp->pdev;
698 data = kmalloc(bp->rx_buf_size, gfp);
702 *mapping = dma_map_single_attrs(&pdev->dev, data + bp->rx_dma_offset,
703 bp->rx_buf_use_size, bp->rx_dir,
704 DMA_ATTR_WEAK_ORDERING);
706 if (dma_mapping_error(&pdev->dev, *mapping)) {
713 int bnxt_alloc_rx_data(struct bnxt *bp, struct bnxt_rx_ring_info *rxr,
716 struct rx_bd *rxbd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
717 struct bnxt_sw_rx_bd *rx_buf = &rxr->rx_buf_ring[prod];
720 if (BNXT_RX_PAGE_MODE(bp)) {
722 __bnxt_alloc_rx_page(bp, &mapping, rxr, gfp);
728 rx_buf->data_ptr = page_address(page) + bp->rx_offset;
730 u8 *data = __bnxt_alloc_rx_data(bp, &mapping, gfp);
736 rx_buf->data_ptr = data + bp->rx_offset;
738 rx_buf->mapping = mapping;
740 rxbd->rx_bd_haddr = cpu_to_le64(mapping);
744 void bnxt_reuse_rx_data(struct bnxt_rx_ring_info *rxr, u16 cons, void *data)
746 u16 prod = rxr->rx_prod;
747 struct bnxt_sw_rx_bd *cons_rx_buf, *prod_rx_buf;
748 struct rx_bd *cons_bd, *prod_bd;
750 prod_rx_buf = &rxr->rx_buf_ring[prod];
751 cons_rx_buf = &rxr->rx_buf_ring[cons];
753 prod_rx_buf->data = data;
754 prod_rx_buf->data_ptr = cons_rx_buf->data_ptr;
756 prod_rx_buf->mapping = cons_rx_buf->mapping;
758 prod_bd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
759 cons_bd = &rxr->rx_desc_ring[RX_RING(cons)][RX_IDX(cons)];
761 prod_bd->rx_bd_haddr = cons_bd->rx_bd_haddr;
764 static inline u16 bnxt_find_next_agg_idx(struct bnxt_rx_ring_info *rxr, u16 idx)
766 u16 next, max = rxr->rx_agg_bmap_size;
768 next = find_next_zero_bit(rxr->rx_agg_bmap, max, idx);
770 next = find_first_zero_bit(rxr->rx_agg_bmap, max);
774 static inline int bnxt_alloc_rx_page(struct bnxt *bp,
775 struct bnxt_rx_ring_info *rxr,
779 &rxr->rx_agg_desc_ring[RX_RING(prod)][RX_IDX(prod)];
780 struct bnxt_sw_rx_agg_bd *rx_agg_buf;
781 struct pci_dev *pdev = bp->pdev;
784 u16 sw_prod = rxr->rx_sw_agg_prod;
785 unsigned int offset = 0;
787 if (PAGE_SIZE > BNXT_RX_PAGE_SIZE) {
790 page = alloc_page(gfp);
794 rxr->rx_page_offset = 0;
796 offset = rxr->rx_page_offset;
797 rxr->rx_page_offset += BNXT_RX_PAGE_SIZE;
798 if (rxr->rx_page_offset == PAGE_SIZE)
803 page = alloc_page(gfp);
808 mapping = dma_map_page_attrs(&pdev->dev, page, offset,
809 BNXT_RX_PAGE_SIZE, PCI_DMA_FROMDEVICE,
810 DMA_ATTR_WEAK_ORDERING);
811 if (dma_mapping_error(&pdev->dev, mapping)) {
816 if (unlikely(test_bit(sw_prod, rxr->rx_agg_bmap)))
817 sw_prod = bnxt_find_next_agg_idx(rxr, sw_prod);
819 __set_bit(sw_prod, rxr->rx_agg_bmap);
820 rx_agg_buf = &rxr->rx_agg_ring[sw_prod];
821 rxr->rx_sw_agg_prod = NEXT_RX_AGG(sw_prod);
823 rx_agg_buf->page = page;
824 rx_agg_buf->offset = offset;
825 rx_agg_buf->mapping = mapping;
826 rxbd->rx_bd_haddr = cpu_to_le64(mapping);
827 rxbd->rx_bd_opaque = sw_prod;
831 static void bnxt_reuse_rx_agg_bufs(struct bnxt_cp_ring_info *cpr, u16 cp_cons,
834 struct bnxt_napi *bnapi = cpr->bnapi;
835 struct bnxt *bp = bnapi->bp;
836 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
837 u16 prod = rxr->rx_agg_prod;
838 u16 sw_prod = rxr->rx_sw_agg_prod;
841 for (i = 0; i < agg_bufs; i++) {
843 struct rx_agg_cmp *agg;
844 struct bnxt_sw_rx_agg_bd *cons_rx_buf, *prod_rx_buf;
845 struct rx_bd *prod_bd;
848 agg = (struct rx_agg_cmp *)
849 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
850 cons = agg->rx_agg_cmp_opaque;
851 __clear_bit(cons, rxr->rx_agg_bmap);
853 if (unlikely(test_bit(sw_prod, rxr->rx_agg_bmap)))
854 sw_prod = bnxt_find_next_agg_idx(rxr, sw_prod);
856 __set_bit(sw_prod, rxr->rx_agg_bmap);
857 prod_rx_buf = &rxr->rx_agg_ring[sw_prod];
858 cons_rx_buf = &rxr->rx_agg_ring[cons];
860 /* It is possible for sw_prod to be equal to cons, so
861 * set cons_rx_buf->page to NULL first.
863 page = cons_rx_buf->page;
864 cons_rx_buf->page = NULL;
865 prod_rx_buf->page = page;
866 prod_rx_buf->offset = cons_rx_buf->offset;
868 prod_rx_buf->mapping = cons_rx_buf->mapping;
870 prod_bd = &rxr->rx_agg_desc_ring[RX_RING(prod)][RX_IDX(prod)];
872 prod_bd->rx_bd_haddr = cpu_to_le64(cons_rx_buf->mapping);
873 prod_bd->rx_bd_opaque = sw_prod;
875 prod = NEXT_RX_AGG(prod);
876 sw_prod = NEXT_RX_AGG(sw_prod);
877 cp_cons = NEXT_CMP(cp_cons);
879 rxr->rx_agg_prod = prod;
880 rxr->rx_sw_agg_prod = sw_prod;
883 static struct sk_buff *bnxt_rx_page_skb(struct bnxt *bp,
884 struct bnxt_rx_ring_info *rxr,
885 u16 cons, void *data, u8 *data_ptr,
887 unsigned int offset_and_len)
889 unsigned int payload = offset_and_len >> 16;
890 unsigned int len = offset_and_len & 0xffff;
891 struct skb_frag_struct *frag;
892 struct page *page = data;
893 u16 prod = rxr->rx_prod;
897 err = bnxt_alloc_rx_data(bp, rxr, prod, GFP_ATOMIC);
899 bnxt_reuse_rx_data(rxr, cons, data);
902 dma_addr -= bp->rx_dma_offset;
903 dma_unmap_page_attrs(&bp->pdev->dev, dma_addr, PAGE_SIZE, bp->rx_dir,
904 DMA_ATTR_WEAK_ORDERING);
906 if (unlikely(!payload))
907 payload = eth_get_headlen(bp->dev, data_ptr, len);
909 skb = napi_alloc_skb(&rxr->bnapi->napi, payload);
915 off = (void *)data_ptr - page_address(page);
916 skb_add_rx_frag(skb, 0, page, off, len, PAGE_SIZE);
917 memcpy(skb->data - NET_IP_ALIGN, data_ptr - NET_IP_ALIGN,
918 payload + NET_IP_ALIGN);
920 frag = &skb_shinfo(skb)->frags[0];
921 skb_frag_size_sub(frag, payload);
922 frag->page_offset += payload;
923 skb->data_len -= payload;
924 skb->tail += payload;
929 static struct sk_buff *bnxt_rx_skb(struct bnxt *bp,
930 struct bnxt_rx_ring_info *rxr, u16 cons,
931 void *data, u8 *data_ptr,
933 unsigned int offset_and_len)
935 u16 prod = rxr->rx_prod;
939 err = bnxt_alloc_rx_data(bp, rxr, prod, GFP_ATOMIC);
941 bnxt_reuse_rx_data(rxr, cons, data);
945 skb = build_skb(data, 0);
946 dma_unmap_single_attrs(&bp->pdev->dev, dma_addr, bp->rx_buf_use_size,
947 bp->rx_dir, DMA_ATTR_WEAK_ORDERING);
953 skb_reserve(skb, bp->rx_offset);
954 skb_put(skb, offset_and_len & 0xffff);
958 static struct sk_buff *bnxt_rx_pages(struct bnxt *bp,
959 struct bnxt_cp_ring_info *cpr,
960 struct sk_buff *skb, u16 cp_cons,
963 struct bnxt_napi *bnapi = cpr->bnapi;
964 struct pci_dev *pdev = bp->pdev;
965 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
966 u16 prod = rxr->rx_agg_prod;
969 for (i = 0; i < agg_bufs; i++) {
971 struct rx_agg_cmp *agg;
972 struct bnxt_sw_rx_agg_bd *cons_rx_buf;
976 agg = (struct rx_agg_cmp *)
977 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
978 cons = agg->rx_agg_cmp_opaque;
979 frag_len = (le32_to_cpu(agg->rx_agg_cmp_len_flags_type) &
980 RX_AGG_CMP_LEN) >> RX_AGG_CMP_LEN_SHIFT;
982 cons_rx_buf = &rxr->rx_agg_ring[cons];
983 skb_fill_page_desc(skb, i, cons_rx_buf->page,
984 cons_rx_buf->offset, frag_len);
985 __clear_bit(cons, rxr->rx_agg_bmap);
987 /* It is possible for bnxt_alloc_rx_page() to allocate
988 * a sw_prod index that equals the cons index, so we
989 * need to clear the cons entry now.
991 mapping = cons_rx_buf->mapping;
992 page = cons_rx_buf->page;
993 cons_rx_buf->page = NULL;
995 if (bnxt_alloc_rx_page(bp, rxr, prod, GFP_ATOMIC) != 0) {
996 struct skb_shared_info *shinfo;
997 unsigned int nr_frags;
999 shinfo = skb_shinfo(skb);
1000 nr_frags = --shinfo->nr_frags;
1001 __skb_frag_set_page(&shinfo->frags[nr_frags], NULL);
1005 cons_rx_buf->page = page;
1007 /* Update prod since possibly some pages have been
1008 * allocated already.
1010 rxr->rx_agg_prod = prod;
1011 bnxt_reuse_rx_agg_bufs(cpr, cp_cons, agg_bufs - i);
1015 dma_unmap_page_attrs(&pdev->dev, mapping, BNXT_RX_PAGE_SIZE,
1017 DMA_ATTR_WEAK_ORDERING);
1019 skb->data_len += frag_len;
1020 skb->len += frag_len;
1021 skb->truesize += PAGE_SIZE;
1023 prod = NEXT_RX_AGG(prod);
1024 cp_cons = NEXT_CMP(cp_cons);
1026 rxr->rx_agg_prod = prod;
1030 static int bnxt_agg_bufs_valid(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1031 u8 agg_bufs, u32 *raw_cons)
1034 struct rx_agg_cmp *agg;
1036 *raw_cons = ADV_RAW_CMP(*raw_cons, agg_bufs);
1037 last = RING_CMP(*raw_cons);
1038 agg = (struct rx_agg_cmp *)
1039 &cpr->cp_desc_ring[CP_RING(last)][CP_IDX(last)];
1040 return RX_AGG_CMP_VALID(agg, *raw_cons);
1043 static inline struct sk_buff *bnxt_copy_skb(struct bnxt_napi *bnapi, u8 *data,
1047 struct bnxt *bp = bnapi->bp;
1048 struct pci_dev *pdev = bp->pdev;
1049 struct sk_buff *skb;
1051 skb = napi_alloc_skb(&bnapi->napi, len);
1055 dma_sync_single_for_cpu(&pdev->dev, mapping, bp->rx_copy_thresh,
1058 memcpy(skb->data - NET_IP_ALIGN, data - NET_IP_ALIGN,
1059 len + NET_IP_ALIGN);
1061 dma_sync_single_for_device(&pdev->dev, mapping, bp->rx_copy_thresh,
1068 static int bnxt_discard_rx(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1069 u32 *raw_cons, void *cmp)
1071 struct rx_cmp *rxcmp = cmp;
1072 u32 tmp_raw_cons = *raw_cons;
1073 u8 cmp_type, agg_bufs = 0;
1075 cmp_type = RX_CMP_TYPE(rxcmp);
1077 if (cmp_type == CMP_TYPE_RX_L2_CMP) {
1078 agg_bufs = (le32_to_cpu(rxcmp->rx_cmp_misc_v1) &
1080 RX_CMP_AGG_BUFS_SHIFT;
1081 } else if (cmp_type == CMP_TYPE_RX_L2_TPA_END_CMP) {
1082 struct rx_tpa_end_cmp *tpa_end = cmp;
1084 agg_bufs = (le32_to_cpu(tpa_end->rx_tpa_end_cmp_misc_v1) &
1085 RX_TPA_END_CMP_AGG_BUFS) >>
1086 RX_TPA_END_CMP_AGG_BUFS_SHIFT;
1090 if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, &tmp_raw_cons))
1093 *raw_cons = tmp_raw_cons;
1097 static void bnxt_queue_sp_work(struct bnxt *bp)
1100 queue_work(bnxt_pf_wq, &bp->sp_task);
1102 schedule_work(&bp->sp_task);
1105 static void bnxt_cancel_sp_work(struct bnxt *bp)
1108 flush_workqueue(bnxt_pf_wq);
1110 cancel_work_sync(&bp->sp_task);
1113 static void bnxt_sched_reset(struct bnxt *bp, struct bnxt_rx_ring_info *rxr)
1115 if (!rxr->bnapi->in_reset) {
1116 rxr->bnapi->in_reset = true;
1117 set_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event);
1118 bnxt_queue_sp_work(bp);
1120 rxr->rx_next_cons = 0xffff;
1123 static void bnxt_tpa_start(struct bnxt *bp, struct bnxt_rx_ring_info *rxr,
1124 struct rx_tpa_start_cmp *tpa_start,
1125 struct rx_tpa_start_cmp_ext *tpa_start1)
1127 u8 agg_id = TPA_START_AGG_ID(tpa_start);
1129 struct bnxt_tpa_info *tpa_info;
1130 struct bnxt_sw_rx_bd *cons_rx_buf, *prod_rx_buf;
1131 struct rx_bd *prod_bd;
1134 cons = tpa_start->rx_tpa_start_cmp_opaque;
1135 prod = rxr->rx_prod;
1136 cons_rx_buf = &rxr->rx_buf_ring[cons];
1137 prod_rx_buf = &rxr->rx_buf_ring[prod];
1138 tpa_info = &rxr->rx_tpa[agg_id];
1140 if (unlikely(cons != rxr->rx_next_cons)) {
1141 netdev_warn(bp->dev, "TPA cons %x != expected cons %x\n",
1142 cons, rxr->rx_next_cons);
1143 bnxt_sched_reset(bp, rxr);
1146 /* Store cfa_code in tpa_info to use in tpa_end
1147 * completion processing.
1149 tpa_info->cfa_code = TPA_START_CFA_CODE(tpa_start1);
1150 prod_rx_buf->data = tpa_info->data;
1151 prod_rx_buf->data_ptr = tpa_info->data_ptr;
1153 mapping = tpa_info->mapping;
1154 prod_rx_buf->mapping = mapping;
1156 prod_bd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
1158 prod_bd->rx_bd_haddr = cpu_to_le64(mapping);
1160 tpa_info->data = cons_rx_buf->data;
1161 tpa_info->data_ptr = cons_rx_buf->data_ptr;
1162 cons_rx_buf->data = NULL;
1163 tpa_info->mapping = cons_rx_buf->mapping;
1166 le32_to_cpu(tpa_start->rx_tpa_start_cmp_len_flags_type) >>
1167 RX_TPA_START_CMP_LEN_SHIFT;
1168 if (likely(TPA_START_HASH_VALID(tpa_start))) {
1169 u32 hash_type = TPA_START_HASH_TYPE(tpa_start);
1171 tpa_info->hash_type = PKT_HASH_TYPE_L4;
1172 tpa_info->gso_type = SKB_GSO_TCPV4;
1173 /* RSS profiles 1 and 3 with extract code 0 for inner 4-tuple */
1174 if (hash_type == 3 || TPA_START_IS_IPV6(tpa_start1))
1175 tpa_info->gso_type = SKB_GSO_TCPV6;
1176 tpa_info->rss_hash =
1177 le32_to_cpu(tpa_start->rx_tpa_start_cmp_rss_hash);
1179 tpa_info->hash_type = PKT_HASH_TYPE_NONE;
1180 tpa_info->gso_type = 0;
1181 if (netif_msg_rx_err(bp))
1182 netdev_warn(bp->dev, "TPA packet without valid hash\n");
1184 tpa_info->flags2 = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_flags2);
1185 tpa_info->metadata = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_metadata);
1186 tpa_info->hdr_info = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_hdr_info);
1188 rxr->rx_prod = NEXT_RX(prod);
1189 cons = NEXT_RX(cons);
1190 rxr->rx_next_cons = NEXT_RX(cons);
1191 cons_rx_buf = &rxr->rx_buf_ring[cons];
1193 bnxt_reuse_rx_data(rxr, cons, cons_rx_buf->data);
1194 rxr->rx_prod = NEXT_RX(rxr->rx_prod);
1195 cons_rx_buf->data = NULL;
1198 static void bnxt_abort_tpa(struct bnxt_cp_ring_info *cpr, u16 cp_cons,
1202 bnxt_reuse_rx_agg_bufs(cpr, cp_cons, agg_bufs);
1205 static struct sk_buff *bnxt_gro_func_5731x(struct bnxt_tpa_info *tpa_info,
1206 int payload_off, int tcp_ts,
1207 struct sk_buff *skb)
1212 u16 outer_ip_off, inner_ip_off, inner_mac_off;
1213 u32 hdr_info = tpa_info->hdr_info;
1214 bool loopback = false;
1216 inner_ip_off = BNXT_TPA_INNER_L3_OFF(hdr_info);
1217 inner_mac_off = BNXT_TPA_INNER_L2_OFF(hdr_info);
1218 outer_ip_off = BNXT_TPA_OUTER_L3_OFF(hdr_info);
1220 /* If the packet is an internal loopback packet, the offsets will
1221 * have an extra 4 bytes.
1223 if (inner_mac_off == 4) {
1225 } else if (inner_mac_off > 4) {
1226 __be16 proto = *((__be16 *)(skb->data + inner_ip_off -
1229 /* We only support inner iPv4/ipv6. If we don't see the
1230 * correct protocol ID, it must be a loopback packet where
1231 * the offsets are off by 4.
1233 if (proto != htons(ETH_P_IP) && proto != htons(ETH_P_IPV6))
1237 /* internal loopback packet, subtract all offsets by 4 */
1243 nw_off = inner_ip_off - ETH_HLEN;
1244 skb_set_network_header(skb, nw_off);
1245 if (tpa_info->flags2 & RX_TPA_START_CMP_FLAGS2_IP_TYPE) {
1246 struct ipv6hdr *iph = ipv6_hdr(skb);
1248 skb_set_transport_header(skb, nw_off + sizeof(struct ipv6hdr));
1249 len = skb->len - skb_transport_offset(skb);
1251 th->check = ~tcp_v6_check(len, &iph->saddr, &iph->daddr, 0);
1253 struct iphdr *iph = ip_hdr(skb);
1255 skb_set_transport_header(skb, nw_off + sizeof(struct iphdr));
1256 len = skb->len - skb_transport_offset(skb);
1258 th->check = ~tcp_v4_check(len, iph->saddr, iph->daddr, 0);
1261 if (inner_mac_off) { /* tunnel */
1262 struct udphdr *uh = NULL;
1263 __be16 proto = *((__be16 *)(skb->data + outer_ip_off -
1266 if (proto == htons(ETH_P_IP)) {
1267 struct iphdr *iph = (struct iphdr *)skb->data;
1269 if (iph->protocol == IPPROTO_UDP)
1270 uh = (struct udphdr *)(iph + 1);
1272 struct ipv6hdr *iph = (struct ipv6hdr *)skb->data;
1274 if (iph->nexthdr == IPPROTO_UDP)
1275 uh = (struct udphdr *)(iph + 1);
1279 skb_shinfo(skb)->gso_type |=
1280 SKB_GSO_UDP_TUNNEL_CSUM;
1282 skb_shinfo(skb)->gso_type |= SKB_GSO_UDP_TUNNEL;
1289 #define BNXT_IPV4_HDR_SIZE (sizeof(struct iphdr) + sizeof(struct tcphdr))
1290 #define BNXT_IPV6_HDR_SIZE (sizeof(struct ipv6hdr) + sizeof(struct tcphdr))
1292 static struct sk_buff *bnxt_gro_func_5730x(struct bnxt_tpa_info *tpa_info,
1293 int payload_off, int tcp_ts,
1294 struct sk_buff *skb)
1298 int len, nw_off, tcp_opt_len = 0;
1303 if (tpa_info->gso_type == SKB_GSO_TCPV4) {
1306 nw_off = payload_off - BNXT_IPV4_HDR_SIZE - tcp_opt_len -
1308 skb_set_network_header(skb, nw_off);
1310 skb_set_transport_header(skb, nw_off + sizeof(struct iphdr));
1311 len = skb->len - skb_transport_offset(skb);
1313 th->check = ~tcp_v4_check(len, iph->saddr, iph->daddr, 0);
1314 } else if (tpa_info->gso_type == SKB_GSO_TCPV6) {
1315 struct ipv6hdr *iph;
1317 nw_off = payload_off - BNXT_IPV6_HDR_SIZE - tcp_opt_len -
1319 skb_set_network_header(skb, nw_off);
1320 iph = ipv6_hdr(skb);
1321 skb_set_transport_header(skb, nw_off + sizeof(struct ipv6hdr));
1322 len = skb->len - skb_transport_offset(skb);
1324 th->check = ~tcp_v6_check(len, &iph->saddr, &iph->daddr, 0);
1326 dev_kfree_skb_any(skb);
1330 if (nw_off) { /* tunnel */
1331 struct udphdr *uh = NULL;
1333 if (skb->protocol == htons(ETH_P_IP)) {
1334 struct iphdr *iph = (struct iphdr *)skb->data;
1336 if (iph->protocol == IPPROTO_UDP)
1337 uh = (struct udphdr *)(iph + 1);
1339 struct ipv6hdr *iph = (struct ipv6hdr *)skb->data;
1341 if (iph->nexthdr == IPPROTO_UDP)
1342 uh = (struct udphdr *)(iph + 1);
1346 skb_shinfo(skb)->gso_type |=
1347 SKB_GSO_UDP_TUNNEL_CSUM;
1349 skb_shinfo(skb)->gso_type |= SKB_GSO_UDP_TUNNEL;
1356 static inline struct sk_buff *bnxt_gro_skb(struct bnxt *bp,
1357 struct bnxt_tpa_info *tpa_info,
1358 struct rx_tpa_end_cmp *tpa_end,
1359 struct rx_tpa_end_cmp_ext *tpa_end1,
1360 struct sk_buff *skb)
1366 segs = TPA_END_TPA_SEGS(tpa_end);
1370 NAPI_GRO_CB(skb)->count = segs;
1371 skb_shinfo(skb)->gso_size =
1372 le32_to_cpu(tpa_end1->rx_tpa_end_cmp_seg_len);
1373 skb_shinfo(skb)->gso_type = tpa_info->gso_type;
1374 payload_off = (le32_to_cpu(tpa_end->rx_tpa_end_cmp_misc_v1) &
1375 RX_TPA_END_CMP_PAYLOAD_OFFSET) >>
1376 RX_TPA_END_CMP_PAYLOAD_OFFSET_SHIFT;
1377 skb = bp->gro_func(tpa_info, payload_off, TPA_END_GRO_TS(tpa_end), skb);
1379 tcp_gro_complete(skb);
1384 /* Given the cfa_code of a received packet determine which
1385 * netdev (vf-rep or PF) the packet is destined to.
1387 static struct net_device *bnxt_get_pkt_dev(struct bnxt *bp, u16 cfa_code)
1389 struct net_device *dev = bnxt_get_vf_rep(bp, cfa_code);
1391 /* if vf-rep dev is NULL, the must belongs to the PF */
1392 return dev ? dev : bp->dev;
1395 static inline struct sk_buff *bnxt_tpa_end(struct bnxt *bp,
1396 struct bnxt_cp_ring_info *cpr,
1398 struct rx_tpa_end_cmp *tpa_end,
1399 struct rx_tpa_end_cmp_ext *tpa_end1,
1402 struct bnxt_napi *bnapi = cpr->bnapi;
1403 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
1404 u8 agg_id = TPA_END_AGG_ID(tpa_end);
1405 u8 *data_ptr, agg_bufs;
1406 u16 cp_cons = RING_CMP(*raw_cons);
1408 struct bnxt_tpa_info *tpa_info;
1410 struct sk_buff *skb;
1413 if (unlikely(bnapi->in_reset)) {
1414 int rc = bnxt_discard_rx(bp, cpr, raw_cons, tpa_end);
1417 return ERR_PTR(-EBUSY);
1421 tpa_info = &rxr->rx_tpa[agg_id];
1422 data = tpa_info->data;
1423 data_ptr = tpa_info->data_ptr;
1425 len = tpa_info->len;
1426 mapping = tpa_info->mapping;
1428 agg_bufs = (le32_to_cpu(tpa_end->rx_tpa_end_cmp_misc_v1) &
1429 RX_TPA_END_CMP_AGG_BUFS) >> RX_TPA_END_CMP_AGG_BUFS_SHIFT;
1432 if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, raw_cons))
1433 return ERR_PTR(-EBUSY);
1435 *event |= BNXT_AGG_EVENT;
1436 cp_cons = NEXT_CMP(cp_cons);
1439 if (unlikely(agg_bufs > MAX_SKB_FRAGS || TPA_END_ERRORS(tpa_end1))) {
1440 bnxt_abort_tpa(cpr, cp_cons, agg_bufs);
1441 if (agg_bufs > MAX_SKB_FRAGS)
1442 netdev_warn(bp->dev, "TPA frags %d exceeded MAX_SKB_FRAGS %d\n",
1443 agg_bufs, (int)MAX_SKB_FRAGS);
1447 if (len <= bp->rx_copy_thresh) {
1448 skb = bnxt_copy_skb(bnapi, data_ptr, len, mapping);
1450 bnxt_abort_tpa(cpr, cp_cons, agg_bufs);
1455 dma_addr_t new_mapping;
1457 new_data = __bnxt_alloc_rx_data(bp, &new_mapping, GFP_ATOMIC);
1459 bnxt_abort_tpa(cpr, cp_cons, agg_bufs);
1463 tpa_info->data = new_data;
1464 tpa_info->data_ptr = new_data + bp->rx_offset;
1465 tpa_info->mapping = new_mapping;
1467 skb = build_skb(data, 0);
1468 dma_unmap_single_attrs(&bp->pdev->dev, mapping,
1469 bp->rx_buf_use_size, bp->rx_dir,
1470 DMA_ATTR_WEAK_ORDERING);
1474 bnxt_abort_tpa(cpr, cp_cons, agg_bufs);
1477 skb_reserve(skb, bp->rx_offset);
1482 skb = bnxt_rx_pages(bp, cpr, skb, cp_cons, agg_bufs);
1484 /* Page reuse already handled by bnxt_rx_pages(). */
1490 eth_type_trans(skb, bnxt_get_pkt_dev(bp, tpa_info->cfa_code));
1492 if (tpa_info->hash_type != PKT_HASH_TYPE_NONE)
1493 skb_set_hash(skb, tpa_info->rss_hash, tpa_info->hash_type);
1495 if ((tpa_info->flags2 & RX_CMP_FLAGS2_META_FORMAT_VLAN) &&
1496 (skb->dev->features & NETIF_F_HW_VLAN_CTAG_RX)) {
1497 u16 vlan_proto = tpa_info->metadata >>
1498 RX_CMP_FLAGS2_METADATA_TPID_SFT;
1499 u16 vtag = tpa_info->metadata & RX_CMP_FLAGS2_METADATA_TCI_MASK;
1501 __vlan_hwaccel_put_tag(skb, htons(vlan_proto), vtag);
1504 skb_checksum_none_assert(skb);
1505 if (likely(tpa_info->flags2 & RX_TPA_START_CMP_FLAGS2_L4_CS_CALC)) {
1506 skb->ip_summed = CHECKSUM_UNNECESSARY;
1508 (tpa_info->flags2 & RX_CMP_FLAGS2_T_L4_CS_CALC) >> 3;
1511 if (TPA_END_GRO(tpa_end))
1512 skb = bnxt_gro_skb(bp, tpa_info, tpa_end, tpa_end1, skb);
1517 static void bnxt_deliver_skb(struct bnxt *bp, struct bnxt_napi *bnapi,
1518 struct sk_buff *skb)
1520 if (skb->dev != bp->dev) {
1521 /* this packet belongs to a vf-rep */
1522 bnxt_vf_rep_rx(bp, skb);
1525 skb_record_rx_queue(skb, bnapi->index);
1526 napi_gro_receive(&bnapi->napi, skb);
1529 /* returns the following:
1530 * 1 - 1 packet successfully received
1531 * 0 - successful TPA_START, packet not completed yet
1532 * -EBUSY - completion ring does not have all the agg buffers yet
1533 * -ENOMEM - packet aborted due to out of memory
1534 * -EIO - packet aborted due to hw error indicated in BD
1536 static int bnxt_rx_pkt(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1537 u32 *raw_cons, u8 *event)
1539 struct bnxt_napi *bnapi = cpr->bnapi;
1540 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
1541 struct net_device *dev = bp->dev;
1542 struct rx_cmp *rxcmp;
1543 struct rx_cmp_ext *rxcmp1;
1544 u32 tmp_raw_cons = *raw_cons;
1545 u16 cfa_code, cons, prod, cp_cons = RING_CMP(tmp_raw_cons);
1546 struct bnxt_sw_rx_bd *rx_buf;
1548 u8 *data_ptr, agg_bufs, cmp_type;
1549 dma_addr_t dma_addr;
1550 struct sk_buff *skb;
1555 rxcmp = (struct rx_cmp *)
1556 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1558 tmp_raw_cons = NEXT_RAW_CMP(tmp_raw_cons);
1559 cp_cons = RING_CMP(tmp_raw_cons);
1560 rxcmp1 = (struct rx_cmp_ext *)
1561 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1563 if (!RX_CMP_VALID(rxcmp1, tmp_raw_cons))
1566 cmp_type = RX_CMP_TYPE(rxcmp);
1568 prod = rxr->rx_prod;
1570 if (cmp_type == CMP_TYPE_RX_L2_TPA_START_CMP) {
1571 bnxt_tpa_start(bp, rxr, (struct rx_tpa_start_cmp *)rxcmp,
1572 (struct rx_tpa_start_cmp_ext *)rxcmp1);
1574 *event |= BNXT_RX_EVENT;
1575 goto next_rx_no_prod_no_len;
1577 } else if (cmp_type == CMP_TYPE_RX_L2_TPA_END_CMP) {
1578 skb = bnxt_tpa_end(bp, cpr, &tmp_raw_cons,
1579 (struct rx_tpa_end_cmp *)rxcmp,
1580 (struct rx_tpa_end_cmp_ext *)rxcmp1, event);
1587 bnxt_deliver_skb(bp, bnapi, skb);
1590 *event |= BNXT_RX_EVENT;
1591 goto next_rx_no_prod_no_len;
1594 cons = rxcmp->rx_cmp_opaque;
1595 if (unlikely(cons != rxr->rx_next_cons)) {
1596 int rc1 = bnxt_discard_rx(bp, cpr, raw_cons, rxcmp);
1598 netdev_warn(bp->dev, "RX cons %x != expected cons %x\n",
1599 cons, rxr->rx_next_cons);
1600 bnxt_sched_reset(bp, rxr);
1603 rx_buf = &rxr->rx_buf_ring[cons];
1604 data = rx_buf->data;
1605 data_ptr = rx_buf->data_ptr;
1608 misc = le32_to_cpu(rxcmp->rx_cmp_misc_v1);
1609 agg_bufs = (misc & RX_CMP_AGG_BUFS) >> RX_CMP_AGG_BUFS_SHIFT;
1612 if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, &tmp_raw_cons))
1615 cp_cons = NEXT_CMP(cp_cons);
1616 *event |= BNXT_AGG_EVENT;
1618 *event |= BNXT_RX_EVENT;
1620 rx_buf->data = NULL;
1621 if (rxcmp1->rx_cmp_cfa_code_errors_v2 & RX_CMP_L2_ERRORS) {
1622 u32 rx_err = le32_to_cpu(rxcmp1->rx_cmp_cfa_code_errors_v2);
1624 bnxt_reuse_rx_data(rxr, cons, data);
1626 bnxt_reuse_rx_agg_bufs(cpr, cp_cons, agg_bufs);
1629 if (rx_err & RX_CMPL_ERRORS_BUFFER_ERROR_MASK) {
1630 netdev_warn(bp->dev, "RX buffer error %x\n", rx_err);
1631 bnxt_sched_reset(bp, rxr);
1633 goto next_rx_no_len;
1636 len = le32_to_cpu(rxcmp->rx_cmp_len_flags_type) >> RX_CMP_LEN_SHIFT;
1637 dma_addr = rx_buf->mapping;
1639 if (bnxt_rx_xdp(bp, rxr, cons, data, &data_ptr, &len, event)) {
1644 if (len <= bp->rx_copy_thresh) {
1645 skb = bnxt_copy_skb(bnapi, data_ptr, len, dma_addr);
1646 bnxt_reuse_rx_data(rxr, cons, data);
1649 bnxt_reuse_rx_agg_bufs(cpr, cp_cons, agg_bufs);
1656 if (rx_buf->data_ptr == data_ptr)
1657 payload = misc & RX_CMP_PAYLOAD_OFFSET;
1660 skb = bp->rx_skb_func(bp, rxr, cons, data, data_ptr, dma_addr,
1669 skb = bnxt_rx_pages(bp, cpr, skb, cp_cons, agg_bufs);
1676 if (RX_CMP_HASH_VALID(rxcmp)) {
1677 u32 hash_type = RX_CMP_HASH_TYPE(rxcmp);
1678 enum pkt_hash_types type = PKT_HASH_TYPE_L4;
1680 /* RSS profiles 1 and 3 with extract code 0 for inner 4-tuple */
1681 if (hash_type != 1 && hash_type != 3)
1682 type = PKT_HASH_TYPE_L3;
1683 skb_set_hash(skb, le32_to_cpu(rxcmp->rx_cmp_rss_hash), type);
1686 cfa_code = RX_CMP_CFA_CODE(rxcmp1);
1687 skb->protocol = eth_type_trans(skb, bnxt_get_pkt_dev(bp, cfa_code));
1689 if ((rxcmp1->rx_cmp_flags2 &
1690 cpu_to_le32(RX_CMP_FLAGS2_META_FORMAT_VLAN)) &&
1691 (skb->dev->features & NETIF_F_HW_VLAN_CTAG_RX)) {
1692 u32 meta_data = le32_to_cpu(rxcmp1->rx_cmp_meta_data);
1693 u16 vtag = meta_data & RX_CMP_FLAGS2_METADATA_TCI_MASK;
1694 u16 vlan_proto = meta_data >> RX_CMP_FLAGS2_METADATA_TPID_SFT;
1696 __vlan_hwaccel_put_tag(skb, htons(vlan_proto), vtag);
1699 skb_checksum_none_assert(skb);
1700 if (RX_CMP_L4_CS_OK(rxcmp1)) {
1701 if (dev->features & NETIF_F_RXCSUM) {
1702 skb->ip_summed = CHECKSUM_UNNECESSARY;
1703 skb->csum_level = RX_CMP_ENCAP(rxcmp1);
1706 if (rxcmp1->rx_cmp_cfa_code_errors_v2 & RX_CMP_L4_CS_ERR_BITS) {
1707 if (dev->features & NETIF_F_RXCSUM)
1708 bnapi->cp_ring.rx_l4_csum_errors++;
1712 bnxt_deliver_skb(bp, bnapi, skb);
1716 cpr->rx_packets += 1;
1717 cpr->rx_bytes += len;
1720 rxr->rx_prod = NEXT_RX(prod);
1721 rxr->rx_next_cons = NEXT_RX(cons);
1723 next_rx_no_prod_no_len:
1724 *raw_cons = tmp_raw_cons;
1729 /* In netpoll mode, if we are using a combined completion ring, we need to
1730 * discard the rx packets and recycle the buffers.
1732 static int bnxt_force_rx_discard(struct bnxt *bp,
1733 struct bnxt_cp_ring_info *cpr,
1734 u32 *raw_cons, u8 *event)
1736 u32 tmp_raw_cons = *raw_cons;
1737 struct rx_cmp_ext *rxcmp1;
1738 struct rx_cmp *rxcmp;
1742 cp_cons = RING_CMP(tmp_raw_cons);
1743 rxcmp = (struct rx_cmp *)
1744 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1746 tmp_raw_cons = NEXT_RAW_CMP(tmp_raw_cons);
1747 cp_cons = RING_CMP(tmp_raw_cons);
1748 rxcmp1 = (struct rx_cmp_ext *)
1749 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1751 if (!RX_CMP_VALID(rxcmp1, tmp_raw_cons))
1754 cmp_type = RX_CMP_TYPE(rxcmp);
1755 if (cmp_type == CMP_TYPE_RX_L2_CMP) {
1756 rxcmp1->rx_cmp_cfa_code_errors_v2 |=
1757 cpu_to_le32(RX_CMPL_ERRORS_CRC_ERROR);
1758 } else if (cmp_type == CMP_TYPE_RX_L2_TPA_END_CMP) {
1759 struct rx_tpa_end_cmp_ext *tpa_end1;
1761 tpa_end1 = (struct rx_tpa_end_cmp_ext *)rxcmp1;
1762 tpa_end1->rx_tpa_end_cmp_errors_v2 |=
1763 cpu_to_le32(RX_TPA_END_CMP_ERRORS);
1765 return bnxt_rx_pkt(bp, cpr, raw_cons, event);
1768 #define BNXT_GET_EVENT_PORT(data) \
1770 ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK)
1772 static int bnxt_async_event_process(struct bnxt *bp,
1773 struct hwrm_async_event_cmpl *cmpl)
1775 u16 event_id = le16_to_cpu(cmpl->event_id);
1777 /* TODO CHIMP_FW: Define event id's for link change, error etc */
1779 case ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE: {
1780 u32 data1 = le32_to_cpu(cmpl->event_data1);
1781 struct bnxt_link_info *link_info = &bp->link_info;
1784 goto async_event_process_exit;
1786 /* print unsupported speed warning in forced speed mode only */
1787 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED) &&
1788 (data1 & 0x20000)) {
1789 u16 fw_speed = link_info->force_link_speed;
1790 u32 speed = bnxt_fw_to_ethtool_speed(fw_speed);
1792 if (speed != SPEED_UNKNOWN)
1793 netdev_warn(bp->dev, "Link speed %d no longer supported\n",
1796 set_bit(BNXT_LINK_SPEED_CHNG_SP_EVENT, &bp->sp_event);
1799 case ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE:
1800 set_bit(BNXT_LINK_CHNG_SP_EVENT, &bp->sp_event);
1802 case ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD:
1803 set_bit(BNXT_HWRM_PF_UNLOAD_SP_EVENT, &bp->sp_event);
1805 case ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED: {
1806 u32 data1 = le32_to_cpu(cmpl->event_data1);
1807 u16 port_id = BNXT_GET_EVENT_PORT(data1);
1812 if (bp->pf.port_id != port_id)
1815 set_bit(BNXT_HWRM_PORT_MODULE_SP_EVENT, &bp->sp_event);
1818 case ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE:
1820 goto async_event_process_exit;
1821 set_bit(BNXT_RESET_TASK_SILENT_SP_EVENT, &bp->sp_event);
1824 goto async_event_process_exit;
1826 bnxt_queue_sp_work(bp);
1827 async_event_process_exit:
1828 bnxt_ulp_async_events(bp, cmpl);
1832 static int bnxt_hwrm_handler(struct bnxt *bp, struct tx_cmp *txcmp)
1834 u16 cmpl_type = TX_CMP_TYPE(txcmp), vf_id, seq_id;
1835 struct hwrm_cmpl *h_cmpl = (struct hwrm_cmpl *)txcmp;
1836 struct hwrm_fwd_req_cmpl *fwd_req_cmpl =
1837 (struct hwrm_fwd_req_cmpl *)txcmp;
1839 switch (cmpl_type) {
1840 case CMPL_BASE_TYPE_HWRM_DONE:
1841 seq_id = le16_to_cpu(h_cmpl->sequence_id);
1842 if (seq_id == bp->hwrm_intr_seq_id)
1843 bp->hwrm_intr_seq_id = (u16)~bp->hwrm_intr_seq_id;
1845 netdev_err(bp->dev, "Invalid hwrm seq id %d\n", seq_id);
1848 case CMPL_BASE_TYPE_HWRM_FWD_REQ:
1849 vf_id = le16_to_cpu(fwd_req_cmpl->source_id);
1851 if ((vf_id < bp->pf.first_vf_id) ||
1852 (vf_id >= bp->pf.first_vf_id + bp->pf.active_vfs)) {
1853 netdev_err(bp->dev, "Msg contains invalid VF id %x\n",
1858 set_bit(vf_id - bp->pf.first_vf_id, bp->pf.vf_event_bmap);
1859 set_bit(BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT, &bp->sp_event);
1860 bnxt_queue_sp_work(bp);
1863 case CMPL_BASE_TYPE_HWRM_ASYNC_EVENT:
1864 bnxt_async_event_process(bp,
1865 (struct hwrm_async_event_cmpl *)txcmp);
1874 static irqreturn_t bnxt_msix(int irq, void *dev_instance)
1876 struct bnxt_napi *bnapi = dev_instance;
1877 struct bnxt *bp = bnapi->bp;
1878 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1879 u32 cons = RING_CMP(cpr->cp_raw_cons);
1882 prefetch(&cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]);
1883 napi_schedule(&bnapi->napi);
1887 static inline int bnxt_has_work(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1889 u32 raw_cons = cpr->cp_raw_cons;
1890 u16 cons = RING_CMP(raw_cons);
1891 struct tx_cmp *txcmp;
1893 txcmp = &cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)];
1895 return TX_CMP_VALID(txcmp, raw_cons);
1898 static irqreturn_t bnxt_inta(int irq, void *dev_instance)
1900 struct bnxt_napi *bnapi = dev_instance;
1901 struct bnxt *bp = bnapi->bp;
1902 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1903 u32 cons = RING_CMP(cpr->cp_raw_cons);
1906 prefetch(&cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]);
1908 if (!bnxt_has_work(bp, cpr)) {
1909 int_status = readl(bp->bar0 + BNXT_CAG_REG_LEGACY_INT_STATUS);
1910 /* return if erroneous interrupt */
1911 if (!(int_status & (0x10000 << cpr->cp_ring_struct.fw_ring_id)))
1915 /* disable ring IRQ */
1916 BNXT_CP_DB_IRQ_DIS(cpr->cp_db.doorbell);
1918 /* Return here if interrupt is shared and is disabled. */
1919 if (unlikely(atomic_read(&bp->intr_sem) != 0))
1922 napi_schedule(&bnapi->napi);
1926 static int __bnxt_poll_work(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1929 struct bnxt_napi *bnapi = cpr->bnapi;
1930 u32 raw_cons = cpr->cp_raw_cons;
1935 struct tx_cmp *txcmp;
1937 cpr->has_more_work = 0;
1941 cons = RING_CMP(raw_cons);
1942 txcmp = &cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)];
1944 if (!TX_CMP_VALID(txcmp, raw_cons))
1947 /* The valid test of the entry must be done first before
1948 * reading any further.
1951 cpr->had_work_done = 1;
1952 if (TX_CMP_TYPE(txcmp) == CMP_TYPE_TX_L2_CMP) {
1954 /* return full budget so NAPI will complete. */
1955 if (unlikely(tx_pkts > bp->tx_wake_thresh)) {
1957 raw_cons = NEXT_RAW_CMP(raw_cons);
1959 cpr->has_more_work = 1;
1962 } else if ((TX_CMP_TYPE(txcmp) & 0x30) == 0x10) {
1964 rc = bnxt_rx_pkt(bp, cpr, &raw_cons, &event);
1966 rc = bnxt_force_rx_discard(bp, cpr, &raw_cons,
1968 if (likely(rc >= 0))
1970 /* Increment rx_pkts when rc is -ENOMEM to count towards
1971 * the NAPI budget. Otherwise, we may potentially loop
1972 * here forever if we consistently cannot allocate
1975 else if (rc == -ENOMEM && budget)
1977 else if (rc == -EBUSY) /* partial completion */
1979 } else if (unlikely((TX_CMP_TYPE(txcmp) ==
1980 CMPL_BASE_TYPE_HWRM_DONE) ||
1981 (TX_CMP_TYPE(txcmp) ==
1982 CMPL_BASE_TYPE_HWRM_FWD_REQ) ||
1983 (TX_CMP_TYPE(txcmp) ==
1984 CMPL_BASE_TYPE_HWRM_ASYNC_EVENT))) {
1985 bnxt_hwrm_handler(bp, txcmp);
1987 raw_cons = NEXT_RAW_CMP(raw_cons);
1989 if (rx_pkts && rx_pkts == budget) {
1990 cpr->has_more_work = 1;
1995 if (event & BNXT_REDIRECT_EVENT)
1998 if (event & BNXT_TX_EVENT) {
1999 struct bnxt_tx_ring_info *txr = bnapi->tx_ring;
2000 u16 prod = txr->tx_prod;
2002 /* Sync BD data before updating doorbell */
2005 bnxt_db_write_relaxed(bp, &txr->tx_db, prod);
2008 cpr->cp_raw_cons = raw_cons;
2009 bnapi->tx_pkts += tx_pkts;
2010 bnapi->events |= event;
2014 static void __bnxt_poll_work_done(struct bnxt *bp, struct bnxt_napi *bnapi)
2016 if (bnapi->tx_pkts) {
2017 bnapi->tx_int(bp, bnapi, bnapi->tx_pkts);
2021 if (bnapi->events & BNXT_RX_EVENT) {
2022 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
2024 bnxt_db_write(bp, &rxr->rx_db, rxr->rx_prod);
2025 if (bnapi->events & BNXT_AGG_EVENT)
2026 bnxt_db_write(bp, &rxr->rx_agg_db, rxr->rx_agg_prod);
2031 static int bnxt_poll_work(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
2034 struct bnxt_napi *bnapi = cpr->bnapi;
2037 rx_pkts = __bnxt_poll_work(bp, cpr, budget);
2039 /* ACK completion ring before freeing tx ring and producing new
2040 * buffers in rx/agg rings to prevent overflowing the completion
2043 bnxt_db_cq(bp, &cpr->cp_db, cpr->cp_raw_cons);
2045 __bnxt_poll_work_done(bp, bnapi);
2049 static int bnxt_poll_nitroa0(struct napi_struct *napi, int budget)
2051 struct bnxt_napi *bnapi = container_of(napi, struct bnxt_napi, napi);
2052 struct bnxt *bp = bnapi->bp;
2053 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
2054 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
2055 struct tx_cmp *txcmp;
2056 struct rx_cmp_ext *rxcmp1;
2057 u32 cp_cons, tmp_raw_cons;
2058 u32 raw_cons = cpr->cp_raw_cons;
2065 cp_cons = RING_CMP(raw_cons);
2066 txcmp = &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
2068 if (!TX_CMP_VALID(txcmp, raw_cons))
2071 if ((TX_CMP_TYPE(txcmp) & 0x30) == 0x10) {
2072 tmp_raw_cons = NEXT_RAW_CMP(raw_cons);
2073 cp_cons = RING_CMP(tmp_raw_cons);
2074 rxcmp1 = (struct rx_cmp_ext *)
2075 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
2077 if (!RX_CMP_VALID(rxcmp1, tmp_raw_cons))
2080 /* force an error to recycle the buffer */
2081 rxcmp1->rx_cmp_cfa_code_errors_v2 |=
2082 cpu_to_le32(RX_CMPL_ERRORS_CRC_ERROR);
2084 rc = bnxt_rx_pkt(bp, cpr, &raw_cons, &event);
2085 if (likely(rc == -EIO) && budget)
2087 else if (rc == -EBUSY) /* partial completion */
2089 } else if (unlikely(TX_CMP_TYPE(txcmp) ==
2090 CMPL_BASE_TYPE_HWRM_DONE)) {
2091 bnxt_hwrm_handler(bp, txcmp);
2094 "Invalid completion received on special ring\n");
2096 raw_cons = NEXT_RAW_CMP(raw_cons);
2098 if (rx_pkts == budget)
2102 cpr->cp_raw_cons = raw_cons;
2103 BNXT_DB_CQ(&cpr->cp_db, cpr->cp_raw_cons);
2104 bnxt_db_write(bp, &rxr->rx_db, rxr->rx_prod);
2106 if (event & BNXT_AGG_EVENT)
2107 bnxt_db_write(bp, &rxr->rx_agg_db, rxr->rx_agg_prod);
2109 if (!bnxt_has_work(bp, cpr) && rx_pkts < budget) {
2110 napi_complete_done(napi, rx_pkts);
2111 BNXT_DB_CQ_ARM(&cpr->cp_db, cpr->cp_raw_cons);
2116 static int bnxt_poll(struct napi_struct *napi, int budget)
2118 struct bnxt_napi *bnapi = container_of(napi, struct bnxt_napi, napi);
2119 struct bnxt *bp = bnapi->bp;
2120 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
2124 work_done += bnxt_poll_work(bp, cpr, budget - work_done);
2126 if (work_done >= budget) {
2128 BNXT_DB_CQ_ARM(&cpr->cp_db, cpr->cp_raw_cons);
2132 if (!bnxt_has_work(bp, cpr)) {
2133 if (napi_complete_done(napi, work_done))
2134 BNXT_DB_CQ_ARM(&cpr->cp_db, cpr->cp_raw_cons);
2138 if (bp->flags & BNXT_FLAG_DIM) {
2139 struct dim_sample dim_sample;
2141 dim_update_sample(cpr->event_ctr,
2145 net_dim(&cpr->dim, dim_sample);
2150 static int __bnxt_poll_cqs(struct bnxt *bp, struct bnxt_napi *bnapi, int budget)
2152 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
2153 int i, work_done = 0;
2155 for (i = 0; i < 2; i++) {
2156 struct bnxt_cp_ring_info *cpr2 = cpr->cp_ring_arr[i];
2159 work_done += __bnxt_poll_work(bp, cpr2,
2160 budget - work_done);
2161 cpr->has_more_work |= cpr2->has_more_work;
2167 static void __bnxt_poll_cqs_done(struct bnxt *bp, struct bnxt_napi *bnapi,
2168 u64 dbr_type, bool all)
2170 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
2173 for (i = 0; i < 2; i++) {
2174 struct bnxt_cp_ring_info *cpr2 = cpr->cp_ring_arr[i];
2175 struct bnxt_db_info *db;
2177 if (cpr2 && (all || cpr2->had_work_done)) {
2179 writeq(db->db_key64 | dbr_type |
2180 RING_CMP(cpr2->cp_raw_cons), db->doorbell);
2181 cpr2->had_work_done = 0;
2184 __bnxt_poll_work_done(bp, bnapi);
2187 static int bnxt_poll_p5(struct napi_struct *napi, int budget)
2189 struct bnxt_napi *bnapi = container_of(napi, struct bnxt_napi, napi);
2190 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
2191 u32 raw_cons = cpr->cp_raw_cons;
2192 struct bnxt *bp = bnapi->bp;
2193 struct nqe_cn *nqcmp;
2197 if (cpr->has_more_work) {
2198 cpr->has_more_work = 0;
2199 work_done = __bnxt_poll_cqs(bp, bnapi, budget);
2200 if (cpr->has_more_work) {
2201 __bnxt_poll_cqs_done(bp, bnapi, DBR_TYPE_CQ, false);
2204 __bnxt_poll_cqs_done(bp, bnapi, DBR_TYPE_CQ_ARMALL, true);
2205 if (napi_complete_done(napi, work_done))
2206 BNXT_DB_NQ_ARM_P5(&cpr->cp_db, cpr->cp_raw_cons);
2210 cons = RING_CMP(raw_cons);
2211 nqcmp = &cpr->nq_desc_ring[CP_RING(cons)][CP_IDX(cons)];
2213 if (!NQ_CMP_VALID(nqcmp, raw_cons)) {
2214 __bnxt_poll_cqs_done(bp, bnapi, DBR_TYPE_CQ_ARMALL,
2216 cpr->cp_raw_cons = raw_cons;
2217 if (napi_complete_done(napi, work_done))
2218 BNXT_DB_NQ_ARM_P5(&cpr->cp_db,
2223 /* The valid test of the entry must be done first before
2224 * reading any further.
2228 if (nqcmp->type == cpu_to_le16(NQ_CN_TYPE_CQ_NOTIFICATION)) {
2229 u32 idx = le32_to_cpu(nqcmp->cq_handle_low);
2230 struct bnxt_cp_ring_info *cpr2;
2232 cpr2 = cpr->cp_ring_arr[idx];
2233 work_done += __bnxt_poll_work(bp, cpr2,
2234 budget - work_done);
2235 cpr->has_more_work = cpr2->has_more_work;
2237 bnxt_hwrm_handler(bp, (struct tx_cmp *)nqcmp);
2239 raw_cons = NEXT_RAW_CMP(raw_cons);
2240 if (cpr->has_more_work)
2243 __bnxt_poll_cqs_done(bp, bnapi, DBR_TYPE_CQ, true);
2244 cpr->cp_raw_cons = raw_cons;
2248 static void bnxt_free_tx_skbs(struct bnxt *bp)
2251 struct pci_dev *pdev = bp->pdev;
2256 max_idx = bp->tx_nr_pages * TX_DESC_CNT;
2257 for (i = 0; i < bp->tx_nr_rings; i++) {
2258 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
2261 for (j = 0; j < max_idx;) {
2262 struct bnxt_sw_tx_bd *tx_buf = &txr->tx_buf_ring[j];
2263 struct sk_buff *skb;
2266 if (i < bp->tx_nr_rings_xdp &&
2267 tx_buf->action == XDP_REDIRECT) {
2268 dma_unmap_single(&pdev->dev,
2269 dma_unmap_addr(tx_buf, mapping),
2270 dma_unmap_len(tx_buf, len),
2272 xdp_return_frame(tx_buf->xdpf);
2274 tx_buf->xdpf = NULL;
2287 if (tx_buf->is_push) {
2293 dma_unmap_single(&pdev->dev,
2294 dma_unmap_addr(tx_buf, mapping),
2298 last = tx_buf->nr_frags;
2300 for (k = 0; k < last; k++, j++) {
2301 int ring_idx = j & bp->tx_ring_mask;
2302 skb_frag_t *frag = &skb_shinfo(skb)->frags[k];
2304 tx_buf = &txr->tx_buf_ring[ring_idx];
2307 dma_unmap_addr(tx_buf, mapping),
2308 skb_frag_size(frag), PCI_DMA_TODEVICE);
2312 netdev_tx_reset_queue(netdev_get_tx_queue(bp->dev, i));
2316 static void bnxt_free_rx_skbs(struct bnxt *bp)
2318 int i, max_idx, max_agg_idx;
2319 struct pci_dev *pdev = bp->pdev;
2324 max_idx = bp->rx_nr_pages * RX_DESC_CNT;
2325 max_agg_idx = bp->rx_agg_nr_pages * RX_DESC_CNT;
2326 for (i = 0; i < bp->rx_nr_rings; i++) {
2327 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
2331 for (j = 0; j < MAX_TPA; j++) {
2332 struct bnxt_tpa_info *tpa_info =
2334 u8 *data = tpa_info->data;
2339 dma_unmap_single_attrs(&pdev->dev,
2341 bp->rx_buf_use_size,
2343 DMA_ATTR_WEAK_ORDERING);
2345 tpa_info->data = NULL;
2351 for (j = 0; j < max_idx; j++) {
2352 struct bnxt_sw_rx_bd *rx_buf = &rxr->rx_buf_ring[j];
2353 dma_addr_t mapping = rx_buf->mapping;
2354 void *data = rx_buf->data;
2359 rx_buf->data = NULL;
2361 if (BNXT_RX_PAGE_MODE(bp)) {
2362 mapping -= bp->rx_dma_offset;
2363 dma_unmap_page_attrs(&pdev->dev, mapping,
2364 PAGE_SIZE, bp->rx_dir,
2365 DMA_ATTR_WEAK_ORDERING);
2366 page_pool_recycle_direct(rxr->page_pool, data);
2368 dma_unmap_single_attrs(&pdev->dev, mapping,
2369 bp->rx_buf_use_size,
2371 DMA_ATTR_WEAK_ORDERING);
2376 for (j = 0; j < max_agg_idx; j++) {
2377 struct bnxt_sw_rx_agg_bd *rx_agg_buf =
2378 &rxr->rx_agg_ring[j];
2379 struct page *page = rx_agg_buf->page;
2384 dma_unmap_page_attrs(&pdev->dev, rx_agg_buf->mapping,
2387 DMA_ATTR_WEAK_ORDERING);
2389 rx_agg_buf->page = NULL;
2390 __clear_bit(j, rxr->rx_agg_bmap);
2395 __free_page(rxr->rx_page);
2396 rxr->rx_page = NULL;
2401 static void bnxt_free_skbs(struct bnxt *bp)
2403 bnxt_free_tx_skbs(bp);
2404 bnxt_free_rx_skbs(bp);
2407 static void bnxt_free_ring(struct bnxt *bp, struct bnxt_ring_mem_info *rmem)
2409 struct pci_dev *pdev = bp->pdev;
2412 for (i = 0; i < rmem->nr_pages; i++) {
2413 if (!rmem->pg_arr[i])
2416 dma_free_coherent(&pdev->dev, rmem->page_size,
2417 rmem->pg_arr[i], rmem->dma_arr[i]);
2419 rmem->pg_arr[i] = NULL;
2422 size_t pg_tbl_size = rmem->nr_pages * 8;
2424 if (rmem->flags & BNXT_RMEM_USE_FULL_PAGE_FLAG)
2425 pg_tbl_size = rmem->page_size;
2426 dma_free_coherent(&pdev->dev, pg_tbl_size,
2427 rmem->pg_tbl, rmem->pg_tbl_map);
2428 rmem->pg_tbl = NULL;
2430 if (rmem->vmem_size && *rmem->vmem) {
2436 static int bnxt_alloc_ring(struct bnxt *bp, struct bnxt_ring_mem_info *rmem)
2438 struct pci_dev *pdev = bp->pdev;
2442 if (rmem->flags & (BNXT_RMEM_VALID_PTE_FLAG | BNXT_RMEM_RING_PTE_FLAG))
2443 valid_bit = PTU_PTE_VALID;
2444 if ((rmem->nr_pages > 1 || rmem->depth > 0) && !rmem->pg_tbl) {
2445 size_t pg_tbl_size = rmem->nr_pages * 8;
2447 if (rmem->flags & BNXT_RMEM_USE_FULL_PAGE_FLAG)
2448 pg_tbl_size = rmem->page_size;
2449 rmem->pg_tbl = dma_alloc_coherent(&pdev->dev, pg_tbl_size,
2456 for (i = 0; i < rmem->nr_pages; i++) {
2457 u64 extra_bits = valid_bit;
2459 rmem->pg_arr[i] = dma_alloc_coherent(&pdev->dev,
2463 if (!rmem->pg_arr[i])
2466 if (rmem->nr_pages > 1 || rmem->depth > 0) {
2467 if (i == rmem->nr_pages - 2 &&
2468 (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
2469 extra_bits |= PTU_PTE_NEXT_TO_LAST;
2470 else if (i == rmem->nr_pages - 1 &&
2471 (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
2472 extra_bits |= PTU_PTE_LAST;
2474 cpu_to_le64(rmem->dma_arr[i] | extra_bits);
2478 if (rmem->vmem_size) {
2479 *rmem->vmem = vzalloc(rmem->vmem_size);
2486 static void bnxt_free_rx_rings(struct bnxt *bp)
2493 for (i = 0; i < bp->rx_nr_rings; i++) {
2494 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
2495 struct bnxt_ring_struct *ring;
2498 bpf_prog_put(rxr->xdp_prog);
2500 if (xdp_rxq_info_is_reg(&rxr->xdp_rxq))
2501 xdp_rxq_info_unreg(&rxr->xdp_rxq);
2503 page_pool_destroy(rxr->page_pool);
2504 rxr->page_pool = NULL;
2509 kfree(rxr->rx_agg_bmap);
2510 rxr->rx_agg_bmap = NULL;
2512 ring = &rxr->rx_ring_struct;
2513 bnxt_free_ring(bp, &ring->ring_mem);
2515 ring = &rxr->rx_agg_ring_struct;
2516 bnxt_free_ring(bp, &ring->ring_mem);
2520 static int bnxt_alloc_rx_page_pool(struct bnxt *bp,
2521 struct bnxt_rx_ring_info *rxr)
2523 struct page_pool_params pp = { 0 };
2525 pp.pool_size = bp->rx_ring_size;
2526 pp.nid = dev_to_node(&bp->pdev->dev);
2527 pp.dev = &bp->pdev->dev;
2528 pp.dma_dir = DMA_BIDIRECTIONAL;
2530 rxr->page_pool = page_pool_create(&pp);
2531 if (IS_ERR(rxr->page_pool)) {
2532 int err = PTR_ERR(rxr->page_pool);
2534 rxr->page_pool = NULL;
2540 static int bnxt_alloc_rx_rings(struct bnxt *bp)
2542 int i, rc, agg_rings = 0, tpa_rings = 0;
2547 if (bp->flags & BNXT_FLAG_AGG_RINGS)
2550 if (bp->flags & BNXT_FLAG_TPA)
2553 for (i = 0; i < bp->rx_nr_rings; i++) {
2554 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
2555 struct bnxt_ring_struct *ring;
2557 ring = &rxr->rx_ring_struct;
2559 rc = bnxt_alloc_rx_page_pool(bp, rxr);
2563 rc = xdp_rxq_info_reg(&rxr->xdp_rxq, bp->dev, i);
2567 rc = xdp_rxq_info_reg_mem_model(&rxr->xdp_rxq,
2571 xdp_rxq_info_unreg(&rxr->xdp_rxq);
2575 rc = bnxt_alloc_ring(bp, &ring->ring_mem);
2583 ring = &rxr->rx_agg_ring_struct;
2584 rc = bnxt_alloc_ring(bp, &ring->ring_mem);
2589 rxr->rx_agg_bmap_size = bp->rx_agg_ring_mask + 1;
2590 mem_size = rxr->rx_agg_bmap_size / 8;
2591 rxr->rx_agg_bmap = kzalloc(mem_size, GFP_KERNEL);
2592 if (!rxr->rx_agg_bmap)
2596 rxr->rx_tpa = kcalloc(MAX_TPA,
2597 sizeof(struct bnxt_tpa_info),
2607 static void bnxt_free_tx_rings(struct bnxt *bp)
2610 struct pci_dev *pdev = bp->pdev;
2615 for (i = 0; i < bp->tx_nr_rings; i++) {
2616 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
2617 struct bnxt_ring_struct *ring;
2620 dma_free_coherent(&pdev->dev, bp->tx_push_size,
2621 txr->tx_push, txr->tx_push_mapping);
2622 txr->tx_push = NULL;
2625 ring = &txr->tx_ring_struct;
2627 bnxt_free_ring(bp, &ring->ring_mem);
2631 static int bnxt_alloc_tx_rings(struct bnxt *bp)
2634 struct pci_dev *pdev = bp->pdev;
2636 bp->tx_push_size = 0;
2637 if (bp->tx_push_thresh) {
2640 push_size = L1_CACHE_ALIGN(sizeof(struct tx_push_bd) +
2641 bp->tx_push_thresh);
2643 if (push_size > 256) {
2645 bp->tx_push_thresh = 0;
2648 bp->tx_push_size = push_size;
2651 for (i = 0, j = 0; i < bp->tx_nr_rings; i++) {
2652 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
2653 struct bnxt_ring_struct *ring;
2656 ring = &txr->tx_ring_struct;
2658 rc = bnxt_alloc_ring(bp, &ring->ring_mem);
2662 ring->grp_idx = txr->bnapi->index;
2663 if (bp->tx_push_size) {
2666 /* One pre-allocated DMA buffer to backup
2669 txr->tx_push = dma_alloc_coherent(&pdev->dev,
2671 &txr->tx_push_mapping,
2677 mapping = txr->tx_push_mapping +
2678 sizeof(struct tx_push_bd);
2679 txr->data_mapping = cpu_to_le64(mapping);
2681 qidx = bp->tc_to_qidx[j];
2682 ring->queue_id = bp->q_info[qidx].queue_id;
2683 if (i < bp->tx_nr_rings_xdp)
2685 if (i % bp->tx_nr_rings_per_tc == (bp->tx_nr_rings_per_tc - 1))
2691 static void bnxt_free_cp_rings(struct bnxt *bp)
2698 for (i = 0; i < bp->cp_nr_rings; i++) {
2699 struct bnxt_napi *bnapi = bp->bnapi[i];
2700 struct bnxt_cp_ring_info *cpr;
2701 struct bnxt_ring_struct *ring;
2707 cpr = &bnapi->cp_ring;
2708 ring = &cpr->cp_ring_struct;
2710 bnxt_free_ring(bp, &ring->ring_mem);
2712 for (j = 0; j < 2; j++) {
2713 struct bnxt_cp_ring_info *cpr2 = cpr->cp_ring_arr[j];
2716 ring = &cpr2->cp_ring_struct;
2717 bnxt_free_ring(bp, &ring->ring_mem);
2719 cpr->cp_ring_arr[j] = NULL;
2725 static struct bnxt_cp_ring_info *bnxt_alloc_cp_sub_ring(struct bnxt *bp)
2727 struct bnxt_ring_mem_info *rmem;
2728 struct bnxt_ring_struct *ring;
2729 struct bnxt_cp_ring_info *cpr;
2732 cpr = kzalloc(sizeof(*cpr), GFP_KERNEL);
2736 ring = &cpr->cp_ring_struct;
2737 rmem = &ring->ring_mem;
2738 rmem->nr_pages = bp->cp_nr_pages;
2739 rmem->page_size = HW_CMPD_RING_SIZE;
2740 rmem->pg_arr = (void **)cpr->cp_desc_ring;
2741 rmem->dma_arr = cpr->cp_desc_mapping;
2742 rmem->flags = BNXT_RMEM_RING_PTE_FLAG;
2743 rc = bnxt_alloc_ring(bp, rmem);
2745 bnxt_free_ring(bp, rmem);
2752 static int bnxt_alloc_cp_rings(struct bnxt *bp)
2754 bool sh = !!(bp->flags & BNXT_FLAG_SHARED_RINGS);
2755 int i, rc, ulp_base_vec, ulp_msix;
2757 ulp_msix = bnxt_get_ulp_msix_num(bp);
2758 ulp_base_vec = bnxt_get_ulp_msix_base(bp);
2759 for (i = 0; i < bp->cp_nr_rings; i++) {
2760 struct bnxt_napi *bnapi = bp->bnapi[i];
2761 struct bnxt_cp_ring_info *cpr;
2762 struct bnxt_ring_struct *ring;
2767 cpr = &bnapi->cp_ring;
2769 ring = &cpr->cp_ring_struct;
2771 rc = bnxt_alloc_ring(bp, &ring->ring_mem);
2775 if (ulp_msix && i >= ulp_base_vec)
2776 ring->map_idx = i + ulp_msix;
2780 if (!(bp->flags & BNXT_FLAG_CHIP_P5))
2783 if (i < bp->rx_nr_rings) {
2784 struct bnxt_cp_ring_info *cpr2 =
2785 bnxt_alloc_cp_sub_ring(bp);
2787 cpr->cp_ring_arr[BNXT_RX_HDL] = cpr2;
2790 cpr2->bnapi = bnapi;
2792 if ((sh && i < bp->tx_nr_rings) ||
2793 (!sh && i >= bp->rx_nr_rings)) {
2794 struct bnxt_cp_ring_info *cpr2 =
2795 bnxt_alloc_cp_sub_ring(bp);
2797 cpr->cp_ring_arr[BNXT_TX_HDL] = cpr2;
2800 cpr2->bnapi = bnapi;
2806 static void bnxt_init_ring_struct(struct bnxt *bp)
2810 for (i = 0; i < bp->cp_nr_rings; i++) {
2811 struct bnxt_napi *bnapi = bp->bnapi[i];
2812 struct bnxt_ring_mem_info *rmem;
2813 struct bnxt_cp_ring_info *cpr;
2814 struct bnxt_rx_ring_info *rxr;
2815 struct bnxt_tx_ring_info *txr;
2816 struct bnxt_ring_struct *ring;
2821 cpr = &bnapi->cp_ring;
2822 ring = &cpr->cp_ring_struct;
2823 rmem = &ring->ring_mem;
2824 rmem->nr_pages = bp->cp_nr_pages;
2825 rmem->page_size = HW_CMPD_RING_SIZE;
2826 rmem->pg_arr = (void **)cpr->cp_desc_ring;
2827 rmem->dma_arr = cpr->cp_desc_mapping;
2828 rmem->vmem_size = 0;
2830 rxr = bnapi->rx_ring;
2834 ring = &rxr->rx_ring_struct;
2835 rmem = &ring->ring_mem;
2836 rmem->nr_pages = bp->rx_nr_pages;
2837 rmem->page_size = HW_RXBD_RING_SIZE;
2838 rmem->pg_arr = (void **)rxr->rx_desc_ring;
2839 rmem->dma_arr = rxr->rx_desc_mapping;
2840 rmem->vmem_size = SW_RXBD_RING_SIZE * bp->rx_nr_pages;
2841 rmem->vmem = (void **)&rxr->rx_buf_ring;
2843 ring = &rxr->rx_agg_ring_struct;
2844 rmem = &ring->ring_mem;
2845 rmem->nr_pages = bp->rx_agg_nr_pages;
2846 rmem->page_size = HW_RXBD_RING_SIZE;
2847 rmem->pg_arr = (void **)rxr->rx_agg_desc_ring;
2848 rmem->dma_arr = rxr->rx_agg_desc_mapping;
2849 rmem->vmem_size = SW_RXBD_AGG_RING_SIZE * bp->rx_agg_nr_pages;
2850 rmem->vmem = (void **)&rxr->rx_agg_ring;
2853 txr = bnapi->tx_ring;
2857 ring = &txr->tx_ring_struct;
2858 rmem = &ring->ring_mem;
2859 rmem->nr_pages = bp->tx_nr_pages;
2860 rmem->page_size = HW_RXBD_RING_SIZE;
2861 rmem->pg_arr = (void **)txr->tx_desc_ring;
2862 rmem->dma_arr = txr->tx_desc_mapping;
2863 rmem->vmem_size = SW_TXBD_RING_SIZE * bp->tx_nr_pages;
2864 rmem->vmem = (void **)&txr->tx_buf_ring;
2868 static void bnxt_init_rxbd_pages(struct bnxt_ring_struct *ring, u32 type)
2872 struct rx_bd **rx_buf_ring;
2874 rx_buf_ring = (struct rx_bd **)ring->ring_mem.pg_arr;
2875 for (i = 0, prod = 0; i < ring->ring_mem.nr_pages; i++) {
2879 rxbd = rx_buf_ring[i];
2883 for (j = 0; j < RX_DESC_CNT; j++, rxbd++, prod++) {
2884 rxbd->rx_bd_len_flags_type = cpu_to_le32(type);
2885 rxbd->rx_bd_opaque = prod;
2890 static int bnxt_init_one_rx_ring(struct bnxt *bp, int ring_nr)
2892 struct net_device *dev = bp->dev;
2893 struct bnxt_rx_ring_info *rxr;
2894 struct bnxt_ring_struct *ring;
2898 type = (bp->rx_buf_use_size << RX_BD_LEN_SHIFT) |
2899 RX_BD_TYPE_RX_PACKET_BD | RX_BD_FLAGS_EOP;
2901 if (NET_IP_ALIGN == 2)
2902 type |= RX_BD_FLAGS_SOP;
2904 rxr = &bp->rx_ring[ring_nr];
2905 ring = &rxr->rx_ring_struct;
2906 bnxt_init_rxbd_pages(ring, type);
2908 if (BNXT_RX_PAGE_MODE(bp) && bp->xdp_prog) {
2909 rxr->xdp_prog = bpf_prog_add(bp->xdp_prog, 1);
2910 if (IS_ERR(rxr->xdp_prog)) {
2911 int rc = PTR_ERR(rxr->xdp_prog);
2913 rxr->xdp_prog = NULL;
2917 prod = rxr->rx_prod;
2918 for (i = 0; i < bp->rx_ring_size; i++) {
2919 if (bnxt_alloc_rx_data(bp, rxr, prod, GFP_KERNEL) != 0) {
2920 netdev_warn(dev, "init'ed rx ring %d with %d/%d skbs only\n",
2921 ring_nr, i, bp->rx_ring_size);
2924 prod = NEXT_RX(prod);
2926 rxr->rx_prod = prod;
2927 ring->fw_ring_id = INVALID_HW_RING_ID;
2929 ring = &rxr->rx_agg_ring_struct;
2930 ring->fw_ring_id = INVALID_HW_RING_ID;
2932 if (!(bp->flags & BNXT_FLAG_AGG_RINGS))
2935 type = ((u32)BNXT_RX_PAGE_SIZE << RX_BD_LEN_SHIFT) |
2936 RX_BD_TYPE_RX_AGG_BD | RX_BD_FLAGS_SOP;
2938 bnxt_init_rxbd_pages(ring, type);
2940 prod = rxr->rx_agg_prod;
2941 for (i = 0; i < bp->rx_agg_ring_size; i++) {
2942 if (bnxt_alloc_rx_page(bp, rxr, prod, GFP_KERNEL) != 0) {
2943 netdev_warn(dev, "init'ed rx ring %d with %d/%d pages only\n",
2944 ring_nr, i, bp->rx_ring_size);
2947 prod = NEXT_RX_AGG(prod);
2949 rxr->rx_agg_prod = prod;
2951 if (bp->flags & BNXT_FLAG_TPA) {
2956 for (i = 0; i < MAX_TPA; i++) {
2957 data = __bnxt_alloc_rx_data(bp, &mapping,
2962 rxr->rx_tpa[i].data = data;
2963 rxr->rx_tpa[i].data_ptr = data + bp->rx_offset;
2964 rxr->rx_tpa[i].mapping = mapping;
2967 netdev_err(bp->dev, "No resource allocated for LRO/GRO\n");
2975 static void bnxt_init_cp_rings(struct bnxt *bp)
2979 for (i = 0; i < bp->cp_nr_rings; i++) {
2980 struct bnxt_cp_ring_info *cpr = &bp->bnapi[i]->cp_ring;
2981 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct;
2983 ring->fw_ring_id = INVALID_HW_RING_ID;
2984 cpr->rx_ring_coal.coal_ticks = bp->rx_coal.coal_ticks;
2985 cpr->rx_ring_coal.coal_bufs = bp->rx_coal.coal_bufs;
2986 for (j = 0; j < 2; j++) {
2987 struct bnxt_cp_ring_info *cpr2 = cpr->cp_ring_arr[j];
2992 ring = &cpr2->cp_ring_struct;
2993 ring->fw_ring_id = INVALID_HW_RING_ID;
2994 cpr2->rx_ring_coal.coal_ticks = bp->rx_coal.coal_ticks;
2995 cpr2->rx_ring_coal.coal_bufs = bp->rx_coal.coal_bufs;
3000 static int bnxt_init_rx_rings(struct bnxt *bp)
3004 if (BNXT_RX_PAGE_MODE(bp)) {
3005 bp->rx_offset = NET_IP_ALIGN + XDP_PACKET_HEADROOM;
3006 bp->rx_dma_offset = XDP_PACKET_HEADROOM;
3008 bp->rx_offset = BNXT_RX_OFFSET;
3009 bp->rx_dma_offset = BNXT_RX_DMA_OFFSET;
3012 for (i = 0; i < bp->rx_nr_rings; i++) {
3013 rc = bnxt_init_one_rx_ring(bp, i);
3021 static int bnxt_init_tx_rings(struct bnxt *bp)
3025 bp->tx_wake_thresh = max_t(int, bp->tx_ring_size / 2,
3028 for (i = 0; i < bp->tx_nr_rings; i++) {
3029 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
3030 struct bnxt_ring_struct *ring = &txr->tx_ring_struct;
3032 ring->fw_ring_id = INVALID_HW_RING_ID;
3038 static void bnxt_free_ring_grps(struct bnxt *bp)
3040 kfree(bp->grp_info);
3041 bp->grp_info = NULL;
3044 static int bnxt_init_ring_grps(struct bnxt *bp, bool irq_re_init)
3049 bp->grp_info = kcalloc(bp->cp_nr_rings,
3050 sizeof(struct bnxt_ring_grp_info),
3055 for (i = 0; i < bp->cp_nr_rings; i++) {
3057 bp->grp_info[i].fw_stats_ctx = INVALID_HW_RING_ID;
3058 bp->grp_info[i].fw_grp_id = INVALID_HW_RING_ID;
3059 bp->grp_info[i].rx_fw_ring_id = INVALID_HW_RING_ID;
3060 bp->grp_info[i].agg_fw_ring_id = INVALID_HW_RING_ID;
3061 bp->grp_info[i].cp_fw_ring_id = INVALID_HW_RING_ID;
3066 static void bnxt_free_vnics(struct bnxt *bp)
3068 kfree(bp->vnic_info);
3069 bp->vnic_info = NULL;
3073 static int bnxt_alloc_vnics(struct bnxt *bp)
3077 #ifdef CONFIG_RFS_ACCEL
3078 if ((bp->flags & (BNXT_FLAG_RFS | BNXT_FLAG_CHIP_P5)) == BNXT_FLAG_RFS)
3079 num_vnics += bp->rx_nr_rings;
3082 if (BNXT_CHIP_TYPE_NITRO_A0(bp))
3085 bp->vnic_info = kcalloc(num_vnics, sizeof(struct bnxt_vnic_info),
3090 bp->nr_vnics = num_vnics;
3094 static void bnxt_init_vnics(struct bnxt *bp)
3098 for (i = 0; i < bp->nr_vnics; i++) {
3099 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3102 vnic->fw_vnic_id = INVALID_HW_RING_ID;
3103 for (j = 0; j < BNXT_MAX_CTX_PER_VNIC; j++)
3104 vnic->fw_rss_cos_lb_ctx[j] = INVALID_HW_RING_ID;
3106 vnic->fw_l2_ctx_id = INVALID_HW_RING_ID;
3108 if (bp->vnic_info[i].rss_hash_key) {
3110 prandom_bytes(vnic->rss_hash_key,
3113 memcpy(vnic->rss_hash_key,
3114 bp->vnic_info[0].rss_hash_key,
3120 static int bnxt_calc_nr_ring_pages(u32 ring_size, int desc_per_pg)
3124 pages = ring_size / desc_per_pg;
3131 while (pages & (pages - 1))
3137 void bnxt_set_tpa_flags(struct bnxt *bp)
3139 bp->flags &= ~BNXT_FLAG_TPA;
3140 if (bp->flags & BNXT_FLAG_NO_AGG_RINGS)
3142 if (bp->dev->features & NETIF_F_LRO)
3143 bp->flags |= BNXT_FLAG_LRO;
3144 else if (bp->dev->features & NETIF_F_GRO_HW)
3145 bp->flags |= BNXT_FLAG_GRO;
3148 /* bp->rx_ring_size, bp->tx_ring_size, dev->mtu, BNXT_FLAG_{G|L}RO flags must
3151 void bnxt_set_ring_params(struct bnxt *bp)
3153 u32 ring_size, rx_size, rx_space;
3154 u32 agg_factor = 0, agg_ring_size = 0;
3156 /* 8 for CRC and VLAN */
3157 rx_size = SKB_DATA_ALIGN(bp->dev->mtu + ETH_HLEN + NET_IP_ALIGN + 8);
3159 rx_space = rx_size + NET_SKB_PAD +
3160 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
3162 bp->rx_copy_thresh = BNXT_RX_COPY_THRESH;
3163 ring_size = bp->rx_ring_size;
3164 bp->rx_agg_ring_size = 0;
3165 bp->rx_agg_nr_pages = 0;
3167 if (bp->flags & BNXT_FLAG_TPA)
3168 agg_factor = min_t(u32, 4, 65536 / BNXT_RX_PAGE_SIZE);
3170 bp->flags &= ~BNXT_FLAG_JUMBO;
3171 if (rx_space > PAGE_SIZE && !(bp->flags & BNXT_FLAG_NO_AGG_RINGS)) {
3174 bp->flags |= BNXT_FLAG_JUMBO;
3175 jumbo_factor = PAGE_ALIGN(bp->dev->mtu - 40) >> PAGE_SHIFT;
3176 if (jumbo_factor > agg_factor)
3177 agg_factor = jumbo_factor;
3179 agg_ring_size = ring_size * agg_factor;
3181 if (agg_ring_size) {
3182 bp->rx_agg_nr_pages = bnxt_calc_nr_ring_pages(agg_ring_size,
3184 if (bp->rx_agg_nr_pages > MAX_RX_AGG_PAGES) {
3185 u32 tmp = agg_ring_size;
3187 bp->rx_agg_nr_pages = MAX_RX_AGG_PAGES;
3188 agg_ring_size = MAX_RX_AGG_PAGES * RX_DESC_CNT - 1;
3189 netdev_warn(bp->dev, "rx agg ring size %d reduced to %d.\n",
3190 tmp, agg_ring_size);
3192 bp->rx_agg_ring_size = agg_ring_size;
3193 bp->rx_agg_ring_mask = (bp->rx_agg_nr_pages * RX_DESC_CNT) - 1;
3194 rx_size = SKB_DATA_ALIGN(BNXT_RX_COPY_THRESH + NET_IP_ALIGN);
3195 rx_space = rx_size + NET_SKB_PAD +
3196 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
3199 bp->rx_buf_use_size = rx_size;
3200 bp->rx_buf_size = rx_space;
3202 bp->rx_nr_pages = bnxt_calc_nr_ring_pages(ring_size, RX_DESC_CNT);
3203 bp->rx_ring_mask = (bp->rx_nr_pages * RX_DESC_CNT) - 1;
3205 ring_size = bp->tx_ring_size;
3206 bp->tx_nr_pages = bnxt_calc_nr_ring_pages(ring_size, TX_DESC_CNT);
3207 bp->tx_ring_mask = (bp->tx_nr_pages * TX_DESC_CNT) - 1;
3209 ring_size = bp->rx_ring_size * (2 + agg_factor) + bp->tx_ring_size;
3210 bp->cp_ring_size = ring_size;
3212 bp->cp_nr_pages = bnxt_calc_nr_ring_pages(ring_size, CP_DESC_CNT);
3213 if (bp->cp_nr_pages > MAX_CP_PAGES) {
3214 bp->cp_nr_pages = MAX_CP_PAGES;
3215 bp->cp_ring_size = MAX_CP_PAGES * CP_DESC_CNT - 1;
3216 netdev_warn(bp->dev, "completion ring size %d reduced to %d.\n",
3217 ring_size, bp->cp_ring_size);
3219 bp->cp_bit = bp->cp_nr_pages * CP_DESC_CNT;
3220 bp->cp_ring_mask = bp->cp_bit - 1;
3223 /* Changing allocation mode of RX rings.
3224 * TODO: Update when extending xdp_rxq_info to support allocation modes.
3226 int bnxt_set_rx_skb_mode(struct bnxt *bp, bool page_mode)
3229 if (bp->dev->mtu > BNXT_MAX_PAGE_MODE_MTU)
3232 min_t(u16, bp->max_mtu, BNXT_MAX_PAGE_MODE_MTU);
3233 bp->flags &= ~BNXT_FLAG_AGG_RINGS;
3234 bp->flags |= BNXT_FLAG_NO_AGG_RINGS | BNXT_FLAG_RX_PAGE_MODE;
3235 bp->rx_dir = DMA_BIDIRECTIONAL;
3236 bp->rx_skb_func = bnxt_rx_page_skb;
3237 /* Disable LRO or GRO_HW */
3238 netdev_update_features(bp->dev);
3240 bp->dev->max_mtu = bp->max_mtu;
3241 bp->flags &= ~BNXT_FLAG_RX_PAGE_MODE;
3242 bp->rx_dir = DMA_FROM_DEVICE;
3243 bp->rx_skb_func = bnxt_rx_skb;
3248 static void bnxt_free_vnic_attributes(struct bnxt *bp)
3251 struct bnxt_vnic_info *vnic;
3252 struct pci_dev *pdev = bp->pdev;
3257 for (i = 0; i < bp->nr_vnics; i++) {
3258 vnic = &bp->vnic_info[i];
3260 kfree(vnic->fw_grp_ids);
3261 vnic->fw_grp_ids = NULL;
3263 kfree(vnic->uc_list);
3264 vnic->uc_list = NULL;
3266 if (vnic->mc_list) {
3267 dma_free_coherent(&pdev->dev, vnic->mc_list_size,
3268 vnic->mc_list, vnic->mc_list_mapping);
3269 vnic->mc_list = NULL;
3272 if (vnic->rss_table) {
3273 dma_free_coherent(&pdev->dev, PAGE_SIZE,
3275 vnic->rss_table_dma_addr);
3276 vnic->rss_table = NULL;
3279 vnic->rss_hash_key = NULL;
3284 static int bnxt_alloc_vnic_attributes(struct bnxt *bp)
3286 int i, rc = 0, size;
3287 struct bnxt_vnic_info *vnic;
3288 struct pci_dev *pdev = bp->pdev;
3291 for (i = 0; i < bp->nr_vnics; i++) {
3292 vnic = &bp->vnic_info[i];
3294 if (vnic->flags & BNXT_VNIC_UCAST_FLAG) {
3295 int mem_size = (BNXT_MAX_UC_ADDRS - 1) * ETH_ALEN;
3298 vnic->uc_list = kmalloc(mem_size, GFP_KERNEL);
3299 if (!vnic->uc_list) {
3306 if (vnic->flags & BNXT_VNIC_MCAST_FLAG) {
3307 vnic->mc_list_size = BNXT_MAX_MC_ADDRS * ETH_ALEN;
3309 dma_alloc_coherent(&pdev->dev,
3311 &vnic->mc_list_mapping,
3313 if (!vnic->mc_list) {
3319 if (bp->flags & BNXT_FLAG_CHIP_P5)
3320 goto vnic_skip_grps;
3322 if (vnic->flags & BNXT_VNIC_RSS_FLAG)
3323 max_rings = bp->rx_nr_rings;
3327 vnic->fw_grp_ids = kcalloc(max_rings, sizeof(u16), GFP_KERNEL);
3328 if (!vnic->fw_grp_ids) {
3333 if ((bp->flags & BNXT_FLAG_NEW_RSS_CAP) &&
3334 !(vnic->flags & BNXT_VNIC_RSS_FLAG))
3337 /* Allocate rss table and hash key */
3338 vnic->rss_table = dma_alloc_coherent(&pdev->dev, PAGE_SIZE,
3339 &vnic->rss_table_dma_addr,
3341 if (!vnic->rss_table) {
3346 size = L1_CACHE_ALIGN(HW_HASH_INDEX_SIZE * sizeof(u16));
3348 vnic->rss_hash_key = ((void *)vnic->rss_table) + size;
3349 vnic->rss_hash_key_dma_addr = vnic->rss_table_dma_addr + size;
3357 static void bnxt_free_hwrm_resources(struct bnxt *bp)
3359 struct pci_dev *pdev = bp->pdev;
3361 if (bp->hwrm_cmd_resp_addr) {
3362 dma_free_coherent(&pdev->dev, PAGE_SIZE, bp->hwrm_cmd_resp_addr,
3363 bp->hwrm_cmd_resp_dma_addr);
3364 bp->hwrm_cmd_resp_addr = NULL;
3367 if (bp->hwrm_cmd_kong_resp_addr) {
3368 dma_free_coherent(&pdev->dev, PAGE_SIZE,
3369 bp->hwrm_cmd_kong_resp_addr,
3370 bp->hwrm_cmd_kong_resp_dma_addr);
3371 bp->hwrm_cmd_kong_resp_addr = NULL;
3375 static int bnxt_alloc_kong_hwrm_resources(struct bnxt *bp)
3377 struct pci_dev *pdev = bp->pdev;
3379 bp->hwrm_cmd_kong_resp_addr =
3380 dma_alloc_coherent(&pdev->dev, PAGE_SIZE,
3381 &bp->hwrm_cmd_kong_resp_dma_addr,
3383 if (!bp->hwrm_cmd_kong_resp_addr)
3389 static int bnxt_alloc_hwrm_resources(struct bnxt *bp)
3391 struct pci_dev *pdev = bp->pdev;
3393 bp->hwrm_cmd_resp_addr = dma_alloc_coherent(&pdev->dev, PAGE_SIZE,
3394 &bp->hwrm_cmd_resp_dma_addr,
3396 if (!bp->hwrm_cmd_resp_addr)
3402 static void bnxt_free_hwrm_short_cmd_req(struct bnxt *bp)
3404 if (bp->hwrm_short_cmd_req_addr) {
3405 struct pci_dev *pdev = bp->pdev;
3407 dma_free_coherent(&pdev->dev, bp->hwrm_max_ext_req_len,
3408 bp->hwrm_short_cmd_req_addr,
3409 bp->hwrm_short_cmd_req_dma_addr);
3410 bp->hwrm_short_cmd_req_addr = NULL;
3414 static int bnxt_alloc_hwrm_short_cmd_req(struct bnxt *bp)
3416 struct pci_dev *pdev = bp->pdev;
3418 bp->hwrm_short_cmd_req_addr =
3419 dma_alloc_coherent(&pdev->dev, bp->hwrm_max_ext_req_len,
3420 &bp->hwrm_short_cmd_req_dma_addr,
3422 if (!bp->hwrm_short_cmd_req_addr)
3428 static void bnxt_free_port_stats(struct bnxt *bp)
3430 struct pci_dev *pdev = bp->pdev;
3432 bp->flags &= ~BNXT_FLAG_PORT_STATS;
3433 bp->flags &= ~BNXT_FLAG_PORT_STATS_EXT;
3435 if (bp->hw_rx_port_stats) {
3436 dma_free_coherent(&pdev->dev, bp->hw_port_stats_size,
3437 bp->hw_rx_port_stats,
3438 bp->hw_rx_port_stats_map);
3439 bp->hw_rx_port_stats = NULL;
3442 if (bp->hw_tx_port_stats_ext) {
3443 dma_free_coherent(&pdev->dev, sizeof(struct tx_port_stats_ext),
3444 bp->hw_tx_port_stats_ext,
3445 bp->hw_tx_port_stats_ext_map);
3446 bp->hw_tx_port_stats_ext = NULL;
3449 if (bp->hw_rx_port_stats_ext) {
3450 dma_free_coherent(&pdev->dev, sizeof(struct rx_port_stats_ext),
3451 bp->hw_rx_port_stats_ext,
3452 bp->hw_rx_port_stats_ext_map);
3453 bp->hw_rx_port_stats_ext = NULL;
3456 if (bp->hw_pcie_stats) {
3457 dma_free_coherent(&pdev->dev, sizeof(struct pcie_ctx_hw_stats),
3458 bp->hw_pcie_stats, bp->hw_pcie_stats_map);
3459 bp->hw_pcie_stats = NULL;
3463 static void bnxt_free_ring_stats(struct bnxt *bp)
3465 struct pci_dev *pdev = bp->pdev;
3471 size = sizeof(struct ctx_hw_stats);
3473 for (i = 0; i < bp->cp_nr_rings; i++) {
3474 struct bnxt_napi *bnapi = bp->bnapi[i];
3475 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
3477 if (cpr->hw_stats) {
3478 dma_free_coherent(&pdev->dev, size, cpr->hw_stats,
3480 cpr->hw_stats = NULL;
3485 static int bnxt_alloc_stats(struct bnxt *bp)
3488 struct pci_dev *pdev = bp->pdev;
3490 size = sizeof(struct ctx_hw_stats);
3492 for (i = 0; i < bp->cp_nr_rings; i++) {
3493 struct bnxt_napi *bnapi = bp->bnapi[i];
3494 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
3496 cpr->hw_stats = dma_alloc_coherent(&pdev->dev, size,
3502 cpr->hw_stats_ctx_id = INVALID_STATS_CTX_ID;
3505 if (BNXT_VF(bp) || bp->chip_num == CHIP_NUM_58700)
3508 if (bp->hw_rx_port_stats)
3509 goto alloc_ext_stats;
3511 bp->hw_port_stats_size = sizeof(struct rx_port_stats) +
3512 sizeof(struct tx_port_stats) + 1024;
3514 bp->hw_rx_port_stats =
3515 dma_alloc_coherent(&pdev->dev, bp->hw_port_stats_size,
3516 &bp->hw_rx_port_stats_map,
3518 if (!bp->hw_rx_port_stats)
3521 bp->hw_tx_port_stats = (void *)(bp->hw_rx_port_stats + 1) + 512;
3522 bp->hw_tx_port_stats_map = bp->hw_rx_port_stats_map +
3523 sizeof(struct rx_port_stats) + 512;
3524 bp->flags |= BNXT_FLAG_PORT_STATS;
3527 /* Display extended statistics only if FW supports it */
3528 if (bp->hwrm_spec_code < 0x10804 || bp->hwrm_spec_code == 0x10900)
3529 if (!(bp->fw_cap & BNXT_FW_CAP_EXT_STATS_SUPPORTED))
3532 if (bp->hw_rx_port_stats_ext)
3533 goto alloc_tx_ext_stats;
3535 bp->hw_rx_port_stats_ext =
3536 dma_alloc_coherent(&pdev->dev, sizeof(struct rx_port_stats_ext),
3537 &bp->hw_rx_port_stats_ext_map, GFP_KERNEL);
3538 if (!bp->hw_rx_port_stats_ext)
3542 if (bp->hw_tx_port_stats_ext)
3543 goto alloc_pcie_stats;
3545 if (bp->hwrm_spec_code >= 0x10902 ||
3546 (bp->fw_cap & BNXT_FW_CAP_EXT_STATS_SUPPORTED)) {
3547 bp->hw_tx_port_stats_ext =
3548 dma_alloc_coherent(&pdev->dev,
3549 sizeof(struct tx_port_stats_ext),
3550 &bp->hw_tx_port_stats_ext_map,
3553 bp->flags |= BNXT_FLAG_PORT_STATS_EXT;
3556 if (bp->hw_pcie_stats ||
3557 !(bp->fw_cap & BNXT_FW_CAP_PCIE_STATS_SUPPORTED))
3561 dma_alloc_coherent(&pdev->dev, sizeof(struct pcie_ctx_hw_stats),
3562 &bp->hw_pcie_stats_map, GFP_KERNEL);
3563 if (!bp->hw_pcie_stats)
3566 bp->flags |= BNXT_FLAG_PCIE_STATS;
3570 static void bnxt_clear_ring_indices(struct bnxt *bp)
3577 for (i = 0; i < bp->cp_nr_rings; i++) {
3578 struct bnxt_napi *bnapi = bp->bnapi[i];
3579 struct bnxt_cp_ring_info *cpr;
3580 struct bnxt_rx_ring_info *rxr;
3581 struct bnxt_tx_ring_info *txr;
3586 cpr = &bnapi->cp_ring;
3587 cpr->cp_raw_cons = 0;
3589 txr = bnapi->tx_ring;
3595 rxr = bnapi->rx_ring;
3598 rxr->rx_agg_prod = 0;
3599 rxr->rx_sw_agg_prod = 0;
3600 rxr->rx_next_cons = 0;
3605 static void bnxt_free_ntp_fltrs(struct bnxt *bp, bool irq_reinit)
3607 #ifdef CONFIG_RFS_ACCEL
3610 /* Under rtnl_lock and all our NAPIs have been disabled. It's
3611 * safe to delete the hash table.
3613 for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) {
3614 struct hlist_head *head;
3615 struct hlist_node *tmp;
3616 struct bnxt_ntuple_filter *fltr;
3618 head = &bp->ntp_fltr_hash_tbl[i];
3619 hlist_for_each_entry_safe(fltr, tmp, head, hash) {
3620 hlist_del(&fltr->hash);
3625 kfree(bp->ntp_fltr_bmap);
3626 bp->ntp_fltr_bmap = NULL;
3628 bp->ntp_fltr_count = 0;
3632 static int bnxt_alloc_ntp_fltrs(struct bnxt *bp)
3634 #ifdef CONFIG_RFS_ACCEL
3637 if (!(bp->flags & BNXT_FLAG_RFS))
3640 for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++)
3641 INIT_HLIST_HEAD(&bp->ntp_fltr_hash_tbl[i]);
3643 bp->ntp_fltr_count = 0;
3644 bp->ntp_fltr_bmap = kcalloc(BITS_TO_LONGS(BNXT_NTP_FLTR_MAX_FLTR),
3648 if (!bp->ntp_fltr_bmap)
3657 static void bnxt_free_mem(struct bnxt *bp, bool irq_re_init)
3659 bnxt_free_vnic_attributes(bp);
3660 bnxt_free_tx_rings(bp);
3661 bnxt_free_rx_rings(bp);
3662 bnxt_free_cp_rings(bp);
3663 bnxt_free_ntp_fltrs(bp, irq_re_init);
3665 bnxt_free_ring_stats(bp);
3666 bnxt_free_ring_grps(bp);
3667 bnxt_free_vnics(bp);
3668 kfree(bp->tx_ring_map);
3669 bp->tx_ring_map = NULL;
3677 bnxt_clear_ring_indices(bp);
3681 static int bnxt_alloc_mem(struct bnxt *bp, bool irq_re_init)
3683 int i, j, rc, size, arr_size;
3687 /* Allocate bnapi mem pointer array and mem block for
3690 arr_size = L1_CACHE_ALIGN(sizeof(struct bnxt_napi *) *
3692 size = L1_CACHE_ALIGN(sizeof(struct bnxt_napi));
3693 bnapi = kzalloc(arr_size + size * bp->cp_nr_rings, GFP_KERNEL);
3699 for (i = 0; i < bp->cp_nr_rings; i++, bnapi += size) {
3700 bp->bnapi[i] = bnapi;
3701 bp->bnapi[i]->index = i;
3702 bp->bnapi[i]->bp = bp;
3703 if (bp->flags & BNXT_FLAG_CHIP_P5) {
3704 struct bnxt_cp_ring_info *cpr =
3705 &bp->bnapi[i]->cp_ring;
3707 cpr->cp_ring_struct.ring_mem.flags =
3708 BNXT_RMEM_RING_PTE_FLAG;
3712 bp->rx_ring = kcalloc(bp->rx_nr_rings,
3713 sizeof(struct bnxt_rx_ring_info),
3718 for (i = 0; i < bp->rx_nr_rings; i++) {
3719 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
3721 if (bp->flags & BNXT_FLAG_CHIP_P5) {
3722 rxr->rx_ring_struct.ring_mem.flags =
3723 BNXT_RMEM_RING_PTE_FLAG;
3724 rxr->rx_agg_ring_struct.ring_mem.flags =
3725 BNXT_RMEM_RING_PTE_FLAG;
3727 rxr->bnapi = bp->bnapi[i];
3728 bp->bnapi[i]->rx_ring = &bp->rx_ring[i];
3731 bp->tx_ring = kcalloc(bp->tx_nr_rings,
3732 sizeof(struct bnxt_tx_ring_info),
3737 bp->tx_ring_map = kcalloc(bp->tx_nr_rings, sizeof(u16),
3740 if (!bp->tx_ring_map)
3743 if (bp->flags & BNXT_FLAG_SHARED_RINGS)
3746 j = bp->rx_nr_rings;
3748 for (i = 0; i < bp->tx_nr_rings; i++, j++) {
3749 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
3751 if (bp->flags & BNXT_FLAG_CHIP_P5)
3752 txr->tx_ring_struct.ring_mem.flags =
3753 BNXT_RMEM_RING_PTE_FLAG;
3754 txr->bnapi = bp->bnapi[j];
3755 bp->bnapi[j]->tx_ring = txr;
3756 bp->tx_ring_map[i] = bp->tx_nr_rings_xdp + i;
3757 if (i >= bp->tx_nr_rings_xdp) {
3758 txr->txq_index = i - bp->tx_nr_rings_xdp;
3759 bp->bnapi[j]->tx_int = bnxt_tx_int;
3761 bp->bnapi[j]->flags |= BNXT_NAPI_FLAG_XDP;
3762 bp->bnapi[j]->tx_int = bnxt_tx_int_xdp;
3766 rc = bnxt_alloc_stats(bp);
3770 rc = bnxt_alloc_ntp_fltrs(bp);
3774 rc = bnxt_alloc_vnics(bp);
3779 bnxt_init_ring_struct(bp);
3781 rc = bnxt_alloc_rx_rings(bp);
3785 rc = bnxt_alloc_tx_rings(bp);
3789 rc = bnxt_alloc_cp_rings(bp);
3793 bp->vnic_info[0].flags |= BNXT_VNIC_RSS_FLAG | BNXT_VNIC_MCAST_FLAG |
3794 BNXT_VNIC_UCAST_FLAG;
3795 rc = bnxt_alloc_vnic_attributes(bp);
3801 bnxt_free_mem(bp, true);
3805 static void bnxt_disable_int(struct bnxt *bp)
3812 for (i = 0; i < bp->cp_nr_rings; i++) {
3813 struct bnxt_napi *bnapi = bp->bnapi[i];
3814 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
3815 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct;
3817 if (ring->fw_ring_id != INVALID_HW_RING_ID)
3818 bnxt_db_nq(bp, &cpr->cp_db, cpr->cp_raw_cons);
3822 static int bnxt_cp_num_to_irq_num(struct bnxt *bp, int n)
3824 struct bnxt_napi *bnapi = bp->bnapi[n];
3825 struct bnxt_cp_ring_info *cpr;
3827 cpr = &bnapi->cp_ring;
3828 return cpr->cp_ring_struct.map_idx;
3831 static void bnxt_disable_int_sync(struct bnxt *bp)
3835 atomic_inc(&bp->intr_sem);
3837 bnxt_disable_int(bp);
3838 for (i = 0; i < bp->cp_nr_rings; i++) {
3839 int map_idx = bnxt_cp_num_to_irq_num(bp, i);
3841 synchronize_irq(bp->irq_tbl[map_idx].vector);
3845 static void bnxt_enable_int(struct bnxt *bp)
3849 atomic_set(&bp->intr_sem, 0);
3850 for (i = 0; i < bp->cp_nr_rings; i++) {
3851 struct bnxt_napi *bnapi = bp->bnapi[i];
3852 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
3854 bnxt_db_nq_arm(bp, &cpr->cp_db, cpr->cp_raw_cons);
3858 void bnxt_hwrm_cmd_hdr_init(struct bnxt *bp, void *request, u16 req_type,
3859 u16 cmpl_ring, u16 target_id)
3861 struct input *req = request;
3863 req->req_type = cpu_to_le16(req_type);
3864 req->cmpl_ring = cpu_to_le16(cmpl_ring);
3865 req->target_id = cpu_to_le16(target_id);
3866 if (bnxt_kong_hwrm_message(bp, req))
3867 req->resp_addr = cpu_to_le64(bp->hwrm_cmd_kong_resp_dma_addr);
3869 req->resp_addr = cpu_to_le64(bp->hwrm_cmd_resp_dma_addr);
3872 static int bnxt_hwrm_do_send_msg(struct bnxt *bp, void *msg, u32 msg_len,
3873 int timeout, bool silent)
3875 int i, intr_process, rc, tmo_count;
3876 struct input *req = msg;
3880 u16 cp_ring_id, len = 0;
3881 struct hwrm_err_output *resp = bp->hwrm_cmd_resp_addr;
3882 u16 max_req_len = BNXT_HWRM_MAX_REQ_LEN;
3883 struct hwrm_short_input short_input = {0};
3884 u32 doorbell_offset = BNXT_GRCPF_REG_CHIMP_COMM_TRIGGER;
3885 u8 *resp_addr = (u8 *)bp->hwrm_cmd_resp_addr;
3886 u32 bar_offset = BNXT_GRCPF_REG_CHIMP_COMM;
3887 u16 dst = BNXT_HWRM_CHNL_CHIMP;
3889 if (msg_len > BNXT_HWRM_MAX_REQ_LEN) {
3890 if (msg_len > bp->hwrm_max_ext_req_len ||
3891 !bp->hwrm_short_cmd_req_addr)
3895 if (bnxt_hwrm_kong_chnl(bp, req)) {
3896 dst = BNXT_HWRM_CHNL_KONG;
3897 bar_offset = BNXT_GRCPF_REG_KONG_COMM;
3898 doorbell_offset = BNXT_GRCPF_REG_KONG_COMM_TRIGGER;
3899 resp = bp->hwrm_cmd_kong_resp_addr;
3900 resp_addr = (u8 *)bp->hwrm_cmd_kong_resp_addr;
3903 memset(resp, 0, PAGE_SIZE);
3904 cp_ring_id = le16_to_cpu(req->cmpl_ring);
3905 intr_process = (cp_ring_id == INVALID_HW_RING_ID) ? 0 : 1;
3907 req->seq_id = cpu_to_le16(bnxt_get_hwrm_seq_id(bp, dst));
3908 /* currently supports only one outstanding message */
3910 bp->hwrm_intr_seq_id = le16_to_cpu(req->seq_id);
3912 if ((bp->fw_cap & BNXT_FW_CAP_SHORT_CMD) ||
3913 msg_len > BNXT_HWRM_MAX_REQ_LEN) {
3914 void *short_cmd_req = bp->hwrm_short_cmd_req_addr;
3917 /* Set boundary for maximum extended request length for short
3918 * cmd format. If passed up from device use the max supported
3919 * internal req length.
3921 max_msg_len = bp->hwrm_max_ext_req_len;
3923 memcpy(short_cmd_req, req, msg_len);
3924 if (msg_len < max_msg_len)
3925 memset(short_cmd_req + msg_len, 0,
3926 max_msg_len - msg_len);
3928 short_input.req_type = req->req_type;
3929 short_input.signature =
3930 cpu_to_le16(SHORT_REQ_SIGNATURE_SHORT_CMD);
3931 short_input.size = cpu_to_le16(msg_len);
3932 short_input.req_addr =
3933 cpu_to_le64(bp->hwrm_short_cmd_req_dma_addr);
3935 data = (u32 *)&short_input;
3936 msg_len = sizeof(short_input);
3938 /* Sync memory write before updating doorbell */
3941 max_req_len = BNXT_HWRM_SHORT_REQ_LEN;
3944 /* Write request msg to hwrm channel */
3945 __iowrite32_copy(bp->bar0 + bar_offset, data, msg_len / 4);
3947 for (i = msg_len; i < max_req_len; i += 4)
3948 writel(0, bp->bar0 + bar_offset + i);
3950 /* Ring channel doorbell */
3951 writel(1, bp->bar0 + doorbell_offset);
3954 timeout = DFLT_HWRM_CMD_TIMEOUT;
3955 /* convert timeout to usec */
3959 /* Short timeout for the first few iterations:
3960 * number of loops = number of loops for short timeout +
3961 * number of loops for standard timeout.
3963 tmo_count = HWRM_SHORT_TIMEOUT_COUNTER;
3964 timeout = timeout - HWRM_SHORT_MIN_TIMEOUT * HWRM_SHORT_TIMEOUT_COUNTER;
3965 tmo_count += DIV_ROUND_UP(timeout, HWRM_MIN_TIMEOUT);
3966 resp_len = (__le32 *)(resp_addr + HWRM_RESP_LEN_OFFSET);
3969 u16 seq_id = bp->hwrm_intr_seq_id;
3971 /* Wait until hwrm response cmpl interrupt is processed */
3972 while (bp->hwrm_intr_seq_id != (u16)~seq_id &&
3974 /* on first few passes, just barely sleep */
3975 if (i < HWRM_SHORT_TIMEOUT_COUNTER)
3976 usleep_range(HWRM_SHORT_MIN_TIMEOUT,
3977 HWRM_SHORT_MAX_TIMEOUT);
3979 usleep_range(HWRM_MIN_TIMEOUT,
3983 if (bp->hwrm_intr_seq_id != (u16)~seq_id) {
3984 netdev_err(bp->dev, "Resp cmpl intr err msg: 0x%x\n",
3985 le16_to_cpu(req->req_type));
3988 len = (le32_to_cpu(*resp_len) & HWRM_RESP_LEN_MASK) >>
3990 valid = resp_addr + len - 1;
3994 /* Check if response len is updated */
3995 for (i = 0; i < tmo_count; i++) {
3996 len = (le32_to_cpu(*resp_len) & HWRM_RESP_LEN_MASK) >>
4000 /* on first few passes, just barely sleep */
4001 if (i < HWRM_SHORT_TIMEOUT_COUNTER)
4002 usleep_range(HWRM_SHORT_MIN_TIMEOUT,
4003 HWRM_SHORT_MAX_TIMEOUT);
4005 usleep_range(HWRM_MIN_TIMEOUT,
4009 if (i >= tmo_count) {
4010 netdev_err(bp->dev, "Error (timeout: %d) msg {0x%x 0x%x} len:%d\n",
4011 HWRM_TOTAL_TIMEOUT(i),
4012 le16_to_cpu(req->req_type),
4013 le16_to_cpu(req->seq_id), len);
4017 /* Last byte of resp contains valid bit */
4018 valid = resp_addr + len - 1;
4019 for (j = 0; j < HWRM_VALID_BIT_DELAY_USEC; j++) {
4020 /* make sure we read from updated DMA memory */
4027 if (j >= HWRM_VALID_BIT_DELAY_USEC) {
4028 netdev_err(bp->dev, "Error (timeout: %d) msg {0x%x 0x%x} len:%d v:%d\n",
4029 HWRM_TOTAL_TIMEOUT(i),
4030 le16_to_cpu(req->req_type),
4031 le16_to_cpu(req->seq_id), len, *valid);
4036 /* Zero valid bit for compatibility. Valid bit in an older spec
4037 * may become a new field in a newer spec. We must make sure that
4038 * a new field not implemented by old spec will read zero.
4041 rc = le16_to_cpu(resp->error_code);
4043 netdev_err(bp->dev, "hwrm req_type 0x%x seq id 0x%x error 0x%x\n",
4044 le16_to_cpu(resp->req_type),
4045 le16_to_cpu(resp->seq_id), rc);
4049 int _hwrm_send_message(struct bnxt *bp, void *msg, u32 msg_len, int timeout)
4051 return bnxt_hwrm_do_send_msg(bp, msg, msg_len, timeout, false);
4054 int _hwrm_send_message_silent(struct bnxt *bp, void *msg, u32 msg_len,
4057 return bnxt_hwrm_do_send_msg(bp, msg, msg_len, timeout, true);
4060 int hwrm_send_message(struct bnxt *bp, void *msg, u32 msg_len, int timeout)
4064 mutex_lock(&bp->hwrm_cmd_lock);
4065 rc = _hwrm_send_message(bp, msg, msg_len, timeout);
4066 mutex_unlock(&bp->hwrm_cmd_lock);
4070 int hwrm_send_message_silent(struct bnxt *bp, void *msg, u32 msg_len,
4075 mutex_lock(&bp->hwrm_cmd_lock);
4076 rc = bnxt_hwrm_do_send_msg(bp, msg, msg_len, timeout, true);
4077 mutex_unlock(&bp->hwrm_cmd_lock);
4081 int bnxt_hwrm_func_rgtr_async_events(struct bnxt *bp, unsigned long *bmap,
4084 struct hwrm_func_drv_rgtr_input req = {0};
4085 DECLARE_BITMAP(async_events_bmap, 256);
4086 u32 *events = (u32 *)async_events_bmap;
4089 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_RGTR, -1, -1);
4092 cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_ASYNC_EVENT_FWD);
4094 memset(async_events_bmap, 0, sizeof(async_events_bmap));
4095 for (i = 0; i < ARRAY_SIZE(bnxt_async_events_arr); i++)
4096 __set_bit(bnxt_async_events_arr[i], async_events_bmap);
4098 if (bmap && bmap_size) {
4099 for (i = 0; i < bmap_size; i++) {
4100 if (test_bit(i, bmap))
4101 __set_bit(i, async_events_bmap);
4105 for (i = 0; i < 8; i++)
4106 req.async_event_fwd[i] |= cpu_to_le32(events[i]);
4108 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4111 static int bnxt_hwrm_func_drv_rgtr(struct bnxt *bp)
4113 struct hwrm_func_drv_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
4114 struct hwrm_func_drv_rgtr_input req = {0};
4117 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_RGTR, -1, -1);
4120 cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_OS_TYPE |
4121 FUNC_DRV_RGTR_REQ_ENABLES_VER);
4123 req.os_type = cpu_to_le16(FUNC_DRV_RGTR_REQ_OS_TYPE_LINUX);
4124 req.flags = cpu_to_le32(FUNC_DRV_RGTR_REQ_FLAGS_16BIT_VER_MODE);
4125 req.ver_maj_8b = DRV_VER_MAJ;
4126 req.ver_min_8b = DRV_VER_MIN;
4127 req.ver_upd_8b = DRV_VER_UPD;
4128 req.ver_maj = cpu_to_le16(DRV_VER_MAJ);
4129 req.ver_min = cpu_to_le16(DRV_VER_MIN);
4130 req.ver_upd = cpu_to_le16(DRV_VER_UPD);
4136 memset(data, 0, sizeof(data));
4137 for (i = 0; i < ARRAY_SIZE(bnxt_vf_req_snif); i++) {
4138 u16 cmd = bnxt_vf_req_snif[i];
4139 unsigned int bit, idx;
4143 data[idx] |= 1 << bit;
4146 for (i = 0; i < 8; i++)
4147 req.vf_req_fwd[i] = cpu_to_le32(data[i]);
4150 cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_VF_REQ_FWD);
4153 if (bp->fw_cap & BNXT_FW_CAP_OVS_64BIT_HANDLE)
4154 req.flags |= cpu_to_le32(
4155 FUNC_DRV_RGTR_REQ_FLAGS_FLOW_HANDLE_64BIT_MODE);
4157 mutex_lock(&bp->hwrm_cmd_lock);
4158 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4161 else if (resp->flags &
4162 cpu_to_le32(FUNC_DRV_RGTR_RESP_FLAGS_IF_CHANGE_SUPPORTED))
4163 bp->fw_cap |= BNXT_FW_CAP_IF_CHANGE;
4164 mutex_unlock(&bp->hwrm_cmd_lock);
4168 static int bnxt_hwrm_func_drv_unrgtr(struct bnxt *bp)
4170 struct hwrm_func_drv_unrgtr_input req = {0};
4172 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_UNRGTR, -1, -1);
4173 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4176 static int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, u8 tunnel_type)
4179 struct hwrm_tunnel_dst_port_free_input req = {0};
4181 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_TUNNEL_DST_PORT_FREE, -1, -1);
4182 req.tunnel_type = tunnel_type;
4184 switch (tunnel_type) {
4185 case TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN:
4186 req.tunnel_dst_port_id = bp->vxlan_fw_dst_port_id;
4188 case TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE:
4189 req.tunnel_dst_port_id = bp->nge_fw_dst_port_id;
4195 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4197 netdev_err(bp->dev, "hwrm_tunnel_dst_port_free failed. rc:%d\n",
4202 static int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, __be16 port,
4206 struct hwrm_tunnel_dst_port_alloc_input req = {0};
4207 struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr;
4209 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_TUNNEL_DST_PORT_ALLOC, -1, -1);
4211 req.tunnel_type = tunnel_type;
4212 req.tunnel_dst_port_val = port;
4214 mutex_lock(&bp->hwrm_cmd_lock);
4215 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4217 netdev_err(bp->dev, "hwrm_tunnel_dst_port_alloc failed. rc:%d\n",
4222 switch (tunnel_type) {
4223 case TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN:
4224 bp->vxlan_fw_dst_port_id = resp->tunnel_dst_port_id;
4226 case TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_GENEVE:
4227 bp->nge_fw_dst_port_id = resp->tunnel_dst_port_id;
4234 mutex_unlock(&bp->hwrm_cmd_lock);
4238 static int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp, u16 vnic_id)
4240 struct hwrm_cfa_l2_set_rx_mask_input req = {0};
4241 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
4243 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_SET_RX_MASK, -1, -1);
4244 req.vnic_id = cpu_to_le32(vnic->fw_vnic_id);
4246 req.num_mc_entries = cpu_to_le32(vnic->mc_list_count);
4247 req.mc_tbl_addr = cpu_to_le64(vnic->mc_list_mapping);
4248 req.mask = cpu_to_le32(vnic->rx_mask);
4249 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4252 #ifdef CONFIG_RFS_ACCEL
4253 static int bnxt_hwrm_cfa_ntuple_filter_free(struct bnxt *bp,
4254 struct bnxt_ntuple_filter *fltr)
4256 struct hwrm_cfa_ntuple_filter_free_input req = {0};
4258 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_NTUPLE_FILTER_FREE, -1, -1);
4259 req.ntuple_filter_id = fltr->filter_id;
4260 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4263 #define BNXT_NTP_FLTR_FLAGS \
4264 (CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID | \
4265 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_ETHERTYPE | \
4266 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_MACADDR | \
4267 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IPADDR_TYPE | \
4268 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR | \
4269 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR_MASK | \
4270 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR | \
4271 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR_MASK | \
4272 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IP_PROTOCOL | \
4273 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT | \
4274 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT_MASK | \
4275 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT | \
4276 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT_MASK | \
4277 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_ID)
4279 #define BNXT_NTP_TUNNEL_FLTR_FLAG \
4280 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE
4282 static int bnxt_hwrm_cfa_ntuple_filter_alloc(struct bnxt *bp,
4283 struct bnxt_ntuple_filter *fltr)
4285 struct hwrm_cfa_ntuple_filter_alloc_input req = {0};
4286 struct hwrm_cfa_ntuple_filter_alloc_output *resp;
4287 struct flow_keys *keys = &fltr->fkeys;
4288 struct bnxt_vnic_info *vnic;
4292 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_NTUPLE_FILTER_ALLOC, -1, -1);
4293 req.l2_filter_id = bp->vnic_info[0].fw_l2_filter_id[fltr->l2_fltr_idx];
4295 if (bp->fw_cap & BNXT_FW_CAP_CFA_RFS_RING_TBL_IDX) {
4296 dst_ena = CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_RFS_RING_TBL_IDX;
4297 req.rfs_ring_tbl_idx = cpu_to_le16(fltr->rxq);
4298 vnic = &bp->vnic_info[0];
4300 vnic = &bp->vnic_info[fltr->rxq + 1];
4302 req.dst_id = cpu_to_le16(vnic->fw_vnic_id);
4303 req.enables = cpu_to_le32(BNXT_NTP_FLTR_FLAGS | dst_ena);
4305 req.ethertype = htons(ETH_P_IP);
4306 memcpy(req.src_macaddr, fltr->src_mac_addr, ETH_ALEN);
4307 req.ip_addr_type = CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV4;
4308 req.ip_protocol = keys->basic.ip_proto;
4310 if (keys->basic.n_proto == htons(ETH_P_IPV6)) {
4313 req.ethertype = htons(ETH_P_IPV6);
4315 CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6;
4316 *(struct in6_addr *)&req.src_ipaddr[0] =
4317 keys->addrs.v6addrs.src;
4318 *(struct in6_addr *)&req.dst_ipaddr[0] =
4319 keys->addrs.v6addrs.dst;
4320 for (i = 0; i < 4; i++) {
4321 req.src_ipaddr_mask[i] = cpu_to_be32(0xffffffff);
4322 req.dst_ipaddr_mask[i] = cpu_to_be32(0xffffffff);
4325 req.src_ipaddr[0] = keys->addrs.v4addrs.src;
4326 req.src_ipaddr_mask[0] = cpu_to_be32(0xffffffff);
4327 req.dst_ipaddr[0] = keys->addrs.v4addrs.dst;
4328 req.dst_ipaddr_mask[0] = cpu_to_be32(0xffffffff);
4330 if (keys->control.flags & FLOW_DIS_ENCAPSULATION) {
4331 req.enables |= cpu_to_le32(BNXT_NTP_TUNNEL_FLTR_FLAG);
4333 CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL;
4336 req.src_port = keys->ports.src;
4337 req.src_port_mask = cpu_to_be16(0xffff);
4338 req.dst_port = keys->ports.dst;
4339 req.dst_port_mask = cpu_to_be16(0xffff);
4341 mutex_lock(&bp->hwrm_cmd_lock);
4342 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4344 resp = bnxt_get_hwrm_resp_addr(bp, &req);
4345 fltr->filter_id = resp->ntuple_filter_id;
4347 mutex_unlock(&bp->hwrm_cmd_lock);
4352 static int bnxt_hwrm_set_vnic_filter(struct bnxt *bp, u16 vnic_id, u16 idx,
4356 struct hwrm_cfa_l2_filter_alloc_input req = {0};
4357 struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
4359 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_FILTER_ALLOC, -1, -1);
4360 req.flags = cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX);
4361 if (!BNXT_CHIP_TYPE_NITRO_A0(bp))
4363 cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_FLAGS_OUTERMOST);
4364 req.dst_id = cpu_to_le16(bp->vnic_info[vnic_id].fw_vnic_id);
4366 cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR |
4367 CFA_L2_FILTER_ALLOC_REQ_ENABLES_DST_ID |
4368 CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR_MASK);
4369 memcpy(req.l2_addr, mac_addr, ETH_ALEN);
4370 req.l2_addr_mask[0] = 0xff;
4371 req.l2_addr_mask[1] = 0xff;
4372 req.l2_addr_mask[2] = 0xff;
4373 req.l2_addr_mask[3] = 0xff;
4374 req.l2_addr_mask[4] = 0xff;
4375 req.l2_addr_mask[5] = 0xff;
4377 mutex_lock(&bp->hwrm_cmd_lock);
4378 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4380 bp->vnic_info[vnic_id].fw_l2_filter_id[idx] =
4382 mutex_unlock(&bp->hwrm_cmd_lock);
4386 static int bnxt_hwrm_clear_vnic_filter(struct bnxt *bp)
4388 u16 i, j, num_of_vnics = 1; /* only vnic 0 supported */
4391 /* Any associated ntuple filters will also be cleared by firmware. */
4392 mutex_lock(&bp->hwrm_cmd_lock);
4393 for (i = 0; i < num_of_vnics; i++) {
4394 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
4396 for (j = 0; j < vnic->uc_filter_count; j++) {
4397 struct hwrm_cfa_l2_filter_free_input req = {0};
4399 bnxt_hwrm_cmd_hdr_init(bp, &req,
4400 HWRM_CFA_L2_FILTER_FREE, -1, -1);
4402 req.l2_filter_id = vnic->fw_l2_filter_id[j];
4404 rc = _hwrm_send_message(bp, &req, sizeof(req),
4407 vnic->uc_filter_count = 0;
4409 mutex_unlock(&bp->hwrm_cmd_lock);
4414 static int bnxt_hwrm_vnic_set_tpa(struct bnxt *bp, u16 vnic_id, u32 tpa_flags)
4416 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
4417 struct hwrm_vnic_tpa_cfg_input req = {0};
4419 if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
4422 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_TPA_CFG, -1, -1);
4425 u16 mss = bp->dev->mtu - 40;
4426 u32 nsegs, n, segs = 0, flags;
4428 flags = VNIC_TPA_CFG_REQ_FLAGS_TPA |
4429 VNIC_TPA_CFG_REQ_FLAGS_ENCAP_TPA |
4430 VNIC_TPA_CFG_REQ_FLAGS_RSC_WND_UPDATE |
4431 VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_ECN |
4432 VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_SAME_GRE_SEQ;
4433 if (tpa_flags & BNXT_FLAG_GRO)
4434 flags |= VNIC_TPA_CFG_REQ_FLAGS_GRO;
4436 req.flags = cpu_to_le32(flags);
4439 cpu_to_le32(VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_SEGS |
4440 VNIC_TPA_CFG_REQ_ENABLES_MAX_AGGS |
4441 VNIC_TPA_CFG_REQ_ENABLES_MIN_AGG_LEN);
4443 /* Number of segs are log2 units, and first packet is not
4444 * included as part of this units.
4446 if (mss <= BNXT_RX_PAGE_SIZE) {
4447 n = BNXT_RX_PAGE_SIZE / mss;
4448 nsegs = (MAX_SKB_FRAGS - 1) * n;
4450 n = mss / BNXT_RX_PAGE_SIZE;
4451 if (mss & (BNXT_RX_PAGE_SIZE - 1))
4453 nsegs = (MAX_SKB_FRAGS - n) / n;
4456 segs = ilog2(nsegs);
4457 req.max_agg_segs = cpu_to_le16(segs);
4458 req.max_aggs = cpu_to_le16(VNIC_TPA_CFG_REQ_MAX_AGGS_MAX);
4460 req.min_agg_len = cpu_to_le32(512);
4462 req.vnic_id = cpu_to_le16(vnic->fw_vnic_id);
4464 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4467 static u16 bnxt_cp_ring_from_grp(struct bnxt *bp, struct bnxt_ring_struct *ring)
4469 struct bnxt_ring_grp_info *grp_info;
4471 grp_info = &bp->grp_info[ring->grp_idx];
4472 return grp_info->cp_fw_ring_id;
4475 static u16 bnxt_cp_ring_for_rx(struct bnxt *bp, struct bnxt_rx_ring_info *rxr)
4477 if (bp->flags & BNXT_FLAG_CHIP_P5) {
4478 struct bnxt_napi *bnapi = rxr->bnapi;
4479 struct bnxt_cp_ring_info *cpr;
4481 cpr = bnapi->cp_ring.cp_ring_arr[BNXT_RX_HDL];
4482 return cpr->cp_ring_struct.fw_ring_id;
4484 return bnxt_cp_ring_from_grp(bp, &rxr->rx_ring_struct);
4488 static u16 bnxt_cp_ring_for_tx(struct bnxt *bp, struct bnxt_tx_ring_info *txr)
4490 if (bp->flags & BNXT_FLAG_CHIP_P5) {
4491 struct bnxt_napi *bnapi = txr->bnapi;
4492 struct bnxt_cp_ring_info *cpr;
4494 cpr = bnapi->cp_ring.cp_ring_arr[BNXT_TX_HDL];
4495 return cpr->cp_ring_struct.fw_ring_id;
4497 return bnxt_cp_ring_from_grp(bp, &txr->tx_ring_struct);
4501 static int bnxt_hwrm_vnic_set_rss(struct bnxt *bp, u16 vnic_id, bool set_rss)
4503 u32 i, j, max_rings;
4504 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
4505 struct hwrm_vnic_rss_cfg_input req = {0};
4507 if ((bp->flags & BNXT_FLAG_CHIP_P5) ||
4508 vnic->fw_rss_cos_lb_ctx[0] == INVALID_HW_RING_ID)
4511 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_CFG, -1, -1);
4513 req.hash_type = cpu_to_le32(bp->rss_hash_cfg);
4514 req.hash_mode_flags = VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_DEFAULT;
4515 if (vnic->flags & BNXT_VNIC_RSS_FLAG) {
4516 if (BNXT_CHIP_TYPE_NITRO_A0(bp))
4517 max_rings = bp->rx_nr_rings - 1;
4519 max_rings = bp->rx_nr_rings;
4524 /* Fill the RSS indirection table with ring group ids */
4525 for (i = 0, j = 0; i < HW_HASH_INDEX_SIZE; i++, j++) {
4528 vnic->rss_table[i] = cpu_to_le16(vnic->fw_grp_ids[j]);
4531 req.ring_grp_tbl_addr = cpu_to_le64(vnic->rss_table_dma_addr);
4532 req.hash_key_tbl_addr =
4533 cpu_to_le64(vnic->rss_hash_key_dma_addr);
4535 req.rss_ctx_idx = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[0]);
4536 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4539 static int bnxt_hwrm_vnic_set_rss_p5(struct bnxt *bp, u16 vnic_id, bool set_rss)
4541 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
4542 u32 i, j, k, nr_ctxs, max_rings = bp->rx_nr_rings;
4543 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[0];
4544 struct hwrm_vnic_rss_cfg_input req = {0};
4546 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_CFG, -1, -1);
4547 req.vnic_id = cpu_to_le16(vnic->fw_vnic_id);
4549 hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4552 req.hash_type = cpu_to_le32(bp->rss_hash_cfg);
4553 req.hash_mode_flags = VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_DEFAULT;
4554 req.ring_grp_tbl_addr = cpu_to_le64(vnic->rss_table_dma_addr);
4555 req.hash_key_tbl_addr = cpu_to_le64(vnic->rss_hash_key_dma_addr);
4556 nr_ctxs = DIV_ROUND_UP(bp->rx_nr_rings, 64);
4557 for (i = 0, k = 0; i < nr_ctxs; i++) {
4558 __le16 *ring_tbl = vnic->rss_table;
4561 req.ring_table_pair_index = i;
4562 req.rss_ctx_idx = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[i]);
4563 for (j = 0; j < 64; j++) {
4566 ring_id = rxr->rx_ring_struct.fw_ring_id;
4567 *ring_tbl++ = cpu_to_le16(ring_id);
4568 ring_id = bnxt_cp_ring_for_rx(bp, rxr);
4569 *ring_tbl++ = cpu_to_le16(ring_id);
4572 if (k == max_rings) {
4574 rxr = &bp->rx_ring[0];
4577 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4584 static int bnxt_hwrm_vnic_set_hds(struct bnxt *bp, u16 vnic_id)
4586 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
4587 struct hwrm_vnic_plcmodes_cfg_input req = {0};
4589 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_PLCMODES_CFG, -1, -1);
4590 req.flags = cpu_to_le32(VNIC_PLCMODES_CFG_REQ_FLAGS_JUMBO_PLACEMENT |
4591 VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV4 |
4592 VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV6);
4594 cpu_to_le32(VNIC_PLCMODES_CFG_REQ_ENABLES_JUMBO_THRESH_VALID |
4595 VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_THRESHOLD_VALID);
4596 /* thresholds not implemented in firmware yet */
4597 req.jumbo_thresh = cpu_to_le16(bp->rx_copy_thresh);
4598 req.hds_threshold = cpu_to_le16(bp->rx_copy_thresh);
4599 req.vnic_id = cpu_to_le32(vnic->fw_vnic_id);
4600 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4603 static void bnxt_hwrm_vnic_ctx_free_one(struct bnxt *bp, u16 vnic_id,
4606 struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {0};
4608 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_COS_LB_CTX_FREE, -1, -1);
4609 req.rss_cos_lb_ctx_id =
4610 cpu_to_le16(bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[ctx_idx]);
4612 hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4613 bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[ctx_idx] = INVALID_HW_RING_ID;
4616 static void bnxt_hwrm_vnic_ctx_free(struct bnxt *bp)
4620 for (i = 0; i < bp->nr_vnics; i++) {
4621 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
4623 for (j = 0; j < BNXT_MAX_CTX_PER_VNIC; j++) {
4624 if (vnic->fw_rss_cos_lb_ctx[j] != INVALID_HW_RING_ID)
4625 bnxt_hwrm_vnic_ctx_free_one(bp, i, j);
4628 bp->rsscos_nr_ctxs = 0;
4631 static int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp, u16 vnic_id, u16 ctx_idx)
4634 struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {0};
4635 struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp =
4636 bp->hwrm_cmd_resp_addr;
4638 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_COS_LB_CTX_ALLOC, -1,
4641 mutex_lock(&bp->hwrm_cmd_lock);
4642 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4644 bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[ctx_idx] =
4645 le16_to_cpu(resp->rss_cos_lb_ctx_id);
4646 mutex_unlock(&bp->hwrm_cmd_lock);
4651 static u32 bnxt_get_roce_vnic_mode(struct bnxt *bp)
4653 if (bp->flags & BNXT_FLAG_ROCE_MIRROR_CAP)
4654 return VNIC_CFG_REQ_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_MODE;
4655 return VNIC_CFG_REQ_FLAGS_ROCE_DUAL_VNIC_MODE;
4658 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, u16 vnic_id)
4660 unsigned int ring = 0, grp_idx;
4661 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
4662 struct hwrm_vnic_cfg_input req = {0};
4665 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_CFG, -1, -1);
4667 if (bp->flags & BNXT_FLAG_CHIP_P5) {
4668 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[0];
4670 req.default_rx_ring_id =
4671 cpu_to_le16(rxr->rx_ring_struct.fw_ring_id);
4672 req.default_cmpl_ring_id =
4673 cpu_to_le16(bnxt_cp_ring_for_rx(bp, rxr));
4675 cpu_to_le32(VNIC_CFG_REQ_ENABLES_DEFAULT_RX_RING_ID |
4676 VNIC_CFG_REQ_ENABLES_DEFAULT_CMPL_RING_ID);
4679 req.enables = cpu_to_le32(VNIC_CFG_REQ_ENABLES_DFLT_RING_GRP);
4680 /* Only RSS support for now TBD: COS & LB */
4681 if (vnic->fw_rss_cos_lb_ctx[0] != INVALID_HW_RING_ID) {
4682 req.rss_rule = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[0]);
4683 req.enables |= cpu_to_le32(VNIC_CFG_REQ_ENABLES_RSS_RULE |
4684 VNIC_CFG_REQ_ENABLES_MRU);
4685 } else if (vnic->flags & BNXT_VNIC_RFS_NEW_RSS_FLAG) {
4687 cpu_to_le16(bp->vnic_info[0].fw_rss_cos_lb_ctx[0]);
4688 req.enables |= cpu_to_le32(VNIC_CFG_REQ_ENABLES_RSS_RULE |
4689 VNIC_CFG_REQ_ENABLES_MRU);
4690 req.flags |= cpu_to_le32(VNIC_CFG_REQ_FLAGS_RSS_DFLT_CR_MODE);
4692 req.rss_rule = cpu_to_le16(0xffff);
4695 if (BNXT_CHIP_TYPE_NITRO_A0(bp) &&
4696 (vnic->fw_rss_cos_lb_ctx[0] != INVALID_HW_RING_ID)) {
4697 req.cos_rule = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[1]);
4698 req.enables |= cpu_to_le32(VNIC_CFG_REQ_ENABLES_COS_RULE);
4700 req.cos_rule = cpu_to_le16(0xffff);
4703 if (vnic->flags & BNXT_VNIC_RSS_FLAG)
4705 else if (vnic->flags & BNXT_VNIC_RFS_FLAG)
4707 else if ((vnic_id == 1) && BNXT_CHIP_TYPE_NITRO_A0(bp))
4708 ring = bp->rx_nr_rings - 1;
4710 grp_idx = bp->rx_ring[ring].bnapi->index;
4711 req.dflt_ring_grp = cpu_to_le16(bp->grp_info[grp_idx].fw_grp_id);
4712 req.lb_rule = cpu_to_le16(0xffff);
4714 req.mru = cpu_to_le16(bp->dev->mtu + ETH_HLEN + ETH_FCS_LEN +
4717 req.vnic_id = cpu_to_le16(vnic->fw_vnic_id);
4718 #ifdef CONFIG_BNXT_SRIOV
4720 def_vlan = bp->vf.vlan;
4722 if ((bp->flags & BNXT_FLAG_STRIP_VLAN) || def_vlan)
4723 req.flags |= cpu_to_le32(VNIC_CFG_REQ_FLAGS_VLAN_STRIP_MODE);
4724 if (!vnic_id && bnxt_ulp_registered(bp->edev, BNXT_ROCE_ULP))
4725 req.flags |= cpu_to_le32(bnxt_get_roce_vnic_mode(bp));
4727 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4730 static int bnxt_hwrm_vnic_free_one(struct bnxt *bp, u16 vnic_id)
4734 if (bp->vnic_info[vnic_id].fw_vnic_id != INVALID_HW_RING_ID) {
4735 struct hwrm_vnic_free_input req = {0};
4737 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_FREE, -1, -1);
4739 cpu_to_le32(bp->vnic_info[vnic_id].fw_vnic_id);
4741 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4744 bp->vnic_info[vnic_id].fw_vnic_id = INVALID_HW_RING_ID;
4749 static void bnxt_hwrm_vnic_free(struct bnxt *bp)
4753 for (i = 0; i < bp->nr_vnics; i++)
4754 bnxt_hwrm_vnic_free_one(bp, i);
4757 static int bnxt_hwrm_vnic_alloc(struct bnxt *bp, u16 vnic_id,
4758 unsigned int start_rx_ring_idx,
4759 unsigned int nr_rings)
4762 unsigned int i, j, grp_idx, end_idx = start_rx_ring_idx + nr_rings;
4763 struct hwrm_vnic_alloc_input req = {0};
4764 struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
4765 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
4767 if (bp->flags & BNXT_FLAG_CHIP_P5)
4768 goto vnic_no_ring_grps;
4770 /* map ring groups to this vnic */
4771 for (i = start_rx_ring_idx, j = 0; i < end_idx; i++, j++) {
4772 grp_idx = bp->rx_ring[i].bnapi->index;
4773 if (bp->grp_info[grp_idx].fw_grp_id == INVALID_HW_RING_ID) {
4774 netdev_err(bp->dev, "Not enough ring groups avail:%x req:%x\n",
4778 vnic->fw_grp_ids[j] = bp->grp_info[grp_idx].fw_grp_id;
4782 for (i = 0; i < BNXT_MAX_CTX_PER_VNIC; i++)
4783 vnic->fw_rss_cos_lb_ctx[i] = INVALID_HW_RING_ID;
4785 req.flags = cpu_to_le32(VNIC_ALLOC_REQ_FLAGS_DEFAULT);
4787 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_ALLOC, -1, -1);
4789 mutex_lock(&bp->hwrm_cmd_lock);
4790 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4792 vnic->fw_vnic_id = le32_to_cpu(resp->vnic_id);
4793 mutex_unlock(&bp->hwrm_cmd_lock);
4797 static int bnxt_hwrm_vnic_qcaps(struct bnxt *bp)
4799 struct hwrm_vnic_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
4800 struct hwrm_vnic_qcaps_input req = {0};
4803 if (bp->hwrm_spec_code < 0x10600)
4806 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_QCAPS, -1, -1);
4807 mutex_lock(&bp->hwrm_cmd_lock);
4808 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4810 u32 flags = le32_to_cpu(resp->flags);
4812 if (!(bp->flags & BNXT_FLAG_CHIP_P5) &&
4813 (flags & VNIC_QCAPS_RESP_FLAGS_RSS_DFLT_CR_CAP))
4814 bp->flags |= BNXT_FLAG_NEW_RSS_CAP;
4816 VNIC_QCAPS_RESP_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_CAP)
4817 bp->flags |= BNXT_FLAG_ROCE_MIRROR_CAP;
4819 mutex_unlock(&bp->hwrm_cmd_lock);
4823 static int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp)
4828 if (bp->flags & BNXT_FLAG_CHIP_P5)
4831 mutex_lock(&bp->hwrm_cmd_lock);
4832 for (i = 0; i < bp->rx_nr_rings; i++) {
4833 struct hwrm_ring_grp_alloc_input req = {0};
4834 struct hwrm_ring_grp_alloc_output *resp =
4835 bp->hwrm_cmd_resp_addr;
4836 unsigned int grp_idx = bp->rx_ring[i].bnapi->index;
4838 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_GRP_ALLOC, -1, -1);
4840 req.cr = cpu_to_le16(bp->grp_info[grp_idx].cp_fw_ring_id);
4841 req.rr = cpu_to_le16(bp->grp_info[grp_idx].rx_fw_ring_id);
4842 req.ar = cpu_to_le16(bp->grp_info[grp_idx].agg_fw_ring_id);
4843 req.sc = cpu_to_le16(bp->grp_info[grp_idx].fw_stats_ctx);
4845 rc = _hwrm_send_message(bp, &req, sizeof(req),
4850 bp->grp_info[grp_idx].fw_grp_id =
4851 le32_to_cpu(resp->ring_group_id);
4853 mutex_unlock(&bp->hwrm_cmd_lock);
4857 static int bnxt_hwrm_ring_grp_free(struct bnxt *bp)
4861 struct hwrm_ring_grp_free_input req = {0};
4863 if (!bp->grp_info || (bp->flags & BNXT_FLAG_CHIP_P5))
4866 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_GRP_FREE, -1, -1);
4868 mutex_lock(&bp->hwrm_cmd_lock);
4869 for (i = 0; i < bp->cp_nr_rings; i++) {
4870 if (bp->grp_info[i].fw_grp_id == INVALID_HW_RING_ID)
4873 cpu_to_le32(bp->grp_info[i].fw_grp_id);
4875 rc = _hwrm_send_message(bp, &req, sizeof(req),
4879 bp->grp_info[i].fw_grp_id = INVALID_HW_RING_ID;
4881 mutex_unlock(&bp->hwrm_cmd_lock);
4885 static int hwrm_ring_alloc_send_msg(struct bnxt *bp,
4886 struct bnxt_ring_struct *ring,
4887 u32 ring_type, u32 map_index)
4889 int rc = 0, err = 0;
4890 struct hwrm_ring_alloc_input req = {0};
4891 struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr;
4892 struct bnxt_ring_mem_info *rmem = &ring->ring_mem;
4893 struct bnxt_ring_grp_info *grp_info;
4896 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_ALLOC, -1, -1);
4899 if (rmem->nr_pages > 1) {
4900 req.page_tbl_addr = cpu_to_le64(rmem->pg_tbl_map);
4901 /* Page size is in log2 units */
4902 req.page_size = BNXT_PAGE_SHIFT;
4903 req.page_tbl_depth = 1;
4905 req.page_tbl_addr = cpu_to_le64(rmem->dma_arr[0]);
4908 /* Association of ring index with doorbell index and MSIX number */
4909 req.logical_id = cpu_to_le16(map_index);
4911 switch (ring_type) {
4912 case HWRM_RING_ALLOC_TX: {
4913 struct bnxt_tx_ring_info *txr;
4915 txr = container_of(ring, struct bnxt_tx_ring_info,
4917 req.ring_type = RING_ALLOC_REQ_RING_TYPE_TX;
4918 /* Association of transmit ring with completion ring */
4919 grp_info = &bp->grp_info[ring->grp_idx];
4920 req.cmpl_ring_id = cpu_to_le16(bnxt_cp_ring_for_tx(bp, txr));
4921 req.length = cpu_to_le32(bp->tx_ring_mask + 1);
4922 req.stat_ctx_id = cpu_to_le32(grp_info->fw_stats_ctx);
4923 req.queue_id = cpu_to_le16(ring->queue_id);
4926 case HWRM_RING_ALLOC_RX:
4927 req.ring_type = RING_ALLOC_REQ_RING_TYPE_RX;
4928 req.length = cpu_to_le32(bp->rx_ring_mask + 1);
4929 if (bp->flags & BNXT_FLAG_CHIP_P5) {
4932 /* Association of rx ring with stats context */
4933 grp_info = &bp->grp_info[ring->grp_idx];
4934 req.rx_buf_size = cpu_to_le16(bp->rx_buf_use_size);
4935 req.stat_ctx_id = cpu_to_le32(grp_info->fw_stats_ctx);
4936 req.enables |= cpu_to_le32(
4937 RING_ALLOC_REQ_ENABLES_RX_BUF_SIZE_VALID);
4938 if (NET_IP_ALIGN == 2)
4939 flags = RING_ALLOC_REQ_FLAGS_RX_SOP_PAD;
4940 req.flags = cpu_to_le16(flags);
4943 case HWRM_RING_ALLOC_AGG:
4944 if (bp->flags & BNXT_FLAG_CHIP_P5) {
4945 req.ring_type = RING_ALLOC_REQ_RING_TYPE_RX_AGG;
4946 /* Association of agg ring with rx ring */
4947 grp_info = &bp->grp_info[ring->grp_idx];
4948 req.rx_ring_id = cpu_to_le16(grp_info->rx_fw_ring_id);
4949 req.rx_buf_size = cpu_to_le16(BNXT_RX_PAGE_SIZE);
4950 req.stat_ctx_id = cpu_to_le32(grp_info->fw_stats_ctx);
4951 req.enables |= cpu_to_le32(
4952 RING_ALLOC_REQ_ENABLES_RX_RING_ID_VALID |
4953 RING_ALLOC_REQ_ENABLES_RX_BUF_SIZE_VALID);
4955 req.ring_type = RING_ALLOC_REQ_RING_TYPE_RX;
4957 req.length = cpu_to_le32(bp->rx_agg_ring_mask + 1);
4959 case HWRM_RING_ALLOC_CMPL:
4960 req.ring_type = RING_ALLOC_REQ_RING_TYPE_L2_CMPL;
4961 req.length = cpu_to_le32(bp->cp_ring_mask + 1);
4962 if (bp->flags & BNXT_FLAG_CHIP_P5) {
4963 /* Association of cp ring with nq */
4964 grp_info = &bp->grp_info[map_index];
4965 req.nq_ring_id = cpu_to_le16(grp_info->cp_fw_ring_id);
4966 req.cq_handle = cpu_to_le64(ring->handle);
4967 req.enables |= cpu_to_le32(
4968 RING_ALLOC_REQ_ENABLES_NQ_RING_ID_VALID);
4969 } else if (bp->flags & BNXT_FLAG_USING_MSIX) {
4970 req.int_mode = RING_ALLOC_REQ_INT_MODE_MSIX;
4973 case HWRM_RING_ALLOC_NQ:
4974 req.ring_type = RING_ALLOC_REQ_RING_TYPE_NQ;
4975 req.length = cpu_to_le32(bp->cp_ring_mask + 1);
4976 if (bp->flags & BNXT_FLAG_USING_MSIX)
4977 req.int_mode = RING_ALLOC_REQ_INT_MODE_MSIX;
4980 netdev_err(bp->dev, "hwrm alloc invalid ring type %d\n",
4985 mutex_lock(&bp->hwrm_cmd_lock);
4986 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4987 err = le16_to_cpu(resp->error_code);
4988 ring_id = le16_to_cpu(resp->ring_id);
4989 mutex_unlock(&bp->hwrm_cmd_lock);
4992 netdev_err(bp->dev, "hwrm_ring_alloc type %d failed. rc:%x err:%x\n",
4993 ring_type, rc, err);
4996 ring->fw_ring_id = ring_id;
5000 static int bnxt_hwrm_set_async_event_cr(struct bnxt *bp, int idx)
5005 struct hwrm_func_cfg_input req = {0};
5007 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_CFG, -1, -1);
5008 req.fid = cpu_to_le16(0xffff);
5009 req.enables = cpu_to_le32(FUNC_CFG_REQ_ENABLES_ASYNC_EVENT_CR);
5010 req.async_event_cr = cpu_to_le16(idx);
5011 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5013 struct hwrm_func_vf_cfg_input req = {0};
5015 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_VF_CFG, -1, -1);
5017 cpu_to_le32(FUNC_VF_CFG_REQ_ENABLES_ASYNC_EVENT_CR);
5018 req.async_event_cr = cpu_to_le16(idx);
5019 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5024 static void bnxt_set_db(struct bnxt *bp, struct bnxt_db_info *db, u32 ring_type,
5025 u32 map_idx, u32 xid)
5027 if (bp->flags & BNXT_FLAG_CHIP_P5) {
5029 db->doorbell = bp->bar1 + 0x10000;
5031 db->doorbell = bp->bar1 + 0x4000;
5032 switch (ring_type) {
5033 case HWRM_RING_ALLOC_TX:
5034 db->db_key64 = DBR_PATH_L2 | DBR_TYPE_SQ;
5036 case HWRM_RING_ALLOC_RX:
5037 case HWRM_RING_ALLOC_AGG:
5038 db->db_key64 = DBR_PATH_L2 | DBR_TYPE_SRQ;
5040 case HWRM_RING_ALLOC_CMPL:
5041 db->db_key64 = DBR_PATH_L2;
5043 case HWRM_RING_ALLOC_NQ:
5044 db->db_key64 = DBR_PATH_L2;
5047 db->db_key64 |= (u64)xid << DBR_XID_SFT;
5049 db->doorbell = bp->bar1 + map_idx * 0x80;
5050 switch (ring_type) {
5051 case HWRM_RING_ALLOC_TX:
5052 db->db_key32 = DB_KEY_TX;
5054 case HWRM_RING_ALLOC_RX:
5055 case HWRM_RING_ALLOC_AGG:
5056 db->db_key32 = DB_KEY_RX;
5058 case HWRM_RING_ALLOC_CMPL:
5059 db->db_key32 = DB_KEY_CP;
5065 static int bnxt_hwrm_ring_alloc(struct bnxt *bp)
5070 if (bp->flags & BNXT_FLAG_CHIP_P5)
5071 type = HWRM_RING_ALLOC_NQ;
5073 type = HWRM_RING_ALLOC_CMPL;
5074 for (i = 0; i < bp->cp_nr_rings; i++) {
5075 struct bnxt_napi *bnapi = bp->bnapi[i];
5076 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
5077 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct;
5078 u32 map_idx = ring->map_idx;
5079 unsigned int vector;
5081 vector = bp->irq_tbl[map_idx].vector;
5082 disable_irq_nosync(vector);
5083 rc = hwrm_ring_alloc_send_msg(bp, ring, type, map_idx);
5088 bnxt_set_db(bp, &cpr->cp_db, type, map_idx, ring->fw_ring_id);
5089 bnxt_db_nq(bp, &cpr->cp_db, cpr->cp_raw_cons);
5091 bp->grp_info[i].cp_fw_ring_id = ring->fw_ring_id;
5094 rc = bnxt_hwrm_set_async_event_cr(bp, ring->fw_ring_id);
5096 netdev_warn(bp->dev, "Failed to set async event completion ring.\n");
5100 type = HWRM_RING_ALLOC_TX;
5101 for (i = 0; i < bp->tx_nr_rings; i++) {
5102 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
5103 struct bnxt_ring_struct *ring;
5106 if (bp->flags & BNXT_FLAG_CHIP_P5) {
5107 struct bnxt_napi *bnapi = txr->bnapi;
5108 struct bnxt_cp_ring_info *cpr, *cpr2;
5109 u32 type2 = HWRM_RING_ALLOC_CMPL;
5111 cpr = &bnapi->cp_ring;
5112 cpr2 = cpr->cp_ring_arr[BNXT_TX_HDL];
5113 ring = &cpr2->cp_ring_struct;
5114 ring->handle = BNXT_TX_HDL;
5115 map_idx = bnapi->index;
5116 rc = hwrm_ring_alloc_send_msg(bp, ring, type2, map_idx);
5119 bnxt_set_db(bp, &cpr2->cp_db, type2, map_idx,
5121 bnxt_db_cq(bp, &cpr2->cp_db, cpr2->cp_raw_cons);
5123 ring = &txr->tx_ring_struct;
5125 rc = hwrm_ring_alloc_send_msg(bp, ring, type, map_idx);
5128 bnxt_set_db(bp, &txr->tx_db, type, map_idx, ring->fw_ring_id);
5131 type = HWRM_RING_ALLOC_RX;
5132 for (i = 0; i < bp->rx_nr_rings; i++) {
5133 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
5134 struct bnxt_ring_struct *ring = &rxr->rx_ring_struct;
5135 struct bnxt_napi *bnapi = rxr->bnapi;
5136 u32 map_idx = bnapi->index;
5138 rc = hwrm_ring_alloc_send_msg(bp, ring, type, map_idx);
5141 bnxt_set_db(bp, &rxr->rx_db, type, map_idx, ring->fw_ring_id);
5142 bnxt_db_write(bp, &rxr->rx_db, rxr->rx_prod);
5143 bp->grp_info[map_idx].rx_fw_ring_id = ring->fw_ring_id;
5144 if (bp->flags & BNXT_FLAG_CHIP_P5) {
5145 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
5146 u32 type2 = HWRM_RING_ALLOC_CMPL;
5147 struct bnxt_cp_ring_info *cpr2;
5149 cpr2 = cpr->cp_ring_arr[BNXT_RX_HDL];
5150 ring = &cpr2->cp_ring_struct;
5151 ring->handle = BNXT_RX_HDL;
5152 rc = hwrm_ring_alloc_send_msg(bp, ring, type2, map_idx);
5155 bnxt_set_db(bp, &cpr2->cp_db, type2, map_idx,
5157 bnxt_db_cq(bp, &cpr2->cp_db, cpr2->cp_raw_cons);
5161 if (bp->flags & BNXT_FLAG_AGG_RINGS) {
5162 type = HWRM_RING_ALLOC_AGG;
5163 for (i = 0; i < bp->rx_nr_rings; i++) {
5164 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
5165 struct bnxt_ring_struct *ring =
5166 &rxr->rx_agg_ring_struct;
5167 u32 grp_idx = ring->grp_idx;
5168 u32 map_idx = grp_idx + bp->rx_nr_rings;
5170 rc = hwrm_ring_alloc_send_msg(bp, ring, type, map_idx);
5174 bnxt_set_db(bp, &rxr->rx_agg_db, type, map_idx,
5176 bnxt_db_write(bp, &rxr->rx_agg_db, rxr->rx_agg_prod);
5177 bp->grp_info[grp_idx].agg_fw_ring_id = ring->fw_ring_id;
5184 static int hwrm_ring_free_send_msg(struct bnxt *bp,
5185 struct bnxt_ring_struct *ring,
5186 u32 ring_type, int cmpl_ring_id)
5189 struct hwrm_ring_free_input req = {0};
5190 struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;
5193 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_FREE, cmpl_ring_id, -1);
5194 req.ring_type = ring_type;
5195 req.ring_id = cpu_to_le16(ring->fw_ring_id);
5197 mutex_lock(&bp->hwrm_cmd_lock);
5198 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5199 error_code = le16_to_cpu(resp->error_code);
5200 mutex_unlock(&bp->hwrm_cmd_lock);
5202 if (rc || error_code) {
5203 netdev_err(bp->dev, "hwrm_ring_free type %d failed. rc:%x err:%x\n",
5204 ring_type, rc, error_code);
5210 static void bnxt_hwrm_ring_free(struct bnxt *bp, bool close_path)
5218 for (i = 0; i < bp->tx_nr_rings; i++) {
5219 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
5220 struct bnxt_ring_struct *ring = &txr->tx_ring_struct;
5222 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
5223 u32 cmpl_ring_id = bnxt_cp_ring_for_tx(bp, txr);
5225 hwrm_ring_free_send_msg(bp, ring,
5226 RING_FREE_REQ_RING_TYPE_TX,
5227 close_path ? cmpl_ring_id :
5228 INVALID_HW_RING_ID);
5229 ring->fw_ring_id = INVALID_HW_RING_ID;
5233 for (i = 0; i < bp->rx_nr_rings; i++) {
5234 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
5235 struct bnxt_ring_struct *ring = &rxr->rx_ring_struct;
5236 u32 grp_idx = rxr->bnapi->index;
5238 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
5239 u32 cmpl_ring_id = bnxt_cp_ring_for_rx(bp, rxr);
5241 hwrm_ring_free_send_msg(bp, ring,
5242 RING_FREE_REQ_RING_TYPE_RX,
5243 close_path ? cmpl_ring_id :
5244 INVALID_HW_RING_ID);
5245 ring->fw_ring_id = INVALID_HW_RING_ID;
5246 bp->grp_info[grp_idx].rx_fw_ring_id =
5251 if (bp->flags & BNXT_FLAG_CHIP_P5)
5252 type = RING_FREE_REQ_RING_TYPE_RX_AGG;
5254 type = RING_FREE_REQ_RING_TYPE_RX;
5255 for (i = 0; i < bp->rx_nr_rings; i++) {
5256 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
5257 struct bnxt_ring_struct *ring = &rxr->rx_agg_ring_struct;
5258 u32 grp_idx = rxr->bnapi->index;
5260 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
5261 u32 cmpl_ring_id = bnxt_cp_ring_for_rx(bp, rxr);
5263 hwrm_ring_free_send_msg(bp, ring, type,
5264 close_path ? cmpl_ring_id :
5265 INVALID_HW_RING_ID);
5266 ring->fw_ring_id = INVALID_HW_RING_ID;
5267 bp->grp_info[grp_idx].agg_fw_ring_id =
5272 /* The completion rings are about to be freed. After that the
5273 * IRQ doorbell will not work anymore. So we need to disable
5276 bnxt_disable_int_sync(bp);
5278 if (bp->flags & BNXT_FLAG_CHIP_P5)
5279 type = RING_FREE_REQ_RING_TYPE_NQ;
5281 type = RING_FREE_REQ_RING_TYPE_L2_CMPL;
5282 for (i = 0; i < bp->cp_nr_rings; i++) {
5283 struct bnxt_napi *bnapi = bp->bnapi[i];
5284 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
5285 struct bnxt_ring_struct *ring;
5288 for (j = 0; j < 2; j++) {
5289 struct bnxt_cp_ring_info *cpr2 = cpr->cp_ring_arr[j];
5292 ring = &cpr2->cp_ring_struct;
5293 if (ring->fw_ring_id == INVALID_HW_RING_ID)
5295 hwrm_ring_free_send_msg(bp, ring,
5296 RING_FREE_REQ_RING_TYPE_L2_CMPL,
5297 INVALID_HW_RING_ID);
5298 ring->fw_ring_id = INVALID_HW_RING_ID;
5301 ring = &cpr->cp_ring_struct;
5302 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
5303 hwrm_ring_free_send_msg(bp, ring, type,
5304 INVALID_HW_RING_ID);
5305 ring->fw_ring_id = INVALID_HW_RING_ID;
5306 bp->grp_info[i].cp_fw_ring_id = INVALID_HW_RING_ID;
5311 static int bnxt_trim_rings(struct bnxt *bp, int *rx, int *tx, int max,
5314 static int bnxt_hwrm_get_rings(struct bnxt *bp)
5316 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
5317 struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
5318 struct hwrm_func_qcfg_input req = {0};
5321 if (bp->hwrm_spec_code < 0x10601)
5324 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCFG, -1, -1);
5325 req.fid = cpu_to_le16(0xffff);
5326 mutex_lock(&bp->hwrm_cmd_lock);
5327 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5329 mutex_unlock(&bp->hwrm_cmd_lock);
5333 hw_resc->resv_tx_rings = le16_to_cpu(resp->alloc_tx_rings);
5334 if (BNXT_NEW_RM(bp)) {
5337 hw_resc->resv_rx_rings = le16_to_cpu(resp->alloc_rx_rings);
5338 hw_resc->resv_hw_ring_grps =
5339 le32_to_cpu(resp->alloc_hw_ring_grps);
5340 hw_resc->resv_vnics = le16_to_cpu(resp->alloc_vnics);
5341 cp = le16_to_cpu(resp->alloc_cmpl_rings);
5342 stats = le16_to_cpu(resp->alloc_stat_ctx);
5343 hw_resc->resv_irqs = cp;
5344 if (bp->flags & BNXT_FLAG_CHIP_P5) {
5345 int rx = hw_resc->resv_rx_rings;
5346 int tx = hw_resc->resv_tx_rings;
5348 if (bp->flags & BNXT_FLAG_AGG_RINGS)
5350 if (cp < (rx + tx)) {
5351 bnxt_trim_rings(bp, &rx, &tx, cp, false);
5352 if (bp->flags & BNXT_FLAG_AGG_RINGS)
5354 hw_resc->resv_rx_rings = rx;
5355 hw_resc->resv_tx_rings = tx;
5357 hw_resc->resv_irqs = le16_to_cpu(resp->alloc_msix);
5358 hw_resc->resv_hw_ring_grps = rx;
5360 hw_resc->resv_cp_rings = cp;
5361 hw_resc->resv_stat_ctxs = stats;
5363 mutex_unlock(&bp->hwrm_cmd_lock);
5367 /* Caller must hold bp->hwrm_cmd_lock */
5368 int __bnxt_hwrm_get_tx_rings(struct bnxt *bp, u16 fid, int *tx_rings)
5370 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
5371 struct hwrm_func_qcfg_input req = {0};
5374 if (bp->hwrm_spec_code < 0x10601)
5377 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCFG, -1, -1);
5378 req.fid = cpu_to_le16(fid);
5379 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5381 *tx_rings = le16_to_cpu(resp->alloc_tx_rings);
5386 static bool bnxt_rfs_supported(struct bnxt *bp);
5389 __bnxt_hwrm_reserve_pf_rings(struct bnxt *bp, struct hwrm_func_cfg_input *req,
5390 int tx_rings, int rx_rings, int ring_grps,
5391 int cp_rings, int stats, int vnics)
5395 bnxt_hwrm_cmd_hdr_init(bp, req, HWRM_FUNC_CFG, -1, -1);
5396 req->fid = cpu_to_le16(0xffff);
5397 enables |= tx_rings ? FUNC_CFG_REQ_ENABLES_NUM_TX_RINGS : 0;
5398 req->num_tx_rings = cpu_to_le16(tx_rings);
5399 if (BNXT_NEW_RM(bp)) {
5400 enables |= rx_rings ? FUNC_CFG_REQ_ENABLES_NUM_RX_RINGS : 0;
5401 enables |= stats ? FUNC_CFG_REQ_ENABLES_NUM_STAT_CTXS : 0;
5402 if (bp->flags & BNXT_FLAG_CHIP_P5) {
5403 enables |= cp_rings ? FUNC_CFG_REQ_ENABLES_NUM_MSIX : 0;
5404 enables |= tx_rings + ring_grps ?
5405 FUNC_CFG_REQ_ENABLES_NUM_CMPL_RINGS : 0;
5406 enables |= rx_rings ?
5407 FUNC_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS : 0;
5409 enables |= cp_rings ?
5410 FUNC_CFG_REQ_ENABLES_NUM_CMPL_RINGS : 0;
5411 enables |= ring_grps ?
5412 FUNC_CFG_REQ_ENABLES_NUM_HW_RING_GRPS |
5413 FUNC_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS : 0;
5415 enables |= vnics ? FUNC_CFG_REQ_ENABLES_NUM_VNICS : 0;
5417 req->num_rx_rings = cpu_to_le16(rx_rings);
5418 if (bp->flags & BNXT_FLAG_CHIP_P5) {
5419 req->num_cmpl_rings = cpu_to_le16(tx_rings + ring_grps);
5420 req->num_msix = cpu_to_le16(cp_rings);
5421 req->num_rsscos_ctxs =
5422 cpu_to_le16(DIV_ROUND_UP(ring_grps, 64));
5424 req->num_cmpl_rings = cpu_to_le16(cp_rings);
5425 req->num_hw_ring_grps = cpu_to_le16(ring_grps);
5426 req->num_rsscos_ctxs = cpu_to_le16(1);
5427 if (!(bp->flags & BNXT_FLAG_NEW_RSS_CAP) &&
5428 bnxt_rfs_supported(bp))
5429 req->num_rsscos_ctxs =
5430 cpu_to_le16(ring_grps + 1);
5432 req->num_stat_ctxs = cpu_to_le16(stats);
5433 req->num_vnics = cpu_to_le16(vnics);
5435 req->enables = cpu_to_le32(enables);
5439 __bnxt_hwrm_reserve_vf_rings(struct bnxt *bp,
5440 struct hwrm_func_vf_cfg_input *req, int tx_rings,
5441 int rx_rings, int ring_grps, int cp_rings,
5442 int stats, int vnics)
5446 bnxt_hwrm_cmd_hdr_init(bp, req, HWRM_FUNC_VF_CFG, -1, -1);
5447 enables |= tx_rings ? FUNC_VF_CFG_REQ_ENABLES_NUM_TX_RINGS : 0;
5448 enables |= rx_rings ? FUNC_VF_CFG_REQ_ENABLES_NUM_RX_RINGS |
5449 FUNC_VF_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS : 0;
5450 enables |= stats ? FUNC_VF_CFG_REQ_ENABLES_NUM_STAT_CTXS : 0;
5451 if (bp->flags & BNXT_FLAG_CHIP_P5) {
5452 enables |= tx_rings + ring_grps ?
5453 FUNC_VF_CFG_REQ_ENABLES_NUM_CMPL_RINGS : 0;
5455 enables |= cp_rings ?
5456 FUNC_VF_CFG_REQ_ENABLES_NUM_CMPL_RINGS : 0;
5457 enables |= ring_grps ?
5458 FUNC_VF_CFG_REQ_ENABLES_NUM_HW_RING_GRPS : 0;
5460 enables |= vnics ? FUNC_VF_CFG_REQ_ENABLES_NUM_VNICS : 0;
5461 enables |= FUNC_VF_CFG_REQ_ENABLES_NUM_L2_CTXS;
5463 req->num_l2_ctxs = cpu_to_le16(BNXT_VF_MAX_L2_CTX);
5464 req->num_tx_rings = cpu_to_le16(tx_rings);
5465 req->num_rx_rings = cpu_to_le16(rx_rings);
5466 if (bp->flags & BNXT_FLAG_CHIP_P5) {
5467 req->num_cmpl_rings = cpu_to_le16(tx_rings + ring_grps);
5468 req->num_rsscos_ctxs = cpu_to_le16(DIV_ROUND_UP(ring_grps, 64));
5470 req->num_cmpl_rings = cpu_to_le16(cp_rings);
5471 req->num_hw_ring_grps = cpu_to_le16(ring_grps);
5472 req->num_rsscos_ctxs = cpu_to_le16(BNXT_VF_MAX_RSS_CTX);
5474 req->num_stat_ctxs = cpu_to_le16(stats);
5475 req->num_vnics = cpu_to_le16(vnics);
5477 req->enables = cpu_to_le32(enables);
5481 bnxt_hwrm_reserve_pf_rings(struct bnxt *bp, int tx_rings, int rx_rings,
5482 int ring_grps, int cp_rings, int stats, int vnics)
5484 struct hwrm_func_cfg_input req = {0};
5487 __bnxt_hwrm_reserve_pf_rings(bp, &req, tx_rings, rx_rings, ring_grps,
5488 cp_rings, stats, vnics);
5492 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5496 if (bp->hwrm_spec_code < 0x10601)
5497 bp->hw_resc.resv_tx_rings = tx_rings;
5499 rc = bnxt_hwrm_get_rings(bp);
5504 bnxt_hwrm_reserve_vf_rings(struct bnxt *bp, int tx_rings, int rx_rings,
5505 int ring_grps, int cp_rings, int stats, int vnics)
5507 struct hwrm_func_vf_cfg_input req = {0};
5510 if (!BNXT_NEW_RM(bp)) {
5511 bp->hw_resc.resv_tx_rings = tx_rings;
5515 __bnxt_hwrm_reserve_vf_rings(bp, &req, tx_rings, rx_rings, ring_grps,
5516 cp_rings, stats, vnics);
5517 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5521 rc = bnxt_hwrm_get_rings(bp);
5525 static int bnxt_hwrm_reserve_rings(struct bnxt *bp, int tx, int rx, int grp,
5526 int cp, int stat, int vnic)
5529 return bnxt_hwrm_reserve_pf_rings(bp, tx, rx, grp, cp, stat,
5532 return bnxt_hwrm_reserve_vf_rings(bp, tx, rx, grp, cp, stat,
5536 int bnxt_nq_rings_in_use(struct bnxt *bp)
5538 int cp = bp->cp_nr_rings;
5539 int ulp_msix, ulp_base;
5541 ulp_msix = bnxt_get_ulp_msix_num(bp);
5543 ulp_base = bnxt_get_ulp_msix_base(bp);
5545 if ((ulp_base + ulp_msix) > cp)
5546 cp = ulp_base + ulp_msix;
5551 static int bnxt_cp_rings_in_use(struct bnxt *bp)
5555 if (!(bp->flags & BNXT_FLAG_CHIP_P5))
5556 return bnxt_nq_rings_in_use(bp);
5558 cp = bp->tx_nr_rings + bp->rx_nr_rings;
5562 static int bnxt_get_func_stat_ctxs(struct bnxt *bp)
5564 int ulp_stat = bnxt_get_ulp_stat_ctxs(bp);
5565 int cp = bp->cp_nr_rings;
5570 if (bnxt_nq_rings_in_use(bp) > cp + bnxt_get_ulp_msix_num(bp))
5571 return bnxt_get_ulp_msix_base(bp) + ulp_stat;
5573 return cp + ulp_stat;
5576 static bool bnxt_need_reserve_rings(struct bnxt *bp)
5578 struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
5579 int cp = bnxt_cp_rings_in_use(bp);
5580 int nq = bnxt_nq_rings_in_use(bp);
5581 int rx = bp->rx_nr_rings, stat;
5582 int vnic = 1, grp = rx;
5584 if (bp->hwrm_spec_code < 0x10601)
5587 if (hw_resc->resv_tx_rings != bp->tx_nr_rings)
5590 if ((bp->flags & BNXT_FLAG_RFS) && !(bp->flags & BNXT_FLAG_CHIP_P5))
5592 if (bp->flags & BNXT_FLAG_AGG_RINGS)
5594 stat = bnxt_get_func_stat_ctxs(bp);
5595 if (BNXT_NEW_RM(bp) &&
5596 (hw_resc->resv_rx_rings != rx || hw_resc->resv_cp_rings != cp ||
5597 hw_resc->resv_vnics != vnic || hw_resc->resv_stat_ctxs != stat ||
5598 (hw_resc->resv_hw_ring_grps != grp &&
5599 !(bp->flags & BNXT_FLAG_CHIP_P5))))
5601 if ((bp->flags & BNXT_FLAG_CHIP_P5) && BNXT_PF(bp) &&
5602 hw_resc->resv_irqs != nq)
5607 static int __bnxt_reserve_rings(struct bnxt *bp)
5609 struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
5610 int cp = bnxt_nq_rings_in_use(bp);
5611 int tx = bp->tx_nr_rings;
5612 int rx = bp->rx_nr_rings;
5613 int grp, rx_rings, rc;
5617 if (!bnxt_need_reserve_rings(bp))
5620 if (bp->flags & BNXT_FLAG_SHARED_RINGS)
5622 if ((bp->flags & BNXT_FLAG_RFS) && !(bp->flags & BNXT_FLAG_CHIP_P5))
5624 if (bp->flags & BNXT_FLAG_AGG_RINGS)
5626 grp = bp->rx_nr_rings;
5627 stat = bnxt_get_func_stat_ctxs(bp);
5629 rc = bnxt_hwrm_reserve_rings(bp, tx, rx, grp, cp, stat, vnic);
5633 tx = hw_resc->resv_tx_rings;
5634 if (BNXT_NEW_RM(bp)) {
5635 rx = hw_resc->resv_rx_rings;
5636 cp = hw_resc->resv_irqs;
5637 grp = hw_resc->resv_hw_ring_grps;
5638 vnic = hw_resc->resv_vnics;
5639 stat = hw_resc->resv_stat_ctxs;
5643 if (bp->flags & BNXT_FLAG_AGG_RINGS) {
5647 if (netif_running(bp->dev))
5650 bp->flags &= ~BNXT_FLAG_AGG_RINGS;
5651 bp->flags |= BNXT_FLAG_NO_AGG_RINGS;
5652 bp->dev->hw_features &= ~NETIF_F_LRO;
5653 bp->dev->features &= ~NETIF_F_LRO;
5654 bnxt_set_ring_params(bp);
5657 rx_rings = min_t(int, rx_rings, grp);
5658 cp = min_t(int, cp, bp->cp_nr_rings);
5659 if (stat > bnxt_get_ulp_stat_ctxs(bp))
5660 stat -= bnxt_get_ulp_stat_ctxs(bp);
5661 cp = min_t(int, cp, stat);
5662 rc = bnxt_trim_rings(bp, &rx_rings, &tx, cp, sh);
5663 if (bp->flags & BNXT_FLAG_AGG_RINGS)
5665 cp = sh ? max_t(int, tx, rx_rings) : tx + rx_rings;
5666 bp->tx_nr_rings = tx;
5667 bp->rx_nr_rings = rx_rings;
5668 bp->cp_nr_rings = cp;
5670 if (!tx || !rx || !cp || !grp || !vnic || !stat)
5676 static int bnxt_hwrm_check_vf_rings(struct bnxt *bp, int tx_rings, int rx_rings,
5677 int ring_grps, int cp_rings, int stats,
5680 struct hwrm_func_vf_cfg_input req = {0};
5684 if (!BNXT_NEW_RM(bp))
5687 __bnxt_hwrm_reserve_vf_rings(bp, &req, tx_rings, rx_rings, ring_grps,
5688 cp_rings, stats, vnics);
5689 flags = FUNC_VF_CFG_REQ_FLAGS_TX_ASSETS_TEST |
5690 FUNC_VF_CFG_REQ_FLAGS_RX_ASSETS_TEST |
5691 FUNC_VF_CFG_REQ_FLAGS_CMPL_ASSETS_TEST |
5692 FUNC_VF_CFG_REQ_FLAGS_STAT_CTX_ASSETS_TEST |
5693 FUNC_VF_CFG_REQ_FLAGS_VNIC_ASSETS_TEST |
5694 FUNC_VF_CFG_REQ_FLAGS_RSSCOS_CTX_ASSETS_TEST;
5695 if (!(bp->flags & BNXT_FLAG_CHIP_P5))
5696 flags |= FUNC_VF_CFG_REQ_FLAGS_RING_GRP_ASSETS_TEST;
5698 req.flags = cpu_to_le32(flags);
5699 rc = hwrm_send_message_silent(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5705 static int bnxt_hwrm_check_pf_rings(struct bnxt *bp, int tx_rings, int rx_rings,
5706 int ring_grps, int cp_rings, int stats,
5709 struct hwrm_func_cfg_input req = {0};
5713 __bnxt_hwrm_reserve_pf_rings(bp, &req, tx_rings, rx_rings, ring_grps,
5714 cp_rings, stats, vnics);
5715 flags = FUNC_CFG_REQ_FLAGS_TX_ASSETS_TEST;
5716 if (BNXT_NEW_RM(bp)) {
5717 flags |= FUNC_CFG_REQ_FLAGS_RX_ASSETS_TEST |
5718 FUNC_CFG_REQ_FLAGS_CMPL_ASSETS_TEST |
5719 FUNC_CFG_REQ_FLAGS_STAT_CTX_ASSETS_TEST |
5720 FUNC_CFG_REQ_FLAGS_VNIC_ASSETS_TEST;
5721 if (bp->flags & BNXT_FLAG_CHIP_P5)
5722 flags |= FUNC_CFG_REQ_FLAGS_RSSCOS_CTX_ASSETS_TEST |
5723 FUNC_CFG_REQ_FLAGS_NQ_ASSETS_TEST;
5725 flags |= FUNC_CFG_REQ_FLAGS_RING_GRP_ASSETS_TEST;
5728 req.flags = cpu_to_le32(flags);
5729 rc = hwrm_send_message_silent(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5735 static int bnxt_hwrm_check_rings(struct bnxt *bp, int tx_rings, int rx_rings,
5736 int ring_grps, int cp_rings, int stats,
5739 if (bp->hwrm_spec_code < 0x10801)
5743 return bnxt_hwrm_check_pf_rings(bp, tx_rings, rx_rings,
5744 ring_grps, cp_rings, stats,
5747 return bnxt_hwrm_check_vf_rings(bp, tx_rings, rx_rings, ring_grps,
5748 cp_rings, stats, vnics);
5751 static void bnxt_hwrm_coal_params_qcaps(struct bnxt *bp)
5753 struct hwrm_ring_aggint_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
5754 struct bnxt_coal_cap *coal_cap = &bp->coal_cap;
5755 struct hwrm_ring_aggint_qcaps_input req = {0};
5758 coal_cap->cmpl_params = BNXT_LEGACY_COAL_CMPL_PARAMS;
5759 coal_cap->num_cmpl_dma_aggr_max = 63;
5760 coal_cap->num_cmpl_dma_aggr_during_int_max = 63;
5761 coal_cap->cmpl_aggr_dma_tmr_max = 65535;
5762 coal_cap->cmpl_aggr_dma_tmr_during_int_max = 65535;
5763 coal_cap->int_lat_tmr_min_max = 65535;
5764 coal_cap->int_lat_tmr_max_max = 65535;
5765 coal_cap->num_cmpl_aggr_int_max = 65535;
5766 coal_cap->timer_units = 80;
5768 if (bp->hwrm_spec_code < 0x10902)
5771 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_AGGINT_QCAPS, -1, -1);
5772 mutex_lock(&bp->hwrm_cmd_lock);
5773 rc = _hwrm_send_message_silent(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5775 coal_cap->cmpl_params = le32_to_cpu(resp->cmpl_params);
5776 coal_cap->nq_params = le32_to_cpu(resp->nq_params);
5777 coal_cap->num_cmpl_dma_aggr_max =
5778 le16_to_cpu(resp->num_cmpl_dma_aggr_max);
5779 coal_cap->num_cmpl_dma_aggr_during_int_max =
5780 le16_to_cpu(resp->num_cmpl_dma_aggr_during_int_max);
5781 coal_cap->cmpl_aggr_dma_tmr_max =
5782 le16_to_cpu(resp->cmpl_aggr_dma_tmr_max);
5783 coal_cap->cmpl_aggr_dma_tmr_during_int_max =
5784 le16_to_cpu(resp->cmpl_aggr_dma_tmr_during_int_max);
5785 coal_cap->int_lat_tmr_min_max =
5786 le16_to_cpu(resp->int_lat_tmr_min_max);
5787 coal_cap->int_lat_tmr_max_max =
5788 le16_to_cpu(resp->int_lat_tmr_max_max);
5789 coal_cap->num_cmpl_aggr_int_max =
5790 le16_to_cpu(resp->num_cmpl_aggr_int_max);
5791 coal_cap->timer_units = le16_to_cpu(resp->timer_units);
5793 mutex_unlock(&bp->hwrm_cmd_lock);
5796 static u16 bnxt_usec_to_coal_tmr(struct bnxt *bp, u16 usec)
5798 struct bnxt_coal_cap *coal_cap = &bp->coal_cap;
5800 return usec * 1000 / coal_cap->timer_units;
5803 static void bnxt_hwrm_set_coal_params(struct bnxt *bp,
5804 struct bnxt_coal *hw_coal,
5805 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *req)
5807 struct bnxt_coal_cap *coal_cap = &bp->coal_cap;
5808 u32 cmpl_params = coal_cap->cmpl_params;
5809 u16 val, tmr, max, flags = 0;
5811 max = hw_coal->bufs_per_record * 128;
5812 if (hw_coal->budget)
5813 max = hw_coal->bufs_per_record * hw_coal->budget;
5814 max = min_t(u16, max, coal_cap->num_cmpl_aggr_int_max);
5816 val = clamp_t(u16, hw_coal->coal_bufs, 1, max);
5817 req->num_cmpl_aggr_int = cpu_to_le16(val);
5819 val = min_t(u16, val, coal_cap->num_cmpl_dma_aggr_max);
5820 req->num_cmpl_dma_aggr = cpu_to_le16(val);
5822 val = clamp_t(u16, hw_coal->coal_bufs_irq, 1,
5823 coal_cap->num_cmpl_dma_aggr_during_int_max);
5824 req->num_cmpl_dma_aggr_during_int = cpu_to_le16(val);
5826 tmr = bnxt_usec_to_coal_tmr(bp, hw_coal->coal_ticks);
5827 tmr = clamp_t(u16, tmr, 1, coal_cap->int_lat_tmr_max_max);
5828 req->int_lat_tmr_max = cpu_to_le16(tmr);
5830 /* min timer set to 1/2 of interrupt timer */
5831 if (cmpl_params & RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_INT_LAT_TMR_MIN) {
5833 val = clamp_t(u16, val, 1, coal_cap->int_lat_tmr_min_max);
5834 req->int_lat_tmr_min = cpu_to_le16(val);
5835 req->enables |= cpu_to_le16(BNXT_COAL_CMPL_MIN_TMR_ENABLE);
5838 /* buf timer set to 1/4 of interrupt timer */
5839 val = clamp_t(u16, tmr / 4, 1, coal_cap->cmpl_aggr_dma_tmr_max);
5840 req->cmpl_aggr_dma_tmr = cpu_to_le16(val);
5843 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_DMA_AGGR_DURING_INT) {
5844 tmr = bnxt_usec_to_coal_tmr(bp, hw_coal->coal_ticks_irq);
5845 val = clamp_t(u16, tmr, 1,
5846 coal_cap->cmpl_aggr_dma_tmr_during_int_max);
5847 req->cmpl_aggr_dma_tmr_during_int = cpu_to_le16(tmr);
5849 cpu_to_le16(BNXT_COAL_CMPL_AGGR_TMR_DURING_INT_ENABLE);
5852 if (cmpl_params & RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_TIMER_RESET)
5853 flags |= RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET;
5854 if ((cmpl_params & RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_RING_IDLE) &&
5855 hw_coal->idle_thresh && hw_coal->coal_ticks < hw_coal->idle_thresh)
5856 flags |= RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_RING_IDLE;
5857 req->flags = cpu_to_le16(flags);
5858 req->enables |= cpu_to_le16(BNXT_COAL_CMPL_ENABLES);
5861 /* Caller holds bp->hwrm_cmd_lock */
5862 static int __bnxt_hwrm_set_coal_nq(struct bnxt *bp, struct bnxt_napi *bnapi,
5863 struct bnxt_coal *hw_coal)
5865 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req = {0};
5866 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
5867 struct bnxt_coal_cap *coal_cap = &bp->coal_cap;
5868 u32 nq_params = coal_cap->nq_params;
5871 if (!(nq_params & RING_AGGINT_QCAPS_RESP_NQ_PARAMS_INT_LAT_TMR_MIN))
5874 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS,
5876 req.ring_id = cpu_to_le16(cpr->cp_ring_struct.fw_ring_id);
5878 cpu_to_le16(RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_IS_NQ);
5880 tmr = bnxt_usec_to_coal_tmr(bp, hw_coal->coal_ticks) / 2;
5881 tmr = clamp_t(u16, tmr, 1, coal_cap->int_lat_tmr_min_max);
5882 req.int_lat_tmr_min = cpu_to_le16(tmr);
5883 req.enables |= cpu_to_le16(BNXT_COAL_CMPL_MIN_TMR_ENABLE);
5884 return _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5887 int bnxt_hwrm_set_ring_coal(struct bnxt *bp, struct bnxt_napi *bnapi)
5889 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req_rx = {0};
5890 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
5891 struct bnxt_coal coal;
5893 /* Tick values in micro seconds.
5894 * 1 coal_buf x bufs_per_record = 1 completion record.
5896 memcpy(&coal, &bp->rx_coal, sizeof(struct bnxt_coal));
5898 coal.coal_ticks = cpr->rx_ring_coal.coal_ticks;
5899 coal.coal_bufs = cpr->rx_ring_coal.coal_bufs;
5901 if (!bnapi->rx_ring)
5904 bnxt_hwrm_cmd_hdr_init(bp, &req_rx,
5905 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS, -1, -1);
5907 bnxt_hwrm_set_coal_params(bp, &coal, &req_rx);
5909 req_rx.ring_id = cpu_to_le16(bnxt_cp_ring_for_rx(bp, bnapi->rx_ring));
5911 return hwrm_send_message(bp, &req_rx, sizeof(req_rx),
5915 int bnxt_hwrm_set_coal(struct bnxt *bp)
5918 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req_rx = {0},
5921 bnxt_hwrm_cmd_hdr_init(bp, &req_rx,
5922 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS, -1, -1);
5923 bnxt_hwrm_cmd_hdr_init(bp, &req_tx,
5924 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS, -1, -1);
5926 bnxt_hwrm_set_coal_params(bp, &bp->rx_coal, &req_rx);
5927 bnxt_hwrm_set_coal_params(bp, &bp->tx_coal, &req_tx);
5929 mutex_lock(&bp->hwrm_cmd_lock);
5930 for (i = 0; i < bp->cp_nr_rings; i++) {
5931 struct bnxt_napi *bnapi = bp->bnapi[i];
5932 struct bnxt_coal *hw_coal;
5936 if (!bnapi->rx_ring) {
5937 ring_id = bnxt_cp_ring_for_tx(bp, bnapi->tx_ring);
5940 ring_id = bnxt_cp_ring_for_rx(bp, bnapi->rx_ring);
5942 req->ring_id = cpu_to_le16(ring_id);
5944 rc = _hwrm_send_message(bp, req, sizeof(*req),
5949 if (!(bp->flags & BNXT_FLAG_CHIP_P5))
5952 if (bnapi->rx_ring && bnapi->tx_ring) {
5954 ring_id = bnxt_cp_ring_for_tx(bp, bnapi->tx_ring);
5955 req->ring_id = cpu_to_le16(ring_id);
5956 rc = _hwrm_send_message(bp, req, sizeof(*req),
5962 hw_coal = &bp->rx_coal;
5964 hw_coal = &bp->tx_coal;
5965 __bnxt_hwrm_set_coal_nq(bp, bnapi, hw_coal);
5967 mutex_unlock(&bp->hwrm_cmd_lock);
5971 static int bnxt_hwrm_stat_ctx_free(struct bnxt *bp)
5974 struct hwrm_stat_ctx_free_input req = {0};
5979 if (BNXT_CHIP_TYPE_NITRO_A0(bp))
5982 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_STAT_CTX_FREE, -1, -1);
5984 mutex_lock(&bp->hwrm_cmd_lock);
5985 for (i = 0; i < bp->cp_nr_rings; i++) {
5986 struct bnxt_napi *bnapi = bp->bnapi[i];
5987 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
5989 if (cpr->hw_stats_ctx_id != INVALID_STATS_CTX_ID) {
5990 req.stat_ctx_id = cpu_to_le32(cpr->hw_stats_ctx_id);
5992 rc = _hwrm_send_message(bp, &req, sizeof(req),
5997 cpr->hw_stats_ctx_id = INVALID_STATS_CTX_ID;
6000 mutex_unlock(&bp->hwrm_cmd_lock);
6004 static int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp)
6007 struct hwrm_stat_ctx_alloc_input req = {0};
6008 struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;
6010 if (BNXT_CHIP_TYPE_NITRO_A0(bp))
6013 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_STAT_CTX_ALLOC, -1, -1);
6015 req.update_period_ms = cpu_to_le32(bp->stats_coal_ticks / 1000);
6017 mutex_lock(&bp->hwrm_cmd_lock);
6018 for (i = 0; i < bp->cp_nr_rings; i++) {
6019 struct bnxt_napi *bnapi = bp->bnapi[i];
6020 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
6022 req.stats_dma_addr = cpu_to_le64(cpr->hw_stats_map);
6024 rc = _hwrm_send_message(bp, &req, sizeof(req),
6029 cpr->hw_stats_ctx_id = le32_to_cpu(resp->stat_ctx_id);
6031 bp->grp_info[i].fw_stats_ctx = cpr->hw_stats_ctx_id;
6033 mutex_unlock(&bp->hwrm_cmd_lock);
6037 static int bnxt_hwrm_func_qcfg(struct bnxt *bp)
6039 struct hwrm_func_qcfg_input req = {0};
6040 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
6044 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCFG, -1, -1);
6045 req.fid = cpu_to_le16(0xffff);
6046 mutex_lock(&bp->hwrm_cmd_lock);
6047 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6049 goto func_qcfg_exit;
6051 #ifdef CONFIG_BNXT_SRIOV
6053 struct bnxt_vf_info *vf = &bp->vf;
6055 vf->vlan = le16_to_cpu(resp->vlan) & VLAN_VID_MASK;
6058 flags = le16_to_cpu(resp->flags);
6059 if (flags & (FUNC_QCFG_RESP_FLAGS_FW_DCBX_AGENT_ENABLED |
6060 FUNC_QCFG_RESP_FLAGS_FW_LLDP_AGENT_ENABLED)) {
6061 bp->fw_cap |= BNXT_FW_CAP_LLDP_AGENT;
6062 if (flags & FUNC_QCFG_RESP_FLAGS_FW_DCBX_AGENT_ENABLED)
6063 bp->fw_cap |= BNXT_FW_CAP_DCBX_AGENT;
6065 if (BNXT_PF(bp) && (flags & FUNC_QCFG_RESP_FLAGS_MULTI_HOST))
6066 bp->flags |= BNXT_FLAG_MULTI_HOST;
6068 switch (resp->port_partition_type) {
6069 case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_0:
6070 case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_5:
6071 case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR2_0:
6072 bp->port_partition_type = resp->port_partition_type;
6075 if (bp->hwrm_spec_code < 0x10707 ||
6076 resp->evb_mode == FUNC_QCFG_RESP_EVB_MODE_VEB)
6077 bp->br_mode = BRIDGE_MODE_VEB;
6078 else if (resp->evb_mode == FUNC_QCFG_RESP_EVB_MODE_VEPA)
6079 bp->br_mode = BRIDGE_MODE_VEPA;
6081 bp->br_mode = BRIDGE_MODE_UNDEF;
6083 bp->max_mtu = le16_to_cpu(resp->max_mtu_configured);
6085 bp->max_mtu = BNXT_MAX_MTU;
6088 mutex_unlock(&bp->hwrm_cmd_lock);
6092 static int bnxt_hwrm_func_backing_store_qcaps(struct bnxt *bp)
6094 struct hwrm_func_backing_store_qcaps_input req = {0};
6095 struct hwrm_func_backing_store_qcaps_output *resp =
6096 bp->hwrm_cmd_resp_addr;
6099 if (bp->hwrm_spec_code < 0x10902 || BNXT_VF(bp) || bp->ctx)
6102 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_BACKING_STORE_QCAPS, -1, -1);
6103 mutex_lock(&bp->hwrm_cmd_lock);
6104 rc = _hwrm_send_message_silent(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6106 struct bnxt_ctx_pg_info *ctx_pg;
6107 struct bnxt_ctx_mem_info *ctx;
6110 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
6115 ctx_pg = kzalloc(sizeof(*ctx_pg) * (bp->max_q + 1), GFP_KERNEL);
6121 for (i = 0; i < bp->max_q + 1; i++, ctx_pg++)
6122 ctx->tqm_mem[i] = ctx_pg;
6125 ctx->qp_max_entries = le32_to_cpu(resp->qp_max_entries);
6126 ctx->qp_min_qp1_entries = le16_to_cpu(resp->qp_min_qp1_entries);
6127 ctx->qp_max_l2_entries = le16_to_cpu(resp->qp_max_l2_entries);
6128 ctx->qp_entry_size = le16_to_cpu(resp->qp_entry_size);
6129 ctx->srq_max_l2_entries = le16_to_cpu(resp->srq_max_l2_entries);
6130 ctx->srq_max_entries = le32_to_cpu(resp->srq_max_entries);
6131 ctx->srq_entry_size = le16_to_cpu(resp->srq_entry_size);
6132 ctx->cq_max_l2_entries = le16_to_cpu(resp->cq_max_l2_entries);
6133 ctx->cq_max_entries = le32_to_cpu(resp->cq_max_entries);
6134 ctx->cq_entry_size = le16_to_cpu(resp->cq_entry_size);
6135 ctx->vnic_max_vnic_entries =
6136 le16_to_cpu(resp->vnic_max_vnic_entries);
6137 ctx->vnic_max_ring_table_entries =
6138 le16_to_cpu(resp->vnic_max_ring_table_entries);
6139 ctx->vnic_entry_size = le16_to_cpu(resp->vnic_entry_size);
6140 ctx->stat_max_entries = le32_to_cpu(resp->stat_max_entries);
6141 ctx->stat_entry_size = le16_to_cpu(resp->stat_entry_size);
6142 ctx->tqm_entry_size = le16_to_cpu(resp->tqm_entry_size);
6143 ctx->tqm_min_entries_per_ring =
6144 le32_to_cpu(resp->tqm_min_entries_per_ring);
6145 ctx->tqm_max_entries_per_ring =
6146 le32_to_cpu(resp->tqm_max_entries_per_ring);
6147 ctx->tqm_entries_multiple = resp->tqm_entries_multiple;
6148 if (!ctx->tqm_entries_multiple)
6149 ctx->tqm_entries_multiple = 1;
6150 ctx->mrav_max_entries = le32_to_cpu(resp->mrav_max_entries);
6151 ctx->mrav_entry_size = le16_to_cpu(resp->mrav_entry_size);
6152 ctx->mrav_num_entries_units =
6153 le16_to_cpu(resp->mrav_num_entries_units);
6154 ctx->tim_entry_size = le16_to_cpu(resp->tim_entry_size);
6155 ctx->tim_max_entries = le32_to_cpu(resp->tim_max_entries);
6160 mutex_unlock(&bp->hwrm_cmd_lock);
6164 static void bnxt_hwrm_set_pg_attr(struct bnxt_ring_mem_info *rmem, u8 *pg_attr,
6169 if (BNXT_PAGE_SHIFT == 13)
6171 else if (BNXT_PAGE_SIZE == 16)
6175 if (rmem->depth >= 1) {
6176 if (rmem->depth == 2)
6180 *pg_dir = cpu_to_le64(rmem->pg_tbl_map);
6182 *pg_dir = cpu_to_le64(rmem->dma_arr[0]);
6186 #define FUNC_BACKING_STORE_CFG_REQ_DFLT_ENABLES \
6187 (FUNC_BACKING_STORE_CFG_REQ_ENABLES_QP | \
6188 FUNC_BACKING_STORE_CFG_REQ_ENABLES_SRQ | \
6189 FUNC_BACKING_STORE_CFG_REQ_ENABLES_CQ | \
6190 FUNC_BACKING_STORE_CFG_REQ_ENABLES_VNIC | \
6191 FUNC_BACKING_STORE_CFG_REQ_ENABLES_STAT)
6193 static int bnxt_hwrm_func_backing_store_cfg(struct bnxt *bp, u32 enables)
6195 struct hwrm_func_backing_store_cfg_input req = {0};
6196 struct bnxt_ctx_mem_info *ctx = bp->ctx;
6197 struct bnxt_ctx_pg_info *ctx_pg;
6198 __le32 *num_entries;
6208 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_BACKING_STORE_CFG, -1, -1);
6209 req.enables = cpu_to_le32(enables);
6211 if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_QP) {
6212 ctx_pg = &ctx->qp_mem;
6213 req.qp_num_entries = cpu_to_le32(ctx_pg->entries);
6214 req.qp_num_qp1_entries = cpu_to_le16(ctx->qp_min_qp1_entries);
6215 req.qp_num_l2_entries = cpu_to_le16(ctx->qp_max_l2_entries);
6216 req.qp_entry_size = cpu_to_le16(ctx->qp_entry_size);
6217 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
6218 &req.qpc_pg_size_qpc_lvl,
6221 if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_SRQ) {
6222 ctx_pg = &ctx->srq_mem;
6223 req.srq_num_entries = cpu_to_le32(ctx_pg->entries);
6224 req.srq_num_l2_entries = cpu_to_le16(ctx->srq_max_l2_entries);
6225 req.srq_entry_size = cpu_to_le16(ctx->srq_entry_size);
6226 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
6227 &req.srq_pg_size_srq_lvl,
6230 if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_CQ) {
6231 ctx_pg = &ctx->cq_mem;
6232 req.cq_num_entries = cpu_to_le32(ctx_pg->entries);
6233 req.cq_num_l2_entries = cpu_to_le16(ctx->cq_max_l2_entries);
6234 req.cq_entry_size = cpu_to_le16(ctx->cq_entry_size);
6235 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, &req.cq_pg_size_cq_lvl,
6238 if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_VNIC) {
6239 ctx_pg = &ctx->vnic_mem;
6240 req.vnic_num_vnic_entries =
6241 cpu_to_le16(ctx->vnic_max_vnic_entries);
6242 req.vnic_num_ring_table_entries =
6243 cpu_to_le16(ctx->vnic_max_ring_table_entries);
6244 req.vnic_entry_size = cpu_to_le16(ctx->vnic_entry_size);
6245 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
6246 &req.vnic_pg_size_vnic_lvl,
6247 &req.vnic_page_dir);
6249 if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_STAT) {
6250 ctx_pg = &ctx->stat_mem;
6251 req.stat_num_entries = cpu_to_le32(ctx->stat_max_entries);
6252 req.stat_entry_size = cpu_to_le16(ctx->stat_entry_size);
6253 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
6254 &req.stat_pg_size_stat_lvl,
6255 &req.stat_page_dir);
6257 if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_MRAV) {
6258 ctx_pg = &ctx->mrav_mem;
6259 req.mrav_num_entries = cpu_to_le32(ctx_pg->entries);
6260 if (ctx->mrav_num_entries_units)
6262 FUNC_BACKING_STORE_CFG_REQ_FLAGS_MRAV_RESERVATION_SPLIT;
6263 req.mrav_entry_size = cpu_to_le16(ctx->mrav_entry_size);
6264 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
6265 &req.mrav_pg_size_mrav_lvl,
6266 &req.mrav_page_dir);
6268 if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_TIM) {
6269 ctx_pg = &ctx->tim_mem;
6270 req.tim_num_entries = cpu_to_le32(ctx_pg->entries);
6271 req.tim_entry_size = cpu_to_le16(ctx->tim_entry_size);
6272 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
6273 &req.tim_pg_size_tim_lvl,
6276 for (i = 0, num_entries = &req.tqm_sp_num_entries,
6277 pg_attr = &req.tqm_sp_pg_size_tqm_sp_lvl,
6278 pg_dir = &req.tqm_sp_page_dir,
6279 ena = FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_SP;
6280 i < 9; i++, num_entries++, pg_attr++, pg_dir++, ena <<= 1) {
6281 if (!(enables & ena))
6284 req.tqm_entry_size = cpu_to_le16(ctx->tqm_entry_size);
6285 ctx_pg = ctx->tqm_mem[i];
6286 *num_entries = cpu_to_le32(ctx_pg->entries);
6287 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, pg_attr, pg_dir);
6289 req.flags = cpu_to_le32(flags);
6290 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6296 static int bnxt_alloc_ctx_mem_blk(struct bnxt *bp,
6297 struct bnxt_ctx_pg_info *ctx_pg)
6299 struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
6301 rmem->page_size = BNXT_PAGE_SIZE;
6302 rmem->pg_arr = ctx_pg->ctx_pg_arr;
6303 rmem->dma_arr = ctx_pg->ctx_dma_arr;
6304 rmem->flags = BNXT_RMEM_VALID_PTE_FLAG;
6305 if (rmem->depth >= 1)
6306 rmem->flags |= BNXT_RMEM_USE_FULL_PAGE_FLAG;
6307 return bnxt_alloc_ring(bp, rmem);
6310 static int bnxt_alloc_ctx_pg_tbls(struct bnxt *bp,
6311 struct bnxt_ctx_pg_info *ctx_pg, u32 mem_size,
6314 struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
6320 ctx_pg->nr_pages = DIV_ROUND_UP(mem_size, BNXT_PAGE_SIZE);
6321 if (ctx_pg->nr_pages > MAX_CTX_TOTAL_PAGES) {
6322 ctx_pg->nr_pages = 0;
6325 if (ctx_pg->nr_pages > MAX_CTX_PAGES || depth > 1) {
6329 ctx_pg->ctx_pg_tbl = kcalloc(MAX_CTX_PAGES, sizeof(ctx_pg),
6331 if (!ctx_pg->ctx_pg_tbl)
6333 nr_tbls = DIV_ROUND_UP(ctx_pg->nr_pages, MAX_CTX_PAGES);
6334 rmem->nr_pages = nr_tbls;
6335 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg);
6338 for (i = 0; i < nr_tbls; i++) {
6339 struct bnxt_ctx_pg_info *pg_tbl;
6341 pg_tbl = kzalloc(sizeof(*pg_tbl), GFP_KERNEL);
6344 ctx_pg->ctx_pg_tbl[i] = pg_tbl;
6345 rmem = &pg_tbl->ring_mem;
6346 rmem->pg_tbl = ctx_pg->ctx_pg_arr[i];
6347 rmem->pg_tbl_map = ctx_pg->ctx_dma_arr[i];
6349 rmem->nr_pages = MAX_CTX_PAGES;
6350 if (i == (nr_tbls - 1)) {
6351 int rem = ctx_pg->nr_pages % MAX_CTX_PAGES;
6354 rmem->nr_pages = rem;
6356 rc = bnxt_alloc_ctx_mem_blk(bp, pg_tbl);
6361 rmem->nr_pages = DIV_ROUND_UP(mem_size, BNXT_PAGE_SIZE);
6362 if (rmem->nr_pages > 1 || depth)
6364 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg);
6369 static void bnxt_free_ctx_pg_tbls(struct bnxt *bp,
6370 struct bnxt_ctx_pg_info *ctx_pg)
6372 struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
6374 if (rmem->depth > 1 || ctx_pg->nr_pages > MAX_CTX_PAGES ||
6375 ctx_pg->ctx_pg_tbl) {
6376 int i, nr_tbls = rmem->nr_pages;
6378 for (i = 0; i < nr_tbls; i++) {
6379 struct bnxt_ctx_pg_info *pg_tbl;
6380 struct bnxt_ring_mem_info *rmem2;
6382 pg_tbl = ctx_pg->ctx_pg_tbl[i];
6385 rmem2 = &pg_tbl->ring_mem;
6386 bnxt_free_ring(bp, rmem2);
6387 ctx_pg->ctx_pg_arr[i] = NULL;
6389 ctx_pg->ctx_pg_tbl[i] = NULL;
6391 kfree(ctx_pg->ctx_pg_tbl);
6392 ctx_pg->ctx_pg_tbl = NULL;
6394 bnxt_free_ring(bp, rmem);
6395 ctx_pg->nr_pages = 0;
6398 static void bnxt_free_ctx_mem(struct bnxt *bp)
6400 struct bnxt_ctx_mem_info *ctx = bp->ctx;
6406 if (ctx->tqm_mem[0]) {
6407 for (i = 0; i < bp->max_q + 1; i++)
6408 bnxt_free_ctx_pg_tbls(bp, ctx->tqm_mem[i]);
6409 kfree(ctx->tqm_mem[0]);
6410 ctx->tqm_mem[0] = NULL;
6413 bnxt_free_ctx_pg_tbls(bp, &ctx->tim_mem);
6414 bnxt_free_ctx_pg_tbls(bp, &ctx->mrav_mem);
6415 bnxt_free_ctx_pg_tbls(bp, &ctx->stat_mem);
6416 bnxt_free_ctx_pg_tbls(bp, &ctx->vnic_mem);
6417 bnxt_free_ctx_pg_tbls(bp, &ctx->cq_mem);
6418 bnxt_free_ctx_pg_tbls(bp, &ctx->srq_mem);
6419 bnxt_free_ctx_pg_tbls(bp, &ctx->qp_mem);
6420 ctx->flags &= ~BNXT_CTX_FLAG_INITED;
6423 static int bnxt_alloc_ctx_mem(struct bnxt *bp)
6425 struct bnxt_ctx_pg_info *ctx_pg;
6426 struct bnxt_ctx_mem_info *ctx;
6427 u32 mem_size, ena, entries;
6434 rc = bnxt_hwrm_func_backing_store_qcaps(bp);
6436 netdev_err(bp->dev, "Failed querying context mem capability, rc = %d.\n",
6441 if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED))
6444 if ((bp->flags & BNXT_FLAG_ROCE_CAP) && !is_kdump_kernel()) {
6450 ctx_pg = &ctx->qp_mem;
6451 ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries +
6453 mem_size = ctx->qp_entry_size * ctx_pg->entries;
6454 rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, pg_lvl);
6458 ctx_pg = &ctx->srq_mem;
6459 ctx_pg->entries = ctx->srq_max_l2_entries + extra_srqs;
6460 mem_size = ctx->srq_entry_size * ctx_pg->entries;
6461 rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, pg_lvl);
6465 ctx_pg = &ctx->cq_mem;
6466 ctx_pg->entries = ctx->cq_max_l2_entries + extra_qps * 2;
6467 mem_size = ctx->cq_entry_size * ctx_pg->entries;
6468 rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, pg_lvl);
6472 ctx_pg = &ctx->vnic_mem;
6473 ctx_pg->entries = ctx->vnic_max_vnic_entries +
6474 ctx->vnic_max_ring_table_entries;
6475 mem_size = ctx->vnic_entry_size * ctx_pg->entries;
6476 rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, 1);
6480 ctx_pg = &ctx->stat_mem;
6481 ctx_pg->entries = ctx->stat_max_entries;
6482 mem_size = ctx->stat_entry_size * ctx_pg->entries;
6483 rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, 1);
6488 if (!(bp->flags & BNXT_FLAG_ROCE_CAP))
6491 ctx_pg = &ctx->mrav_mem;
6492 /* 128K extra is needed to accommodate static AH context
6493 * allocation by f/w.
6495 num_mr = 1024 * 256;
6496 num_ah = 1024 * 128;
6497 ctx_pg->entries = num_mr + num_ah;
6498 mem_size = ctx->mrav_entry_size * ctx_pg->entries;
6499 rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, 2);
6502 ena = FUNC_BACKING_STORE_CFG_REQ_ENABLES_MRAV;
6503 if (ctx->mrav_num_entries_units)
6505 ((num_mr / ctx->mrav_num_entries_units) << 16) |
6506 (num_ah / ctx->mrav_num_entries_units);
6508 ctx_pg = &ctx->tim_mem;
6509 ctx_pg->entries = ctx->qp_mem.entries;
6510 mem_size = ctx->tim_entry_size * ctx_pg->entries;
6511 rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, 1);
6514 ena |= FUNC_BACKING_STORE_CFG_REQ_ENABLES_TIM;
6517 entries = ctx->qp_max_l2_entries + extra_qps;
6518 entries = roundup(entries, ctx->tqm_entries_multiple);
6519 entries = clamp_t(u32, entries, ctx->tqm_min_entries_per_ring,
6520 ctx->tqm_max_entries_per_ring);
6521 for (i = 0; i < bp->max_q + 1; i++) {
6522 ctx_pg = ctx->tqm_mem[i];
6523 ctx_pg->entries = entries;
6524 mem_size = ctx->tqm_entry_size * entries;
6525 rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, 1);
6528 ena |= FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_SP << i;
6530 ena |= FUNC_BACKING_STORE_CFG_REQ_DFLT_ENABLES;
6531 rc = bnxt_hwrm_func_backing_store_cfg(bp, ena);
6533 netdev_err(bp->dev, "Failed configuring context mem, rc = %d.\n",
6536 ctx->flags |= BNXT_CTX_FLAG_INITED;
6541 int bnxt_hwrm_func_resc_qcaps(struct bnxt *bp, bool all)
6543 struct hwrm_func_resource_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
6544 struct hwrm_func_resource_qcaps_input req = {0};
6545 struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
6548 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_RESOURCE_QCAPS, -1, -1);
6549 req.fid = cpu_to_le16(0xffff);
6551 mutex_lock(&bp->hwrm_cmd_lock);
6552 rc = _hwrm_send_message_silent(bp, &req, sizeof(req),
6556 goto hwrm_func_resc_qcaps_exit;
6559 hw_resc->max_tx_sch_inputs = le16_to_cpu(resp->max_tx_scheduler_inputs);
6561 goto hwrm_func_resc_qcaps_exit;
6563 hw_resc->min_rsscos_ctxs = le16_to_cpu(resp->min_rsscos_ctx);
6564 hw_resc->max_rsscos_ctxs = le16_to_cpu(resp->max_rsscos_ctx);
6565 hw_resc->min_cp_rings = le16_to_cpu(resp->min_cmpl_rings);
6566 hw_resc->max_cp_rings = le16_to_cpu(resp->max_cmpl_rings);
6567 hw_resc->min_tx_rings = le16_to_cpu(resp->min_tx_rings);
6568 hw_resc->max_tx_rings = le16_to_cpu(resp->max_tx_rings);
6569 hw_resc->min_rx_rings = le16_to_cpu(resp->min_rx_rings);
6570 hw_resc->max_rx_rings = le16_to_cpu(resp->max_rx_rings);
6571 hw_resc->min_hw_ring_grps = le16_to_cpu(resp->min_hw_ring_grps);
6572 hw_resc->max_hw_ring_grps = le16_to_cpu(resp->max_hw_ring_grps);
6573 hw_resc->min_l2_ctxs = le16_to_cpu(resp->min_l2_ctxs);
6574 hw_resc->max_l2_ctxs = le16_to_cpu(resp->max_l2_ctxs);
6575 hw_resc->min_vnics = le16_to_cpu(resp->min_vnics);
6576 hw_resc->max_vnics = le16_to_cpu(resp->max_vnics);
6577 hw_resc->min_stat_ctxs = le16_to_cpu(resp->min_stat_ctx);
6578 hw_resc->max_stat_ctxs = le16_to_cpu(resp->max_stat_ctx);
6580 if (bp->flags & BNXT_FLAG_CHIP_P5) {
6581 u16 max_msix = le16_to_cpu(resp->max_msix);
6583 hw_resc->max_nqs = max_msix;
6584 hw_resc->max_hw_ring_grps = hw_resc->max_rx_rings;
6588 struct bnxt_pf_info *pf = &bp->pf;
6590 pf->vf_resv_strategy =
6591 le16_to_cpu(resp->vf_reservation_strategy);
6592 if (pf->vf_resv_strategy > BNXT_VF_RESV_STRATEGY_MINIMAL_STATIC)
6593 pf->vf_resv_strategy = BNXT_VF_RESV_STRATEGY_MAXIMAL;
6595 hwrm_func_resc_qcaps_exit:
6596 mutex_unlock(&bp->hwrm_cmd_lock);
6600 static int __bnxt_hwrm_func_qcaps(struct bnxt *bp)
6603 struct hwrm_func_qcaps_input req = {0};
6604 struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
6605 struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
6608 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCAPS, -1, -1);
6609 req.fid = cpu_to_le16(0xffff);
6611 mutex_lock(&bp->hwrm_cmd_lock);
6612 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6614 goto hwrm_func_qcaps_exit;
6616 flags = le32_to_cpu(resp->flags);
6617 if (flags & FUNC_QCAPS_RESP_FLAGS_ROCE_V1_SUPPORTED)
6618 bp->flags |= BNXT_FLAG_ROCEV1_CAP;
6619 if (flags & FUNC_QCAPS_RESP_FLAGS_ROCE_V2_SUPPORTED)
6620 bp->flags |= BNXT_FLAG_ROCEV2_CAP;
6621 if (flags & FUNC_QCAPS_RESP_FLAGS_PCIE_STATS_SUPPORTED)
6622 bp->fw_cap |= BNXT_FW_CAP_PCIE_STATS_SUPPORTED;
6623 if (flags & FUNC_QCAPS_RESP_FLAGS_EXT_STATS_SUPPORTED)
6624 bp->fw_cap |= BNXT_FW_CAP_EXT_STATS_SUPPORTED;
6626 bp->tx_push_thresh = 0;
6627 if (flags & FUNC_QCAPS_RESP_FLAGS_PUSH_MODE_SUPPORTED)
6628 bp->tx_push_thresh = BNXT_TX_PUSH_THRESH;
6630 hw_resc->max_rsscos_ctxs = le16_to_cpu(resp->max_rsscos_ctx);
6631 hw_resc->max_cp_rings = le16_to_cpu(resp->max_cmpl_rings);
6632 hw_resc->max_tx_rings = le16_to_cpu(resp->max_tx_rings);
6633 hw_resc->max_rx_rings = le16_to_cpu(resp->max_rx_rings);
6634 hw_resc->max_hw_ring_grps = le32_to_cpu(resp->max_hw_ring_grps);
6635 if (!hw_resc->max_hw_ring_grps)
6636 hw_resc->max_hw_ring_grps = hw_resc->max_tx_rings;
6637 hw_resc->max_l2_ctxs = le16_to_cpu(resp->max_l2_ctxs);
6638 hw_resc->max_vnics = le16_to_cpu(resp->max_vnics);
6639 hw_resc->max_stat_ctxs = le16_to_cpu(resp->max_stat_ctx);
6642 struct bnxt_pf_info *pf = &bp->pf;
6644 pf->fw_fid = le16_to_cpu(resp->fid);
6645 pf->port_id = le16_to_cpu(resp->port_id);
6646 bp->dev->dev_port = pf->port_id;
6647 memcpy(pf->mac_addr, resp->mac_address, ETH_ALEN);
6648 pf->first_vf_id = le16_to_cpu(resp->first_vf_id);
6649 pf->max_vfs = le16_to_cpu(resp->max_vfs);
6650 pf->max_encap_records = le32_to_cpu(resp->max_encap_records);
6651 pf->max_decap_records = le32_to_cpu(resp->max_decap_records);
6652 pf->max_tx_em_flows = le32_to_cpu(resp->max_tx_em_flows);
6653 pf->max_tx_wm_flows = le32_to_cpu(resp->max_tx_wm_flows);
6654 pf->max_rx_em_flows = le32_to_cpu(resp->max_rx_em_flows);
6655 pf->max_rx_wm_flows = le32_to_cpu(resp->max_rx_wm_flows);
6656 if (flags & FUNC_QCAPS_RESP_FLAGS_WOL_MAGICPKT_SUPPORTED)
6657 bp->flags |= BNXT_FLAG_WOL_CAP;
6659 #ifdef CONFIG_BNXT_SRIOV
6660 struct bnxt_vf_info *vf = &bp->vf;
6662 vf->fw_fid = le16_to_cpu(resp->fid);
6663 memcpy(vf->mac_addr, resp->mac_address, ETH_ALEN);
6667 hwrm_func_qcaps_exit:
6668 mutex_unlock(&bp->hwrm_cmd_lock);
6672 static int bnxt_hwrm_queue_qportcfg(struct bnxt *bp);
6674 static int bnxt_hwrm_func_qcaps(struct bnxt *bp)
6678 rc = __bnxt_hwrm_func_qcaps(bp);
6681 rc = bnxt_hwrm_queue_qportcfg(bp);
6683 netdev_err(bp->dev, "hwrm query qportcfg failure rc: %d\n", rc);
6686 if (bp->hwrm_spec_code >= 0x10803) {
6687 rc = bnxt_alloc_ctx_mem(bp);
6690 rc = bnxt_hwrm_func_resc_qcaps(bp, true);
6692 bp->fw_cap |= BNXT_FW_CAP_NEW_RM;
6697 static int bnxt_hwrm_cfa_adv_flow_mgnt_qcaps(struct bnxt *bp)
6699 struct hwrm_cfa_adv_flow_mgnt_qcaps_input req = {0};
6700 struct hwrm_cfa_adv_flow_mgnt_qcaps_output *resp;
6704 if (!(bp->fw_cap & BNXT_FW_CAP_CFA_ADV_FLOW))
6707 resp = bp->hwrm_cmd_resp_addr;
6708 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_ADV_FLOW_MGNT_QCAPS, -1, -1);
6710 mutex_lock(&bp->hwrm_cmd_lock);
6711 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6713 goto hwrm_cfa_adv_qcaps_exit;
6715 flags = le32_to_cpu(resp->flags);
6717 CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_RFS_RING_TBL_IDX_SUPPORTED)
6718 bp->fw_cap |= BNXT_FW_CAP_CFA_RFS_RING_TBL_IDX;
6720 hwrm_cfa_adv_qcaps_exit:
6721 mutex_unlock(&bp->hwrm_cmd_lock);
6725 static int bnxt_hwrm_func_reset(struct bnxt *bp)
6727 struct hwrm_func_reset_input req = {0};
6729 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_RESET, -1, -1);
6732 return hwrm_send_message(bp, &req, sizeof(req), HWRM_RESET_TIMEOUT);
6735 static int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
6738 struct hwrm_queue_qportcfg_input req = {0};
6739 struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
6743 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_QUEUE_QPORTCFG, -1, -1);
6745 mutex_lock(&bp->hwrm_cmd_lock);
6746 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6750 if (!resp->max_configurable_queues) {
6754 bp->max_tc = resp->max_configurable_queues;
6755 bp->max_lltc = resp->max_configurable_lossless_queues;
6756 if (bp->max_tc > BNXT_MAX_QUEUE)
6757 bp->max_tc = BNXT_MAX_QUEUE;
6759 no_rdma = !(bp->flags & BNXT_FLAG_ROCE_CAP);
6760 qptr = &resp->queue_id0;
6761 for (i = 0, j = 0; i < bp->max_tc; i++) {
6762 bp->q_info[j].queue_id = *qptr;
6763 bp->q_ids[i] = *qptr++;
6764 bp->q_info[j].queue_profile = *qptr++;
6765 bp->tc_to_qidx[j] = j;
6766 if (!BNXT_CNPQ(bp->q_info[j].queue_profile) ||
6767 (no_rdma && BNXT_PF(bp)))
6770 bp->max_q = bp->max_tc;
6771 bp->max_tc = max_t(u8, j, 1);
6773 if (resp->queue_cfg_info & QUEUE_QPORTCFG_RESP_QUEUE_CFG_INFO_ASYM_CFG)
6776 if (bp->max_lltc > bp->max_tc)
6777 bp->max_lltc = bp->max_tc;
6780 mutex_unlock(&bp->hwrm_cmd_lock);
6784 static int bnxt_hwrm_ver_get(struct bnxt *bp)
6787 struct hwrm_ver_get_input req = {0};
6788 struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
6791 bp->hwrm_max_req_len = HWRM_MAX_REQ_LEN;
6792 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VER_GET, -1, -1);
6793 req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
6794 req.hwrm_intf_min = HWRM_VERSION_MINOR;
6795 req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
6796 mutex_lock(&bp->hwrm_cmd_lock);
6797 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6799 goto hwrm_ver_get_exit;
6801 memcpy(&bp->ver_resp, resp, sizeof(struct hwrm_ver_get_output));
6803 bp->hwrm_spec_code = resp->hwrm_intf_maj_8b << 16 |
6804 resp->hwrm_intf_min_8b << 8 |
6805 resp->hwrm_intf_upd_8b;
6806 if (resp->hwrm_intf_maj_8b < 1) {
6807 netdev_warn(bp->dev, "HWRM interface %d.%d.%d is older than 1.0.0.\n",
6808 resp->hwrm_intf_maj_8b, resp->hwrm_intf_min_8b,
6809 resp->hwrm_intf_upd_8b);
6810 netdev_warn(bp->dev, "Please update firmware with HWRM interface 1.0.0 or newer.\n");
6812 snprintf(bp->fw_ver_str, BC_HWRM_STR_LEN, "%d.%d.%d.%d",
6813 resp->hwrm_fw_maj_8b, resp->hwrm_fw_min_8b,
6814 resp->hwrm_fw_bld_8b, resp->hwrm_fw_rsvd_8b);
6816 if (strlen(resp->active_pkg_name)) {
6817 int fw_ver_len = strlen(bp->fw_ver_str);
6819 snprintf(bp->fw_ver_str + fw_ver_len,
6820 FW_VER_STR_LEN - fw_ver_len - 1, "/pkg %s",
6821 resp->active_pkg_name);
6822 bp->fw_cap |= BNXT_FW_CAP_PKG_VER;
6825 bp->hwrm_cmd_timeout = le16_to_cpu(resp->def_req_timeout);
6826 if (!bp->hwrm_cmd_timeout)
6827 bp->hwrm_cmd_timeout = DFLT_HWRM_CMD_TIMEOUT;
6829 if (resp->hwrm_intf_maj_8b >= 1) {
6830 bp->hwrm_max_req_len = le16_to_cpu(resp->max_req_win_len);
6831 bp->hwrm_max_ext_req_len = le16_to_cpu(resp->max_ext_req_len);
6833 if (bp->hwrm_max_ext_req_len < HWRM_MAX_REQ_LEN)
6834 bp->hwrm_max_ext_req_len = HWRM_MAX_REQ_LEN;
6836 bp->chip_num = le16_to_cpu(resp->chip_num);
6837 if (bp->chip_num == CHIP_NUM_58700 && !resp->chip_rev &&
6839 bp->flags |= BNXT_FLAG_CHIP_NITRO_A0;
6841 dev_caps_cfg = le32_to_cpu(resp->dev_caps_cfg);
6842 if ((dev_caps_cfg & VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
6843 (dev_caps_cfg & VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_REQUIRED))
6844 bp->fw_cap |= BNXT_FW_CAP_SHORT_CMD;
6846 if (dev_caps_cfg & VER_GET_RESP_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED)
6847 bp->fw_cap |= BNXT_FW_CAP_KONG_MB_CHNL;
6850 VER_GET_RESP_DEV_CAPS_CFG_FLOW_HANDLE_64BIT_SUPPORTED)
6851 bp->fw_cap |= BNXT_FW_CAP_OVS_64BIT_HANDLE;
6854 VER_GET_RESP_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED)
6855 bp->fw_cap |= BNXT_FW_CAP_TRUSTED_VF;
6858 VER_GET_RESP_DEV_CAPS_CFG_CFA_ADV_FLOW_MGNT_SUPPORTED)
6859 bp->fw_cap |= BNXT_FW_CAP_CFA_ADV_FLOW;
6862 mutex_unlock(&bp->hwrm_cmd_lock);
6866 int bnxt_hwrm_fw_set_time(struct bnxt *bp)
6868 struct hwrm_fw_set_time_input req = {0};
6870 time64_t now = ktime_get_real_seconds();
6872 if ((BNXT_VF(bp) && bp->hwrm_spec_code < 0x10901) ||
6873 bp->hwrm_spec_code < 0x10400)
6876 time64_to_tm(now, 0, &tm);
6877 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FW_SET_TIME, -1, -1);
6878 req.year = cpu_to_le16(1900 + tm.tm_year);
6879 req.month = 1 + tm.tm_mon;
6880 req.day = tm.tm_mday;
6881 req.hour = tm.tm_hour;
6882 req.minute = tm.tm_min;
6883 req.second = tm.tm_sec;
6884 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6887 static int bnxt_hwrm_port_qstats(struct bnxt *bp)
6890 struct bnxt_pf_info *pf = &bp->pf;
6891 struct hwrm_port_qstats_input req = {0};
6893 if (!(bp->flags & BNXT_FLAG_PORT_STATS))
6896 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_QSTATS, -1, -1);
6897 req.port_id = cpu_to_le16(pf->port_id);
6898 req.tx_stat_host_addr = cpu_to_le64(bp->hw_tx_port_stats_map);
6899 req.rx_stat_host_addr = cpu_to_le64(bp->hw_rx_port_stats_map);
6900 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6904 static int bnxt_hwrm_port_qstats_ext(struct bnxt *bp)
6906 struct hwrm_port_qstats_ext_output *resp = bp->hwrm_cmd_resp_addr;
6907 struct hwrm_queue_pri2cos_qcfg_input req2 = {0};
6908 struct hwrm_port_qstats_ext_input req = {0};
6909 struct bnxt_pf_info *pf = &bp->pf;
6913 if (!(bp->flags & BNXT_FLAG_PORT_STATS_EXT))
6916 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_QSTATS_EXT, -1, -1);
6917 req.port_id = cpu_to_le16(pf->port_id);
6918 req.rx_stat_size = cpu_to_le16(sizeof(struct rx_port_stats_ext));
6919 req.rx_stat_host_addr = cpu_to_le64(bp->hw_rx_port_stats_ext_map);
6920 tx_stat_size = bp->hw_tx_port_stats_ext ?
6921 sizeof(*bp->hw_tx_port_stats_ext) : 0;
6922 req.tx_stat_size = cpu_to_le16(tx_stat_size);
6923 req.tx_stat_host_addr = cpu_to_le64(bp->hw_tx_port_stats_ext_map);
6924 mutex_lock(&bp->hwrm_cmd_lock);
6925 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6927 bp->fw_rx_stats_ext_size = le16_to_cpu(resp->rx_stat_size) / 8;
6928 bp->fw_tx_stats_ext_size = tx_stat_size ?
6929 le16_to_cpu(resp->tx_stat_size) / 8 : 0;
6931 bp->fw_rx_stats_ext_size = 0;
6932 bp->fw_tx_stats_ext_size = 0;
6934 if (bp->fw_tx_stats_ext_size <=
6935 offsetof(struct tx_port_stats_ext, pfc_pri0_tx_duration_us) / 8) {
6936 mutex_unlock(&bp->hwrm_cmd_lock);
6937 bp->pri2cos_valid = 0;
6941 bnxt_hwrm_cmd_hdr_init(bp, &req2, HWRM_QUEUE_PRI2COS_QCFG, -1, -1);
6942 req2.flags = cpu_to_le32(QUEUE_PRI2COS_QCFG_REQ_FLAGS_IVLAN);
6944 rc = _hwrm_send_message(bp, &req2, sizeof(req2), HWRM_CMD_TIMEOUT);
6946 struct hwrm_queue_pri2cos_qcfg_output *resp2;
6950 resp2 = bp->hwrm_cmd_resp_addr;
6951 pri2cos = &resp2->pri0_cos_queue_id;
6952 for (i = 0; i < 8; i++) {
6953 u8 queue_id = pri2cos[i];
6955 for (j = 0; j < bp->max_q; j++) {
6956 if (bp->q_ids[j] == queue_id)
6960 bp->pri2cos_valid = 1;
6962 mutex_unlock(&bp->hwrm_cmd_lock);
6966 static int bnxt_hwrm_pcie_qstats(struct bnxt *bp)
6968 struct hwrm_pcie_qstats_input req = {0};
6970 if (!(bp->flags & BNXT_FLAG_PCIE_STATS))
6973 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PCIE_QSTATS, -1, -1);
6974 req.pcie_stat_size = cpu_to_le16(sizeof(struct pcie_ctx_hw_stats));
6975 req.pcie_stat_host_addr = cpu_to_le64(bp->hw_pcie_stats_map);
6976 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6979 static void bnxt_hwrm_free_tunnel_ports(struct bnxt *bp)
6981 if (bp->vxlan_port_cnt) {
6982 bnxt_hwrm_tunnel_dst_port_free(
6983 bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN);
6985 bp->vxlan_port_cnt = 0;
6986 if (bp->nge_port_cnt) {
6987 bnxt_hwrm_tunnel_dst_port_free(
6988 bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE);
6990 bp->nge_port_cnt = 0;
6993 static int bnxt_set_tpa(struct bnxt *bp, bool set_tpa)
6999 tpa_flags = bp->flags & BNXT_FLAG_TPA;
7000 for (i = 0; i < bp->nr_vnics; i++) {
7001 rc = bnxt_hwrm_vnic_set_tpa(bp, i, tpa_flags);
7003 netdev_err(bp->dev, "hwrm vnic set tpa failure rc for vnic %d: %x\n",
7011 static void bnxt_hwrm_clear_vnic_rss(struct bnxt *bp)
7015 for (i = 0; i < bp->nr_vnics; i++)
7016 bnxt_hwrm_vnic_set_rss(bp, i, false);
7019 static void bnxt_hwrm_resource_free(struct bnxt *bp, bool close_path,
7022 if (bp->vnic_info) {
7023 bnxt_hwrm_clear_vnic_filter(bp);
7024 /* clear all RSS setting before free vnic ctx */
7025 bnxt_hwrm_clear_vnic_rss(bp);
7026 bnxt_hwrm_vnic_ctx_free(bp);
7027 /* before free the vnic, undo the vnic tpa settings */
7028 if (bp->flags & BNXT_FLAG_TPA)
7029 bnxt_set_tpa(bp, false);
7030 bnxt_hwrm_vnic_free(bp);
7032 bnxt_hwrm_ring_free(bp, close_path);
7033 bnxt_hwrm_ring_grp_free(bp);
7035 bnxt_hwrm_stat_ctx_free(bp);
7036 bnxt_hwrm_free_tunnel_ports(bp);
7040 static int bnxt_hwrm_set_br_mode(struct bnxt *bp, u16 br_mode)
7042 struct hwrm_func_cfg_input req = {0};
7045 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_CFG, -1, -1);
7046 req.fid = cpu_to_le16(0xffff);
7047 req.enables = cpu_to_le32(FUNC_CFG_REQ_ENABLES_EVB_MODE);
7048 if (br_mode == BRIDGE_MODE_VEB)
7049 req.evb_mode = FUNC_CFG_REQ_EVB_MODE_VEB;
7050 else if (br_mode == BRIDGE_MODE_VEPA)
7051 req.evb_mode = FUNC_CFG_REQ_EVB_MODE_VEPA;
7054 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
7060 static int bnxt_hwrm_set_cache_line_size(struct bnxt *bp, int size)
7062 struct hwrm_func_cfg_input req = {0};
7065 if (BNXT_VF(bp) || bp->hwrm_spec_code < 0x10803)
7068 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_CFG, -1, -1);
7069 req.fid = cpu_to_le16(0xffff);
7070 req.enables = cpu_to_le32(FUNC_CFG_REQ_ENABLES_CACHE_LINESIZE);
7071 req.options = FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_64;
7073 req.options = FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_128;
7075 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
7081 static int __bnxt_setup_vnic(struct bnxt *bp, u16 vnic_id)
7083 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
7086 if (vnic->flags & BNXT_VNIC_RFS_NEW_RSS_FLAG)
7089 /* allocate context for vnic */
7090 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic_id, 0);
7092 netdev_err(bp->dev, "hwrm vnic %d alloc failure rc: %x\n",
7094 goto vnic_setup_err;
7096 bp->rsscos_nr_ctxs++;
7098 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) {
7099 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic_id, 1);
7101 netdev_err(bp->dev, "hwrm vnic %d cos ctx alloc failure rc: %x\n",
7103 goto vnic_setup_err;
7105 bp->rsscos_nr_ctxs++;
7109 /* configure default vnic, ring grp */
7110 rc = bnxt_hwrm_vnic_cfg(bp, vnic_id);
7112 netdev_err(bp->dev, "hwrm vnic %d cfg failure rc: %x\n",
7114 goto vnic_setup_err;
7117 /* Enable RSS hashing on vnic */
7118 rc = bnxt_hwrm_vnic_set_rss(bp, vnic_id, true);
7120 netdev_err(bp->dev, "hwrm vnic %d set rss failure rc: %x\n",
7122 goto vnic_setup_err;
7125 if (bp->flags & BNXT_FLAG_AGG_RINGS) {
7126 rc = bnxt_hwrm_vnic_set_hds(bp, vnic_id);
7128 netdev_err(bp->dev, "hwrm vnic %d set hds failure rc: %x\n",
7137 static int __bnxt_setup_vnic_p5(struct bnxt *bp, u16 vnic_id)
7141 nr_ctxs = DIV_ROUND_UP(bp->rx_nr_rings, 64);
7142 for (i = 0; i < nr_ctxs; i++) {
7143 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic_id, i);
7145 netdev_err(bp->dev, "hwrm vnic %d ctx %d alloc failure rc: %x\n",
7149 bp->rsscos_nr_ctxs++;
7154 rc = bnxt_hwrm_vnic_set_rss_p5(bp, vnic_id, true);
7156 netdev_err(bp->dev, "hwrm vnic %d set rss failure rc: %d\n",
7160 rc = bnxt_hwrm_vnic_cfg(bp, vnic_id);
7162 netdev_err(bp->dev, "hwrm vnic %d cfg failure rc: %x\n",
7166 if (bp->flags & BNXT_FLAG_AGG_RINGS) {
7167 rc = bnxt_hwrm_vnic_set_hds(bp, vnic_id);
7169 netdev_err(bp->dev, "hwrm vnic %d set hds failure rc: %x\n",
7176 static int bnxt_setup_vnic(struct bnxt *bp, u16 vnic_id)
7178 if (bp->flags & BNXT_FLAG_CHIP_P5)
7179 return __bnxt_setup_vnic_p5(bp, vnic_id);
7181 return __bnxt_setup_vnic(bp, vnic_id);
7184 static int bnxt_alloc_rfs_vnics(struct bnxt *bp)
7186 #ifdef CONFIG_RFS_ACCEL
7189 if (bp->flags & BNXT_FLAG_CHIP_P5)
7192 for (i = 0; i < bp->rx_nr_rings; i++) {
7193 struct bnxt_vnic_info *vnic;
7194 u16 vnic_id = i + 1;
7197 if (vnic_id >= bp->nr_vnics)
7200 vnic = &bp->vnic_info[vnic_id];
7201 vnic->flags |= BNXT_VNIC_RFS_FLAG;
7202 if (bp->flags & BNXT_FLAG_NEW_RSS_CAP)
7203 vnic->flags |= BNXT_VNIC_RFS_NEW_RSS_FLAG;
7204 rc = bnxt_hwrm_vnic_alloc(bp, vnic_id, ring_id, 1);
7206 netdev_err(bp->dev, "hwrm vnic %d alloc failure rc: %x\n",
7210 rc = bnxt_setup_vnic(bp, vnic_id);
7220 /* Allow PF and VF with default VLAN to be in promiscuous mode */
7221 static bool bnxt_promisc_ok(struct bnxt *bp)
7223 #ifdef CONFIG_BNXT_SRIOV
7224 if (BNXT_VF(bp) && !bp->vf.vlan)
7230 static int bnxt_setup_nitroa0_vnic(struct bnxt *bp)
7232 unsigned int rc = 0;
7234 rc = bnxt_hwrm_vnic_alloc(bp, 1, bp->rx_nr_rings - 1, 1);
7236 netdev_err(bp->dev, "Cannot allocate special vnic for NS2 A0: %x\n",
7241 rc = bnxt_hwrm_vnic_cfg(bp, 1);
7243 netdev_err(bp->dev, "Cannot allocate special vnic for NS2 A0: %x\n",
7250 static int bnxt_cfg_rx_mode(struct bnxt *);
7251 static bool bnxt_mc_list_updated(struct bnxt *, u32 *);
7253 static int bnxt_init_chip(struct bnxt *bp, bool irq_re_init)
7255 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
7257 unsigned int rx_nr_rings = bp->rx_nr_rings;
7260 rc = bnxt_hwrm_stat_ctx_alloc(bp);
7262 netdev_err(bp->dev, "hwrm stat ctx alloc failure rc: %x\n",
7268 rc = bnxt_hwrm_ring_alloc(bp);
7270 netdev_err(bp->dev, "hwrm ring alloc failure rc: %x\n", rc);
7274 rc = bnxt_hwrm_ring_grp_alloc(bp);
7276 netdev_err(bp->dev, "hwrm_ring_grp alloc failure: %x\n", rc);
7280 if (BNXT_CHIP_TYPE_NITRO_A0(bp))
7283 /* default vnic 0 */
7284 rc = bnxt_hwrm_vnic_alloc(bp, 0, 0, rx_nr_rings);
7286 netdev_err(bp->dev, "hwrm vnic alloc failure rc: %x\n", rc);
7290 rc = bnxt_setup_vnic(bp, 0);
7294 if (bp->flags & BNXT_FLAG_RFS) {
7295 rc = bnxt_alloc_rfs_vnics(bp);
7300 if (bp->flags & BNXT_FLAG_TPA) {
7301 rc = bnxt_set_tpa(bp, true);
7307 bnxt_update_vf_mac(bp);
7309 /* Filter for default vnic 0 */
7310 rc = bnxt_hwrm_set_vnic_filter(bp, 0, 0, bp->dev->dev_addr);
7312 netdev_err(bp->dev, "HWRM vnic filter failure rc: %x\n", rc);
7315 vnic->uc_filter_count = 1;
7318 if (bp->dev->flags & IFF_BROADCAST)
7319 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_BCAST;
7321 if ((bp->dev->flags & IFF_PROMISC) && bnxt_promisc_ok(bp))
7322 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS;
7324 if (bp->dev->flags & IFF_ALLMULTI) {
7325 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST;
7326 vnic->mc_list_count = 0;
7330 bnxt_mc_list_updated(bp, &mask);
7331 vnic->rx_mask |= mask;
7334 rc = bnxt_cfg_rx_mode(bp);
7338 rc = bnxt_hwrm_set_coal(bp);
7340 netdev_warn(bp->dev, "HWRM set coalescing failure rc: %x\n",
7343 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) {
7344 rc = bnxt_setup_nitroa0_vnic(bp);
7346 netdev_err(bp->dev, "Special vnic setup failure for NS2 A0 rc: %x\n",
7351 bnxt_hwrm_func_qcfg(bp);
7352 netdev_update_features(bp->dev);
7358 bnxt_hwrm_resource_free(bp, 0, true);
7363 static int bnxt_shutdown_nic(struct bnxt *bp, bool irq_re_init)
7365 bnxt_hwrm_resource_free(bp, 1, irq_re_init);
7369 static int bnxt_init_nic(struct bnxt *bp, bool irq_re_init)
7371 bnxt_init_cp_rings(bp);
7372 bnxt_init_rx_rings(bp);
7373 bnxt_init_tx_rings(bp);
7374 bnxt_init_ring_grps(bp, irq_re_init);
7375 bnxt_init_vnics(bp);
7377 return bnxt_init_chip(bp, irq_re_init);
7380 static int bnxt_set_real_num_queues(struct bnxt *bp)
7383 struct net_device *dev = bp->dev;
7385 rc = netif_set_real_num_tx_queues(dev, bp->tx_nr_rings -
7386 bp->tx_nr_rings_xdp);
7390 rc = netif_set_real_num_rx_queues(dev, bp->rx_nr_rings);
7394 #ifdef CONFIG_RFS_ACCEL
7395 if (bp->flags & BNXT_FLAG_RFS)
7396 dev->rx_cpu_rmap = alloc_irq_cpu_rmap(bp->rx_nr_rings);
7402 static int bnxt_trim_rings(struct bnxt *bp, int *rx, int *tx, int max,
7405 int _rx = *rx, _tx = *tx;
7408 *rx = min_t(int, _rx, max);
7409 *tx = min_t(int, _tx, max);
7414 while (_rx + _tx > max) {
7415 if (_rx > _tx && _rx > 1)
7426 static void bnxt_setup_msix(struct bnxt *bp)
7428 const int len = sizeof(bp->irq_tbl[0].name);
7429 struct net_device *dev = bp->dev;
7432 tcs = netdev_get_num_tc(dev);
7436 for (i = 0; i < tcs; i++) {
7437 count = bp->tx_nr_rings_per_tc;
7439 netdev_set_tc_queue(dev, i, count, off);
7443 for (i = 0; i < bp->cp_nr_rings; i++) {
7444 int map_idx = bnxt_cp_num_to_irq_num(bp, i);
7447 if (bp->flags & BNXT_FLAG_SHARED_RINGS)
7449 else if (i < bp->rx_nr_rings)
7454 snprintf(bp->irq_tbl[map_idx].name, len, "%s-%s-%d", dev->name,
7456 bp->irq_tbl[map_idx].handler = bnxt_msix;
7460 static void bnxt_setup_inta(struct bnxt *bp)
7462 const int len = sizeof(bp->irq_tbl[0].name);
7464 if (netdev_get_num_tc(bp->dev))
7465 netdev_reset_tc(bp->dev);
7467 snprintf(bp->irq_tbl[0].name, len, "%s-%s-%d", bp->dev->name, "TxRx",
7469 bp->irq_tbl[0].handler = bnxt_inta;
7472 static int bnxt_setup_int_mode(struct bnxt *bp)
7476 if (bp->flags & BNXT_FLAG_USING_MSIX)
7477 bnxt_setup_msix(bp);
7479 bnxt_setup_inta(bp);
7481 rc = bnxt_set_real_num_queues(bp);
7485 #ifdef CONFIG_RFS_ACCEL
7486 static unsigned int bnxt_get_max_func_rss_ctxs(struct bnxt *bp)
7488 return bp->hw_resc.max_rsscos_ctxs;
7491 static unsigned int bnxt_get_max_func_vnics(struct bnxt *bp)
7493 return bp->hw_resc.max_vnics;
7497 unsigned int bnxt_get_max_func_stat_ctxs(struct bnxt *bp)
7499 return bp->hw_resc.max_stat_ctxs;
7502 unsigned int bnxt_get_max_func_cp_rings(struct bnxt *bp)
7504 return bp->hw_resc.max_cp_rings;
7507 static unsigned int bnxt_get_max_func_cp_rings_for_en(struct bnxt *bp)
7509 unsigned int cp = bp->hw_resc.max_cp_rings;
7511 if (!(bp->flags & BNXT_FLAG_CHIP_P5))
7512 cp -= bnxt_get_ulp_msix_num(bp);
7517 static unsigned int bnxt_get_max_func_irqs(struct bnxt *bp)
7519 struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
7521 if (bp->flags & BNXT_FLAG_CHIP_P5)
7522 return min_t(unsigned int, hw_resc->max_irqs, hw_resc->max_nqs);
7524 return min_t(unsigned int, hw_resc->max_irqs, hw_resc->max_cp_rings);
7527 static void bnxt_set_max_func_irqs(struct bnxt *bp, unsigned int max_irqs)
7529 bp->hw_resc.max_irqs = max_irqs;
7532 unsigned int bnxt_get_avail_cp_rings_for_en(struct bnxt *bp)
7536 cp = bnxt_get_max_func_cp_rings_for_en(bp);
7537 if (bp->flags & BNXT_FLAG_CHIP_P5)
7538 return cp - bp->rx_nr_rings - bp->tx_nr_rings;
7540 return cp - bp->cp_nr_rings;
7543 unsigned int bnxt_get_avail_stat_ctxs_for_en(struct bnxt *bp)
7545 return bnxt_get_max_func_stat_ctxs(bp) - bnxt_get_func_stat_ctxs(bp);
7548 int bnxt_get_avail_msix(struct bnxt *bp, int num)
7550 int max_cp = bnxt_get_max_func_cp_rings(bp);
7551 int max_irq = bnxt_get_max_func_irqs(bp);
7552 int total_req = bp->cp_nr_rings + num;
7553 int max_idx, avail_msix;
7555 max_idx = bp->total_irqs;
7556 if (!(bp->flags & BNXT_FLAG_CHIP_P5))
7557 max_idx = min_t(int, bp->total_irqs, max_cp);
7558 avail_msix = max_idx - bp->cp_nr_rings;
7559 if (!BNXT_NEW_RM(bp) || avail_msix >= num)
7562 if (max_irq < total_req) {
7563 num = max_irq - bp->cp_nr_rings;
7570 static int bnxt_get_num_msix(struct bnxt *bp)
7572 if (!BNXT_NEW_RM(bp))
7573 return bnxt_get_max_func_irqs(bp);
7575 return bnxt_nq_rings_in_use(bp);
7578 static int bnxt_init_msix(struct bnxt *bp)
7580 int i, total_vecs, max, rc = 0, min = 1, ulp_msix;
7581 struct msix_entry *msix_ent;
7583 total_vecs = bnxt_get_num_msix(bp);
7584 max = bnxt_get_max_func_irqs(bp);
7585 if (total_vecs > max)
7591 msix_ent = kcalloc(total_vecs, sizeof(struct msix_entry), GFP_KERNEL);
7595 for (i = 0; i < total_vecs; i++) {
7596 msix_ent[i].entry = i;
7597 msix_ent[i].vector = 0;
7600 if (!(bp->flags & BNXT_FLAG_SHARED_RINGS))
7603 total_vecs = pci_enable_msix_range(bp->pdev, msix_ent, min, total_vecs);
7604 ulp_msix = bnxt_get_ulp_msix_num(bp);
7605 if (total_vecs < 0 || total_vecs < ulp_msix) {
7607 goto msix_setup_exit;
7610 bp->irq_tbl = kcalloc(total_vecs, sizeof(struct bnxt_irq), GFP_KERNEL);
7612 for (i = 0; i < total_vecs; i++)
7613 bp->irq_tbl[i].vector = msix_ent[i].vector;
7615 bp->total_irqs = total_vecs;
7616 /* Trim rings based upon num of vectors allocated */
7617 rc = bnxt_trim_rings(bp, &bp->rx_nr_rings, &bp->tx_nr_rings,
7618 total_vecs - ulp_msix, min == 1);
7620 goto msix_setup_exit;
7622 bp->cp_nr_rings = (min == 1) ?
7623 max_t(int, bp->tx_nr_rings, bp->rx_nr_rings) :
7624 bp->tx_nr_rings + bp->rx_nr_rings;
7628 goto msix_setup_exit;
7630 bp->flags |= BNXT_FLAG_USING_MSIX;
7635 netdev_err(bp->dev, "bnxt_init_msix err: %x\n", rc);
7638 pci_disable_msix(bp->pdev);
7643 static int bnxt_init_inta(struct bnxt *bp)
7645 bp->irq_tbl = kcalloc(1, sizeof(struct bnxt_irq), GFP_KERNEL);
7650 bp->rx_nr_rings = 1;
7651 bp->tx_nr_rings = 1;
7652 bp->cp_nr_rings = 1;
7653 bp->flags |= BNXT_FLAG_SHARED_RINGS;
7654 bp->irq_tbl[0].vector = bp->pdev->irq;
7658 static int bnxt_init_int_mode(struct bnxt *bp)
7662 if (bp->flags & BNXT_FLAG_MSIX_CAP)
7663 rc = bnxt_init_msix(bp);
7665 if (!(bp->flags & BNXT_FLAG_USING_MSIX) && BNXT_PF(bp)) {
7666 /* fallback to INTA */
7667 rc = bnxt_init_inta(bp);
7672 static void bnxt_clear_int_mode(struct bnxt *bp)
7674 if (bp->flags & BNXT_FLAG_USING_MSIX)
7675 pci_disable_msix(bp->pdev);
7679 bp->flags &= ~BNXT_FLAG_USING_MSIX;
7682 int bnxt_reserve_rings(struct bnxt *bp, bool irq_re_init)
7684 int tcs = netdev_get_num_tc(bp->dev);
7685 bool irq_cleared = false;
7688 if (!bnxt_need_reserve_rings(bp))
7691 if (irq_re_init && BNXT_NEW_RM(bp) &&
7692 bnxt_get_num_msix(bp) != bp->total_irqs) {
7693 bnxt_ulp_irq_stop(bp);
7694 bnxt_clear_int_mode(bp);
7697 rc = __bnxt_reserve_rings(bp);
7700 rc = bnxt_init_int_mode(bp);
7701 bnxt_ulp_irq_restart(bp, rc);
7704 netdev_err(bp->dev, "ring reservation/IRQ init failure rc: %d\n", rc);
7707 if (tcs && (bp->tx_nr_rings_per_tc * tcs != bp->tx_nr_rings)) {
7708 netdev_err(bp->dev, "tx ring reservation failure\n");
7709 netdev_reset_tc(bp->dev);
7710 bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
7716 static void bnxt_free_irq(struct bnxt *bp)
7718 struct bnxt_irq *irq;
7721 #ifdef CONFIG_RFS_ACCEL
7722 free_irq_cpu_rmap(bp->dev->rx_cpu_rmap);
7723 bp->dev->rx_cpu_rmap = NULL;
7725 if (!bp->irq_tbl || !bp->bnapi)
7728 for (i = 0; i < bp->cp_nr_rings; i++) {
7729 int map_idx = bnxt_cp_num_to_irq_num(bp, i);
7731 irq = &bp->irq_tbl[map_idx];
7732 if (irq->requested) {
7733 if (irq->have_cpumask) {
7734 irq_set_affinity_hint(irq->vector, NULL);
7735 free_cpumask_var(irq->cpu_mask);
7736 irq->have_cpumask = 0;
7738 free_irq(irq->vector, bp->bnapi[i]);
7745 static int bnxt_request_irq(struct bnxt *bp)
7748 unsigned long flags = 0;
7749 #ifdef CONFIG_RFS_ACCEL
7750 struct cpu_rmap *rmap;
7753 rc = bnxt_setup_int_mode(bp);
7755 netdev_err(bp->dev, "bnxt_setup_int_mode err: %x\n",
7759 #ifdef CONFIG_RFS_ACCEL
7760 rmap = bp->dev->rx_cpu_rmap;
7762 if (!(bp->flags & BNXT_FLAG_USING_MSIX))
7763 flags = IRQF_SHARED;
7765 for (i = 0, j = 0; i < bp->cp_nr_rings; i++) {
7766 int map_idx = bnxt_cp_num_to_irq_num(bp, i);
7767 struct bnxt_irq *irq = &bp->irq_tbl[map_idx];
7769 #ifdef CONFIG_RFS_ACCEL
7770 if (rmap && bp->bnapi[i]->rx_ring) {
7771 rc = irq_cpu_rmap_add(rmap, irq->vector);
7773 netdev_warn(bp->dev, "failed adding irq rmap for ring %d\n",
7778 rc = request_irq(irq->vector, irq->handler, flags, irq->name,
7785 if (zalloc_cpumask_var(&irq->cpu_mask, GFP_KERNEL)) {
7786 int numa_node = dev_to_node(&bp->pdev->dev);
7788 irq->have_cpumask = 1;
7789 cpumask_set_cpu(cpumask_local_spread(i, numa_node),
7791 rc = irq_set_affinity_hint(irq->vector, irq->cpu_mask);
7793 netdev_warn(bp->dev,
7794 "Set affinity failed, IRQ = %d\n",
7803 static void bnxt_del_napi(struct bnxt *bp)
7810 for (i = 0; i < bp->cp_nr_rings; i++) {
7811 struct bnxt_napi *bnapi = bp->bnapi[i];
7813 napi_hash_del(&bnapi->napi);
7814 netif_napi_del(&bnapi->napi);
7816 /* We called napi_hash_del() before netif_napi_del(), we need
7817 * to respect an RCU grace period before freeing napi structures.
7822 static void bnxt_init_napi(struct bnxt *bp)
7825 unsigned int cp_nr_rings = bp->cp_nr_rings;
7826 struct bnxt_napi *bnapi;
7828 if (bp->flags & BNXT_FLAG_USING_MSIX) {
7829 int (*poll_fn)(struct napi_struct *, int) = bnxt_poll;
7831 if (bp->flags & BNXT_FLAG_CHIP_P5)
7832 poll_fn = bnxt_poll_p5;
7833 else if (BNXT_CHIP_TYPE_NITRO_A0(bp))
7835 for (i = 0; i < cp_nr_rings; i++) {
7836 bnapi = bp->bnapi[i];
7837 netif_napi_add(bp->dev, &bnapi->napi, poll_fn, 64);
7839 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) {
7840 bnapi = bp->bnapi[cp_nr_rings];
7841 netif_napi_add(bp->dev, &bnapi->napi,
7842 bnxt_poll_nitroa0, 64);
7845 bnapi = bp->bnapi[0];
7846 netif_napi_add(bp->dev, &bnapi->napi, bnxt_poll, 64);
7850 static void bnxt_disable_napi(struct bnxt *bp)
7857 for (i = 0; i < bp->cp_nr_rings; i++) {
7858 struct bnxt_cp_ring_info *cpr = &bp->bnapi[i]->cp_ring;
7860 if (bp->bnapi[i]->rx_ring)
7861 cancel_work_sync(&cpr->dim.work);
7863 napi_disable(&bp->bnapi[i]->napi);
7867 static void bnxt_enable_napi(struct bnxt *bp)
7871 for (i = 0; i < bp->cp_nr_rings; i++) {
7872 struct bnxt_cp_ring_info *cpr = &bp->bnapi[i]->cp_ring;
7873 bp->bnapi[i]->in_reset = false;
7875 if (bp->bnapi[i]->rx_ring) {
7876 INIT_WORK(&cpr->dim.work, bnxt_dim_work);
7877 cpr->dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE;
7879 napi_enable(&bp->bnapi[i]->napi);
7883 void bnxt_tx_disable(struct bnxt *bp)
7886 struct bnxt_tx_ring_info *txr;
7889 for (i = 0; i < bp->tx_nr_rings; i++) {
7890 txr = &bp->tx_ring[i];
7891 txr->dev_state = BNXT_DEV_STATE_CLOSING;
7894 /* Stop all TX queues */
7895 netif_tx_disable(bp->dev);
7896 netif_carrier_off(bp->dev);
7899 void bnxt_tx_enable(struct bnxt *bp)
7902 struct bnxt_tx_ring_info *txr;
7904 for (i = 0; i < bp->tx_nr_rings; i++) {
7905 txr = &bp->tx_ring[i];
7908 netif_tx_wake_all_queues(bp->dev);
7909 if (bp->link_info.link_up)
7910 netif_carrier_on(bp->dev);
7913 static void bnxt_report_link(struct bnxt *bp)
7915 if (bp->link_info.link_up) {
7917 const char *flow_ctrl;
7921 netif_carrier_on(bp->dev);
7922 if (bp->link_info.duplex == BNXT_LINK_DUPLEX_FULL)
7926 if (bp->link_info.pause == BNXT_LINK_PAUSE_BOTH)
7927 flow_ctrl = "ON - receive & transmit";
7928 else if (bp->link_info.pause == BNXT_LINK_PAUSE_TX)
7929 flow_ctrl = "ON - transmit";
7930 else if (bp->link_info.pause == BNXT_LINK_PAUSE_RX)
7931 flow_ctrl = "ON - receive";
7934 speed = bnxt_fw_to_ethtool_speed(bp->link_info.link_speed);
7935 netdev_info(bp->dev, "NIC Link is Up, %u Mbps %s duplex, Flow control: %s\n",
7936 speed, duplex, flow_ctrl);
7937 if (bp->flags & BNXT_FLAG_EEE_CAP)
7938 netdev_info(bp->dev, "EEE is %s\n",
7939 bp->eee.eee_active ? "active" :
7941 fec = bp->link_info.fec_cfg;
7942 if (!(fec & PORT_PHY_QCFG_RESP_FEC_CFG_FEC_NONE_SUPPORTED))
7943 netdev_info(bp->dev, "FEC autoneg %s encodings: %s\n",
7944 (fec & BNXT_FEC_AUTONEG) ? "on" : "off",
7945 (fec & BNXT_FEC_ENC_BASE_R) ? "BaseR" :
7946 (fec & BNXT_FEC_ENC_RS) ? "RS" : "None");
7948 netif_carrier_off(bp->dev);
7949 netdev_err(bp->dev, "NIC Link is Down\n");
7953 static int bnxt_hwrm_phy_qcaps(struct bnxt *bp)
7956 struct hwrm_port_phy_qcaps_input req = {0};
7957 struct hwrm_port_phy_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
7958 struct bnxt_link_info *link_info = &bp->link_info;
7960 if (bp->hwrm_spec_code < 0x10201)
7963 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_QCAPS, -1, -1);
7965 mutex_lock(&bp->hwrm_cmd_lock);
7966 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
7968 goto hwrm_phy_qcaps_exit;
7970 if (resp->flags & PORT_PHY_QCAPS_RESP_FLAGS_EEE_SUPPORTED) {
7971 struct ethtool_eee *eee = &bp->eee;
7972 u16 fw_speeds = le16_to_cpu(resp->supported_speeds_eee_mode);
7974 bp->flags |= BNXT_FLAG_EEE_CAP;
7975 eee->supported = _bnxt_fw_to_ethtool_adv_spds(fw_speeds, 0);
7976 bp->lpi_tmr_lo = le32_to_cpu(resp->tx_lpi_timer_low) &
7977 PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_LOW_MASK;
7978 bp->lpi_tmr_hi = le32_to_cpu(resp->valid_tx_lpi_timer_high) &
7979 PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_HIGH_MASK;
7981 if (resp->flags & PORT_PHY_QCAPS_RESP_FLAGS_EXTERNAL_LPBK_SUPPORTED) {
7983 bp->test_info->flags |= BNXT_TEST_FL_EXT_LPBK;
7985 if (resp->supported_speeds_auto_mode)
7986 link_info->support_auto_speeds =
7987 le16_to_cpu(resp->supported_speeds_auto_mode);
7989 bp->port_count = resp->port_cnt;
7991 hwrm_phy_qcaps_exit:
7992 mutex_unlock(&bp->hwrm_cmd_lock);
7996 static int bnxt_update_link(struct bnxt *bp, bool chng_link_state)
7999 struct bnxt_link_info *link_info = &bp->link_info;
8000 struct hwrm_port_phy_qcfg_input req = {0};
8001 struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
8002 u8 link_up = link_info->link_up;
8005 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_QCFG, -1, -1);
8007 mutex_lock(&bp->hwrm_cmd_lock);
8008 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
8010 mutex_unlock(&bp->hwrm_cmd_lock);
8014 memcpy(&link_info->phy_qcfg_resp, resp, sizeof(*resp));
8015 link_info->phy_link_status = resp->link;
8016 link_info->duplex = resp->duplex_cfg;
8017 if (bp->hwrm_spec_code >= 0x10800)
8018 link_info->duplex = resp->duplex_state;
8019 link_info->pause = resp->pause;
8020 link_info->auto_mode = resp->auto_mode;
8021 link_info->auto_pause_setting = resp->auto_pause;
8022 link_info->lp_pause = resp->link_partner_adv_pause;
8023 link_info->force_pause_setting = resp->force_pause;
8024 link_info->duplex_setting = resp->duplex_cfg;
8025 if (link_info->phy_link_status == BNXT_LINK_LINK)
8026 link_info->link_speed = le16_to_cpu(resp->link_speed);
8028 link_info->link_speed = 0;
8029 link_info->force_link_speed = le16_to_cpu(resp->force_link_speed);
8030 link_info->support_speeds = le16_to_cpu(resp->support_speeds);
8031 link_info->auto_link_speeds = le16_to_cpu(resp->auto_link_speed_mask);
8032 link_info->lp_auto_link_speeds =
8033 le16_to_cpu(resp->link_partner_adv_speeds);
8034 link_info->preemphasis = le32_to_cpu(resp->preemphasis);
8035 link_info->phy_ver[0] = resp->phy_maj;
8036 link_info->phy_ver[1] = resp->phy_min;
8037 link_info->phy_ver[2] = resp->phy_bld;
8038 link_info->media_type = resp->media_type;
8039 link_info->phy_type = resp->phy_type;
8040 link_info->transceiver = resp->xcvr_pkg_type;
8041 link_info->phy_addr = resp->eee_config_phy_addr &
8042 PORT_PHY_QCFG_RESP_PHY_ADDR_MASK;
8043 link_info->module_status = resp->module_status;
8045 if (bp->flags & BNXT_FLAG_EEE_CAP) {
8046 struct ethtool_eee *eee = &bp->eee;
8049 eee->eee_active = 0;
8050 if (resp->eee_config_phy_addr &
8051 PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ACTIVE) {
8052 eee->eee_active = 1;
8053 fw_speeds = le16_to_cpu(
8054 resp->link_partner_adv_eee_link_speed_mask);
8055 eee->lp_advertised =
8056 _bnxt_fw_to_ethtool_adv_spds(fw_speeds, 0);
8059 /* Pull initial EEE config */
8060 if (!chng_link_state) {
8061 if (resp->eee_config_phy_addr &
8062 PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ENABLED)
8063 eee->eee_enabled = 1;
8065 fw_speeds = le16_to_cpu(resp->adv_eee_link_speed_mask);
8067 _bnxt_fw_to_ethtool_adv_spds(fw_speeds, 0);
8069 if (resp->eee_config_phy_addr &
8070 PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_TX_LPI) {
8073 eee->tx_lpi_enabled = 1;
8074 tmr = resp->xcvr_identifier_type_tx_lpi_timer;
8075 eee->tx_lpi_timer = le32_to_cpu(tmr) &
8076 PORT_PHY_QCFG_RESP_TX_LPI_TIMER_MASK;
8081 link_info->fec_cfg = PORT_PHY_QCFG_RESP_FEC_CFG_FEC_NONE_SUPPORTED;
8082 if (bp->hwrm_spec_code >= 0x10504)
8083 link_info->fec_cfg = le16_to_cpu(resp->fec_cfg);
8085 /* TODO: need to add more logic to report VF link */
8086 if (chng_link_state) {
8087 if (link_info->phy_link_status == BNXT_LINK_LINK)
8088 link_info->link_up = 1;
8090 link_info->link_up = 0;
8091 if (link_up != link_info->link_up)
8092 bnxt_report_link(bp);
8094 /* alwasy link down if not require to update link state */
8095 link_info->link_up = 0;
8097 mutex_unlock(&bp->hwrm_cmd_lock);
8099 if (!BNXT_SINGLE_PF(bp))
8102 diff = link_info->support_auto_speeds ^ link_info->advertising;
8103 if ((link_info->support_auto_speeds | diff) !=
8104 link_info->support_auto_speeds) {
8105 /* An advertised speed is no longer supported, so we need to
8106 * update the advertisement settings. Caller holds RTNL
8107 * so we can modify link settings.
8109 link_info->advertising = link_info->support_auto_speeds;
8110 if (link_info->autoneg & BNXT_AUTONEG_SPEED)
8111 bnxt_hwrm_set_link_setting(bp, true, false);
8116 static void bnxt_get_port_module_status(struct bnxt *bp)
8118 struct bnxt_link_info *link_info = &bp->link_info;
8119 struct hwrm_port_phy_qcfg_output *resp = &link_info->phy_qcfg_resp;
8122 if (bnxt_update_link(bp, true))
8125 module_status = link_info->module_status;
8126 switch (module_status) {
8127 case PORT_PHY_QCFG_RESP_MODULE_STATUS_DISABLETX:
8128 case PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN:
8129 case PORT_PHY_QCFG_RESP_MODULE_STATUS_WARNINGMSG:
8130 netdev_warn(bp->dev, "Unqualified SFP+ module detected on port %d\n",
8132 if (bp->hwrm_spec_code >= 0x10201) {
8133 netdev_warn(bp->dev, "Module part number %s\n",
8134 resp->phy_vendor_partnumber);
8136 if (module_status == PORT_PHY_QCFG_RESP_MODULE_STATUS_DISABLETX)
8137 netdev_warn(bp->dev, "TX is disabled\n");
8138 if (module_status == PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN)
8139 netdev_warn(bp->dev, "SFP+ module is shutdown\n");
8144 bnxt_hwrm_set_pause_common(struct bnxt *bp, struct hwrm_port_phy_cfg_input *req)
8146 if (bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL) {
8147 if (bp->hwrm_spec_code >= 0x10201)
8149 PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE;
8150 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_RX)
8151 req->auto_pause |= PORT_PHY_CFG_REQ_AUTO_PAUSE_RX;
8152 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_TX)
8153 req->auto_pause |= PORT_PHY_CFG_REQ_AUTO_PAUSE_TX;
8155 cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE);
8157 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_RX)
8158 req->force_pause |= PORT_PHY_CFG_REQ_FORCE_PAUSE_RX;
8159 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_TX)
8160 req->force_pause |= PORT_PHY_CFG_REQ_FORCE_PAUSE_TX;
8162 cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_FORCE_PAUSE);
8163 if (bp->hwrm_spec_code >= 0x10201) {
8164 req->auto_pause = req->force_pause;
8165 req->enables |= cpu_to_le32(
8166 PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE);
8171 static void bnxt_hwrm_set_link_common(struct bnxt *bp,
8172 struct hwrm_port_phy_cfg_input *req)
8174 u8 autoneg = bp->link_info.autoneg;
8175 u16 fw_link_speed = bp->link_info.req_link_speed;
8176 u16 advertising = bp->link_info.advertising;
8178 if (autoneg & BNXT_AUTONEG_SPEED) {
8180 PORT_PHY_CFG_REQ_AUTO_MODE_SPEED_MASK;
8182 req->enables |= cpu_to_le32(
8183 PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED_MASK);
8184 req->auto_link_speed_mask = cpu_to_le16(advertising);
8186 req->enables |= cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_MODE);
8188 cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_RESTART_AUTONEG);
8190 req->force_link_speed = cpu_to_le16(fw_link_speed);
8191 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_FORCE);
8194 /* tell chimp that the setting takes effect immediately */
8195 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_RESET_PHY);
8198 int bnxt_hwrm_set_pause(struct bnxt *bp)
8200 struct hwrm_port_phy_cfg_input req = {0};
8203 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1);
8204 bnxt_hwrm_set_pause_common(bp, &req);
8206 if ((bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL) ||
8207 bp->link_info.force_link_chng)
8208 bnxt_hwrm_set_link_common(bp, &req);
8210 mutex_lock(&bp->hwrm_cmd_lock);
8211 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
8212 if (!rc && !(bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL)) {
8213 /* since changing of pause setting doesn't trigger any link
8214 * change event, the driver needs to update the current pause
8215 * result upon successfully return of the phy_cfg command
8217 bp->link_info.pause =
8218 bp->link_info.force_pause_setting = bp->link_info.req_flow_ctrl;
8219 bp->link_info.auto_pause_setting = 0;
8220 if (!bp->link_info.force_link_chng)
8221 bnxt_report_link(bp);
8223 bp->link_info.force_link_chng = false;
8224 mutex_unlock(&bp->hwrm_cmd_lock);
8228 static void bnxt_hwrm_set_eee(struct bnxt *bp,
8229 struct hwrm_port_phy_cfg_input *req)
8231 struct ethtool_eee *eee = &bp->eee;
8233 if (eee->eee_enabled) {
8235 u32 flags = PORT_PHY_CFG_REQ_FLAGS_EEE_ENABLE;
8237 if (eee->tx_lpi_enabled)
8238 flags |= PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_ENABLE;
8240 flags |= PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_DISABLE;
8242 req->flags |= cpu_to_le32(flags);
8243 eee_speeds = bnxt_get_fw_auto_link_speeds(eee->advertised);
8244 req->eee_link_speed_mask = cpu_to_le16(eee_speeds);
8245 req->tx_lpi_timer = cpu_to_le32(eee->tx_lpi_timer);
8247 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_EEE_DISABLE);
8251 int bnxt_hwrm_set_link_setting(struct bnxt *bp, bool set_pause, bool set_eee)
8253 struct hwrm_port_phy_cfg_input req = {0};
8255 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1);
8257 bnxt_hwrm_set_pause_common(bp, &req);
8259 bnxt_hwrm_set_link_common(bp, &req);
8262 bnxt_hwrm_set_eee(bp, &req);
8263 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
8266 static int bnxt_hwrm_shutdown_link(struct bnxt *bp)
8268 struct hwrm_port_phy_cfg_input req = {0};
8270 if (!BNXT_SINGLE_PF(bp))
8273 if (pci_num_vf(bp->pdev))
8276 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1);
8277 req.flags = cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_FORCE_LINK_DWN);
8278 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
8281 static int bnxt_hwrm_if_change(struct bnxt *bp, bool up)
8283 struct hwrm_func_drv_if_change_output *resp = bp->hwrm_cmd_resp_addr;
8284 struct hwrm_func_drv_if_change_input req = {0};
8285 bool resc_reinit = false;
8288 if (!(bp->fw_cap & BNXT_FW_CAP_IF_CHANGE))
8291 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_IF_CHANGE, -1, -1);
8293 req.flags = cpu_to_le32(FUNC_DRV_IF_CHANGE_REQ_FLAGS_UP);
8294 mutex_lock(&bp->hwrm_cmd_lock);
8295 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
8296 if (!rc && (resp->flags &
8297 cpu_to_le32(FUNC_DRV_IF_CHANGE_RESP_FLAGS_RESC_CHANGE)))
8299 mutex_unlock(&bp->hwrm_cmd_lock);
8301 if (up && resc_reinit && BNXT_NEW_RM(bp)) {
8302 struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
8304 rc = bnxt_hwrm_func_resc_qcaps(bp, true);
8305 hw_resc->resv_cp_rings = 0;
8306 hw_resc->resv_stat_ctxs = 0;
8307 hw_resc->resv_irqs = 0;
8308 hw_resc->resv_tx_rings = 0;
8309 hw_resc->resv_rx_rings = 0;
8310 hw_resc->resv_hw_ring_grps = 0;
8311 hw_resc->resv_vnics = 0;
8312 bp->tx_nr_rings = 0;
8313 bp->rx_nr_rings = 0;
8318 static int bnxt_hwrm_port_led_qcaps(struct bnxt *bp)
8320 struct hwrm_port_led_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
8321 struct hwrm_port_led_qcaps_input req = {0};
8322 struct bnxt_pf_info *pf = &bp->pf;
8325 if (BNXT_VF(bp) || bp->hwrm_spec_code < 0x10601)
8328 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_LED_QCAPS, -1, -1);
8329 req.port_id = cpu_to_le16(pf->port_id);
8330 mutex_lock(&bp->hwrm_cmd_lock);
8331 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
8333 mutex_unlock(&bp->hwrm_cmd_lock);
8336 if (resp->num_leds > 0 && resp->num_leds < BNXT_MAX_LED) {
8339 bp->num_leds = resp->num_leds;
8340 memcpy(bp->leds, &resp->led0_id, sizeof(bp->leds[0]) *
8342 for (i = 0; i < bp->num_leds; i++) {
8343 struct bnxt_led_info *led = &bp->leds[i];
8344 __le16 caps = led->led_state_caps;
8346 if (!led->led_group_id ||
8347 !BNXT_LED_ALT_BLINK_CAP(caps)) {
8353 mutex_unlock(&bp->hwrm_cmd_lock);
8357 int bnxt_hwrm_alloc_wol_fltr(struct bnxt *bp)
8359 struct hwrm_wol_filter_alloc_input req = {0};
8360 struct hwrm_wol_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
8363 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_WOL_FILTER_ALLOC, -1, -1);
8364 req.port_id = cpu_to_le16(bp->pf.port_id);
8365 req.wol_type = WOL_FILTER_ALLOC_REQ_WOL_TYPE_MAGICPKT;
8366 req.enables = cpu_to_le32(WOL_FILTER_ALLOC_REQ_ENABLES_MAC_ADDRESS);
8367 memcpy(req.mac_address, bp->dev->dev_addr, ETH_ALEN);
8368 mutex_lock(&bp->hwrm_cmd_lock);
8369 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
8371 bp->wol_filter_id = resp->wol_filter_id;
8372 mutex_unlock(&bp->hwrm_cmd_lock);
8376 int bnxt_hwrm_free_wol_fltr(struct bnxt *bp)
8378 struct hwrm_wol_filter_free_input req = {0};
8381 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_WOL_FILTER_FREE, -1, -1);
8382 req.port_id = cpu_to_le16(bp->pf.port_id);
8383 req.enables = cpu_to_le32(WOL_FILTER_FREE_REQ_ENABLES_WOL_FILTER_ID);
8384 req.wol_filter_id = bp->wol_filter_id;
8385 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
8389 static u16 bnxt_hwrm_get_wol_fltrs(struct bnxt *bp, u16 handle)
8391 struct hwrm_wol_filter_qcfg_input req = {0};
8392 struct hwrm_wol_filter_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
8393 u16 next_handle = 0;
8396 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_WOL_FILTER_QCFG, -1, -1);
8397 req.port_id = cpu_to_le16(bp->pf.port_id);
8398 req.handle = cpu_to_le16(handle);
8399 mutex_lock(&bp->hwrm_cmd_lock);
8400 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
8402 next_handle = le16_to_cpu(resp->next_handle);
8403 if (next_handle != 0) {
8404 if (resp->wol_type ==
8405 WOL_FILTER_ALLOC_REQ_WOL_TYPE_MAGICPKT) {
8407 bp->wol_filter_id = resp->wol_filter_id;
8411 mutex_unlock(&bp->hwrm_cmd_lock);
8415 static void bnxt_get_wol_settings(struct bnxt *bp)
8419 if (!BNXT_PF(bp) || !(bp->flags & BNXT_FLAG_WOL_CAP))
8423 handle = bnxt_hwrm_get_wol_fltrs(bp, handle);
8424 } while (handle && handle != 0xffff);
8427 #ifdef CONFIG_BNXT_HWMON
8428 static ssize_t bnxt_show_temp(struct device *dev,
8429 struct device_attribute *devattr, char *buf)
8431 struct hwrm_temp_monitor_query_input req = {0};
8432 struct hwrm_temp_monitor_query_output *resp;
8433 struct bnxt *bp = dev_get_drvdata(dev);
8436 resp = bp->hwrm_cmd_resp_addr;
8437 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_TEMP_MONITOR_QUERY, -1, -1);
8438 mutex_lock(&bp->hwrm_cmd_lock);
8439 if (!_hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT))
8440 temp = resp->temp * 1000; /* display millidegree */
8441 mutex_unlock(&bp->hwrm_cmd_lock);
8443 return sprintf(buf, "%u\n", temp);
8445 static SENSOR_DEVICE_ATTR(temp1_input, 0444, bnxt_show_temp, NULL, 0);
8447 static struct attribute *bnxt_attrs[] = {
8448 &sensor_dev_attr_temp1_input.dev_attr.attr,
8451 ATTRIBUTE_GROUPS(bnxt);
8453 static void bnxt_hwmon_close(struct bnxt *bp)
8455 if (bp->hwmon_dev) {
8456 hwmon_device_unregister(bp->hwmon_dev);
8457 bp->hwmon_dev = NULL;
8461 static void bnxt_hwmon_open(struct bnxt *bp)
8463 struct pci_dev *pdev = bp->pdev;
8465 bp->hwmon_dev = hwmon_device_register_with_groups(&pdev->dev,
8466 DRV_MODULE_NAME, bp,
8468 if (IS_ERR(bp->hwmon_dev)) {
8469 bp->hwmon_dev = NULL;
8470 dev_warn(&pdev->dev, "Cannot register hwmon device\n");
8474 static void bnxt_hwmon_close(struct bnxt *bp)
8478 static void bnxt_hwmon_open(struct bnxt *bp)
8483 static bool bnxt_eee_config_ok(struct bnxt *bp)
8485 struct ethtool_eee *eee = &bp->eee;
8486 struct bnxt_link_info *link_info = &bp->link_info;
8488 if (!(bp->flags & BNXT_FLAG_EEE_CAP))
8491 if (eee->eee_enabled) {
8493 _bnxt_fw_to_ethtool_adv_spds(link_info->advertising, 0);
8495 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) {
8496 eee->eee_enabled = 0;
8499 if (eee->advertised & ~advertising) {
8500 eee->advertised = advertising & eee->supported;
8507 static int bnxt_update_phy_setting(struct bnxt *bp)
8510 bool update_link = false;
8511 bool update_pause = false;
8512 bool update_eee = false;
8513 struct bnxt_link_info *link_info = &bp->link_info;
8515 rc = bnxt_update_link(bp, true);
8517 netdev_err(bp->dev, "failed to update link (rc: %x)\n",
8521 if (!BNXT_SINGLE_PF(bp))
8524 if ((link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) &&
8525 (link_info->auto_pause_setting & BNXT_LINK_PAUSE_BOTH) !=
8526 link_info->req_flow_ctrl)
8527 update_pause = true;
8528 if (!(link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) &&
8529 link_info->force_pause_setting != link_info->req_flow_ctrl)
8530 update_pause = true;
8531 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) {
8532 if (BNXT_AUTO_MODE(link_info->auto_mode))
8534 if (link_info->req_link_speed != link_info->force_link_speed)
8536 if (link_info->req_duplex != link_info->duplex_setting)
8539 if (link_info->auto_mode == BNXT_LINK_AUTO_NONE)
8541 if (link_info->advertising != link_info->auto_link_speeds)
8545 /* The last close may have shutdown the link, so need to call
8546 * PHY_CFG to bring it back up.
8548 if (!netif_carrier_ok(bp->dev))
8551 if (!bnxt_eee_config_ok(bp))
8555 rc = bnxt_hwrm_set_link_setting(bp, update_pause, update_eee);
8556 else if (update_pause)
8557 rc = bnxt_hwrm_set_pause(bp);
8559 netdev_err(bp->dev, "failed to update phy setting (rc: %x)\n",
8567 /* Common routine to pre-map certain register block to different GRC window.
8568 * A PF has 16 4K windows and a VF has 4 4K windows. However, only 15 windows
8569 * in PF and 3 windows in VF that can be customized to map in different
8572 static void bnxt_preset_reg_win(struct bnxt *bp)
8575 /* CAG registers map to GRC window #4 */
8576 writel(BNXT_CAG_REG_BASE,
8577 bp->bar0 + BNXT_GRCPF_REG_WINDOW_BASE_OUT + 12);
8581 static int bnxt_init_dflt_ring_mode(struct bnxt *bp);
8583 static int __bnxt_open_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init)
8587 bnxt_preset_reg_win(bp);
8588 netif_carrier_off(bp->dev);
8590 /* Reserve rings now if none were reserved at driver probe. */
8591 rc = bnxt_init_dflt_ring_mode(bp);
8593 netdev_err(bp->dev, "Failed to reserve default rings at open\n");
8597 rc = bnxt_reserve_rings(bp, irq_re_init);
8600 if ((bp->flags & BNXT_FLAG_RFS) &&
8601 !(bp->flags & BNXT_FLAG_USING_MSIX)) {
8602 /* disable RFS if falling back to INTA */
8603 bp->dev->hw_features &= ~NETIF_F_NTUPLE;
8604 bp->flags &= ~BNXT_FLAG_RFS;
8607 rc = bnxt_alloc_mem(bp, irq_re_init);
8609 netdev_err(bp->dev, "bnxt_alloc_mem err: %x\n", rc);
8610 goto open_err_free_mem;
8615 rc = bnxt_request_irq(bp);
8617 netdev_err(bp->dev, "bnxt_request_irq err: %x\n", rc);
8622 bnxt_enable_napi(bp);
8623 bnxt_debug_dev_init(bp);
8625 rc = bnxt_init_nic(bp, irq_re_init);
8627 netdev_err(bp->dev, "bnxt_init_nic err: %x\n", rc);
8632 mutex_lock(&bp->link_lock);
8633 rc = bnxt_update_phy_setting(bp);
8634 mutex_unlock(&bp->link_lock);
8636 netdev_warn(bp->dev, "failed to update phy settings\n");
8637 if (BNXT_SINGLE_PF(bp)) {
8638 bp->link_info.phy_retry = true;
8639 bp->link_info.phy_retry_expires =
8646 udp_tunnel_get_rx_info(bp->dev);
8648 set_bit(BNXT_STATE_OPEN, &bp->state);
8649 bnxt_enable_int(bp);
8650 /* Enable TX queues */
8652 mod_timer(&bp->timer, jiffies + bp->current_interval);
8653 /* Poll link status and check for SFP+ module status */
8654 bnxt_get_port_module_status(bp);
8656 /* VF-reps may need to be re-opened after the PF is re-opened */
8658 bnxt_vf_reps_open(bp);
8662 bnxt_debug_dev_exit(bp);
8663 bnxt_disable_napi(bp);
8671 bnxt_free_mem(bp, true);
8675 /* rtnl_lock held */
8676 int bnxt_open_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init)
8680 rc = __bnxt_open_nic(bp, irq_re_init, link_re_init);
8682 netdev_err(bp->dev, "nic open fail (rc: %x)\n", rc);
8688 /* rtnl_lock held, open the NIC half way by allocating all resources, but
8689 * NAPI, IRQ, and TX are not enabled. This is mainly used for offline
8692 int bnxt_half_open_nic(struct bnxt *bp)
8696 rc = bnxt_alloc_mem(bp, false);
8698 netdev_err(bp->dev, "bnxt_alloc_mem err: %x\n", rc);
8701 rc = bnxt_init_nic(bp, false);
8703 netdev_err(bp->dev, "bnxt_init_nic err: %x\n", rc);
8710 bnxt_free_mem(bp, false);
8715 /* rtnl_lock held, this call can only be made after a previous successful
8716 * call to bnxt_half_open_nic().
8718 void bnxt_half_close_nic(struct bnxt *bp)
8720 bnxt_hwrm_resource_free(bp, false, false);
8722 bnxt_free_mem(bp, false);
8725 static int bnxt_open(struct net_device *dev)
8727 struct bnxt *bp = netdev_priv(dev);
8730 bnxt_hwrm_if_change(bp, true);
8731 rc = __bnxt_open_nic(bp, true, true);
8733 bnxt_hwrm_if_change(bp, false);
8735 bnxt_hwmon_open(bp);
8740 static bool bnxt_drv_busy(struct bnxt *bp)
8742 return (test_bit(BNXT_STATE_IN_SP_TASK, &bp->state) ||
8743 test_bit(BNXT_STATE_READ_STATS, &bp->state));
8746 static void bnxt_get_ring_stats(struct bnxt *bp,
8747 struct rtnl_link_stats64 *stats);
8749 static void __bnxt_close_nic(struct bnxt *bp, bool irq_re_init,
8752 /* Close the VF-reps before closing PF */
8754 bnxt_vf_reps_close(bp);
8756 /* Change device state to avoid TX queue wake up's */
8757 bnxt_tx_disable(bp);
8759 clear_bit(BNXT_STATE_OPEN, &bp->state);
8760 smp_mb__after_atomic();
8761 while (bnxt_drv_busy(bp))
8764 /* Flush rings and and disable interrupts */
8765 bnxt_shutdown_nic(bp, irq_re_init);
8767 /* TODO CHIMP_FW: Link/PHY related cleanup if (link_re_init) */
8769 bnxt_debug_dev_exit(bp);
8770 bnxt_disable_napi(bp);
8771 del_timer_sync(&bp->timer);
8774 /* Save ring stats before shutdown */
8776 bnxt_get_ring_stats(bp, &bp->net_stats_prev);
8781 bnxt_free_mem(bp, irq_re_init);
8784 int bnxt_close_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init)
8788 #ifdef CONFIG_BNXT_SRIOV
8789 if (bp->sriov_cfg) {
8790 rc = wait_event_interruptible_timeout(bp->sriov_cfg_wait,
8792 BNXT_SRIOV_CFG_WAIT_TMO);
8794 netdev_warn(bp->dev, "timeout waiting for SRIOV config operation to complete!\n");
8797 __bnxt_close_nic(bp, irq_re_init, link_re_init);
8801 static int bnxt_close(struct net_device *dev)
8803 struct bnxt *bp = netdev_priv(dev);
8805 bnxt_hwmon_close(bp);
8806 bnxt_close_nic(bp, true, true);
8807 bnxt_hwrm_shutdown_link(bp);
8808 bnxt_hwrm_if_change(bp, false);
8812 static int bnxt_hwrm_port_phy_read(struct bnxt *bp, u16 phy_addr, u16 reg,
8815 struct hwrm_port_phy_mdio_read_output *resp = bp->hwrm_cmd_resp_addr;
8816 struct hwrm_port_phy_mdio_read_input req = {0};
8819 if (bp->hwrm_spec_code < 0x10a00)
8822 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_MDIO_READ, -1, -1);
8823 req.port_id = cpu_to_le16(bp->pf.port_id);
8824 req.phy_addr = phy_addr;
8825 req.reg_addr = cpu_to_le16(reg & 0x1f);
8826 if (mdio_phy_id_is_c45(phy_addr)) {
8828 req.phy_addr = mdio_phy_id_prtad(phy_addr);
8829 req.dev_addr = mdio_phy_id_devad(phy_addr);
8830 req.reg_addr = cpu_to_le16(reg);
8833 mutex_lock(&bp->hwrm_cmd_lock);
8834 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
8836 *val = le16_to_cpu(resp->reg_data);
8837 mutex_unlock(&bp->hwrm_cmd_lock);
8841 static int bnxt_hwrm_port_phy_write(struct bnxt *bp, u16 phy_addr, u16 reg,
8844 struct hwrm_port_phy_mdio_write_input req = {0};
8846 if (bp->hwrm_spec_code < 0x10a00)
8849 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_MDIO_WRITE, -1, -1);
8850 req.port_id = cpu_to_le16(bp->pf.port_id);
8851 req.phy_addr = phy_addr;
8852 req.reg_addr = cpu_to_le16(reg & 0x1f);
8853 if (mdio_phy_id_is_c45(phy_addr)) {
8855 req.phy_addr = mdio_phy_id_prtad(phy_addr);
8856 req.dev_addr = mdio_phy_id_devad(phy_addr);
8857 req.reg_addr = cpu_to_le16(reg);
8859 req.reg_data = cpu_to_le16(val);
8861 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
8864 /* rtnl_lock held */
8865 static int bnxt_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
8867 struct mii_ioctl_data *mdio = if_mii(ifr);
8868 struct bnxt *bp = netdev_priv(dev);
8873 mdio->phy_id = bp->link_info.phy_addr;
8879 if (!netif_running(dev))
8882 rc = bnxt_hwrm_port_phy_read(bp, mdio->phy_id, mdio->reg_num,
8884 mdio->val_out = mii_regval;
8889 if (!netif_running(dev))
8892 return bnxt_hwrm_port_phy_write(bp, mdio->phy_id, mdio->reg_num,
8902 static void bnxt_get_ring_stats(struct bnxt *bp,
8903 struct rtnl_link_stats64 *stats)
8908 for (i = 0; i < bp->cp_nr_rings; i++) {
8909 struct bnxt_napi *bnapi = bp->bnapi[i];
8910 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
8911 struct ctx_hw_stats *hw_stats = cpr->hw_stats;
8913 stats->rx_packets += le64_to_cpu(hw_stats->rx_ucast_pkts);
8914 stats->rx_packets += le64_to_cpu(hw_stats->rx_mcast_pkts);
8915 stats->rx_packets += le64_to_cpu(hw_stats->rx_bcast_pkts);
8917 stats->tx_packets += le64_to_cpu(hw_stats->tx_ucast_pkts);
8918 stats->tx_packets += le64_to_cpu(hw_stats->tx_mcast_pkts);
8919 stats->tx_packets += le64_to_cpu(hw_stats->tx_bcast_pkts);
8921 stats->rx_bytes += le64_to_cpu(hw_stats->rx_ucast_bytes);
8922 stats->rx_bytes += le64_to_cpu(hw_stats->rx_mcast_bytes);
8923 stats->rx_bytes += le64_to_cpu(hw_stats->rx_bcast_bytes);
8925 stats->tx_bytes += le64_to_cpu(hw_stats->tx_ucast_bytes);
8926 stats->tx_bytes += le64_to_cpu(hw_stats->tx_mcast_bytes);
8927 stats->tx_bytes += le64_to_cpu(hw_stats->tx_bcast_bytes);
8929 stats->rx_missed_errors +=
8930 le64_to_cpu(hw_stats->rx_discard_pkts);
8932 stats->multicast += le64_to_cpu(hw_stats->rx_mcast_pkts);
8934 stats->tx_dropped += le64_to_cpu(hw_stats->tx_drop_pkts);
8938 static void bnxt_add_prev_stats(struct bnxt *bp,
8939 struct rtnl_link_stats64 *stats)
8941 struct rtnl_link_stats64 *prev_stats = &bp->net_stats_prev;
8943 stats->rx_packets += prev_stats->rx_packets;
8944 stats->tx_packets += prev_stats->tx_packets;
8945 stats->rx_bytes += prev_stats->rx_bytes;
8946 stats->tx_bytes += prev_stats->tx_bytes;
8947 stats->rx_missed_errors += prev_stats->rx_missed_errors;
8948 stats->multicast += prev_stats->multicast;
8949 stats->tx_dropped += prev_stats->tx_dropped;
8953 bnxt_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
8955 struct bnxt *bp = netdev_priv(dev);
8957 set_bit(BNXT_STATE_READ_STATS, &bp->state);
8958 /* Make sure bnxt_close_nic() sees that we are reading stats before
8959 * we check the BNXT_STATE_OPEN flag.
8961 smp_mb__after_atomic();
8962 if (!test_bit(BNXT_STATE_OPEN, &bp->state)) {
8963 clear_bit(BNXT_STATE_READ_STATS, &bp->state);
8964 *stats = bp->net_stats_prev;
8968 bnxt_get_ring_stats(bp, stats);
8969 bnxt_add_prev_stats(bp, stats);
8971 if (bp->flags & BNXT_FLAG_PORT_STATS) {
8972 struct rx_port_stats *rx = bp->hw_rx_port_stats;
8973 struct tx_port_stats *tx = bp->hw_tx_port_stats;
8975 stats->rx_crc_errors = le64_to_cpu(rx->rx_fcs_err_frames);
8976 stats->rx_frame_errors = le64_to_cpu(rx->rx_align_err_frames);
8977 stats->rx_length_errors = le64_to_cpu(rx->rx_undrsz_frames) +
8978 le64_to_cpu(rx->rx_ovrsz_frames) +
8979 le64_to_cpu(rx->rx_runt_frames);
8980 stats->rx_errors = le64_to_cpu(rx->rx_false_carrier_frames) +
8981 le64_to_cpu(rx->rx_jbr_frames);
8982 stats->collisions = le64_to_cpu(tx->tx_total_collisions);
8983 stats->tx_fifo_errors = le64_to_cpu(tx->tx_fifo_underruns);
8984 stats->tx_errors = le64_to_cpu(tx->tx_err);
8986 clear_bit(BNXT_STATE_READ_STATS, &bp->state);
8989 static bool bnxt_mc_list_updated(struct bnxt *bp, u32 *rx_mask)
8991 struct net_device *dev = bp->dev;
8992 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
8993 struct netdev_hw_addr *ha;
8996 bool update = false;
8999 netdev_for_each_mc_addr(ha, dev) {
9000 if (mc_count >= BNXT_MAX_MC_ADDRS) {
9001 *rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST;
9002 vnic->mc_list_count = 0;
9006 if (!ether_addr_equal(haddr, vnic->mc_list + off)) {
9007 memcpy(vnic->mc_list + off, haddr, ETH_ALEN);
9014 *rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_MCAST;
9016 if (mc_count != vnic->mc_list_count) {
9017 vnic->mc_list_count = mc_count;
9023 static bool bnxt_uc_list_updated(struct bnxt *bp)
9025 struct net_device *dev = bp->dev;
9026 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
9027 struct netdev_hw_addr *ha;
9030 if (netdev_uc_count(dev) != (vnic->uc_filter_count - 1))
9033 netdev_for_each_uc_addr(ha, dev) {
9034 if (!ether_addr_equal(ha->addr, vnic->uc_list + off))
9042 static void bnxt_set_rx_mode(struct net_device *dev)
9044 struct bnxt *bp = netdev_priv(dev);
9045 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
9046 u32 mask = vnic->rx_mask;
9047 bool mc_update = false;
9050 if (!netif_running(dev))
9053 mask &= ~(CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS |
9054 CFA_L2_SET_RX_MASK_REQ_MASK_MCAST |
9055 CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST |
9056 CFA_L2_SET_RX_MASK_REQ_MASK_BCAST);
9058 if ((dev->flags & IFF_PROMISC) && bnxt_promisc_ok(bp))
9059 mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS;
9061 uc_update = bnxt_uc_list_updated(bp);
9063 if (dev->flags & IFF_BROADCAST)
9064 mask |= CFA_L2_SET_RX_MASK_REQ_MASK_BCAST;
9065 if (dev->flags & IFF_ALLMULTI) {
9066 mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST;
9067 vnic->mc_list_count = 0;
9069 mc_update = bnxt_mc_list_updated(bp, &mask);
9072 if (mask != vnic->rx_mask || uc_update || mc_update) {
9073 vnic->rx_mask = mask;
9075 set_bit(BNXT_RX_MASK_SP_EVENT, &bp->sp_event);
9076 bnxt_queue_sp_work(bp);
9080 static int bnxt_cfg_rx_mode(struct bnxt *bp)
9082 struct net_device *dev = bp->dev;
9083 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
9084 struct netdev_hw_addr *ha;
9088 netif_addr_lock_bh(dev);
9089 uc_update = bnxt_uc_list_updated(bp);
9090 netif_addr_unlock_bh(dev);
9095 mutex_lock(&bp->hwrm_cmd_lock);
9096 for (i = 1; i < vnic->uc_filter_count; i++) {
9097 struct hwrm_cfa_l2_filter_free_input req = {0};
9099 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_FILTER_FREE, -1,
9102 req.l2_filter_id = vnic->fw_l2_filter_id[i];
9104 rc = _hwrm_send_message(bp, &req, sizeof(req),
9107 mutex_unlock(&bp->hwrm_cmd_lock);
9109 vnic->uc_filter_count = 1;
9111 netif_addr_lock_bh(dev);
9112 if (netdev_uc_count(dev) > (BNXT_MAX_UC_ADDRS - 1)) {
9113 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS;
9115 netdev_for_each_uc_addr(ha, dev) {
9116 memcpy(vnic->uc_list + off, ha->addr, ETH_ALEN);
9118 vnic->uc_filter_count++;
9121 netif_addr_unlock_bh(dev);
9123 for (i = 1, off = 0; i < vnic->uc_filter_count; i++, off += ETH_ALEN) {
9124 rc = bnxt_hwrm_set_vnic_filter(bp, 0, i, vnic->uc_list + off);
9126 netdev_err(bp->dev, "HWRM vnic filter failure rc: %x\n",
9128 vnic->uc_filter_count = i;
9134 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, 0);
9135 if (rc && vnic->mc_list_count) {
9136 netdev_info(bp->dev, "Failed setting MC filters rc: %d, turning on ALL_MCAST mode\n",
9138 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST;
9139 vnic->mc_list_count = 0;
9140 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, 0);
9143 netdev_err(bp->dev, "HWRM cfa l2 rx mask failure rc: %d\n",
9149 static bool bnxt_can_reserve_rings(struct bnxt *bp)
9151 #ifdef CONFIG_BNXT_SRIOV
9152 if (BNXT_NEW_RM(bp) && BNXT_VF(bp)) {
9153 struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
9155 /* No minimum rings were provisioned by the PF. Don't
9156 * reserve rings by default when device is down.
9158 if (hw_resc->min_tx_rings || hw_resc->resv_tx_rings)
9161 if (!netif_running(bp->dev))
9168 /* If the chip and firmware supports RFS */
9169 static bool bnxt_rfs_supported(struct bnxt *bp)
9171 if (bp->flags & BNXT_FLAG_CHIP_P5) {
9172 if (bp->fw_cap & BNXT_FW_CAP_CFA_RFS_RING_TBL_IDX)
9176 if (BNXT_PF(bp) && !BNXT_CHIP_TYPE_NITRO_A0(bp))
9178 if (bp->flags & BNXT_FLAG_NEW_RSS_CAP)
9183 /* If runtime conditions support RFS */
9184 static bool bnxt_rfs_capable(struct bnxt *bp)
9186 #ifdef CONFIG_RFS_ACCEL
9187 int vnics, max_vnics, max_rss_ctxs;
9189 if (bp->flags & BNXT_FLAG_CHIP_P5)
9190 return bnxt_rfs_supported(bp);
9191 if (!(bp->flags & BNXT_FLAG_MSIX_CAP) || !bnxt_can_reserve_rings(bp))
9194 vnics = 1 + bp->rx_nr_rings;
9195 max_vnics = bnxt_get_max_func_vnics(bp);
9196 max_rss_ctxs = bnxt_get_max_func_rss_ctxs(bp);
9198 /* RSS contexts not a limiting factor */
9199 if (bp->flags & BNXT_FLAG_NEW_RSS_CAP)
9200 max_rss_ctxs = max_vnics;
9201 if (vnics > max_vnics || vnics > max_rss_ctxs) {
9202 if (bp->rx_nr_rings > 1)
9203 netdev_warn(bp->dev,
9204 "Not enough resources to support NTUPLE filters, enough resources for up to %d rx rings\n",
9205 min(max_rss_ctxs - 1, max_vnics - 1));
9209 if (!BNXT_NEW_RM(bp))
9212 if (vnics == bp->hw_resc.resv_vnics)
9215 bnxt_hwrm_reserve_rings(bp, 0, 0, 0, 0, 0, vnics);
9216 if (vnics <= bp->hw_resc.resv_vnics)
9219 netdev_warn(bp->dev, "Unable to reserve resources to support NTUPLE filters.\n");
9220 bnxt_hwrm_reserve_rings(bp, 0, 0, 0, 0, 0, 1);
9227 static netdev_features_t bnxt_fix_features(struct net_device *dev,
9228 netdev_features_t features)
9230 struct bnxt *bp = netdev_priv(dev);
9232 if ((features & NETIF_F_NTUPLE) && !bnxt_rfs_capable(bp))
9233 features &= ~NETIF_F_NTUPLE;
9235 if (bp->flags & BNXT_FLAG_NO_AGG_RINGS)
9236 features &= ~(NETIF_F_LRO | NETIF_F_GRO_HW);
9238 if (!(features & NETIF_F_GRO))
9239 features &= ~NETIF_F_GRO_HW;
9241 if (features & NETIF_F_GRO_HW)
9242 features &= ~NETIF_F_LRO;
9244 /* Both CTAG and STAG VLAN accelaration on the RX side have to be
9245 * turned on or off together.
9247 if ((features & (NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_STAG_RX)) !=
9248 (NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_STAG_RX)) {
9249 if (dev->features & NETIF_F_HW_VLAN_CTAG_RX)
9250 features &= ~(NETIF_F_HW_VLAN_CTAG_RX |
9251 NETIF_F_HW_VLAN_STAG_RX);
9253 features |= NETIF_F_HW_VLAN_CTAG_RX |
9254 NETIF_F_HW_VLAN_STAG_RX;
9256 #ifdef CONFIG_BNXT_SRIOV
9259 features &= ~(NETIF_F_HW_VLAN_CTAG_RX |
9260 NETIF_F_HW_VLAN_STAG_RX);
9267 static int bnxt_set_features(struct net_device *dev, netdev_features_t features)
9269 struct bnxt *bp = netdev_priv(dev);
9270 u32 flags = bp->flags;
9273 bool re_init = false;
9274 bool update_tpa = false;
9276 flags &= ~BNXT_FLAG_ALL_CONFIG_FEATS;
9277 if (features & NETIF_F_GRO_HW)
9278 flags |= BNXT_FLAG_GRO;
9279 else if (features & NETIF_F_LRO)
9280 flags |= BNXT_FLAG_LRO;
9282 if (bp->flags & BNXT_FLAG_NO_AGG_RINGS)
9283 flags &= ~BNXT_FLAG_TPA;
9285 if (features & NETIF_F_HW_VLAN_CTAG_RX)
9286 flags |= BNXT_FLAG_STRIP_VLAN;
9288 if (features & NETIF_F_NTUPLE)
9289 flags |= BNXT_FLAG_RFS;
9291 changes = flags ^ bp->flags;
9292 if (changes & BNXT_FLAG_TPA) {
9294 if ((bp->flags & BNXT_FLAG_TPA) == 0 ||
9295 (flags & BNXT_FLAG_TPA) == 0)
9299 if (changes & ~BNXT_FLAG_TPA)
9302 if (flags != bp->flags) {
9303 u32 old_flags = bp->flags;
9307 if (!test_bit(BNXT_STATE_OPEN, &bp->state)) {
9309 bnxt_set_ring_params(bp);
9314 bnxt_close_nic(bp, false, false);
9316 bnxt_set_ring_params(bp);
9318 return bnxt_open_nic(bp, false, false);
9321 rc = bnxt_set_tpa(bp,
9322 (flags & BNXT_FLAG_TPA) ?
9325 bp->flags = old_flags;
9331 static int bnxt_dbg_hwrm_ring_info_get(struct bnxt *bp, u8 ring_type,
9332 u32 ring_id, u32 *prod, u32 *cons)
9334 struct hwrm_dbg_ring_info_get_output *resp = bp->hwrm_cmd_resp_addr;
9335 struct hwrm_dbg_ring_info_get_input req = {0};
9338 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_DBG_RING_INFO_GET, -1, -1);
9339 req.ring_type = ring_type;
9340 req.fw_ring_id = cpu_to_le32(ring_id);
9341 mutex_lock(&bp->hwrm_cmd_lock);
9342 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
9344 *prod = le32_to_cpu(resp->producer_index);
9345 *cons = le32_to_cpu(resp->consumer_index);
9347 mutex_unlock(&bp->hwrm_cmd_lock);
9351 static void bnxt_dump_tx_sw_state(struct bnxt_napi *bnapi)
9353 struct bnxt_tx_ring_info *txr = bnapi->tx_ring;
9354 int i = bnapi->index;
9359 netdev_info(bnapi->bp->dev, "[%d]: tx{fw_ring: %d prod: %x cons: %x}\n",
9360 i, txr->tx_ring_struct.fw_ring_id, txr->tx_prod,
9364 static void bnxt_dump_rx_sw_state(struct bnxt_napi *bnapi)
9366 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
9367 int i = bnapi->index;
9372 netdev_info(bnapi->bp->dev, "[%d]: rx{fw_ring: %d prod: %x} rx_agg{fw_ring: %d agg_prod: %x sw_agg_prod: %x}\n",
9373 i, rxr->rx_ring_struct.fw_ring_id, rxr->rx_prod,
9374 rxr->rx_agg_ring_struct.fw_ring_id, rxr->rx_agg_prod,
9375 rxr->rx_sw_agg_prod);
9378 static void bnxt_dump_cp_sw_state(struct bnxt_napi *bnapi)
9380 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
9381 int i = bnapi->index;
9383 netdev_info(bnapi->bp->dev, "[%d]: cp{fw_ring: %d raw_cons: %x}\n",
9384 i, cpr->cp_ring_struct.fw_ring_id, cpr->cp_raw_cons);
9387 static void bnxt_dbg_dump_states(struct bnxt *bp)
9390 struct bnxt_napi *bnapi;
9392 for (i = 0; i < bp->cp_nr_rings; i++) {
9393 bnapi = bp->bnapi[i];
9394 if (netif_msg_drv(bp)) {
9395 bnxt_dump_tx_sw_state(bnapi);
9396 bnxt_dump_rx_sw_state(bnapi);
9397 bnxt_dump_cp_sw_state(bnapi);
9402 static void bnxt_reset_task(struct bnxt *bp, bool silent)
9405 bnxt_dbg_dump_states(bp);
9406 if (netif_running(bp->dev)) {
9411 bnxt_close_nic(bp, false, false);
9412 rc = bnxt_open_nic(bp, false, false);
9418 static void bnxt_tx_timeout(struct net_device *dev)
9420 struct bnxt *bp = netdev_priv(dev);
9422 netdev_err(bp->dev, "TX timeout detected, starting reset task!\n");
9423 set_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event);
9424 bnxt_queue_sp_work(bp);
9427 static void bnxt_timer(struct timer_list *t)
9429 struct bnxt *bp = from_timer(bp, t, timer);
9430 struct net_device *dev = bp->dev;
9432 if (!netif_running(dev))
9435 if (atomic_read(&bp->intr_sem) != 0)
9436 goto bnxt_restart_timer;
9438 if (bp->link_info.link_up && (bp->flags & BNXT_FLAG_PORT_STATS) &&
9439 bp->stats_coal_ticks) {
9440 set_bit(BNXT_PERIODIC_STATS_SP_EVENT, &bp->sp_event);
9441 bnxt_queue_sp_work(bp);
9444 if (bnxt_tc_flower_enabled(bp)) {
9445 set_bit(BNXT_FLOW_STATS_SP_EVENT, &bp->sp_event);
9446 bnxt_queue_sp_work(bp);
9449 if (bp->link_info.phy_retry) {
9450 if (time_after(jiffies, bp->link_info.phy_retry_expires)) {
9451 bp->link_info.phy_retry = 0;
9452 netdev_warn(bp->dev, "failed to update phy settings after maximum retries.\n");
9454 set_bit(BNXT_UPDATE_PHY_SP_EVENT, &bp->sp_event);
9455 bnxt_queue_sp_work(bp);
9459 if ((bp->flags & BNXT_FLAG_CHIP_P5) && netif_carrier_ok(dev)) {
9460 set_bit(BNXT_RING_COAL_NOW_SP_EVENT, &bp->sp_event);
9461 bnxt_queue_sp_work(bp);
9464 mod_timer(&bp->timer, jiffies + bp->current_interval);
9467 static void bnxt_rtnl_lock_sp(struct bnxt *bp)
9469 /* We are called from bnxt_sp_task which has BNXT_STATE_IN_SP_TASK
9470 * set. If the device is being closed, bnxt_close() may be holding
9471 * rtnl() and waiting for BNXT_STATE_IN_SP_TASK to clear. So we
9472 * must clear BNXT_STATE_IN_SP_TASK before holding rtnl().
9474 clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
9478 static void bnxt_rtnl_unlock_sp(struct bnxt *bp)
9480 set_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
9484 /* Only called from bnxt_sp_task() */
9485 static void bnxt_reset(struct bnxt *bp, bool silent)
9487 bnxt_rtnl_lock_sp(bp);
9488 if (test_bit(BNXT_STATE_OPEN, &bp->state))
9489 bnxt_reset_task(bp, silent);
9490 bnxt_rtnl_unlock_sp(bp);
9493 static void bnxt_chk_missed_irq(struct bnxt *bp)
9497 if (!(bp->flags & BNXT_FLAG_CHIP_P5))
9500 for (i = 0; i < bp->cp_nr_rings; i++) {
9501 struct bnxt_napi *bnapi = bp->bnapi[i];
9502 struct bnxt_cp_ring_info *cpr;
9509 cpr = &bnapi->cp_ring;
9510 for (j = 0; j < 2; j++) {
9511 struct bnxt_cp_ring_info *cpr2 = cpr->cp_ring_arr[j];
9514 if (!cpr2 || cpr2->has_more_work ||
9515 !bnxt_has_work(bp, cpr2))
9518 if (cpr2->cp_raw_cons != cpr2->last_cp_raw_cons) {
9519 cpr2->last_cp_raw_cons = cpr2->cp_raw_cons;
9522 fw_ring_id = cpr2->cp_ring_struct.fw_ring_id;
9523 bnxt_dbg_hwrm_ring_info_get(bp,
9524 DBG_RING_INFO_GET_REQ_RING_TYPE_L2_CMPL,
9525 fw_ring_id, &val[0], &val[1]);
9531 static void bnxt_cfg_ntp_filters(struct bnxt *);
9533 static void bnxt_sp_task(struct work_struct *work)
9535 struct bnxt *bp = container_of(work, struct bnxt, sp_task);
9537 set_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
9538 smp_mb__after_atomic();
9539 if (!test_bit(BNXT_STATE_OPEN, &bp->state)) {
9540 clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
9544 if (test_and_clear_bit(BNXT_RX_MASK_SP_EVENT, &bp->sp_event))
9545 bnxt_cfg_rx_mode(bp);
9547 if (test_and_clear_bit(BNXT_RX_NTP_FLTR_SP_EVENT, &bp->sp_event))
9548 bnxt_cfg_ntp_filters(bp);
9549 if (test_and_clear_bit(BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT, &bp->sp_event))
9550 bnxt_hwrm_exec_fwd_req(bp);
9551 if (test_and_clear_bit(BNXT_VXLAN_ADD_PORT_SP_EVENT, &bp->sp_event)) {
9552 bnxt_hwrm_tunnel_dst_port_alloc(
9554 TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN);
9556 if (test_and_clear_bit(BNXT_VXLAN_DEL_PORT_SP_EVENT, &bp->sp_event)) {
9557 bnxt_hwrm_tunnel_dst_port_free(
9558 bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN);
9560 if (test_and_clear_bit(BNXT_GENEVE_ADD_PORT_SP_EVENT, &bp->sp_event)) {
9561 bnxt_hwrm_tunnel_dst_port_alloc(
9563 TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE);
9565 if (test_and_clear_bit(BNXT_GENEVE_DEL_PORT_SP_EVENT, &bp->sp_event)) {
9566 bnxt_hwrm_tunnel_dst_port_free(
9567 bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE);
9569 if (test_and_clear_bit(BNXT_PERIODIC_STATS_SP_EVENT, &bp->sp_event)) {
9570 bnxt_hwrm_port_qstats(bp);
9571 bnxt_hwrm_port_qstats_ext(bp);
9572 bnxt_hwrm_pcie_qstats(bp);
9575 if (test_and_clear_bit(BNXT_LINK_CHNG_SP_EVENT, &bp->sp_event)) {
9578 mutex_lock(&bp->link_lock);
9579 if (test_and_clear_bit(BNXT_LINK_SPEED_CHNG_SP_EVENT,
9581 bnxt_hwrm_phy_qcaps(bp);
9583 rc = bnxt_update_link(bp, true);
9584 mutex_unlock(&bp->link_lock);
9586 netdev_err(bp->dev, "SP task can't update link (rc: %x)\n",
9589 if (test_and_clear_bit(BNXT_UPDATE_PHY_SP_EVENT, &bp->sp_event)) {
9592 mutex_lock(&bp->link_lock);
9593 rc = bnxt_update_phy_setting(bp);
9594 mutex_unlock(&bp->link_lock);
9596 netdev_warn(bp->dev, "update phy settings retry failed\n");
9598 bp->link_info.phy_retry = false;
9599 netdev_info(bp->dev, "update phy settings retry succeeded\n");
9602 if (test_and_clear_bit(BNXT_HWRM_PORT_MODULE_SP_EVENT, &bp->sp_event)) {
9603 mutex_lock(&bp->link_lock);
9604 bnxt_get_port_module_status(bp);
9605 mutex_unlock(&bp->link_lock);
9608 if (test_and_clear_bit(BNXT_FLOW_STATS_SP_EVENT, &bp->sp_event))
9609 bnxt_tc_flow_stats_work(bp);
9611 if (test_and_clear_bit(BNXT_RING_COAL_NOW_SP_EVENT, &bp->sp_event))
9612 bnxt_chk_missed_irq(bp);
9614 /* These functions below will clear BNXT_STATE_IN_SP_TASK. They
9615 * must be the last functions to be called before exiting.
9617 if (test_and_clear_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event))
9618 bnxt_reset(bp, false);
9620 if (test_and_clear_bit(BNXT_RESET_TASK_SILENT_SP_EVENT, &bp->sp_event))
9621 bnxt_reset(bp, true);
9623 smp_mb__before_atomic();
9624 clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
9627 /* Under rtnl_lock */
9628 int bnxt_check_rings(struct bnxt *bp, int tx, int rx, bool sh, int tcs,
9631 int max_rx, max_tx, tx_sets = 1;
9632 int tx_rings_needed, stats;
9639 rc = bnxt_get_max_rings(bp, &max_rx, &max_tx, sh);
9646 tx_rings_needed = tx * tx_sets + tx_xdp;
9647 if (max_tx < tx_rings_needed)
9651 if ((bp->flags & (BNXT_FLAG_RFS | BNXT_FLAG_CHIP_P5)) == BNXT_FLAG_RFS)
9654 if (bp->flags & BNXT_FLAG_AGG_RINGS)
9656 cp = sh ? max_t(int, tx_rings_needed, rx) : tx_rings_needed + rx;
9658 if (BNXT_NEW_RM(bp)) {
9659 cp += bnxt_get_ulp_msix_num(bp);
9660 stats += bnxt_get_ulp_stat_ctxs(bp);
9662 return bnxt_hwrm_check_rings(bp, tx_rings_needed, rx_rings, rx, cp,
9666 static void bnxt_unmap_bars(struct bnxt *bp, struct pci_dev *pdev)
9669 pci_iounmap(pdev, bp->bar2);
9674 pci_iounmap(pdev, bp->bar1);
9679 pci_iounmap(pdev, bp->bar0);
9684 static void bnxt_cleanup_pci(struct bnxt *bp)
9686 bnxt_unmap_bars(bp, bp->pdev);
9687 pci_release_regions(bp->pdev);
9688 pci_disable_device(bp->pdev);
9691 static void bnxt_init_dflt_coal(struct bnxt *bp)
9693 struct bnxt_coal *coal;
9695 /* Tick values in micro seconds.
9696 * 1 coal_buf x bufs_per_record = 1 completion record.
9698 coal = &bp->rx_coal;
9699 coal->coal_ticks = 10;
9700 coal->coal_bufs = 30;
9701 coal->coal_ticks_irq = 1;
9702 coal->coal_bufs_irq = 2;
9703 coal->idle_thresh = 50;
9704 coal->bufs_per_record = 2;
9705 coal->budget = 64; /* NAPI budget */
9707 coal = &bp->tx_coal;
9708 coal->coal_ticks = 28;
9709 coal->coal_bufs = 30;
9710 coal->coal_ticks_irq = 2;
9711 coal->coal_bufs_irq = 2;
9712 coal->bufs_per_record = 1;
9714 bp->stats_coal_ticks = BNXT_DEF_STATS_COAL_TICKS;
9717 static int bnxt_init_board(struct pci_dev *pdev, struct net_device *dev)
9720 struct bnxt *bp = netdev_priv(dev);
9722 SET_NETDEV_DEV(dev, &pdev->dev);
9724 /* enable device (incl. PCI PM wakeup), and bus-mastering */
9725 rc = pci_enable_device(pdev);
9727 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
9731 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
9733 "Cannot find PCI device base address, aborting\n");
9735 goto init_err_disable;
9738 rc = pci_request_regions(pdev, DRV_MODULE_NAME);
9740 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n");
9741 goto init_err_disable;
9744 if (dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)) != 0 &&
9745 dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)) != 0) {
9746 dev_err(&pdev->dev, "System does not support DMA, aborting\n");
9747 goto init_err_disable;
9750 pci_set_master(pdev);
9755 bp->bar0 = pci_ioremap_bar(pdev, 0);
9757 dev_err(&pdev->dev, "Cannot map device registers, aborting\n");
9759 goto init_err_release;
9762 bp->bar1 = pci_ioremap_bar(pdev, 2);
9764 dev_err(&pdev->dev, "Cannot map doorbell registers, aborting\n");
9766 goto init_err_release;
9769 bp->bar2 = pci_ioremap_bar(pdev, 4);
9771 dev_err(&pdev->dev, "Cannot map bar4 registers, aborting\n");
9773 goto init_err_release;
9776 pci_enable_pcie_error_reporting(pdev);
9778 INIT_WORK(&bp->sp_task, bnxt_sp_task);
9780 spin_lock_init(&bp->ntp_fltr_lock);
9781 #if BITS_PER_LONG == 32
9782 spin_lock_init(&bp->db_lock);
9785 bp->rx_ring_size = BNXT_DEFAULT_RX_RING_SIZE;
9786 bp->tx_ring_size = BNXT_DEFAULT_TX_RING_SIZE;
9788 bnxt_init_dflt_coal(bp);
9790 timer_setup(&bp->timer, bnxt_timer, 0);
9791 bp->current_interval = BNXT_TIMER_INTERVAL;
9793 clear_bit(BNXT_STATE_OPEN, &bp->state);
9797 bnxt_unmap_bars(bp, pdev);
9798 pci_release_regions(pdev);
9801 pci_disable_device(pdev);
9807 /* rtnl_lock held */
9808 static int bnxt_change_mac_addr(struct net_device *dev, void *p)
9810 struct sockaddr *addr = p;
9811 struct bnxt *bp = netdev_priv(dev);
9814 if (!is_valid_ether_addr(addr->sa_data))
9815 return -EADDRNOTAVAIL;
9817 if (ether_addr_equal(addr->sa_data, dev->dev_addr))
9820 rc = bnxt_approve_mac(bp, addr->sa_data, true);
9824 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
9825 if (netif_running(dev)) {
9826 bnxt_close_nic(bp, false, false);
9827 rc = bnxt_open_nic(bp, false, false);
9833 /* rtnl_lock held */
9834 static int bnxt_change_mtu(struct net_device *dev, int new_mtu)
9836 struct bnxt *bp = netdev_priv(dev);
9838 if (netif_running(dev))
9839 bnxt_close_nic(bp, false, false);
9842 bnxt_set_ring_params(bp);
9844 if (netif_running(dev))
9845 return bnxt_open_nic(bp, false, false);
9850 int bnxt_setup_mq_tc(struct net_device *dev, u8 tc)
9852 struct bnxt *bp = netdev_priv(dev);
9856 if (tc > bp->max_tc) {
9857 netdev_err(dev, "Too many traffic classes requested: %d. Max supported is %d.\n",
9862 if (netdev_get_num_tc(dev) == tc)
9865 if (bp->flags & BNXT_FLAG_SHARED_RINGS)
9868 rc = bnxt_check_rings(bp, bp->tx_nr_rings_per_tc, bp->rx_nr_rings,
9869 sh, tc, bp->tx_nr_rings_xdp);
9873 /* Needs to close the device and do hw resource re-allocations */
9874 if (netif_running(bp->dev))
9875 bnxt_close_nic(bp, true, false);
9878 bp->tx_nr_rings = bp->tx_nr_rings_per_tc * tc;
9879 netdev_set_num_tc(dev, tc);
9881 bp->tx_nr_rings = bp->tx_nr_rings_per_tc;
9882 netdev_reset_tc(dev);
9884 bp->tx_nr_rings += bp->tx_nr_rings_xdp;
9885 bp->cp_nr_rings = sh ? max_t(int, bp->tx_nr_rings, bp->rx_nr_rings) :
9886 bp->tx_nr_rings + bp->rx_nr_rings;
9888 if (netif_running(bp->dev))
9889 return bnxt_open_nic(bp, true, false);
9894 static int bnxt_setup_tc_block_cb(enum tc_setup_type type, void *type_data,
9897 struct bnxt *bp = cb_priv;
9899 if (!bnxt_tc_flower_enabled(bp) ||
9900 !tc_cls_can_offload_and_chain0(bp->dev, type_data))
9904 case TC_SETUP_CLSFLOWER:
9905 return bnxt_tc_setup_flower(bp, bp->pf.fw_fid, type_data);
9911 static LIST_HEAD(bnxt_block_cb_list);
9913 static int bnxt_setup_tc(struct net_device *dev, enum tc_setup_type type,
9916 struct bnxt *bp = netdev_priv(dev);
9919 case TC_SETUP_BLOCK:
9920 return flow_block_cb_setup_simple(type_data,
9921 &bnxt_block_cb_list,
9922 bnxt_setup_tc_block_cb,
9924 case TC_SETUP_QDISC_MQPRIO: {
9925 struct tc_mqprio_qopt *mqprio = type_data;
9927 mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS;
9929 return bnxt_setup_mq_tc(dev, mqprio->num_tc);
9936 #ifdef CONFIG_RFS_ACCEL
9937 static bool bnxt_fltr_match(struct bnxt_ntuple_filter *f1,
9938 struct bnxt_ntuple_filter *f2)
9940 struct flow_keys *keys1 = &f1->fkeys;
9941 struct flow_keys *keys2 = &f2->fkeys;
9943 if (keys1->addrs.v4addrs.src == keys2->addrs.v4addrs.src &&
9944 keys1->addrs.v4addrs.dst == keys2->addrs.v4addrs.dst &&
9945 keys1->ports.ports == keys2->ports.ports &&
9946 keys1->basic.ip_proto == keys2->basic.ip_proto &&
9947 keys1->basic.n_proto == keys2->basic.n_proto &&
9948 keys1->control.flags == keys2->control.flags &&
9949 ether_addr_equal(f1->src_mac_addr, f2->src_mac_addr) &&
9950 ether_addr_equal(f1->dst_mac_addr, f2->dst_mac_addr))
9956 static int bnxt_rx_flow_steer(struct net_device *dev, const struct sk_buff *skb,
9957 u16 rxq_index, u32 flow_id)
9959 struct bnxt *bp = netdev_priv(dev);
9960 struct bnxt_ntuple_filter *fltr, *new_fltr;
9961 struct flow_keys *fkeys;
9962 struct ethhdr *eth = (struct ethhdr *)skb_mac_header(skb);
9963 int rc = 0, idx, bit_id, l2_idx = 0;
9964 struct hlist_head *head;
9966 if (!ether_addr_equal(dev->dev_addr, eth->h_dest)) {
9967 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
9970 netif_addr_lock_bh(dev);
9971 for (j = 0; j < vnic->uc_filter_count; j++, off += ETH_ALEN) {
9972 if (ether_addr_equal(eth->h_dest,
9973 vnic->uc_list + off)) {
9978 netif_addr_unlock_bh(dev);
9982 new_fltr = kzalloc(sizeof(*new_fltr), GFP_ATOMIC);
9986 fkeys = &new_fltr->fkeys;
9987 if (!skb_flow_dissect_flow_keys(skb, fkeys, 0)) {
9988 rc = -EPROTONOSUPPORT;
9992 if ((fkeys->basic.n_proto != htons(ETH_P_IP) &&
9993 fkeys->basic.n_proto != htons(ETH_P_IPV6)) ||
9994 ((fkeys->basic.ip_proto != IPPROTO_TCP) &&
9995 (fkeys->basic.ip_proto != IPPROTO_UDP))) {
9996 rc = -EPROTONOSUPPORT;
9999 if (fkeys->basic.n_proto == htons(ETH_P_IPV6) &&
10000 bp->hwrm_spec_code < 0x10601) {
10001 rc = -EPROTONOSUPPORT;
10004 if ((fkeys->control.flags & FLOW_DIS_ENCAPSULATION) &&
10005 bp->hwrm_spec_code < 0x10601) {
10006 rc = -EPROTONOSUPPORT;
10010 memcpy(new_fltr->dst_mac_addr, eth->h_dest, ETH_ALEN);
10011 memcpy(new_fltr->src_mac_addr, eth->h_source, ETH_ALEN);
10013 idx = skb_get_hash_raw(skb) & BNXT_NTP_FLTR_HASH_MASK;
10014 head = &bp->ntp_fltr_hash_tbl[idx];
10016 hlist_for_each_entry_rcu(fltr, head, hash) {
10017 if (bnxt_fltr_match(fltr, new_fltr)) {
10025 spin_lock_bh(&bp->ntp_fltr_lock);
10026 bit_id = bitmap_find_free_region(bp->ntp_fltr_bmap,
10027 BNXT_NTP_FLTR_MAX_FLTR, 0);
10029 spin_unlock_bh(&bp->ntp_fltr_lock);
10034 new_fltr->sw_id = (u16)bit_id;
10035 new_fltr->flow_id = flow_id;
10036 new_fltr->l2_fltr_idx = l2_idx;
10037 new_fltr->rxq = rxq_index;
10038 hlist_add_head_rcu(&new_fltr->hash, head);
10039 bp->ntp_fltr_count++;
10040 spin_unlock_bh(&bp->ntp_fltr_lock);
10042 set_bit(BNXT_RX_NTP_FLTR_SP_EVENT, &bp->sp_event);
10043 bnxt_queue_sp_work(bp);
10045 return new_fltr->sw_id;
10052 static void bnxt_cfg_ntp_filters(struct bnxt *bp)
10056 for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) {
10057 struct hlist_head *head;
10058 struct hlist_node *tmp;
10059 struct bnxt_ntuple_filter *fltr;
10062 head = &bp->ntp_fltr_hash_tbl[i];
10063 hlist_for_each_entry_safe(fltr, tmp, head, hash) {
10066 if (test_bit(BNXT_FLTR_VALID, &fltr->state)) {
10067 if (rps_may_expire_flow(bp->dev, fltr->rxq,
10070 bnxt_hwrm_cfa_ntuple_filter_free(bp,
10075 rc = bnxt_hwrm_cfa_ntuple_filter_alloc(bp,
10080 set_bit(BNXT_FLTR_VALID, &fltr->state);
10084 spin_lock_bh(&bp->ntp_fltr_lock);
10085 hlist_del_rcu(&fltr->hash);
10086 bp->ntp_fltr_count--;
10087 spin_unlock_bh(&bp->ntp_fltr_lock);
10089 clear_bit(fltr->sw_id, bp->ntp_fltr_bmap);
10094 if (test_and_clear_bit(BNXT_HWRM_PF_UNLOAD_SP_EVENT, &bp->sp_event))
10095 netdev_info(bp->dev, "Receive PF driver unload event!");
10100 static void bnxt_cfg_ntp_filters(struct bnxt *bp)
10104 #endif /* CONFIG_RFS_ACCEL */
10106 static void bnxt_udp_tunnel_add(struct net_device *dev,
10107 struct udp_tunnel_info *ti)
10109 struct bnxt *bp = netdev_priv(dev);
10111 if (ti->sa_family != AF_INET6 && ti->sa_family != AF_INET)
10114 if (!netif_running(dev))
10117 switch (ti->type) {
10118 case UDP_TUNNEL_TYPE_VXLAN:
10119 if (bp->vxlan_port_cnt && bp->vxlan_port != ti->port)
10122 bp->vxlan_port_cnt++;
10123 if (bp->vxlan_port_cnt == 1) {
10124 bp->vxlan_port = ti->port;
10125 set_bit(BNXT_VXLAN_ADD_PORT_SP_EVENT, &bp->sp_event);
10126 bnxt_queue_sp_work(bp);
10129 case UDP_TUNNEL_TYPE_GENEVE:
10130 if (bp->nge_port_cnt && bp->nge_port != ti->port)
10133 bp->nge_port_cnt++;
10134 if (bp->nge_port_cnt == 1) {
10135 bp->nge_port = ti->port;
10136 set_bit(BNXT_GENEVE_ADD_PORT_SP_EVENT, &bp->sp_event);
10143 bnxt_queue_sp_work(bp);
10146 static void bnxt_udp_tunnel_del(struct net_device *dev,
10147 struct udp_tunnel_info *ti)
10149 struct bnxt *bp = netdev_priv(dev);
10151 if (ti->sa_family != AF_INET6 && ti->sa_family != AF_INET)
10154 if (!netif_running(dev))
10157 switch (ti->type) {
10158 case UDP_TUNNEL_TYPE_VXLAN:
10159 if (!bp->vxlan_port_cnt || bp->vxlan_port != ti->port)
10161 bp->vxlan_port_cnt--;
10163 if (bp->vxlan_port_cnt != 0)
10166 set_bit(BNXT_VXLAN_DEL_PORT_SP_EVENT, &bp->sp_event);
10168 case UDP_TUNNEL_TYPE_GENEVE:
10169 if (!bp->nge_port_cnt || bp->nge_port != ti->port)
10171 bp->nge_port_cnt--;
10173 if (bp->nge_port_cnt != 0)
10176 set_bit(BNXT_GENEVE_DEL_PORT_SP_EVENT, &bp->sp_event);
10182 bnxt_queue_sp_work(bp);
10185 static int bnxt_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq,
10186 struct net_device *dev, u32 filter_mask,
10189 struct bnxt *bp = netdev_priv(dev);
10191 return ndo_dflt_bridge_getlink(skb, pid, seq, dev, bp->br_mode, 0, 0,
10192 nlflags, filter_mask, NULL);
10195 static int bnxt_bridge_setlink(struct net_device *dev, struct nlmsghdr *nlh,
10196 u16 flags, struct netlink_ext_ack *extack)
10198 struct bnxt *bp = netdev_priv(dev);
10199 struct nlattr *attr, *br_spec;
10202 if (bp->hwrm_spec_code < 0x10708 || !BNXT_SINGLE_PF(bp))
10203 return -EOPNOTSUPP;
10205 br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC);
10209 nla_for_each_nested(attr, br_spec, rem) {
10212 if (nla_type(attr) != IFLA_BRIDGE_MODE)
10215 if (nla_len(attr) < sizeof(mode))
10218 mode = nla_get_u16(attr);
10219 if (mode == bp->br_mode)
10222 rc = bnxt_hwrm_set_br_mode(bp, mode);
10224 bp->br_mode = mode;
10230 int bnxt_get_port_parent_id(struct net_device *dev,
10231 struct netdev_phys_item_id *ppid)
10233 struct bnxt *bp = netdev_priv(dev);
10235 if (bp->eswitch_mode != DEVLINK_ESWITCH_MODE_SWITCHDEV)
10236 return -EOPNOTSUPP;
10238 /* The PF and it's VF-reps only support the switchdev framework */
10240 return -EOPNOTSUPP;
10242 ppid->id_len = sizeof(bp->switch_id);
10243 memcpy(ppid->id, bp->switch_id, ppid->id_len);
10248 static struct devlink_port *bnxt_get_devlink_port(struct net_device *dev)
10250 struct bnxt *bp = netdev_priv(dev);
10252 return &bp->dl_port;
10255 static const struct net_device_ops bnxt_netdev_ops = {
10256 .ndo_open = bnxt_open,
10257 .ndo_start_xmit = bnxt_start_xmit,
10258 .ndo_stop = bnxt_close,
10259 .ndo_get_stats64 = bnxt_get_stats64,
10260 .ndo_set_rx_mode = bnxt_set_rx_mode,
10261 .ndo_do_ioctl = bnxt_ioctl,
10262 .ndo_validate_addr = eth_validate_addr,
10263 .ndo_set_mac_address = bnxt_change_mac_addr,
10264 .ndo_change_mtu = bnxt_change_mtu,
10265 .ndo_fix_features = bnxt_fix_features,
10266 .ndo_set_features = bnxt_set_features,
10267 .ndo_tx_timeout = bnxt_tx_timeout,
10268 #ifdef CONFIG_BNXT_SRIOV
10269 .ndo_get_vf_config = bnxt_get_vf_config,
10270 .ndo_set_vf_mac = bnxt_set_vf_mac,
10271 .ndo_set_vf_vlan = bnxt_set_vf_vlan,
10272 .ndo_set_vf_rate = bnxt_set_vf_bw,
10273 .ndo_set_vf_link_state = bnxt_set_vf_link_state,
10274 .ndo_set_vf_spoofchk = bnxt_set_vf_spoofchk,
10275 .ndo_set_vf_trust = bnxt_set_vf_trust,
10277 .ndo_setup_tc = bnxt_setup_tc,
10278 #ifdef CONFIG_RFS_ACCEL
10279 .ndo_rx_flow_steer = bnxt_rx_flow_steer,
10281 .ndo_udp_tunnel_add = bnxt_udp_tunnel_add,
10282 .ndo_udp_tunnel_del = bnxt_udp_tunnel_del,
10283 .ndo_bpf = bnxt_xdp,
10284 .ndo_xdp_xmit = bnxt_xdp_xmit,
10285 .ndo_bridge_getlink = bnxt_bridge_getlink,
10286 .ndo_bridge_setlink = bnxt_bridge_setlink,
10287 .ndo_get_devlink_port = bnxt_get_devlink_port,
10290 static void bnxt_remove_one(struct pci_dev *pdev)
10292 struct net_device *dev = pci_get_drvdata(pdev);
10293 struct bnxt *bp = netdev_priv(dev);
10296 bnxt_sriov_disable(bp);
10297 bnxt_dl_unregister(bp);
10300 pci_disable_pcie_error_reporting(pdev);
10301 unregister_netdev(dev);
10302 bnxt_shutdown_tc(bp);
10303 bnxt_cancel_sp_work(bp);
10306 bnxt_clear_int_mode(bp);
10307 bnxt_hwrm_func_drv_unrgtr(bp);
10308 bnxt_free_hwrm_resources(bp);
10309 bnxt_free_hwrm_short_cmd_req(bp);
10310 bnxt_ethtool_free(bp);
10314 bnxt_cleanup_pci(bp);
10315 bnxt_free_ctx_mem(bp);
10318 bnxt_free_port_stats(bp);
10322 static int bnxt_probe_phy(struct bnxt *bp)
10325 struct bnxt_link_info *link_info = &bp->link_info;
10327 rc = bnxt_hwrm_phy_qcaps(bp);
10329 netdev_err(bp->dev, "Probe phy can't get phy capabilities (rc: %x)\n",
10333 mutex_init(&bp->link_lock);
10335 rc = bnxt_update_link(bp, false);
10337 netdev_err(bp->dev, "Probe phy can't update link (rc: %x)\n",
10342 /* Older firmware does not have supported_auto_speeds, so assume
10343 * that all supported speeds can be autonegotiated.
10345 if (link_info->auto_link_speeds && !link_info->support_auto_speeds)
10346 link_info->support_auto_speeds = link_info->support_speeds;
10348 /*initialize the ethool setting copy with NVM settings */
10349 if (BNXT_AUTO_MODE(link_info->auto_mode)) {
10350 link_info->autoneg = BNXT_AUTONEG_SPEED;
10351 if (bp->hwrm_spec_code >= 0x10201) {
10352 if (link_info->auto_pause_setting &
10353 PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE)
10354 link_info->autoneg |= BNXT_AUTONEG_FLOW_CTRL;
10356 link_info->autoneg |= BNXT_AUTONEG_FLOW_CTRL;
10358 link_info->advertising = link_info->auto_link_speeds;
10360 link_info->req_link_speed = link_info->force_link_speed;
10361 link_info->req_duplex = link_info->duplex_setting;
10363 if (link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL)
10364 link_info->req_flow_ctrl =
10365 link_info->auto_pause_setting & BNXT_LINK_PAUSE_BOTH;
10367 link_info->req_flow_ctrl = link_info->force_pause_setting;
10371 static int bnxt_get_max_irq(struct pci_dev *pdev)
10375 if (!pdev->msix_cap)
10378 pci_read_config_word(pdev, pdev->msix_cap + PCI_MSIX_FLAGS, &ctrl);
10379 return (ctrl & PCI_MSIX_FLAGS_QSIZE) + 1;
10382 static void _bnxt_get_max_rings(struct bnxt *bp, int *max_rx, int *max_tx,
10385 struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
10386 int max_ring_grps = 0, max_irq;
10388 *max_tx = hw_resc->max_tx_rings;
10389 *max_rx = hw_resc->max_rx_rings;
10390 *max_cp = bnxt_get_max_func_cp_rings_for_en(bp);
10391 max_irq = min_t(int, bnxt_get_max_func_irqs(bp) -
10392 bnxt_get_ulp_msix_num(bp),
10393 hw_resc->max_stat_ctxs - bnxt_get_ulp_stat_ctxs(bp));
10394 if (!(bp->flags & BNXT_FLAG_CHIP_P5))
10395 *max_cp = min_t(int, *max_cp, max_irq);
10396 max_ring_grps = hw_resc->max_hw_ring_grps;
10397 if (BNXT_CHIP_TYPE_NITRO_A0(bp) && BNXT_PF(bp)) {
10401 if (bp->flags & BNXT_FLAG_AGG_RINGS)
10403 if (bp->flags & BNXT_FLAG_CHIP_P5) {
10404 bnxt_trim_rings(bp, max_rx, max_tx, *max_cp, false);
10405 /* On P5 chips, max_cp output param should be available NQs */
10408 *max_rx = min_t(int, *max_rx, max_ring_grps);
10411 int bnxt_get_max_rings(struct bnxt *bp, int *max_rx, int *max_tx, bool shared)
10415 _bnxt_get_max_rings(bp, &rx, &tx, &cp);
10418 if (!rx || !tx || !cp)
10421 return bnxt_trim_rings(bp, max_rx, max_tx, cp, shared);
10424 static int bnxt_get_dflt_rings(struct bnxt *bp, int *max_rx, int *max_tx,
10429 rc = bnxt_get_max_rings(bp, max_rx, max_tx, shared);
10430 if (rc && (bp->flags & BNXT_FLAG_AGG_RINGS)) {
10431 /* Not enough rings, try disabling agg rings. */
10432 bp->flags &= ~BNXT_FLAG_AGG_RINGS;
10433 rc = bnxt_get_max_rings(bp, max_rx, max_tx, shared);
10435 /* set BNXT_FLAG_AGG_RINGS back for consistency */
10436 bp->flags |= BNXT_FLAG_AGG_RINGS;
10439 bp->flags |= BNXT_FLAG_NO_AGG_RINGS;
10440 bp->dev->hw_features &= ~(NETIF_F_LRO | NETIF_F_GRO_HW);
10441 bp->dev->features &= ~(NETIF_F_LRO | NETIF_F_GRO_HW);
10442 bnxt_set_ring_params(bp);
10445 if (bp->flags & BNXT_FLAG_ROCE_CAP) {
10446 int max_cp, max_stat, max_irq;
10448 /* Reserve minimum resources for RoCE */
10449 max_cp = bnxt_get_max_func_cp_rings(bp);
10450 max_stat = bnxt_get_max_func_stat_ctxs(bp);
10451 max_irq = bnxt_get_max_func_irqs(bp);
10452 if (max_cp <= BNXT_MIN_ROCE_CP_RINGS ||
10453 max_irq <= BNXT_MIN_ROCE_CP_RINGS ||
10454 max_stat <= BNXT_MIN_ROCE_STAT_CTXS)
10457 max_cp -= BNXT_MIN_ROCE_CP_RINGS;
10458 max_irq -= BNXT_MIN_ROCE_CP_RINGS;
10459 max_stat -= BNXT_MIN_ROCE_STAT_CTXS;
10460 max_cp = min_t(int, max_cp, max_irq);
10461 max_cp = min_t(int, max_cp, max_stat);
10462 rc = bnxt_trim_rings(bp, max_rx, max_tx, max_cp, shared);
10469 /* In initial default shared ring setting, each shared ring must have a
10472 static void bnxt_trim_dflt_sh_rings(struct bnxt *bp)
10474 bp->cp_nr_rings = min_t(int, bp->tx_nr_rings_per_tc, bp->rx_nr_rings);
10475 bp->rx_nr_rings = bp->cp_nr_rings;
10476 bp->tx_nr_rings_per_tc = bp->cp_nr_rings;
10477 bp->tx_nr_rings = bp->tx_nr_rings_per_tc;
10480 static int bnxt_set_dflt_rings(struct bnxt *bp, bool sh)
10482 int dflt_rings, max_rx_rings, max_tx_rings, rc;
10484 if (!bnxt_can_reserve_rings(bp))
10488 bp->flags |= BNXT_FLAG_SHARED_RINGS;
10489 dflt_rings = is_kdump_kernel() ? 1 : netif_get_num_default_rss_queues();
10490 /* Reduce default rings on multi-port cards so that total default
10491 * rings do not exceed CPU count.
10493 if (bp->port_count > 1) {
10495 max_t(int, num_online_cpus() / bp->port_count, 1);
10497 dflt_rings = min_t(int, dflt_rings, max_rings);
10499 rc = bnxt_get_dflt_rings(bp, &max_rx_rings, &max_tx_rings, sh);
10502 bp->rx_nr_rings = min_t(int, dflt_rings, max_rx_rings);
10503 bp->tx_nr_rings_per_tc = min_t(int, dflt_rings, max_tx_rings);
10505 bnxt_trim_dflt_sh_rings(bp);
10507 bp->cp_nr_rings = bp->tx_nr_rings_per_tc + bp->rx_nr_rings;
10508 bp->tx_nr_rings = bp->tx_nr_rings_per_tc;
10510 rc = __bnxt_reserve_rings(bp);
10512 netdev_warn(bp->dev, "Unable to reserve tx rings\n");
10513 bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
10515 bnxt_trim_dflt_sh_rings(bp);
10517 /* Rings may have been trimmed, re-reserve the trimmed rings. */
10518 if (bnxt_need_reserve_rings(bp)) {
10519 rc = __bnxt_reserve_rings(bp);
10521 netdev_warn(bp->dev, "2nd rings reservation failed.\n");
10522 bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
10524 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) {
10531 static int bnxt_init_dflt_ring_mode(struct bnxt *bp)
10535 if (bp->tx_nr_rings)
10538 bnxt_ulp_irq_stop(bp);
10539 bnxt_clear_int_mode(bp);
10540 rc = bnxt_set_dflt_rings(bp, true);
10542 netdev_err(bp->dev, "Not enough rings available.\n");
10543 goto init_dflt_ring_err;
10545 rc = bnxt_init_int_mode(bp);
10547 goto init_dflt_ring_err;
10549 bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
10550 if (bnxt_rfs_supported(bp) && bnxt_rfs_capable(bp)) {
10551 bp->flags |= BNXT_FLAG_RFS;
10552 bp->dev->features |= NETIF_F_NTUPLE;
10554 init_dflt_ring_err:
10555 bnxt_ulp_irq_restart(bp, rc);
10559 int bnxt_restore_pf_fw_resources(struct bnxt *bp)
10564 bnxt_hwrm_func_qcaps(bp);
10566 if (netif_running(bp->dev))
10567 __bnxt_close_nic(bp, true, false);
10569 bnxt_ulp_irq_stop(bp);
10570 bnxt_clear_int_mode(bp);
10571 rc = bnxt_init_int_mode(bp);
10572 bnxt_ulp_irq_restart(bp, rc);
10574 if (netif_running(bp->dev)) {
10576 dev_close(bp->dev);
10578 rc = bnxt_open_nic(bp, true, false);
10584 static int bnxt_init_mac_addr(struct bnxt *bp)
10589 memcpy(bp->dev->dev_addr, bp->pf.mac_addr, ETH_ALEN);
10591 #ifdef CONFIG_BNXT_SRIOV
10592 struct bnxt_vf_info *vf = &bp->vf;
10593 bool strict_approval = true;
10595 if (is_valid_ether_addr(vf->mac_addr)) {
10596 /* overwrite netdev dev_addr with admin VF MAC */
10597 memcpy(bp->dev->dev_addr, vf->mac_addr, ETH_ALEN);
10598 /* Older PF driver or firmware may not approve this
10601 strict_approval = false;
10603 eth_hw_addr_random(bp->dev);
10605 rc = bnxt_approve_mac(bp, bp->dev->dev_addr, strict_approval);
10611 static int bnxt_pcie_dsn_get(struct bnxt *bp, u8 dsn[])
10613 struct pci_dev *pdev = bp->pdev;
10614 int pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_DSN);
10618 netdev_info(bp->dev, "Unable do read adapter's DSN");
10619 return -EOPNOTSUPP;
10622 /* DSN (two dw) is at an offset of 4 from the cap pos */
10624 pci_read_config_dword(pdev, pos, &dw);
10625 put_unaligned_le32(dw, &dsn[0]);
10626 pci_read_config_dword(pdev, pos + 4, &dw);
10627 put_unaligned_le32(dw, &dsn[4]);
10631 static int bnxt_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
10633 static int version_printed;
10634 struct net_device *dev;
10638 if (pci_is_bridge(pdev))
10641 if (version_printed++ == 0)
10642 pr_info("%s", version);
10644 max_irqs = bnxt_get_max_irq(pdev);
10645 dev = alloc_etherdev_mq(sizeof(*bp), max_irqs);
10649 bp = netdev_priv(dev);
10650 bnxt_set_max_func_irqs(bp, max_irqs);
10652 if (bnxt_vf_pciid(ent->driver_data))
10653 bp->flags |= BNXT_FLAG_VF;
10655 if (pdev->msix_cap)
10656 bp->flags |= BNXT_FLAG_MSIX_CAP;
10658 rc = bnxt_init_board(pdev, dev);
10660 goto init_err_free;
10662 dev->netdev_ops = &bnxt_netdev_ops;
10663 dev->watchdog_timeo = BNXT_TX_TIMEOUT;
10664 dev->ethtool_ops = &bnxt_ethtool_ops;
10665 pci_set_drvdata(pdev, dev);
10667 rc = bnxt_alloc_hwrm_resources(bp);
10669 goto init_err_pci_clean;
10671 mutex_init(&bp->hwrm_cmd_lock);
10672 rc = bnxt_hwrm_ver_get(bp);
10674 goto init_err_pci_clean;
10676 if (bp->fw_cap & BNXT_FW_CAP_KONG_MB_CHNL) {
10677 rc = bnxt_alloc_kong_hwrm_resources(bp);
10679 bp->fw_cap &= ~BNXT_FW_CAP_KONG_MB_CHNL;
10682 if ((bp->fw_cap & BNXT_FW_CAP_SHORT_CMD) ||
10683 bp->hwrm_max_ext_req_len > BNXT_HWRM_MAX_REQ_LEN) {
10684 rc = bnxt_alloc_hwrm_short_cmd_req(bp);
10686 goto init_err_pci_clean;
10689 if (BNXT_CHIP_P5(bp))
10690 bp->flags |= BNXT_FLAG_CHIP_P5;
10692 rc = bnxt_hwrm_func_reset(bp);
10694 goto init_err_pci_clean;
10696 bnxt_hwrm_fw_set_time(bp);
10698 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG |
10699 NETIF_F_TSO | NETIF_F_TSO6 |
10700 NETIF_F_GSO_UDP_TUNNEL | NETIF_F_GSO_GRE |
10701 NETIF_F_GSO_IPXIP4 |
10702 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_GSO_GRE_CSUM |
10703 NETIF_F_GSO_PARTIAL | NETIF_F_RXHASH |
10704 NETIF_F_RXCSUM | NETIF_F_GRO;
10706 if (BNXT_SUPPORTS_TPA(bp))
10707 dev->hw_features |= NETIF_F_LRO;
10709 dev->hw_enc_features =
10710 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG |
10711 NETIF_F_TSO | NETIF_F_TSO6 |
10712 NETIF_F_GSO_UDP_TUNNEL | NETIF_F_GSO_GRE |
10713 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_GSO_GRE_CSUM |
10714 NETIF_F_GSO_IPXIP4 | NETIF_F_GSO_PARTIAL;
10715 dev->gso_partial_features = NETIF_F_GSO_UDP_TUNNEL_CSUM |
10716 NETIF_F_GSO_GRE_CSUM;
10717 dev->vlan_features = dev->hw_features | NETIF_F_HIGHDMA;
10718 dev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX |
10719 NETIF_F_HW_VLAN_STAG_RX | NETIF_F_HW_VLAN_STAG_TX;
10720 if (BNXT_SUPPORTS_TPA(bp))
10721 dev->hw_features |= NETIF_F_GRO_HW;
10722 dev->features |= dev->hw_features | NETIF_F_HIGHDMA;
10723 if (dev->features & NETIF_F_GRO_HW)
10724 dev->features &= ~NETIF_F_LRO;
10725 dev->priv_flags |= IFF_UNICAST_FLT;
10727 #ifdef CONFIG_BNXT_SRIOV
10728 init_waitqueue_head(&bp->sriov_cfg_wait);
10729 mutex_init(&bp->sriov_lock);
10731 if (BNXT_SUPPORTS_TPA(bp)) {
10732 bp->gro_func = bnxt_gro_func_5730x;
10733 if (BNXT_CHIP_P4(bp))
10734 bp->gro_func = bnxt_gro_func_5731x;
10736 if (!BNXT_CHIP_P4_PLUS(bp))
10737 bp->flags |= BNXT_FLAG_DOUBLE_DB;
10739 rc = bnxt_hwrm_func_drv_rgtr(bp);
10741 goto init_err_pci_clean;
10743 rc = bnxt_hwrm_func_rgtr_async_events(bp, NULL, 0);
10745 goto init_err_pci_clean;
10747 bp->ulp_probe = bnxt_ulp_probe;
10749 rc = bnxt_hwrm_queue_qportcfg(bp);
10751 netdev_err(bp->dev, "hwrm query qportcfg failure rc: %x\n",
10754 goto init_err_pci_clean;
10756 /* Get the MAX capabilities for this function */
10757 rc = bnxt_hwrm_func_qcaps(bp);
10759 netdev_err(bp->dev, "hwrm query capability failure rc: %x\n",
10762 goto init_err_pci_clean;
10765 rc = bnxt_hwrm_cfa_adv_flow_mgnt_qcaps(bp);
10767 netdev_warn(bp->dev, "hwrm query adv flow mgnt failure rc: %d\n",
10770 rc = bnxt_init_mac_addr(bp);
10772 dev_err(&pdev->dev, "Unable to initialize mac address.\n");
10773 rc = -EADDRNOTAVAIL;
10774 goto init_err_pci_clean;
10778 /* Read the adapter's DSN to use as the eswitch switch_id */
10779 rc = bnxt_pcie_dsn_get(bp, bp->switch_id);
10781 goto init_err_pci_clean;
10783 bnxt_hwrm_func_qcfg(bp);
10784 bnxt_hwrm_vnic_qcaps(bp);
10785 bnxt_hwrm_port_led_qcaps(bp);
10786 bnxt_ethtool_init(bp);
10789 /* MTU range: 60 - FW defined max */
10790 dev->min_mtu = ETH_ZLEN;
10791 dev->max_mtu = bp->max_mtu;
10793 rc = bnxt_probe_phy(bp);
10795 goto init_err_pci_clean;
10797 bnxt_set_rx_skb_mode(bp, false);
10798 bnxt_set_tpa_flags(bp);
10799 bnxt_set_ring_params(bp);
10800 rc = bnxt_set_dflt_rings(bp, true);
10802 netdev_err(bp->dev, "Not enough rings available.\n");
10804 goto init_err_pci_clean;
10807 /* Default RSS hash cfg. */
10808 bp->rss_hash_cfg = VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4 |
10809 VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4 |
10810 VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6 |
10811 VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6;
10812 if (BNXT_CHIP_P4(bp) && bp->hwrm_spec_code >= 0x10501) {
10813 bp->flags |= BNXT_FLAG_UDP_RSS_CAP;
10814 bp->rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4 |
10815 VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6;
10818 if (bnxt_rfs_supported(bp)) {
10819 dev->hw_features |= NETIF_F_NTUPLE;
10820 if (bnxt_rfs_capable(bp)) {
10821 bp->flags |= BNXT_FLAG_RFS;
10822 dev->features |= NETIF_F_NTUPLE;
10826 if (dev->hw_features & NETIF_F_HW_VLAN_CTAG_RX)
10827 bp->flags |= BNXT_FLAG_STRIP_VLAN;
10829 rc = bnxt_init_int_mode(bp);
10831 goto init_err_pci_clean;
10833 /* No TC has been set yet and rings may have been trimmed due to
10834 * limited MSIX, so we re-initialize the TX rings per TC.
10836 bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
10838 bnxt_get_wol_settings(bp);
10839 if (bp->flags & BNXT_FLAG_WOL_CAP)
10840 device_set_wakeup_enable(&pdev->dev, bp->wol);
10842 device_set_wakeup_capable(&pdev->dev, false);
10844 bnxt_hwrm_set_cache_line_size(bp, cache_line_size());
10846 bnxt_hwrm_coal_params_qcaps(bp);
10851 create_singlethread_workqueue("bnxt_pf_wq");
10853 dev_err(&pdev->dev, "Unable to create workqueue.\n");
10854 goto init_err_pci_clean;
10860 rc = register_netdev(dev);
10862 goto init_err_cleanup_tc;
10865 bnxt_dl_register(bp);
10867 netdev_info(dev, "%s found at mem %lx, node addr %pM\n",
10868 board_info[ent->driver_data].name,
10869 (long)pci_resource_start(pdev, 0), dev->dev_addr);
10870 pcie_print_link_status(pdev);
10874 init_err_cleanup_tc:
10875 bnxt_shutdown_tc(bp);
10876 bnxt_clear_int_mode(bp);
10878 init_err_pci_clean:
10879 bnxt_free_hwrm_short_cmd_req(bp);
10880 bnxt_free_hwrm_resources(bp);
10881 bnxt_free_ctx_mem(bp);
10884 bnxt_cleanup_pci(bp);
10891 static void bnxt_shutdown(struct pci_dev *pdev)
10893 struct net_device *dev = pci_get_drvdata(pdev);
10900 bp = netdev_priv(dev);
10902 goto shutdown_exit;
10904 if (netif_running(dev))
10907 bnxt_ulp_shutdown(bp);
10909 if (system_state == SYSTEM_POWER_OFF) {
10910 bnxt_clear_int_mode(bp);
10911 pci_disable_device(pdev);
10912 pci_wake_from_d3(pdev, bp->wol);
10913 pci_set_power_state(pdev, PCI_D3hot);
10920 #ifdef CONFIG_PM_SLEEP
10921 static int bnxt_suspend(struct device *device)
10923 struct pci_dev *pdev = to_pci_dev(device);
10924 struct net_device *dev = pci_get_drvdata(pdev);
10925 struct bnxt *bp = netdev_priv(dev);
10929 if (netif_running(dev)) {
10930 netif_device_detach(dev);
10931 rc = bnxt_close(dev);
10933 bnxt_hwrm_func_drv_unrgtr(bp);
10938 static int bnxt_resume(struct device *device)
10940 struct pci_dev *pdev = to_pci_dev(device);
10941 struct net_device *dev = pci_get_drvdata(pdev);
10942 struct bnxt *bp = netdev_priv(dev);
10946 if (bnxt_hwrm_ver_get(bp) || bnxt_hwrm_func_drv_rgtr(bp)) {
10950 rc = bnxt_hwrm_func_reset(bp);
10955 bnxt_get_wol_settings(bp);
10956 if (netif_running(dev)) {
10957 rc = bnxt_open(dev);
10959 netif_device_attach(dev);
10967 static SIMPLE_DEV_PM_OPS(bnxt_pm_ops, bnxt_suspend, bnxt_resume);
10968 #define BNXT_PM_OPS (&bnxt_pm_ops)
10972 #define BNXT_PM_OPS NULL
10974 #endif /* CONFIG_PM_SLEEP */
10977 * bnxt_io_error_detected - called when PCI error is detected
10978 * @pdev: Pointer to PCI device
10979 * @state: The current pci connection state
10981 * This function is called after a PCI bus error affecting
10982 * this device has been detected.
10984 static pci_ers_result_t bnxt_io_error_detected(struct pci_dev *pdev,
10985 pci_channel_state_t state)
10987 struct net_device *netdev = pci_get_drvdata(pdev);
10988 struct bnxt *bp = netdev_priv(netdev);
10990 netdev_info(netdev, "PCI I/O error detected\n");
10993 netif_device_detach(netdev);
10997 if (state == pci_channel_io_perm_failure) {
10999 return PCI_ERS_RESULT_DISCONNECT;
11002 if (netif_running(netdev))
11003 bnxt_close(netdev);
11005 pci_disable_device(pdev);
11008 /* Request a slot slot reset. */
11009 return PCI_ERS_RESULT_NEED_RESET;
11013 * bnxt_io_slot_reset - called after the pci bus has been reset.
11014 * @pdev: Pointer to PCI device
11016 * Restart the card from scratch, as if from a cold-boot.
11017 * At this point, the card has exprienced a hard reset,
11018 * followed by fixups by BIOS, and has its config space
11019 * set up identically to what it was at cold boot.
11021 static pci_ers_result_t bnxt_io_slot_reset(struct pci_dev *pdev)
11023 struct net_device *netdev = pci_get_drvdata(pdev);
11024 struct bnxt *bp = netdev_priv(netdev);
11026 pci_ers_result_t result = PCI_ERS_RESULT_DISCONNECT;
11028 netdev_info(bp->dev, "PCI Slot Reset\n");
11032 if (pci_enable_device(pdev)) {
11033 dev_err(&pdev->dev,
11034 "Cannot re-enable PCI device after reset.\n");
11036 pci_set_master(pdev);
11038 err = bnxt_hwrm_func_reset(bp);
11039 if (!err && netif_running(netdev))
11040 err = bnxt_open(netdev);
11043 result = PCI_ERS_RESULT_RECOVERED;
11044 bnxt_ulp_start(bp);
11048 if (result != PCI_ERS_RESULT_RECOVERED && netif_running(netdev))
11053 return PCI_ERS_RESULT_RECOVERED;
11057 * bnxt_io_resume - called when traffic can start flowing again.
11058 * @pdev: Pointer to PCI device
11060 * This callback is called when the error recovery driver tells
11061 * us that its OK to resume normal operation.
11063 static void bnxt_io_resume(struct pci_dev *pdev)
11065 struct net_device *netdev = pci_get_drvdata(pdev);
11069 netif_device_attach(netdev);
11074 static const struct pci_error_handlers bnxt_err_handler = {
11075 .error_detected = bnxt_io_error_detected,
11076 .slot_reset = bnxt_io_slot_reset,
11077 .resume = bnxt_io_resume
11080 static struct pci_driver bnxt_pci_driver = {
11081 .name = DRV_MODULE_NAME,
11082 .id_table = bnxt_pci_tbl,
11083 .probe = bnxt_init_one,
11084 .remove = bnxt_remove_one,
11085 .shutdown = bnxt_shutdown,
11086 .driver.pm = BNXT_PM_OPS,
11087 .err_handler = &bnxt_err_handler,
11088 #if defined(CONFIG_BNXT_SRIOV)
11089 .sriov_configure = bnxt_sriov_configure,
11093 static int __init bnxt_init(void)
11096 return pci_register_driver(&bnxt_pci_driver);
11099 static void __exit bnxt_exit(void)
11101 pci_unregister_driver(&bnxt_pci_driver);
11103 destroy_workqueue(bnxt_pf_wq);
11107 module_init(bnxt_init);
11108 module_exit(bnxt_exit);