1 /* Broadcom NetXtreme-C/E network driver.
3 * Copyright (c) 2014-2016 Broadcom Corporation
4 * Copyright (c) 2016-2019 Broadcom Limited
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation.
11 #include <linux/module.h>
13 #include <linux/stringify.h>
14 #include <linux/kernel.h>
15 #include <linux/timer.h>
16 #include <linux/errno.h>
17 #include <linux/ioport.h>
18 #include <linux/slab.h>
19 #include <linux/vmalloc.h>
20 #include <linux/interrupt.h>
21 #include <linux/pci.h>
22 #include <linux/netdevice.h>
23 #include <linux/etherdevice.h>
24 #include <linux/skbuff.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/bitops.h>
28 #include <linux/irq.h>
29 #include <linux/delay.h>
30 #include <asm/byteorder.h>
32 #include <linux/time.h>
33 #include <linux/mii.h>
34 #include <linux/mdio.h>
36 #include <linux/if_vlan.h>
37 #include <linux/if_bridge.h>
38 #include <linux/rtc.h>
39 #include <linux/bpf.h>
43 #include <net/checksum.h>
44 #include <net/ip6_checksum.h>
45 #include <net/udp_tunnel.h>
46 #include <linux/workqueue.h>
47 #include <linux/prefetch.h>
48 #include <linux/cache.h>
49 #include <linux/log2.h>
50 #include <linux/aer.h>
51 #include <linux/bitmap.h>
52 #include <linux/cpu_rmap.h>
53 #include <linux/cpumask.h>
54 #include <net/pkt_cls.h>
55 #include <linux/hwmon.h>
56 #include <linux/hwmon-sysfs.h>
61 #include "bnxt_sriov.h"
62 #include "bnxt_ethtool.h"
67 #include "bnxt_devlink.h"
68 #include "bnxt_debugfs.h"
70 #define BNXT_TX_TIMEOUT (5 * HZ)
72 static const char version[] =
73 "Broadcom NetXtreme-C/E driver " DRV_MODULE_NAME " v" DRV_MODULE_VERSION "\n";
75 MODULE_LICENSE("GPL");
76 MODULE_DESCRIPTION("Broadcom BCM573xx network driver");
77 MODULE_VERSION(DRV_MODULE_VERSION);
79 #define BNXT_RX_OFFSET (NET_SKB_PAD + NET_IP_ALIGN)
80 #define BNXT_RX_DMA_OFFSET NET_SKB_PAD
81 #define BNXT_RX_COPY_THRESH 256
83 #define BNXT_TX_PUSH_THRESH 164
127 /* indexed by enum above */
128 static const struct {
131 [BCM57301] = { "Broadcom BCM57301 NetXtreme-C 10Gb Ethernet" },
132 [BCM57302] = { "Broadcom BCM57302 NetXtreme-C 10Gb/25Gb Ethernet" },
133 [BCM57304] = { "Broadcom BCM57304 NetXtreme-C 10Gb/25Gb/40Gb/50Gb Ethernet" },
134 [BCM57417_NPAR] = { "Broadcom BCM57417 NetXtreme-E Ethernet Partition" },
135 [BCM58700] = { "Broadcom BCM58700 Nitro 1Gb/2.5Gb/10Gb Ethernet" },
136 [BCM57311] = { "Broadcom BCM57311 NetXtreme-C 10Gb Ethernet" },
137 [BCM57312] = { "Broadcom BCM57312 NetXtreme-C 10Gb/25Gb Ethernet" },
138 [BCM57402] = { "Broadcom BCM57402 NetXtreme-E 10Gb Ethernet" },
139 [BCM57404] = { "Broadcom BCM57404 NetXtreme-E 10Gb/25Gb Ethernet" },
140 [BCM57406] = { "Broadcom BCM57406 NetXtreme-E 10GBase-T Ethernet" },
141 [BCM57402_NPAR] = { "Broadcom BCM57402 NetXtreme-E Ethernet Partition" },
142 [BCM57407] = { "Broadcom BCM57407 NetXtreme-E 10GBase-T Ethernet" },
143 [BCM57412] = { "Broadcom BCM57412 NetXtreme-E 10Gb Ethernet" },
144 [BCM57414] = { "Broadcom BCM57414 NetXtreme-E 10Gb/25Gb Ethernet" },
145 [BCM57416] = { "Broadcom BCM57416 NetXtreme-E 10GBase-T Ethernet" },
146 [BCM57417] = { "Broadcom BCM57417 NetXtreme-E 10GBase-T Ethernet" },
147 [BCM57412_NPAR] = { "Broadcom BCM57412 NetXtreme-E Ethernet Partition" },
148 [BCM57314] = { "Broadcom BCM57314 NetXtreme-C 10Gb/25Gb/40Gb/50Gb Ethernet" },
149 [BCM57417_SFP] = { "Broadcom BCM57417 NetXtreme-E 10Gb/25Gb Ethernet" },
150 [BCM57416_SFP] = { "Broadcom BCM57416 NetXtreme-E 10Gb Ethernet" },
151 [BCM57404_NPAR] = { "Broadcom BCM57404 NetXtreme-E Ethernet Partition" },
152 [BCM57406_NPAR] = { "Broadcom BCM57406 NetXtreme-E Ethernet Partition" },
153 [BCM57407_SFP] = { "Broadcom BCM57407 NetXtreme-E 25Gb Ethernet" },
154 [BCM57407_NPAR] = { "Broadcom BCM57407 NetXtreme-E Ethernet Partition" },
155 [BCM57414_NPAR] = { "Broadcom BCM57414 NetXtreme-E Ethernet Partition" },
156 [BCM57416_NPAR] = { "Broadcom BCM57416 NetXtreme-E Ethernet Partition" },
157 [BCM57452] = { "Broadcom BCM57452 NetXtreme-E 10Gb/25Gb/40Gb/50Gb Ethernet" },
158 [BCM57454] = { "Broadcom BCM57454 NetXtreme-E 10Gb/25Gb/40Gb/50Gb/100Gb Ethernet" },
159 [BCM5745x_NPAR] = { "Broadcom BCM5745x NetXtreme-E Ethernet Partition" },
160 [BCM57508] = { "Broadcom BCM57508 NetXtreme-E 10Gb/25Gb/50Gb/100Gb/200Gb Ethernet" },
161 [BCM57504] = { "Broadcom BCM57504 NetXtreme-E 10Gb/25Gb/50Gb/100Gb/200Gb Ethernet" },
162 [BCM57502] = { "Broadcom BCM57502 NetXtreme-E 10Gb/25Gb/50Gb Ethernet" },
163 [BCM58802] = { "Broadcom BCM58802 NetXtreme-S 10Gb/25Gb/40Gb/50Gb Ethernet" },
164 [BCM58804] = { "Broadcom BCM58804 NetXtreme-S 10Gb/25Gb/40Gb/50Gb/100Gb Ethernet" },
165 [BCM58808] = { "Broadcom BCM58808 NetXtreme-S 10Gb/25Gb/40Gb/50Gb/100Gb Ethernet" },
166 [NETXTREME_E_VF] = { "Broadcom NetXtreme-E Ethernet Virtual Function" },
167 [NETXTREME_C_VF] = { "Broadcom NetXtreme-C Ethernet Virtual Function" },
168 [NETXTREME_S_VF] = { "Broadcom NetXtreme-S Ethernet Virtual Function" },
169 [NETXTREME_E_P5_VF] = { "Broadcom BCM5750X NetXtreme-E Ethernet Virtual Function" },
172 static const struct pci_device_id bnxt_pci_tbl[] = {
173 { PCI_VDEVICE(BROADCOM, 0x1604), .driver_data = BCM5745x_NPAR },
174 { PCI_VDEVICE(BROADCOM, 0x1605), .driver_data = BCM5745x_NPAR },
175 { PCI_VDEVICE(BROADCOM, 0x1614), .driver_data = BCM57454 },
176 { PCI_VDEVICE(BROADCOM, 0x16c0), .driver_data = BCM57417_NPAR },
177 { PCI_VDEVICE(BROADCOM, 0x16c8), .driver_data = BCM57301 },
178 { PCI_VDEVICE(BROADCOM, 0x16c9), .driver_data = BCM57302 },
179 { PCI_VDEVICE(BROADCOM, 0x16ca), .driver_data = BCM57304 },
180 { PCI_VDEVICE(BROADCOM, 0x16cc), .driver_data = BCM57417_NPAR },
181 { PCI_VDEVICE(BROADCOM, 0x16cd), .driver_data = BCM58700 },
182 { PCI_VDEVICE(BROADCOM, 0x16ce), .driver_data = BCM57311 },
183 { PCI_VDEVICE(BROADCOM, 0x16cf), .driver_data = BCM57312 },
184 { PCI_VDEVICE(BROADCOM, 0x16d0), .driver_data = BCM57402 },
185 { PCI_VDEVICE(BROADCOM, 0x16d1), .driver_data = BCM57404 },
186 { PCI_VDEVICE(BROADCOM, 0x16d2), .driver_data = BCM57406 },
187 { PCI_VDEVICE(BROADCOM, 0x16d4), .driver_data = BCM57402_NPAR },
188 { PCI_VDEVICE(BROADCOM, 0x16d5), .driver_data = BCM57407 },
189 { PCI_VDEVICE(BROADCOM, 0x16d6), .driver_data = BCM57412 },
190 { PCI_VDEVICE(BROADCOM, 0x16d7), .driver_data = BCM57414 },
191 { PCI_VDEVICE(BROADCOM, 0x16d8), .driver_data = BCM57416 },
192 { PCI_VDEVICE(BROADCOM, 0x16d9), .driver_data = BCM57417 },
193 { PCI_VDEVICE(BROADCOM, 0x16de), .driver_data = BCM57412_NPAR },
194 { PCI_VDEVICE(BROADCOM, 0x16df), .driver_data = BCM57314 },
195 { PCI_VDEVICE(BROADCOM, 0x16e2), .driver_data = BCM57417_SFP },
196 { PCI_VDEVICE(BROADCOM, 0x16e3), .driver_data = BCM57416_SFP },
197 { PCI_VDEVICE(BROADCOM, 0x16e7), .driver_data = BCM57404_NPAR },
198 { PCI_VDEVICE(BROADCOM, 0x16e8), .driver_data = BCM57406_NPAR },
199 { PCI_VDEVICE(BROADCOM, 0x16e9), .driver_data = BCM57407_SFP },
200 { PCI_VDEVICE(BROADCOM, 0x16ea), .driver_data = BCM57407_NPAR },
201 { PCI_VDEVICE(BROADCOM, 0x16eb), .driver_data = BCM57412_NPAR },
202 { PCI_VDEVICE(BROADCOM, 0x16ec), .driver_data = BCM57414_NPAR },
203 { PCI_VDEVICE(BROADCOM, 0x16ed), .driver_data = BCM57414_NPAR },
204 { PCI_VDEVICE(BROADCOM, 0x16ee), .driver_data = BCM57416_NPAR },
205 { PCI_VDEVICE(BROADCOM, 0x16ef), .driver_data = BCM57416_NPAR },
206 { PCI_VDEVICE(BROADCOM, 0x16f0), .driver_data = BCM58808 },
207 { PCI_VDEVICE(BROADCOM, 0x16f1), .driver_data = BCM57452 },
208 { PCI_VDEVICE(BROADCOM, 0x1750), .driver_data = BCM57508 },
209 { PCI_VDEVICE(BROADCOM, 0x1751), .driver_data = BCM57504 },
210 { PCI_VDEVICE(BROADCOM, 0x1752), .driver_data = BCM57502 },
211 { PCI_VDEVICE(BROADCOM, 0xd802), .driver_data = BCM58802 },
212 { PCI_VDEVICE(BROADCOM, 0xd804), .driver_data = BCM58804 },
213 #ifdef CONFIG_BNXT_SRIOV
214 { PCI_VDEVICE(BROADCOM, 0x1606), .driver_data = NETXTREME_E_VF },
215 { PCI_VDEVICE(BROADCOM, 0x1609), .driver_data = NETXTREME_E_VF },
216 { PCI_VDEVICE(BROADCOM, 0x16c1), .driver_data = NETXTREME_E_VF },
217 { PCI_VDEVICE(BROADCOM, 0x16cb), .driver_data = NETXTREME_C_VF },
218 { PCI_VDEVICE(BROADCOM, 0x16d3), .driver_data = NETXTREME_E_VF },
219 { PCI_VDEVICE(BROADCOM, 0x16dc), .driver_data = NETXTREME_E_VF },
220 { PCI_VDEVICE(BROADCOM, 0x16e1), .driver_data = NETXTREME_C_VF },
221 { PCI_VDEVICE(BROADCOM, 0x16e5), .driver_data = NETXTREME_C_VF },
222 { PCI_VDEVICE(BROADCOM, 0x1806), .driver_data = NETXTREME_E_P5_VF },
223 { PCI_VDEVICE(BROADCOM, 0x1807), .driver_data = NETXTREME_E_P5_VF },
224 { PCI_VDEVICE(BROADCOM, 0xd800), .driver_data = NETXTREME_S_VF },
229 MODULE_DEVICE_TABLE(pci, bnxt_pci_tbl);
231 static const u16 bnxt_vf_req_snif[] = {
235 HWRM_CFA_L2_FILTER_ALLOC,
238 static const u16 bnxt_async_events_arr[] = {
239 ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE,
240 ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD,
241 ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED,
242 ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE,
243 ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE,
246 static struct workqueue_struct *bnxt_pf_wq;
248 static bool bnxt_vf_pciid(enum board_idx idx)
250 return (idx == NETXTREME_C_VF || idx == NETXTREME_E_VF ||
251 idx == NETXTREME_S_VF || idx == NETXTREME_E_P5_VF);
254 #define DB_CP_REARM_FLAGS (DB_KEY_CP | DB_IDX_VALID)
255 #define DB_CP_FLAGS (DB_KEY_CP | DB_IDX_VALID | DB_IRQ_DIS)
256 #define DB_CP_IRQ_DIS_FLAGS (DB_KEY_CP | DB_IRQ_DIS)
258 #define BNXT_CP_DB_IRQ_DIS(db) \
259 writel(DB_CP_IRQ_DIS_FLAGS, db)
261 #define BNXT_DB_CQ(db, idx) \
262 writel(DB_CP_FLAGS | RING_CMP(idx), (db)->doorbell)
264 #define BNXT_DB_NQ_P5(db, idx) \
265 writeq((db)->db_key64 | DBR_TYPE_NQ | RING_CMP(idx), (db)->doorbell)
267 #define BNXT_DB_CQ_ARM(db, idx) \
268 writel(DB_CP_REARM_FLAGS | RING_CMP(idx), (db)->doorbell)
270 #define BNXT_DB_NQ_ARM_P5(db, idx) \
271 writeq((db)->db_key64 | DBR_TYPE_NQ_ARM | RING_CMP(idx), (db)->doorbell)
273 static void bnxt_db_nq(struct bnxt *bp, struct bnxt_db_info *db, u32 idx)
275 if (bp->flags & BNXT_FLAG_CHIP_P5)
276 BNXT_DB_NQ_P5(db, idx);
281 static void bnxt_db_nq_arm(struct bnxt *bp, struct bnxt_db_info *db, u32 idx)
283 if (bp->flags & BNXT_FLAG_CHIP_P5)
284 BNXT_DB_NQ_ARM_P5(db, idx);
286 BNXT_DB_CQ_ARM(db, idx);
289 static void bnxt_db_cq(struct bnxt *bp, struct bnxt_db_info *db, u32 idx)
291 if (bp->flags & BNXT_FLAG_CHIP_P5)
292 writeq(db->db_key64 | DBR_TYPE_CQ_ARMALL | RING_CMP(idx),
298 const u16 bnxt_lhint_arr[] = {
299 TX_BD_FLAGS_LHINT_512_AND_SMALLER,
300 TX_BD_FLAGS_LHINT_512_TO_1023,
301 TX_BD_FLAGS_LHINT_1024_TO_2047,
302 TX_BD_FLAGS_LHINT_1024_TO_2047,
303 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
304 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
305 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
306 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
307 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
308 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
309 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
310 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
311 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
312 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
313 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
314 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
315 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
316 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
317 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
320 static u16 bnxt_xmit_get_cfa_action(struct sk_buff *skb)
322 struct metadata_dst *md_dst = skb_metadata_dst(skb);
324 if (!md_dst || md_dst->type != METADATA_HW_PORT_MUX)
327 return md_dst->u.port_info.port_id;
330 static netdev_tx_t bnxt_start_xmit(struct sk_buff *skb, struct net_device *dev)
332 struct bnxt *bp = netdev_priv(dev);
334 struct tx_bd_ext *txbd1;
335 struct netdev_queue *txq;
338 unsigned int length, pad = 0;
339 u32 len, free_size, vlan_tag_flags, cfa_action, flags;
341 struct pci_dev *pdev = bp->pdev;
342 struct bnxt_tx_ring_info *txr;
343 struct bnxt_sw_tx_bd *tx_buf;
345 i = skb_get_queue_mapping(skb);
346 if (unlikely(i >= bp->tx_nr_rings)) {
347 dev_kfree_skb_any(skb);
351 txq = netdev_get_tx_queue(dev, i);
352 txr = &bp->tx_ring[bp->tx_ring_map[i]];
355 free_size = bnxt_tx_avail(bp, txr);
356 if (unlikely(free_size < skb_shinfo(skb)->nr_frags + 2)) {
357 netif_tx_stop_queue(txq);
358 return NETDEV_TX_BUSY;
362 len = skb_headlen(skb);
363 last_frag = skb_shinfo(skb)->nr_frags;
365 txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
367 txbd->tx_bd_opaque = prod;
369 tx_buf = &txr->tx_buf_ring[prod];
371 tx_buf->nr_frags = last_frag;
374 cfa_action = bnxt_xmit_get_cfa_action(skb);
375 if (skb_vlan_tag_present(skb)) {
376 vlan_tag_flags = TX_BD_CFA_META_KEY_VLAN |
377 skb_vlan_tag_get(skb);
378 /* Currently supports 8021Q, 8021AD vlan offloads
379 * QINQ1, QINQ2, QINQ3 vlan headers are deprecated
381 if (skb->vlan_proto == htons(ETH_P_8021Q))
382 vlan_tag_flags |= 1 << TX_BD_CFA_META_TPID_SHIFT;
385 if (free_size == bp->tx_ring_size && length <= bp->tx_push_thresh) {
386 struct tx_push_buffer *tx_push_buf = txr->tx_push;
387 struct tx_push_bd *tx_push = &tx_push_buf->push_bd;
388 struct tx_bd_ext *tx_push1 = &tx_push->txbd2;
389 void __iomem *db = txr->tx_db.doorbell;
390 void *pdata = tx_push_buf->data;
394 /* Set COAL_NOW to be ready quickly for the next push */
395 tx_push->tx_bd_len_flags_type =
396 cpu_to_le32((length << TX_BD_LEN_SHIFT) |
397 TX_BD_TYPE_LONG_TX_BD |
398 TX_BD_FLAGS_LHINT_512_AND_SMALLER |
399 TX_BD_FLAGS_COAL_NOW |
400 TX_BD_FLAGS_PACKET_END |
401 (2 << TX_BD_FLAGS_BD_CNT_SHIFT));
403 if (skb->ip_summed == CHECKSUM_PARTIAL)
404 tx_push1->tx_bd_hsize_lflags =
405 cpu_to_le32(TX_BD_FLAGS_TCP_UDP_CHKSUM);
407 tx_push1->tx_bd_hsize_lflags = 0;
409 tx_push1->tx_bd_cfa_meta = cpu_to_le32(vlan_tag_flags);
410 tx_push1->tx_bd_cfa_action =
411 cpu_to_le32(cfa_action << TX_BD_CFA_ACTION_SHIFT);
413 end = pdata + length;
414 end = PTR_ALIGN(end, 8) - 1;
417 skb_copy_from_linear_data(skb, pdata, len);
419 for (j = 0; j < last_frag; j++) {
420 skb_frag_t *frag = &skb_shinfo(skb)->frags[j];
423 fptr = skb_frag_address_safe(frag);
427 memcpy(pdata, fptr, skb_frag_size(frag));
428 pdata += skb_frag_size(frag);
431 txbd->tx_bd_len_flags_type = tx_push->tx_bd_len_flags_type;
432 txbd->tx_bd_haddr = txr->data_mapping;
433 prod = NEXT_TX(prod);
434 txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
435 memcpy(txbd, tx_push1, sizeof(*txbd));
436 prod = NEXT_TX(prod);
438 cpu_to_le32(DB_KEY_TX_PUSH | DB_LONG_TX_PUSH | prod);
442 netdev_tx_sent_queue(txq, skb->len);
443 wmb(); /* Sync is_push and byte queue before pushing data */
445 push_len = (length + sizeof(*tx_push) + 7) / 8;
447 __iowrite64_copy(db, tx_push_buf, 16);
448 __iowrite32_copy(db + 4, tx_push_buf + 1,
449 (push_len - 16) << 1);
451 __iowrite64_copy(db, tx_push_buf, push_len);
458 if (length < BNXT_MIN_PKT_SIZE) {
459 pad = BNXT_MIN_PKT_SIZE - length;
460 if (skb_pad(skb, pad)) {
461 /* SKB already freed. */
465 length = BNXT_MIN_PKT_SIZE;
468 mapping = dma_map_single(&pdev->dev, skb->data, len, DMA_TO_DEVICE);
470 if (unlikely(dma_mapping_error(&pdev->dev, mapping))) {
471 dev_kfree_skb_any(skb);
476 dma_unmap_addr_set(tx_buf, mapping, mapping);
477 flags = (len << TX_BD_LEN_SHIFT) | TX_BD_TYPE_LONG_TX_BD |
478 ((last_frag + 2) << TX_BD_FLAGS_BD_CNT_SHIFT);
480 txbd->tx_bd_haddr = cpu_to_le64(mapping);
482 prod = NEXT_TX(prod);
483 txbd1 = (struct tx_bd_ext *)
484 &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
486 txbd1->tx_bd_hsize_lflags = 0;
487 if (skb_is_gso(skb)) {
490 if (skb->encapsulation)
491 hdr_len = skb_inner_network_offset(skb) +
492 skb_inner_network_header_len(skb) +
493 inner_tcp_hdrlen(skb);
495 hdr_len = skb_transport_offset(skb) +
498 txbd1->tx_bd_hsize_lflags = cpu_to_le32(TX_BD_FLAGS_LSO |
500 (hdr_len << (TX_BD_HSIZE_SHIFT - 1)));
501 length = skb_shinfo(skb)->gso_size;
502 txbd1->tx_bd_mss = cpu_to_le32(length);
504 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
505 txbd1->tx_bd_hsize_lflags =
506 cpu_to_le32(TX_BD_FLAGS_TCP_UDP_CHKSUM);
507 txbd1->tx_bd_mss = 0;
511 if (unlikely(length >= ARRAY_SIZE(bnxt_lhint_arr))) {
512 dev_warn_ratelimited(&pdev->dev, "Dropped oversize %d bytes TX packet.\n",
517 flags |= bnxt_lhint_arr[length];
518 txbd->tx_bd_len_flags_type = cpu_to_le32(flags);
520 txbd1->tx_bd_cfa_meta = cpu_to_le32(vlan_tag_flags);
521 txbd1->tx_bd_cfa_action =
522 cpu_to_le32(cfa_action << TX_BD_CFA_ACTION_SHIFT);
523 for (i = 0; i < last_frag; i++) {
524 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
526 prod = NEXT_TX(prod);
527 txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
529 len = skb_frag_size(frag);
530 mapping = skb_frag_dma_map(&pdev->dev, frag, 0, len,
533 if (unlikely(dma_mapping_error(&pdev->dev, mapping)))
536 tx_buf = &txr->tx_buf_ring[prod];
537 dma_unmap_addr_set(tx_buf, mapping, mapping);
539 txbd->tx_bd_haddr = cpu_to_le64(mapping);
541 flags = len << TX_BD_LEN_SHIFT;
542 txbd->tx_bd_len_flags_type = cpu_to_le32(flags);
546 txbd->tx_bd_len_flags_type =
547 cpu_to_le32(((len + pad) << TX_BD_LEN_SHIFT) | flags |
548 TX_BD_FLAGS_PACKET_END);
550 netdev_tx_sent_queue(txq, skb->len);
552 /* Sync BD data before updating doorbell */
555 prod = NEXT_TX(prod);
558 if (!netdev_xmit_more() || netif_xmit_stopped(txq))
559 bnxt_db_write(bp, &txr->tx_db, prod);
563 if (unlikely(bnxt_tx_avail(bp, txr) <= MAX_SKB_FRAGS + 1)) {
564 if (netdev_xmit_more() && !tx_buf->is_push)
565 bnxt_db_write(bp, &txr->tx_db, prod);
567 netif_tx_stop_queue(txq);
569 /* netif_tx_stop_queue() must be done before checking
570 * tx index in bnxt_tx_avail() below, because in
571 * bnxt_tx_int(), we update tx index before checking for
572 * netif_tx_queue_stopped().
575 if (bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh)
576 netif_tx_wake_queue(txq);
583 /* start back at beginning and unmap skb */
585 tx_buf = &txr->tx_buf_ring[prod];
587 dma_unmap_single(&pdev->dev, dma_unmap_addr(tx_buf, mapping),
588 skb_headlen(skb), PCI_DMA_TODEVICE);
589 prod = NEXT_TX(prod);
591 /* unmap remaining mapped pages */
592 for (i = 0; i < last_frag; i++) {
593 prod = NEXT_TX(prod);
594 tx_buf = &txr->tx_buf_ring[prod];
595 dma_unmap_page(&pdev->dev, dma_unmap_addr(tx_buf, mapping),
596 skb_frag_size(&skb_shinfo(skb)->frags[i]),
600 dev_kfree_skb_any(skb);
604 static void bnxt_tx_int(struct bnxt *bp, struct bnxt_napi *bnapi, int nr_pkts)
606 struct bnxt_tx_ring_info *txr = bnapi->tx_ring;
607 struct netdev_queue *txq = netdev_get_tx_queue(bp->dev, txr->txq_index);
608 u16 cons = txr->tx_cons;
609 struct pci_dev *pdev = bp->pdev;
611 unsigned int tx_bytes = 0;
613 for (i = 0; i < nr_pkts; i++) {
614 struct bnxt_sw_tx_bd *tx_buf;
618 tx_buf = &txr->tx_buf_ring[cons];
619 cons = NEXT_TX(cons);
623 if (tx_buf->is_push) {
628 dma_unmap_single(&pdev->dev, dma_unmap_addr(tx_buf, mapping),
629 skb_headlen(skb), PCI_DMA_TODEVICE);
630 last = tx_buf->nr_frags;
632 for (j = 0; j < last; j++) {
633 cons = NEXT_TX(cons);
634 tx_buf = &txr->tx_buf_ring[cons];
637 dma_unmap_addr(tx_buf, mapping),
638 skb_frag_size(&skb_shinfo(skb)->frags[j]),
643 cons = NEXT_TX(cons);
645 tx_bytes += skb->len;
646 dev_kfree_skb_any(skb);
649 netdev_tx_completed_queue(txq, nr_pkts, tx_bytes);
652 /* Need to make the tx_cons update visible to bnxt_start_xmit()
653 * before checking for netif_tx_queue_stopped(). Without the
654 * memory barrier, there is a small possibility that bnxt_start_xmit()
655 * will miss it and cause the queue to be stopped forever.
659 if (unlikely(netif_tx_queue_stopped(txq)) &&
660 (bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh)) {
661 __netif_tx_lock(txq, smp_processor_id());
662 if (netif_tx_queue_stopped(txq) &&
663 bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh &&
664 txr->dev_state != BNXT_DEV_STATE_CLOSING)
665 netif_tx_wake_queue(txq);
666 __netif_tx_unlock(txq);
670 static struct page *__bnxt_alloc_rx_page(struct bnxt *bp, dma_addr_t *mapping,
673 struct device *dev = &bp->pdev->dev;
676 page = alloc_page(gfp);
680 *mapping = dma_map_page_attrs(dev, page, 0, PAGE_SIZE, bp->rx_dir,
681 DMA_ATTR_WEAK_ORDERING);
682 if (dma_mapping_error(dev, *mapping)) {
686 *mapping += bp->rx_dma_offset;
690 static inline u8 *__bnxt_alloc_rx_data(struct bnxt *bp, dma_addr_t *mapping,
694 struct pci_dev *pdev = bp->pdev;
696 data = kmalloc(bp->rx_buf_size, gfp);
700 *mapping = dma_map_single_attrs(&pdev->dev, data + bp->rx_dma_offset,
701 bp->rx_buf_use_size, bp->rx_dir,
702 DMA_ATTR_WEAK_ORDERING);
704 if (dma_mapping_error(&pdev->dev, *mapping)) {
711 int bnxt_alloc_rx_data(struct bnxt *bp, struct bnxt_rx_ring_info *rxr,
714 struct rx_bd *rxbd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
715 struct bnxt_sw_rx_bd *rx_buf = &rxr->rx_buf_ring[prod];
718 if (BNXT_RX_PAGE_MODE(bp)) {
719 struct page *page = __bnxt_alloc_rx_page(bp, &mapping, gfp);
725 rx_buf->data_ptr = page_address(page) + bp->rx_offset;
727 u8 *data = __bnxt_alloc_rx_data(bp, &mapping, gfp);
733 rx_buf->data_ptr = data + bp->rx_offset;
735 rx_buf->mapping = mapping;
737 rxbd->rx_bd_haddr = cpu_to_le64(mapping);
741 void bnxt_reuse_rx_data(struct bnxt_rx_ring_info *rxr, u16 cons, void *data)
743 u16 prod = rxr->rx_prod;
744 struct bnxt_sw_rx_bd *cons_rx_buf, *prod_rx_buf;
745 struct rx_bd *cons_bd, *prod_bd;
747 prod_rx_buf = &rxr->rx_buf_ring[prod];
748 cons_rx_buf = &rxr->rx_buf_ring[cons];
750 prod_rx_buf->data = data;
751 prod_rx_buf->data_ptr = cons_rx_buf->data_ptr;
753 prod_rx_buf->mapping = cons_rx_buf->mapping;
755 prod_bd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
756 cons_bd = &rxr->rx_desc_ring[RX_RING(cons)][RX_IDX(cons)];
758 prod_bd->rx_bd_haddr = cons_bd->rx_bd_haddr;
761 static inline u16 bnxt_find_next_agg_idx(struct bnxt_rx_ring_info *rxr, u16 idx)
763 u16 next, max = rxr->rx_agg_bmap_size;
765 next = find_next_zero_bit(rxr->rx_agg_bmap, max, idx);
767 next = find_first_zero_bit(rxr->rx_agg_bmap, max);
771 static inline int bnxt_alloc_rx_page(struct bnxt *bp,
772 struct bnxt_rx_ring_info *rxr,
776 &rxr->rx_agg_desc_ring[RX_RING(prod)][RX_IDX(prod)];
777 struct bnxt_sw_rx_agg_bd *rx_agg_buf;
778 struct pci_dev *pdev = bp->pdev;
781 u16 sw_prod = rxr->rx_sw_agg_prod;
782 unsigned int offset = 0;
784 if (PAGE_SIZE > BNXT_RX_PAGE_SIZE) {
787 page = alloc_page(gfp);
791 rxr->rx_page_offset = 0;
793 offset = rxr->rx_page_offset;
794 rxr->rx_page_offset += BNXT_RX_PAGE_SIZE;
795 if (rxr->rx_page_offset == PAGE_SIZE)
800 page = alloc_page(gfp);
805 mapping = dma_map_page_attrs(&pdev->dev, page, offset,
806 BNXT_RX_PAGE_SIZE, PCI_DMA_FROMDEVICE,
807 DMA_ATTR_WEAK_ORDERING);
808 if (dma_mapping_error(&pdev->dev, mapping)) {
813 if (unlikely(test_bit(sw_prod, rxr->rx_agg_bmap)))
814 sw_prod = bnxt_find_next_agg_idx(rxr, sw_prod);
816 __set_bit(sw_prod, rxr->rx_agg_bmap);
817 rx_agg_buf = &rxr->rx_agg_ring[sw_prod];
818 rxr->rx_sw_agg_prod = NEXT_RX_AGG(sw_prod);
820 rx_agg_buf->page = page;
821 rx_agg_buf->offset = offset;
822 rx_agg_buf->mapping = mapping;
823 rxbd->rx_bd_haddr = cpu_to_le64(mapping);
824 rxbd->rx_bd_opaque = sw_prod;
828 static void bnxt_reuse_rx_agg_bufs(struct bnxt_cp_ring_info *cpr, u16 cp_cons,
831 struct bnxt_napi *bnapi = cpr->bnapi;
832 struct bnxt *bp = bnapi->bp;
833 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
834 u16 prod = rxr->rx_agg_prod;
835 u16 sw_prod = rxr->rx_sw_agg_prod;
838 for (i = 0; i < agg_bufs; i++) {
840 struct rx_agg_cmp *agg;
841 struct bnxt_sw_rx_agg_bd *cons_rx_buf, *prod_rx_buf;
842 struct rx_bd *prod_bd;
845 agg = (struct rx_agg_cmp *)
846 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
847 cons = agg->rx_agg_cmp_opaque;
848 __clear_bit(cons, rxr->rx_agg_bmap);
850 if (unlikely(test_bit(sw_prod, rxr->rx_agg_bmap)))
851 sw_prod = bnxt_find_next_agg_idx(rxr, sw_prod);
853 __set_bit(sw_prod, rxr->rx_agg_bmap);
854 prod_rx_buf = &rxr->rx_agg_ring[sw_prod];
855 cons_rx_buf = &rxr->rx_agg_ring[cons];
857 /* It is possible for sw_prod to be equal to cons, so
858 * set cons_rx_buf->page to NULL first.
860 page = cons_rx_buf->page;
861 cons_rx_buf->page = NULL;
862 prod_rx_buf->page = page;
863 prod_rx_buf->offset = cons_rx_buf->offset;
865 prod_rx_buf->mapping = cons_rx_buf->mapping;
867 prod_bd = &rxr->rx_agg_desc_ring[RX_RING(prod)][RX_IDX(prod)];
869 prod_bd->rx_bd_haddr = cpu_to_le64(cons_rx_buf->mapping);
870 prod_bd->rx_bd_opaque = sw_prod;
872 prod = NEXT_RX_AGG(prod);
873 sw_prod = NEXT_RX_AGG(sw_prod);
874 cp_cons = NEXT_CMP(cp_cons);
876 rxr->rx_agg_prod = prod;
877 rxr->rx_sw_agg_prod = sw_prod;
880 static struct sk_buff *bnxt_rx_page_skb(struct bnxt *bp,
881 struct bnxt_rx_ring_info *rxr,
882 u16 cons, void *data, u8 *data_ptr,
884 unsigned int offset_and_len)
886 unsigned int payload = offset_and_len >> 16;
887 unsigned int len = offset_and_len & 0xffff;
888 struct skb_frag_struct *frag;
889 struct page *page = data;
890 u16 prod = rxr->rx_prod;
894 err = bnxt_alloc_rx_data(bp, rxr, prod, GFP_ATOMIC);
896 bnxt_reuse_rx_data(rxr, cons, data);
899 dma_addr -= bp->rx_dma_offset;
900 dma_unmap_page_attrs(&bp->pdev->dev, dma_addr, PAGE_SIZE, bp->rx_dir,
901 DMA_ATTR_WEAK_ORDERING);
903 if (unlikely(!payload))
904 payload = eth_get_headlen(bp->dev, data_ptr, len);
906 skb = napi_alloc_skb(&rxr->bnapi->napi, payload);
912 off = (void *)data_ptr - page_address(page);
913 skb_add_rx_frag(skb, 0, page, off, len, PAGE_SIZE);
914 memcpy(skb->data - NET_IP_ALIGN, data_ptr - NET_IP_ALIGN,
915 payload + NET_IP_ALIGN);
917 frag = &skb_shinfo(skb)->frags[0];
918 skb_frag_size_sub(frag, payload);
919 frag->page_offset += payload;
920 skb->data_len -= payload;
921 skb->tail += payload;
926 static struct sk_buff *bnxt_rx_skb(struct bnxt *bp,
927 struct bnxt_rx_ring_info *rxr, u16 cons,
928 void *data, u8 *data_ptr,
930 unsigned int offset_and_len)
932 u16 prod = rxr->rx_prod;
936 err = bnxt_alloc_rx_data(bp, rxr, prod, GFP_ATOMIC);
938 bnxt_reuse_rx_data(rxr, cons, data);
942 skb = build_skb(data, 0);
943 dma_unmap_single_attrs(&bp->pdev->dev, dma_addr, bp->rx_buf_use_size,
944 bp->rx_dir, DMA_ATTR_WEAK_ORDERING);
950 skb_reserve(skb, bp->rx_offset);
951 skb_put(skb, offset_and_len & 0xffff);
955 static struct sk_buff *bnxt_rx_pages(struct bnxt *bp,
956 struct bnxt_cp_ring_info *cpr,
957 struct sk_buff *skb, u16 cp_cons,
960 struct bnxt_napi *bnapi = cpr->bnapi;
961 struct pci_dev *pdev = bp->pdev;
962 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
963 u16 prod = rxr->rx_agg_prod;
966 for (i = 0; i < agg_bufs; i++) {
968 struct rx_agg_cmp *agg;
969 struct bnxt_sw_rx_agg_bd *cons_rx_buf;
973 agg = (struct rx_agg_cmp *)
974 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
975 cons = agg->rx_agg_cmp_opaque;
976 frag_len = (le32_to_cpu(agg->rx_agg_cmp_len_flags_type) &
977 RX_AGG_CMP_LEN) >> RX_AGG_CMP_LEN_SHIFT;
979 cons_rx_buf = &rxr->rx_agg_ring[cons];
980 skb_fill_page_desc(skb, i, cons_rx_buf->page,
981 cons_rx_buf->offset, frag_len);
982 __clear_bit(cons, rxr->rx_agg_bmap);
984 /* It is possible for bnxt_alloc_rx_page() to allocate
985 * a sw_prod index that equals the cons index, so we
986 * need to clear the cons entry now.
988 mapping = cons_rx_buf->mapping;
989 page = cons_rx_buf->page;
990 cons_rx_buf->page = NULL;
992 if (bnxt_alloc_rx_page(bp, rxr, prod, GFP_ATOMIC) != 0) {
993 struct skb_shared_info *shinfo;
994 unsigned int nr_frags;
996 shinfo = skb_shinfo(skb);
997 nr_frags = --shinfo->nr_frags;
998 __skb_frag_set_page(&shinfo->frags[nr_frags], NULL);
1002 cons_rx_buf->page = page;
1004 /* Update prod since possibly some pages have been
1005 * allocated already.
1007 rxr->rx_agg_prod = prod;
1008 bnxt_reuse_rx_agg_bufs(cpr, cp_cons, agg_bufs - i);
1012 dma_unmap_page_attrs(&pdev->dev, mapping, BNXT_RX_PAGE_SIZE,
1014 DMA_ATTR_WEAK_ORDERING);
1016 skb->data_len += frag_len;
1017 skb->len += frag_len;
1018 skb->truesize += PAGE_SIZE;
1020 prod = NEXT_RX_AGG(prod);
1021 cp_cons = NEXT_CMP(cp_cons);
1023 rxr->rx_agg_prod = prod;
1027 static int bnxt_agg_bufs_valid(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1028 u8 agg_bufs, u32 *raw_cons)
1031 struct rx_agg_cmp *agg;
1033 *raw_cons = ADV_RAW_CMP(*raw_cons, agg_bufs);
1034 last = RING_CMP(*raw_cons);
1035 agg = (struct rx_agg_cmp *)
1036 &cpr->cp_desc_ring[CP_RING(last)][CP_IDX(last)];
1037 return RX_AGG_CMP_VALID(agg, *raw_cons);
1040 static inline struct sk_buff *bnxt_copy_skb(struct bnxt_napi *bnapi, u8 *data,
1044 struct bnxt *bp = bnapi->bp;
1045 struct pci_dev *pdev = bp->pdev;
1046 struct sk_buff *skb;
1048 skb = napi_alloc_skb(&bnapi->napi, len);
1052 dma_sync_single_for_cpu(&pdev->dev, mapping, bp->rx_copy_thresh,
1055 memcpy(skb->data - NET_IP_ALIGN, data - NET_IP_ALIGN,
1056 len + NET_IP_ALIGN);
1058 dma_sync_single_for_device(&pdev->dev, mapping, bp->rx_copy_thresh,
1065 static int bnxt_discard_rx(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1066 u32 *raw_cons, void *cmp)
1068 struct rx_cmp *rxcmp = cmp;
1069 u32 tmp_raw_cons = *raw_cons;
1070 u8 cmp_type, agg_bufs = 0;
1072 cmp_type = RX_CMP_TYPE(rxcmp);
1074 if (cmp_type == CMP_TYPE_RX_L2_CMP) {
1075 agg_bufs = (le32_to_cpu(rxcmp->rx_cmp_misc_v1) &
1077 RX_CMP_AGG_BUFS_SHIFT;
1078 } else if (cmp_type == CMP_TYPE_RX_L2_TPA_END_CMP) {
1079 struct rx_tpa_end_cmp *tpa_end = cmp;
1081 agg_bufs = (le32_to_cpu(tpa_end->rx_tpa_end_cmp_misc_v1) &
1082 RX_TPA_END_CMP_AGG_BUFS) >>
1083 RX_TPA_END_CMP_AGG_BUFS_SHIFT;
1087 if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, &tmp_raw_cons))
1090 *raw_cons = tmp_raw_cons;
1094 static void bnxt_queue_sp_work(struct bnxt *bp)
1097 queue_work(bnxt_pf_wq, &bp->sp_task);
1099 schedule_work(&bp->sp_task);
1102 static void bnxt_cancel_sp_work(struct bnxt *bp)
1105 flush_workqueue(bnxt_pf_wq);
1107 cancel_work_sync(&bp->sp_task);
1110 static void bnxt_sched_reset(struct bnxt *bp, struct bnxt_rx_ring_info *rxr)
1112 if (!rxr->bnapi->in_reset) {
1113 rxr->bnapi->in_reset = true;
1114 set_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event);
1115 bnxt_queue_sp_work(bp);
1117 rxr->rx_next_cons = 0xffff;
1120 static void bnxt_tpa_start(struct bnxt *bp, struct bnxt_rx_ring_info *rxr,
1121 struct rx_tpa_start_cmp *tpa_start,
1122 struct rx_tpa_start_cmp_ext *tpa_start1)
1124 u8 agg_id = TPA_START_AGG_ID(tpa_start);
1126 struct bnxt_tpa_info *tpa_info;
1127 struct bnxt_sw_rx_bd *cons_rx_buf, *prod_rx_buf;
1128 struct rx_bd *prod_bd;
1131 cons = tpa_start->rx_tpa_start_cmp_opaque;
1132 prod = rxr->rx_prod;
1133 cons_rx_buf = &rxr->rx_buf_ring[cons];
1134 prod_rx_buf = &rxr->rx_buf_ring[prod];
1135 tpa_info = &rxr->rx_tpa[agg_id];
1137 if (unlikely(cons != rxr->rx_next_cons)) {
1138 netdev_warn(bp->dev, "TPA cons %x != expected cons %x\n",
1139 cons, rxr->rx_next_cons);
1140 bnxt_sched_reset(bp, rxr);
1143 /* Store cfa_code in tpa_info to use in tpa_end
1144 * completion processing.
1146 tpa_info->cfa_code = TPA_START_CFA_CODE(tpa_start1);
1147 prod_rx_buf->data = tpa_info->data;
1148 prod_rx_buf->data_ptr = tpa_info->data_ptr;
1150 mapping = tpa_info->mapping;
1151 prod_rx_buf->mapping = mapping;
1153 prod_bd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
1155 prod_bd->rx_bd_haddr = cpu_to_le64(mapping);
1157 tpa_info->data = cons_rx_buf->data;
1158 tpa_info->data_ptr = cons_rx_buf->data_ptr;
1159 cons_rx_buf->data = NULL;
1160 tpa_info->mapping = cons_rx_buf->mapping;
1163 le32_to_cpu(tpa_start->rx_tpa_start_cmp_len_flags_type) >>
1164 RX_TPA_START_CMP_LEN_SHIFT;
1165 if (likely(TPA_START_HASH_VALID(tpa_start))) {
1166 u32 hash_type = TPA_START_HASH_TYPE(tpa_start);
1168 tpa_info->hash_type = PKT_HASH_TYPE_L4;
1169 tpa_info->gso_type = SKB_GSO_TCPV4;
1170 /* RSS profiles 1 and 3 with extract code 0 for inner 4-tuple */
1171 if (hash_type == 3 || TPA_START_IS_IPV6(tpa_start1))
1172 tpa_info->gso_type = SKB_GSO_TCPV6;
1173 tpa_info->rss_hash =
1174 le32_to_cpu(tpa_start->rx_tpa_start_cmp_rss_hash);
1176 tpa_info->hash_type = PKT_HASH_TYPE_NONE;
1177 tpa_info->gso_type = 0;
1178 if (netif_msg_rx_err(bp))
1179 netdev_warn(bp->dev, "TPA packet without valid hash\n");
1181 tpa_info->flags2 = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_flags2);
1182 tpa_info->metadata = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_metadata);
1183 tpa_info->hdr_info = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_hdr_info);
1185 rxr->rx_prod = NEXT_RX(prod);
1186 cons = NEXT_RX(cons);
1187 rxr->rx_next_cons = NEXT_RX(cons);
1188 cons_rx_buf = &rxr->rx_buf_ring[cons];
1190 bnxt_reuse_rx_data(rxr, cons, cons_rx_buf->data);
1191 rxr->rx_prod = NEXT_RX(rxr->rx_prod);
1192 cons_rx_buf->data = NULL;
1195 static void bnxt_abort_tpa(struct bnxt_cp_ring_info *cpr, u16 cp_cons,
1199 bnxt_reuse_rx_agg_bufs(cpr, cp_cons, agg_bufs);
1202 static struct sk_buff *bnxt_gro_func_5731x(struct bnxt_tpa_info *tpa_info,
1203 int payload_off, int tcp_ts,
1204 struct sk_buff *skb)
1209 u16 outer_ip_off, inner_ip_off, inner_mac_off;
1210 u32 hdr_info = tpa_info->hdr_info;
1211 bool loopback = false;
1213 inner_ip_off = BNXT_TPA_INNER_L3_OFF(hdr_info);
1214 inner_mac_off = BNXT_TPA_INNER_L2_OFF(hdr_info);
1215 outer_ip_off = BNXT_TPA_OUTER_L3_OFF(hdr_info);
1217 /* If the packet is an internal loopback packet, the offsets will
1218 * have an extra 4 bytes.
1220 if (inner_mac_off == 4) {
1222 } else if (inner_mac_off > 4) {
1223 __be16 proto = *((__be16 *)(skb->data + inner_ip_off -
1226 /* We only support inner iPv4/ipv6. If we don't see the
1227 * correct protocol ID, it must be a loopback packet where
1228 * the offsets are off by 4.
1230 if (proto != htons(ETH_P_IP) && proto != htons(ETH_P_IPV6))
1234 /* internal loopback packet, subtract all offsets by 4 */
1240 nw_off = inner_ip_off - ETH_HLEN;
1241 skb_set_network_header(skb, nw_off);
1242 if (tpa_info->flags2 & RX_TPA_START_CMP_FLAGS2_IP_TYPE) {
1243 struct ipv6hdr *iph = ipv6_hdr(skb);
1245 skb_set_transport_header(skb, nw_off + sizeof(struct ipv6hdr));
1246 len = skb->len - skb_transport_offset(skb);
1248 th->check = ~tcp_v6_check(len, &iph->saddr, &iph->daddr, 0);
1250 struct iphdr *iph = ip_hdr(skb);
1252 skb_set_transport_header(skb, nw_off + sizeof(struct iphdr));
1253 len = skb->len - skb_transport_offset(skb);
1255 th->check = ~tcp_v4_check(len, iph->saddr, iph->daddr, 0);
1258 if (inner_mac_off) { /* tunnel */
1259 struct udphdr *uh = NULL;
1260 __be16 proto = *((__be16 *)(skb->data + outer_ip_off -
1263 if (proto == htons(ETH_P_IP)) {
1264 struct iphdr *iph = (struct iphdr *)skb->data;
1266 if (iph->protocol == IPPROTO_UDP)
1267 uh = (struct udphdr *)(iph + 1);
1269 struct ipv6hdr *iph = (struct ipv6hdr *)skb->data;
1271 if (iph->nexthdr == IPPROTO_UDP)
1272 uh = (struct udphdr *)(iph + 1);
1276 skb_shinfo(skb)->gso_type |=
1277 SKB_GSO_UDP_TUNNEL_CSUM;
1279 skb_shinfo(skb)->gso_type |= SKB_GSO_UDP_TUNNEL;
1286 #define BNXT_IPV4_HDR_SIZE (sizeof(struct iphdr) + sizeof(struct tcphdr))
1287 #define BNXT_IPV6_HDR_SIZE (sizeof(struct ipv6hdr) + sizeof(struct tcphdr))
1289 static struct sk_buff *bnxt_gro_func_5730x(struct bnxt_tpa_info *tpa_info,
1290 int payload_off, int tcp_ts,
1291 struct sk_buff *skb)
1295 int len, nw_off, tcp_opt_len = 0;
1300 if (tpa_info->gso_type == SKB_GSO_TCPV4) {
1303 nw_off = payload_off - BNXT_IPV4_HDR_SIZE - tcp_opt_len -
1305 skb_set_network_header(skb, nw_off);
1307 skb_set_transport_header(skb, nw_off + sizeof(struct iphdr));
1308 len = skb->len - skb_transport_offset(skb);
1310 th->check = ~tcp_v4_check(len, iph->saddr, iph->daddr, 0);
1311 } else if (tpa_info->gso_type == SKB_GSO_TCPV6) {
1312 struct ipv6hdr *iph;
1314 nw_off = payload_off - BNXT_IPV6_HDR_SIZE - tcp_opt_len -
1316 skb_set_network_header(skb, nw_off);
1317 iph = ipv6_hdr(skb);
1318 skb_set_transport_header(skb, nw_off + sizeof(struct ipv6hdr));
1319 len = skb->len - skb_transport_offset(skb);
1321 th->check = ~tcp_v6_check(len, &iph->saddr, &iph->daddr, 0);
1323 dev_kfree_skb_any(skb);
1327 if (nw_off) { /* tunnel */
1328 struct udphdr *uh = NULL;
1330 if (skb->protocol == htons(ETH_P_IP)) {
1331 struct iphdr *iph = (struct iphdr *)skb->data;
1333 if (iph->protocol == IPPROTO_UDP)
1334 uh = (struct udphdr *)(iph + 1);
1336 struct ipv6hdr *iph = (struct ipv6hdr *)skb->data;
1338 if (iph->nexthdr == IPPROTO_UDP)
1339 uh = (struct udphdr *)(iph + 1);
1343 skb_shinfo(skb)->gso_type |=
1344 SKB_GSO_UDP_TUNNEL_CSUM;
1346 skb_shinfo(skb)->gso_type |= SKB_GSO_UDP_TUNNEL;
1353 static inline struct sk_buff *bnxt_gro_skb(struct bnxt *bp,
1354 struct bnxt_tpa_info *tpa_info,
1355 struct rx_tpa_end_cmp *tpa_end,
1356 struct rx_tpa_end_cmp_ext *tpa_end1,
1357 struct sk_buff *skb)
1363 segs = TPA_END_TPA_SEGS(tpa_end);
1367 NAPI_GRO_CB(skb)->count = segs;
1368 skb_shinfo(skb)->gso_size =
1369 le32_to_cpu(tpa_end1->rx_tpa_end_cmp_seg_len);
1370 skb_shinfo(skb)->gso_type = tpa_info->gso_type;
1371 payload_off = (le32_to_cpu(tpa_end->rx_tpa_end_cmp_misc_v1) &
1372 RX_TPA_END_CMP_PAYLOAD_OFFSET) >>
1373 RX_TPA_END_CMP_PAYLOAD_OFFSET_SHIFT;
1374 skb = bp->gro_func(tpa_info, payload_off, TPA_END_GRO_TS(tpa_end), skb);
1376 tcp_gro_complete(skb);
1381 /* Given the cfa_code of a received packet determine which
1382 * netdev (vf-rep or PF) the packet is destined to.
1384 static struct net_device *bnxt_get_pkt_dev(struct bnxt *bp, u16 cfa_code)
1386 struct net_device *dev = bnxt_get_vf_rep(bp, cfa_code);
1388 /* if vf-rep dev is NULL, the must belongs to the PF */
1389 return dev ? dev : bp->dev;
1392 static inline struct sk_buff *bnxt_tpa_end(struct bnxt *bp,
1393 struct bnxt_cp_ring_info *cpr,
1395 struct rx_tpa_end_cmp *tpa_end,
1396 struct rx_tpa_end_cmp_ext *tpa_end1,
1399 struct bnxt_napi *bnapi = cpr->bnapi;
1400 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
1401 u8 agg_id = TPA_END_AGG_ID(tpa_end);
1402 u8 *data_ptr, agg_bufs;
1403 u16 cp_cons = RING_CMP(*raw_cons);
1405 struct bnxt_tpa_info *tpa_info;
1407 struct sk_buff *skb;
1410 if (unlikely(bnapi->in_reset)) {
1411 int rc = bnxt_discard_rx(bp, cpr, raw_cons, tpa_end);
1414 return ERR_PTR(-EBUSY);
1418 tpa_info = &rxr->rx_tpa[agg_id];
1419 data = tpa_info->data;
1420 data_ptr = tpa_info->data_ptr;
1422 len = tpa_info->len;
1423 mapping = tpa_info->mapping;
1425 agg_bufs = (le32_to_cpu(tpa_end->rx_tpa_end_cmp_misc_v1) &
1426 RX_TPA_END_CMP_AGG_BUFS) >> RX_TPA_END_CMP_AGG_BUFS_SHIFT;
1429 if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, raw_cons))
1430 return ERR_PTR(-EBUSY);
1432 *event |= BNXT_AGG_EVENT;
1433 cp_cons = NEXT_CMP(cp_cons);
1436 if (unlikely(agg_bufs > MAX_SKB_FRAGS || TPA_END_ERRORS(tpa_end1))) {
1437 bnxt_abort_tpa(cpr, cp_cons, agg_bufs);
1438 if (agg_bufs > MAX_SKB_FRAGS)
1439 netdev_warn(bp->dev, "TPA frags %d exceeded MAX_SKB_FRAGS %d\n",
1440 agg_bufs, (int)MAX_SKB_FRAGS);
1444 if (len <= bp->rx_copy_thresh) {
1445 skb = bnxt_copy_skb(bnapi, data_ptr, len, mapping);
1447 bnxt_abort_tpa(cpr, cp_cons, agg_bufs);
1452 dma_addr_t new_mapping;
1454 new_data = __bnxt_alloc_rx_data(bp, &new_mapping, GFP_ATOMIC);
1456 bnxt_abort_tpa(cpr, cp_cons, agg_bufs);
1460 tpa_info->data = new_data;
1461 tpa_info->data_ptr = new_data + bp->rx_offset;
1462 tpa_info->mapping = new_mapping;
1464 skb = build_skb(data, 0);
1465 dma_unmap_single_attrs(&bp->pdev->dev, mapping,
1466 bp->rx_buf_use_size, bp->rx_dir,
1467 DMA_ATTR_WEAK_ORDERING);
1471 bnxt_abort_tpa(cpr, cp_cons, agg_bufs);
1474 skb_reserve(skb, bp->rx_offset);
1479 skb = bnxt_rx_pages(bp, cpr, skb, cp_cons, agg_bufs);
1481 /* Page reuse already handled by bnxt_rx_pages(). */
1487 eth_type_trans(skb, bnxt_get_pkt_dev(bp, tpa_info->cfa_code));
1489 if (tpa_info->hash_type != PKT_HASH_TYPE_NONE)
1490 skb_set_hash(skb, tpa_info->rss_hash, tpa_info->hash_type);
1492 if ((tpa_info->flags2 & RX_CMP_FLAGS2_META_FORMAT_VLAN) &&
1493 (skb->dev->features & NETIF_F_HW_VLAN_CTAG_RX)) {
1494 u16 vlan_proto = tpa_info->metadata >>
1495 RX_CMP_FLAGS2_METADATA_TPID_SFT;
1496 u16 vtag = tpa_info->metadata & RX_CMP_FLAGS2_METADATA_TCI_MASK;
1498 __vlan_hwaccel_put_tag(skb, htons(vlan_proto), vtag);
1501 skb_checksum_none_assert(skb);
1502 if (likely(tpa_info->flags2 & RX_TPA_START_CMP_FLAGS2_L4_CS_CALC)) {
1503 skb->ip_summed = CHECKSUM_UNNECESSARY;
1505 (tpa_info->flags2 & RX_CMP_FLAGS2_T_L4_CS_CALC) >> 3;
1508 if (TPA_END_GRO(tpa_end))
1509 skb = bnxt_gro_skb(bp, tpa_info, tpa_end, tpa_end1, skb);
1514 static void bnxt_deliver_skb(struct bnxt *bp, struct bnxt_napi *bnapi,
1515 struct sk_buff *skb)
1517 if (skb->dev != bp->dev) {
1518 /* this packet belongs to a vf-rep */
1519 bnxt_vf_rep_rx(bp, skb);
1522 skb_record_rx_queue(skb, bnapi->index);
1523 napi_gro_receive(&bnapi->napi, skb);
1526 /* returns the following:
1527 * 1 - 1 packet successfully received
1528 * 0 - successful TPA_START, packet not completed yet
1529 * -EBUSY - completion ring does not have all the agg buffers yet
1530 * -ENOMEM - packet aborted due to out of memory
1531 * -EIO - packet aborted due to hw error indicated in BD
1533 static int bnxt_rx_pkt(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1534 u32 *raw_cons, u8 *event)
1536 struct bnxt_napi *bnapi = cpr->bnapi;
1537 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
1538 struct net_device *dev = bp->dev;
1539 struct rx_cmp *rxcmp;
1540 struct rx_cmp_ext *rxcmp1;
1541 u32 tmp_raw_cons = *raw_cons;
1542 u16 cfa_code, cons, prod, cp_cons = RING_CMP(tmp_raw_cons);
1543 struct bnxt_sw_rx_bd *rx_buf;
1545 u8 *data_ptr, agg_bufs, cmp_type;
1546 dma_addr_t dma_addr;
1547 struct sk_buff *skb;
1552 rxcmp = (struct rx_cmp *)
1553 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1555 tmp_raw_cons = NEXT_RAW_CMP(tmp_raw_cons);
1556 cp_cons = RING_CMP(tmp_raw_cons);
1557 rxcmp1 = (struct rx_cmp_ext *)
1558 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1560 if (!RX_CMP_VALID(rxcmp1, tmp_raw_cons))
1563 cmp_type = RX_CMP_TYPE(rxcmp);
1565 prod = rxr->rx_prod;
1567 if (cmp_type == CMP_TYPE_RX_L2_TPA_START_CMP) {
1568 bnxt_tpa_start(bp, rxr, (struct rx_tpa_start_cmp *)rxcmp,
1569 (struct rx_tpa_start_cmp_ext *)rxcmp1);
1571 *event |= BNXT_RX_EVENT;
1572 goto next_rx_no_prod_no_len;
1574 } else if (cmp_type == CMP_TYPE_RX_L2_TPA_END_CMP) {
1575 skb = bnxt_tpa_end(bp, cpr, &tmp_raw_cons,
1576 (struct rx_tpa_end_cmp *)rxcmp,
1577 (struct rx_tpa_end_cmp_ext *)rxcmp1, event);
1584 bnxt_deliver_skb(bp, bnapi, skb);
1587 *event |= BNXT_RX_EVENT;
1588 goto next_rx_no_prod_no_len;
1591 cons = rxcmp->rx_cmp_opaque;
1592 if (unlikely(cons != rxr->rx_next_cons)) {
1593 int rc1 = bnxt_discard_rx(bp, cpr, raw_cons, rxcmp);
1595 netdev_warn(bp->dev, "RX cons %x != expected cons %x\n",
1596 cons, rxr->rx_next_cons);
1597 bnxt_sched_reset(bp, rxr);
1600 rx_buf = &rxr->rx_buf_ring[cons];
1601 data = rx_buf->data;
1602 data_ptr = rx_buf->data_ptr;
1605 misc = le32_to_cpu(rxcmp->rx_cmp_misc_v1);
1606 agg_bufs = (misc & RX_CMP_AGG_BUFS) >> RX_CMP_AGG_BUFS_SHIFT;
1609 if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, &tmp_raw_cons))
1612 cp_cons = NEXT_CMP(cp_cons);
1613 *event |= BNXT_AGG_EVENT;
1615 *event |= BNXT_RX_EVENT;
1617 rx_buf->data = NULL;
1618 if (rxcmp1->rx_cmp_cfa_code_errors_v2 & RX_CMP_L2_ERRORS) {
1619 u32 rx_err = le32_to_cpu(rxcmp1->rx_cmp_cfa_code_errors_v2);
1621 bnxt_reuse_rx_data(rxr, cons, data);
1623 bnxt_reuse_rx_agg_bufs(cpr, cp_cons, agg_bufs);
1626 if (rx_err & RX_CMPL_ERRORS_BUFFER_ERROR_MASK) {
1627 netdev_warn(bp->dev, "RX buffer error %x\n", rx_err);
1628 bnxt_sched_reset(bp, rxr);
1630 goto next_rx_no_len;
1633 len = le32_to_cpu(rxcmp->rx_cmp_len_flags_type) >> RX_CMP_LEN_SHIFT;
1634 dma_addr = rx_buf->mapping;
1636 if (bnxt_rx_xdp(bp, rxr, cons, data, &data_ptr, &len, event)) {
1641 if (len <= bp->rx_copy_thresh) {
1642 skb = bnxt_copy_skb(bnapi, data_ptr, len, dma_addr);
1643 bnxt_reuse_rx_data(rxr, cons, data);
1651 if (rx_buf->data_ptr == data_ptr)
1652 payload = misc & RX_CMP_PAYLOAD_OFFSET;
1655 skb = bp->rx_skb_func(bp, rxr, cons, data, data_ptr, dma_addr,
1664 skb = bnxt_rx_pages(bp, cpr, skb, cp_cons, agg_bufs);
1671 if (RX_CMP_HASH_VALID(rxcmp)) {
1672 u32 hash_type = RX_CMP_HASH_TYPE(rxcmp);
1673 enum pkt_hash_types type = PKT_HASH_TYPE_L4;
1675 /* RSS profiles 1 and 3 with extract code 0 for inner 4-tuple */
1676 if (hash_type != 1 && hash_type != 3)
1677 type = PKT_HASH_TYPE_L3;
1678 skb_set_hash(skb, le32_to_cpu(rxcmp->rx_cmp_rss_hash), type);
1681 cfa_code = RX_CMP_CFA_CODE(rxcmp1);
1682 skb->protocol = eth_type_trans(skb, bnxt_get_pkt_dev(bp, cfa_code));
1684 if ((rxcmp1->rx_cmp_flags2 &
1685 cpu_to_le32(RX_CMP_FLAGS2_META_FORMAT_VLAN)) &&
1686 (skb->dev->features & NETIF_F_HW_VLAN_CTAG_RX)) {
1687 u32 meta_data = le32_to_cpu(rxcmp1->rx_cmp_meta_data);
1688 u16 vtag = meta_data & RX_CMP_FLAGS2_METADATA_TCI_MASK;
1689 u16 vlan_proto = meta_data >> RX_CMP_FLAGS2_METADATA_TPID_SFT;
1691 __vlan_hwaccel_put_tag(skb, htons(vlan_proto), vtag);
1694 skb_checksum_none_assert(skb);
1695 if (RX_CMP_L4_CS_OK(rxcmp1)) {
1696 if (dev->features & NETIF_F_RXCSUM) {
1697 skb->ip_summed = CHECKSUM_UNNECESSARY;
1698 skb->csum_level = RX_CMP_ENCAP(rxcmp1);
1701 if (rxcmp1->rx_cmp_cfa_code_errors_v2 & RX_CMP_L4_CS_ERR_BITS) {
1702 if (dev->features & NETIF_F_RXCSUM)
1703 bnapi->cp_ring.rx_l4_csum_errors++;
1707 bnxt_deliver_skb(bp, bnapi, skb);
1711 cpr->rx_packets += 1;
1712 cpr->rx_bytes += len;
1715 rxr->rx_prod = NEXT_RX(prod);
1716 rxr->rx_next_cons = NEXT_RX(cons);
1718 next_rx_no_prod_no_len:
1719 *raw_cons = tmp_raw_cons;
1724 /* In netpoll mode, if we are using a combined completion ring, we need to
1725 * discard the rx packets and recycle the buffers.
1727 static int bnxt_force_rx_discard(struct bnxt *bp,
1728 struct bnxt_cp_ring_info *cpr,
1729 u32 *raw_cons, u8 *event)
1731 u32 tmp_raw_cons = *raw_cons;
1732 struct rx_cmp_ext *rxcmp1;
1733 struct rx_cmp *rxcmp;
1737 cp_cons = RING_CMP(tmp_raw_cons);
1738 rxcmp = (struct rx_cmp *)
1739 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1741 tmp_raw_cons = NEXT_RAW_CMP(tmp_raw_cons);
1742 cp_cons = RING_CMP(tmp_raw_cons);
1743 rxcmp1 = (struct rx_cmp_ext *)
1744 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1746 if (!RX_CMP_VALID(rxcmp1, tmp_raw_cons))
1749 cmp_type = RX_CMP_TYPE(rxcmp);
1750 if (cmp_type == CMP_TYPE_RX_L2_CMP) {
1751 rxcmp1->rx_cmp_cfa_code_errors_v2 |=
1752 cpu_to_le32(RX_CMPL_ERRORS_CRC_ERROR);
1753 } else if (cmp_type == CMP_TYPE_RX_L2_TPA_END_CMP) {
1754 struct rx_tpa_end_cmp_ext *tpa_end1;
1756 tpa_end1 = (struct rx_tpa_end_cmp_ext *)rxcmp1;
1757 tpa_end1->rx_tpa_end_cmp_errors_v2 |=
1758 cpu_to_le32(RX_TPA_END_CMP_ERRORS);
1760 return bnxt_rx_pkt(bp, cpr, raw_cons, event);
1763 #define BNXT_GET_EVENT_PORT(data) \
1765 ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK)
1767 static int bnxt_async_event_process(struct bnxt *bp,
1768 struct hwrm_async_event_cmpl *cmpl)
1770 u16 event_id = le16_to_cpu(cmpl->event_id);
1772 /* TODO CHIMP_FW: Define event id's for link change, error etc */
1774 case ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE: {
1775 u32 data1 = le32_to_cpu(cmpl->event_data1);
1776 struct bnxt_link_info *link_info = &bp->link_info;
1779 goto async_event_process_exit;
1781 /* print unsupported speed warning in forced speed mode only */
1782 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED) &&
1783 (data1 & 0x20000)) {
1784 u16 fw_speed = link_info->force_link_speed;
1785 u32 speed = bnxt_fw_to_ethtool_speed(fw_speed);
1787 if (speed != SPEED_UNKNOWN)
1788 netdev_warn(bp->dev, "Link speed %d no longer supported\n",
1791 set_bit(BNXT_LINK_SPEED_CHNG_SP_EVENT, &bp->sp_event);
1794 case ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE:
1795 set_bit(BNXT_LINK_CHNG_SP_EVENT, &bp->sp_event);
1797 case ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD:
1798 set_bit(BNXT_HWRM_PF_UNLOAD_SP_EVENT, &bp->sp_event);
1800 case ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED: {
1801 u32 data1 = le32_to_cpu(cmpl->event_data1);
1802 u16 port_id = BNXT_GET_EVENT_PORT(data1);
1807 if (bp->pf.port_id != port_id)
1810 set_bit(BNXT_HWRM_PORT_MODULE_SP_EVENT, &bp->sp_event);
1813 case ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE:
1815 goto async_event_process_exit;
1816 set_bit(BNXT_RESET_TASK_SILENT_SP_EVENT, &bp->sp_event);
1819 goto async_event_process_exit;
1821 bnxt_queue_sp_work(bp);
1822 async_event_process_exit:
1823 bnxt_ulp_async_events(bp, cmpl);
1827 static int bnxt_hwrm_handler(struct bnxt *bp, struct tx_cmp *txcmp)
1829 u16 cmpl_type = TX_CMP_TYPE(txcmp), vf_id, seq_id;
1830 struct hwrm_cmpl *h_cmpl = (struct hwrm_cmpl *)txcmp;
1831 struct hwrm_fwd_req_cmpl *fwd_req_cmpl =
1832 (struct hwrm_fwd_req_cmpl *)txcmp;
1834 switch (cmpl_type) {
1835 case CMPL_BASE_TYPE_HWRM_DONE:
1836 seq_id = le16_to_cpu(h_cmpl->sequence_id);
1837 if (seq_id == bp->hwrm_intr_seq_id)
1838 bp->hwrm_intr_seq_id = (u16)~bp->hwrm_intr_seq_id;
1840 netdev_err(bp->dev, "Invalid hwrm seq id %d\n", seq_id);
1843 case CMPL_BASE_TYPE_HWRM_FWD_REQ:
1844 vf_id = le16_to_cpu(fwd_req_cmpl->source_id);
1846 if ((vf_id < bp->pf.first_vf_id) ||
1847 (vf_id >= bp->pf.first_vf_id + bp->pf.active_vfs)) {
1848 netdev_err(bp->dev, "Msg contains invalid VF id %x\n",
1853 set_bit(vf_id - bp->pf.first_vf_id, bp->pf.vf_event_bmap);
1854 set_bit(BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT, &bp->sp_event);
1855 bnxt_queue_sp_work(bp);
1858 case CMPL_BASE_TYPE_HWRM_ASYNC_EVENT:
1859 bnxt_async_event_process(bp,
1860 (struct hwrm_async_event_cmpl *)txcmp);
1869 static irqreturn_t bnxt_msix(int irq, void *dev_instance)
1871 struct bnxt_napi *bnapi = dev_instance;
1872 struct bnxt *bp = bnapi->bp;
1873 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1874 u32 cons = RING_CMP(cpr->cp_raw_cons);
1877 prefetch(&cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]);
1878 napi_schedule(&bnapi->napi);
1882 static inline int bnxt_has_work(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1884 u32 raw_cons = cpr->cp_raw_cons;
1885 u16 cons = RING_CMP(raw_cons);
1886 struct tx_cmp *txcmp;
1888 txcmp = &cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)];
1890 return TX_CMP_VALID(txcmp, raw_cons);
1893 static irqreturn_t bnxt_inta(int irq, void *dev_instance)
1895 struct bnxt_napi *bnapi = dev_instance;
1896 struct bnxt *bp = bnapi->bp;
1897 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1898 u32 cons = RING_CMP(cpr->cp_raw_cons);
1901 prefetch(&cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]);
1903 if (!bnxt_has_work(bp, cpr)) {
1904 int_status = readl(bp->bar0 + BNXT_CAG_REG_LEGACY_INT_STATUS);
1905 /* return if erroneous interrupt */
1906 if (!(int_status & (0x10000 << cpr->cp_ring_struct.fw_ring_id)))
1910 /* disable ring IRQ */
1911 BNXT_CP_DB_IRQ_DIS(cpr->cp_db.doorbell);
1913 /* Return here if interrupt is shared and is disabled. */
1914 if (unlikely(atomic_read(&bp->intr_sem) != 0))
1917 napi_schedule(&bnapi->napi);
1921 static int __bnxt_poll_work(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1924 struct bnxt_napi *bnapi = cpr->bnapi;
1925 u32 raw_cons = cpr->cp_raw_cons;
1930 struct tx_cmp *txcmp;
1932 cpr->has_more_work = 0;
1936 cons = RING_CMP(raw_cons);
1937 txcmp = &cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)];
1939 if (!TX_CMP_VALID(txcmp, raw_cons))
1942 /* The valid test of the entry must be done first before
1943 * reading any further.
1946 cpr->had_work_done = 1;
1947 if (TX_CMP_TYPE(txcmp) == CMP_TYPE_TX_L2_CMP) {
1949 /* return full budget so NAPI will complete. */
1950 if (unlikely(tx_pkts > bp->tx_wake_thresh)) {
1952 raw_cons = NEXT_RAW_CMP(raw_cons);
1954 cpr->has_more_work = 1;
1957 } else if ((TX_CMP_TYPE(txcmp) & 0x30) == 0x10) {
1959 rc = bnxt_rx_pkt(bp, cpr, &raw_cons, &event);
1961 rc = bnxt_force_rx_discard(bp, cpr, &raw_cons,
1963 if (likely(rc >= 0))
1965 /* Increment rx_pkts when rc is -ENOMEM to count towards
1966 * the NAPI budget. Otherwise, we may potentially loop
1967 * here forever if we consistently cannot allocate
1970 else if (rc == -ENOMEM && budget)
1972 else if (rc == -EBUSY) /* partial completion */
1974 } else if (unlikely((TX_CMP_TYPE(txcmp) ==
1975 CMPL_BASE_TYPE_HWRM_DONE) ||
1976 (TX_CMP_TYPE(txcmp) ==
1977 CMPL_BASE_TYPE_HWRM_FWD_REQ) ||
1978 (TX_CMP_TYPE(txcmp) ==
1979 CMPL_BASE_TYPE_HWRM_ASYNC_EVENT))) {
1980 bnxt_hwrm_handler(bp, txcmp);
1982 raw_cons = NEXT_RAW_CMP(raw_cons);
1984 if (rx_pkts && rx_pkts == budget) {
1985 cpr->has_more_work = 1;
1990 if (event & BNXT_TX_EVENT) {
1991 struct bnxt_tx_ring_info *txr = bnapi->tx_ring;
1992 u16 prod = txr->tx_prod;
1994 /* Sync BD data before updating doorbell */
1997 bnxt_db_write_relaxed(bp, &txr->tx_db, prod);
2000 cpr->cp_raw_cons = raw_cons;
2001 bnapi->tx_pkts += tx_pkts;
2002 bnapi->events |= event;
2006 static void __bnxt_poll_work_done(struct bnxt *bp, struct bnxt_napi *bnapi)
2008 if (bnapi->tx_pkts) {
2009 bnapi->tx_int(bp, bnapi, bnapi->tx_pkts);
2013 if (bnapi->events & BNXT_RX_EVENT) {
2014 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
2016 bnxt_db_write(bp, &rxr->rx_db, rxr->rx_prod);
2017 if (bnapi->events & BNXT_AGG_EVENT)
2018 bnxt_db_write(bp, &rxr->rx_agg_db, rxr->rx_agg_prod);
2023 static int bnxt_poll_work(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
2026 struct bnxt_napi *bnapi = cpr->bnapi;
2029 rx_pkts = __bnxt_poll_work(bp, cpr, budget);
2031 /* ACK completion ring before freeing tx ring and producing new
2032 * buffers in rx/agg rings to prevent overflowing the completion
2035 bnxt_db_cq(bp, &cpr->cp_db, cpr->cp_raw_cons);
2037 __bnxt_poll_work_done(bp, bnapi);
2041 static int bnxt_poll_nitroa0(struct napi_struct *napi, int budget)
2043 struct bnxt_napi *bnapi = container_of(napi, struct bnxt_napi, napi);
2044 struct bnxt *bp = bnapi->bp;
2045 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
2046 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
2047 struct tx_cmp *txcmp;
2048 struct rx_cmp_ext *rxcmp1;
2049 u32 cp_cons, tmp_raw_cons;
2050 u32 raw_cons = cpr->cp_raw_cons;
2057 cp_cons = RING_CMP(raw_cons);
2058 txcmp = &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
2060 if (!TX_CMP_VALID(txcmp, raw_cons))
2063 if ((TX_CMP_TYPE(txcmp) & 0x30) == 0x10) {
2064 tmp_raw_cons = NEXT_RAW_CMP(raw_cons);
2065 cp_cons = RING_CMP(tmp_raw_cons);
2066 rxcmp1 = (struct rx_cmp_ext *)
2067 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
2069 if (!RX_CMP_VALID(rxcmp1, tmp_raw_cons))
2072 /* force an error to recycle the buffer */
2073 rxcmp1->rx_cmp_cfa_code_errors_v2 |=
2074 cpu_to_le32(RX_CMPL_ERRORS_CRC_ERROR);
2076 rc = bnxt_rx_pkt(bp, cpr, &raw_cons, &event);
2077 if (likely(rc == -EIO) && budget)
2079 else if (rc == -EBUSY) /* partial completion */
2081 } else if (unlikely(TX_CMP_TYPE(txcmp) ==
2082 CMPL_BASE_TYPE_HWRM_DONE)) {
2083 bnxt_hwrm_handler(bp, txcmp);
2086 "Invalid completion received on special ring\n");
2088 raw_cons = NEXT_RAW_CMP(raw_cons);
2090 if (rx_pkts == budget)
2094 cpr->cp_raw_cons = raw_cons;
2095 BNXT_DB_CQ(&cpr->cp_db, cpr->cp_raw_cons);
2096 bnxt_db_write(bp, &rxr->rx_db, rxr->rx_prod);
2098 if (event & BNXT_AGG_EVENT)
2099 bnxt_db_write(bp, &rxr->rx_agg_db, rxr->rx_agg_prod);
2101 if (!bnxt_has_work(bp, cpr) && rx_pkts < budget) {
2102 napi_complete_done(napi, rx_pkts);
2103 BNXT_DB_CQ_ARM(&cpr->cp_db, cpr->cp_raw_cons);
2108 static int bnxt_poll(struct napi_struct *napi, int budget)
2110 struct bnxt_napi *bnapi = container_of(napi, struct bnxt_napi, napi);
2111 struct bnxt *bp = bnapi->bp;
2112 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
2116 work_done += bnxt_poll_work(bp, cpr, budget - work_done);
2118 if (work_done >= budget) {
2120 BNXT_DB_CQ_ARM(&cpr->cp_db, cpr->cp_raw_cons);
2124 if (!bnxt_has_work(bp, cpr)) {
2125 if (napi_complete_done(napi, work_done))
2126 BNXT_DB_CQ_ARM(&cpr->cp_db, cpr->cp_raw_cons);
2130 if (bp->flags & BNXT_FLAG_DIM) {
2131 struct net_dim_sample dim_sample;
2133 net_dim_sample(cpr->event_ctr,
2137 net_dim(&cpr->dim, dim_sample);
2142 static int __bnxt_poll_cqs(struct bnxt *bp, struct bnxt_napi *bnapi, int budget)
2144 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
2145 int i, work_done = 0;
2147 for (i = 0; i < 2; i++) {
2148 struct bnxt_cp_ring_info *cpr2 = cpr->cp_ring_arr[i];
2151 work_done += __bnxt_poll_work(bp, cpr2,
2152 budget - work_done);
2153 cpr->has_more_work |= cpr2->has_more_work;
2159 static void __bnxt_poll_cqs_done(struct bnxt *bp, struct bnxt_napi *bnapi,
2160 u64 dbr_type, bool all)
2162 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
2165 for (i = 0; i < 2; i++) {
2166 struct bnxt_cp_ring_info *cpr2 = cpr->cp_ring_arr[i];
2167 struct bnxt_db_info *db;
2169 if (cpr2 && (all || cpr2->had_work_done)) {
2171 writeq(db->db_key64 | dbr_type |
2172 RING_CMP(cpr2->cp_raw_cons), db->doorbell);
2173 cpr2->had_work_done = 0;
2176 __bnxt_poll_work_done(bp, bnapi);
2179 static int bnxt_poll_p5(struct napi_struct *napi, int budget)
2181 struct bnxt_napi *bnapi = container_of(napi, struct bnxt_napi, napi);
2182 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
2183 u32 raw_cons = cpr->cp_raw_cons;
2184 struct bnxt *bp = bnapi->bp;
2185 struct nqe_cn *nqcmp;
2189 if (cpr->has_more_work) {
2190 cpr->has_more_work = 0;
2191 work_done = __bnxt_poll_cqs(bp, bnapi, budget);
2192 if (cpr->has_more_work) {
2193 __bnxt_poll_cqs_done(bp, bnapi, DBR_TYPE_CQ, false);
2196 __bnxt_poll_cqs_done(bp, bnapi, DBR_TYPE_CQ_ARMALL, true);
2197 if (napi_complete_done(napi, work_done))
2198 BNXT_DB_NQ_ARM_P5(&cpr->cp_db, cpr->cp_raw_cons);
2202 cons = RING_CMP(raw_cons);
2203 nqcmp = &cpr->nq_desc_ring[CP_RING(cons)][CP_IDX(cons)];
2205 if (!NQ_CMP_VALID(nqcmp, raw_cons)) {
2206 __bnxt_poll_cqs_done(bp, bnapi, DBR_TYPE_CQ_ARMALL,
2208 cpr->cp_raw_cons = raw_cons;
2209 if (napi_complete_done(napi, work_done))
2210 BNXT_DB_NQ_ARM_P5(&cpr->cp_db,
2215 /* The valid test of the entry must be done first before
2216 * reading any further.
2220 if (nqcmp->type == cpu_to_le16(NQ_CN_TYPE_CQ_NOTIFICATION)) {
2221 u32 idx = le32_to_cpu(nqcmp->cq_handle_low);
2222 struct bnxt_cp_ring_info *cpr2;
2224 cpr2 = cpr->cp_ring_arr[idx];
2225 work_done += __bnxt_poll_work(bp, cpr2,
2226 budget - work_done);
2227 cpr->has_more_work = cpr2->has_more_work;
2229 bnxt_hwrm_handler(bp, (struct tx_cmp *)nqcmp);
2231 raw_cons = NEXT_RAW_CMP(raw_cons);
2232 if (cpr->has_more_work)
2235 __bnxt_poll_cqs_done(bp, bnapi, DBR_TYPE_CQ, true);
2236 cpr->cp_raw_cons = raw_cons;
2240 static void bnxt_free_tx_skbs(struct bnxt *bp)
2243 struct pci_dev *pdev = bp->pdev;
2248 max_idx = bp->tx_nr_pages * TX_DESC_CNT;
2249 for (i = 0; i < bp->tx_nr_rings; i++) {
2250 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
2253 for (j = 0; j < max_idx;) {
2254 struct bnxt_sw_tx_bd *tx_buf = &txr->tx_buf_ring[j];
2255 struct sk_buff *skb = tx_buf->skb;
2265 if (tx_buf->is_push) {
2271 dma_unmap_single(&pdev->dev,
2272 dma_unmap_addr(tx_buf, mapping),
2276 last = tx_buf->nr_frags;
2278 for (k = 0; k < last; k++, j++) {
2279 int ring_idx = j & bp->tx_ring_mask;
2280 skb_frag_t *frag = &skb_shinfo(skb)->frags[k];
2282 tx_buf = &txr->tx_buf_ring[ring_idx];
2285 dma_unmap_addr(tx_buf, mapping),
2286 skb_frag_size(frag), PCI_DMA_TODEVICE);
2290 netdev_tx_reset_queue(netdev_get_tx_queue(bp->dev, i));
2294 static void bnxt_free_rx_skbs(struct bnxt *bp)
2296 int i, max_idx, max_agg_idx;
2297 struct pci_dev *pdev = bp->pdev;
2302 max_idx = bp->rx_nr_pages * RX_DESC_CNT;
2303 max_agg_idx = bp->rx_agg_nr_pages * RX_DESC_CNT;
2304 for (i = 0; i < bp->rx_nr_rings; i++) {
2305 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
2309 for (j = 0; j < MAX_TPA; j++) {
2310 struct bnxt_tpa_info *tpa_info =
2312 u8 *data = tpa_info->data;
2317 dma_unmap_single_attrs(&pdev->dev,
2319 bp->rx_buf_use_size,
2321 DMA_ATTR_WEAK_ORDERING);
2323 tpa_info->data = NULL;
2329 for (j = 0; j < max_idx; j++) {
2330 struct bnxt_sw_rx_bd *rx_buf = &rxr->rx_buf_ring[j];
2331 dma_addr_t mapping = rx_buf->mapping;
2332 void *data = rx_buf->data;
2337 rx_buf->data = NULL;
2339 if (BNXT_RX_PAGE_MODE(bp)) {
2340 mapping -= bp->rx_dma_offset;
2341 dma_unmap_page_attrs(&pdev->dev, mapping,
2342 PAGE_SIZE, bp->rx_dir,
2343 DMA_ATTR_WEAK_ORDERING);
2346 dma_unmap_single_attrs(&pdev->dev, mapping,
2347 bp->rx_buf_use_size,
2349 DMA_ATTR_WEAK_ORDERING);
2354 for (j = 0; j < max_agg_idx; j++) {
2355 struct bnxt_sw_rx_agg_bd *rx_agg_buf =
2356 &rxr->rx_agg_ring[j];
2357 struct page *page = rx_agg_buf->page;
2362 dma_unmap_page_attrs(&pdev->dev, rx_agg_buf->mapping,
2365 DMA_ATTR_WEAK_ORDERING);
2367 rx_agg_buf->page = NULL;
2368 __clear_bit(j, rxr->rx_agg_bmap);
2373 __free_page(rxr->rx_page);
2374 rxr->rx_page = NULL;
2379 static void bnxt_free_skbs(struct bnxt *bp)
2381 bnxt_free_tx_skbs(bp);
2382 bnxt_free_rx_skbs(bp);
2385 static void bnxt_free_ring(struct bnxt *bp, struct bnxt_ring_mem_info *rmem)
2387 struct pci_dev *pdev = bp->pdev;
2390 for (i = 0; i < rmem->nr_pages; i++) {
2391 if (!rmem->pg_arr[i])
2394 dma_free_coherent(&pdev->dev, rmem->page_size,
2395 rmem->pg_arr[i], rmem->dma_arr[i]);
2397 rmem->pg_arr[i] = NULL;
2400 size_t pg_tbl_size = rmem->nr_pages * 8;
2402 if (rmem->flags & BNXT_RMEM_USE_FULL_PAGE_FLAG)
2403 pg_tbl_size = rmem->page_size;
2404 dma_free_coherent(&pdev->dev, pg_tbl_size,
2405 rmem->pg_tbl, rmem->pg_tbl_map);
2406 rmem->pg_tbl = NULL;
2408 if (rmem->vmem_size && *rmem->vmem) {
2414 static int bnxt_alloc_ring(struct bnxt *bp, struct bnxt_ring_mem_info *rmem)
2416 struct pci_dev *pdev = bp->pdev;
2420 if (rmem->flags & (BNXT_RMEM_VALID_PTE_FLAG | BNXT_RMEM_RING_PTE_FLAG))
2421 valid_bit = PTU_PTE_VALID;
2422 if ((rmem->nr_pages > 1 || rmem->depth > 0) && !rmem->pg_tbl) {
2423 size_t pg_tbl_size = rmem->nr_pages * 8;
2425 if (rmem->flags & BNXT_RMEM_USE_FULL_PAGE_FLAG)
2426 pg_tbl_size = rmem->page_size;
2427 rmem->pg_tbl = dma_alloc_coherent(&pdev->dev, pg_tbl_size,
2434 for (i = 0; i < rmem->nr_pages; i++) {
2435 u64 extra_bits = valid_bit;
2437 rmem->pg_arr[i] = dma_alloc_coherent(&pdev->dev,
2441 if (!rmem->pg_arr[i])
2444 if (rmem->nr_pages > 1 || rmem->depth > 0) {
2445 if (i == rmem->nr_pages - 2 &&
2446 (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
2447 extra_bits |= PTU_PTE_NEXT_TO_LAST;
2448 else if (i == rmem->nr_pages - 1 &&
2449 (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
2450 extra_bits |= PTU_PTE_LAST;
2452 cpu_to_le64(rmem->dma_arr[i] | extra_bits);
2456 if (rmem->vmem_size) {
2457 *rmem->vmem = vzalloc(rmem->vmem_size);
2464 static void bnxt_free_rx_rings(struct bnxt *bp)
2471 for (i = 0; i < bp->rx_nr_rings; i++) {
2472 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
2473 struct bnxt_ring_struct *ring;
2476 bpf_prog_put(rxr->xdp_prog);
2478 if (xdp_rxq_info_is_reg(&rxr->xdp_rxq))
2479 xdp_rxq_info_unreg(&rxr->xdp_rxq);
2484 kfree(rxr->rx_agg_bmap);
2485 rxr->rx_agg_bmap = NULL;
2487 ring = &rxr->rx_ring_struct;
2488 bnxt_free_ring(bp, &ring->ring_mem);
2490 ring = &rxr->rx_agg_ring_struct;
2491 bnxt_free_ring(bp, &ring->ring_mem);
2495 static int bnxt_alloc_rx_rings(struct bnxt *bp)
2497 int i, rc, agg_rings = 0, tpa_rings = 0;
2502 if (bp->flags & BNXT_FLAG_AGG_RINGS)
2505 if (bp->flags & BNXT_FLAG_TPA)
2508 for (i = 0; i < bp->rx_nr_rings; i++) {
2509 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
2510 struct bnxt_ring_struct *ring;
2512 ring = &rxr->rx_ring_struct;
2514 rc = xdp_rxq_info_reg(&rxr->xdp_rxq, bp->dev, i);
2518 rc = bnxt_alloc_ring(bp, &ring->ring_mem);
2526 ring = &rxr->rx_agg_ring_struct;
2527 rc = bnxt_alloc_ring(bp, &ring->ring_mem);
2532 rxr->rx_agg_bmap_size = bp->rx_agg_ring_mask + 1;
2533 mem_size = rxr->rx_agg_bmap_size / 8;
2534 rxr->rx_agg_bmap = kzalloc(mem_size, GFP_KERNEL);
2535 if (!rxr->rx_agg_bmap)
2539 rxr->rx_tpa = kcalloc(MAX_TPA,
2540 sizeof(struct bnxt_tpa_info),
2550 static void bnxt_free_tx_rings(struct bnxt *bp)
2553 struct pci_dev *pdev = bp->pdev;
2558 for (i = 0; i < bp->tx_nr_rings; i++) {
2559 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
2560 struct bnxt_ring_struct *ring;
2563 dma_free_coherent(&pdev->dev, bp->tx_push_size,
2564 txr->tx_push, txr->tx_push_mapping);
2565 txr->tx_push = NULL;
2568 ring = &txr->tx_ring_struct;
2570 bnxt_free_ring(bp, &ring->ring_mem);
2574 static int bnxt_alloc_tx_rings(struct bnxt *bp)
2577 struct pci_dev *pdev = bp->pdev;
2579 bp->tx_push_size = 0;
2580 if (bp->tx_push_thresh) {
2583 push_size = L1_CACHE_ALIGN(sizeof(struct tx_push_bd) +
2584 bp->tx_push_thresh);
2586 if (push_size > 256) {
2588 bp->tx_push_thresh = 0;
2591 bp->tx_push_size = push_size;
2594 for (i = 0, j = 0; i < bp->tx_nr_rings; i++) {
2595 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
2596 struct bnxt_ring_struct *ring;
2599 ring = &txr->tx_ring_struct;
2601 rc = bnxt_alloc_ring(bp, &ring->ring_mem);
2605 ring->grp_idx = txr->bnapi->index;
2606 if (bp->tx_push_size) {
2609 /* One pre-allocated DMA buffer to backup
2612 txr->tx_push = dma_alloc_coherent(&pdev->dev,
2614 &txr->tx_push_mapping,
2620 mapping = txr->tx_push_mapping +
2621 sizeof(struct tx_push_bd);
2622 txr->data_mapping = cpu_to_le64(mapping);
2624 memset(txr->tx_push, 0, sizeof(struct tx_push_bd));
2626 qidx = bp->tc_to_qidx[j];
2627 ring->queue_id = bp->q_info[qidx].queue_id;
2628 if (i < bp->tx_nr_rings_xdp)
2630 if (i % bp->tx_nr_rings_per_tc == (bp->tx_nr_rings_per_tc - 1))
2636 static void bnxt_free_cp_rings(struct bnxt *bp)
2643 for (i = 0; i < bp->cp_nr_rings; i++) {
2644 struct bnxt_napi *bnapi = bp->bnapi[i];
2645 struct bnxt_cp_ring_info *cpr;
2646 struct bnxt_ring_struct *ring;
2652 cpr = &bnapi->cp_ring;
2653 ring = &cpr->cp_ring_struct;
2655 bnxt_free_ring(bp, &ring->ring_mem);
2657 for (j = 0; j < 2; j++) {
2658 struct bnxt_cp_ring_info *cpr2 = cpr->cp_ring_arr[j];
2661 ring = &cpr2->cp_ring_struct;
2662 bnxt_free_ring(bp, &ring->ring_mem);
2664 cpr->cp_ring_arr[j] = NULL;
2670 static struct bnxt_cp_ring_info *bnxt_alloc_cp_sub_ring(struct bnxt *bp)
2672 struct bnxt_ring_mem_info *rmem;
2673 struct bnxt_ring_struct *ring;
2674 struct bnxt_cp_ring_info *cpr;
2677 cpr = kzalloc(sizeof(*cpr), GFP_KERNEL);
2681 ring = &cpr->cp_ring_struct;
2682 rmem = &ring->ring_mem;
2683 rmem->nr_pages = bp->cp_nr_pages;
2684 rmem->page_size = HW_CMPD_RING_SIZE;
2685 rmem->pg_arr = (void **)cpr->cp_desc_ring;
2686 rmem->dma_arr = cpr->cp_desc_mapping;
2687 rmem->flags = BNXT_RMEM_RING_PTE_FLAG;
2688 rc = bnxt_alloc_ring(bp, rmem);
2690 bnxt_free_ring(bp, rmem);
2697 static int bnxt_alloc_cp_rings(struct bnxt *bp)
2699 bool sh = !!(bp->flags & BNXT_FLAG_SHARED_RINGS);
2700 int i, rc, ulp_base_vec, ulp_msix;
2702 ulp_msix = bnxt_get_ulp_msix_num(bp);
2703 ulp_base_vec = bnxt_get_ulp_msix_base(bp);
2704 for (i = 0; i < bp->cp_nr_rings; i++) {
2705 struct bnxt_napi *bnapi = bp->bnapi[i];
2706 struct bnxt_cp_ring_info *cpr;
2707 struct bnxt_ring_struct *ring;
2712 cpr = &bnapi->cp_ring;
2714 ring = &cpr->cp_ring_struct;
2716 rc = bnxt_alloc_ring(bp, &ring->ring_mem);
2720 if (ulp_msix && i >= ulp_base_vec)
2721 ring->map_idx = i + ulp_msix;
2725 if (!(bp->flags & BNXT_FLAG_CHIP_P5))
2728 if (i < bp->rx_nr_rings) {
2729 struct bnxt_cp_ring_info *cpr2 =
2730 bnxt_alloc_cp_sub_ring(bp);
2732 cpr->cp_ring_arr[BNXT_RX_HDL] = cpr2;
2735 cpr2->bnapi = bnapi;
2737 if ((sh && i < bp->tx_nr_rings) ||
2738 (!sh && i >= bp->rx_nr_rings)) {
2739 struct bnxt_cp_ring_info *cpr2 =
2740 bnxt_alloc_cp_sub_ring(bp);
2742 cpr->cp_ring_arr[BNXT_TX_HDL] = cpr2;
2745 cpr2->bnapi = bnapi;
2751 static void bnxt_init_ring_struct(struct bnxt *bp)
2755 for (i = 0; i < bp->cp_nr_rings; i++) {
2756 struct bnxt_napi *bnapi = bp->bnapi[i];
2757 struct bnxt_ring_mem_info *rmem;
2758 struct bnxt_cp_ring_info *cpr;
2759 struct bnxt_rx_ring_info *rxr;
2760 struct bnxt_tx_ring_info *txr;
2761 struct bnxt_ring_struct *ring;
2766 cpr = &bnapi->cp_ring;
2767 ring = &cpr->cp_ring_struct;
2768 rmem = &ring->ring_mem;
2769 rmem->nr_pages = bp->cp_nr_pages;
2770 rmem->page_size = HW_CMPD_RING_SIZE;
2771 rmem->pg_arr = (void **)cpr->cp_desc_ring;
2772 rmem->dma_arr = cpr->cp_desc_mapping;
2773 rmem->vmem_size = 0;
2775 rxr = bnapi->rx_ring;
2779 ring = &rxr->rx_ring_struct;
2780 rmem = &ring->ring_mem;
2781 rmem->nr_pages = bp->rx_nr_pages;
2782 rmem->page_size = HW_RXBD_RING_SIZE;
2783 rmem->pg_arr = (void **)rxr->rx_desc_ring;
2784 rmem->dma_arr = rxr->rx_desc_mapping;
2785 rmem->vmem_size = SW_RXBD_RING_SIZE * bp->rx_nr_pages;
2786 rmem->vmem = (void **)&rxr->rx_buf_ring;
2788 ring = &rxr->rx_agg_ring_struct;
2789 rmem = &ring->ring_mem;
2790 rmem->nr_pages = bp->rx_agg_nr_pages;
2791 rmem->page_size = HW_RXBD_RING_SIZE;
2792 rmem->pg_arr = (void **)rxr->rx_agg_desc_ring;
2793 rmem->dma_arr = rxr->rx_agg_desc_mapping;
2794 rmem->vmem_size = SW_RXBD_AGG_RING_SIZE * bp->rx_agg_nr_pages;
2795 rmem->vmem = (void **)&rxr->rx_agg_ring;
2798 txr = bnapi->tx_ring;
2802 ring = &txr->tx_ring_struct;
2803 rmem = &ring->ring_mem;
2804 rmem->nr_pages = bp->tx_nr_pages;
2805 rmem->page_size = HW_RXBD_RING_SIZE;
2806 rmem->pg_arr = (void **)txr->tx_desc_ring;
2807 rmem->dma_arr = txr->tx_desc_mapping;
2808 rmem->vmem_size = SW_TXBD_RING_SIZE * bp->tx_nr_pages;
2809 rmem->vmem = (void **)&txr->tx_buf_ring;
2813 static void bnxt_init_rxbd_pages(struct bnxt_ring_struct *ring, u32 type)
2817 struct rx_bd **rx_buf_ring;
2819 rx_buf_ring = (struct rx_bd **)ring->ring_mem.pg_arr;
2820 for (i = 0, prod = 0; i < ring->ring_mem.nr_pages; i++) {
2824 rxbd = rx_buf_ring[i];
2828 for (j = 0; j < RX_DESC_CNT; j++, rxbd++, prod++) {
2829 rxbd->rx_bd_len_flags_type = cpu_to_le32(type);
2830 rxbd->rx_bd_opaque = prod;
2835 static int bnxt_init_one_rx_ring(struct bnxt *bp, int ring_nr)
2837 struct net_device *dev = bp->dev;
2838 struct bnxt_rx_ring_info *rxr;
2839 struct bnxt_ring_struct *ring;
2843 type = (bp->rx_buf_use_size << RX_BD_LEN_SHIFT) |
2844 RX_BD_TYPE_RX_PACKET_BD | RX_BD_FLAGS_EOP;
2846 if (NET_IP_ALIGN == 2)
2847 type |= RX_BD_FLAGS_SOP;
2849 rxr = &bp->rx_ring[ring_nr];
2850 ring = &rxr->rx_ring_struct;
2851 bnxt_init_rxbd_pages(ring, type);
2853 if (BNXT_RX_PAGE_MODE(bp) && bp->xdp_prog) {
2854 rxr->xdp_prog = bpf_prog_add(bp->xdp_prog, 1);
2855 if (IS_ERR(rxr->xdp_prog)) {
2856 int rc = PTR_ERR(rxr->xdp_prog);
2858 rxr->xdp_prog = NULL;
2862 prod = rxr->rx_prod;
2863 for (i = 0; i < bp->rx_ring_size; i++) {
2864 if (bnxt_alloc_rx_data(bp, rxr, prod, GFP_KERNEL) != 0) {
2865 netdev_warn(dev, "init'ed rx ring %d with %d/%d skbs only\n",
2866 ring_nr, i, bp->rx_ring_size);
2869 prod = NEXT_RX(prod);
2871 rxr->rx_prod = prod;
2872 ring->fw_ring_id = INVALID_HW_RING_ID;
2874 ring = &rxr->rx_agg_ring_struct;
2875 ring->fw_ring_id = INVALID_HW_RING_ID;
2877 if (!(bp->flags & BNXT_FLAG_AGG_RINGS))
2880 type = ((u32)BNXT_RX_PAGE_SIZE << RX_BD_LEN_SHIFT) |
2881 RX_BD_TYPE_RX_AGG_BD | RX_BD_FLAGS_SOP;
2883 bnxt_init_rxbd_pages(ring, type);
2885 prod = rxr->rx_agg_prod;
2886 for (i = 0; i < bp->rx_agg_ring_size; i++) {
2887 if (bnxt_alloc_rx_page(bp, rxr, prod, GFP_KERNEL) != 0) {
2888 netdev_warn(dev, "init'ed rx ring %d with %d/%d pages only\n",
2889 ring_nr, i, bp->rx_ring_size);
2892 prod = NEXT_RX_AGG(prod);
2894 rxr->rx_agg_prod = prod;
2896 if (bp->flags & BNXT_FLAG_TPA) {
2901 for (i = 0; i < MAX_TPA; i++) {
2902 data = __bnxt_alloc_rx_data(bp, &mapping,
2907 rxr->rx_tpa[i].data = data;
2908 rxr->rx_tpa[i].data_ptr = data + bp->rx_offset;
2909 rxr->rx_tpa[i].mapping = mapping;
2912 netdev_err(bp->dev, "No resource allocated for LRO/GRO\n");
2920 static void bnxt_init_cp_rings(struct bnxt *bp)
2924 for (i = 0; i < bp->cp_nr_rings; i++) {
2925 struct bnxt_cp_ring_info *cpr = &bp->bnapi[i]->cp_ring;
2926 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct;
2928 ring->fw_ring_id = INVALID_HW_RING_ID;
2929 cpr->rx_ring_coal.coal_ticks = bp->rx_coal.coal_ticks;
2930 cpr->rx_ring_coal.coal_bufs = bp->rx_coal.coal_bufs;
2931 for (j = 0; j < 2; j++) {
2932 struct bnxt_cp_ring_info *cpr2 = cpr->cp_ring_arr[j];
2937 ring = &cpr2->cp_ring_struct;
2938 ring->fw_ring_id = INVALID_HW_RING_ID;
2939 cpr2->rx_ring_coal.coal_ticks = bp->rx_coal.coal_ticks;
2940 cpr2->rx_ring_coal.coal_bufs = bp->rx_coal.coal_bufs;
2945 static int bnxt_init_rx_rings(struct bnxt *bp)
2949 if (BNXT_RX_PAGE_MODE(bp)) {
2950 bp->rx_offset = NET_IP_ALIGN + XDP_PACKET_HEADROOM;
2951 bp->rx_dma_offset = XDP_PACKET_HEADROOM;
2953 bp->rx_offset = BNXT_RX_OFFSET;
2954 bp->rx_dma_offset = BNXT_RX_DMA_OFFSET;
2957 for (i = 0; i < bp->rx_nr_rings; i++) {
2958 rc = bnxt_init_one_rx_ring(bp, i);
2966 static int bnxt_init_tx_rings(struct bnxt *bp)
2970 bp->tx_wake_thresh = max_t(int, bp->tx_ring_size / 2,
2973 for (i = 0; i < bp->tx_nr_rings; i++) {
2974 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
2975 struct bnxt_ring_struct *ring = &txr->tx_ring_struct;
2977 ring->fw_ring_id = INVALID_HW_RING_ID;
2983 static void bnxt_free_ring_grps(struct bnxt *bp)
2985 kfree(bp->grp_info);
2986 bp->grp_info = NULL;
2989 static int bnxt_init_ring_grps(struct bnxt *bp, bool irq_re_init)
2994 bp->grp_info = kcalloc(bp->cp_nr_rings,
2995 sizeof(struct bnxt_ring_grp_info),
3000 for (i = 0; i < bp->cp_nr_rings; i++) {
3002 bp->grp_info[i].fw_stats_ctx = INVALID_HW_RING_ID;
3003 bp->grp_info[i].fw_grp_id = INVALID_HW_RING_ID;
3004 bp->grp_info[i].rx_fw_ring_id = INVALID_HW_RING_ID;
3005 bp->grp_info[i].agg_fw_ring_id = INVALID_HW_RING_ID;
3006 bp->grp_info[i].cp_fw_ring_id = INVALID_HW_RING_ID;
3011 static void bnxt_free_vnics(struct bnxt *bp)
3013 kfree(bp->vnic_info);
3014 bp->vnic_info = NULL;
3018 static int bnxt_alloc_vnics(struct bnxt *bp)
3022 #ifdef CONFIG_RFS_ACCEL
3023 if (bp->flags & BNXT_FLAG_RFS)
3024 num_vnics += bp->rx_nr_rings;
3027 if (BNXT_CHIP_TYPE_NITRO_A0(bp))
3030 bp->vnic_info = kcalloc(num_vnics, sizeof(struct bnxt_vnic_info),
3035 bp->nr_vnics = num_vnics;
3039 static void bnxt_init_vnics(struct bnxt *bp)
3043 for (i = 0; i < bp->nr_vnics; i++) {
3044 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3047 vnic->fw_vnic_id = INVALID_HW_RING_ID;
3048 for (j = 0; j < BNXT_MAX_CTX_PER_VNIC; j++)
3049 vnic->fw_rss_cos_lb_ctx[j] = INVALID_HW_RING_ID;
3051 vnic->fw_l2_ctx_id = INVALID_HW_RING_ID;
3053 if (bp->vnic_info[i].rss_hash_key) {
3055 prandom_bytes(vnic->rss_hash_key,
3058 memcpy(vnic->rss_hash_key,
3059 bp->vnic_info[0].rss_hash_key,
3065 static int bnxt_calc_nr_ring_pages(u32 ring_size, int desc_per_pg)
3069 pages = ring_size / desc_per_pg;
3076 while (pages & (pages - 1))
3082 void bnxt_set_tpa_flags(struct bnxt *bp)
3084 bp->flags &= ~BNXT_FLAG_TPA;
3085 if (bp->flags & BNXT_FLAG_NO_AGG_RINGS)
3087 if (bp->dev->features & NETIF_F_LRO)
3088 bp->flags |= BNXT_FLAG_LRO;
3089 else if (bp->dev->features & NETIF_F_GRO_HW)
3090 bp->flags |= BNXT_FLAG_GRO;
3093 /* bp->rx_ring_size, bp->tx_ring_size, dev->mtu, BNXT_FLAG_{G|L}RO flags must
3096 void bnxt_set_ring_params(struct bnxt *bp)
3098 u32 ring_size, rx_size, rx_space;
3099 u32 agg_factor = 0, agg_ring_size = 0;
3101 /* 8 for CRC and VLAN */
3102 rx_size = SKB_DATA_ALIGN(bp->dev->mtu + ETH_HLEN + NET_IP_ALIGN + 8);
3104 rx_space = rx_size + NET_SKB_PAD +
3105 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
3107 bp->rx_copy_thresh = BNXT_RX_COPY_THRESH;
3108 ring_size = bp->rx_ring_size;
3109 bp->rx_agg_ring_size = 0;
3110 bp->rx_agg_nr_pages = 0;
3112 if (bp->flags & BNXT_FLAG_TPA)
3113 agg_factor = min_t(u32, 4, 65536 / BNXT_RX_PAGE_SIZE);
3115 bp->flags &= ~BNXT_FLAG_JUMBO;
3116 if (rx_space > PAGE_SIZE && !(bp->flags & BNXT_FLAG_NO_AGG_RINGS)) {
3119 bp->flags |= BNXT_FLAG_JUMBO;
3120 jumbo_factor = PAGE_ALIGN(bp->dev->mtu - 40) >> PAGE_SHIFT;
3121 if (jumbo_factor > agg_factor)
3122 agg_factor = jumbo_factor;
3124 agg_ring_size = ring_size * agg_factor;
3126 if (agg_ring_size) {
3127 bp->rx_agg_nr_pages = bnxt_calc_nr_ring_pages(agg_ring_size,
3129 if (bp->rx_agg_nr_pages > MAX_RX_AGG_PAGES) {
3130 u32 tmp = agg_ring_size;
3132 bp->rx_agg_nr_pages = MAX_RX_AGG_PAGES;
3133 agg_ring_size = MAX_RX_AGG_PAGES * RX_DESC_CNT - 1;
3134 netdev_warn(bp->dev, "rx agg ring size %d reduced to %d.\n",
3135 tmp, agg_ring_size);
3137 bp->rx_agg_ring_size = agg_ring_size;
3138 bp->rx_agg_ring_mask = (bp->rx_agg_nr_pages * RX_DESC_CNT) - 1;
3139 rx_size = SKB_DATA_ALIGN(BNXT_RX_COPY_THRESH + NET_IP_ALIGN);
3140 rx_space = rx_size + NET_SKB_PAD +
3141 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
3144 bp->rx_buf_use_size = rx_size;
3145 bp->rx_buf_size = rx_space;
3147 bp->rx_nr_pages = bnxt_calc_nr_ring_pages(ring_size, RX_DESC_CNT);
3148 bp->rx_ring_mask = (bp->rx_nr_pages * RX_DESC_CNT) - 1;
3150 ring_size = bp->tx_ring_size;
3151 bp->tx_nr_pages = bnxt_calc_nr_ring_pages(ring_size, TX_DESC_CNT);
3152 bp->tx_ring_mask = (bp->tx_nr_pages * TX_DESC_CNT) - 1;
3154 ring_size = bp->rx_ring_size * (2 + agg_factor) + bp->tx_ring_size;
3155 bp->cp_ring_size = ring_size;
3157 bp->cp_nr_pages = bnxt_calc_nr_ring_pages(ring_size, CP_DESC_CNT);
3158 if (bp->cp_nr_pages > MAX_CP_PAGES) {
3159 bp->cp_nr_pages = MAX_CP_PAGES;
3160 bp->cp_ring_size = MAX_CP_PAGES * CP_DESC_CNT - 1;
3161 netdev_warn(bp->dev, "completion ring size %d reduced to %d.\n",
3162 ring_size, bp->cp_ring_size);
3164 bp->cp_bit = bp->cp_nr_pages * CP_DESC_CNT;
3165 bp->cp_ring_mask = bp->cp_bit - 1;
3168 /* Changing allocation mode of RX rings.
3169 * TODO: Update when extending xdp_rxq_info to support allocation modes.
3171 int bnxt_set_rx_skb_mode(struct bnxt *bp, bool page_mode)
3174 if (bp->dev->mtu > BNXT_MAX_PAGE_MODE_MTU)
3177 min_t(u16, bp->max_mtu, BNXT_MAX_PAGE_MODE_MTU);
3178 bp->flags &= ~BNXT_FLAG_AGG_RINGS;
3179 bp->flags |= BNXT_FLAG_NO_AGG_RINGS | BNXT_FLAG_RX_PAGE_MODE;
3180 bp->rx_dir = DMA_BIDIRECTIONAL;
3181 bp->rx_skb_func = bnxt_rx_page_skb;
3182 /* Disable LRO or GRO_HW */
3183 netdev_update_features(bp->dev);
3185 bp->dev->max_mtu = bp->max_mtu;
3186 bp->flags &= ~BNXT_FLAG_RX_PAGE_MODE;
3187 bp->rx_dir = DMA_FROM_DEVICE;
3188 bp->rx_skb_func = bnxt_rx_skb;
3193 static void bnxt_free_vnic_attributes(struct bnxt *bp)
3196 struct bnxt_vnic_info *vnic;
3197 struct pci_dev *pdev = bp->pdev;
3202 for (i = 0; i < bp->nr_vnics; i++) {
3203 vnic = &bp->vnic_info[i];
3205 kfree(vnic->fw_grp_ids);
3206 vnic->fw_grp_ids = NULL;
3208 kfree(vnic->uc_list);
3209 vnic->uc_list = NULL;
3211 if (vnic->mc_list) {
3212 dma_free_coherent(&pdev->dev, vnic->mc_list_size,
3213 vnic->mc_list, vnic->mc_list_mapping);
3214 vnic->mc_list = NULL;
3217 if (vnic->rss_table) {
3218 dma_free_coherent(&pdev->dev, PAGE_SIZE,
3220 vnic->rss_table_dma_addr);
3221 vnic->rss_table = NULL;
3224 vnic->rss_hash_key = NULL;
3229 static int bnxt_alloc_vnic_attributes(struct bnxt *bp)
3231 int i, rc = 0, size;
3232 struct bnxt_vnic_info *vnic;
3233 struct pci_dev *pdev = bp->pdev;
3236 for (i = 0; i < bp->nr_vnics; i++) {
3237 vnic = &bp->vnic_info[i];
3239 if (vnic->flags & BNXT_VNIC_UCAST_FLAG) {
3240 int mem_size = (BNXT_MAX_UC_ADDRS - 1) * ETH_ALEN;
3243 vnic->uc_list = kmalloc(mem_size, GFP_KERNEL);
3244 if (!vnic->uc_list) {
3251 if (vnic->flags & BNXT_VNIC_MCAST_FLAG) {
3252 vnic->mc_list_size = BNXT_MAX_MC_ADDRS * ETH_ALEN;
3254 dma_alloc_coherent(&pdev->dev,
3256 &vnic->mc_list_mapping,
3258 if (!vnic->mc_list) {
3264 if (bp->flags & BNXT_FLAG_CHIP_P5)
3265 goto vnic_skip_grps;
3267 if (vnic->flags & BNXT_VNIC_RSS_FLAG)
3268 max_rings = bp->rx_nr_rings;
3272 vnic->fw_grp_ids = kcalloc(max_rings, sizeof(u16), GFP_KERNEL);
3273 if (!vnic->fw_grp_ids) {
3278 if ((bp->flags & BNXT_FLAG_NEW_RSS_CAP) &&
3279 !(vnic->flags & BNXT_VNIC_RSS_FLAG))
3282 /* Allocate rss table and hash key */
3283 vnic->rss_table = dma_alloc_coherent(&pdev->dev, PAGE_SIZE,
3284 &vnic->rss_table_dma_addr,
3286 if (!vnic->rss_table) {
3291 size = L1_CACHE_ALIGN(HW_HASH_INDEX_SIZE * sizeof(u16));
3293 vnic->rss_hash_key = ((void *)vnic->rss_table) + size;
3294 vnic->rss_hash_key_dma_addr = vnic->rss_table_dma_addr + size;
3302 static void bnxt_free_hwrm_resources(struct bnxt *bp)
3304 struct pci_dev *pdev = bp->pdev;
3306 if (bp->hwrm_cmd_resp_addr) {
3307 dma_free_coherent(&pdev->dev, PAGE_SIZE, bp->hwrm_cmd_resp_addr,
3308 bp->hwrm_cmd_resp_dma_addr);
3309 bp->hwrm_cmd_resp_addr = NULL;
3312 if (bp->hwrm_cmd_kong_resp_addr) {
3313 dma_free_coherent(&pdev->dev, PAGE_SIZE,
3314 bp->hwrm_cmd_kong_resp_addr,
3315 bp->hwrm_cmd_kong_resp_dma_addr);
3316 bp->hwrm_cmd_kong_resp_addr = NULL;
3320 static int bnxt_alloc_kong_hwrm_resources(struct bnxt *bp)
3322 struct pci_dev *pdev = bp->pdev;
3324 bp->hwrm_cmd_kong_resp_addr =
3325 dma_alloc_coherent(&pdev->dev, PAGE_SIZE,
3326 &bp->hwrm_cmd_kong_resp_dma_addr,
3328 if (!bp->hwrm_cmd_kong_resp_addr)
3334 static int bnxt_alloc_hwrm_resources(struct bnxt *bp)
3336 struct pci_dev *pdev = bp->pdev;
3338 bp->hwrm_cmd_resp_addr = dma_alloc_coherent(&pdev->dev, PAGE_SIZE,
3339 &bp->hwrm_cmd_resp_dma_addr,
3341 if (!bp->hwrm_cmd_resp_addr)
3347 static void bnxt_free_hwrm_short_cmd_req(struct bnxt *bp)
3349 if (bp->hwrm_short_cmd_req_addr) {
3350 struct pci_dev *pdev = bp->pdev;
3352 dma_free_coherent(&pdev->dev, bp->hwrm_max_ext_req_len,
3353 bp->hwrm_short_cmd_req_addr,
3354 bp->hwrm_short_cmd_req_dma_addr);
3355 bp->hwrm_short_cmd_req_addr = NULL;
3359 static int bnxt_alloc_hwrm_short_cmd_req(struct bnxt *bp)
3361 struct pci_dev *pdev = bp->pdev;
3363 bp->hwrm_short_cmd_req_addr =
3364 dma_alloc_coherent(&pdev->dev, bp->hwrm_max_ext_req_len,
3365 &bp->hwrm_short_cmd_req_dma_addr,
3367 if (!bp->hwrm_short_cmd_req_addr)
3373 static void bnxt_free_port_stats(struct bnxt *bp)
3375 struct pci_dev *pdev = bp->pdev;
3377 bp->flags &= ~BNXT_FLAG_PORT_STATS;
3378 bp->flags &= ~BNXT_FLAG_PORT_STATS_EXT;
3380 if (bp->hw_rx_port_stats) {
3381 dma_free_coherent(&pdev->dev, bp->hw_port_stats_size,
3382 bp->hw_rx_port_stats,
3383 bp->hw_rx_port_stats_map);
3384 bp->hw_rx_port_stats = NULL;
3387 if (bp->hw_tx_port_stats_ext) {
3388 dma_free_coherent(&pdev->dev, sizeof(struct tx_port_stats_ext),
3389 bp->hw_tx_port_stats_ext,
3390 bp->hw_tx_port_stats_ext_map);
3391 bp->hw_tx_port_stats_ext = NULL;
3394 if (bp->hw_rx_port_stats_ext) {
3395 dma_free_coherent(&pdev->dev, sizeof(struct rx_port_stats_ext),
3396 bp->hw_rx_port_stats_ext,
3397 bp->hw_rx_port_stats_ext_map);
3398 bp->hw_rx_port_stats_ext = NULL;
3401 if (bp->hw_pcie_stats) {
3402 dma_free_coherent(&pdev->dev, sizeof(struct pcie_ctx_hw_stats),
3403 bp->hw_pcie_stats, bp->hw_pcie_stats_map);
3404 bp->hw_pcie_stats = NULL;
3408 static void bnxt_free_ring_stats(struct bnxt *bp)
3410 struct pci_dev *pdev = bp->pdev;
3416 size = sizeof(struct ctx_hw_stats);
3418 for (i = 0; i < bp->cp_nr_rings; i++) {
3419 struct bnxt_napi *bnapi = bp->bnapi[i];
3420 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
3422 if (cpr->hw_stats) {
3423 dma_free_coherent(&pdev->dev, size, cpr->hw_stats,
3425 cpr->hw_stats = NULL;
3430 static int bnxt_alloc_stats(struct bnxt *bp)
3433 struct pci_dev *pdev = bp->pdev;
3435 size = sizeof(struct ctx_hw_stats);
3437 for (i = 0; i < bp->cp_nr_rings; i++) {
3438 struct bnxt_napi *bnapi = bp->bnapi[i];
3439 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
3441 cpr->hw_stats = dma_alloc_coherent(&pdev->dev, size,
3447 cpr->hw_stats_ctx_id = INVALID_STATS_CTX_ID;
3450 if (BNXT_VF(bp) || bp->chip_num == CHIP_NUM_58700)
3453 if (bp->hw_rx_port_stats)
3454 goto alloc_ext_stats;
3456 bp->hw_port_stats_size = sizeof(struct rx_port_stats) +
3457 sizeof(struct tx_port_stats) + 1024;
3459 bp->hw_rx_port_stats =
3460 dma_alloc_coherent(&pdev->dev, bp->hw_port_stats_size,
3461 &bp->hw_rx_port_stats_map,
3463 if (!bp->hw_rx_port_stats)
3466 bp->hw_tx_port_stats = (void *)(bp->hw_rx_port_stats + 1) + 512;
3467 bp->hw_tx_port_stats_map = bp->hw_rx_port_stats_map +
3468 sizeof(struct rx_port_stats) + 512;
3469 bp->flags |= BNXT_FLAG_PORT_STATS;
3472 /* Display extended statistics only if FW supports it */
3473 if (bp->hwrm_spec_code < 0x10804 || bp->hwrm_spec_code == 0x10900)
3474 if (!(bp->fw_cap & BNXT_FW_CAP_EXT_STATS_SUPPORTED))
3477 if (bp->hw_rx_port_stats_ext)
3478 goto alloc_tx_ext_stats;
3480 bp->hw_rx_port_stats_ext =
3481 dma_alloc_coherent(&pdev->dev, sizeof(struct rx_port_stats_ext),
3482 &bp->hw_rx_port_stats_ext_map, GFP_KERNEL);
3483 if (!bp->hw_rx_port_stats_ext)
3487 if (bp->hw_tx_port_stats_ext)
3488 goto alloc_pcie_stats;
3490 if (bp->hwrm_spec_code >= 0x10902 ||
3491 (bp->fw_cap & BNXT_FW_CAP_EXT_STATS_SUPPORTED)) {
3492 bp->hw_tx_port_stats_ext =
3493 dma_alloc_coherent(&pdev->dev,
3494 sizeof(struct tx_port_stats_ext),
3495 &bp->hw_tx_port_stats_ext_map,
3498 bp->flags |= BNXT_FLAG_PORT_STATS_EXT;
3501 if (bp->hw_pcie_stats ||
3502 !(bp->fw_cap & BNXT_FW_CAP_PCIE_STATS_SUPPORTED))
3506 dma_alloc_coherent(&pdev->dev, sizeof(struct pcie_ctx_hw_stats),
3507 &bp->hw_pcie_stats_map, GFP_KERNEL);
3508 if (!bp->hw_pcie_stats)
3511 bp->flags |= BNXT_FLAG_PCIE_STATS;
3515 static void bnxt_clear_ring_indices(struct bnxt *bp)
3522 for (i = 0; i < bp->cp_nr_rings; i++) {
3523 struct bnxt_napi *bnapi = bp->bnapi[i];
3524 struct bnxt_cp_ring_info *cpr;
3525 struct bnxt_rx_ring_info *rxr;
3526 struct bnxt_tx_ring_info *txr;
3531 cpr = &bnapi->cp_ring;
3532 cpr->cp_raw_cons = 0;
3534 txr = bnapi->tx_ring;
3540 rxr = bnapi->rx_ring;
3543 rxr->rx_agg_prod = 0;
3544 rxr->rx_sw_agg_prod = 0;
3545 rxr->rx_next_cons = 0;
3550 static void bnxt_free_ntp_fltrs(struct bnxt *bp, bool irq_reinit)
3552 #ifdef CONFIG_RFS_ACCEL
3555 /* Under rtnl_lock and all our NAPIs have been disabled. It's
3556 * safe to delete the hash table.
3558 for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) {
3559 struct hlist_head *head;
3560 struct hlist_node *tmp;
3561 struct bnxt_ntuple_filter *fltr;
3563 head = &bp->ntp_fltr_hash_tbl[i];
3564 hlist_for_each_entry_safe(fltr, tmp, head, hash) {
3565 hlist_del(&fltr->hash);
3570 kfree(bp->ntp_fltr_bmap);
3571 bp->ntp_fltr_bmap = NULL;
3573 bp->ntp_fltr_count = 0;
3577 static int bnxt_alloc_ntp_fltrs(struct bnxt *bp)
3579 #ifdef CONFIG_RFS_ACCEL
3582 if (!(bp->flags & BNXT_FLAG_RFS))
3585 for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++)
3586 INIT_HLIST_HEAD(&bp->ntp_fltr_hash_tbl[i]);
3588 bp->ntp_fltr_count = 0;
3589 bp->ntp_fltr_bmap = kcalloc(BITS_TO_LONGS(BNXT_NTP_FLTR_MAX_FLTR),
3593 if (!bp->ntp_fltr_bmap)
3602 static void bnxt_free_mem(struct bnxt *bp, bool irq_re_init)
3604 bnxt_free_vnic_attributes(bp);
3605 bnxt_free_tx_rings(bp);
3606 bnxt_free_rx_rings(bp);
3607 bnxt_free_cp_rings(bp);
3608 bnxt_free_ntp_fltrs(bp, irq_re_init);
3610 bnxt_free_ring_stats(bp);
3611 bnxt_free_ring_grps(bp);
3612 bnxt_free_vnics(bp);
3613 kfree(bp->tx_ring_map);
3614 bp->tx_ring_map = NULL;
3622 bnxt_clear_ring_indices(bp);
3626 static int bnxt_alloc_mem(struct bnxt *bp, bool irq_re_init)
3628 int i, j, rc, size, arr_size;
3632 /* Allocate bnapi mem pointer array and mem block for
3635 arr_size = L1_CACHE_ALIGN(sizeof(struct bnxt_napi *) *
3637 size = L1_CACHE_ALIGN(sizeof(struct bnxt_napi));
3638 bnapi = kzalloc(arr_size + size * bp->cp_nr_rings, GFP_KERNEL);
3644 for (i = 0; i < bp->cp_nr_rings; i++, bnapi += size) {
3645 bp->bnapi[i] = bnapi;
3646 bp->bnapi[i]->index = i;
3647 bp->bnapi[i]->bp = bp;
3648 if (bp->flags & BNXT_FLAG_CHIP_P5) {
3649 struct bnxt_cp_ring_info *cpr =
3650 &bp->bnapi[i]->cp_ring;
3652 cpr->cp_ring_struct.ring_mem.flags =
3653 BNXT_RMEM_RING_PTE_FLAG;
3657 bp->rx_ring = kcalloc(bp->rx_nr_rings,
3658 sizeof(struct bnxt_rx_ring_info),
3663 for (i = 0; i < bp->rx_nr_rings; i++) {
3664 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
3666 if (bp->flags & BNXT_FLAG_CHIP_P5) {
3667 rxr->rx_ring_struct.ring_mem.flags =
3668 BNXT_RMEM_RING_PTE_FLAG;
3669 rxr->rx_agg_ring_struct.ring_mem.flags =
3670 BNXT_RMEM_RING_PTE_FLAG;
3672 rxr->bnapi = bp->bnapi[i];
3673 bp->bnapi[i]->rx_ring = &bp->rx_ring[i];
3676 bp->tx_ring = kcalloc(bp->tx_nr_rings,
3677 sizeof(struct bnxt_tx_ring_info),
3682 bp->tx_ring_map = kcalloc(bp->tx_nr_rings, sizeof(u16),
3685 if (!bp->tx_ring_map)
3688 if (bp->flags & BNXT_FLAG_SHARED_RINGS)
3691 j = bp->rx_nr_rings;
3693 for (i = 0; i < bp->tx_nr_rings; i++, j++) {
3694 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
3696 if (bp->flags & BNXT_FLAG_CHIP_P5)
3697 txr->tx_ring_struct.ring_mem.flags =
3698 BNXT_RMEM_RING_PTE_FLAG;
3699 txr->bnapi = bp->bnapi[j];
3700 bp->bnapi[j]->tx_ring = txr;
3701 bp->tx_ring_map[i] = bp->tx_nr_rings_xdp + i;
3702 if (i >= bp->tx_nr_rings_xdp) {
3703 txr->txq_index = i - bp->tx_nr_rings_xdp;
3704 bp->bnapi[j]->tx_int = bnxt_tx_int;
3706 bp->bnapi[j]->flags |= BNXT_NAPI_FLAG_XDP;
3707 bp->bnapi[j]->tx_int = bnxt_tx_int_xdp;
3711 rc = bnxt_alloc_stats(bp);
3715 rc = bnxt_alloc_ntp_fltrs(bp);
3719 rc = bnxt_alloc_vnics(bp);
3724 bnxt_init_ring_struct(bp);
3726 rc = bnxt_alloc_rx_rings(bp);
3730 rc = bnxt_alloc_tx_rings(bp);
3734 rc = bnxt_alloc_cp_rings(bp);
3738 bp->vnic_info[0].flags |= BNXT_VNIC_RSS_FLAG | BNXT_VNIC_MCAST_FLAG |
3739 BNXT_VNIC_UCAST_FLAG;
3740 rc = bnxt_alloc_vnic_attributes(bp);
3746 bnxt_free_mem(bp, true);
3750 static void bnxt_disable_int(struct bnxt *bp)
3757 for (i = 0; i < bp->cp_nr_rings; i++) {
3758 struct bnxt_napi *bnapi = bp->bnapi[i];
3759 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
3760 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct;
3762 if (ring->fw_ring_id != INVALID_HW_RING_ID)
3763 bnxt_db_nq(bp, &cpr->cp_db, cpr->cp_raw_cons);
3767 static int bnxt_cp_num_to_irq_num(struct bnxt *bp, int n)
3769 struct bnxt_napi *bnapi = bp->bnapi[n];
3770 struct bnxt_cp_ring_info *cpr;
3772 cpr = &bnapi->cp_ring;
3773 return cpr->cp_ring_struct.map_idx;
3776 static void bnxt_disable_int_sync(struct bnxt *bp)
3780 atomic_inc(&bp->intr_sem);
3782 bnxt_disable_int(bp);
3783 for (i = 0; i < bp->cp_nr_rings; i++) {
3784 int map_idx = bnxt_cp_num_to_irq_num(bp, i);
3786 synchronize_irq(bp->irq_tbl[map_idx].vector);
3790 static void bnxt_enable_int(struct bnxt *bp)
3794 atomic_set(&bp->intr_sem, 0);
3795 for (i = 0; i < bp->cp_nr_rings; i++) {
3796 struct bnxt_napi *bnapi = bp->bnapi[i];
3797 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
3799 bnxt_db_nq_arm(bp, &cpr->cp_db, cpr->cp_raw_cons);
3803 void bnxt_hwrm_cmd_hdr_init(struct bnxt *bp, void *request, u16 req_type,
3804 u16 cmpl_ring, u16 target_id)
3806 struct input *req = request;
3808 req->req_type = cpu_to_le16(req_type);
3809 req->cmpl_ring = cpu_to_le16(cmpl_ring);
3810 req->target_id = cpu_to_le16(target_id);
3811 if (bnxt_kong_hwrm_message(bp, req))
3812 req->resp_addr = cpu_to_le64(bp->hwrm_cmd_kong_resp_dma_addr);
3814 req->resp_addr = cpu_to_le64(bp->hwrm_cmd_resp_dma_addr);
3817 static int bnxt_hwrm_do_send_msg(struct bnxt *bp, void *msg, u32 msg_len,
3818 int timeout, bool silent)
3820 int i, intr_process, rc, tmo_count;
3821 struct input *req = msg;
3825 u16 cp_ring_id, len = 0;
3826 struct hwrm_err_output *resp = bp->hwrm_cmd_resp_addr;
3827 u16 max_req_len = BNXT_HWRM_MAX_REQ_LEN;
3828 struct hwrm_short_input short_input = {0};
3829 u32 doorbell_offset = BNXT_GRCPF_REG_CHIMP_COMM_TRIGGER;
3830 u8 *resp_addr = (u8 *)bp->hwrm_cmd_resp_addr;
3831 u32 bar_offset = BNXT_GRCPF_REG_CHIMP_COMM;
3832 u16 dst = BNXT_HWRM_CHNL_CHIMP;
3834 if (msg_len > BNXT_HWRM_MAX_REQ_LEN) {
3835 if (msg_len > bp->hwrm_max_ext_req_len ||
3836 !bp->hwrm_short_cmd_req_addr)
3840 if (bnxt_hwrm_kong_chnl(bp, req)) {
3841 dst = BNXT_HWRM_CHNL_KONG;
3842 bar_offset = BNXT_GRCPF_REG_KONG_COMM;
3843 doorbell_offset = BNXT_GRCPF_REG_KONG_COMM_TRIGGER;
3844 resp = bp->hwrm_cmd_kong_resp_addr;
3845 resp_addr = (u8 *)bp->hwrm_cmd_kong_resp_addr;
3848 memset(resp, 0, PAGE_SIZE);
3849 cp_ring_id = le16_to_cpu(req->cmpl_ring);
3850 intr_process = (cp_ring_id == INVALID_HW_RING_ID) ? 0 : 1;
3852 req->seq_id = cpu_to_le16(bnxt_get_hwrm_seq_id(bp, dst));
3853 /* currently supports only one outstanding message */
3855 bp->hwrm_intr_seq_id = le16_to_cpu(req->seq_id);
3857 if ((bp->fw_cap & BNXT_FW_CAP_SHORT_CMD) ||
3858 msg_len > BNXT_HWRM_MAX_REQ_LEN) {
3859 void *short_cmd_req = bp->hwrm_short_cmd_req_addr;
3862 /* Set boundary for maximum extended request length for short
3863 * cmd format. If passed up from device use the max supported
3864 * internal req length.
3866 max_msg_len = bp->hwrm_max_ext_req_len;
3868 memcpy(short_cmd_req, req, msg_len);
3869 if (msg_len < max_msg_len)
3870 memset(short_cmd_req + msg_len, 0,
3871 max_msg_len - msg_len);
3873 short_input.req_type = req->req_type;
3874 short_input.signature =
3875 cpu_to_le16(SHORT_REQ_SIGNATURE_SHORT_CMD);
3876 short_input.size = cpu_to_le16(msg_len);
3877 short_input.req_addr =
3878 cpu_to_le64(bp->hwrm_short_cmd_req_dma_addr);
3880 data = (u32 *)&short_input;
3881 msg_len = sizeof(short_input);
3883 /* Sync memory write before updating doorbell */
3886 max_req_len = BNXT_HWRM_SHORT_REQ_LEN;
3889 /* Write request msg to hwrm channel */
3890 __iowrite32_copy(bp->bar0 + bar_offset, data, msg_len / 4);
3892 for (i = msg_len; i < max_req_len; i += 4)
3893 writel(0, bp->bar0 + bar_offset + i);
3895 /* Ring channel doorbell */
3896 writel(1, bp->bar0 + doorbell_offset);
3899 timeout = DFLT_HWRM_CMD_TIMEOUT;
3900 /* convert timeout to usec */
3904 /* Short timeout for the first few iterations:
3905 * number of loops = number of loops for short timeout +
3906 * number of loops for standard timeout.
3908 tmo_count = HWRM_SHORT_TIMEOUT_COUNTER;
3909 timeout = timeout - HWRM_SHORT_MIN_TIMEOUT * HWRM_SHORT_TIMEOUT_COUNTER;
3910 tmo_count += DIV_ROUND_UP(timeout, HWRM_MIN_TIMEOUT);
3911 resp_len = (__le32 *)(resp_addr + HWRM_RESP_LEN_OFFSET);
3914 u16 seq_id = bp->hwrm_intr_seq_id;
3916 /* Wait until hwrm response cmpl interrupt is processed */
3917 while (bp->hwrm_intr_seq_id != (u16)~seq_id &&
3919 /* on first few passes, just barely sleep */
3920 if (i < HWRM_SHORT_TIMEOUT_COUNTER)
3921 usleep_range(HWRM_SHORT_MIN_TIMEOUT,
3922 HWRM_SHORT_MAX_TIMEOUT);
3924 usleep_range(HWRM_MIN_TIMEOUT,
3928 if (bp->hwrm_intr_seq_id != (u16)~seq_id) {
3929 netdev_err(bp->dev, "Resp cmpl intr err msg: 0x%x\n",
3930 le16_to_cpu(req->req_type));
3933 len = (le32_to_cpu(*resp_len) & HWRM_RESP_LEN_MASK) >>
3935 valid = resp_addr + len - 1;
3939 /* Check if response len is updated */
3940 for (i = 0; i < tmo_count; i++) {
3941 len = (le32_to_cpu(*resp_len) & HWRM_RESP_LEN_MASK) >>
3945 /* on first few passes, just barely sleep */
3946 if (i < HWRM_SHORT_TIMEOUT_COUNTER)
3947 usleep_range(HWRM_SHORT_MIN_TIMEOUT,
3948 HWRM_SHORT_MAX_TIMEOUT);
3950 usleep_range(HWRM_MIN_TIMEOUT,
3954 if (i >= tmo_count) {
3955 netdev_err(bp->dev, "Error (timeout: %d) msg {0x%x 0x%x} len:%d\n",
3956 HWRM_TOTAL_TIMEOUT(i),
3957 le16_to_cpu(req->req_type),
3958 le16_to_cpu(req->seq_id), len);
3962 /* Last byte of resp contains valid bit */
3963 valid = resp_addr + len - 1;
3964 for (j = 0; j < HWRM_VALID_BIT_DELAY_USEC; j++) {
3965 /* make sure we read from updated DMA memory */
3972 if (j >= HWRM_VALID_BIT_DELAY_USEC) {
3973 netdev_err(bp->dev, "Error (timeout: %d) msg {0x%x 0x%x} len:%d v:%d\n",
3974 HWRM_TOTAL_TIMEOUT(i),
3975 le16_to_cpu(req->req_type),
3976 le16_to_cpu(req->seq_id), len, *valid);
3981 /* Zero valid bit for compatibility. Valid bit in an older spec
3982 * may become a new field in a newer spec. We must make sure that
3983 * a new field not implemented by old spec will read zero.
3986 rc = le16_to_cpu(resp->error_code);
3988 netdev_err(bp->dev, "hwrm req_type 0x%x seq id 0x%x error 0x%x\n",
3989 le16_to_cpu(resp->req_type),
3990 le16_to_cpu(resp->seq_id), rc);
3994 int _hwrm_send_message(struct bnxt *bp, void *msg, u32 msg_len, int timeout)
3996 return bnxt_hwrm_do_send_msg(bp, msg, msg_len, timeout, false);
3999 int _hwrm_send_message_silent(struct bnxt *bp, void *msg, u32 msg_len,
4002 return bnxt_hwrm_do_send_msg(bp, msg, msg_len, timeout, true);
4005 int hwrm_send_message(struct bnxt *bp, void *msg, u32 msg_len, int timeout)
4009 mutex_lock(&bp->hwrm_cmd_lock);
4010 rc = _hwrm_send_message(bp, msg, msg_len, timeout);
4011 mutex_unlock(&bp->hwrm_cmd_lock);
4015 int hwrm_send_message_silent(struct bnxt *bp, void *msg, u32 msg_len,
4020 mutex_lock(&bp->hwrm_cmd_lock);
4021 rc = bnxt_hwrm_do_send_msg(bp, msg, msg_len, timeout, true);
4022 mutex_unlock(&bp->hwrm_cmd_lock);
4026 int bnxt_hwrm_func_rgtr_async_events(struct bnxt *bp, unsigned long *bmap,
4029 struct hwrm_func_drv_rgtr_input req = {0};
4030 DECLARE_BITMAP(async_events_bmap, 256);
4031 u32 *events = (u32 *)async_events_bmap;
4034 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_RGTR, -1, -1);
4037 cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_ASYNC_EVENT_FWD);
4039 memset(async_events_bmap, 0, sizeof(async_events_bmap));
4040 for (i = 0; i < ARRAY_SIZE(bnxt_async_events_arr); i++)
4041 __set_bit(bnxt_async_events_arr[i], async_events_bmap);
4043 if (bmap && bmap_size) {
4044 for (i = 0; i < bmap_size; i++) {
4045 if (test_bit(i, bmap))
4046 __set_bit(i, async_events_bmap);
4050 for (i = 0; i < 8; i++)
4051 req.async_event_fwd[i] |= cpu_to_le32(events[i]);
4053 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4056 static int bnxt_hwrm_func_drv_rgtr(struct bnxt *bp)
4058 struct hwrm_func_drv_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
4059 struct hwrm_func_drv_rgtr_input req = {0};
4062 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_RGTR, -1, -1);
4065 cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_OS_TYPE |
4066 FUNC_DRV_RGTR_REQ_ENABLES_VER);
4068 req.os_type = cpu_to_le16(FUNC_DRV_RGTR_REQ_OS_TYPE_LINUX);
4069 req.flags = cpu_to_le32(FUNC_DRV_RGTR_REQ_FLAGS_16BIT_VER_MODE);
4070 req.ver_maj_8b = DRV_VER_MAJ;
4071 req.ver_min_8b = DRV_VER_MIN;
4072 req.ver_upd_8b = DRV_VER_UPD;
4073 req.ver_maj = cpu_to_le16(DRV_VER_MAJ);
4074 req.ver_min = cpu_to_le16(DRV_VER_MIN);
4075 req.ver_upd = cpu_to_le16(DRV_VER_UPD);
4081 memset(data, 0, sizeof(data));
4082 for (i = 0; i < ARRAY_SIZE(bnxt_vf_req_snif); i++) {
4083 u16 cmd = bnxt_vf_req_snif[i];
4084 unsigned int bit, idx;
4088 data[idx] |= 1 << bit;
4091 for (i = 0; i < 8; i++)
4092 req.vf_req_fwd[i] = cpu_to_le32(data[i]);
4095 cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_VF_REQ_FWD);
4098 if (bp->fw_cap & BNXT_FW_CAP_OVS_64BIT_HANDLE)
4099 req.flags |= cpu_to_le32(
4100 FUNC_DRV_RGTR_REQ_FLAGS_FLOW_HANDLE_64BIT_MODE);
4102 mutex_lock(&bp->hwrm_cmd_lock);
4103 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4106 else if (resp->flags &
4107 cpu_to_le32(FUNC_DRV_RGTR_RESP_FLAGS_IF_CHANGE_SUPPORTED))
4108 bp->fw_cap |= BNXT_FW_CAP_IF_CHANGE;
4109 mutex_unlock(&bp->hwrm_cmd_lock);
4113 static int bnxt_hwrm_func_drv_unrgtr(struct bnxt *bp)
4115 struct hwrm_func_drv_unrgtr_input req = {0};
4117 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_UNRGTR, -1, -1);
4118 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4121 static int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, u8 tunnel_type)
4124 struct hwrm_tunnel_dst_port_free_input req = {0};
4126 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_TUNNEL_DST_PORT_FREE, -1, -1);
4127 req.tunnel_type = tunnel_type;
4129 switch (tunnel_type) {
4130 case TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN:
4131 req.tunnel_dst_port_id = bp->vxlan_fw_dst_port_id;
4133 case TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE:
4134 req.tunnel_dst_port_id = bp->nge_fw_dst_port_id;
4140 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4142 netdev_err(bp->dev, "hwrm_tunnel_dst_port_free failed. rc:%d\n",
4147 static int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, __be16 port,
4151 struct hwrm_tunnel_dst_port_alloc_input req = {0};
4152 struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr;
4154 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_TUNNEL_DST_PORT_ALLOC, -1, -1);
4156 req.tunnel_type = tunnel_type;
4157 req.tunnel_dst_port_val = port;
4159 mutex_lock(&bp->hwrm_cmd_lock);
4160 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4162 netdev_err(bp->dev, "hwrm_tunnel_dst_port_alloc failed. rc:%d\n",
4167 switch (tunnel_type) {
4168 case TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN:
4169 bp->vxlan_fw_dst_port_id = resp->tunnel_dst_port_id;
4171 case TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_GENEVE:
4172 bp->nge_fw_dst_port_id = resp->tunnel_dst_port_id;
4179 mutex_unlock(&bp->hwrm_cmd_lock);
4183 static int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp, u16 vnic_id)
4185 struct hwrm_cfa_l2_set_rx_mask_input req = {0};
4186 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
4188 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_SET_RX_MASK, -1, -1);
4189 req.vnic_id = cpu_to_le32(vnic->fw_vnic_id);
4191 req.num_mc_entries = cpu_to_le32(vnic->mc_list_count);
4192 req.mc_tbl_addr = cpu_to_le64(vnic->mc_list_mapping);
4193 req.mask = cpu_to_le32(vnic->rx_mask);
4194 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4197 #ifdef CONFIG_RFS_ACCEL
4198 static int bnxt_hwrm_cfa_ntuple_filter_free(struct bnxt *bp,
4199 struct bnxt_ntuple_filter *fltr)
4201 struct hwrm_cfa_ntuple_filter_free_input req = {0};
4203 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_NTUPLE_FILTER_FREE, -1, -1);
4204 req.ntuple_filter_id = fltr->filter_id;
4205 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4208 #define BNXT_NTP_FLTR_FLAGS \
4209 (CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID | \
4210 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_ETHERTYPE | \
4211 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_MACADDR | \
4212 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IPADDR_TYPE | \
4213 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR | \
4214 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR_MASK | \
4215 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR | \
4216 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR_MASK | \
4217 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IP_PROTOCOL | \
4218 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT | \
4219 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT_MASK | \
4220 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT | \
4221 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT_MASK | \
4222 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_ID)
4224 #define BNXT_NTP_TUNNEL_FLTR_FLAG \
4225 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE
4227 static int bnxt_hwrm_cfa_ntuple_filter_alloc(struct bnxt *bp,
4228 struct bnxt_ntuple_filter *fltr)
4230 struct hwrm_cfa_ntuple_filter_alloc_input req = {0};
4231 struct hwrm_cfa_ntuple_filter_alloc_output *resp;
4232 struct flow_keys *keys = &fltr->fkeys;
4233 struct bnxt_vnic_info *vnic;
4237 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_NTUPLE_FILTER_ALLOC, -1, -1);
4238 req.l2_filter_id = bp->vnic_info[0].fw_l2_filter_id[fltr->l2_fltr_idx];
4240 if (bp->fw_cap & BNXT_FW_CAP_CFA_RFS_RING_TBL_IDX) {
4241 dst_ena = CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_RFS_RING_TBL_IDX;
4242 req.rfs_ring_tbl_idx = cpu_to_le16(fltr->rxq);
4243 vnic = &bp->vnic_info[0];
4245 vnic = &bp->vnic_info[fltr->rxq + 1];
4247 req.dst_id = cpu_to_le16(vnic->fw_vnic_id);
4248 req.enables = cpu_to_le32(BNXT_NTP_FLTR_FLAGS | dst_ena);
4250 req.ethertype = htons(ETH_P_IP);
4251 memcpy(req.src_macaddr, fltr->src_mac_addr, ETH_ALEN);
4252 req.ip_addr_type = CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV4;
4253 req.ip_protocol = keys->basic.ip_proto;
4255 if (keys->basic.n_proto == htons(ETH_P_IPV6)) {
4258 req.ethertype = htons(ETH_P_IPV6);
4260 CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6;
4261 *(struct in6_addr *)&req.src_ipaddr[0] =
4262 keys->addrs.v6addrs.src;
4263 *(struct in6_addr *)&req.dst_ipaddr[0] =
4264 keys->addrs.v6addrs.dst;
4265 for (i = 0; i < 4; i++) {
4266 req.src_ipaddr_mask[i] = cpu_to_be32(0xffffffff);
4267 req.dst_ipaddr_mask[i] = cpu_to_be32(0xffffffff);
4270 req.src_ipaddr[0] = keys->addrs.v4addrs.src;
4271 req.src_ipaddr_mask[0] = cpu_to_be32(0xffffffff);
4272 req.dst_ipaddr[0] = keys->addrs.v4addrs.dst;
4273 req.dst_ipaddr_mask[0] = cpu_to_be32(0xffffffff);
4275 if (keys->control.flags & FLOW_DIS_ENCAPSULATION) {
4276 req.enables |= cpu_to_le32(BNXT_NTP_TUNNEL_FLTR_FLAG);
4278 CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL;
4281 req.src_port = keys->ports.src;
4282 req.src_port_mask = cpu_to_be16(0xffff);
4283 req.dst_port = keys->ports.dst;
4284 req.dst_port_mask = cpu_to_be16(0xffff);
4286 mutex_lock(&bp->hwrm_cmd_lock);
4287 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4289 resp = bnxt_get_hwrm_resp_addr(bp, &req);
4290 fltr->filter_id = resp->ntuple_filter_id;
4292 mutex_unlock(&bp->hwrm_cmd_lock);
4297 static int bnxt_hwrm_set_vnic_filter(struct bnxt *bp, u16 vnic_id, u16 idx,
4301 struct hwrm_cfa_l2_filter_alloc_input req = {0};
4302 struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
4304 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_FILTER_ALLOC, -1, -1);
4305 req.flags = cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX);
4306 if (!BNXT_CHIP_TYPE_NITRO_A0(bp))
4308 cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_FLAGS_OUTERMOST);
4309 req.dst_id = cpu_to_le16(bp->vnic_info[vnic_id].fw_vnic_id);
4311 cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR |
4312 CFA_L2_FILTER_ALLOC_REQ_ENABLES_DST_ID |
4313 CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR_MASK);
4314 memcpy(req.l2_addr, mac_addr, ETH_ALEN);
4315 req.l2_addr_mask[0] = 0xff;
4316 req.l2_addr_mask[1] = 0xff;
4317 req.l2_addr_mask[2] = 0xff;
4318 req.l2_addr_mask[3] = 0xff;
4319 req.l2_addr_mask[4] = 0xff;
4320 req.l2_addr_mask[5] = 0xff;
4322 mutex_lock(&bp->hwrm_cmd_lock);
4323 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4325 bp->vnic_info[vnic_id].fw_l2_filter_id[idx] =
4327 mutex_unlock(&bp->hwrm_cmd_lock);
4331 static int bnxt_hwrm_clear_vnic_filter(struct bnxt *bp)
4333 u16 i, j, num_of_vnics = 1; /* only vnic 0 supported */
4336 /* Any associated ntuple filters will also be cleared by firmware. */
4337 mutex_lock(&bp->hwrm_cmd_lock);
4338 for (i = 0; i < num_of_vnics; i++) {
4339 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
4341 for (j = 0; j < vnic->uc_filter_count; j++) {
4342 struct hwrm_cfa_l2_filter_free_input req = {0};
4344 bnxt_hwrm_cmd_hdr_init(bp, &req,
4345 HWRM_CFA_L2_FILTER_FREE, -1, -1);
4347 req.l2_filter_id = vnic->fw_l2_filter_id[j];
4349 rc = _hwrm_send_message(bp, &req, sizeof(req),
4352 vnic->uc_filter_count = 0;
4354 mutex_unlock(&bp->hwrm_cmd_lock);
4359 static int bnxt_hwrm_vnic_set_tpa(struct bnxt *bp, u16 vnic_id, u32 tpa_flags)
4361 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
4362 struct hwrm_vnic_tpa_cfg_input req = {0};
4364 if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
4367 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_TPA_CFG, -1, -1);
4370 u16 mss = bp->dev->mtu - 40;
4371 u32 nsegs, n, segs = 0, flags;
4373 flags = VNIC_TPA_CFG_REQ_FLAGS_TPA |
4374 VNIC_TPA_CFG_REQ_FLAGS_ENCAP_TPA |
4375 VNIC_TPA_CFG_REQ_FLAGS_RSC_WND_UPDATE |
4376 VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_ECN |
4377 VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_SAME_GRE_SEQ;
4378 if (tpa_flags & BNXT_FLAG_GRO)
4379 flags |= VNIC_TPA_CFG_REQ_FLAGS_GRO;
4381 req.flags = cpu_to_le32(flags);
4384 cpu_to_le32(VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_SEGS |
4385 VNIC_TPA_CFG_REQ_ENABLES_MAX_AGGS |
4386 VNIC_TPA_CFG_REQ_ENABLES_MIN_AGG_LEN);
4388 /* Number of segs are log2 units, and first packet is not
4389 * included as part of this units.
4391 if (mss <= BNXT_RX_PAGE_SIZE) {
4392 n = BNXT_RX_PAGE_SIZE / mss;
4393 nsegs = (MAX_SKB_FRAGS - 1) * n;
4395 n = mss / BNXT_RX_PAGE_SIZE;
4396 if (mss & (BNXT_RX_PAGE_SIZE - 1))
4398 nsegs = (MAX_SKB_FRAGS - n) / n;
4401 segs = ilog2(nsegs);
4402 req.max_agg_segs = cpu_to_le16(segs);
4403 req.max_aggs = cpu_to_le16(VNIC_TPA_CFG_REQ_MAX_AGGS_MAX);
4405 req.min_agg_len = cpu_to_le32(512);
4407 req.vnic_id = cpu_to_le16(vnic->fw_vnic_id);
4409 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4412 static u16 bnxt_cp_ring_from_grp(struct bnxt *bp, struct bnxt_ring_struct *ring)
4414 struct bnxt_ring_grp_info *grp_info;
4416 grp_info = &bp->grp_info[ring->grp_idx];
4417 return grp_info->cp_fw_ring_id;
4420 static u16 bnxt_cp_ring_for_rx(struct bnxt *bp, struct bnxt_rx_ring_info *rxr)
4422 if (bp->flags & BNXT_FLAG_CHIP_P5) {
4423 struct bnxt_napi *bnapi = rxr->bnapi;
4424 struct bnxt_cp_ring_info *cpr;
4426 cpr = bnapi->cp_ring.cp_ring_arr[BNXT_RX_HDL];
4427 return cpr->cp_ring_struct.fw_ring_id;
4429 return bnxt_cp_ring_from_grp(bp, &rxr->rx_ring_struct);
4433 static u16 bnxt_cp_ring_for_tx(struct bnxt *bp, struct bnxt_tx_ring_info *txr)
4435 if (bp->flags & BNXT_FLAG_CHIP_P5) {
4436 struct bnxt_napi *bnapi = txr->bnapi;
4437 struct bnxt_cp_ring_info *cpr;
4439 cpr = bnapi->cp_ring.cp_ring_arr[BNXT_TX_HDL];
4440 return cpr->cp_ring_struct.fw_ring_id;
4442 return bnxt_cp_ring_from_grp(bp, &txr->tx_ring_struct);
4446 static int bnxt_hwrm_vnic_set_rss(struct bnxt *bp, u16 vnic_id, bool set_rss)
4448 u32 i, j, max_rings;
4449 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
4450 struct hwrm_vnic_rss_cfg_input req = {0};
4452 if ((bp->flags & BNXT_FLAG_CHIP_P5) ||
4453 vnic->fw_rss_cos_lb_ctx[0] == INVALID_HW_RING_ID)
4456 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_CFG, -1, -1);
4458 req.hash_type = cpu_to_le32(bp->rss_hash_cfg);
4459 req.hash_mode_flags = VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_DEFAULT;
4460 if (vnic->flags & BNXT_VNIC_RSS_FLAG) {
4461 if (BNXT_CHIP_TYPE_NITRO_A0(bp))
4462 max_rings = bp->rx_nr_rings - 1;
4464 max_rings = bp->rx_nr_rings;
4469 /* Fill the RSS indirection table with ring group ids */
4470 for (i = 0, j = 0; i < HW_HASH_INDEX_SIZE; i++, j++) {
4473 vnic->rss_table[i] = cpu_to_le16(vnic->fw_grp_ids[j]);
4476 req.ring_grp_tbl_addr = cpu_to_le64(vnic->rss_table_dma_addr);
4477 req.hash_key_tbl_addr =
4478 cpu_to_le64(vnic->rss_hash_key_dma_addr);
4480 req.rss_ctx_idx = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[0]);
4481 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4484 static int bnxt_hwrm_vnic_set_rss_p5(struct bnxt *bp, u16 vnic_id, bool set_rss)
4486 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
4487 u32 i, j, k, nr_ctxs, max_rings = bp->rx_nr_rings;
4488 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[0];
4489 struct hwrm_vnic_rss_cfg_input req = {0};
4491 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_CFG, -1, -1);
4492 req.vnic_id = cpu_to_le16(vnic->fw_vnic_id);
4494 hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4497 req.hash_type = cpu_to_le32(bp->rss_hash_cfg);
4498 req.hash_mode_flags = VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_DEFAULT;
4499 req.ring_grp_tbl_addr = cpu_to_le64(vnic->rss_table_dma_addr);
4500 req.hash_key_tbl_addr = cpu_to_le64(vnic->rss_hash_key_dma_addr);
4501 nr_ctxs = DIV_ROUND_UP(bp->rx_nr_rings, 64);
4502 for (i = 0, k = 0; i < nr_ctxs; i++) {
4503 __le16 *ring_tbl = vnic->rss_table;
4506 req.ring_table_pair_index = i;
4507 req.rss_ctx_idx = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[i]);
4508 for (j = 0; j < 64; j++) {
4511 ring_id = rxr->rx_ring_struct.fw_ring_id;
4512 *ring_tbl++ = cpu_to_le16(ring_id);
4513 ring_id = bnxt_cp_ring_for_rx(bp, rxr);
4514 *ring_tbl++ = cpu_to_le16(ring_id);
4517 if (k == max_rings) {
4519 rxr = &bp->rx_ring[0];
4522 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4529 static int bnxt_hwrm_vnic_set_hds(struct bnxt *bp, u16 vnic_id)
4531 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
4532 struct hwrm_vnic_plcmodes_cfg_input req = {0};
4534 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_PLCMODES_CFG, -1, -1);
4535 req.flags = cpu_to_le32(VNIC_PLCMODES_CFG_REQ_FLAGS_JUMBO_PLACEMENT |
4536 VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV4 |
4537 VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV6);
4539 cpu_to_le32(VNIC_PLCMODES_CFG_REQ_ENABLES_JUMBO_THRESH_VALID |
4540 VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_THRESHOLD_VALID);
4541 /* thresholds not implemented in firmware yet */
4542 req.jumbo_thresh = cpu_to_le16(bp->rx_copy_thresh);
4543 req.hds_threshold = cpu_to_le16(bp->rx_copy_thresh);
4544 req.vnic_id = cpu_to_le32(vnic->fw_vnic_id);
4545 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4548 static void bnxt_hwrm_vnic_ctx_free_one(struct bnxt *bp, u16 vnic_id,
4551 struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {0};
4553 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_COS_LB_CTX_FREE, -1, -1);
4554 req.rss_cos_lb_ctx_id =
4555 cpu_to_le16(bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[ctx_idx]);
4557 hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4558 bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[ctx_idx] = INVALID_HW_RING_ID;
4561 static void bnxt_hwrm_vnic_ctx_free(struct bnxt *bp)
4565 for (i = 0; i < bp->nr_vnics; i++) {
4566 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
4568 for (j = 0; j < BNXT_MAX_CTX_PER_VNIC; j++) {
4569 if (vnic->fw_rss_cos_lb_ctx[j] != INVALID_HW_RING_ID)
4570 bnxt_hwrm_vnic_ctx_free_one(bp, i, j);
4573 bp->rsscos_nr_ctxs = 0;
4576 static int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp, u16 vnic_id, u16 ctx_idx)
4579 struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {0};
4580 struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp =
4581 bp->hwrm_cmd_resp_addr;
4583 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_COS_LB_CTX_ALLOC, -1,
4586 mutex_lock(&bp->hwrm_cmd_lock);
4587 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4589 bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[ctx_idx] =
4590 le16_to_cpu(resp->rss_cos_lb_ctx_id);
4591 mutex_unlock(&bp->hwrm_cmd_lock);
4596 static u32 bnxt_get_roce_vnic_mode(struct bnxt *bp)
4598 if (bp->flags & BNXT_FLAG_ROCE_MIRROR_CAP)
4599 return VNIC_CFG_REQ_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_MODE;
4600 return VNIC_CFG_REQ_FLAGS_ROCE_DUAL_VNIC_MODE;
4603 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, u16 vnic_id)
4605 unsigned int ring = 0, grp_idx;
4606 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
4607 struct hwrm_vnic_cfg_input req = {0};
4610 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_CFG, -1, -1);
4612 if (bp->flags & BNXT_FLAG_CHIP_P5) {
4613 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[0];
4615 req.default_rx_ring_id =
4616 cpu_to_le16(rxr->rx_ring_struct.fw_ring_id);
4617 req.default_cmpl_ring_id =
4618 cpu_to_le16(bnxt_cp_ring_for_rx(bp, rxr));
4620 cpu_to_le32(VNIC_CFG_REQ_ENABLES_DEFAULT_RX_RING_ID |
4621 VNIC_CFG_REQ_ENABLES_DEFAULT_CMPL_RING_ID);
4624 req.enables = cpu_to_le32(VNIC_CFG_REQ_ENABLES_DFLT_RING_GRP);
4625 /* Only RSS support for now TBD: COS & LB */
4626 if (vnic->fw_rss_cos_lb_ctx[0] != INVALID_HW_RING_ID) {
4627 req.rss_rule = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[0]);
4628 req.enables |= cpu_to_le32(VNIC_CFG_REQ_ENABLES_RSS_RULE |
4629 VNIC_CFG_REQ_ENABLES_MRU);
4630 } else if (vnic->flags & BNXT_VNIC_RFS_NEW_RSS_FLAG) {
4632 cpu_to_le16(bp->vnic_info[0].fw_rss_cos_lb_ctx[0]);
4633 req.enables |= cpu_to_le32(VNIC_CFG_REQ_ENABLES_RSS_RULE |
4634 VNIC_CFG_REQ_ENABLES_MRU);
4635 req.flags |= cpu_to_le32(VNIC_CFG_REQ_FLAGS_RSS_DFLT_CR_MODE);
4637 req.rss_rule = cpu_to_le16(0xffff);
4640 if (BNXT_CHIP_TYPE_NITRO_A0(bp) &&
4641 (vnic->fw_rss_cos_lb_ctx[0] != INVALID_HW_RING_ID)) {
4642 req.cos_rule = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[1]);
4643 req.enables |= cpu_to_le32(VNIC_CFG_REQ_ENABLES_COS_RULE);
4645 req.cos_rule = cpu_to_le16(0xffff);
4648 if (vnic->flags & BNXT_VNIC_RSS_FLAG)
4650 else if (vnic->flags & BNXT_VNIC_RFS_FLAG)
4652 else if ((vnic_id == 1) && BNXT_CHIP_TYPE_NITRO_A0(bp))
4653 ring = bp->rx_nr_rings - 1;
4655 grp_idx = bp->rx_ring[ring].bnapi->index;
4656 req.dflt_ring_grp = cpu_to_le16(bp->grp_info[grp_idx].fw_grp_id);
4657 req.lb_rule = cpu_to_le16(0xffff);
4659 req.mru = cpu_to_le16(bp->dev->mtu + ETH_HLEN + ETH_FCS_LEN +
4662 req.vnic_id = cpu_to_le16(vnic->fw_vnic_id);
4663 #ifdef CONFIG_BNXT_SRIOV
4665 def_vlan = bp->vf.vlan;
4667 if ((bp->flags & BNXT_FLAG_STRIP_VLAN) || def_vlan)
4668 req.flags |= cpu_to_le32(VNIC_CFG_REQ_FLAGS_VLAN_STRIP_MODE);
4669 if (!vnic_id && bnxt_ulp_registered(bp->edev, BNXT_ROCE_ULP))
4670 req.flags |= cpu_to_le32(bnxt_get_roce_vnic_mode(bp));
4672 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4675 static int bnxt_hwrm_vnic_free_one(struct bnxt *bp, u16 vnic_id)
4679 if (bp->vnic_info[vnic_id].fw_vnic_id != INVALID_HW_RING_ID) {
4680 struct hwrm_vnic_free_input req = {0};
4682 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_FREE, -1, -1);
4684 cpu_to_le32(bp->vnic_info[vnic_id].fw_vnic_id);
4686 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4689 bp->vnic_info[vnic_id].fw_vnic_id = INVALID_HW_RING_ID;
4694 static void bnxt_hwrm_vnic_free(struct bnxt *bp)
4698 for (i = 0; i < bp->nr_vnics; i++)
4699 bnxt_hwrm_vnic_free_one(bp, i);
4702 static int bnxt_hwrm_vnic_alloc(struct bnxt *bp, u16 vnic_id,
4703 unsigned int start_rx_ring_idx,
4704 unsigned int nr_rings)
4707 unsigned int i, j, grp_idx, end_idx = start_rx_ring_idx + nr_rings;
4708 struct hwrm_vnic_alloc_input req = {0};
4709 struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
4710 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
4712 if (bp->flags & BNXT_FLAG_CHIP_P5)
4713 goto vnic_no_ring_grps;
4715 /* map ring groups to this vnic */
4716 for (i = start_rx_ring_idx, j = 0; i < end_idx; i++, j++) {
4717 grp_idx = bp->rx_ring[i].bnapi->index;
4718 if (bp->grp_info[grp_idx].fw_grp_id == INVALID_HW_RING_ID) {
4719 netdev_err(bp->dev, "Not enough ring groups avail:%x req:%x\n",
4723 vnic->fw_grp_ids[j] = bp->grp_info[grp_idx].fw_grp_id;
4727 for (i = 0; i < BNXT_MAX_CTX_PER_VNIC; i++)
4728 vnic->fw_rss_cos_lb_ctx[i] = INVALID_HW_RING_ID;
4730 req.flags = cpu_to_le32(VNIC_ALLOC_REQ_FLAGS_DEFAULT);
4732 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_ALLOC, -1, -1);
4734 mutex_lock(&bp->hwrm_cmd_lock);
4735 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4737 vnic->fw_vnic_id = le32_to_cpu(resp->vnic_id);
4738 mutex_unlock(&bp->hwrm_cmd_lock);
4742 static int bnxt_hwrm_vnic_qcaps(struct bnxt *bp)
4744 struct hwrm_vnic_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
4745 struct hwrm_vnic_qcaps_input req = {0};
4748 if (bp->hwrm_spec_code < 0x10600)
4751 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_QCAPS, -1, -1);
4752 mutex_lock(&bp->hwrm_cmd_lock);
4753 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4755 u32 flags = le32_to_cpu(resp->flags);
4757 if (!(bp->flags & BNXT_FLAG_CHIP_P5) &&
4758 (flags & VNIC_QCAPS_RESP_FLAGS_RSS_DFLT_CR_CAP))
4759 bp->flags |= BNXT_FLAG_NEW_RSS_CAP;
4761 VNIC_QCAPS_RESP_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_CAP)
4762 bp->flags |= BNXT_FLAG_ROCE_MIRROR_CAP;
4764 mutex_unlock(&bp->hwrm_cmd_lock);
4768 static int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp)
4773 if (bp->flags & BNXT_FLAG_CHIP_P5)
4776 mutex_lock(&bp->hwrm_cmd_lock);
4777 for (i = 0; i < bp->rx_nr_rings; i++) {
4778 struct hwrm_ring_grp_alloc_input req = {0};
4779 struct hwrm_ring_grp_alloc_output *resp =
4780 bp->hwrm_cmd_resp_addr;
4781 unsigned int grp_idx = bp->rx_ring[i].bnapi->index;
4783 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_GRP_ALLOC, -1, -1);
4785 req.cr = cpu_to_le16(bp->grp_info[grp_idx].cp_fw_ring_id);
4786 req.rr = cpu_to_le16(bp->grp_info[grp_idx].rx_fw_ring_id);
4787 req.ar = cpu_to_le16(bp->grp_info[grp_idx].agg_fw_ring_id);
4788 req.sc = cpu_to_le16(bp->grp_info[grp_idx].fw_stats_ctx);
4790 rc = _hwrm_send_message(bp, &req, sizeof(req),
4795 bp->grp_info[grp_idx].fw_grp_id =
4796 le32_to_cpu(resp->ring_group_id);
4798 mutex_unlock(&bp->hwrm_cmd_lock);
4802 static int bnxt_hwrm_ring_grp_free(struct bnxt *bp)
4806 struct hwrm_ring_grp_free_input req = {0};
4808 if (!bp->grp_info || (bp->flags & BNXT_FLAG_CHIP_P5))
4811 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_GRP_FREE, -1, -1);
4813 mutex_lock(&bp->hwrm_cmd_lock);
4814 for (i = 0; i < bp->cp_nr_rings; i++) {
4815 if (bp->grp_info[i].fw_grp_id == INVALID_HW_RING_ID)
4818 cpu_to_le32(bp->grp_info[i].fw_grp_id);
4820 rc = _hwrm_send_message(bp, &req, sizeof(req),
4824 bp->grp_info[i].fw_grp_id = INVALID_HW_RING_ID;
4826 mutex_unlock(&bp->hwrm_cmd_lock);
4830 static int hwrm_ring_alloc_send_msg(struct bnxt *bp,
4831 struct bnxt_ring_struct *ring,
4832 u32 ring_type, u32 map_index)
4834 int rc = 0, err = 0;
4835 struct hwrm_ring_alloc_input req = {0};
4836 struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr;
4837 struct bnxt_ring_mem_info *rmem = &ring->ring_mem;
4838 struct bnxt_ring_grp_info *grp_info;
4841 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_ALLOC, -1, -1);
4844 if (rmem->nr_pages > 1) {
4845 req.page_tbl_addr = cpu_to_le64(rmem->pg_tbl_map);
4846 /* Page size is in log2 units */
4847 req.page_size = BNXT_PAGE_SHIFT;
4848 req.page_tbl_depth = 1;
4850 req.page_tbl_addr = cpu_to_le64(rmem->dma_arr[0]);
4853 /* Association of ring index with doorbell index and MSIX number */
4854 req.logical_id = cpu_to_le16(map_index);
4856 switch (ring_type) {
4857 case HWRM_RING_ALLOC_TX: {
4858 struct bnxt_tx_ring_info *txr;
4860 txr = container_of(ring, struct bnxt_tx_ring_info,
4862 req.ring_type = RING_ALLOC_REQ_RING_TYPE_TX;
4863 /* Association of transmit ring with completion ring */
4864 grp_info = &bp->grp_info[ring->grp_idx];
4865 req.cmpl_ring_id = cpu_to_le16(bnxt_cp_ring_for_tx(bp, txr));
4866 req.length = cpu_to_le32(bp->tx_ring_mask + 1);
4867 req.stat_ctx_id = cpu_to_le32(grp_info->fw_stats_ctx);
4868 req.queue_id = cpu_to_le16(ring->queue_id);
4871 case HWRM_RING_ALLOC_RX:
4872 req.ring_type = RING_ALLOC_REQ_RING_TYPE_RX;
4873 req.length = cpu_to_le32(bp->rx_ring_mask + 1);
4874 if (bp->flags & BNXT_FLAG_CHIP_P5) {
4877 /* Association of rx ring with stats context */
4878 grp_info = &bp->grp_info[ring->grp_idx];
4879 req.rx_buf_size = cpu_to_le16(bp->rx_buf_use_size);
4880 req.stat_ctx_id = cpu_to_le32(grp_info->fw_stats_ctx);
4881 req.enables |= cpu_to_le32(
4882 RING_ALLOC_REQ_ENABLES_RX_BUF_SIZE_VALID);
4883 if (NET_IP_ALIGN == 2)
4884 flags = RING_ALLOC_REQ_FLAGS_RX_SOP_PAD;
4885 req.flags = cpu_to_le16(flags);
4888 case HWRM_RING_ALLOC_AGG:
4889 if (bp->flags & BNXT_FLAG_CHIP_P5) {
4890 req.ring_type = RING_ALLOC_REQ_RING_TYPE_RX_AGG;
4891 /* Association of agg ring with rx ring */
4892 grp_info = &bp->grp_info[ring->grp_idx];
4893 req.rx_ring_id = cpu_to_le16(grp_info->rx_fw_ring_id);
4894 req.rx_buf_size = cpu_to_le16(BNXT_RX_PAGE_SIZE);
4895 req.stat_ctx_id = cpu_to_le32(grp_info->fw_stats_ctx);
4896 req.enables |= cpu_to_le32(
4897 RING_ALLOC_REQ_ENABLES_RX_RING_ID_VALID |
4898 RING_ALLOC_REQ_ENABLES_RX_BUF_SIZE_VALID);
4900 req.ring_type = RING_ALLOC_REQ_RING_TYPE_RX;
4902 req.length = cpu_to_le32(bp->rx_agg_ring_mask + 1);
4904 case HWRM_RING_ALLOC_CMPL:
4905 req.ring_type = RING_ALLOC_REQ_RING_TYPE_L2_CMPL;
4906 req.length = cpu_to_le32(bp->cp_ring_mask + 1);
4907 if (bp->flags & BNXT_FLAG_CHIP_P5) {
4908 /* Association of cp ring with nq */
4909 grp_info = &bp->grp_info[map_index];
4910 req.nq_ring_id = cpu_to_le16(grp_info->cp_fw_ring_id);
4911 req.cq_handle = cpu_to_le64(ring->handle);
4912 req.enables |= cpu_to_le32(
4913 RING_ALLOC_REQ_ENABLES_NQ_RING_ID_VALID);
4914 } else if (bp->flags & BNXT_FLAG_USING_MSIX) {
4915 req.int_mode = RING_ALLOC_REQ_INT_MODE_MSIX;
4918 case HWRM_RING_ALLOC_NQ:
4919 req.ring_type = RING_ALLOC_REQ_RING_TYPE_NQ;
4920 req.length = cpu_to_le32(bp->cp_ring_mask + 1);
4921 if (bp->flags & BNXT_FLAG_USING_MSIX)
4922 req.int_mode = RING_ALLOC_REQ_INT_MODE_MSIX;
4925 netdev_err(bp->dev, "hwrm alloc invalid ring type %d\n",
4930 mutex_lock(&bp->hwrm_cmd_lock);
4931 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4932 err = le16_to_cpu(resp->error_code);
4933 ring_id = le16_to_cpu(resp->ring_id);
4934 mutex_unlock(&bp->hwrm_cmd_lock);
4937 netdev_err(bp->dev, "hwrm_ring_alloc type %d failed. rc:%x err:%x\n",
4938 ring_type, rc, err);
4941 ring->fw_ring_id = ring_id;
4945 static int bnxt_hwrm_set_async_event_cr(struct bnxt *bp, int idx)
4950 struct hwrm_func_cfg_input req = {0};
4952 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_CFG, -1, -1);
4953 req.fid = cpu_to_le16(0xffff);
4954 req.enables = cpu_to_le32(FUNC_CFG_REQ_ENABLES_ASYNC_EVENT_CR);
4955 req.async_event_cr = cpu_to_le16(idx);
4956 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4958 struct hwrm_func_vf_cfg_input req = {0};
4960 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_VF_CFG, -1, -1);
4962 cpu_to_le32(FUNC_VF_CFG_REQ_ENABLES_ASYNC_EVENT_CR);
4963 req.async_event_cr = cpu_to_le16(idx);
4964 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4969 static void bnxt_set_db(struct bnxt *bp, struct bnxt_db_info *db, u32 ring_type,
4970 u32 map_idx, u32 xid)
4972 if (bp->flags & BNXT_FLAG_CHIP_P5) {
4974 db->doorbell = bp->bar1 + 0x10000;
4976 db->doorbell = bp->bar1 + 0x4000;
4977 switch (ring_type) {
4978 case HWRM_RING_ALLOC_TX:
4979 db->db_key64 = DBR_PATH_L2 | DBR_TYPE_SQ;
4981 case HWRM_RING_ALLOC_RX:
4982 case HWRM_RING_ALLOC_AGG:
4983 db->db_key64 = DBR_PATH_L2 | DBR_TYPE_SRQ;
4985 case HWRM_RING_ALLOC_CMPL:
4986 db->db_key64 = DBR_PATH_L2;
4988 case HWRM_RING_ALLOC_NQ:
4989 db->db_key64 = DBR_PATH_L2;
4992 db->db_key64 |= (u64)xid << DBR_XID_SFT;
4994 db->doorbell = bp->bar1 + map_idx * 0x80;
4995 switch (ring_type) {
4996 case HWRM_RING_ALLOC_TX:
4997 db->db_key32 = DB_KEY_TX;
4999 case HWRM_RING_ALLOC_RX:
5000 case HWRM_RING_ALLOC_AGG:
5001 db->db_key32 = DB_KEY_RX;
5003 case HWRM_RING_ALLOC_CMPL:
5004 db->db_key32 = DB_KEY_CP;
5010 static int bnxt_hwrm_ring_alloc(struct bnxt *bp)
5015 if (bp->flags & BNXT_FLAG_CHIP_P5)
5016 type = HWRM_RING_ALLOC_NQ;
5018 type = HWRM_RING_ALLOC_CMPL;
5019 for (i = 0; i < bp->cp_nr_rings; i++) {
5020 struct bnxt_napi *bnapi = bp->bnapi[i];
5021 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
5022 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct;
5023 u32 map_idx = ring->map_idx;
5024 unsigned int vector;
5026 vector = bp->irq_tbl[map_idx].vector;
5027 disable_irq_nosync(vector);
5028 rc = hwrm_ring_alloc_send_msg(bp, ring, type, map_idx);
5033 bnxt_set_db(bp, &cpr->cp_db, type, map_idx, ring->fw_ring_id);
5034 bnxt_db_nq(bp, &cpr->cp_db, cpr->cp_raw_cons);
5036 bp->grp_info[i].cp_fw_ring_id = ring->fw_ring_id;
5039 rc = bnxt_hwrm_set_async_event_cr(bp, ring->fw_ring_id);
5041 netdev_warn(bp->dev, "Failed to set async event completion ring.\n");
5045 type = HWRM_RING_ALLOC_TX;
5046 for (i = 0; i < bp->tx_nr_rings; i++) {
5047 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
5048 struct bnxt_ring_struct *ring;
5051 if (bp->flags & BNXT_FLAG_CHIP_P5) {
5052 struct bnxt_napi *bnapi = txr->bnapi;
5053 struct bnxt_cp_ring_info *cpr, *cpr2;
5054 u32 type2 = HWRM_RING_ALLOC_CMPL;
5056 cpr = &bnapi->cp_ring;
5057 cpr2 = cpr->cp_ring_arr[BNXT_TX_HDL];
5058 ring = &cpr2->cp_ring_struct;
5059 ring->handle = BNXT_TX_HDL;
5060 map_idx = bnapi->index;
5061 rc = hwrm_ring_alloc_send_msg(bp, ring, type2, map_idx);
5064 bnxt_set_db(bp, &cpr2->cp_db, type2, map_idx,
5066 bnxt_db_cq(bp, &cpr2->cp_db, cpr2->cp_raw_cons);
5068 ring = &txr->tx_ring_struct;
5070 rc = hwrm_ring_alloc_send_msg(bp, ring, type, map_idx);
5073 bnxt_set_db(bp, &txr->tx_db, type, map_idx, ring->fw_ring_id);
5076 type = HWRM_RING_ALLOC_RX;
5077 for (i = 0; i < bp->rx_nr_rings; i++) {
5078 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
5079 struct bnxt_ring_struct *ring = &rxr->rx_ring_struct;
5080 struct bnxt_napi *bnapi = rxr->bnapi;
5081 u32 map_idx = bnapi->index;
5083 rc = hwrm_ring_alloc_send_msg(bp, ring, type, map_idx);
5086 bnxt_set_db(bp, &rxr->rx_db, type, map_idx, ring->fw_ring_id);
5087 bnxt_db_write(bp, &rxr->rx_db, rxr->rx_prod);
5088 bp->grp_info[map_idx].rx_fw_ring_id = ring->fw_ring_id;
5089 if (bp->flags & BNXT_FLAG_CHIP_P5) {
5090 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
5091 u32 type2 = HWRM_RING_ALLOC_CMPL;
5092 struct bnxt_cp_ring_info *cpr2;
5094 cpr2 = cpr->cp_ring_arr[BNXT_RX_HDL];
5095 ring = &cpr2->cp_ring_struct;
5096 ring->handle = BNXT_RX_HDL;
5097 rc = hwrm_ring_alloc_send_msg(bp, ring, type2, map_idx);
5100 bnxt_set_db(bp, &cpr2->cp_db, type2, map_idx,
5102 bnxt_db_cq(bp, &cpr2->cp_db, cpr2->cp_raw_cons);
5106 if (bp->flags & BNXT_FLAG_AGG_RINGS) {
5107 type = HWRM_RING_ALLOC_AGG;
5108 for (i = 0; i < bp->rx_nr_rings; i++) {
5109 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
5110 struct bnxt_ring_struct *ring =
5111 &rxr->rx_agg_ring_struct;
5112 u32 grp_idx = ring->grp_idx;
5113 u32 map_idx = grp_idx + bp->rx_nr_rings;
5115 rc = hwrm_ring_alloc_send_msg(bp, ring, type, map_idx);
5119 bnxt_set_db(bp, &rxr->rx_agg_db, type, map_idx,
5121 bnxt_db_write(bp, &rxr->rx_agg_db, rxr->rx_agg_prod);
5122 bp->grp_info[grp_idx].agg_fw_ring_id = ring->fw_ring_id;
5129 static int hwrm_ring_free_send_msg(struct bnxt *bp,
5130 struct bnxt_ring_struct *ring,
5131 u32 ring_type, int cmpl_ring_id)
5134 struct hwrm_ring_free_input req = {0};
5135 struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;
5138 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_FREE, cmpl_ring_id, -1);
5139 req.ring_type = ring_type;
5140 req.ring_id = cpu_to_le16(ring->fw_ring_id);
5142 mutex_lock(&bp->hwrm_cmd_lock);
5143 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5144 error_code = le16_to_cpu(resp->error_code);
5145 mutex_unlock(&bp->hwrm_cmd_lock);
5147 if (rc || error_code) {
5148 netdev_err(bp->dev, "hwrm_ring_free type %d failed. rc:%x err:%x\n",
5149 ring_type, rc, error_code);
5155 static void bnxt_hwrm_ring_free(struct bnxt *bp, bool close_path)
5163 for (i = 0; i < bp->tx_nr_rings; i++) {
5164 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
5165 struct bnxt_ring_struct *ring = &txr->tx_ring_struct;
5167 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
5168 u32 cmpl_ring_id = bnxt_cp_ring_for_tx(bp, txr);
5170 hwrm_ring_free_send_msg(bp, ring,
5171 RING_FREE_REQ_RING_TYPE_TX,
5172 close_path ? cmpl_ring_id :
5173 INVALID_HW_RING_ID);
5174 ring->fw_ring_id = INVALID_HW_RING_ID;
5178 for (i = 0; i < bp->rx_nr_rings; i++) {
5179 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
5180 struct bnxt_ring_struct *ring = &rxr->rx_ring_struct;
5181 u32 grp_idx = rxr->bnapi->index;
5183 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
5184 u32 cmpl_ring_id = bnxt_cp_ring_for_rx(bp, rxr);
5186 hwrm_ring_free_send_msg(bp, ring,
5187 RING_FREE_REQ_RING_TYPE_RX,
5188 close_path ? cmpl_ring_id :
5189 INVALID_HW_RING_ID);
5190 ring->fw_ring_id = INVALID_HW_RING_ID;
5191 bp->grp_info[grp_idx].rx_fw_ring_id =
5196 if (bp->flags & BNXT_FLAG_CHIP_P5)
5197 type = RING_FREE_REQ_RING_TYPE_RX_AGG;
5199 type = RING_FREE_REQ_RING_TYPE_RX;
5200 for (i = 0; i < bp->rx_nr_rings; i++) {
5201 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
5202 struct bnxt_ring_struct *ring = &rxr->rx_agg_ring_struct;
5203 u32 grp_idx = rxr->bnapi->index;
5205 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
5206 u32 cmpl_ring_id = bnxt_cp_ring_for_rx(bp, rxr);
5208 hwrm_ring_free_send_msg(bp, ring, type,
5209 close_path ? cmpl_ring_id :
5210 INVALID_HW_RING_ID);
5211 ring->fw_ring_id = INVALID_HW_RING_ID;
5212 bp->grp_info[grp_idx].agg_fw_ring_id =
5217 /* The completion rings are about to be freed. After that the
5218 * IRQ doorbell will not work anymore. So we need to disable
5221 bnxt_disable_int_sync(bp);
5223 if (bp->flags & BNXT_FLAG_CHIP_P5)
5224 type = RING_FREE_REQ_RING_TYPE_NQ;
5226 type = RING_FREE_REQ_RING_TYPE_L2_CMPL;
5227 for (i = 0; i < bp->cp_nr_rings; i++) {
5228 struct bnxt_napi *bnapi = bp->bnapi[i];
5229 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
5230 struct bnxt_ring_struct *ring;
5233 for (j = 0; j < 2; j++) {
5234 struct bnxt_cp_ring_info *cpr2 = cpr->cp_ring_arr[j];
5237 ring = &cpr2->cp_ring_struct;
5238 if (ring->fw_ring_id == INVALID_HW_RING_ID)
5240 hwrm_ring_free_send_msg(bp, ring,
5241 RING_FREE_REQ_RING_TYPE_L2_CMPL,
5242 INVALID_HW_RING_ID);
5243 ring->fw_ring_id = INVALID_HW_RING_ID;
5246 ring = &cpr->cp_ring_struct;
5247 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
5248 hwrm_ring_free_send_msg(bp, ring, type,
5249 INVALID_HW_RING_ID);
5250 ring->fw_ring_id = INVALID_HW_RING_ID;
5251 bp->grp_info[i].cp_fw_ring_id = INVALID_HW_RING_ID;
5256 static int bnxt_trim_rings(struct bnxt *bp, int *rx, int *tx, int max,
5259 static int bnxt_hwrm_get_rings(struct bnxt *bp)
5261 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
5262 struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
5263 struct hwrm_func_qcfg_input req = {0};
5266 if (bp->hwrm_spec_code < 0x10601)
5269 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCFG, -1, -1);
5270 req.fid = cpu_to_le16(0xffff);
5271 mutex_lock(&bp->hwrm_cmd_lock);
5272 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5274 mutex_unlock(&bp->hwrm_cmd_lock);
5278 hw_resc->resv_tx_rings = le16_to_cpu(resp->alloc_tx_rings);
5279 if (BNXT_NEW_RM(bp)) {
5282 hw_resc->resv_rx_rings = le16_to_cpu(resp->alloc_rx_rings);
5283 hw_resc->resv_hw_ring_grps =
5284 le32_to_cpu(resp->alloc_hw_ring_grps);
5285 hw_resc->resv_vnics = le16_to_cpu(resp->alloc_vnics);
5286 cp = le16_to_cpu(resp->alloc_cmpl_rings);
5287 stats = le16_to_cpu(resp->alloc_stat_ctx);
5288 hw_resc->resv_irqs = cp;
5289 if (bp->flags & BNXT_FLAG_CHIP_P5) {
5290 int rx = hw_resc->resv_rx_rings;
5291 int tx = hw_resc->resv_tx_rings;
5293 if (bp->flags & BNXT_FLAG_AGG_RINGS)
5295 if (cp < (rx + tx)) {
5296 bnxt_trim_rings(bp, &rx, &tx, cp, false);
5297 if (bp->flags & BNXT_FLAG_AGG_RINGS)
5299 hw_resc->resv_rx_rings = rx;
5300 hw_resc->resv_tx_rings = tx;
5302 hw_resc->resv_irqs = le16_to_cpu(resp->alloc_msix);
5303 hw_resc->resv_hw_ring_grps = rx;
5305 hw_resc->resv_cp_rings = cp;
5306 hw_resc->resv_stat_ctxs = stats;
5308 mutex_unlock(&bp->hwrm_cmd_lock);
5312 /* Caller must hold bp->hwrm_cmd_lock */
5313 int __bnxt_hwrm_get_tx_rings(struct bnxt *bp, u16 fid, int *tx_rings)
5315 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
5316 struct hwrm_func_qcfg_input req = {0};
5319 if (bp->hwrm_spec_code < 0x10601)
5322 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCFG, -1, -1);
5323 req.fid = cpu_to_le16(fid);
5324 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5326 *tx_rings = le16_to_cpu(resp->alloc_tx_rings);
5331 static bool bnxt_rfs_supported(struct bnxt *bp);
5334 __bnxt_hwrm_reserve_pf_rings(struct bnxt *bp, struct hwrm_func_cfg_input *req,
5335 int tx_rings, int rx_rings, int ring_grps,
5336 int cp_rings, int stats, int vnics)
5340 bnxt_hwrm_cmd_hdr_init(bp, req, HWRM_FUNC_CFG, -1, -1);
5341 req->fid = cpu_to_le16(0xffff);
5342 enables |= tx_rings ? FUNC_CFG_REQ_ENABLES_NUM_TX_RINGS : 0;
5343 req->num_tx_rings = cpu_to_le16(tx_rings);
5344 if (BNXT_NEW_RM(bp)) {
5345 enables |= rx_rings ? FUNC_CFG_REQ_ENABLES_NUM_RX_RINGS : 0;
5346 enables |= stats ? FUNC_CFG_REQ_ENABLES_NUM_STAT_CTXS : 0;
5347 if (bp->flags & BNXT_FLAG_CHIP_P5) {
5348 enables |= cp_rings ? FUNC_CFG_REQ_ENABLES_NUM_MSIX : 0;
5349 enables |= tx_rings + ring_grps ?
5350 FUNC_CFG_REQ_ENABLES_NUM_CMPL_RINGS : 0;
5351 enables |= rx_rings ?
5352 FUNC_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS : 0;
5354 enables |= cp_rings ?
5355 FUNC_CFG_REQ_ENABLES_NUM_CMPL_RINGS : 0;
5356 enables |= ring_grps ?
5357 FUNC_CFG_REQ_ENABLES_NUM_HW_RING_GRPS |
5358 FUNC_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS : 0;
5360 enables |= vnics ? FUNC_CFG_REQ_ENABLES_NUM_VNICS : 0;
5362 req->num_rx_rings = cpu_to_le16(rx_rings);
5363 if (bp->flags & BNXT_FLAG_CHIP_P5) {
5364 req->num_cmpl_rings = cpu_to_le16(tx_rings + ring_grps);
5365 req->num_msix = cpu_to_le16(cp_rings);
5366 req->num_rsscos_ctxs =
5367 cpu_to_le16(DIV_ROUND_UP(ring_grps, 64));
5369 req->num_cmpl_rings = cpu_to_le16(cp_rings);
5370 req->num_hw_ring_grps = cpu_to_le16(ring_grps);
5371 req->num_rsscos_ctxs = cpu_to_le16(1);
5372 if (!(bp->flags & BNXT_FLAG_NEW_RSS_CAP) &&
5373 bnxt_rfs_supported(bp))
5374 req->num_rsscos_ctxs =
5375 cpu_to_le16(ring_grps + 1);
5377 req->num_stat_ctxs = cpu_to_le16(stats);
5378 req->num_vnics = cpu_to_le16(vnics);
5380 req->enables = cpu_to_le32(enables);
5384 __bnxt_hwrm_reserve_vf_rings(struct bnxt *bp,
5385 struct hwrm_func_vf_cfg_input *req, int tx_rings,
5386 int rx_rings, int ring_grps, int cp_rings,
5387 int stats, int vnics)
5391 bnxt_hwrm_cmd_hdr_init(bp, req, HWRM_FUNC_VF_CFG, -1, -1);
5392 enables |= tx_rings ? FUNC_VF_CFG_REQ_ENABLES_NUM_TX_RINGS : 0;
5393 enables |= rx_rings ? FUNC_VF_CFG_REQ_ENABLES_NUM_RX_RINGS |
5394 FUNC_VF_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS : 0;
5395 enables |= stats ? FUNC_VF_CFG_REQ_ENABLES_NUM_STAT_CTXS : 0;
5396 if (bp->flags & BNXT_FLAG_CHIP_P5) {
5397 enables |= tx_rings + ring_grps ?
5398 FUNC_VF_CFG_REQ_ENABLES_NUM_CMPL_RINGS : 0;
5400 enables |= cp_rings ?
5401 FUNC_VF_CFG_REQ_ENABLES_NUM_CMPL_RINGS : 0;
5402 enables |= ring_grps ?
5403 FUNC_VF_CFG_REQ_ENABLES_NUM_HW_RING_GRPS : 0;
5405 enables |= vnics ? FUNC_VF_CFG_REQ_ENABLES_NUM_VNICS : 0;
5406 enables |= FUNC_VF_CFG_REQ_ENABLES_NUM_L2_CTXS;
5408 req->num_l2_ctxs = cpu_to_le16(BNXT_VF_MAX_L2_CTX);
5409 req->num_tx_rings = cpu_to_le16(tx_rings);
5410 req->num_rx_rings = cpu_to_le16(rx_rings);
5411 if (bp->flags & BNXT_FLAG_CHIP_P5) {
5412 req->num_cmpl_rings = cpu_to_le16(tx_rings + ring_grps);
5413 req->num_rsscos_ctxs = cpu_to_le16(DIV_ROUND_UP(ring_grps, 64));
5415 req->num_cmpl_rings = cpu_to_le16(cp_rings);
5416 req->num_hw_ring_grps = cpu_to_le16(ring_grps);
5417 req->num_rsscos_ctxs = cpu_to_le16(BNXT_VF_MAX_RSS_CTX);
5419 req->num_stat_ctxs = cpu_to_le16(stats);
5420 req->num_vnics = cpu_to_le16(vnics);
5422 req->enables = cpu_to_le32(enables);
5426 bnxt_hwrm_reserve_pf_rings(struct bnxt *bp, int tx_rings, int rx_rings,
5427 int ring_grps, int cp_rings, int stats, int vnics)
5429 struct hwrm_func_cfg_input req = {0};
5432 __bnxt_hwrm_reserve_pf_rings(bp, &req, tx_rings, rx_rings, ring_grps,
5433 cp_rings, stats, vnics);
5437 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5441 if (bp->hwrm_spec_code < 0x10601)
5442 bp->hw_resc.resv_tx_rings = tx_rings;
5444 rc = bnxt_hwrm_get_rings(bp);
5449 bnxt_hwrm_reserve_vf_rings(struct bnxt *bp, int tx_rings, int rx_rings,
5450 int ring_grps, int cp_rings, int stats, int vnics)
5452 struct hwrm_func_vf_cfg_input req = {0};
5455 if (!BNXT_NEW_RM(bp)) {
5456 bp->hw_resc.resv_tx_rings = tx_rings;
5460 __bnxt_hwrm_reserve_vf_rings(bp, &req, tx_rings, rx_rings, ring_grps,
5461 cp_rings, stats, vnics);
5462 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5466 rc = bnxt_hwrm_get_rings(bp);
5470 static int bnxt_hwrm_reserve_rings(struct bnxt *bp, int tx, int rx, int grp,
5471 int cp, int stat, int vnic)
5474 return bnxt_hwrm_reserve_pf_rings(bp, tx, rx, grp, cp, stat,
5477 return bnxt_hwrm_reserve_vf_rings(bp, tx, rx, grp, cp, stat,
5481 int bnxt_nq_rings_in_use(struct bnxt *bp)
5483 int cp = bp->cp_nr_rings;
5484 int ulp_msix, ulp_base;
5486 ulp_msix = bnxt_get_ulp_msix_num(bp);
5488 ulp_base = bnxt_get_ulp_msix_base(bp);
5490 if ((ulp_base + ulp_msix) > cp)
5491 cp = ulp_base + ulp_msix;
5496 static int bnxt_cp_rings_in_use(struct bnxt *bp)
5500 if (!(bp->flags & BNXT_FLAG_CHIP_P5))
5501 return bnxt_nq_rings_in_use(bp);
5503 cp = bp->tx_nr_rings + bp->rx_nr_rings;
5507 static int bnxt_get_func_stat_ctxs(struct bnxt *bp)
5509 return bp->cp_nr_rings + bnxt_get_ulp_stat_ctxs(bp);
5512 static bool bnxt_need_reserve_rings(struct bnxt *bp)
5514 struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
5515 int cp = bnxt_cp_rings_in_use(bp);
5516 int nq = bnxt_nq_rings_in_use(bp);
5517 int rx = bp->rx_nr_rings, stat;
5518 int vnic = 1, grp = rx;
5520 if (bp->hwrm_spec_code < 0x10601)
5523 if (hw_resc->resv_tx_rings != bp->tx_nr_rings)
5526 if ((bp->flags & BNXT_FLAG_RFS) && !(bp->flags & BNXT_FLAG_CHIP_P5))
5528 if (bp->flags & BNXT_FLAG_AGG_RINGS)
5530 stat = bnxt_get_func_stat_ctxs(bp);
5531 if (BNXT_NEW_RM(bp) &&
5532 (hw_resc->resv_rx_rings != rx || hw_resc->resv_cp_rings != cp ||
5533 hw_resc->resv_vnics != vnic || hw_resc->resv_stat_ctxs != stat ||
5534 (hw_resc->resv_hw_ring_grps != grp &&
5535 !(bp->flags & BNXT_FLAG_CHIP_P5))))
5537 if ((bp->flags & BNXT_FLAG_CHIP_P5) && BNXT_PF(bp) &&
5538 hw_resc->resv_irqs != nq)
5543 static int __bnxt_reserve_rings(struct bnxt *bp)
5545 struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
5546 int cp = bnxt_nq_rings_in_use(bp);
5547 int tx = bp->tx_nr_rings;
5548 int rx = bp->rx_nr_rings;
5549 int grp, rx_rings, rc;
5553 if (!bnxt_need_reserve_rings(bp))
5556 if (bp->flags & BNXT_FLAG_SHARED_RINGS)
5558 if ((bp->flags & BNXT_FLAG_RFS) && !(bp->flags & BNXT_FLAG_CHIP_P5))
5560 if (bp->flags & BNXT_FLAG_AGG_RINGS)
5562 grp = bp->rx_nr_rings;
5563 stat = bnxt_get_func_stat_ctxs(bp);
5565 rc = bnxt_hwrm_reserve_rings(bp, tx, rx, grp, cp, stat, vnic);
5569 tx = hw_resc->resv_tx_rings;
5570 if (BNXT_NEW_RM(bp)) {
5571 rx = hw_resc->resv_rx_rings;
5572 cp = hw_resc->resv_irqs;
5573 grp = hw_resc->resv_hw_ring_grps;
5574 vnic = hw_resc->resv_vnics;
5575 stat = hw_resc->resv_stat_ctxs;
5579 if (bp->flags & BNXT_FLAG_AGG_RINGS) {
5583 if (netif_running(bp->dev))
5586 bp->flags &= ~BNXT_FLAG_AGG_RINGS;
5587 bp->flags |= BNXT_FLAG_NO_AGG_RINGS;
5588 bp->dev->hw_features &= ~NETIF_F_LRO;
5589 bp->dev->features &= ~NETIF_F_LRO;
5590 bnxt_set_ring_params(bp);
5593 rx_rings = min_t(int, rx_rings, grp);
5594 cp = min_t(int, cp, bp->cp_nr_rings);
5595 if (stat > bnxt_get_ulp_stat_ctxs(bp))
5596 stat -= bnxt_get_ulp_stat_ctxs(bp);
5597 cp = min_t(int, cp, stat);
5598 rc = bnxt_trim_rings(bp, &rx_rings, &tx, cp, sh);
5599 if (bp->flags & BNXT_FLAG_AGG_RINGS)
5601 cp = sh ? max_t(int, tx, rx_rings) : tx + rx_rings;
5602 bp->tx_nr_rings = tx;
5603 bp->rx_nr_rings = rx_rings;
5604 bp->cp_nr_rings = cp;
5606 if (!tx || !rx || !cp || !grp || !vnic || !stat)
5612 static int bnxt_hwrm_check_vf_rings(struct bnxt *bp, int tx_rings, int rx_rings,
5613 int ring_grps, int cp_rings, int stats,
5616 struct hwrm_func_vf_cfg_input req = {0};
5620 if (!BNXT_NEW_RM(bp))
5623 __bnxt_hwrm_reserve_vf_rings(bp, &req, tx_rings, rx_rings, ring_grps,
5624 cp_rings, stats, vnics);
5625 flags = FUNC_VF_CFG_REQ_FLAGS_TX_ASSETS_TEST |
5626 FUNC_VF_CFG_REQ_FLAGS_RX_ASSETS_TEST |
5627 FUNC_VF_CFG_REQ_FLAGS_CMPL_ASSETS_TEST |
5628 FUNC_VF_CFG_REQ_FLAGS_STAT_CTX_ASSETS_TEST |
5629 FUNC_VF_CFG_REQ_FLAGS_VNIC_ASSETS_TEST |
5630 FUNC_VF_CFG_REQ_FLAGS_RSSCOS_CTX_ASSETS_TEST;
5631 if (!(bp->flags & BNXT_FLAG_CHIP_P5))
5632 flags |= FUNC_VF_CFG_REQ_FLAGS_RING_GRP_ASSETS_TEST;
5634 req.flags = cpu_to_le32(flags);
5635 rc = hwrm_send_message_silent(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5641 static int bnxt_hwrm_check_pf_rings(struct bnxt *bp, int tx_rings, int rx_rings,
5642 int ring_grps, int cp_rings, int stats,
5645 struct hwrm_func_cfg_input req = {0};
5649 __bnxt_hwrm_reserve_pf_rings(bp, &req, tx_rings, rx_rings, ring_grps,
5650 cp_rings, stats, vnics);
5651 flags = FUNC_CFG_REQ_FLAGS_TX_ASSETS_TEST;
5652 if (BNXT_NEW_RM(bp)) {
5653 flags |= FUNC_CFG_REQ_FLAGS_RX_ASSETS_TEST |
5654 FUNC_CFG_REQ_FLAGS_CMPL_ASSETS_TEST |
5655 FUNC_CFG_REQ_FLAGS_STAT_CTX_ASSETS_TEST |
5656 FUNC_CFG_REQ_FLAGS_VNIC_ASSETS_TEST;
5657 if (bp->flags & BNXT_FLAG_CHIP_P5)
5658 flags |= FUNC_CFG_REQ_FLAGS_RSSCOS_CTX_ASSETS_TEST |
5659 FUNC_CFG_REQ_FLAGS_NQ_ASSETS_TEST;
5661 flags |= FUNC_CFG_REQ_FLAGS_RING_GRP_ASSETS_TEST;
5664 req.flags = cpu_to_le32(flags);
5665 rc = hwrm_send_message_silent(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5671 static int bnxt_hwrm_check_rings(struct bnxt *bp, int tx_rings, int rx_rings,
5672 int ring_grps, int cp_rings, int stats,
5675 if (bp->hwrm_spec_code < 0x10801)
5679 return bnxt_hwrm_check_pf_rings(bp, tx_rings, rx_rings,
5680 ring_grps, cp_rings, stats,
5683 return bnxt_hwrm_check_vf_rings(bp, tx_rings, rx_rings, ring_grps,
5684 cp_rings, stats, vnics);
5687 static void bnxt_hwrm_coal_params_qcaps(struct bnxt *bp)
5689 struct hwrm_ring_aggint_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
5690 struct bnxt_coal_cap *coal_cap = &bp->coal_cap;
5691 struct hwrm_ring_aggint_qcaps_input req = {0};
5694 coal_cap->cmpl_params = BNXT_LEGACY_COAL_CMPL_PARAMS;
5695 coal_cap->num_cmpl_dma_aggr_max = 63;
5696 coal_cap->num_cmpl_dma_aggr_during_int_max = 63;
5697 coal_cap->cmpl_aggr_dma_tmr_max = 65535;
5698 coal_cap->cmpl_aggr_dma_tmr_during_int_max = 65535;
5699 coal_cap->int_lat_tmr_min_max = 65535;
5700 coal_cap->int_lat_tmr_max_max = 65535;
5701 coal_cap->num_cmpl_aggr_int_max = 65535;
5702 coal_cap->timer_units = 80;
5704 if (bp->hwrm_spec_code < 0x10902)
5707 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_AGGINT_QCAPS, -1, -1);
5708 mutex_lock(&bp->hwrm_cmd_lock);
5709 rc = _hwrm_send_message_silent(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5711 coal_cap->cmpl_params = le32_to_cpu(resp->cmpl_params);
5712 coal_cap->nq_params = le32_to_cpu(resp->nq_params);
5713 coal_cap->num_cmpl_dma_aggr_max =
5714 le16_to_cpu(resp->num_cmpl_dma_aggr_max);
5715 coal_cap->num_cmpl_dma_aggr_during_int_max =
5716 le16_to_cpu(resp->num_cmpl_dma_aggr_during_int_max);
5717 coal_cap->cmpl_aggr_dma_tmr_max =
5718 le16_to_cpu(resp->cmpl_aggr_dma_tmr_max);
5719 coal_cap->cmpl_aggr_dma_tmr_during_int_max =
5720 le16_to_cpu(resp->cmpl_aggr_dma_tmr_during_int_max);
5721 coal_cap->int_lat_tmr_min_max =
5722 le16_to_cpu(resp->int_lat_tmr_min_max);
5723 coal_cap->int_lat_tmr_max_max =
5724 le16_to_cpu(resp->int_lat_tmr_max_max);
5725 coal_cap->num_cmpl_aggr_int_max =
5726 le16_to_cpu(resp->num_cmpl_aggr_int_max);
5727 coal_cap->timer_units = le16_to_cpu(resp->timer_units);
5729 mutex_unlock(&bp->hwrm_cmd_lock);
5732 static u16 bnxt_usec_to_coal_tmr(struct bnxt *bp, u16 usec)
5734 struct bnxt_coal_cap *coal_cap = &bp->coal_cap;
5736 return usec * 1000 / coal_cap->timer_units;
5739 static void bnxt_hwrm_set_coal_params(struct bnxt *bp,
5740 struct bnxt_coal *hw_coal,
5741 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *req)
5743 struct bnxt_coal_cap *coal_cap = &bp->coal_cap;
5744 u32 cmpl_params = coal_cap->cmpl_params;
5745 u16 val, tmr, max, flags = 0;
5747 max = hw_coal->bufs_per_record * 128;
5748 if (hw_coal->budget)
5749 max = hw_coal->bufs_per_record * hw_coal->budget;
5750 max = min_t(u16, max, coal_cap->num_cmpl_aggr_int_max);
5752 val = clamp_t(u16, hw_coal->coal_bufs, 1, max);
5753 req->num_cmpl_aggr_int = cpu_to_le16(val);
5755 val = min_t(u16, val, coal_cap->num_cmpl_dma_aggr_max);
5756 req->num_cmpl_dma_aggr = cpu_to_le16(val);
5758 val = clamp_t(u16, hw_coal->coal_bufs_irq, 1,
5759 coal_cap->num_cmpl_dma_aggr_during_int_max);
5760 req->num_cmpl_dma_aggr_during_int = cpu_to_le16(val);
5762 tmr = bnxt_usec_to_coal_tmr(bp, hw_coal->coal_ticks);
5763 tmr = clamp_t(u16, tmr, 1, coal_cap->int_lat_tmr_max_max);
5764 req->int_lat_tmr_max = cpu_to_le16(tmr);
5766 /* min timer set to 1/2 of interrupt timer */
5767 if (cmpl_params & RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_INT_LAT_TMR_MIN) {
5769 val = clamp_t(u16, val, 1, coal_cap->int_lat_tmr_min_max);
5770 req->int_lat_tmr_min = cpu_to_le16(val);
5771 req->enables |= cpu_to_le16(BNXT_COAL_CMPL_MIN_TMR_ENABLE);
5774 /* buf timer set to 1/4 of interrupt timer */
5775 val = clamp_t(u16, tmr / 4, 1, coal_cap->cmpl_aggr_dma_tmr_max);
5776 req->cmpl_aggr_dma_tmr = cpu_to_le16(val);
5779 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_DMA_AGGR_DURING_INT) {
5780 tmr = bnxt_usec_to_coal_tmr(bp, hw_coal->coal_ticks_irq);
5781 val = clamp_t(u16, tmr, 1,
5782 coal_cap->cmpl_aggr_dma_tmr_during_int_max);
5783 req->cmpl_aggr_dma_tmr_during_int = cpu_to_le16(tmr);
5785 cpu_to_le16(BNXT_COAL_CMPL_AGGR_TMR_DURING_INT_ENABLE);
5788 if (cmpl_params & RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_TIMER_RESET)
5789 flags |= RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET;
5790 if ((cmpl_params & RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_RING_IDLE) &&
5791 hw_coal->idle_thresh && hw_coal->coal_ticks < hw_coal->idle_thresh)
5792 flags |= RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_RING_IDLE;
5793 req->flags = cpu_to_le16(flags);
5794 req->enables |= cpu_to_le16(BNXT_COAL_CMPL_ENABLES);
5797 /* Caller holds bp->hwrm_cmd_lock */
5798 static int __bnxt_hwrm_set_coal_nq(struct bnxt *bp, struct bnxt_napi *bnapi,
5799 struct bnxt_coal *hw_coal)
5801 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req = {0};
5802 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
5803 struct bnxt_coal_cap *coal_cap = &bp->coal_cap;
5804 u32 nq_params = coal_cap->nq_params;
5807 if (!(nq_params & RING_AGGINT_QCAPS_RESP_NQ_PARAMS_INT_LAT_TMR_MIN))
5810 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS,
5812 req.ring_id = cpu_to_le16(cpr->cp_ring_struct.fw_ring_id);
5814 cpu_to_le16(RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_IS_NQ);
5816 tmr = bnxt_usec_to_coal_tmr(bp, hw_coal->coal_ticks) / 2;
5817 tmr = clamp_t(u16, tmr, 1, coal_cap->int_lat_tmr_min_max);
5818 req.int_lat_tmr_min = cpu_to_le16(tmr);
5819 req.enables |= cpu_to_le16(BNXT_COAL_CMPL_MIN_TMR_ENABLE);
5820 return _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5823 int bnxt_hwrm_set_ring_coal(struct bnxt *bp, struct bnxt_napi *bnapi)
5825 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req_rx = {0};
5826 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
5827 struct bnxt_coal coal;
5829 /* Tick values in micro seconds.
5830 * 1 coal_buf x bufs_per_record = 1 completion record.
5832 memcpy(&coal, &bp->rx_coal, sizeof(struct bnxt_coal));
5834 coal.coal_ticks = cpr->rx_ring_coal.coal_ticks;
5835 coal.coal_bufs = cpr->rx_ring_coal.coal_bufs;
5837 if (!bnapi->rx_ring)
5840 bnxt_hwrm_cmd_hdr_init(bp, &req_rx,
5841 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS, -1, -1);
5843 bnxt_hwrm_set_coal_params(bp, &coal, &req_rx);
5845 req_rx.ring_id = cpu_to_le16(bnxt_cp_ring_for_rx(bp, bnapi->rx_ring));
5847 return hwrm_send_message(bp, &req_rx, sizeof(req_rx),
5851 int bnxt_hwrm_set_coal(struct bnxt *bp)
5854 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req_rx = {0},
5857 bnxt_hwrm_cmd_hdr_init(bp, &req_rx,
5858 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS, -1, -1);
5859 bnxt_hwrm_cmd_hdr_init(bp, &req_tx,
5860 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS, -1, -1);
5862 bnxt_hwrm_set_coal_params(bp, &bp->rx_coal, &req_rx);
5863 bnxt_hwrm_set_coal_params(bp, &bp->tx_coal, &req_tx);
5865 mutex_lock(&bp->hwrm_cmd_lock);
5866 for (i = 0; i < bp->cp_nr_rings; i++) {
5867 struct bnxt_napi *bnapi = bp->bnapi[i];
5868 struct bnxt_coal *hw_coal;
5872 if (!bnapi->rx_ring) {
5873 ring_id = bnxt_cp_ring_for_tx(bp, bnapi->tx_ring);
5876 ring_id = bnxt_cp_ring_for_rx(bp, bnapi->rx_ring);
5878 req->ring_id = cpu_to_le16(ring_id);
5880 rc = _hwrm_send_message(bp, req, sizeof(*req),
5885 if (!(bp->flags & BNXT_FLAG_CHIP_P5))
5888 if (bnapi->rx_ring && bnapi->tx_ring) {
5890 ring_id = bnxt_cp_ring_for_tx(bp, bnapi->tx_ring);
5891 req->ring_id = cpu_to_le16(ring_id);
5892 rc = _hwrm_send_message(bp, req, sizeof(*req),
5898 hw_coal = &bp->rx_coal;
5900 hw_coal = &bp->tx_coal;
5901 __bnxt_hwrm_set_coal_nq(bp, bnapi, hw_coal);
5903 mutex_unlock(&bp->hwrm_cmd_lock);
5907 static int bnxt_hwrm_stat_ctx_free(struct bnxt *bp)
5910 struct hwrm_stat_ctx_free_input req = {0};
5915 if (BNXT_CHIP_TYPE_NITRO_A0(bp))
5918 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_STAT_CTX_FREE, -1, -1);
5920 mutex_lock(&bp->hwrm_cmd_lock);
5921 for (i = 0; i < bp->cp_nr_rings; i++) {
5922 struct bnxt_napi *bnapi = bp->bnapi[i];
5923 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
5925 if (cpr->hw_stats_ctx_id != INVALID_STATS_CTX_ID) {
5926 req.stat_ctx_id = cpu_to_le32(cpr->hw_stats_ctx_id);
5928 rc = _hwrm_send_message(bp, &req, sizeof(req),
5933 cpr->hw_stats_ctx_id = INVALID_STATS_CTX_ID;
5936 mutex_unlock(&bp->hwrm_cmd_lock);
5940 static int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp)
5943 struct hwrm_stat_ctx_alloc_input req = {0};
5944 struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;
5946 if (BNXT_CHIP_TYPE_NITRO_A0(bp))
5949 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_STAT_CTX_ALLOC, -1, -1);
5951 req.update_period_ms = cpu_to_le32(bp->stats_coal_ticks / 1000);
5953 mutex_lock(&bp->hwrm_cmd_lock);
5954 for (i = 0; i < bp->cp_nr_rings; i++) {
5955 struct bnxt_napi *bnapi = bp->bnapi[i];
5956 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
5958 req.stats_dma_addr = cpu_to_le64(cpr->hw_stats_map);
5960 rc = _hwrm_send_message(bp, &req, sizeof(req),
5965 cpr->hw_stats_ctx_id = le32_to_cpu(resp->stat_ctx_id);
5967 bp->grp_info[i].fw_stats_ctx = cpr->hw_stats_ctx_id;
5969 mutex_unlock(&bp->hwrm_cmd_lock);
5973 static int bnxt_hwrm_func_qcfg(struct bnxt *bp)
5975 struct hwrm_func_qcfg_input req = {0};
5976 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
5980 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCFG, -1, -1);
5981 req.fid = cpu_to_le16(0xffff);
5982 mutex_lock(&bp->hwrm_cmd_lock);
5983 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5985 goto func_qcfg_exit;
5987 #ifdef CONFIG_BNXT_SRIOV
5989 struct bnxt_vf_info *vf = &bp->vf;
5991 vf->vlan = le16_to_cpu(resp->vlan) & VLAN_VID_MASK;
5994 flags = le16_to_cpu(resp->flags);
5995 if (flags & (FUNC_QCFG_RESP_FLAGS_FW_DCBX_AGENT_ENABLED |
5996 FUNC_QCFG_RESP_FLAGS_FW_LLDP_AGENT_ENABLED)) {
5997 bp->fw_cap |= BNXT_FW_CAP_LLDP_AGENT;
5998 if (flags & FUNC_QCFG_RESP_FLAGS_FW_DCBX_AGENT_ENABLED)
5999 bp->fw_cap |= BNXT_FW_CAP_DCBX_AGENT;
6001 if (BNXT_PF(bp) && (flags & FUNC_QCFG_RESP_FLAGS_MULTI_HOST))
6002 bp->flags |= BNXT_FLAG_MULTI_HOST;
6004 switch (resp->port_partition_type) {
6005 case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_0:
6006 case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_5:
6007 case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR2_0:
6008 bp->port_partition_type = resp->port_partition_type;
6011 if (bp->hwrm_spec_code < 0x10707 ||
6012 resp->evb_mode == FUNC_QCFG_RESP_EVB_MODE_VEB)
6013 bp->br_mode = BRIDGE_MODE_VEB;
6014 else if (resp->evb_mode == FUNC_QCFG_RESP_EVB_MODE_VEPA)
6015 bp->br_mode = BRIDGE_MODE_VEPA;
6017 bp->br_mode = BRIDGE_MODE_UNDEF;
6019 bp->max_mtu = le16_to_cpu(resp->max_mtu_configured);
6021 bp->max_mtu = BNXT_MAX_MTU;
6024 mutex_unlock(&bp->hwrm_cmd_lock);
6028 static int bnxt_hwrm_func_backing_store_qcaps(struct bnxt *bp)
6030 struct hwrm_func_backing_store_qcaps_input req = {0};
6031 struct hwrm_func_backing_store_qcaps_output *resp =
6032 bp->hwrm_cmd_resp_addr;
6035 if (bp->hwrm_spec_code < 0x10902 || BNXT_VF(bp) || bp->ctx)
6038 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_BACKING_STORE_QCAPS, -1, -1);
6039 mutex_lock(&bp->hwrm_cmd_lock);
6040 rc = _hwrm_send_message_silent(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6042 struct bnxt_ctx_pg_info *ctx_pg;
6043 struct bnxt_ctx_mem_info *ctx;
6046 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
6051 ctx_pg = kzalloc(sizeof(*ctx_pg) * (bp->max_q + 1), GFP_KERNEL);
6057 for (i = 0; i < bp->max_q + 1; i++, ctx_pg++)
6058 ctx->tqm_mem[i] = ctx_pg;
6061 ctx->qp_max_entries = le32_to_cpu(resp->qp_max_entries);
6062 ctx->qp_min_qp1_entries = le16_to_cpu(resp->qp_min_qp1_entries);
6063 ctx->qp_max_l2_entries = le16_to_cpu(resp->qp_max_l2_entries);
6064 ctx->qp_entry_size = le16_to_cpu(resp->qp_entry_size);
6065 ctx->srq_max_l2_entries = le16_to_cpu(resp->srq_max_l2_entries);
6066 ctx->srq_max_entries = le32_to_cpu(resp->srq_max_entries);
6067 ctx->srq_entry_size = le16_to_cpu(resp->srq_entry_size);
6068 ctx->cq_max_l2_entries = le16_to_cpu(resp->cq_max_l2_entries);
6069 ctx->cq_max_entries = le32_to_cpu(resp->cq_max_entries);
6070 ctx->cq_entry_size = le16_to_cpu(resp->cq_entry_size);
6071 ctx->vnic_max_vnic_entries =
6072 le16_to_cpu(resp->vnic_max_vnic_entries);
6073 ctx->vnic_max_ring_table_entries =
6074 le16_to_cpu(resp->vnic_max_ring_table_entries);
6075 ctx->vnic_entry_size = le16_to_cpu(resp->vnic_entry_size);
6076 ctx->stat_max_entries = le32_to_cpu(resp->stat_max_entries);
6077 ctx->stat_entry_size = le16_to_cpu(resp->stat_entry_size);
6078 ctx->tqm_entry_size = le16_to_cpu(resp->tqm_entry_size);
6079 ctx->tqm_min_entries_per_ring =
6080 le32_to_cpu(resp->tqm_min_entries_per_ring);
6081 ctx->tqm_max_entries_per_ring =
6082 le32_to_cpu(resp->tqm_max_entries_per_ring);
6083 ctx->tqm_entries_multiple = resp->tqm_entries_multiple;
6084 if (!ctx->tqm_entries_multiple)
6085 ctx->tqm_entries_multiple = 1;
6086 ctx->mrav_max_entries = le32_to_cpu(resp->mrav_max_entries);
6087 ctx->mrav_entry_size = le16_to_cpu(resp->mrav_entry_size);
6088 ctx->mrav_num_entries_units =
6089 le16_to_cpu(resp->mrav_num_entries_units);
6090 ctx->tim_entry_size = le16_to_cpu(resp->tim_entry_size);
6091 ctx->tim_max_entries = le32_to_cpu(resp->tim_max_entries);
6096 mutex_unlock(&bp->hwrm_cmd_lock);
6100 static void bnxt_hwrm_set_pg_attr(struct bnxt_ring_mem_info *rmem, u8 *pg_attr,
6105 if (BNXT_PAGE_SHIFT == 13)
6107 else if (BNXT_PAGE_SIZE == 16)
6111 if (rmem->depth >= 1) {
6112 if (rmem->depth == 2)
6116 *pg_dir = cpu_to_le64(rmem->pg_tbl_map);
6118 *pg_dir = cpu_to_le64(rmem->dma_arr[0]);
6122 #define FUNC_BACKING_STORE_CFG_REQ_DFLT_ENABLES \
6123 (FUNC_BACKING_STORE_CFG_REQ_ENABLES_QP | \
6124 FUNC_BACKING_STORE_CFG_REQ_ENABLES_SRQ | \
6125 FUNC_BACKING_STORE_CFG_REQ_ENABLES_CQ | \
6126 FUNC_BACKING_STORE_CFG_REQ_ENABLES_VNIC | \
6127 FUNC_BACKING_STORE_CFG_REQ_ENABLES_STAT)
6129 static int bnxt_hwrm_func_backing_store_cfg(struct bnxt *bp, u32 enables)
6131 struct hwrm_func_backing_store_cfg_input req = {0};
6132 struct bnxt_ctx_mem_info *ctx = bp->ctx;
6133 struct bnxt_ctx_pg_info *ctx_pg;
6134 __le32 *num_entries;
6144 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_BACKING_STORE_CFG, -1, -1);
6145 req.enables = cpu_to_le32(enables);
6147 if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_QP) {
6148 ctx_pg = &ctx->qp_mem;
6149 req.qp_num_entries = cpu_to_le32(ctx_pg->entries);
6150 req.qp_num_qp1_entries = cpu_to_le16(ctx->qp_min_qp1_entries);
6151 req.qp_num_l2_entries = cpu_to_le16(ctx->qp_max_l2_entries);
6152 req.qp_entry_size = cpu_to_le16(ctx->qp_entry_size);
6153 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
6154 &req.qpc_pg_size_qpc_lvl,
6157 if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_SRQ) {
6158 ctx_pg = &ctx->srq_mem;
6159 req.srq_num_entries = cpu_to_le32(ctx_pg->entries);
6160 req.srq_num_l2_entries = cpu_to_le16(ctx->srq_max_l2_entries);
6161 req.srq_entry_size = cpu_to_le16(ctx->srq_entry_size);
6162 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
6163 &req.srq_pg_size_srq_lvl,
6166 if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_CQ) {
6167 ctx_pg = &ctx->cq_mem;
6168 req.cq_num_entries = cpu_to_le32(ctx_pg->entries);
6169 req.cq_num_l2_entries = cpu_to_le16(ctx->cq_max_l2_entries);
6170 req.cq_entry_size = cpu_to_le16(ctx->cq_entry_size);
6171 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, &req.cq_pg_size_cq_lvl,
6174 if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_VNIC) {
6175 ctx_pg = &ctx->vnic_mem;
6176 req.vnic_num_vnic_entries =
6177 cpu_to_le16(ctx->vnic_max_vnic_entries);
6178 req.vnic_num_ring_table_entries =
6179 cpu_to_le16(ctx->vnic_max_ring_table_entries);
6180 req.vnic_entry_size = cpu_to_le16(ctx->vnic_entry_size);
6181 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
6182 &req.vnic_pg_size_vnic_lvl,
6183 &req.vnic_page_dir);
6185 if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_STAT) {
6186 ctx_pg = &ctx->stat_mem;
6187 req.stat_num_entries = cpu_to_le32(ctx->stat_max_entries);
6188 req.stat_entry_size = cpu_to_le16(ctx->stat_entry_size);
6189 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
6190 &req.stat_pg_size_stat_lvl,
6191 &req.stat_page_dir);
6193 if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_MRAV) {
6194 ctx_pg = &ctx->mrav_mem;
6195 req.mrav_num_entries = cpu_to_le32(ctx_pg->entries);
6196 if (ctx->mrav_num_entries_units)
6198 FUNC_BACKING_STORE_CFG_REQ_FLAGS_MRAV_RESERVATION_SPLIT;
6199 req.mrav_entry_size = cpu_to_le16(ctx->mrav_entry_size);
6200 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
6201 &req.mrav_pg_size_mrav_lvl,
6202 &req.mrav_page_dir);
6204 if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_TIM) {
6205 ctx_pg = &ctx->tim_mem;
6206 req.tim_num_entries = cpu_to_le32(ctx_pg->entries);
6207 req.tim_entry_size = cpu_to_le16(ctx->tim_entry_size);
6208 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
6209 &req.tim_pg_size_tim_lvl,
6212 for (i = 0, num_entries = &req.tqm_sp_num_entries,
6213 pg_attr = &req.tqm_sp_pg_size_tqm_sp_lvl,
6214 pg_dir = &req.tqm_sp_page_dir,
6215 ena = FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_SP;
6216 i < 9; i++, num_entries++, pg_attr++, pg_dir++, ena <<= 1) {
6217 if (!(enables & ena))
6220 req.tqm_entry_size = cpu_to_le16(ctx->tqm_entry_size);
6221 ctx_pg = ctx->tqm_mem[i];
6222 *num_entries = cpu_to_le32(ctx_pg->entries);
6223 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, pg_attr, pg_dir);
6225 req.flags = cpu_to_le32(flags);
6226 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6232 static int bnxt_alloc_ctx_mem_blk(struct bnxt *bp,
6233 struct bnxt_ctx_pg_info *ctx_pg)
6235 struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
6237 rmem->page_size = BNXT_PAGE_SIZE;
6238 rmem->pg_arr = ctx_pg->ctx_pg_arr;
6239 rmem->dma_arr = ctx_pg->ctx_dma_arr;
6240 rmem->flags = BNXT_RMEM_VALID_PTE_FLAG;
6241 if (rmem->depth >= 1)
6242 rmem->flags |= BNXT_RMEM_USE_FULL_PAGE_FLAG;
6243 return bnxt_alloc_ring(bp, rmem);
6246 static int bnxt_alloc_ctx_pg_tbls(struct bnxt *bp,
6247 struct bnxt_ctx_pg_info *ctx_pg, u32 mem_size,
6250 struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
6256 ctx_pg->nr_pages = DIV_ROUND_UP(mem_size, BNXT_PAGE_SIZE);
6257 if (ctx_pg->nr_pages > MAX_CTX_TOTAL_PAGES) {
6258 ctx_pg->nr_pages = 0;
6261 if (ctx_pg->nr_pages > MAX_CTX_PAGES || depth > 1) {
6265 ctx_pg->ctx_pg_tbl = kcalloc(MAX_CTX_PAGES, sizeof(ctx_pg),
6267 if (!ctx_pg->ctx_pg_tbl)
6269 nr_tbls = DIV_ROUND_UP(ctx_pg->nr_pages, MAX_CTX_PAGES);
6270 rmem->nr_pages = nr_tbls;
6271 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg);
6274 for (i = 0; i < nr_tbls; i++) {
6275 struct bnxt_ctx_pg_info *pg_tbl;
6277 pg_tbl = kzalloc(sizeof(*pg_tbl), GFP_KERNEL);
6280 ctx_pg->ctx_pg_tbl[i] = pg_tbl;
6281 rmem = &pg_tbl->ring_mem;
6282 rmem->pg_tbl = ctx_pg->ctx_pg_arr[i];
6283 rmem->pg_tbl_map = ctx_pg->ctx_dma_arr[i];
6285 rmem->nr_pages = MAX_CTX_PAGES;
6286 if (i == (nr_tbls - 1)) {
6287 int rem = ctx_pg->nr_pages % MAX_CTX_PAGES;
6290 rmem->nr_pages = rem;
6292 rc = bnxt_alloc_ctx_mem_blk(bp, pg_tbl);
6297 rmem->nr_pages = DIV_ROUND_UP(mem_size, BNXT_PAGE_SIZE);
6298 if (rmem->nr_pages > 1 || depth)
6300 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg);
6305 static void bnxt_free_ctx_pg_tbls(struct bnxt *bp,
6306 struct bnxt_ctx_pg_info *ctx_pg)
6308 struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
6310 if (rmem->depth > 1 || ctx_pg->nr_pages > MAX_CTX_PAGES ||
6311 ctx_pg->ctx_pg_tbl) {
6312 int i, nr_tbls = rmem->nr_pages;
6314 for (i = 0; i < nr_tbls; i++) {
6315 struct bnxt_ctx_pg_info *pg_tbl;
6316 struct bnxt_ring_mem_info *rmem2;
6318 pg_tbl = ctx_pg->ctx_pg_tbl[i];
6321 rmem2 = &pg_tbl->ring_mem;
6322 bnxt_free_ring(bp, rmem2);
6323 ctx_pg->ctx_pg_arr[i] = NULL;
6325 ctx_pg->ctx_pg_tbl[i] = NULL;
6327 kfree(ctx_pg->ctx_pg_tbl);
6328 ctx_pg->ctx_pg_tbl = NULL;
6330 bnxt_free_ring(bp, rmem);
6331 ctx_pg->nr_pages = 0;
6334 static void bnxt_free_ctx_mem(struct bnxt *bp)
6336 struct bnxt_ctx_mem_info *ctx = bp->ctx;
6342 if (ctx->tqm_mem[0]) {
6343 for (i = 0; i < bp->max_q + 1; i++)
6344 bnxt_free_ctx_pg_tbls(bp, ctx->tqm_mem[i]);
6345 kfree(ctx->tqm_mem[0]);
6346 ctx->tqm_mem[0] = NULL;
6349 bnxt_free_ctx_pg_tbls(bp, &ctx->tim_mem);
6350 bnxt_free_ctx_pg_tbls(bp, &ctx->mrav_mem);
6351 bnxt_free_ctx_pg_tbls(bp, &ctx->stat_mem);
6352 bnxt_free_ctx_pg_tbls(bp, &ctx->vnic_mem);
6353 bnxt_free_ctx_pg_tbls(bp, &ctx->cq_mem);
6354 bnxt_free_ctx_pg_tbls(bp, &ctx->srq_mem);
6355 bnxt_free_ctx_pg_tbls(bp, &ctx->qp_mem);
6356 ctx->flags &= ~BNXT_CTX_FLAG_INITED;
6359 static int bnxt_alloc_ctx_mem(struct bnxt *bp)
6361 struct bnxt_ctx_pg_info *ctx_pg;
6362 struct bnxt_ctx_mem_info *ctx;
6363 u32 mem_size, ena, entries;
6370 rc = bnxt_hwrm_func_backing_store_qcaps(bp);
6372 netdev_err(bp->dev, "Failed querying context mem capability, rc = %d.\n",
6377 if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED))
6380 if (bp->flags & BNXT_FLAG_ROCE_CAP) {
6386 ctx_pg = &ctx->qp_mem;
6387 ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries +
6389 mem_size = ctx->qp_entry_size * ctx_pg->entries;
6390 rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, pg_lvl);
6394 ctx_pg = &ctx->srq_mem;
6395 ctx_pg->entries = ctx->srq_max_l2_entries + extra_srqs;
6396 mem_size = ctx->srq_entry_size * ctx_pg->entries;
6397 rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, pg_lvl);
6401 ctx_pg = &ctx->cq_mem;
6402 ctx_pg->entries = ctx->cq_max_l2_entries + extra_qps * 2;
6403 mem_size = ctx->cq_entry_size * ctx_pg->entries;
6404 rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, pg_lvl);
6408 ctx_pg = &ctx->vnic_mem;
6409 ctx_pg->entries = ctx->vnic_max_vnic_entries +
6410 ctx->vnic_max_ring_table_entries;
6411 mem_size = ctx->vnic_entry_size * ctx_pg->entries;
6412 rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, 1);
6416 ctx_pg = &ctx->stat_mem;
6417 ctx_pg->entries = ctx->stat_max_entries;
6418 mem_size = ctx->stat_entry_size * ctx_pg->entries;
6419 rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, 1);
6424 if (!(bp->flags & BNXT_FLAG_ROCE_CAP))
6427 ctx_pg = &ctx->mrav_mem;
6428 /* 128K extra is needed to accommodate static AH context
6429 * allocation by f/w.
6431 num_mr = 1024 * 256;
6432 num_ah = 1024 * 128;
6433 ctx_pg->entries = num_mr + num_ah;
6434 mem_size = ctx->mrav_entry_size * ctx_pg->entries;
6435 rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, 2);
6438 ena = FUNC_BACKING_STORE_CFG_REQ_ENABLES_MRAV;
6439 if (ctx->mrav_num_entries_units)
6441 ((num_mr / ctx->mrav_num_entries_units) << 16) |
6442 (num_ah / ctx->mrav_num_entries_units);
6444 ctx_pg = &ctx->tim_mem;
6445 ctx_pg->entries = ctx->qp_mem.entries;
6446 mem_size = ctx->tim_entry_size * ctx_pg->entries;
6447 rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, 1);
6450 ena |= FUNC_BACKING_STORE_CFG_REQ_ENABLES_TIM;
6453 entries = ctx->qp_max_l2_entries + extra_qps;
6454 entries = roundup(entries, ctx->tqm_entries_multiple);
6455 entries = clamp_t(u32, entries, ctx->tqm_min_entries_per_ring,
6456 ctx->tqm_max_entries_per_ring);
6457 for (i = 0; i < bp->max_q + 1; i++) {
6458 ctx_pg = ctx->tqm_mem[i];
6459 ctx_pg->entries = entries;
6460 mem_size = ctx->tqm_entry_size * entries;
6461 rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, 1);
6464 ena |= FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_SP << i;
6466 ena |= FUNC_BACKING_STORE_CFG_REQ_DFLT_ENABLES;
6467 rc = bnxt_hwrm_func_backing_store_cfg(bp, ena);
6469 netdev_err(bp->dev, "Failed configuring context mem, rc = %d.\n",
6472 ctx->flags |= BNXT_CTX_FLAG_INITED;
6477 int bnxt_hwrm_func_resc_qcaps(struct bnxt *bp, bool all)
6479 struct hwrm_func_resource_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
6480 struct hwrm_func_resource_qcaps_input req = {0};
6481 struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
6484 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_RESOURCE_QCAPS, -1, -1);
6485 req.fid = cpu_to_le16(0xffff);
6487 mutex_lock(&bp->hwrm_cmd_lock);
6488 rc = _hwrm_send_message_silent(bp, &req, sizeof(req),
6492 goto hwrm_func_resc_qcaps_exit;
6495 hw_resc->max_tx_sch_inputs = le16_to_cpu(resp->max_tx_scheduler_inputs);
6497 goto hwrm_func_resc_qcaps_exit;
6499 hw_resc->min_rsscos_ctxs = le16_to_cpu(resp->min_rsscos_ctx);
6500 hw_resc->max_rsscos_ctxs = le16_to_cpu(resp->max_rsscos_ctx);
6501 hw_resc->min_cp_rings = le16_to_cpu(resp->min_cmpl_rings);
6502 hw_resc->max_cp_rings = le16_to_cpu(resp->max_cmpl_rings);
6503 hw_resc->min_tx_rings = le16_to_cpu(resp->min_tx_rings);
6504 hw_resc->max_tx_rings = le16_to_cpu(resp->max_tx_rings);
6505 hw_resc->min_rx_rings = le16_to_cpu(resp->min_rx_rings);
6506 hw_resc->max_rx_rings = le16_to_cpu(resp->max_rx_rings);
6507 hw_resc->min_hw_ring_grps = le16_to_cpu(resp->min_hw_ring_grps);
6508 hw_resc->max_hw_ring_grps = le16_to_cpu(resp->max_hw_ring_grps);
6509 hw_resc->min_l2_ctxs = le16_to_cpu(resp->min_l2_ctxs);
6510 hw_resc->max_l2_ctxs = le16_to_cpu(resp->max_l2_ctxs);
6511 hw_resc->min_vnics = le16_to_cpu(resp->min_vnics);
6512 hw_resc->max_vnics = le16_to_cpu(resp->max_vnics);
6513 hw_resc->min_stat_ctxs = le16_to_cpu(resp->min_stat_ctx);
6514 hw_resc->max_stat_ctxs = le16_to_cpu(resp->max_stat_ctx);
6516 if (bp->flags & BNXT_FLAG_CHIP_P5) {
6517 u16 max_msix = le16_to_cpu(resp->max_msix);
6519 hw_resc->max_nqs = max_msix;
6520 hw_resc->max_hw_ring_grps = hw_resc->max_rx_rings;
6524 struct bnxt_pf_info *pf = &bp->pf;
6526 pf->vf_resv_strategy =
6527 le16_to_cpu(resp->vf_reservation_strategy);
6528 if (pf->vf_resv_strategy > BNXT_VF_RESV_STRATEGY_MINIMAL_STATIC)
6529 pf->vf_resv_strategy = BNXT_VF_RESV_STRATEGY_MAXIMAL;
6531 hwrm_func_resc_qcaps_exit:
6532 mutex_unlock(&bp->hwrm_cmd_lock);
6536 static int __bnxt_hwrm_func_qcaps(struct bnxt *bp)
6539 struct hwrm_func_qcaps_input req = {0};
6540 struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
6541 struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
6544 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCAPS, -1, -1);
6545 req.fid = cpu_to_le16(0xffff);
6547 mutex_lock(&bp->hwrm_cmd_lock);
6548 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6550 goto hwrm_func_qcaps_exit;
6552 flags = le32_to_cpu(resp->flags);
6553 if (flags & FUNC_QCAPS_RESP_FLAGS_ROCE_V1_SUPPORTED)
6554 bp->flags |= BNXT_FLAG_ROCEV1_CAP;
6555 if (flags & FUNC_QCAPS_RESP_FLAGS_ROCE_V2_SUPPORTED)
6556 bp->flags |= BNXT_FLAG_ROCEV2_CAP;
6557 if (flags & FUNC_QCAPS_RESP_FLAGS_PCIE_STATS_SUPPORTED)
6558 bp->fw_cap |= BNXT_FW_CAP_PCIE_STATS_SUPPORTED;
6559 if (flags & FUNC_QCAPS_RESP_FLAGS_EXT_STATS_SUPPORTED)
6560 bp->fw_cap |= BNXT_FW_CAP_EXT_STATS_SUPPORTED;
6562 bp->tx_push_thresh = 0;
6563 if (flags & FUNC_QCAPS_RESP_FLAGS_PUSH_MODE_SUPPORTED)
6564 bp->tx_push_thresh = BNXT_TX_PUSH_THRESH;
6566 hw_resc->max_rsscos_ctxs = le16_to_cpu(resp->max_rsscos_ctx);
6567 hw_resc->max_cp_rings = le16_to_cpu(resp->max_cmpl_rings);
6568 hw_resc->max_tx_rings = le16_to_cpu(resp->max_tx_rings);
6569 hw_resc->max_rx_rings = le16_to_cpu(resp->max_rx_rings);
6570 hw_resc->max_hw_ring_grps = le32_to_cpu(resp->max_hw_ring_grps);
6571 if (!hw_resc->max_hw_ring_grps)
6572 hw_resc->max_hw_ring_grps = hw_resc->max_tx_rings;
6573 hw_resc->max_l2_ctxs = le16_to_cpu(resp->max_l2_ctxs);
6574 hw_resc->max_vnics = le16_to_cpu(resp->max_vnics);
6575 hw_resc->max_stat_ctxs = le16_to_cpu(resp->max_stat_ctx);
6578 struct bnxt_pf_info *pf = &bp->pf;
6580 pf->fw_fid = le16_to_cpu(resp->fid);
6581 pf->port_id = le16_to_cpu(resp->port_id);
6582 bp->dev->dev_port = pf->port_id;
6583 memcpy(pf->mac_addr, resp->mac_address, ETH_ALEN);
6584 pf->first_vf_id = le16_to_cpu(resp->first_vf_id);
6585 pf->max_vfs = le16_to_cpu(resp->max_vfs);
6586 pf->max_encap_records = le32_to_cpu(resp->max_encap_records);
6587 pf->max_decap_records = le32_to_cpu(resp->max_decap_records);
6588 pf->max_tx_em_flows = le32_to_cpu(resp->max_tx_em_flows);
6589 pf->max_tx_wm_flows = le32_to_cpu(resp->max_tx_wm_flows);
6590 pf->max_rx_em_flows = le32_to_cpu(resp->max_rx_em_flows);
6591 pf->max_rx_wm_flows = le32_to_cpu(resp->max_rx_wm_flows);
6592 if (flags & FUNC_QCAPS_RESP_FLAGS_WOL_MAGICPKT_SUPPORTED)
6593 bp->flags |= BNXT_FLAG_WOL_CAP;
6595 #ifdef CONFIG_BNXT_SRIOV
6596 struct bnxt_vf_info *vf = &bp->vf;
6598 vf->fw_fid = le16_to_cpu(resp->fid);
6599 memcpy(vf->mac_addr, resp->mac_address, ETH_ALEN);
6603 hwrm_func_qcaps_exit:
6604 mutex_unlock(&bp->hwrm_cmd_lock);
6608 static int bnxt_hwrm_queue_qportcfg(struct bnxt *bp);
6610 static int bnxt_hwrm_func_qcaps(struct bnxt *bp)
6614 rc = __bnxt_hwrm_func_qcaps(bp);
6617 rc = bnxt_hwrm_queue_qportcfg(bp);
6619 netdev_err(bp->dev, "hwrm query qportcfg failure rc: %d\n", rc);
6622 if (bp->hwrm_spec_code >= 0x10803) {
6623 rc = bnxt_alloc_ctx_mem(bp);
6626 rc = bnxt_hwrm_func_resc_qcaps(bp, true);
6628 bp->fw_cap |= BNXT_FW_CAP_NEW_RM;
6633 static int bnxt_hwrm_cfa_adv_flow_mgnt_qcaps(struct bnxt *bp)
6635 struct hwrm_cfa_adv_flow_mgnt_qcaps_input req = {0};
6636 struct hwrm_cfa_adv_flow_mgnt_qcaps_output *resp;
6640 if (!(bp->fw_cap & BNXT_FW_CAP_CFA_ADV_FLOW))
6643 resp = bp->hwrm_cmd_resp_addr;
6644 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_ADV_FLOW_MGNT_QCAPS, -1, -1);
6646 mutex_lock(&bp->hwrm_cmd_lock);
6647 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6649 goto hwrm_cfa_adv_qcaps_exit;
6651 flags = le32_to_cpu(resp->flags);
6653 CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_RFS_RING_TBL_IDX_SUPPORTED)
6654 bp->fw_cap |= BNXT_FW_CAP_CFA_RFS_RING_TBL_IDX;
6656 hwrm_cfa_adv_qcaps_exit:
6657 mutex_unlock(&bp->hwrm_cmd_lock);
6661 static int bnxt_hwrm_func_reset(struct bnxt *bp)
6663 struct hwrm_func_reset_input req = {0};
6665 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_RESET, -1, -1);
6668 return hwrm_send_message(bp, &req, sizeof(req), HWRM_RESET_TIMEOUT);
6671 static int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
6674 struct hwrm_queue_qportcfg_input req = {0};
6675 struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
6679 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_QUEUE_QPORTCFG, -1, -1);
6681 mutex_lock(&bp->hwrm_cmd_lock);
6682 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6686 if (!resp->max_configurable_queues) {
6690 bp->max_tc = resp->max_configurable_queues;
6691 bp->max_lltc = resp->max_configurable_lossless_queues;
6692 if (bp->max_tc > BNXT_MAX_QUEUE)
6693 bp->max_tc = BNXT_MAX_QUEUE;
6695 no_rdma = !(bp->flags & BNXT_FLAG_ROCE_CAP);
6696 qptr = &resp->queue_id0;
6697 for (i = 0, j = 0; i < bp->max_tc; i++) {
6698 bp->q_info[j].queue_id = *qptr;
6699 bp->q_ids[i] = *qptr++;
6700 bp->q_info[j].queue_profile = *qptr++;
6701 bp->tc_to_qidx[j] = j;
6702 if (!BNXT_CNPQ(bp->q_info[j].queue_profile) ||
6703 (no_rdma && BNXT_PF(bp)))
6706 bp->max_q = bp->max_tc;
6707 bp->max_tc = max_t(u8, j, 1);
6709 if (resp->queue_cfg_info & QUEUE_QPORTCFG_RESP_QUEUE_CFG_INFO_ASYM_CFG)
6712 if (bp->max_lltc > bp->max_tc)
6713 bp->max_lltc = bp->max_tc;
6716 mutex_unlock(&bp->hwrm_cmd_lock);
6720 static int bnxt_hwrm_ver_get(struct bnxt *bp)
6723 struct hwrm_ver_get_input req = {0};
6724 struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
6727 bp->hwrm_max_req_len = HWRM_MAX_REQ_LEN;
6728 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VER_GET, -1, -1);
6729 req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
6730 req.hwrm_intf_min = HWRM_VERSION_MINOR;
6731 req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
6732 mutex_lock(&bp->hwrm_cmd_lock);
6733 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6735 goto hwrm_ver_get_exit;
6737 memcpy(&bp->ver_resp, resp, sizeof(struct hwrm_ver_get_output));
6739 bp->hwrm_spec_code = resp->hwrm_intf_maj_8b << 16 |
6740 resp->hwrm_intf_min_8b << 8 |
6741 resp->hwrm_intf_upd_8b;
6742 if (resp->hwrm_intf_maj_8b < 1) {
6743 netdev_warn(bp->dev, "HWRM interface %d.%d.%d is older than 1.0.0.\n",
6744 resp->hwrm_intf_maj_8b, resp->hwrm_intf_min_8b,
6745 resp->hwrm_intf_upd_8b);
6746 netdev_warn(bp->dev, "Please update firmware with HWRM interface 1.0.0 or newer.\n");
6748 snprintf(bp->fw_ver_str, BC_HWRM_STR_LEN, "%d.%d.%d.%d",
6749 resp->hwrm_fw_maj_8b, resp->hwrm_fw_min_8b,
6750 resp->hwrm_fw_bld_8b, resp->hwrm_fw_rsvd_8b);
6752 if (strlen(resp->active_pkg_name)) {
6753 int fw_ver_len = strlen(bp->fw_ver_str);
6755 snprintf(bp->fw_ver_str + fw_ver_len,
6756 FW_VER_STR_LEN - fw_ver_len - 1, "/pkg %s",
6757 resp->active_pkg_name);
6758 bp->fw_cap |= BNXT_FW_CAP_PKG_VER;
6761 bp->hwrm_cmd_timeout = le16_to_cpu(resp->def_req_timeout);
6762 if (!bp->hwrm_cmd_timeout)
6763 bp->hwrm_cmd_timeout = DFLT_HWRM_CMD_TIMEOUT;
6765 if (resp->hwrm_intf_maj_8b >= 1) {
6766 bp->hwrm_max_req_len = le16_to_cpu(resp->max_req_win_len);
6767 bp->hwrm_max_ext_req_len = le16_to_cpu(resp->max_ext_req_len);
6769 if (bp->hwrm_max_ext_req_len < HWRM_MAX_REQ_LEN)
6770 bp->hwrm_max_ext_req_len = HWRM_MAX_REQ_LEN;
6772 bp->chip_num = le16_to_cpu(resp->chip_num);
6773 if (bp->chip_num == CHIP_NUM_58700 && !resp->chip_rev &&
6775 bp->flags |= BNXT_FLAG_CHIP_NITRO_A0;
6777 dev_caps_cfg = le32_to_cpu(resp->dev_caps_cfg);
6778 if ((dev_caps_cfg & VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
6779 (dev_caps_cfg & VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_REQUIRED))
6780 bp->fw_cap |= BNXT_FW_CAP_SHORT_CMD;
6782 if (dev_caps_cfg & VER_GET_RESP_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED)
6783 bp->fw_cap |= BNXT_FW_CAP_KONG_MB_CHNL;
6786 VER_GET_RESP_DEV_CAPS_CFG_FLOW_HANDLE_64BIT_SUPPORTED)
6787 bp->fw_cap |= BNXT_FW_CAP_OVS_64BIT_HANDLE;
6790 VER_GET_RESP_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED)
6791 bp->fw_cap |= BNXT_FW_CAP_TRUSTED_VF;
6794 VER_GET_RESP_DEV_CAPS_CFG_CFA_ADV_FLOW_MGNT_SUPPORTED)
6795 bp->fw_cap |= BNXT_FW_CAP_CFA_ADV_FLOW;
6798 mutex_unlock(&bp->hwrm_cmd_lock);
6802 int bnxt_hwrm_fw_set_time(struct bnxt *bp)
6804 struct hwrm_fw_set_time_input req = {0};
6806 time64_t now = ktime_get_real_seconds();
6808 if ((BNXT_VF(bp) && bp->hwrm_spec_code < 0x10901) ||
6809 bp->hwrm_spec_code < 0x10400)
6812 time64_to_tm(now, 0, &tm);
6813 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FW_SET_TIME, -1, -1);
6814 req.year = cpu_to_le16(1900 + tm.tm_year);
6815 req.month = 1 + tm.tm_mon;
6816 req.day = tm.tm_mday;
6817 req.hour = tm.tm_hour;
6818 req.minute = tm.tm_min;
6819 req.second = tm.tm_sec;
6820 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6823 static int bnxt_hwrm_port_qstats(struct bnxt *bp)
6826 struct bnxt_pf_info *pf = &bp->pf;
6827 struct hwrm_port_qstats_input req = {0};
6829 if (!(bp->flags & BNXT_FLAG_PORT_STATS))
6832 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_QSTATS, -1, -1);
6833 req.port_id = cpu_to_le16(pf->port_id);
6834 req.tx_stat_host_addr = cpu_to_le64(bp->hw_tx_port_stats_map);
6835 req.rx_stat_host_addr = cpu_to_le64(bp->hw_rx_port_stats_map);
6836 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6840 static int bnxt_hwrm_port_qstats_ext(struct bnxt *bp)
6842 struct hwrm_port_qstats_ext_output *resp = bp->hwrm_cmd_resp_addr;
6843 struct hwrm_queue_pri2cos_qcfg_input req2 = {0};
6844 struct hwrm_port_qstats_ext_input req = {0};
6845 struct bnxt_pf_info *pf = &bp->pf;
6849 if (!(bp->flags & BNXT_FLAG_PORT_STATS_EXT))
6852 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_QSTATS_EXT, -1, -1);
6853 req.port_id = cpu_to_le16(pf->port_id);
6854 req.rx_stat_size = cpu_to_le16(sizeof(struct rx_port_stats_ext));
6855 req.rx_stat_host_addr = cpu_to_le64(bp->hw_rx_port_stats_ext_map);
6856 tx_stat_size = bp->hw_tx_port_stats_ext ?
6857 sizeof(*bp->hw_tx_port_stats_ext) : 0;
6858 req.tx_stat_size = cpu_to_le16(tx_stat_size);
6859 req.tx_stat_host_addr = cpu_to_le64(bp->hw_tx_port_stats_ext_map);
6860 mutex_lock(&bp->hwrm_cmd_lock);
6861 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6863 bp->fw_rx_stats_ext_size = le16_to_cpu(resp->rx_stat_size) / 8;
6864 bp->fw_tx_stats_ext_size = tx_stat_size ?
6865 le16_to_cpu(resp->tx_stat_size) / 8 : 0;
6867 bp->fw_rx_stats_ext_size = 0;
6868 bp->fw_tx_stats_ext_size = 0;
6870 if (bp->fw_tx_stats_ext_size <=
6871 offsetof(struct tx_port_stats_ext, pfc_pri0_tx_duration_us) / 8) {
6872 mutex_unlock(&bp->hwrm_cmd_lock);
6873 bp->pri2cos_valid = 0;
6877 bnxt_hwrm_cmd_hdr_init(bp, &req2, HWRM_QUEUE_PRI2COS_QCFG, -1, -1);
6878 req2.flags = cpu_to_le32(QUEUE_PRI2COS_QCFG_REQ_FLAGS_IVLAN);
6880 rc = _hwrm_send_message(bp, &req2, sizeof(req2), HWRM_CMD_TIMEOUT);
6882 struct hwrm_queue_pri2cos_qcfg_output *resp2;
6886 resp2 = bp->hwrm_cmd_resp_addr;
6887 pri2cos = &resp2->pri0_cos_queue_id;
6888 for (i = 0; i < 8; i++) {
6889 u8 queue_id = pri2cos[i];
6891 for (j = 0; j < bp->max_q; j++) {
6892 if (bp->q_ids[j] == queue_id)
6896 bp->pri2cos_valid = 1;
6898 mutex_unlock(&bp->hwrm_cmd_lock);
6902 static int bnxt_hwrm_pcie_qstats(struct bnxt *bp)
6904 struct hwrm_pcie_qstats_input req = {0};
6906 if (!(bp->flags & BNXT_FLAG_PCIE_STATS))
6909 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PCIE_QSTATS, -1, -1);
6910 req.pcie_stat_size = cpu_to_le16(sizeof(struct pcie_ctx_hw_stats));
6911 req.pcie_stat_host_addr = cpu_to_le64(bp->hw_pcie_stats_map);
6912 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6915 static void bnxt_hwrm_free_tunnel_ports(struct bnxt *bp)
6917 if (bp->vxlan_port_cnt) {
6918 bnxt_hwrm_tunnel_dst_port_free(
6919 bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN);
6921 bp->vxlan_port_cnt = 0;
6922 if (bp->nge_port_cnt) {
6923 bnxt_hwrm_tunnel_dst_port_free(
6924 bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE);
6926 bp->nge_port_cnt = 0;
6929 static int bnxt_set_tpa(struct bnxt *bp, bool set_tpa)
6935 tpa_flags = bp->flags & BNXT_FLAG_TPA;
6936 for (i = 0; i < bp->nr_vnics; i++) {
6937 rc = bnxt_hwrm_vnic_set_tpa(bp, i, tpa_flags);
6939 netdev_err(bp->dev, "hwrm vnic set tpa failure rc for vnic %d: %x\n",
6947 static void bnxt_hwrm_clear_vnic_rss(struct bnxt *bp)
6951 for (i = 0; i < bp->nr_vnics; i++)
6952 bnxt_hwrm_vnic_set_rss(bp, i, false);
6955 static void bnxt_hwrm_resource_free(struct bnxt *bp, bool close_path,
6958 if (bp->vnic_info) {
6959 bnxt_hwrm_clear_vnic_filter(bp);
6960 /* clear all RSS setting before free vnic ctx */
6961 bnxt_hwrm_clear_vnic_rss(bp);
6962 bnxt_hwrm_vnic_ctx_free(bp);
6963 /* before free the vnic, undo the vnic tpa settings */
6964 if (bp->flags & BNXT_FLAG_TPA)
6965 bnxt_set_tpa(bp, false);
6966 bnxt_hwrm_vnic_free(bp);
6968 bnxt_hwrm_ring_free(bp, close_path);
6969 bnxt_hwrm_ring_grp_free(bp);
6971 bnxt_hwrm_stat_ctx_free(bp);
6972 bnxt_hwrm_free_tunnel_ports(bp);
6976 static int bnxt_hwrm_set_br_mode(struct bnxt *bp, u16 br_mode)
6978 struct hwrm_func_cfg_input req = {0};
6981 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_CFG, -1, -1);
6982 req.fid = cpu_to_le16(0xffff);
6983 req.enables = cpu_to_le32(FUNC_CFG_REQ_ENABLES_EVB_MODE);
6984 if (br_mode == BRIDGE_MODE_VEB)
6985 req.evb_mode = FUNC_CFG_REQ_EVB_MODE_VEB;
6986 else if (br_mode == BRIDGE_MODE_VEPA)
6987 req.evb_mode = FUNC_CFG_REQ_EVB_MODE_VEPA;
6990 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6996 static int bnxt_hwrm_set_cache_line_size(struct bnxt *bp, int size)
6998 struct hwrm_func_cfg_input req = {0};
7001 if (BNXT_VF(bp) || bp->hwrm_spec_code < 0x10803)
7004 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_CFG, -1, -1);
7005 req.fid = cpu_to_le16(0xffff);
7006 req.enables = cpu_to_le32(FUNC_CFG_REQ_ENABLES_CACHE_LINESIZE);
7007 req.options = FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_64;
7009 req.options = FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_128;
7011 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
7017 static int __bnxt_setup_vnic(struct bnxt *bp, u16 vnic_id)
7019 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
7022 if (vnic->flags & BNXT_VNIC_RFS_NEW_RSS_FLAG)
7025 /* allocate context for vnic */
7026 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic_id, 0);
7028 netdev_err(bp->dev, "hwrm vnic %d alloc failure rc: %x\n",
7030 goto vnic_setup_err;
7032 bp->rsscos_nr_ctxs++;
7034 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) {
7035 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic_id, 1);
7037 netdev_err(bp->dev, "hwrm vnic %d cos ctx alloc failure rc: %x\n",
7039 goto vnic_setup_err;
7041 bp->rsscos_nr_ctxs++;
7045 /* configure default vnic, ring grp */
7046 rc = bnxt_hwrm_vnic_cfg(bp, vnic_id);
7048 netdev_err(bp->dev, "hwrm vnic %d cfg failure rc: %x\n",
7050 goto vnic_setup_err;
7053 /* Enable RSS hashing on vnic */
7054 rc = bnxt_hwrm_vnic_set_rss(bp, vnic_id, true);
7056 netdev_err(bp->dev, "hwrm vnic %d set rss failure rc: %x\n",
7058 goto vnic_setup_err;
7061 if (bp->flags & BNXT_FLAG_AGG_RINGS) {
7062 rc = bnxt_hwrm_vnic_set_hds(bp, vnic_id);
7064 netdev_err(bp->dev, "hwrm vnic %d set hds failure rc: %x\n",
7073 static int __bnxt_setup_vnic_p5(struct bnxt *bp, u16 vnic_id)
7077 nr_ctxs = DIV_ROUND_UP(bp->rx_nr_rings, 64);
7078 for (i = 0; i < nr_ctxs; i++) {
7079 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic_id, i);
7081 netdev_err(bp->dev, "hwrm vnic %d ctx %d alloc failure rc: %x\n",
7085 bp->rsscos_nr_ctxs++;
7090 rc = bnxt_hwrm_vnic_set_rss_p5(bp, vnic_id, true);
7092 netdev_err(bp->dev, "hwrm vnic %d set rss failure rc: %d\n",
7096 rc = bnxt_hwrm_vnic_cfg(bp, vnic_id);
7098 netdev_err(bp->dev, "hwrm vnic %d cfg failure rc: %x\n",
7102 if (bp->flags & BNXT_FLAG_AGG_RINGS) {
7103 rc = bnxt_hwrm_vnic_set_hds(bp, vnic_id);
7105 netdev_err(bp->dev, "hwrm vnic %d set hds failure rc: %x\n",
7112 static int bnxt_setup_vnic(struct bnxt *bp, u16 vnic_id)
7114 if (bp->flags & BNXT_FLAG_CHIP_P5)
7115 return __bnxt_setup_vnic_p5(bp, vnic_id);
7117 return __bnxt_setup_vnic(bp, vnic_id);
7120 static int bnxt_alloc_rfs_vnics(struct bnxt *bp)
7122 #ifdef CONFIG_RFS_ACCEL
7125 for (i = 0; i < bp->rx_nr_rings; i++) {
7126 struct bnxt_vnic_info *vnic;
7127 u16 vnic_id = i + 1;
7130 if (vnic_id >= bp->nr_vnics)
7133 vnic = &bp->vnic_info[vnic_id];
7134 vnic->flags |= BNXT_VNIC_RFS_FLAG;
7135 if (bp->flags & BNXT_FLAG_NEW_RSS_CAP)
7136 vnic->flags |= BNXT_VNIC_RFS_NEW_RSS_FLAG;
7137 rc = bnxt_hwrm_vnic_alloc(bp, vnic_id, ring_id, 1);
7139 netdev_err(bp->dev, "hwrm vnic %d alloc failure rc: %x\n",
7143 rc = bnxt_setup_vnic(bp, vnic_id);
7153 /* Allow PF and VF with default VLAN to be in promiscuous mode */
7154 static bool bnxt_promisc_ok(struct bnxt *bp)
7156 #ifdef CONFIG_BNXT_SRIOV
7157 if (BNXT_VF(bp) && !bp->vf.vlan)
7163 static int bnxt_setup_nitroa0_vnic(struct bnxt *bp)
7165 unsigned int rc = 0;
7167 rc = bnxt_hwrm_vnic_alloc(bp, 1, bp->rx_nr_rings - 1, 1);
7169 netdev_err(bp->dev, "Cannot allocate special vnic for NS2 A0: %x\n",
7174 rc = bnxt_hwrm_vnic_cfg(bp, 1);
7176 netdev_err(bp->dev, "Cannot allocate special vnic for NS2 A0: %x\n",
7183 static int bnxt_cfg_rx_mode(struct bnxt *);
7184 static bool bnxt_mc_list_updated(struct bnxt *, u32 *);
7186 static int bnxt_init_chip(struct bnxt *bp, bool irq_re_init)
7188 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
7190 unsigned int rx_nr_rings = bp->rx_nr_rings;
7193 rc = bnxt_hwrm_stat_ctx_alloc(bp);
7195 netdev_err(bp->dev, "hwrm stat ctx alloc failure rc: %x\n",
7201 rc = bnxt_hwrm_ring_alloc(bp);
7203 netdev_err(bp->dev, "hwrm ring alloc failure rc: %x\n", rc);
7207 rc = bnxt_hwrm_ring_grp_alloc(bp);
7209 netdev_err(bp->dev, "hwrm_ring_grp alloc failure: %x\n", rc);
7213 if (BNXT_CHIP_TYPE_NITRO_A0(bp))
7216 /* default vnic 0 */
7217 rc = bnxt_hwrm_vnic_alloc(bp, 0, 0, rx_nr_rings);
7219 netdev_err(bp->dev, "hwrm vnic alloc failure rc: %x\n", rc);
7223 rc = bnxt_setup_vnic(bp, 0);
7227 if (bp->flags & BNXT_FLAG_RFS) {
7228 rc = bnxt_alloc_rfs_vnics(bp);
7233 if (bp->flags & BNXT_FLAG_TPA) {
7234 rc = bnxt_set_tpa(bp, true);
7240 bnxt_update_vf_mac(bp);
7242 /* Filter for default vnic 0 */
7243 rc = bnxt_hwrm_set_vnic_filter(bp, 0, 0, bp->dev->dev_addr);
7245 netdev_err(bp->dev, "HWRM vnic filter failure rc: %x\n", rc);
7248 vnic->uc_filter_count = 1;
7251 if (bp->dev->flags & IFF_BROADCAST)
7252 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_BCAST;
7254 if ((bp->dev->flags & IFF_PROMISC) && bnxt_promisc_ok(bp))
7255 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS;
7257 if (bp->dev->flags & IFF_ALLMULTI) {
7258 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST;
7259 vnic->mc_list_count = 0;
7263 bnxt_mc_list_updated(bp, &mask);
7264 vnic->rx_mask |= mask;
7267 rc = bnxt_cfg_rx_mode(bp);
7271 rc = bnxt_hwrm_set_coal(bp);
7273 netdev_warn(bp->dev, "HWRM set coalescing failure rc: %x\n",
7276 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) {
7277 rc = bnxt_setup_nitroa0_vnic(bp);
7279 netdev_err(bp->dev, "Special vnic setup failure for NS2 A0 rc: %x\n",
7284 bnxt_hwrm_func_qcfg(bp);
7285 netdev_update_features(bp->dev);
7291 bnxt_hwrm_resource_free(bp, 0, true);
7296 static int bnxt_shutdown_nic(struct bnxt *bp, bool irq_re_init)
7298 bnxt_hwrm_resource_free(bp, 1, irq_re_init);
7302 static int bnxt_init_nic(struct bnxt *bp, bool irq_re_init)
7304 bnxt_init_cp_rings(bp);
7305 bnxt_init_rx_rings(bp);
7306 bnxt_init_tx_rings(bp);
7307 bnxt_init_ring_grps(bp, irq_re_init);
7308 bnxt_init_vnics(bp);
7310 return bnxt_init_chip(bp, irq_re_init);
7313 static int bnxt_set_real_num_queues(struct bnxt *bp)
7316 struct net_device *dev = bp->dev;
7318 rc = netif_set_real_num_tx_queues(dev, bp->tx_nr_rings -
7319 bp->tx_nr_rings_xdp);
7323 rc = netif_set_real_num_rx_queues(dev, bp->rx_nr_rings);
7327 #ifdef CONFIG_RFS_ACCEL
7328 if (bp->flags & BNXT_FLAG_RFS)
7329 dev->rx_cpu_rmap = alloc_irq_cpu_rmap(bp->rx_nr_rings);
7335 static int bnxt_trim_rings(struct bnxt *bp, int *rx, int *tx, int max,
7338 int _rx = *rx, _tx = *tx;
7341 *rx = min_t(int, _rx, max);
7342 *tx = min_t(int, _tx, max);
7347 while (_rx + _tx > max) {
7348 if (_rx > _tx && _rx > 1)
7359 static void bnxt_setup_msix(struct bnxt *bp)
7361 const int len = sizeof(bp->irq_tbl[0].name);
7362 struct net_device *dev = bp->dev;
7365 tcs = netdev_get_num_tc(dev);
7369 for (i = 0; i < tcs; i++) {
7370 count = bp->tx_nr_rings_per_tc;
7372 netdev_set_tc_queue(dev, i, count, off);
7376 for (i = 0; i < bp->cp_nr_rings; i++) {
7377 int map_idx = bnxt_cp_num_to_irq_num(bp, i);
7380 if (bp->flags & BNXT_FLAG_SHARED_RINGS)
7382 else if (i < bp->rx_nr_rings)
7387 snprintf(bp->irq_tbl[map_idx].name, len, "%s-%s-%d", dev->name,
7389 bp->irq_tbl[map_idx].handler = bnxt_msix;
7393 static void bnxt_setup_inta(struct bnxt *bp)
7395 const int len = sizeof(bp->irq_tbl[0].name);
7397 if (netdev_get_num_tc(bp->dev))
7398 netdev_reset_tc(bp->dev);
7400 snprintf(bp->irq_tbl[0].name, len, "%s-%s-%d", bp->dev->name, "TxRx",
7402 bp->irq_tbl[0].handler = bnxt_inta;
7405 static int bnxt_setup_int_mode(struct bnxt *bp)
7409 if (bp->flags & BNXT_FLAG_USING_MSIX)
7410 bnxt_setup_msix(bp);
7412 bnxt_setup_inta(bp);
7414 rc = bnxt_set_real_num_queues(bp);
7418 #ifdef CONFIG_RFS_ACCEL
7419 static unsigned int bnxt_get_max_func_rss_ctxs(struct bnxt *bp)
7421 return bp->hw_resc.max_rsscos_ctxs;
7424 static unsigned int bnxt_get_max_func_vnics(struct bnxt *bp)
7426 return bp->hw_resc.max_vnics;
7430 unsigned int bnxt_get_max_func_stat_ctxs(struct bnxt *bp)
7432 return bp->hw_resc.max_stat_ctxs;
7435 unsigned int bnxt_get_max_func_cp_rings(struct bnxt *bp)
7437 return bp->hw_resc.max_cp_rings;
7440 static unsigned int bnxt_get_max_func_cp_rings_for_en(struct bnxt *bp)
7442 unsigned int cp = bp->hw_resc.max_cp_rings;
7444 if (!(bp->flags & BNXT_FLAG_CHIP_P5))
7445 cp -= bnxt_get_ulp_msix_num(bp);
7450 static unsigned int bnxt_get_max_func_irqs(struct bnxt *bp)
7452 struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
7454 if (bp->flags & BNXT_FLAG_CHIP_P5)
7455 return min_t(unsigned int, hw_resc->max_irqs, hw_resc->max_nqs);
7457 return min_t(unsigned int, hw_resc->max_irqs, hw_resc->max_cp_rings);
7460 static void bnxt_set_max_func_irqs(struct bnxt *bp, unsigned int max_irqs)
7462 bp->hw_resc.max_irqs = max_irqs;
7465 unsigned int bnxt_get_avail_cp_rings_for_en(struct bnxt *bp)
7469 cp = bnxt_get_max_func_cp_rings_for_en(bp);
7470 if (bp->flags & BNXT_FLAG_CHIP_P5)
7471 return cp - bp->rx_nr_rings - bp->tx_nr_rings;
7473 return cp - bp->cp_nr_rings;
7476 unsigned int bnxt_get_avail_stat_ctxs_for_en(struct bnxt *bp)
7480 stat = bnxt_get_max_func_stat_ctxs(bp) - bnxt_get_ulp_stat_ctxs(bp);
7481 stat -= bp->cp_nr_rings;
7485 int bnxt_get_avail_msix(struct bnxt *bp, int num)
7487 int max_cp = bnxt_get_max_func_cp_rings(bp);
7488 int max_irq = bnxt_get_max_func_irqs(bp);
7489 int total_req = bp->cp_nr_rings + num;
7490 int max_idx, avail_msix;
7492 max_idx = bp->total_irqs;
7493 if (!(bp->flags & BNXT_FLAG_CHIP_P5))
7494 max_idx = min_t(int, bp->total_irqs, max_cp);
7495 avail_msix = max_idx - bp->cp_nr_rings;
7496 if (!BNXT_NEW_RM(bp) || avail_msix >= num)
7499 if (max_irq < total_req) {
7500 num = max_irq - bp->cp_nr_rings;
7507 static int bnxt_get_num_msix(struct bnxt *bp)
7509 if (!BNXT_NEW_RM(bp))
7510 return bnxt_get_max_func_irqs(bp);
7512 return bnxt_nq_rings_in_use(bp);
7515 static int bnxt_init_msix(struct bnxt *bp)
7517 int i, total_vecs, max, rc = 0, min = 1, ulp_msix;
7518 struct msix_entry *msix_ent;
7520 total_vecs = bnxt_get_num_msix(bp);
7521 max = bnxt_get_max_func_irqs(bp);
7522 if (total_vecs > max)
7528 msix_ent = kcalloc(total_vecs, sizeof(struct msix_entry), GFP_KERNEL);
7532 for (i = 0; i < total_vecs; i++) {
7533 msix_ent[i].entry = i;
7534 msix_ent[i].vector = 0;
7537 if (!(bp->flags & BNXT_FLAG_SHARED_RINGS))
7540 total_vecs = pci_enable_msix_range(bp->pdev, msix_ent, min, total_vecs);
7541 ulp_msix = bnxt_get_ulp_msix_num(bp);
7542 if (total_vecs < 0 || total_vecs < ulp_msix) {
7544 goto msix_setup_exit;
7547 bp->irq_tbl = kcalloc(total_vecs, sizeof(struct bnxt_irq), GFP_KERNEL);
7549 for (i = 0; i < total_vecs; i++)
7550 bp->irq_tbl[i].vector = msix_ent[i].vector;
7552 bp->total_irqs = total_vecs;
7553 /* Trim rings based upon num of vectors allocated */
7554 rc = bnxt_trim_rings(bp, &bp->rx_nr_rings, &bp->tx_nr_rings,
7555 total_vecs - ulp_msix, min == 1);
7557 goto msix_setup_exit;
7559 bp->cp_nr_rings = (min == 1) ?
7560 max_t(int, bp->tx_nr_rings, bp->rx_nr_rings) :
7561 bp->tx_nr_rings + bp->rx_nr_rings;
7565 goto msix_setup_exit;
7567 bp->flags |= BNXT_FLAG_USING_MSIX;
7572 netdev_err(bp->dev, "bnxt_init_msix err: %x\n", rc);
7575 pci_disable_msix(bp->pdev);
7580 static int bnxt_init_inta(struct bnxt *bp)
7582 bp->irq_tbl = kcalloc(1, sizeof(struct bnxt_irq), GFP_KERNEL);
7587 bp->rx_nr_rings = 1;
7588 bp->tx_nr_rings = 1;
7589 bp->cp_nr_rings = 1;
7590 bp->flags |= BNXT_FLAG_SHARED_RINGS;
7591 bp->irq_tbl[0].vector = bp->pdev->irq;
7595 static int bnxt_init_int_mode(struct bnxt *bp)
7599 if (bp->flags & BNXT_FLAG_MSIX_CAP)
7600 rc = bnxt_init_msix(bp);
7602 if (!(bp->flags & BNXT_FLAG_USING_MSIX) && BNXT_PF(bp)) {
7603 /* fallback to INTA */
7604 rc = bnxt_init_inta(bp);
7609 static void bnxt_clear_int_mode(struct bnxt *bp)
7611 if (bp->flags & BNXT_FLAG_USING_MSIX)
7612 pci_disable_msix(bp->pdev);
7616 bp->flags &= ~BNXT_FLAG_USING_MSIX;
7619 int bnxt_reserve_rings(struct bnxt *bp)
7621 int tcs = netdev_get_num_tc(bp->dev);
7622 bool reinit_irq = false;
7625 if (!bnxt_need_reserve_rings(bp))
7628 if (BNXT_NEW_RM(bp) && (bnxt_get_num_msix(bp) != bp->total_irqs)) {
7629 bnxt_ulp_irq_stop(bp);
7630 bnxt_clear_int_mode(bp);
7633 rc = __bnxt_reserve_rings(bp);
7636 rc = bnxt_init_int_mode(bp);
7637 bnxt_ulp_irq_restart(bp, rc);
7640 netdev_err(bp->dev, "ring reservation/IRQ init failure rc: %d\n", rc);
7643 if (tcs && (bp->tx_nr_rings_per_tc * tcs != bp->tx_nr_rings)) {
7644 netdev_err(bp->dev, "tx ring reservation failure\n");
7645 netdev_reset_tc(bp->dev);
7646 bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
7652 static void bnxt_free_irq(struct bnxt *bp)
7654 struct bnxt_irq *irq;
7657 #ifdef CONFIG_RFS_ACCEL
7658 free_irq_cpu_rmap(bp->dev->rx_cpu_rmap);
7659 bp->dev->rx_cpu_rmap = NULL;
7661 if (!bp->irq_tbl || !bp->bnapi)
7664 for (i = 0; i < bp->cp_nr_rings; i++) {
7665 int map_idx = bnxt_cp_num_to_irq_num(bp, i);
7667 irq = &bp->irq_tbl[map_idx];
7668 if (irq->requested) {
7669 if (irq->have_cpumask) {
7670 irq_set_affinity_hint(irq->vector, NULL);
7671 free_cpumask_var(irq->cpu_mask);
7672 irq->have_cpumask = 0;
7674 free_irq(irq->vector, bp->bnapi[i]);
7681 static int bnxt_request_irq(struct bnxt *bp)
7684 unsigned long flags = 0;
7685 #ifdef CONFIG_RFS_ACCEL
7686 struct cpu_rmap *rmap;
7689 rc = bnxt_setup_int_mode(bp);
7691 netdev_err(bp->dev, "bnxt_setup_int_mode err: %x\n",
7695 #ifdef CONFIG_RFS_ACCEL
7696 rmap = bp->dev->rx_cpu_rmap;
7698 if (!(bp->flags & BNXT_FLAG_USING_MSIX))
7699 flags = IRQF_SHARED;
7701 for (i = 0, j = 0; i < bp->cp_nr_rings; i++) {
7702 int map_idx = bnxt_cp_num_to_irq_num(bp, i);
7703 struct bnxt_irq *irq = &bp->irq_tbl[map_idx];
7705 #ifdef CONFIG_RFS_ACCEL
7706 if (rmap && bp->bnapi[i]->rx_ring) {
7707 rc = irq_cpu_rmap_add(rmap, irq->vector);
7709 netdev_warn(bp->dev, "failed adding irq rmap for ring %d\n",
7714 rc = request_irq(irq->vector, irq->handler, flags, irq->name,
7721 if (zalloc_cpumask_var(&irq->cpu_mask, GFP_KERNEL)) {
7722 int numa_node = dev_to_node(&bp->pdev->dev);
7724 irq->have_cpumask = 1;
7725 cpumask_set_cpu(cpumask_local_spread(i, numa_node),
7727 rc = irq_set_affinity_hint(irq->vector, irq->cpu_mask);
7729 netdev_warn(bp->dev,
7730 "Set affinity failed, IRQ = %d\n",
7739 static void bnxt_del_napi(struct bnxt *bp)
7746 for (i = 0; i < bp->cp_nr_rings; i++) {
7747 struct bnxt_napi *bnapi = bp->bnapi[i];
7749 napi_hash_del(&bnapi->napi);
7750 netif_napi_del(&bnapi->napi);
7752 /* We called napi_hash_del() before netif_napi_del(), we need
7753 * to respect an RCU grace period before freeing napi structures.
7758 static void bnxt_init_napi(struct bnxt *bp)
7761 unsigned int cp_nr_rings = bp->cp_nr_rings;
7762 struct bnxt_napi *bnapi;
7764 if (bp->flags & BNXT_FLAG_USING_MSIX) {
7765 int (*poll_fn)(struct napi_struct *, int) = bnxt_poll;
7767 if (bp->flags & BNXT_FLAG_CHIP_P5)
7768 poll_fn = bnxt_poll_p5;
7769 else if (BNXT_CHIP_TYPE_NITRO_A0(bp))
7771 for (i = 0; i < cp_nr_rings; i++) {
7772 bnapi = bp->bnapi[i];
7773 netif_napi_add(bp->dev, &bnapi->napi, poll_fn, 64);
7775 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) {
7776 bnapi = bp->bnapi[cp_nr_rings];
7777 netif_napi_add(bp->dev, &bnapi->napi,
7778 bnxt_poll_nitroa0, 64);
7781 bnapi = bp->bnapi[0];
7782 netif_napi_add(bp->dev, &bnapi->napi, bnxt_poll, 64);
7786 static void bnxt_disable_napi(struct bnxt *bp)
7793 for (i = 0; i < bp->cp_nr_rings; i++) {
7794 struct bnxt_cp_ring_info *cpr = &bp->bnapi[i]->cp_ring;
7796 if (bp->bnapi[i]->rx_ring)
7797 cancel_work_sync(&cpr->dim.work);
7799 napi_disable(&bp->bnapi[i]->napi);
7803 static void bnxt_enable_napi(struct bnxt *bp)
7807 for (i = 0; i < bp->cp_nr_rings; i++) {
7808 struct bnxt_cp_ring_info *cpr = &bp->bnapi[i]->cp_ring;
7809 bp->bnapi[i]->in_reset = false;
7811 if (bp->bnapi[i]->rx_ring) {
7812 INIT_WORK(&cpr->dim.work, bnxt_dim_work);
7813 cpr->dim.mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE;
7815 napi_enable(&bp->bnapi[i]->napi);
7819 void bnxt_tx_disable(struct bnxt *bp)
7822 struct bnxt_tx_ring_info *txr;
7825 for (i = 0; i < bp->tx_nr_rings; i++) {
7826 txr = &bp->tx_ring[i];
7827 txr->dev_state = BNXT_DEV_STATE_CLOSING;
7830 /* Stop all TX queues */
7831 netif_tx_disable(bp->dev);
7832 netif_carrier_off(bp->dev);
7835 void bnxt_tx_enable(struct bnxt *bp)
7838 struct bnxt_tx_ring_info *txr;
7840 for (i = 0; i < bp->tx_nr_rings; i++) {
7841 txr = &bp->tx_ring[i];
7844 netif_tx_wake_all_queues(bp->dev);
7845 if (bp->link_info.link_up)
7846 netif_carrier_on(bp->dev);
7849 static void bnxt_report_link(struct bnxt *bp)
7851 if (bp->link_info.link_up) {
7853 const char *flow_ctrl;
7857 netif_carrier_on(bp->dev);
7858 if (bp->link_info.duplex == BNXT_LINK_DUPLEX_FULL)
7862 if (bp->link_info.pause == BNXT_LINK_PAUSE_BOTH)
7863 flow_ctrl = "ON - receive & transmit";
7864 else if (bp->link_info.pause == BNXT_LINK_PAUSE_TX)
7865 flow_ctrl = "ON - transmit";
7866 else if (bp->link_info.pause == BNXT_LINK_PAUSE_RX)
7867 flow_ctrl = "ON - receive";
7870 speed = bnxt_fw_to_ethtool_speed(bp->link_info.link_speed);
7871 netdev_info(bp->dev, "NIC Link is Up, %u Mbps %s duplex, Flow control: %s\n",
7872 speed, duplex, flow_ctrl);
7873 if (bp->flags & BNXT_FLAG_EEE_CAP)
7874 netdev_info(bp->dev, "EEE is %s\n",
7875 bp->eee.eee_active ? "active" :
7877 fec = bp->link_info.fec_cfg;
7878 if (!(fec & PORT_PHY_QCFG_RESP_FEC_CFG_FEC_NONE_SUPPORTED))
7879 netdev_info(bp->dev, "FEC autoneg %s encodings: %s\n",
7880 (fec & BNXT_FEC_AUTONEG) ? "on" : "off",
7881 (fec & BNXT_FEC_ENC_BASE_R) ? "BaseR" :
7882 (fec & BNXT_FEC_ENC_RS) ? "RS" : "None");
7884 netif_carrier_off(bp->dev);
7885 netdev_err(bp->dev, "NIC Link is Down\n");
7889 static int bnxt_hwrm_phy_qcaps(struct bnxt *bp)
7892 struct hwrm_port_phy_qcaps_input req = {0};
7893 struct hwrm_port_phy_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
7894 struct bnxt_link_info *link_info = &bp->link_info;
7896 if (bp->hwrm_spec_code < 0x10201)
7899 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_QCAPS, -1, -1);
7901 mutex_lock(&bp->hwrm_cmd_lock);
7902 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
7904 goto hwrm_phy_qcaps_exit;
7906 if (resp->flags & PORT_PHY_QCAPS_RESP_FLAGS_EEE_SUPPORTED) {
7907 struct ethtool_eee *eee = &bp->eee;
7908 u16 fw_speeds = le16_to_cpu(resp->supported_speeds_eee_mode);
7910 bp->flags |= BNXT_FLAG_EEE_CAP;
7911 eee->supported = _bnxt_fw_to_ethtool_adv_spds(fw_speeds, 0);
7912 bp->lpi_tmr_lo = le32_to_cpu(resp->tx_lpi_timer_low) &
7913 PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_LOW_MASK;
7914 bp->lpi_tmr_hi = le32_to_cpu(resp->valid_tx_lpi_timer_high) &
7915 PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_HIGH_MASK;
7917 if (resp->flags & PORT_PHY_QCAPS_RESP_FLAGS_EXTERNAL_LPBK_SUPPORTED) {
7919 bp->test_info->flags |= BNXT_TEST_FL_EXT_LPBK;
7921 if (resp->supported_speeds_auto_mode)
7922 link_info->support_auto_speeds =
7923 le16_to_cpu(resp->supported_speeds_auto_mode);
7925 bp->port_count = resp->port_cnt;
7927 hwrm_phy_qcaps_exit:
7928 mutex_unlock(&bp->hwrm_cmd_lock);
7932 static int bnxt_update_link(struct bnxt *bp, bool chng_link_state)
7935 struct bnxt_link_info *link_info = &bp->link_info;
7936 struct hwrm_port_phy_qcfg_input req = {0};
7937 struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
7938 u8 link_up = link_info->link_up;
7941 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_QCFG, -1, -1);
7943 mutex_lock(&bp->hwrm_cmd_lock);
7944 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
7946 mutex_unlock(&bp->hwrm_cmd_lock);
7950 memcpy(&link_info->phy_qcfg_resp, resp, sizeof(*resp));
7951 link_info->phy_link_status = resp->link;
7952 link_info->duplex = resp->duplex_cfg;
7953 if (bp->hwrm_spec_code >= 0x10800)
7954 link_info->duplex = resp->duplex_state;
7955 link_info->pause = resp->pause;
7956 link_info->auto_mode = resp->auto_mode;
7957 link_info->auto_pause_setting = resp->auto_pause;
7958 link_info->lp_pause = resp->link_partner_adv_pause;
7959 link_info->force_pause_setting = resp->force_pause;
7960 link_info->duplex_setting = resp->duplex_cfg;
7961 if (link_info->phy_link_status == BNXT_LINK_LINK)
7962 link_info->link_speed = le16_to_cpu(resp->link_speed);
7964 link_info->link_speed = 0;
7965 link_info->force_link_speed = le16_to_cpu(resp->force_link_speed);
7966 link_info->support_speeds = le16_to_cpu(resp->support_speeds);
7967 link_info->auto_link_speeds = le16_to_cpu(resp->auto_link_speed_mask);
7968 link_info->lp_auto_link_speeds =
7969 le16_to_cpu(resp->link_partner_adv_speeds);
7970 link_info->preemphasis = le32_to_cpu(resp->preemphasis);
7971 link_info->phy_ver[0] = resp->phy_maj;
7972 link_info->phy_ver[1] = resp->phy_min;
7973 link_info->phy_ver[2] = resp->phy_bld;
7974 link_info->media_type = resp->media_type;
7975 link_info->phy_type = resp->phy_type;
7976 link_info->transceiver = resp->xcvr_pkg_type;
7977 link_info->phy_addr = resp->eee_config_phy_addr &
7978 PORT_PHY_QCFG_RESP_PHY_ADDR_MASK;
7979 link_info->module_status = resp->module_status;
7981 if (bp->flags & BNXT_FLAG_EEE_CAP) {
7982 struct ethtool_eee *eee = &bp->eee;
7985 eee->eee_active = 0;
7986 if (resp->eee_config_phy_addr &
7987 PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ACTIVE) {
7988 eee->eee_active = 1;
7989 fw_speeds = le16_to_cpu(
7990 resp->link_partner_adv_eee_link_speed_mask);
7991 eee->lp_advertised =
7992 _bnxt_fw_to_ethtool_adv_spds(fw_speeds, 0);
7995 /* Pull initial EEE config */
7996 if (!chng_link_state) {
7997 if (resp->eee_config_phy_addr &
7998 PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ENABLED)
7999 eee->eee_enabled = 1;
8001 fw_speeds = le16_to_cpu(resp->adv_eee_link_speed_mask);
8003 _bnxt_fw_to_ethtool_adv_spds(fw_speeds, 0);
8005 if (resp->eee_config_phy_addr &
8006 PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_TX_LPI) {
8009 eee->tx_lpi_enabled = 1;
8010 tmr = resp->xcvr_identifier_type_tx_lpi_timer;
8011 eee->tx_lpi_timer = le32_to_cpu(tmr) &
8012 PORT_PHY_QCFG_RESP_TX_LPI_TIMER_MASK;
8017 link_info->fec_cfg = PORT_PHY_QCFG_RESP_FEC_CFG_FEC_NONE_SUPPORTED;
8018 if (bp->hwrm_spec_code >= 0x10504)
8019 link_info->fec_cfg = le16_to_cpu(resp->fec_cfg);
8021 /* TODO: need to add more logic to report VF link */
8022 if (chng_link_state) {
8023 if (link_info->phy_link_status == BNXT_LINK_LINK)
8024 link_info->link_up = 1;
8026 link_info->link_up = 0;
8027 if (link_up != link_info->link_up)
8028 bnxt_report_link(bp);
8030 /* alwasy link down if not require to update link state */
8031 link_info->link_up = 0;
8033 mutex_unlock(&bp->hwrm_cmd_lock);
8035 if (!BNXT_SINGLE_PF(bp))
8038 diff = link_info->support_auto_speeds ^ link_info->advertising;
8039 if ((link_info->support_auto_speeds | diff) !=
8040 link_info->support_auto_speeds) {
8041 /* An advertised speed is no longer supported, so we need to
8042 * update the advertisement settings. Caller holds RTNL
8043 * so we can modify link settings.
8045 link_info->advertising = link_info->support_auto_speeds;
8046 if (link_info->autoneg & BNXT_AUTONEG_SPEED)
8047 bnxt_hwrm_set_link_setting(bp, true, false);
8052 static void bnxt_get_port_module_status(struct bnxt *bp)
8054 struct bnxt_link_info *link_info = &bp->link_info;
8055 struct hwrm_port_phy_qcfg_output *resp = &link_info->phy_qcfg_resp;
8058 if (bnxt_update_link(bp, true))
8061 module_status = link_info->module_status;
8062 switch (module_status) {
8063 case PORT_PHY_QCFG_RESP_MODULE_STATUS_DISABLETX:
8064 case PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN:
8065 case PORT_PHY_QCFG_RESP_MODULE_STATUS_WARNINGMSG:
8066 netdev_warn(bp->dev, "Unqualified SFP+ module detected on port %d\n",
8068 if (bp->hwrm_spec_code >= 0x10201) {
8069 netdev_warn(bp->dev, "Module part number %s\n",
8070 resp->phy_vendor_partnumber);
8072 if (module_status == PORT_PHY_QCFG_RESP_MODULE_STATUS_DISABLETX)
8073 netdev_warn(bp->dev, "TX is disabled\n");
8074 if (module_status == PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN)
8075 netdev_warn(bp->dev, "SFP+ module is shutdown\n");
8080 bnxt_hwrm_set_pause_common(struct bnxt *bp, struct hwrm_port_phy_cfg_input *req)
8082 if (bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL) {
8083 if (bp->hwrm_spec_code >= 0x10201)
8085 PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE;
8086 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_RX)
8087 req->auto_pause |= PORT_PHY_CFG_REQ_AUTO_PAUSE_RX;
8088 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_TX)
8089 req->auto_pause |= PORT_PHY_CFG_REQ_AUTO_PAUSE_TX;
8091 cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE);
8093 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_RX)
8094 req->force_pause |= PORT_PHY_CFG_REQ_FORCE_PAUSE_RX;
8095 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_TX)
8096 req->force_pause |= PORT_PHY_CFG_REQ_FORCE_PAUSE_TX;
8098 cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_FORCE_PAUSE);
8099 if (bp->hwrm_spec_code >= 0x10201) {
8100 req->auto_pause = req->force_pause;
8101 req->enables |= cpu_to_le32(
8102 PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE);
8107 static void bnxt_hwrm_set_link_common(struct bnxt *bp,
8108 struct hwrm_port_phy_cfg_input *req)
8110 u8 autoneg = bp->link_info.autoneg;
8111 u16 fw_link_speed = bp->link_info.req_link_speed;
8112 u16 advertising = bp->link_info.advertising;
8114 if (autoneg & BNXT_AUTONEG_SPEED) {
8116 PORT_PHY_CFG_REQ_AUTO_MODE_SPEED_MASK;
8118 req->enables |= cpu_to_le32(
8119 PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED_MASK);
8120 req->auto_link_speed_mask = cpu_to_le16(advertising);
8122 req->enables |= cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_MODE);
8124 cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_RESTART_AUTONEG);
8126 req->force_link_speed = cpu_to_le16(fw_link_speed);
8127 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_FORCE);
8130 /* tell chimp that the setting takes effect immediately */
8131 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_RESET_PHY);
8134 int bnxt_hwrm_set_pause(struct bnxt *bp)
8136 struct hwrm_port_phy_cfg_input req = {0};
8139 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1);
8140 bnxt_hwrm_set_pause_common(bp, &req);
8142 if ((bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL) ||
8143 bp->link_info.force_link_chng)
8144 bnxt_hwrm_set_link_common(bp, &req);
8146 mutex_lock(&bp->hwrm_cmd_lock);
8147 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
8148 if (!rc && !(bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL)) {
8149 /* since changing of pause setting doesn't trigger any link
8150 * change event, the driver needs to update the current pause
8151 * result upon successfully return of the phy_cfg command
8153 bp->link_info.pause =
8154 bp->link_info.force_pause_setting = bp->link_info.req_flow_ctrl;
8155 bp->link_info.auto_pause_setting = 0;
8156 if (!bp->link_info.force_link_chng)
8157 bnxt_report_link(bp);
8159 bp->link_info.force_link_chng = false;
8160 mutex_unlock(&bp->hwrm_cmd_lock);
8164 static void bnxt_hwrm_set_eee(struct bnxt *bp,
8165 struct hwrm_port_phy_cfg_input *req)
8167 struct ethtool_eee *eee = &bp->eee;
8169 if (eee->eee_enabled) {
8171 u32 flags = PORT_PHY_CFG_REQ_FLAGS_EEE_ENABLE;
8173 if (eee->tx_lpi_enabled)
8174 flags |= PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_ENABLE;
8176 flags |= PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_DISABLE;
8178 req->flags |= cpu_to_le32(flags);
8179 eee_speeds = bnxt_get_fw_auto_link_speeds(eee->advertised);
8180 req->eee_link_speed_mask = cpu_to_le16(eee_speeds);
8181 req->tx_lpi_timer = cpu_to_le32(eee->tx_lpi_timer);
8183 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_EEE_DISABLE);
8187 int bnxt_hwrm_set_link_setting(struct bnxt *bp, bool set_pause, bool set_eee)
8189 struct hwrm_port_phy_cfg_input req = {0};
8191 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1);
8193 bnxt_hwrm_set_pause_common(bp, &req);
8195 bnxt_hwrm_set_link_common(bp, &req);
8198 bnxt_hwrm_set_eee(bp, &req);
8199 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
8202 static int bnxt_hwrm_shutdown_link(struct bnxt *bp)
8204 struct hwrm_port_phy_cfg_input req = {0};
8206 if (!BNXT_SINGLE_PF(bp))
8209 if (pci_num_vf(bp->pdev))
8212 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1);
8213 req.flags = cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_FORCE_LINK_DWN);
8214 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
8217 static int bnxt_hwrm_if_change(struct bnxt *bp, bool up)
8219 struct hwrm_func_drv_if_change_output *resp = bp->hwrm_cmd_resp_addr;
8220 struct hwrm_func_drv_if_change_input req = {0};
8221 bool resc_reinit = false;
8224 if (!(bp->fw_cap & BNXT_FW_CAP_IF_CHANGE))
8227 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_IF_CHANGE, -1, -1);
8229 req.flags = cpu_to_le32(FUNC_DRV_IF_CHANGE_REQ_FLAGS_UP);
8230 mutex_lock(&bp->hwrm_cmd_lock);
8231 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
8232 if (!rc && (resp->flags &
8233 cpu_to_le32(FUNC_DRV_IF_CHANGE_RESP_FLAGS_RESC_CHANGE)))
8235 mutex_unlock(&bp->hwrm_cmd_lock);
8237 if (up && resc_reinit && BNXT_NEW_RM(bp)) {
8238 struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
8240 rc = bnxt_hwrm_func_resc_qcaps(bp, true);
8241 hw_resc->resv_cp_rings = 0;
8242 hw_resc->resv_stat_ctxs = 0;
8243 hw_resc->resv_irqs = 0;
8244 hw_resc->resv_tx_rings = 0;
8245 hw_resc->resv_rx_rings = 0;
8246 hw_resc->resv_hw_ring_grps = 0;
8247 hw_resc->resv_vnics = 0;
8248 bp->tx_nr_rings = 0;
8249 bp->rx_nr_rings = 0;
8254 static int bnxt_hwrm_port_led_qcaps(struct bnxt *bp)
8256 struct hwrm_port_led_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
8257 struct hwrm_port_led_qcaps_input req = {0};
8258 struct bnxt_pf_info *pf = &bp->pf;
8261 if (BNXT_VF(bp) || bp->hwrm_spec_code < 0x10601)
8264 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_LED_QCAPS, -1, -1);
8265 req.port_id = cpu_to_le16(pf->port_id);
8266 mutex_lock(&bp->hwrm_cmd_lock);
8267 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
8269 mutex_unlock(&bp->hwrm_cmd_lock);
8272 if (resp->num_leds > 0 && resp->num_leds < BNXT_MAX_LED) {
8275 bp->num_leds = resp->num_leds;
8276 memcpy(bp->leds, &resp->led0_id, sizeof(bp->leds[0]) *
8278 for (i = 0; i < bp->num_leds; i++) {
8279 struct bnxt_led_info *led = &bp->leds[i];
8280 __le16 caps = led->led_state_caps;
8282 if (!led->led_group_id ||
8283 !BNXT_LED_ALT_BLINK_CAP(caps)) {
8289 mutex_unlock(&bp->hwrm_cmd_lock);
8293 int bnxt_hwrm_alloc_wol_fltr(struct bnxt *bp)
8295 struct hwrm_wol_filter_alloc_input req = {0};
8296 struct hwrm_wol_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
8299 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_WOL_FILTER_ALLOC, -1, -1);
8300 req.port_id = cpu_to_le16(bp->pf.port_id);
8301 req.wol_type = WOL_FILTER_ALLOC_REQ_WOL_TYPE_MAGICPKT;
8302 req.enables = cpu_to_le32(WOL_FILTER_ALLOC_REQ_ENABLES_MAC_ADDRESS);
8303 memcpy(req.mac_address, bp->dev->dev_addr, ETH_ALEN);
8304 mutex_lock(&bp->hwrm_cmd_lock);
8305 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
8307 bp->wol_filter_id = resp->wol_filter_id;
8308 mutex_unlock(&bp->hwrm_cmd_lock);
8312 int bnxt_hwrm_free_wol_fltr(struct bnxt *bp)
8314 struct hwrm_wol_filter_free_input req = {0};
8317 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_WOL_FILTER_FREE, -1, -1);
8318 req.port_id = cpu_to_le16(bp->pf.port_id);
8319 req.enables = cpu_to_le32(WOL_FILTER_FREE_REQ_ENABLES_WOL_FILTER_ID);
8320 req.wol_filter_id = bp->wol_filter_id;
8321 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
8325 static u16 bnxt_hwrm_get_wol_fltrs(struct bnxt *bp, u16 handle)
8327 struct hwrm_wol_filter_qcfg_input req = {0};
8328 struct hwrm_wol_filter_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
8329 u16 next_handle = 0;
8332 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_WOL_FILTER_QCFG, -1, -1);
8333 req.port_id = cpu_to_le16(bp->pf.port_id);
8334 req.handle = cpu_to_le16(handle);
8335 mutex_lock(&bp->hwrm_cmd_lock);
8336 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
8338 next_handle = le16_to_cpu(resp->next_handle);
8339 if (next_handle != 0) {
8340 if (resp->wol_type ==
8341 WOL_FILTER_ALLOC_REQ_WOL_TYPE_MAGICPKT) {
8343 bp->wol_filter_id = resp->wol_filter_id;
8347 mutex_unlock(&bp->hwrm_cmd_lock);
8351 static void bnxt_get_wol_settings(struct bnxt *bp)
8355 if (!BNXT_PF(bp) || !(bp->flags & BNXT_FLAG_WOL_CAP))
8359 handle = bnxt_hwrm_get_wol_fltrs(bp, handle);
8360 } while (handle && handle != 0xffff);
8363 #ifdef CONFIG_BNXT_HWMON
8364 static ssize_t bnxt_show_temp(struct device *dev,
8365 struct device_attribute *devattr, char *buf)
8367 struct hwrm_temp_monitor_query_input req = {0};
8368 struct hwrm_temp_monitor_query_output *resp;
8369 struct bnxt *bp = dev_get_drvdata(dev);
8372 resp = bp->hwrm_cmd_resp_addr;
8373 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_TEMP_MONITOR_QUERY, -1, -1);
8374 mutex_lock(&bp->hwrm_cmd_lock);
8375 if (!_hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT))
8376 temp = resp->temp * 1000; /* display millidegree */
8377 mutex_unlock(&bp->hwrm_cmd_lock);
8379 return sprintf(buf, "%u\n", temp);
8381 static SENSOR_DEVICE_ATTR(temp1_input, 0444, bnxt_show_temp, NULL, 0);
8383 static struct attribute *bnxt_attrs[] = {
8384 &sensor_dev_attr_temp1_input.dev_attr.attr,
8387 ATTRIBUTE_GROUPS(bnxt);
8389 static void bnxt_hwmon_close(struct bnxt *bp)
8391 if (bp->hwmon_dev) {
8392 hwmon_device_unregister(bp->hwmon_dev);
8393 bp->hwmon_dev = NULL;
8397 static void bnxt_hwmon_open(struct bnxt *bp)
8399 struct pci_dev *pdev = bp->pdev;
8401 bp->hwmon_dev = hwmon_device_register_with_groups(&pdev->dev,
8402 DRV_MODULE_NAME, bp,
8404 if (IS_ERR(bp->hwmon_dev)) {
8405 bp->hwmon_dev = NULL;
8406 dev_warn(&pdev->dev, "Cannot register hwmon device\n");
8410 static void bnxt_hwmon_close(struct bnxt *bp)
8414 static void bnxt_hwmon_open(struct bnxt *bp)
8419 static bool bnxt_eee_config_ok(struct bnxt *bp)
8421 struct ethtool_eee *eee = &bp->eee;
8422 struct bnxt_link_info *link_info = &bp->link_info;
8424 if (!(bp->flags & BNXT_FLAG_EEE_CAP))
8427 if (eee->eee_enabled) {
8429 _bnxt_fw_to_ethtool_adv_spds(link_info->advertising, 0);
8431 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) {
8432 eee->eee_enabled = 0;
8435 if (eee->advertised & ~advertising) {
8436 eee->advertised = advertising & eee->supported;
8443 static int bnxt_update_phy_setting(struct bnxt *bp)
8446 bool update_link = false;
8447 bool update_pause = false;
8448 bool update_eee = false;
8449 struct bnxt_link_info *link_info = &bp->link_info;
8451 rc = bnxt_update_link(bp, true);
8453 netdev_err(bp->dev, "failed to update link (rc: %x)\n",
8457 if (!BNXT_SINGLE_PF(bp))
8460 if ((link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) &&
8461 (link_info->auto_pause_setting & BNXT_LINK_PAUSE_BOTH) !=
8462 link_info->req_flow_ctrl)
8463 update_pause = true;
8464 if (!(link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) &&
8465 link_info->force_pause_setting != link_info->req_flow_ctrl)
8466 update_pause = true;
8467 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) {
8468 if (BNXT_AUTO_MODE(link_info->auto_mode))
8470 if (link_info->req_link_speed != link_info->force_link_speed)
8472 if (link_info->req_duplex != link_info->duplex_setting)
8475 if (link_info->auto_mode == BNXT_LINK_AUTO_NONE)
8477 if (link_info->advertising != link_info->auto_link_speeds)
8481 /* The last close may have shutdown the link, so need to call
8482 * PHY_CFG to bring it back up.
8484 if (!netif_carrier_ok(bp->dev))
8487 if (!bnxt_eee_config_ok(bp))
8491 rc = bnxt_hwrm_set_link_setting(bp, update_pause, update_eee);
8492 else if (update_pause)
8493 rc = bnxt_hwrm_set_pause(bp);
8495 netdev_err(bp->dev, "failed to update phy setting (rc: %x)\n",
8503 /* Common routine to pre-map certain register block to different GRC window.
8504 * A PF has 16 4K windows and a VF has 4 4K windows. However, only 15 windows
8505 * in PF and 3 windows in VF that can be customized to map in different
8508 static void bnxt_preset_reg_win(struct bnxt *bp)
8511 /* CAG registers map to GRC window #4 */
8512 writel(BNXT_CAG_REG_BASE,
8513 bp->bar0 + BNXT_GRCPF_REG_WINDOW_BASE_OUT + 12);
8517 static int bnxt_init_dflt_ring_mode(struct bnxt *bp);
8519 static int __bnxt_open_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init)
8523 bnxt_preset_reg_win(bp);
8524 netif_carrier_off(bp->dev);
8526 /* Reserve rings now if none were reserved at driver probe. */
8527 rc = bnxt_init_dflt_ring_mode(bp);
8529 netdev_err(bp->dev, "Failed to reserve default rings at open\n");
8533 rc = bnxt_reserve_rings(bp);
8536 if ((bp->flags & BNXT_FLAG_RFS) &&
8537 !(bp->flags & BNXT_FLAG_USING_MSIX)) {
8538 /* disable RFS if falling back to INTA */
8539 bp->dev->hw_features &= ~NETIF_F_NTUPLE;
8540 bp->flags &= ~BNXT_FLAG_RFS;
8543 rc = bnxt_alloc_mem(bp, irq_re_init);
8545 netdev_err(bp->dev, "bnxt_alloc_mem err: %x\n", rc);
8546 goto open_err_free_mem;
8551 rc = bnxt_request_irq(bp);
8553 netdev_err(bp->dev, "bnxt_request_irq err: %x\n", rc);
8558 bnxt_enable_napi(bp);
8559 bnxt_debug_dev_init(bp);
8561 rc = bnxt_init_nic(bp, irq_re_init);
8563 netdev_err(bp->dev, "bnxt_init_nic err: %x\n", rc);
8568 mutex_lock(&bp->link_lock);
8569 rc = bnxt_update_phy_setting(bp);
8570 mutex_unlock(&bp->link_lock);
8572 netdev_warn(bp->dev, "failed to update phy settings\n");
8573 if (BNXT_SINGLE_PF(bp)) {
8574 bp->link_info.phy_retry = true;
8575 bp->link_info.phy_retry_expires =
8582 udp_tunnel_get_rx_info(bp->dev);
8584 set_bit(BNXT_STATE_OPEN, &bp->state);
8585 bnxt_enable_int(bp);
8586 /* Enable TX queues */
8588 mod_timer(&bp->timer, jiffies + bp->current_interval);
8589 /* Poll link status and check for SFP+ module status */
8590 bnxt_get_port_module_status(bp);
8592 /* VF-reps may need to be re-opened after the PF is re-opened */
8594 bnxt_vf_reps_open(bp);
8598 bnxt_debug_dev_exit(bp);
8599 bnxt_disable_napi(bp);
8607 bnxt_free_mem(bp, true);
8611 /* rtnl_lock held */
8612 int bnxt_open_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init)
8616 rc = __bnxt_open_nic(bp, irq_re_init, link_re_init);
8618 netdev_err(bp->dev, "nic open fail (rc: %x)\n", rc);
8624 /* rtnl_lock held, open the NIC half way by allocating all resources, but
8625 * NAPI, IRQ, and TX are not enabled. This is mainly used for offline
8628 int bnxt_half_open_nic(struct bnxt *bp)
8632 rc = bnxt_alloc_mem(bp, false);
8634 netdev_err(bp->dev, "bnxt_alloc_mem err: %x\n", rc);
8637 rc = bnxt_init_nic(bp, false);
8639 netdev_err(bp->dev, "bnxt_init_nic err: %x\n", rc);
8646 bnxt_free_mem(bp, false);
8651 /* rtnl_lock held, this call can only be made after a previous successful
8652 * call to bnxt_half_open_nic().
8654 void bnxt_half_close_nic(struct bnxt *bp)
8656 bnxt_hwrm_resource_free(bp, false, false);
8658 bnxt_free_mem(bp, false);
8661 static int bnxt_open(struct net_device *dev)
8663 struct bnxt *bp = netdev_priv(dev);
8666 bnxt_hwrm_if_change(bp, true);
8667 rc = __bnxt_open_nic(bp, true, true);
8669 bnxt_hwrm_if_change(bp, false);
8671 bnxt_hwmon_open(bp);
8676 static bool bnxt_drv_busy(struct bnxt *bp)
8678 return (test_bit(BNXT_STATE_IN_SP_TASK, &bp->state) ||
8679 test_bit(BNXT_STATE_READ_STATS, &bp->state));
8682 static void bnxt_get_ring_stats(struct bnxt *bp,
8683 struct rtnl_link_stats64 *stats);
8685 static void __bnxt_close_nic(struct bnxt *bp, bool irq_re_init,
8688 /* Close the VF-reps before closing PF */
8690 bnxt_vf_reps_close(bp);
8692 /* Change device state to avoid TX queue wake up's */
8693 bnxt_tx_disable(bp);
8695 clear_bit(BNXT_STATE_OPEN, &bp->state);
8696 smp_mb__after_atomic();
8697 while (bnxt_drv_busy(bp))
8700 /* Flush rings and and disable interrupts */
8701 bnxt_shutdown_nic(bp, irq_re_init);
8703 /* TODO CHIMP_FW: Link/PHY related cleanup if (link_re_init) */
8705 bnxt_debug_dev_exit(bp);
8706 bnxt_disable_napi(bp);
8707 del_timer_sync(&bp->timer);
8710 /* Save ring stats before shutdown */
8712 bnxt_get_ring_stats(bp, &bp->net_stats_prev);
8717 bnxt_free_mem(bp, irq_re_init);
8720 int bnxt_close_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init)
8724 #ifdef CONFIG_BNXT_SRIOV
8725 if (bp->sriov_cfg) {
8726 rc = wait_event_interruptible_timeout(bp->sriov_cfg_wait,
8728 BNXT_SRIOV_CFG_WAIT_TMO);
8730 netdev_warn(bp->dev, "timeout waiting for SRIOV config operation to complete!\n");
8733 __bnxt_close_nic(bp, irq_re_init, link_re_init);
8737 static int bnxt_close(struct net_device *dev)
8739 struct bnxt *bp = netdev_priv(dev);
8741 bnxt_hwmon_close(bp);
8742 bnxt_close_nic(bp, true, true);
8743 bnxt_hwrm_shutdown_link(bp);
8744 bnxt_hwrm_if_change(bp, false);
8748 static int bnxt_hwrm_port_phy_read(struct bnxt *bp, u16 phy_addr, u16 reg,
8751 struct hwrm_port_phy_mdio_read_output *resp = bp->hwrm_cmd_resp_addr;
8752 struct hwrm_port_phy_mdio_read_input req = {0};
8755 if (bp->hwrm_spec_code < 0x10a00)
8758 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_MDIO_READ, -1, -1);
8759 req.port_id = cpu_to_le16(bp->pf.port_id);
8760 req.phy_addr = phy_addr;
8761 req.reg_addr = cpu_to_le16(reg & 0x1f);
8762 if (mdio_phy_id_is_c45(phy_addr)) {
8764 req.phy_addr = mdio_phy_id_prtad(phy_addr);
8765 req.dev_addr = mdio_phy_id_devad(phy_addr);
8766 req.reg_addr = cpu_to_le16(reg);
8769 mutex_lock(&bp->hwrm_cmd_lock);
8770 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
8772 *val = le16_to_cpu(resp->reg_data);
8773 mutex_unlock(&bp->hwrm_cmd_lock);
8777 static int bnxt_hwrm_port_phy_write(struct bnxt *bp, u16 phy_addr, u16 reg,
8780 struct hwrm_port_phy_mdio_write_input req = {0};
8782 if (bp->hwrm_spec_code < 0x10a00)
8785 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_MDIO_WRITE, -1, -1);
8786 req.port_id = cpu_to_le16(bp->pf.port_id);
8787 req.phy_addr = phy_addr;
8788 req.reg_addr = cpu_to_le16(reg & 0x1f);
8789 if (mdio_phy_id_is_c45(phy_addr)) {
8791 req.phy_addr = mdio_phy_id_prtad(phy_addr);
8792 req.dev_addr = mdio_phy_id_devad(phy_addr);
8793 req.reg_addr = cpu_to_le16(reg);
8795 req.reg_data = cpu_to_le16(val);
8797 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
8800 /* rtnl_lock held */
8801 static int bnxt_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
8803 struct mii_ioctl_data *mdio = if_mii(ifr);
8804 struct bnxt *bp = netdev_priv(dev);
8809 mdio->phy_id = bp->link_info.phy_addr;
8815 if (!netif_running(dev))
8818 rc = bnxt_hwrm_port_phy_read(bp, mdio->phy_id, mdio->reg_num,
8820 mdio->val_out = mii_regval;
8825 if (!netif_running(dev))
8828 return bnxt_hwrm_port_phy_write(bp, mdio->phy_id, mdio->reg_num,
8838 static void bnxt_get_ring_stats(struct bnxt *bp,
8839 struct rtnl_link_stats64 *stats)
8844 for (i = 0; i < bp->cp_nr_rings; i++) {
8845 struct bnxt_napi *bnapi = bp->bnapi[i];
8846 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
8847 struct ctx_hw_stats *hw_stats = cpr->hw_stats;
8849 stats->rx_packets += le64_to_cpu(hw_stats->rx_ucast_pkts);
8850 stats->rx_packets += le64_to_cpu(hw_stats->rx_mcast_pkts);
8851 stats->rx_packets += le64_to_cpu(hw_stats->rx_bcast_pkts);
8853 stats->tx_packets += le64_to_cpu(hw_stats->tx_ucast_pkts);
8854 stats->tx_packets += le64_to_cpu(hw_stats->tx_mcast_pkts);
8855 stats->tx_packets += le64_to_cpu(hw_stats->tx_bcast_pkts);
8857 stats->rx_bytes += le64_to_cpu(hw_stats->rx_ucast_bytes);
8858 stats->rx_bytes += le64_to_cpu(hw_stats->rx_mcast_bytes);
8859 stats->rx_bytes += le64_to_cpu(hw_stats->rx_bcast_bytes);
8861 stats->tx_bytes += le64_to_cpu(hw_stats->tx_ucast_bytes);
8862 stats->tx_bytes += le64_to_cpu(hw_stats->tx_mcast_bytes);
8863 stats->tx_bytes += le64_to_cpu(hw_stats->tx_bcast_bytes);
8865 stats->rx_missed_errors +=
8866 le64_to_cpu(hw_stats->rx_discard_pkts);
8868 stats->multicast += le64_to_cpu(hw_stats->rx_mcast_pkts);
8870 stats->tx_dropped += le64_to_cpu(hw_stats->tx_drop_pkts);
8874 static void bnxt_add_prev_stats(struct bnxt *bp,
8875 struct rtnl_link_stats64 *stats)
8877 struct rtnl_link_stats64 *prev_stats = &bp->net_stats_prev;
8879 stats->rx_packets += prev_stats->rx_packets;
8880 stats->tx_packets += prev_stats->tx_packets;
8881 stats->rx_bytes += prev_stats->rx_bytes;
8882 stats->tx_bytes += prev_stats->tx_bytes;
8883 stats->rx_missed_errors += prev_stats->rx_missed_errors;
8884 stats->multicast += prev_stats->multicast;
8885 stats->tx_dropped += prev_stats->tx_dropped;
8889 bnxt_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
8891 struct bnxt *bp = netdev_priv(dev);
8893 set_bit(BNXT_STATE_READ_STATS, &bp->state);
8894 /* Make sure bnxt_close_nic() sees that we are reading stats before
8895 * we check the BNXT_STATE_OPEN flag.
8897 smp_mb__after_atomic();
8898 if (!test_bit(BNXT_STATE_OPEN, &bp->state)) {
8899 clear_bit(BNXT_STATE_READ_STATS, &bp->state);
8900 *stats = bp->net_stats_prev;
8904 bnxt_get_ring_stats(bp, stats);
8905 bnxt_add_prev_stats(bp, stats);
8907 if (bp->flags & BNXT_FLAG_PORT_STATS) {
8908 struct rx_port_stats *rx = bp->hw_rx_port_stats;
8909 struct tx_port_stats *tx = bp->hw_tx_port_stats;
8911 stats->rx_crc_errors = le64_to_cpu(rx->rx_fcs_err_frames);
8912 stats->rx_frame_errors = le64_to_cpu(rx->rx_align_err_frames);
8913 stats->rx_length_errors = le64_to_cpu(rx->rx_undrsz_frames) +
8914 le64_to_cpu(rx->rx_ovrsz_frames) +
8915 le64_to_cpu(rx->rx_runt_frames);
8916 stats->rx_errors = le64_to_cpu(rx->rx_false_carrier_frames) +
8917 le64_to_cpu(rx->rx_jbr_frames);
8918 stats->collisions = le64_to_cpu(tx->tx_total_collisions);
8919 stats->tx_fifo_errors = le64_to_cpu(tx->tx_fifo_underruns);
8920 stats->tx_errors = le64_to_cpu(tx->tx_err);
8922 clear_bit(BNXT_STATE_READ_STATS, &bp->state);
8925 static bool bnxt_mc_list_updated(struct bnxt *bp, u32 *rx_mask)
8927 struct net_device *dev = bp->dev;
8928 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
8929 struct netdev_hw_addr *ha;
8932 bool update = false;
8935 netdev_for_each_mc_addr(ha, dev) {
8936 if (mc_count >= BNXT_MAX_MC_ADDRS) {
8937 *rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST;
8938 vnic->mc_list_count = 0;
8942 if (!ether_addr_equal(haddr, vnic->mc_list + off)) {
8943 memcpy(vnic->mc_list + off, haddr, ETH_ALEN);
8950 *rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_MCAST;
8952 if (mc_count != vnic->mc_list_count) {
8953 vnic->mc_list_count = mc_count;
8959 static bool bnxt_uc_list_updated(struct bnxt *bp)
8961 struct net_device *dev = bp->dev;
8962 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
8963 struct netdev_hw_addr *ha;
8966 if (netdev_uc_count(dev) != (vnic->uc_filter_count - 1))
8969 netdev_for_each_uc_addr(ha, dev) {
8970 if (!ether_addr_equal(ha->addr, vnic->uc_list + off))
8978 static void bnxt_set_rx_mode(struct net_device *dev)
8980 struct bnxt *bp = netdev_priv(dev);
8981 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
8982 u32 mask = vnic->rx_mask;
8983 bool mc_update = false;
8986 if (!netif_running(dev))
8989 mask &= ~(CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS |
8990 CFA_L2_SET_RX_MASK_REQ_MASK_MCAST |
8991 CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST |
8992 CFA_L2_SET_RX_MASK_REQ_MASK_BCAST);
8994 if ((dev->flags & IFF_PROMISC) && bnxt_promisc_ok(bp))
8995 mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS;
8997 uc_update = bnxt_uc_list_updated(bp);
8999 if (dev->flags & IFF_BROADCAST)
9000 mask |= CFA_L2_SET_RX_MASK_REQ_MASK_BCAST;
9001 if (dev->flags & IFF_ALLMULTI) {
9002 mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST;
9003 vnic->mc_list_count = 0;
9005 mc_update = bnxt_mc_list_updated(bp, &mask);
9008 if (mask != vnic->rx_mask || uc_update || mc_update) {
9009 vnic->rx_mask = mask;
9011 set_bit(BNXT_RX_MASK_SP_EVENT, &bp->sp_event);
9012 bnxt_queue_sp_work(bp);
9016 static int bnxt_cfg_rx_mode(struct bnxt *bp)
9018 struct net_device *dev = bp->dev;
9019 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
9020 struct netdev_hw_addr *ha;
9024 netif_addr_lock_bh(dev);
9025 uc_update = bnxt_uc_list_updated(bp);
9026 netif_addr_unlock_bh(dev);
9031 mutex_lock(&bp->hwrm_cmd_lock);
9032 for (i = 1; i < vnic->uc_filter_count; i++) {
9033 struct hwrm_cfa_l2_filter_free_input req = {0};
9035 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_FILTER_FREE, -1,
9038 req.l2_filter_id = vnic->fw_l2_filter_id[i];
9040 rc = _hwrm_send_message(bp, &req, sizeof(req),
9043 mutex_unlock(&bp->hwrm_cmd_lock);
9045 vnic->uc_filter_count = 1;
9047 netif_addr_lock_bh(dev);
9048 if (netdev_uc_count(dev) > (BNXT_MAX_UC_ADDRS - 1)) {
9049 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS;
9051 netdev_for_each_uc_addr(ha, dev) {
9052 memcpy(vnic->uc_list + off, ha->addr, ETH_ALEN);
9054 vnic->uc_filter_count++;
9057 netif_addr_unlock_bh(dev);
9059 for (i = 1, off = 0; i < vnic->uc_filter_count; i++, off += ETH_ALEN) {
9060 rc = bnxt_hwrm_set_vnic_filter(bp, 0, i, vnic->uc_list + off);
9062 netdev_err(bp->dev, "HWRM vnic filter failure rc: %x\n",
9064 vnic->uc_filter_count = i;
9070 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, 0);
9071 if (rc && vnic->mc_list_count) {
9072 netdev_info(bp->dev, "Failed setting MC filters rc: %d, turning on ALL_MCAST mode\n",
9074 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST;
9075 vnic->mc_list_count = 0;
9076 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, 0);
9079 netdev_err(bp->dev, "HWRM cfa l2 rx mask failure rc: %d\n",
9085 static bool bnxt_can_reserve_rings(struct bnxt *bp)
9087 #ifdef CONFIG_BNXT_SRIOV
9088 if (BNXT_NEW_RM(bp) && BNXT_VF(bp)) {
9089 struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
9091 /* No minimum rings were provisioned by the PF. Don't
9092 * reserve rings by default when device is down.
9094 if (hw_resc->min_tx_rings || hw_resc->resv_tx_rings)
9097 if (!netif_running(bp->dev))
9104 /* If the chip and firmware supports RFS */
9105 static bool bnxt_rfs_supported(struct bnxt *bp)
9107 if (bp->flags & BNXT_FLAG_CHIP_P5) {
9108 if (bp->fw_cap & BNXT_FW_CAP_CFA_RFS_RING_TBL_IDX)
9112 if (BNXT_PF(bp) && !BNXT_CHIP_TYPE_NITRO_A0(bp))
9114 if (bp->flags & BNXT_FLAG_NEW_RSS_CAP)
9119 /* If runtime conditions support RFS */
9120 static bool bnxt_rfs_capable(struct bnxt *bp)
9122 #ifdef CONFIG_RFS_ACCEL
9123 int vnics, max_vnics, max_rss_ctxs;
9125 if (bp->flags & BNXT_FLAG_CHIP_P5)
9126 return bnxt_rfs_supported(bp);
9127 if (!(bp->flags & BNXT_FLAG_MSIX_CAP) || !bnxt_can_reserve_rings(bp))
9130 vnics = 1 + bp->rx_nr_rings;
9131 max_vnics = bnxt_get_max_func_vnics(bp);
9132 max_rss_ctxs = bnxt_get_max_func_rss_ctxs(bp);
9134 /* RSS contexts not a limiting factor */
9135 if (bp->flags & BNXT_FLAG_NEW_RSS_CAP)
9136 max_rss_ctxs = max_vnics;
9137 if (vnics > max_vnics || vnics > max_rss_ctxs) {
9138 if (bp->rx_nr_rings > 1)
9139 netdev_warn(bp->dev,
9140 "Not enough resources to support NTUPLE filters, enough resources for up to %d rx rings\n",
9141 min(max_rss_ctxs - 1, max_vnics - 1));
9145 if (!BNXT_NEW_RM(bp))
9148 if (vnics == bp->hw_resc.resv_vnics)
9151 bnxt_hwrm_reserve_rings(bp, 0, 0, 0, 0, 0, vnics);
9152 if (vnics <= bp->hw_resc.resv_vnics)
9155 netdev_warn(bp->dev, "Unable to reserve resources to support NTUPLE filters.\n");
9156 bnxt_hwrm_reserve_rings(bp, 0, 0, 0, 0, 0, 1);
9163 static netdev_features_t bnxt_fix_features(struct net_device *dev,
9164 netdev_features_t features)
9166 struct bnxt *bp = netdev_priv(dev);
9168 if ((features & NETIF_F_NTUPLE) && !bnxt_rfs_capable(bp))
9169 features &= ~NETIF_F_NTUPLE;
9171 if (bp->flags & BNXT_FLAG_NO_AGG_RINGS)
9172 features &= ~(NETIF_F_LRO | NETIF_F_GRO_HW);
9174 if (!(features & NETIF_F_GRO))
9175 features &= ~NETIF_F_GRO_HW;
9177 if (features & NETIF_F_GRO_HW)
9178 features &= ~NETIF_F_LRO;
9180 /* Both CTAG and STAG VLAN accelaration on the RX side have to be
9181 * turned on or off together.
9183 if ((features & (NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_STAG_RX)) !=
9184 (NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_STAG_RX)) {
9185 if (dev->features & NETIF_F_HW_VLAN_CTAG_RX)
9186 features &= ~(NETIF_F_HW_VLAN_CTAG_RX |
9187 NETIF_F_HW_VLAN_STAG_RX);
9189 features |= NETIF_F_HW_VLAN_CTAG_RX |
9190 NETIF_F_HW_VLAN_STAG_RX;
9192 #ifdef CONFIG_BNXT_SRIOV
9195 features &= ~(NETIF_F_HW_VLAN_CTAG_RX |
9196 NETIF_F_HW_VLAN_STAG_RX);
9203 static int bnxt_set_features(struct net_device *dev, netdev_features_t features)
9205 struct bnxt *bp = netdev_priv(dev);
9206 u32 flags = bp->flags;
9209 bool re_init = false;
9210 bool update_tpa = false;
9212 flags &= ~BNXT_FLAG_ALL_CONFIG_FEATS;
9213 if (features & NETIF_F_GRO_HW)
9214 flags |= BNXT_FLAG_GRO;
9215 else if (features & NETIF_F_LRO)
9216 flags |= BNXT_FLAG_LRO;
9218 if (bp->flags & BNXT_FLAG_NO_AGG_RINGS)
9219 flags &= ~BNXT_FLAG_TPA;
9221 if (features & NETIF_F_HW_VLAN_CTAG_RX)
9222 flags |= BNXT_FLAG_STRIP_VLAN;
9224 if (features & NETIF_F_NTUPLE)
9225 flags |= BNXT_FLAG_RFS;
9227 changes = flags ^ bp->flags;
9228 if (changes & BNXT_FLAG_TPA) {
9230 if ((bp->flags & BNXT_FLAG_TPA) == 0 ||
9231 (flags & BNXT_FLAG_TPA) == 0)
9235 if (changes & ~BNXT_FLAG_TPA)
9238 if (flags != bp->flags) {
9239 u32 old_flags = bp->flags;
9243 if (!test_bit(BNXT_STATE_OPEN, &bp->state)) {
9245 bnxt_set_ring_params(bp);
9250 bnxt_close_nic(bp, false, false);
9252 bnxt_set_ring_params(bp);
9254 return bnxt_open_nic(bp, false, false);
9257 rc = bnxt_set_tpa(bp,
9258 (flags & BNXT_FLAG_TPA) ?
9261 bp->flags = old_flags;
9267 static int bnxt_dbg_hwrm_ring_info_get(struct bnxt *bp, u8 ring_type,
9268 u32 ring_id, u32 *prod, u32 *cons)
9270 struct hwrm_dbg_ring_info_get_output *resp = bp->hwrm_cmd_resp_addr;
9271 struct hwrm_dbg_ring_info_get_input req = {0};
9274 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_DBG_RING_INFO_GET, -1, -1);
9275 req.ring_type = ring_type;
9276 req.fw_ring_id = cpu_to_le32(ring_id);
9277 mutex_lock(&bp->hwrm_cmd_lock);
9278 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
9280 *prod = le32_to_cpu(resp->producer_index);
9281 *cons = le32_to_cpu(resp->consumer_index);
9283 mutex_unlock(&bp->hwrm_cmd_lock);
9287 static void bnxt_dump_tx_sw_state(struct bnxt_napi *bnapi)
9289 struct bnxt_tx_ring_info *txr = bnapi->tx_ring;
9290 int i = bnapi->index;
9295 netdev_info(bnapi->bp->dev, "[%d]: tx{fw_ring: %d prod: %x cons: %x}\n",
9296 i, txr->tx_ring_struct.fw_ring_id, txr->tx_prod,
9300 static void bnxt_dump_rx_sw_state(struct bnxt_napi *bnapi)
9302 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
9303 int i = bnapi->index;
9308 netdev_info(bnapi->bp->dev, "[%d]: rx{fw_ring: %d prod: %x} rx_agg{fw_ring: %d agg_prod: %x sw_agg_prod: %x}\n",
9309 i, rxr->rx_ring_struct.fw_ring_id, rxr->rx_prod,
9310 rxr->rx_agg_ring_struct.fw_ring_id, rxr->rx_agg_prod,
9311 rxr->rx_sw_agg_prod);
9314 static void bnxt_dump_cp_sw_state(struct bnxt_napi *bnapi)
9316 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
9317 int i = bnapi->index;
9319 netdev_info(bnapi->bp->dev, "[%d]: cp{fw_ring: %d raw_cons: %x}\n",
9320 i, cpr->cp_ring_struct.fw_ring_id, cpr->cp_raw_cons);
9323 static void bnxt_dbg_dump_states(struct bnxt *bp)
9326 struct bnxt_napi *bnapi;
9328 for (i = 0; i < bp->cp_nr_rings; i++) {
9329 bnapi = bp->bnapi[i];
9330 if (netif_msg_drv(bp)) {
9331 bnxt_dump_tx_sw_state(bnapi);
9332 bnxt_dump_rx_sw_state(bnapi);
9333 bnxt_dump_cp_sw_state(bnapi);
9338 static void bnxt_reset_task(struct bnxt *bp, bool silent)
9341 bnxt_dbg_dump_states(bp);
9342 if (netif_running(bp->dev)) {
9347 bnxt_close_nic(bp, false, false);
9348 rc = bnxt_open_nic(bp, false, false);
9354 static void bnxt_tx_timeout(struct net_device *dev)
9356 struct bnxt *bp = netdev_priv(dev);
9358 netdev_err(bp->dev, "TX timeout detected, starting reset task!\n");
9359 set_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event);
9360 bnxt_queue_sp_work(bp);
9363 static void bnxt_timer(struct timer_list *t)
9365 struct bnxt *bp = from_timer(bp, t, timer);
9366 struct net_device *dev = bp->dev;
9368 if (!netif_running(dev))
9371 if (atomic_read(&bp->intr_sem) != 0)
9372 goto bnxt_restart_timer;
9374 if (bp->link_info.link_up && (bp->flags & BNXT_FLAG_PORT_STATS) &&
9375 bp->stats_coal_ticks) {
9376 set_bit(BNXT_PERIODIC_STATS_SP_EVENT, &bp->sp_event);
9377 bnxt_queue_sp_work(bp);
9380 if (bnxt_tc_flower_enabled(bp)) {
9381 set_bit(BNXT_FLOW_STATS_SP_EVENT, &bp->sp_event);
9382 bnxt_queue_sp_work(bp);
9385 if (bp->link_info.phy_retry) {
9386 if (time_after(jiffies, bp->link_info.phy_retry_expires)) {
9387 bp->link_info.phy_retry = 0;
9388 netdev_warn(bp->dev, "failed to update phy settings after maximum retries.\n");
9390 set_bit(BNXT_UPDATE_PHY_SP_EVENT, &bp->sp_event);
9391 bnxt_queue_sp_work(bp);
9395 if ((bp->flags & BNXT_FLAG_CHIP_P5) && netif_carrier_ok(dev)) {
9396 set_bit(BNXT_RING_COAL_NOW_SP_EVENT, &bp->sp_event);
9397 bnxt_queue_sp_work(bp);
9400 mod_timer(&bp->timer, jiffies + bp->current_interval);
9403 static void bnxt_rtnl_lock_sp(struct bnxt *bp)
9405 /* We are called from bnxt_sp_task which has BNXT_STATE_IN_SP_TASK
9406 * set. If the device is being closed, bnxt_close() may be holding
9407 * rtnl() and waiting for BNXT_STATE_IN_SP_TASK to clear. So we
9408 * must clear BNXT_STATE_IN_SP_TASK before holding rtnl().
9410 clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
9414 static void bnxt_rtnl_unlock_sp(struct bnxt *bp)
9416 set_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
9420 /* Only called from bnxt_sp_task() */
9421 static void bnxt_reset(struct bnxt *bp, bool silent)
9423 bnxt_rtnl_lock_sp(bp);
9424 if (test_bit(BNXT_STATE_OPEN, &bp->state))
9425 bnxt_reset_task(bp, silent);
9426 bnxt_rtnl_unlock_sp(bp);
9429 static void bnxt_chk_missed_irq(struct bnxt *bp)
9433 if (!(bp->flags & BNXT_FLAG_CHIP_P5))
9436 for (i = 0; i < bp->cp_nr_rings; i++) {
9437 struct bnxt_napi *bnapi = bp->bnapi[i];
9438 struct bnxt_cp_ring_info *cpr;
9445 cpr = &bnapi->cp_ring;
9446 for (j = 0; j < 2; j++) {
9447 struct bnxt_cp_ring_info *cpr2 = cpr->cp_ring_arr[j];
9450 if (!cpr2 || cpr2->has_more_work ||
9451 !bnxt_has_work(bp, cpr2))
9454 if (cpr2->cp_raw_cons != cpr2->last_cp_raw_cons) {
9455 cpr2->last_cp_raw_cons = cpr2->cp_raw_cons;
9458 fw_ring_id = cpr2->cp_ring_struct.fw_ring_id;
9459 bnxt_dbg_hwrm_ring_info_get(bp,
9460 DBG_RING_INFO_GET_REQ_RING_TYPE_L2_CMPL,
9461 fw_ring_id, &val[0], &val[1]);
9467 static void bnxt_cfg_ntp_filters(struct bnxt *);
9469 static void bnxt_sp_task(struct work_struct *work)
9471 struct bnxt *bp = container_of(work, struct bnxt, sp_task);
9473 set_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
9474 smp_mb__after_atomic();
9475 if (!test_bit(BNXT_STATE_OPEN, &bp->state)) {
9476 clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
9480 if (test_and_clear_bit(BNXT_RX_MASK_SP_EVENT, &bp->sp_event))
9481 bnxt_cfg_rx_mode(bp);
9483 if (test_and_clear_bit(BNXT_RX_NTP_FLTR_SP_EVENT, &bp->sp_event))
9484 bnxt_cfg_ntp_filters(bp);
9485 if (test_and_clear_bit(BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT, &bp->sp_event))
9486 bnxt_hwrm_exec_fwd_req(bp);
9487 if (test_and_clear_bit(BNXT_VXLAN_ADD_PORT_SP_EVENT, &bp->sp_event)) {
9488 bnxt_hwrm_tunnel_dst_port_alloc(
9490 TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN);
9492 if (test_and_clear_bit(BNXT_VXLAN_DEL_PORT_SP_EVENT, &bp->sp_event)) {
9493 bnxt_hwrm_tunnel_dst_port_free(
9494 bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN);
9496 if (test_and_clear_bit(BNXT_GENEVE_ADD_PORT_SP_EVENT, &bp->sp_event)) {
9497 bnxt_hwrm_tunnel_dst_port_alloc(
9499 TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE);
9501 if (test_and_clear_bit(BNXT_GENEVE_DEL_PORT_SP_EVENT, &bp->sp_event)) {
9502 bnxt_hwrm_tunnel_dst_port_free(
9503 bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE);
9505 if (test_and_clear_bit(BNXT_PERIODIC_STATS_SP_EVENT, &bp->sp_event)) {
9506 bnxt_hwrm_port_qstats(bp);
9507 bnxt_hwrm_port_qstats_ext(bp);
9508 bnxt_hwrm_pcie_qstats(bp);
9511 if (test_and_clear_bit(BNXT_LINK_CHNG_SP_EVENT, &bp->sp_event)) {
9514 mutex_lock(&bp->link_lock);
9515 if (test_and_clear_bit(BNXT_LINK_SPEED_CHNG_SP_EVENT,
9517 bnxt_hwrm_phy_qcaps(bp);
9519 rc = bnxt_update_link(bp, true);
9520 mutex_unlock(&bp->link_lock);
9522 netdev_err(bp->dev, "SP task can't update link (rc: %x)\n",
9525 if (test_and_clear_bit(BNXT_UPDATE_PHY_SP_EVENT, &bp->sp_event)) {
9528 mutex_lock(&bp->link_lock);
9529 rc = bnxt_update_phy_setting(bp);
9530 mutex_unlock(&bp->link_lock);
9532 netdev_warn(bp->dev, "update phy settings retry failed\n");
9534 bp->link_info.phy_retry = false;
9535 netdev_info(bp->dev, "update phy settings retry succeeded\n");
9538 if (test_and_clear_bit(BNXT_HWRM_PORT_MODULE_SP_EVENT, &bp->sp_event)) {
9539 mutex_lock(&bp->link_lock);
9540 bnxt_get_port_module_status(bp);
9541 mutex_unlock(&bp->link_lock);
9544 if (test_and_clear_bit(BNXT_FLOW_STATS_SP_EVENT, &bp->sp_event))
9545 bnxt_tc_flow_stats_work(bp);
9547 if (test_and_clear_bit(BNXT_RING_COAL_NOW_SP_EVENT, &bp->sp_event))
9548 bnxt_chk_missed_irq(bp);
9550 /* These functions below will clear BNXT_STATE_IN_SP_TASK. They
9551 * must be the last functions to be called before exiting.
9553 if (test_and_clear_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event))
9554 bnxt_reset(bp, false);
9556 if (test_and_clear_bit(BNXT_RESET_TASK_SILENT_SP_EVENT, &bp->sp_event))
9557 bnxt_reset(bp, true);
9559 smp_mb__before_atomic();
9560 clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
9563 /* Under rtnl_lock */
9564 int bnxt_check_rings(struct bnxt *bp, int tx, int rx, bool sh, int tcs,
9567 int max_rx, max_tx, tx_sets = 1;
9568 int tx_rings_needed, stats;
9575 rc = bnxt_get_max_rings(bp, &max_rx, &max_tx, sh);
9582 tx_rings_needed = tx * tx_sets + tx_xdp;
9583 if (max_tx < tx_rings_needed)
9587 if (bp->flags & BNXT_FLAG_RFS)
9590 if (bp->flags & BNXT_FLAG_AGG_RINGS)
9592 cp = sh ? max_t(int, tx_rings_needed, rx) : tx_rings_needed + rx;
9594 if (BNXT_NEW_RM(bp)) {
9595 cp += bnxt_get_ulp_msix_num(bp);
9596 stats += bnxt_get_ulp_stat_ctxs(bp);
9598 return bnxt_hwrm_check_rings(bp, tx_rings_needed, rx_rings, rx, cp,
9602 static void bnxt_unmap_bars(struct bnxt *bp, struct pci_dev *pdev)
9605 pci_iounmap(pdev, bp->bar2);
9610 pci_iounmap(pdev, bp->bar1);
9615 pci_iounmap(pdev, bp->bar0);
9620 static void bnxt_cleanup_pci(struct bnxt *bp)
9622 bnxt_unmap_bars(bp, bp->pdev);
9623 pci_release_regions(bp->pdev);
9624 pci_disable_device(bp->pdev);
9627 static void bnxt_init_dflt_coal(struct bnxt *bp)
9629 struct bnxt_coal *coal;
9631 /* Tick values in micro seconds.
9632 * 1 coal_buf x bufs_per_record = 1 completion record.
9634 coal = &bp->rx_coal;
9635 coal->coal_ticks = 10;
9636 coal->coal_bufs = 30;
9637 coal->coal_ticks_irq = 1;
9638 coal->coal_bufs_irq = 2;
9639 coal->idle_thresh = 50;
9640 coal->bufs_per_record = 2;
9641 coal->budget = 64; /* NAPI budget */
9643 coal = &bp->tx_coal;
9644 coal->coal_ticks = 28;
9645 coal->coal_bufs = 30;
9646 coal->coal_ticks_irq = 2;
9647 coal->coal_bufs_irq = 2;
9648 coal->bufs_per_record = 1;
9650 bp->stats_coal_ticks = BNXT_DEF_STATS_COAL_TICKS;
9653 static int bnxt_init_board(struct pci_dev *pdev, struct net_device *dev)
9656 struct bnxt *bp = netdev_priv(dev);
9658 SET_NETDEV_DEV(dev, &pdev->dev);
9660 /* enable device (incl. PCI PM wakeup), and bus-mastering */
9661 rc = pci_enable_device(pdev);
9663 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
9667 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
9669 "Cannot find PCI device base address, aborting\n");
9671 goto init_err_disable;
9674 rc = pci_request_regions(pdev, DRV_MODULE_NAME);
9676 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n");
9677 goto init_err_disable;
9680 if (dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)) != 0 &&
9681 dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)) != 0) {
9682 dev_err(&pdev->dev, "System does not support DMA, aborting\n");
9683 goto init_err_disable;
9686 pci_set_master(pdev);
9691 bp->bar0 = pci_ioremap_bar(pdev, 0);
9693 dev_err(&pdev->dev, "Cannot map device registers, aborting\n");
9695 goto init_err_release;
9698 bp->bar1 = pci_ioremap_bar(pdev, 2);
9700 dev_err(&pdev->dev, "Cannot map doorbell registers, aborting\n");
9702 goto init_err_release;
9705 bp->bar2 = pci_ioremap_bar(pdev, 4);
9707 dev_err(&pdev->dev, "Cannot map bar4 registers, aborting\n");
9709 goto init_err_release;
9712 pci_enable_pcie_error_reporting(pdev);
9714 INIT_WORK(&bp->sp_task, bnxt_sp_task);
9716 spin_lock_init(&bp->ntp_fltr_lock);
9717 #if BITS_PER_LONG == 32
9718 spin_lock_init(&bp->db_lock);
9721 bp->rx_ring_size = BNXT_DEFAULT_RX_RING_SIZE;
9722 bp->tx_ring_size = BNXT_DEFAULT_TX_RING_SIZE;
9724 bnxt_init_dflt_coal(bp);
9726 timer_setup(&bp->timer, bnxt_timer, 0);
9727 bp->current_interval = BNXT_TIMER_INTERVAL;
9729 clear_bit(BNXT_STATE_OPEN, &bp->state);
9733 bnxt_unmap_bars(bp, pdev);
9734 pci_release_regions(pdev);
9737 pci_disable_device(pdev);
9743 /* rtnl_lock held */
9744 static int bnxt_change_mac_addr(struct net_device *dev, void *p)
9746 struct sockaddr *addr = p;
9747 struct bnxt *bp = netdev_priv(dev);
9750 if (!is_valid_ether_addr(addr->sa_data))
9751 return -EADDRNOTAVAIL;
9753 if (ether_addr_equal(addr->sa_data, dev->dev_addr))
9756 rc = bnxt_approve_mac(bp, addr->sa_data, true);
9760 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
9761 if (netif_running(dev)) {
9762 bnxt_close_nic(bp, false, false);
9763 rc = bnxt_open_nic(bp, false, false);
9769 /* rtnl_lock held */
9770 static int bnxt_change_mtu(struct net_device *dev, int new_mtu)
9772 struct bnxt *bp = netdev_priv(dev);
9774 if (netif_running(dev))
9775 bnxt_close_nic(bp, false, false);
9778 bnxt_set_ring_params(bp);
9780 if (netif_running(dev))
9781 return bnxt_open_nic(bp, false, false);
9786 int bnxt_setup_mq_tc(struct net_device *dev, u8 tc)
9788 struct bnxt *bp = netdev_priv(dev);
9792 if (tc > bp->max_tc) {
9793 netdev_err(dev, "Too many traffic classes requested: %d. Max supported is %d.\n",
9798 if (netdev_get_num_tc(dev) == tc)
9801 if (bp->flags & BNXT_FLAG_SHARED_RINGS)
9804 rc = bnxt_check_rings(bp, bp->tx_nr_rings_per_tc, bp->rx_nr_rings,
9805 sh, tc, bp->tx_nr_rings_xdp);
9809 /* Needs to close the device and do hw resource re-allocations */
9810 if (netif_running(bp->dev))
9811 bnxt_close_nic(bp, true, false);
9814 bp->tx_nr_rings = bp->tx_nr_rings_per_tc * tc;
9815 netdev_set_num_tc(dev, tc);
9817 bp->tx_nr_rings = bp->tx_nr_rings_per_tc;
9818 netdev_reset_tc(dev);
9820 bp->tx_nr_rings += bp->tx_nr_rings_xdp;
9821 bp->cp_nr_rings = sh ? max_t(int, bp->tx_nr_rings, bp->rx_nr_rings) :
9822 bp->tx_nr_rings + bp->rx_nr_rings;
9824 if (netif_running(bp->dev))
9825 return bnxt_open_nic(bp, true, false);
9830 static int bnxt_setup_tc_block_cb(enum tc_setup_type type, void *type_data,
9833 struct bnxt *bp = cb_priv;
9835 if (!bnxt_tc_flower_enabled(bp) ||
9836 !tc_cls_can_offload_and_chain0(bp->dev, type_data))
9840 case TC_SETUP_CLSFLOWER:
9841 return bnxt_tc_setup_flower(bp, bp->pf.fw_fid, type_data);
9847 static int bnxt_setup_tc_block(struct net_device *dev,
9848 struct tc_block_offload *f)
9850 struct bnxt *bp = netdev_priv(dev);
9852 if (f->binder_type != TCF_BLOCK_BINDER_TYPE_CLSACT_INGRESS)
9855 switch (f->command) {
9857 return tcf_block_cb_register(f->block, bnxt_setup_tc_block_cb,
9859 case TC_BLOCK_UNBIND:
9860 tcf_block_cb_unregister(f->block, bnxt_setup_tc_block_cb, bp);
9867 static int bnxt_setup_tc(struct net_device *dev, enum tc_setup_type type,
9871 case TC_SETUP_BLOCK:
9872 return bnxt_setup_tc_block(dev, type_data);
9873 case TC_SETUP_QDISC_MQPRIO: {
9874 struct tc_mqprio_qopt *mqprio = type_data;
9876 mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS;
9878 return bnxt_setup_mq_tc(dev, mqprio->num_tc);
9885 #ifdef CONFIG_RFS_ACCEL
9886 static bool bnxt_fltr_match(struct bnxt_ntuple_filter *f1,
9887 struct bnxt_ntuple_filter *f2)
9889 struct flow_keys *keys1 = &f1->fkeys;
9890 struct flow_keys *keys2 = &f2->fkeys;
9892 if (keys1->addrs.v4addrs.src == keys2->addrs.v4addrs.src &&
9893 keys1->addrs.v4addrs.dst == keys2->addrs.v4addrs.dst &&
9894 keys1->ports.ports == keys2->ports.ports &&
9895 keys1->basic.ip_proto == keys2->basic.ip_proto &&
9896 keys1->basic.n_proto == keys2->basic.n_proto &&
9897 keys1->control.flags == keys2->control.flags &&
9898 ether_addr_equal(f1->src_mac_addr, f2->src_mac_addr) &&
9899 ether_addr_equal(f1->dst_mac_addr, f2->dst_mac_addr))
9905 static int bnxt_rx_flow_steer(struct net_device *dev, const struct sk_buff *skb,
9906 u16 rxq_index, u32 flow_id)
9908 struct bnxt *bp = netdev_priv(dev);
9909 struct bnxt_ntuple_filter *fltr, *new_fltr;
9910 struct flow_keys *fkeys;
9911 struct ethhdr *eth = (struct ethhdr *)skb_mac_header(skb);
9912 int rc = 0, idx, bit_id, l2_idx = 0;
9913 struct hlist_head *head;
9915 if (!ether_addr_equal(dev->dev_addr, eth->h_dest)) {
9916 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
9919 netif_addr_lock_bh(dev);
9920 for (j = 0; j < vnic->uc_filter_count; j++, off += ETH_ALEN) {
9921 if (ether_addr_equal(eth->h_dest,
9922 vnic->uc_list + off)) {
9927 netif_addr_unlock_bh(dev);
9931 new_fltr = kzalloc(sizeof(*new_fltr), GFP_ATOMIC);
9935 fkeys = &new_fltr->fkeys;
9936 if (!skb_flow_dissect_flow_keys(skb, fkeys, 0)) {
9937 rc = -EPROTONOSUPPORT;
9941 if ((fkeys->basic.n_proto != htons(ETH_P_IP) &&
9942 fkeys->basic.n_proto != htons(ETH_P_IPV6)) ||
9943 ((fkeys->basic.ip_proto != IPPROTO_TCP) &&
9944 (fkeys->basic.ip_proto != IPPROTO_UDP))) {
9945 rc = -EPROTONOSUPPORT;
9948 if (fkeys->basic.n_proto == htons(ETH_P_IPV6) &&
9949 bp->hwrm_spec_code < 0x10601) {
9950 rc = -EPROTONOSUPPORT;
9953 if ((fkeys->control.flags & FLOW_DIS_ENCAPSULATION) &&
9954 bp->hwrm_spec_code < 0x10601) {
9955 rc = -EPROTONOSUPPORT;
9959 memcpy(new_fltr->dst_mac_addr, eth->h_dest, ETH_ALEN);
9960 memcpy(new_fltr->src_mac_addr, eth->h_source, ETH_ALEN);
9962 idx = skb_get_hash_raw(skb) & BNXT_NTP_FLTR_HASH_MASK;
9963 head = &bp->ntp_fltr_hash_tbl[idx];
9965 hlist_for_each_entry_rcu(fltr, head, hash) {
9966 if (bnxt_fltr_match(fltr, new_fltr)) {
9974 spin_lock_bh(&bp->ntp_fltr_lock);
9975 bit_id = bitmap_find_free_region(bp->ntp_fltr_bmap,
9976 BNXT_NTP_FLTR_MAX_FLTR, 0);
9978 spin_unlock_bh(&bp->ntp_fltr_lock);
9983 new_fltr->sw_id = (u16)bit_id;
9984 new_fltr->flow_id = flow_id;
9985 new_fltr->l2_fltr_idx = l2_idx;
9986 new_fltr->rxq = rxq_index;
9987 hlist_add_head_rcu(&new_fltr->hash, head);
9988 bp->ntp_fltr_count++;
9989 spin_unlock_bh(&bp->ntp_fltr_lock);
9991 set_bit(BNXT_RX_NTP_FLTR_SP_EVENT, &bp->sp_event);
9992 bnxt_queue_sp_work(bp);
9994 return new_fltr->sw_id;
10001 static void bnxt_cfg_ntp_filters(struct bnxt *bp)
10005 for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) {
10006 struct hlist_head *head;
10007 struct hlist_node *tmp;
10008 struct bnxt_ntuple_filter *fltr;
10011 head = &bp->ntp_fltr_hash_tbl[i];
10012 hlist_for_each_entry_safe(fltr, tmp, head, hash) {
10015 if (test_bit(BNXT_FLTR_VALID, &fltr->state)) {
10016 if (rps_may_expire_flow(bp->dev, fltr->rxq,
10019 bnxt_hwrm_cfa_ntuple_filter_free(bp,
10024 rc = bnxt_hwrm_cfa_ntuple_filter_alloc(bp,
10029 set_bit(BNXT_FLTR_VALID, &fltr->state);
10033 spin_lock_bh(&bp->ntp_fltr_lock);
10034 hlist_del_rcu(&fltr->hash);
10035 bp->ntp_fltr_count--;
10036 spin_unlock_bh(&bp->ntp_fltr_lock);
10038 clear_bit(fltr->sw_id, bp->ntp_fltr_bmap);
10043 if (test_and_clear_bit(BNXT_HWRM_PF_UNLOAD_SP_EVENT, &bp->sp_event))
10044 netdev_info(bp->dev, "Receive PF driver unload event!");
10049 static void bnxt_cfg_ntp_filters(struct bnxt *bp)
10053 #endif /* CONFIG_RFS_ACCEL */
10055 static void bnxt_udp_tunnel_add(struct net_device *dev,
10056 struct udp_tunnel_info *ti)
10058 struct bnxt *bp = netdev_priv(dev);
10060 if (ti->sa_family != AF_INET6 && ti->sa_family != AF_INET)
10063 if (!netif_running(dev))
10066 switch (ti->type) {
10067 case UDP_TUNNEL_TYPE_VXLAN:
10068 if (bp->vxlan_port_cnt && bp->vxlan_port != ti->port)
10071 bp->vxlan_port_cnt++;
10072 if (bp->vxlan_port_cnt == 1) {
10073 bp->vxlan_port = ti->port;
10074 set_bit(BNXT_VXLAN_ADD_PORT_SP_EVENT, &bp->sp_event);
10075 bnxt_queue_sp_work(bp);
10078 case UDP_TUNNEL_TYPE_GENEVE:
10079 if (bp->nge_port_cnt && bp->nge_port != ti->port)
10082 bp->nge_port_cnt++;
10083 if (bp->nge_port_cnt == 1) {
10084 bp->nge_port = ti->port;
10085 set_bit(BNXT_GENEVE_ADD_PORT_SP_EVENT, &bp->sp_event);
10092 bnxt_queue_sp_work(bp);
10095 static void bnxt_udp_tunnel_del(struct net_device *dev,
10096 struct udp_tunnel_info *ti)
10098 struct bnxt *bp = netdev_priv(dev);
10100 if (ti->sa_family != AF_INET6 && ti->sa_family != AF_INET)
10103 if (!netif_running(dev))
10106 switch (ti->type) {
10107 case UDP_TUNNEL_TYPE_VXLAN:
10108 if (!bp->vxlan_port_cnt || bp->vxlan_port != ti->port)
10110 bp->vxlan_port_cnt--;
10112 if (bp->vxlan_port_cnt != 0)
10115 set_bit(BNXT_VXLAN_DEL_PORT_SP_EVENT, &bp->sp_event);
10117 case UDP_TUNNEL_TYPE_GENEVE:
10118 if (!bp->nge_port_cnt || bp->nge_port != ti->port)
10120 bp->nge_port_cnt--;
10122 if (bp->nge_port_cnt != 0)
10125 set_bit(BNXT_GENEVE_DEL_PORT_SP_EVENT, &bp->sp_event);
10131 bnxt_queue_sp_work(bp);
10134 static int bnxt_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq,
10135 struct net_device *dev, u32 filter_mask,
10138 struct bnxt *bp = netdev_priv(dev);
10140 return ndo_dflt_bridge_getlink(skb, pid, seq, dev, bp->br_mode, 0, 0,
10141 nlflags, filter_mask, NULL);
10144 static int bnxt_bridge_setlink(struct net_device *dev, struct nlmsghdr *nlh,
10145 u16 flags, struct netlink_ext_ack *extack)
10147 struct bnxt *bp = netdev_priv(dev);
10148 struct nlattr *attr, *br_spec;
10151 if (bp->hwrm_spec_code < 0x10708 || !BNXT_SINGLE_PF(bp))
10152 return -EOPNOTSUPP;
10154 br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC);
10158 nla_for_each_nested(attr, br_spec, rem) {
10161 if (nla_type(attr) != IFLA_BRIDGE_MODE)
10164 if (nla_len(attr) < sizeof(mode))
10167 mode = nla_get_u16(attr);
10168 if (mode == bp->br_mode)
10171 rc = bnxt_hwrm_set_br_mode(bp, mode);
10173 bp->br_mode = mode;
10179 int bnxt_get_port_parent_id(struct net_device *dev,
10180 struct netdev_phys_item_id *ppid)
10182 struct bnxt *bp = netdev_priv(dev);
10184 if (bp->eswitch_mode != DEVLINK_ESWITCH_MODE_SWITCHDEV)
10185 return -EOPNOTSUPP;
10187 /* The PF and it's VF-reps only support the switchdev framework */
10189 return -EOPNOTSUPP;
10191 ppid->id_len = sizeof(bp->switch_id);
10192 memcpy(ppid->id, bp->switch_id, ppid->id_len);
10197 static struct devlink_port *bnxt_get_devlink_port(struct net_device *dev)
10199 struct bnxt *bp = netdev_priv(dev);
10201 return &bp->dl_port;
10204 static const struct net_device_ops bnxt_netdev_ops = {
10205 .ndo_open = bnxt_open,
10206 .ndo_start_xmit = bnxt_start_xmit,
10207 .ndo_stop = bnxt_close,
10208 .ndo_get_stats64 = bnxt_get_stats64,
10209 .ndo_set_rx_mode = bnxt_set_rx_mode,
10210 .ndo_do_ioctl = bnxt_ioctl,
10211 .ndo_validate_addr = eth_validate_addr,
10212 .ndo_set_mac_address = bnxt_change_mac_addr,
10213 .ndo_change_mtu = bnxt_change_mtu,
10214 .ndo_fix_features = bnxt_fix_features,
10215 .ndo_set_features = bnxt_set_features,
10216 .ndo_tx_timeout = bnxt_tx_timeout,
10217 #ifdef CONFIG_BNXT_SRIOV
10218 .ndo_get_vf_config = bnxt_get_vf_config,
10219 .ndo_set_vf_mac = bnxt_set_vf_mac,
10220 .ndo_set_vf_vlan = bnxt_set_vf_vlan,
10221 .ndo_set_vf_rate = bnxt_set_vf_bw,
10222 .ndo_set_vf_link_state = bnxt_set_vf_link_state,
10223 .ndo_set_vf_spoofchk = bnxt_set_vf_spoofchk,
10224 .ndo_set_vf_trust = bnxt_set_vf_trust,
10226 .ndo_setup_tc = bnxt_setup_tc,
10227 #ifdef CONFIG_RFS_ACCEL
10228 .ndo_rx_flow_steer = bnxt_rx_flow_steer,
10230 .ndo_udp_tunnel_add = bnxt_udp_tunnel_add,
10231 .ndo_udp_tunnel_del = bnxt_udp_tunnel_del,
10232 .ndo_bpf = bnxt_xdp,
10233 .ndo_bridge_getlink = bnxt_bridge_getlink,
10234 .ndo_bridge_setlink = bnxt_bridge_setlink,
10235 .ndo_get_devlink_port = bnxt_get_devlink_port,
10238 static void bnxt_remove_one(struct pci_dev *pdev)
10240 struct net_device *dev = pci_get_drvdata(pdev);
10241 struct bnxt *bp = netdev_priv(dev);
10244 bnxt_sriov_disable(bp);
10245 bnxt_dl_unregister(bp);
10248 pci_disable_pcie_error_reporting(pdev);
10249 unregister_netdev(dev);
10250 bnxt_shutdown_tc(bp);
10251 bnxt_cancel_sp_work(bp);
10254 bnxt_clear_int_mode(bp);
10255 bnxt_hwrm_func_drv_unrgtr(bp);
10256 bnxt_free_hwrm_resources(bp);
10257 bnxt_free_hwrm_short_cmd_req(bp);
10258 bnxt_ethtool_free(bp);
10262 bnxt_free_ctx_mem(bp);
10265 bnxt_cleanup_pci(bp);
10266 bnxt_free_port_stats(bp);
10270 static int bnxt_probe_phy(struct bnxt *bp)
10273 struct bnxt_link_info *link_info = &bp->link_info;
10275 rc = bnxt_hwrm_phy_qcaps(bp);
10277 netdev_err(bp->dev, "Probe phy can't get phy capabilities (rc: %x)\n",
10281 mutex_init(&bp->link_lock);
10283 rc = bnxt_update_link(bp, false);
10285 netdev_err(bp->dev, "Probe phy can't update link (rc: %x)\n",
10290 /* Older firmware does not have supported_auto_speeds, so assume
10291 * that all supported speeds can be autonegotiated.
10293 if (link_info->auto_link_speeds && !link_info->support_auto_speeds)
10294 link_info->support_auto_speeds = link_info->support_speeds;
10296 /*initialize the ethool setting copy with NVM settings */
10297 if (BNXT_AUTO_MODE(link_info->auto_mode)) {
10298 link_info->autoneg = BNXT_AUTONEG_SPEED;
10299 if (bp->hwrm_spec_code >= 0x10201) {
10300 if (link_info->auto_pause_setting &
10301 PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE)
10302 link_info->autoneg |= BNXT_AUTONEG_FLOW_CTRL;
10304 link_info->autoneg |= BNXT_AUTONEG_FLOW_CTRL;
10306 link_info->advertising = link_info->auto_link_speeds;
10308 link_info->req_link_speed = link_info->force_link_speed;
10309 link_info->req_duplex = link_info->duplex_setting;
10311 if (link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL)
10312 link_info->req_flow_ctrl =
10313 link_info->auto_pause_setting & BNXT_LINK_PAUSE_BOTH;
10315 link_info->req_flow_ctrl = link_info->force_pause_setting;
10319 static int bnxt_get_max_irq(struct pci_dev *pdev)
10323 if (!pdev->msix_cap)
10326 pci_read_config_word(pdev, pdev->msix_cap + PCI_MSIX_FLAGS, &ctrl);
10327 return (ctrl & PCI_MSIX_FLAGS_QSIZE) + 1;
10330 static void _bnxt_get_max_rings(struct bnxt *bp, int *max_rx, int *max_tx,
10333 struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
10334 int max_ring_grps = 0, max_irq;
10336 *max_tx = hw_resc->max_tx_rings;
10337 *max_rx = hw_resc->max_rx_rings;
10338 *max_cp = bnxt_get_max_func_cp_rings_for_en(bp);
10339 max_irq = min_t(int, bnxt_get_max_func_irqs(bp) -
10340 bnxt_get_ulp_msix_num(bp),
10341 hw_resc->max_stat_ctxs - bnxt_get_ulp_stat_ctxs(bp));
10342 if (!(bp->flags & BNXT_FLAG_CHIP_P5))
10343 *max_cp = min_t(int, *max_cp, max_irq);
10344 max_ring_grps = hw_resc->max_hw_ring_grps;
10345 if (BNXT_CHIP_TYPE_NITRO_A0(bp) && BNXT_PF(bp)) {
10349 if (bp->flags & BNXT_FLAG_AGG_RINGS)
10351 if (bp->flags & BNXT_FLAG_CHIP_P5) {
10352 bnxt_trim_rings(bp, max_rx, max_tx, *max_cp, false);
10353 /* On P5 chips, max_cp output param should be available NQs */
10356 *max_rx = min_t(int, *max_rx, max_ring_grps);
10359 int bnxt_get_max_rings(struct bnxt *bp, int *max_rx, int *max_tx, bool shared)
10363 _bnxt_get_max_rings(bp, &rx, &tx, &cp);
10366 if (!rx || !tx || !cp)
10369 return bnxt_trim_rings(bp, max_rx, max_tx, cp, shared);
10372 static int bnxt_get_dflt_rings(struct bnxt *bp, int *max_rx, int *max_tx,
10377 rc = bnxt_get_max_rings(bp, max_rx, max_tx, shared);
10378 if (rc && (bp->flags & BNXT_FLAG_AGG_RINGS)) {
10379 /* Not enough rings, try disabling agg rings. */
10380 bp->flags &= ~BNXT_FLAG_AGG_RINGS;
10381 rc = bnxt_get_max_rings(bp, max_rx, max_tx, shared);
10383 /* set BNXT_FLAG_AGG_RINGS back for consistency */
10384 bp->flags |= BNXT_FLAG_AGG_RINGS;
10387 bp->flags |= BNXT_FLAG_NO_AGG_RINGS;
10388 bp->dev->hw_features &= ~(NETIF_F_LRO | NETIF_F_GRO_HW);
10389 bp->dev->features &= ~(NETIF_F_LRO | NETIF_F_GRO_HW);
10390 bnxt_set_ring_params(bp);
10393 if (bp->flags & BNXT_FLAG_ROCE_CAP) {
10394 int max_cp, max_stat, max_irq;
10396 /* Reserve minimum resources for RoCE */
10397 max_cp = bnxt_get_max_func_cp_rings(bp);
10398 max_stat = bnxt_get_max_func_stat_ctxs(bp);
10399 max_irq = bnxt_get_max_func_irqs(bp);
10400 if (max_cp <= BNXT_MIN_ROCE_CP_RINGS ||
10401 max_irq <= BNXT_MIN_ROCE_CP_RINGS ||
10402 max_stat <= BNXT_MIN_ROCE_STAT_CTXS)
10405 max_cp -= BNXT_MIN_ROCE_CP_RINGS;
10406 max_irq -= BNXT_MIN_ROCE_CP_RINGS;
10407 max_stat -= BNXT_MIN_ROCE_STAT_CTXS;
10408 max_cp = min_t(int, max_cp, max_irq);
10409 max_cp = min_t(int, max_cp, max_stat);
10410 rc = bnxt_trim_rings(bp, max_rx, max_tx, max_cp, shared);
10417 /* In initial default shared ring setting, each shared ring must have a
10420 static void bnxt_trim_dflt_sh_rings(struct bnxt *bp)
10422 bp->cp_nr_rings = min_t(int, bp->tx_nr_rings_per_tc, bp->rx_nr_rings);
10423 bp->rx_nr_rings = bp->cp_nr_rings;
10424 bp->tx_nr_rings_per_tc = bp->cp_nr_rings;
10425 bp->tx_nr_rings = bp->tx_nr_rings_per_tc;
10428 static int bnxt_set_dflt_rings(struct bnxt *bp, bool sh)
10430 int dflt_rings, max_rx_rings, max_tx_rings, rc;
10432 if (!bnxt_can_reserve_rings(bp))
10436 bp->flags |= BNXT_FLAG_SHARED_RINGS;
10437 dflt_rings = netif_get_num_default_rss_queues();
10438 /* Reduce default rings on multi-port cards so that total default
10439 * rings do not exceed CPU count.
10441 if (bp->port_count > 1) {
10443 max_t(int, num_online_cpus() / bp->port_count, 1);
10445 dflt_rings = min_t(int, dflt_rings, max_rings);
10447 rc = bnxt_get_dflt_rings(bp, &max_rx_rings, &max_tx_rings, sh);
10450 bp->rx_nr_rings = min_t(int, dflt_rings, max_rx_rings);
10451 bp->tx_nr_rings_per_tc = min_t(int, dflt_rings, max_tx_rings);
10453 bnxt_trim_dflt_sh_rings(bp);
10455 bp->cp_nr_rings = bp->tx_nr_rings_per_tc + bp->rx_nr_rings;
10456 bp->tx_nr_rings = bp->tx_nr_rings_per_tc;
10458 rc = __bnxt_reserve_rings(bp);
10460 netdev_warn(bp->dev, "Unable to reserve tx rings\n");
10461 bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
10463 bnxt_trim_dflt_sh_rings(bp);
10465 /* Rings may have been trimmed, re-reserve the trimmed rings. */
10466 if (bnxt_need_reserve_rings(bp)) {
10467 rc = __bnxt_reserve_rings(bp);
10469 netdev_warn(bp->dev, "2nd rings reservation failed.\n");
10470 bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
10472 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) {
10479 static int bnxt_init_dflt_ring_mode(struct bnxt *bp)
10483 if (bp->tx_nr_rings)
10486 bnxt_ulp_irq_stop(bp);
10487 bnxt_clear_int_mode(bp);
10488 rc = bnxt_set_dflt_rings(bp, true);
10490 netdev_err(bp->dev, "Not enough rings available.\n");
10491 goto init_dflt_ring_err;
10493 rc = bnxt_init_int_mode(bp);
10495 goto init_dflt_ring_err;
10497 bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
10498 if (bnxt_rfs_supported(bp) && bnxt_rfs_capable(bp)) {
10499 bp->flags |= BNXT_FLAG_RFS;
10500 bp->dev->features |= NETIF_F_NTUPLE;
10502 init_dflt_ring_err:
10503 bnxt_ulp_irq_restart(bp, rc);
10507 int bnxt_restore_pf_fw_resources(struct bnxt *bp)
10512 bnxt_hwrm_func_qcaps(bp);
10514 if (netif_running(bp->dev))
10515 __bnxt_close_nic(bp, true, false);
10517 bnxt_ulp_irq_stop(bp);
10518 bnxt_clear_int_mode(bp);
10519 rc = bnxt_init_int_mode(bp);
10520 bnxt_ulp_irq_restart(bp, rc);
10522 if (netif_running(bp->dev)) {
10524 dev_close(bp->dev);
10526 rc = bnxt_open_nic(bp, true, false);
10532 static int bnxt_init_mac_addr(struct bnxt *bp)
10537 memcpy(bp->dev->dev_addr, bp->pf.mac_addr, ETH_ALEN);
10539 #ifdef CONFIG_BNXT_SRIOV
10540 struct bnxt_vf_info *vf = &bp->vf;
10541 bool strict_approval = true;
10543 if (is_valid_ether_addr(vf->mac_addr)) {
10544 /* overwrite netdev dev_addr with admin VF MAC */
10545 memcpy(bp->dev->dev_addr, vf->mac_addr, ETH_ALEN);
10546 /* Older PF driver or firmware may not approve this
10549 strict_approval = false;
10551 eth_hw_addr_random(bp->dev);
10553 rc = bnxt_approve_mac(bp, bp->dev->dev_addr, strict_approval);
10559 static int bnxt_pcie_dsn_get(struct bnxt *bp, u8 dsn[])
10561 struct pci_dev *pdev = bp->pdev;
10562 int pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_DSN);
10566 netdev_info(bp->dev, "Unable do read adapter's DSN");
10567 return -EOPNOTSUPP;
10570 /* DSN (two dw) is at an offset of 4 from the cap pos */
10572 pci_read_config_dword(pdev, pos, &dw);
10573 put_unaligned_le32(dw, &dsn[0]);
10574 pci_read_config_dword(pdev, pos + 4, &dw);
10575 put_unaligned_le32(dw, &dsn[4]);
10579 static int bnxt_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
10581 static int version_printed;
10582 struct net_device *dev;
10586 if (pci_is_bridge(pdev))
10589 if (version_printed++ == 0)
10590 pr_info("%s", version);
10592 max_irqs = bnxt_get_max_irq(pdev);
10593 dev = alloc_etherdev_mq(sizeof(*bp), max_irqs);
10597 bp = netdev_priv(dev);
10598 bnxt_set_max_func_irqs(bp, max_irqs);
10600 if (bnxt_vf_pciid(ent->driver_data))
10601 bp->flags |= BNXT_FLAG_VF;
10603 if (pdev->msix_cap)
10604 bp->flags |= BNXT_FLAG_MSIX_CAP;
10606 rc = bnxt_init_board(pdev, dev);
10608 goto init_err_free;
10610 dev->netdev_ops = &bnxt_netdev_ops;
10611 dev->watchdog_timeo = BNXT_TX_TIMEOUT;
10612 dev->ethtool_ops = &bnxt_ethtool_ops;
10613 pci_set_drvdata(pdev, dev);
10615 rc = bnxt_alloc_hwrm_resources(bp);
10617 goto init_err_pci_clean;
10619 mutex_init(&bp->hwrm_cmd_lock);
10620 rc = bnxt_hwrm_ver_get(bp);
10622 goto init_err_pci_clean;
10624 if (bp->fw_cap & BNXT_FW_CAP_KONG_MB_CHNL) {
10625 rc = bnxt_alloc_kong_hwrm_resources(bp);
10627 bp->fw_cap &= ~BNXT_FW_CAP_KONG_MB_CHNL;
10630 if ((bp->fw_cap & BNXT_FW_CAP_SHORT_CMD) ||
10631 bp->hwrm_max_ext_req_len > BNXT_HWRM_MAX_REQ_LEN) {
10632 rc = bnxt_alloc_hwrm_short_cmd_req(bp);
10634 goto init_err_pci_clean;
10637 if (BNXT_CHIP_P5(bp))
10638 bp->flags |= BNXT_FLAG_CHIP_P5;
10640 rc = bnxt_hwrm_func_reset(bp);
10642 goto init_err_pci_clean;
10644 bnxt_hwrm_fw_set_time(bp);
10646 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG |
10647 NETIF_F_TSO | NETIF_F_TSO6 |
10648 NETIF_F_GSO_UDP_TUNNEL | NETIF_F_GSO_GRE |
10649 NETIF_F_GSO_IPXIP4 |
10650 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_GSO_GRE_CSUM |
10651 NETIF_F_GSO_PARTIAL | NETIF_F_RXHASH |
10652 NETIF_F_RXCSUM | NETIF_F_GRO;
10654 if (BNXT_SUPPORTS_TPA(bp))
10655 dev->hw_features |= NETIF_F_LRO;
10657 dev->hw_enc_features =
10658 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG |
10659 NETIF_F_TSO | NETIF_F_TSO6 |
10660 NETIF_F_GSO_UDP_TUNNEL | NETIF_F_GSO_GRE |
10661 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_GSO_GRE_CSUM |
10662 NETIF_F_GSO_IPXIP4 | NETIF_F_GSO_PARTIAL;
10663 dev->gso_partial_features = NETIF_F_GSO_UDP_TUNNEL_CSUM |
10664 NETIF_F_GSO_GRE_CSUM;
10665 dev->vlan_features = dev->hw_features | NETIF_F_HIGHDMA;
10666 dev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX |
10667 NETIF_F_HW_VLAN_STAG_RX | NETIF_F_HW_VLAN_STAG_TX;
10668 if (BNXT_SUPPORTS_TPA(bp))
10669 dev->hw_features |= NETIF_F_GRO_HW;
10670 dev->features |= dev->hw_features | NETIF_F_HIGHDMA;
10671 if (dev->features & NETIF_F_GRO_HW)
10672 dev->features &= ~NETIF_F_LRO;
10673 dev->priv_flags |= IFF_UNICAST_FLT;
10675 #ifdef CONFIG_BNXT_SRIOV
10676 init_waitqueue_head(&bp->sriov_cfg_wait);
10677 mutex_init(&bp->sriov_lock);
10679 if (BNXT_SUPPORTS_TPA(bp)) {
10680 bp->gro_func = bnxt_gro_func_5730x;
10681 if (BNXT_CHIP_P4(bp))
10682 bp->gro_func = bnxt_gro_func_5731x;
10684 if (!BNXT_CHIP_P4_PLUS(bp))
10685 bp->flags |= BNXT_FLAG_DOUBLE_DB;
10687 rc = bnxt_hwrm_func_drv_rgtr(bp);
10689 goto init_err_pci_clean;
10691 rc = bnxt_hwrm_func_rgtr_async_events(bp, NULL, 0);
10693 goto init_err_pci_clean;
10695 bp->ulp_probe = bnxt_ulp_probe;
10697 rc = bnxt_hwrm_queue_qportcfg(bp);
10699 netdev_err(bp->dev, "hwrm query qportcfg failure rc: %x\n",
10702 goto init_err_pci_clean;
10704 /* Get the MAX capabilities for this function */
10705 rc = bnxt_hwrm_func_qcaps(bp);
10707 netdev_err(bp->dev, "hwrm query capability failure rc: %x\n",
10710 goto init_err_pci_clean;
10713 rc = bnxt_hwrm_cfa_adv_flow_mgnt_qcaps(bp);
10715 netdev_warn(bp->dev, "hwrm query adv flow mgnt failure rc: %d\n",
10718 rc = bnxt_init_mac_addr(bp);
10720 dev_err(&pdev->dev, "Unable to initialize mac address.\n");
10721 rc = -EADDRNOTAVAIL;
10722 goto init_err_pci_clean;
10725 /* Read the adapter's DSN to use as the eswitch switch_id */
10726 rc = bnxt_pcie_dsn_get(bp, bp->switch_id);
10728 goto init_err_pci_clean;
10730 bnxt_hwrm_func_qcfg(bp);
10731 bnxt_hwrm_vnic_qcaps(bp);
10732 bnxt_hwrm_port_led_qcaps(bp);
10733 bnxt_ethtool_init(bp);
10736 /* MTU range: 60 - FW defined max */
10737 dev->min_mtu = ETH_ZLEN;
10738 dev->max_mtu = bp->max_mtu;
10740 rc = bnxt_probe_phy(bp);
10742 goto init_err_pci_clean;
10744 bnxt_set_rx_skb_mode(bp, false);
10745 bnxt_set_tpa_flags(bp);
10746 bnxt_set_ring_params(bp);
10747 rc = bnxt_set_dflt_rings(bp, true);
10749 netdev_err(bp->dev, "Not enough rings available.\n");
10751 goto init_err_pci_clean;
10754 /* Default RSS hash cfg. */
10755 bp->rss_hash_cfg = VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4 |
10756 VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4 |
10757 VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6 |
10758 VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6;
10759 if (BNXT_CHIP_P4(bp) && bp->hwrm_spec_code >= 0x10501) {
10760 bp->flags |= BNXT_FLAG_UDP_RSS_CAP;
10761 bp->rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4 |
10762 VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6;
10765 if (bnxt_rfs_supported(bp)) {
10766 dev->hw_features |= NETIF_F_NTUPLE;
10767 if (bnxt_rfs_capable(bp)) {
10768 bp->flags |= BNXT_FLAG_RFS;
10769 dev->features |= NETIF_F_NTUPLE;
10773 if (dev->hw_features & NETIF_F_HW_VLAN_CTAG_RX)
10774 bp->flags |= BNXT_FLAG_STRIP_VLAN;
10776 rc = bnxt_init_int_mode(bp);
10778 goto init_err_pci_clean;
10780 /* No TC has been set yet and rings may have been trimmed due to
10781 * limited MSIX, so we re-initialize the TX rings per TC.
10783 bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
10785 bnxt_get_wol_settings(bp);
10786 if (bp->flags & BNXT_FLAG_WOL_CAP)
10787 device_set_wakeup_enable(&pdev->dev, bp->wol);
10789 device_set_wakeup_capable(&pdev->dev, false);
10791 bnxt_hwrm_set_cache_line_size(bp, cache_line_size());
10793 bnxt_hwrm_coal_params_qcaps(bp);
10798 create_singlethread_workqueue("bnxt_pf_wq");
10800 dev_err(&pdev->dev, "Unable to create workqueue.\n");
10801 goto init_err_pci_clean;
10807 rc = register_netdev(dev);
10809 goto init_err_cleanup_tc;
10812 bnxt_dl_register(bp);
10814 netdev_info(dev, "%s found at mem %lx, node addr %pM\n",
10815 board_info[ent->driver_data].name,
10816 (long)pci_resource_start(pdev, 0), dev->dev_addr);
10817 pcie_print_link_status(pdev);
10821 init_err_cleanup_tc:
10822 bnxt_shutdown_tc(bp);
10823 bnxt_clear_int_mode(bp);
10825 init_err_pci_clean:
10826 bnxt_free_hwrm_short_cmd_req(bp);
10827 bnxt_free_hwrm_resources(bp);
10828 bnxt_free_ctx_mem(bp);
10831 bnxt_cleanup_pci(bp);
10838 static void bnxt_shutdown(struct pci_dev *pdev)
10840 struct net_device *dev = pci_get_drvdata(pdev);
10847 bp = netdev_priv(dev);
10849 goto shutdown_exit;
10851 if (netif_running(dev))
10854 bnxt_ulp_shutdown(bp);
10856 if (system_state == SYSTEM_POWER_OFF) {
10857 bnxt_clear_int_mode(bp);
10858 pci_wake_from_d3(pdev, bp->wol);
10859 pci_set_power_state(pdev, PCI_D3hot);
10866 #ifdef CONFIG_PM_SLEEP
10867 static int bnxt_suspend(struct device *device)
10869 struct pci_dev *pdev = to_pci_dev(device);
10870 struct net_device *dev = pci_get_drvdata(pdev);
10871 struct bnxt *bp = netdev_priv(dev);
10875 if (netif_running(dev)) {
10876 netif_device_detach(dev);
10877 rc = bnxt_close(dev);
10879 bnxt_hwrm_func_drv_unrgtr(bp);
10884 static int bnxt_resume(struct device *device)
10886 struct pci_dev *pdev = to_pci_dev(device);
10887 struct net_device *dev = pci_get_drvdata(pdev);
10888 struct bnxt *bp = netdev_priv(dev);
10892 if (bnxt_hwrm_ver_get(bp) || bnxt_hwrm_func_drv_rgtr(bp)) {
10896 rc = bnxt_hwrm_func_reset(bp);
10901 bnxt_get_wol_settings(bp);
10902 if (netif_running(dev)) {
10903 rc = bnxt_open(dev);
10905 netif_device_attach(dev);
10913 static SIMPLE_DEV_PM_OPS(bnxt_pm_ops, bnxt_suspend, bnxt_resume);
10914 #define BNXT_PM_OPS (&bnxt_pm_ops)
10918 #define BNXT_PM_OPS NULL
10920 #endif /* CONFIG_PM_SLEEP */
10923 * bnxt_io_error_detected - called when PCI error is detected
10924 * @pdev: Pointer to PCI device
10925 * @state: The current pci connection state
10927 * This function is called after a PCI bus error affecting
10928 * this device has been detected.
10930 static pci_ers_result_t bnxt_io_error_detected(struct pci_dev *pdev,
10931 pci_channel_state_t state)
10933 struct net_device *netdev = pci_get_drvdata(pdev);
10934 struct bnxt *bp = netdev_priv(netdev);
10936 netdev_info(netdev, "PCI I/O error detected\n");
10939 netif_device_detach(netdev);
10943 if (state == pci_channel_io_perm_failure) {
10945 return PCI_ERS_RESULT_DISCONNECT;
10948 if (netif_running(netdev))
10949 bnxt_close(netdev);
10951 pci_disable_device(pdev);
10954 /* Request a slot slot reset. */
10955 return PCI_ERS_RESULT_NEED_RESET;
10959 * bnxt_io_slot_reset - called after the pci bus has been reset.
10960 * @pdev: Pointer to PCI device
10962 * Restart the card from scratch, as if from a cold-boot.
10963 * At this point, the card has exprienced a hard reset,
10964 * followed by fixups by BIOS, and has its config space
10965 * set up identically to what it was at cold boot.
10967 static pci_ers_result_t bnxt_io_slot_reset(struct pci_dev *pdev)
10969 struct net_device *netdev = pci_get_drvdata(pdev);
10970 struct bnxt *bp = netdev_priv(netdev);
10972 pci_ers_result_t result = PCI_ERS_RESULT_DISCONNECT;
10974 netdev_info(bp->dev, "PCI Slot Reset\n");
10978 if (pci_enable_device(pdev)) {
10979 dev_err(&pdev->dev,
10980 "Cannot re-enable PCI device after reset.\n");
10982 pci_set_master(pdev);
10984 err = bnxt_hwrm_func_reset(bp);
10985 if (!err && netif_running(netdev))
10986 err = bnxt_open(netdev);
10989 result = PCI_ERS_RESULT_RECOVERED;
10990 bnxt_ulp_start(bp);
10994 if (result != PCI_ERS_RESULT_RECOVERED && netif_running(netdev))
10999 return PCI_ERS_RESULT_RECOVERED;
11003 * bnxt_io_resume - called when traffic can start flowing again.
11004 * @pdev: Pointer to PCI device
11006 * This callback is called when the error recovery driver tells
11007 * us that its OK to resume normal operation.
11009 static void bnxt_io_resume(struct pci_dev *pdev)
11011 struct net_device *netdev = pci_get_drvdata(pdev);
11015 netif_device_attach(netdev);
11020 static const struct pci_error_handlers bnxt_err_handler = {
11021 .error_detected = bnxt_io_error_detected,
11022 .slot_reset = bnxt_io_slot_reset,
11023 .resume = bnxt_io_resume
11026 static struct pci_driver bnxt_pci_driver = {
11027 .name = DRV_MODULE_NAME,
11028 .id_table = bnxt_pci_tbl,
11029 .probe = bnxt_init_one,
11030 .remove = bnxt_remove_one,
11031 .shutdown = bnxt_shutdown,
11032 .driver.pm = BNXT_PM_OPS,
11033 .err_handler = &bnxt_err_handler,
11034 #if defined(CONFIG_BNXT_SRIOV)
11035 .sriov_configure = bnxt_sriov_configure,
11039 static int __init bnxt_init(void)
11042 return pci_register_driver(&bnxt_pci_driver);
11045 static void __exit bnxt_exit(void)
11047 pci_unregister_driver(&bnxt_pci_driver);
11049 destroy_workqueue(bnxt_pf_wq);
11053 module_init(bnxt_init);
11054 module_exit(bnxt_exit);