1 /* Broadcom NetXtreme-C/E network driver.
3 * Copyright (c) 2014-2016 Broadcom Corporation
4 * Copyright (c) 2016-2019 Broadcom Limited
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation.
11 #include <linux/module.h>
13 #include <linux/stringify.h>
14 #include <linux/kernel.h>
15 #include <linux/timer.h>
16 #include <linux/errno.h>
17 #include <linux/ioport.h>
18 #include <linux/slab.h>
19 #include <linux/vmalloc.h>
20 #include <linux/interrupt.h>
21 #include <linux/pci.h>
22 #include <linux/netdevice.h>
23 #include <linux/etherdevice.h>
24 #include <linux/skbuff.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/bitops.h>
28 #include <linux/irq.h>
29 #include <linux/delay.h>
30 #include <asm/byteorder.h>
32 #include <linux/time.h>
33 #include <linux/mii.h>
34 #include <linux/mdio.h>
36 #include <linux/if_vlan.h>
37 #include <linux/if_bridge.h>
38 #include <linux/rtc.h>
39 #include <linux/bpf.h>
43 #include <net/checksum.h>
44 #include <net/ip6_checksum.h>
45 #include <net/udp_tunnel.h>
46 #include <linux/workqueue.h>
47 #include <linux/prefetch.h>
48 #include <linux/cache.h>
49 #include <linux/log2.h>
50 #include <linux/aer.h>
51 #include <linux/bitmap.h>
52 #include <linux/cpu_rmap.h>
53 #include <linux/cpumask.h>
54 #include <net/pkt_cls.h>
55 #include <linux/hwmon.h>
56 #include <linux/hwmon-sysfs.h>
61 #include "bnxt_sriov.h"
62 #include "bnxt_ethtool.h"
67 #include "bnxt_devlink.h"
68 #include "bnxt_debugfs.h"
70 #define BNXT_TX_TIMEOUT (5 * HZ)
72 static const char version[] =
73 "Broadcom NetXtreme-C/E driver " DRV_MODULE_NAME " v" DRV_MODULE_VERSION "\n";
75 MODULE_LICENSE("GPL");
76 MODULE_DESCRIPTION("Broadcom BCM573xx network driver");
77 MODULE_VERSION(DRV_MODULE_VERSION);
79 #define BNXT_RX_OFFSET (NET_SKB_PAD + NET_IP_ALIGN)
80 #define BNXT_RX_DMA_OFFSET NET_SKB_PAD
81 #define BNXT_RX_COPY_THRESH 256
83 #define BNXT_TX_PUSH_THRESH 164
127 /* indexed by enum above */
128 static const struct {
131 [BCM57301] = { "Broadcom BCM57301 NetXtreme-C 10Gb Ethernet" },
132 [BCM57302] = { "Broadcom BCM57302 NetXtreme-C 10Gb/25Gb Ethernet" },
133 [BCM57304] = { "Broadcom BCM57304 NetXtreme-C 10Gb/25Gb/40Gb/50Gb Ethernet" },
134 [BCM57417_NPAR] = { "Broadcom BCM57417 NetXtreme-E Ethernet Partition" },
135 [BCM58700] = { "Broadcom BCM58700 Nitro 1Gb/2.5Gb/10Gb Ethernet" },
136 [BCM57311] = { "Broadcom BCM57311 NetXtreme-C 10Gb Ethernet" },
137 [BCM57312] = { "Broadcom BCM57312 NetXtreme-C 10Gb/25Gb Ethernet" },
138 [BCM57402] = { "Broadcom BCM57402 NetXtreme-E 10Gb Ethernet" },
139 [BCM57404] = { "Broadcom BCM57404 NetXtreme-E 10Gb/25Gb Ethernet" },
140 [BCM57406] = { "Broadcom BCM57406 NetXtreme-E 10GBase-T Ethernet" },
141 [BCM57402_NPAR] = { "Broadcom BCM57402 NetXtreme-E Ethernet Partition" },
142 [BCM57407] = { "Broadcom BCM57407 NetXtreme-E 10GBase-T Ethernet" },
143 [BCM57412] = { "Broadcom BCM57412 NetXtreme-E 10Gb Ethernet" },
144 [BCM57414] = { "Broadcom BCM57414 NetXtreme-E 10Gb/25Gb Ethernet" },
145 [BCM57416] = { "Broadcom BCM57416 NetXtreme-E 10GBase-T Ethernet" },
146 [BCM57417] = { "Broadcom BCM57417 NetXtreme-E 10GBase-T Ethernet" },
147 [BCM57412_NPAR] = { "Broadcom BCM57412 NetXtreme-E Ethernet Partition" },
148 [BCM57314] = { "Broadcom BCM57314 NetXtreme-C 10Gb/25Gb/40Gb/50Gb Ethernet" },
149 [BCM57417_SFP] = { "Broadcom BCM57417 NetXtreme-E 10Gb/25Gb Ethernet" },
150 [BCM57416_SFP] = { "Broadcom BCM57416 NetXtreme-E 10Gb Ethernet" },
151 [BCM57404_NPAR] = { "Broadcom BCM57404 NetXtreme-E Ethernet Partition" },
152 [BCM57406_NPAR] = { "Broadcom BCM57406 NetXtreme-E Ethernet Partition" },
153 [BCM57407_SFP] = { "Broadcom BCM57407 NetXtreme-E 25Gb Ethernet" },
154 [BCM57407_NPAR] = { "Broadcom BCM57407 NetXtreme-E Ethernet Partition" },
155 [BCM57414_NPAR] = { "Broadcom BCM57414 NetXtreme-E Ethernet Partition" },
156 [BCM57416_NPAR] = { "Broadcom BCM57416 NetXtreme-E Ethernet Partition" },
157 [BCM57452] = { "Broadcom BCM57452 NetXtreme-E 10Gb/25Gb/40Gb/50Gb Ethernet" },
158 [BCM57454] = { "Broadcom BCM57454 NetXtreme-E 10Gb/25Gb/40Gb/50Gb/100Gb Ethernet" },
159 [BCM5745x_NPAR] = { "Broadcom BCM5745x NetXtreme-E Ethernet Partition" },
160 [BCM57508] = { "Broadcom BCM57508 NetXtreme-E 10Gb/25Gb/50Gb/100Gb/200Gb Ethernet" },
161 [BCM57504] = { "Broadcom BCM57504 NetXtreme-E 10Gb/25Gb/50Gb/100Gb/200Gb Ethernet" },
162 [BCM57502] = { "Broadcom BCM57502 NetXtreme-E 10Gb/25Gb/50Gb Ethernet" },
163 [BCM58802] = { "Broadcom BCM58802 NetXtreme-S 10Gb/25Gb/40Gb/50Gb Ethernet" },
164 [BCM58804] = { "Broadcom BCM58804 NetXtreme-S 10Gb/25Gb/40Gb/50Gb/100Gb Ethernet" },
165 [BCM58808] = { "Broadcom BCM58808 NetXtreme-S 10Gb/25Gb/40Gb/50Gb/100Gb Ethernet" },
166 [NETXTREME_E_VF] = { "Broadcom NetXtreme-E Ethernet Virtual Function" },
167 [NETXTREME_C_VF] = { "Broadcom NetXtreme-C Ethernet Virtual Function" },
168 [NETXTREME_S_VF] = { "Broadcom NetXtreme-S Ethernet Virtual Function" },
169 [NETXTREME_E_P5_VF] = { "Broadcom BCM5750X NetXtreme-E Ethernet Virtual Function" },
172 static const struct pci_device_id bnxt_pci_tbl[] = {
173 { PCI_VDEVICE(BROADCOM, 0x1604), .driver_data = BCM5745x_NPAR },
174 { PCI_VDEVICE(BROADCOM, 0x1605), .driver_data = BCM5745x_NPAR },
175 { PCI_VDEVICE(BROADCOM, 0x1614), .driver_data = BCM57454 },
176 { PCI_VDEVICE(BROADCOM, 0x16c0), .driver_data = BCM57417_NPAR },
177 { PCI_VDEVICE(BROADCOM, 0x16c8), .driver_data = BCM57301 },
178 { PCI_VDEVICE(BROADCOM, 0x16c9), .driver_data = BCM57302 },
179 { PCI_VDEVICE(BROADCOM, 0x16ca), .driver_data = BCM57304 },
180 { PCI_VDEVICE(BROADCOM, 0x16cc), .driver_data = BCM57417_NPAR },
181 { PCI_VDEVICE(BROADCOM, 0x16cd), .driver_data = BCM58700 },
182 { PCI_VDEVICE(BROADCOM, 0x16ce), .driver_data = BCM57311 },
183 { PCI_VDEVICE(BROADCOM, 0x16cf), .driver_data = BCM57312 },
184 { PCI_VDEVICE(BROADCOM, 0x16d0), .driver_data = BCM57402 },
185 { PCI_VDEVICE(BROADCOM, 0x16d1), .driver_data = BCM57404 },
186 { PCI_VDEVICE(BROADCOM, 0x16d2), .driver_data = BCM57406 },
187 { PCI_VDEVICE(BROADCOM, 0x16d4), .driver_data = BCM57402_NPAR },
188 { PCI_VDEVICE(BROADCOM, 0x16d5), .driver_data = BCM57407 },
189 { PCI_VDEVICE(BROADCOM, 0x16d6), .driver_data = BCM57412 },
190 { PCI_VDEVICE(BROADCOM, 0x16d7), .driver_data = BCM57414 },
191 { PCI_VDEVICE(BROADCOM, 0x16d8), .driver_data = BCM57416 },
192 { PCI_VDEVICE(BROADCOM, 0x16d9), .driver_data = BCM57417 },
193 { PCI_VDEVICE(BROADCOM, 0x16de), .driver_data = BCM57412_NPAR },
194 { PCI_VDEVICE(BROADCOM, 0x16df), .driver_data = BCM57314 },
195 { PCI_VDEVICE(BROADCOM, 0x16e2), .driver_data = BCM57417_SFP },
196 { PCI_VDEVICE(BROADCOM, 0x16e3), .driver_data = BCM57416_SFP },
197 { PCI_VDEVICE(BROADCOM, 0x16e7), .driver_data = BCM57404_NPAR },
198 { PCI_VDEVICE(BROADCOM, 0x16e8), .driver_data = BCM57406_NPAR },
199 { PCI_VDEVICE(BROADCOM, 0x16e9), .driver_data = BCM57407_SFP },
200 { PCI_VDEVICE(BROADCOM, 0x16ea), .driver_data = BCM57407_NPAR },
201 { PCI_VDEVICE(BROADCOM, 0x16eb), .driver_data = BCM57412_NPAR },
202 { PCI_VDEVICE(BROADCOM, 0x16ec), .driver_data = BCM57414_NPAR },
203 { PCI_VDEVICE(BROADCOM, 0x16ed), .driver_data = BCM57414_NPAR },
204 { PCI_VDEVICE(BROADCOM, 0x16ee), .driver_data = BCM57416_NPAR },
205 { PCI_VDEVICE(BROADCOM, 0x16ef), .driver_data = BCM57416_NPAR },
206 { PCI_VDEVICE(BROADCOM, 0x16f0), .driver_data = BCM58808 },
207 { PCI_VDEVICE(BROADCOM, 0x16f1), .driver_data = BCM57452 },
208 { PCI_VDEVICE(BROADCOM, 0x1750), .driver_data = BCM57508 },
209 { PCI_VDEVICE(BROADCOM, 0x1751), .driver_data = BCM57504 },
210 { PCI_VDEVICE(BROADCOM, 0x1752), .driver_data = BCM57502 },
211 { PCI_VDEVICE(BROADCOM, 0xd802), .driver_data = BCM58802 },
212 { PCI_VDEVICE(BROADCOM, 0xd804), .driver_data = BCM58804 },
213 #ifdef CONFIG_BNXT_SRIOV
214 { PCI_VDEVICE(BROADCOM, 0x1606), .driver_data = NETXTREME_E_VF },
215 { PCI_VDEVICE(BROADCOM, 0x1609), .driver_data = NETXTREME_E_VF },
216 { PCI_VDEVICE(BROADCOM, 0x16c1), .driver_data = NETXTREME_E_VF },
217 { PCI_VDEVICE(BROADCOM, 0x16cb), .driver_data = NETXTREME_C_VF },
218 { PCI_VDEVICE(BROADCOM, 0x16d3), .driver_data = NETXTREME_E_VF },
219 { PCI_VDEVICE(BROADCOM, 0x16dc), .driver_data = NETXTREME_E_VF },
220 { PCI_VDEVICE(BROADCOM, 0x16e1), .driver_data = NETXTREME_C_VF },
221 { PCI_VDEVICE(BROADCOM, 0x16e5), .driver_data = NETXTREME_C_VF },
222 { PCI_VDEVICE(BROADCOM, 0x1806), .driver_data = NETXTREME_E_P5_VF },
223 { PCI_VDEVICE(BROADCOM, 0x1807), .driver_data = NETXTREME_E_P5_VF },
224 { PCI_VDEVICE(BROADCOM, 0xd800), .driver_data = NETXTREME_S_VF },
229 MODULE_DEVICE_TABLE(pci, bnxt_pci_tbl);
231 static const u16 bnxt_vf_req_snif[] = {
235 HWRM_CFA_L2_FILTER_ALLOC,
238 static const u16 bnxt_async_events_arr[] = {
239 ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE,
240 ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD,
241 ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED,
242 ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE,
243 ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE,
246 static struct workqueue_struct *bnxt_pf_wq;
248 static bool bnxt_vf_pciid(enum board_idx idx)
250 return (idx == NETXTREME_C_VF || idx == NETXTREME_E_VF ||
251 idx == NETXTREME_S_VF || idx == NETXTREME_E_P5_VF);
254 #define DB_CP_REARM_FLAGS (DB_KEY_CP | DB_IDX_VALID)
255 #define DB_CP_FLAGS (DB_KEY_CP | DB_IDX_VALID | DB_IRQ_DIS)
256 #define DB_CP_IRQ_DIS_FLAGS (DB_KEY_CP | DB_IRQ_DIS)
258 #define BNXT_CP_DB_IRQ_DIS(db) \
259 writel(DB_CP_IRQ_DIS_FLAGS, db)
261 #define BNXT_DB_CQ(db, idx) \
262 writel(DB_CP_FLAGS | RING_CMP(idx), (db)->doorbell)
264 #define BNXT_DB_NQ_P5(db, idx) \
265 writeq((db)->db_key64 | DBR_TYPE_NQ | RING_CMP(idx), (db)->doorbell)
267 #define BNXT_DB_CQ_ARM(db, idx) \
268 writel(DB_CP_REARM_FLAGS | RING_CMP(idx), (db)->doorbell)
270 #define BNXT_DB_NQ_ARM_P5(db, idx) \
271 writeq((db)->db_key64 | DBR_TYPE_NQ_ARM | RING_CMP(idx), (db)->doorbell)
273 static void bnxt_db_nq(struct bnxt *bp, struct bnxt_db_info *db, u32 idx)
275 if (bp->flags & BNXT_FLAG_CHIP_P5)
276 BNXT_DB_NQ_P5(db, idx);
281 static void bnxt_db_nq_arm(struct bnxt *bp, struct bnxt_db_info *db, u32 idx)
283 if (bp->flags & BNXT_FLAG_CHIP_P5)
284 BNXT_DB_NQ_ARM_P5(db, idx);
286 BNXT_DB_CQ_ARM(db, idx);
289 static void bnxt_db_cq(struct bnxt *bp, struct bnxt_db_info *db, u32 idx)
291 if (bp->flags & BNXT_FLAG_CHIP_P5)
292 writeq(db->db_key64 | DBR_TYPE_CQ_ARMALL | RING_CMP(idx),
298 const u16 bnxt_lhint_arr[] = {
299 TX_BD_FLAGS_LHINT_512_AND_SMALLER,
300 TX_BD_FLAGS_LHINT_512_TO_1023,
301 TX_BD_FLAGS_LHINT_1024_TO_2047,
302 TX_BD_FLAGS_LHINT_1024_TO_2047,
303 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
304 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
305 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
306 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
307 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
308 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
309 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
310 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
311 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
312 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
313 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
314 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
315 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
316 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
317 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
320 static u16 bnxt_xmit_get_cfa_action(struct sk_buff *skb)
322 struct metadata_dst *md_dst = skb_metadata_dst(skb);
324 if (!md_dst || md_dst->type != METADATA_HW_PORT_MUX)
327 return md_dst->u.port_info.port_id;
330 static netdev_tx_t bnxt_start_xmit(struct sk_buff *skb, struct net_device *dev)
332 struct bnxt *bp = netdev_priv(dev);
334 struct tx_bd_ext *txbd1;
335 struct netdev_queue *txq;
338 unsigned int length, pad = 0;
339 u32 len, free_size, vlan_tag_flags, cfa_action, flags;
341 struct pci_dev *pdev = bp->pdev;
342 struct bnxt_tx_ring_info *txr;
343 struct bnxt_sw_tx_bd *tx_buf;
345 i = skb_get_queue_mapping(skb);
346 if (unlikely(i >= bp->tx_nr_rings)) {
347 dev_kfree_skb_any(skb);
351 txq = netdev_get_tx_queue(dev, i);
352 txr = &bp->tx_ring[bp->tx_ring_map[i]];
355 free_size = bnxt_tx_avail(bp, txr);
356 if (unlikely(free_size < skb_shinfo(skb)->nr_frags + 2)) {
357 netif_tx_stop_queue(txq);
358 return NETDEV_TX_BUSY;
362 len = skb_headlen(skb);
363 last_frag = skb_shinfo(skb)->nr_frags;
365 txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
367 txbd->tx_bd_opaque = prod;
369 tx_buf = &txr->tx_buf_ring[prod];
371 tx_buf->nr_frags = last_frag;
374 cfa_action = bnxt_xmit_get_cfa_action(skb);
375 if (skb_vlan_tag_present(skb)) {
376 vlan_tag_flags = TX_BD_CFA_META_KEY_VLAN |
377 skb_vlan_tag_get(skb);
378 /* Currently supports 8021Q, 8021AD vlan offloads
379 * QINQ1, QINQ2, QINQ3 vlan headers are deprecated
381 if (skb->vlan_proto == htons(ETH_P_8021Q))
382 vlan_tag_flags |= 1 << TX_BD_CFA_META_TPID_SHIFT;
385 if (free_size == bp->tx_ring_size && length <= bp->tx_push_thresh) {
386 struct tx_push_buffer *tx_push_buf = txr->tx_push;
387 struct tx_push_bd *tx_push = &tx_push_buf->push_bd;
388 struct tx_bd_ext *tx_push1 = &tx_push->txbd2;
389 void __iomem *db = txr->tx_db.doorbell;
390 void *pdata = tx_push_buf->data;
394 /* Set COAL_NOW to be ready quickly for the next push */
395 tx_push->tx_bd_len_flags_type =
396 cpu_to_le32((length << TX_BD_LEN_SHIFT) |
397 TX_BD_TYPE_LONG_TX_BD |
398 TX_BD_FLAGS_LHINT_512_AND_SMALLER |
399 TX_BD_FLAGS_COAL_NOW |
400 TX_BD_FLAGS_PACKET_END |
401 (2 << TX_BD_FLAGS_BD_CNT_SHIFT));
403 if (skb->ip_summed == CHECKSUM_PARTIAL)
404 tx_push1->tx_bd_hsize_lflags =
405 cpu_to_le32(TX_BD_FLAGS_TCP_UDP_CHKSUM);
407 tx_push1->tx_bd_hsize_lflags = 0;
409 tx_push1->tx_bd_cfa_meta = cpu_to_le32(vlan_tag_flags);
410 tx_push1->tx_bd_cfa_action =
411 cpu_to_le32(cfa_action << TX_BD_CFA_ACTION_SHIFT);
413 end = pdata + length;
414 end = PTR_ALIGN(end, 8) - 1;
417 skb_copy_from_linear_data(skb, pdata, len);
419 for (j = 0; j < last_frag; j++) {
420 skb_frag_t *frag = &skb_shinfo(skb)->frags[j];
423 fptr = skb_frag_address_safe(frag);
427 memcpy(pdata, fptr, skb_frag_size(frag));
428 pdata += skb_frag_size(frag);
431 txbd->tx_bd_len_flags_type = tx_push->tx_bd_len_flags_type;
432 txbd->tx_bd_haddr = txr->data_mapping;
433 prod = NEXT_TX(prod);
434 txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
435 memcpy(txbd, tx_push1, sizeof(*txbd));
436 prod = NEXT_TX(prod);
438 cpu_to_le32(DB_KEY_TX_PUSH | DB_LONG_TX_PUSH | prod);
442 netdev_tx_sent_queue(txq, skb->len);
443 wmb(); /* Sync is_push and byte queue before pushing data */
445 push_len = (length + sizeof(*tx_push) + 7) / 8;
447 __iowrite64_copy(db, tx_push_buf, 16);
448 __iowrite32_copy(db + 4, tx_push_buf + 1,
449 (push_len - 16) << 1);
451 __iowrite64_copy(db, tx_push_buf, push_len);
458 if (length < BNXT_MIN_PKT_SIZE) {
459 pad = BNXT_MIN_PKT_SIZE - length;
460 if (skb_pad(skb, pad)) {
461 /* SKB already freed. */
465 length = BNXT_MIN_PKT_SIZE;
468 mapping = dma_map_single(&pdev->dev, skb->data, len, DMA_TO_DEVICE);
470 if (unlikely(dma_mapping_error(&pdev->dev, mapping))) {
471 dev_kfree_skb_any(skb);
476 dma_unmap_addr_set(tx_buf, mapping, mapping);
477 flags = (len << TX_BD_LEN_SHIFT) | TX_BD_TYPE_LONG_TX_BD |
478 ((last_frag + 2) << TX_BD_FLAGS_BD_CNT_SHIFT);
480 txbd->tx_bd_haddr = cpu_to_le64(mapping);
482 prod = NEXT_TX(prod);
483 txbd1 = (struct tx_bd_ext *)
484 &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
486 txbd1->tx_bd_hsize_lflags = 0;
487 if (skb_is_gso(skb)) {
490 if (skb->encapsulation)
491 hdr_len = skb_inner_network_offset(skb) +
492 skb_inner_network_header_len(skb) +
493 inner_tcp_hdrlen(skb);
495 hdr_len = skb_transport_offset(skb) +
498 txbd1->tx_bd_hsize_lflags = cpu_to_le32(TX_BD_FLAGS_LSO |
500 (hdr_len << (TX_BD_HSIZE_SHIFT - 1)));
501 length = skb_shinfo(skb)->gso_size;
502 txbd1->tx_bd_mss = cpu_to_le32(length);
504 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
505 txbd1->tx_bd_hsize_lflags =
506 cpu_to_le32(TX_BD_FLAGS_TCP_UDP_CHKSUM);
507 txbd1->tx_bd_mss = 0;
511 if (unlikely(length >= ARRAY_SIZE(bnxt_lhint_arr))) {
512 dev_warn_ratelimited(&pdev->dev, "Dropped oversize %d bytes TX packet.\n",
517 flags |= bnxt_lhint_arr[length];
518 txbd->tx_bd_len_flags_type = cpu_to_le32(flags);
520 txbd1->tx_bd_cfa_meta = cpu_to_le32(vlan_tag_flags);
521 txbd1->tx_bd_cfa_action =
522 cpu_to_le32(cfa_action << TX_BD_CFA_ACTION_SHIFT);
523 for (i = 0; i < last_frag; i++) {
524 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
526 prod = NEXT_TX(prod);
527 txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
529 len = skb_frag_size(frag);
530 mapping = skb_frag_dma_map(&pdev->dev, frag, 0, len,
533 if (unlikely(dma_mapping_error(&pdev->dev, mapping)))
536 tx_buf = &txr->tx_buf_ring[prod];
537 dma_unmap_addr_set(tx_buf, mapping, mapping);
539 txbd->tx_bd_haddr = cpu_to_le64(mapping);
541 flags = len << TX_BD_LEN_SHIFT;
542 txbd->tx_bd_len_flags_type = cpu_to_le32(flags);
546 txbd->tx_bd_len_flags_type =
547 cpu_to_le32(((len + pad) << TX_BD_LEN_SHIFT) | flags |
548 TX_BD_FLAGS_PACKET_END);
550 netdev_tx_sent_queue(txq, skb->len);
552 /* Sync BD data before updating doorbell */
555 prod = NEXT_TX(prod);
558 if (!netdev_xmit_more() || netif_xmit_stopped(txq))
559 bnxt_db_write(bp, &txr->tx_db, prod);
563 if (unlikely(bnxt_tx_avail(bp, txr) <= MAX_SKB_FRAGS + 1)) {
564 if (netdev_xmit_more() && !tx_buf->is_push)
565 bnxt_db_write(bp, &txr->tx_db, prod);
567 netif_tx_stop_queue(txq);
569 /* netif_tx_stop_queue() must be done before checking
570 * tx index in bnxt_tx_avail() below, because in
571 * bnxt_tx_int(), we update tx index before checking for
572 * netif_tx_queue_stopped().
575 if (bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh)
576 netif_tx_wake_queue(txq);
583 /* start back at beginning and unmap skb */
585 tx_buf = &txr->tx_buf_ring[prod];
587 dma_unmap_single(&pdev->dev, dma_unmap_addr(tx_buf, mapping),
588 skb_headlen(skb), PCI_DMA_TODEVICE);
589 prod = NEXT_TX(prod);
591 /* unmap remaining mapped pages */
592 for (i = 0; i < last_frag; i++) {
593 prod = NEXT_TX(prod);
594 tx_buf = &txr->tx_buf_ring[prod];
595 dma_unmap_page(&pdev->dev, dma_unmap_addr(tx_buf, mapping),
596 skb_frag_size(&skb_shinfo(skb)->frags[i]),
600 dev_kfree_skb_any(skb);
604 static void bnxt_tx_int(struct bnxt *bp, struct bnxt_napi *bnapi, int nr_pkts)
606 struct bnxt_tx_ring_info *txr = bnapi->tx_ring;
607 struct netdev_queue *txq = netdev_get_tx_queue(bp->dev, txr->txq_index);
608 u16 cons = txr->tx_cons;
609 struct pci_dev *pdev = bp->pdev;
611 unsigned int tx_bytes = 0;
613 for (i = 0; i < nr_pkts; i++) {
614 struct bnxt_sw_tx_bd *tx_buf;
618 tx_buf = &txr->tx_buf_ring[cons];
619 cons = NEXT_TX(cons);
623 if (tx_buf->is_push) {
628 dma_unmap_single(&pdev->dev, dma_unmap_addr(tx_buf, mapping),
629 skb_headlen(skb), PCI_DMA_TODEVICE);
630 last = tx_buf->nr_frags;
632 for (j = 0; j < last; j++) {
633 cons = NEXT_TX(cons);
634 tx_buf = &txr->tx_buf_ring[cons];
637 dma_unmap_addr(tx_buf, mapping),
638 skb_frag_size(&skb_shinfo(skb)->frags[j]),
643 cons = NEXT_TX(cons);
645 tx_bytes += skb->len;
646 dev_kfree_skb_any(skb);
649 netdev_tx_completed_queue(txq, nr_pkts, tx_bytes);
652 /* Need to make the tx_cons update visible to bnxt_start_xmit()
653 * before checking for netif_tx_queue_stopped(). Without the
654 * memory barrier, there is a small possibility that bnxt_start_xmit()
655 * will miss it and cause the queue to be stopped forever.
659 if (unlikely(netif_tx_queue_stopped(txq)) &&
660 (bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh)) {
661 __netif_tx_lock(txq, smp_processor_id());
662 if (netif_tx_queue_stopped(txq) &&
663 bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh &&
664 txr->dev_state != BNXT_DEV_STATE_CLOSING)
665 netif_tx_wake_queue(txq);
666 __netif_tx_unlock(txq);
670 static struct page *__bnxt_alloc_rx_page(struct bnxt *bp, dma_addr_t *mapping,
673 struct device *dev = &bp->pdev->dev;
676 page = alloc_page(gfp);
680 *mapping = dma_map_page_attrs(dev, page, 0, PAGE_SIZE, bp->rx_dir,
681 DMA_ATTR_WEAK_ORDERING);
682 if (dma_mapping_error(dev, *mapping)) {
686 *mapping += bp->rx_dma_offset;
690 static inline u8 *__bnxt_alloc_rx_data(struct bnxt *bp, dma_addr_t *mapping,
694 struct pci_dev *pdev = bp->pdev;
696 data = kmalloc(bp->rx_buf_size, gfp);
700 *mapping = dma_map_single_attrs(&pdev->dev, data + bp->rx_dma_offset,
701 bp->rx_buf_use_size, bp->rx_dir,
702 DMA_ATTR_WEAK_ORDERING);
704 if (dma_mapping_error(&pdev->dev, *mapping)) {
711 int bnxt_alloc_rx_data(struct bnxt *bp, struct bnxt_rx_ring_info *rxr,
714 struct rx_bd *rxbd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
715 struct bnxt_sw_rx_bd *rx_buf = &rxr->rx_buf_ring[prod];
718 if (BNXT_RX_PAGE_MODE(bp)) {
719 struct page *page = __bnxt_alloc_rx_page(bp, &mapping, gfp);
725 rx_buf->data_ptr = page_address(page) + bp->rx_offset;
727 u8 *data = __bnxt_alloc_rx_data(bp, &mapping, gfp);
733 rx_buf->data_ptr = data + bp->rx_offset;
735 rx_buf->mapping = mapping;
737 rxbd->rx_bd_haddr = cpu_to_le64(mapping);
741 void bnxt_reuse_rx_data(struct bnxt_rx_ring_info *rxr, u16 cons, void *data)
743 u16 prod = rxr->rx_prod;
744 struct bnxt_sw_rx_bd *cons_rx_buf, *prod_rx_buf;
745 struct rx_bd *cons_bd, *prod_bd;
747 prod_rx_buf = &rxr->rx_buf_ring[prod];
748 cons_rx_buf = &rxr->rx_buf_ring[cons];
750 prod_rx_buf->data = data;
751 prod_rx_buf->data_ptr = cons_rx_buf->data_ptr;
753 prod_rx_buf->mapping = cons_rx_buf->mapping;
755 prod_bd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
756 cons_bd = &rxr->rx_desc_ring[RX_RING(cons)][RX_IDX(cons)];
758 prod_bd->rx_bd_haddr = cons_bd->rx_bd_haddr;
761 static inline u16 bnxt_find_next_agg_idx(struct bnxt_rx_ring_info *rxr, u16 idx)
763 u16 next, max = rxr->rx_agg_bmap_size;
765 next = find_next_zero_bit(rxr->rx_agg_bmap, max, idx);
767 next = find_first_zero_bit(rxr->rx_agg_bmap, max);
771 static inline int bnxt_alloc_rx_page(struct bnxt *bp,
772 struct bnxt_rx_ring_info *rxr,
776 &rxr->rx_agg_desc_ring[RX_RING(prod)][RX_IDX(prod)];
777 struct bnxt_sw_rx_agg_bd *rx_agg_buf;
778 struct pci_dev *pdev = bp->pdev;
781 u16 sw_prod = rxr->rx_sw_agg_prod;
782 unsigned int offset = 0;
784 if (PAGE_SIZE > BNXT_RX_PAGE_SIZE) {
787 page = alloc_page(gfp);
791 rxr->rx_page_offset = 0;
793 offset = rxr->rx_page_offset;
794 rxr->rx_page_offset += BNXT_RX_PAGE_SIZE;
795 if (rxr->rx_page_offset == PAGE_SIZE)
800 page = alloc_page(gfp);
805 mapping = dma_map_page_attrs(&pdev->dev, page, offset,
806 BNXT_RX_PAGE_SIZE, PCI_DMA_FROMDEVICE,
807 DMA_ATTR_WEAK_ORDERING);
808 if (dma_mapping_error(&pdev->dev, mapping)) {
813 if (unlikely(test_bit(sw_prod, rxr->rx_agg_bmap)))
814 sw_prod = bnxt_find_next_agg_idx(rxr, sw_prod);
816 __set_bit(sw_prod, rxr->rx_agg_bmap);
817 rx_agg_buf = &rxr->rx_agg_ring[sw_prod];
818 rxr->rx_sw_agg_prod = NEXT_RX_AGG(sw_prod);
820 rx_agg_buf->page = page;
821 rx_agg_buf->offset = offset;
822 rx_agg_buf->mapping = mapping;
823 rxbd->rx_bd_haddr = cpu_to_le64(mapping);
824 rxbd->rx_bd_opaque = sw_prod;
828 static void bnxt_reuse_rx_agg_bufs(struct bnxt_cp_ring_info *cpr, u16 cp_cons,
831 struct bnxt_napi *bnapi = cpr->bnapi;
832 struct bnxt *bp = bnapi->bp;
833 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
834 u16 prod = rxr->rx_agg_prod;
835 u16 sw_prod = rxr->rx_sw_agg_prod;
838 for (i = 0; i < agg_bufs; i++) {
840 struct rx_agg_cmp *agg;
841 struct bnxt_sw_rx_agg_bd *cons_rx_buf, *prod_rx_buf;
842 struct rx_bd *prod_bd;
845 agg = (struct rx_agg_cmp *)
846 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
847 cons = agg->rx_agg_cmp_opaque;
848 __clear_bit(cons, rxr->rx_agg_bmap);
850 if (unlikely(test_bit(sw_prod, rxr->rx_agg_bmap)))
851 sw_prod = bnxt_find_next_agg_idx(rxr, sw_prod);
853 __set_bit(sw_prod, rxr->rx_agg_bmap);
854 prod_rx_buf = &rxr->rx_agg_ring[sw_prod];
855 cons_rx_buf = &rxr->rx_agg_ring[cons];
857 /* It is possible for sw_prod to be equal to cons, so
858 * set cons_rx_buf->page to NULL first.
860 page = cons_rx_buf->page;
861 cons_rx_buf->page = NULL;
862 prod_rx_buf->page = page;
863 prod_rx_buf->offset = cons_rx_buf->offset;
865 prod_rx_buf->mapping = cons_rx_buf->mapping;
867 prod_bd = &rxr->rx_agg_desc_ring[RX_RING(prod)][RX_IDX(prod)];
869 prod_bd->rx_bd_haddr = cpu_to_le64(cons_rx_buf->mapping);
870 prod_bd->rx_bd_opaque = sw_prod;
872 prod = NEXT_RX_AGG(prod);
873 sw_prod = NEXT_RX_AGG(sw_prod);
874 cp_cons = NEXT_CMP(cp_cons);
876 rxr->rx_agg_prod = prod;
877 rxr->rx_sw_agg_prod = sw_prod;
880 static struct sk_buff *bnxt_rx_page_skb(struct bnxt *bp,
881 struct bnxt_rx_ring_info *rxr,
882 u16 cons, void *data, u8 *data_ptr,
884 unsigned int offset_and_len)
886 unsigned int payload = offset_and_len >> 16;
887 unsigned int len = offset_and_len & 0xffff;
888 struct skb_frag_struct *frag;
889 struct page *page = data;
890 u16 prod = rxr->rx_prod;
894 err = bnxt_alloc_rx_data(bp, rxr, prod, GFP_ATOMIC);
896 bnxt_reuse_rx_data(rxr, cons, data);
899 dma_addr -= bp->rx_dma_offset;
900 dma_unmap_page_attrs(&bp->pdev->dev, dma_addr, PAGE_SIZE, bp->rx_dir,
901 DMA_ATTR_WEAK_ORDERING);
903 if (unlikely(!payload))
904 payload = eth_get_headlen(bp->dev, data_ptr, len);
906 skb = napi_alloc_skb(&rxr->bnapi->napi, payload);
912 off = (void *)data_ptr - page_address(page);
913 skb_add_rx_frag(skb, 0, page, off, len, PAGE_SIZE);
914 memcpy(skb->data - NET_IP_ALIGN, data_ptr - NET_IP_ALIGN,
915 payload + NET_IP_ALIGN);
917 frag = &skb_shinfo(skb)->frags[0];
918 skb_frag_size_sub(frag, payload);
919 frag->page_offset += payload;
920 skb->data_len -= payload;
921 skb->tail += payload;
926 static struct sk_buff *bnxt_rx_skb(struct bnxt *bp,
927 struct bnxt_rx_ring_info *rxr, u16 cons,
928 void *data, u8 *data_ptr,
930 unsigned int offset_and_len)
932 u16 prod = rxr->rx_prod;
936 err = bnxt_alloc_rx_data(bp, rxr, prod, GFP_ATOMIC);
938 bnxt_reuse_rx_data(rxr, cons, data);
942 skb = build_skb(data, 0);
943 dma_unmap_single_attrs(&bp->pdev->dev, dma_addr, bp->rx_buf_use_size,
944 bp->rx_dir, DMA_ATTR_WEAK_ORDERING);
950 skb_reserve(skb, bp->rx_offset);
951 skb_put(skb, offset_and_len & 0xffff);
955 static struct sk_buff *bnxt_rx_pages(struct bnxt *bp,
956 struct bnxt_cp_ring_info *cpr,
957 struct sk_buff *skb, u16 cp_cons,
960 struct bnxt_napi *bnapi = cpr->bnapi;
961 struct pci_dev *pdev = bp->pdev;
962 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
963 u16 prod = rxr->rx_agg_prod;
966 for (i = 0; i < agg_bufs; i++) {
968 struct rx_agg_cmp *agg;
969 struct bnxt_sw_rx_agg_bd *cons_rx_buf;
973 agg = (struct rx_agg_cmp *)
974 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
975 cons = agg->rx_agg_cmp_opaque;
976 frag_len = (le32_to_cpu(agg->rx_agg_cmp_len_flags_type) &
977 RX_AGG_CMP_LEN) >> RX_AGG_CMP_LEN_SHIFT;
979 cons_rx_buf = &rxr->rx_agg_ring[cons];
980 skb_fill_page_desc(skb, i, cons_rx_buf->page,
981 cons_rx_buf->offset, frag_len);
982 __clear_bit(cons, rxr->rx_agg_bmap);
984 /* It is possible for bnxt_alloc_rx_page() to allocate
985 * a sw_prod index that equals the cons index, so we
986 * need to clear the cons entry now.
988 mapping = cons_rx_buf->mapping;
989 page = cons_rx_buf->page;
990 cons_rx_buf->page = NULL;
992 if (bnxt_alloc_rx_page(bp, rxr, prod, GFP_ATOMIC) != 0) {
993 struct skb_shared_info *shinfo;
994 unsigned int nr_frags;
996 shinfo = skb_shinfo(skb);
997 nr_frags = --shinfo->nr_frags;
998 __skb_frag_set_page(&shinfo->frags[nr_frags], NULL);
1002 cons_rx_buf->page = page;
1004 /* Update prod since possibly some pages have been
1005 * allocated already.
1007 rxr->rx_agg_prod = prod;
1008 bnxt_reuse_rx_agg_bufs(cpr, cp_cons, agg_bufs - i);
1012 dma_unmap_page_attrs(&pdev->dev, mapping, BNXT_RX_PAGE_SIZE,
1014 DMA_ATTR_WEAK_ORDERING);
1016 skb->data_len += frag_len;
1017 skb->len += frag_len;
1018 skb->truesize += PAGE_SIZE;
1020 prod = NEXT_RX_AGG(prod);
1021 cp_cons = NEXT_CMP(cp_cons);
1023 rxr->rx_agg_prod = prod;
1027 static int bnxt_agg_bufs_valid(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1028 u8 agg_bufs, u32 *raw_cons)
1031 struct rx_agg_cmp *agg;
1033 *raw_cons = ADV_RAW_CMP(*raw_cons, agg_bufs);
1034 last = RING_CMP(*raw_cons);
1035 agg = (struct rx_agg_cmp *)
1036 &cpr->cp_desc_ring[CP_RING(last)][CP_IDX(last)];
1037 return RX_AGG_CMP_VALID(agg, *raw_cons);
1040 static inline struct sk_buff *bnxt_copy_skb(struct bnxt_napi *bnapi, u8 *data,
1044 struct bnxt *bp = bnapi->bp;
1045 struct pci_dev *pdev = bp->pdev;
1046 struct sk_buff *skb;
1048 skb = napi_alloc_skb(&bnapi->napi, len);
1052 dma_sync_single_for_cpu(&pdev->dev, mapping, bp->rx_copy_thresh,
1055 memcpy(skb->data - NET_IP_ALIGN, data - NET_IP_ALIGN,
1056 len + NET_IP_ALIGN);
1058 dma_sync_single_for_device(&pdev->dev, mapping, bp->rx_copy_thresh,
1065 static int bnxt_discard_rx(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1066 u32 *raw_cons, void *cmp)
1068 struct rx_cmp *rxcmp = cmp;
1069 u32 tmp_raw_cons = *raw_cons;
1070 u8 cmp_type, agg_bufs = 0;
1072 cmp_type = RX_CMP_TYPE(rxcmp);
1074 if (cmp_type == CMP_TYPE_RX_L2_CMP) {
1075 agg_bufs = (le32_to_cpu(rxcmp->rx_cmp_misc_v1) &
1077 RX_CMP_AGG_BUFS_SHIFT;
1078 } else if (cmp_type == CMP_TYPE_RX_L2_TPA_END_CMP) {
1079 struct rx_tpa_end_cmp *tpa_end = cmp;
1081 agg_bufs = (le32_to_cpu(tpa_end->rx_tpa_end_cmp_misc_v1) &
1082 RX_TPA_END_CMP_AGG_BUFS) >>
1083 RX_TPA_END_CMP_AGG_BUFS_SHIFT;
1087 if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, &tmp_raw_cons))
1090 *raw_cons = tmp_raw_cons;
1094 static void bnxt_queue_sp_work(struct bnxt *bp)
1097 queue_work(bnxt_pf_wq, &bp->sp_task);
1099 schedule_work(&bp->sp_task);
1102 static void bnxt_cancel_sp_work(struct bnxt *bp)
1105 flush_workqueue(bnxt_pf_wq);
1107 cancel_work_sync(&bp->sp_task);
1110 static void bnxt_sched_reset(struct bnxt *bp, struct bnxt_rx_ring_info *rxr)
1112 if (!rxr->bnapi->in_reset) {
1113 rxr->bnapi->in_reset = true;
1114 set_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event);
1115 bnxt_queue_sp_work(bp);
1117 rxr->rx_next_cons = 0xffff;
1120 static void bnxt_tpa_start(struct bnxt *bp, struct bnxt_rx_ring_info *rxr,
1121 struct rx_tpa_start_cmp *tpa_start,
1122 struct rx_tpa_start_cmp_ext *tpa_start1)
1124 u8 agg_id = TPA_START_AGG_ID(tpa_start);
1126 struct bnxt_tpa_info *tpa_info;
1127 struct bnxt_sw_rx_bd *cons_rx_buf, *prod_rx_buf;
1128 struct rx_bd *prod_bd;
1131 cons = tpa_start->rx_tpa_start_cmp_opaque;
1132 prod = rxr->rx_prod;
1133 cons_rx_buf = &rxr->rx_buf_ring[cons];
1134 prod_rx_buf = &rxr->rx_buf_ring[prod];
1135 tpa_info = &rxr->rx_tpa[agg_id];
1137 if (unlikely(cons != rxr->rx_next_cons)) {
1138 netdev_warn(bp->dev, "TPA cons %x != expected cons %x\n",
1139 cons, rxr->rx_next_cons);
1140 bnxt_sched_reset(bp, rxr);
1143 /* Store cfa_code in tpa_info to use in tpa_end
1144 * completion processing.
1146 tpa_info->cfa_code = TPA_START_CFA_CODE(tpa_start1);
1147 prod_rx_buf->data = tpa_info->data;
1148 prod_rx_buf->data_ptr = tpa_info->data_ptr;
1150 mapping = tpa_info->mapping;
1151 prod_rx_buf->mapping = mapping;
1153 prod_bd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
1155 prod_bd->rx_bd_haddr = cpu_to_le64(mapping);
1157 tpa_info->data = cons_rx_buf->data;
1158 tpa_info->data_ptr = cons_rx_buf->data_ptr;
1159 cons_rx_buf->data = NULL;
1160 tpa_info->mapping = cons_rx_buf->mapping;
1163 le32_to_cpu(tpa_start->rx_tpa_start_cmp_len_flags_type) >>
1164 RX_TPA_START_CMP_LEN_SHIFT;
1165 if (likely(TPA_START_HASH_VALID(tpa_start))) {
1166 u32 hash_type = TPA_START_HASH_TYPE(tpa_start);
1168 tpa_info->hash_type = PKT_HASH_TYPE_L4;
1169 tpa_info->gso_type = SKB_GSO_TCPV4;
1170 /* RSS profiles 1 and 3 with extract code 0 for inner 4-tuple */
1171 if (hash_type == 3 || TPA_START_IS_IPV6(tpa_start1))
1172 tpa_info->gso_type = SKB_GSO_TCPV6;
1173 tpa_info->rss_hash =
1174 le32_to_cpu(tpa_start->rx_tpa_start_cmp_rss_hash);
1176 tpa_info->hash_type = PKT_HASH_TYPE_NONE;
1177 tpa_info->gso_type = 0;
1178 if (netif_msg_rx_err(bp))
1179 netdev_warn(bp->dev, "TPA packet without valid hash\n");
1181 tpa_info->flags2 = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_flags2);
1182 tpa_info->metadata = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_metadata);
1183 tpa_info->hdr_info = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_hdr_info);
1185 rxr->rx_prod = NEXT_RX(prod);
1186 cons = NEXT_RX(cons);
1187 rxr->rx_next_cons = NEXT_RX(cons);
1188 cons_rx_buf = &rxr->rx_buf_ring[cons];
1190 bnxt_reuse_rx_data(rxr, cons, cons_rx_buf->data);
1191 rxr->rx_prod = NEXT_RX(rxr->rx_prod);
1192 cons_rx_buf->data = NULL;
1195 static void bnxt_abort_tpa(struct bnxt_cp_ring_info *cpr, u16 cp_cons,
1199 bnxt_reuse_rx_agg_bufs(cpr, cp_cons, agg_bufs);
1202 static struct sk_buff *bnxt_gro_func_5731x(struct bnxt_tpa_info *tpa_info,
1203 int payload_off, int tcp_ts,
1204 struct sk_buff *skb)
1209 u16 outer_ip_off, inner_ip_off, inner_mac_off;
1210 u32 hdr_info = tpa_info->hdr_info;
1211 bool loopback = false;
1213 inner_ip_off = BNXT_TPA_INNER_L3_OFF(hdr_info);
1214 inner_mac_off = BNXT_TPA_INNER_L2_OFF(hdr_info);
1215 outer_ip_off = BNXT_TPA_OUTER_L3_OFF(hdr_info);
1217 /* If the packet is an internal loopback packet, the offsets will
1218 * have an extra 4 bytes.
1220 if (inner_mac_off == 4) {
1222 } else if (inner_mac_off > 4) {
1223 __be16 proto = *((__be16 *)(skb->data + inner_ip_off -
1226 /* We only support inner iPv4/ipv6. If we don't see the
1227 * correct protocol ID, it must be a loopback packet where
1228 * the offsets are off by 4.
1230 if (proto != htons(ETH_P_IP) && proto != htons(ETH_P_IPV6))
1234 /* internal loopback packet, subtract all offsets by 4 */
1240 nw_off = inner_ip_off - ETH_HLEN;
1241 skb_set_network_header(skb, nw_off);
1242 if (tpa_info->flags2 & RX_TPA_START_CMP_FLAGS2_IP_TYPE) {
1243 struct ipv6hdr *iph = ipv6_hdr(skb);
1245 skb_set_transport_header(skb, nw_off + sizeof(struct ipv6hdr));
1246 len = skb->len - skb_transport_offset(skb);
1248 th->check = ~tcp_v6_check(len, &iph->saddr, &iph->daddr, 0);
1250 struct iphdr *iph = ip_hdr(skb);
1252 skb_set_transport_header(skb, nw_off + sizeof(struct iphdr));
1253 len = skb->len - skb_transport_offset(skb);
1255 th->check = ~tcp_v4_check(len, iph->saddr, iph->daddr, 0);
1258 if (inner_mac_off) { /* tunnel */
1259 struct udphdr *uh = NULL;
1260 __be16 proto = *((__be16 *)(skb->data + outer_ip_off -
1263 if (proto == htons(ETH_P_IP)) {
1264 struct iphdr *iph = (struct iphdr *)skb->data;
1266 if (iph->protocol == IPPROTO_UDP)
1267 uh = (struct udphdr *)(iph + 1);
1269 struct ipv6hdr *iph = (struct ipv6hdr *)skb->data;
1271 if (iph->nexthdr == IPPROTO_UDP)
1272 uh = (struct udphdr *)(iph + 1);
1276 skb_shinfo(skb)->gso_type |=
1277 SKB_GSO_UDP_TUNNEL_CSUM;
1279 skb_shinfo(skb)->gso_type |= SKB_GSO_UDP_TUNNEL;
1286 #define BNXT_IPV4_HDR_SIZE (sizeof(struct iphdr) + sizeof(struct tcphdr))
1287 #define BNXT_IPV6_HDR_SIZE (sizeof(struct ipv6hdr) + sizeof(struct tcphdr))
1289 static struct sk_buff *bnxt_gro_func_5730x(struct bnxt_tpa_info *tpa_info,
1290 int payload_off, int tcp_ts,
1291 struct sk_buff *skb)
1295 int len, nw_off, tcp_opt_len = 0;
1300 if (tpa_info->gso_type == SKB_GSO_TCPV4) {
1303 nw_off = payload_off - BNXT_IPV4_HDR_SIZE - tcp_opt_len -
1305 skb_set_network_header(skb, nw_off);
1307 skb_set_transport_header(skb, nw_off + sizeof(struct iphdr));
1308 len = skb->len - skb_transport_offset(skb);
1310 th->check = ~tcp_v4_check(len, iph->saddr, iph->daddr, 0);
1311 } else if (tpa_info->gso_type == SKB_GSO_TCPV6) {
1312 struct ipv6hdr *iph;
1314 nw_off = payload_off - BNXT_IPV6_HDR_SIZE - tcp_opt_len -
1316 skb_set_network_header(skb, nw_off);
1317 iph = ipv6_hdr(skb);
1318 skb_set_transport_header(skb, nw_off + sizeof(struct ipv6hdr));
1319 len = skb->len - skb_transport_offset(skb);
1321 th->check = ~tcp_v6_check(len, &iph->saddr, &iph->daddr, 0);
1323 dev_kfree_skb_any(skb);
1327 if (nw_off) { /* tunnel */
1328 struct udphdr *uh = NULL;
1330 if (skb->protocol == htons(ETH_P_IP)) {
1331 struct iphdr *iph = (struct iphdr *)skb->data;
1333 if (iph->protocol == IPPROTO_UDP)
1334 uh = (struct udphdr *)(iph + 1);
1336 struct ipv6hdr *iph = (struct ipv6hdr *)skb->data;
1338 if (iph->nexthdr == IPPROTO_UDP)
1339 uh = (struct udphdr *)(iph + 1);
1343 skb_shinfo(skb)->gso_type |=
1344 SKB_GSO_UDP_TUNNEL_CSUM;
1346 skb_shinfo(skb)->gso_type |= SKB_GSO_UDP_TUNNEL;
1353 static inline struct sk_buff *bnxt_gro_skb(struct bnxt *bp,
1354 struct bnxt_tpa_info *tpa_info,
1355 struct rx_tpa_end_cmp *tpa_end,
1356 struct rx_tpa_end_cmp_ext *tpa_end1,
1357 struct sk_buff *skb)
1363 segs = TPA_END_TPA_SEGS(tpa_end);
1367 NAPI_GRO_CB(skb)->count = segs;
1368 skb_shinfo(skb)->gso_size =
1369 le32_to_cpu(tpa_end1->rx_tpa_end_cmp_seg_len);
1370 skb_shinfo(skb)->gso_type = tpa_info->gso_type;
1371 payload_off = (le32_to_cpu(tpa_end->rx_tpa_end_cmp_misc_v1) &
1372 RX_TPA_END_CMP_PAYLOAD_OFFSET) >>
1373 RX_TPA_END_CMP_PAYLOAD_OFFSET_SHIFT;
1374 skb = bp->gro_func(tpa_info, payload_off, TPA_END_GRO_TS(tpa_end), skb);
1376 tcp_gro_complete(skb);
1381 /* Given the cfa_code of a received packet determine which
1382 * netdev (vf-rep or PF) the packet is destined to.
1384 static struct net_device *bnxt_get_pkt_dev(struct bnxt *bp, u16 cfa_code)
1386 struct net_device *dev = bnxt_get_vf_rep(bp, cfa_code);
1388 /* if vf-rep dev is NULL, the must belongs to the PF */
1389 return dev ? dev : bp->dev;
1392 static inline struct sk_buff *bnxt_tpa_end(struct bnxt *bp,
1393 struct bnxt_cp_ring_info *cpr,
1395 struct rx_tpa_end_cmp *tpa_end,
1396 struct rx_tpa_end_cmp_ext *tpa_end1,
1399 struct bnxt_napi *bnapi = cpr->bnapi;
1400 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
1401 u8 agg_id = TPA_END_AGG_ID(tpa_end);
1402 u8 *data_ptr, agg_bufs;
1403 u16 cp_cons = RING_CMP(*raw_cons);
1405 struct bnxt_tpa_info *tpa_info;
1407 struct sk_buff *skb;
1410 if (unlikely(bnapi->in_reset)) {
1411 int rc = bnxt_discard_rx(bp, cpr, raw_cons, tpa_end);
1414 return ERR_PTR(-EBUSY);
1418 tpa_info = &rxr->rx_tpa[agg_id];
1419 data = tpa_info->data;
1420 data_ptr = tpa_info->data_ptr;
1422 len = tpa_info->len;
1423 mapping = tpa_info->mapping;
1425 agg_bufs = (le32_to_cpu(tpa_end->rx_tpa_end_cmp_misc_v1) &
1426 RX_TPA_END_CMP_AGG_BUFS) >> RX_TPA_END_CMP_AGG_BUFS_SHIFT;
1429 if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, raw_cons))
1430 return ERR_PTR(-EBUSY);
1432 *event |= BNXT_AGG_EVENT;
1433 cp_cons = NEXT_CMP(cp_cons);
1436 if (unlikely(agg_bufs > MAX_SKB_FRAGS || TPA_END_ERRORS(tpa_end1))) {
1437 bnxt_abort_tpa(cpr, cp_cons, agg_bufs);
1438 if (agg_bufs > MAX_SKB_FRAGS)
1439 netdev_warn(bp->dev, "TPA frags %d exceeded MAX_SKB_FRAGS %d\n",
1440 agg_bufs, (int)MAX_SKB_FRAGS);
1444 if (len <= bp->rx_copy_thresh) {
1445 skb = bnxt_copy_skb(bnapi, data_ptr, len, mapping);
1447 bnxt_abort_tpa(cpr, cp_cons, agg_bufs);
1452 dma_addr_t new_mapping;
1454 new_data = __bnxt_alloc_rx_data(bp, &new_mapping, GFP_ATOMIC);
1456 bnxt_abort_tpa(cpr, cp_cons, agg_bufs);
1460 tpa_info->data = new_data;
1461 tpa_info->data_ptr = new_data + bp->rx_offset;
1462 tpa_info->mapping = new_mapping;
1464 skb = build_skb(data, 0);
1465 dma_unmap_single_attrs(&bp->pdev->dev, mapping,
1466 bp->rx_buf_use_size, bp->rx_dir,
1467 DMA_ATTR_WEAK_ORDERING);
1471 bnxt_abort_tpa(cpr, cp_cons, agg_bufs);
1474 skb_reserve(skb, bp->rx_offset);
1479 skb = bnxt_rx_pages(bp, cpr, skb, cp_cons, agg_bufs);
1481 /* Page reuse already handled by bnxt_rx_pages(). */
1487 eth_type_trans(skb, bnxt_get_pkt_dev(bp, tpa_info->cfa_code));
1489 if (tpa_info->hash_type != PKT_HASH_TYPE_NONE)
1490 skb_set_hash(skb, tpa_info->rss_hash, tpa_info->hash_type);
1492 if ((tpa_info->flags2 & RX_CMP_FLAGS2_META_FORMAT_VLAN) &&
1493 (skb->dev->features & NETIF_F_HW_VLAN_CTAG_RX)) {
1494 u16 vlan_proto = tpa_info->metadata >>
1495 RX_CMP_FLAGS2_METADATA_TPID_SFT;
1496 u16 vtag = tpa_info->metadata & RX_CMP_FLAGS2_METADATA_TCI_MASK;
1498 __vlan_hwaccel_put_tag(skb, htons(vlan_proto), vtag);
1501 skb_checksum_none_assert(skb);
1502 if (likely(tpa_info->flags2 & RX_TPA_START_CMP_FLAGS2_L4_CS_CALC)) {
1503 skb->ip_summed = CHECKSUM_UNNECESSARY;
1505 (tpa_info->flags2 & RX_CMP_FLAGS2_T_L4_CS_CALC) >> 3;
1508 if (TPA_END_GRO(tpa_end))
1509 skb = bnxt_gro_skb(bp, tpa_info, tpa_end, tpa_end1, skb);
1514 static void bnxt_deliver_skb(struct bnxt *bp, struct bnxt_napi *bnapi,
1515 struct sk_buff *skb)
1517 if (skb->dev != bp->dev) {
1518 /* this packet belongs to a vf-rep */
1519 bnxt_vf_rep_rx(bp, skb);
1522 skb_record_rx_queue(skb, bnapi->index);
1523 napi_gro_receive(&bnapi->napi, skb);
1526 /* returns the following:
1527 * 1 - 1 packet successfully received
1528 * 0 - successful TPA_START, packet not completed yet
1529 * -EBUSY - completion ring does not have all the agg buffers yet
1530 * -ENOMEM - packet aborted due to out of memory
1531 * -EIO - packet aborted due to hw error indicated in BD
1533 static int bnxt_rx_pkt(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1534 u32 *raw_cons, u8 *event)
1536 struct bnxt_napi *bnapi = cpr->bnapi;
1537 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
1538 struct net_device *dev = bp->dev;
1539 struct rx_cmp *rxcmp;
1540 struct rx_cmp_ext *rxcmp1;
1541 u32 tmp_raw_cons = *raw_cons;
1542 u16 cfa_code, cons, prod, cp_cons = RING_CMP(tmp_raw_cons);
1543 struct bnxt_sw_rx_bd *rx_buf;
1545 u8 *data_ptr, agg_bufs, cmp_type;
1546 dma_addr_t dma_addr;
1547 struct sk_buff *skb;
1552 rxcmp = (struct rx_cmp *)
1553 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1555 tmp_raw_cons = NEXT_RAW_CMP(tmp_raw_cons);
1556 cp_cons = RING_CMP(tmp_raw_cons);
1557 rxcmp1 = (struct rx_cmp_ext *)
1558 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1560 if (!RX_CMP_VALID(rxcmp1, tmp_raw_cons))
1563 cmp_type = RX_CMP_TYPE(rxcmp);
1565 prod = rxr->rx_prod;
1567 if (cmp_type == CMP_TYPE_RX_L2_TPA_START_CMP) {
1568 bnxt_tpa_start(bp, rxr, (struct rx_tpa_start_cmp *)rxcmp,
1569 (struct rx_tpa_start_cmp_ext *)rxcmp1);
1571 *event |= BNXT_RX_EVENT;
1572 goto next_rx_no_prod_no_len;
1574 } else if (cmp_type == CMP_TYPE_RX_L2_TPA_END_CMP) {
1575 skb = bnxt_tpa_end(bp, cpr, &tmp_raw_cons,
1576 (struct rx_tpa_end_cmp *)rxcmp,
1577 (struct rx_tpa_end_cmp_ext *)rxcmp1, event);
1584 bnxt_deliver_skb(bp, bnapi, skb);
1587 *event |= BNXT_RX_EVENT;
1588 goto next_rx_no_prod_no_len;
1591 cons = rxcmp->rx_cmp_opaque;
1592 if (unlikely(cons != rxr->rx_next_cons)) {
1593 int rc1 = bnxt_discard_rx(bp, cpr, raw_cons, rxcmp);
1595 netdev_warn(bp->dev, "RX cons %x != expected cons %x\n",
1596 cons, rxr->rx_next_cons);
1597 bnxt_sched_reset(bp, rxr);
1600 rx_buf = &rxr->rx_buf_ring[cons];
1601 data = rx_buf->data;
1602 data_ptr = rx_buf->data_ptr;
1605 misc = le32_to_cpu(rxcmp->rx_cmp_misc_v1);
1606 agg_bufs = (misc & RX_CMP_AGG_BUFS) >> RX_CMP_AGG_BUFS_SHIFT;
1609 if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, &tmp_raw_cons))
1612 cp_cons = NEXT_CMP(cp_cons);
1613 *event |= BNXT_AGG_EVENT;
1615 *event |= BNXT_RX_EVENT;
1617 rx_buf->data = NULL;
1618 if (rxcmp1->rx_cmp_cfa_code_errors_v2 & RX_CMP_L2_ERRORS) {
1619 u32 rx_err = le32_to_cpu(rxcmp1->rx_cmp_cfa_code_errors_v2);
1621 bnxt_reuse_rx_data(rxr, cons, data);
1623 bnxt_reuse_rx_agg_bufs(cpr, cp_cons, agg_bufs);
1626 if (rx_err & RX_CMPL_ERRORS_BUFFER_ERROR_MASK) {
1627 netdev_warn(bp->dev, "RX buffer error %x\n", rx_err);
1628 bnxt_sched_reset(bp, rxr);
1630 goto next_rx_no_len;
1633 len = le32_to_cpu(rxcmp->rx_cmp_len_flags_type) >> RX_CMP_LEN_SHIFT;
1634 dma_addr = rx_buf->mapping;
1636 if (bnxt_rx_xdp(bp, rxr, cons, data, &data_ptr, &len, event)) {
1641 if (len <= bp->rx_copy_thresh) {
1642 skb = bnxt_copy_skb(bnapi, data_ptr, len, dma_addr);
1643 bnxt_reuse_rx_data(rxr, cons, data);
1646 bnxt_reuse_rx_agg_bufs(cpr, cp_cons, agg_bufs);
1653 if (rx_buf->data_ptr == data_ptr)
1654 payload = misc & RX_CMP_PAYLOAD_OFFSET;
1657 skb = bp->rx_skb_func(bp, rxr, cons, data, data_ptr, dma_addr,
1666 skb = bnxt_rx_pages(bp, cpr, skb, cp_cons, agg_bufs);
1673 if (RX_CMP_HASH_VALID(rxcmp)) {
1674 u32 hash_type = RX_CMP_HASH_TYPE(rxcmp);
1675 enum pkt_hash_types type = PKT_HASH_TYPE_L4;
1677 /* RSS profiles 1 and 3 with extract code 0 for inner 4-tuple */
1678 if (hash_type != 1 && hash_type != 3)
1679 type = PKT_HASH_TYPE_L3;
1680 skb_set_hash(skb, le32_to_cpu(rxcmp->rx_cmp_rss_hash), type);
1683 cfa_code = RX_CMP_CFA_CODE(rxcmp1);
1684 skb->protocol = eth_type_trans(skb, bnxt_get_pkt_dev(bp, cfa_code));
1686 if ((rxcmp1->rx_cmp_flags2 &
1687 cpu_to_le32(RX_CMP_FLAGS2_META_FORMAT_VLAN)) &&
1688 (skb->dev->features & NETIF_F_HW_VLAN_CTAG_RX)) {
1689 u32 meta_data = le32_to_cpu(rxcmp1->rx_cmp_meta_data);
1690 u16 vtag = meta_data & RX_CMP_FLAGS2_METADATA_TCI_MASK;
1691 u16 vlan_proto = meta_data >> RX_CMP_FLAGS2_METADATA_TPID_SFT;
1693 __vlan_hwaccel_put_tag(skb, htons(vlan_proto), vtag);
1696 skb_checksum_none_assert(skb);
1697 if (RX_CMP_L4_CS_OK(rxcmp1)) {
1698 if (dev->features & NETIF_F_RXCSUM) {
1699 skb->ip_summed = CHECKSUM_UNNECESSARY;
1700 skb->csum_level = RX_CMP_ENCAP(rxcmp1);
1703 if (rxcmp1->rx_cmp_cfa_code_errors_v2 & RX_CMP_L4_CS_ERR_BITS) {
1704 if (dev->features & NETIF_F_RXCSUM)
1705 bnapi->cp_ring.rx_l4_csum_errors++;
1709 bnxt_deliver_skb(bp, bnapi, skb);
1713 cpr->rx_packets += 1;
1714 cpr->rx_bytes += len;
1717 rxr->rx_prod = NEXT_RX(prod);
1718 rxr->rx_next_cons = NEXT_RX(cons);
1720 next_rx_no_prod_no_len:
1721 *raw_cons = tmp_raw_cons;
1726 /* In netpoll mode, if we are using a combined completion ring, we need to
1727 * discard the rx packets and recycle the buffers.
1729 static int bnxt_force_rx_discard(struct bnxt *bp,
1730 struct bnxt_cp_ring_info *cpr,
1731 u32 *raw_cons, u8 *event)
1733 u32 tmp_raw_cons = *raw_cons;
1734 struct rx_cmp_ext *rxcmp1;
1735 struct rx_cmp *rxcmp;
1739 cp_cons = RING_CMP(tmp_raw_cons);
1740 rxcmp = (struct rx_cmp *)
1741 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1743 tmp_raw_cons = NEXT_RAW_CMP(tmp_raw_cons);
1744 cp_cons = RING_CMP(tmp_raw_cons);
1745 rxcmp1 = (struct rx_cmp_ext *)
1746 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1748 if (!RX_CMP_VALID(rxcmp1, tmp_raw_cons))
1751 cmp_type = RX_CMP_TYPE(rxcmp);
1752 if (cmp_type == CMP_TYPE_RX_L2_CMP) {
1753 rxcmp1->rx_cmp_cfa_code_errors_v2 |=
1754 cpu_to_le32(RX_CMPL_ERRORS_CRC_ERROR);
1755 } else if (cmp_type == CMP_TYPE_RX_L2_TPA_END_CMP) {
1756 struct rx_tpa_end_cmp_ext *tpa_end1;
1758 tpa_end1 = (struct rx_tpa_end_cmp_ext *)rxcmp1;
1759 tpa_end1->rx_tpa_end_cmp_errors_v2 |=
1760 cpu_to_le32(RX_TPA_END_CMP_ERRORS);
1762 return bnxt_rx_pkt(bp, cpr, raw_cons, event);
1765 #define BNXT_GET_EVENT_PORT(data) \
1767 ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK)
1769 static int bnxt_async_event_process(struct bnxt *bp,
1770 struct hwrm_async_event_cmpl *cmpl)
1772 u16 event_id = le16_to_cpu(cmpl->event_id);
1774 /* TODO CHIMP_FW: Define event id's for link change, error etc */
1776 case ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE: {
1777 u32 data1 = le32_to_cpu(cmpl->event_data1);
1778 struct bnxt_link_info *link_info = &bp->link_info;
1781 goto async_event_process_exit;
1783 /* print unsupported speed warning in forced speed mode only */
1784 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED) &&
1785 (data1 & 0x20000)) {
1786 u16 fw_speed = link_info->force_link_speed;
1787 u32 speed = bnxt_fw_to_ethtool_speed(fw_speed);
1789 if (speed != SPEED_UNKNOWN)
1790 netdev_warn(bp->dev, "Link speed %d no longer supported\n",
1793 set_bit(BNXT_LINK_SPEED_CHNG_SP_EVENT, &bp->sp_event);
1796 case ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE:
1797 set_bit(BNXT_LINK_CHNG_SP_EVENT, &bp->sp_event);
1799 case ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD:
1800 set_bit(BNXT_HWRM_PF_UNLOAD_SP_EVENT, &bp->sp_event);
1802 case ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED: {
1803 u32 data1 = le32_to_cpu(cmpl->event_data1);
1804 u16 port_id = BNXT_GET_EVENT_PORT(data1);
1809 if (bp->pf.port_id != port_id)
1812 set_bit(BNXT_HWRM_PORT_MODULE_SP_EVENT, &bp->sp_event);
1815 case ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE:
1817 goto async_event_process_exit;
1818 set_bit(BNXT_RESET_TASK_SILENT_SP_EVENT, &bp->sp_event);
1821 goto async_event_process_exit;
1823 bnxt_queue_sp_work(bp);
1824 async_event_process_exit:
1825 bnxt_ulp_async_events(bp, cmpl);
1829 static int bnxt_hwrm_handler(struct bnxt *bp, struct tx_cmp *txcmp)
1831 u16 cmpl_type = TX_CMP_TYPE(txcmp), vf_id, seq_id;
1832 struct hwrm_cmpl *h_cmpl = (struct hwrm_cmpl *)txcmp;
1833 struct hwrm_fwd_req_cmpl *fwd_req_cmpl =
1834 (struct hwrm_fwd_req_cmpl *)txcmp;
1836 switch (cmpl_type) {
1837 case CMPL_BASE_TYPE_HWRM_DONE:
1838 seq_id = le16_to_cpu(h_cmpl->sequence_id);
1839 if (seq_id == bp->hwrm_intr_seq_id)
1840 bp->hwrm_intr_seq_id = (u16)~bp->hwrm_intr_seq_id;
1842 netdev_err(bp->dev, "Invalid hwrm seq id %d\n", seq_id);
1845 case CMPL_BASE_TYPE_HWRM_FWD_REQ:
1846 vf_id = le16_to_cpu(fwd_req_cmpl->source_id);
1848 if ((vf_id < bp->pf.first_vf_id) ||
1849 (vf_id >= bp->pf.first_vf_id + bp->pf.active_vfs)) {
1850 netdev_err(bp->dev, "Msg contains invalid VF id %x\n",
1855 set_bit(vf_id - bp->pf.first_vf_id, bp->pf.vf_event_bmap);
1856 set_bit(BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT, &bp->sp_event);
1857 bnxt_queue_sp_work(bp);
1860 case CMPL_BASE_TYPE_HWRM_ASYNC_EVENT:
1861 bnxt_async_event_process(bp,
1862 (struct hwrm_async_event_cmpl *)txcmp);
1871 static irqreturn_t bnxt_msix(int irq, void *dev_instance)
1873 struct bnxt_napi *bnapi = dev_instance;
1874 struct bnxt *bp = bnapi->bp;
1875 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1876 u32 cons = RING_CMP(cpr->cp_raw_cons);
1879 prefetch(&cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]);
1880 napi_schedule(&bnapi->napi);
1884 static inline int bnxt_has_work(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1886 u32 raw_cons = cpr->cp_raw_cons;
1887 u16 cons = RING_CMP(raw_cons);
1888 struct tx_cmp *txcmp;
1890 txcmp = &cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)];
1892 return TX_CMP_VALID(txcmp, raw_cons);
1895 static irqreturn_t bnxt_inta(int irq, void *dev_instance)
1897 struct bnxt_napi *bnapi = dev_instance;
1898 struct bnxt *bp = bnapi->bp;
1899 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1900 u32 cons = RING_CMP(cpr->cp_raw_cons);
1903 prefetch(&cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]);
1905 if (!bnxt_has_work(bp, cpr)) {
1906 int_status = readl(bp->bar0 + BNXT_CAG_REG_LEGACY_INT_STATUS);
1907 /* return if erroneous interrupt */
1908 if (!(int_status & (0x10000 << cpr->cp_ring_struct.fw_ring_id)))
1912 /* disable ring IRQ */
1913 BNXT_CP_DB_IRQ_DIS(cpr->cp_db.doorbell);
1915 /* Return here if interrupt is shared and is disabled. */
1916 if (unlikely(atomic_read(&bp->intr_sem) != 0))
1919 napi_schedule(&bnapi->napi);
1923 static int __bnxt_poll_work(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1926 struct bnxt_napi *bnapi = cpr->bnapi;
1927 u32 raw_cons = cpr->cp_raw_cons;
1932 struct tx_cmp *txcmp;
1934 cpr->has_more_work = 0;
1938 cons = RING_CMP(raw_cons);
1939 txcmp = &cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)];
1941 if (!TX_CMP_VALID(txcmp, raw_cons))
1944 /* The valid test of the entry must be done first before
1945 * reading any further.
1948 cpr->had_work_done = 1;
1949 if (TX_CMP_TYPE(txcmp) == CMP_TYPE_TX_L2_CMP) {
1951 /* return full budget so NAPI will complete. */
1952 if (unlikely(tx_pkts > bp->tx_wake_thresh)) {
1954 raw_cons = NEXT_RAW_CMP(raw_cons);
1956 cpr->has_more_work = 1;
1959 } else if ((TX_CMP_TYPE(txcmp) & 0x30) == 0x10) {
1961 rc = bnxt_rx_pkt(bp, cpr, &raw_cons, &event);
1963 rc = bnxt_force_rx_discard(bp, cpr, &raw_cons,
1965 if (likely(rc >= 0))
1967 /* Increment rx_pkts when rc is -ENOMEM to count towards
1968 * the NAPI budget. Otherwise, we may potentially loop
1969 * here forever if we consistently cannot allocate
1972 else if (rc == -ENOMEM && budget)
1974 else if (rc == -EBUSY) /* partial completion */
1976 } else if (unlikely((TX_CMP_TYPE(txcmp) ==
1977 CMPL_BASE_TYPE_HWRM_DONE) ||
1978 (TX_CMP_TYPE(txcmp) ==
1979 CMPL_BASE_TYPE_HWRM_FWD_REQ) ||
1980 (TX_CMP_TYPE(txcmp) ==
1981 CMPL_BASE_TYPE_HWRM_ASYNC_EVENT))) {
1982 bnxt_hwrm_handler(bp, txcmp);
1984 raw_cons = NEXT_RAW_CMP(raw_cons);
1986 if (rx_pkts && rx_pkts == budget) {
1987 cpr->has_more_work = 1;
1992 if (event & BNXT_TX_EVENT) {
1993 struct bnxt_tx_ring_info *txr = bnapi->tx_ring;
1994 u16 prod = txr->tx_prod;
1996 /* Sync BD data before updating doorbell */
1999 bnxt_db_write_relaxed(bp, &txr->tx_db, prod);
2002 cpr->cp_raw_cons = raw_cons;
2003 bnapi->tx_pkts += tx_pkts;
2004 bnapi->events |= event;
2008 static void __bnxt_poll_work_done(struct bnxt *bp, struct bnxt_napi *bnapi)
2010 if (bnapi->tx_pkts) {
2011 bnapi->tx_int(bp, bnapi, bnapi->tx_pkts);
2015 if (bnapi->events & BNXT_RX_EVENT) {
2016 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
2018 bnxt_db_write(bp, &rxr->rx_db, rxr->rx_prod);
2019 if (bnapi->events & BNXT_AGG_EVENT)
2020 bnxt_db_write(bp, &rxr->rx_agg_db, rxr->rx_agg_prod);
2025 static int bnxt_poll_work(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
2028 struct bnxt_napi *bnapi = cpr->bnapi;
2031 rx_pkts = __bnxt_poll_work(bp, cpr, budget);
2033 /* ACK completion ring before freeing tx ring and producing new
2034 * buffers in rx/agg rings to prevent overflowing the completion
2037 bnxt_db_cq(bp, &cpr->cp_db, cpr->cp_raw_cons);
2039 __bnxt_poll_work_done(bp, bnapi);
2043 static int bnxt_poll_nitroa0(struct napi_struct *napi, int budget)
2045 struct bnxt_napi *bnapi = container_of(napi, struct bnxt_napi, napi);
2046 struct bnxt *bp = bnapi->bp;
2047 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
2048 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
2049 struct tx_cmp *txcmp;
2050 struct rx_cmp_ext *rxcmp1;
2051 u32 cp_cons, tmp_raw_cons;
2052 u32 raw_cons = cpr->cp_raw_cons;
2059 cp_cons = RING_CMP(raw_cons);
2060 txcmp = &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
2062 if (!TX_CMP_VALID(txcmp, raw_cons))
2065 if ((TX_CMP_TYPE(txcmp) & 0x30) == 0x10) {
2066 tmp_raw_cons = NEXT_RAW_CMP(raw_cons);
2067 cp_cons = RING_CMP(tmp_raw_cons);
2068 rxcmp1 = (struct rx_cmp_ext *)
2069 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
2071 if (!RX_CMP_VALID(rxcmp1, tmp_raw_cons))
2074 /* force an error to recycle the buffer */
2075 rxcmp1->rx_cmp_cfa_code_errors_v2 |=
2076 cpu_to_le32(RX_CMPL_ERRORS_CRC_ERROR);
2078 rc = bnxt_rx_pkt(bp, cpr, &raw_cons, &event);
2079 if (likely(rc == -EIO) && budget)
2081 else if (rc == -EBUSY) /* partial completion */
2083 } else if (unlikely(TX_CMP_TYPE(txcmp) ==
2084 CMPL_BASE_TYPE_HWRM_DONE)) {
2085 bnxt_hwrm_handler(bp, txcmp);
2088 "Invalid completion received on special ring\n");
2090 raw_cons = NEXT_RAW_CMP(raw_cons);
2092 if (rx_pkts == budget)
2096 cpr->cp_raw_cons = raw_cons;
2097 BNXT_DB_CQ(&cpr->cp_db, cpr->cp_raw_cons);
2098 bnxt_db_write(bp, &rxr->rx_db, rxr->rx_prod);
2100 if (event & BNXT_AGG_EVENT)
2101 bnxt_db_write(bp, &rxr->rx_agg_db, rxr->rx_agg_prod);
2103 if (!bnxt_has_work(bp, cpr) && rx_pkts < budget) {
2104 napi_complete_done(napi, rx_pkts);
2105 BNXT_DB_CQ_ARM(&cpr->cp_db, cpr->cp_raw_cons);
2110 static int bnxt_poll(struct napi_struct *napi, int budget)
2112 struct bnxt_napi *bnapi = container_of(napi, struct bnxt_napi, napi);
2113 struct bnxt *bp = bnapi->bp;
2114 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
2118 work_done += bnxt_poll_work(bp, cpr, budget - work_done);
2120 if (work_done >= budget) {
2122 BNXT_DB_CQ_ARM(&cpr->cp_db, cpr->cp_raw_cons);
2126 if (!bnxt_has_work(bp, cpr)) {
2127 if (napi_complete_done(napi, work_done))
2128 BNXT_DB_CQ_ARM(&cpr->cp_db, cpr->cp_raw_cons);
2132 if (bp->flags & BNXT_FLAG_DIM) {
2133 struct net_dim_sample dim_sample;
2135 net_dim_sample(cpr->event_ctr,
2139 net_dim(&cpr->dim, dim_sample);
2144 static int __bnxt_poll_cqs(struct bnxt *bp, struct bnxt_napi *bnapi, int budget)
2146 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
2147 int i, work_done = 0;
2149 for (i = 0; i < 2; i++) {
2150 struct bnxt_cp_ring_info *cpr2 = cpr->cp_ring_arr[i];
2153 work_done += __bnxt_poll_work(bp, cpr2,
2154 budget - work_done);
2155 cpr->has_more_work |= cpr2->has_more_work;
2161 static void __bnxt_poll_cqs_done(struct bnxt *bp, struct bnxt_napi *bnapi,
2162 u64 dbr_type, bool all)
2164 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
2167 for (i = 0; i < 2; i++) {
2168 struct bnxt_cp_ring_info *cpr2 = cpr->cp_ring_arr[i];
2169 struct bnxt_db_info *db;
2171 if (cpr2 && (all || cpr2->had_work_done)) {
2173 writeq(db->db_key64 | dbr_type |
2174 RING_CMP(cpr2->cp_raw_cons), db->doorbell);
2175 cpr2->had_work_done = 0;
2178 __bnxt_poll_work_done(bp, bnapi);
2181 static int bnxt_poll_p5(struct napi_struct *napi, int budget)
2183 struct bnxt_napi *bnapi = container_of(napi, struct bnxt_napi, napi);
2184 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
2185 u32 raw_cons = cpr->cp_raw_cons;
2186 struct bnxt *bp = bnapi->bp;
2187 struct nqe_cn *nqcmp;
2191 if (cpr->has_more_work) {
2192 cpr->has_more_work = 0;
2193 work_done = __bnxt_poll_cqs(bp, bnapi, budget);
2194 if (cpr->has_more_work) {
2195 __bnxt_poll_cqs_done(bp, bnapi, DBR_TYPE_CQ, false);
2198 __bnxt_poll_cqs_done(bp, bnapi, DBR_TYPE_CQ_ARMALL, true);
2199 if (napi_complete_done(napi, work_done))
2200 BNXT_DB_NQ_ARM_P5(&cpr->cp_db, cpr->cp_raw_cons);
2204 cons = RING_CMP(raw_cons);
2205 nqcmp = &cpr->nq_desc_ring[CP_RING(cons)][CP_IDX(cons)];
2207 if (!NQ_CMP_VALID(nqcmp, raw_cons)) {
2208 __bnxt_poll_cqs_done(bp, bnapi, DBR_TYPE_CQ_ARMALL,
2210 cpr->cp_raw_cons = raw_cons;
2211 if (napi_complete_done(napi, work_done))
2212 BNXT_DB_NQ_ARM_P5(&cpr->cp_db,
2217 /* The valid test of the entry must be done first before
2218 * reading any further.
2222 if (nqcmp->type == cpu_to_le16(NQ_CN_TYPE_CQ_NOTIFICATION)) {
2223 u32 idx = le32_to_cpu(nqcmp->cq_handle_low);
2224 struct bnxt_cp_ring_info *cpr2;
2226 cpr2 = cpr->cp_ring_arr[idx];
2227 work_done += __bnxt_poll_work(bp, cpr2,
2228 budget - work_done);
2229 cpr->has_more_work = cpr2->has_more_work;
2231 bnxt_hwrm_handler(bp, (struct tx_cmp *)nqcmp);
2233 raw_cons = NEXT_RAW_CMP(raw_cons);
2234 if (cpr->has_more_work)
2237 __bnxt_poll_cqs_done(bp, bnapi, DBR_TYPE_CQ, true);
2238 cpr->cp_raw_cons = raw_cons;
2242 static void bnxt_free_tx_skbs(struct bnxt *bp)
2245 struct pci_dev *pdev = bp->pdev;
2250 max_idx = bp->tx_nr_pages * TX_DESC_CNT;
2251 for (i = 0; i < bp->tx_nr_rings; i++) {
2252 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
2255 for (j = 0; j < max_idx;) {
2256 struct bnxt_sw_tx_bd *tx_buf = &txr->tx_buf_ring[j];
2257 struct sk_buff *skb = tx_buf->skb;
2267 if (tx_buf->is_push) {
2273 dma_unmap_single(&pdev->dev,
2274 dma_unmap_addr(tx_buf, mapping),
2278 last = tx_buf->nr_frags;
2280 for (k = 0; k < last; k++, j++) {
2281 int ring_idx = j & bp->tx_ring_mask;
2282 skb_frag_t *frag = &skb_shinfo(skb)->frags[k];
2284 tx_buf = &txr->tx_buf_ring[ring_idx];
2287 dma_unmap_addr(tx_buf, mapping),
2288 skb_frag_size(frag), PCI_DMA_TODEVICE);
2292 netdev_tx_reset_queue(netdev_get_tx_queue(bp->dev, i));
2296 static void bnxt_free_rx_skbs(struct bnxt *bp)
2298 int i, max_idx, max_agg_idx;
2299 struct pci_dev *pdev = bp->pdev;
2304 max_idx = bp->rx_nr_pages * RX_DESC_CNT;
2305 max_agg_idx = bp->rx_agg_nr_pages * RX_DESC_CNT;
2306 for (i = 0; i < bp->rx_nr_rings; i++) {
2307 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
2311 for (j = 0; j < MAX_TPA; j++) {
2312 struct bnxt_tpa_info *tpa_info =
2314 u8 *data = tpa_info->data;
2319 dma_unmap_single_attrs(&pdev->dev,
2321 bp->rx_buf_use_size,
2323 DMA_ATTR_WEAK_ORDERING);
2325 tpa_info->data = NULL;
2331 for (j = 0; j < max_idx; j++) {
2332 struct bnxt_sw_rx_bd *rx_buf = &rxr->rx_buf_ring[j];
2333 dma_addr_t mapping = rx_buf->mapping;
2334 void *data = rx_buf->data;
2339 rx_buf->data = NULL;
2341 if (BNXT_RX_PAGE_MODE(bp)) {
2342 mapping -= bp->rx_dma_offset;
2343 dma_unmap_page_attrs(&pdev->dev, mapping,
2344 PAGE_SIZE, bp->rx_dir,
2345 DMA_ATTR_WEAK_ORDERING);
2348 dma_unmap_single_attrs(&pdev->dev, mapping,
2349 bp->rx_buf_use_size,
2351 DMA_ATTR_WEAK_ORDERING);
2356 for (j = 0; j < max_agg_idx; j++) {
2357 struct bnxt_sw_rx_agg_bd *rx_agg_buf =
2358 &rxr->rx_agg_ring[j];
2359 struct page *page = rx_agg_buf->page;
2364 dma_unmap_page_attrs(&pdev->dev, rx_agg_buf->mapping,
2367 DMA_ATTR_WEAK_ORDERING);
2369 rx_agg_buf->page = NULL;
2370 __clear_bit(j, rxr->rx_agg_bmap);
2375 __free_page(rxr->rx_page);
2376 rxr->rx_page = NULL;
2381 static void bnxt_free_skbs(struct bnxt *bp)
2383 bnxt_free_tx_skbs(bp);
2384 bnxt_free_rx_skbs(bp);
2387 static void bnxt_free_ring(struct bnxt *bp, struct bnxt_ring_mem_info *rmem)
2389 struct pci_dev *pdev = bp->pdev;
2392 for (i = 0; i < rmem->nr_pages; i++) {
2393 if (!rmem->pg_arr[i])
2396 dma_free_coherent(&pdev->dev, rmem->page_size,
2397 rmem->pg_arr[i], rmem->dma_arr[i]);
2399 rmem->pg_arr[i] = NULL;
2402 size_t pg_tbl_size = rmem->nr_pages * 8;
2404 if (rmem->flags & BNXT_RMEM_USE_FULL_PAGE_FLAG)
2405 pg_tbl_size = rmem->page_size;
2406 dma_free_coherent(&pdev->dev, pg_tbl_size,
2407 rmem->pg_tbl, rmem->pg_tbl_map);
2408 rmem->pg_tbl = NULL;
2410 if (rmem->vmem_size && *rmem->vmem) {
2416 static int bnxt_alloc_ring(struct bnxt *bp, struct bnxt_ring_mem_info *rmem)
2418 struct pci_dev *pdev = bp->pdev;
2422 if (rmem->flags & (BNXT_RMEM_VALID_PTE_FLAG | BNXT_RMEM_RING_PTE_FLAG))
2423 valid_bit = PTU_PTE_VALID;
2424 if ((rmem->nr_pages > 1 || rmem->depth > 0) && !rmem->pg_tbl) {
2425 size_t pg_tbl_size = rmem->nr_pages * 8;
2427 if (rmem->flags & BNXT_RMEM_USE_FULL_PAGE_FLAG)
2428 pg_tbl_size = rmem->page_size;
2429 rmem->pg_tbl = dma_alloc_coherent(&pdev->dev, pg_tbl_size,
2436 for (i = 0; i < rmem->nr_pages; i++) {
2437 u64 extra_bits = valid_bit;
2439 rmem->pg_arr[i] = dma_alloc_coherent(&pdev->dev,
2443 if (!rmem->pg_arr[i])
2446 if (rmem->nr_pages > 1 || rmem->depth > 0) {
2447 if (i == rmem->nr_pages - 2 &&
2448 (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
2449 extra_bits |= PTU_PTE_NEXT_TO_LAST;
2450 else if (i == rmem->nr_pages - 1 &&
2451 (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
2452 extra_bits |= PTU_PTE_LAST;
2454 cpu_to_le64(rmem->dma_arr[i] | extra_bits);
2458 if (rmem->vmem_size) {
2459 *rmem->vmem = vzalloc(rmem->vmem_size);
2466 static void bnxt_free_rx_rings(struct bnxt *bp)
2473 for (i = 0; i < bp->rx_nr_rings; i++) {
2474 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
2475 struct bnxt_ring_struct *ring;
2478 bpf_prog_put(rxr->xdp_prog);
2480 if (xdp_rxq_info_is_reg(&rxr->xdp_rxq))
2481 xdp_rxq_info_unreg(&rxr->xdp_rxq);
2486 kfree(rxr->rx_agg_bmap);
2487 rxr->rx_agg_bmap = NULL;
2489 ring = &rxr->rx_ring_struct;
2490 bnxt_free_ring(bp, &ring->ring_mem);
2492 ring = &rxr->rx_agg_ring_struct;
2493 bnxt_free_ring(bp, &ring->ring_mem);
2497 static int bnxt_alloc_rx_rings(struct bnxt *bp)
2499 int i, rc, agg_rings = 0, tpa_rings = 0;
2504 if (bp->flags & BNXT_FLAG_AGG_RINGS)
2507 if (bp->flags & BNXT_FLAG_TPA)
2510 for (i = 0; i < bp->rx_nr_rings; i++) {
2511 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
2512 struct bnxt_ring_struct *ring;
2514 ring = &rxr->rx_ring_struct;
2516 rc = xdp_rxq_info_reg(&rxr->xdp_rxq, bp->dev, i);
2520 rc = bnxt_alloc_ring(bp, &ring->ring_mem);
2528 ring = &rxr->rx_agg_ring_struct;
2529 rc = bnxt_alloc_ring(bp, &ring->ring_mem);
2534 rxr->rx_agg_bmap_size = bp->rx_agg_ring_mask + 1;
2535 mem_size = rxr->rx_agg_bmap_size / 8;
2536 rxr->rx_agg_bmap = kzalloc(mem_size, GFP_KERNEL);
2537 if (!rxr->rx_agg_bmap)
2541 rxr->rx_tpa = kcalloc(MAX_TPA,
2542 sizeof(struct bnxt_tpa_info),
2552 static void bnxt_free_tx_rings(struct bnxt *bp)
2555 struct pci_dev *pdev = bp->pdev;
2560 for (i = 0; i < bp->tx_nr_rings; i++) {
2561 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
2562 struct bnxt_ring_struct *ring;
2565 dma_free_coherent(&pdev->dev, bp->tx_push_size,
2566 txr->tx_push, txr->tx_push_mapping);
2567 txr->tx_push = NULL;
2570 ring = &txr->tx_ring_struct;
2572 bnxt_free_ring(bp, &ring->ring_mem);
2576 static int bnxt_alloc_tx_rings(struct bnxt *bp)
2579 struct pci_dev *pdev = bp->pdev;
2581 bp->tx_push_size = 0;
2582 if (bp->tx_push_thresh) {
2585 push_size = L1_CACHE_ALIGN(sizeof(struct tx_push_bd) +
2586 bp->tx_push_thresh);
2588 if (push_size > 256) {
2590 bp->tx_push_thresh = 0;
2593 bp->tx_push_size = push_size;
2596 for (i = 0, j = 0; i < bp->tx_nr_rings; i++) {
2597 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
2598 struct bnxt_ring_struct *ring;
2601 ring = &txr->tx_ring_struct;
2603 rc = bnxt_alloc_ring(bp, &ring->ring_mem);
2607 ring->grp_idx = txr->bnapi->index;
2608 if (bp->tx_push_size) {
2611 /* One pre-allocated DMA buffer to backup
2614 txr->tx_push = dma_alloc_coherent(&pdev->dev,
2616 &txr->tx_push_mapping,
2622 mapping = txr->tx_push_mapping +
2623 sizeof(struct tx_push_bd);
2624 txr->data_mapping = cpu_to_le64(mapping);
2626 memset(txr->tx_push, 0, sizeof(struct tx_push_bd));
2628 qidx = bp->tc_to_qidx[j];
2629 ring->queue_id = bp->q_info[qidx].queue_id;
2630 if (i < bp->tx_nr_rings_xdp)
2632 if (i % bp->tx_nr_rings_per_tc == (bp->tx_nr_rings_per_tc - 1))
2638 static void bnxt_free_cp_rings(struct bnxt *bp)
2645 for (i = 0; i < bp->cp_nr_rings; i++) {
2646 struct bnxt_napi *bnapi = bp->bnapi[i];
2647 struct bnxt_cp_ring_info *cpr;
2648 struct bnxt_ring_struct *ring;
2654 cpr = &bnapi->cp_ring;
2655 ring = &cpr->cp_ring_struct;
2657 bnxt_free_ring(bp, &ring->ring_mem);
2659 for (j = 0; j < 2; j++) {
2660 struct bnxt_cp_ring_info *cpr2 = cpr->cp_ring_arr[j];
2663 ring = &cpr2->cp_ring_struct;
2664 bnxt_free_ring(bp, &ring->ring_mem);
2666 cpr->cp_ring_arr[j] = NULL;
2672 static struct bnxt_cp_ring_info *bnxt_alloc_cp_sub_ring(struct bnxt *bp)
2674 struct bnxt_ring_mem_info *rmem;
2675 struct bnxt_ring_struct *ring;
2676 struct bnxt_cp_ring_info *cpr;
2679 cpr = kzalloc(sizeof(*cpr), GFP_KERNEL);
2683 ring = &cpr->cp_ring_struct;
2684 rmem = &ring->ring_mem;
2685 rmem->nr_pages = bp->cp_nr_pages;
2686 rmem->page_size = HW_CMPD_RING_SIZE;
2687 rmem->pg_arr = (void **)cpr->cp_desc_ring;
2688 rmem->dma_arr = cpr->cp_desc_mapping;
2689 rmem->flags = BNXT_RMEM_RING_PTE_FLAG;
2690 rc = bnxt_alloc_ring(bp, rmem);
2692 bnxt_free_ring(bp, rmem);
2699 static int bnxt_alloc_cp_rings(struct bnxt *bp)
2701 bool sh = !!(bp->flags & BNXT_FLAG_SHARED_RINGS);
2702 int i, rc, ulp_base_vec, ulp_msix;
2704 ulp_msix = bnxt_get_ulp_msix_num(bp);
2705 ulp_base_vec = bnxt_get_ulp_msix_base(bp);
2706 for (i = 0; i < bp->cp_nr_rings; i++) {
2707 struct bnxt_napi *bnapi = bp->bnapi[i];
2708 struct bnxt_cp_ring_info *cpr;
2709 struct bnxt_ring_struct *ring;
2714 cpr = &bnapi->cp_ring;
2716 ring = &cpr->cp_ring_struct;
2718 rc = bnxt_alloc_ring(bp, &ring->ring_mem);
2722 if (ulp_msix && i >= ulp_base_vec)
2723 ring->map_idx = i + ulp_msix;
2727 if (!(bp->flags & BNXT_FLAG_CHIP_P5))
2730 if (i < bp->rx_nr_rings) {
2731 struct bnxt_cp_ring_info *cpr2 =
2732 bnxt_alloc_cp_sub_ring(bp);
2734 cpr->cp_ring_arr[BNXT_RX_HDL] = cpr2;
2737 cpr2->bnapi = bnapi;
2739 if ((sh && i < bp->tx_nr_rings) ||
2740 (!sh && i >= bp->rx_nr_rings)) {
2741 struct bnxt_cp_ring_info *cpr2 =
2742 bnxt_alloc_cp_sub_ring(bp);
2744 cpr->cp_ring_arr[BNXT_TX_HDL] = cpr2;
2747 cpr2->bnapi = bnapi;
2753 static void bnxt_init_ring_struct(struct bnxt *bp)
2757 for (i = 0; i < bp->cp_nr_rings; i++) {
2758 struct bnxt_napi *bnapi = bp->bnapi[i];
2759 struct bnxt_ring_mem_info *rmem;
2760 struct bnxt_cp_ring_info *cpr;
2761 struct bnxt_rx_ring_info *rxr;
2762 struct bnxt_tx_ring_info *txr;
2763 struct bnxt_ring_struct *ring;
2768 cpr = &bnapi->cp_ring;
2769 ring = &cpr->cp_ring_struct;
2770 rmem = &ring->ring_mem;
2771 rmem->nr_pages = bp->cp_nr_pages;
2772 rmem->page_size = HW_CMPD_RING_SIZE;
2773 rmem->pg_arr = (void **)cpr->cp_desc_ring;
2774 rmem->dma_arr = cpr->cp_desc_mapping;
2775 rmem->vmem_size = 0;
2777 rxr = bnapi->rx_ring;
2781 ring = &rxr->rx_ring_struct;
2782 rmem = &ring->ring_mem;
2783 rmem->nr_pages = bp->rx_nr_pages;
2784 rmem->page_size = HW_RXBD_RING_SIZE;
2785 rmem->pg_arr = (void **)rxr->rx_desc_ring;
2786 rmem->dma_arr = rxr->rx_desc_mapping;
2787 rmem->vmem_size = SW_RXBD_RING_SIZE * bp->rx_nr_pages;
2788 rmem->vmem = (void **)&rxr->rx_buf_ring;
2790 ring = &rxr->rx_agg_ring_struct;
2791 rmem = &ring->ring_mem;
2792 rmem->nr_pages = bp->rx_agg_nr_pages;
2793 rmem->page_size = HW_RXBD_RING_SIZE;
2794 rmem->pg_arr = (void **)rxr->rx_agg_desc_ring;
2795 rmem->dma_arr = rxr->rx_agg_desc_mapping;
2796 rmem->vmem_size = SW_RXBD_AGG_RING_SIZE * bp->rx_agg_nr_pages;
2797 rmem->vmem = (void **)&rxr->rx_agg_ring;
2800 txr = bnapi->tx_ring;
2804 ring = &txr->tx_ring_struct;
2805 rmem = &ring->ring_mem;
2806 rmem->nr_pages = bp->tx_nr_pages;
2807 rmem->page_size = HW_RXBD_RING_SIZE;
2808 rmem->pg_arr = (void **)txr->tx_desc_ring;
2809 rmem->dma_arr = txr->tx_desc_mapping;
2810 rmem->vmem_size = SW_TXBD_RING_SIZE * bp->tx_nr_pages;
2811 rmem->vmem = (void **)&txr->tx_buf_ring;
2815 static void bnxt_init_rxbd_pages(struct bnxt_ring_struct *ring, u32 type)
2819 struct rx_bd **rx_buf_ring;
2821 rx_buf_ring = (struct rx_bd **)ring->ring_mem.pg_arr;
2822 for (i = 0, prod = 0; i < ring->ring_mem.nr_pages; i++) {
2826 rxbd = rx_buf_ring[i];
2830 for (j = 0; j < RX_DESC_CNT; j++, rxbd++, prod++) {
2831 rxbd->rx_bd_len_flags_type = cpu_to_le32(type);
2832 rxbd->rx_bd_opaque = prod;
2837 static int bnxt_init_one_rx_ring(struct bnxt *bp, int ring_nr)
2839 struct net_device *dev = bp->dev;
2840 struct bnxt_rx_ring_info *rxr;
2841 struct bnxt_ring_struct *ring;
2845 type = (bp->rx_buf_use_size << RX_BD_LEN_SHIFT) |
2846 RX_BD_TYPE_RX_PACKET_BD | RX_BD_FLAGS_EOP;
2848 if (NET_IP_ALIGN == 2)
2849 type |= RX_BD_FLAGS_SOP;
2851 rxr = &bp->rx_ring[ring_nr];
2852 ring = &rxr->rx_ring_struct;
2853 bnxt_init_rxbd_pages(ring, type);
2855 if (BNXT_RX_PAGE_MODE(bp) && bp->xdp_prog) {
2856 rxr->xdp_prog = bpf_prog_add(bp->xdp_prog, 1);
2857 if (IS_ERR(rxr->xdp_prog)) {
2858 int rc = PTR_ERR(rxr->xdp_prog);
2860 rxr->xdp_prog = NULL;
2864 prod = rxr->rx_prod;
2865 for (i = 0; i < bp->rx_ring_size; i++) {
2866 if (bnxt_alloc_rx_data(bp, rxr, prod, GFP_KERNEL) != 0) {
2867 netdev_warn(dev, "init'ed rx ring %d with %d/%d skbs only\n",
2868 ring_nr, i, bp->rx_ring_size);
2871 prod = NEXT_RX(prod);
2873 rxr->rx_prod = prod;
2874 ring->fw_ring_id = INVALID_HW_RING_ID;
2876 ring = &rxr->rx_agg_ring_struct;
2877 ring->fw_ring_id = INVALID_HW_RING_ID;
2879 if (!(bp->flags & BNXT_FLAG_AGG_RINGS))
2882 type = ((u32)BNXT_RX_PAGE_SIZE << RX_BD_LEN_SHIFT) |
2883 RX_BD_TYPE_RX_AGG_BD | RX_BD_FLAGS_SOP;
2885 bnxt_init_rxbd_pages(ring, type);
2887 prod = rxr->rx_agg_prod;
2888 for (i = 0; i < bp->rx_agg_ring_size; i++) {
2889 if (bnxt_alloc_rx_page(bp, rxr, prod, GFP_KERNEL) != 0) {
2890 netdev_warn(dev, "init'ed rx ring %d with %d/%d pages only\n",
2891 ring_nr, i, bp->rx_ring_size);
2894 prod = NEXT_RX_AGG(prod);
2896 rxr->rx_agg_prod = prod;
2898 if (bp->flags & BNXT_FLAG_TPA) {
2903 for (i = 0; i < MAX_TPA; i++) {
2904 data = __bnxt_alloc_rx_data(bp, &mapping,
2909 rxr->rx_tpa[i].data = data;
2910 rxr->rx_tpa[i].data_ptr = data + bp->rx_offset;
2911 rxr->rx_tpa[i].mapping = mapping;
2914 netdev_err(bp->dev, "No resource allocated for LRO/GRO\n");
2922 static void bnxt_init_cp_rings(struct bnxt *bp)
2926 for (i = 0; i < bp->cp_nr_rings; i++) {
2927 struct bnxt_cp_ring_info *cpr = &bp->bnapi[i]->cp_ring;
2928 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct;
2930 ring->fw_ring_id = INVALID_HW_RING_ID;
2931 cpr->rx_ring_coal.coal_ticks = bp->rx_coal.coal_ticks;
2932 cpr->rx_ring_coal.coal_bufs = bp->rx_coal.coal_bufs;
2933 for (j = 0; j < 2; j++) {
2934 struct bnxt_cp_ring_info *cpr2 = cpr->cp_ring_arr[j];
2939 ring = &cpr2->cp_ring_struct;
2940 ring->fw_ring_id = INVALID_HW_RING_ID;
2941 cpr2->rx_ring_coal.coal_ticks = bp->rx_coal.coal_ticks;
2942 cpr2->rx_ring_coal.coal_bufs = bp->rx_coal.coal_bufs;
2947 static int bnxt_init_rx_rings(struct bnxt *bp)
2951 if (BNXT_RX_PAGE_MODE(bp)) {
2952 bp->rx_offset = NET_IP_ALIGN + XDP_PACKET_HEADROOM;
2953 bp->rx_dma_offset = XDP_PACKET_HEADROOM;
2955 bp->rx_offset = BNXT_RX_OFFSET;
2956 bp->rx_dma_offset = BNXT_RX_DMA_OFFSET;
2959 for (i = 0; i < bp->rx_nr_rings; i++) {
2960 rc = bnxt_init_one_rx_ring(bp, i);
2968 static int bnxt_init_tx_rings(struct bnxt *bp)
2972 bp->tx_wake_thresh = max_t(int, bp->tx_ring_size / 2,
2975 for (i = 0; i < bp->tx_nr_rings; i++) {
2976 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
2977 struct bnxt_ring_struct *ring = &txr->tx_ring_struct;
2979 ring->fw_ring_id = INVALID_HW_RING_ID;
2985 static void bnxt_free_ring_grps(struct bnxt *bp)
2987 kfree(bp->grp_info);
2988 bp->grp_info = NULL;
2991 static int bnxt_init_ring_grps(struct bnxt *bp, bool irq_re_init)
2996 bp->grp_info = kcalloc(bp->cp_nr_rings,
2997 sizeof(struct bnxt_ring_grp_info),
3002 for (i = 0; i < bp->cp_nr_rings; i++) {
3004 bp->grp_info[i].fw_stats_ctx = INVALID_HW_RING_ID;
3005 bp->grp_info[i].fw_grp_id = INVALID_HW_RING_ID;
3006 bp->grp_info[i].rx_fw_ring_id = INVALID_HW_RING_ID;
3007 bp->grp_info[i].agg_fw_ring_id = INVALID_HW_RING_ID;
3008 bp->grp_info[i].cp_fw_ring_id = INVALID_HW_RING_ID;
3013 static void bnxt_free_vnics(struct bnxt *bp)
3015 kfree(bp->vnic_info);
3016 bp->vnic_info = NULL;
3020 static int bnxt_alloc_vnics(struct bnxt *bp)
3024 #ifdef CONFIG_RFS_ACCEL
3025 if (bp->flags & BNXT_FLAG_RFS)
3026 num_vnics += bp->rx_nr_rings;
3029 if (BNXT_CHIP_TYPE_NITRO_A0(bp))
3032 bp->vnic_info = kcalloc(num_vnics, sizeof(struct bnxt_vnic_info),
3037 bp->nr_vnics = num_vnics;
3041 static void bnxt_init_vnics(struct bnxt *bp)
3045 for (i = 0; i < bp->nr_vnics; i++) {
3046 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3049 vnic->fw_vnic_id = INVALID_HW_RING_ID;
3050 for (j = 0; j < BNXT_MAX_CTX_PER_VNIC; j++)
3051 vnic->fw_rss_cos_lb_ctx[j] = INVALID_HW_RING_ID;
3053 vnic->fw_l2_ctx_id = INVALID_HW_RING_ID;
3055 if (bp->vnic_info[i].rss_hash_key) {
3057 prandom_bytes(vnic->rss_hash_key,
3060 memcpy(vnic->rss_hash_key,
3061 bp->vnic_info[0].rss_hash_key,
3067 static int bnxt_calc_nr_ring_pages(u32 ring_size, int desc_per_pg)
3071 pages = ring_size / desc_per_pg;
3078 while (pages & (pages - 1))
3084 void bnxt_set_tpa_flags(struct bnxt *bp)
3086 bp->flags &= ~BNXT_FLAG_TPA;
3087 if (bp->flags & BNXT_FLAG_NO_AGG_RINGS)
3089 if (bp->dev->features & NETIF_F_LRO)
3090 bp->flags |= BNXT_FLAG_LRO;
3091 else if (bp->dev->features & NETIF_F_GRO_HW)
3092 bp->flags |= BNXT_FLAG_GRO;
3095 /* bp->rx_ring_size, bp->tx_ring_size, dev->mtu, BNXT_FLAG_{G|L}RO flags must
3098 void bnxt_set_ring_params(struct bnxt *bp)
3100 u32 ring_size, rx_size, rx_space;
3101 u32 agg_factor = 0, agg_ring_size = 0;
3103 /* 8 for CRC and VLAN */
3104 rx_size = SKB_DATA_ALIGN(bp->dev->mtu + ETH_HLEN + NET_IP_ALIGN + 8);
3106 rx_space = rx_size + NET_SKB_PAD +
3107 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
3109 bp->rx_copy_thresh = BNXT_RX_COPY_THRESH;
3110 ring_size = bp->rx_ring_size;
3111 bp->rx_agg_ring_size = 0;
3112 bp->rx_agg_nr_pages = 0;
3114 if (bp->flags & BNXT_FLAG_TPA)
3115 agg_factor = min_t(u32, 4, 65536 / BNXT_RX_PAGE_SIZE);
3117 bp->flags &= ~BNXT_FLAG_JUMBO;
3118 if (rx_space > PAGE_SIZE && !(bp->flags & BNXT_FLAG_NO_AGG_RINGS)) {
3121 bp->flags |= BNXT_FLAG_JUMBO;
3122 jumbo_factor = PAGE_ALIGN(bp->dev->mtu - 40) >> PAGE_SHIFT;
3123 if (jumbo_factor > agg_factor)
3124 agg_factor = jumbo_factor;
3126 agg_ring_size = ring_size * agg_factor;
3128 if (agg_ring_size) {
3129 bp->rx_agg_nr_pages = bnxt_calc_nr_ring_pages(agg_ring_size,
3131 if (bp->rx_agg_nr_pages > MAX_RX_AGG_PAGES) {
3132 u32 tmp = agg_ring_size;
3134 bp->rx_agg_nr_pages = MAX_RX_AGG_PAGES;
3135 agg_ring_size = MAX_RX_AGG_PAGES * RX_DESC_CNT - 1;
3136 netdev_warn(bp->dev, "rx agg ring size %d reduced to %d.\n",
3137 tmp, agg_ring_size);
3139 bp->rx_agg_ring_size = agg_ring_size;
3140 bp->rx_agg_ring_mask = (bp->rx_agg_nr_pages * RX_DESC_CNT) - 1;
3141 rx_size = SKB_DATA_ALIGN(BNXT_RX_COPY_THRESH + NET_IP_ALIGN);
3142 rx_space = rx_size + NET_SKB_PAD +
3143 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
3146 bp->rx_buf_use_size = rx_size;
3147 bp->rx_buf_size = rx_space;
3149 bp->rx_nr_pages = bnxt_calc_nr_ring_pages(ring_size, RX_DESC_CNT);
3150 bp->rx_ring_mask = (bp->rx_nr_pages * RX_DESC_CNT) - 1;
3152 ring_size = bp->tx_ring_size;
3153 bp->tx_nr_pages = bnxt_calc_nr_ring_pages(ring_size, TX_DESC_CNT);
3154 bp->tx_ring_mask = (bp->tx_nr_pages * TX_DESC_CNT) - 1;
3156 ring_size = bp->rx_ring_size * (2 + agg_factor) + bp->tx_ring_size;
3157 bp->cp_ring_size = ring_size;
3159 bp->cp_nr_pages = bnxt_calc_nr_ring_pages(ring_size, CP_DESC_CNT);
3160 if (bp->cp_nr_pages > MAX_CP_PAGES) {
3161 bp->cp_nr_pages = MAX_CP_PAGES;
3162 bp->cp_ring_size = MAX_CP_PAGES * CP_DESC_CNT - 1;
3163 netdev_warn(bp->dev, "completion ring size %d reduced to %d.\n",
3164 ring_size, bp->cp_ring_size);
3166 bp->cp_bit = bp->cp_nr_pages * CP_DESC_CNT;
3167 bp->cp_ring_mask = bp->cp_bit - 1;
3170 /* Changing allocation mode of RX rings.
3171 * TODO: Update when extending xdp_rxq_info to support allocation modes.
3173 int bnxt_set_rx_skb_mode(struct bnxt *bp, bool page_mode)
3176 if (bp->dev->mtu > BNXT_MAX_PAGE_MODE_MTU)
3179 min_t(u16, bp->max_mtu, BNXT_MAX_PAGE_MODE_MTU);
3180 bp->flags &= ~BNXT_FLAG_AGG_RINGS;
3181 bp->flags |= BNXT_FLAG_NO_AGG_RINGS | BNXT_FLAG_RX_PAGE_MODE;
3182 bp->rx_dir = DMA_BIDIRECTIONAL;
3183 bp->rx_skb_func = bnxt_rx_page_skb;
3184 /* Disable LRO or GRO_HW */
3185 netdev_update_features(bp->dev);
3187 bp->dev->max_mtu = bp->max_mtu;
3188 bp->flags &= ~BNXT_FLAG_RX_PAGE_MODE;
3189 bp->rx_dir = DMA_FROM_DEVICE;
3190 bp->rx_skb_func = bnxt_rx_skb;
3195 static void bnxt_free_vnic_attributes(struct bnxt *bp)
3198 struct bnxt_vnic_info *vnic;
3199 struct pci_dev *pdev = bp->pdev;
3204 for (i = 0; i < bp->nr_vnics; i++) {
3205 vnic = &bp->vnic_info[i];
3207 kfree(vnic->fw_grp_ids);
3208 vnic->fw_grp_ids = NULL;
3210 kfree(vnic->uc_list);
3211 vnic->uc_list = NULL;
3213 if (vnic->mc_list) {
3214 dma_free_coherent(&pdev->dev, vnic->mc_list_size,
3215 vnic->mc_list, vnic->mc_list_mapping);
3216 vnic->mc_list = NULL;
3219 if (vnic->rss_table) {
3220 dma_free_coherent(&pdev->dev, PAGE_SIZE,
3222 vnic->rss_table_dma_addr);
3223 vnic->rss_table = NULL;
3226 vnic->rss_hash_key = NULL;
3231 static int bnxt_alloc_vnic_attributes(struct bnxt *bp)
3233 int i, rc = 0, size;
3234 struct bnxt_vnic_info *vnic;
3235 struct pci_dev *pdev = bp->pdev;
3238 for (i = 0; i < bp->nr_vnics; i++) {
3239 vnic = &bp->vnic_info[i];
3241 if (vnic->flags & BNXT_VNIC_UCAST_FLAG) {
3242 int mem_size = (BNXT_MAX_UC_ADDRS - 1) * ETH_ALEN;
3245 vnic->uc_list = kmalloc(mem_size, GFP_KERNEL);
3246 if (!vnic->uc_list) {
3253 if (vnic->flags & BNXT_VNIC_MCAST_FLAG) {
3254 vnic->mc_list_size = BNXT_MAX_MC_ADDRS * ETH_ALEN;
3256 dma_alloc_coherent(&pdev->dev,
3258 &vnic->mc_list_mapping,
3260 if (!vnic->mc_list) {
3266 if (bp->flags & BNXT_FLAG_CHIP_P5)
3267 goto vnic_skip_grps;
3269 if (vnic->flags & BNXT_VNIC_RSS_FLAG)
3270 max_rings = bp->rx_nr_rings;
3274 vnic->fw_grp_ids = kcalloc(max_rings, sizeof(u16), GFP_KERNEL);
3275 if (!vnic->fw_grp_ids) {
3280 if ((bp->flags & BNXT_FLAG_NEW_RSS_CAP) &&
3281 !(vnic->flags & BNXT_VNIC_RSS_FLAG))
3284 /* Allocate rss table and hash key */
3285 vnic->rss_table = dma_alloc_coherent(&pdev->dev, PAGE_SIZE,
3286 &vnic->rss_table_dma_addr,
3288 if (!vnic->rss_table) {
3293 size = L1_CACHE_ALIGN(HW_HASH_INDEX_SIZE * sizeof(u16));
3295 vnic->rss_hash_key = ((void *)vnic->rss_table) + size;
3296 vnic->rss_hash_key_dma_addr = vnic->rss_table_dma_addr + size;
3304 static void bnxt_free_hwrm_resources(struct bnxt *bp)
3306 struct pci_dev *pdev = bp->pdev;
3308 if (bp->hwrm_cmd_resp_addr) {
3309 dma_free_coherent(&pdev->dev, PAGE_SIZE, bp->hwrm_cmd_resp_addr,
3310 bp->hwrm_cmd_resp_dma_addr);
3311 bp->hwrm_cmd_resp_addr = NULL;
3314 if (bp->hwrm_cmd_kong_resp_addr) {
3315 dma_free_coherent(&pdev->dev, PAGE_SIZE,
3316 bp->hwrm_cmd_kong_resp_addr,
3317 bp->hwrm_cmd_kong_resp_dma_addr);
3318 bp->hwrm_cmd_kong_resp_addr = NULL;
3322 static int bnxt_alloc_kong_hwrm_resources(struct bnxt *bp)
3324 struct pci_dev *pdev = bp->pdev;
3326 bp->hwrm_cmd_kong_resp_addr =
3327 dma_alloc_coherent(&pdev->dev, PAGE_SIZE,
3328 &bp->hwrm_cmd_kong_resp_dma_addr,
3330 if (!bp->hwrm_cmd_kong_resp_addr)
3336 static int bnxt_alloc_hwrm_resources(struct bnxt *bp)
3338 struct pci_dev *pdev = bp->pdev;
3340 bp->hwrm_cmd_resp_addr = dma_alloc_coherent(&pdev->dev, PAGE_SIZE,
3341 &bp->hwrm_cmd_resp_dma_addr,
3343 if (!bp->hwrm_cmd_resp_addr)
3349 static void bnxt_free_hwrm_short_cmd_req(struct bnxt *bp)
3351 if (bp->hwrm_short_cmd_req_addr) {
3352 struct pci_dev *pdev = bp->pdev;
3354 dma_free_coherent(&pdev->dev, bp->hwrm_max_ext_req_len,
3355 bp->hwrm_short_cmd_req_addr,
3356 bp->hwrm_short_cmd_req_dma_addr);
3357 bp->hwrm_short_cmd_req_addr = NULL;
3361 static int bnxt_alloc_hwrm_short_cmd_req(struct bnxt *bp)
3363 struct pci_dev *pdev = bp->pdev;
3365 bp->hwrm_short_cmd_req_addr =
3366 dma_alloc_coherent(&pdev->dev, bp->hwrm_max_ext_req_len,
3367 &bp->hwrm_short_cmd_req_dma_addr,
3369 if (!bp->hwrm_short_cmd_req_addr)
3375 static void bnxt_free_port_stats(struct bnxt *bp)
3377 struct pci_dev *pdev = bp->pdev;
3379 bp->flags &= ~BNXT_FLAG_PORT_STATS;
3380 bp->flags &= ~BNXT_FLAG_PORT_STATS_EXT;
3382 if (bp->hw_rx_port_stats) {
3383 dma_free_coherent(&pdev->dev, bp->hw_port_stats_size,
3384 bp->hw_rx_port_stats,
3385 bp->hw_rx_port_stats_map);
3386 bp->hw_rx_port_stats = NULL;
3389 if (bp->hw_tx_port_stats_ext) {
3390 dma_free_coherent(&pdev->dev, sizeof(struct tx_port_stats_ext),
3391 bp->hw_tx_port_stats_ext,
3392 bp->hw_tx_port_stats_ext_map);
3393 bp->hw_tx_port_stats_ext = NULL;
3396 if (bp->hw_rx_port_stats_ext) {
3397 dma_free_coherent(&pdev->dev, sizeof(struct rx_port_stats_ext),
3398 bp->hw_rx_port_stats_ext,
3399 bp->hw_rx_port_stats_ext_map);
3400 bp->hw_rx_port_stats_ext = NULL;
3403 if (bp->hw_pcie_stats) {
3404 dma_free_coherent(&pdev->dev, sizeof(struct pcie_ctx_hw_stats),
3405 bp->hw_pcie_stats, bp->hw_pcie_stats_map);
3406 bp->hw_pcie_stats = NULL;
3410 static void bnxt_free_ring_stats(struct bnxt *bp)
3412 struct pci_dev *pdev = bp->pdev;
3418 size = sizeof(struct ctx_hw_stats);
3420 for (i = 0; i < bp->cp_nr_rings; i++) {
3421 struct bnxt_napi *bnapi = bp->bnapi[i];
3422 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
3424 if (cpr->hw_stats) {
3425 dma_free_coherent(&pdev->dev, size, cpr->hw_stats,
3427 cpr->hw_stats = NULL;
3432 static int bnxt_alloc_stats(struct bnxt *bp)
3435 struct pci_dev *pdev = bp->pdev;
3437 size = sizeof(struct ctx_hw_stats);
3439 for (i = 0; i < bp->cp_nr_rings; i++) {
3440 struct bnxt_napi *bnapi = bp->bnapi[i];
3441 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
3443 cpr->hw_stats = dma_alloc_coherent(&pdev->dev, size,
3449 cpr->hw_stats_ctx_id = INVALID_STATS_CTX_ID;
3452 if (BNXT_VF(bp) || bp->chip_num == CHIP_NUM_58700)
3455 if (bp->hw_rx_port_stats)
3456 goto alloc_ext_stats;
3458 bp->hw_port_stats_size = sizeof(struct rx_port_stats) +
3459 sizeof(struct tx_port_stats) + 1024;
3461 bp->hw_rx_port_stats =
3462 dma_alloc_coherent(&pdev->dev, bp->hw_port_stats_size,
3463 &bp->hw_rx_port_stats_map,
3465 if (!bp->hw_rx_port_stats)
3468 bp->hw_tx_port_stats = (void *)(bp->hw_rx_port_stats + 1) + 512;
3469 bp->hw_tx_port_stats_map = bp->hw_rx_port_stats_map +
3470 sizeof(struct rx_port_stats) + 512;
3471 bp->flags |= BNXT_FLAG_PORT_STATS;
3474 /* Display extended statistics only if FW supports it */
3475 if (bp->hwrm_spec_code < 0x10804 || bp->hwrm_spec_code == 0x10900)
3476 if (!(bp->fw_cap & BNXT_FW_CAP_EXT_STATS_SUPPORTED))
3479 if (bp->hw_rx_port_stats_ext)
3480 goto alloc_tx_ext_stats;
3482 bp->hw_rx_port_stats_ext =
3483 dma_alloc_coherent(&pdev->dev, sizeof(struct rx_port_stats_ext),
3484 &bp->hw_rx_port_stats_ext_map, GFP_KERNEL);
3485 if (!bp->hw_rx_port_stats_ext)
3489 if (bp->hw_tx_port_stats_ext)
3490 goto alloc_pcie_stats;
3492 if (bp->hwrm_spec_code >= 0x10902 ||
3493 (bp->fw_cap & BNXT_FW_CAP_EXT_STATS_SUPPORTED)) {
3494 bp->hw_tx_port_stats_ext =
3495 dma_alloc_coherent(&pdev->dev,
3496 sizeof(struct tx_port_stats_ext),
3497 &bp->hw_tx_port_stats_ext_map,
3500 bp->flags |= BNXT_FLAG_PORT_STATS_EXT;
3503 if (bp->hw_pcie_stats ||
3504 !(bp->fw_cap & BNXT_FW_CAP_PCIE_STATS_SUPPORTED))
3508 dma_alloc_coherent(&pdev->dev, sizeof(struct pcie_ctx_hw_stats),
3509 &bp->hw_pcie_stats_map, GFP_KERNEL);
3510 if (!bp->hw_pcie_stats)
3513 bp->flags |= BNXT_FLAG_PCIE_STATS;
3517 static void bnxt_clear_ring_indices(struct bnxt *bp)
3524 for (i = 0; i < bp->cp_nr_rings; i++) {
3525 struct bnxt_napi *bnapi = bp->bnapi[i];
3526 struct bnxt_cp_ring_info *cpr;
3527 struct bnxt_rx_ring_info *rxr;
3528 struct bnxt_tx_ring_info *txr;
3533 cpr = &bnapi->cp_ring;
3534 cpr->cp_raw_cons = 0;
3536 txr = bnapi->tx_ring;
3542 rxr = bnapi->rx_ring;
3545 rxr->rx_agg_prod = 0;
3546 rxr->rx_sw_agg_prod = 0;
3547 rxr->rx_next_cons = 0;
3552 static void bnxt_free_ntp_fltrs(struct bnxt *bp, bool irq_reinit)
3554 #ifdef CONFIG_RFS_ACCEL
3557 /* Under rtnl_lock and all our NAPIs have been disabled. It's
3558 * safe to delete the hash table.
3560 for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) {
3561 struct hlist_head *head;
3562 struct hlist_node *tmp;
3563 struct bnxt_ntuple_filter *fltr;
3565 head = &bp->ntp_fltr_hash_tbl[i];
3566 hlist_for_each_entry_safe(fltr, tmp, head, hash) {
3567 hlist_del(&fltr->hash);
3572 kfree(bp->ntp_fltr_bmap);
3573 bp->ntp_fltr_bmap = NULL;
3575 bp->ntp_fltr_count = 0;
3579 static int bnxt_alloc_ntp_fltrs(struct bnxt *bp)
3581 #ifdef CONFIG_RFS_ACCEL
3584 if (!(bp->flags & BNXT_FLAG_RFS))
3587 for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++)
3588 INIT_HLIST_HEAD(&bp->ntp_fltr_hash_tbl[i]);
3590 bp->ntp_fltr_count = 0;
3591 bp->ntp_fltr_bmap = kcalloc(BITS_TO_LONGS(BNXT_NTP_FLTR_MAX_FLTR),
3595 if (!bp->ntp_fltr_bmap)
3604 static void bnxt_free_mem(struct bnxt *bp, bool irq_re_init)
3606 bnxt_free_vnic_attributes(bp);
3607 bnxt_free_tx_rings(bp);
3608 bnxt_free_rx_rings(bp);
3609 bnxt_free_cp_rings(bp);
3610 bnxt_free_ntp_fltrs(bp, irq_re_init);
3612 bnxt_free_ring_stats(bp);
3613 bnxt_free_ring_grps(bp);
3614 bnxt_free_vnics(bp);
3615 kfree(bp->tx_ring_map);
3616 bp->tx_ring_map = NULL;
3624 bnxt_clear_ring_indices(bp);
3628 static int bnxt_alloc_mem(struct bnxt *bp, bool irq_re_init)
3630 int i, j, rc, size, arr_size;
3634 /* Allocate bnapi mem pointer array and mem block for
3637 arr_size = L1_CACHE_ALIGN(sizeof(struct bnxt_napi *) *
3639 size = L1_CACHE_ALIGN(sizeof(struct bnxt_napi));
3640 bnapi = kzalloc(arr_size + size * bp->cp_nr_rings, GFP_KERNEL);
3646 for (i = 0; i < bp->cp_nr_rings; i++, bnapi += size) {
3647 bp->bnapi[i] = bnapi;
3648 bp->bnapi[i]->index = i;
3649 bp->bnapi[i]->bp = bp;
3650 if (bp->flags & BNXT_FLAG_CHIP_P5) {
3651 struct bnxt_cp_ring_info *cpr =
3652 &bp->bnapi[i]->cp_ring;
3654 cpr->cp_ring_struct.ring_mem.flags =
3655 BNXT_RMEM_RING_PTE_FLAG;
3659 bp->rx_ring = kcalloc(bp->rx_nr_rings,
3660 sizeof(struct bnxt_rx_ring_info),
3665 for (i = 0; i < bp->rx_nr_rings; i++) {
3666 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
3668 if (bp->flags & BNXT_FLAG_CHIP_P5) {
3669 rxr->rx_ring_struct.ring_mem.flags =
3670 BNXT_RMEM_RING_PTE_FLAG;
3671 rxr->rx_agg_ring_struct.ring_mem.flags =
3672 BNXT_RMEM_RING_PTE_FLAG;
3674 rxr->bnapi = bp->bnapi[i];
3675 bp->bnapi[i]->rx_ring = &bp->rx_ring[i];
3678 bp->tx_ring = kcalloc(bp->tx_nr_rings,
3679 sizeof(struct bnxt_tx_ring_info),
3684 bp->tx_ring_map = kcalloc(bp->tx_nr_rings, sizeof(u16),
3687 if (!bp->tx_ring_map)
3690 if (bp->flags & BNXT_FLAG_SHARED_RINGS)
3693 j = bp->rx_nr_rings;
3695 for (i = 0; i < bp->tx_nr_rings; i++, j++) {
3696 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
3698 if (bp->flags & BNXT_FLAG_CHIP_P5)
3699 txr->tx_ring_struct.ring_mem.flags =
3700 BNXT_RMEM_RING_PTE_FLAG;
3701 txr->bnapi = bp->bnapi[j];
3702 bp->bnapi[j]->tx_ring = txr;
3703 bp->tx_ring_map[i] = bp->tx_nr_rings_xdp + i;
3704 if (i >= bp->tx_nr_rings_xdp) {
3705 txr->txq_index = i - bp->tx_nr_rings_xdp;
3706 bp->bnapi[j]->tx_int = bnxt_tx_int;
3708 bp->bnapi[j]->flags |= BNXT_NAPI_FLAG_XDP;
3709 bp->bnapi[j]->tx_int = bnxt_tx_int_xdp;
3713 rc = bnxt_alloc_stats(bp);
3717 rc = bnxt_alloc_ntp_fltrs(bp);
3721 rc = bnxt_alloc_vnics(bp);
3726 bnxt_init_ring_struct(bp);
3728 rc = bnxt_alloc_rx_rings(bp);
3732 rc = bnxt_alloc_tx_rings(bp);
3736 rc = bnxt_alloc_cp_rings(bp);
3740 bp->vnic_info[0].flags |= BNXT_VNIC_RSS_FLAG | BNXT_VNIC_MCAST_FLAG |
3741 BNXT_VNIC_UCAST_FLAG;
3742 rc = bnxt_alloc_vnic_attributes(bp);
3748 bnxt_free_mem(bp, true);
3752 static void bnxt_disable_int(struct bnxt *bp)
3759 for (i = 0; i < bp->cp_nr_rings; i++) {
3760 struct bnxt_napi *bnapi = bp->bnapi[i];
3761 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
3762 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct;
3764 if (ring->fw_ring_id != INVALID_HW_RING_ID)
3765 bnxt_db_nq(bp, &cpr->cp_db, cpr->cp_raw_cons);
3769 static int bnxt_cp_num_to_irq_num(struct bnxt *bp, int n)
3771 struct bnxt_napi *bnapi = bp->bnapi[n];
3772 struct bnxt_cp_ring_info *cpr;
3774 cpr = &bnapi->cp_ring;
3775 return cpr->cp_ring_struct.map_idx;
3778 static void bnxt_disable_int_sync(struct bnxt *bp)
3782 atomic_inc(&bp->intr_sem);
3784 bnxt_disable_int(bp);
3785 for (i = 0; i < bp->cp_nr_rings; i++) {
3786 int map_idx = bnxt_cp_num_to_irq_num(bp, i);
3788 synchronize_irq(bp->irq_tbl[map_idx].vector);
3792 static void bnxt_enable_int(struct bnxt *bp)
3796 atomic_set(&bp->intr_sem, 0);
3797 for (i = 0; i < bp->cp_nr_rings; i++) {
3798 struct bnxt_napi *bnapi = bp->bnapi[i];
3799 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
3801 bnxt_db_nq_arm(bp, &cpr->cp_db, cpr->cp_raw_cons);
3805 void bnxt_hwrm_cmd_hdr_init(struct bnxt *bp, void *request, u16 req_type,
3806 u16 cmpl_ring, u16 target_id)
3808 struct input *req = request;
3810 req->req_type = cpu_to_le16(req_type);
3811 req->cmpl_ring = cpu_to_le16(cmpl_ring);
3812 req->target_id = cpu_to_le16(target_id);
3813 if (bnxt_kong_hwrm_message(bp, req))
3814 req->resp_addr = cpu_to_le64(bp->hwrm_cmd_kong_resp_dma_addr);
3816 req->resp_addr = cpu_to_le64(bp->hwrm_cmd_resp_dma_addr);
3819 static int bnxt_hwrm_do_send_msg(struct bnxt *bp, void *msg, u32 msg_len,
3820 int timeout, bool silent)
3822 int i, intr_process, rc, tmo_count;
3823 struct input *req = msg;
3827 u16 cp_ring_id, len = 0;
3828 struct hwrm_err_output *resp = bp->hwrm_cmd_resp_addr;
3829 u16 max_req_len = BNXT_HWRM_MAX_REQ_LEN;
3830 struct hwrm_short_input short_input = {0};
3831 u32 doorbell_offset = BNXT_GRCPF_REG_CHIMP_COMM_TRIGGER;
3832 u8 *resp_addr = (u8 *)bp->hwrm_cmd_resp_addr;
3833 u32 bar_offset = BNXT_GRCPF_REG_CHIMP_COMM;
3834 u16 dst = BNXT_HWRM_CHNL_CHIMP;
3836 if (msg_len > BNXT_HWRM_MAX_REQ_LEN) {
3837 if (msg_len > bp->hwrm_max_ext_req_len ||
3838 !bp->hwrm_short_cmd_req_addr)
3842 if (bnxt_hwrm_kong_chnl(bp, req)) {
3843 dst = BNXT_HWRM_CHNL_KONG;
3844 bar_offset = BNXT_GRCPF_REG_KONG_COMM;
3845 doorbell_offset = BNXT_GRCPF_REG_KONG_COMM_TRIGGER;
3846 resp = bp->hwrm_cmd_kong_resp_addr;
3847 resp_addr = (u8 *)bp->hwrm_cmd_kong_resp_addr;
3850 memset(resp, 0, PAGE_SIZE);
3851 cp_ring_id = le16_to_cpu(req->cmpl_ring);
3852 intr_process = (cp_ring_id == INVALID_HW_RING_ID) ? 0 : 1;
3854 req->seq_id = cpu_to_le16(bnxt_get_hwrm_seq_id(bp, dst));
3855 /* currently supports only one outstanding message */
3857 bp->hwrm_intr_seq_id = le16_to_cpu(req->seq_id);
3859 if ((bp->fw_cap & BNXT_FW_CAP_SHORT_CMD) ||
3860 msg_len > BNXT_HWRM_MAX_REQ_LEN) {
3861 void *short_cmd_req = bp->hwrm_short_cmd_req_addr;
3864 /* Set boundary for maximum extended request length for short
3865 * cmd format. If passed up from device use the max supported
3866 * internal req length.
3868 max_msg_len = bp->hwrm_max_ext_req_len;
3870 memcpy(short_cmd_req, req, msg_len);
3871 if (msg_len < max_msg_len)
3872 memset(short_cmd_req + msg_len, 0,
3873 max_msg_len - msg_len);
3875 short_input.req_type = req->req_type;
3876 short_input.signature =
3877 cpu_to_le16(SHORT_REQ_SIGNATURE_SHORT_CMD);
3878 short_input.size = cpu_to_le16(msg_len);
3879 short_input.req_addr =
3880 cpu_to_le64(bp->hwrm_short_cmd_req_dma_addr);
3882 data = (u32 *)&short_input;
3883 msg_len = sizeof(short_input);
3885 /* Sync memory write before updating doorbell */
3888 max_req_len = BNXT_HWRM_SHORT_REQ_LEN;
3891 /* Write request msg to hwrm channel */
3892 __iowrite32_copy(bp->bar0 + bar_offset, data, msg_len / 4);
3894 for (i = msg_len; i < max_req_len; i += 4)
3895 writel(0, bp->bar0 + bar_offset + i);
3897 /* Ring channel doorbell */
3898 writel(1, bp->bar0 + doorbell_offset);
3901 timeout = DFLT_HWRM_CMD_TIMEOUT;
3902 /* convert timeout to usec */
3906 /* Short timeout for the first few iterations:
3907 * number of loops = number of loops for short timeout +
3908 * number of loops for standard timeout.
3910 tmo_count = HWRM_SHORT_TIMEOUT_COUNTER;
3911 timeout = timeout - HWRM_SHORT_MIN_TIMEOUT * HWRM_SHORT_TIMEOUT_COUNTER;
3912 tmo_count += DIV_ROUND_UP(timeout, HWRM_MIN_TIMEOUT);
3913 resp_len = (__le32 *)(resp_addr + HWRM_RESP_LEN_OFFSET);
3916 u16 seq_id = bp->hwrm_intr_seq_id;
3918 /* Wait until hwrm response cmpl interrupt is processed */
3919 while (bp->hwrm_intr_seq_id != (u16)~seq_id &&
3921 /* on first few passes, just barely sleep */
3922 if (i < HWRM_SHORT_TIMEOUT_COUNTER)
3923 usleep_range(HWRM_SHORT_MIN_TIMEOUT,
3924 HWRM_SHORT_MAX_TIMEOUT);
3926 usleep_range(HWRM_MIN_TIMEOUT,
3930 if (bp->hwrm_intr_seq_id != (u16)~seq_id) {
3931 netdev_err(bp->dev, "Resp cmpl intr err msg: 0x%x\n",
3932 le16_to_cpu(req->req_type));
3935 len = (le32_to_cpu(*resp_len) & HWRM_RESP_LEN_MASK) >>
3937 valid = resp_addr + len - 1;
3941 /* Check if response len is updated */
3942 for (i = 0; i < tmo_count; i++) {
3943 len = (le32_to_cpu(*resp_len) & HWRM_RESP_LEN_MASK) >>
3947 /* on first few passes, just barely sleep */
3948 if (i < HWRM_SHORT_TIMEOUT_COUNTER)
3949 usleep_range(HWRM_SHORT_MIN_TIMEOUT,
3950 HWRM_SHORT_MAX_TIMEOUT);
3952 usleep_range(HWRM_MIN_TIMEOUT,
3956 if (i >= tmo_count) {
3957 netdev_err(bp->dev, "Error (timeout: %d) msg {0x%x 0x%x} len:%d\n",
3958 HWRM_TOTAL_TIMEOUT(i),
3959 le16_to_cpu(req->req_type),
3960 le16_to_cpu(req->seq_id), len);
3964 /* Last byte of resp contains valid bit */
3965 valid = resp_addr + len - 1;
3966 for (j = 0; j < HWRM_VALID_BIT_DELAY_USEC; j++) {
3967 /* make sure we read from updated DMA memory */
3974 if (j >= HWRM_VALID_BIT_DELAY_USEC) {
3975 netdev_err(bp->dev, "Error (timeout: %d) msg {0x%x 0x%x} len:%d v:%d\n",
3976 HWRM_TOTAL_TIMEOUT(i),
3977 le16_to_cpu(req->req_type),
3978 le16_to_cpu(req->seq_id), len, *valid);
3983 /* Zero valid bit for compatibility. Valid bit in an older spec
3984 * may become a new field in a newer spec. We must make sure that
3985 * a new field not implemented by old spec will read zero.
3988 rc = le16_to_cpu(resp->error_code);
3990 netdev_err(bp->dev, "hwrm req_type 0x%x seq id 0x%x error 0x%x\n",
3991 le16_to_cpu(resp->req_type),
3992 le16_to_cpu(resp->seq_id), rc);
3996 int _hwrm_send_message(struct bnxt *bp, void *msg, u32 msg_len, int timeout)
3998 return bnxt_hwrm_do_send_msg(bp, msg, msg_len, timeout, false);
4001 int _hwrm_send_message_silent(struct bnxt *bp, void *msg, u32 msg_len,
4004 return bnxt_hwrm_do_send_msg(bp, msg, msg_len, timeout, true);
4007 int hwrm_send_message(struct bnxt *bp, void *msg, u32 msg_len, int timeout)
4011 mutex_lock(&bp->hwrm_cmd_lock);
4012 rc = _hwrm_send_message(bp, msg, msg_len, timeout);
4013 mutex_unlock(&bp->hwrm_cmd_lock);
4017 int hwrm_send_message_silent(struct bnxt *bp, void *msg, u32 msg_len,
4022 mutex_lock(&bp->hwrm_cmd_lock);
4023 rc = bnxt_hwrm_do_send_msg(bp, msg, msg_len, timeout, true);
4024 mutex_unlock(&bp->hwrm_cmd_lock);
4028 int bnxt_hwrm_func_rgtr_async_events(struct bnxt *bp, unsigned long *bmap,
4031 struct hwrm_func_drv_rgtr_input req = {0};
4032 DECLARE_BITMAP(async_events_bmap, 256);
4033 u32 *events = (u32 *)async_events_bmap;
4036 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_RGTR, -1, -1);
4039 cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_ASYNC_EVENT_FWD);
4041 memset(async_events_bmap, 0, sizeof(async_events_bmap));
4042 for (i = 0; i < ARRAY_SIZE(bnxt_async_events_arr); i++)
4043 __set_bit(bnxt_async_events_arr[i], async_events_bmap);
4045 if (bmap && bmap_size) {
4046 for (i = 0; i < bmap_size; i++) {
4047 if (test_bit(i, bmap))
4048 __set_bit(i, async_events_bmap);
4052 for (i = 0; i < 8; i++)
4053 req.async_event_fwd[i] |= cpu_to_le32(events[i]);
4055 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4058 static int bnxt_hwrm_func_drv_rgtr(struct bnxt *bp)
4060 struct hwrm_func_drv_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
4061 struct hwrm_func_drv_rgtr_input req = {0};
4064 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_RGTR, -1, -1);
4067 cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_OS_TYPE |
4068 FUNC_DRV_RGTR_REQ_ENABLES_VER);
4070 req.os_type = cpu_to_le16(FUNC_DRV_RGTR_REQ_OS_TYPE_LINUX);
4071 req.flags = cpu_to_le32(FUNC_DRV_RGTR_REQ_FLAGS_16BIT_VER_MODE);
4072 req.ver_maj_8b = DRV_VER_MAJ;
4073 req.ver_min_8b = DRV_VER_MIN;
4074 req.ver_upd_8b = DRV_VER_UPD;
4075 req.ver_maj = cpu_to_le16(DRV_VER_MAJ);
4076 req.ver_min = cpu_to_le16(DRV_VER_MIN);
4077 req.ver_upd = cpu_to_le16(DRV_VER_UPD);
4083 memset(data, 0, sizeof(data));
4084 for (i = 0; i < ARRAY_SIZE(bnxt_vf_req_snif); i++) {
4085 u16 cmd = bnxt_vf_req_snif[i];
4086 unsigned int bit, idx;
4090 data[idx] |= 1 << bit;
4093 for (i = 0; i < 8; i++)
4094 req.vf_req_fwd[i] = cpu_to_le32(data[i]);
4097 cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_VF_REQ_FWD);
4100 if (bp->fw_cap & BNXT_FW_CAP_OVS_64BIT_HANDLE)
4101 req.flags |= cpu_to_le32(
4102 FUNC_DRV_RGTR_REQ_FLAGS_FLOW_HANDLE_64BIT_MODE);
4104 mutex_lock(&bp->hwrm_cmd_lock);
4105 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4108 else if (resp->flags &
4109 cpu_to_le32(FUNC_DRV_RGTR_RESP_FLAGS_IF_CHANGE_SUPPORTED))
4110 bp->fw_cap |= BNXT_FW_CAP_IF_CHANGE;
4111 mutex_unlock(&bp->hwrm_cmd_lock);
4115 static int bnxt_hwrm_func_drv_unrgtr(struct bnxt *bp)
4117 struct hwrm_func_drv_unrgtr_input req = {0};
4119 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_UNRGTR, -1, -1);
4120 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4123 static int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, u8 tunnel_type)
4126 struct hwrm_tunnel_dst_port_free_input req = {0};
4128 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_TUNNEL_DST_PORT_FREE, -1, -1);
4129 req.tunnel_type = tunnel_type;
4131 switch (tunnel_type) {
4132 case TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN:
4133 req.tunnel_dst_port_id = bp->vxlan_fw_dst_port_id;
4135 case TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE:
4136 req.tunnel_dst_port_id = bp->nge_fw_dst_port_id;
4142 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4144 netdev_err(bp->dev, "hwrm_tunnel_dst_port_free failed. rc:%d\n",
4149 static int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, __be16 port,
4153 struct hwrm_tunnel_dst_port_alloc_input req = {0};
4154 struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr;
4156 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_TUNNEL_DST_PORT_ALLOC, -1, -1);
4158 req.tunnel_type = tunnel_type;
4159 req.tunnel_dst_port_val = port;
4161 mutex_lock(&bp->hwrm_cmd_lock);
4162 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4164 netdev_err(bp->dev, "hwrm_tunnel_dst_port_alloc failed. rc:%d\n",
4169 switch (tunnel_type) {
4170 case TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN:
4171 bp->vxlan_fw_dst_port_id = resp->tunnel_dst_port_id;
4173 case TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_GENEVE:
4174 bp->nge_fw_dst_port_id = resp->tunnel_dst_port_id;
4181 mutex_unlock(&bp->hwrm_cmd_lock);
4185 static int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp, u16 vnic_id)
4187 struct hwrm_cfa_l2_set_rx_mask_input req = {0};
4188 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
4190 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_SET_RX_MASK, -1, -1);
4191 req.vnic_id = cpu_to_le32(vnic->fw_vnic_id);
4193 req.num_mc_entries = cpu_to_le32(vnic->mc_list_count);
4194 req.mc_tbl_addr = cpu_to_le64(vnic->mc_list_mapping);
4195 req.mask = cpu_to_le32(vnic->rx_mask);
4196 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4199 #ifdef CONFIG_RFS_ACCEL
4200 static int bnxt_hwrm_cfa_ntuple_filter_free(struct bnxt *bp,
4201 struct bnxt_ntuple_filter *fltr)
4203 struct hwrm_cfa_ntuple_filter_free_input req = {0};
4205 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_NTUPLE_FILTER_FREE, -1, -1);
4206 req.ntuple_filter_id = fltr->filter_id;
4207 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4210 #define BNXT_NTP_FLTR_FLAGS \
4211 (CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID | \
4212 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_ETHERTYPE | \
4213 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_MACADDR | \
4214 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IPADDR_TYPE | \
4215 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR | \
4216 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR_MASK | \
4217 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR | \
4218 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR_MASK | \
4219 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IP_PROTOCOL | \
4220 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT | \
4221 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT_MASK | \
4222 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT | \
4223 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT_MASK | \
4224 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_ID)
4226 #define BNXT_NTP_TUNNEL_FLTR_FLAG \
4227 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE
4229 static int bnxt_hwrm_cfa_ntuple_filter_alloc(struct bnxt *bp,
4230 struct bnxt_ntuple_filter *fltr)
4232 struct hwrm_cfa_ntuple_filter_alloc_input req = {0};
4233 struct hwrm_cfa_ntuple_filter_alloc_output *resp;
4234 struct flow_keys *keys = &fltr->fkeys;
4235 struct bnxt_vnic_info *vnic;
4239 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_NTUPLE_FILTER_ALLOC, -1, -1);
4240 req.l2_filter_id = bp->vnic_info[0].fw_l2_filter_id[fltr->l2_fltr_idx];
4242 if (bp->fw_cap & BNXT_FW_CAP_CFA_RFS_RING_TBL_IDX) {
4243 dst_ena = CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_RFS_RING_TBL_IDX;
4244 req.rfs_ring_tbl_idx = cpu_to_le16(fltr->rxq);
4245 vnic = &bp->vnic_info[0];
4247 vnic = &bp->vnic_info[fltr->rxq + 1];
4249 req.dst_id = cpu_to_le16(vnic->fw_vnic_id);
4250 req.enables = cpu_to_le32(BNXT_NTP_FLTR_FLAGS | dst_ena);
4252 req.ethertype = htons(ETH_P_IP);
4253 memcpy(req.src_macaddr, fltr->src_mac_addr, ETH_ALEN);
4254 req.ip_addr_type = CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV4;
4255 req.ip_protocol = keys->basic.ip_proto;
4257 if (keys->basic.n_proto == htons(ETH_P_IPV6)) {
4260 req.ethertype = htons(ETH_P_IPV6);
4262 CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6;
4263 *(struct in6_addr *)&req.src_ipaddr[0] =
4264 keys->addrs.v6addrs.src;
4265 *(struct in6_addr *)&req.dst_ipaddr[0] =
4266 keys->addrs.v6addrs.dst;
4267 for (i = 0; i < 4; i++) {
4268 req.src_ipaddr_mask[i] = cpu_to_be32(0xffffffff);
4269 req.dst_ipaddr_mask[i] = cpu_to_be32(0xffffffff);
4272 req.src_ipaddr[0] = keys->addrs.v4addrs.src;
4273 req.src_ipaddr_mask[0] = cpu_to_be32(0xffffffff);
4274 req.dst_ipaddr[0] = keys->addrs.v4addrs.dst;
4275 req.dst_ipaddr_mask[0] = cpu_to_be32(0xffffffff);
4277 if (keys->control.flags & FLOW_DIS_ENCAPSULATION) {
4278 req.enables |= cpu_to_le32(BNXT_NTP_TUNNEL_FLTR_FLAG);
4280 CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL;
4283 req.src_port = keys->ports.src;
4284 req.src_port_mask = cpu_to_be16(0xffff);
4285 req.dst_port = keys->ports.dst;
4286 req.dst_port_mask = cpu_to_be16(0xffff);
4288 mutex_lock(&bp->hwrm_cmd_lock);
4289 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4291 resp = bnxt_get_hwrm_resp_addr(bp, &req);
4292 fltr->filter_id = resp->ntuple_filter_id;
4294 mutex_unlock(&bp->hwrm_cmd_lock);
4299 static int bnxt_hwrm_set_vnic_filter(struct bnxt *bp, u16 vnic_id, u16 idx,
4303 struct hwrm_cfa_l2_filter_alloc_input req = {0};
4304 struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
4306 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_FILTER_ALLOC, -1, -1);
4307 req.flags = cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX);
4308 if (!BNXT_CHIP_TYPE_NITRO_A0(bp))
4310 cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_FLAGS_OUTERMOST);
4311 req.dst_id = cpu_to_le16(bp->vnic_info[vnic_id].fw_vnic_id);
4313 cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR |
4314 CFA_L2_FILTER_ALLOC_REQ_ENABLES_DST_ID |
4315 CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR_MASK);
4316 memcpy(req.l2_addr, mac_addr, ETH_ALEN);
4317 req.l2_addr_mask[0] = 0xff;
4318 req.l2_addr_mask[1] = 0xff;
4319 req.l2_addr_mask[2] = 0xff;
4320 req.l2_addr_mask[3] = 0xff;
4321 req.l2_addr_mask[4] = 0xff;
4322 req.l2_addr_mask[5] = 0xff;
4324 mutex_lock(&bp->hwrm_cmd_lock);
4325 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4327 bp->vnic_info[vnic_id].fw_l2_filter_id[idx] =
4329 mutex_unlock(&bp->hwrm_cmd_lock);
4333 static int bnxt_hwrm_clear_vnic_filter(struct bnxt *bp)
4335 u16 i, j, num_of_vnics = 1; /* only vnic 0 supported */
4338 /* Any associated ntuple filters will also be cleared by firmware. */
4339 mutex_lock(&bp->hwrm_cmd_lock);
4340 for (i = 0; i < num_of_vnics; i++) {
4341 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
4343 for (j = 0; j < vnic->uc_filter_count; j++) {
4344 struct hwrm_cfa_l2_filter_free_input req = {0};
4346 bnxt_hwrm_cmd_hdr_init(bp, &req,
4347 HWRM_CFA_L2_FILTER_FREE, -1, -1);
4349 req.l2_filter_id = vnic->fw_l2_filter_id[j];
4351 rc = _hwrm_send_message(bp, &req, sizeof(req),
4354 vnic->uc_filter_count = 0;
4356 mutex_unlock(&bp->hwrm_cmd_lock);
4361 static int bnxt_hwrm_vnic_set_tpa(struct bnxt *bp, u16 vnic_id, u32 tpa_flags)
4363 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
4364 struct hwrm_vnic_tpa_cfg_input req = {0};
4366 if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
4369 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_TPA_CFG, -1, -1);
4372 u16 mss = bp->dev->mtu - 40;
4373 u32 nsegs, n, segs = 0, flags;
4375 flags = VNIC_TPA_CFG_REQ_FLAGS_TPA |
4376 VNIC_TPA_CFG_REQ_FLAGS_ENCAP_TPA |
4377 VNIC_TPA_CFG_REQ_FLAGS_RSC_WND_UPDATE |
4378 VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_ECN |
4379 VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_SAME_GRE_SEQ;
4380 if (tpa_flags & BNXT_FLAG_GRO)
4381 flags |= VNIC_TPA_CFG_REQ_FLAGS_GRO;
4383 req.flags = cpu_to_le32(flags);
4386 cpu_to_le32(VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_SEGS |
4387 VNIC_TPA_CFG_REQ_ENABLES_MAX_AGGS |
4388 VNIC_TPA_CFG_REQ_ENABLES_MIN_AGG_LEN);
4390 /* Number of segs are log2 units, and first packet is not
4391 * included as part of this units.
4393 if (mss <= BNXT_RX_PAGE_SIZE) {
4394 n = BNXT_RX_PAGE_SIZE / mss;
4395 nsegs = (MAX_SKB_FRAGS - 1) * n;
4397 n = mss / BNXT_RX_PAGE_SIZE;
4398 if (mss & (BNXT_RX_PAGE_SIZE - 1))
4400 nsegs = (MAX_SKB_FRAGS - n) / n;
4403 segs = ilog2(nsegs);
4404 req.max_agg_segs = cpu_to_le16(segs);
4405 req.max_aggs = cpu_to_le16(VNIC_TPA_CFG_REQ_MAX_AGGS_MAX);
4407 req.min_agg_len = cpu_to_le32(512);
4409 req.vnic_id = cpu_to_le16(vnic->fw_vnic_id);
4411 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4414 static u16 bnxt_cp_ring_from_grp(struct bnxt *bp, struct bnxt_ring_struct *ring)
4416 struct bnxt_ring_grp_info *grp_info;
4418 grp_info = &bp->grp_info[ring->grp_idx];
4419 return grp_info->cp_fw_ring_id;
4422 static u16 bnxt_cp_ring_for_rx(struct bnxt *bp, struct bnxt_rx_ring_info *rxr)
4424 if (bp->flags & BNXT_FLAG_CHIP_P5) {
4425 struct bnxt_napi *bnapi = rxr->bnapi;
4426 struct bnxt_cp_ring_info *cpr;
4428 cpr = bnapi->cp_ring.cp_ring_arr[BNXT_RX_HDL];
4429 return cpr->cp_ring_struct.fw_ring_id;
4431 return bnxt_cp_ring_from_grp(bp, &rxr->rx_ring_struct);
4435 static u16 bnxt_cp_ring_for_tx(struct bnxt *bp, struct bnxt_tx_ring_info *txr)
4437 if (bp->flags & BNXT_FLAG_CHIP_P5) {
4438 struct bnxt_napi *bnapi = txr->bnapi;
4439 struct bnxt_cp_ring_info *cpr;
4441 cpr = bnapi->cp_ring.cp_ring_arr[BNXT_TX_HDL];
4442 return cpr->cp_ring_struct.fw_ring_id;
4444 return bnxt_cp_ring_from_grp(bp, &txr->tx_ring_struct);
4448 static int bnxt_hwrm_vnic_set_rss(struct bnxt *bp, u16 vnic_id, bool set_rss)
4450 u32 i, j, max_rings;
4451 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
4452 struct hwrm_vnic_rss_cfg_input req = {0};
4454 if ((bp->flags & BNXT_FLAG_CHIP_P5) ||
4455 vnic->fw_rss_cos_lb_ctx[0] == INVALID_HW_RING_ID)
4458 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_CFG, -1, -1);
4460 req.hash_type = cpu_to_le32(bp->rss_hash_cfg);
4461 req.hash_mode_flags = VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_DEFAULT;
4462 if (vnic->flags & BNXT_VNIC_RSS_FLAG) {
4463 if (BNXT_CHIP_TYPE_NITRO_A0(bp))
4464 max_rings = bp->rx_nr_rings - 1;
4466 max_rings = bp->rx_nr_rings;
4471 /* Fill the RSS indirection table with ring group ids */
4472 for (i = 0, j = 0; i < HW_HASH_INDEX_SIZE; i++, j++) {
4475 vnic->rss_table[i] = cpu_to_le16(vnic->fw_grp_ids[j]);
4478 req.ring_grp_tbl_addr = cpu_to_le64(vnic->rss_table_dma_addr);
4479 req.hash_key_tbl_addr =
4480 cpu_to_le64(vnic->rss_hash_key_dma_addr);
4482 req.rss_ctx_idx = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[0]);
4483 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4486 static int bnxt_hwrm_vnic_set_rss_p5(struct bnxt *bp, u16 vnic_id, bool set_rss)
4488 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
4489 u32 i, j, k, nr_ctxs, max_rings = bp->rx_nr_rings;
4490 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[0];
4491 struct hwrm_vnic_rss_cfg_input req = {0};
4493 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_CFG, -1, -1);
4494 req.vnic_id = cpu_to_le16(vnic->fw_vnic_id);
4496 hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4499 req.hash_type = cpu_to_le32(bp->rss_hash_cfg);
4500 req.hash_mode_flags = VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_DEFAULT;
4501 req.ring_grp_tbl_addr = cpu_to_le64(vnic->rss_table_dma_addr);
4502 req.hash_key_tbl_addr = cpu_to_le64(vnic->rss_hash_key_dma_addr);
4503 nr_ctxs = DIV_ROUND_UP(bp->rx_nr_rings, 64);
4504 for (i = 0, k = 0; i < nr_ctxs; i++) {
4505 __le16 *ring_tbl = vnic->rss_table;
4508 req.ring_table_pair_index = i;
4509 req.rss_ctx_idx = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[i]);
4510 for (j = 0; j < 64; j++) {
4513 ring_id = rxr->rx_ring_struct.fw_ring_id;
4514 *ring_tbl++ = cpu_to_le16(ring_id);
4515 ring_id = bnxt_cp_ring_for_rx(bp, rxr);
4516 *ring_tbl++ = cpu_to_le16(ring_id);
4519 if (k == max_rings) {
4521 rxr = &bp->rx_ring[0];
4524 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4531 static int bnxt_hwrm_vnic_set_hds(struct bnxt *bp, u16 vnic_id)
4533 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
4534 struct hwrm_vnic_plcmodes_cfg_input req = {0};
4536 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_PLCMODES_CFG, -1, -1);
4537 req.flags = cpu_to_le32(VNIC_PLCMODES_CFG_REQ_FLAGS_JUMBO_PLACEMENT |
4538 VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV4 |
4539 VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV6);
4541 cpu_to_le32(VNIC_PLCMODES_CFG_REQ_ENABLES_JUMBO_THRESH_VALID |
4542 VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_THRESHOLD_VALID);
4543 /* thresholds not implemented in firmware yet */
4544 req.jumbo_thresh = cpu_to_le16(bp->rx_copy_thresh);
4545 req.hds_threshold = cpu_to_le16(bp->rx_copy_thresh);
4546 req.vnic_id = cpu_to_le32(vnic->fw_vnic_id);
4547 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4550 static void bnxt_hwrm_vnic_ctx_free_one(struct bnxt *bp, u16 vnic_id,
4553 struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {0};
4555 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_COS_LB_CTX_FREE, -1, -1);
4556 req.rss_cos_lb_ctx_id =
4557 cpu_to_le16(bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[ctx_idx]);
4559 hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4560 bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[ctx_idx] = INVALID_HW_RING_ID;
4563 static void bnxt_hwrm_vnic_ctx_free(struct bnxt *bp)
4567 for (i = 0; i < bp->nr_vnics; i++) {
4568 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
4570 for (j = 0; j < BNXT_MAX_CTX_PER_VNIC; j++) {
4571 if (vnic->fw_rss_cos_lb_ctx[j] != INVALID_HW_RING_ID)
4572 bnxt_hwrm_vnic_ctx_free_one(bp, i, j);
4575 bp->rsscos_nr_ctxs = 0;
4578 static int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp, u16 vnic_id, u16 ctx_idx)
4581 struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {0};
4582 struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp =
4583 bp->hwrm_cmd_resp_addr;
4585 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_COS_LB_CTX_ALLOC, -1,
4588 mutex_lock(&bp->hwrm_cmd_lock);
4589 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4591 bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[ctx_idx] =
4592 le16_to_cpu(resp->rss_cos_lb_ctx_id);
4593 mutex_unlock(&bp->hwrm_cmd_lock);
4598 static u32 bnxt_get_roce_vnic_mode(struct bnxt *bp)
4600 if (bp->flags & BNXT_FLAG_ROCE_MIRROR_CAP)
4601 return VNIC_CFG_REQ_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_MODE;
4602 return VNIC_CFG_REQ_FLAGS_ROCE_DUAL_VNIC_MODE;
4605 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, u16 vnic_id)
4607 unsigned int ring = 0, grp_idx;
4608 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
4609 struct hwrm_vnic_cfg_input req = {0};
4612 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_CFG, -1, -1);
4614 if (bp->flags & BNXT_FLAG_CHIP_P5) {
4615 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[0];
4617 req.default_rx_ring_id =
4618 cpu_to_le16(rxr->rx_ring_struct.fw_ring_id);
4619 req.default_cmpl_ring_id =
4620 cpu_to_le16(bnxt_cp_ring_for_rx(bp, rxr));
4622 cpu_to_le32(VNIC_CFG_REQ_ENABLES_DEFAULT_RX_RING_ID |
4623 VNIC_CFG_REQ_ENABLES_DEFAULT_CMPL_RING_ID);
4626 req.enables = cpu_to_le32(VNIC_CFG_REQ_ENABLES_DFLT_RING_GRP);
4627 /* Only RSS support for now TBD: COS & LB */
4628 if (vnic->fw_rss_cos_lb_ctx[0] != INVALID_HW_RING_ID) {
4629 req.rss_rule = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[0]);
4630 req.enables |= cpu_to_le32(VNIC_CFG_REQ_ENABLES_RSS_RULE |
4631 VNIC_CFG_REQ_ENABLES_MRU);
4632 } else if (vnic->flags & BNXT_VNIC_RFS_NEW_RSS_FLAG) {
4634 cpu_to_le16(bp->vnic_info[0].fw_rss_cos_lb_ctx[0]);
4635 req.enables |= cpu_to_le32(VNIC_CFG_REQ_ENABLES_RSS_RULE |
4636 VNIC_CFG_REQ_ENABLES_MRU);
4637 req.flags |= cpu_to_le32(VNIC_CFG_REQ_FLAGS_RSS_DFLT_CR_MODE);
4639 req.rss_rule = cpu_to_le16(0xffff);
4642 if (BNXT_CHIP_TYPE_NITRO_A0(bp) &&
4643 (vnic->fw_rss_cos_lb_ctx[0] != INVALID_HW_RING_ID)) {
4644 req.cos_rule = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[1]);
4645 req.enables |= cpu_to_le32(VNIC_CFG_REQ_ENABLES_COS_RULE);
4647 req.cos_rule = cpu_to_le16(0xffff);
4650 if (vnic->flags & BNXT_VNIC_RSS_FLAG)
4652 else if (vnic->flags & BNXT_VNIC_RFS_FLAG)
4654 else if ((vnic_id == 1) && BNXT_CHIP_TYPE_NITRO_A0(bp))
4655 ring = bp->rx_nr_rings - 1;
4657 grp_idx = bp->rx_ring[ring].bnapi->index;
4658 req.dflt_ring_grp = cpu_to_le16(bp->grp_info[grp_idx].fw_grp_id);
4659 req.lb_rule = cpu_to_le16(0xffff);
4661 req.mru = cpu_to_le16(bp->dev->mtu + ETH_HLEN + ETH_FCS_LEN +
4664 req.vnic_id = cpu_to_le16(vnic->fw_vnic_id);
4665 #ifdef CONFIG_BNXT_SRIOV
4667 def_vlan = bp->vf.vlan;
4669 if ((bp->flags & BNXT_FLAG_STRIP_VLAN) || def_vlan)
4670 req.flags |= cpu_to_le32(VNIC_CFG_REQ_FLAGS_VLAN_STRIP_MODE);
4671 if (!vnic_id && bnxt_ulp_registered(bp->edev, BNXT_ROCE_ULP))
4672 req.flags |= cpu_to_le32(bnxt_get_roce_vnic_mode(bp));
4674 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4677 static int bnxt_hwrm_vnic_free_one(struct bnxt *bp, u16 vnic_id)
4681 if (bp->vnic_info[vnic_id].fw_vnic_id != INVALID_HW_RING_ID) {
4682 struct hwrm_vnic_free_input req = {0};
4684 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_FREE, -1, -1);
4686 cpu_to_le32(bp->vnic_info[vnic_id].fw_vnic_id);
4688 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4691 bp->vnic_info[vnic_id].fw_vnic_id = INVALID_HW_RING_ID;
4696 static void bnxt_hwrm_vnic_free(struct bnxt *bp)
4700 for (i = 0; i < bp->nr_vnics; i++)
4701 bnxt_hwrm_vnic_free_one(bp, i);
4704 static int bnxt_hwrm_vnic_alloc(struct bnxt *bp, u16 vnic_id,
4705 unsigned int start_rx_ring_idx,
4706 unsigned int nr_rings)
4709 unsigned int i, j, grp_idx, end_idx = start_rx_ring_idx + nr_rings;
4710 struct hwrm_vnic_alloc_input req = {0};
4711 struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
4712 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
4714 if (bp->flags & BNXT_FLAG_CHIP_P5)
4715 goto vnic_no_ring_grps;
4717 /* map ring groups to this vnic */
4718 for (i = start_rx_ring_idx, j = 0; i < end_idx; i++, j++) {
4719 grp_idx = bp->rx_ring[i].bnapi->index;
4720 if (bp->grp_info[grp_idx].fw_grp_id == INVALID_HW_RING_ID) {
4721 netdev_err(bp->dev, "Not enough ring groups avail:%x req:%x\n",
4725 vnic->fw_grp_ids[j] = bp->grp_info[grp_idx].fw_grp_id;
4729 for (i = 0; i < BNXT_MAX_CTX_PER_VNIC; i++)
4730 vnic->fw_rss_cos_lb_ctx[i] = INVALID_HW_RING_ID;
4732 req.flags = cpu_to_le32(VNIC_ALLOC_REQ_FLAGS_DEFAULT);
4734 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_ALLOC, -1, -1);
4736 mutex_lock(&bp->hwrm_cmd_lock);
4737 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4739 vnic->fw_vnic_id = le32_to_cpu(resp->vnic_id);
4740 mutex_unlock(&bp->hwrm_cmd_lock);
4744 static int bnxt_hwrm_vnic_qcaps(struct bnxt *bp)
4746 struct hwrm_vnic_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
4747 struct hwrm_vnic_qcaps_input req = {0};
4750 if (bp->hwrm_spec_code < 0x10600)
4753 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_QCAPS, -1, -1);
4754 mutex_lock(&bp->hwrm_cmd_lock);
4755 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4757 u32 flags = le32_to_cpu(resp->flags);
4759 if (!(bp->flags & BNXT_FLAG_CHIP_P5) &&
4760 (flags & VNIC_QCAPS_RESP_FLAGS_RSS_DFLT_CR_CAP))
4761 bp->flags |= BNXT_FLAG_NEW_RSS_CAP;
4763 VNIC_QCAPS_RESP_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_CAP)
4764 bp->flags |= BNXT_FLAG_ROCE_MIRROR_CAP;
4766 mutex_unlock(&bp->hwrm_cmd_lock);
4770 static int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp)
4775 if (bp->flags & BNXT_FLAG_CHIP_P5)
4778 mutex_lock(&bp->hwrm_cmd_lock);
4779 for (i = 0; i < bp->rx_nr_rings; i++) {
4780 struct hwrm_ring_grp_alloc_input req = {0};
4781 struct hwrm_ring_grp_alloc_output *resp =
4782 bp->hwrm_cmd_resp_addr;
4783 unsigned int grp_idx = bp->rx_ring[i].bnapi->index;
4785 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_GRP_ALLOC, -1, -1);
4787 req.cr = cpu_to_le16(bp->grp_info[grp_idx].cp_fw_ring_id);
4788 req.rr = cpu_to_le16(bp->grp_info[grp_idx].rx_fw_ring_id);
4789 req.ar = cpu_to_le16(bp->grp_info[grp_idx].agg_fw_ring_id);
4790 req.sc = cpu_to_le16(bp->grp_info[grp_idx].fw_stats_ctx);
4792 rc = _hwrm_send_message(bp, &req, sizeof(req),
4797 bp->grp_info[grp_idx].fw_grp_id =
4798 le32_to_cpu(resp->ring_group_id);
4800 mutex_unlock(&bp->hwrm_cmd_lock);
4804 static int bnxt_hwrm_ring_grp_free(struct bnxt *bp)
4808 struct hwrm_ring_grp_free_input req = {0};
4810 if (!bp->grp_info || (bp->flags & BNXT_FLAG_CHIP_P5))
4813 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_GRP_FREE, -1, -1);
4815 mutex_lock(&bp->hwrm_cmd_lock);
4816 for (i = 0; i < bp->cp_nr_rings; i++) {
4817 if (bp->grp_info[i].fw_grp_id == INVALID_HW_RING_ID)
4820 cpu_to_le32(bp->grp_info[i].fw_grp_id);
4822 rc = _hwrm_send_message(bp, &req, sizeof(req),
4826 bp->grp_info[i].fw_grp_id = INVALID_HW_RING_ID;
4828 mutex_unlock(&bp->hwrm_cmd_lock);
4832 static int hwrm_ring_alloc_send_msg(struct bnxt *bp,
4833 struct bnxt_ring_struct *ring,
4834 u32 ring_type, u32 map_index)
4836 int rc = 0, err = 0;
4837 struct hwrm_ring_alloc_input req = {0};
4838 struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr;
4839 struct bnxt_ring_mem_info *rmem = &ring->ring_mem;
4840 struct bnxt_ring_grp_info *grp_info;
4843 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_ALLOC, -1, -1);
4846 if (rmem->nr_pages > 1) {
4847 req.page_tbl_addr = cpu_to_le64(rmem->pg_tbl_map);
4848 /* Page size is in log2 units */
4849 req.page_size = BNXT_PAGE_SHIFT;
4850 req.page_tbl_depth = 1;
4852 req.page_tbl_addr = cpu_to_le64(rmem->dma_arr[0]);
4855 /* Association of ring index with doorbell index and MSIX number */
4856 req.logical_id = cpu_to_le16(map_index);
4858 switch (ring_type) {
4859 case HWRM_RING_ALLOC_TX: {
4860 struct bnxt_tx_ring_info *txr;
4862 txr = container_of(ring, struct bnxt_tx_ring_info,
4864 req.ring_type = RING_ALLOC_REQ_RING_TYPE_TX;
4865 /* Association of transmit ring with completion ring */
4866 grp_info = &bp->grp_info[ring->grp_idx];
4867 req.cmpl_ring_id = cpu_to_le16(bnxt_cp_ring_for_tx(bp, txr));
4868 req.length = cpu_to_le32(bp->tx_ring_mask + 1);
4869 req.stat_ctx_id = cpu_to_le32(grp_info->fw_stats_ctx);
4870 req.queue_id = cpu_to_le16(ring->queue_id);
4873 case HWRM_RING_ALLOC_RX:
4874 req.ring_type = RING_ALLOC_REQ_RING_TYPE_RX;
4875 req.length = cpu_to_le32(bp->rx_ring_mask + 1);
4876 if (bp->flags & BNXT_FLAG_CHIP_P5) {
4879 /* Association of rx ring with stats context */
4880 grp_info = &bp->grp_info[ring->grp_idx];
4881 req.rx_buf_size = cpu_to_le16(bp->rx_buf_use_size);
4882 req.stat_ctx_id = cpu_to_le32(grp_info->fw_stats_ctx);
4883 req.enables |= cpu_to_le32(
4884 RING_ALLOC_REQ_ENABLES_RX_BUF_SIZE_VALID);
4885 if (NET_IP_ALIGN == 2)
4886 flags = RING_ALLOC_REQ_FLAGS_RX_SOP_PAD;
4887 req.flags = cpu_to_le16(flags);
4890 case HWRM_RING_ALLOC_AGG:
4891 if (bp->flags & BNXT_FLAG_CHIP_P5) {
4892 req.ring_type = RING_ALLOC_REQ_RING_TYPE_RX_AGG;
4893 /* Association of agg ring with rx ring */
4894 grp_info = &bp->grp_info[ring->grp_idx];
4895 req.rx_ring_id = cpu_to_le16(grp_info->rx_fw_ring_id);
4896 req.rx_buf_size = cpu_to_le16(BNXT_RX_PAGE_SIZE);
4897 req.stat_ctx_id = cpu_to_le32(grp_info->fw_stats_ctx);
4898 req.enables |= cpu_to_le32(
4899 RING_ALLOC_REQ_ENABLES_RX_RING_ID_VALID |
4900 RING_ALLOC_REQ_ENABLES_RX_BUF_SIZE_VALID);
4902 req.ring_type = RING_ALLOC_REQ_RING_TYPE_RX;
4904 req.length = cpu_to_le32(bp->rx_agg_ring_mask + 1);
4906 case HWRM_RING_ALLOC_CMPL:
4907 req.ring_type = RING_ALLOC_REQ_RING_TYPE_L2_CMPL;
4908 req.length = cpu_to_le32(bp->cp_ring_mask + 1);
4909 if (bp->flags & BNXT_FLAG_CHIP_P5) {
4910 /* Association of cp ring with nq */
4911 grp_info = &bp->grp_info[map_index];
4912 req.nq_ring_id = cpu_to_le16(grp_info->cp_fw_ring_id);
4913 req.cq_handle = cpu_to_le64(ring->handle);
4914 req.enables |= cpu_to_le32(
4915 RING_ALLOC_REQ_ENABLES_NQ_RING_ID_VALID);
4916 } else if (bp->flags & BNXT_FLAG_USING_MSIX) {
4917 req.int_mode = RING_ALLOC_REQ_INT_MODE_MSIX;
4920 case HWRM_RING_ALLOC_NQ:
4921 req.ring_type = RING_ALLOC_REQ_RING_TYPE_NQ;
4922 req.length = cpu_to_le32(bp->cp_ring_mask + 1);
4923 if (bp->flags & BNXT_FLAG_USING_MSIX)
4924 req.int_mode = RING_ALLOC_REQ_INT_MODE_MSIX;
4927 netdev_err(bp->dev, "hwrm alloc invalid ring type %d\n",
4932 mutex_lock(&bp->hwrm_cmd_lock);
4933 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4934 err = le16_to_cpu(resp->error_code);
4935 ring_id = le16_to_cpu(resp->ring_id);
4936 mutex_unlock(&bp->hwrm_cmd_lock);
4939 netdev_err(bp->dev, "hwrm_ring_alloc type %d failed. rc:%x err:%x\n",
4940 ring_type, rc, err);
4943 ring->fw_ring_id = ring_id;
4947 static int bnxt_hwrm_set_async_event_cr(struct bnxt *bp, int idx)
4952 struct hwrm_func_cfg_input req = {0};
4954 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_CFG, -1, -1);
4955 req.fid = cpu_to_le16(0xffff);
4956 req.enables = cpu_to_le32(FUNC_CFG_REQ_ENABLES_ASYNC_EVENT_CR);
4957 req.async_event_cr = cpu_to_le16(idx);
4958 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4960 struct hwrm_func_vf_cfg_input req = {0};
4962 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_VF_CFG, -1, -1);
4964 cpu_to_le32(FUNC_VF_CFG_REQ_ENABLES_ASYNC_EVENT_CR);
4965 req.async_event_cr = cpu_to_le16(idx);
4966 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4971 static void bnxt_set_db(struct bnxt *bp, struct bnxt_db_info *db, u32 ring_type,
4972 u32 map_idx, u32 xid)
4974 if (bp->flags & BNXT_FLAG_CHIP_P5) {
4976 db->doorbell = bp->bar1 + 0x10000;
4978 db->doorbell = bp->bar1 + 0x4000;
4979 switch (ring_type) {
4980 case HWRM_RING_ALLOC_TX:
4981 db->db_key64 = DBR_PATH_L2 | DBR_TYPE_SQ;
4983 case HWRM_RING_ALLOC_RX:
4984 case HWRM_RING_ALLOC_AGG:
4985 db->db_key64 = DBR_PATH_L2 | DBR_TYPE_SRQ;
4987 case HWRM_RING_ALLOC_CMPL:
4988 db->db_key64 = DBR_PATH_L2;
4990 case HWRM_RING_ALLOC_NQ:
4991 db->db_key64 = DBR_PATH_L2;
4994 db->db_key64 |= (u64)xid << DBR_XID_SFT;
4996 db->doorbell = bp->bar1 + map_idx * 0x80;
4997 switch (ring_type) {
4998 case HWRM_RING_ALLOC_TX:
4999 db->db_key32 = DB_KEY_TX;
5001 case HWRM_RING_ALLOC_RX:
5002 case HWRM_RING_ALLOC_AGG:
5003 db->db_key32 = DB_KEY_RX;
5005 case HWRM_RING_ALLOC_CMPL:
5006 db->db_key32 = DB_KEY_CP;
5012 static int bnxt_hwrm_ring_alloc(struct bnxt *bp)
5017 if (bp->flags & BNXT_FLAG_CHIP_P5)
5018 type = HWRM_RING_ALLOC_NQ;
5020 type = HWRM_RING_ALLOC_CMPL;
5021 for (i = 0; i < bp->cp_nr_rings; i++) {
5022 struct bnxt_napi *bnapi = bp->bnapi[i];
5023 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
5024 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct;
5025 u32 map_idx = ring->map_idx;
5026 unsigned int vector;
5028 vector = bp->irq_tbl[map_idx].vector;
5029 disable_irq_nosync(vector);
5030 rc = hwrm_ring_alloc_send_msg(bp, ring, type, map_idx);
5035 bnxt_set_db(bp, &cpr->cp_db, type, map_idx, ring->fw_ring_id);
5036 bnxt_db_nq(bp, &cpr->cp_db, cpr->cp_raw_cons);
5038 bp->grp_info[i].cp_fw_ring_id = ring->fw_ring_id;
5041 rc = bnxt_hwrm_set_async_event_cr(bp, ring->fw_ring_id);
5043 netdev_warn(bp->dev, "Failed to set async event completion ring.\n");
5047 type = HWRM_RING_ALLOC_TX;
5048 for (i = 0; i < bp->tx_nr_rings; i++) {
5049 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
5050 struct bnxt_ring_struct *ring;
5053 if (bp->flags & BNXT_FLAG_CHIP_P5) {
5054 struct bnxt_napi *bnapi = txr->bnapi;
5055 struct bnxt_cp_ring_info *cpr, *cpr2;
5056 u32 type2 = HWRM_RING_ALLOC_CMPL;
5058 cpr = &bnapi->cp_ring;
5059 cpr2 = cpr->cp_ring_arr[BNXT_TX_HDL];
5060 ring = &cpr2->cp_ring_struct;
5061 ring->handle = BNXT_TX_HDL;
5062 map_idx = bnapi->index;
5063 rc = hwrm_ring_alloc_send_msg(bp, ring, type2, map_idx);
5066 bnxt_set_db(bp, &cpr2->cp_db, type2, map_idx,
5068 bnxt_db_cq(bp, &cpr2->cp_db, cpr2->cp_raw_cons);
5070 ring = &txr->tx_ring_struct;
5072 rc = hwrm_ring_alloc_send_msg(bp, ring, type, map_idx);
5075 bnxt_set_db(bp, &txr->tx_db, type, map_idx, ring->fw_ring_id);
5078 type = HWRM_RING_ALLOC_RX;
5079 for (i = 0; i < bp->rx_nr_rings; i++) {
5080 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
5081 struct bnxt_ring_struct *ring = &rxr->rx_ring_struct;
5082 struct bnxt_napi *bnapi = rxr->bnapi;
5083 u32 map_idx = bnapi->index;
5085 rc = hwrm_ring_alloc_send_msg(bp, ring, type, map_idx);
5088 bnxt_set_db(bp, &rxr->rx_db, type, map_idx, ring->fw_ring_id);
5089 bnxt_db_write(bp, &rxr->rx_db, rxr->rx_prod);
5090 bp->grp_info[map_idx].rx_fw_ring_id = ring->fw_ring_id;
5091 if (bp->flags & BNXT_FLAG_CHIP_P5) {
5092 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
5093 u32 type2 = HWRM_RING_ALLOC_CMPL;
5094 struct bnxt_cp_ring_info *cpr2;
5096 cpr2 = cpr->cp_ring_arr[BNXT_RX_HDL];
5097 ring = &cpr2->cp_ring_struct;
5098 ring->handle = BNXT_RX_HDL;
5099 rc = hwrm_ring_alloc_send_msg(bp, ring, type2, map_idx);
5102 bnxt_set_db(bp, &cpr2->cp_db, type2, map_idx,
5104 bnxt_db_cq(bp, &cpr2->cp_db, cpr2->cp_raw_cons);
5108 if (bp->flags & BNXT_FLAG_AGG_RINGS) {
5109 type = HWRM_RING_ALLOC_AGG;
5110 for (i = 0; i < bp->rx_nr_rings; i++) {
5111 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
5112 struct bnxt_ring_struct *ring =
5113 &rxr->rx_agg_ring_struct;
5114 u32 grp_idx = ring->grp_idx;
5115 u32 map_idx = grp_idx + bp->rx_nr_rings;
5117 rc = hwrm_ring_alloc_send_msg(bp, ring, type, map_idx);
5121 bnxt_set_db(bp, &rxr->rx_agg_db, type, map_idx,
5123 bnxt_db_write(bp, &rxr->rx_agg_db, rxr->rx_agg_prod);
5124 bp->grp_info[grp_idx].agg_fw_ring_id = ring->fw_ring_id;
5131 static int hwrm_ring_free_send_msg(struct bnxt *bp,
5132 struct bnxt_ring_struct *ring,
5133 u32 ring_type, int cmpl_ring_id)
5136 struct hwrm_ring_free_input req = {0};
5137 struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;
5140 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_FREE, cmpl_ring_id, -1);
5141 req.ring_type = ring_type;
5142 req.ring_id = cpu_to_le16(ring->fw_ring_id);
5144 mutex_lock(&bp->hwrm_cmd_lock);
5145 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5146 error_code = le16_to_cpu(resp->error_code);
5147 mutex_unlock(&bp->hwrm_cmd_lock);
5149 if (rc || error_code) {
5150 netdev_err(bp->dev, "hwrm_ring_free type %d failed. rc:%x err:%x\n",
5151 ring_type, rc, error_code);
5157 static void bnxt_hwrm_ring_free(struct bnxt *bp, bool close_path)
5165 for (i = 0; i < bp->tx_nr_rings; i++) {
5166 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
5167 struct bnxt_ring_struct *ring = &txr->tx_ring_struct;
5169 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
5170 u32 cmpl_ring_id = bnxt_cp_ring_for_tx(bp, txr);
5172 hwrm_ring_free_send_msg(bp, ring,
5173 RING_FREE_REQ_RING_TYPE_TX,
5174 close_path ? cmpl_ring_id :
5175 INVALID_HW_RING_ID);
5176 ring->fw_ring_id = INVALID_HW_RING_ID;
5180 for (i = 0; i < bp->rx_nr_rings; i++) {
5181 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
5182 struct bnxt_ring_struct *ring = &rxr->rx_ring_struct;
5183 u32 grp_idx = rxr->bnapi->index;
5185 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
5186 u32 cmpl_ring_id = bnxt_cp_ring_for_rx(bp, rxr);
5188 hwrm_ring_free_send_msg(bp, ring,
5189 RING_FREE_REQ_RING_TYPE_RX,
5190 close_path ? cmpl_ring_id :
5191 INVALID_HW_RING_ID);
5192 ring->fw_ring_id = INVALID_HW_RING_ID;
5193 bp->grp_info[grp_idx].rx_fw_ring_id =
5198 if (bp->flags & BNXT_FLAG_CHIP_P5)
5199 type = RING_FREE_REQ_RING_TYPE_RX_AGG;
5201 type = RING_FREE_REQ_RING_TYPE_RX;
5202 for (i = 0; i < bp->rx_nr_rings; i++) {
5203 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
5204 struct bnxt_ring_struct *ring = &rxr->rx_agg_ring_struct;
5205 u32 grp_idx = rxr->bnapi->index;
5207 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
5208 u32 cmpl_ring_id = bnxt_cp_ring_for_rx(bp, rxr);
5210 hwrm_ring_free_send_msg(bp, ring, type,
5211 close_path ? cmpl_ring_id :
5212 INVALID_HW_RING_ID);
5213 ring->fw_ring_id = INVALID_HW_RING_ID;
5214 bp->grp_info[grp_idx].agg_fw_ring_id =
5219 /* The completion rings are about to be freed. After that the
5220 * IRQ doorbell will not work anymore. So we need to disable
5223 bnxt_disable_int_sync(bp);
5225 if (bp->flags & BNXT_FLAG_CHIP_P5)
5226 type = RING_FREE_REQ_RING_TYPE_NQ;
5228 type = RING_FREE_REQ_RING_TYPE_L2_CMPL;
5229 for (i = 0; i < bp->cp_nr_rings; i++) {
5230 struct bnxt_napi *bnapi = bp->bnapi[i];
5231 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
5232 struct bnxt_ring_struct *ring;
5235 for (j = 0; j < 2; j++) {
5236 struct bnxt_cp_ring_info *cpr2 = cpr->cp_ring_arr[j];
5239 ring = &cpr2->cp_ring_struct;
5240 if (ring->fw_ring_id == INVALID_HW_RING_ID)
5242 hwrm_ring_free_send_msg(bp, ring,
5243 RING_FREE_REQ_RING_TYPE_L2_CMPL,
5244 INVALID_HW_RING_ID);
5245 ring->fw_ring_id = INVALID_HW_RING_ID;
5248 ring = &cpr->cp_ring_struct;
5249 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
5250 hwrm_ring_free_send_msg(bp, ring, type,
5251 INVALID_HW_RING_ID);
5252 ring->fw_ring_id = INVALID_HW_RING_ID;
5253 bp->grp_info[i].cp_fw_ring_id = INVALID_HW_RING_ID;
5258 static int bnxt_trim_rings(struct bnxt *bp, int *rx, int *tx, int max,
5261 static int bnxt_hwrm_get_rings(struct bnxt *bp)
5263 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
5264 struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
5265 struct hwrm_func_qcfg_input req = {0};
5268 if (bp->hwrm_spec_code < 0x10601)
5271 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCFG, -1, -1);
5272 req.fid = cpu_to_le16(0xffff);
5273 mutex_lock(&bp->hwrm_cmd_lock);
5274 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5276 mutex_unlock(&bp->hwrm_cmd_lock);
5280 hw_resc->resv_tx_rings = le16_to_cpu(resp->alloc_tx_rings);
5281 if (BNXT_NEW_RM(bp)) {
5284 hw_resc->resv_rx_rings = le16_to_cpu(resp->alloc_rx_rings);
5285 hw_resc->resv_hw_ring_grps =
5286 le32_to_cpu(resp->alloc_hw_ring_grps);
5287 hw_resc->resv_vnics = le16_to_cpu(resp->alloc_vnics);
5288 cp = le16_to_cpu(resp->alloc_cmpl_rings);
5289 stats = le16_to_cpu(resp->alloc_stat_ctx);
5290 hw_resc->resv_irqs = cp;
5291 if (bp->flags & BNXT_FLAG_CHIP_P5) {
5292 int rx = hw_resc->resv_rx_rings;
5293 int tx = hw_resc->resv_tx_rings;
5295 if (bp->flags & BNXT_FLAG_AGG_RINGS)
5297 if (cp < (rx + tx)) {
5298 bnxt_trim_rings(bp, &rx, &tx, cp, false);
5299 if (bp->flags & BNXT_FLAG_AGG_RINGS)
5301 hw_resc->resv_rx_rings = rx;
5302 hw_resc->resv_tx_rings = tx;
5304 hw_resc->resv_irqs = le16_to_cpu(resp->alloc_msix);
5305 hw_resc->resv_hw_ring_grps = rx;
5307 hw_resc->resv_cp_rings = cp;
5308 hw_resc->resv_stat_ctxs = stats;
5310 mutex_unlock(&bp->hwrm_cmd_lock);
5314 /* Caller must hold bp->hwrm_cmd_lock */
5315 int __bnxt_hwrm_get_tx_rings(struct bnxt *bp, u16 fid, int *tx_rings)
5317 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
5318 struct hwrm_func_qcfg_input req = {0};
5321 if (bp->hwrm_spec_code < 0x10601)
5324 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCFG, -1, -1);
5325 req.fid = cpu_to_le16(fid);
5326 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5328 *tx_rings = le16_to_cpu(resp->alloc_tx_rings);
5333 static bool bnxt_rfs_supported(struct bnxt *bp);
5336 __bnxt_hwrm_reserve_pf_rings(struct bnxt *bp, struct hwrm_func_cfg_input *req,
5337 int tx_rings, int rx_rings, int ring_grps,
5338 int cp_rings, int stats, int vnics)
5342 bnxt_hwrm_cmd_hdr_init(bp, req, HWRM_FUNC_CFG, -1, -1);
5343 req->fid = cpu_to_le16(0xffff);
5344 enables |= tx_rings ? FUNC_CFG_REQ_ENABLES_NUM_TX_RINGS : 0;
5345 req->num_tx_rings = cpu_to_le16(tx_rings);
5346 if (BNXT_NEW_RM(bp)) {
5347 enables |= rx_rings ? FUNC_CFG_REQ_ENABLES_NUM_RX_RINGS : 0;
5348 enables |= stats ? FUNC_CFG_REQ_ENABLES_NUM_STAT_CTXS : 0;
5349 if (bp->flags & BNXT_FLAG_CHIP_P5) {
5350 enables |= cp_rings ? FUNC_CFG_REQ_ENABLES_NUM_MSIX : 0;
5351 enables |= tx_rings + ring_grps ?
5352 FUNC_CFG_REQ_ENABLES_NUM_CMPL_RINGS : 0;
5353 enables |= rx_rings ?
5354 FUNC_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS : 0;
5356 enables |= cp_rings ?
5357 FUNC_CFG_REQ_ENABLES_NUM_CMPL_RINGS : 0;
5358 enables |= ring_grps ?
5359 FUNC_CFG_REQ_ENABLES_NUM_HW_RING_GRPS |
5360 FUNC_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS : 0;
5362 enables |= vnics ? FUNC_CFG_REQ_ENABLES_NUM_VNICS : 0;
5364 req->num_rx_rings = cpu_to_le16(rx_rings);
5365 if (bp->flags & BNXT_FLAG_CHIP_P5) {
5366 req->num_cmpl_rings = cpu_to_le16(tx_rings + ring_grps);
5367 req->num_msix = cpu_to_le16(cp_rings);
5368 req->num_rsscos_ctxs =
5369 cpu_to_le16(DIV_ROUND_UP(ring_grps, 64));
5371 req->num_cmpl_rings = cpu_to_le16(cp_rings);
5372 req->num_hw_ring_grps = cpu_to_le16(ring_grps);
5373 req->num_rsscos_ctxs = cpu_to_le16(1);
5374 if (!(bp->flags & BNXT_FLAG_NEW_RSS_CAP) &&
5375 bnxt_rfs_supported(bp))
5376 req->num_rsscos_ctxs =
5377 cpu_to_le16(ring_grps + 1);
5379 req->num_stat_ctxs = cpu_to_le16(stats);
5380 req->num_vnics = cpu_to_le16(vnics);
5382 req->enables = cpu_to_le32(enables);
5386 __bnxt_hwrm_reserve_vf_rings(struct bnxt *bp,
5387 struct hwrm_func_vf_cfg_input *req, int tx_rings,
5388 int rx_rings, int ring_grps, int cp_rings,
5389 int stats, int vnics)
5393 bnxt_hwrm_cmd_hdr_init(bp, req, HWRM_FUNC_VF_CFG, -1, -1);
5394 enables |= tx_rings ? FUNC_VF_CFG_REQ_ENABLES_NUM_TX_RINGS : 0;
5395 enables |= rx_rings ? FUNC_VF_CFG_REQ_ENABLES_NUM_RX_RINGS |
5396 FUNC_VF_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS : 0;
5397 enables |= stats ? FUNC_VF_CFG_REQ_ENABLES_NUM_STAT_CTXS : 0;
5398 if (bp->flags & BNXT_FLAG_CHIP_P5) {
5399 enables |= tx_rings + ring_grps ?
5400 FUNC_VF_CFG_REQ_ENABLES_NUM_CMPL_RINGS : 0;
5402 enables |= cp_rings ?
5403 FUNC_VF_CFG_REQ_ENABLES_NUM_CMPL_RINGS : 0;
5404 enables |= ring_grps ?
5405 FUNC_VF_CFG_REQ_ENABLES_NUM_HW_RING_GRPS : 0;
5407 enables |= vnics ? FUNC_VF_CFG_REQ_ENABLES_NUM_VNICS : 0;
5408 enables |= FUNC_VF_CFG_REQ_ENABLES_NUM_L2_CTXS;
5410 req->num_l2_ctxs = cpu_to_le16(BNXT_VF_MAX_L2_CTX);
5411 req->num_tx_rings = cpu_to_le16(tx_rings);
5412 req->num_rx_rings = cpu_to_le16(rx_rings);
5413 if (bp->flags & BNXT_FLAG_CHIP_P5) {
5414 req->num_cmpl_rings = cpu_to_le16(tx_rings + ring_grps);
5415 req->num_rsscos_ctxs = cpu_to_le16(DIV_ROUND_UP(ring_grps, 64));
5417 req->num_cmpl_rings = cpu_to_le16(cp_rings);
5418 req->num_hw_ring_grps = cpu_to_le16(ring_grps);
5419 req->num_rsscos_ctxs = cpu_to_le16(BNXT_VF_MAX_RSS_CTX);
5421 req->num_stat_ctxs = cpu_to_le16(stats);
5422 req->num_vnics = cpu_to_le16(vnics);
5424 req->enables = cpu_to_le32(enables);
5428 bnxt_hwrm_reserve_pf_rings(struct bnxt *bp, int tx_rings, int rx_rings,
5429 int ring_grps, int cp_rings, int stats, int vnics)
5431 struct hwrm_func_cfg_input req = {0};
5434 __bnxt_hwrm_reserve_pf_rings(bp, &req, tx_rings, rx_rings, ring_grps,
5435 cp_rings, stats, vnics);
5439 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5443 if (bp->hwrm_spec_code < 0x10601)
5444 bp->hw_resc.resv_tx_rings = tx_rings;
5446 rc = bnxt_hwrm_get_rings(bp);
5451 bnxt_hwrm_reserve_vf_rings(struct bnxt *bp, int tx_rings, int rx_rings,
5452 int ring_grps, int cp_rings, int stats, int vnics)
5454 struct hwrm_func_vf_cfg_input req = {0};
5457 if (!BNXT_NEW_RM(bp)) {
5458 bp->hw_resc.resv_tx_rings = tx_rings;
5462 __bnxt_hwrm_reserve_vf_rings(bp, &req, tx_rings, rx_rings, ring_grps,
5463 cp_rings, stats, vnics);
5464 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5468 rc = bnxt_hwrm_get_rings(bp);
5472 static int bnxt_hwrm_reserve_rings(struct bnxt *bp, int tx, int rx, int grp,
5473 int cp, int stat, int vnic)
5476 return bnxt_hwrm_reserve_pf_rings(bp, tx, rx, grp, cp, stat,
5479 return bnxt_hwrm_reserve_vf_rings(bp, tx, rx, grp, cp, stat,
5483 int bnxt_nq_rings_in_use(struct bnxt *bp)
5485 int cp = bp->cp_nr_rings;
5486 int ulp_msix, ulp_base;
5488 ulp_msix = bnxt_get_ulp_msix_num(bp);
5490 ulp_base = bnxt_get_ulp_msix_base(bp);
5492 if ((ulp_base + ulp_msix) > cp)
5493 cp = ulp_base + ulp_msix;
5498 static int bnxt_cp_rings_in_use(struct bnxt *bp)
5502 if (!(bp->flags & BNXT_FLAG_CHIP_P5))
5503 return bnxt_nq_rings_in_use(bp);
5505 cp = bp->tx_nr_rings + bp->rx_nr_rings;
5509 static int bnxt_get_func_stat_ctxs(struct bnxt *bp)
5511 return bp->cp_nr_rings + bnxt_get_ulp_stat_ctxs(bp);
5514 static bool bnxt_need_reserve_rings(struct bnxt *bp)
5516 struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
5517 int cp = bnxt_cp_rings_in_use(bp);
5518 int nq = bnxt_nq_rings_in_use(bp);
5519 int rx = bp->rx_nr_rings, stat;
5520 int vnic = 1, grp = rx;
5522 if (bp->hwrm_spec_code < 0x10601)
5525 if (hw_resc->resv_tx_rings != bp->tx_nr_rings)
5528 if ((bp->flags & BNXT_FLAG_RFS) && !(bp->flags & BNXT_FLAG_CHIP_P5))
5530 if (bp->flags & BNXT_FLAG_AGG_RINGS)
5532 stat = bnxt_get_func_stat_ctxs(bp);
5533 if (BNXT_NEW_RM(bp) &&
5534 (hw_resc->resv_rx_rings != rx || hw_resc->resv_cp_rings != cp ||
5535 hw_resc->resv_vnics != vnic || hw_resc->resv_stat_ctxs != stat ||
5536 (hw_resc->resv_hw_ring_grps != grp &&
5537 !(bp->flags & BNXT_FLAG_CHIP_P5))))
5539 if ((bp->flags & BNXT_FLAG_CHIP_P5) && BNXT_PF(bp) &&
5540 hw_resc->resv_irqs != nq)
5545 static int __bnxt_reserve_rings(struct bnxt *bp)
5547 struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
5548 int cp = bnxt_nq_rings_in_use(bp);
5549 int tx = bp->tx_nr_rings;
5550 int rx = bp->rx_nr_rings;
5551 int grp, rx_rings, rc;
5555 if (!bnxt_need_reserve_rings(bp))
5558 if (bp->flags & BNXT_FLAG_SHARED_RINGS)
5560 if ((bp->flags & BNXT_FLAG_RFS) && !(bp->flags & BNXT_FLAG_CHIP_P5))
5562 if (bp->flags & BNXT_FLAG_AGG_RINGS)
5564 grp = bp->rx_nr_rings;
5565 stat = bnxt_get_func_stat_ctxs(bp);
5567 rc = bnxt_hwrm_reserve_rings(bp, tx, rx, grp, cp, stat, vnic);
5571 tx = hw_resc->resv_tx_rings;
5572 if (BNXT_NEW_RM(bp)) {
5573 rx = hw_resc->resv_rx_rings;
5574 cp = hw_resc->resv_irqs;
5575 grp = hw_resc->resv_hw_ring_grps;
5576 vnic = hw_resc->resv_vnics;
5577 stat = hw_resc->resv_stat_ctxs;
5581 if (bp->flags & BNXT_FLAG_AGG_RINGS) {
5585 if (netif_running(bp->dev))
5588 bp->flags &= ~BNXT_FLAG_AGG_RINGS;
5589 bp->flags |= BNXT_FLAG_NO_AGG_RINGS;
5590 bp->dev->hw_features &= ~NETIF_F_LRO;
5591 bp->dev->features &= ~NETIF_F_LRO;
5592 bnxt_set_ring_params(bp);
5595 rx_rings = min_t(int, rx_rings, grp);
5596 cp = min_t(int, cp, bp->cp_nr_rings);
5597 if (stat > bnxt_get_ulp_stat_ctxs(bp))
5598 stat -= bnxt_get_ulp_stat_ctxs(bp);
5599 cp = min_t(int, cp, stat);
5600 rc = bnxt_trim_rings(bp, &rx_rings, &tx, cp, sh);
5601 if (bp->flags & BNXT_FLAG_AGG_RINGS)
5603 cp = sh ? max_t(int, tx, rx_rings) : tx + rx_rings;
5604 bp->tx_nr_rings = tx;
5605 bp->rx_nr_rings = rx_rings;
5606 bp->cp_nr_rings = cp;
5608 if (!tx || !rx || !cp || !grp || !vnic || !stat)
5614 static int bnxt_hwrm_check_vf_rings(struct bnxt *bp, int tx_rings, int rx_rings,
5615 int ring_grps, int cp_rings, int stats,
5618 struct hwrm_func_vf_cfg_input req = {0};
5622 if (!BNXT_NEW_RM(bp))
5625 __bnxt_hwrm_reserve_vf_rings(bp, &req, tx_rings, rx_rings, ring_grps,
5626 cp_rings, stats, vnics);
5627 flags = FUNC_VF_CFG_REQ_FLAGS_TX_ASSETS_TEST |
5628 FUNC_VF_CFG_REQ_FLAGS_RX_ASSETS_TEST |
5629 FUNC_VF_CFG_REQ_FLAGS_CMPL_ASSETS_TEST |
5630 FUNC_VF_CFG_REQ_FLAGS_STAT_CTX_ASSETS_TEST |
5631 FUNC_VF_CFG_REQ_FLAGS_VNIC_ASSETS_TEST |
5632 FUNC_VF_CFG_REQ_FLAGS_RSSCOS_CTX_ASSETS_TEST;
5633 if (!(bp->flags & BNXT_FLAG_CHIP_P5))
5634 flags |= FUNC_VF_CFG_REQ_FLAGS_RING_GRP_ASSETS_TEST;
5636 req.flags = cpu_to_le32(flags);
5637 rc = hwrm_send_message_silent(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5643 static int bnxt_hwrm_check_pf_rings(struct bnxt *bp, int tx_rings, int rx_rings,
5644 int ring_grps, int cp_rings, int stats,
5647 struct hwrm_func_cfg_input req = {0};
5651 __bnxt_hwrm_reserve_pf_rings(bp, &req, tx_rings, rx_rings, ring_grps,
5652 cp_rings, stats, vnics);
5653 flags = FUNC_CFG_REQ_FLAGS_TX_ASSETS_TEST;
5654 if (BNXT_NEW_RM(bp)) {
5655 flags |= FUNC_CFG_REQ_FLAGS_RX_ASSETS_TEST |
5656 FUNC_CFG_REQ_FLAGS_CMPL_ASSETS_TEST |
5657 FUNC_CFG_REQ_FLAGS_STAT_CTX_ASSETS_TEST |
5658 FUNC_CFG_REQ_FLAGS_VNIC_ASSETS_TEST;
5659 if (bp->flags & BNXT_FLAG_CHIP_P5)
5660 flags |= FUNC_CFG_REQ_FLAGS_RSSCOS_CTX_ASSETS_TEST |
5661 FUNC_CFG_REQ_FLAGS_NQ_ASSETS_TEST;
5663 flags |= FUNC_CFG_REQ_FLAGS_RING_GRP_ASSETS_TEST;
5666 req.flags = cpu_to_le32(flags);
5667 rc = hwrm_send_message_silent(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5673 static int bnxt_hwrm_check_rings(struct bnxt *bp, int tx_rings, int rx_rings,
5674 int ring_grps, int cp_rings, int stats,
5677 if (bp->hwrm_spec_code < 0x10801)
5681 return bnxt_hwrm_check_pf_rings(bp, tx_rings, rx_rings,
5682 ring_grps, cp_rings, stats,
5685 return bnxt_hwrm_check_vf_rings(bp, tx_rings, rx_rings, ring_grps,
5686 cp_rings, stats, vnics);
5689 static void bnxt_hwrm_coal_params_qcaps(struct bnxt *bp)
5691 struct hwrm_ring_aggint_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
5692 struct bnxt_coal_cap *coal_cap = &bp->coal_cap;
5693 struct hwrm_ring_aggint_qcaps_input req = {0};
5696 coal_cap->cmpl_params = BNXT_LEGACY_COAL_CMPL_PARAMS;
5697 coal_cap->num_cmpl_dma_aggr_max = 63;
5698 coal_cap->num_cmpl_dma_aggr_during_int_max = 63;
5699 coal_cap->cmpl_aggr_dma_tmr_max = 65535;
5700 coal_cap->cmpl_aggr_dma_tmr_during_int_max = 65535;
5701 coal_cap->int_lat_tmr_min_max = 65535;
5702 coal_cap->int_lat_tmr_max_max = 65535;
5703 coal_cap->num_cmpl_aggr_int_max = 65535;
5704 coal_cap->timer_units = 80;
5706 if (bp->hwrm_spec_code < 0x10902)
5709 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_AGGINT_QCAPS, -1, -1);
5710 mutex_lock(&bp->hwrm_cmd_lock);
5711 rc = _hwrm_send_message_silent(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5713 coal_cap->cmpl_params = le32_to_cpu(resp->cmpl_params);
5714 coal_cap->nq_params = le32_to_cpu(resp->nq_params);
5715 coal_cap->num_cmpl_dma_aggr_max =
5716 le16_to_cpu(resp->num_cmpl_dma_aggr_max);
5717 coal_cap->num_cmpl_dma_aggr_during_int_max =
5718 le16_to_cpu(resp->num_cmpl_dma_aggr_during_int_max);
5719 coal_cap->cmpl_aggr_dma_tmr_max =
5720 le16_to_cpu(resp->cmpl_aggr_dma_tmr_max);
5721 coal_cap->cmpl_aggr_dma_tmr_during_int_max =
5722 le16_to_cpu(resp->cmpl_aggr_dma_tmr_during_int_max);
5723 coal_cap->int_lat_tmr_min_max =
5724 le16_to_cpu(resp->int_lat_tmr_min_max);
5725 coal_cap->int_lat_tmr_max_max =
5726 le16_to_cpu(resp->int_lat_tmr_max_max);
5727 coal_cap->num_cmpl_aggr_int_max =
5728 le16_to_cpu(resp->num_cmpl_aggr_int_max);
5729 coal_cap->timer_units = le16_to_cpu(resp->timer_units);
5731 mutex_unlock(&bp->hwrm_cmd_lock);
5734 static u16 bnxt_usec_to_coal_tmr(struct bnxt *bp, u16 usec)
5736 struct bnxt_coal_cap *coal_cap = &bp->coal_cap;
5738 return usec * 1000 / coal_cap->timer_units;
5741 static void bnxt_hwrm_set_coal_params(struct bnxt *bp,
5742 struct bnxt_coal *hw_coal,
5743 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *req)
5745 struct bnxt_coal_cap *coal_cap = &bp->coal_cap;
5746 u32 cmpl_params = coal_cap->cmpl_params;
5747 u16 val, tmr, max, flags = 0;
5749 max = hw_coal->bufs_per_record * 128;
5750 if (hw_coal->budget)
5751 max = hw_coal->bufs_per_record * hw_coal->budget;
5752 max = min_t(u16, max, coal_cap->num_cmpl_aggr_int_max);
5754 val = clamp_t(u16, hw_coal->coal_bufs, 1, max);
5755 req->num_cmpl_aggr_int = cpu_to_le16(val);
5757 val = min_t(u16, val, coal_cap->num_cmpl_dma_aggr_max);
5758 req->num_cmpl_dma_aggr = cpu_to_le16(val);
5760 val = clamp_t(u16, hw_coal->coal_bufs_irq, 1,
5761 coal_cap->num_cmpl_dma_aggr_during_int_max);
5762 req->num_cmpl_dma_aggr_during_int = cpu_to_le16(val);
5764 tmr = bnxt_usec_to_coal_tmr(bp, hw_coal->coal_ticks);
5765 tmr = clamp_t(u16, tmr, 1, coal_cap->int_lat_tmr_max_max);
5766 req->int_lat_tmr_max = cpu_to_le16(tmr);
5768 /* min timer set to 1/2 of interrupt timer */
5769 if (cmpl_params & RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_INT_LAT_TMR_MIN) {
5771 val = clamp_t(u16, val, 1, coal_cap->int_lat_tmr_min_max);
5772 req->int_lat_tmr_min = cpu_to_le16(val);
5773 req->enables |= cpu_to_le16(BNXT_COAL_CMPL_MIN_TMR_ENABLE);
5776 /* buf timer set to 1/4 of interrupt timer */
5777 val = clamp_t(u16, tmr / 4, 1, coal_cap->cmpl_aggr_dma_tmr_max);
5778 req->cmpl_aggr_dma_tmr = cpu_to_le16(val);
5781 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_DMA_AGGR_DURING_INT) {
5782 tmr = bnxt_usec_to_coal_tmr(bp, hw_coal->coal_ticks_irq);
5783 val = clamp_t(u16, tmr, 1,
5784 coal_cap->cmpl_aggr_dma_tmr_during_int_max);
5785 req->cmpl_aggr_dma_tmr_during_int = cpu_to_le16(tmr);
5787 cpu_to_le16(BNXT_COAL_CMPL_AGGR_TMR_DURING_INT_ENABLE);
5790 if (cmpl_params & RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_TIMER_RESET)
5791 flags |= RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET;
5792 if ((cmpl_params & RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_RING_IDLE) &&
5793 hw_coal->idle_thresh && hw_coal->coal_ticks < hw_coal->idle_thresh)
5794 flags |= RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_RING_IDLE;
5795 req->flags = cpu_to_le16(flags);
5796 req->enables |= cpu_to_le16(BNXT_COAL_CMPL_ENABLES);
5799 /* Caller holds bp->hwrm_cmd_lock */
5800 static int __bnxt_hwrm_set_coal_nq(struct bnxt *bp, struct bnxt_napi *bnapi,
5801 struct bnxt_coal *hw_coal)
5803 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req = {0};
5804 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
5805 struct bnxt_coal_cap *coal_cap = &bp->coal_cap;
5806 u32 nq_params = coal_cap->nq_params;
5809 if (!(nq_params & RING_AGGINT_QCAPS_RESP_NQ_PARAMS_INT_LAT_TMR_MIN))
5812 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS,
5814 req.ring_id = cpu_to_le16(cpr->cp_ring_struct.fw_ring_id);
5816 cpu_to_le16(RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_IS_NQ);
5818 tmr = bnxt_usec_to_coal_tmr(bp, hw_coal->coal_ticks) / 2;
5819 tmr = clamp_t(u16, tmr, 1, coal_cap->int_lat_tmr_min_max);
5820 req.int_lat_tmr_min = cpu_to_le16(tmr);
5821 req.enables |= cpu_to_le16(BNXT_COAL_CMPL_MIN_TMR_ENABLE);
5822 return _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5825 int bnxt_hwrm_set_ring_coal(struct bnxt *bp, struct bnxt_napi *bnapi)
5827 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req_rx = {0};
5828 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
5829 struct bnxt_coal coal;
5831 /* Tick values in micro seconds.
5832 * 1 coal_buf x bufs_per_record = 1 completion record.
5834 memcpy(&coal, &bp->rx_coal, sizeof(struct bnxt_coal));
5836 coal.coal_ticks = cpr->rx_ring_coal.coal_ticks;
5837 coal.coal_bufs = cpr->rx_ring_coal.coal_bufs;
5839 if (!bnapi->rx_ring)
5842 bnxt_hwrm_cmd_hdr_init(bp, &req_rx,
5843 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS, -1, -1);
5845 bnxt_hwrm_set_coal_params(bp, &coal, &req_rx);
5847 req_rx.ring_id = cpu_to_le16(bnxt_cp_ring_for_rx(bp, bnapi->rx_ring));
5849 return hwrm_send_message(bp, &req_rx, sizeof(req_rx),
5853 int bnxt_hwrm_set_coal(struct bnxt *bp)
5856 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req_rx = {0},
5859 bnxt_hwrm_cmd_hdr_init(bp, &req_rx,
5860 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS, -1, -1);
5861 bnxt_hwrm_cmd_hdr_init(bp, &req_tx,
5862 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS, -1, -1);
5864 bnxt_hwrm_set_coal_params(bp, &bp->rx_coal, &req_rx);
5865 bnxt_hwrm_set_coal_params(bp, &bp->tx_coal, &req_tx);
5867 mutex_lock(&bp->hwrm_cmd_lock);
5868 for (i = 0; i < bp->cp_nr_rings; i++) {
5869 struct bnxt_napi *bnapi = bp->bnapi[i];
5870 struct bnxt_coal *hw_coal;
5874 if (!bnapi->rx_ring) {
5875 ring_id = bnxt_cp_ring_for_tx(bp, bnapi->tx_ring);
5878 ring_id = bnxt_cp_ring_for_rx(bp, bnapi->rx_ring);
5880 req->ring_id = cpu_to_le16(ring_id);
5882 rc = _hwrm_send_message(bp, req, sizeof(*req),
5887 if (!(bp->flags & BNXT_FLAG_CHIP_P5))
5890 if (bnapi->rx_ring && bnapi->tx_ring) {
5892 ring_id = bnxt_cp_ring_for_tx(bp, bnapi->tx_ring);
5893 req->ring_id = cpu_to_le16(ring_id);
5894 rc = _hwrm_send_message(bp, req, sizeof(*req),
5900 hw_coal = &bp->rx_coal;
5902 hw_coal = &bp->tx_coal;
5903 __bnxt_hwrm_set_coal_nq(bp, bnapi, hw_coal);
5905 mutex_unlock(&bp->hwrm_cmd_lock);
5909 static int bnxt_hwrm_stat_ctx_free(struct bnxt *bp)
5912 struct hwrm_stat_ctx_free_input req = {0};
5917 if (BNXT_CHIP_TYPE_NITRO_A0(bp))
5920 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_STAT_CTX_FREE, -1, -1);
5922 mutex_lock(&bp->hwrm_cmd_lock);
5923 for (i = 0; i < bp->cp_nr_rings; i++) {
5924 struct bnxt_napi *bnapi = bp->bnapi[i];
5925 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
5927 if (cpr->hw_stats_ctx_id != INVALID_STATS_CTX_ID) {
5928 req.stat_ctx_id = cpu_to_le32(cpr->hw_stats_ctx_id);
5930 rc = _hwrm_send_message(bp, &req, sizeof(req),
5935 cpr->hw_stats_ctx_id = INVALID_STATS_CTX_ID;
5938 mutex_unlock(&bp->hwrm_cmd_lock);
5942 static int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp)
5945 struct hwrm_stat_ctx_alloc_input req = {0};
5946 struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;
5948 if (BNXT_CHIP_TYPE_NITRO_A0(bp))
5951 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_STAT_CTX_ALLOC, -1, -1);
5953 req.update_period_ms = cpu_to_le32(bp->stats_coal_ticks / 1000);
5955 mutex_lock(&bp->hwrm_cmd_lock);
5956 for (i = 0; i < bp->cp_nr_rings; i++) {
5957 struct bnxt_napi *bnapi = bp->bnapi[i];
5958 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
5960 req.stats_dma_addr = cpu_to_le64(cpr->hw_stats_map);
5962 rc = _hwrm_send_message(bp, &req, sizeof(req),
5967 cpr->hw_stats_ctx_id = le32_to_cpu(resp->stat_ctx_id);
5969 bp->grp_info[i].fw_stats_ctx = cpr->hw_stats_ctx_id;
5971 mutex_unlock(&bp->hwrm_cmd_lock);
5975 static int bnxt_hwrm_func_qcfg(struct bnxt *bp)
5977 struct hwrm_func_qcfg_input req = {0};
5978 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
5982 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCFG, -1, -1);
5983 req.fid = cpu_to_le16(0xffff);
5984 mutex_lock(&bp->hwrm_cmd_lock);
5985 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5987 goto func_qcfg_exit;
5989 #ifdef CONFIG_BNXT_SRIOV
5991 struct bnxt_vf_info *vf = &bp->vf;
5993 vf->vlan = le16_to_cpu(resp->vlan) & VLAN_VID_MASK;
5996 flags = le16_to_cpu(resp->flags);
5997 if (flags & (FUNC_QCFG_RESP_FLAGS_FW_DCBX_AGENT_ENABLED |
5998 FUNC_QCFG_RESP_FLAGS_FW_LLDP_AGENT_ENABLED)) {
5999 bp->fw_cap |= BNXT_FW_CAP_LLDP_AGENT;
6000 if (flags & FUNC_QCFG_RESP_FLAGS_FW_DCBX_AGENT_ENABLED)
6001 bp->fw_cap |= BNXT_FW_CAP_DCBX_AGENT;
6003 if (BNXT_PF(bp) && (flags & FUNC_QCFG_RESP_FLAGS_MULTI_HOST))
6004 bp->flags |= BNXT_FLAG_MULTI_HOST;
6006 switch (resp->port_partition_type) {
6007 case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_0:
6008 case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_5:
6009 case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR2_0:
6010 bp->port_partition_type = resp->port_partition_type;
6013 if (bp->hwrm_spec_code < 0x10707 ||
6014 resp->evb_mode == FUNC_QCFG_RESP_EVB_MODE_VEB)
6015 bp->br_mode = BRIDGE_MODE_VEB;
6016 else if (resp->evb_mode == FUNC_QCFG_RESP_EVB_MODE_VEPA)
6017 bp->br_mode = BRIDGE_MODE_VEPA;
6019 bp->br_mode = BRIDGE_MODE_UNDEF;
6021 bp->max_mtu = le16_to_cpu(resp->max_mtu_configured);
6023 bp->max_mtu = BNXT_MAX_MTU;
6026 mutex_unlock(&bp->hwrm_cmd_lock);
6030 static int bnxt_hwrm_func_backing_store_qcaps(struct bnxt *bp)
6032 struct hwrm_func_backing_store_qcaps_input req = {0};
6033 struct hwrm_func_backing_store_qcaps_output *resp =
6034 bp->hwrm_cmd_resp_addr;
6037 if (bp->hwrm_spec_code < 0x10902 || BNXT_VF(bp) || bp->ctx)
6040 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_BACKING_STORE_QCAPS, -1, -1);
6041 mutex_lock(&bp->hwrm_cmd_lock);
6042 rc = _hwrm_send_message_silent(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6044 struct bnxt_ctx_pg_info *ctx_pg;
6045 struct bnxt_ctx_mem_info *ctx;
6048 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
6053 ctx_pg = kzalloc(sizeof(*ctx_pg) * (bp->max_q + 1), GFP_KERNEL);
6059 for (i = 0; i < bp->max_q + 1; i++, ctx_pg++)
6060 ctx->tqm_mem[i] = ctx_pg;
6063 ctx->qp_max_entries = le32_to_cpu(resp->qp_max_entries);
6064 ctx->qp_min_qp1_entries = le16_to_cpu(resp->qp_min_qp1_entries);
6065 ctx->qp_max_l2_entries = le16_to_cpu(resp->qp_max_l2_entries);
6066 ctx->qp_entry_size = le16_to_cpu(resp->qp_entry_size);
6067 ctx->srq_max_l2_entries = le16_to_cpu(resp->srq_max_l2_entries);
6068 ctx->srq_max_entries = le32_to_cpu(resp->srq_max_entries);
6069 ctx->srq_entry_size = le16_to_cpu(resp->srq_entry_size);
6070 ctx->cq_max_l2_entries = le16_to_cpu(resp->cq_max_l2_entries);
6071 ctx->cq_max_entries = le32_to_cpu(resp->cq_max_entries);
6072 ctx->cq_entry_size = le16_to_cpu(resp->cq_entry_size);
6073 ctx->vnic_max_vnic_entries =
6074 le16_to_cpu(resp->vnic_max_vnic_entries);
6075 ctx->vnic_max_ring_table_entries =
6076 le16_to_cpu(resp->vnic_max_ring_table_entries);
6077 ctx->vnic_entry_size = le16_to_cpu(resp->vnic_entry_size);
6078 ctx->stat_max_entries = le32_to_cpu(resp->stat_max_entries);
6079 ctx->stat_entry_size = le16_to_cpu(resp->stat_entry_size);
6080 ctx->tqm_entry_size = le16_to_cpu(resp->tqm_entry_size);
6081 ctx->tqm_min_entries_per_ring =
6082 le32_to_cpu(resp->tqm_min_entries_per_ring);
6083 ctx->tqm_max_entries_per_ring =
6084 le32_to_cpu(resp->tqm_max_entries_per_ring);
6085 ctx->tqm_entries_multiple = resp->tqm_entries_multiple;
6086 if (!ctx->tqm_entries_multiple)
6087 ctx->tqm_entries_multiple = 1;
6088 ctx->mrav_max_entries = le32_to_cpu(resp->mrav_max_entries);
6089 ctx->mrav_entry_size = le16_to_cpu(resp->mrav_entry_size);
6090 ctx->mrav_num_entries_units =
6091 le16_to_cpu(resp->mrav_num_entries_units);
6092 ctx->tim_entry_size = le16_to_cpu(resp->tim_entry_size);
6093 ctx->tim_max_entries = le32_to_cpu(resp->tim_max_entries);
6098 mutex_unlock(&bp->hwrm_cmd_lock);
6102 static void bnxt_hwrm_set_pg_attr(struct bnxt_ring_mem_info *rmem, u8 *pg_attr,
6107 if (BNXT_PAGE_SHIFT == 13)
6109 else if (BNXT_PAGE_SIZE == 16)
6113 if (rmem->depth >= 1) {
6114 if (rmem->depth == 2)
6118 *pg_dir = cpu_to_le64(rmem->pg_tbl_map);
6120 *pg_dir = cpu_to_le64(rmem->dma_arr[0]);
6124 #define FUNC_BACKING_STORE_CFG_REQ_DFLT_ENABLES \
6125 (FUNC_BACKING_STORE_CFG_REQ_ENABLES_QP | \
6126 FUNC_BACKING_STORE_CFG_REQ_ENABLES_SRQ | \
6127 FUNC_BACKING_STORE_CFG_REQ_ENABLES_CQ | \
6128 FUNC_BACKING_STORE_CFG_REQ_ENABLES_VNIC | \
6129 FUNC_BACKING_STORE_CFG_REQ_ENABLES_STAT)
6131 static int bnxt_hwrm_func_backing_store_cfg(struct bnxt *bp, u32 enables)
6133 struct hwrm_func_backing_store_cfg_input req = {0};
6134 struct bnxt_ctx_mem_info *ctx = bp->ctx;
6135 struct bnxt_ctx_pg_info *ctx_pg;
6136 __le32 *num_entries;
6146 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_BACKING_STORE_CFG, -1, -1);
6147 req.enables = cpu_to_le32(enables);
6149 if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_QP) {
6150 ctx_pg = &ctx->qp_mem;
6151 req.qp_num_entries = cpu_to_le32(ctx_pg->entries);
6152 req.qp_num_qp1_entries = cpu_to_le16(ctx->qp_min_qp1_entries);
6153 req.qp_num_l2_entries = cpu_to_le16(ctx->qp_max_l2_entries);
6154 req.qp_entry_size = cpu_to_le16(ctx->qp_entry_size);
6155 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
6156 &req.qpc_pg_size_qpc_lvl,
6159 if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_SRQ) {
6160 ctx_pg = &ctx->srq_mem;
6161 req.srq_num_entries = cpu_to_le32(ctx_pg->entries);
6162 req.srq_num_l2_entries = cpu_to_le16(ctx->srq_max_l2_entries);
6163 req.srq_entry_size = cpu_to_le16(ctx->srq_entry_size);
6164 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
6165 &req.srq_pg_size_srq_lvl,
6168 if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_CQ) {
6169 ctx_pg = &ctx->cq_mem;
6170 req.cq_num_entries = cpu_to_le32(ctx_pg->entries);
6171 req.cq_num_l2_entries = cpu_to_le16(ctx->cq_max_l2_entries);
6172 req.cq_entry_size = cpu_to_le16(ctx->cq_entry_size);
6173 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, &req.cq_pg_size_cq_lvl,
6176 if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_VNIC) {
6177 ctx_pg = &ctx->vnic_mem;
6178 req.vnic_num_vnic_entries =
6179 cpu_to_le16(ctx->vnic_max_vnic_entries);
6180 req.vnic_num_ring_table_entries =
6181 cpu_to_le16(ctx->vnic_max_ring_table_entries);
6182 req.vnic_entry_size = cpu_to_le16(ctx->vnic_entry_size);
6183 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
6184 &req.vnic_pg_size_vnic_lvl,
6185 &req.vnic_page_dir);
6187 if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_STAT) {
6188 ctx_pg = &ctx->stat_mem;
6189 req.stat_num_entries = cpu_to_le32(ctx->stat_max_entries);
6190 req.stat_entry_size = cpu_to_le16(ctx->stat_entry_size);
6191 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
6192 &req.stat_pg_size_stat_lvl,
6193 &req.stat_page_dir);
6195 if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_MRAV) {
6196 ctx_pg = &ctx->mrav_mem;
6197 req.mrav_num_entries = cpu_to_le32(ctx_pg->entries);
6198 if (ctx->mrav_num_entries_units)
6200 FUNC_BACKING_STORE_CFG_REQ_FLAGS_MRAV_RESERVATION_SPLIT;
6201 req.mrav_entry_size = cpu_to_le16(ctx->mrav_entry_size);
6202 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
6203 &req.mrav_pg_size_mrav_lvl,
6204 &req.mrav_page_dir);
6206 if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_TIM) {
6207 ctx_pg = &ctx->tim_mem;
6208 req.tim_num_entries = cpu_to_le32(ctx_pg->entries);
6209 req.tim_entry_size = cpu_to_le16(ctx->tim_entry_size);
6210 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
6211 &req.tim_pg_size_tim_lvl,
6214 for (i = 0, num_entries = &req.tqm_sp_num_entries,
6215 pg_attr = &req.tqm_sp_pg_size_tqm_sp_lvl,
6216 pg_dir = &req.tqm_sp_page_dir,
6217 ena = FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_SP;
6218 i < 9; i++, num_entries++, pg_attr++, pg_dir++, ena <<= 1) {
6219 if (!(enables & ena))
6222 req.tqm_entry_size = cpu_to_le16(ctx->tqm_entry_size);
6223 ctx_pg = ctx->tqm_mem[i];
6224 *num_entries = cpu_to_le32(ctx_pg->entries);
6225 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, pg_attr, pg_dir);
6227 req.flags = cpu_to_le32(flags);
6228 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6234 static int bnxt_alloc_ctx_mem_blk(struct bnxt *bp,
6235 struct bnxt_ctx_pg_info *ctx_pg)
6237 struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
6239 rmem->page_size = BNXT_PAGE_SIZE;
6240 rmem->pg_arr = ctx_pg->ctx_pg_arr;
6241 rmem->dma_arr = ctx_pg->ctx_dma_arr;
6242 rmem->flags = BNXT_RMEM_VALID_PTE_FLAG;
6243 if (rmem->depth >= 1)
6244 rmem->flags |= BNXT_RMEM_USE_FULL_PAGE_FLAG;
6245 return bnxt_alloc_ring(bp, rmem);
6248 static int bnxt_alloc_ctx_pg_tbls(struct bnxt *bp,
6249 struct bnxt_ctx_pg_info *ctx_pg, u32 mem_size,
6252 struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
6258 ctx_pg->nr_pages = DIV_ROUND_UP(mem_size, BNXT_PAGE_SIZE);
6259 if (ctx_pg->nr_pages > MAX_CTX_TOTAL_PAGES) {
6260 ctx_pg->nr_pages = 0;
6263 if (ctx_pg->nr_pages > MAX_CTX_PAGES || depth > 1) {
6267 ctx_pg->ctx_pg_tbl = kcalloc(MAX_CTX_PAGES, sizeof(ctx_pg),
6269 if (!ctx_pg->ctx_pg_tbl)
6271 nr_tbls = DIV_ROUND_UP(ctx_pg->nr_pages, MAX_CTX_PAGES);
6272 rmem->nr_pages = nr_tbls;
6273 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg);
6276 for (i = 0; i < nr_tbls; i++) {
6277 struct bnxt_ctx_pg_info *pg_tbl;
6279 pg_tbl = kzalloc(sizeof(*pg_tbl), GFP_KERNEL);
6282 ctx_pg->ctx_pg_tbl[i] = pg_tbl;
6283 rmem = &pg_tbl->ring_mem;
6284 rmem->pg_tbl = ctx_pg->ctx_pg_arr[i];
6285 rmem->pg_tbl_map = ctx_pg->ctx_dma_arr[i];
6287 rmem->nr_pages = MAX_CTX_PAGES;
6288 if (i == (nr_tbls - 1)) {
6289 int rem = ctx_pg->nr_pages % MAX_CTX_PAGES;
6292 rmem->nr_pages = rem;
6294 rc = bnxt_alloc_ctx_mem_blk(bp, pg_tbl);
6299 rmem->nr_pages = DIV_ROUND_UP(mem_size, BNXT_PAGE_SIZE);
6300 if (rmem->nr_pages > 1 || depth)
6302 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg);
6307 static void bnxt_free_ctx_pg_tbls(struct bnxt *bp,
6308 struct bnxt_ctx_pg_info *ctx_pg)
6310 struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
6312 if (rmem->depth > 1 || ctx_pg->nr_pages > MAX_CTX_PAGES ||
6313 ctx_pg->ctx_pg_tbl) {
6314 int i, nr_tbls = rmem->nr_pages;
6316 for (i = 0; i < nr_tbls; i++) {
6317 struct bnxt_ctx_pg_info *pg_tbl;
6318 struct bnxt_ring_mem_info *rmem2;
6320 pg_tbl = ctx_pg->ctx_pg_tbl[i];
6323 rmem2 = &pg_tbl->ring_mem;
6324 bnxt_free_ring(bp, rmem2);
6325 ctx_pg->ctx_pg_arr[i] = NULL;
6327 ctx_pg->ctx_pg_tbl[i] = NULL;
6329 kfree(ctx_pg->ctx_pg_tbl);
6330 ctx_pg->ctx_pg_tbl = NULL;
6332 bnxt_free_ring(bp, rmem);
6333 ctx_pg->nr_pages = 0;
6336 static void bnxt_free_ctx_mem(struct bnxt *bp)
6338 struct bnxt_ctx_mem_info *ctx = bp->ctx;
6344 if (ctx->tqm_mem[0]) {
6345 for (i = 0; i < bp->max_q + 1; i++)
6346 bnxt_free_ctx_pg_tbls(bp, ctx->tqm_mem[i]);
6347 kfree(ctx->tqm_mem[0]);
6348 ctx->tqm_mem[0] = NULL;
6351 bnxt_free_ctx_pg_tbls(bp, &ctx->tim_mem);
6352 bnxt_free_ctx_pg_tbls(bp, &ctx->mrav_mem);
6353 bnxt_free_ctx_pg_tbls(bp, &ctx->stat_mem);
6354 bnxt_free_ctx_pg_tbls(bp, &ctx->vnic_mem);
6355 bnxt_free_ctx_pg_tbls(bp, &ctx->cq_mem);
6356 bnxt_free_ctx_pg_tbls(bp, &ctx->srq_mem);
6357 bnxt_free_ctx_pg_tbls(bp, &ctx->qp_mem);
6358 ctx->flags &= ~BNXT_CTX_FLAG_INITED;
6361 static int bnxt_alloc_ctx_mem(struct bnxt *bp)
6363 struct bnxt_ctx_pg_info *ctx_pg;
6364 struct bnxt_ctx_mem_info *ctx;
6365 u32 mem_size, ena, entries;
6372 rc = bnxt_hwrm_func_backing_store_qcaps(bp);
6374 netdev_err(bp->dev, "Failed querying context mem capability, rc = %d.\n",
6379 if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED))
6382 if ((bp->flags & BNXT_FLAG_ROCE_CAP) && !is_kdump_kernel()) {
6388 ctx_pg = &ctx->qp_mem;
6389 ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries +
6391 mem_size = ctx->qp_entry_size * ctx_pg->entries;
6392 rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, pg_lvl);
6396 ctx_pg = &ctx->srq_mem;
6397 ctx_pg->entries = ctx->srq_max_l2_entries + extra_srqs;
6398 mem_size = ctx->srq_entry_size * ctx_pg->entries;
6399 rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, pg_lvl);
6403 ctx_pg = &ctx->cq_mem;
6404 ctx_pg->entries = ctx->cq_max_l2_entries + extra_qps * 2;
6405 mem_size = ctx->cq_entry_size * ctx_pg->entries;
6406 rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, pg_lvl);
6410 ctx_pg = &ctx->vnic_mem;
6411 ctx_pg->entries = ctx->vnic_max_vnic_entries +
6412 ctx->vnic_max_ring_table_entries;
6413 mem_size = ctx->vnic_entry_size * ctx_pg->entries;
6414 rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, 1);
6418 ctx_pg = &ctx->stat_mem;
6419 ctx_pg->entries = ctx->stat_max_entries;
6420 mem_size = ctx->stat_entry_size * ctx_pg->entries;
6421 rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, 1);
6426 if (!(bp->flags & BNXT_FLAG_ROCE_CAP))
6429 ctx_pg = &ctx->mrav_mem;
6430 /* 128K extra is needed to accommodate static AH context
6431 * allocation by f/w.
6433 num_mr = 1024 * 256;
6434 num_ah = 1024 * 128;
6435 ctx_pg->entries = num_mr + num_ah;
6436 mem_size = ctx->mrav_entry_size * ctx_pg->entries;
6437 rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, 2);
6440 ena = FUNC_BACKING_STORE_CFG_REQ_ENABLES_MRAV;
6441 if (ctx->mrav_num_entries_units)
6443 ((num_mr / ctx->mrav_num_entries_units) << 16) |
6444 (num_ah / ctx->mrav_num_entries_units);
6446 ctx_pg = &ctx->tim_mem;
6447 ctx_pg->entries = ctx->qp_mem.entries;
6448 mem_size = ctx->tim_entry_size * ctx_pg->entries;
6449 rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, 1);
6452 ena |= FUNC_BACKING_STORE_CFG_REQ_ENABLES_TIM;
6455 entries = ctx->qp_max_l2_entries + extra_qps;
6456 entries = roundup(entries, ctx->tqm_entries_multiple);
6457 entries = clamp_t(u32, entries, ctx->tqm_min_entries_per_ring,
6458 ctx->tqm_max_entries_per_ring);
6459 for (i = 0; i < bp->max_q + 1; i++) {
6460 ctx_pg = ctx->tqm_mem[i];
6461 ctx_pg->entries = entries;
6462 mem_size = ctx->tqm_entry_size * entries;
6463 rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, 1);
6466 ena |= FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_SP << i;
6468 ena |= FUNC_BACKING_STORE_CFG_REQ_DFLT_ENABLES;
6469 rc = bnxt_hwrm_func_backing_store_cfg(bp, ena);
6471 netdev_err(bp->dev, "Failed configuring context mem, rc = %d.\n",
6474 ctx->flags |= BNXT_CTX_FLAG_INITED;
6479 int bnxt_hwrm_func_resc_qcaps(struct bnxt *bp, bool all)
6481 struct hwrm_func_resource_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
6482 struct hwrm_func_resource_qcaps_input req = {0};
6483 struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
6486 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_RESOURCE_QCAPS, -1, -1);
6487 req.fid = cpu_to_le16(0xffff);
6489 mutex_lock(&bp->hwrm_cmd_lock);
6490 rc = _hwrm_send_message_silent(bp, &req, sizeof(req),
6494 goto hwrm_func_resc_qcaps_exit;
6497 hw_resc->max_tx_sch_inputs = le16_to_cpu(resp->max_tx_scheduler_inputs);
6499 goto hwrm_func_resc_qcaps_exit;
6501 hw_resc->min_rsscos_ctxs = le16_to_cpu(resp->min_rsscos_ctx);
6502 hw_resc->max_rsscos_ctxs = le16_to_cpu(resp->max_rsscos_ctx);
6503 hw_resc->min_cp_rings = le16_to_cpu(resp->min_cmpl_rings);
6504 hw_resc->max_cp_rings = le16_to_cpu(resp->max_cmpl_rings);
6505 hw_resc->min_tx_rings = le16_to_cpu(resp->min_tx_rings);
6506 hw_resc->max_tx_rings = le16_to_cpu(resp->max_tx_rings);
6507 hw_resc->min_rx_rings = le16_to_cpu(resp->min_rx_rings);
6508 hw_resc->max_rx_rings = le16_to_cpu(resp->max_rx_rings);
6509 hw_resc->min_hw_ring_grps = le16_to_cpu(resp->min_hw_ring_grps);
6510 hw_resc->max_hw_ring_grps = le16_to_cpu(resp->max_hw_ring_grps);
6511 hw_resc->min_l2_ctxs = le16_to_cpu(resp->min_l2_ctxs);
6512 hw_resc->max_l2_ctxs = le16_to_cpu(resp->max_l2_ctxs);
6513 hw_resc->min_vnics = le16_to_cpu(resp->min_vnics);
6514 hw_resc->max_vnics = le16_to_cpu(resp->max_vnics);
6515 hw_resc->min_stat_ctxs = le16_to_cpu(resp->min_stat_ctx);
6516 hw_resc->max_stat_ctxs = le16_to_cpu(resp->max_stat_ctx);
6518 if (bp->flags & BNXT_FLAG_CHIP_P5) {
6519 u16 max_msix = le16_to_cpu(resp->max_msix);
6521 hw_resc->max_nqs = max_msix;
6522 hw_resc->max_hw_ring_grps = hw_resc->max_rx_rings;
6526 struct bnxt_pf_info *pf = &bp->pf;
6528 pf->vf_resv_strategy =
6529 le16_to_cpu(resp->vf_reservation_strategy);
6530 if (pf->vf_resv_strategy > BNXT_VF_RESV_STRATEGY_MINIMAL_STATIC)
6531 pf->vf_resv_strategy = BNXT_VF_RESV_STRATEGY_MAXIMAL;
6533 hwrm_func_resc_qcaps_exit:
6534 mutex_unlock(&bp->hwrm_cmd_lock);
6538 static int __bnxt_hwrm_func_qcaps(struct bnxt *bp)
6541 struct hwrm_func_qcaps_input req = {0};
6542 struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
6543 struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
6546 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCAPS, -1, -1);
6547 req.fid = cpu_to_le16(0xffff);
6549 mutex_lock(&bp->hwrm_cmd_lock);
6550 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6552 goto hwrm_func_qcaps_exit;
6554 flags = le32_to_cpu(resp->flags);
6555 if (flags & FUNC_QCAPS_RESP_FLAGS_ROCE_V1_SUPPORTED)
6556 bp->flags |= BNXT_FLAG_ROCEV1_CAP;
6557 if (flags & FUNC_QCAPS_RESP_FLAGS_ROCE_V2_SUPPORTED)
6558 bp->flags |= BNXT_FLAG_ROCEV2_CAP;
6559 if (flags & FUNC_QCAPS_RESP_FLAGS_PCIE_STATS_SUPPORTED)
6560 bp->fw_cap |= BNXT_FW_CAP_PCIE_STATS_SUPPORTED;
6561 if (flags & FUNC_QCAPS_RESP_FLAGS_EXT_STATS_SUPPORTED)
6562 bp->fw_cap |= BNXT_FW_CAP_EXT_STATS_SUPPORTED;
6564 bp->tx_push_thresh = 0;
6565 if (flags & FUNC_QCAPS_RESP_FLAGS_PUSH_MODE_SUPPORTED)
6566 bp->tx_push_thresh = BNXT_TX_PUSH_THRESH;
6568 hw_resc->max_rsscos_ctxs = le16_to_cpu(resp->max_rsscos_ctx);
6569 hw_resc->max_cp_rings = le16_to_cpu(resp->max_cmpl_rings);
6570 hw_resc->max_tx_rings = le16_to_cpu(resp->max_tx_rings);
6571 hw_resc->max_rx_rings = le16_to_cpu(resp->max_rx_rings);
6572 hw_resc->max_hw_ring_grps = le32_to_cpu(resp->max_hw_ring_grps);
6573 if (!hw_resc->max_hw_ring_grps)
6574 hw_resc->max_hw_ring_grps = hw_resc->max_tx_rings;
6575 hw_resc->max_l2_ctxs = le16_to_cpu(resp->max_l2_ctxs);
6576 hw_resc->max_vnics = le16_to_cpu(resp->max_vnics);
6577 hw_resc->max_stat_ctxs = le16_to_cpu(resp->max_stat_ctx);
6580 struct bnxt_pf_info *pf = &bp->pf;
6582 pf->fw_fid = le16_to_cpu(resp->fid);
6583 pf->port_id = le16_to_cpu(resp->port_id);
6584 bp->dev->dev_port = pf->port_id;
6585 memcpy(pf->mac_addr, resp->mac_address, ETH_ALEN);
6586 pf->first_vf_id = le16_to_cpu(resp->first_vf_id);
6587 pf->max_vfs = le16_to_cpu(resp->max_vfs);
6588 pf->max_encap_records = le32_to_cpu(resp->max_encap_records);
6589 pf->max_decap_records = le32_to_cpu(resp->max_decap_records);
6590 pf->max_tx_em_flows = le32_to_cpu(resp->max_tx_em_flows);
6591 pf->max_tx_wm_flows = le32_to_cpu(resp->max_tx_wm_flows);
6592 pf->max_rx_em_flows = le32_to_cpu(resp->max_rx_em_flows);
6593 pf->max_rx_wm_flows = le32_to_cpu(resp->max_rx_wm_flows);
6594 if (flags & FUNC_QCAPS_RESP_FLAGS_WOL_MAGICPKT_SUPPORTED)
6595 bp->flags |= BNXT_FLAG_WOL_CAP;
6597 #ifdef CONFIG_BNXT_SRIOV
6598 struct bnxt_vf_info *vf = &bp->vf;
6600 vf->fw_fid = le16_to_cpu(resp->fid);
6601 memcpy(vf->mac_addr, resp->mac_address, ETH_ALEN);
6605 hwrm_func_qcaps_exit:
6606 mutex_unlock(&bp->hwrm_cmd_lock);
6610 static int bnxt_hwrm_queue_qportcfg(struct bnxt *bp);
6612 static int bnxt_hwrm_func_qcaps(struct bnxt *bp)
6616 rc = __bnxt_hwrm_func_qcaps(bp);
6619 rc = bnxt_hwrm_queue_qportcfg(bp);
6621 netdev_err(bp->dev, "hwrm query qportcfg failure rc: %d\n", rc);
6624 if (bp->hwrm_spec_code >= 0x10803) {
6625 rc = bnxt_alloc_ctx_mem(bp);
6628 rc = bnxt_hwrm_func_resc_qcaps(bp, true);
6630 bp->fw_cap |= BNXT_FW_CAP_NEW_RM;
6635 static int bnxt_hwrm_cfa_adv_flow_mgnt_qcaps(struct bnxt *bp)
6637 struct hwrm_cfa_adv_flow_mgnt_qcaps_input req = {0};
6638 struct hwrm_cfa_adv_flow_mgnt_qcaps_output *resp;
6642 if (!(bp->fw_cap & BNXT_FW_CAP_CFA_ADV_FLOW))
6645 resp = bp->hwrm_cmd_resp_addr;
6646 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_ADV_FLOW_MGNT_QCAPS, -1, -1);
6648 mutex_lock(&bp->hwrm_cmd_lock);
6649 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6651 goto hwrm_cfa_adv_qcaps_exit;
6653 flags = le32_to_cpu(resp->flags);
6655 CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_RFS_RING_TBL_IDX_SUPPORTED)
6656 bp->fw_cap |= BNXT_FW_CAP_CFA_RFS_RING_TBL_IDX;
6658 hwrm_cfa_adv_qcaps_exit:
6659 mutex_unlock(&bp->hwrm_cmd_lock);
6663 static int bnxt_hwrm_func_reset(struct bnxt *bp)
6665 struct hwrm_func_reset_input req = {0};
6667 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_RESET, -1, -1);
6670 return hwrm_send_message(bp, &req, sizeof(req), HWRM_RESET_TIMEOUT);
6673 static int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
6676 struct hwrm_queue_qportcfg_input req = {0};
6677 struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
6681 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_QUEUE_QPORTCFG, -1, -1);
6683 mutex_lock(&bp->hwrm_cmd_lock);
6684 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6688 if (!resp->max_configurable_queues) {
6692 bp->max_tc = resp->max_configurable_queues;
6693 bp->max_lltc = resp->max_configurable_lossless_queues;
6694 if (bp->max_tc > BNXT_MAX_QUEUE)
6695 bp->max_tc = BNXT_MAX_QUEUE;
6697 no_rdma = !(bp->flags & BNXT_FLAG_ROCE_CAP);
6698 qptr = &resp->queue_id0;
6699 for (i = 0, j = 0; i < bp->max_tc; i++) {
6700 bp->q_info[j].queue_id = *qptr;
6701 bp->q_ids[i] = *qptr++;
6702 bp->q_info[j].queue_profile = *qptr++;
6703 bp->tc_to_qidx[j] = j;
6704 if (!BNXT_CNPQ(bp->q_info[j].queue_profile) ||
6705 (no_rdma && BNXT_PF(bp)))
6708 bp->max_q = bp->max_tc;
6709 bp->max_tc = max_t(u8, j, 1);
6711 if (resp->queue_cfg_info & QUEUE_QPORTCFG_RESP_QUEUE_CFG_INFO_ASYM_CFG)
6714 if (bp->max_lltc > bp->max_tc)
6715 bp->max_lltc = bp->max_tc;
6718 mutex_unlock(&bp->hwrm_cmd_lock);
6722 static int bnxt_hwrm_ver_get(struct bnxt *bp)
6725 struct hwrm_ver_get_input req = {0};
6726 struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
6729 bp->hwrm_max_req_len = HWRM_MAX_REQ_LEN;
6730 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VER_GET, -1, -1);
6731 req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
6732 req.hwrm_intf_min = HWRM_VERSION_MINOR;
6733 req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
6734 mutex_lock(&bp->hwrm_cmd_lock);
6735 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6737 goto hwrm_ver_get_exit;
6739 memcpy(&bp->ver_resp, resp, sizeof(struct hwrm_ver_get_output));
6741 bp->hwrm_spec_code = resp->hwrm_intf_maj_8b << 16 |
6742 resp->hwrm_intf_min_8b << 8 |
6743 resp->hwrm_intf_upd_8b;
6744 if (resp->hwrm_intf_maj_8b < 1) {
6745 netdev_warn(bp->dev, "HWRM interface %d.%d.%d is older than 1.0.0.\n",
6746 resp->hwrm_intf_maj_8b, resp->hwrm_intf_min_8b,
6747 resp->hwrm_intf_upd_8b);
6748 netdev_warn(bp->dev, "Please update firmware with HWRM interface 1.0.0 or newer.\n");
6750 snprintf(bp->fw_ver_str, BC_HWRM_STR_LEN, "%d.%d.%d.%d",
6751 resp->hwrm_fw_maj_8b, resp->hwrm_fw_min_8b,
6752 resp->hwrm_fw_bld_8b, resp->hwrm_fw_rsvd_8b);
6754 if (strlen(resp->active_pkg_name)) {
6755 int fw_ver_len = strlen(bp->fw_ver_str);
6757 snprintf(bp->fw_ver_str + fw_ver_len,
6758 FW_VER_STR_LEN - fw_ver_len - 1, "/pkg %s",
6759 resp->active_pkg_name);
6760 bp->fw_cap |= BNXT_FW_CAP_PKG_VER;
6763 bp->hwrm_cmd_timeout = le16_to_cpu(resp->def_req_timeout);
6764 if (!bp->hwrm_cmd_timeout)
6765 bp->hwrm_cmd_timeout = DFLT_HWRM_CMD_TIMEOUT;
6767 if (resp->hwrm_intf_maj_8b >= 1) {
6768 bp->hwrm_max_req_len = le16_to_cpu(resp->max_req_win_len);
6769 bp->hwrm_max_ext_req_len = le16_to_cpu(resp->max_ext_req_len);
6771 if (bp->hwrm_max_ext_req_len < HWRM_MAX_REQ_LEN)
6772 bp->hwrm_max_ext_req_len = HWRM_MAX_REQ_LEN;
6774 bp->chip_num = le16_to_cpu(resp->chip_num);
6775 if (bp->chip_num == CHIP_NUM_58700 && !resp->chip_rev &&
6777 bp->flags |= BNXT_FLAG_CHIP_NITRO_A0;
6779 dev_caps_cfg = le32_to_cpu(resp->dev_caps_cfg);
6780 if ((dev_caps_cfg & VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
6781 (dev_caps_cfg & VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_REQUIRED))
6782 bp->fw_cap |= BNXT_FW_CAP_SHORT_CMD;
6784 if (dev_caps_cfg & VER_GET_RESP_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED)
6785 bp->fw_cap |= BNXT_FW_CAP_KONG_MB_CHNL;
6788 VER_GET_RESP_DEV_CAPS_CFG_FLOW_HANDLE_64BIT_SUPPORTED)
6789 bp->fw_cap |= BNXT_FW_CAP_OVS_64BIT_HANDLE;
6792 VER_GET_RESP_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED)
6793 bp->fw_cap |= BNXT_FW_CAP_TRUSTED_VF;
6796 VER_GET_RESP_DEV_CAPS_CFG_CFA_ADV_FLOW_MGNT_SUPPORTED)
6797 bp->fw_cap |= BNXT_FW_CAP_CFA_ADV_FLOW;
6800 mutex_unlock(&bp->hwrm_cmd_lock);
6804 int bnxt_hwrm_fw_set_time(struct bnxt *bp)
6806 struct hwrm_fw_set_time_input req = {0};
6808 time64_t now = ktime_get_real_seconds();
6810 if ((BNXT_VF(bp) && bp->hwrm_spec_code < 0x10901) ||
6811 bp->hwrm_spec_code < 0x10400)
6814 time64_to_tm(now, 0, &tm);
6815 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FW_SET_TIME, -1, -1);
6816 req.year = cpu_to_le16(1900 + tm.tm_year);
6817 req.month = 1 + tm.tm_mon;
6818 req.day = tm.tm_mday;
6819 req.hour = tm.tm_hour;
6820 req.minute = tm.tm_min;
6821 req.second = tm.tm_sec;
6822 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6825 static int bnxt_hwrm_port_qstats(struct bnxt *bp)
6828 struct bnxt_pf_info *pf = &bp->pf;
6829 struct hwrm_port_qstats_input req = {0};
6831 if (!(bp->flags & BNXT_FLAG_PORT_STATS))
6834 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_QSTATS, -1, -1);
6835 req.port_id = cpu_to_le16(pf->port_id);
6836 req.tx_stat_host_addr = cpu_to_le64(bp->hw_tx_port_stats_map);
6837 req.rx_stat_host_addr = cpu_to_le64(bp->hw_rx_port_stats_map);
6838 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6842 static int bnxt_hwrm_port_qstats_ext(struct bnxt *bp)
6844 struct hwrm_port_qstats_ext_output *resp = bp->hwrm_cmd_resp_addr;
6845 struct hwrm_queue_pri2cos_qcfg_input req2 = {0};
6846 struct hwrm_port_qstats_ext_input req = {0};
6847 struct bnxt_pf_info *pf = &bp->pf;
6851 if (!(bp->flags & BNXT_FLAG_PORT_STATS_EXT))
6854 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_QSTATS_EXT, -1, -1);
6855 req.port_id = cpu_to_le16(pf->port_id);
6856 req.rx_stat_size = cpu_to_le16(sizeof(struct rx_port_stats_ext));
6857 req.rx_stat_host_addr = cpu_to_le64(bp->hw_rx_port_stats_ext_map);
6858 tx_stat_size = bp->hw_tx_port_stats_ext ?
6859 sizeof(*bp->hw_tx_port_stats_ext) : 0;
6860 req.tx_stat_size = cpu_to_le16(tx_stat_size);
6861 req.tx_stat_host_addr = cpu_to_le64(bp->hw_tx_port_stats_ext_map);
6862 mutex_lock(&bp->hwrm_cmd_lock);
6863 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6865 bp->fw_rx_stats_ext_size = le16_to_cpu(resp->rx_stat_size) / 8;
6866 bp->fw_tx_stats_ext_size = tx_stat_size ?
6867 le16_to_cpu(resp->tx_stat_size) / 8 : 0;
6869 bp->fw_rx_stats_ext_size = 0;
6870 bp->fw_tx_stats_ext_size = 0;
6872 if (bp->fw_tx_stats_ext_size <=
6873 offsetof(struct tx_port_stats_ext, pfc_pri0_tx_duration_us) / 8) {
6874 mutex_unlock(&bp->hwrm_cmd_lock);
6875 bp->pri2cos_valid = 0;
6879 bnxt_hwrm_cmd_hdr_init(bp, &req2, HWRM_QUEUE_PRI2COS_QCFG, -1, -1);
6880 req2.flags = cpu_to_le32(QUEUE_PRI2COS_QCFG_REQ_FLAGS_IVLAN);
6882 rc = _hwrm_send_message(bp, &req2, sizeof(req2), HWRM_CMD_TIMEOUT);
6884 struct hwrm_queue_pri2cos_qcfg_output *resp2;
6888 resp2 = bp->hwrm_cmd_resp_addr;
6889 pri2cos = &resp2->pri0_cos_queue_id;
6890 for (i = 0; i < 8; i++) {
6891 u8 queue_id = pri2cos[i];
6893 for (j = 0; j < bp->max_q; j++) {
6894 if (bp->q_ids[j] == queue_id)
6898 bp->pri2cos_valid = 1;
6900 mutex_unlock(&bp->hwrm_cmd_lock);
6904 static int bnxt_hwrm_pcie_qstats(struct bnxt *bp)
6906 struct hwrm_pcie_qstats_input req = {0};
6908 if (!(bp->flags & BNXT_FLAG_PCIE_STATS))
6911 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PCIE_QSTATS, -1, -1);
6912 req.pcie_stat_size = cpu_to_le16(sizeof(struct pcie_ctx_hw_stats));
6913 req.pcie_stat_host_addr = cpu_to_le64(bp->hw_pcie_stats_map);
6914 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6917 static void bnxt_hwrm_free_tunnel_ports(struct bnxt *bp)
6919 if (bp->vxlan_port_cnt) {
6920 bnxt_hwrm_tunnel_dst_port_free(
6921 bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN);
6923 bp->vxlan_port_cnt = 0;
6924 if (bp->nge_port_cnt) {
6925 bnxt_hwrm_tunnel_dst_port_free(
6926 bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE);
6928 bp->nge_port_cnt = 0;
6931 static int bnxt_set_tpa(struct bnxt *bp, bool set_tpa)
6937 tpa_flags = bp->flags & BNXT_FLAG_TPA;
6938 for (i = 0; i < bp->nr_vnics; i++) {
6939 rc = bnxt_hwrm_vnic_set_tpa(bp, i, tpa_flags);
6941 netdev_err(bp->dev, "hwrm vnic set tpa failure rc for vnic %d: %x\n",
6949 static void bnxt_hwrm_clear_vnic_rss(struct bnxt *bp)
6953 for (i = 0; i < bp->nr_vnics; i++)
6954 bnxt_hwrm_vnic_set_rss(bp, i, false);
6957 static void bnxt_hwrm_resource_free(struct bnxt *bp, bool close_path,
6960 if (bp->vnic_info) {
6961 bnxt_hwrm_clear_vnic_filter(bp);
6962 /* clear all RSS setting before free vnic ctx */
6963 bnxt_hwrm_clear_vnic_rss(bp);
6964 bnxt_hwrm_vnic_ctx_free(bp);
6965 /* before free the vnic, undo the vnic tpa settings */
6966 if (bp->flags & BNXT_FLAG_TPA)
6967 bnxt_set_tpa(bp, false);
6968 bnxt_hwrm_vnic_free(bp);
6970 bnxt_hwrm_ring_free(bp, close_path);
6971 bnxt_hwrm_ring_grp_free(bp);
6973 bnxt_hwrm_stat_ctx_free(bp);
6974 bnxt_hwrm_free_tunnel_ports(bp);
6978 static int bnxt_hwrm_set_br_mode(struct bnxt *bp, u16 br_mode)
6980 struct hwrm_func_cfg_input req = {0};
6983 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_CFG, -1, -1);
6984 req.fid = cpu_to_le16(0xffff);
6985 req.enables = cpu_to_le32(FUNC_CFG_REQ_ENABLES_EVB_MODE);
6986 if (br_mode == BRIDGE_MODE_VEB)
6987 req.evb_mode = FUNC_CFG_REQ_EVB_MODE_VEB;
6988 else if (br_mode == BRIDGE_MODE_VEPA)
6989 req.evb_mode = FUNC_CFG_REQ_EVB_MODE_VEPA;
6992 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6998 static int bnxt_hwrm_set_cache_line_size(struct bnxt *bp, int size)
7000 struct hwrm_func_cfg_input req = {0};
7003 if (BNXT_VF(bp) || bp->hwrm_spec_code < 0x10803)
7006 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_CFG, -1, -1);
7007 req.fid = cpu_to_le16(0xffff);
7008 req.enables = cpu_to_le32(FUNC_CFG_REQ_ENABLES_CACHE_LINESIZE);
7009 req.options = FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_64;
7011 req.options = FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_128;
7013 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
7019 static int __bnxt_setup_vnic(struct bnxt *bp, u16 vnic_id)
7021 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
7024 if (vnic->flags & BNXT_VNIC_RFS_NEW_RSS_FLAG)
7027 /* allocate context for vnic */
7028 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic_id, 0);
7030 netdev_err(bp->dev, "hwrm vnic %d alloc failure rc: %x\n",
7032 goto vnic_setup_err;
7034 bp->rsscos_nr_ctxs++;
7036 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) {
7037 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic_id, 1);
7039 netdev_err(bp->dev, "hwrm vnic %d cos ctx alloc failure rc: %x\n",
7041 goto vnic_setup_err;
7043 bp->rsscos_nr_ctxs++;
7047 /* configure default vnic, ring grp */
7048 rc = bnxt_hwrm_vnic_cfg(bp, vnic_id);
7050 netdev_err(bp->dev, "hwrm vnic %d cfg failure rc: %x\n",
7052 goto vnic_setup_err;
7055 /* Enable RSS hashing on vnic */
7056 rc = bnxt_hwrm_vnic_set_rss(bp, vnic_id, true);
7058 netdev_err(bp->dev, "hwrm vnic %d set rss failure rc: %x\n",
7060 goto vnic_setup_err;
7063 if (bp->flags & BNXT_FLAG_AGG_RINGS) {
7064 rc = bnxt_hwrm_vnic_set_hds(bp, vnic_id);
7066 netdev_err(bp->dev, "hwrm vnic %d set hds failure rc: %x\n",
7075 static int __bnxt_setup_vnic_p5(struct bnxt *bp, u16 vnic_id)
7079 nr_ctxs = DIV_ROUND_UP(bp->rx_nr_rings, 64);
7080 for (i = 0; i < nr_ctxs; i++) {
7081 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic_id, i);
7083 netdev_err(bp->dev, "hwrm vnic %d ctx %d alloc failure rc: %x\n",
7087 bp->rsscos_nr_ctxs++;
7092 rc = bnxt_hwrm_vnic_set_rss_p5(bp, vnic_id, true);
7094 netdev_err(bp->dev, "hwrm vnic %d set rss failure rc: %d\n",
7098 rc = bnxt_hwrm_vnic_cfg(bp, vnic_id);
7100 netdev_err(bp->dev, "hwrm vnic %d cfg failure rc: %x\n",
7104 if (bp->flags & BNXT_FLAG_AGG_RINGS) {
7105 rc = bnxt_hwrm_vnic_set_hds(bp, vnic_id);
7107 netdev_err(bp->dev, "hwrm vnic %d set hds failure rc: %x\n",
7114 static int bnxt_setup_vnic(struct bnxt *bp, u16 vnic_id)
7116 if (bp->flags & BNXT_FLAG_CHIP_P5)
7117 return __bnxt_setup_vnic_p5(bp, vnic_id);
7119 return __bnxt_setup_vnic(bp, vnic_id);
7122 static int bnxt_alloc_rfs_vnics(struct bnxt *bp)
7124 #ifdef CONFIG_RFS_ACCEL
7127 for (i = 0; i < bp->rx_nr_rings; i++) {
7128 struct bnxt_vnic_info *vnic;
7129 u16 vnic_id = i + 1;
7132 if (vnic_id >= bp->nr_vnics)
7135 vnic = &bp->vnic_info[vnic_id];
7136 vnic->flags |= BNXT_VNIC_RFS_FLAG;
7137 if (bp->flags & BNXT_FLAG_NEW_RSS_CAP)
7138 vnic->flags |= BNXT_VNIC_RFS_NEW_RSS_FLAG;
7139 rc = bnxt_hwrm_vnic_alloc(bp, vnic_id, ring_id, 1);
7141 netdev_err(bp->dev, "hwrm vnic %d alloc failure rc: %x\n",
7145 rc = bnxt_setup_vnic(bp, vnic_id);
7155 /* Allow PF and VF with default VLAN to be in promiscuous mode */
7156 static bool bnxt_promisc_ok(struct bnxt *bp)
7158 #ifdef CONFIG_BNXT_SRIOV
7159 if (BNXT_VF(bp) && !bp->vf.vlan)
7165 static int bnxt_setup_nitroa0_vnic(struct bnxt *bp)
7167 unsigned int rc = 0;
7169 rc = bnxt_hwrm_vnic_alloc(bp, 1, bp->rx_nr_rings - 1, 1);
7171 netdev_err(bp->dev, "Cannot allocate special vnic for NS2 A0: %x\n",
7176 rc = bnxt_hwrm_vnic_cfg(bp, 1);
7178 netdev_err(bp->dev, "Cannot allocate special vnic for NS2 A0: %x\n",
7185 static int bnxt_cfg_rx_mode(struct bnxt *);
7186 static bool bnxt_mc_list_updated(struct bnxt *, u32 *);
7188 static int bnxt_init_chip(struct bnxt *bp, bool irq_re_init)
7190 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
7192 unsigned int rx_nr_rings = bp->rx_nr_rings;
7195 rc = bnxt_hwrm_stat_ctx_alloc(bp);
7197 netdev_err(bp->dev, "hwrm stat ctx alloc failure rc: %x\n",
7203 rc = bnxt_hwrm_ring_alloc(bp);
7205 netdev_err(bp->dev, "hwrm ring alloc failure rc: %x\n", rc);
7209 rc = bnxt_hwrm_ring_grp_alloc(bp);
7211 netdev_err(bp->dev, "hwrm_ring_grp alloc failure: %x\n", rc);
7215 if (BNXT_CHIP_TYPE_NITRO_A0(bp))
7218 /* default vnic 0 */
7219 rc = bnxt_hwrm_vnic_alloc(bp, 0, 0, rx_nr_rings);
7221 netdev_err(bp->dev, "hwrm vnic alloc failure rc: %x\n", rc);
7225 rc = bnxt_setup_vnic(bp, 0);
7229 if (bp->flags & BNXT_FLAG_RFS) {
7230 rc = bnxt_alloc_rfs_vnics(bp);
7235 if (bp->flags & BNXT_FLAG_TPA) {
7236 rc = bnxt_set_tpa(bp, true);
7242 bnxt_update_vf_mac(bp);
7244 /* Filter for default vnic 0 */
7245 rc = bnxt_hwrm_set_vnic_filter(bp, 0, 0, bp->dev->dev_addr);
7247 netdev_err(bp->dev, "HWRM vnic filter failure rc: %x\n", rc);
7250 vnic->uc_filter_count = 1;
7253 if (bp->dev->flags & IFF_BROADCAST)
7254 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_BCAST;
7256 if ((bp->dev->flags & IFF_PROMISC) && bnxt_promisc_ok(bp))
7257 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS;
7259 if (bp->dev->flags & IFF_ALLMULTI) {
7260 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST;
7261 vnic->mc_list_count = 0;
7265 bnxt_mc_list_updated(bp, &mask);
7266 vnic->rx_mask |= mask;
7269 rc = bnxt_cfg_rx_mode(bp);
7273 rc = bnxt_hwrm_set_coal(bp);
7275 netdev_warn(bp->dev, "HWRM set coalescing failure rc: %x\n",
7278 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) {
7279 rc = bnxt_setup_nitroa0_vnic(bp);
7281 netdev_err(bp->dev, "Special vnic setup failure for NS2 A0 rc: %x\n",
7286 bnxt_hwrm_func_qcfg(bp);
7287 netdev_update_features(bp->dev);
7293 bnxt_hwrm_resource_free(bp, 0, true);
7298 static int bnxt_shutdown_nic(struct bnxt *bp, bool irq_re_init)
7300 bnxt_hwrm_resource_free(bp, 1, irq_re_init);
7304 static int bnxt_init_nic(struct bnxt *bp, bool irq_re_init)
7306 bnxt_init_cp_rings(bp);
7307 bnxt_init_rx_rings(bp);
7308 bnxt_init_tx_rings(bp);
7309 bnxt_init_ring_grps(bp, irq_re_init);
7310 bnxt_init_vnics(bp);
7312 return bnxt_init_chip(bp, irq_re_init);
7315 static int bnxt_set_real_num_queues(struct bnxt *bp)
7318 struct net_device *dev = bp->dev;
7320 rc = netif_set_real_num_tx_queues(dev, bp->tx_nr_rings -
7321 bp->tx_nr_rings_xdp);
7325 rc = netif_set_real_num_rx_queues(dev, bp->rx_nr_rings);
7329 #ifdef CONFIG_RFS_ACCEL
7330 if (bp->flags & BNXT_FLAG_RFS)
7331 dev->rx_cpu_rmap = alloc_irq_cpu_rmap(bp->rx_nr_rings);
7337 static int bnxt_trim_rings(struct bnxt *bp, int *rx, int *tx, int max,
7340 int _rx = *rx, _tx = *tx;
7343 *rx = min_t(int, _rx, max);
7344 *tx = min_t(int, _tx, max);
7349 while (_rx + _tx > max) {
7350 if (_rx > _tx && _rx > 1)
7361 static void bnxt_setup_msix(struct bnxt *bp)
7363 const int len = sizeof(bp->irq_tbl[0].name);
7364 struct net_device *dev = bp->dev;
7367 tcs = netdev_get_num_tc(dev);
7371 for (i = 0; i < tcs; i++) {
7372 count = bp->tx_nr_rings_per_tc;
7374 netdev_set_tc_queue(dev, i, count, off);
7378 for (i = 0; i < bp->cp_nr_rings; i++) {
7379 int map_idx = bnxt_cp_num_to_irq_num(bp, i);
7382 if (bp->flags & BNXT_FLAG_SHARED_RINGS)
7384 else if (i < bp->rx_nr_rings)
7389 snprintf(bp->irq_tbl[map_idx].name, len, "%s-%s-%d", dev->name,
7391 bp->irq_tbl[map_idx].handler = bnxt_msix;
7395 static void bnxt_setup_inta(struct bnxt *bp)
7397 const int len = sizeof(bp->irq_tbl[0].name);
7399 if (netdev_get_num_tc(bp->dev))
7400 netdev_reset_tc(bp->dev);
7402 snprintf(bp->irq_tbl[0].name, len, "%s-%s-%d", bp->dev->name, "TxRx",
7404 bp->irq_tbl[0].handler = bnxt_inta;
7407 static int bnxt_setup_int_mode(struct bnxt *bp)
7411 if (bp->flags & BNXT_FLAG_USING_MSIX)
7412 bnxt_setup_msix(bp);
7414 bnxt_setup_inta(bp);
7416 rc = bnxt_set_real_num_queues(bp);
7420 #ifdef CONFIG_RFS_ACCEL
7421 static unsigned int bnxt_get_max_func_rss_ctxs(struct bnxt *bp)
7423 return bp->hw_resc.max_rsscos_ctxs;
7426 static unsigned int bnxt_get_max_func_vnics(struct bnxt *bp)
7428 return bp->hw_resc.max_vnics;
7432 unsigned int bnxt_get_max_func_stat_ctxs(struct bnxt *bp)
7434 return bp->hw_resc.max_stat_ctxs;
7437 unsigned int bnxt_get_max_func_cp_rings(struct bnxt *bp)
7439 return bp->hw_resc.max_cp_rings;
7442 static unsigned int bnxt_get_max_func_cp_rings_for_en(struct bnxt *bp)
7444 unsigned int cp = bp->hw_resc.max_cp_rings;
7446 if (!(bp->flags & BNXT_FLAG_CHIP_P5))
7447 cp -= bnxt_get_ulp_msix_num(bp);
7452 static unsigned int bnxt_get_max_func_irqs(struct bnxt *bp)
7454 struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
7456 if (bp->flags & BNXT_FLAG_CHIP_P5)
7457 return min_t(unsigned int, hw_resc->max_irqs, hw_resc->max_nqs);
7459 return min_t(unsigned int, hw_resc->max_irqs, hw_resc->max_cp_rings);
7462 static void bnxt_set_max_func_irqs(struct bnxt *bp, unsigned int max_irqs)
7464 bp->hw_resc.max_irqs = max_irqs;
7467 unsigned int bnxt_get_avail_cp_rings_for_en(struct bnxt *bp)
7471 cp = bnxt_get_max_func_cp_rings_for_en(bp);
7472 if (bp->flags & BNXT_FLAG_CHIP_P5)
7473 return cp - bp->rx_nr_rings - bp->tx_nr_rings;
7475 return cp - bp->cp_nr_rings;
7478 unsigned int bnxt_get_avail_stat_ctxs_for_en(struct bnxt *bp)
7482 stat = bnxt_get_max_func_stat_ctxs(bp) - bnxt_get_ulp_stat_ctxs(bp);
7483 stat -= bp->cp_nr_rings;
7487 int bnxt_get_avail_msix(struct bnxt *bp, int num)
7489 int max_cp = bnxt_get_max_func_cp_rings(bp);
7490 int max_irq = bnxt_get_max_func_irqs(bp);
7491 int total_req = bp->cp_nr_rings + num;
7492 int max_idx, avail_msix;
7494 max_idx = bp->total_irqs;
7495 if (!(bp->flags & BNXT_FLAG_CHIP_P5))
7496 max_idx = min_t(int, bp->total_irqs, max_cp);
7497 avail_msix = max_idx - bp->cp_nr_rings;
7498 if (!BNXT_NEW_RM(bp) || avail_msix >= num)
7501 if (max_irq < total_req) {
7502 num = max_irq - bp->cp_nr_rings;
7509 static int bnxt_get_num_msix(struct bnxt *bp)
7511 if (!BNXT_NEW_RM(bp))
7512 return bnxt_get_max_func_irqs(bp);
7514 return bnxt_nq_rings_in_use(bp);
7517 static int bnxt_init_msix(struct bnxt *bp)
7519 int i, total_vecs, max, rc = 0, min = 1, ulp_msix;
7520 struct msix_entry *msix_ent;
7522 total_vecs = bnxt_get_num_msix(bp);
7523 max = bnxt_get_max_func_irqs(bp);
7524 if (total_vecs > max)
7530 msix_ent = kcalloc(total_vecs, sizeof(struct msix_entry), GFP_KERNEL);
7534 for (i = 0; i < total_vecs; i++) {
7535 msix_ent[i].entry = i;
7536 msix_ent[i].vector = 0;
7539 if (!(bp->flags & BNXT_FLAG_SHARED_RINGS))
7542 total_vecs = pci_enable_msix_range(bp->pdev, msix_ent, min, total_vecs);
7543 ulp_msix = bnxt_get_ulp_msix_num(bp);
7544 if (total_vecs < 0 || total_vecs < ulp_msix) {
7546 goto msix_setup_exit;
7549 bp->irq_tbl = kcalloc(total_vecs, sizeof(struct bnxt_irq), GFP_KERNEL);
7551 for (i = 0; i < total_vecs; i++)
7552 bp->irq_tbl[i].vector = msix_ent[i].vector;
7554 bp->total_irqs = total_vecs;
7555 /* Trim rings based upon num of vectors allocated */
7556 rc = bnxt_trim_rings(bp, &bp->rx_nr_rings, &bp->tx_nr_rings,
7557 total_vecs - ulp_msix, min == 1);
7559 goto msix_setup_exit;
7561 bp->cp_nr_rings = (min == 1) ?
7562 max_t(int, bp->tx_nr_rings, bp->rx_nr_rings) :
7563 bp->tx_nr_rings + bp->rx_nr_rings;
7567 goto msix_setup_exit;
7569 bp->flags |= BNXT_FLAG_USING_MSIX;
7574 netdev_err(bp->dev, "bnxt_init_msix err: %x\n", rc);
7577 pci_disable_msix(bp->pdev);
7582 static int bnxt_init_inta(struct bnxt *bp)
7584 bp->irq_tbl = kcalloc(1, sizeof(struct bnxt_irq), GFP_KERNEL);
7589 bp->rx_nr_rings = 1;
7590 bp->tx_nr_rings = 1;
7591 bp->cp_nr_rings = 1;
7592 bp->flags |= BNXT_FLAG_SHARED_RINGS;
7593 bp->irq_tbl[0].vector = bp->pdev->irq;
7597 static int bnxt_init_int_mode(struct bnxt *bp)
7601 if (bp->flags & BNXT_FLAG_MSIX_CAP)
7602 rc = bnxt_init_msix(bp);
7604 if (!(bp->flags & BNXT_FLAG_USING_MSIX) && BNXT_PF(bp)) {
7605 /* fallback to INTA */
7606 rc = bnxt_init_inta(bp);
7611 static void bnxt_clear_int_mode(struct bnxt *bp)
7613 if (bp->flags & BNXT_FLAG_USING_MSIX)
7614 pci_disable_msix(bp->pdev);
7618 bp->flags &= ~BNXT_FLAG_USING_MSIX;
7621 int bnxt_reserve_rings(struct bnxt *bp, bool irq_re_init)
7623 int tcs = netdev_get_num_tc(bp->dev);
7624 bool irq_cleared = false;
7627 if (!bnxt_need_reserve_rings(bp))
7630 if (irq_re_init && BNXT_NEW_RM(bp) &&
7631 bnxt_get_num_msix(bp) != bp->total_irqs) {
7632 bnxt_ulp_irq_stop(bp);
7633 bnxt_clear_int_mode(bp);
7636 rc = __bnxt_reserve_rings(bp);
7639 rc = bnxt_init_int_mode(bp);
7640 bnxt_ulp_irq_restart(bp, rc);
7643 netdev_err(bp->dev, "ring reservation/IRQ init failure rc: %d\n", rc);
7646 if (tcs && (bp->tx_nr_rings_per_tc * tcs != bp->tx_nr_rings)) {
7647 netdev_err(bp->dev, "tx ring reservation failure\n");
7648 netdev_reset_tc(bp->dev);
7649 bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
7655 static void bnxt_free_irq(struct bnxt *bp)
7657 struct bnxt_irq *irq;
7660 #ifdef CONFIG_RFS_ACCEL
7661 free_irq_cpu_rmap(bp->dev->rx_cpu_rmap);
7662 bp->dev->rx_cpu_rmap = NULL;
7664 if (!bp->irq_tbl || !bp->bnapi)
7667 for (i = 0; i < bp->cp_nr_rings; i++) {
7668 int map_idx = bnxt_cp_num_to_irq_num(bp, i);
7670 irq = &bp->irq_tbl[map_idx];
7671 if (irq->requested) {
7672 if (irq->have_cpumask) {
7673 irq_set_affinity_hint(irq->vector, NULL);
7674 free_cpumask_var(irq->cpu_mask);
7675 irq->have_cpumask = 0;
7677 free_irq(irq->vector, bp->bnapi[i]);
7684 static int bnxt_request_irq(struct bnxt *bp)
7687 unsigned long flags = 0;
7688 #ifdef CONFIG_RFS_ACCEL
7689 struct cpu_rmap *rmap;
7692 rc = bnxt_setup_int_mode(bp);
7694 netdev_err(bp->dev, "bnxt_setup_int_mode err: %x\n",
7698 #ifdef CONFIG_RFS_ACCEL
7699 rmap = bp->dev->rx_cpu_rmap;
7701 if (!(bp->flags & BNXT_FLAG_USING_MSIX))
7702 flags = IRQF_SHARED;
7704 for (i = 0, j = 0; i < bp->cp_nr_rings; i++) {
7705 int map_idx = bnxt_cp_num_to_irq_num(bp, i);
7706 struct bnxt_irq *irq = &bp->irq_tbl[map_idx];
7708 #ifdef CONFIG_RFS_ACCEL
7709 if (rmap && bp->bnapi[i]->rx_ring) {
7710 rc = irq_cpu_rmap_add(rmap, irq->vector);
7712 netdev_warn(bp->dev, "failed adding irq rmap for ring %d\n",
7717 rc = request_irq(irq->vector, irq->handler, flags, irq->name,
7724 if (zalloc_cpumask_var(&irq->cpu_mask, GFP_KERNEL)) {
7725 int numa_node = dev_to_node(&bp->pdev->dev);
7727 irq->have_cpumask = 1;
7728 cpumask_set_cpu(cpumask_local_spread(i, numa_node),
7730 rc = irq_set_affinity_hint(irq->vector, irq->cpu_mask);
7732 netdev_warn(bp->dev,
7733 "Set affinity failed, IRQ = %d\n",
7742 static void bnxt_del_napi(struct bnxt *bp)
7749 for (i = 0; i < bp->cp_nr_rings; i++) {
7750 struct bnxt_napi *bnapi = bp->bnapi[i];
7752 napi_hash_del(&bnapi->napi);
7753 netif_napi_del(&bnapi->napi);
7755 /* We called napi_hash_del() before netif_napi_del(), we need
7756 * to respect an RCU grace period before freeing napi structures.
7761 static void bnxt_init_napi(struct bnxt *bp)
7764 unsigned int cp_nr_rings = bp->cp_nr_rings;
7765 struct bnxt_napi *bnapi;
7767 if (bp->flags & BNXT_FLAG_USING_MSIX) {
7768 int (*poll_fn)(struct napi_struct *, int) = bnxt_poll;
7770 if (bp->flags & BNXT_FLAG_CHIP_P5)
7771 poll_fn = bnxt_poll_p5;
7772 else if (BNXT_CHIP_TYPE_NITRO_A0(bp))
7774 for (i = 0; i < cp_nr_rings; i++) {
7775 bnapi = bp->bnapi[i];
7776 netif_napi_add(bp->dev, &bnapi->napi, poll_fn, 64);
7778 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) {
7779 bnapi = bp->bnapi[cp_nr_rings];
7780 netif_napi_add(bp->dev, &bnapi->napi,
7781 bnxt_poll_nitroa0, 64);
7784 bnapi = bp->bnapi[0];
7785 netif_napi_add(bp->dev, &bnapi->napi, bnxt_poll, 64);
7789 static void bnxt_disable_napi(struct bnxt *bp)
7796 for (i = 0; i < bp->cp_nr_rings; i++) {
7797 struct bnxt_cp_ring_info *cpr = &bp->bnapi[i]->cp_ring;
7799 if (bp->bnapi[i]->rx_ring)
7800 cancel_work_sync(&cpr->dim.work);
7802 napi_disable(&bp->bnapi[i]->napi);
7806 static void bnxt_enable_napi(struct bnxt *bp)
7810 for (i = 0; i < bp->cp_nr_rings; i++) {
7811 struct bnxt_cp_ring_info *cpr = &bp->bnapi[i]->cp_ring;
7812 bp->bnapi[i]->in_reset = false;
7814 if (bp->bnapi[i]->rx_ring) {
7815 INIT_WORK(&cpr->dim.work, bnxt_dim_work);
7816 cpr->dim.mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE;
7818 napi_enable(&bp->bnapi[i]->napi);
7822 void bnxt_tx_disable(struct bnxt *bp)
7825 struct bnxt_tx_ring_info *txr;
7828 for (i = 0; i < bp->tx_nr_rings; i++) {
7829 txr = &bp->tx_ring[i];
7830 txr->dev_state = BNXT_DEV_STATE_CLOSING;
7833 /* Stop all TX queues */
7834 netif_tx_disable(bp->dev);
7835 netif_carrier_off(bp->dev);
7838 void bnxt_tx_enable(struct bnxt *bp)
7841 struct bnxt_tx_ring_info *txr;
7843 for (i = 0; i < bp->tx_nr_rings; i++) {
7844 txr = &bp->tx_ring[i];
7847 netif_tx_wake_all_queues(bp->dev);
7848 if (bp->link_info.link_up)
7849 netif_carrier_on(bp->dev);
7852 static void bnxt_report_link(struct bnxt *bp)
7854 if (bp->link_info.link_up) {
7856 const char *flow_ctrl;
7860 netif_carrier_on(bp->dev);
7861 if (bp->link_info.duplex == BNXT_LINK_DUPLEX_FULL)
7865 if (bp->link_info.pause == BNXT_LINK_PAUSE_BOTH)
7866 flow_ctrl = "ON - receive & transmit";
7867 else if (bp->link_info.pause == BNXT_LINK_PAUSE_TX)
7868 flow_ctrl = "ON - transmit";
7869 else if (bp->link_info.pause == BNXT_LINK_PAUSE_RX)
7870 flow_ctrl = "ON - receive";
7873 speed = bnxt_fw_to_ethtool_speed(bp->link_info.link_speed);
7874 netdev_info(bp->dev, "NIC Link is Up, %u Mbps %s duplex, Flow control: %s\n",
7875 speed, duplex, flow_ctrl);
7876 if (bp->flags & BNXT_FLAG_EEE_CAP)
7877 netdev_info(bp->dev, "EEE is %s\n",
7878 bp->eee.eee_active ? "active" :
7880 fec = bp->link_info.fec_cfg;
7881 if (!(fec & PORT_PHY_QCFG_RESP_FEC_CFG_FEC_NONE_SUPPORTED))
7882 netdev_info(bp->dev, "FEC autoneg %s encodings: %s\n",
7883 (fec & BNXT_FEC_AUTONEG) ? "on" : "off",
7884 (fec & BNXT_FEC_ENC_BASE_R) ? "BaseR" :
7885 (fec & BNXT_FEC_ENC_RS) ? "RS" : "None");
7887 netif_carrier_off(bp->dev);
7888 netdev_err(bp->dev, "NIC Link is Down\n");
7892 static int bnxt_hwrm_phy_qcaps(struct bnxt *bp)
7895 struct hwrm_port_phy_qcaps_input req = {0};
7896 struct hwrm_port_phy_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
7897 struct bnxt_link_info *link_info = &bp->link_info;
7899 if (bp->hwrm_spec_code < 0x10201)
7902 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_QCAPS, -1, -1);
7904 mutex_lock(&bp->hwrm_cmd_lock);
7905 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
7907 goto hwrm_phy_qcaps_exit;
7909 if (resp->flags & PORT_PHY_QCAPS_RESP_FLAGS_EEE_SUPPORTED) {
7910 struct ethtool_eee *eee = &bp->eee;
7911 u16 fw_speeds = le16_to_cpu(resp->supported_speeds_eee_mode);
7913 bp->flags |= BNXT_FLAG_EEE_CAP;
7914 eee->supported = _bnxt_fw_to_ethtool_adv_spds(fw_speeds, 0);
7915 bp->lpi_tmr_lo = le32_to_cpu(resp->tx_lpi_timer_low) &
7916 PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_LOW_MASK;
7917 bp->lpi_tmr_hi = le32_to_cpu(resp->valid_tx_lpi_timer_high) &
7918 PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_HIGH_MASK;
7920 if (resp->flags & PORT_PHY_QCAPS_RESP_FLAGS_EXTERNAL_LPBK_SUPPORTED) {
7922 bp->test_info->flags |= BNXT_TEST_FL_EXT_LPBK;
7924 if (resp->supported_speeds_auto_mode)
7925 link_info->support_auto_speeds =
7926 le16_to_cpu(resp->supported_speeds_auto_mode);
7928 bp->port_count = resp->port_cnt;
7930 hwrm_phy_qcaps_exit:
7931 mutex_unlock(&bp->hwrm_cmd_lock);
7935 static int bnxt_update_link(struct bnxt *bp, bool chng_link_state)
7938 struct bnxt_link_info *link_info = &bp->link_info;
7939 struct hwrm_port_phy_qcfg_input req = {0};
7940 struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
7941 u8 link_up = link_info->link_up;
7944 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_QCFG, -1, -1);
7946 mutex_lock(&bp->hwrm_cmd_lock);
7947 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
7949 mutex_unlock(&bp->hwrm_cmd_lock);
7953 memcpy(&link_info->phy_qcfg_resp, resp, sizeof(*resp));
7954 link_info->phy_link_status = resp->link;
7955 link_info->duplex = resp->duplex_cfg;
7956 if (bp->hwrm_spec_code >= 0x10800)
7957 link_info->duplex = resp->duplex_state;
7958 link_info->pause = resp->pause;
7959 link_info->auto_mode = resp->auto_mode;
7960 link_info->auto_pause_setting = resp->auto_pause;
7961 link_info->lp_pause = resp->link_partner_adv_pause;
7962 link_info->force_pause_setting = resp->force_pause;
7963 link_info->duplex_setting = resp->duplex_cfg;
7964 if (link_info->phy_link_status == BNXT_LINK_LINK)
7965 link_info->link_speed = le16_to_cpu(resp->link_speed);
7967 link_info->link_speed = 0;
7968 link_info->force_link_speed = le16_to_cpu(resp->force_link_speed);
7969 link_info->support_speeds = le16_to_cpu(resp->support_speeds);
7970 link_info->auto_link_speeds = le16_to_cpu(resp->auto_link_speed_mask);
7971 link_info->lp_auto_link_speeds =
7972 le16_to_cpu(resp->link_partner_adv_speeds);
7973 link_info->preemphasis = le32_to_cpu(resp->preemphasis);
7974 link_info->phy_ver[0] = resp->phy_maj;
7975 link_info->phy_ver[1] = resp->phy_min;
7976 link_info->phy_ver[2] = resp->phy_bld;
7977 link_info->media_type = resp->media_type;
7978 link_info->phy_type = resp->phy_type;
7979 link_info->transceiver = resp->xcvr_pkg_type;
7980 link_info->phy_addr = resp->eee_config_phy_addr &
7981 PORT_PHY_QCFG_RESP_PHY_ADDR_MASK;
7982 link_info->module_status = resp->module_status;
7984 if (bp->flags & BNXT_FLAG_EEE_CAP) {
7985 struct ethtool_eee *eee = &bp->eee;
7988 eee->eee_active = 0;
7989 if (resp->eee_config_phy_addr &
7990 PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ACTIVE) {
7991 eee->eee_active = 1;
7992 fw_speeds = le16_to_cpu(
7993 resp->link_partner_adv_eee_link_speed_mask);
7994 eee->lp_advertised =
7995 _bnxt_fw_to_ethtool_adv_spds(fw_speeds, 0);
7998 /* Pull initial EEE config */
7999 if (!chng_link_state) {
8000 if (resp->eee_config_phy_addr &
8001 PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ENABLED)
8002 eee->eee_enabled = 1;
8004 fw_speeds = le16_to_cpu(resp->adv_eee_link_speed_mask);
8006 _bnxt_fw_to_ethtool_adv_spds(fw_speeds, 0);
8008 if (resp->eee_config_phy_addr &
8009 PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_TX_LPI) {
8012 eee->tx_lpi_enabled = 1;
8013 tmr = resp->xcvr_identifier_type_tx_lpi_timer;
8014 eee->tx_lpi_timer = le32_to_cpu(tmr) &
8015 PORT_PHY_QCFG_RESP_TX_LPI_TIMER_MASK;
8020 link_info->fec_cfg = PORT_PHY_QCFG_RESP_FEC_CFG_FEC_NONE_SUPPORTED;
8021 if (bp->hwrm_spec_code >= 0x10504)
8022 link_info->fec_cfg = le16_to_cpu(resp->fec_cfg);
8024 /* TODO: need to add more logic to report VF link */
8025 if (chng_link_state) {
8026 if (link_info->phy_link_status == BNXT_LINK_LINK)
8027 link_info->link_up = 1;
8029 link_info->link_up = 0;
8030 if (link_up != link_info->link_up)
8031 bnxt_report_link(bp);
8033 /* alwasy link down if not require to update link state */
8034 link_info->link_up = 0;
8036 mutex_unlock(&bp->hwrm_cmd_lock);
8038 if (!BNXT_SINGLE_PF(bp))
8041 diff = link_info->support_auto_speeds ^ link_info->advertising;
8042 if ((link_info->support_auto_speeds | diff) !=
8043 link_info->support_auto_speeds) {
8044 /* An advertised speed is no longer supported, so we need to
8045 * update the advertisement settings. Caller holds RTNL
8046 * so we can modify link settings.
8048 link_info->advertising = link_info->support_auto_speeds;
8049 if (link_info->autoneg & BNXT_AUTONEG_SPEED)
8050 bnxt_hwrm_set_link_setting(bp, true, false);
8055 static void bnxt_get_port_module_status(struct bnxt *bp)
8057 struct bnxt_link_info *link_info = &bp->link_info;
8058 struct hwrm_port_phy_qcfg_output *resp = &link_info->phy_qcfg_resp;
8061 if (bnxt_update_link(bp, true))
8064 module_status = link_info->module_status;
8065 switch (module_status) {
8066 case PORT_PHY_QCFG_RESP_MODULE_STATUS_DISABLETX:
8067 case PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN:
8068 case PORT_PHY_QCFG_RESP_MODULE_STATUS_WARNINGMSG:
8069 netdev_warn(bp->dev, "Unqualified SFP+ module detected on port %d\n",
8071 if (bp->hwrm_spec_code >= 0x10201) {
8072 netdev_warn(bp->dev, "Module part number %s\n",
8073 resp->phy_vendor_partnumber);
8075 if (module_status == PORT_PHY_QCFG_RESP_MODULE_STATUS_DISABLETX)
8076 netdev_warn(bp->dev, "TX is disabled\n");
8077 if (module_status == PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN)
8078 netdev_warn(bp->dev, "SFP+ module is shutdown\n");
8083 bnxt_hwrm_set_pause_common(struct bnxt *bp, struct hwrm_port_phy_cfg_input *req)
8085 if (bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL) {
8086 if (bp->hwrm_spec_code >= 0x10201)
8088 PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE;
8089 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_RX)
8090 req->auto_pause |= PORT_PHY_CFG_REQ_AUTO_PAUSE_RX;
8091 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_TX)
8092 req->auto_pause |= PORT_PHY_CFG_REQ_AUTO_PAUSE_TX;
8094 cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE);
8096 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_RX)
8097 req->force_pause |= PORT_PHY_CFG_REQ_FORCE_PAUSE_RX;
8098 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_TX)
8099 req->force_pause |= PORT_PHY_CFG_REQ_FORCE_PAUSE_TX;
8101 cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_FORCE_PAUSE);
8102 if (bp->hwrm_spec_code >= 0x10201) {
8103 req->auto_pause = req->force_pause;
8104 req->enables |= cpu_to_le32(
8105 PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE);
8110 static void bnxt_hwrm_set_link_common(struct bnxt *bp,
8111 struct hwrm_port_phy_cfg_input *req)
8113 u8 autoneg = bp->link_info.autoneg;
8114 u16 fw_link_speed = bp->link_info.req_link_speed;
8115 u16 advertising = bp->link_info.advertising;
8117 if (autoneg & BNXT_AUTONEG_SPEED) {
8119 PORT_PHY_CFG_REQ_AUTO_MODE_SPEED_MASK;
8121 req->enables |= cpu_to_le32(
8122 PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED_MASK);
8123 req->auto_link_speed_mask = cpu_to_le16(advertising);
8125 req->enables |= cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_MODE);
8127 cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_RESTART_AUTONEG);
8129 req->force_link_speed = cpu_to_le16(fw_link_speed);
8130 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_FORCE);
8133 /* tell chimp that the setting takes effect immediately */
8134 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_RESET_PHY);
8137 int bnxt_hwrm_set_pause(struct bnxt *bp)
8139 struct hwrm_port_phy_cfg_input req = {0};
8142 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1);
8143 bnxt_hwrm_set_pause_common(bp, &req);
8145 if ((bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL) ||
8146 bp->link_info.force_link_chng)
8147 bnxt_hwrm_set_link_common(bp, &req);
8149 mutex_lock(&bp->hwrm_cmd_lock);
8150 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
8151 if (!rc && !(bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL)) {
8152 /* since changing of pause setting doesn't trigger any link
8153 * change event, the driver needs to update the current pause
8154 * result upon successfully return of the phy_cfg command
8156 bp->link_info.pause =
8157 bp->link_info.force_pause_setting = bp->link_info.req_flow_ctrl;
8158 bp->link_info.auto_pause_setting = 0;
8159 if (!bp->link_info.force_link_chng)
8160 bnxt_report_link(bp);
8162 bp->link_info.force_link_chng = false;
8163 mutex_unlock(&bp->hwrm_cmd_lock);
8167 static void bnxt_hwrm_set_eee(struct bnxt *bp,
8168 struct hwrm_port_phy_cfg_input *req)
8170 struct ethtool_eee *eee = &bp->eee;
8172 if (eee->eee_enabled) {
8174 u32 flags = PORT_PHY_CFG_REQ_FLAGS_EEE_ENABLE;
8176 if (eee->tx_lpi_enabled)
8177 flags |= PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_ENABLE;
8179 flags |= PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_DISABLE;
8181 req->flags |= cpu_to_le32(flags);
8182 eee_speeds = bnxt_get_fw_auto_link_speeds(eee->advertised);
8183 req->eee_link_speed_mask = cpu_to_le16(eee_speeds);
8184 req->tx_lpi_timer = cpu_to_le32(eee->tx_lpi_timer);
8186 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_EEE_DISABLE);
8190 int bnxt_hwrm_set_link_setting(struct bnxt *bp, bool set_pause, bool set_eee)
8192 struct hwrm_port_phy_cfg_input req = {0};
8194 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1);
8196 bnxt_hwrm_set_pause_common(bp, &req);
8198 bnxt_hwrm_set_link_common(bp, &req);
8201 bnxt_hwrm_set_eee(bp, &req);
8202 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
8205 static int bnxt_hwrm_shutdown_link(struct bnxt *bp)
8207 struct hwrm_port_phy_cfg_input req = {0};
8209 if (!BNXT_SINGLE_PF(bp))
8212 if (pci_num_vf(bp->pdev))
8215 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1);
8216 req.flags = cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_FORCE_LINK_DWN);
8217 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
8220 static int bnxt_hwrm_if_change(struct bnxt *bp, bool up)
8222 struct hwrm_func_drv_if_change_output *resp = bp->hwrm_cmd_resp_addr;
8223 struct hwrm_func_drv_if_change_input req = {0};
8224 bool resc_reinit = false;
8227 if (!(bp->fw_cap & BNXT_FW_CAP_IF_CHANGE))
8230 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_IF_CHANGE, -1, -1);
8232 req.flags = cpu_to_le32(FUNC_DRV_IF_CHANGE_REQ_FLAGS_UP);
8233 mutex_lock(&bp->hwrm_cmd_lock);
8234 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
8235 if (!rc && (resp->flags &
8236 cpu_to_le32(FUNC_DRV_IF_CHANGE_RESP_FLAGS_RESC_CHANGE)))
8238 mutex_unlock(&bp->hwrm_cmd_lock);
8240 if (up && resc_reinit && BNXT_NEW_RM(bp)) {
8241 struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
8243 rc = bnxt_hwrm_func_resc_qcaps(bp, true);
8244 hw_resc->resv_cp_rings = 0;
8245 hw_resc->resv_stat_ctxs = 0;
8246 hw_resc->resv_irqs = 0;
8247 hw_resc->resv_tx_rings = 0;
8248 hw_resc->resv_rx_rings = 0;
8249 hw_resc->resv_hw_ring_grps = 0;
8250 hw_resc->resv_vnics = 0;
8251 bp->tx_nr_rings = 0;
8252 bp->rx_nr_rings = 0;
8257 static int bnxt_hwrm_port_led_qcaps(struct bnxt *bp)
8259 struct hwrm_port_led_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
8260 struct hwrm_port_led_qcaps_input req = {0};
8261 struct bnxt_pf_info *pf = &bp->pf;
8264 if (BNXT_VF(bp) || bp->hwrm_spec_code < 0x10601)
8267 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_LED_QCAPS, -1, -1);
8268 req.port_id = cpu_to_le16(pf->port_id);
8269 mutex_lock(&bp->hwrm_cmd_lock);
8270 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
8272 mutex_unlock(&bp->hwrm_cmd_lock);
8275 if (resp->num_leds > 0 && resp->num_leds < BNXT_MAX_LED) {
8278 bp->num_leds = resp->num_leds;
8279 memcpy(bp->leds, &resp->led0_id, sizeof(bp->leds[0]) *
8281 for (i = 0; i < bp->num_leds; i++) {
8282 struct bnxt_led_info *led = &bp->leds[i];
8283 __le16 caps = led->led_state_caps;
8285 if (!led->led_group_id ||
8286 !BNXT_LED_ALT_BLINK_CAP(caps)) {
8292 mutex_unlock(&bp->hwrm_cmd_lock);
8296 int bnxt_hwrm_alloc_wol_fltr(struct bnxt *bp)
8298 struct hwrm_wol_filter_alloc_input req = {0};
8299 struct hwrm_wol_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
8302 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_WOL_FILTER_ALLOC, -1, -1);
8303 req.port_id = cpu_to_le16(bp->pf.port_id);
8304 req.wol_type = WOL_FILTER_ALLOC_REQ_WOL_TYPE_MAGICPKT;
8305 req.enables = cpu_to_le32(WOL_FILTER_ALLOC_REQ_ENABLES_MAC_ADDRESS);
8306 memcpy(req.mac_address, bp->dev->dev_addr, ETH_ALEN);
8307 mutex_lock(&bp->hwrm_cmd_lock);
8308 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
8310 bp->wol_filter_id = resp->wol_filter_id;
8311 mutex_unlock(&bp->hwrm_cmd_lock);
8315 int bnxt_hwrm_free_wol_fltr(struct bnxt *bp)
8317 struct hwrm_wol_filter_free_input req = {0};
8320 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_WOL_FILTER_FREE, -1, -1);
8321 req.port_id = cpu_to_le16(bp->pf.port_id);
8322 req.enables = cpu_to_le32(WOL_FILTER_FREE_REQ_ENABLES_WOL_FILTER_ID);
8323 req.wol_filter_id = bp->wol_filter_id;
8324 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
8328 static u16 bnxt_hwrm_get_wol_fltrs(struct bnxt *bp, u16 handle)
8330 struct hwrm_wol_filter_qcfg_input req = {0};
8331 struct hwrm_wol_filter_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
8332 u16 next_handle = 0;
8335 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_WOL_FILTER_QCFG, -1, -1);
8336 req.port_id = cpu_to_le16(bp->pf.port_id);
8337 req.handle = cpu_to_le16(handle);
8338 mutex_lock(&bp->hwrm_cmd_lock);
8339 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
8341 next_handle = le16_to_cpu(resp->next_handle);
8342 if (next_handle != 0) {
8343 if (resp->wol_type ==
8344 WOL_FILTER_ALLOC_REQ_WOL_TYPE_MAGICPKT) {
8346 bp->wol_filter_id = resp->wol_filter_id;
8350 mutex_unlock(&bp->hwrm_cmd_lock);
8354 static void bnxt_get_wol_settings(struct bnxt *bp)
8358 if (!BNXT_PF(bp) || !(bp->flags & BNXT_FLAG_WOL_CAP))
8362 handle = bnxt_hwrm_get_wol_fltrs(bp, handle);
8363 } while (handle && handle != 0xffff);
8366 #ifdef CONFIG_BNXT_HWMON
8367 static ssize_t bnxt_show_temp(struct device *dev,
8368 struct device_attribute *devattr, char *buf)
8370 struct hwrm_temp_monitor_query_input req = {0};
8371 struct hwrm_temp_monitor_query_output *resp;
8372 struct bnxt *bp = dev_get_drvdata(dev);
8375 resp = bp->hwrm_cmd_resp_addr;
8376 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_TEMP_MONITOR_QUERY, -1, -1);
8377 mutex_lock(&bp->hwrm_cmd_lock);
8378 if (!_hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT))
8379 temp = resp->temp * 1000; /* display millidegree */
8380 mutex_unlock(&bp->hwrm_cmd_lock);
8382 return sprintf(buf, "%u\n", temp);
8384 static SENSOR_DEVICE_ATTR(temp1_input, 0444, bnxt_show_temp, NULL, 0);
8386 static struct attribute *bnxt_attrs[] = {
8387 &sensor_dev_attr_temp1_input.dev_attr.attr,
8390 ATTRIBUTE_GROUPS(bnxt);
8392 static void bnxt_hwmon_close(struct bnxt *bp)
8394 if (bp->hwmon_dev) {
8395 hwmon_device_unregister(bp->hwmon_dev);
8396 bp->hwmon_dev = NULL;
8400 static void bnxt_hwmon_open(struct bnxt *bp)
8402 struct pci_dev *pdev = bp->pdev;
8404 bp->hwmon_dev = hwmon_device_register_with_groups(&pdev->dev,
8405 DRV_MODULE_NAME, bp,
8407 if (IS_ERR(bp->hwmon_dev)) {
8408 bp->hwmon_dev = NULL;
8409 dev_warn(&pdev->dev, "Cannot register hwmon device\n");
8413 static void bnxt_hwmon_close(struct bnxt *bp)
8417 static void bnxt_hwmon_open(struct bnxt *bp)
8422 static bool bnxt_eee_config_ok(struct bnxt *bp)
8424 struct ethtool_eee *eee = &bp->eee;
8425 struct bnxt_link_info *link_info = &bp->link_info;
8427 if (!(bp->flags & BNXT_FLAG_EEE_CAP))
8430 if (eee->eee_enabled) {
8432 _bnxt_fw_to_ethtool_adv_spds(link_info->advertising, 0);
8434 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) {
8435 eee->eee_enabled = 0;
8438 if (eee->advertised & ~advertising) {
8439 eee->advertised = advertising & eee->supported;
8446 static int bnxt_update_phy_setting(struct bnxt *bp)
8449 bool update_link = false;
8450 bool update_pause = false;
8451 bool update_eee = false;
8452 struct bnxt_link_info *link_info = &bp->link_info;
8454 rc = bnxt_update_link(bp, true);
8456 netdev_err(bp->dev, "failed to update link (rc: %x)\n",
8460 if (!BNXT_SINGLE_PF(bp))
8463 if ((link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) &&
8464 (link_info->auto_pause_setting & BNXT_LINK_PAUSE_BOTH) !=
8465 link_info->req_flow_ctrl)
8466 update_pause = true;
8467 if (!(link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) &&
8468 link_info->force_pause_setting != link_info->req_flow_ctrl)
8469 update_pause = true;
8470 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) {
8471 if (BNXT_AUTO_MODE(link_info->auto_mode))
8473 if (link_info->req_link_speed != link_info->force_link_speed)
8475 if (link_info->req_duplex != link_info->duplex_setting)
8478 if (link_info->auto_mode == BNXT_LINK_AUTO_NONE)
8480 if (link_info->advertising != link_info->auto_link_speeds)
8484 /* The last close may have shutdown the link, so need to call
8485 * PHY_CFG to bring it back up.
8487 if (!netif_carrier_ok(bp->dev))
8490 if (!bnxt_eee_config_ok(bp))
8494 rc = bnxt_hwrm_set_link_setting(bp, update_pause, update_eee);
8495 else if (update_pause)
8496 rc = bnxt_hwrm_set_pause(bp);
8498 netdev_err(bp->dev, "failed to update phy setting (rc: %x)\n",
8506 /* Common routine to pre-map certain register block to different GRC window.
8507 * A PF has 16 4K windows and a VF has 4 4K windows. However, only 15 windows
8508 * in PF and 3 windows in VF that can be customized to map in different
8511 static void bnxt_preset_reg_win(struct bnxt *bp)
8514 /* CAG registers map to GRC window #4 */
8515 writel(BNXT_CAG_REG_BASE,
8516 bp->bar0 + BNXT_GRCPF_REG_WINDOW_BASE_OUT + 12);
8520 static int bnxt_init_dflt_ring_mode(struct bnxt *bp);
8522 static int __bnxt_open_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init)
8526 bnxt_preset_reg_win(bp);
8527 netif_carrier_off(bp->dev);
8529 /* Reserve rings now if none were reserved at driver probe. */
8530 rc = bnxt_init_dflt_ring_mode(bp);
8532 netdev_err(bp->dev, "Failed to reserve default rings at open\n");
8536 rc = bnxt_reserve_rings(bp, irq_re_init);
8539 if ((bp->flags & BNXT_FLAG_RFS) &&
8540 !(bp->flags & BNXT_FLAG_USING_MSIX)) {
8541 /* disable RFS if falling back to INTA */
8542 bp->dev->hw_features &= ~NETIF_F_NTUPLE;
8543 bp->flags &= ~BNXT_FLAG_RFS;
8546 rc = bnxt_alloc_mem(bp, irq_re_init);
8548 netdev_err(bp->dev, "bnxt_alloc_mem err: %x\n", rc);
8549 goto open_err_free_mem;
8554 rc = bnxt_request_irq(bp);
8556 netdev_err(bp->dev, "bnxt_request_irq err: %x\n", rc);
8561 bnxt_enable_napi(bp);
8562 bnxt_debug_dev_init(bp);
8564 rc = bnxt_init_nic(bp, irq_re_init);
8566 netdev_err(bp->dev, "bnxt_init_nic err: %x\n", rc);
8571 mutex_lock(&bp->link_lock);
8572 rc = bnxt_update_phy_setting(bp);
8573 mutex_unlock(&bp->link_lock);
8575 netdev_warn(bp->dev, "failed to update phy settings\n");
8576 if (BNXT_SINGLE_PF(bp)) {
8577 bp->link_info.phy_retry = true;
8578 bp->link_info.phy_retry_expires =
8585 udp_tunnel_get_rx_info(bp->dev);
8587 set_bit(BNXT_STATE_OPEN, &bp->state);
8588 bnxt_enable_int(bp);
8589 /* Enable TX queues */
8591 mod_timer(&bp->timer, jiffies + bp->current_interval);
8592 /* Poll link status and check for SFP+ module status */
8593 bnxt_get_port_module_status(bp);
8595 /* VF-reps may need to be re-opened after the PF is re-opened */
8597 bnxt_vf_reps_open(bp);
8601 bnxt_debug_dev_exit(bp);
8602 bnxt_disable_napi(bp);
8610 bnxt_free_mem(bp, true);
8614 /* rtnl_lock held */
8615 int bnxt_open_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init)
8619 rc = __bnxt_open_nic(bp, irq_re_init, link_re_init);
8621 netdev_err(bp->dev, "nic open fail (rc: %x)\n", rc);
8627 /* rtnl_lock held, open the NIC half way by allocating all resources, but
8628 * NAPI, IRQ, and TX are not enabled. This is mainly used for offline
8631 int bnxt_half_open_nic(struct bnxt *bp)
8635 rc = bnxt_alloc_mem(bp, false);
8637 netdev_err(bp->dev, "bnxt_alloc_mem err: %x\n", rc);
8640 rc = bnxt_init_nic(bp, false);
8642 netdev_err(bp->dev, "bnxt_init_nic err: %x\n", rc);
8649 bnxt_free_mem(bp, false);
8654 /* rtnl_lock held, this call can only be made after a previous successful
8655 * call to bnxt_half_open_nic().
8657 void bnxt_half_close_nic(struct bnxt *bp)
8659 bnxt_hwrm_resource_free(bp, false, false);
8661 bnxt_free_mem(bp, false);
8664 static int bnxt_open(struct net_device *dev)
8666 struct bnxt *bp = netdev_priv(dev);
8669 bnxt_hwrm_if_change(bp, true);
8670 rc = __bnxt_open_nic(bp, true, true);
8672 bnxt_hwrm_if_change(bp, false);
8674 bnxt_hwmon_open(bp);
8679 static bool bnxt_drv_busy(struct bnxt *bp)
8681 return (test_bit(BNXT_STATE_IN_SP_TASK, &bp->state) ||
8682 test_bit(BNXT_STATE_READ_STATS, &bp->state));
8685 static void bnxt_get_ring_stats(struct bnxt *bp,
8686 struct rtnl_link_stats64 *stats);
8688 static void __bnxt_close_nic(struct bnxt *bp, bool irq_re_init,
8691 /* Close the VF-reps before closing PF */
8693 bnxt_vf_reps_close(bp);
8695 /* Change device state to avoid TX queue wake up's */
8696 bnxt_tx_disable(bp);
8698 clear_bit(BNXT_STATE_OPEN, &bp->state);
8699 smp_mb__after_atomic();
8700 while (bnxt_drv_busy(bp))
8703 /* Flush rings and and disable interrupts */
8704 bnxt_shutdown_nic(bp, irq_re_init);
8706 /* TODO CHIMP_FW: Link/PHY related cleanup if (link_re_init) */
8708 bnxt_debug_dev_exit(bp);
8709 bnxt_disable_napi(bp);
8710 del_timer_sync(&bp->timer);
8713 /* Save ring stats before shutdown */
8715 bnxt_get_ring_stats(bp, &bp->net_stats_prev);
8720 bnxt_free_mem(bp, irq_re_init);
8723 int bnxt_close_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init)
8727 #ifdef CONFIG_BNXT_SRIOV
8728 if (bp->sriov_cfg) {
8729 rc = wait_event_interruptible_timeout(bp->sriov_cfg_wait,
8731 BNXT_SRIOV_CFG_WAIT_TMO);
8733 netdev_warn(bp->dev, "timeout waiting for SRIOV config operation to complete!\n");
8736 __bnxt_close_nic(bp, irq_re_init, link_re_init);
8740 static int bnxt_close(struct net_device *dev)
8742 struct bnxt *bp = netdev_priv(dev);
8744 bnxt_hwmon_close(bp);
8745 bnxt_close_nic(bp, true, true);
8746 bnxt_hwrm_shutdown_link(bp);
8747 bnxt_hwrm_if_change(bp, false);
8751 static int bnxt_hwrm_port_phy_read(struct bnxt *bp, u16 phy_addr, u16 reg,
8754 struct hwrm_port_phy_mdio_read_output *resp = bp->hwrm_cmd_resp_addr;
8755 struct hwrm_port_phy_mdio_read_input req = {0};
8758 if (bp->hwrm_spec_code < 0x10a00)
8761 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_MDIO_READ, -1, -1);
8762 req.port_id = cpu_to_le16(bp->pf.port_id);
8763 req.phy_addr = phy_addr;
8764 req.reg_addr = cpu_to_le16(reg & 0x1f);
8765 if (mdio_phy_id_is_c45(phy_addr)) {
8767 req.phy_addr = mdio_phy_id_prtad(phy_addr);
8768 req.dev_addr = mdio_phy_id_devad(phy_addr);
8769 req.reg_addr = cpu_to_le16(reg);
8772 mutex_lock(&bp->hwrm_cmd_lock);
8773 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
8775 *val = le16_to_cpu(resp->reg_data);
8776 mutex_unlock(&bp->hwrm_cmd_lock);
8780 static int bnxt_hwrm_port_phy_write(struct bnxt *bp, u16 phy_addr, u16 reg,
8783 struct hwrm_port_phy_mdio_write_input req = {0};
8785 if (bp->hwrm_spec_code < 0x10a00)
8788 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_MDIO_WRITE, -1, -1);
8789 req.port_id = cpu_to_le16(bp->pf.port_id);
8790 req.phy_addr = phy_addr;
8791 req.reg_addr = cpu_to_le16(reg & 0x1f);
8792 if (mdio_phy_id_is_c45(phy_addr)) {
8794 req.phy_addr = mdio_phy_id_prtad(phy_addr);
8795 req.dev_addr = mdio_phy_id_devad(phy_addr);
8796 req.reg_addr = cpu_to_le16(reg);
8798 req.reg_data = cpu_to_le16(val);
8800 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
8803 /* rtnl_lock held */
8804 static int bnxt_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
8806 struct mii_ioctl_data *mdio = if_mii(ifr);
8807 struct bnxt *bp = netdev_priv(dev);
8812 mdio->phy_id = bp->link_info.phy_addr;
8818 if (!netif_running(dev))
8821 rc = bnxt_hwrm_port_phy_read(bp, mdio->phy_id, mdio->reg_num,
8823 mdio->val_out = mii_regval;
8828 if (!netif_running(dev))
8831 return bnxt_hwrm_port_phy_write(bp, mdio->phy_id, mdio->reg_num,
8841 static void bnxt_get_ring_stats(struct bnxt *bp,
8842 struct rtnl_link_stats64 *stats)
8847 for (i = 0; i < bp->cp_nr_rings; i++) {
8848 struct bnxt_napi *bnapi = bp->bnapi[i];
8849 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
8850 struct ctx_hw_stats *hw_stats = cpr->hw_stats;
8852 stats->rx_packets += le64_to_cpu(hw_stats->rx_ucast_pkts);
8853 stats->rx_packets += le64_to_cpu(hw_stats->rx_mcast_pkts);
8854 stats->rx_packets += le64_to_cpu(hw_stats->rx_bcast_pkts);
8856 stats->tx_packets += le64_to_cpu(hw_stats->tx_ucast_pkts);
8857 stats->tx_packets += le64_to_cpu(hw_stats->tx_mcast_pkts);
8858 stats->tx_packets += le64_to_cpu(hw_stats->tx_bcast_pkts);
8860 stats->rx_bytes += le64_to_cpu(hw_stats->rx_ucast_bytes);
8861 stats->rx_bytes += le64_to_cpu(hw_stats->rx_mcast_bytes);
8862 stats->rx_bytes += le64_to_cpu(hw_stats->rx_bcast_bytes);
8864 stats->tx_bytes += le64_to_cpu(hw_stats->tx_ucast_bytes);
8865 stats->tx_bytes += le64_to_cpu(hw_stats->tx_mcast_bytes);
8866 stats->tx_bytes += le64_to_cpu(hw_stats->tx_bcast_bytes);
8868 stats->rx_missed_errors +=
8869 le64_to_cpu(hw_stats->rx_discard_pkts);
8871 stats->multicast += le64_to_cpu(hw_stats->rx_mcast_pkts);
8873 stats->tx_dropped += le64_to_cpu(hw_stats->tx_drop_pkts);
8877 static void bnxt_add_prev_stats(struct bnxt *bp,
8878 struct rtnl_link_stats64 *stats)
8880 struct rtnl_link_stats64 *prev_stats = &bp->net_stats_prev;
8882 stats->rx_packets += prev_stats->rx_packets;
8883 stats->tx_packets += prev_stats->tx_packets;
8884 stats->rx_bytes += prev_stats->rx_bytes;
8885 stats->tx_bytes += prev_stats->tx_bytes;
8886 stats->rx_missed_errors += prev_stats->rx_missed_errors;
8887 stats->multicast += prev_stats->multicast;
8888 stats->tx_dropped += prev_stats->tx_dropped;
8892 bnxt_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
8894 struct bnxt *bp = netdev_priv(dev);
8896 set_bit(BNXT_STATE_READ_STATS, &bp->state);
8897 /* Make sure bnxt_close_nic() sees that we are reading stats before
8898 * we check the BNXT_STATE_OPEN flag.
8900 smp_mb__after_atomic();
8901 if (!test_bit(BNXT_STATE_OPEN, &bp->state)) {
8902 clear_bit(BNXT_STATE_READ_STATS, &bp->state);
8903 *stats = bp->net_stats_prev;
8907 bnxt_get_ring_stats(bp, stats);
8908 bnxt_add_prev_stats(bp, stats);
8910 if (bp->flags & BNXT_FLAG_PORT_STATS) {
8911 struct rx_port_stats *rx = bp->hw_rx_port_stats;
8912 struct tx_port_stats *tx = bp->hw_tx_port_stats;
8914 stats->rx_crc_errors = le64_to_cpu(rx->rx_fcs_err_frames);
8915 stats->rx_frame_errors = le64_to_cpu(rx->rx_align_err_frames);
8916 stats->rx_length_errors = le64_to_cpu(rx->rx_undrsz_frames) +
8917 le64_to_cpu(rx->rx_ovrsz_frames) +
8918 le64_to_cpu(rx->rx_runt_frames);
8919 stats->rx_errors = le64_to_cpu(rx->rx_false_carrier_frames) +
8920 le64_to_cpu(rx->rx_jbr_frames);
8921 stats->collisions = le64_to_cpu(tx->tx_total_collisions);
8922 stats->tx_fifo_errors = le64_to_cpu(tx->tx_fifo_underruns);
8923 stats->tx_errors = le64_to_cpu(tx->tx_err);
8925 clear_bit(BNXT_STATE_READ_STATS, &bp->state);
8928 static bool bnxt_mc_list_updated(struct bnxt *bp, u32 *rx_mask)
8930 struct net_device *dev = bp->dev;
8931 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
8932 struct netdev_hw_addr *ha;
8935 bool update = false;
8938 netdev_for_each_mc_addr(ha, dev) {
8939 if (mc_count >= BNXT_MAX_MC_ADDRS) {
8940 *rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST;
8941 vnic->mc_list_count = 0;
8945 if (!ether_addr_equal(haddr, vnic->mc_list + off)) {
8946 memcpy(vnic->mc_list + off, haddr, ETH_ALEN);
8953 *rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_MCAST;
8955 if (mc_count != vnic->mc_list_count) {
8956 vnic->mc_list_count = mc_count;
8962 static bool bnxt_uc_list_updated(struct bnxt *bp)
8964 struct net_device *dev = bp->dev;
8965 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
8966 struct netdev_hw_addr *ha;
8969 if (netdev_uc_count(dev) != (vnic->uc_filter_count - 1))
8972 netdev_for_each_uc_addr(ha, dev) {
8973 if (!ether_addr_equal(ha->addr, vnic->uc_list + off))
8981 static void bnxt_set_rx_mode(struct net_device *dev)
8983 struct bnxt *bp = netdev_priv(dev);
8984 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
8985 u32 mask = vnic->rx_mask;
8986 bool mc_update = false;
8989 if (!netif_running(dev))
8992 mask &= ~(CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS |
8993 CFA_L2_SET_RX_MASK_REQ_MASK_MCAST |
8994 CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST |
8995 CFA_L2_SET_RX_MASK_REQ_MASK_BCAST);
8997 if ((dev->flags & IFF_PROMISC) && bnxt_promisc_ok(bp))
8998 mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS;
9000 uc_update = bnxt_uc_list_updated(bp);
9002 if (dev->flags & IFF_BROADCAST)
9003 mask |= CFA_L2_SET_RX_MASK_REQ_MASK_BCAST;
9004 if (dev->flags & IFF_ALLMULTI) {
9005 mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST;
9006 vnic->mc_list_count = 0;
9008 mc_update = bnxt_mc_list_updated(bp, &mask);
9011 if (mask != vnic->rx_mask || uc_update || mc_update) {
9012 vnic->rx_mask = mask;
9014 set_bit(BNXT_RX_MASK_SP_EVENT, &bp->sp_event);
9015 bnxt_queue_sp_work(bp);
9019 static int bnxt_cfg_rx_mode(struct bnxt *bp)
9021 struct net_device *dev = bp->dev;
9022 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
9023 struct netdev_hw_addr *ha;
9027 netif_addr_lock_bh(dev);
9028 uc_update = bnxt_uc_list_updated(bp);
9029 netif_addr_unlock_bh(dev);
9034 mutex_lock(&bp->hwrm_cmd_lock);
9035 for (i = 1; i < vnic->uc_filter_count; i++) {
9036 struct hwrm_cfa_l2_filter_free_input req = {0};
9038 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_FILTER_FREE, -1,
9041 req.l2_filter_id = vnic->fw_l2_filter_id[i];
9043 rc = _hwrm_send_message(bp, &req, sizeof(req),
9046 mutex_unlock(&bp->hwrm_cmd_lock);
9048 vnic->uc_filter_count = 1;
9050 netif_addr_lock_bh(dev);
9051 if (netdev_uc_count(dev) > (BNXT_MAX_UC_ADDRS - 1)) {
9052 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS;
9054 netdev_for_each_uc_addr(ha, dev) {
9055 memcpy(vnic->uc_list + off, ha->addr, ETH_ALEN);
9057 vnic->uc_filter_count++;
9060 netif_addr_unlock_bh(dev);
9062 for (i = 1, off = 0; i < vnic->uc_filter_count; i++, off += ETH_ALEN) {
9063 rc = bnxt_hwrm_set_vnic_filter(bp, 0, i, vnic->uc_list + off);
9065 netdev_err(bp->dev, "HWRM vnic filter failure rc: %x\n",
9067 vnic->uc_filter_count = i;
9073 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, 0);
9074 if (rc && vnic->mc_list_count) {
9075 netdev_info(bp->dev, "Failed setting MC filters rc: %d, turning on ALL_MCAST mode\n",
9077 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST;
9078 vnic->mc_list_count = 0;
9079 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, 0);
9082 netdev_err(bp->dev, "HWRM cfa l2 rx mask failure rc: %d\n",
9088 static bool bnxt_can_reserve_rings(struct bnxt *bp)
9090 #ifdef CONFIG_BNXT_SRIOV
9091 if (BNXT_NEW_RM(bp) && BNXT_VF(bp)) {
9092 struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
9094 /* No minimum rings were provisioned by the PF. Don't
9095 * reserve rings by default when device is down.
9097 if (hw_resc->min_tx_rings || hw_resc->resv_tx_rings)
9100 if (!netif_running(bp->dev))
9107 /* If the chip and firmware supports RFS */
9108 static bool bnxt_rfs_supported(struct bnxt *bp)
9110 if (bp->flags & BNXT_FLAG_CHIP_P5) {
9111 if (bp->fw_cap & BNXT_FW_CAP_CFA_RFS_RING_TBL_IDX)
9115 if (BNXT_PF(bp) && !BNXT_CHIP_TYPE_NITRO_A0(bp))
9117 if (bp->flags & BNXT_FLAG_NEW_RSS_CAP)
9122 /* If runtime conditions support RFS */
9123 static bool bnxt_rfs_capable(struct bnxt *bp)
9125 #ifdef CONFIG_RFS_ACCEL
9126 int vnics, max_vnics, max_rss_ctxs;
9128 if (bp->flags & BNXT_FLAG_CHIP_P5)
9129 return bnxt_rfs_supported(bp);
9130 if (!(bp->flags & BNXT_FLAG_MSIX_CAP) || !bnxt_can_reserve_rings(bp))
9133 vnics = 1 + bp->rx_nr_rings;
9134 max_vnics = bnxt_get_max_func_vnics(bp);
9135 max_rss_ctxs = bnxt_get_max_func_rss_ctxs(bp);
9137 /* RSS contexts not a limiting factor */
9138 if (bp->flags & BNXT_FLAG_NEW_RSS_CAP)
9139 max_rss_ctxs = max_vnics;
9140 if (vnics > max_vnics || vnics > max_rss_ctxs) {
9141 if (bp->rx_nr_rings > 1)
9142 netdev_warn(bp->dev,
9143 "Not enough resources to support NTUPLE filters, enough resources for up to %d rx rings\n",
9144 min(max_rss_ctxs - 1, max_vnics - 1));
9148 if (!BNXT_NEW_RM(bp))
9151 if (vnics == bp->hw_resc.resv_vnics)
9154 bnxt_hwrm_reserve_rings(bp, 0, 0, 0, 0, 0, vnics);
9155 if (vnics <= bp->hw_resc.resv_vnics)
9158 netdev_warn(bp->dev, "Unable to reserve resources to support NTUPLE filters.\n");
9159 bnxt_hwrm_reserve_rings(bp, 0, 0, 0, 0, 0, 1);
9166 static netdev_features_t bnxt_fix_features(struct net_device *dev,
9167 netdev_features_t features)
9169 struct bnxt *bp = netdev_priv(dev);
9171 if ((features & NETIF_F_NTUPLE) && !bnxt_rfs_capable(bp))
9172 features &= ~NETIF_F_NTUPLE;
9174 if (bp->flags & BNXT_FLAG_NO_AGG_RINGS)
9175 features &= ~(NETIF_F_LRO | NETIF_F_GRO_HW);
9177 if (!(features & NETIF_F_GRO))
9178 features &= ~NETIF_F_GRO_HW;
9180 if (features & NETIF_F_GRO_HW)
9181 features &= ~NETIF_F_LRO;
9183 /* Both CTAG and STAG VLAN accelaration on the RX side have to be
9184 * turned on or off together.
9186 if ((features & (NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_STAG_RX)) !=
9187 (NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_STAG_RX)) {
9188 if (dev->features & NETIF_F_HW_VLAN_CTAG_RX)
9189 features &= ~(NETIF_F_HW_VLAN_CTAG_RX |
9190 NETIF_F_HW_VLAN_STAG_RX);
9192 features |= NETIF_F_HW_VLAN_CTAG_RX |
9193 NETIF_F_HW_VLAN_STAG_RX;
9195 #ifdef CONFIG_BNXT_SRIOV
9198 features &= ~(NETIF_F_HW_VLAN_CTAG_RX |
9199 NETIF_F_HW_VLAN_STAG_RX);
9206 static int bnxt_set_features(struct net_device *dev, netdev_features_t features)
9208 struct bnxt *bp = netdev_priv(dev);
9209 u32 flags = bp->flags;
9212 bool re_init = false;
9213 bool update_tpa = false;
9215 flags &= ~BNXT_FLAG_ALL_CONFIG_FEATS;
9216 if (features & NETIF_F_GRO_HW)
9217 flags |= BNXT_FLAG_GRO;
9218 else if (features & NETIF_F_LRO)
9219 flags |= BNXT_FLAG_LRO;
9221 if (bp->flags & BNXT_FLAG_NO_AGG_RINGS)
9222 flags &= ~BNXT_FLAG_TPA;
9224 if (features & NETIF_F_HW_VLAN_CTAG_RX)
9225 flags |= BNXT_FLAG_STRIP_VLAN;
9227 if (features & NETIF_F_NTUPLE)
9228 flags |= BNXT_FLAG_RFS;
9230 changes = flags ^ bp->flags;
9231 if (changes & BNXT_FLAG_TPA) {
9233 if ((bp->flags & BNXT_FLAG_TPA) == 0 ||
9234 (flags & BNXT_FLAG_TPA) == 0)
9238 if (changes & ~BNXT_FLAG_TPA)
9241 if (flags != bp->flags) {
9242 u32 old_flags = bp->flags;
9246 if (!test_bit(BNXT_STATE_OPEN, &bp->state)) {
9248 bnxt_set_ring_params(bp);
9253 bnxt_close_nic(bp, false, false);
9255 bnxt_set_ring_params(bp);
9257 return bnxt_open_nic(bp, false, false);
9260 rc = bnxt_set_tpa(bp,
9261 (flags & BNXT_FLAG_TPA) ?
9264 bp->flags = old_flags;
9270 static int bnxt_dbg_hwrm_ring_info_get(struct bnxt *bp, u8 ring_type,
9271 u32 ring_id, u32 *prod, u32 *cons)
9273 struct hwrm_dbg_ring_info_get_output *resp = bp->hwrm_cmd_resp_addr;
9274 struct hwrm_dbg_ring_info_get_input req = {0};
9277 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_DBG_RING_INFO_GET, -1, -1);
9278 req.ring_type = ring_type;
9279 req.fw_ring_id = cpu_to_le32(ring_id);
9280 mutex_lock(&bp->hwrm_cmd_lock);
9281 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
9283 *prod = le32_to_cpu(resp->producer_index);
9284 *cons = le32_to_cpu(resp->consumer_index);
9286 mutex_unlock(&bp->hwrm_cmd_lock);
9290 static void bnxt_dump_tx_sw_state(struct bnxt_napi *bnapi)
9292 struct bnxt_tx_ring_info *txr = bnapi->tx_ring;
9293 int i = bnapi->index;
9298 netdev_info(bnapi->bp->dev, "[%d]: tx{fw_ring: %d prod: %x cons: %x}\n",
9299 i, txr->tx_ring_struct.fw_ring_id, txr->tx_prod,
9303 static void bnxt_dump_rx_sw_state(struct bnxt_napi *bnapi)
9305 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
9306 int i = bnapi->index;
9311 netdev_info(bnapi->bp->dev, "[%d]: rx{fw_ring: %d prod: %x} rx_agg{fw_ring: %d agg_prod: %x sw_agg_prod: %x}\n",
9312 i, rxr->rx_ring_struct.fw_ring_id, rxr->rx_prod,
9313 rxr->rx_agg_ring_struct.fw_ring_id, rxr->rx_agg_prod,
9314 rxr->rx_sw_agg_prod);
9317 static void bnxt_dump_cp_sw_state(struct bnxt_napi *bnapi)
9319 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
9320 int i = bnapi->index;
9322 netdev_info(bnapi->bp->dev, "[%d]: cp{fw_ring: %d raw_cons: %x}\n",
9323 i, cpr->cp_ring_struct.fw_ring_id, cpr->cp_raw_cons);
9326 static void bnxt_dbg_dump_states(struct bnxt *bp)
9329 struct bnxt_napi *bnapi;
9331 for (i = 0; i < bp->cp_nr_rings; i++) {
9332 bnapi = bp->bnapi[i];
9333 if (netif_msg_drv(bp)) {
9334 bnxt_dump_tx_sw_state(bnapi);
9335 bnxt_dump_rx_sw_state(bnapi);
9336 bnxt_dump_cp_sw_state(bnapi);
9341 static void bnxt_reset_task(struct bnxt *bp, bool silent)
9344 bnxt_dbg_dump_states(bp);
9345 if (netif_running(bp->dev)) {
9350 bnxt_close_nic(bp, false, false);
9351 rc = bnxt_open_nic(bp, false, false);
9357 static void bnxt_tx_timeout(struct net_device *dev)
9359 struct bnxt *bp = netdev_priv(dev);
9361 netdev_err(bp->dev, "TX timeout detected, starting reset task!\n");
9362 set_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event);
9363 bnxt_queue_sp_work(bp);
9366 static void bnxt_timer(struct timer_list *t)
9368 struct bnxt *bp = from_timer(bp, t, timer);
9369 struct net_device *dev = bp->dev;
9371 if (!netif_running(dev))
9374 if (atomic_read(&bp->intr_sem) != 0)
9375 goto bnxt_restart_timer;
9377 if (bp->link_info.link_up && (bp->flags & BNXT_FLAG_PORT_STATS) &&
9378 bp->stats_coal_ticks) {
9379 set_bit(BNXT_PERIODIC_STATS_SP_EVENT, &bp->sp_event);
9380 bnxt_queue_sp_work(bp);
9383 if (bnxt_tc_flower_enabled(bp)) {
9384 set_bit(BNXT_FLOW_STATS_SP_EVENT, &bp->sp_event);
9385 bnxt_queue_sp_work(bp);
9388 if (bp->link_info.phy_retry) {
9389 if (time_after(jiffies, bp->link_info.phy_retry_expires)) {
9390 bp->link_info.phy_retry = 0;
9391 netdev_warn(bp->dev, "failed to update phy settings after maximum retries.\n");
9393 set_bit(BNXT_UPDATE_PHY_SP_EVENT, &bp->sp_event);
9394 bnxt_queue_sp_work(bp);
9398 if ((bp->flags & BNXT_FLAG_CHIP_P5) && netif_carrier_ok(dev)) {
9399 set_bit(BNXT_RING_COAL_NOW_SP_EVENT, &bp->sp_event);
9400 bnxt_queue_sp_work(bp);
9403 mod_timer(&bp->timer, jiffies + bp->current_interval);
9406 static void bnxt_rtnl_lock_sp(struct bnxt *bp)
9408 /* We are called from bnxt_sp_task which has BNXT_STATE_IN_SP_TASK
9409 * set. If the device is being closed, bnxt_close() may be holding
9410 * rtnl() and waiting for BNXT_STATE_IN_SP_TASK to clear. So we
9411 * must clear BNXT_STATE_IN_SP_TASK before holding rtnl().
9413 clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
9417 static void bnxt_rtnl_unlock_sp(struct bnxt *bp)
9419 set_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
9423 /* Only called from bnxt_sp_task() */
9424 static void bnxt_reset(struct bnxt *bp, bool silent)
9426 bnxt_rtnl_lock_sp(bp);
9427 if (test_bit(BNXT_STATE_OPEN, &bp->state))
9428 bnxt_reset_task(bp, silent);
9429 bnxt_rtnl_unlock_sp(bp);
9432 static void bnxt_chk_missed_irq(struct bnxt *bp)
9436 if (!(bp->flags & BNXT_FLAG_CHIP_P5))
9439 for (i = 0; i < bp->cp_nr_rings; i++) {
9440 struct bnxt_napi *bnapi = bp->bnapi[i];
9441 struct bnxt_cp_ring_info *cpr;
9448 cpr = &bnapi->cp_ring;
9449 for (j = 0; j < 2; j++) {
9450 struct bnxt_cp_ring_info *cpr2 = cpr->cp_ring_arr[j];
9453 if (!cpr2 || cpr2->has_more_work ||
9454 !bnxt_has_work(bp, cpr2))
9457 if (cpr2->cp_raw_cons != cpr2->last_cp_raw_cons) {
9458 cpr2->last_cp_raw_cons = cpr2->cp_raw_cons;
9461 fw_ring_id = cpr2->cp_ring_struct.fw_ring_id;
9462 bnxt_dbg_hwrm_ring_info_get(bp,
9463 DBG_RING_INFO_GET_REQ_RING_TYPE_L2_CMPL,
9464 fw_ring_id, &val[0], &val[1]);
9470 static void bnxt_cfg_ntp_filters(struct bnxt *);
9472 static void bnxt_sp_task(struct work_struct *work)
9474 struct bnxt *bp = container_of(work, struct bnxt, sp_task);
9476 set_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
9477 smp_mb__after_atomic();
9478 if (!test_bit(BNXT_STATE_OPEN, &bp->state)) {
9479 clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
9483 if (test_and_clear_bit(BNXT_RX_MASK_SP_EVENT, &bp->sp_event))
9484 bnxt_cfg_rx_mode(bp);
9486 if (test_and_clear_bit(BNXT_RX_NTP_FLTR_SP_EVENT, &bp->sp_event))
9487 bnxt_cfg_ntp_filters(bp);
9488 if (test_and_clear_bit(BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT, &bp->sp_event))
9489 bnxt_hwrm_exec_fwd_req(bp);
9490 if (test_and_clear_bit(BNXT_VXLAN_ADD_PORT_SP_EVENT, &bp->sp_event)) {
9491 bnxt_hwrm_tunnel_dst_port_alloc(
9493 TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN);
9495 if (test_and_clear_bit(BNXT_VXLAN_DEL_PORT_SP_EVENT, &bp->sp_event)) {
9496 bnxt_hwrm_tunnel_dst_port_free(
9497 bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN);
9499 if (test_and_clear_bit(BNXT_GENEVE_ADD_PORT_SP_EVENT, &bp->sp_event)) {
9500 bnxt_hwrm_tunnel_dst_port_alloc(
9502 TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE);
9504 if (test_and_clear_bit(BNXT_GENEVE_DEL_PORT_SP_EVENT, &bp->sp_event)) {
9505 bnxt_hwrm_tunnel_dst_port_free(
9506 bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE);
9508 if (test_and_clear_bit(BNXT_PERIODIC_STATS_SP_EVENT, &bp->sp_event)) {
9509 bnxt_hwrm_port_qstats(bp);
9510 bnxt_hwrm_port_qstats_ext(bp);
9511 bnxt_hwrm_pcie_qstats(bp);
9514 if (test_and_clear_bit(BNXT_LINK_CHNG_SP_EVENT, &bp->sp_event)) {
9517 mutex_lock(&bp->link_lock);
9518 if (test_and_clear_bit(BNXT_LINK_SPEED_CHNG_SP_EVENT,
9520 bnxt_hwrm_phy_qcaps(bp);
9522 rc = bnxt_update_link(bp, true);
9523 mutex_unlock(&bp->link_lock);
9525 netdev_err(bp->dev, "SP task can't update link (rc: %x)\n",
9528 if (test_and_clear_bit(BNXT_UPDATE_PHY_SP_EVENT, &bp->sp_event)) {
9531 mutex_lock(&bp->link_lock);
9532 rc = bnxt_update_phy_setting(bp);
9533 mutex_unlock(&bp->link_lock);
9535 netdev_warn(bp->dev, "update phy settings retry failed\n");
9537 bp->link_info.phy_retry = false;
9538 netdev_info(bp->dev, "update phy settings retry succeeded\n");
9541 if (test_and_clear_bit(BNXT_HWRM_PORT_MODULE_SP_EVENT, &bp->sp_event)) {
9542 mutex_lock(&bp->link_lock);
9543 bnxt_get_port_module_status(bp);
9544 mutex_unlock(&bp->link_lock);
9547 if (test_and_clear_bit(BNXT_FLOW_STATS_SP_EVENT, &bp->sp_event))
9548 bnxt_tc_flow_stats_work(bp);
9550 if (test_and_clear_bit(BNXT_RING_COAL_NOW_SP_EVENT, &bp->sp_event))
9551 bnxt_chk_missed_irq(bp);
9553 /* These functions below will clear BNXT_STATE_IN_SP_TASK. They
9554 * must be the last functions to be called before exiting.
9556 if (test_and_clear_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event))
9557 bnxt_reset(bp, false);
9559 if (test_and_clear_bit(BNXT_RESET_TASK_SILENT_SP_EVENT, &bp->sp_event))
9560 bnxt_reset(bp, true);
9562 smp_mb__before_atomic();
9563 clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
9566 /* Under rtnl_lock */
9567 int bnxt_check_rings(struct bnxt *bp, int tx, int rx, bool sh, int tcs,
9570 int max_rx, max_tx, tx_sets = 1;
9571 int tx_rings_needed, stats;
9578 rc = bnxt_get_max_rings(bp, &max_rx, &max_tx, sh);
9585 tx_rings_needed = tx * tx_sets + tx_xdp;
9586 if (max_tx < tx_rings_needed)
9590 if (bp->flags & BNXT_FLAG_RFS)
9593 if (bp->flags & BNXT_FLAG_AGG_RINGS)
9595 cp = sh ? max_t(int, tx_rings_needed, rx) : tx_rings_needed + rx;
9597 if (BNXT_NEW_RM(bp)) {
9598 cp += bnxt_get_ulp_msix_num(bp);
9599 stats += bnxt_get_ulp_stat_ctxs(bp);
9601 return bnxt_hwrm_check_rings(bp, tx_rings_needed, rx_rings, rx, cp,
9605 static void bnxt_unmap_bars(struct bnxt *bp, struct pci_dev *pdev)
9608 pci_iounmap(pdev, bp->bar2);
9613 pci_iounmap(pdev, bp->bar1);
9618 pci_iounmap(pdev, bp->bar0);
9623 static void bnxt_cleanup_pci(struct bnxt *bp)
9625 bnxt_unmap_bars(bp, bp->pdev);
9626 pci_release_regions(bp->pdev);
9627 pci_disable_device(bp->pdev);
9630 static void bnxt_init_dflt_coal(struct bnxt *bp)
9632 struct bnxt_coal *coal;
9634 /* Tick values in micro seconds.
9635 * 1 coal_buf x bufs_per_record = 1 completion record.
9637 coal = &bp->rx_coal;
9638 coal->coal_ticks = 10;
9639 coal->coal_bufs = 30;
9640 coal->coal_ticks_irq = 1;
9641 coal->coal_bufs_irq = 2;
9642 coal->idle_thresh = 50;
9643 coal->bufs_per_record = 2;
9644 coal->budget = 64; /* NAPI budget */
9646 coal = &bp->tx_coal;
9647 coal->coal_ticks = 28;
9648 coal->coal_bufs = 30;
9649 coal->coal_ticks_irq = 2;
9650 coal->coal_bufs_irq = 2;
9651 coal->bufs_per_record = 1;
9653 bp->stats_coal_ticks = BNXT_DEF_STATS_COAL_TICKS;
9656 static int bnxt_init_board(struct pci_dev *pdev, struct net_device *dev)
9659 struct bnxt *bp = netdev_priv(dev);
9661 SET_NETDEV_DEV(dev, &pdev->dev);
9663 /* enable device (incl. PCI PM wakeup), and bus-mastering */
9664 rc = pci_enable_device(pdev);
9666 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
9670 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
9672 "Cannot find PCI device base address, aborting\n");
9674 goto init_err_disable;
9677 rc = pci_request_regions(pdev, DRV_MODULE_NAME);
9679 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n");
9680 goto init_err_disable;
9683 if (dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)) != 0 &&
9684 dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)) != 0) {
9685 dev_err(&pdev->dev, "System does not support DMA, aborting\n");
9686 goto init_err_disable;
9689 pci_set_master(pdev);
9694 bp->bar0 = pci_ioremap_bar(pdev, 0);
9696 dev_err(&pdev->dev, "Cannot map device registers, aborting\n");
9698 goto init_err_release;
9701 bp->bar1 = pci_ioremap_bar(pdev, 2);
9703 dev_err(&pdev->dev, "Cannot map doorbell registers, aborting\n");
9705 goto init_err_release;
9708 bp->bar2 = pci_ioremap_bar(pdev, 4);
9710 dev_err(&pdev->dev, "Cannot map bar4 registers, aborting\n");
9712 goto init_err_release;
9715 pci_enable_pcie_error_reporting(pdev);
9717 INIT_WORK(&bp->sp_task, bnxt_sp_task);
9719 spin_lock_init(&bp->ntp_fltr_lock);
9720 #if BITS_PER_LONG == 32
9721 spin_lock_init(&bp->db_lock);
9724 bp->rx_ring_size = BNXT_DEFAULT_RX_RING_SIZE;
9725 bp->tx_ring_size = BNXT_DEFAULT_TX_RING_SIZE;
9727 bnxt_init_dflt_coal(bp);
9729 timer_setup(&bp->timer, bnxt_timer, 0);
9730 bp->current_interval = BNXT_TIMER_INTERVAL;
9732 clear_bit(BNXT_STATE_OPEN, &bp->state);
9736 bnxt_unmap_bars(bp, pdev);
9737 pci_release_regions(pdev);
9740 pci_disable_device(pdev);
9746 /* rtnl_lock held */
9747 static int bnxt_change_mac_addr(struct net_device *dev, void *p)
9749 struct sockaddr *addr = p;
9750 struct bnxt *bp = netdev_priv(dev);
9753 if (!is_valid_ether_addr(addr->sa_data))
9754 return -EADDRNOTAVAIL;
9756 if (ether_addr_equal(addr->sa_data, dev->dev_addr))
9759 rc = bnxt_approve_mac(bp, addr->sa_data, true);
9763 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
9764 if (netif_running(dev)) {
9765 bnxt_close_nic(bp, false, false);
9766 rc = bnxt_open_nic(bp, false, false);
9772 /* rtnl_lock held */
9773 static int bnxt_change_mtu(struct net_device *dev, int new_mtu)
9775 struct bnxt *bp = netdev_priv(dev);
9777 if (netif_running(dev))
9778 bnxt_close_nic(bp, false, false);
9781 bnxt_set_ring_params(bp);
9783 if (netif_running(dev))
9784 return bnxt_open_nic(bp, false, false);
9789 int bnxt_setup_mq_tc(struct net_device *dev, u8 tc)
9791 struct bnxt *bp = netdev_priv(dev);
9795 if (tc > bp->max_tc) {
9796 netdev_err(dev, "Too many traffic classes requested: %d. Max supported is %d.\n",
9801 if (netdev_get_num_tc(dev) == tc)
9804 if (bp->flags & BNXT_FLAG_SHARED_RINGS)
9807 rc = bnxt_check_rings(bp, bp->tx_nr_rings_per_tc, bp->rx_nr_rings,
9808 sh, tc, bp->tx_nr_rings_xdp);
9812 /* Needs to close the device and do hw resource re-allocations */
9813 if (netif_running(bp->dev))
9814 bnxt_close_nic(bp, true, false);
9817 bp->tx_nr_rings = bp->tx_nr_rings_per_tc * tc;
9818 netdev_set_num_tc(dev, tc);
9820 bp->tx_nr_rings = bp->tx_nr_rings_per_tc;
9821 netdev_reset_tc(dev);
9823 bp->tx_nr_rings += bp->tx_nr_rings_xdp;
9824 bp->cp_nr_rings = sh ? max_t(int, bp->tx_nr_rings, bp->rx_nr_rings) :
9825 bp->tx_nr_rings + bp->rx_nr_rings;
9827 if (netif_running(bp->dev))
9828 return bnxt_open_nic(bp, true, false);
9833 static int bnxt_setup_tc_block_cb(enum tc_setup_type type, void *type_data,
9836 struct bnxt *bp = cb_priv;
9838 if (!bnxt_tc_flower_enabled(bp) ||
9839 !tc_cls_can_offload_and_chain0(bp->dev, type_data))
9843 case TC_SETUP_CLSFLOWER:
9844 return bnxt_tc_setup_flower(bp, bp->pf.fw_fid, type_data);
9850 static int bnxt_setup_tc_block(struct net_device *dev,
9851 struct tc_block_offload *f)
9853 struct bnxt *bp = netdev_priv(dev);
9855 if (f->binder_type != TCF_BLOCK_BINDER_TYPE_CLSACT_INGRESS)
9858 switch (f->command) {
9860 return tcf_block_cb_register(f->block, bnxt_setup_tc_block_cb,
9862 case TC_BLOCK_UNBIND:
9863 tcf_block_cb_unregister(f->block, bnxt_setup_tc_block_cb, bp);
9870 static int bnxt_setup_tc(struct net_device *dev, enum tc_setup_type type,
9874 case TC_SETUP_BLOCK:
9875 return bnxt_setup_tc_block(dev, type_data);
9876 case TC_SETUP_QDISC_MQPRIO: {
9877 struct tc_mqprio_qopt *mqprio = type_data;
9879 mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS;
9881 return bnxt_setup_mq_tc(dev, mqprio->num_tc);
9888 #ifdef CONFIG_RFS_ACCEL
9889 static bool bnxt_fltr_match(struct bnxt_ntuple_filter *f1,
9890 struct bnxt_ntuple_filter *f2)
9892 struct flow_keys *keys1 = &f1->fkeys;
9893 struct flow_keys *keys2 = &f2->fkeys;
9895 if (keys1->addrs.v4addrs.src == keys2->addrs.v4addrs.src &&
9896 keys1->addrs.v4addrs.dst == keys2->addrs.v4addrs.dst &&
9897 keys1->ports.ports == keys2->ports.ports &&
9898 keys1->basic.ip_proto == keys2->basic.ip_proto &&
9899 keys1->basic.n_proto == keys2->basic.n_proto &&
9900 keys1->control.flags == keys2->control.flags &&
9901 ether_addr_equal(f1->src_mac_addr, f2->src_mac_addr) &&
9902 ether_addr_equal(f1->dst_mac_addr, f2->dst_mac_addr))
9908 static int bnxt_rx_flow_steer(struct net_device *dev, const struct sk_buff *skb,
9909 u16 rxq_index, u32 flow_id)
9911 struct bnxt *bp = netdev_priv(dev);
9912 struct bnxt_ntuple_filter *fltr, *new_fltr;
9913 struct flow_keys *fkeys;
9914 struct ethhdr *eth = (struct ethhdr *)skb_mac_header(skb);
9915 int rc = 0, idx, bit_id, l2_idx = 0;
9916 struct hlist_head *head;
9918 if (!ether_addr_equal(dev->dev_addr, eth->h_dest)) {
9919 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
9922 netif_addr_lock_bh(dev);
9923 for (j = 0; j < vnic->uc_filter_count; j++, off += ETH_ALEN) {
9924 if (ether_addr_equal(eth->h_dest,
9925 vnic->uc_list + off)) {
9930 netif_addr_unlock_bh(dev);
9934 new_fltr = kzalloc(sizeof(*new_fltr), GFP_ATOMIC);
9938 fkeys = &new_fltr->fkeys;
9939 if (!skb_flow_dissect_flow_keys(skb, fkeys, 0)) {
9940 rc = -EPROTONOSUPPORT;
9944 if ((fkeys->basic.n_proto != htons(ETH_P_IP) &&
9945 fkeys->basic.n_proto != htons(ETH_P_IPV6)) ||
9946 ((fkeys->basic.ip_proto != IPPROTO_TCP) &&
9947 (fkeys->basic.ip_proto != IPPROTO_UDP))) {
9948 rc = -EPROTONOSUPPORT;
9951 if (fkeys->basic.n_proto == htons(ETH_P_IPV6) &&
9952 bp->hwrm_spec_code < 0x10601) {
9953 rc = -EPROTONOSUPPORT;
9956 if ((fkeys->control.flags & FLOW_DIS_ENCAPSULATION) &&
9957 bp->hwrm_spec_code < 0x10601) {
9958 rc = -EPROTONOSUPPORT;
9962 memcpy(new_fltr->dst_mac_addr, eth->h_dest, ETH_ALEN);
9963 memcpy(new_fltr->src_mac_addr, eth->h_source, ETH_ALEN);
9965 idx = skb_get_hash_raw(skb) & BNXT_NTP_FLTR_HASH_MASK;
9966 head = &bp->ntp_fltr_hash_tbl[idx];
9968 hlist_for_each_entry_rcu(fltr, head, hash) {
9969 if (bnxt_fltr_match(fltr, new_fltr)) {
9977 spin_lock_bh(&bp->ntp_fltr_lock);
9978 bit_id = bitmap_find_free_region(bp->ntp_fltr_bmap,
9979 BNXT_NTP_FLTR_MAX_FLTR, 0);
9981 spin_unlock_bh(&bp->ntp_fltr_lock);
9986 new_fltr->sw_id = (u16)bit_id;
9987 new_fltr->flow_id = flow_id;
9988 new_fltr->l2_fltr_idx = l2_idx;
9989 new_fltr->rxq = rxq_index;
9990 hlist_add_head_rcu(&new_fltr->hash, head);
9991 bp->ntp_fltr_count++;
9992 spin_unlock_bh(&bp->ntp_fltr_lock);
9994 set_bit(BNXT_RX_NTP_FLTR_SP_EVENT, &bp->sp_event);
9995 bnxt_queue_sp_work(bp);
9997 return new_fltr->sw_id;
10004 static void bnxt_cfg_ntp_filters(struct bnxt *bp)
10008 for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) {
10009 struct hlist_head *head;
10010 struct hlist_node *tmp;
10011 struct bnxt_ntuple_filter *fltr;
10014 head = &bp->ntp_fltr_hash_tbl[i];
10015 hlist_for_each_entry_safe(fltr, tmp, head, hash) {
10018 if (test_bit(BNXT_FLTR_VALID, &fltr->state)) {
10019 if (rps_may_expire_flow(bp->dev, fltr->rxq,
10022 bnxt_hwrm_cfa_ntuple_filter_free(bp,
10027 rc = bnxt_hwrm_cfa_ntuple_filter_alloc(bp,
10032 set_bit(BNXT_FLTR_VALID, &fltr->state);
10036 spin_lock_bh(&bp->ntp_fltr_lock);
10037 hlist_del_rcu(&fltr->hash);
10038 bp->ntp_fltr_count--;
10039 spin_unlock_bh(&bp->ntp_fltr_lock);
10041 clear_bit(fltr->sw_id, bp->ntp_fltr_bmap);
10046 if (test_and_clear_bit(BNXT_HWRM_PF_UNLOAD_SP_EVENT, &bp->sp_event))
10047 netdev_info(bp->dev, "Receive PF driver unload event!");
10052 static void bnxt_cfg_ntp_filters(struct bnxt *bp)
10056 #endif /* CONFIG_RFS_ACCEL */
10058 static void bnxt_udp_tunnel_add(struct net_device *dev,
10059 struct udp_tunnel_info *ti)
10061 struct bnxt *bp = netdev_priv(dev);
10063 if (ti->sa_family != AF_INET6 && ti->sa_family != AF_INET)
10066 if (!netif_running(dev))
10069 switch (ti->type) {
10070 case UDP_TUNNEL_TYPE_VXLAN:
10071 if (bp->vxlan_port_cnt && bp->vxlan_port != ti->port)
10074 bp->vxlan_port_cnt++;
10075 if (bp->vxlan_port_cnt == 1) {
10076 bp->vxlan_port = ti->port;
10077 set_bit(BNXT_VXLAN_ADD_PORT_SP_EVENT, &bp->sp_event);
10078 bnxt_queue_sp_work(bp);
10081 case UDP_TUNNEL_TYPE_GENEVE:
10082 if (bp->nge_port_cnt && bp->nge_port != ti->port)
10085 bp->nge_port_cnt++;
10086 if (bp->nge_port_cnt == 1) {
10087 bp->nge_port = ti->port;
10088 set_bit(BNXT_GENEVE_ADD_PORT_SP_EVENT, &bp->sp_event);
10095 bnxt_queue_sp_work(bp);
10098 static void bnxt_udp_tunnel_del(struct net_device *dev,
10099 struct udp_tunnel_info *ti)
10101 struct bnxt *bp = netdev_priv(dev);
10103 if (ti->sa_family != AF_INET6 && ti->sa_family != AF_INET)
10106 if (!netif_running(dev))
10109 switch (ti->type) {
10110 case UDP_TUNNEL_TYPE_VXLAN:
10111 if (!bp->vxlan_port_cnt || bp->vxlan_port != ti->port)
10113 bp->vxlan_port_cnt--;
10115 if (bp->vxlan_port_cnt != 0)
10118 set_bit(BNXT_VXLAN_DEL_PORT_SP_EVENT, &bp->sp_event);
10120 case UDP_TUNNEL_TYPE_GENEVE:
10121 if (!bp->nge_port_cnt || bp->nge_port != ti->port)
10123 bp->nge_port_cnt--;
10125 if (bp->nge_port_cnt != 0)
10128 set_bit(BNXT_GENEVE_DEL_PORT_SP_EVENT, &bp->sp_event);
10134 bnxt_queue_sp_work(bp);
10137 static int bnxt_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq,
10138 struct net_device *dev, u32 filter_mask,
10141 struct bnxt *bp = netdev_priv(dev);
10143 return ndo_dflt_bridge_getlink(skb, pid, seq, dev, bp->br_mode, 0, 0,
10144 nlflags, filter_mask, NULL);
10147 static int bnxt_bridge_setlink(struct net_device *dev, struct nlmsghdr *nlh,
10148 u16 flags, struct netlink_ext_ack *extack)
10150 struct bnxt *bp = netdev_priv(dev);
10151 struct nlattr *attr, *br_spec;
10154 if (bp->hwrm_spec_code < 0x10708 || !BNXT_SINGLE_PF(bp))
10155 return -EOPNOTSUPP;
10157 br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC);
10161 nla_for_each_nested(attr, br_spec, rem) {
10164 if (nla_type(attr) != IFLA_BRIDGE_MODE)
10167 if (nla_len(attr) < sizeof(mode))
10170 mode = nla_get_u16(attr);
10171 if (mode == bp->br_mode)
10174 rc = bnxt_hwrm_set_br_mode(bp, mode);
10176 bp->br_mode = mode;
10182 int bnxt_get_port_parent_id(struct net_device *dev,
10183 struct netdev_phys_item_id *ppid)
10185 struct bnxt *bp = netdev_priv(dev);
10187 if (bp->eswitch_mode != DEVLINK_ESWITCH_MODE_SWITCHDEV)
10188 return -EOPNOTSUPP;
10190 /* The PF and it's VF-reps only support the switchdev framework */
10192 return -EOPNOTSUPP;
10194 ppid->id_len = sizeof(bp->switch_id);
10195 memcpy(ppid->id, bp->switch_id, ppid->id_len);
10200 static struct devlink_port *bnxt_get_devlink_port(struct net_device *dev)
10202 struct bnxt *bp = netdev_priv(dev);
10204 return &bp->dl_port;
10207 static const struct net_device_ops bnxt_netdev_ops = {
10208 .ndo_open = bnxt_open,
10209 .ndo_start_xmit = bnxt_start_xmit,
10210 .ndo_stop = bnxt_close,
10211 .ndo_get_stats64 = bnxt_get_stats64,
10212 .ndo_set_rx_mode = bnxt_set_rx_mode,
10213 .ndo_do_ioctl = bnxt_ioctl,
10214 .ndo_validate_addr = eth_validate_addr,
10215 .ndo_set_mac_address = bnxt_change_mac_addr,
10216 .ndo_change_mtu = bnxt_change_mtu,
10217 .ndo_fix_features = bnxt_fix_features,
10218 .ndo_set_features = bnxt_set_features,
10219 .ndo_tx_timeout = bnxt_tx_timeout,
10220 #ifdef CONFIG_BNXT_SRIOV
10221 .ndo_get_vf_config = bnxt_get_vf_config,
10222 .ndo_set_vf_mac = bnxt_set_vf_mac,
10223 .ndo_set_vf_vlan = bnxt_set_vf_vlan,
10224 .ndo_set_vf_rate = bnxt_set_vf_bw,
10225 .ndo_set_vf_link_state = bnxt_set_vf_link_state,
10226 .ndo_set_vf_spoofchk = bnxt_set_vf_spoofchk,
10227 .ndo_set_vf_trust = bnxt_set_vf_trust,
10229 .ndo_setup_tc = bnxt_setup_tc,
10230 #ifdef CONFIG_RFS_ACCEL
10231 .ndo_rx_flow_steer = bnxt_rx_flow_steer,
10233 .ndo_udp_tunnel_add = bnxt_udp_tunnel_add,
10234 .ndo_udp_tunnel_del = bnxt_udp_tunnel_del,
10235 .ndo_bpf = bnxt_xdp,
10236 .ndo_bridge_getlink = bnxt_bridge_getlink,
10237 .ndo_bridge_setlink = bnxt_bridge_setlink,
10238 .ndo_get_devlink_port = bnxt_get_devlink_port,
10241 static void bnxt_remove_one(struct pci_dev *pdev)
10243 struct net_device *dev = pci_get_drvdata(pdev);
10244 struct bnxt *bp = netdev_priv(dev);
10247 bnxt_sriov_disable(bp);
10248 bnxt_dl_unregister(bp);
10251 pci_disable_pcie_error_reporting(pdev);
10252 unregister_netdev(dev);
10253 bnxt_shutdown_tc(bp);
10254 bnxt_cancel_sp_work(bp);
10257 bnxt_clear_int_mode(bp);
10258 bnxt_hwrm_func_drv_unrgtr(bp);
10259 bnxt_free_hwrm_resources(bp);
10260 bnxt_free_hwrm_short_cmd_req(bp);
10261 bnxt_ethtool_free(bp);
10265 bnxt_free_ctx_mem(bp);
10268 bnxt_cleanup_pci(bp);
10269 bnxt_free_port_stats(bp);
10273 static int bnxt_probe_phy(struct bnxt *bp)
10276 struct bnxt_link_info *link_info = &bp->link_info;
10278 rc = bnxt_hwrm_phy_qcaps(bp);
10280 netdev_err(bp->dev, "Probe phy can't get phy capabilities (rc: %x)\n",
10284 mutex_init(&bp->link_lock);
10286 rc = bnxt_update_link(bp, false);
10288 netdev_err(bp->dev, "Probe phy can't update link (rc: %x)\n",
10293 /* Older firmware does not have supported_auto_speeds, so assume
10294 * that all supported speeds can be autonegotiated.
10296 if (link_info->auto_link_speeds && !link_info->support_auto_speeds)
10297 link_info->support_auto_speeds = link_info->support_speeds;
10299 /*initialize the ethool setting copy with NVM settings */
10300 if (BNXT_AUTO_MODE(link_info->auto_mode)) {
10301 link_info->autoneg = BNXT_AUTONEG_SPEED;
10302 if (bp->hwrm_spec_code >= 0x10201) {
10303 if (link_info->auto_pause_setting &
10304 PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE)
10305 link_info->autoneg |= BNXT_AUTONEG_FLOW_CTRL;
10307 link_info->autoneg |= BNXT_AUTONEG_FLOW_CTRL;
10309 link_info->advertising = link_info->auto_link_speeds;
10311 link_info->req_link_speed = link_info->force_link_speed;
10312 link_info->req_duplex = link_info->duplex_setting;
10314 if (link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL)
10315 link_info->req_flow_ctrl =
10316 link_info->auto_pause_setting & BNXT_LINK_PAUSE_BOTH;
10318 link_info->req_flow_ctrl = link_info->force_pause_setting;
10322 static int bnxt_get_max_irq(struct pci_dev *pdev)
10326 if (!pdev->msix_cap)
10329 pci_read_config_word(pdev, pdev->msix_cap + PCI_MSIX_FLAGS, &ctrl);
10330 return (ctrl & PCI_MSIX_FLAGS_QSIZE) + 1;
10333 static void _bnxt_get_max_rings(struct bnxt *bp, int *max_rx, int *max_tx,
10336 struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
10337 int max_ring_grps = 0, max_irq;
10339 *max_tx = hw_resc->max_tx_rings;
10340 *max_rx = hw_resc->max_rx_rings;
10341 *max_cp = bnxt_get_max_func_cp_rings_for_en(bp);
10342 max_irq = min_t(int, bnxt_get_max_func_irqs(bp) -
10343 bnxt_get_ulp_msix_num(bp),
10344 hw_resc->max_stat_ctxs - bnxt_get_ulp_stat_ctxs(bp));
10345 if (!(bp->flags & BNXT_FLAG_CHIP_P5))
10346 *max_cp = min_t(int, *max_cp, max_irq);
10347 max_ring_grps = hw_resc->max_hw_ring_grps;
10348 if (BNXT_CHIP_TYPE_NITRO_A0(bp) && BNXT_PF(bp)) {
10352 if (bp->flags & BNXT_FLAG_AGG_RINGS)
10354 if (bp->flags & BNXT_FLAG_CHIP_P5) {
10355 bnxt_trim_rings(bp, max_rx, max_tx, *max_cp, false);
10356 /* On P5 chips, max_cp output param should be available NQs */
10359 *max_rx = min_t(int, *max_rx, max_ring_grps);
10362 int bnxt_get_max_rings(struct bnxt *bp, int *max_rx, int *max_tx, bool shared)
10366 _bnxt_get_max_rings(bp, &rx, &tx, &cp);
10369 if (!rx || !tx || !cp)
10372 return bnxt_trim_rings(bp, max_rx, max_tx, cp, shared);
10375 static int bnxt_get_dflt_rings(struct bnxt *bp, int *max_rx, int *max_tx,
10380 rc = bnxt_get_max_rings(bp, max_rx, max_tx, shared);
10381 if (rc && (bp->flags & BNXT_FLAG_AGG_RINGS)) {
10382 /* Not enough rings, try disabling agg rings. */
10383 bp->flags &= ~BNXT_FLAG_AGG_RINGS;
10384 rc = bnxt_get_max_rings(bp, max_rx, max_tx, shared);
10386 /* set BNXT_FLAG_AGG_RINGS back for consistency */
10387 bp->flags |= BNXT_FLAG_AGG_RINGS;
10390 bp->flags |= BNXT_FLAG_NO_AGG_RINGS;
10391 bp->dev->hw_features &= ~(NETIF_F_LRO | NETIF_F_GRO_HW);
10392 bp->dev->features &= ~(NETIF_F_LRO | NETIF_F_GRO_HW);
10393 bnxt_set_ring_params(bp);
10396 if (bp->flags & BNXT_FLAG_ROCE_CAP) {
10397 int max_cp, max_stat, max_irq;
10399 /* Reserve minimum resources for RoCE */
10400 max_cp = bnxt_get_max_func_cp_rings(bp);
10401 max_stat = bnxt_get_max_func_stat_ctxs(bp);
10402 max_irq = bnxt_get_max_func_irqs(bp);
10403 if (max_cp <= BNXT_MIN_ROCE_CP_RINGS ||
10404 max_irq <= BNXT_MIN_ROCE_CP_RINGS ||
10405 max_stat <= BNXT_MIN_ROCE_STAT_CTXS)
10408 max_cp -= BNXT_MIN_ROCE_CP_RINGS;
10409 max_irq -= BNXT_MIN_ROCE_CP_RINGS;
10410 max_stat -= BNXT_MIN_ROCE_STAT_CTXS;
10411 max_cp = min_t(int, max_cp, max_irq);
10412 max_cp = min_t(int, max_cp, max_stat);
10413 rc = bnxt_trim_rings(bp, max_rx, max_tx, max_cp, shared);
10420 /* In initial default shared ring setting, each shared ring must have a
10423 static void bnxt_trim_dflt_sh_rings(struct bnxt *bp)
10425 bp->cp_nr_rings = min_t(int, bp->tx_nr_rings_per_tc, bp->rx_nr_rings);
10426 bp->rx_nr_rings = bp->cp_nr_rings;
10427 bp->tx_nr_rings_per_tc = bp->cp_nr_rings;
10428 bp->tx_nr_rings = bp->tx_nr_rings_per_tc;
10431 static int bnxt_set_dflt_rings(struct bnxt *bp, bool sh)
10433 int dflt_rings, max_rx_rings, max_tx_rings, rc;
10435 if (!bnxt_can_reserve_rings(bp))
10439 bp->flags |= BNXT_FLAG_SHARED_RINGS;
10440 dflt_rings = is_kdump_kernel() ? 1 : netif_get_num_default_rss_queues();
10441 /* Reduce default rings on multi-port cards so that total default
10442 * rings do not exceed CPU count.
10444 if (bp->port_count > 1) {
10446 max_t(int, num_online_cpus() / bp->port_count, 1);
10448 dflt_rings = min_t(int, dflt_rings, max_rings);
10450 rc = bnxt_get_dflt_rings(bp, &max_rx_rings, &max_tx_rings, sh);
10453 bp->rx_nr_rings = min_t(int, dflt_rings, max_rx_rings);
10454 bp->tx_nr_rings_per_tc = min_t(int, dflt_rings, max_tx_rings);
10456 bnxt_trim_dflt_sh_rings(bp);
10458 bp->cp_nr_rings = bp->tx_nr_rings_per_tc + bp->rx_nr_rings;
10459 bp->tx_nr_rings = bp->tx_nr_rings_per_tc;
10461 rc = __bnxt_reserve_rings(bp);
10463 netdev_warn(bp->dev, "Unable to reserve tx rings\n");
10464 bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
10466 bnxt_trim_dflt_sh_rings(bp);
10468 /* Rings may have been trimmed, re-reserve the trimmed rings. */
10469 if (bnxt_need_reserve_rings(bp)) {
10470 rc = __bnxt_reserve_rings(bp);
10472 netdev_warn(bp->dev, "2nd rings reservation failed.\n");
10473 bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
10475 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) {
10482 static int bnxt_init_dflt_ring_mode(struct bnxt *bp)
10486 if (bp->tx_nr_rings)
10489 bnxt_ulp_irq_stop(bp);
10490 bnxt_clear_int_mode(bp);
10491 rc = bnxt_set_dflt_rings(bp, true);
10493 netdev_err(bp->dev, "Not enough rings available.\n");
10494 goto init_dflt_ring_err;
10496 rc = bnxt_init_int_mode(bp);
10498 goto init_dflt_ring_err;
10500 bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
10501 if (bnxt_rfs_supported(bp) && bnxt_rfs_capable(bp)) {
10502 bp->flags |= BNXT_FLAG_RFS;
10503 bp->dev->features |= NETIF_F_NTUPLE;
10505 init_dflt_ring_err:
10506 bnxt_ulp_irq_restart(bp, rc);
10510 int bnxt_restore_pf_fw_resources(struct bnxt *bp)
10515 bnxt_hwrm_func_qcaps(bp);
10517 if (netif_running(bp->dev))
10518 __bnxt_close_nic(bp, true, false);
10520 bnxt_ulp_irq_stop(bp);
10521 bnxt_clear_int_mode(bp);
10522 rc = bnxt_init_int_mode(bp);
10523 bnxt_ulp_irq_restart(bp, rc);
10525 if (netif_running(bp->dev)) {
10527 dev_close(bp->dev);
10529 rc = bnxt_open_nic(bp, true, false);
10535 static int bnxt_init_mac_addr(struct bnxt *bp)
10540 memcpy(bp->dev->dev_addr, bp->pf.mac_addr, ETH_ALEN);
10542 #ifdef CONFIG_BNXT_SRIOV
10543 struct bnxt_vf_info *vf = &bp->vf;
10544 bool strict_approval = true;
10546 if (is_valid_ether_addr(vf->mac_addr)) {
10547 /* overwrite netdev dev_addr with admin VF MAC */
10548 memcpy(bp->dev->dev_addr, vf->mac_addr, ETH_ALEN);
10549 /* Older PF driver or firmware may not approve this
10552 strict_approval = false;
10554 eth_hw_addr_random(bp->dev);
10556 rc = bnxt_approve_mac(bp, bp->dev->dev_addr, strict_approval);
10562 static int bnxt_pcie_dsn_get(struct bnxt *bp, u8 dsn[])
10564 struct pci_dev *pdev = bp->pdev;
10565 int pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_DSN);
10569 netdev_info(bp->dev, "Unable do read adapter's DSN");
10570 return -EOPNOTSUPP;
10573 /* DSN (two dw) is at an offset of 4 from the cap pos */
10575 pci_read_config_dword(pdev, pos, &dw);
10576 put_unaligned_le32(dw, &dsn[0]);
10577 pci_read_config_dword(pdev, pos + 4, &dw);
10578 put_unaligned_le32(dw, &dsn[4]);
10582 static int bnxt_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
10584 static int version_printed;
10585 struct net_device *dev;
10589 if (pci_is_bridge(pdev))
10592 if (version_printed++ == 0)
10593 pr_info("%s", version);
10595 max_irqs = bnxt_get_max_irq(pdev);
10596 dev = alloc_etherdev_mq(sizeof(*bp), max_irqs);
10600 bp = netdev_priv(dev);
10601 bnxt_set_max_func_irqs(bp, max_irqs);
10603 if (bnxt_vf_pciid(ent->driver_data))
10604 bp->flags |= BNXT_FLAG_VF;
10606 if (pdev->msix_cap)
10607 bp->flags |= BNXT_FLAG_MSIX_CAP;
10609 rc = bnxt_init_board(pdev, dev);
10611 goto init_err_free;
10613 dev->netdev_ops = &bnxt_netdev_ops;
10614 dev->watchdog_timeo = BNXT_TX_TIMEOUT;
10615 dev->ethtool_ops = &bnxt_ethtool_ops;
10616 pci_set_drvdata(pdev, dev);
10618 rc = bnxt_alloc_hwrm_resources(bp);
10620 goto init_err_pci_clean;
10622 mutex_init(&bp->hwrm_cmd_lock);
10623 rc = bnxt_hwrm_ver_get(bp);
10625 goto init_err_pci_clean;
10627 if (bp->fw_cap & BNXT_FW_CAP_KONG_MB_CHNL) {
10628 rc = bnxt_alloc_kong_hwrm_resources(bp);
10630 bp->fw_cap &= ~BNXT_FW_CAP_KONG_MB_CHNL;
10633 if ((bp->fw_cap & BNXT_FW_CAP_SHORT_CMD) ||
10634 bp->hwrm_max_ext_req_len > BNXT_HWRM_MAX_REQ_LEN) {
10635 rc = bnxt_alloc_hwrm_short_cmd_req(bp);
10637 goto init_err_pci_clean;
10640 if (BNXT_CHIP_P5(bp))
10641 bp->flags |= BNXT_FLAG_CHIP_P5;
10643 rc = bnxt_hwrm_func_reset(bp);
10645 goto init_err_pci_clean;
10647 bnxt_hwrm_fw_set_time(bp);
10649 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG |
10650 NETIF_F_TSO | NETIF_F_TSO6 |
10651 NETIF_F_GSO_UDP_TUNNEL | NETIF_F_GSO_GRE |
10652 NETIF_F_GSO_IPXIP4 |
10653 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_GSO_GRE_CSUM |
10654 NETIF_F_GSO_PARTIAL | NETIF_F_RXHASH |
10655 NETIF_F_RXCSUM | NETIF_F_GRO;
10657 if (BNXT_SUPPORTS_TPA(bp))
10658 dev->hw_features |= NETIF_F_LRO;
10660 dev->hw_enc_features =
10661 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG |
10662 NETIF_F_TSO | NETIF_F_TSO6 |
10663 NETIF_F_GSO_UDP_TUNNEL | NETIF_F_GSO_GRE |
10664 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_GSO_GRE_CSUM |
10665 NETIF_F_GSO_IPXIP4 | NETIF_F_GSO_PARTIAL;
10666 dev->gso_partial_features = NETIF_F_GSO_UDP_TUNNEL_CSUM |
10667 NETIF_F_GSO_GRE_CSUM;
10668 dev->vlan_features = dev->hw_features | NETIF_F_HIGHDMA;
10669 dev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX |
10670 NETIF_F_HW_VLAN_STAG_RX | NETIF_F_HW_VLAN_STAG_TX;
10671 if (BNXT_SUPPORTS_TPA(bp))
10672 dev->hw_features |= NETIF_F_GRO_HW;
10673 dev->features |= dev->hw_features | NETIF_F_HIGHDMA;
10674 if (dev->features & NETIF_F_GRO_HW)
10675 dev->features &= ~NETIF_F_LRO;
10676 dev->priv_flags |= IFF_UNICAST_FLT;
10678 #ifdef CONFIG_BNXT_SRIOV
10679 init_waitqueue_head(&bp->sriov_cfg_wait);
10680 mutex_init(&bp->sriov_lock);
10682 if (BNXT_SUPPORTS_TPA(bp)) {
10683 bp->gro_func = bnxt_gro_func_5730x;
10684 if (BNXT_CHIP_P4(bp))
10685 bp->gro_func = bnxt_gro_func_5731x;
10687 if (!BNXT_CHIP_P4_PLUS(bp))
10688 bp->flags |= BNXT_FLAG_DOUBLE_DB;
10690 rc = bnxt_hwrm_func_drv_rgtr(bp);
10692 goto init_err_pci_clean;
10694 rc = bnxt_hwrm_func_rgtr_async_events(bp, NULL, 0);
10696 goto init_err_pci_clean;
10698 bp->ulp_probe = bnxt_ulp_probe;
10700 rc = bnxt_hwrm_queue_qportcfg(bp);
10702 netdev_err(bp->dev, "hwrm query qportcfg failure rc: %x\n",
10705 goto init_err_pci_clean;
10707 /* Get the MAX capabilities for this function */
10708 rc = bnxt_hwrm_func_qcaps(bp);
10710 netdev_err(bp->dev, "hwrm query capability failure rc: %x\n",
10713 goto init_err_pci_clean;
10716 rc = bnxt_hwrm_cfa_adv_flow_mgnt_qcaps(bp);
10718 netdev_warn(bp->dev, "hwrm query adv flow mgnt failure rc: %d\n",
10721 rc = bnxt_init_mac_addr(bp);
10723 dev_err(&pdev->dev, "Unable to initialize mac address.\n");
10724 rc = -EADDRNOTAVAIL;
10725 goto init_err_pci_clean;
10729 /* Read the adapter's DSN to use as the eswitch switch_id */
10730 rc = bnxt_pcie_dsn_get(bp, bp->switch_id);
10732 goto init_err_pci_clean;
10734 bnxt_hwrm_func_qcfg(bp);
10735 bnxt_hwrm_vnic_qcaps(bp);
10736 bnxt_hwrm_port_led_qcaps(bp);
10737 bnxt_ethtool_init(bp);
10740 /* MTU range: 60 - FW defined max */
10741 dev->min_mtu = ETH_ZLEN;
10742 dev->max_mtu = bp->max_mtu;
10744 rc = bnxt_probe_phy(bp);
10746 goto init_err_pci_clean;
10748 bnxt_set_rx_skb_mode(bp, false);
10749 bnxt_set_tpa_flags(bp);
10750 bnxt_set_ring_params(bp);
10751 rc = bnxt_set_dflt_rings(bp, true);
10753 netdev_err(bp->dev, "Not enough rings available.\n");
10755 goto init_err_pci_clean;
10758 /* Default RSS hash cfg. */
10759 bp->rss_hash_cfg = VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4 |
10760 VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4 |
10761 VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6 |
10762 VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6;
10763 if (BNXT_CHIP_P4(bp) && bp->hwrm_spec_code >= 0x10501) {
10764 bp->flags |= BNXT_FLAG_UDP_RSS_CAP;
10765 bp->rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4 |
10766 VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6;
10769 if (bnxt_rfs_supported(bp)) {
10770 dev->hw_features |= NETIF_F_NTUPLE;
10771 if (bnxt_rfs_capable(bp)) {
10772 bp->flags |= BNXT_FLAG_RFS;
10773 dev->features |= NETIF_F_NTUPLE;
10777 if (dev->hw_features & NETIF_F_HW_VLAN_CTAG_RX)
10778 bp->flags |= BNXT_FLAG_STRIP_VLAN;
10780 rc = bnxt_init_int_mode(bp);
10782 goto init_err_pci_clean;
10784 /* No TC has been set yet and rings may have been trimmed due to
10785 * limited MSIX, so we re-initialize the TX rings per TC.
10787 bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
10789 bnxt_get_wol_settings(bp);
10790 if (bp->flags & BNXT_FLAG_WOL_CAP)
10791 device_set_wakeup_enable(&pdev->dev, bp->wol);
10793 device_set_wakeup_capable(&pdev->dev, false);
10795 bnxt_hwrm_set_cache_line_size(bp, cache_line_size());
10797 bnxt_hwrm_coal_params_qcaps(bp);
10802 create_singlethread_workqueue("bnxt_pf_wq");
10804 dev_err(&pdev->dev, "Unable to create workqueue.\n");
10805 goto init_err_pci_clean;
10811 rc = register_netdev(dev);
10813 goto init_err_cleanup_tc;
10816 bnxt_dl_register(bp);
10818 netdev_info(dev, "%s found at mem %lx, node addr %pM\n",
10819 board_info[ent->driver_data].name,
10820 (long)pci_resource_start(pdev, 0), dev->dev_addr);
10821 pcie_print_link_status(pdev);
10825 init_err_cleanup_tc:
10826 bnxt_shutdown_tc(bp);
10827 bnxt_clear_int_mode(bp);
10829 init_err_pci_clean:
10830 bnxt_free_hwrm_short_cmd_req(bp);
10831 bnxt_free_hwrm_resources(bp);
10832 bnxt_free_ctx_mem(bp);
10835 bnxt_cleanup_pci(bp);
10842 static void bnxt_shutdown(struct pci_dev *pdev)
10844 struct net_device *dev = pci_get_drvdata(pdev);
10851 bp = netdev_priv(dev);
10853 goto shutdown_exit;
10855 if (netif_running(dev))
10858 bnxt_ulp_shutdown(bp);
10860 if (system_state == SYSTEM_POWER_OFF) {
10861 bnxt_clear_int_mode(bp);
10862 pci_wake_from_d3(pdev, bp->wol);
10863 pci_set_power_state(pdev, PCI_D3hot);
10870 #ifdef CONFIG_PM_SLEEP
10871 static int bnxt_suspend(struct device *device)
10873 struct pci_dev *pdev = to_pci_dev(device);
10874 struct net_device *dev = pci_get_drvdata(pdev);
10875 struct bnxt *bp = netdev_priv(dev);
10879 if (netif_running(dev)) {
10880 netif_device_detach(dev);
10881 rc = bnxt_close(dev);
10883 bnxt_hwrm_func_drv_unrgtr(bp);
10888 static int bnxt_resume(struct device *device)
10890 struct pci_dev *pdev = to_pci_dev(device);
10891 struct net_device *dev = pci_get_drvdata(pdev);
10892 struct bnxt *bp = netdev_priv(dev);
10896 if (bnxt_hwrm_ver_get(bp) || bnxt_hwrm_func_drv_rgtr(bp)) {
10900 rc = bnxt_hwrm_func_reset(bp);
10905 bnxt_get_wol_settings(bp);
10906 if (netif_running(dev)) {
10907 rc = bnxt_open(dev);
10909 netif_device_attach(dev);
10917 static SIMPLE_DEV_PM_OPS(bnxt_pm_ops, bnxt_suspend, bnxt_resume);
10918 #define BNXT_PM_OPS (&bnxt_pm_ops)
10922 #define BNXT_PM_OPS NULL
10924 #endif /* CONFIG_PM_SLEEP */
10927 * bnxt_io_error_detected - called when PCI error is detected
10928 * @pdev: Pointer to PCI device
10929 * @state: The current pci connection state
10931 * This function is called after a PCI bus error affecting
10932 * this device has been detected.
10934 static pci_ers_result_t bnxt_io_error_detected(struct pci_dev *pdev,
10935 pci_channel_state_t state)
10937 struct net_device *netdev = pci_get_drvdata(pdev);
10938 struct bnxt *bp = netdev_priv(netdev);
10940 netdev_info(netdev, "PCI I/O error detected\n");
10943 netif_device_detach(netdev);
10947 if (state == pci_channel_io_perm_failure) {
10949 return PCI_ERS_RESULT_DISCONNECT;
10952 if (netif_running(netdev))
10953 bnxt_close(netdev);
10955 pci_disable_device(pdev);
10958 /* Request a slot slot reset. */
10959 return PCI_ERS_RESULT_NEED_RESET;
10963 * bnxt_io_slot_reset - called after the pci bus has been reset.
10964 * @pdev: Pointer to PCI device
10966 * Restart the card from scratch, as if from a cold-boot.
10967 * At this point, the card has exprienced a hard reset,
10968 * followed by fixups by BIOS, and has its config space
10969 * set up identically to what it was at cold boot.
10971 static pci_ers_result_t bnxt_io_slot_reset(struct pci_dev *pdev)
10973 struct net_device *netdev = pci_get_drvdata(pdev);
10974 struct bnxt *bp = netdev_priv(netdev);
10976 pci_ers_result_t result = PCI_ERS_RESULT_DISCONNECT;
10978 netdev_info(bp->dev, "PCI Slot Reset\n");
10982 if (pci_enable_device(pdev)) {
10983 dev_err(&pdev->dev,
10984 "Cannot re-enable PCI device after reset.\n");
10986 pci_set_master(pdev);
10988 err = bnxt_hwrm_func_reset(bp);
10989 if (!err && netif_running(netdev))
10990 err = bnxt_open(netdev);
10993 result = PCI_ERS_RESULT_RECOVERED;
10994 bnxt_ulp_start(bp);
10998 if (result != PCI_ERS_RESULT_RECOVERED && netif_running(netdev))
11003 return PCI_ERS_RESULT_RECOVERED;
11007 * bnxt_io_resume - called when traffic can start flowing again.
11008 * @pdev: Pointer to PCI device
11010 * This callback is called when the error recovery driver tells
11011 * us that its OK to resume normal operation.
11013 static void bnxt_io_resume(struct pci_dev *pdev)
11015 struct net_device *netdev = pci_get_drvdata(pdev);
11019 netif_device_attach(netdev);
11024 static const struct pci_error_handlers bnxt_err_handler = {
11025 .error_detected = bnxt_io_error_detected,
11026 .slot_reset = bnxt_io_slot_reset,
11027 .resume = bnxt_io_resume
11030 static struct pci_driver bnxt_pci_driver = {
11031 .name = DRV_MODULE_NAME,
11032 .id_table = bnxt_pci_tbl,
11033 .probe = bnxt_init_one,
11034 .remove = bnxt_remove_one,
11035 .shutdown = bnxt_shutdown,
11036 .driver.pm = BNXT_PM_OPS,
11037 .err_handler = &bnxt_err_handler,
11038 #if defined(CONFIG_BNXT_SRIOV)
11039 .sriov_configure = bnxt_sriov_configure,
11043 static int __init bnxt_init(void)
11046 return pci_register_driver(&bnxt_pci_driver);
11049 static void __exit bnxt_exit(void)
11051 pci_unregister_driver(&bnxt_pci_driver);
11053 destroy_workqueue(bnxt_pf_wq);
11057 module_init(bnxt_init);
11058 module_exit(bnxt_exit);