drivers/net/ethernet/broadcom/bnxt/bnxt.c

   1 /* Broadcom NetXtreme-C/E network driver.
   2  *
   3  * Copyright (c) 2014-2016 Broadcom Corporation
   4  * Copyright (c) 2016-2019 Broadcom Limited
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation.
   9  */
  10
  11 #include <linux/module.h>
  12
  13 #include <linux/stringify.h>
  14 #include <linux/kernel.h>
  15 #include <linux/timer.h>
  16 #include <linux/errno.h>
  17 #include <linux/ioport.h>
  18 #include <linux/slab.h>
  19 #include <linux/vmalloc.h>
  20 #include <linux/interrupt.h>
  21 #include <linux/pci.h>
  22 #include <linux/netdevice.h>
  23 #include <linux/etherdevice.h>
  24 #include <linux/skbuff.h>
  25 #include <linux/dma-mapping.h>
  26 #include <linux/bitops.h>
  27 #include <linux/io.h>
  28 #include <linux/irq.h>
  29 #include <linux/delay.h>
  30 #include <asm/byteorder.h>
  31 #include <asm/page.h>
  32 #include <linux/time.h>
  33 #include <linux/mii.h>
  34 #include <linux/mdio.h>
  35 #include <linux/if.h>
  36 #include <linux/if_vlan.h>
  37 #include <linux/if_bridge.h>
  38 #include <linux/rtc.h>
  39 #include <linux/bpf.h>
  40 #include <net/gro.h>
  41 #include <net/ip.h>
  42 #include <net/tcp.h>
  43 #include <net/udp.h>
  44 #include <net/checksum.h>
  45 #include <net/ip6_checksum.h>
  46 #include <net/udp_tunnel.h>
  47 #include <linux/workqueue.h>
  48 #include <linux/prefetch.h>
  49 #include <linux/cache.h>
  50 #include <linux/log2.h>
  51 #include <linux/bitmap.h>
  52 #include <linux/cpu_rmap.h>
  53 #include <linux/cpumask.h>
  54 #include <net/pkt_cls.h>
  55 #include <linux/hwmon.h>
  56 #include <linux/hwmon-sysfs.h>
  57 #include <net/page_pool.h>
  58 #include <linux/align.h>
  59
  60 #include "bnxt_hsi.h"
  61 #include "bnxt.h"
  62 #include "bnxt_hwrm.h"
  63 #include "bnxt_ulp.h"
  64 #include "bnxt_sriov.h"
  65 #include "bnxt_ethtool.h"
  66 #include "bnxt_dcb.h"
  67 #include "bnxt_xdp.h"
  68 #include "bnxt_ptp.h"
  69 #include "bnxt_vfr.h"
  70 #include "bnxt_tc.h"
  71 #include "bnxt_devlink.h"
  72 #include "bnxt_debugfs.h"
  73
  74 #define BNXT_TX_TIMEOUT         (5 * HZ)
  75 #define BNXT_DEF_MSG_ENABLE     (NETIF_MSG_DRV | NETIF_MSG_HW | \
  76                                  NETIF_MSG_TX_ERR)
  77
  78 MODULE_LICENSE("GPL");
  79 MODULE_DESCRIPTION("Broadcom BCM573xx network driver");
  80
  81 #define BNXT_RX_OFFSET (NET_SKB_PAD + NET_IP_ALIGN)
  82 #define BNXT_RX_DMA_OFFSET NET_SKB_PAD
  83 #define BNXT_RX_COPY_THRESH 256
  84
  85 #define BNXT_TX_PUSH_THRESH 164
  86
  87 /* indexed by enum board_idx */
  88 static const struct {
  89         char *name;
  90 } board_info[] = {
  91         [BCM57301] = { "Broadcom BCM57301 NetXtreme-C 10Gb Ethernet" },
  92         [BCM57302] = { "Broadcom BCM57302 NetXtreme-C 10Gb/25Gb Ethernet" },
  93         [BCM57304] = { "Broadcom BCM57304 NetXtreme-C 10Gb/25Gb/40Gb/50Gb Ethernet" },
  94         [BCM57417_NPAR] = { "Broadcom BCM57417 NetXtreme-E Ethernet Partition" },
  95         [BCM58700] = { "Broadcom BCM58700 Nitro 1Gb/2.5Gb/10Gb Ethernet" },
  96         [BCM57311] = { "Broadcom BCM57311 NetXtreme-C 10Gb Ethernet" },
  97         [BCM57312] = { "Broadcom BCM57312 NetXtreme-C 10Gb/25Gb Ethernet" },
  98         [BCM57402] = { "Broadcom BCM57402 NetXtreme-E 10Gb Ethernet" },
  99         [BCM57404] = { "Broadcom BCM57404 NetXtreme-E 10Gb/25Gb Ethernet" },
 100         [BCM57406] = { "Broadcom BCM57406 NetXtreme-E 10GBase-T Ethernet" },
 101         [BCM57402_NPAR] = { "Broadcom BCM57402 NetXtreme-E Ethernet Partition" },
 102         [BCM57407] = { "Broadcom BCM57407 NetXtreme-E 10GBase-T Ethernet" },
 103         [BCM57412] = { "Broadcom BCM57412 NetXtreme-E 10Gb Ethernet" },
 104         [BCM57414] = { "Broadcom BCM57414 NetXtreme-E 10Gb/25Gb Ethernet" },
 105         [BCM57416] = { "Broadcom BCM57416 NetXtreme-E 10GBase-T Ethernet" },
 106         [BCM57417] = { "Broadcom BCM57417 NetXtreme-E 10GBase-T Ethernet" },
 107         [BCM57412_NPAR] = { "Broadcom BCM57412 NetXtreme-E Ethernet Partition" },
 108         [BCM57314] = { "Broadcom BCM57314 NetXtreme-C 10Gb/25Gb/40Gb/50Gb Ethernet" },
 109         [BCM57417_SFP] = { "Broadcom BCM57417 NetXtreme-E 10Gb/25Gb Ethernet" },
 110         [BCM57416_SFP] = { "Broadcom BCM57416 NetXtreme-E 10Gb Ethernet" },
 111         [BCM57404_NPAR] = { "Broadcom BCM57404 NetXtreme-E Ethernet Partition" },
 112         [BCM57406_NPAR] = { "Broadcom BCM57406 NetXtreme-E Ethernet Partition" },
 113         [BCM57407_SFP] = { "Broadcom BCM57407 NetXtreme-E 25Gb Ethernet" },
 114         [BCM57407_NPAR] = { "Broadcom BCM57407 NetXtreme-E Ethernet Partition" },
 115         [BCM57414_NPAR] = { "Broadcom BCM57414 NetXtreme-E Ethernet Partition" },
 116         [BCM57416_NPAR] = { "Broadcom BCM57416 NetXtreme-E Ethernet Partition" },
 117         [BCM57452] = { "Broadcom BCM57452 NetXtreme-E 10Gb/25Gb/40Gb/50Gb Ethernet" },
 118         [BCM57454] = { "Broadcom BCM57454 NetXtreme-E 10Gb/25Gb/40Gb/50Gb/100Gb Ethernet" },
 119         [BCM5745x_NPAR] = { "Broadcom BCM5745x NetXtreme-E Ethernet Partition" },
 120         [BCM57508] = { "Broadcom BCM57508 NetXtreme-E 10Gb/25Gb/50Gb/100Gb/200Gb Ethernet" },
 121         [BCM57504] = { "Broadcom BCM57504 NetXtreme-E 10Gb/25Gb/50Gb/100Gb/200Gb Ethernet" },
 122         [BCM57502] = { "Broadcom BCM57502 NetXtreme-E 10Gb/25Gb/50Gb Ethernet" },
 123         [BCM57508_NPAR] = { "Broadcom BCM57508 NetXtreme-E Ethernet Partition" },
 124         [BCM57504_NPAR] = { "Broadcom BCM57504 NetXtreme-E Ethernet Partition" },
 125         [BCM57502_NPAR] = { "Broadcom BCM57502 NetXtreme-E Ethernet Partition" },
 126         [BCM58802] = { "Broadcom BCM58802 NetXtreme-S 10Gb/25Gb/40Gb/50Gb Ethernet" },
 127         [BCM58804] = { "Broadcom BCM58804 NetXtreme-S 10Gb/25Gb/40Gb/50Gb/100Gb Ethernet" },
 128         [BCM58808] = { "Broadcom BCM58808 NetXtreme-S 10Gb/25Gb/40Gb/50Gb/100Gb Ethernet" },
 129         [NETXTREME_E_VF] = { "Broadcom NetXtreme-E Ethernet Virtual Function" },
 130         [NETXTREME_C_VF] = { "Broadcom NetXtreme-C Ethernet Virtual Function" },
 131         [NETXTREME_S_VF] = { "Broadcom NetXtreme-S Ethernet Virtual Function" },
 132         [NETXTREME_C_VF_HV] = { "Broadcom NetXtreme-C Virtual Function for Hyper-V" },
 133         [NETXTREME_E_VF_HV] = { "Broadcom NetXtreme-E Virtual Function for Hyper-V" },
 134         [NETXTREME_E_P5_VF] = { "Broadcom BCM5750X NetXtreme-E Ethernet Virtual Function" },
 135         [NETXTREME_E_P5_VF_HV] = { "Broadcom BCM5750X NetXtreme-E Virtual Function for Hyper-V" },
 136 };
 137
 138 static const struct pci_device_id bnxt_pci_tbl[] = {
 139         { PCI_VDEVICE(BROADCOM, 0x1604), .driver_data = BCM5745x_NPAR },
 140         { PCI_VDEVICE(BROADCOM, 0x1605), .driver_data = BCM5745x_NPAR },
 141         { PCI_VDEVICE(BROADCOM, 0x1614), .driver_data = BCM57454 },
 142         { PCI_VDEVICE(BROADCOM, 0x16c0), .driver_data = BCM57417_NPAR },
 143         { PCI_VDEVICE(BROADCOM, 0x16c8), .driver_data = BCM57301 },
 144         { PCI_VDEVICE(BROADCOM, 0x16c9), .driver_data = BCM57302 },
 145         { PCI_VDEVICE(BROADCOM, 0x16ca), .driver_data = BCM57304 },
 146         { PCI_VDEVICE(BROADCOM, 0x16cc), .driver_data = BCM57417_NPAR },
 147         { PCI_VDEVICE(BROADCOM, 0x16cd), .driver_data = BCM58700 },
 148         { PCI_VDEVICE(BROADCOM, 0x16ce), .driver_data = BCM57311 },
 149         { PCI_VDEVICE(BROADCOM, 0x16cf), .driver_data = BCM57312 },
 150         { PCI_VDEVICE(BROADCOM, 0x16d0), .driver_data = BCM57402 },
 151         { PCI_VDEVICE(BROADCOM, 0x16d1), .driver_data = BCM57404 },
 152         { PCI_VDEVICE(BROADCOM, 0x16d2), .driver_data = BCM57406 },
 153         { PCI_VDEVICE(BROADCOM, 0x16d4), .driver_data = BCM57402_NPAR },
 154         { PCI_VDEVICE(BROADCOM, 0x16d5), .driver_data = BCM57407 },
 155         { PCI_VDEVICE(BROADCOM, 0x16d6), .driver_data = BCM57412 },
 156         { PCI_VDEVICE(BROADCOM, 0x16d7), .driver_data = BCM57414 },
 157         { PCI_VDEVICE(BROADCOM, 0x16d8), .driver_data = BCM57416 },
 158         { PCI_VDEVICE(BROADCOM, 0x16d9), .driver_data = BCM57417 },
 159         { PCI_VDEVICE(BROADCOM, 0x16de), .driver_data = BCM57412_NPAR },
 160         { PCI_VDEVICE(BROADCOM, 0x16df), .driver_data = BCM57314 },
 161         { PCI_VDEVICE(BROADCOM, 0x16e2), .driver_data = BCM57417_SFP },
 162         { PCI_VDEVICE(BROADCOM, 0x16e3), .driver_data = BCM57416_SFP },
 163         { PCI_VDEVICE(BROADCOM, 0x16e7), .driver_data = BCM57404_NPAR },
 164         { PCI_VDEVICE(BROADCOM, 0x16e8), .driver_data = BCM57406_NPAR },
 165         { PCI_VDEVICE(BROADCOM, 0x16e9), .driver_data = BCM57407_SFP },
 166         { PCI_VDEVICE(BROADCOM, 0x16ea), .driver_data = BCM57407_NPAR },
 167         { PCI_VDEVICE(BROADCOM, 0x16eb), .driver_data = BCM57412_NPAR },
 168         { PCI_VDEVICE(BROADCOM, 0x16ec), .driver_data = BCM57414_NPAR },
 169         { PCI_VDEVICE(BROADCOM, 0x16ed), .driver_data = BCM57414_NPAR },
 170         { PCI_VDEVICE(BROADCOM, 0x16ee), .driver_data = BCM57416_NPAR },
 171         { PCI_VDEVICE(BROADCOM, 0x16ef), .driver_data = BCM57416_NPAR },
 172         { PCI_VDEVICE(BROADCOM, 0x16f0), .driver_data = BCM58808 },
 173         { PCI_VDEVICE(BROADCOM, 0x16f1), .driver_data = BCM57452 },
 174         { PCI_VDEVICE(BROADCOM, 0x1750), .driver_data = BCM57508 },
 175         { PCI_VDEVICE(BROADCOM, 0x1751), .driver_data = BCM57504 },
 176         { PCI_VDEVICE(BROADCOM, 0x1752), .driver_data = BCM57502 },
 177         { PCI_VDEVICE(BROADCOM, 0x1800), .driver_data = BCM57508_NPAR },
 178         { PCI_VDEVICE(BROADCOM, 0x1801), .driver_data = BCM57504_NPAR },
 179         { PCI_VDEVICE(BROADCOM, 0x1802), .driver_data = BCM57502_NPAR },
 180         { PCI_VDEVICE(BROADCOM, 0x1803), .driver_data = BCM57508_NPAR },
 181         { PCI_VDEVICE(BROADCOM, 0x1804), .driver_data = BCM57504_NPAR },
 182         { PCI_VDEVICE(BROADCOM, 0x1805), .driver_data = BCM57502_NPAR },
 183         { PCI_VDEVICE(BROADCOM, 0xd802), .driver_data = BCM58802 },
 184         { PCI_VDEVICE(BROADCOM, 0xd804), .driver_data = BCM58804 },
 185 #ifdef CONFIG_BNXT_SRIOV
 186         { PCI_VDEVICE(BROADCOM, 0x1606), .driver_data = NETXTREME_E_VF },
 187         { PCI_VDEVICE(BROADCOM, 0x1607), .driver_data = NETXTREME_E_VF_HV },
 188         { PCI_VDEVICE(BROADCOM, 0x1608), .driver_data = NETXTREME_E_VF_HV },
 189         { PCI_VDEVICE(BROADCOM, 0x1609), .driver_data = NETXTREME_E_VF },
 190         { PCI_VDEVICE(BROADCOM, 0x16bd), .driver_data = NETXTREME_E_VF_HV },
 191         { PCI_VDEVICE(BROADCOM, 0x16c1), .driver_data = NETXTREME_E_VF },
 192         { PCI_VDEVICE(BROADCOM, 0x16c2), .driver_data = NETXTREME_C_VF_HV },
 193         { PCI_VDEVICE(BROADCOM, 0x16c3), .driver_data = NETXTREME_C_VF_HV },
 194         { PCI_VDEVICE(BROADCOM, 0x16c4), .driver_data = NETXTREME_E_VF_HV },
 195         { PCI_VDEVICE(BROADCOM, 0x16c5), .driver_data = NETXTREME_E_VF_HV },
 196         { PCI_VDEVICE(BROADCOM, 0x16cb), .driver_data = NETXTREME_C_VF },
 197         { PCI_VDEVICE(BROADCOM, 0x16d3), .driver_data = NETXTREME_E_VF },
 198         { PCI_VDEVICE(BROADCOM, 0x16dc), .driver_data = NETXTREME_E_VF },
 199         { PCI_VDEVICE(BROADCOM, 0x16e1), .driver_data = NETXTREME_C_VF },
 200         { PCI_VDEVICE(BROADCOM, 0x16e5), .driver_data = NETXTREME_C_VF },
 201         { PCI_VDEVICE(BROADCOM, 0x16e6), .driver_data = NETXTREME_C_VF_HV },
 202         { PCI_VDEVICE(BROADCOM, 0x1806), .driver_data = NETXTREME_E_P5_VF },
 203         { PCI_VDEVICE(BROADCOM, 0x1807), .driver_data = NETXTREME_E_P5_VF },
 204         { PCI_VDEVICE(BROADCOM, 0x1808), .driver_data = NETXTREME_E_P5_VF_HV },
 205         { PCI_VDEVICE(BROADCOM, 0x1809), .driver_data = NETXTREME_E_P5_VF_HV },
 206         { PCI_VDEVICE(BROADCOM, 0xd800), .driver_data = NETXTREME_S_VF },
 207 #endif
 208         { 0 }
 209 };
 210
 211 MODULE_DEVICE_TABLE(pci, bnxt_pci_tbl);
 212
 213 static const u16 bnxt_vf_req_snif[] = {
 214         HWRM_FUNC_CFG,
 215         HWRM_FUNC_VF_CFG,
 216         HWRM_PORT_PHY_QCFG,
 217         HWRM_CFA_L2_FILTER_ALLOC,
 218 };
 219
 220 static const u16 bnxt_async_events_arr[] = {
 221         ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE,
 222         ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CHANGE,
 223         ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD,
 224         ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED,
 225         ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE,
 226         ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE,
 227         ASYNC_EVENT_CMPL_EVENT_ID_PORT_PHY_CFG_CHANGE,
 228         ASYNC_EVENT_CMPL_EVENT_ID_RESET_NOTIFY,
 229         ASYNC_EVENT_CMPL_EVENT_ID_ERROR_RECOVERY,
 230         ASYNC_EVENT_CMPL_EVENT_ID_DEBUG_NOTIFICATION,
 231         ASYNC_EVENT_CMPL_EVENT_ID_DEFERRED_RESPONSE,
 232         ASYNC_EVENT_CMPL_EVENT_ID_RING_MONITOR_MSG,
 233         ASYNC_EVENT_CMPL_EVENT_ID_ECHO_REQUEST,
 234         ASYNC_EVENT_CMPL_EVENT_ID_PPS_TIMESTAMP,
 235         ASYNC_EVENT_CMPL_EVENT_ID_ERROR_REPORT,
 236         ASYNC_EVENT_CMPL_EVENT_ID_PHC_UPDATE,
 237 };
 238
 239 static struct workqueue_struct *bnxt_pf_wq;
 240
 241 static bool bnxt_vf_pciid(enum board_idx idx)
 242 {
 243         return (idx == NETXTREME_C_VF || idx == NETXTREME_E_VF ||
 244                 idx == NETXTREME_S_VF || idx == NETXTREME_C_VF_HV ||
 245                 idx == NETXTREME_E_VF_HV || idx == NETXTREME_E_P5_VF ||
 246                 idx == NETXTREME_E_P5_VF_HV);
 247 }
 248
 249 #define DB_CP_REARM_FLAGS       (DB_KEY_CP | DB_IDX_VALID)
 250 #define DB_CP_FLAGS             (DB_KEY_CP | DB_IDX_VALID | DB_IRQ_DIS)
 251 #define DB_CP_IRQ_DIS_FLAGS     (DB_KEY_CP | DB_IRQ_DIS)
 252
 253 #define BNXT_CP_DB_IRQ_DIS(db)                                          \
 254                 writel(DB_CP_IRQ_DIS_FLAGS, db)
 255
 256 #define BNXT_DB_CQ(db, idx)                                             \
 257         writel(DB_CP_FLAGS | RING_CMP(idx), (db)->doorbell)
 258
 259 #define BNXT_DB_NQ_P5(db, idx)                                          \
 260         bnxt_writeq(bp, (db)->db_key64 | DBR_TYPE_NQ | RING_CMP(idx),   \
 261                     (db)->doorbell)
 262
 263 #define BNXT_DB_CQ_ARM(db, idx)                                         \
 264         writel(DB_CP_REARM_FLAGS | RING_CMP(idx), (db)->doorbell)
 265
 266 #define BNXT_DB_NQ_ARM_P5(db, idx)                                      \
 267         bnxt_writeq(bp, (db)->db_key64 | DBR_TYPE_NQ_ARM | RING_CMP(idx),\
 268                     (db)->doorbell)
 269
 270 static void bnxt_db_nq(struct bnxt *bp, struct bnxt_db_info *db, u32 idx)
 271 {
 272         if (bp->flags & BNXT_FLAG_CHIP_P5)
 273                 BNXT_DB_NQ_P5(db, idx);
 274         else
 275                 BNXT_DB_CQ(db, idx);
 276 }
 277
 278 static void bnxt_db_nq_arm(struct bnxt *bp, struct bnxt_db_info *db, u32 idx)
 279 {
 280         if (bp->flags & BNXT_FLAG_CHIP_P5)
 281                 BNXT_DB_NQ_ARM_P5(db, idx);
 282         else
 283                 BNXT_DB_CQ_ARM(db, idx);
 284 }
 285
 286 static void bnxt_db_cq(struct bnxt *bp, struct bnxt_db_info *db, u32 idx)
 287 {
 288         if (bp->flags & BNXT_FLAG_CHIP_P5)
 289                 bnxt_writeq(bp, db->db_key64 | DBR_TYPE_CQ_ARMALL |
 290                             RING_CMP(idx), db->doorbell);
 291         else
 292                 BNXT_DB_CQ(db, idx);
 293 }
 294
 295 const u16 bnxt_lhint_arr[] = {
 296         TX_BD_FLAGS_LHINT_512_AND_SMALLER,
 297         TX_BD_FLAGS_LHINT_512_TO_1023,
 298         TX_BD_FLAGS_LHINT_1024_TO_2047,
 299         TX_BD_FLAGS_LHINT_1024_TO_2047,
 300         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 301         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 302         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 303         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 304         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 305         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 306         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 307         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 308         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 309         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 310         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 311         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 312         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 313         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 314         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 315 };
 316
 317 static u16 bnxt_xmit_get_cfa_action(struct sk_buff *skb)
 318 {
 319         struct metadata_dst *md_dst = skb_metadata_dst(skb);
 320
 321         if (!md_dst || md_dst->type != METADATA_HW_PORT_MUX)
 322                 return 0;
 323
 324         return md_dst->u.port_info.port_id;
 325 }
 326
 327 static void bnxt_txr_db_kick(struct bnxt *bp, struct bnxt_tx_ring_info *txr,
 328                              u16 prod)
 329 {
 330         bnxt_db_write(bp, &txr->tx_db, prod);
 331         txr->kick_pending = 0;
 332 }
 333
 334 static bool bnxt_txr_netif_try_stop_queue(struct bnxt *bp,
 335                                           struct bnxt_tx_ring_info *txr,
 336                                           struct netdev_queue *txq)
 337 {
 338         netif_tx_stop_queue(txq);
 339
 340         /* netif_tx_stop_queue() must be done before checking
 341          * tx index in bnxt_tx_avail() below, because in
 342          * bnxt_tx_int(), we update tx index before checking for
 343          * netif_tx_queue_stopped().
 344          */
 345         smp_mb();
 346         if (bnxt_tx_avail(bp, txr) >= bp->tx_wake_thresh) {
 347                 netif_tx_wake_queue(txq);
 348                 return false;
 349         }
 350
 351         return true;
 352 }
 353
 354 static netdev_tx_t bnxt_start_xmit(struct sk_buff *skb, struct net_device *dev)
 355 {
 356         struct bnxt *bp = netdev_priv(dev);
 357         struct tx_bd *txbd;
 358         struct tx_bd_ext *txbd1;
 359         struct netdev_queue *txq;
 360         int i;
 361         dma_addr_t mapping;
 362         unsigned int length, pad = 0;
 363         u32 len, free_size, vlan_tag_flags, cfa_action, flags;
 364         u16 prod, last_frag;
 365         struct pci_dev *pdev = bp->pdev;
 366         struct bnxt_tx_ring_info *txr;
 367         struct bnxt_sw_tx_bd *tx_buf;
 368         __le32 lflags = 0;
 369
 370         i = skb_get_queue_mapping(skb);
 371         if (unlikely(i >= bp->tx_nr_rings)) {
 372                 dev_kfree_skb_any(skb);
 373                 dev_core_stats_tx_dropped_inc(dev);
 374                 return NETDEV_TX_OK;
 375         }
 376
 377         txq = netdev_get_tx_queue(dev, i);
 378         txr = &bp->tx_ring[bp->tx_ring_map[i]];
 379         prod = txr->tx_prod;
 380
 381         free_size = bnxt_tx_avail(bp, txr);
 382         if (unlikely(free_size < skb_shinfo(skb)->nr_frags + 2)) {
 383                 /* We must have raced with NAPI cleanup */
 384                 if (net_ratelimit() && txr->kick_pending)
 385                         netif_warn(bp, tx_err, dev,
 386                                    "bnxt: ring busy w/ flush pending!\n");
 387                 if (bnxt_txr_netif_try_stop_queue(bp, txr, txq))
 388                         return NETDEV_TX_BUSY;
 389         }
 390
 391         if (unlikely(ipv6_hopopt_jumbo_remove(skb)))
 392                 goto tx_free;
 393
 394         length = skb->len;
 395         len = skb_headlen(skb);
 396         last_frag = skb_shinfo(skb)->nr_frags;
 397
 398         txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
 399
 400         txbd->tx_bd_opaque = prod;
 401
 402         tx_buf = &txr->tx_buf_ring[prod];
 403         tx_buf->skb = skb;
 404         tx_buf->nr_frags = last_frag;
 405
 406         vlan_tag_flags = 0;
 407         cfa_action = bnxt_xmit_get_cfa_action(skb);
 408         if (skb_vlan_tag_present(skb)) {
 409                 vlan_tag_flags = TX_BD_CFA_META_KEY_VLAN |
 410                                  skb_vlan_tag_get(skb);
 411                 /* Currently supports 8021Q, 8021AD vlan offloads
 412                  * QINQ1, QINQ2, QINQ3 vlan headers are deprecated
 413                  */
 414                 if (skb->vlan_proto == htons(ETH_P_8021Q))
 415                         vlan_tag_flags |= 1 << TX_BD_CFA_META_TPID_SHIFT;
 416         }
 417
 418         if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) {
 419                 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
 420
 421                 if (ptp && ptp->tx_tstamp_en && !skb_is_gso(skb) &&
 422                     atomic_dec_if_positive(&ptp->tx_avail) >= 0) {
 423                         if (!bnxt_ptp_parse(skb, &ptp->tx_seqid,
 424                                             &ptp->tx_hdr_off)) {
 425                                 if (vlan_tag_flags)
 426                                         ptp->tx_hdr_off += VLAN_HLEN;
 427                                 lflags |= cpu_to_le32(TX_BD_FLAGS_STAMP);
 428                                 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
 429                         } else {
 430                                 atomic_inc(&bp->ptp_cfg->tx_avail);
 431                         }
 432                 }
 433         }
 434
 435         if (unlikely(skb->no_fcs))
 436                 lflags |= cpu_to_le32(TX_BD_FLAGS_NO_CRC);
 437
 438         if (free_size == bp->tx_ring_size && length <= bp->tx_push_thresh &&
 439             !lflags) {
 440                 struct tx_push_buffer *tx_push_buf = txr->tx_push;
 441                 struct tx_push_bd *tx_push = &tx_push_buf->push_bd;
 442                 struct tx_bd_ext *tx_push1 = &tx_push->txbd2;
 443                 void __iomem *db = txr->tx_db.doorbell;
 444                 void *pdata = tx_push_buf->data;
 445                 u64 *end;
 446                 int j, push_len;
 447
 448                 /* Set COAL_NOW to be ready quickly for the next push */
 449                 tx_push->tx_bd_len_flags_type =
 450                         cpu_to_le32((length << TX_BD_LEN_SHIFT) |
 451                                         TX_BD_TYPE_LONG_TX_BD |
 452                                         TX_BD_FLAGS_LHINT_512_AND_SMALLER |
 453                                         TX_BD_FLAGS_COAL_NOW |
 454                                         TX_BD_FLAGS_PACKET_END |
 455                                         (2 << TX_BD_FLAGS_BD_CNT_SHIFT));
 456
 457                 if (skb->ip_summed == CHECKSUM_PARTIAL)
 458                         tx_push1->tx_bd_hsize_lflags =
 459                                         cpu_to_le32(TX_BD_FLAGS_TCP_UDP_CHKSUM);
 460                 else
 461                         tx_push1->tx_bd_hsize_lflags = 0;
 462
 463                 tx_push1->tx_bd_cfa_meta = cpu_to_le32(vlan_tag_flags);
 464                 tx_push1->tx_bd_cfa_action =
 465                         cpu_to_le32(cfa_action << TX_BD_CFA_ACTION_SHIFT);
 466
 467                 end = pdata + length;
 468                 end = PTR_ALIGN(end, 8) - 1;
 469                 *end = 0;
 470
 471                 skb_copy_from_linear_data(skb, pdata, len);
 472                 pdata += len;
 473                 for (j = 0; j < last_frag; j++) {
 474                         skb_frag_t *frag = &skb_shinfo(skb)->frags[j];
 475                         void *fptr;
 476
 477                         fptr = skb_frag_address_safe(frag);
 478                         if (!fptr)
 479                                 goto normal_tx;
 480
 481                         memcpy(pdata, fptr, skb_frag_size(frag));
 482                         pdata += skb_frag_size(frag);
 483                 }
 484
 485                 txbd->tx_bd_len_flags_type = tx_push->tx_bd_len_flags_type;
 486                 txbd->tx_bd_haddr = txr->data_mapping;
 487                 prod = NEXT_TX(prod);
 488                 txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
 489                 memcpy(txbd, tx_push1, sizeof(*txbd));
 490                 prod = NEXT_TX(prod);
 491                 tx_push->doorbell =
 492                         cpu_to_le32(DB_KEY_TX_PUSH | DB_LONG_TX_PUSH | prod);
 493                 txr->tx_prod = prod;
 494
 495                 tx_buf->is_push = 1;
 496                 netdev_tx_sent_queue(txq, skb->len);
 497                 wmb();  /* Sync is_push and byte queue before pushing data */
 498
 499                 push_len = (length + sizeof(*tx_push) + 7) / 8;
 500                 if (push_len > 16) {
 501                         __iowrite64_copy(db, tx_push_buf, 16);
 502                         __iowrite32_copy(db + 4, tx_push_buf + 1,
 503                                          (push_len - 16) << 1);
 504                 } else {
 505                         __iowrite64_copy(db, tx_push_buf, push_len);
 506                 }
 507
 508                 goto tx_done;
 509         }
 510
 511 normal_tx:
 512         if (length < BNXT_MIN_PKT_SIZE) {
 513                 pad = BNXT_MIN_PKT_SIZE - length;
 514                 if (skb_pad(skb, pad))
 515                         /* SKB already freed. */
 516                         goto tx_kick_pending;
 517                 length = BNXT_MIN_PKT_SIZE;
 518         }
 519
 520         mapping = dma_map_single(&pdev->dev, skb->data, len, DMA_TO_DEVICE);
 521
 522         if (unlikely(dma_mapping_error(&pdev->dev, mapping)))
 523                 goto tx_free;
 524
 525         dma_unmap_addr_set(tx_buf, mapping, mapping);
 526         flags = (len << TX_BD_LEN_SHIFT) | TX_BD_TYPE_LONG_TX_BD |
 527                 ((last_frag + 2) << TX_BD_FLAGS_BD_CNT_SHIFT);
 528
 529         txbd->tx_bd_haddr = cpu_to_le64(mapping);
 530
 531         prod = NEXT_TX(prod);
 532         txbd1 = (struct tx_bd_ext *)
 533                 &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
 534
 535         txbd1->tx_bd_hsize_lflags = lflags;
 536         if (skb_is_gso(skb)) {
 537                 u32 hdr_len;
 538
 539                 if (skb->encapsulation)
 540                         hdr_len = skb_inner_tcp_all_headers(skb);
 541                 else
 542                         hdr_len = skb_tcp_all_headers(skb);
 543
 544                 txbd1->tx_bd_hsize_lflags |= cpu_to_le32(TX_BD_FLAGS_LSO |
 545                                         TX_BD_FLAGS_T_IPID |
 546                                         (hdr_len << (TX_BD_HSIZE_SHIFT - 1)));
 547                 length = skb_shinfo(skb)->gso_size;
 548                 txbd1->tx_bd_mss = cpu_to_le32(length);
 549                 length += hdr_len;
 550         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
 551                 txbd1->tx_bd_hsize_lflags |=
 552                         cpu_to_le32(TX_BD_FLAGS_TCP_UDP_CHKSUM);
 553                 txbd1->tx_bd_mss = 0;
 554         }
 555
 556         length >>= 9;
 557         if (unlikely(length >= ARRAY_SIZE(bnxt_lhint_arr))) {
 558                 dev_warn_ratelimited(&pdev->dev, "Dropped oversize %d bytes TX packet.\n",
 559                                      skb->len);
 560                 i = 0;
 561                 goto tx_dma_error;
 562         }
 563         flags |= bnxt_lhint_arr[length];
 564         txbd->tx_bd_len_flags_type = cpu_to_le32(flags);
 565
 566         txbd1->tx_bd_cfa_meta = cpu_to_le32(vlan_tag_flags);
 567         txbd1->tx_bd_cfa_action =
 568                         cpu_to_le32(cfa_action << TX_BD_CFA_ACTION_SHIFT);
 569         for (i = 0; i < last_frag; i++) {
 570                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
 571
 572                 prod = NEXT_TX(prod);
 573                 txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
 574
 575                 len = skb_frag_size(frag);
 576                 mapping = skb_frag_dma_map(&pdev->dev, frag, 0, len,
 577                                            DMA_TO_DEVICE);
 578
 579                 if (unlikely(dma_mapping_error(&pdev->dev, mapping)))
 580                         goto tx_dma_error;
 581
 582                 tx_buf = &txr->tx_buf_ring[prod];
 583                 dma_unmap_addr_set(tx_buf, mapping, mapping);
 584
 585                 txbd->tx_bd_haddr = cpu_to_le64(mapping);
 586
 587                 flags = len << TX_BD_LEN_SHIFT;
 588                 txbd->tx_bd_len_flags_type = cpu_to_le32(flags);
 589         }
 590
 591         flags &= ~TX_BD_LEN;
 592         txbd->tx_bd_len_flags_type =
 593                 cpu_to_le32(((len + pad) << TX_BD_LEN_SHIFT) | flags |
 594                             TX_BD_FLAGS_PACKET_END);
 595
 596         netdev_tx_sent_queue(txq, skb->len);
 597
 598         skb_tx_timestamp(skb);
 599
 600         /* Sync BD data before updating doorbell */
 601         wmb();
 602
 603         prod = NEXT_TX(prod);
 604         txr->tx_prod = prod;
 605
 606         if (!netdev_xmit_more() || netif_xmit_stopped(txq))
 607                 bnxt_txr_db_kick(bp, txr, prod);
 608         else
 609                 txr->kick_pending = 1;
 610
 611 tx_done:
 612
 613         if (unlikely(bnxt_tx_avail(bp, txr) <= MAX_SKB_FRAGS + 1)) {
 614                 if (netdev_xmit_more() && !tx_buf->is_push)
 615                         bnxt_txr_db_kick(bp, txr, prod);
 616
 617                 bnxt_txr_netif_try_stop_queue(bp, txr, txq);
 618         }
 619         return NETDEV_TX_OK;
 620
 621 tx_dma_error:
 622         if (BNXT_TX_PTP_IS_SET(lflags))
 623                 atomic_inc(&bp->ptp_cfg->tx_avail);
 624
 625         last_frag = i;
 626
 627         /* start back at beginning and unmap skb */
 628         prod = txr->tx_prod;
 629         tx_buf = &txr->tx_buf_ring[prod];
 630         dma_unmap_single(&pdev->dev, dma_unmap_addr(tx_buf, mapping),
 631                          skb_headlen(skb), DMA_TO_DEVICE);
 632         prod = NEXT_TX(prod);
 633
 634         /* unmap remaining mapped pages */
 635         for (i = 0; i < last_frag; i++) {
 636                 prod = NEXT_TX(prod);
 637                 tx_buf = &txr->tx_buf_ring[prod];
 638                 dma_unmap_page(&pdev->dev, dma_unmap_addr(tx_buf, mapping),
 639                                skb_frag_size(&skb_shinfo(skb)->frags[i]),
 640                                DMA_TO_DEVICE);
 641         }
 642
 643 tx_free:
 644         dev_kfree_skb_any(skb);
 645 tx_kick_pending:
 646         if (txr->kick_pending)
 647                 bnxt_txr_db_kick(bp, txr, txr->tx_prod);
 648         txr->tx_buf_ring[txr->tx_prod].skb = NULL;
 649         dev_core_stats_tx_dropped_inc(dev);
 650         return NETDEV_TX_OK;
 651 }
 652
 653 static void bnxt_tx_int(struct bnxt *bp, struct bnxt_napi *bnapi, int nr_pkts)
 654 {
 655         struct bnxt_tx_ring_info *txr = bnapi->tx_ring;
 656         struct netdev_queue *txq = netdev_get_tx_queue(bp->dev, txr->txq_index);
 657         u16 cons = txr->tx_cons;
 658         struct pci_dev *pdev = bp->pdev;
 659         int i;
 660         unsigned int tx_bytes = 0;
 661
 662         for (i = 0; i < nr_pkts; i++) {
 663                 struct bnxt_sw_tx_bd *tx_buf;
 664                 struct sk_buff *skb;
 665                 int j, last;
 666
 667                 tx_buf = &txr->tx_buf_ring[cons];
 668                 cons = NEXT_TX(cons);
 669                 skb = tx_buf->skb;
 670                 tx_buf->skb = NULL;
 671
 672                 tx_bytes += skb->len;
 673
 674                 if (tx_buf->is_push) {
 675                         tx_buf->is_push = 0;
 676                         goto next_tx_int;
 677                 }
 678
 679                 dma_unmap_single(&pdev->dev, dma_unmap_addr(tx_buf, mapping),
 680                                  skb_headlen(skb), DMA_TO_DEVICE);
 681                 last = tx_buf->nr_frags;
 682
 683                 for (j = 0; j < last; j++) {
 684                         cons = NEXT_TX(cons);
 685                         tx_buf = &txr->tx_buf_ring[cons];
 686                         dma_unmap_page(
 687                                 &pdev->dev,
 688                                 dma_unmap_addr(tx_buf, mapping),
 689                                 skb_frag_size(&skb_shinfo(skb)->frags[j]),
 690                                 DMA_TO_DEVICE);
 691                 }
 692                 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)) {
 693                         if (bp->flags & BNXT_FLAG_CHIP_P5) {
 694                                 /* PTP worker takes ownership of the skb */
 695                                 if (!bnxt_get_tx_ts_p5(bp, skb))
 696                                         skb = NULL;
 697                                 else
 698                                         atomic_inc(&bp->ptp_cfg->tx_avail);
 699                         }
 700                 }
 701
 702 next_tx_int:
 703                 cons = NEXT_TX(cons);
 704
 705                 dev_kfree_skb_any(skb);
 706         }
 707
 708         netdev_tx_completed_queue(txq, nr_pkts, tx_bytes);
 709         txr->tx_cons = cons;
 710
 711         /* Need to make the tx_cons update visible to bnxt_start_xmit()
 712          * before checking for netif_tx_queue_stopped().  Without the
 713          * memory barrier, there is a small possibility that bnxt_start_xmit()
 714          * will miss it and cause the queue to be stopped forever.
 715          */
 716         smp_mb();
 717
 718         if (unlikely(netif_tx_queue_stopped(txq)) &&
 719             bnxt_tx_avail(bp, txr) >= bp->tx_wake_thresh &&
 720             READ_ONCE(txr->dev_state) != BNXT_DEV_STATE_CLOSING)
 721                 netif_tx_wake_queue(txq);
 722 }
 723
 724 static struct page *__bnxt_alloc_rx_page(struct bnxt *bp, dma_addr_t *mapping,
 725                                          struct bnxt_rx_ring_info *rxr,
 726                                          gfp_t gfp)
 727 {
 728         struct device *dev = &bp->pdev->dev;
 729         struct page *page;
 730
 731         page = page_pool_dev_alloc_pages(rxr->page_pool);
 732         if (!page)
 733                 return NULL;
 734
 735         *mapping = dma_map_page_attrs(dev, page, 0, PAGE_SIZE, bp->rx_dir,
 736                                       DMA_ATTR_WEAK_ORDERING);
 737         if (dma_mapping_error(dev, *mapping)) {
 738                 page_pool_recycle_direct(rxr->page_pool, page);
 739                 return NULL;
 740         }
 741         return page;
 742 }
 743
 744 static inline u8 *__bnxt_alloc_rx_frag(struct bnxt *bp, dma_addr_t *mapping,
 745                                        gfp_t gfp)
 746 {
 747         u8 *data;
 748         struct pci_dev *pdev = bp->pdev;
 749
 750         if (gfp == GFP_ATOMIC)
 751                 data = napi_alloc_frag(bp->rx_buf_size);
 752         else
 753                 data = netdev_alloc_frag(bp->rx_buf_size);
 754         if (!data)
 755                 return NULL;
 756
 757         *mapping = dma_map_single_attrs(&pdev->dev, data + bp->rx_dma_offset,
 758                                         bp->rx_buf_use_size, bp->rx_dir,
 759                                         DMA_ATTR_WEAK_ORDERING);
 760
 761         if (dma_mapping_error(&pdev->dev, *mapping)) {
 762                 skb_free_frag(data);
 763                 data = NULL;
 764         }
 765         return data;
 766 }
 767
 768 int bnxt_alloc_rx_data(struct bnxt *bp, struct bnxt_rx_ring_info *rxr,
 769                        u16 prod, gfp_t gfp)
 770 {
 771         struct rx_bd *rxbd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
 772         struct bnxt_sw_rx_bd *rx_buf = &rxr->rx_buf_ring[prod];
 773         dma_addr_t mapping;
 774
 775         if (BNXT_RX_PAGE_MODE(bp)) {
 776                 struct page *page =
 777                         __bnxt_alloc_rx_page(bp, &mapping, rxr, gfp);
 778
 779                 if (!page)
 780                         return -ENOMEM;
 781
 782                 mapping += bp->rx_dma_offset;
 783                 rx_buf->data = page;
 784                 rx_buf->data_ptr = page_address(page) + bp->rx_offset;
 785         } else {
 786                 u8 *data = __bnxt_alloc_rx_frag(bp, &mapping, gfp);
 787
 788                 if (!data)
 789                         return -ENOMEM;
 790
 791                 rx_buf->data = data;
 792                 rx_buf->data_ptr = data + bp->rx_offset;
 793         }
 794         rx_buf->mapping = mapping;
 795
 796         rxbd->rx_bd_haddr = cpu_to_le64(mapping);
 797         return 0;
 798 }
 799
 800 void bnxt_reuse_rx_data(struct bnxt_rx_ring_info *rxr, u16 cons, void *data)
 801 {
 802         u16 prod = rxr->rx_prod;
 803         struct bnxt_sw_rx_bd *cons_rx_buf, *prod_rx_buf;
 804         struct rx_bd *cons_bd, *prod_bd;
 805
 806         prod_rx_buf = &rxr->rx_buf_ring[prod];
 807         cons_rx_buf = &rxr->rx_buf_ring[cons];
 808
 809         prod_rx_buf->data = data;
 810         prod_rx_buf->data_ptr = cons_rx_buf->data_ptr;
 811
 812         prod_rx_buf->mapping = cons_rx_buf->mapping;
 813
 814         prod_bd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
 815         cons_bd = &rxr->rx_desc_ring[RX_RING(cons)][RX_IDX(cons)];
 816
 817         prod_bd->rx_bd_haddr = cons_bd->rx_bd_haddr;
 818 }
 819
 820 static inline u16 bnxt_find_next_agg_idx(struct bnxt_rx_ring_info *rxr, u16 idx)
 821 {
 822         u16 next, max = rxr->rx_agg_bmap_size;
 823
 824         next = find_next_zero_bit(rxr->rx_agg_bmap, max, idx);
 825         if (next >= max)
 826                 next = find_first_zero_bit(rxr->rx_agg_bmap, max);
 827         return next;
 828 }
 829
 830 static inline int bnxt_alloc_rx_page(struct bnxt *bp,
 831                                      struct bnxt_rx_ring_info *rxr,
 832                                      u16 prod, gfp_t gfp)
 833 {
 834         struct rx_bd *rxbd =
 835                 &rxr->rx_agg_desc_ring[RX_RING(prod)][RX_IDX(prod)];
 836         struct bnxt_sw_rx_agg_bd *rx_agg_buf;
 837         struct pci_dev *pdev = bp->pdev;
 838         struct page *page;
 839         dma_addr_t mapping;
 840         u16 sw_prod = rxr->rx_sw_agg_prod;
 841         unsigned int offset = 0;
 842
 843         if (BNXT_RX_PAGE_MODE(bp)) {
 844                 page = __bnxt_alloc_rx_page(bp, &mapping, rxr, gfp);
 845
 846                 if (!page)
 847                         return -ENOMEM;
 848
 849         } else {
 850                 if (PAGE_SIZE > BNXT_RX_PAGE_SIZE) {
 851                         page = rxr->rx_page;
 852                         if (!page) {
 853                                 page = alloc_page(gfp);
 854                                 if (!page)
 855                                         return -ENOMEM;
 856                                 rxr->rx_page = page;
 857                                 rxr->rx_page_offset = 0;
 858                         }
 859                         offset = rxr->rx_page_offset;
 860                         rxr->rx_page_offset += BNXT_RX_PAGE_SIZE;
 861                         if (rxr->rx_page_offset == PAGE_SIZE)
 862                                 rxr->rx_page = NULL;
 863                         else
 864                                 get_page(page);
 865                 } else {
 866                         page = alloc_page(gfp);
 867                         if (!page)
 868                                 return -ENOMEM;
 869                 }
 870
 871                 mapping = dma_map_page_attrs(&pdev->dev, page, offset,
 872                                              BNXT_RX_PAGE_SIZE, DMA_FROM_DEVICE,
 873                                              DMA_ATTR_WEAK_ORDERING);
 874                 if (dma_mapping_error(&pdev->dev, mapping)) {
 875                         __free_page(page);
 876                         return -EIO;
 877                 }
 878         }
 879
 880         if (unlikely(test_bit(sw_prod, rxr->rx_agg_bmap)))
 881                 sw_prod = bnxt_find_next_agg_idx(rxr, sw_prod);
 882
 883         __set_bit(sw_prod, rxr->rx_agg_bmap);
 884         rx_agg_buf = &rxr->rx_agg_ring[sw_prod];
 885         rxr->rx_sw_agg_prod = NEXT_RX_AGG(sw_prod);
 886
 887         rx_agg_buf->page = page;
 888         rx_agg_buf->offset = offset;
 889         rx_agg_buf->mapping = mapping;
 890         rxbd->rx_bd_haddr = cpu_to_le64(mapping);
 891         rxbd->rx_bd_opaque = sw_prod;
 892         return 0;
 893 }
 894
 895 static struct rx_agg_cmp *bnxt_get_agg(struct bnxt *bp,
 896                                        struct bnxt_cp_ring_info *cpr,
 897                                        u16 cp_cons, u16 curr)
 898 {
 899         struct rx_agg_cmp *agg;
 900
 901         cp_cons = RING_CMP(ADV_RAW_CMP(cp_cons, curr));
 902         agg = (struct rx_agg_cmp *)
 903                 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
 904         return agg;
 905 }
 906
 907 static struct rx_agg_cmp *bnxt_get_tpa_agg_p5(struct bnxt *bp,
 908                                               struct bnxt_rx_ring_info *rxr,
 909                                               u16 agg_id, u16 curr)
 910 {
 911         struct bnxt_tpa_info *tpa_info = &rxr->rx_tpa[agg_id];
 912
 913         return &tpa_info->agg_arr[curr];
 914 }
 915
 916 static void bnxt_reuse_rx_agg_bufs(struct bnxt_cp_ring_info *cpr, u16 idx,
 917                                    u16 start, u32 agg_bufs, bool tpa)
 918 {
 919         struct bnxt_napi *bnapi = cpr->bnapi;
 920         struct bnxt *bp = bnapi->bp;
 921         struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
 922         u16 prod = rxr->rx_agg_prod;
 923         u16 sw_prod = rxr->rx_sw_agg_prod;
 924         bool p5_tpa = false;
 925         u32 i;
 926
 927         if ((bp->flags & BNXT_FLAG_CHIP_P5) && tpa)
 928                 p5_tpa = true;
 929
 930         for (i = 0; i < agg_bufs; i++) {
 931                 u16 cons;
 932                 struct rx_agg_cmp *agg;
 933                 struct bnxt_sw_rx_agg_bd *cons_rx_buf, *prod_rx_buf;
 934                 struct rx_bd *prod_bd;
 935                 struct page *page;
 936
 937                 if (p5_tpa)
 938                         agg = bnxt_get_tpa_agg_p5(bp, rxr, idx, start + i);
 939                 else
 940                         agg = bnxt_get_agg(bp, cpr, idx, start + i);
 941                 cons = agg->rx_agg_cmp_opaque;
 942                 __clear_bit(cons, rxr->rx_agg_bmap);
 943
 944                 if (unlikely(test_bit(sw_prod, rxr->rx_agg_bmap)))
 945                         sw_prod = bnxt_find_next_agg_idx(rxr, sw_prod);
 946
 947                 __set_bit(sw_prod, rxr->rx_agg_bmap);
 948                 prod_rx_buf = &rxr->rx_agg_ring[sw_prod];
 949                 cons_rx_buf = &rxr->rx_agg_ring[cons];
 950
 951                 /* It is possible for sw_prod to be equal to cons, so
 952                  * set cons_rx_buf->page to NULL first.
 953                  */
 954                 page = cons_rx_buf->page;
 955                 cons_rx_buf->page = NULL;
 956                 prod_rx_buf->page = page;
 957                 prod_rx_buf->offset = cons_rx_buf->offset;
 958
 959                 prod_rx_buf->mapping = cons_rx_buf->mapping;
 960
 961                 prod_bd = &rxr->rx_agg_desc_ring[RX_RING(prod)][RX_IDX(prod)];
 962
 963                 prod_bd->rx_bd_haddr = cpu_to_le64(cons_rx_buf->mapping);
 964                 prod_bd->rx_bd_opaque = sw_prod;
 965
 966                 prod = NEXT_RX_AGG(prod);
 967                 sw_prod = NEXT_RX_AGG(sw_prod);
 968         }
 969         rxr->rx_agg_prod = prod;
 970         rxr->rx_sw_agg_prod = sw_prod;
 971 }
 972
 973 static struct sk_buff *bnxt_rx_multi_page_skb(struct bnxt *bp,
 974                                               struct bnxt_rx_ring_info *rxr,
 975                                               u16 cons, void *data, u8 *data_ptr,
 976                                               dma_addr_t dma_addr,
 977                                               unsigned int offset_and_len)
 978 {
 979         unsigned int len = offset_and_len & 0xffff;
 980         struct page *page = data;
 981         u16 prod = rxr->rx_prod;
 982         struct sk_buff *skb;
 983         int err;
 984
 985         err = bnxt_alloc_rx_data(bp, rxr, prod, GFP_ATOMIC);
 986         if (unlikely(err)) {
 987                 bnxt_reuse_rx_data(rxr, cons, data);
 988                 return NULL;
 989         }
 990         dma_addr -= bp->rx_dma_offset;
 991         dma_unmap_page_attrs(&bp->pdev->dev, dma_addr, PAGE_SIZE, bp->rx_dir,
 992                              DMA_ATTR_WEAK_ORDERING);
 993         skb = build_skb(page_address(page), PAGE_SIZE);
 994         if (!skb) {
 995                 page_pool_recycle_direct(rxr->page_pool, page);
 996                 return NULL;
 997         }
 998         skb_mark_for_recycle(skb);
 999         skb_reserve(skb, bp->rx_dma_offset);
1000         __skb_put(skb, len);
1001
1002         return skb;
1003 }
1004
1005 static struct sk_buff *bnxt_rx_page_skb(struct bnxt *bp,
1006                                         struct bnxt_rx_ring_info *rxr,
1007                                         u16 cons, void *data, u8 *data_ptr,
1008                                         dma_addr_t dma_addr,
1009                                         unsigned int offset_and_len)
1010 {
1011         unsigned int payload = offset_and_len >> 16;
1012         unsigned int len = offset_and_len & 0xffff;
1013         skb_frag_t *frag;
1014         struct page *page = data;
1015         u16 prod = rxr->rx_prod;
1016         struct sk_buff *skb;
1017         int off, err;
1018
1019         err = bnxt_alloc_rx_data(bp, rxr, prod, GFP_ATOMIC);
1020         if (unlikely(err)) {
1021                 bnxt_reuse_rx_data(rxr, cons, data);
1022                 return NULL;
1023         }
1024         dma_addr -= bp->rx_dma_offset;
1025         dma_unmap_page_attrs(&bp->pdev->dev, dma_addr, PAGE_SIZE, bp->rx_dir,
1026                              DMA_ATTR_WEAK_ORDERING);
1027
1028         if (unlikely(!payload))
1029                 payload = eth_get_headlen(bp->dev, data_ptr, len);
1030
1031         skb = napi_alloc_skb(&rxr->bnapi->napi, payload);
1032         if (!skb) {
1033                 page_pool_recycle_direct(rxr->page_pool, page);
1034                 return NULL;
1035         }
1036
1037         skb_mark_for_recycle(skb);
1038         off = (void *)data_ptr - page_address(page);
1039         skb_add_rx_frag(skb, 0, page, off, len, PAGE_SIZE);
1040         memcpy(skb->data - NET_IP_ALIGN, data_ptr - NET_IP_ALIGN,
1041                payload + NET_IP_ALIGN);
1042
1043         frag = &skb_shinfo(skb)->frags[0];
1044         skb_frag_size_sub(frag, payload);
1045         skb_frag_off_add(frag, payload);
1046         skb->data_len -= payload;
1047         skb->tail += payload;
1048
1049         return skb;
1050 }
1051
1052 static struct sk_buff *bnxt_rx_skb(struct bnxt *bp,
1053                                    struct bnxt_rx_ring_info *rxr, u16 cons,
1054                                    void *data, u8 *data_ptr,
1055                                    dma_addr_t dma_addr,
1056                                    unsigned int offset_and_len)
1057 {
1058         u16 prod = rxr->rx_prod;
1059         struct sk_buff *skb;
1060         int err;
1061
1062         err = bnxt_alloc_rx_data(bp, rxr, prod, GFP_ATOMIC);
1063         if (unlikely(err)) {
1064                 bnxt_reuse_rx_data(rxr, cons, data);
1065                 return NULL;
1066         }
1067
1068         skb = build_skb(data, bp->rx_buf_size);
1069         dma_unmap_single_attrs(&bp->pdev->dev, dma_addr, bp->rx_buf_use_size,
1070                                bp->rx_dir, DMA_ATTR_WEAK_ORDERING);
1071         if (!skb) {
1072                 skb_free_frag(data);
1073                 return NULL;
1074         }
1075
1076         skb_reserve(skb, bp->rx_offset);
1077         skb_put(skb, offset_and_len & 0xffff);
1078         return skb;
1079 }
1080
1081 static u32 __bnxt_rx_agg_pages(struct bnxt *bp,
1082                                struct bnxt_cp_ring_info *cpr,
1083                                struct skb_shared_info *shinfo,
1084                                u16 idx, u32 agg_bufs, bool tpa,
1085                                struct xdp_buff *xdp)
1086 {
1087         struct bnxt_napi *bnapi = cpr->bnapi;
1088         struct pci_dev *pdev = bp->pdev;
1089         struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
1090         u16 prod = rxr->rx_agg_prod;
1091         u32 i, total_frag_len = 0;
1092         bool p5_tpa = false;
1093
1094         if ((bp->flags & BNXT_FLAG_CHIP_P5) && tpa)
1095                 p5_tpa = true;
1096
1097         for (i = 0; i < agg_bufs; i++) {
1098                 skb_frag_t *frag = &shinfo->frags[i];
1099                 u16 cons, frag_len;
1100                 struct rx_agg_cmp *agg;
1101                 struct bnxt_sw_rx_agg_bd *cons_rx_buf;
1102                 struct page *page;
1103                 dma_addr_t mapping;
1104
1105                 if (p5_tpa)
1106                         agg = bnxt_get_tpa_agg_p5(bp, rxr, idx, i);
1107                 else
1108                         agg = bnxt_get_agg(bp, cpr, idx, i);
1109                 cons = agg->rx_agg_cmp_opaque;
1110                 frag_len = (le32_to_cpu(agg->rx_agg_cmp_len_flags_type) &
1111                             RX_AGG_CMP_LEN) >> RX_AGG_CMP_LEN_SHIFT;
1112
1113                 cons_rx_buf = &rxr->rx_agg_ring[cons];
1114                 skb_frag_off_set(frag, cons_rx_buf->offset);
1115                 skb_frag_size_set(frag, frag_len);
1116                 __skb_frag_set_page(frag, cons_rx_buf->page);
1117                 shinfo->nr_frags = i + 1;
1118                 __clear_bit(cons, rxr->rx_agg_bmap);
1119
1120                 /* It is possible for bnxt_alloc_rx_page() to allocate
1121                  * a sw_prod index that equals the cons index, so we
1122                  * need to clear the cons entry now.
1123                  */
1124                 mapping = cons_rx_buf->mapping;
1125                 page = cons_rx_buf->page;
1126                 cons_rx_buf->page = NULL;
1127
1128                 if (xdp && page_is_pfmemalloc(page))
1129                         xdp_buff_set_frag_pfmemalloc(xdp);
1130
1131                 if (bnxt_alloc_rx_page(bp, rxr, prod, GFP_ATOMIC) != 0) {
1132                         unsigned int nr_frags;
1133
1134                         nr_frags = --shinfo->nr_frags;
1135                         __skb_frag_set_page(&shinfo->frags[nr_frags], NULL);
1136                         cons_rx_buf->page = page;
1137
1138                         /* Update prod since possibly some pages have been
1139                          * allocated already.
1140                          */
1141                         rxr->rx_agg_prod = prod;
1142                         bnxt_reuse_rx_agg_bufs(cpr, idx, i, agg_bufs - i, tpa);
1143                         return 0;
1144                 }
1145
1146                 dma_unmap_page_attrs(&pdev->dev, mapping, BNXT_RX_PAGE_SIZE,
1147                                      bp->rx_dir,
1148                                      DMA_ATTR_WEAK_ORDERING);
1149
1150                 total_frag_len += frag_len;
1151                 prod = NEXT_RX_AGG(prod);
1152         }
1153         rxr->rx_agg_prod = prod;
1154         return total_frag_len;
1155 }
1156
1157 static struct sk_buff *bnxt_rx_agg_pages_skb(struct bnxt *bp,
1158                                              struct bnxt_cp_ring_info *cpr,
1159                                              struct sk_buff *skb, u16 idx,
1160                                              u32 agg_bufs, bool tpa)
1161 {
1162         struct skb_shared_info *shinfo = skb_shinfo(skb);
1163         u32 total_frag_len = 0;
1164
1165         total_frag_len = __bnxt_rx_agg_pages(bp, cpr, shinfo, idx,
1166                                              agg_bufs, tpa, NULL);
1167         if (!total_frag_len) {
1168                 dev_kfree_skb(skb);
1169                 return NULL;
1170         }
1171
1172         skb->data_len += total_frag_len;
1173         skb->len += total_frag_len;
1174         skb->truesize += PAGE_SIZE * agg_bufs;
1175         return skb;
1176 }
1177
1178 static u32 bnxt_rx_agg_pages_xdp(struct bnxt *bp,
1179                                  struct bnxt_cp_ring_info *cpr,
1180                                  struct xdp_buff *xdp, u16 idx,
1181                                  u32 agg_bufs, bool tpa)
1182 {
1183         struct skb_shared_info *shinfo = xdp_get_shared_info_from_buff(xdp);
1184         u32 total_frag_len = 0;
1185
1186         if (!xdp_buff_has_frags(xdp))
1187                 shinfo->nr_frags = 0;
1188
1189         total_frag_len = __bnxt_rx_agg_pages(bp, cpr, shinfo,
1190                                              idx, agg_bufs, tpa, xdp);
1191         if (total_frag_len) {
1192                 xdp_buff_set_frags_flag(xdp);
1193                 shinfo->nr_frags = agg_bufs;
1194                 shinfo->xdp_frags_size = total_frag_len;
1195         }
1196         return total_frag_len;
1197 }
1198
1199 static int bnxt_agg_bufs_valid(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1200                                u8 agg_bufs, u32 *raw_cons)
1201 {
1202         u16 last;
1203         struct rx_agg_cmp *agg;
1204
1205         *raw_cons = ADV_RAW_CMP(*raw_cons, agg_bufs);
1206         last = RING_CMP(*raw_cons);
1207         agg = (struct rx_agg_cmp *)
1208                 &cpr->cp_desc_ring[CP_RING(last)][CP_IDX(last)];
1209         return RX_AGG_CMP_VALID(agg, *raw_cons);
1210 }
1211
1212 static inline struct sk_buff *bnxt_copy_skb(struct bnxt_napi *bnapi, u8 *data,
1213                                             unsigned int len,
1214                                             dma_addr_t mapping)
1215 {
1216         struct bnxt *bp = bnapi->bp;
1217         struct pci_dev *pdev = bp->pdev;
1218         struct sk_buff *skb;
1219
1220         skb = napi_alloc_skb(&bnapi->napi, len);
1221         if (!skb)
1222                 return NULL;
1223
1224         dma_sync_single_for_cpu(&pdev->dev, mapping, bp->rx_copy_thresh,
1225                                 bp->rx_dir);
1226
1227         memcpy(skb->data - NET_IP_ALIGN, data - NET_IP_ALIGN,
1228                len + NET_IP_ALIGN);
1229
1230         dma_sync_single_for_device(&pdev->dev, mapping, bp->rx_copy_thresh,
1231                                    bp->rx_dir);
1232
1233         skb_put(skb, len);
1234         return skb;
1235 }
1236
1237 static int bnxt_discard_rx(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1238                            u32 *raw_cons, void *cmp)
1239 {
1240         struct rx_cmp *rxcmp = cmp;
1241         u32 tmp_raw_cons = *raw_cons;
1242         u8 cmp_type, agg_bufs = 0;
1243
1244         cmp_type = RX_CMP_TYPE(rxcmp);
1245
1246         if (cmp_type == CMP_TYPE_RX_L2_CMP) {
1247                 agg_bufs = (le32_to_cpu(rxcmp->rx_cmp_misc_v1) &
1248                             RX_CMP_AGG_BUFS) >>
1249                            RX_CMP_AGG_BUFS_SHIFT;
1250         } else if (cmp_type == CMP_TYPE_RX_L2_TPA_END_CMP) {
1251                 struct rx_tpa_end_cmp *tpa_end = cmp;
1252
1253                 if (bp->flags & BNXT_FLAG_CHIP_P5)
1254                         return 0;
1255
1256                 agg_bufs = TPA_END_AGG_BUFS(tpa_end);
1257         }
1258
1259         if (agg_bufs) {
1260                 if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, &tmp_raw_cons))
1261                         return -EBUSY;
1262         }
1263         *raw_cons = tmp_raw_cons;
1264         return 0;
1265 }
1266
1267 static void bnxt_queue_fw_reset_work(struct bnxt *bp, unsigned long delay)
1268 {
1269         if (!(test_bit(BNXT_STATE_IN_FW_RESET, &bp->state)))
1270                 return;
1271
1272         if (BNXT_PF(bp))
1273                 queue_delayed_work(bnxt_pf_wq, &bp->fw_reset_task, delay);
1274         else
1275                 schedule_delayed_work(&bp->fw_reset_task, delay);
1276 }
1277
1278 static void bnxt_queue_sp_work(struct bnxt *bp)
1279 {
1280         if (BNXT_PF(bp))
1281                 queue_work(bnxt_pf_wq, &bp->sp_task);
1282         else
1283                 schedule_work(&bp->sp_task);
1284 }
1285
1286 static void bnxt_sched_reset(struct bnxt *bp, struct bnxt_rx_ring_info *rxr)
1287 {
1288         if (!rxr->bnapi->in_reset) {
1289                 rxr->bnapi->in_reset = true;
1290                 if (bp->flags & BNXT_FLAG_CHIP_P5)
1291                         set_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event);
1292                 else
1293                         set_bit(BNXT_RST_RING_SP_EVENT, &bp->sp_event);
1294                 bnxt_queue_sp_work(bp);
1295         }
1296         rxr->rx_next_cons = 0xffff;
1297 }
1298
1299 static u16 bnxt_alloc_agg_idx(struct bnxt_rx_ring_info *rxr, u16 agg_id)
1300 {
1301         struct bnxt_tpa_idx_map *map = rxr->rx_tpa_idx_map;
1302         u16 idx = agg_id & MAX_TPA_P5_MASK;
1303
1304         if (test_bit(idx, map->agg_idx_bmap))
1305                 idx = find_first_zero_bit(map->agg_idx_bmap,
1306                                           BNXT_AGG_IDX_BMAP_SIZE);
1307         __set_bit(idx, map->agg_idx_bmap);
1308         map->agg_id_tbl[agg_id] = idx;
1309         return idx;
1310 }
1311
1312 static void bnxt_free_agg_idx(struct bnxt_rx_ring_info *rxr, u16 idx)
1313 {
1314         struct bnxt_tpa_idx_map *map = rxr->rx_tpa_idx_map;
1315
1316         __clear_bit(idx, map->agg_idx_bmap);
1317 }
1318
1319 static u16 bnxt_lookup_agg_idx(struct bnxt_rx_ring_info *rxr, u16 agg_id)
1320 {
1321         struct bnxt_tpa_idx_map *map = rxr->rx_tpa_idx_map;
1322
1323         return map->agg_id_tbl[agg_id];
1324 }
1325
1326 static void bnxt_tpa_start(struct bnxt *bp, struct bnxt_rx_ring_info *rxr,
1327                            struct rx_tpa_start_cmp *tpa_start,
1328                            struct rx_tpa_start_cmp_ext *tpa_start1)
1329 {
1330         struct bnxt_sw_rx_bd *cons_rx_buf, *prod_rx_buf;
1331         struct bnxt_tpa_info *tpa_info;
1332         u16 cons, prod, agg_id;
1333         struct rx_bd *prod_bd;
1334         dma_addr_t mapping;
1335
1336         if (bp->flags & BNXT_FLAG_CHIP_P5) {
1337                 agg_id = TPA_START_AGG_ID_P5(tpa_start);
1338                 agg_id = bnxt_alloc_agg_idx(rxr, agg_id);
1339         } else {
1340                 agg_id = TPA_START_AGG_ID(tpa_start);
1341         }
1342         cons = tpa_start->rx_tpa_start_cmp_opaque;
1343         prod = rxr->rx_prod;
1344         cons_rx_buf = &rxr->rx_buf_ring[cons];
1345         prod_rx_buf = &rxr->rx_buf_ring[prod];
1346         tpa_info = &rxr->rx_tpa[agg_id];
1347
1348         if (unlikely(cons != rxr->rx_next_cons ||
1349                      TPA_START_ERROR(tpa_start))) {
1350                 netdev_warn(bp->dev, "TPA cons %x, expected cons %x, error code %x\n",
1351                             cons, rxr->rx_next_cons,
1352                             TPA_START_ERROR_CODE(tpa_start1));
1353                 bnxt_sched_reset(bp, rxr);
1354                 return;
1355         }
1356         /* Store cfa_code in tpa_info to use in tpa_end
1357          * completion processing.
1358          */
1359         tpa_info->cfa_code = TPA_START_CFA_CODE(tpa_start1);
1360         prod_rx_buf->data = tpa_info->data;
1361         prod_rx_buf->data_ptr = tpa_info->data_ptr;
1362
1363         mapping = tpa_info->mapping;
1364         prod_rx_buf->mapping = mapping;
1365
1366         prod_bd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
1367
1368         prod_bd->rx_bd_haddr = cpu_to_le64(mapping);
1369
1370         tpa_info->data = cons_rx_buf->data;
1371         tpa_info->data_ptr = cons_rx_buf->data_ptr;
1372         cons_rx_buf->data = NULL;
1373         tpa_info->mapping = cons_rx_buf->mapping;
1374
1375         tpa_info->len =
1376                 le32_to_cpu(tpa_start->rx_tpa_start_cmp_len_flags_type) >>
1377                                 RX_TPA_START_CMP_LEN_SHIFT;
1378         if (likely(TPA_START_HASH_VALID(tpa_start))) {
1379                 u32 hash_type = TPA_START_HASH_TYPE(tpa_start);
1380
1381                 tpa_info->hash_type = PKT_HASH_TYPE_L4;
1382                 tpa_info->gso_type = SKB_GSO_TCPV4;
1383                 /* RSS profiles 1 and 3 with extract code 0 for inner 4-tuple */
1384                 if (hash_type == 3 || TPA_START_IS_IPV6(tpa_start1))
1385                         tpa_info->gso_type = SKB_GSO_TCPV6;
1386                 tpa_info->rss_hash =
1387                         le32_to_cpu(tpa_start->rx_tpa_start_cmp_rss_hash);
1388         } else {
1389                 tpa_info->hash_type = PKT_HASH_TYPE_NONE;
1390                 tpa_info->gso_type = 0;
1391                 netif_warn(bp, rx_err, bp->dev, "TPA packet without valid hash\n");
1392         }
1393         tpa_info->flags2 = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_flags2);
1394         tpa_info->metadata = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_metadata);
1395         tpa_info->hdr_info = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_hdr_info);
1396         tpa_info->agg_count = 0;
1397
1398         rxr->rx_prod = NEXT_RX(prod);
1399         cons = NEXT_RX(cons);
1400         rxr->rx_next_cons = NEXT_RX(cons);
1401         cons_rx_buf = &rxr->rx_buf_ring[cons];
1402
1403         bnxt_reuse_rx_data(rxr, cons, cons_rx_buf->data);
1404         rxr->rx_prod = NEXT_RX(rxr->rx_prod);
1405         cons_rx_buf->data = NULL;
1406 }
1407
1408 static void bnxt_abort_tpa(struct bnxt_cp_ring_info *cpr, u16 idx, u32 agg_bufs)
1409 {
1410         if (agg_bufs)
1411                 bnxt_reuse_rx_agg_bufs(cpr, idx, 0, agg_bufs, true);
1412 }
1413
1414 #ifdef CONFIG_INET
1415 static void bnxt_gro_tunnel(struct sk_buff *skb, __be16 ip_proto)
1416 {
1417         struct udphdr *uh = NULL;
1418
1419         if (ip_proto == htons(ETH_P_IP)) {
1420                 struct iphdr *iph = (struct iphdr *)skb->data;
1421
1422                 if (iph->protocol == IPPROTO_UDP)
1423                         uh = (struct udphdr *)(iph + 1);
1424         } else {
1425                 struct ipv6hdr *iph = (struct ipv6hdr *)skb->data;
1426
1427                 if (iph->nexthdr == IPPROTO_UDP)
1428                         uh = (struct udphdr *)(iph + 1);
1429         }
1430         if (uh) {
1431                 if (uh->check)
1432                         skb_shinfo(skb)->gso_type |= SKB_GSO_UDP_TUNNEL_CSUM;
1433                 else
1434                         skb_shinfo(skb)->gso_type |= SKB_GSO_UDP_TUNNEL;
1435         }
1436 }
1437 #endif
1438
1439 static struct sk_buff *bnxt_gro_func_5731x(struct bnxt_tpa_info *tpa_info,
1440                                            int payload_off, int tcp_ts,
1441                                            struct sk_buff *skb)
1442 {
1443 #ifdef CONFIG_INET
1444         struct tcphdr *th;
1445         int len, nw_off;
1446         u16 outer_ip_off, inner_ip_off, inner_mac_off;
1447         u32 hdr_info = tpa_info->hdr_info;
1448         bool loopback = false;
1449
1450         inner_ip_off = BNXT_TPA_INNER_L3_OFF(hdr_info);
1451         inner_mac_off = BNXT_TPA_INNER_L2_OFF(hdr_info);
1452         outer_ip_off = BNXT_TPA_OUTER_L3_OFF(hdr_info);
1453
1454         /* If the packet is an internal loopback packet, the offsets will
1455          * have an extra 4 bytes.
1456          */
1457         if (inner_mac_off == 4) {
1458                 loopback = true;
1459         } else if (inner_mac_off > 4) {
1460                 __be16 proto = *((__be16 *)(skb->data + inner_ip_off -
1461                                             ETH_HLEN - 2));
1462
1463                 /* We only support inner iPv4/ipv6.  If we don't see the
1464                  * correct protocol ID, it must be a loopback packet where
1465                  * the offsets are off by 4.
1466                  */
1467                 if (proto != htons(ETH_P_IP) && proto != htons(ETH_P_IPV6))
1468                         loopback = true;
1469         }
1470         if (loopback) {
1471                 /* internal loopback packet, subtract all offsets by 4 */
1472                 inner_ip_off -= 4;
1473                 inner_mac_off -= 4;
1474                 outer_ip_off -= 4;
1475         }
1476
1477         nw_off = inner_ip_off - ETH_HLEN;
1478         skb_set_network_header(skb, nw_off);
1479         if (tpa_info->flags2 & RX_TPA_START_CMP_FLAGS2_IP_TYPE) {
1480                 struct ipv6hdr *iph = ipv6_hdr(skb);
1481
1482                 skb_set_transport_header(skb, nw_off + sizeof(struct ipv6hdr));
1483                 len = skb->len - skb_transport_offset(skb);
1484                 th = tcp_hdr(skb);
1485                 th->check = ~tcp_v6_check(len, &iph->saddr, &iph->daddr, 0);
1486         } else {
1487                 struct iphdr *iph = ip_hdr(skb);
1488
1489                 skb_set_transport_header(skb, nw_off + sizeof(struct iphdr));
1490                 len = skb->len - skb_transport_offset(skb);
1491                 th = tcp_hdr(skb);
1492                 th->check = ~tcp_v4_check(len, iph->saddr, iph->daddr, 0);
1493         }
1494
1495         if (inner_mac_off) { /* tunnel */
1496                 __be16 proto = *((__be16 *)(skb->data + outer_ip_off -
1497                                             ETH_HLEN - 2));
1498
1499                 bnxt_gro_tunnel(skb, proto);
1500         }
1501 #endif
1502         return skb;
1503 }
1504
1505 static struct sk_buff *bnxt_gro_func_5750x(struct bnxt_tpa_info *tpa_info,
1506                                            int payload_off, int tcp_ts,
1507                                            struct sk_buff *skb)
1508 {
1509 #ifdef CONFIG_INET
1510         u16 outer_ip_off, inner_ip_off, inner_mac_off;
1511         u32 hdr_info = tpa_info->hdr_info;
1512         int iphdr_len, nw_off;
1513
1514         inner_ip_off = BNXT_TPA_INNER_L3_OFF(hdr_info);
1515         inner_mac_off = BNXT_TPA_INNER_L2_OFF(hdr_info);
1516         outer_ip_off = BNXT_TPA_OUTER_L3_OFF(hdr_info);
1517
1518         nw_off = inner_ip_off - ETH_HLEN;
1519         skb_set_network_header(skb, nw_off);
1520         iphdr_len = (tpa_info->flags2 & RX_TPA_START_CMP_FLAGS2_IP_TYPE) ?
1521                      sizeof(struct ipv6hdr) : sizeof(struct iphdr);
1522         skb_set_transport_header(skb, nw_off + iphdr_len);
1523
1524         if (inner_mac_off) { /* tunnel */
1525                 __be16 proto = *((__be16 *)(skb->data + outer_ip_off -
1526                                             ETH_HLEN - 2));
1527
1528                 bnxt_gro_tunnel(skb, proto);
1529         }
1530 #endif
1531         return skb;
1532 }
1533
1534 #define BNXT_IPV4_HDR_SIZE      (sizeof(struct iphdr) + sizeof(struct tcphdr))
1535 #define BNXT_IPV6_HDR_SIZE      (sizeof(struct ipv6hdr) + sizeof(struct tcphdr))
1536
1537 static struct sk_buff *bnxt_gro_func_5730x(struct bnxt_tpa_info *tpa_info,
1538                                            int payload_off, int tcp_ts,
1539                                            struct sk_buff *skb)
1540 {
1541 #ifdef CONFIG_INET
1542         struct tcphdr *th;
1543         int len, nw_off, tcp_opt_len = 0;
1544
1545         if (tcp_ts)
1546                 tcp_opt_len = 12;
1547
1548         if (tpa_info->gso_type == SKB_GSO_TCPV4) {
1549                 struct iphdr *iph;
1550
1551                 nw_off = payload_off - BNXT_IPV4_HDR_SIZE - tcp_opt_len -
1552                          ETH_HLEN;
1553                 skb_set_network_header(skb, nw_off);
1554                 iph = ip_hdr(skb);
1555                 skb_set_transport_header(skb, nw_off + sizeof(struct iphdr));
1556                 len = skb->len - skb_transport_offset(skb);
1557                 th = tcp_hdr(skb);
1558                 th->check = ~tcp_v4_check(len, iph->saddr, iph->daddr, 0);
1559         } else if (tpa_info->gso_type == SKB_GSO_TCPV6) {
1560                 struct ipv6hdr *iph;
1561
1562                 nw_off = payload_off - BNXT_IPV6_HDR_SIZE - tcp_opt_len -
1563                          ETH_HLEN;
1564                 skb_set_network_header(skb, nw_off);
1565                 iph = ipv6_hdr(skb);
1566                 skb_set_transport_header(skb, nw_off + sizeof(struct ipv6hdr));
1567                 len = skb->len - skb_transport_offset(skb);
1568                 th = tcp_hdr(skb);
1569                 th->check = ~tcp_v6_check(len, &iph->saddr, &iph->daddr, 0);
1570         } else {
1571                 dev_kfree_skb_any(skb);
1572                 return NULL;
1573         }
1574
1575         if (nw_off) /* tunnel */
1576                 bnxt_gro_tunnel(skb, skb->protocol);
1577 #endif
1578         return skb;
1579 }
1580
1581 static inline struct sk_buff *bnxt_gro_skb(struct bnxt *bp,
1582                                            struct bnxt_tpa_info *tpa_info,
1583                                            struct rx_tpa_end_cmp *tpa_end,
1584                                            struct rx_tpa_end_cmp_ext *tpa_end1,
1585                                            struct sk_buff *skb)
1586 {
1587 #ifdef CONFIG_INET
1588         int payload_off;
1589         u16 segs;
1590
1591         segs = TPA_END_TPA_SEGS(tpa_end);
1592         if (segs == 1)
1593                 return skb;
1594
1595         NAPI_GRO_CB(skb)->count = segs;
1596         skb_shinfo(skb)->gso_size =
1597                 le32_to_cpu(tpa_end1->rx_tpa_end_cmp_seg_len);
1598         skb_shinfo(skb)->gso_type = tpa_info->gso_type;
1599         if (bp->flags & BNXT_FLAG_CHIP_P5)
1600                 payload_off = TPA_END_PAYLOAD_OFF_P5(tpa_end1);
1601         else
1602                 payload_off = TPA_END_PAYLOAD_OFF(tpa_end);
1603         skb = bp->gro_func(tpa_info, payload_off, TPA_END_GRO_TS(tpa_end), skb);
1604         if (likely(skb))
1605                 tcp_gro_complete(skb);
1606 #endif
1607         return skb;
1608 }
1609
1610 /* Given the cfa_code of a received packet determine which
1611  * netdev (vf-rep or PF) the packet is destined to.
1612  */
1613 static struct net_device *bnxt_get_pkt_dev(struct bnxt *bp, u16 cfa_code)
1614 {
1615         struct net_device *dev = bnxt_get_vf_rep(bp, cfa_code);
1616
1617         /* if vf-rep dev is NULL, the must belongs to the PF */
1618         return dev ? dev : bp->dev;
1619 }
1620
1621 static inline struct sk_buff *bnxt_tpa_end(struct bnxt *bp,
1622                                            struct bnxt_cp_ring_info *cpr,
1623                                            u32 *raw_cons,
1624                                            struct rx_tpa_end_cmp *tpa_end,
1625                                            struct rx_tpa_end_cmp_ext *tpa_end1,
1626                                            u8 *event)
1627 {
1628         struct bnxt_napi *bnapi = cpr->bnapi;
1629         struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
1630         u8 *data_ptr, agg_bufs;
1631         unsigned int len;
1632         struct bnxt_tpa_info *tpa_info;
1633         dma_addr_t mapping;
1634         struct sk_buff *skb;
1635         u16 idx = 0, agg_id;
1636         void *data;
1637         bool gro;
1638
1639         if (unlikely(bnapi->in_reset)) {
1640                 int rc = bnxt_discard_rx(bp, cpr, raw_cons, tpa_end);
1641
1642                 if (rc < 0)
1643                         return ERR_PTR(-EBUSY);
1644                 return NULL;
1645         }
1646
1647         if (bp->flags & BNXT_FLAG_CHIP_P5) {
1648                 agg_id = TPA_END_AGG_ID_P5(tpa_end);
1649                 agg_id = bnxt_lookup_agg_idx(rxr, agg_id);
1650                 agg_bufs = TPA_END_AGG_BUFS_P5(tpa_end1);
1651                 tpa_info = &rxr->rx_tpa[agg_id];
1652                 if (unlikely(agg_bufs != tpa_info->agg_count)) {
1653                         netdev_warn(bp->dev, "TPA end agg_buf %d != expected agg_bufs %d\n",
1654                                     agg_bufs, tpa_info->agg_count);
1655                         agg_bufs = tpa_info->agg_count;
1656                 }
1657                 tpa_info->agg_count = 0;
1658                 *event |= BNXT_AGG_EVENT;
1659                 bnxt_free_agg_idx(rxr, agg_id);
1660                 idx = agg_id;
1661                 gro = !!(bp->flags & BNXT_FLAG_GRO);
1662         } else {
1663                 agg_id = TPA_END_AGG_ID(tpa_end);
1664                 agg_bufs = TPA_END_AGG_BUFS(tpa_end);
1665                 tpa_info = &rxr->rx_tpa[agg_id];
1666                 idx = RING_CMP(*raw_cons);
1667                 if (agg_bufs) {
1668                         if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, raw_cons))
1669                                 return ERR_PTR(-EBUSY);
1670
1671                         *event |= BNXT_AGG_EVENT;
1672                         idx = NEXT_CMP(idx);
1673                 }
1674                 gro = !!TPA_END_GRO(tpa_end);
1675         }
1676         data = tpa_info->data;
1677         data_ptr = tpa_info->data_ptr;
1678         prefetch(data_ptr);
1679         len = tpa_info->len;
1680         mapping = tpa_info->mapping;
1681
1682         if (unlikely(agg_bufs > MAX_SKB_FRAGS || TPA_END_ERRORS(tpa_end1))) {
1683                 bnxt_abort_tpa(cpr, idx, agg_bufs);
1684                 if (agg_bufs > MAX_SKB_FRAGS)
1685                         netdev_warn(bp->dev, "TPA frags %d exceeded MAX_SKB_FRAGS %d\n",
1686                                     agg_bufs, (int)MAX_SKB_FRAGS);
1687                 return NULL;
1688         }
1689
1690         if (len <= bp->rx_copy_thresh) {
1691                 skb = bnxt_copy_skb(bnapi, data_ptr, len, mapping);
1692                 if (!skb) {
1693                         bnxt_abort_tpa(cpr, idx, agg_bufs);
1694                         cpr->sw_stats.rx.rx_oom_discards += 1;
1695                         return NULL;
1696                 }
1697         } else {
1698                 u8 *new_data;
1699                 dma_addr_t new_mapping;
1700
1701                 new_data = __bnxt_alloc_rx_frag(bp, &new_mapping, GFP_ATOMIC);
1702                 if (!new_data) {
1703                         bnxt_abort_tpa(cpr, idx, agg_bufs);
1704                         cpr->sw_stats.rx.rx_oom_discards += 1;
1705                         return NULL;
1706                 }
1707
1708                 tpa_info->data = new_data;
1709                 tpa_info->data_ptr = new_data + bp->rx_offset;
1710                 tpa_info->mapping = new_mapping;
1711
1712                 skb = build_skb(data, bp->rx_buf_size);
1713                 dma_unmap_single_attrs(&bp->pdev->dev, mapping,
1714                                        bp->rx_buf_use_size, bp->rx_dir,
1715                                        DMA_ATTR_WEAK_ORDERING);
1716
1717                 if (!skb) {
1718                         skb_free_frag(data);
1719                         bnxt_abort_tpa(cpr, idx, agg_bufs);
1720                         cpr->sw_stats.rx.rx_oom_discards += 1;
1721                         return NULL;
1722                 }
1723                 skb_reserve(skb, bp->rx_offset);
1724                 skb_put(skb, len);
1725         }
1726
1727         if (agg_bufs) {
1728                 skb = bnxt_rx_agg_pages_skb(bp, cpr, skb, idx, agg_bufs, true);
1729                 if (!skb) {
1730                         /* Page reuse already handled by bnxt_rx_pages(). */
1731                         cpr->sw_stats.rx.rx_oom_discards += 1;
1732                         return NULL;
1733                 }
1734         }
1735
1736         skb->protocol =
1737                 eth_type_trans(skb, bnxt_get_pkt_dev(bp, tpa_info->cfa_code));
1738
1739         if (tpa_info->hash_type != PKT_HASH_TYPE_NONE)
1740                 skb_set_hash(skb, tpa_info->rss_hash, tpa_info->hash_type);
1741
1742         if ((tpa_info->flags2 & RX_CMP_FLAGS2_META_FORMAT_VLAN) &&
1743             (skb->dev->features & BNXT_HW_FEATURE_VLAN_ALL_RX)) {
1744                 __be16 vlan_proto = htons(tpa_info->metadata >>
1745                                           RX_CMP_FLAGS2_METADATA_TPID_SFT);
1746                 u16 vtag = tpa_info->metadata & RX_CMP_FLAGS2_METADATA_TCI_MASK;
1747
1748                 if (eth_type_vlan(vlan_proto)) {
1749                         __vlan_hwaccel_put_tag(skb, vlan_proto, vtag);
1750                 } else {
1751                         dev_kfree_skb(skb);
1752                         return NULL;
1753                 }
1754         }
1755
1756         skb_checksum_none_assert(skb);
1757         if (likely(tpa_info->flags2 & RX_TPA_START_CMP_FLAGS2_L4_CS_CALC)) {
1758                 skb->ip_summed = CHECKSUM_UNNECESSARY;
1759                 skb->csum_level =
1760                         (tpa_info->flags2 & RX_CMP_FLAGS2_T_L4_CS_CALC) >> 3;
1761         }
1762
1763         if (gro)
1764                 skb = bnxt_gro_skb(bp, tpa_info, tpa_end, tpa_end1, skb);
1765
1766         return skb;
1767 }
1768
1769 static void bnxt_tpa_agg(struct bnxt *bp, struct bnxt_rx_ring_info *rxr,
1770                          struct rx_agg_cmp *rx_agg)
1771 {
1772         u16 agg_id = TPA_AGG_AGG_ID(rx_agg);
1773         struct bnxt_tpa_info *tpa_info;
1774
1775         agg_id = bnxt_lookup_agg_idx(rxr, agg_id);
1776         tpa_info = &rxr->rx_tpa[agg_id];
1777         BUG_ON(tpa_info->agg_count >= MAX_SKB_FRAGS);
1778         tpa_info->agg_arr[tpa_info->agg_count++] = *rx_agg;
1779 }
1780
1781 static void bnxt_deliver_skb(struct bnxt *bp, struct bnxt_napi *bnapi,
1782                              struct sk_buff *skb)
1783 {
1784         if (skb->dev != bp->dev) {
1785                 /* this packet belongs to a vf-rep */
1786                 bnxt_vf_rep_rx(bp, skb);
1787                 return;
1788         }
1789         skb_record_rx_queue(skb, bnapi->index);
1790         napi_gro_receive(&bnapi->napi, skb);
1791 }
1792
1793 /* returns the following:
1794  * 1       - 1 packet successfully received
1795  * 0       - successful TPA_START, packet not completed yet
1796  * -EBUSY  - completion ring does not have all the agg buffers yet
1797  * -ENOMEM - packet aborted due to out of memory
1798  * -EIO    - packet aborted due to hw error indicated in BD
1799  */
1800 static int bnxt_rx_pkt(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1801                        u32 *raw_cons, u8 *event)
1802 {
1803         struct bnxt_napi *bnapi = cpr->bnapi;
1804         struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
1805         struct net_device *dev = bp->dev;
1806         struct rx_cmp *rxcmp;
1807         struct rx_cmp_ext *rxcmp1;
1808         u32 tmp_raw_cons = *raw_cons;
1809         u16 cfa_code, cons, prod, cp_cons = RING_CMP(tmp_raw_cons);
1810         struct bnxt_sw_rx_bd *rx_buf;
1811         unsigned int len;
1812         u8 *data_ptr, agg_bufs, cmp_type;
1813         bool xdp_active = false;
1814         dma_addr_t dma_addr;
1815         struct sk_buff *skb;
1816         struct xdp_buff xdp;
1817         u32 flags, misc;
1818         void *data;
1819         int rc = 0;
1820
1821         rxcmp = (struct rx_cmp *)
1822                         &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1823
1824         cmp_type = RX_CMP_TYPE(rxcmp);
1825
1826         if (cmp_type == CMP_TYPE_RX_TPA_AGG_CMP) {
1827                 bnxt_tpa_agg(bp, rxr, (struct rx_agg_cmp *)rxcmp);
1828                 goto next_rx_no_prod_no_len;
1829         }
1830
1831         tmp_raw_cons = NEXT_RAW_CMP(tmp_raw_cons);
1832         cp_cons = RING_CMP(tmp_raw_cons);
1833         rxcmp1 = (struct rx_cmp_ext *)
1834                         &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1835
1836         if (!RX_CMP_VALID(rxcmp1, tmp_raw_cons))
1837                 return -EBUSY;
1838
1839         /* The valid test of the entry must be done first before
1840          * reading any further.
1841          */
1842         dma_rmb();
1843         prod = rxr->rx_prod;
1844
1845         if (cmp_type == CMP_TYPE_RX_L2_TPA_START_CMP) {
1846                 bnxt_tpa_start(bp, rxr, (struct rx_tpa_start_cmp *)rxcmp,
1847                                (struct rx_tpa_start_cmp_ext *)rxcmp1);
1848
1849                 *event |= BNXT_RX_EVENT;
1850                 goto next_rx_no_prod_no_len;
1851
1852         } else if (cmp_type == CMP_TYPE_RX_L2_TPA_END_CMP) {
1853                 skb = bnxt_tpa_end(bp, cpr, &tmp_raw_cons,
1854                                    (struct rx_tpa_end_cmp *)rxcmp,
1855                                    (struct rx_tpa_end_cmp_ext *)rxcmp1, event);
1856
1857                 if (IS_ERR(skb))
1858                         return -EBUSY;
1859
1860                 rc = -ENOMEM;
1861                 if (likely(skb)) {
1862                         bnxt_deliver_skb(bp, bnapi, skb);
1863                         rc = 1;
1864                 }
1865                 *event |= BNXT_RX_EVENT;
1866                 goto next_rx_no_prod_no_len;
1867         }
1868
1869         cons = rxcmp->rx_cmp_opaque;
1870         if (unlikely(cons != rxr->rx_next_cons)) {
1871                 int rc1 = bnxt_discard_rx(bp, cpr, &tmp_raw_cons, rxcmp);
1872
1873                 /* 0xffff is forced error, don't print it */
1874                 if (rxr->rx_next_cons != 0xffff)
1875                         netdev_warn(bp->dev, "RX cons %x != expected cons %x\n",
1876                                     cons, rxr->rx_next_cons);
1877                 bnxt_sched_reset(bp, rxr);
1878                 if (rc1)
1879                         return rc1;
1880                 goto next_rx_no_prod_no_len;
1881         }
1882         rx_buf = &rxr->rx_buf_ring[cons];
1883         data = rx_buf->data;
1884         data_ptr = rx_buf->data_ptr;
1885         prefetch(data_ptr);
1886
1887         misc = le32_to_cpu(rxcmp->rx_cmp_misc_v1);
1888         agg_bufs = (misc & RX_CMP_AGG_BUFS) >> RX_CMP_AGG_BUFS_SHIFT;
1889
1890         if (agg_bufs) {
1891                 if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, &tmp_raw_cons))
1892                         return -EBUSY;
1893
1894                 cp_cons = NEXT_CMP(cp_cons);
1895                 *event |= BNXT_AGG_EVENT;
1896         }
1897         *event |= BNXT_RX_EVENT;
1898
1899         rx_buf->data = NULL;
1900         if (rxcmp1->rx_cmp_cfa_code_errors_v2 & RX_CMP_L2_ERRORS) {
1901                 u32 rx_err = le32_to_cpu(rxcmp1->rx_cmp_cfa_code_errors_v2);
1902
1903                 bnxt_reuse_rx_data(rxr, cons, data);
1904                 if (agg_bufs)
1905                         bnxt_reuse_rx_agg_bufs(cpr, cp_cons, 0, agg_bufs,
1906                                                false);
1907
1908                 rc = -EIO;
1909                 if (rx_err & RX_CMPL_ERRORS_BUFFER_ERROR_MASK) {
1910                         bnapi->cp_ring.sw_stats.rx.rx_buf_errors++;
1911                         if (!(bp->flags & BNXT_FLAG_CHIP_P5) &&
1912                             !(bp->fw_cap & BNXT_FW_CAP_RING_MONITOR)) {
1913                                 netdev_warn_once(bp->dev, "RX buffer error %x\n",
1914                                                  rx_err);
1915                                 bnxt_sched_reset(bp, rxr);
1916                         }
1917                 }
1918                 goto next_rx_no_len;
1919         }
1920
1921         flags = le32_to_cpu(rxcmp->rx_cmp_len_flags_type);
1922         len = flags >> RX_CMP_LEN_SHIFT;
1923         dma_addr = rx_buf->mapping;
1924
1925         if (bnxt_xdp_attached(bp, rxr)) {
1926                 bnxt_xdp_buff_init(bp, rxr, cons, data_ptr, len, &xdp);
1927                 if (agg_bufs) {
1928                         u32 frag_len = bnxt_rx_agg_pages_xdp(bp, cpr, &xdp,
1929                                                              cp_cons, agg_bufs,
1930                                                              false);
1931                         if (!frag_len) {
1932                                 cpr->sw_stats.rx.rx_oom_discards += 1;
1933                                 rc = -ENOMEM;
1934                                 goto next_rx;
1935                         }
1936                 }
1937                 xdp_active = true;
1938         }
1939
1940         if (xdp_active) {
1941                 if (bnxt_rx_xdp(bp, rxr, cons, xdp, data, &data_ptr, &len, event)) {
1942                         rc = 1;
1943                         goto next_rx;
1944                 }
1945         }
1946
1947         if (len <= bp->rx_copy_thresh) {
1948                 skb = bnxt_copy_skb(bnapi, data_ptr, len, dma_addr);
1949                 bnxt_reuse_rx_data(rxr, cons, data);
1950                 if (!skb) {
1951                         if (agg_bufs) {
1952                                 if (!xdp_active)
1953                                         bnxt_reuse_rx_agg_bufs(cpr, cp_cons, 0,
1954                                                                agg_bufs, false);
1955                                 else
1956                                         bnxt_xdp_buff_frags_free(rxr, &xdp);
1957                         }
1958                         cpr->sw_stats.rx.rx_oom_discards += 1;
1959                         rc = -ENOMEM;
1960                         goto next_rx;
1961                 }
1962         } else {
1963                 u32 payload;
1964
1965                 if (rx_buf->data_ptr == data_ptr)
1966                         payload = misc & RX_CMP_PAYLOAD_OFFSET;
1967                 else
1968                         payload = 0;
1969                 skb = bp->rx_skb_func(bp, rxr, cons, data, data_ptr, dma_addr,
1970                                       payload | len);
1971                 if (!skb) {
1972                         cpr->sw_stats.rx.rx_oom_discards += 1;
1973                         rc = -ENOMEM;
1974                         goto next_rx;
1975                 }
1976         }
1977
1978         if (agg_bufs) {
1979                 if (!xdp_active) {
1980                         skb = bnxt_rx_agg_pages_skb(bp, cpr, skb, cp_cons, agg_bufs, false);
1981                         if (!skb) {
1982                                 cpr->sw_stats.rx.rx_oom_discards += 1;
1983                                 rc = -ENOMEM;
1984                                 goto next_rx;
1985                         }
1986                 } else {
1987                         skb = bnxt_xdp_build_skb(bp, skb, agg_bufs, rxr->page_pool, &xdp, rxcmp1);
1988                         if (!skb) {
1989                                 /* we should be able to free the old skb here */
1990                                 bnxt_xdp_buff_frags_free(rxr, &xdp);
1991                                 cpr->sw_stats.rx.rx_oom_discards += 1;
1992                                 rc = -ENOMEM;
1993                                 goto next_rx;
1994                         }
1995                 }
1996         }
1997
1998         if (RX_CMP_HASH_VALID(rxcmp)) {
1999                 u32 hash_type = RX_CMP_HASH_TYPE(rxcmp);
2000                 enum pkt_hash_types type = PKT_HASH_TYPE_L4;
2001
2002                 /* RSS profiles 1 and 3 with extract code 0 for inner 4-tuple */
2003                 if (hash_type != 1 && hash_type != 3)
2004                         type = PKT_HASH_TYPE_L3;
2005                 skb_set_hash(skb, le32_to_cpu(rxcmp->rx_cmp_rss_hash), type);
2006         }
2007
2008         cfa_code = RX_CMP_CFA_CODE(rxcmp1);
2009         skb->protocol = eth_type_trans(skb, bnxt_get_pkt_dev(bp, cfa_code));
2010
2011         if ((rxcmp1->rx_cmp_flags2 &
2012              cpu_to_le32(RX_CMP_FLAGS2_META_FORMAT_VLAN)) &&
2013             (skb->dev->features & BNXT_HW_FEATURE_VLAN_ALL_RX)) {
2014                 u32 meta_data = le32_to_cpu(rxcmp1->rx_cmp_meta_data);
2015                 u16 vtag = meta_data & RX_CMP_FLAGS2_METADATA_TCI_MASK;
2016                 __be16 vlan_proto = htons(meta_data >>
2017                                           RX_CMP_FLAGS2_METADATA_TPID_SFT);
2018
2019                 if (eth_type_vlan(vlan_proto)) {
2020                         __vlan_hwaccel_put_tag(skb, vlan_proto, vtag);
2021                 } else {
2022                         dev_kfree_skb(skb);
2023                         goto next_rx;
2024                 }
2025         }
2026
2027         skb_checksum_none_assert(skb);
2028         if (RX_CMP_L4_CS_OK(rxcmp1)) {
2029                 if (dev->features & NETIF_F_RXCSUM) {
2030                         skb->ip_summed = CHECKSUM_UNNECESSARY;
2031                         skb->csum_level = RX_CMP_ENCAP(rxcmp1);
2032                 }
2033         } else {
2034                 if (rxcmp1->rx_cmp_cfa_code_errors_v2 & RX_CMP_L4_CS_ERR_BITS) {
2035                         if (dev->features & NETIF_F_RXCSUM)
2036                                 bnapi->cp_ring.sw_stats.rx.rx_l4_csum_errors++;
2037                 }
2038         }
2039
2040         if (unlikely((flags & RX_CMP_FLAGS_ITYPES_MASK) ==
2041                      RX_CMP_FLAGS_ITYPE_PTP_W_TS) || bp->ptp_all_rx_tstamp) {
2042                 if (bp->flags & BNXT_FLAG_CHIP_P5) {
2043                         u32 cmpl_ts = le32_to_cpu(rxcmp1->rx_cmp_timestamp);
2044                         u64 ns, ts;
2045
2046                         if (!bnxt_get_rx_ts_p5(bp, &ts, cmpl_ts)) {
2047                                 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2048
2049                                 spin_lock_bh(&ptp->ptp_lock);
2050                                 ns = timecounter_cyc2time(&ptp->tc, ts);
2051                                 spin_unlock_bh(&ptp->ptp_lock);
2052                                 memset(skb_hwtstamps(skb), 0,
2053                                        sizeof(*skb_hwtstamps(skb)));
2054                                 skb_hwtstamps(skb)->hwtstamp = ns_to_ktime(ns);
2055                         }
2056                 }
2057         }
2058         bnxt_deliver_skb(bp, bnapi, skb);
2059         rc = 1;
2060
2061 next_rx:
2062         cpr->rx_packets += 1;
2063         cpr->rx_bytes += len;
2064
2065 next_rx_no_len:
2066         rxr->rx_prod = NEXT_RX(prod);
2067         rxr->rx_next_cons = NEXT_RX(cons);
2068
2069 next_rx_no_prod_no_len:
2070         *raw_cons = tmp_raw_cons;
2071
2072         return rc;
2073 }
2074
2075 /* In netpoll mode, if we are using a combined completion ring, we need to
2076  * discard the rx packets and recycle the buffers.
2077  */
2078 static int bnxt_force_rx_discard(struct bnxt *bp,
2079                                  struct bnxt_cp_ring_info *cpr,
2080                                  u32 *raw_cons, u8 *event)
2081 {
2082         u32 tmp_raw_cons = *raw_cons;
2083         struct rx_cmp_ext *rxcmp1;
2084         struct rx_cmp *rxcmp;
2085         u16 cp_cons;
2086         u8 cmp_type;
2087         int rc;
2088
2089         cp_cons = RING_CMP(tmp_raw_cons);
2090         rxcmp = (struct rx_cmp *)
2091                         &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
2092
2093         tmp_raw_cons = NEXT_RAW_CMP(tmp_raw_cons);
2094         cp_cons = RING_CMP(tmp_raw_cons);
2095         rxcmp1 = (struct rx_cmp_ext *)
2096                         &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
2097
2098         if (!RX_CMP_VALID(rxcmp1, tmp_raw_cons))
2099                 return -EBUSY;
2100
2101         /* The valid test of the entry must be done first before
2102          * reading any further.
2103          */
2104         dma_rmb();
2105         cmp_type = RX_CMP_TYPE(rxcmp);
2106         if (cmp_type == CMP_TYPE_RX_L2_CMP) {
2107                 rxcmp1->rx_cmp_cfa_code_errors_v2 |=
2108                         cpu_to_le32(RX_CMPL_ERRORS_CRC_ERROR);
2109         } else if (cmp_type == CMP_TYPE_RX_L2_TPA_END_CMP) {
2110                 struct rx_tpa_end_cmp_ext *tpa_end1;
2111
2112                 tpa_end1 = (struct rx_tpa_end_cmp_ext *)rxcmp1;
2113                 tpa_end1->rx_tpa_end_cmp_errors_v2 |=
2114                         cpu_to_le32(RX_TPA_END_CMP_ERRORS);
2115         }
2116         rc = bnxt_rx_pkt(bp, cpr, raw_cons, event);
2117         if (rc && rc != -EBUSY)
2118                 cpr->sw_stats.rx.rx_netpoll_discards += 1;
2119         return rc;
2120 }
2121
2122 u32 bnxt_fw_health_readl(struct bnxt *bp, int reg_idx)
2123 {
2124         struct bnxt_fw_health *fw_health = bp->fw_health;
2125         u32 reg = fw_health->regs[reg_idx];
2126         u32 reg_type, reg_off, val = 0;
2127
2128         reg_type = BNXT_FW_HEALTH_REG_TYPE(reg);
2129         reg_off = BNXT_FW_HEALTH_REG_OFF(reg);
2130         switch (reg_type) {
2131         case BNXT_FW_HEALTH_REG_TYPE_CFG:
2132                 pci_read_config_dword(bp->pdev, reg_off, &val);
2133                 break;
2134         case BNXT_FW_HEALTH_REG_TYPE_GRC:
2135                 reg_off = fw_health->mapped_regs[reg_idx];
2136                 fallthrough;
2137         case BNXT_FW_HEALTH_REG_TYPE_BAR0:
2138                 val = readl(bp->bar0 + reg_off);
2139                 break;
2140         case BNXT_FW_HEALTH_REG_TYPE_BAR1:
2141                 val = readl(bp->bar1 + reg_off);
2142                 break;
2143         }
2144         if (reg_idx == BNXT_FW_RESET_INPROG_REG)
2145                 val &= fw_health->fw_reset_inprog_reg_mask;
2146         return val;
2147 }
2148
2149 static u16 bnxt_agg_ring_id_to_grp_idx(struct bnxt *bp, u16 ring_id)
2150 {
2151         int i;
2152
2153         for (i = 0; i < bp->rx_nr_rings; i++) {
2154                 u16 grp_idx = bp->rx_ring[i].bnapi->index;
2155                 struct bnxt_ring_grp_info *grp_info;
2156
2157                 grp_info = &bp->grp_info[grp_idx];
2158                 if (grp_info->agg_fw_ring_id == ring_id)
2159                         return grp_idx;
2160         }
2161         return INVALID_HW_RING_ID;
2162 }
2163
2164 static void bnxt_event_error_report(struct bnxt *bp, u32 data1, u32 data2)
2165 {
2166         u32 err_type = BNXT_EVENT_ERROR_REPORT_TYPE(data1);
2167
2168         switch (err_type) {
2169         case ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_INVALID_SIGNAL:
2170                 netdev_err(bp->dev, "1PPS: Received invalid signal on pin%lu from the external source. Please fix the signal and reconfigure the pin\n",
2171                            BNXT_EVENT_INVALID_SIGNAL_DATA(data2));
2172                 break;
2173         case ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_PAUSE_STORM:
2174                 netdev_warn(bp->dev, "Pause Storm detected!\n");
2175                 break;
2176         case ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_DOORBELL_DROP_THRESHOLD:
2177                 netdev_warn(bp->dev, "One or more MMIO doorbells dropped by the device!\n");
2178                 break;
2179         default:
2180                 netdev_err(bp->dev, "FW reported unknown error type %u\n",
2181                            err_type);
2182                 break;
2183         }
2184 }
2185
2186 #define BNXT_GET_EVENT_PORT(data)       \
2187         ((data) &                       \
2188          ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK)
2189
2190 #define BNXT_EVENT_RING_TYPE(data2)     \
2191         ((data2) &                      \
2192          ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_MASK)
2193
2194 #define BNXT_EVENT_RING_TYPE_RX(data2)  \
2195         (BNXT_EVENT_RING_TYPE(data2) == \
2196          ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_RX)
2197
2198 #define BNXT_EVENT_PHC_EVENT_TYPE(data1)        \
2199         (((data1) & ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_FLAGS_MASK) >>\
2200          ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_FLAGS_SFT)
2201
2202 #define BNXT_EVENT_PHC_RTC_UPDATE(data1)        \
2203         (((data1) & ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_PHC_TIME_MSB_MASK) >>\
2204          ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_PHC_TIME_MSB_SFT)
2205
2206 #define BNXT_PHC_BITS   48
2207
2208 static int bnxt_async_event_process(struct bnxt *bp,
2209                                     struct hwrm_async_event_cmpl *cmpl)
2210 {
2211         u16 event_id = le16_to_cpu(cmpl->event_id);
2212         u32 data1 = le32_to_cpu(cmpl->event_data1);
2213         u32 data2 = le32_to_cpu(cmpl->event_data2);
2214
2215         netdev_dbg(bp->dev, "hwrm event 0x%x {0x%x, 0x%x}\n",
2216                    event_id, data1, data2);
2217
2218         /* TODO CHIMP_FW: Define event id's for link change, error etc */
2219         switch (event_id) {
2220         case ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE: {
2221                 struct bnxt_link_info *link_info = &bp->link_info;
2222
2223                 if (BNXT_VF(bp))
2224                         goto async_event_process_exit;
2225
2226                 /* print unsupported speed warning in forced speed mode only */
2227                 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED) &&
2228                     (data1 & 0x20000)) {
2229                         u16 fw_speed = link_info->force_link_speed;
2230                         u32 speed = bnxt_fw_to_ethtool_speed(fw_speed);
2231
2232                         if (speed != SPEED_UNKNOWN)
2233                                 netdev_warn(bp->dev, "Link speed %d no longer supported\n",
2234                                             speed);
2235                 }
2236                 set_bit(BNXT_LINK_SPEED_CHNG_SP_EVENT, &bp->sp_event);
2237         }
2238                 fallthrough;
2239         case ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CHANGE:
2240         case ASYNC_EVENT_CMPL_EVENT_ID_PORT_PHY_CFG_CHANGE:
2241                 set_bit(BNXT_LINK_CFG_CHANGE_SP_EVENT, &bp->sp_event);
2242                 fallthrough;
2243         case ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE:
2244                 set_bit(BNXT_LINK_CHNG_SP_EVENT, &bp->sp_event);
2245                 break;
2246         case ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD:
2247                 set_bit(BNXT_HWRM_PF_UNLOAD_SP_EVENT, &bp->sp_event);
2248                 break;
2249         case ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED: {
2250                 u16 port_id = BNXT_GET_EVENT_PORT(data1);
2251
2252                 if (BNXT_VF(bp))
2253                         break;
2254
2255                 if (bp->pf.port_id != port_id)
2256                         break;
2257
2258                 set_bit(BNXT_HWRM_PORT_MODULE_SP_EVENT, &bp->sp_event);
2259                 break;
2260         }
2261         case ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE:
2262                 if (BNXT_PF(bp))
2263                         goto async_event_process_exit;
2264                 set_bit(BNXT_RESET_TASK_SILENT_SP_EVENT, &bp->sp_event);
2265                 break;
2266         case ASYNC_EVENT_CMPL_EVENT_ID_RESET_NOTIFY: {
2267                 char *type_str = "Solicited";
2268
2269                 if (!bp->fw_health)
2270                         goto async_event_process_exit;
2271
2272                 bp->fw_reset_timestamp = jiffies;
2273                 bp->fw_reset_min_dsecs = cmpl->timestamp_lo;
2274                 if (!bp->fw_reset_min_dsecs)
2275                         bp->fw_reset_min_dsecs = BNXT_DFLT_FW_RST_MIN_DSECS;
2276                 bp->fw_reset_max_dsecs = le16_to_cpu(cmpl->timestamp_hi);
2277                 if (!bp->fw_reset_max_dsecs)
2278                         bp->fw_reset_max_dsecs = BNXT_DFLT_FW_RST_MAX_DSECS;
2279                 if (EVENT_DATA1_RESET_NOTIFY_FW_ACTIVATION(data1)) {
2280                         set_bit(BNXT_STATE_FW_ACTIVATE_RESET, &bp->state);
2281                 } else if (EVENT_DATA1_RESET_NOTIFY_FATAL(data1)) {
2282                         type_str = "Fatal";
2283                         bp->fw_health->fatalities++;
2284                         set_bit(BNXT_STATE_FW_FATAL_COND, &bp->state);
2285                 } else if (data2 && BNXT_FW_STATUS_HEALTHY !=
2286                            EVENT_DATA2_RESET_NOTIFY_FW_STATUS_CODE(data2)) {
2287                         type_str = "Non-fatal";
2288                         bp->fw_health->survivals++;
2289                         set_bit(BNXT_STATE_FW_NON_FATAL_COND, &bp->state);
2290                 }
2291                 netif_warn(bp, hw, bp->dev,
2292                            "%s firmware reset event, data1: 0x%x, data2: 0x%x, min wait %u ms, max wait %u ms\n",
2293                            type_str, data1, data2,
2294                            bp->fw_reset_min_dsecs * 100,
2295                            bp->fw_reset_max_dsecs * 100);
2296                 set_bit(BNXT_FW_RESET_NOTIFY_SP_EVENT, &bp->sp_event);
2297                 break;
2298         }
2299         case ASYNC_EVENT_CMPL_EVENT_ID_ERROR_RECOVERY: {
2300                 struct bnxt_fw_health *fw_health = bp->fw_health;
2301                 char *status_desc = "healthy";
2302                 u32 status;
2303
2304                 if (!fw_health)
2305                         goto async_event_process_exit;
2306
2307                 if (!EVENT_DATA1_RECOVERY_ENABLED(data1)) {
2308                         fw_health->enabled = false;
2309                         netif_info(bp, drv, bp->dev, "Driver recovery watchdog is disabled\n");
2310                         break;
2311                 }
2312                 fw_health->primary = EVENT_DATA1_RECOVERY_MASTER_FUNC(data1);
2313                 fw_health->tmr_multiplier =
2314                         DIV_ROUND_UP(fw_health->polling_dsecs * HZ,
2315                                      bp->current_interval * 10);
2316                 fw_health->tmr_counter = fw_health->tmr_multiplier;
2317                 if (!fw_health->enabled)
2318                         fw_health->last_fw_heartbeat =
2319                                 bnxt_fw_health_readl(bp, BNXT_FW_HEARTBEAT_REG);
2320                 fw_health->last_fw_reset_cnt =
2321                         bnxt_fw_health_readl(bp, BNXT_FW_RESET_CNT_REG);
2322                 status = bnxt_fw_health_readl(bp, BNXT_FW_HEALTH_REG);
2323                 if (status != BNXT_FW_STATUS_HEALTHY)
2324                         status_desc = "unhealthy";
2325                 netif_info(bp, drv, bp->dev,
2326                            "Driver recovery watchdog, role: %s, firmware status: 0x%x (%s), resets: %u\n",
2327                            fw_health->primary ? "primary" : "backup", status,
2328                            status_desc, fw_health->last_fw_reset_cnt);
2329                 if (!fw_health->enabled) {
2330                         /* Make sure tmr_counter is set and visible to
2331                          * bnxt_health_check() before setting enabled to true.
2332                          */
2333                         smp_wmb();
2334                         fw_health->enabled = true;
2335                 }
2336                 goto async_event_process_exit;
2337         }
2338         case ASYNC_EVENT_CMPL_EVENT_ID_DEBUG_NOTIFICATION:
2339                 netif_notice(bp, hw, bp->dev,
2340                              "Received firmware debug notification, data1: 0x%x, data2: 0x%x\n",
2341                              data1, data2);
2342                 goto async_event_process_exit;
2343         case ASYNC_EVENT_CMPL_EVENT_ID_RING_MONITOR_MSG: {
2344                 struct bnxt_rx_ring_info *rxr;
2345                 u16 grp_idx;
2346
2347                 if (bp->flags & BNXT_FLAG_CHIP_P5)
2348                         goto async_event_process_exit;
2349
2350                 netdev_warn(bp->dev, "Ring monitor event, ring type %lu id 0x%x\n",
2351                             BNXT_EVENT_RING_TYPE(data2), data1);
2352                 if (!BNXT_EVENT_RING_TYPE_RX(data2))
2353                         goto async_event_process_exit;
2354
2355                 grp_idx = bnxt_agg_ring_id_to_grp_idx(bp, data1);
2356                 if (grp_idx == INVALID_HW_RING_ID) {
2357                         netdev_warn(bp->dev, "Unknown RX agg ring id 0x%x\n",
2358                                     data1);
2359                         goto async_event_process_exit;
2360                 }
2361                 rxr = bp->bnapi[grp_idx]->rx_ring;
2362                 bnxt_sched_reset(bp, rxr);
2363                 goto async_event_process_exit;
2364         }
2365         case ASYNC_EVENT_CMPL_EVENT_ID_ECHO_REQUEST: {
2366                 struct bnxt_fw_health *fw_health = bp->fw_health;
2367
2368                 netif_notice(bp, hw, bp->dev,
2369                              "Received firmware echo request, data1: 0x%x, data2: 0x%x\n",
2370                              data1, data2);
2371                 if (fw_health) {
2372                         fw_health->echo_req_data1 = data1;
2373                         fw_health->echo_req_data2 = data2;
2374                         set_bit(BNXT_FW_ECHO_REQUEST_SP_EVENT, &bp->sp_event);
2375                         break;
2376                 }
2377                 goto async_event_process_exit;
2378         }
2379         case ASYNC_EVENT_CMPL_EVENT_ID_PPS_TIMESTAMP: {
2380                 bnxt_ptp_pps_event(bp, data1, data2);
2381                 goto async_event_process_exit;
2382         }
2383         case ASYNC_EVENT_CMPL_EVENT_ID_ERROR_REPORT: {
2384                 bnxt_event_error_report(bp, data1, data2);
2385                 goto async_event_process_exit;
2386         }
2387         case ASYNC_EVENT_CMPL_EVENT_ID_PHC_UPDATE: {
2388                 switch (BNXT_EVENT_PHC_EVENT_TYPE(data1)) {
2389                 case ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_FLAGS_PHC_RTC_UPDATE:
2390                         if (bp->fw_cap & BNXT_FW_CAP_PTP_RTC) {
2391                                 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2392                                 u64 ns;
2393
2394                                 spin_lock_bh(&ptp->ptp_lock);
2395                                 bnxt_ptp_update_current_time(bp);
2396                                 ns = (((u64)BNXT_EVENT_PHC_RTC_UPDATE(data1) <<
2397                                        BNXT_PHC_BITS) | ptp->current_time);
2398                                 bnxt_ptp_rtc_timecounter_init(ptp, ns);
2399                                 spin_unlock_bh(&ptp->ptp_lock);
2400                         }
2401                         break;
2402                 }
2403                 goto async_event_process_exit;
2404         }
2405         case ASYNC_EVENT_CMPL_EVENT_ID_DEFERRED_RESPONSE: {
2406                 u16 seq_id = le32_to_cpu(cmpl->event_data2) & 0xffff;
2407
2408                 hwrm_update_token(bp, seq_id, BNXT_HWRM_DEFERRED);
2409                 goto async_event_process_exit;
2410         }
2411         default:
2412                 goto async_event_process_exit;
2413         }
2414         bnxt_queue_sp_work(bp);
2415 async_event_process_exit:
2416         return 0;
2417 }
2418
2419 static int bnxt_hwrm_handler(struct bnxt *bp, struct tx_cmp *txcmp)
2420 {
2421         u16 cmpl_type = TX_CMP_TYPE(txcmp), vf_id, seq_id;
2422         struct hwrm_cmpl *h_cmpl = (struct hwrm_cmpl *)txcmp;
2423         struct hwrm_fwd_req_cmpl *fwd_req_cmpl =
2424                                 (struct hwrm_fwd_req_cmpl *)txcmp;
2425
2426         switch (cmpl_type) {
2427         case CMPL_BASE_TYPE_HWRM_DONE:
2428                 seq_id = le16_to_cpu(h_cmpl->sequence_id);
2429                 hwrm_update_token(bp, seq_id, BNXT_HWRM_COMPLETE);
2430                 break;
2431
2432         case CMPL_BASE_TYPE_HWRM_FWD_REQ:
2433                 vf_id = le16_to_cpu(fwd_req_cmpl->source_id);
2434
2435                 if ((vf_id < bp->pf.first_vf_id) ||
2436                     (vf_id >= bp->pf.first_vf_id + bp->pf.active_vfs)) {
2437                         netdev_err(bp->dev, "Msg contains invalid VF id %x\n",
2438                                    vf_id);
2439                         return -EINVAL;
2440                 }
2441
2442                 set_bit(vf_id - bp->pf.first_vf_id, bp->pf.vf_event_bmap);
2443                 set_bit(BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT, &bp->sp_event);
2444                 bnxt_queue_sp_work(bp);
2445                 break;
2446
2447         case CMPL_BASE_TYPE_HWRM_ASYNC_EVENT:
2448                 bnxt_async_event_process(bp,
2449                                          (struct hwrm_async_event_cmpl *)txcmp);
2450                 break;
2451
2452         default:
2453                 break;
2454         }
2455
2456         return 0;
2457 }
2458
2459 static irqreturn_t bnxt_msix(int irq, void *dev_instance)
2460 {
2461         struct bnxt_napi *bnapi = dev_instance;
2462         struct bnxt *bp = bnapi->bp;
2463         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
2464         u32 cons = RING_CMP(cpr->cp_raw_cons);
2465
2466         cpr->event_ctr++;
2467         prefetch(&cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]);
2468         napi_schedule(&bnapi->napi);
2469         return IRQ_HANDLED;
2470 }
2471
2472 static inline int bnxt_has_work(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2473 {
2474         u32 raw_cons = cpr->cp_raw_cons;
2475         u16 cons = RING_CMP(raw_cons);
2476         struct tx_cmp *txcmp;
2477
2478         txcmp = &cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)];
2479
2480         return TX_CMP_VALID(txcmp, raw_cons);
2481 }
2482
2483 static irqreturn_t bnxt_inta(int irq, void *dev_instance)
2484 {
2485         struct bnxt_napi *bnapi = dev_instance;
2486         struct bnxt *bp = bnapi->bp;
2487         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
2488         u32 cons = RING_CMP(cpr->cp_raw_cons);
2489         u32 int_status;
2490
2491         prefetch(&cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]);
2492
2493         if (!bnxt_has_work(bp, cpr)) {
2494                 int_status = readl(bp->bar0 + BNXT_CAG_REG_LEGACY_INT_STATUS);
2495                 /* return if erroneous interrupt */
2496                 if (!(int_status & (0x10000 << cpr->cp_ring_struct.fw_ring_id)))
2497                         return IRQ_NONE;
2498         }
2499
2500         /* disable ring IRQ */
2501         BNXT_CP_DB_IRQ_DIS(cpr->cp_db.doorbell);
2502
2503         /* Return here if interrupt is shared and is disabled. */
2504         if (unlikely(atomic_read(&bp->intr_sem) != 0))
2505                 return IRQ_HANDLED;
2506
2507         napi_schedule(&bnapi->napi);
2508         return IRQ_HANDLED;
2509 }
2510
2511 static int __bnxt_poll_work(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
2512                             int budget)
2513 {
2514         struct bnxt_napi *bnapi = cpr->bnapi;
2515         u32 raw_cons = cpr->cp_raw_cons;
2516         u32 cons;
2517         int tx_pkts = 0;
2518         int rx_pkts = 0;
2519         u8 event = 0;
2520         struct tx_cmp *txcmp;
2521
2522         cpr->has_more_work = 0;
2523         cpr->had_work_done = 1;
2524         while (1) {
2525                 int rc;
2526
2527                 cons = RING_CMP(raw_cons);
2528                 txcmp = &cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)];
2529
2530                 if (!TX_CMP_VALID(txcmp, raw_cons))
2531                         break;
2532
2533                 /* The valid test of the entry must be done first before
2534                  * reading any further.
2535                  */
2536                 dma_rmb();
2537                 if (TX_CMP_TYPE(txcmp) == CMP_TYPE_TX_L2_CMP) {
2538                         tx_pkts++;
2539                         /* return full budget so NAPI will complete. */
2540                         if (unlikely(tx_pkts >= bp->tx_wake_thresh)) {
2541                                 rx_pkts = budget;
2542                                 raw_cons = NEXT_RAW_CMP(raw_cons);
2543                                 if (budget)
2544                                         cpr->has_more_work = 1;
2545                                 break;
2546                         }
2547                 } else if ((TX_CMP_TYPE(txcmp) & 0x30) == 0x10) {
2548                         if (likely(budget))
2549                                 rc = bnxt_rx_pkt(bp, cpr, &raw_cons, &event);
2550                         else
2551                                 rc = bnxt_force_rx_discard(bp, cpr, &raw_cons,
2552                                                            &event);
2553                         if (likely(rc >= 0))
2554                                 rx_pkts += rc;
2555                         /* Increment rx_pkts when rc is -ENOMEM to count towards
2556                          * the NAPI budget.  Otherwise, we may potentially loop
2557                          * here forever if we consistently cannot allocate
2558                          * buffers.
2559                          */
2560                         else if (rc == -ENOMEM && budget)
2561                                 rx_pkts++;
2562                         else if (rc == -EBUSY)  /* partial completion */
2563                                 break;
2564                 } else if (unlikely((TX_CMP_TYPE(txcmp) ==
2565                                      CMPL_BASE_TYPE_HWRM_DONE) ||
2566                                     (TX_CMP_TYPE(txcmp) ==
2567                                      CMPL_BASE_TYPE_HWRM_FWD_REQ) ||
2568                                     (TX_CMP_TYPE(txcmp) ==
2569                                      CMPL_BASE_TYPE_HWRM_ASYNC_EVENT))) {
2570                         bnxt_hwrm_handler(bp, txcmp);
2571                 }
2572                 raw_cons = NEXT_RAW_CMP(raw_cons);
2573
2574                 if (rx_pkts && rx_pkts == budget) {
2575                         cpr->has_more_work = 1;
2576                         break;
2577                 }
2578         }
2579
2580         if (event & BNXT_REDIRECT_EVENT)
2581                 xdp_do_flush();
2582
2583         if (event & BNXT_TX_EVENT) {
2584                 struct bnxt_tx_ring_info *txr = bnapi->tx_ring;
2585                 u16 prod = txr->tx_prod;
2586
2587                 /* Sync BD data before updating doorbell */
2588                 wmb();
2589
2590                 bnxt_db_write_relaxed(bp, &txr->tx_db, prod);
2591         }
2592
2593         cpr->cp_raw_cons = raw_cons;
2594         bnapi->tx_pkts += tx_pkts;
2595         bnapi->events |= event;
2596         return rx_pkts;
2597 }
2598
2599 static void __bnxt_poll_work_done(struct bnxt *bp, struct bnxt_napi *bnapi)
2600 {
2601         if (bnapi->tx_pkts) {
2602                 bnapi->tx_int(bp, bnapi, bnapi->tx_pkts);
2603                 bnapi->tx_pkts = 0;
2604         }
2605
2606         if ((bnapi->events & BNXT_RX_EVENT) && !(bnapi->in_reset)) {
2607                 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
2608
2609                 bnxt_db_write(bp, &rxr->rx_db, rxr->rx_prod);
2610         }
2611         if (bnapi->events & BNXT_AGG_EVENT) {
2612                 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
2613
2614                 bnxt_db_write(bp, &rxr->rx_agg_db, rxr->rx_agg_prod);
2615         }
2616         bnapi->events = 0;
2617 }
2618
2619 static int bnxt_poll_work(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
2620                           int budget)
2621 {
2622         struct bnxt_napi *bnapi = cpr->bnapi;
2623         int rx_pkts;
2624
2625         rx_pkts = __bnxt_poll_work(bp, cpr, budget);
2626
2627         /* ACK completion ring before freeing tx ring and producing new
2628          * buffers in rx/agg rings to prevent overflowing the completion
2629          * ring.
2630          */
2631         bnxt_db_cq(bp, &cpr->cp_db, cpr->cp_raw_cons);
2632
2633         __bnxt_poll_work_done(bp, bnapi);
2634         return rx_pkts;
2635 }
2636
2637 static int bnxt_poll_nitroa0(struct napi_struct *napi, int budget)
2638 {
2639         struct bnxt_napi *bnapi = container_of(napi, struct bnxt_napi, napi);
2640         struct bnxt *bp = bnapi->bp;
2641         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
2642         struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
2643         struct tx_cmp *txcmp;
2644         struct rx_cmp_ext *rxcmp1;
2645         u32 cp_cons, tmp_raw_cons;
2646         u32 raw_cons = cpr->cp_raw_cons;
2647         u32 rx_pkts = 0;
2648         u8 event = 0;
2649
2650         while (1) {
2651                 int rc;
2652
2653                 cp_cons = RING_CMP(raw_cons);
2654                 txcmp = &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
2655
2656                 if (!TX_CMP_VALID(txcmp, raw_cons))
2657                         break;
2658
2659                 /* The valid test of the entry must be done first before
2660                  * reading any further.
2661                  */
2662                 dma_rmb();
2663                 if ((TX_CMP_TYPE(txcmp) & 0x30) == 0x10) {
2664                         tmp_raw_cons = NEXT_RAW_CMP(raw_cons);
2665                         cp_cons = RING_CMP(tmp_raw_cons);
2666                         rxcmp1 = (struct rx_cmp_ext *)
2667                           &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
2668
2669                         if (!RX_CMP_VALID(rxcmp1, tmp_raw_cons))
2670                                 break;
2671
2672                         /* force an error to recycle the buffer */
2673                         rxcmp1->rx_cmp_cfa_code_errors_v2 |=
2674                                 cpu_to_le32(RX_CMPL_ERRORS_CRC_ERROR);
2675
2676                         rc = bnxt_rx_pkt(bp, cpr, &raw_cons, &event);
2677                         if (likely(rc == -EIO) && budget)
2678                                 rx_pkts++;
2679                         else if (rc == -EBUSY)  /* partial completion */
2680                                 break;
2681                 } else if (unlikely(TX_CMP_TYPE(txcmp) ==
2682                                     CMPL_BASE_TYPE_HWRM_DONE)) {
2683                         bnxt_hwrm_handler(bp, txcmp);
2684                 } else {
2685                         netdev_err(bp->dev,
2686                                    "Invalid completion received on special ring\n");
2687                 }
2688                 raw_cons = NEXT_RAW_CMP(raw_cons);
2689
2690                 if (rx_pkts == budget)
2691                         break;
2692         }
2693
2694         cpr->cp_raw_cons = raw_cons;
2695         BNXT_DB_CQ(&cpr->cp_db, cpr->cp_raw_cons);
2696         bnxt_db_write(bp, &rxr->rx_db, rxr->rx_prod);
2697
2698         if (event & BNXT_AGG_EVENT)
2699                 bnxt_db_write(bp, &rxr->rx_agg_db, rxr->rx_agg_prod);
2700
2701         if (!bnxt_has_work(bp, cpr) && rx_pkts < budget) {
2702                 napi_complete_done(napi, rx_pkts);
2703                 BNXT_DB_CQ_ARM(&cpr->cp_db, cpr->cp_raw_cons);
2704         }
2705         return rx_pkts;
2706 }
2707
2708 static int bnxt_poll(struct napi_struct *napi, int budget)
2709 {
2710         struct bnxt_napi *bnapi = container_of(napi, struct bnxt_napi, napi);
2711         struct bnxt *bp = bnapi->bp;
2712         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
2713         int work_done = 0;
2714
2715         if (unlikely(test_bit(BNXT_STATE_FW_FATAL_COND, &bp->state))) {
2716                 napi_complete(napi);
2717                 return 0;
2718         }
2719         while (1) {
2720                 work_done += bnxt_poll_work(bp, cpr, budget - work_done);
2721
2722                 if (work_done >= budget) {
2723                         if (!budget)
2724                                 BNXT_DB_CQ_ARM(&cpr->cp_db, cpr->cp_raw_cons);
2725                         break;
2726                 }
2727
2728                 if (!bnxt_has_work(bp, cpr)) {
2729                         if (napi_complete_done(napi, work_done))
2730                                 BNXT_DB_CQ_ARM(&cpr->cp_db, cpr->cp_raw_cons);
2731                         break;
2732                 }
2733         }
2734         if (bp->flags & BNXT_FLAG_DIM) {
2735                 struct dim_sample dim_sample = {};
2736
2737                 dim_update_sample(cpr->event_ctr,
2738                                   cpr->rx_packets,
2739                                   cpr->rx_bytes,
2740                                   &dim_sample);
2741                 net_dim(&cpr->dim, dim_sample);
2742         }
2743         return work_done;
2744 }
2745
2746 static int __bnxt_poll_cqs(struct bnxt *bp, struct bnxt_napi *bnapi, int budget)
2747 {
2748         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
2749         int i, work_done = 0;
2750
2751         for (i = 0; i < 2; i++) {
2752                 struct bnxt_cp_ring_info *cpr2 = cpr->cp_ring_arr[i];
2753
2754                 if (cpr2) {
2755                         work_done += __bnxt_poll_work(bp, cpr2,
2756                                                       budget - work_done);
2757                         cpr->has_more_work |= cpr2->has_more_work;
2758                 }
2759         }
2760         return work_done;
2761 }
2762
2763 static void __bnxt_poll_cqs_done(struct bnxt *bp, struct bnxt_napi *bnapi,
2764                                  u64 dbr_type)
2765 {
2766         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
2767         int i;
2768
2769         for (i = 0; i < 2; i++) {
2770                 struct bnxt_cp_ring_info *cpr2 = cpr->cp_ring_arr[i];
2771                 struct bnxt_db_info *db;
2772
2773                 if (cpr2 && cpr2->had_work_done) {
2774                         db = &cpr2->cp_db;
2775                         bnxt_writeq(bp, db->db_key64 | dbr_type |
2776                                     RING_CMP(cpr2->cp_raw_cons), db->doorbell);
2777                         cpr2->had_work_done = 0;
2778                 }
2779         }
2780         __bnxt_poll_work_done(bp, bnapi);
2781 }
2782
2783 static int bnxt_poll_p5(struct napi_struct *napi, int budget)
2784 {
2785         struct bnxt_napi *bnapi = container_of(napi, struct bnxt_napi, napi);
2786         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
2787         struct bnxt_cp_ring_info *cpr_rx;
2788         u32 raw_cons = cpr->cp_raw_cons;
2789         struct bnxt *bp = bnapi->bp;
2790         struct nqe_cn *nqcmp;
2791         int work_done = 0;
2792         u32 cons;
2793
2794         if (unlikely(test_bit(BNXT_STATE_FW_FATAL_COND, &bp->state))) {
2795                 napi_complete(napi);
2796                 return 0;
2797         }
2798         if (cpr->has_more_work) {
2799                 cpr->has_more_work = 0;
2800                 work_done = __bnxt_poll_cqs(bp, bnapi, budget);
2801         }
2802         while (1) {
2803                 cons = RING_CMP(raw_cons);
2804                 nqcmp = &cpr->nq_desc_ring[CP_RING(cons)][CP_IDX(cons)];
2805
2806                 if (!NQ_CMP_VALID(nqcmp, raw_cons)) {
2807                         if (cpr->has_more_work)
2808                                 break;
2809
2810                         __bnxt_poll_cqs_done(bp, bnapi, DBR_TYPE_CQ_ARMALL);
2811                         cpr->cp_raw_cons = raw_cons;
2812                         if (napi_complete_done(napi, work_done))
2813                                 BNXT_DB_NQ_ARM_P5(&cpr->cp_db,
2814                                                   cpr->cp_raw_cons);
2815                         goto poll_done;
2816                 }
2817
2818                 /* The valid test of the entry must be done first before
2819                  * reading any further.
2820                  */
2821                 dma_rmb();
2822
2823                 if (nqcmp->type == cpu_to_le16(NQ_CN_TYPE_CQ_NOTIFICATION)) {
2824                         u32 idx = le32_to_cpu(nqcmp->cq_handle_low);
2825                         struct bnxt_cp_ring_info *cpr2;
2826
2827                         /* No more budget for RX work */
2828                         if (budget && work_done >= budget && idx == BNXT_RX_HDL)
2829                                 break;
2830
2831                         cpr2 = cpr->cp_ring_arr[idx];
2832                         work_done += __bnxt_poll_work(bp, cpr2,
2833                                                       budget - work_done);
2834                         cpr->has_more_work |= cpr2->has_more_work;
2835                 } else {
2836                         bnxt_hwrm_handler(bp, (struct tx_cmp *)nqcmp);
2837                 }
2838                 raw_cons = NEXT_RAW_CMP(raw_cons);
2839         }
2840         __bnxt_poll_cqs_done(bp, bnapi, DBR_TYPE_CQ);
2841         if (raw_cons != cpr->cp_raw_cons) {
2842                 cpr->cp_raw_cons = raw_cons;
2843                 BNXT_DB_NQ_P5(&cpr->cp_db, raw_cons);
2844         }
2845 poll_done:
2846         cpr_rx = cpr->cp_ring_arr[BNXT_RX_HDL];
2847         if (cpr_rx && (bp->flags & BNXT_FLAG_DIM)) {
2848                 struct dim_sample dim_sample = {};
2849
2850                 dim_update_sample(cpr->event_ctr,
2851                                   cpr_rx->rx_packets,
2852                                   cpr_rx->rx_bytes,
2853                                   &dim_sample);
2854                 net_dim(&cpr->dim, dim_sample);
2855         }
2856         return work_done;
2857 }
2858
2859 static void bnxt_free_tx_skbs(struct bnxt *bp)
2860 {
2861         int i, max_idx;
2862         struct pci_dev *pdev = bp->pdev;
2863
2864         if (!bp->tx_ring)
2865                 return;
2866
2867         max_idx = bp->tx_nr_pages * TX_DESC_CNT;
2868         for (i = 0; i < bp->tx_nr_rings; i++) {
2869                 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
2870                 int j;
2871
2872                 if (!txr->tx_buf_ring)
2873                         continue;
2874
2875                 for (j = 0; j < max_idx;) {
2876                         struct bnxt_sw_tx_bd *tx_buf = &txr->tx_buf_ring[j];
2877                         struct sk_buff *skb;
2878                         int k, last;
2879
2880                         if (i < bp->tx_nr_rings_xdp &&
2881                             tx_buf->action == XDP_REDIRECT) {
2882                                 dma_unmap_single(&pdev->dev,
2883                                         dma_unmap_addr(tx_buf, mapping),
2884                                         dma_unmap_len(tx_buf, len),
2885                                         DMA_TO_DEVICE);
2886                                 xdp_return_frame(tx_buf->xdpf);
2887                                 tx_buf->action = 0;
2888                                 tx_buf->xdpf = NULL;
2889                                 j++;
2890                                 continue;
2891                         }
2892
2893                         skb = tx_buf->skb;
2894                         if (!skb) {
2895                                 j++;
2896                                 continue;
2897                         }
2898
2899                         tx_buf->skb = NULL;
2900
2901                         if (tx_buf->is_push) {
2902                                 dev_kfree_skb(skb);
2903                                 j += 2;
2904                                 continue;
2905                         }
2906
2907                         dma_unmap_single(&pdev->dev,
2908                                          dma_unmap_addr(tx_buf, mapping),
2909                                          skb_headlen(skb),
2910                                          DMA_TO_DEVICE);
2911
2912                         last = tx_buf->nr_frags;
2913                         j += 2;
2914                         for (k = 0; k < last; k++, j++) {
2915                                 int ring_idx = j & bp->tx_ring_mask;
2916                                 skb_frag_t *frag = &skb_shinfo(skb)->frags[k];
2917
2918                                 tx_buf = &txr->tx_buf_ring[ring_idx];
2919                                 dma_unmap_page(
2920                                         &pdev->dev,
2921                                         dma_unmap_addr(tx_buf, mapping),
2922                                         skb_frag_size(frag), DMA_TO_DEVICE);
2923                         }
2924                         dev_kfree_skb(skb);
2925                 }
2926                 netdev_tx_reset_queue(netdev_get_tx_queue(bp->dev, i));
2927         }
2928 }
2929
2930 static void bnxt_free_one_rx_ring_skbs(struct bnxt *bp, int ring_nr)
2931 {
2932         struct bnxt_rx_ring_info *rxr = &bp->rx_ring[ring_nr];
2933         struct pci_dev *pdev = bp->pdev;
2934         struct bnxt_tpa_idx_map *map;
2935         int i, max_idx, max_agg_idx;
2936
2937         max_idx = bp->rx_nr_pages * RX_DESC_CNT;
2938         max_agg_idx = bp->rx_agg_nr_pages * RX_DESC_CNT;
2939         if (!rxr->rx_tpa)
2940                 goto skip_rx_tpa_free;
2941
2942         for (i = 0; i < bp->max_tpa; i++) {
2943                 struct bnxt_tpa_info *tpa_info = &rxr->rx_tpa[i];
2944                 u8 *data = tpa_info->data;
2945
2946                 if (!data)
2947                         continue;
2948
2949                 dma_unmap_single_attrs(&pdev->dev, tpa_info->mapping,
2950                                        bp->rx_buf_use_size, bp->rx_dir,
2951                                        DMA_ATTR_WEAK_ORDERING);
2952
2953                 tpa_info->data = NULL;
2954
2955                 skb_free_frag(data);
2956         }
2957
2958 skip_rx_tpa_free:
2959         if (!rxr->rx_buf_ring)
2960                 goto skip_rx_buf_free;
2961
2962         for (i = 0; i < max_idx; i++) {
2963                 struct bnxt_sw_rx_bd *rx_buf = &rxr->rx_buf_ring[i];
2964                 dma_addr_t mapping = rx_buf->mapping;
2965                 void *data = rx_buf->data;
2966
2967                 if (!data)
2968                         continue;
2969
2970                 rx_buf->data = NULL;
2971                 if (BNXT_RX_PAGE_MODE(bp)) {
2972                         mapping -= bp->rx_dma_offset;
2973                         dma_unmap_page_attrs(&pdev->dev, mapping, PAGE_SIZE,
2974                                              bp->rx_dir,
2975                                              DMA_ATTR_WEAK_ORDERING);
2976                         page_pool_recycle_direct(rxr->page_pool, data);
2977                 } else {
2978                         dma_unmap_single_attrs(&pdev->dev, mapping,
2979                                                bp->rx_buf_use_size, bp->rx_dir,
2980                                                DMA_ATTR_WEAK_ORDERING);
2981                         skb_free_frag(data);
2982                 }
2983         }
2984
2985 skip_rx_buf_free:
2986         if (!rxr->rx_agg_ring)
2987                 goto skip_rx_agg_free;
2988
2989         for (i = 0; i < max_agg_idx; i++) {
2990                 struct bnxt_sw_rx_agg_bd *rx_agg_buf = &rxr->rx_agg_ring[i];
2991                 struct page *page = rx_agg_buf->page;
2992
2993                 if (!page)
2994                         continue;
2995
2996                 if (BNXT_RX_PAGE_MODE(bp)) {
2997                         dma_unmap_page_attrs(&pdev->dev, rx_agg_buf->mapping,
2998                                              BNXT_RX_PAGE_SIZE, bp->rx_dir,
2999                                              DMA_ATTR_WEAK_ORDERING);
3000                         rx_agg_buf->page = NULL;
3001                         __clear_bit(i, rxr->rx_agg_bmap);
3002
3003                         page_pool_recycle_direct(rxr->page_pool, page);
3004                 } else {
3005                         dma_unmap_page_attrs(&pdev->dev, rx_agg_buf->mapping,
3006                                              BNXT_RX_PAGE_SIZE, DMA_FROM_DEVICE,
3007                                              DMA_ATTR_WEAK_ORDERING);
3008                         rx_agg_buf->page = NULL;
3009                         __clear_bit(i, rxr->rx_agg_bmap);
3010
3011                         __free_page(page);
3012                 }
3013         }
3014
3015 skip_rx_agg_free:
3016         if (rxr->rx_page) {
3017                 __free_page(rxr->rx_page);
3018                 rxr->rx_page = NULL;
3019         }
3020         map = rxr->rx_tpa_idx_map;
3021         if (map)
3022                 memset(map->agg_idx_bmap, 0, sizeof(map->agg_idx_bmap));
3023 }
3024
3025 static void bnxt_free_rx_skbs(struct bnxt *bp)
3026 {
3027         int i;
3028
3029         if (!bp->rx_ring)
3030                 return;
3031
3032         for (i = 0; i < bp->rx_nr_rings; i++)
3033                 bnxt_free_one_rx_ring_skbs(bp, i);
3034 }
3035
3036 static void bnxt_free_skbs(struct bnxt *bp)
3037 {
3038         bnxt_free_tx_skbs(bp);
3039         bnxt_free_rx_skbs(bp);
3040 }
3041
3042 static void bnxt_init_ctx_mem(struct bnxt_mem_init *mem_init, void *p, int len)
3043 {
3044         u8 init_val = mem_init->init_val;
3045         u16 offset = mem_init->offset;
3046         u8 *p2 = p;
3047         int i;
3048
3049         if (!init_val)
3050                 return;
3051         if (offset == BNXT_MEM_INVALID_OFFSET) {
3052                 memset(p, init_val, len);
3053                 return;
3054         }
3055         for (i = 0; i < len; i += mem_init->size)
3056                 *(p2 + i + offset) = init_val;
3057 }
3058
3059 static void bnxt_free_ring(struct bnxt *bp, struct bnxt_ring_mem_info *rmem)
3060 {
3061         struct pci_dev *pdev = bp->pdev;
3062         int i;
3063
3064         if (!rmem->pg_arr)
3065                 goto skip_pages;
3066
3067         for (i = 0; i < rmem->nr_pages; i++) {
3068                 if (!rmem->pg_arr[i])
3069                         continue;
3070
3071                 dma_free_coherent(&pdev->dev, rmem->page_size,
3072                                   rmem->pg_arr[i], rmem->dma_arr[i]);
3073
3074                 rmem->pg_arr[i] = NULL;
3075         }
3076 skip_pages:
3077         if (rmem->pg_tbl) {
3078                 size_t pg_tbl_size = rmem->nr_pages * 8;
3079
3080                 if (rmem->flags & BNXT_RMEM_USE_FULL_PAGE_FLAG)
3081                         pg_tbl_size = rmem->page_size;
3082                 dma_free_coherent(&pdev->dev, pg_tbl_size,
3083                                   rmem->pg_tbl, rmem->pg_tbl_map);
3084                 rmem->pg_tbl = NULL;
3085         }
3086         if (rmem->vmem_size && *rmem->vmem) {
3087                 vfree(*rmem->vmem);
3088                 *rmem->vmem = NULL;
3089         }
3090 }
3091
3092 static int bnxt_alloc_ring(struct bnxt *bp, struct bnxt_ring_mem_info *rmem)
3093 {
3094         struct pci_dev *pdev = bp->pdev;
3095         u64 valid_bit = 0;
3096         int i;
3097
3098         if (rmem->flags & (BNXT_RMEM_VALID_PTE_FLAG | BNXT_RMEM_RING_PTE_FLAG))
3099                 valid_bit = PTU_PTE_VALID;
3100         if ((rmem->nr_pages > 1 || rmem->depth > 0) && !rmem->pg_tbl) {
3101                 size_t pg_tbl_size = rmem->nr_pages * 8;
3102
3103                 if (rmem->flags & BNXT_RMEM_USE_FULL_PAGE_FLAG)
3104                         pg_tbl_size = rmem->page_size;
3105                 rmem->pg_tbl = dma_alloc_coherent(&pdev->dev, pg_tbl_size,
3106                                                   &rmem->pg_tbl_map,
3107                                                   GFP_KERNEL);
3108                 if (!rmem->pg_tbl)
3109                         return -ENOMEM;
3110         }
3111
3112         for (i = 0; i < rmem->nr_pages; i++) {
3113                 u64 extra_bits = valid_bit;
3114
3115                 rmem->pg_arr[i] = dma_alloc_coherent(&pdev->dev,
3116                                                      rmem->page_size,
3117                                                      &rmem->dma_arr[i],
3118                                                      GFP_KERNEL);
3119                 if (!rmem->pg_arr[i])
3120                         return -ENOMEM;
3121
3122                 if (rmem->mem_init)
3123                         bnxt_init_ctx_mem(rmem->mem_init, rmem->pg_arr[i],
3124                                           rmem->page_size);
3125                 if (rmem->nr_pages > 1 || rmem->depth > 0) {
3126                         if (i == rmem->nr_pages - 2 &&
3127                             (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
3128                                 extra_bits |= PTU_PTE_NEXT_TO_LAST;
3129                         else if (i == rmem->nr_pages - 1 &&
3130                                  (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
3131                                 extra_bits |= PTU_PTE_LAST;
3132                         rmem->pg_tbl[i] =
3133                                 cpu_to_le64(rmem->dma_arr[i] | extra_bits);
3134                 }
3135         }
3136
3137         if (rmem->vmem_size) {
3138                 *rmem->vmem = vzalloc(rmem->vmem_size);
3139                 if (!(*rmem->vmem))
3140                         return -ENOMEM;
3141         }
3142         return 0;
3143 }
3144
3145 static void bnxt_free_tpa_info(struct bnxt *bp)
3146 {
3147         int i, j;
3148
3149         for (i = 0; i < bp->rx_nr_rings; i++) {
3150                 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
3151
3152                 kfree(rxr->rx_tpa_idx_map);
3153                 rxr->rx_tpa_idx_map = NULL;
3154                 if (rxr->rx_tpa) {
3155                         for (j = 0; j < bp->max_tpa; j++) {
3156                                 kfree(rxr->rx_tpa[j].agg_arr);
3157                                 rxr->rx_tpa[j].agg_arr = NULL;
3158                         }
3159                 }
3160                 kfree(rxr->rx_tpa);
3161                 rxr->rx_tpa = NULL;
3162         }
3163 }
3164
3165 static int bnxt_alloc_tpa_info(struct bnxt *bp)
3166 {
3167         int i, j;
3168
3169         bp->max_tpa = MAX_TPA;
3170         if (bp->flags & BNXT_FLAG_CHIP_P5) {
3171                 if (!bp->max_tpa_v2)
3172                         return 0;
3173                 bp->max_tpa = max_t(u16, bp->max_tpa_v2, MAX_TPA_P5);
3174         }
3175
3176         for (i = 0; i < bp->rx_nr_rings; i++) {
3177                 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
3178                 struct rx_agg_cmp *agg;
3179
3180                 rxr->rx_tpa = kcalloc(bp->max_tpa, sizeof(struct bnxt_tpa_info),
3181                                       GFP_KERNEL);
3182                 if (!rxr->rx_tpa)
3183                         return -ENOMEM;
3184
3185                 if (!(bp->flags & BNXT_FLAG_CHIP_P5))
3186                         continue;
3187                 for (j = 0; j < bp->max_tpa; j++) {
3188                         agg = kcalloc(MAX_SKB_FRAGS, sizeof(*agg), GFP_KERNEL);
3189                         if (!agg)
3190                                 return -ENOMEM;
3191                         rxr->rx_tpa[j].agg_arr = agg;
3192                 }
3193                 rxr->rx_tpa_idx_map = kzalloc(sizeof(*rxr->rx_tpa_idx_map),
3194                                               GFP_KERNEL);
3195                 if (!rxr->rx_tpa_idx_map)
3196                         return -ENOMEM;
3197         }
3198         return 0;
3199 }
3200
3201 static void bnxt_free_rx_rings(struct bnxt *bp)
3202 {
3203         int i;
3204
3205         if (!bp->rx_ring)
3206                 return;
3207
3208         bnxt_free_tpa_info(bp);
3209         for (i = 0; i < bp->rx_nr_rings; i++) {
3210                 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
3211                 struct bnxt_ring_struct *ring;
3212
3213                 if (rxr->xdp_prog)
3214                         bpf_prog_put(rxr->xdp_prog);
3215
3216                 if (xdp_rxq_info_is_reg(&rxr->xdp_rxq))
3217                         xdp_rxq_info_unreg(&rxr->xdp_rxq);
3218
3219                 page_pool_destroy(rxr->page_pool);
3220                 rxr->page_pool = NULL;
3221
3222                 kfree(rxr->rx_agg_bmap);
3223                 rxr->rx_agg_bmap = NULL;
3224
3225                 ring = &rxr->rx_ring_struct;
3226                 bnxt_free_ring(bp, &ring->ring_mem);
3227
3228                 ring = &rxr->rx_agg_ring_struct;
3229                 bnxt_free_ring(bp, &ring->ring_mem);
3230         }
3231 }
3232
3233 static int bnxt_alloc_rx_page_pool(struct bnxt *bp,
3234                                    struct bnxt_rx_ring_info *rxr)
3235 {
3236         struct page_pool_params pp = { 0 };
3237
3238         pp.pool_size = bp->rx_ring_size;
3239         pp.nid = dev_to_node(&bp->pdev->dev);
3240         pp.dev = &bp->pdev->dev;
3241         pp.dma_dir = DMA_BIDIRECTIONAL;
3242
3243         rxr->page_pool = page_pool_create(&pp);
3244         if (IS_ERR(rxr->page_pool)) {
3245                 int err = PTR_ERR(rxr->page_pool);
3246
3247                 rxr->page_pool = NULL;
3248                 return err;
3249         }
3250         return 0;
3251 }
3252
3253 static int bnxt_alloc_rx_rings(struct bnxt *bp)
3254 {
3255         int i, rc = 0, agg_rings = 0;
3256
3257         if (!bp->rx_ring)
3258                 return -ENOMEM;
3259
3260         if (bp->flags & BNXT_FLAG_AGG_RINGS)
3261                 agg_rings = 1;
3262
3263         for (i = 0; i < bp->rx_nr_rings; i++) {
3264                 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
3265                 struct bnxt_ring_struct *ring;
3266
3267                 ring = &rxr->rx_ring_struct;
3268
3269                 rc = bnxt_alloc_rx_page_pool(bp, rxr);
3270                 if (rc)
3271                         return rc;
3272
3273                 rc = xdp_rxq_info_reg(&rxr->xdp_rxq, bp->dev, i, 0);
3274                 if (rc < 0)
3275                         return rc;
3276
3277                 rc = xdp_rxq_info_reg_mem_model(&rxr->xdp_rxq,
3278                                                 MEM_TYPE_PAGE_POOL,
3279                                                 rxr->page_pool);
3280                 if (rc) {
3281                         xdp_rxq_info_unreg(&rxr->xdp_rxq);
3282                         return rc;
3283                 }
3284
3285                 rc = bnxt_alloc_ring(bp, &ring->ring_mem);
3286                 if (rc)
3287                         return rc;
3288
3289                 ring->grp_idx = i;
3290                 if (agg_rings) {
3291                         u16 mem_size;
3292
3293                         ring = &rxr->rx_agg_ring_struct;
3294                         rc = bnxt_alloc_ring(bp, &ring->ring_mem);
3295                         if (rc)
3296                                 return rc;
3297
3298                         ring->grp_idx = i;
3299                         rxr->rx_agg_bmap_size = bp->rx_agg_ring_mask + 1;
3300                         mem_size = rxr->rx_agg_bmap_size / 8;
3301                         rxr->rx_agg_bmap = kzalloc(mem_size, GFP_KERNEL);
3302                         if (!rxr->rx_agg_bmap)
3303                                 return -ENOMEM;
3304                 }
3305         }
3306         if (bp->flags & BNXT_FLAG_TPA)
3307                 rc = bnxt_alloc_tpa_info(bp);
3308         return rc;
3309 }
3310
3311 static void bnxt_free_tx_rings(struct bnxt *bp)
3312 {
3313         int i;
3314         struct pci_dev *pdev = bp->pdev;
3315
3316         if (!bp->tx_ring)
3317                 return;
3318
3319         for (i = 0; i < bp->tx_nr_rings; i++) {
3320                 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
3321                 struct bnxt_ring_struct *ring;
3322
3323                 if (txr->tx_push) {
3324                         dma_free_coherent(&pdev->dev, bp->tx_push_size,
3325                                           txr->tx_push, txr->tx_push_mapping);
3326                         txr->tx_push = NULL;
3327                 }
3328
3329                 ring = &txr->tx_ring_struct;
3330
3331                 bnxt_free_ring(bp, &ring->ring_mem);
3332         }
3333 }
3334
3335 static int bnxt_alloc_tx_rings(struct bnxt *bp)
3336 {
3337         int i, j, rc;
3338         struct pci_dev *pdev = bp->pdev;
3339
3340         bp->tx_push_size = 0;
3341         if (bp->tx_push_thresh) {
3342                 int push_size;
3343
3344                 push_size  = L1_CACHE_ALIGN(sizeof(struct tx_push_bd) +
3345                                         bp->tx_push_thresh);
3346
3347                 if (push_size > 256) {
3348                         push_size = 0;
3349                         bp->tx_push_thresh = 0;
3350                 }
3351
3352                 bp->tx_push_size = push_size;
3353         }
3354
3355         for (i = 0, j = 0; i < bp->tx_nr_rings; i++) {
3356                 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
3357                 struct bnxt_ring_struct *ring;
3358                 u8 qidx;
3359
3360                 ring = &txr->tx_ring_struct;
3361
3362                 rc = bnxt_alloc_ring(bp, &ring->ring_mem);
3363                 if (rc)
3364                         return rc;
3365
3366                 ring->grp_idx = txr->bnapi->index;
3367                 if (bp->tx_push_size) {
3368                         dma_addr_t mapping;
3369
3370                         /* One pre-allocated DMA buffer to backup
3371                          * TX push operation
3372                          */
3373                         txr->tx_push = dma_alloc_coherent(&pdev->dev,
3374                                                 bp->tx_push_size,
3375                                                 &txr->tx_push_mapping,
3376                                                 GFP_KERNEL);
3377
3378                         if (!txr->tx_push)
3379                                 return -ENOMEM;
3380
3381                         mapping = txr->tx_push_mapping +
3382                                 sizeof(struct tx_push_bd);
3383                         txr->data_mapping = cpu_to_le64(mapping);
3384                 }
3385                 qidx = bp->tc_to_qidx[j];
3386                 ring->queue_id = bp->q_info[qidx].queue_id;
3387                 spin_lock_init(&txr->xdp_tx_lock);
3388                 if (i < bp->tx_nr_rings_xdp)
3389                         continue;
3390                 if (i % bp->tx_nr_rings_per_tc == (bp->tx_nr_rings_per_tc - 1))
3391                         j++;
3392         }
3393         return 0;
3394 }
3395
3396 static void bnxt_free_cp_arrays(struct bnxt_cp_ring_info *cpr)
3397 {
3398         struct bnxt_ring_struct *ring = &cpr->cp_ring_struct;
3399
3400         kfree(cpr->cp_desc_ring);
3401         cpr->cp_desc_ring = NULL;
3402         ring->ring_mem.pg_arr = NULL;
3403         kfree(cpr->cp_desc_mapping);
3404         cpr->cp_desc_mapping = NULL;
3405         ring->ring_mem.dma_arr = NULL;
3406 }
3407
3408 static int bnxt_alloc_cp_arrays(struct bnxt_cp_ring_info *cpr, int n)
3409 {
3410         cpr->cp_desc_ring = kcalloc(n, sizeof(*cpr->cp_desc_ring), GFP_KERNEL);
3411         if (!cpr->cp_desc_ring)
3412                 return -ENOMEM;
3413         cpr->cp_desc_mapping = kcalloc(n, sizeof(*cpr->cp_desc_mapping),
3414                                        GFP_KERNEL);
3415         if (!cpr->cp_desc_mapping)
3416                 return -ENOMEM;
3417         return 0;
3418 }
3419
3420 static void bnxt_free_all_cp_arrays(struct bnxt *bp)
3421 {
3422         int i;
3423
3424         if (!bp->bnapi)
3425                 return;
3426         for (i = 0; i < bp->cp_nr_rings; i++) {
3427                 struct bnxt_napi *bnapi = bp->bnapi[i];
3428
3429                 if (!bnapi)
3430                         continue;
3431                 bnxt_free_cp_arrays(&bnapi->cp_ring);
3432         }
3433 }
3434
3435 static int bnxt_alloc_all_cp_arrays(struct bnxt *bp)
3436 {
3437         int i, n = bp->cp_nr_pages;
3438
3439         for (i = 0; i < bp->cp_nr_rings; i++) {
3440                 struct bnxt_napi *bnapi = bp->bnapi[i];
3441                 int rc;
3442
3443                 if (!bnapi)
3444                         continue;
3445                 rc = bnxt_alloc_cp_arrays(&bnapi->cp_ring, n);
3446                 if (rc)
3447                         return rc;
3448         }
3449         return 0;
3450 }
3451
3452 static void bnxt_free_cp_rings(struct bnxt *bp)
3453 {
3454         int i;
3455
3456         if (!bp->bnapi)
3457                 return;
3458
3459         for (i = 0; i < bp->cp_nr_rings; i++) {
3460                 struct bnxt_napi *bnapi = bp->bnapi[i];
3461                 struct bnxt_cp_ring_info *cpr;
3462                 struct bnxt_ring_struct *ring;
3463                 int j;
3464
3465                 if (!bnapi)
3466                         continue;
3467
3468                 cpr = &bnapi->cp_ring;
3469                 ring = &cpr->cp_ring_struct;
3470
3471                 bnxt_free_ring(bp, &ring->ring_mem);
3472
3473                 for (j = 0; j < 2; j++) {
3474                         struct bnxt_cp_ring_info *cpr2 = cpr->cp_ring_arr[j];
3475
3476                         if (cpr2) {
3477                                 ring = &cpr2->cp_ring_struct;
3478                                 bnxt_free_ring(bp, &ring->ring_mem);
3479                                 bnxt_free_cp_arrays(cpr2);
3480                                 kfree(cpr2);
3481                                 cpr->cp_ring_arr[j] = NULL;
3482                         }
3483                 }
3484         }
3485 }
3486
3487 static struct bnxt_cp_ring_info *bnxt_alloc_cp_sub_ring(struct bnxt *bp)
3488 {
3489         struct bnxt_ring_mem_info *rmem;
3490         struct bnxt_ring_struct *ring;
3491         struct bnxt_cp_ring_info *cpr;
3492         int rc;
3493
3494         cpr = kzalloc(sizeof(*cpr), GFP_KERNEL);
3495         if (!cpr)
3496                 return NULL;
3497
3498         rc = bnxt_alloc_cp_arrays(cpr, bp->cp_nr_pages);
3499         if (rc) {
3500                 bnxt_free_cp_arrays(cpr);
3501                 kfree(cpr);
3502                 return NULL;
3503         }
3504         ring = &cpr->cp_ring_struct;
3505         rmem = &ring->ring_mem;
3506         rmem->nr_pages = bp->cp_nr_pages;
3507         rmem->page_size = HW_CMPD_RING_SIZE;
3508         rmem->pg_arr = (void **)cpr->cp_desc_ring;
3509         rmem->dma_arr = cpr->cp_desc_mapping;
3510         rmem->flags = BNXT_RMEM_RING_PTE_FLAG;
3511         rc = bnxt_alloc_ring(bp, rmem);
3512         if (rc) {
3513                 bnxt_free_ring(bp, rmem);
3514                 bnxt_free_cp_arrays(cpr);
3515                 kfree(cpr);
3516                 cpr = NULL;
3517         }
3518         return cpr;
3519 }
3520
3521 static int bnxt_alloc_cp_rings(struct bnxt *bp)
3522 {
3523         bool sh = !!(bp->flags & BNXT_FLAG_SHARED_RINGS);
3524         int i, rc, ulp_base_vec, ulp_msix;
3525
3526         ulp_msix = bnxt_get_ulp_msix_num(bp);
3527         ulp_base_vec = bnxt_get_ulp_msix_base(bp);
3528         for (i = 0; i < bp->cp_nr_rings; i++) {
3529                 struct bnxt_napi *bnapi = bp->bnapi[i];
3530                 struct bnxt_cp_ring_info *cpr;
3531                 struct bnxt_ring_struct *ring;
3532
3533                 if (!bnapi)
3534                         continue;
3535
3536                 cpr = &bnapi->cp_ring;
3537                 cpr->bnapi = bnapi;
3538                 ring = &cpr->cp_ring_struct;
3539
3540                 rc = bnxt_alloc_ring(bp, &ring->ring_mem);
3541                 if (rc)
3542                         return rc;
3543
3544                 if (ulp_msix && i >= ulp_base_vec)
3545                         ring->map_idx = i + ulp_msix;
3546                 else
3547                         ring->map_idx = i;
3548
3549                 if (!(bp->flags & BNXT_FLAG_CHIP_P5))
3550                         continue;
3551
3552                 if (i < bp->rx_nr_rings) {
3553                         struct bnxt_cp_ring_info *cpr2 =
3554                                 bnxt_alloc_cp_sub_ring(bp);
3555
3556                         cpr->cp_ring_arr[BNXT_RX_HDL] = cpr2;
3557                         if (!cpr2)
3558                                 return -ENOMEM;
3559                         cpr2->bnapi = bnapi;
3560                 }
3561                 if ((sh && i < bp->tx_nr_rings) ||
3562                     (!sh && i >= bp->rx_nr_rings)) {
3563                         struct bnxt_cp_ring_info *cpr2 =
3564                                 bnxt_alloc_cp_sub_ring(bp);
3565
3566                         cpr->cp_ring_arr[BNXT_TX_HDL] = cpr2;
3567                         if (!cpr2)
3568                                 return -ENOMEM;
3569                         cpr2->bnapi = bnapi;
3570                 }
3571         }
3572         return 0;
3573 }
3574
3575 static void bnxt_init_ring_struct(struct bnxt *bp)
3576 {
3577         int i;
3578
3579         for (i = 0; i < bp->cp_nr_rings; i++) {
3580                 struct bnxt_napi *bnapi = bp->bnapi[i];
3581                 struct bnxt_ring_mem_info *rmem;
3582                 struct bnxt_cp_ring_info *cpr;
3583                 struct bnxt_rx_ring_info *rxr;
3584                 struct bnxt_tx_ring_info *txr;
3585                 struct bnxt_ring_struct *ring;
3586
3587                 if (!bnapi)
3588                         continue;
3589
3590                 cpr = &bnapi->cp_ring;
3591                 ring = &cpr->cp_ring_struct;
3592                 rmem = &ring->ring_mem;
3593                 rmem->nr_pages = bp->cp_nr_pages;
3594                 rmem->page_size = HW_CMPD_RING_SIZE;
3595                 rmem->pg_arr = (void **)cpr->cp_desc_ring;
3596                 rmem->dma_arr = cpr->cp_desc_mapping;
3597                 rmem->vmem_size = 0;
3598
3599                 rxr = bnapi->rx_ring;
3600                 if (!rxr)
3601                         goto skip_rx;
3602
3603                 ring = &rxr->rx_ring_struct;
3604                 rmem = &ring->ring_mem;
3605                 rmem->nr_pages = bp->rx_nr_pages;
3606                 rmem->page_size = HW_RXBD_RING_SIZE;
3607                 rmem->pg_arr = (void **)rxr->rx_desc_ring;
3608                 rmem->dma_arr = rxr->rx_desc_mapping;
3609                 rmem->vmem_size = SW_RXBD_RING_SIZE * bp->rx_nr_pages;
3610                 rmem->vmem = (void **)&rxr->rx_buf_ring;
3611
3612                 ring = &rxr->rx_agg_ring_struct;
3613                 rmem = &ring->ring_mem;
3614                 rmem->nr_pages = bp->rx_agg_nr_pages;
3615                 rmem->page_size = HW_RXBD_RING_SIZE;
3616                 rmem->pg_arr = (void **)rxr->rx_agg_desc_ring;
3617                 rmem->dma_arr = rxr->rx_agg_desc_mapping;
3618                 rmem->vmem_size = SW_RXBD_AGG_RING_SIZE * bp->rx_agg_nr_pages;
3619                 rmem->vmem = (void **)&rxr->rx_agg_ring;
3620
3621 skip_rx:
3622                 txr = bnapi->tx_ring;
3623                 if (!txr)
3624                         continue;
3625
3626                 ring = &txr->tx_ring_struct;
3627                 rmem = &ring->ring_mem;
3628                 rmem->nr_pages = bp->tx_nr_pages;
3629                 rmem->page_size = HW_RXBD_RING_SIZE;
3630                 rmem->pg_arr = (void **)txr->tx_desc_ring;
3631                 rmem->dma_arr = txr->tx_desc_mapping;
3632                 rmem->vmem_size = SW_TXBD_RING_SIZE * bp->tx_nr_pages;
3633                 rmem->vmem = (void **)&txr->tx_buf_ring;
3634         }
3635 }
3636
3637 static void bnxt_init_rxbd_pages(struct bnxt_ring_struct *ring, u32 type)
3638 {
3639         int i;
3640         u32 prod;
3641         struct rx_bd **rx_buf_ring;
3642
3643         rx_buf_ring = (struct rx_bd **)ring->ring_mem.pg_arr;
3644         for (i = 0, prod = 0; i < ring->ring_mem.nr_pages; i++) {
3645                 int j;
3646                 struct rx_bd *rxbd;
3647
3648                 rxbd = rx_buf_ring[i];
3649                 if (!rxbd)
3650                         continue;
3651
3652                 for (j = 0; j < RX_DESC_CNT; j++, rxbd++, prod++) {
3653                         rxbd->rx_bd_len_flags_type = cpu_to_le32(type);
3654                         rxbd->rx_bd_opaque = prod;
3655                 }
3656         }
3657 }
3658
3659 static int bnxt_alloc_one_rx_ring(struct bnxt *bp, int ring_nr)
3660 {
3661         struct bnxt_rx_ring_info *rxr = &bp->rx_ring[ring_nr];
3662         struct net_device *dev = bp->dev;
3663         u32 prod;
3664         int i;
3665
3666         prod = rxr->rx_prod;
3667         for (i = 0; i < bp->rx_ring_size; i++) {
3668                 if (bnxt_alloc_rx_data(bp, rxr, prod, GFP_KERNEL)) {
3669                         netdev_warn(dev, "init'ed rx ring %d with %d/%d skbs only\n",
3670                                     ring_nr, i, bp->rx_ring_size);
3671                         break;
3672                 }
3673                 prod = NEXT_RX(prod);
3674         }
3675         rxr->rx_prod = prod;
3676
3677         if (!(bp->flags & BNXT_FLAG_AGG_RINGS))
3678                 return 0;
3679
3680         prod = rxr->rx_agg_prod;
3681         for (i = 0; i < bp->rx_agg_ring_size; i++) {
3682                 if (bnxt_alloc_rx_page(bp, rxr, prod, GFP_KERNEL)) {
3683                         netdev_warn(dev, "init'ed rx ring %d with %d/%d pages only\n",
3684                                     ring_nr, i, bp->rx_ring_size);
3685                         break;
3686                 }
3687                 prod = NEXT_RX_AGG(prod);
3688         }
3689         rxr->rx_agg_prod = prod;
3690
3691         if (rxr->rx_tpa) {
3692                 dma_addr_t mapping;
3693                 u8 *data;
3694
3695                 for (i = 0; i < bp->max_tpa; i++) {
3696                         data = __bnxt_alloc_rx_frag(bp, &mapping, GFP_KERNEL);
3697                         if (!data)
3698                                 return -ENOMEM;
3699
3700                         rxr->rx_tpa[i].data = data;
3701                         rxr->rx_tpa[i].data_ptr = data + bp->rx_offset;
3702                         rxr->rx_tpa[i].mapping = mapping;
3703                 }
3704         }
3705         return 0;
3706 }
3707
3708 static int bnxt_init_one_rx_ring(struct bnxt *bp, int ring_nr)
3709 {
3710         struct bnxt_rx_ring_info *rxr;
3711         struct bnxt_ring_struct *ring;
3712         u32 type;
3713
3714         type = (bp->rx_buf_use_size << RX_BD_LEN_SHIFT) |
3715                 RX_BD_TYPE_RX_PACKET_BD | RX_BD_FLAGS_EOP;
3716
3717         if (NET_IP_ALIGN == 2)
3718                 type |= RX_BD_FLAGS_SOP;
3719
3720         rxr = &bp->rx_ring[ring_nr];
3721         ring = &rxr->rx_ring_struct;
3722         bnxt_init_rxbd_pages(ring, type);
3723
3724         if (BNXT_RX_PAGE_MODE(bp) && bp->xdp_prog) {
3725                 bpf_prog_add(bp->xdp_prog, 1);
3726                 rxr->xdp_prog = bp->xdp_prog;
3727         }
3728         ring->fw_ring_id = INVALID_HW_RING_ID;
3729
3730         ring = &rxr->rx_agg_ring_struct;
3731         ring->fw_ring_id = INVALID_HW_RING_ID;
3732
3733         if ((bp->flags & BNXT_FLAG_AGG_RINGS)) {
3734                 type = ((u32)BNXT_RX_PAGE_SIZE << RX_BD_LEN_SHIFT) |
3735                         RX_BD_TYPE_RX_AGG_BD | RX_BD_FLAGS_SOP;
3736
3737                 bnxt_init_rxbd_pages(ring, type);
3738         }
3739
3740         return bnxt_alloc_one_rx_ring(bp, ring_nr);
3741 }
3742
3743 static void bnxt_init_cp_rings(struct bnxt *bp)
3744 {
3745         int i, j;
3746
3747         for (i = 0; i < bp->cp_nr_rings; i++) {
3748                 struct bnxt_cp_ring_info *cpr = &bp->bnapi[i]->cp_ring;
3749                 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct;
3750
3751                 ring->fw_ring_id = INVALID_HW_RING_ID;
3752                 cpr->rx_ring_coal.coal_ticks = bp->rx_coal.coal_ticks;
3753                 cpr->rx_ring_coal.coal_bufs = bp->rx_coal.coal_bufs;
3754                 for (j = 0; j < 2; j++) {
3755                         struct bnxt_cp_ring_info *cpr2 = cpr->cp_ring_arr[j];
3756
3757                         if (!cpr2)
3758                                 continue;
3759
3760                         ring = &cpr2->cp_ring_struct;
3761                         ring->fw_ring_id = INVALID_HW_RING_ID;
3762                         cpr2->rx_ring_coal.coal_ticks = bp->rx_coal.coal_ticks;
3763                         cpr2->rx_ring_coal.coal_bufs = bp->rx_coal.coal_bufs;
3764                 }
3765         }
3766 }
3767
3768 static int bnxt_init_rx_rings(struct bnxt *bp)
3769 {
3770         int i, rc = 0;
3771
3772         if (BNXT_RX_PAGE_MODE(bp)) {
3773                 bp->rx_offset = NET_IP_ALIGN + XDP_PACKET_HEADROOM;
3774                 bp->rx_dma_offset = XDP_PACKET_HEADROOM;
3775         } else {
3776                 bp->rx_offset = BNXT_RX_OFFSET;
3777                 bp->rx_dma_offset = BNXT_RX_DMA_OFFSET;
3778         }
3779
3780         for (i = 0; i < bp->rx_nr_rings; i++) {
3781                 rc = bnxt_init_one_rx_ring(bp, i);
3782                 if (rc)
3783                         break;
3784         }
3785
3786         return rc;
3787 }
3788
3789 static int bnxt_init_tx_rings(struct bnxt *bp)
3790 {
3791         u16 i;
3792
3793         bp->tx_wake_thresh = max_t(int, bp->tx_ring_size / 2,
3794                                    BNXT_MIN_TX_DESC_CNT);
3795
3796         for (i = 0; i < bp->tx_nr_rings; i++) {
3797                 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
3798                 struct bnxt_ring_struct *ring = &txr->tx_ring_struct;
3799
3800                 ring->fw_ring_id = INVALID_HW_RING_ID;
3801         }
3802
3803         return 0;
3804 }
3805
3806 static void bnxt_free_ring_grps(struct bnxt *bp)
3807 {
3808         kfree(bp->grp_info);
3809         bp->grp_info = NULL;
3810 }
3811
3812 static int bnxt_init_ring_grps(struct bnxt *bp, bool irq_re_init)
3813 {
3814         int i;
3815
3816         if (irq_re_init) {
3817                 bp->grp_info = kcalloc(bp->cp_nr_rings,
3818                                        sizeof(struct bnxt_ring_grp_info),
3819                                        GFP_KERNEL);
3820                 if (!bp->grp_info)
3821                         return -ENOMEM;
3822         }
3823         for (i = 0; i < bp->cp_nr_rings; i++) {
3824                 if (irq_re_init)
3825                         bp->grp_info[i].fw_stats_ctx = INVALID_HW_RING_ID;
3826                 bp->grp_info[i].fw_grp_id = INVALID_HW_RING_ID;
3827                 bp->grp_info[i].rx_fw_ring_id = INVALID_HW_RING_ID;
3828                 bp->grp_info[i].agg_fw_ring_id = INVALID_HW_RING_ID;
3829                 bp->grp_info[i].cp_fw_ring_id = INVALID_HW_RING_ID;
3830         }
3831         return 0;
3832 }
3833
3834 static void bnxt_free_vnics(struct bnxt *bp)
3835 {
3836         kfree(bp->vnic_info);
3837         bp->vnic_info = NULL;
3838         bp->nr_vnics = 0;
3839 }
3840
3841 static int bnxt_alloc_vnics(struct bnxt *bp)
3842 {
3843         int num_vnics = 1;
3844
3845 #ifdef CONFIG_RFS_ACCEL
3846         if ((bp->flags & (BNXT_FLAG_RFS | BNXT_FLAG_CHIP_P5)) == BNXT_FLAG_RFS)
3847                 num_vnics += bp->rx_nr_rings;
3848 #endif
3849
3850         if (BNXT_CHIP_TYPE_NITRO_A0(bp))
3851                 num_vnics++;
3852
3853         bp->vnic_info = kcalloc(num_vnics, sizeof(struct bnxt_vnic_info),
3854                                 GFP_KERNEL);
3855         if (!bp->vnic_info)
3856                 return -ENOMEM;
3857
3858         bp->nr_vnics = num_vnics;
3859         return 0;
3860 }
3861
3862 static void bnxt_init_vnics(struct bnxt *bp)
3863 {
3864         int i;
3865
3866         for (i = 0; i < bp->nr_vnics; i++) {
3867                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3868                 int j;
3869
3870                 vnic->fw_vnic_id = INVALID_HW_RING_ID;
3871                 for (j = 0; j < BNXT_MAX_CTX_PER_VNIC; j++)
3872                         vnic->fw_rss_cos_lb_ctx[j] = INVALID_HW_RING_ID;
3873
3874                 vnic->fw_l2_ctx_id = INVALID_HW_RING_ID;
3875
3876                 if (bp->vnic_info[i].rss_hash_key) {
3877                         if (i == 0)
3878                                 get_random_bytes(vnic->rss_hash_key,
3879                                               HW_HASH_KEY_SIZE);
3880                         else
3881                                 memcpy(vnic->rss_hash_key,
3882                                        bp->vnic_info[0].rss_hash_key,
3883                                        HW_HASH_KEY_SIZE);
3884                 }
3885         }
3886 }
3887
3888 static int bnxt_calc_nr_ring_pages(u32 ring_size, int desc_per_pg)
3889 {
3890         int pages;
3891
3892         pages = ring_size / desc_per_pg;
3893
3894         if (!pages)
3895                 return 1;
3896
3897         pages++;
3898
3899         while (pages & (pages - 1))
3900                 pages++;
3901
3902         return pages;
3903 }
3904
3905 void bnxt_set_tpa_flags(struct bnxt *bp)
3906 {
3907         bp->flags &= ~BNXT_FLAG_TPA;
3908         if (bp->flags & BNXT_FLAG_NO_AGG_RINGS)
3909                 return;
3910         if (bp->dev->features & NETIF_F_LRO)
3911                 bp->flags |= BNXT_FLAG_LRO;
3912         else if (bp->dev->features & NETIF_F_GRO_HW)
3913                 bp->flags |= BNXT_FLAG_GRO;
3914 }
3915
3916 /* bp->rx_ring_size, bp->tx_ring_size, dev->mtu, BNXT_FLAG_{G|L}RO flags must
3917  * be set on entry.
3918  */
3919 void bnxt_set_ring_params(struct bnxt *bp)
3920 {
3921         u32 ring_size, rx_size, rx_space, max_rx_cmpl;
3922         u32 agg_factor = 0, agg_ring_size = 0;
3923
3924         /* 8 for CRC and VLAN */
3925         rx_size = SKB_DATA_ALIGN(bp->dev->mtu + ETH_HLEN + NET_IP_ALIGN + 8);
3926
3927         rx_space = rx_size + ALIGN(max(NET_SKB_PAD, XDP_PACKET_HEADROOM), 8) +
3928                 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
3929
3930         bp->rx_copy_thresh = BNXT_RX_COPY_THRESH;
3931         ring_size = bp->rx_ring_size;
3932         bp->rx_agg_ring_size = 0;
3933         bp->rx_agg_nr_pages = 0;
3934
3935         if (bp->flags & BNXT_FLAG_TPA)
3936                 agg_factor = min_t(u32, 4, 65536 / BNXT_RX_PAGE_SIZE);
3937
3938         bp->flags &= ~BNXT_FLAG_JUMBO;
3939         if (rx_space > PAGE_SIZE && !(bp->flags & BNXT_FLAG_NO_AGG_RINGS)) {
3940                 u32 jumbo_factor;
3941
3942                 bp->flags |= BNXT_FLAG_JUMBO;
3943                 jumbo_factor = PAGE_ALIGN(bp->dev->mtu - 40) >> PAGE_SHIFT;
3944                 if (jumbo_factor > agg_factor)
3945                         agg_factor = jumbo_factor;
3946         }
3947         if (agg_factor) {
3948                 if (ring_size > BNXT_MAX_RX_DESC_CNT_JUM_ENA) {
3949                         ring_size = BNXT_MAX_RX_DESC_CNT_JUM_ENA;
3950                         netdev_warn(bp->dev, "RX ring size reduced from %d to %d because the jumbo ring is now enabled\n",
3951                                     bp->rx_ring_size, ring_size);
3952                         bp->rx_ring_size = ring_size;
3953                 }
3954                 agg_ring_size = ring_size * agg_factor;
3955
3956                 bp->rx_agg_nr_pages = bnxt_calc_nr_ring_pages(agg_ring_size,
3957                                                         RX_DESC_CNT);
3958                 if (bp->rx_agg_nr_pages > MAX_RX_AGG_PAGES) {
3959                         u32 tmp = agg_ring_size;
3960
3961                         bp->rx_agg_nr_pages = MAX_RX_AGG_PAGES;
3962                         agg_ring_size = MAX_RX_AGG_PAGES * RX_DESC_CNT - 1;
3963                         netdev_warn(bp->dev, "rx agg ring size %d reduced to %d.\n",
3964                                     tmp, agg_ring_size);
3965                 }
3966                 bp->rx_agg_ring_size = agg_ring_size;
3967                 bp->rx_agg_ring_mask = (bp->rx_agg_nr_pages * RX_DESC_CNT) - 1;
3968
3969                 if (BNXT_RX_PAGE_MODE(bp)) {
3970                         rx_space = PAGE_SIZE;
3971                         rx_size = PAGE_SIZE -
3972                                   ALIGN(max(NET_SKB_PAD, XDP_PACKET_HEADROOM), 8) -
3973                                   SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
3974                 } else {
3975                         rx_size = SKB_DATA_ALIGN(BNXT_RX_COPY_THRESH + NET_IP_ALIGN);
3976                         rx_space = rx_size + NET_SKB_PAD +
3977                                 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
3978                 }
3979         }
3980
3981         bp->rx_buf_use_size = rx_size;
3982         bp->rx_buf_size = rx_space;
3983
3984         bp->rx_nr_pages = bnxt_calc_nr_ring_pages(ring_size, RX_DESC_CNT);
3985         bp->rx_ring_mask = (bp->rx_nr_pages * RX_DESC_CNT) - 1;
3986
3987         ring_size = bp->tx_ring_size;
3988         bp->tx_nr_pages = bnxt_calc_nr_ring_pages(ring_size, TX_DESC_CNT);
3989         bp->tx_ring_mask = (bp->tx_nr_pages * TX_DESC_CNT) - 1;
3990
3991         max_rx_cmpl = bp->rx_ring_size;
3992         /* MAX TPA needs to be added because TPA_START completions are
3993          * immediately recycled, so the TPA completions are not bound by
3994          * the RX ring size.
3995          */
3996         if (bp->flags & BNXT_FLAG_TPA)
3997                 max_rx_cmpl += bp->max_tpa;
3998         /* RX and TPA completions are 32-byte, all others are 16-byte */
3999         ring_size = max_rx_cmpl * 2 + agg_ring_size + bp->tx_ring_size;
4000         bp->cp_ring_size = ring_size;
4001
4002         bp->cp_nr_pages = bnxt_calc_nr_ring_pages(ring_size, CP_DESC_CNT);
4003         if (bp->cp_nr_pages > MAX_CP_PAGES) {
4004                 bp->cp_nr_pages = MAX_CP_PAGES;
4005                 bp->cp_ring_size = MAX_CP_PAGES * CP_DESC_CNT - 1;
4006                 netdev_warn(bp->dev, "completion ring size %d reduced to %d.\n",
4007                             ring_size, bp->cp_ring_size);
4008         }
4009         bp->cp_bit = bp->cp_nr_pages * CP_DESC_CNT;
4010         bp->cp_ring_mask = bp->cp_bit - 1;
4011 }
4012
4013 /* Changing allocation mode of RX rings.
4014  * TODO: Update when extending xdp_rxq_info to support allocation modes.
4015  */
4016 int bnxt_set_rx_skb_mode(struct bnxt *bp, bool page_mode)
4017 {
4018         if (page_mode) {
4019                 bp->flags &= ~BNXT_FLAG_AGG_RINGS;
4020                 bp->flags |= BNXT_FLAG_RX_PAGE_MODE;
4021
4022                 if (bp->dev->mtu > BNXT_MAX_PAGE_MODE_MTU) {
4023                         bp->flags |= BNXT_FLAG_JUMBO;
4024                         bp->rx_skb_func = bnxt_rx_multi_page_skb;
4025                         bp->dev->max_mtu =
4026                                 min_t(u16, bp->max_mtu, BNXT_MAX_MTU);
4027                 } else {
4028                         bp->flags |= BNXT_FLAG_NO_AGG_RINGS;
4029                         bp->rx_skb_func = bnxt_rx_page_skb;
4030                         bp->dev->max_mtu =
4031                                 min_t(u16, bp->max_mtu, BNXT_MAX_PAGE_MODE_MTU);
4032                 }
4033                 bp->rx_dir = DMA_BIDIRECTIONAL;
4034                 /* Disable LRO or GRO_HW */
4035                 netdev_update_features(bp->dev);
4036         } else {
4037                 bp->dev->max_mtu = bp->max_mtu;
4038                 bp->flags &= ~BNXT_FLAG_RX_PAGE_MODE;
4039                 bp->rx_dir = DMA_FROM_DEVICE;
4040                 bp->rx_skb_func = bnxt_rx_skb;
4041         }
4042         return 0;
4043 }
4044
4045 static void bnxt_free_vnic_attributes(struct bnxt *bp)
4046 {
4047         int i;
4048         struct bnxt_vnic_info *vnic;
4049         struct pci_dev *pdev = bp->pdev;
4050
4051         if (!bp->vnic_info)
4052                 return;
4053
4054         for (i = 0; i < bp->nr_vnics; i++) {
4055                 vnic = &bp->vnic_info[i];
4056
4057                 kfree(vnic->fw_grp_ids);
4058                 vnic->fw_grp_ids = NULL;
4059
4060                 kfree(vnic->uc_list);
4061                 vnic->uc_list = NULL;
4062
4063                 if (vnic->mc_list) {
4064                         dma_free_coherent(&pdev->dev, vnic->mc_list_size,
4065                                           vnic->mc_list, vnic->mc_list_mapping);
4066                         vnic->mc_list = NULL;
4067                 }
4068
4069                 if (vnic->rss_table) {
4070                         dma_free_coherent(&pdev->dev, vnic->rss_table_size,
4071                                           vnic->rss_table,
4072                                           vnic->rss_table_dma_addr);
4073                         vnic->rss_table = NULL;
4074                 }
4075
4076                 vnic->rss_hash_key = NULL;
4077                 vnic->flags = 0;
4078         }
4079 }
4080
4081 static int bnxt_alloc_vnic_attributes(struct bnxt *bp)
4082 {
4083         int i, rc = 0, size;
4084         struct bnxt_vnic_info *vnic;
4085         struct pci_dev *pdev = bp->pdev;
4086         int max_rings;
4087
4088         for (i = 0; i < bp->nr_vnics; i++) {
4089                 vnic = &bp->vnic_info[i];
4090
4091                 if (vnic->flags & BNXT_VNIC_UCAST_FLAG) {
4092                         int mem_size = (BNXT_MAX_UC_ADDRS - 1) * ETH_ALEN;
4093
4094                         if (mem_size > 0) {
4095                                 vnic->uc_list = kmalloc(mem_size, GFP_KERNEL);
4096                                 if (!vnic->uc_list) {
4097                                         rc = -ENOMEM;
4098                                         goto out;
4099                                 }
4100                         }
4101                 }
4102
4103                 if (vnic->flags & BNXT_VNIC_MCAST_FLAG) {
4104                         vnic->mc_list_size = BNXT_MAX_MC_ADDRS * ETH_ALEN;
4105                         vnic->mc_list =
4106                                 dma_alloc_coherent(&pdev->dev,
4107                                                    vnic->mc_list_size,
4108                                                    &vnic->mc_list_mapping,
4109                                                    GFP_KERNEL);
4110                         if (!vnic->mc_list) {
4111                                 rc = -ENOMEM;
4112                                 goto out;
4113                         }
4114                 }
4115
4116                 if (bp->flags & BNXT_FLAG_CHIP_P5)
4117                         goto vnic_skip_grps;
4118
4119                 if (vnic->flags & BNXT_VNIC_RSS_FLAG)
4120                         max_rings = bp->rx_nr_rings;
4121                 else
4122                         max_rings = 1;
4123
4124                 vnic->fw_grp_ids = kcalloc(max_rings, sizeof(u16), GFP_KERNEL);
4125                 if (!vnic->fw_grp_ids) {
4126                         rc = -ENOMEM;
4127                         goto out;
4128                 }
4129 vnic_skip_grps:
4130                 if ((bp->flags & BNXT_FLAG_NEW_RSS_CAP) &&
4131                     !(vnic->flags & BNXT_VNIC_RSS_FLAG))
4132                         continue;
4133
4134                 /* Allocate rss table and hash key */
4135                 size = L1_CACHE_ALIGN(HW_HASH_INDEX_SIZE * sizeof(u16));
4136                 if (bp->flags & BNXT_FLAG_CHIP_P5)
4137                         size = L1_CACHE_ALIGN(BNXT_MAX_RSS_TABLE_SIZE_P5);
4138
4139                 vnic->rss_table_size = size + HW_HASH_KEY_SIZE;
4140                 vnic->rss_table = dma_alloc_coherent(&pdev->dev,
4141                                                      vnic->rss_table_size,
4142                                                      &vnic->rss_table_dma_addr,
4143                                                      GFP_KERNEL);
4144                 if (!vnic->rss_table) {
4145                         rc = -ENOMEM;
4146                         goto out;
4147                 }
4148
4149                 vnic->rss_hash_key = ((void *)vnic->rss_table) + size;
4150                 vnic->rss_hash_key_dma_addr = vnic->rss_table_dma_addr + size;
4151         }
4152         return 0;
4153
4154 out:
4155         return rc;
4156 }
4157
4158 static void bnxt_free_hwrm_resources(struct bnxt *bp)
4159 {
4160         struct bnxt_hwrm_wait_token *token;
4161
4162         dma_pool_destroy(bp->hwrm_dma_pool);
4163         bp->hwrm_dma_pool = NULL;
4164
4165         rcu_read_lock();
4166         hlist_for_each_entry_rcu(token, &bp->hwrm_pending_list, node)
4167                 WRITE_ONCE(token->state, BNXT_HWRM_CANCELLED);
4168         rcu_read_unlock();
4169 }
4170
4171 static int bnxt_alloc_hwrm_resources(struct bnxt *bp)
4172 {
4173         bp->hwrm_dma_pool = dma_pool_create("bnxt_hwrm", &bp->pdev->dev,
4174                                             BNXT_HWRM_DMA_SIZE,
4175                                             BNXT_HWRM_DMA_ALIGN, 0);
4176         if (!bp->hwrm_dma_pool)
4177                 return -ENOMEM;
4178
4179         INIT_HLIST_HEAD(&bp->hwrm_pending_list);
4180
4181         return 0;
4182 }
4183
4184 static void bnxt_free_stats_mem(struct bnxt *bp, struct bnxt_stats_mem *stats)
4185 {
4186         kfree(stats->hw_masks);
4187         stats->hw_masks = NULL;
4188         kfree(stats->sw_stats);
4189         stats->sw_stats = NULL;
4190         if (stats->hw_stats) {
4191                 dma_free_coherent(&bp->pdev->dev, stats->len, stats->hw_stats,
4192                                   stats->hw_stats_map);
4193                 stats->hw_stats = NULL;
4194         }
4195 }
4196
4197 static int bnxt_alloc_stats_mem(struct bnxt *bp, struct bnxt_stats_mem *stats,
4198                                 bool alloc_masks)
4199 {
4200         stats->hw_stats = dma_alloc_coherent(&bp->pdev->dev, stats->len,
4201                                              &stats->hw_stats_map, GFP_KERNEL);
4202         if (!stats->hw_stats)
4203                 return -ENOMEM;
4204
4205         stats->sw_stats = kzalloc(stats->len, GFP_KERNEL);
4206         if (!stats->sw_stats)
4207                 goto stats_mem_err;
4208
4209         if (alloc_masks) {
4210                 stats->hw_masks = kzalloc(stats->len, GFP_KERNEL);
4211                 if (!stats->hw_masks)
4212                         goto stats_mem_err;
4213         }
4214         return 0;
4215
4216 stats_mem_err:
4217         bnxt_free_stats_mem(bp, stats);
4218         return -ENOMEM;
4219 }
4220
4221 static void bnxt_fill_masks(u64 *mask_arr, u64 mask, int count)
4222 {
4223         int i;
4224
4225         for (i = 0; i < count; i++)
4226                 mask_arr[i] = mask;
4227 }
4228
4229 static void bnxt_copy_hw_masks(u64 *mask_arr, __le64 *hw_mask_arr, int count)
4230 {
4231         int i;
4232
4233         for (i = 0; i < count; i++)
4234                 mask_arr[i] = le64_to_cpu(hw_mask_arr[i]);
4235 }
4236
4237 static int bnxt_hwrm_func_qstat_ext(struct bnxt *bp,
4238                                     struct bnxt_stats_mem *stats)
4239 {
4240         struct hwrm_func_qstats_ext_output *resp;
4241         struct hwrm_func_qstats_ext_input *req;
4242         __le64 *hw_masks;
4243         int rc;
4244
4245         if (!(bp->fw_cap & BNXT_FW_CAP_EXT_HW_STATS_SUPPORTED) ||
4246             !(bp->flags & BNXT_FLAG_CHIP_P5))
4247                 return -EOPNOTSUPP;
4248
4249         rc = hwrm_req_init(bp, req, HWRM_FUNC_QSTATS_EXT);
4250         if (rc)
4251                 return rc;
4252
4253         req->fid = cpu_to_le16(0xffff);
4254         req->flags = FUNC_QSTATS_EXT_REQ_FLAGS_COUNTER_MASK;
4255
4256         resp = hwrm_req_hold(bp, req);
4257         rc = hwrm_req_send(bp, req);
4258         if (!rc) {
4259                 hw_masks = &resp->rx_ucast_pkts;
4260                 bnxt_copy_hw_masks(stats->hw_masks, hw_masks, stats->len / 8);
4261         }
4262         hwrm_req_drop(bp, req);
4263         return rc;
4264 }
4265
4266 static int bnxt_hwrm_port_qstats(struct bnxt *bp, u8 flags);
4267 static int bnxt_hwrm_port_qstats_ext(struct bnxt *bp, u8 flags);
4268
4269 static void bnxt_init_stats(struct bnxt *bp)
4270 {
4271         struct bnxt_napi *bnapi = bp->bnapi[0];
4272         struct bnxt_cp_ring_info *cpr;
4273         struct bnxt_stats_mem *stats;
4274         __le64 *rx_stats, *tx_stats;
4275         int rc, rx_count, tx_count;
4276         u64 *rx_masks, *tx_masks;
4277         u64 mask;
4278         u8 flags;
4279
4280         cpr = &bnapi->cp_ring;
4281         stats = &cpr->stats;
4282         rc = bnxt_hwrm_func_qstat_ext(bp, stats);
4283         if (rc) {
4284                 if (bp->flags & BNXT_FLAG_CHIP_P5)
4285                         mask = (1ULL << 48) - 1;
4286                 else
4287                         mask = -1ULL;
4288                 bnxt_fill_masks(stats->hw_masks, mask, stats->len / 8);
4289         }
4290         if (bp->flags & BNXT_FLAG_PORT_STATS) {
4291                 stats = &bp->port_stats;
4292                 rx_stats = stats->hw_stats;
4293                 rx_masks = stats->hw_masks;
4294                 rx_count = sizeof(struct rx_port_stats) / 8;
4295                 tx_stats = rx_stats + BNXT_TX_PORT_STATS_BYTE_OFFSET / 8;
4296                 tx_masks = rx_masks + BNXT_TX_PORT_STATS_BYTE_OFFSET / 8;
4297                 tx_count = sizeof(struct tx_port_stats) / 8;
4298
4299                 flags = PORT_QSTATS_REQ_FLAGS_COUNTER_MASK;
4300                 rc = bnxt_hwrm_port_qstats(bp, flags);
4301                 if (rc) {
4302                         mask = (1ULL << 40) - 1;
4303
4304                         bnxt_fill_masks(rx_masks, mask, rx_count);
4305                         bnxt_fill_masks(tx_masks, mask, tx_count);
4306                 } else {
4307                         bnxt_copy_hw_masks(rx_masks, rx_stats, rx_count);
4308                         bnxt_copy_hw_masks(tx_masks, tx_stats, tx_count);
4309                         bnxt_hwrm_port_qstats(bp, 0);
4310                 }
4311         }
4312         if (bp->flags & BNXT_FLAG_PORT_STATS_EXT) {
4313                 stats = &bp->rx_port_stats_ext;
4314                 rx_stats = stats->hw_stats;
4315                 rx_masks = stats->hw_masks;
4316                 rx_count = sizeof(struct rx_port_stats_ext) / 8;
4317                 stats = &bp->tx_port_stats_ext;
4318                 tx_stats = stats->hw_stats;
4319                 tx_masks = stats->hw_masks;
4320                 tx_count = sizeof(struct tx_port_stats_ext) / 8;
4321
4322                 flags = PORT_QSTATS_EXT_REQ_FLAGS_COUNTER_MASK;
4323                 rc = bnxt_hwrm_port_qstats_ext(bp, flags);
4324                 if (rc) {
4325                         mask = (1ULL << 40) - 1;
4326
4327                         bnxt_fill_masks(rx_masks, mask, rx_count);
4328                         if (tx_stats)
4329                                 bnxt_fill_masks(tx_masks, mask, tx_count);
4330                 } else {
4331                         bnxt_copy_hw_masks(rx_masks, rx_stats, rx_count);
4332                         if (tx_stats)
4333                                 bnxt_copy_hw_masks(tx_masks, tx_stats,
4334                                                    tx_count);
4335                         bnxt_hwrm_port_qstats_ext(bp, 0);
4336                 }
4337         }
4338 }
4339
4340 static void bnxt_free_port_stats(struct bnxt *bp)
4341 {
4342         bp->flags &= ~BNXT_FLAG_PORT_STATS;
4343         bp->flags &= ~BNXT_FLAG_PORT_STATS_EXT;
4344
4345         bnxt_free_stats_mem(bp, &bp->port_stats);
4346         bnxt_free_stats_mem(bp, &bp->rx_port_stats_ext);
4347         bnxt_free_stats_mem(bp, &bp->tx_port_stats_ext);
4348 }
4349
4350 static void bnxt_free_ring_stats(struct bnxt *bp)
4351 {
4352         int i;
4353
4354         if (!bp->bnapi)
4355                 return;
4356
4357         for (i = 0; i < bp->cp_nr_rings; i++) {
4358                 struct bnxt_napi *bnapi = bp->bnapi[i];
4359                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
4360
4361                 bnxt_free_stats_mem(bp, &cpr->stats);
4362         }
4363 }
4364
4365 static int bnxt_alloc_stats(struct bnxt *bp)
4366 {
4367         u32 size, i;
4368         int rc;
4369
4370         size = bp->hw_ring_stats_size;
4371
4372         for (i = 0; i < bp->cp_nr_rings; i++) {
4373                 struct bnxt_napi *bnapi = bp->bnapi[i];
4374                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
4375
4376                 cpr->stats.len = size;
4377                 rc = bnxt_alloc_stats_mem(bp, &cpr->stats, !i);
4378                 if (rc)
4379                         return rc;
4380
4381                 cpr->hw_stats_ctx_id = INVALID_STATS_CTX_ID;
4382         }
4383
4384         if (BNXT_VF(bp) || bp->chip_num == CHIP_NUM_58700)
4385                 return 0;
4386
4387         if (bp->port_stats.hw_stats)
4388                 goto alloc_ext_stats;
4389
4390         bp->port_stats.len = BNXT_PORT_STATS_SIZE;
4391         rc = bnxt_alloc_stats_mem(bp, &bp->port_stats, true);
4392         if (rc)
4393                 return rc;
4394
4395         bp->flags |= BNXT_FLAG_PORT_STATS;
4396
4397 alloc_ext_stats:
4398         /* Display extended statistics only if FW supports it */
4399         if (bp->hwrm_spec_code < 0x10804 || bp->hwrm_spec_code == 0x10900)
4400                 if (!(bp->fw_cap & BNXT_FW_CAP_EXT_STATS_SUPPORTED))
4401                         return 0;
4402
4403         if (bp->rx_port_stats_ext.hw_stats)
4404                 goto alloc_tx_ext_stats;
4405
4406         bp->rx_port_stats_ext.len = sizeof(struct rx_port_stats_ext);
4407         rc = bnxt_alloc_stats_mem(bp, &bp->rx_port_stats_ext, true);
4408         /* Extended stats are optional */
4409         if (rc)
4410                 return 0;
4411
4412 alloc_tx_ext_stats:
4413         if (bp->tx_port_stats_ext.hw_stats)
4414                 return 0;
4415
4416         if (bp->hwrm_spec_code >= 0x10902 ||
4417             (bp->fw_cap & BNXT_FW_CAP_EXT_STATS_SUPPORTED)) {
4418                 bp->tx_port_stats_ext.len = sizeof(struct tx_port_stats_ext);
4419                 rc = bnxt_alloc_stats_mem(bp, &bp->tx_port_stats_ext, true);
4420                 /* Extended stats are optional */
4421                 if (rc)
4422                         return 0;
4423         }
4424         bp->flags |= BNXT_FLAG_PORT_STATS_EXT;
4425         return 0;
4426 }
4427
4428 static void bnxt_clear_ring_indices(struct bnxt *bp)
4429 {
4430         int i;
4431
4432         if (!bp->bnapi)
4433                 return;
4434
4435         for (i = 0; i < bp->cp_nr_rings; i++) {
4436                 struct bnxt_napi *bnapi = bp->bnapi[i];
4437                 struct bnxt_cp_ring_info *cpr;
4438                 struct bnxt_rx_ring_info *rxr;
4439                 struct bnxt_tx_ring_info *txr;
4440
4441                 if (!bnapi)
4442                         continue;
4443
4444                 cpr = &bnapi->cp_ring;
4445                 cpr->cp_raw_cons = 0;
4446
4447                 txr = bnapi->tx_ring;
4448                 if (txr) {
4449                         txr->tx_prod = 0;
4450                         txr->tx_cons = 0;
4451                 }
4452
4453                 rxr = bnapi->rx_ring;
4454                 if (rxr) {
4455                         rxr->rx_prod = 0;
4456                         rxr->rx_agg_prod = 0;
4457                         rxr->rx_sw_agg_prod = 0;
4458                         rxr->rx_next_cons = 0;
4459                 }
4460         }
4461 }
4462
4463 static void bnxt_free_ntp_fltrs(struct bnxt *bp, bool irq_reinit)
4464 {
4465 #ifdef CONFIG_RFS_ACCEL
4466         int i;
4467
4468         /* Under rtnl_lock and all our NAPIs have been disabled.  It's
4469          * safe to delete the hash table.
4470          */
4471         for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) {
4472                 struct hlist_head *head;
4473                 struct hlist_node *tmp;
4474                 struct bnxt_ntuple_filter *fltr;
4475
4476                 head = &bp->ntp_fltr_hash_tbl[i];
4477                 hlist_for_each_entry_safe(fltr, tmp, head, hash) {
4478                         hlist_del(&fltr->hash);
4479                         kfree(fltr);
4480                 }
4481         }
4482         if (irq_reinit) {
4483                 bitmap_free(bp->ntp_fltr_bmap);
4484                 bp->ntp_fltr_bmap = NULL;
4485         }
4486         bp->ntp_fltr_count = 0;
4487 #endif
4488 }
4489
4490 static int bnxt_alloc_ntp_fltrs(struct bnxt *bp)
4491 {
4492 #ifdef CONFIG_RFS_ACCEL
4493         int i, rc = 0;
4494
4495         if (!(bp->flags & BNXT_FLAG_RFS))
4496                 return 0;
4497
4498         for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++)
4499                 INIT_HLIST_HEAD(&bp->ntp_fltr_hash_tbl[i]);
4500
4501         bp->ntp_fltr_count = 0;
4502         bp->ntp_fltr_bmap = bitmap_zalloc(BNXT_NTP_FLTR_MAX_FLTR, GFP_KERNEL);
4503
4504         if (!bp->ntp_fltr_bmap)
4505                 rc = -ENOMEM;
4506
4507         return rc;
4508 #else
4509         return 0;
4510 #endif
4511 }
4512
4513 static void bnxt_free_mem(struct bnxt *bp, bool irq_re_init)
4514 {
4515         bnxt_free_vnic_attributes(bp);
4516         bnxt_free_tx_rings(bp);
4517         bnxt_free_rx_rings(bp);
4518         bnxt_free_cp_rings(bp);
4519         bnxt_free_all_cp_arrays(bp);
4520         bnxt_free_ntp_fltrs(bp, irq_re_init);
4521         if (irq_re_init) {
4522                 bnxt_free_ring_stats(bp);
4523                 if (!(bp->phy_flags & BNXT_PHY_FL_PORT_STATS_NO_RESET) ||
4524                     test_bit(BNXT_STATE_IN_FW_RESET, &bp->state))
4525                         bnxt_free_port_stats(bp);
4526                 bnxt_free_ring_grps(bp);
4527                 bnxt_free_vnics(bp);
4528                 kfree(bp->tx_ring_map);
4529                 bp->tx_ring_map = NULL;
4530                 kfree(bp->tx_ring);
4531                 bp->tx_ring = NULL;
4532                 kfree(bp->rx_ring);
4533                 bp->rx_ring = NULL;
4534                 kfree(bp->bnapi);
4535                 bp->bnapi = NULL;
4536         } else {
4537                 bnxt_clear_ring_indices(bp);
4538         }
4539 }
4540
4541 static int bnxt_alloc_mem(struct bnxt *bp, bool irq_re_init)
4542 {
4543         int i, j, rc, size, arr_size;
4544         void *bnapi;
4545
4546         if (irq_re_init) {
4547                 /* Allocate bnapi mem pointer array and mem block for
4548                  * all queues
4549                  */
4550                 arr_size = L1_CACHE_ALIGN(sizeof(struct bnxt_napi *) *
4551                                 bp->cp_nr_rings);
4552                 size = L1_CACHE_ALIGN(sizeof(struct bnxt_napi));
4553                 bnapi = kzalloc(arr_size + size * bp->cp_nr_rings, GFP_KERNEL);
4554                 if (!bnapi)
4555                         return -ENOMEM;
4556
4557                 bp->bnapi = bnapi;
4558                 bnapi += arr_size;
4559                 for (i = 0; i < bp->cp_nr_rings; i++, bnapi += size) {
4560                         bp->bnapi[i] = bnapi;
4561                         bp->bnapi[i]->index = i;
4562                         bp->bnapi[i]->bp = bp;
4563                         if (bp->flags & BNXT_FLAG_CHIP_P5) {
4564                                 struct bnxt_cp_ring_info *cpr =
4565                                         &bp->bnapi[i]->cp_ring;
4566
4567                                 cpr->cp_ring_struct.ring_mem.flags =
4568                                         BNXT_RMEM_RING_PTE_FLAG;
4569                         }
4570                 }
4571
4572                 bp->rx_ring = kcalloc(bp->rx_nr_rings,
4573                                       sizeof(struct bnxt_rx_ring_info),
4574                                       GFP_KERNEL);
4575                 if (!bp->rx_ring)
4576                         return -ENOMEM;
4577
4578                 for (i = 0; i < bp->rx_nr_rings; i++) {
4579                         struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
4580
4581                         if (bp->flags & BNXT_FLAG_CHIP_P5) {
4582                                 rxr->rx_ring_struct.ring_mem.flags =
4583                                         BNXT_RMEM_RING_PTE_FLAG;
4584                                 rxr->rx_agg_ring_struct.ring_mem.flags =
4585                                         BNXT_RMEM_RING_PTE_FLAG;
4586                         }
4587                         rxr->bnapi = bp->bnapi[i];
4588                         bp->bnapi[i]->rx_ring = &bp->rx_ring[i];
4589                 }
4590
4591                 bp->tx_ring = kcalloc(bp->tx_nr_rings,
4592                                       sizeof(struct bnxt_tx_ring_info),
4593                                       GFP_KERNEL);
4594                 if (!bp->tx_ring)
4595                         return -ENOMEM;
4596
4597                 bp->tx_ring_map = kcalloc(bp->tx_nr_rings, sizeof(u16),
4598                                           GFP_KERNEL);
4599
4600                 if (!bp->tx_ring_map)
4601                         return -ENOMEM;
4602
4603                 if (bp->flags & BNXT_FLAG_SHARED_RINGS)
4604                         j = 0;
4605                 else
4606                         j = bp->rx_nr_rings;
4607
4608                 for (i = 0; i < bp->tx_nr_rings; i++, j++) {
4609                         struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
4610
4611                         if (bp->flags & BNXT_FLAG_CHIP_P5)
4612                                 txr->tx_ring_struct.ring_mem.flags =
4613                                         BNXT_RMEM_RING_PTE_FLAG;
4614                         txr->bnapi = bp->bnapi[j];
4615                         bp->bnapi[j]->tx_ring = txr;
4616                         bp->tx_ring_map[i] = bp->tx_nr_rings_xdp + i;
4617                         if (i >= bp->tx_nr_rings_xdp) {
4618                                 txr->txq_index = i - bp->tx_nr_rings_xdp;
4619                                 bp->bnapi[j]->tx_int = bnxt_tx_int;
4620                         } else {
4621                                 bp->bnapi[j]->flags |= BNXT_NAPI_FLAG_XDP;
4622                                 bp->bnapi[j]->tx_int = bnxt_tx_int_xdp;
4623                         }
4624                 }
4625
4626                 rc = bnxt_alloc_stats(bp);
4627                 if (rc)
4628                         goto alloc_mem_err;
4629                 bnxt_init_stats(bp);
4630
4631                 rc = bnxt_alloc_ntp_fltrs(bp);
4632                 if (rc)
4633                         goto alloc_mem_err;
4634
4635                 rc = bnxt_alloc_vnics(bp);
4636                 if (rc)
4637                         goto alloc_mem_err;
4638         }
4639
4640         rc = bnxt_alloc_all_cp_arrays(bp);
4641         if (rc)
4642                 goto alloc_mem_err;
4643
4644         bnxt_init_ring_struct(bp);
4645
4646         rc = bnxt_alloc_rx_rings(bp);
4647         if (rc)
4648                 goto alloc_mem_err;
4649
4650         rc = bnxt_alloc_tx_rings(bp);
4651         if (rc)
4652                 goto alloc_mem_err;
4653
4654         rc = bnxt_alloc_cp_rings(bp);
4655         if (rc)
4656                 goto alloc_mem_err;
4657
4658         bp->vnic_info[0].flags |= BNXT_VNIC_RSS_FLAG | BNXT_VNIC_MCAST_FLAG |
4659                                   BNXT_VNIC_UCAST_FLAG;
4660         rc = bnxt_alloc_vnic_attributes(bp);
4661         if (rc)
4662                 goto alloc_mem_err;
4663         return 0;
4664
4665 alloc_mem_err:
4666         bnxt_free_mem(bp, true);
4667         return rc;
4668 }
4669
4670 static void bnxt_disable_int(struct bnxt *bp)
4671 {
4672         int i;
4673
4674         if (!bp->bnapi)
4675                 return;
4676
4677         for (i = 0; i < bp->cp_nr_rings; i++) {
4678                 struct bnxt_napi *bnapi = bp->bnapi[i];
4679                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
4680                 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct;
4681
4682                 if (ring->fw_ring_id != INVALID_HW_RING_ID)
4683                         bnxt_db_nq(bp, &cpr->cp_db, cpr->cp_raw_cons);
4684         }
4685 }
4686
4687 static int bnxt_cp_num_to_irq_num(struct bnxt *bp, int n)
4688 {
4689         struct bnxt_napi *bnapi = bp->bnapi[n];
4690         struct bnxt_cp_ring_info *cpr;
4691
4692         cpr = &bnapi->cp_ring;
4693         return cpr->cp_ring_struct.map_idx;
4694 }
4695
4696 static void bnxt_disable_int_sync(struct bnxt *bp)
4697 {
4698         int i;
4699
4700         if (!bp->irq_tbl)
4701                 return;
4702
4703         atomic_inc(&bp->intr_sem);
4704
4705         bnxt_disable_int(bp);
4706         for (i = 0; i < bp->cp_nr_rings; i++) {
4707                 int map_idx = bnxt_cp_num_to_irq_num(bp, i);
4708
4709                 synchronize_irq(bp->irq_tbl[map_idx].vector);
4710         }
4711 }
4712
4713 static void bnxt_enable_int(struct bnxt *bp)
4714 {
4715         int i;
4716
4717         atomic_set(&bp->intr_sem, 0);
4718         for (i = 0; i < bp->cp_nr_rings; i++) {
4719                 struct bnxt_napi *bnapi = bp->bnapi[i];
4720                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
4721
4722                 bnxt_db_nq_arm(bp, &cpr->cp_db, cpr->cp_raw_cons);
4723         }
4724 }
4725
4726 int bnxt_hwrm_func_drv_rgtr(struct bnxt *bp, unsigned long *bmap, int bmap_size,
4727                             bool async_only)
4728 {
4729         DECLARE_BITMAP(async_events_bmap, 256);
4730         u32 *events = (u32 *)async_events_bmap;
4731         struct hwrm_func_drv_rgtr_output *resp;
4732         struct hwrm_func_drv_rgtr_input *req;
4733         u32 flags;
4734         int rc, i;
4735
4736         rc = hwrm_req_init(bp, req, HWRM_FUNC_DRV_RGTR);
4737         if (rc)
4738                 return rc;
4739
4740         req->enables = cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_OS_TYPE |
4741                                    FUNC_DRV_RGTR_REQ_ENABLES_VER |
4742                                    FUNC_DRV_RGTR_REQ_ENABLES_ASYNC_EVENT_FWD);
4743
4744         req->os_type = cpu_to_le16(FUNC_DRV_RGTR_REQ_OS_TYPE_LINUX);
4745         flags = FUNC_DRV_RGTR_REQ_FLAGS_16BIT_VER_MODE;
4746         if (bp->fw_cap & BNXT_FW_CAP_HOT_RESET)
4747                 flags |= FUNC_DRV_RGTR_REQ_FLAGS_HOT_RESET_SUPPORT;
4748         if (bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY)
4749                 flags |= FUNC_DRV_RGTR_REQ_FLAGS_ERROR_RECOVERY_SUPPORT |
4750                          FUNC_DRV_RGTR_REQ_FLAGS_MASTER_SUPPORT;
4751         req->flags = cpu_to_le32(flags);
4752         req->ver_maj_8b = DRV_VER_MAJ;
4753         req->ver_min_8b = DRV_VER_MIN;
4754         req->ver_upd_8b = DRV_VER_UPD;
4755         req->ver_maj = cpu_to_le16(DRV_VER_MAJ);
4756         req->ver_min = cpu_to_le16(DRV_VER_MIN);
4757         req->ver_upd = cpu_to_le16(DRV_VER_UPD);
4758
4759         if (BNXT_PF(bp)) {
4760                 u32 data[8];
4761                 int i;
4762
4763                 memset(data, 0, sizeof(data));
4764                 for (i = 0; i < ARRAY_SIZE(bnxt_vf_req_snif); i++) {
4765                         u16 cmd = bnxt_vf_req_snif[i];
4766                         unsigned int bit, idx;
4767
4768                         idx = cmd / 32;
4769                         bit = cmd % 32;
4770                         data[idx] |= 1 << bit;
4771                 }
4772
4773                 for (i = 0; i < 8; i++)
4774                         req->vf_req_fwd[i] = cpu_to_le32(data[i]);
4775
4776                 req->enables |=
4777                         cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_VF_REQ_FWD);
4778         }
4779
4780         if (bp->fw_cap & BNXT_FW_CAP_OVS_64BIT_HANDLE)
4781                 req->flags |= cpu_to_le32(
4782                         FUNC_DRV_RGTR_REQ_FLAGS_FLOW_HANDLE_64BIT_MODE);
4783
4784         memset(async_events_bmap, 0, sizeof(async_events_bmap));
4785         for (i = 0; i < ARRAY_SIZE(bnxt_async_events_arr); i++) {
4786                 u16 event_id = bnxt_async_events_arr[i];
4787
4788                 if (event_id == ASYNC_EVENT_CMPL_EVENT_ID_ERROR_RECOVERY &&
4789                     !(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY))
4790                         continue;
4791                 __set_bit(bnxt_async_events_arr[i], async_events_bmap);
4792         }
4793         if (bmap && bmap_size) {
4794                 for (i = 0; i < bmap_size; i++) {
4795                         if (test_bit(i, bmap))
4796                                 __set_bit(i, async_events_bmap);
4797                 }
4798         }
4799         for (i = 0; i < 8; i++)
4800                 req->async_event_fwd[i] |= cpu_to_le32(events[i]);
4801
4802         if (async_only)
4803                 req->enables =
4804                         cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_ASYNC_EVENT_FWD);
4805
4806         resp = hwrm_req_hold(bp, req);
4807         rc = hwrm_req_send(bp, req);
4808         if (!rc) {
4809                 set_bit(BNXT_STATE_DRV_REGISTERED, &bp->state);
4810                 if (resp->flags &
4811                     cpu_to_le32(FUNC_DRV_RGTR_RESP_FLAGS_IF_CHANGE_SUPPORTED))
4812                         bp->fw_cap |= BNXT_FW_CAP_IF_CHANGE;
4813         }
4814         hwrm_req_drop(bp, req);
4815         return rc;
4816 }
4817
4818 int bnxt_hwrm_func_drv_unrgtr(struct bnxt *bp)
4819 {
4820         struct hwrm_func_drv_unrgtr_input *req;
4821         int rc;
4822
4823         if (!test_and_clear_bit(BNXT_STATE_DRV_REGISTERED, &bp->state))
4824                 return 0;
4825
4826         rc = hwrm_req_init(bp, req, HWRM_FUNC_DRV_UNRGTR);
4827         if (rc)
4828                 return rc;
4829         return hwrm_req_send(bp, req);
4830 }
4831
4832 static int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, u8 tunnel_type)
4833 {
4834         struct hwrm_tunnel_dst_port_free_input *req;
4835         int rc;
4836
4837         if (tunnel_type == TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN &&
4838             bp->vxlan_fw_dst_port_id == INVALID_HW_RING_ID)
4839                 return 0;
4840         if (tunnel_type == TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE &&
4841             bp->nge_fw_dst_port_id == INVALID_HW_RING_ID)
4842                 return 0;
4843
4844         rc = hwrm_req_init(bp, req, HWRM_TUNNEL_DST_PORT_FREE);
4845         if (rc)
4846                 return rc;
4847
4848         req->tunnel_type = tunnel_type;
4849
4850         switch (tunnel_type) {
4851         case TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN:
4852                 req->tunnel_dst_port_id = cpu_to_le16(bp->vxlan_fw_dst_port_id);
4853                 bp->vxlan_port = 0;
4854                 bp->vxlan_fw_dst_port_id = INVALID_HW_RING_ID;
4855                 break;
4856         case TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE:
4857                 req->tunnel_dst_port_id = cpu_to_le16(bp->nge_fw_dst_port_id);
4858                 bp->nge_port = 0;
4859                 bp->nge_fw_dst_port_id = INVALID_HW_RING_ID;
4860                 break;
4861         default:
4862                 break;
4863         }
4864
4865         rc = hwrm_req_send(bp, req);
4866         if (rc)
4867                 netdev_err(bp->dev, "hwrm_tunnel_dst_port_free failed. rc:%d\n",
4868                            rc);
4869         return rc;
4870 }
4871
4872 static int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, __be16 port,
4873                                            u8 tunnel_type)
4874 {
4875         struct hwrm_tunnel_dst_port_alloc_output *resp;
4876         struct hwrm_tunnel_dst_port_alloc_input *req;
4877         int rc;
4878
4879         rc = hwrm_req_init(bp, req, HWRM_TUNNEL_DST_PORT_ALLOC);
4880         if (rc)
4881                 return rc;
4882
4883         req->tunnel_type = tunnel_type;
4884         req->tunnel_dst_port_val = port;
4885
4886         resp = hwrm_req_hold(bp, req);
4887         rc = hwrm_req_send(bp, req);
4888         if (rc) {
4889                 netdev_err(bp->dev, "hwrm_tunnel_dst_port_alloc failed. rc:%d\n",
4890                            rc);
4891                 goto err_out;
4892         }
4893
4894         switch (tunnel_type) {
4895         case TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN:
4896                 bp->vxlan_port = port;
4897                 bp->vxlan_fw_dst_port_id =
4898                         le16_to_cpu(resp->tunnel_dst_port_id);
4899                 break;
4900         case TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_GENEVE:
4901                 bp->nge_port = port;
4902                 bp->nge_fw_dst_port_id = le16_to_cpu(resp->tunnel_dst_port_id);
4903                 break;
4904         default:
4905                 break;
4906         }
4907
4908 err_out:
4909         hwrm_req_drop(bp, req);
4910         return rc;
4911 }
4912
4913 static int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp, u16 vnic_id)
4914 {
4915         struct hwrm_cfa_l2_set_rx_mask_input *req;
4916         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
4917         int rc;
4918
4919         rc = hwrm_req_init(bp, req, HWRM_CFA_L2_SET_RX_MASK);
4920         if (rc)
4921                 return rc;
4922
4923         req->vnic_id = cpu_to_le32(vnic->fw_vnic_id);
4924         if (vnic->rx_mask & CFA_L2_SET_RX_MASK_REQ_MASK_MCAST) {
4925                 req->num_mc_entries = cpu_to_le32(vnic->mc_list_count);
4926                 req->mc_tbl_addr = cpu_to_le64(vnic->mc_list_mapping);
4927         }
4928         req->mask = cpu_to_le32(vnic->rx_mask);
4929         return hwrm_req_send_silent(bp, req);
4930 }
4931
4932 #ifdef CONFIG_RFS_ACCEL
4933 static int bnxt_hwrm_cfa_ntuple_filter_free(struct bnxt *bp,
4934                                             struct bnxt_ntuple_filter *fltr)
4935 {
4936         struct hwrm_cfa_ntuple_filter_free_input *req;
4937         int rc;
4938
4939         rc = hwrm_req_init(bp, req, HWRM_CFA_NTUPLE_FILTER_FREE);
4940         if (rc)
4941                 return rc;
4942
4943         req->ntuple_filter_id = fltr->filter_id;
4944         return hwrm_req_send(bp, req);
4945 }
4946
4947 #define BNXT_NTP_FLTR_FLAGS                                     \
4948         (CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID |     \
4949          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_ETHERTYPE |        \
4950          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_MACADDR |      \
4951          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IPADDR_TYPE |      \
4952          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR |       \
4953          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR_MASK |  \
4954          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR |       \
4955          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR_MASK |  \
4956          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IP_PROTOCOL |      \
4957          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT |         \
4958          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT_MASK |    \
4959          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT |         \
4960          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT_MASK |    \
4961          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_ID)
4962
4963 #define BNXT_NTP_TUNNEL_FLTR_FLAG                               \
4964                 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE
4965
4966 static int bnxt_hwrm_cfa_ntuple_filter_alloc(struct bnxt *bp,
4967                                              struct bnxt_ntuple_filter *fltr)
4968 {
4969         struct hwrm_cfa_ntuple_filter_alloc_output *resp;
4970         struct hwrm_cfa_ntuple_filter_alloc_input *req;
4971         struct flow_keys *keys = &fltr->fkeys;
4972         struct bnxt_vnic_info *vnic;
4973         u32 flags = 0;
4974         int rc;
4975
4976         rc = hwrm_req_init(bp, req, HWRM_CFA_NTUPLE_FILTER_ALLOC);
4977         if (rc)
4978                 return rc;
4979
4980         req->l2_filter_id = bp->vnic_info[0].fw_l2_filter_id[fltr->l2_fltr_idx];
4981
4982         if (bp->fw_cap & BNXT_FW_CAP_CFA_RFS_RING_TBL_IDX_V2) {
4983                 flags = CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_DEST_RFS_RING_IDX;
4984                 req->dst_id = cpu_to_le16(fltr->rxq);
4985         } else {
4986                 vnic = &bp->vnic_info[fltr->rxq + 1];
4987                 req->dst_id = cpu_to_le16(vnic->fw_vnic_id);
4988         }
4989         req->flags = cpu_to_le32(flags);
4990         req->enables = cpu_to_le32(BNXT_NTP_FLTR_FLAGS);
4991
4992         req->ethertype = htons(ETH_P_IP);
4993         memcpy(req->src_macaddr, fltr->src_mac_addr, ETH_ALEN);
4994         req->ip_addr_type = CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV4;
4995         req->ip_protocol = keys->basic.ip_proto;
4996
4997         if (keys->basic.n_proto == htons(ETH_P_IPV6)) {
4998                 int i;
4999
5000                 req->ethertype = htons(ETH_P_IPV6);
5001                 req->ip_addr_type =
5002                         CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6;
5003                 *(struct in6_addr *)&req->src_ipaddr[0] =
5004                         keys->addrs.v6addrs.src;
5005                 *(struct in6_addr *)&req->dst_ipaddr[0] =
5006                         keys->addrs.v6addrs.dst;
5007                 for (i = 0; i < 4; i++) {
5008                         req->src_ipaddr_mask[i] = cpu_to_be32(0xffffffff);
5009                         req->dst_ipaddr_mask[i] = cpu_to_be32(0xffffffff);
5010                 }
5011         } else {
5012                 req->src_ipaddr[0] = keys->addrs.v4addrs.src;
5013                 req->src_ipaddr_mask[0] = cpu_to_be32(0xffffffff);
5014                 req->dst_ipaddr[0] = keys->addrs.v4addrs.dst;
5015                 req->dst_ipaddr_mask[0] = cpu_to_be32(0xffffffff);
5016         }
5017         if (keys->control.flags & FLOW_DIS_ENCAPSULATION) {
5018                 req->enables |= cpu_to_le32(BNXT_NTP_TUNNEL_FLTR_FLAG);
5019                 req->tunnel_type =
5020                         CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL;
5021         }
5022
5023         req->src_port = keys->ports.src;
5024         req->src_port_mask = cpu_to_be16(0xffff);
5025         req->dst_port = keys->ports.dst;
5026         req->dst_port_mask = cpu_to_be16(0xffff);
5027
5028         resp = hwrm_req_hold(bp, req);
5029         rc = hwrm_req_send(bp, req);
5030         if (!rc)
5031                 fltr->filter_id = resp->ntuple_filter_id;
5032         hwrm_req_drop(bp, req);
5033         return rc;
5034 }
5035 #endif
5036
5037 static int bnxt_hwrm_set_vnic_filter(struct bnxt *bp, u16 vnic_id, u16 idx,
5038                                      const u8 *mac_addr)
5039 {
5040         struct hwrm_cfa_l2_filter_alloc_output *resp;
5041         struct hwrm_cfa_l2_filter_alloc_input *req;
5042         int rc;
5043
5044         rc = hwrm_req_init(bp, req, HWRM_CFA_L2_FILTER_ALLOC);
5045         if (rc)
5046                 return rc;
5047
5048         req->flags = cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX);
5049         if (!BNXT_CHIP_TYPE_NITRO_A0(bp))
5050                 req->flags |=
5051                         cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_FLAGS_OUTERMOST);
5052         req->dst_id = cpu_to_le16(bp->vnic_info[vnic_id].fw_vnic_id);
5053         req->enables =
5054                 cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR |
5055                             CFA_L2_FILTER_ALLOC_REQ_ENABLES_DST_ID |
5056                             CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR_MASK);
5057         memcpy(req->l2_addr, mac_addr, ETH_ALEN);
5058         req->l2_addr_mask[0] = 0xff;
5059         req->l2_addr_mask[1] = 0xff;
5060         req->l2_addr_mask[2] = 0xff;
5061         req->l2_addr_mask[3] = 0xff;
5062         req->l2_addr_mask[4] = 0xff;
5063         req->l2_addr_mask[5] = 0xff;
5064
5065         resp = hwrm_req_hold(bp, req);
5066         rc = hwrm_req_send(bp, req);
5067         if (!rc)
5068                 bp->vnic_info[vnic_id].fw_l2_filter_id[idx] =
5069                                                         resp->l2_filter_id;
5070         hwrm_req_drop(bp, req);
5071         return rc;
5072 }
5073
5074 static int bnxt_hwrm_clear_vnic_filter(struct bnxt *bp)
5075 {
5076         struct hwrm_cfa_l2_filter_free_input *req;
5077         u16 i, j, num_of_vnics = 1; /* only vnic 0 supported */
5078         int rc;
5079
5080         /* Any associated ntuple filters will also be cleared by firmware. */
5081         rc = hwrm_req_init(bp, req, HWRM_CFA_L2_FILTER_FREE);
5082         if (rc)
5083                 return rc;
5084         hwrm_req_hold(bp, req);
5085         for (i = 0; i < num_of_vnics; i++) {
5086                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
5087
5088                 for (j = 0; j < vnic->uc_filter_count; j++) {
5089                         req->l2_filter_id = vnic->fw_l2_filter_id[j];
5090
5091                         rc = hwrm_req_send(bp, req);
5092                 }
5093                 vnic->uc_filter_count = 0;
5094         }
5095         hwrm_req_drop(bp, req);
5096         return rc;
5097 }
5098
5099 static int bnxt_hwrm_vnic_set_tpa(struct bnxt *bp, u16 vnic_id, u32 tpa_flags)
5100 {
5101         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
5102         u16 max_aggs = VNIC_TPA_CFG_REQ_MAX_AGGS_MAX;
5103         struct hwrm_vnic_tpa_cfg_input *req;
5104         int rc;
5105
5106         if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
5107                 return 0;
5108
5109         rc = hwrm_req_init(bp, req, HWRM_VNIC_TPA_CFG);
5110         if (rc)
5111                 return rc;
5112
5113         if (tpa_flags) {
5114                 u16 mss = bp->dev->mtu - 40;
5115                 u32 nsegs, n, segs = 0, flags;
5116
5117                 flags = VNIC_TPA_CFG_REQ_FLAGS_TPA |
5118                         VNIC_TPA_CFG_REQ_FLAGS_ENCAP_TPA |
5119                         VNIC_TPA_CFG_REQ_FLAGS_RSC_WND_UPDATE |
5120                         VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_ECN |
5121                         VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_SAME_GRE_SEQ;
5122                 if (tpa_flags & BNXT_FLAG_GRO)
5123                         flags |= VNIC_TPA_CFG_REQ_FLAGS_GRO;
5124
5125                 req->flags = cpu_to_le32(flags);
5126
5127                 req->enables =
5128                         cpu_to_le32(VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_SEGS |
5129                                     VNIC_TPA_CFG_REQ_ENABLES_MAX_AGGS |
5130                                     VNIC_TPA_CFG_REQ_ENABLES_MIN_AGG_LEN);
5131
5132                 /* Number of segs are log2 units, and first packet is not
5133                  * included as part of this units.
5134                  */
5135                 if (mss <= BNXT_RX_PAGE_SIZE) {
5136                         n = BNXT_RX_PAGE_SIZE / mss;
5137                         nsegs = (MAX_SKB_FRAGS - 1) * n;
5138                 } else {
5139                         n = mss / BNXT_RX_PAGE_SIZE;
5140                         if (mss & (BNXT_RX_PAGE_SIZE - 1))
5141                                 n++;
5142                         nsegs = (MAX_SKB_FRAGS - n) / n;
5143                 }
5144
5145                 if (bp->flags & BNXT_FLAG_CHIP_P5) {
5146                         segs = MAX_TPA_SEGS_P5;
5147                         max_aggs = bp->max_tpa;
5148                 } else {
5149                         segs = ilog2(nsegs);
5150                 }
5151                 req->max_agg_segs = cpu_to_le16(segs);
5152                 req->max_aggs = cpu_to_le16(max_aggs);
5153
5154                 req->min_agg_len = cpu_to_le32(512);
5155         }
5156         req->vnic_id = cpu_to_le16(vnic->fw_vnic_id);
5157
5158         return hwrm_req_send(bp, req);
5159 }
5160
5161 static u16 bnxt_cp_ring_from_grp(struct bnxt *bp, struct bnxt_ring_struct *ring)
5162 {
5163         struct bnxt_ring_grp_info *grp_info;
5164
5165         grp_info = &bp->grp_info[ring->grp_idx];
5166         return grp_info->cp_fw_ring_id;
5167 }
5168
5169 static u16 bnxt_cp_ring_for_rx(struct bnxt *bp, struct bnxt_rx_ring_info *rxr)
5170 {
5171         if (bp->flags & BNXT_FLAG_CHIP_P5) {
5172                 struct bnxt_napi *bnapi = rxr->bnapi;
5173                 struct bnxt_cp_ring_info *cpr;
5174
5175                 cpr = bnapi->cp_ring.cp_ring_arr[BNXT_RX_HDL];
5176                 return cpr->cp_ring_struct.fw_ring_id;
5177         } else {
5178                 return bnxt_cp_ring_from_grp(bp, &rxr->rx_ring_struct);
5179         }
5180 }
5181
5182 static u16 bnxt_cp_ring_for_tx(struct bnxt *bp, struct bnxt_tx_ring_info *txr)
5183 {
5184         if (bp->flags & BNXT_FLAG_CHIP_P5) {
5185                 struct bnxt_napi *bnapi = txr->bnapi;
5186                 struct bnxt_cp_ring_info *cpr;
5187
5188                 cpr = bnapi->cp_ring.cp_ring_arr[BNXT_TX_HDL];
5189                 return cpr->cp_ring_struct.fw_ring_id;
5190         } else {
5191                 return bnxt_cp_ring_from_grp(bp, &txr->tx_ring_struct);
5192         }
5193 }
5194
5195 static int bnxt_alloc_rss_indir_tbl(struct bnxt *bp)
5196 {
5197         int entries;
5198
5199         if (bp->flags & BNXT_FLAG_CHIP_P5)
5200                 entries = BNXT_MAX_RSS_TABLE_ENTRIES_P5;
5201         else
5202                 entries = HW_HASH_INDEX_SIZE;
5203
5204         bp->rss_indir_tbl_entries = entries;
5205         bp->rss_indir_tbl = kmalloc_array(entries, sizeof(*bp->rss_indir_tbl),
5206                                           GFP_KERNEL);
5207         if (!bp->rss_indir_tbl)
5208                 return -ENOMEM;
5209         return 0;
5210 }
5211
5212 static void bnxt_set_dflt_rss_indir_tbl(struct bnxt *bp)
5213 {
5214         u16 max_rings, max_entries, pad, i;
5215
5216         if (!bp->rx_nr_rings)
5217                 return;
5218
5219         if (BNXT_CHIP_TYPE_NITRO_A0(bp))
5220                 max_rings = bp->rx_nr_rings - 1;
5221         else
5222                 max_rings = bp->rx_nr_rings;
5223
5224         max_entries = bnxt_get_rxfh_indir_size(bp->dev);
5225
5226         for (i = 0; i < max_entries; i++)
5227                 bp->rss_indir_tbl[i] = ethtool_rxfh_indir_default(i, max_rings);
5228
5229         pad = bp->rss_indir_tbl_entries - max_entries;
5230         if (pad)
5231                 memset(&bp->rss_indir_tbl[i], 0, pad * sizeof(u16));
5232 }
5233
5234 static u16 bnxt_get_max_rss_ring(struct bnxt *bp)
5235 {
5236         u16 i, tbl_size, max_ring = 0;
5237
5238         if (!bp->rss_indir_tbl)
5239                 return 0;
5240
5241         tbl_size = bnxt_get_rxfh_indir_size(bp->dev);
5242         for (i = 0; i < tbl_size; i++)
5243                 max_ring = max(max_ring, bp->rss_indir_tbl[i]);
5244         return max_ring;
5245 }
5246
5247 int bnxt_get_nr_rss_ctxs(struct bnxt *bp, int rx_rings)
5248 {
5249         if (bp->flags & BNXT_FLAG_CHIP_P5)
5250                 return DIV_ROUND_UP(rx_rings, BNXT_RSS_TABLE_ENTRIES_P5);
5251         if (BNXT_CHIP_TYPE_NITRO_A0(bp))
5252                 return 2;
5253         return 1;
5254 }
5255
5256 static void bnxt_fill_hw_rss_tbl(struct bnxt *bp, struct bnxt_vnic_info *vnic)
5257 {
5258         bool no_rss = !(vnic->flags & BNXT_VNIC_RSS_FLAG);
5259         u16 i, j;
5260
5261         /* Fill the RSS indirection table with ring group ids */
5262         for (i = 0, j = 0; i < HW_HASH_INDEX_SIZE; i++) {
5263                 if (!no_rss)
5264                         j = bp->rss_indir_tbl[i];
5265                 vnic->rss_table[i] = cpu_to_le16(vnic->fw_grp_ids[j]);
5266         }
5267 }
5268
5269 static void bnxt_fill_hw_rss_tbl_p5(struct bnxt *bp,
5270                                     struct bnxt_vnic_info *vnic)
5271 {
5272         __le16 *ring_tbl = vnic->rss_table;
5273         struct bnxt_rx_ring_info *rxr;
5274         u16 tbl_size, i;
5275
5276         tbl_size = bnxt_get_rxfh_indir_size(bp->dev);
5277
5278         for (i = 0; i < tbl_size; i++) {
5279                 u16 ring_id, j;
5280
5281                 j = bp->rss_indir_tbl[i];
5282                 rxr = &bp->rx_ring[j];
5283
5284                 ring_id = rxr->rx_ring_struct.fw_ring_id;
5285                 *ring_tbl++ = cpu_to_le16(ring_id);
5286                 ring_id = bnxt_cp_ring_for_rx(bp, rxr);
5287                 *ring_tbl++ = cpu_to_le16(ring_id);
5288         }
5289 }
5290
5291 static void
5292 __bnxt_hwrm_vnic_set_rss(struct bnxt *bp, struct hwrm_vnic_rss_cfg_input *req,
5293                          struct bnxt_vnic_info *vnic)
5294 {
5295         if (bp->flags & BNXT_FLAG_CHIP_P5)
5296                 bnxt_fill_hw_rss_tbl_p5(bp, vnic);
5297         else
5298                 bnxt_fill_hw_rss_tbl(bp, vnic);
5299
5300         if (bp->rss_hash_delta) {
5301                 req->hash_type = cpu_to_le32(bp->rss_hash_delta);
5302                 if (bp->rss_hash_cfg & bp->rss_hash_delta)
5303                         req->flags |= VNIC_RSS_CFG_REQ_FLAGS_HASH_TYPE_INCLUDE;
5304                 else
5305                         req->flags |= VNIC_RSS_CFG_REQ_FLAGS_HASH_TYPE_EXCLUDE;
5306         } else {
5307                 req->hash_type = cpu_to_le32(bp->rss_hash_cfg);
5308         }
5309         req->hash_mode_flags = VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_DEFAULT;
5310         req->ring_grp_tbl_addr = cpu_to_le64(vnic->rss_table_dma_addr);
5311         req->hash_key_tbl_addr = cpu_to_le64(vnic->rss_hash_key_dma_addr);
5312 }
5313
5314 static int bnxt_hwrm_vnic_set_rss(struct bnxt *bp, u16 vnic_id, bool set_rss)
5315 {
5316         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
5317         struct hwrm_vnic_rss_cfg_input *req;
5318         int rc;
5319
5320         if ((bp->flags & BNXT_FLAG_CHIP_P5) ||
5321             vnic->fw_rss_cos_lb_ctx[0] == INVALID_HW_RING_ID)
5322                 return 0;
5323
5324         rc = hwrm_req_init(bp, req, HWRM_VNIC_RSS_CFG);
5325         if (rc)
5326                 return rc;
5327
5328         if (set_rss)
5329                 __bnxt_hwrm_vnic_set_rss(bp, req, vnic);
5330         req->rss_ctx_idx = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[0]);
5331         return hwrm_req_send(bp, req);
5332 }
5333
5334 static int bnxt_hwrm_vnic_set_rss_p5(struct bnxt *bp, u16 vnic_id, bool set_rss)
5335 {
5336         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
5337         struct hwrm_vnic_rss_cfg_input *req;
5338         dma_addr_t ring_tbl_map;
5339         u32 i, nr_ctxs;
5340         int rc;
5341
5342         rc = hwrm_req_init(bp, req, HWRM_VNIC_RSS_CFG);
5343         if (rc)
5344                 return rc;
5345
5346         req->vnic_id = cpu_to_le16(vnic->fw_vnic_id);
5347         if (!set_rss)
5348                 return hwrm_req_send(bp, req);
5349
5350         __bnxt_hwrm_vnic_set_rss(bp, req, vnic);
5351         ring_tbl_map = vnic->rss_table_dma_addr;
5352         nr_ctxs = bnxt_get_nr_rss_ctxs(bp, bp->rx_nr_rings);
5353
5354         hwrm_req_hold(bp, req);
5355         for (i = 0; i < nr_ctxs; ring_tbl_map += BNXT_RSS_TABLE_SIZE_P5, i++) {
5356                 req->ring_grp_tbl_addr = cpu_to_le64(ring_tbl_map);
5357                 req->ring_table_pair_index = i;
5358                 req->rss_ctx_idx = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[i]);
5359                 rc = hwrm_req_send(bp, req);
5360                 if (rc)
5361                         goto exit;
5362         }
5363
5364 exit:
5365         hwrm_req_drop(bp, req);
5366         return rc;
5367 }
5368
5369 static void bnxt_hwrm_update_rss_hash_cfg(struct bnxt *bp)
5370 {
5371         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
5372         struct hwrm_vnic_rss_qcfg_output *resp;
5373         struct hwrm_vnic_rss_qcfg_input *req;
5374
5375         if (hwrm_req_init(bp, req, HWRM_VNIC_RSS_QCFG))
5376                 return;
5377
5378         /* all contexts configured to same hash_type, zero always exists */
5379         req->rss_ctx_idx = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[0]);
5380         resp = hwrm_req_hold(bp, req);
5381         if (!hwrm_req_send(bp, req)) {
5382                 bp->rss_hash_cfg = le32_to_cpu(resp->hash_type) ?: bp->rss_hash_cfg;
5383                 bp->rss_hash_delta = 0;
5384         }
5385         hwrm_req_drop(bp, req);
5386 }
5387
5388 static int bnxt_hwrm_vnic_set_hds(struct bnxt *bp, u16 vnic_id)
5389 {
5390         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
5391         struct hwrm_vnic_plcmodes_cfg_input *req;
5392         int rc;
5393
5394         rc = hwrm_req_init(bp, req, HWRM_VNIC_PLCMODES_CFG);
5395         if (rc)
5396                 return rc;
5397
5398         req->flags = cpu_to_le32(VNIC_PLCMODES_CFG_REQ_FLAGS_JUMBO_PLACEMENT);
5399         req->enables = cpu_to_le32(VNIC_PLCMODES_CFG_REQ_ENABLES_JUMBO_THRESH_VALID);
5400
5401         if (BNXT_RX_PAGE_MODE(bp)) {
5402                 req->jumbo_thresh = cpu_to_le16(bp->rx_buf_use_size);
5403         } else {
5404                 req->flags |= cpu_to_le32(VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV4 |
5405                                           VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV6);
5406                 req->enables |=
5407                         cpu_to_le32(VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_THRESHOLD_VALID);
5408                 req->jumbo_thresh = cpu_to_le16(bp->rx_copy_thresh);
5409                 req->hds_threshold = cpu_to_le16(bp->rx_copy_thresh);
5410         }
5411         req->vnic_id = cpu_to_le32(vnic->fw_vnic_id);
5412         return hwrm_req_send(bp, req);
5413 }
5414
5415 static void bnxt_hwrm_vnic_ctx_free_one(struct bnxt *bp, u16 vnic_id,
5416                                         u16 ctx_idx)
5417 {
5418         struct hwrm_vnic_rss_cos_lb_ctx_free_input *req;
5419
5420         if (hwrm_req_init(bp, req, HWRM_VNIC_RSS_COS_LB_CTX_FREE))
5421                 return;
5422
5423         req->rss_cos_lb_ctx_id =
5424                 cpu_to_le16(bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[ctx_idx]);
5425
5426         hwrm_req_send(bp, req);
5427         bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[ctx_idx] = INVALID_HW_RING_ID;
5428 }
5429
5430 static void bnxt_hwrm_vnic_ctx_free(struct bnxt *bp)
5431 {
5432         int i, j;
5433
5434         for (i = 0; i < bp->nr_vnics; i++) {
5435                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
5436
5437                 for (j = 0; j < BNXT_MAX_CTX_PER_VNIC; j++) {
5438                         if (vnic->fw_rss_cos_lb_ctx[j] != INVALID_HW_RING_ID)
5439                                 bnxt_hwrm_vnic_ctx_free_one(bp, i, j);
5440                 }
5441         }
5442         bp->rsscos_nr_ctxs = 0;
5443 }
5444
5445 static int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp, u16 vnic_id, u16 ctx_idx)
5446 {
5447         struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp;
5448         struct hwrm_vnic_rss_cos_lb_ctx_alloc_input *req;
5449         int rc;
5450
5451         rc = hwrm_req_init(bp, req, HWRM_VNIC_RSS_COS_LB_CTX_ALLOC);
5452         if (rc)
5453                 return rc;
5454
5455         resp = hwrm_req_hold(bp, req);
5456         rc = hwrm_req_send(bp, req);
5457         if (!rc)
5458                 bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[ctx_idx] =
5459                         le16_to_cpu(resp->rss_cos_lb_ctx_id);
5460         hwrm_req_drop(bp, req);
5461
5462         return rc;
5463 }
5464
5465 static u32 bnxt_get_roce_vnic_mode(struct bnxt *bp)
5466 {
5467         if (bp->flags & BNXT_FLAG_ROCE_MIRROR_CAP)
5468                 return VNIC_CFG_REQ_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_MODE;
5469         return VNIC_CFG_REQ_FLAGS_ROCE_DUAL_VNIC_MODE;
5470 }
5471
5472 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, u16 vnic_id)
5473 {
5474         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
5475         struct hwrm_vnic_cfg_input *req;
5476         unsigned int ring = 0, grp_idx;
5477         u16 def_vlan = 0;
5478         int rc;
5479
5480         rc = hwrm_req_init(bp, req, HWRM_VNIC_CFG);
5481         if (rc)
5482                 return rc;
5483
5484         if (bp->flags & BNXT_FLAG_CHIP_P5) {
5485                 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[0];
5486
5487                 req->default_rx_ring_id =
5488                         cpu_to_le16(rxr->rx_ring_struct.fw_ring_id);
5489                 req->default_cmpl_ring_id =
5490                         cpu_to_le16(bnxt_cp_ring_for_rx(bp, rxr));
5491                 req->enables =
5492                         cpu_to_le32(VNIC_CFG_REQ_ENABLES_DEFAULT_RX_RING_ID |
5493                                     VNIC_CFG_REQ_ENABLES_DEFAULT_CMPL_RING_ID);
5494                 goto vnic_mru;
5495         }
5496         req->enables = cpu_to_le32(VNIC_CFG_REQ_ENABLES_DFLT_RING_GRP);
5497         /* Only RSS support for now TBD: COS & LB */
5498         if (vnic->fw_rss_cos_lb_ctx[0] != INVALID_HW_RING_ID) {
5499                 req->rss_rule = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[0]);
5500                 req->enables |= cpu_to_le32(VNIC_CFG_REQ_ENABLES_RSS_RULE |
5501                                            VNIC_CFG_REQ_ENABLES_MRU);
5502         } else if (vnic->flags & BNXT_VNIC_RFS_NEW_RSS_FLAG) {
5503                 req->rss_rule =
5504                         cpu_to_le16(bp->vnic_info[0].fw_rss_cos_lb_ctx[0]);
5505                 req->enables |= cpu_to_le32(VNIC_CFG_REQ_ENABLES_RSS_RULE |
5506                                            VNIC_CFG_REQ_ENABLES_MRU);
5507                 req->flags |= cpu_to_le32(VNIC_CFG_REQ_FLAGS_RSS_DFLT_CR_MODE);
5508         } else {
5509                 req->rss_rule = cpu_to_le16(0xffff);
5510         }
5511
5512         if (BNXT_CHIP_TYPE_NITRO_A0(bp) &&
5513             (vnic->fw_rss_cos_lb_ctx[0] != INVALID_HW_RING_ID)) {
5514                 req->cos_rule = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[1]);
5515                 req->enables |= cpu_to_le32(VNIC_CFG_REQ_ENABLES_COS_RULE);
5516         } else {
5517                 req->cos_rule = cpu_to_le16(0xffff);
5518         }
5519
5520         if (vnic->flags & BNXT_VNIC_RSS_FLAG)
5521                 ring = 0;
5522         else if (vnic->flags & BNXT_VNIC_RFS_FLAG)
5523                 ring = vnic_id - 1;
5524         else if ((vnic_id == 1) && BNXT_CHIP_TYPE_NITRO_A0(bp))
5525                 ring = bp->rx_nr_rings - 1;
5526
5527         grp_idx = bp->rx_ring[ring].bnapi->index;
5528         req->dflt_ring_grp = cpu_to_le16(bp->grp_info[grp_idx].fw_grp_id);
5529         req->lb_rule = cpu_to_le16(0xffff);
5530 vnic_mru:
5531         req->mru = cpu_to_le16(bp->dev->mtu + ETH_HLEN + VLAN_HLEN);
5532
5533         req->vnic_id = cpu_to_le16(vnic->fw_vnic_id);
5534 #ifdef CONFIG_BNXT_SRIOV
5535         if (BNXT_VF(bp))
5536                 def_vlan = bp->vf.vlan;
5537 #endif
5538         if ((bp->flags & BNXT_FLAG_STRIP_VLAN) || def_vlan)
5539                 req->flags |= cpu_to_le32(VNIC_CFG_REQ_FLAGS_VLAN_STRIP_MODE);
5540         if (!vnic_id && bnxt_ulp_registered(bp->edev))
5541                 req->flags |= cpu_to_le32(bnxt_get_roce_vnic_mode(bp));
5542
5543         return hwrm_req_send(bp, req);
5544 }
5545
5546 static void bnxt_hwrm_vnic_free_one(struct bnxt *bp, u16 vnic_id)
5547 {
5548         if (bp->vnic_info[vnic_id].fw_vnic_id != INVALID_HW_RING_ID) {
5549                 struct hwrm_vnic_free_input *req;
5550
5551                 if (hwrm_req_init(bp, req, HWRM_VNIC_FREE))
5552                         return;
5553
5554                 req->vnic_id =
5555                         cpu_to_le32(bp->vnic_info[vnic_id].fw_vnic_id);
5556
5557                 hwrm_req_send(bp, req);
5558                 bp->vnic_info[vnic_id].fw_vnic_id = INVALID_HW_RING_ID;
5559         }
5560 }
5561
5562 static void bnxt_hwrm_vnic_free(struct bnxt *bp)
5563 {
5564         u16 i;
5565
5566         for (i = 0; i < bp->nr_vnics; i++)
5567                 bnxt_hwrm_vnic_free_one(bp, i);
5568 }
5569
5570 static int bnxt_hwrm_vnic_alloc(struct bnxt *bp, u16 vnic_id,
5571                                 unsigned int start_rx_ring_idx,
5572                                 unsigned int nr_rings)
5573 {
5574         unsigned int i, j, grp_idx, end_idx = start_rx_ring_idx + nr_rings;
5575         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
5576         struct hwrm_vnic_alloc_output *resp;
5577         struct hwrm_vnic_alloc_input *req;
5578         int rc;
5579
5580         rc = hwrm_req_init(bp, req, HWRM_VNIC_ALLOC);
5581         if (rc)
5582                 return rc;
5583
5584         if (bp->flags & BNXT_FLAG_CHIP_P5)
5585                 goto vnic_no_ring_grps;
5586
5587         /* map ring groups to this vnic */
5588         for (i = start_rx_ring_idx, j = 0; i < end_idx; i++, j++) {
5589                 grp_idx = bp->rx_ring[i].bnapi->index;
5590                 if (bp->grp_info[grp_idx].fw_grp_id == INVALID_HW_RING_ID) {
5591                         netdev_err(bp->dev, "Not enough ring groups avail:%x req:%x\n",
5592                                    j, nr_rings);
5593                         break;
5594                 }
5595                 vnic->fw_grp_ids[j] = bp->grp_info[grp_idx].fw_grp_id;
5596         }
5597
5598 vnic_no_ring_grps:
5599         for (i = 0; i < BNXT_MAX_CTX_PER_VNIC; i++)
5600                 vnic->fw_rss_cos_lb_ctx[i] = INVALID_HW_RING_ID;
5601         if (vnic_id == 0)
5602                 req->flags = cpu_to_le32(VNIC_ALLOC_REQ_FLAGS_DEFAULT);
5603
5604         resp = hwrm_req_hold(bp, req);
5605         rc = hwrm_req_send(bp, req);
5606         if (!rc)
5607                 vnic->fw_vnic_id = le32_to_cpu(resp->vnic_id);
5608         hwrm_req_drop(bp, req);
5609         return rc;
5610 }
5611
5612 static int bnxt_hwrm_vnic_qcaps(struct bnxt *bp)
5613 {
5614         struct hwrm_vnic_qcaps_output *resp;
5615         struct hwrm_vnic_qcaps_input *req;
5616         int rc;
5617
5618         bp->hw_ring_stats_size = sizeof(struct ctx_hw_stats);
5619         bp->flags &= ~(BNXT_FLAG_NEW_RSS_CAP | BNXT_FLAG_ROCE_MIRROR_CAP);
5620         if (bp->hwrm_spec_code < 0x10600)
5621                 return 0;
5622
5623         rc = hwrm_req_init(bp, req, HWRM_VNIC_QCAPS);
5624         if (rc)
5625                 return rc;
5626
5627         resp = hwrm_req_hold(bp, req);
5628         rc = hwrm_req_send(bp, req);
5629         if (!rc) {
5630                 u32 flags = le32_to_cpu(resp->flags);
5631
5632                 if (!(bp->flags & BNXT_FLAG_CHIP_P5) &&
5633                     (flags & VNIC_QCAPS_RESP_FLAGS_RSS_DFLT_CR_CAP))
5634                         bp->flags |= BNXT_FLAG_NEW_RSS_CAP;
5635                 if (flags &
5636                     VNIC_QCAPS_RESP_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_CAP)
5637                         bp->flags |= BNXT_FLAG_ROCE_MIRROR_CAP;
5638
5639                 /* Older P5 fw before EXT_HW_STATS support did not set
5640                  * VLAN_STRIP_CAP properly.
5641                  */
5642                 if ((flags & VNIC_QCAPS_RESP_FLAGS_VLAN_STRIP_CAP) ||
5643                     (BNXT_CHIP_P5_THOR(bp) &&
5644                      !(bp->fw_cap & BNXT_FW_CAP_EXT_HW_STATS_SUPPORTED)))
5645                         bp->fw_cap |= BNXT_FW_CAP_VLAN_RX_STRIP;
5646                 if (flags & VNIC_QCAPS_RESP_FLAGS_RSS_HASH_TYPE_DELTA_CAP)
5647                         bp->fw_cap |= BNXT_FW_CAP_RSS_HASH_TYPE_DELTA;
5648                 bp->max_tpa_v2 = le16_to_cpu(resp->max_aggs_supported);
5649                 if (bp->max_tpa_v2) {
5650                         if (BNXT_CHIP_P5_THOR(bp))
5651                                 bp->hw_ring_stats_size = BNXT_RING_STATS_SIZE_P5;
5652                         else
5653                                 bp->hw_ring_stats_size = BNXT_RING_STATS_SIZE_P5_SR2;
5654                 }
5655         }
5656         hwrm_req_drop(bp, req);
5657         return rc;
5658 }
5659
5660 static int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp)
5661 {
5662         struct hwrm_ring_grp_alloc_output *resp;
5663         struct hwrm_ring_grp_alloc_input *req;
5664         int rc;
5665         u16 i;
5666
5667         if (bp->flags & BNXT_FLAG_CHIP_P5)
5668                 return 0;
5669
5670         rc = hwrm_req_init(bp, req, HWRM_RING_GRP_ALLOC);
5671         if (rc)
5672                 return rc;
5673
5674         resp = hwrm_req_hold(bp, req);
5675         for (i = 0; i < bp->rx_nr_rings; i++) {
5676                 unsigned int grp_idx = bp->rx_ring[i].bnapi->index;
5677
5678                 req->cr = cpu_to_le16(bp->grp_info[grp_idx].cp_fw_ring_id);
5679                 req->rr = cpu_to_le16(bp->grp_info[grp_idx].rx_fw_ring_id);
5680                 req->ar = cpu_to_le16(bp->grp_info[grp_idx].agg_fw_ring_id);
5681                 req->sc = cpu_to_le16(bp->grp_info[grp_idx].fw_stats_ctx);
5682
5683                 rc = hwrm_req_send(bp, req);
5684
5685                 if (rc)
5686                         break;
5687
5688                 bp->grp_info[grp_idx].fw_grp_id =
5689                         le32_to_cpu(resp->ring_group_id);
5690         }
5691         hwrm_req_drop(bp, req);
5692         return rc;
5693 }
5694
5695 static void bnxt_hwrm_ring_grp_free(struct bnxt *bp)
5696 {
5697         struct hwrm_ring_grp_free_input *req;
5698         u16 i;
5699
5700         if (!bp->grp_info || (bp->flags & BNXT_FLAG_CHIP_P5))
5701                 return;
5702
5703         if (hwrm_req_init(bp, req, HWRM_RING_GRP_FREE))
5704                 return;
5705
5706         hwrm_req_hold(bp, req);
5707         for (i = 0; i < bp->cp_nr_rings; i++) {
5708                 if (bp->grp_info[i].fw_grp_id == INVALID_HW_RING_ID)
5709                         continue;
5710                 req->ring_group_id =
5711                         cpu_to_le32(bp->grp_info[i].fw_grp_id);
5712
5713                 hwrm_req_send(bp, req);
5714                 bp->grp_info[i].fw_grp_id = INVALID_HW_RING_ID;
5715         }
5716         hwrm_req_drop(bp, req);
5717 }
5718
5719 static int hwrm_ring_alloc_send_msg(struct bnxt *bp,
5720                                     struct bnxt_ring_struct *ring,
5721                                     u32 ring_type, u32 map_index)
5722 {
5723         struct hwrm_ring_alloc_output *resp;
5724         struct hwrm_ring_alloc_input *req;
5725         struct bnxt_ring_mem_info *rmem = &ring->ring_mem;
5726         struct bnxt_ring_grp_info *grp_info;
5727         int rc, err = 0;
5728         u16 ring_id;
5729
5730         rc = hwrm_req_init(bp, req, HWRM_RING_ALLOC);
5731         if (rc)
5732                 goto exit;
5733
5734         req->enables = 0;
5735         if (rmem->nr_pages > 1) {
5736                 req->page_tbl_addr = cpu_to_le64(rmem->pg_tbl_map);
5737                 /* Page size is in log2 units */
5738                 req->page_size = BNXT_PAGE_SHIFT;
5739                 req->page_tbl_depth = 1;
5740         } else {
5741                 req->page_tbl_addr =  cpu_to_le64(rmem->dma_arr[0]);
5742         }
5743         req->fbo = 0;
5744         /* Association of ring index with doorbell index and MSIX number */
5745         req->logical_id = cpu_to_le16(map_index);
5746
5747         switch (ring_type) {
5748         case HWRM_RING_ALLOC_TX: {
5749                 struct bnxt_tx_ring_info *txr;
5750
5751                 txr = container_of(ring, struct bnxt_tx_ring_info,
5752                                    tx_ring_struct);
5753                 req->ring_type = RING_ALLOC_REQ_RING_TYPE_TX;
5754                 /* Association of transmit ring with completion ring */
5755                 grp_info = &bp->grp_info[ring->grp_idx];
5756                 req->cmpl_ring_id = cpu_to_le16(bnxt_cp_ring_for_tx(bp, txr));
5757                 req->length = cpu_to_le32(bp->tx_ring_mask + 1);
5758                 req->stat_ctx_id = cpu_to_le32(grp_info->fw_stats_ctx);
5759                 req->queue_id = cpu_to_le16(ring->queue_id);
5760                 break;
5761         }
5762         case HWRM_RING_ALLOC_RX:
5763                 req->ring_type = RING_ALLOC_REQ_RING_TYPE_RX;
5764                 req->length = cpu_to_le32(bp->rx_ring_mask + 1);
5765                 if (bp->flags & BNXT_FLAG_CHIP_P5) {
5766                         u16 flags = 0;
5767
5768                         /* Association of rx ring with stats context */
5769                         grp_info = &bp->grp_info[ring->grp_idx];
5770                         req->rx_buf_size = cpu_to_le16(bp->rx_buf_use_size);
5771                         req->stat_ctx_id = cpu_to_le32(grp_info->fw_stats_ctx);
5772                         req->enables |= cpu_to_le32(
5773                                 RING_ALLOC_REQ_ENABLES_RX_BUF_SIZE_VALID);
5774                         if (NET_IP_ALIGN == 2)
5775                                 flags = RING_ALLOC_REQ_FLAGS_RX_SOP_PAD;
5776                         req->flags = cpu_to_le16(flags);
5777                 }
5778                 break;
5779         case HWRM_RING_ALLOC_AGG:
5780                 if (bp->flags & BNXT_FLAG_CHIP_P5) {
5781                         req->ring_type = RING_ALLOC_REQ_RING_TYPE_RX_AGG;
5782                         /* Association of agg ring with rx ring */
5783                         grp_info = &bp->grp_info[ring->grp_idx];
5784                         req->rx_ring_id = cpu_to_le16(grp_info->rx_fw_ring_id);
5785                         req->rx_buf_size = cpu_to_le16(BNXT_RX_PAGE_SIZE);
5786                         req->stat_ctx_id = cpu_to_le32(grp_info->fw_stats_ctx);
5787                         req->enables |= cpu_to_le32(
5788                                 RING_ALLOC_REQ_ENABLES_RX_RING_ID_VALID |
5789                                 RING_ALLOC_REQ_ENABLES_RX_BUF_SIZE_VALID);
5790                 } else {
5791                         req->ring_type = RING_ALLOC_REQ_RING_TYPE_RX;
5792                 }
5793                 req->length = cpu_to_le32(bp->rx_agg_ring_mask + 1);
5794                 break;
5795         case HWRM_RING_ALLOC_CMPL:
5796                 req->ring_type = RING_ALLOC_REQ_RING_TYPE_L2_CMPL;
5797                 req->length = cpu_to_le32(bp->cp_ring_mask + 1);
5798                 if (bp->flags & BNXT_FLAG_CHIP_P5) {
5799                         /* Association of cp ring with nq */
5800                         grp_info = &bp->grp_info[map_index];
5801                         req->nq_ring_id = cpu_to_le16(grp_info->cp_fw_ring_id);
5802                         req->cq_handle = cpu_to_le64(ring->handle);
5803                         req->enables |= cpu_to_le32(
5804                                 RING_ALLOC_REQ_ENABLES_NQ_RING_ID_VALID);
5805                 } else if (bp->flags & BNXT_FLAG_USING_MSIX) {
5806                         req->int_mode = RING_ALLOC_REQ_INT_MODE_MSIX;
5807                 }
5808                 break;
5809         case HWRM_RING_ALLOC_NQ:
5810                 req->ring_type = RING_ALLOC_REQ_RING_TYPE_NQ;
5811                 req->length = cpu_to_le32(bp->cp_ring_mask + 1);
5812                 if (bp->flags & BNXT_FLAG_USING_MSIX)
5813                         req->int_mode = RING_ALLOC_REQ_INT_MODE_MSIX;
5814                 break;
5815         default:
5816                 netdev_err(bp->dev, "hwrm alloc invalid ring type %d\n",
5817                            ring_type);
5818                 return -1;
5819         }
5820
5821         resp = hwrm_req_hold(bp, req);
5822         rc = hwrm_req_send(bp, req);
5823         err = le16_to_cpu(resp->error_code);
5824         ring_id = le16_to_cpu(resp->ring_id);
5825         hwrm_req_drop(bp, req);
5826
5827 exit:
5828         if (rc || err) {
5829                 netdev_err(bp->dev, "hwrm_ring_alloc type %d failed. rc:%x err:%x\n",
5830                            ring_type, rc, err);
5831                 return -EIO;
5832         }
5833         ring->fw_ring_id = ring_id;
5834         return rc;
5835 }
5836
5837 static int bnxt_hwrm_set_async_event_cr(struct bnxt *bp, int idx)
5838 {
5839         int rc;
5840
5841         if (BNXT_PF(bp)) {
5842                 struct hwrm_func_cfg_input *req;
5843
5844                 rc = hwrm_req_init(bp, req, HWRM_FUNC_CFG);
5845                 if (rc)
5846                         return rc;
5847
5848                 req->fid = cpu_to_le16(0xffff);
5849                 req->enables = cpu_to_le32(FUNC_CFG_REQ_ENABLES_ASYNC_EVENT_CR);
5850                 req->async_event_cr = cpu_to_le16(idx);
5851                 return hwrm_req_send(bp, req);
5852         } else {
5853                 struct hwrm_func_vf_cfg_input *req;
5854
5855                 rc = hwrm_req_init(bp, req, HWRM_FUNC_VF_CFG);
5856                 if (rc)
5857                         return rc;
5858
5859                 req->enables =
5860                         cpu_to_le32(FUNC_VF_CFG_REQ_ENABLES_ASYNC_EVENT_CR);
5861                 req->async_event_cr = cpu_to_le16(idx);
5862                 return hwrm_req_send(bp, req);
5863         }
5864 }
5865
5866 static void bnxt_set_db(struct bnxt *bp, struct bnxt_db_info *db, u32 ring_type,
5867                         u32 map_idx, u32 xid)
5868 {
5869         if (bp->flags & BNXT_FLAG_CHIP_P5) {
5870                 if (BNXT_PF(bp))
5871                         db->doorbell = bp->bar1 + DB_PF_OFFSET_P5;
5872                 else
5873                         db->doorbell = bp->bar1 + DB_VF_OFFSET_P5;
5874                 switch (ring_type) {
5875                 case HWRM_RING_ALLOC_TX:
5876                         db->db_key64 = DBR_PATH_L2 | DBR_TYPE_SQ;
5877                         break;
5878                 case HWRM_RING_ALLOC_RX:
5879                 case HWRM_RING_ALLOC_AGG:
5880                         db->db_key64 = DBR_PATH_L2 | DBR_TYPE_SRQ;
5881                         break;
5882                 case HWRM_RING_ALLOC_CMPL:
5883                         db->db_key64 = DBR_PATH_L2;
5884                         break;
5885                 case HWRM_RING_ALLOC_NQ:
5886                         db->db_key64 = DBR_PATH_L2;
5887                         break;
5888                 }
5889                 db->db_key64 |= (u64)xid << DBR_XID_SFT;
5890         } else {
5891                 db->doorbell = bp->bar1 + map_idx * 0x80;
5892                 switch (ring_type) {
5893                 case HWRM_RING_ALLOC_TX:
5894                         db->db_key32 = DB_KEY_TX;
5895                         break;
5896                 case HWRM_RING_ALLOC_RX:
5897                 case HWRM_RING_ALLOC_AGG:
5898                         db->db_key32 = DB_KEY_RX;
5899                         break;
5900                 case HWRM_RING_ALLOC_CMPL:
5901                         db->db_key32 = DB_KEY_CP;
5902                         break;
5903                 }
5904         }
5905 }
5906
5907 static int bnxt_hwrm_ring_alloc(struct bnxt *bp)
5908 {
5909         bool agg_rings = !!(bp->flags & BNXT_FLAG_AGG_RINGS);
5910         int i, rc = 0;
5911         u32 type;
5912
5913         if (bp->flags & BNXT_FLAG_CHIP_P5)
5914                 type = HWRM_RING_ALLOC_NQ;
5915         else
5916                 type = HWRM_RING_ALLOC_CMPL;
5917         for (i = 0; i < bp->cp_nr_rings; i++) {
5918                 struct bnxt_napi *bnapi = bp->bnapi[i];
5919                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
5920                 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct;
5921                 u32 map_idx = ring->map_idx;
5922                 unsigned int vector;
5923
5924                 vector = bp->irq_tbl[map_idx].vector;
5925                 disable_irq_nosync(vector);
5926                 rc = hwrm_ring_alloc_send_msg(bp, ring, type, map_idx);
5927                 if (rc) {
5928                         enable_irq(vector);
5929                         goto err_out;
5930                 }
5931                 bnxt_set_db(bp, &cpr->cp_db, type, map_idx, ring->fw_ring_id);
5932                 bnxt_db_nq(bp, &cpr->cp_db, cpr->cp_raw_cons);
5933                 enable_irq(vector);
5934                 bp->grp_info[i].cp_fw_ring_id = ring->fw_ring_id;
5935
5936                 if (!i) {
5937                         rc = bnxt_hwrm_set_async_event_cr(bp, ring->fw_ring_id);
5938                         if (rc)
5939                                 netdev_warn(bp->dev, "Failed to set async event completion ring.\n");
5940                 }
5941         }
5942
5943         type = HWRM_RING_ALLOC_TX;
5944         for (i = 0; i < bp->tx_nr_rings; i++) {
5945                 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
5946                 struct bnxt_ring_struct *ring;
5947                 u32 map_idx;
5948
5949                 if (bp->flags & BNXT_FLAG_CHIP_P5) {
5950                         struct bnxt_napi *bnapi = txr->bnapi;
5951                         struct bnxt_cp_ring_info *cpr, *cpr2;
5952                         u32 type2 = HWRM_RING_ALLOC_CMPL;
5953
5954                         cpr = &bnapi->cp_ring;
5955                         cpr2 = cpr->cp_ring_arr[BNXT_TX_HDL];
5956                         ring = &cpr2->cp_ring_struct;
5957                         ring->handle = BNXT_TX_HDL;
5958                         map_idx = bnapi->index;
5959                         rc = hwrm_ring_alloc_send_msg(bp, ring, type2, map_idx);
5960                         if (rc)
5961                                 goto err_out;
5962                         bnxt_set_db(bp, &cpr2->cp_db, type2, map_idx,
5963                                     ring->fw_ring_id);
5964                         bnxt_db_cq(bp, &cpr2->cp_db, cpr2->cp_raw_cons);
5965                 }
5966                 ring = &txr->tx_ring_struct;
5967                 map_idx = i;
5968                 rc = hwrm_ring_alloc_send_msg(bp, ring, type, map_idx);
5969                 if (rc)
5970                         goto err_out;
5971                 bnxt_set_db(bp, &txr->tx_db, type, map_idx, ring->fw_ring_id);
5972         }
5973
5974         type = HWRM_RING_ALLOC_RX;
5975         for (i = 0; i < bp->rx_nr_rings; i++) {
5976                 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
5977                 struct bnxt_ring_struct *ring = &rxr->rx_ring_struct;
5978                 struct bnxt_napi *bnapi = rxr->bnapi;
5979                 u32 map_idx = bnapi->index;
5980
5981                 rc = hwrm_ring_alloc_send_msg(bp, ring, type, map_idx);
5982                 if (rc)
5983                         goto err_out;
5984                 bnxt_set_db(bp, &rxr->rx_db, type, map_idx, ring->fw_ring_id);
5985                 /* If we have agg rings, post agg buffers first. */
5986                 if (!agg_rings)
5987                         bnxt_db_write(bp, &rxr->rx_db, rxr->rx_prod);
5988                 bp->grp_info[map_idx].rx_fw_ring_id = ring->fw_ring_id;
5989                 if (bp->flags & BNXT_FLAG_CHIP_P5) {
5990                         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
5991                         u32 type2 = HWRM_RING_ALLOC_CMPL;
5992                         struct bnxt_cp_ring_info *cpr2;
5993
5994                         cpr2 = cpr->cp_ring_arr[BNXT_RX_HDL];
5995                         ring = &cpr2->cp_ring_struct;
5996                         ring->handle = BNXT_RX_HDL;
5997                         rc = hwrm_ring_alloc_send_msg(bp, ring, type2, map_idx);
5998                         if (rc)
5999                                 goto err_out;
6000                         bnxt_set_db(bp, &cpr2->cp_db, type2, map_idx,
6001                                     ring->fw_ring_id);
6002                         bnxt_db_cq(bp, &cpr2->cp_db, cpr2->cp_raw_cons);
6003                 }
6004         }
6005
6006         if (agg_rings) {
6007                 type = HWRM_RING_ALLOC_AGG;
6008                 for (i = 0; i < bp->rx_nr_rings; i++) {
6009                         struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
6010                         struct bnxt_ring_struct *ring =
6011                                                 &rxr->rx_agg_ring_struct;
6012                         u32 grp_idx = ring->grp_idx;
6013                         u32 map_idx = grp_idx + bp->rx_nr_rings;
6014
6015                         rc = hwrm_ring_alloc_send_msg(bp, ring, type, map_idx);
6016                         if (rc)
6017                                 goto err_out;
6018
6019                         bnxt_set_db(bp, &rxr->rx_agg_db, type, map_idx,
6020                                     ring->fw_ring_id);
6021                         bnxt_db_write(bp, &rxr->rx_agg_db, rxr->rx_agg_prod);
6022                         bnxt_db_write(bp, &rxr->rx_db, rxr->rx_prod);
6023                         bp->grp_info[grp_idx].agg_fw_ring_id = ring->fw_ring_id;
6024                 }
6025         }
6026 err_out:
6027         return rc;
6028 }
6029
6030 static int hwrm_ring_free_send_msg(struct bnxt *bp,
6031                                    struct bnxt_ring_struct *ring,
6032                                    u32 ring_type, int cmpl_ring_id)
6033 {
6034         struct hwrm_ring_free_output *resp;
6035         struct hwrm_ring_free_input *req;
6036         u16 error_code = 0;
6037         int rc;
6038
6039         if (BNXT_NO_FW_ACCESS(bp))
6040                 return 0;
6041
6042         rc = hwrm_req_init(bp, req, HWRM_RING_FREE);
6043         if (rc)
6044                 goto exit;
6045
6046         req->cmpl_ring = cpu_to_le16(cmpl_ring_id);
6047         req->ring_type = ring_type;
6048         req->ring_id = cpu_to_le16(ring->fw_ring_id);
6049
6050         resp = hwrm_req_hold(bp, req);
6051         rc = hwrm_req_send(bp, req);
6052         error_code = le16_to_cpu(resp->error_code);
6053         hwrm_req_drop(bp, req);
6054 exit:
6055         if (rc || error_code) {
6056                 netdev_err(bp->dev, "hwrm_ring_free type %d failed. rc:%x err:%x\n",
6057                            ring_type, rc, error_code);
6058                 return -EIO;
6059         }
6060         return 0;
6061 }
6062
6063 static void bnxt_hwrm_ring_free(struct bnxt *bp, bool close_path)
6064 {
6065         u32 type;
6066         int i;
6067
6068         if (!bp->bnapi)
6069                 return;
6070
6071         for (i = 0; i < bp->tx_nr_rings; i++) {
6072                 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
6073                 struct bnxt_ring_struct *ring = &txr->tx_ring_struct;
6074
6075                 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
6076                         u32 cmpl_ring_id = bnxt_cp_ring_for_tx(bp, txr);
6077
6078                         hwrm_ring_free_send_msg(bp, ring,
6079                                                 RING_FREE_REQ_RING_TYPE_TX,
6080                                                 close_path ? cmpl_ring_id :
6081                                                 INVALID_HW_RING_ID);
6082                         ring->fw_ring_id = INVALID_HW_RING_ID;
6083                 }
6084         }
6085
6086         for (i = 0; i < bp->rx_nr_rings; i++) {
6087                 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
6088                 struct bnxt_ring_struct *ring = &rxr->rx_ring_struct;
6089                 u32 grp_idx = rxr->bnapi->index;
6090
6091                 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
6092                         u32 cmpl_ring_id = bnxt_cp_ring_for_rx(bp, rxr);
6093
6094                         hwrm_ring_free_send_msg(bp, ring,
6095                                                 RING_FREE_REQ_RING_TYPE_RX,
6096                                                 close_path ? cmpl_ring_id :
6097                                                 INVALID_HW_RING_ID);
6098                         ring->fw_ring_id = INVALID_HW_RING_ID;
6099                         bp->grp_info[grp_idx].rx_fw_ring_id =
6100                                 INVALID_HW_RING_ID;
6101                 }
6102         }
6103
6104         if (bp->flags & BNXT_FLAG_CHIP_P5)
6105                 type = RING_FREE_REQ_RING_TYPE_RX_AGG;
6106         else
6107                 type = RING_FREE_REQ_RING_TYPE_RX;
6108         for (i = 0; i < bp->rx_nr_rings; i++) {
6109                 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
6110                 struct bnxt_ring_struct *ring = &rxr->rx_agg_ring_struct;
6111                 u32 grp_idx = rxr->bnapi->index;
6112
6113                 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
6114                         u32 cmpl_ring_id = bnxt_cp_ring_for_rx(bp, rxr);
6115
6116                         hwrm_ring_free_send_msg(bp, ring, type,
6117                                                 close_path ? cmpl_ring_id :
6118                                                 INVALID_HW_RING_ID);
6119                         ring->fw_ring_id = INVALID_HW_RING_ID;
6120                         bp->grp_info[grp_idx].agg_fw_ring_id =
6121                                 INVALID_HW_RING_ID;
6122                 }
6123         }
6124
6125         /* The completion rings are about to be freed.  After that the
6126          * IRQ doorbell will not work anymore.  So we need to disable
6127          * IRQ here.
6128          */
6129         bnxt_disable_int_sync(bp);
6130
6131         if (bp->flags & BNXT_FLAG_CHIP_P5)
6132                 type = RING_FREE_REQ_RING_TYPE_NQ;
6133         else
6134                 type = RING_FREE_REQ_RING_TYPE_L2_CMPL;
6135         for (i = 0; i < bp->cp_nr_rings; i++) {
6136                 struct bnxt_napi *bnapi = bp->bnapi[i];
6137                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
6138                 struct bnxt_ring_struct *ring;
6139                 int j;
6140
6141                 for (j = 0; j < 2; j++) {
6142                         struct bnxt_cp_ring_info *cpr2 = cpr->cp_ring_arr[j];
6143
6144                         if (cpr2) {
6145                                 ring = &cpr2->cp_ring_struct;
6146                                 if (ring->fw_ring_id == INVALID_HW_RING_ID)
6147                                         continue;
6148                                 hwrm_ring_free_send_msg(bp, ring,
6149                                         RING_FREE_REQ_RING_TYPE_L2_CMPL,
6150                                         INVALID_HW_RING_ID);
6151                                 ring->fw_ring_id = INVALID_HW_RING_ID;
6152                         }
6153                 }
6154                 ring = &cpr->cp_ring_struct;
6155                 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
6156                         hwrm_ring_free_send_msg(bp, ring, type,
6157                                                 INVALID_HW_RING_ID);
6158                         ring->fw_ring_id = INVALID_HW_RING_ID;
6159                         bp->grp_info[i].cp_fw_ring_id = INVALID_HW_RING_ID;
6160                 }
6161         }
6162 }
6163
6164 static int bnxt_trim_rings(struct bnxt *bp, int *rx, int *tx, int max,
6165                            bool shared);
6166
6167 static int bnxt_hwrm_get_rings(struct bnxt *bp)
6168 {
6169         struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
6170         struct hwrm_func_qcfg_output *resp;
6171         struct hwrm_func_qcfg_input *req;
6172         int rc;
6173
6174         if (bp->hwrm_spec_code < 0x10601)
6175                 return 0;
6176
6177         rc = hwrm_req_init(bp, req, HWRM_FUNC_QCFG);
6178         if (rc)
6179                 return rc;
6180
6181         req->fid = cpu_to_le16(0xffff);
6182         resp = hwrm_req_hold(bp, req);
6183         rc = hwrm_req_send(bp, req);
6184         if (rc) {
6185                 hwrm_req_drop(bp, req);
6186                 return rc;
6187         }
6188
6189         hw_resc->resv_tx_rings = le16_to_cpu(resp->alloc_tx_rings);
6190         if (BNXT_NEW_RM(bp)) {
6191                 u16 cp, stats;
6192
6193                 hw_resc->resv_rx_rings = le16_to_cpu(resp->alloc_rx_rings);
6194                 hw_resc->resv_hw_ring_grps =
6195                         le32_to_cpu(resp->alloc_hw_ring_grps);
6196                 hw_resc->resv_vnics = le16_to_cpu(resp->alloc_vnics);
6197                 cp = le16_to_cpu(resp->alloc_cmpl_rings);
6198                 stats = le16_to_cpu(resp->alloc_stat_ctx);
6199                 hw_resc->resv_irqs = cp;
6200                 if (bp->flags & BNXT_FLAG_CHIP_P5) {
6201                         int rx = hw_resc->resv_rx_rings;
6202                         int tx = hw_resc->resv_tx_rings;
6203
6204                         if (bp->flags & BNXT_FLAG_AGG_RINGS)
6205                                 rx >>= 1;
6206                         if (cp < (rx + tx)) {
6207                                 bnxt_trim_rings(bp, &rx, &tx, cp, false);
6208                                 if (bp->flags & BNXT_FLAG_AGG_RINGS)
6209                                         rx <<= 1;
6210                                 hw_resc->resv_rx_rings = rx;
6211                                 hw_resc->resv_tx_rings = tx;
6212                         }
6213                         hw_resc->resv_irqs = le16_to_cpu(resp->alloc_msix);
6214                         hw_resc->resv_hw_ring_grps = rx;
6215                 }
6216                 hw_resc->resv_cp_rings = cp;
6217                 hw_resc->resv_stat_ctxs = stats;
6218         }
6219         hwrm_req_drop(bp, req);
6220         return 0;
6221 }
6222
6223 int __bnxt_hwrm_get_tx_rings(struct bnxt *bp, u16 fid, int *tx_rings)
6224 {
6225         struct hwrm_func_qcfg_output *resp;
6226         struct hwrm_func_qcfg_input *req;
6227         int rc;
6228
6229         if (bp->hwrm_spec_code < 0x10601)
6230                 return 0;
6231
6232         rc = hwrm_req_init(bp, req, HWRM_FUNC_QCFG);
6233         if (rc)
6234                 return rc;
6235
6236         req->fid = cpu_to_le16(fid);
6237         resp = hwrm_req_hold(bp, req);
6238         rc = hwrm_req_send(bp, req);
6239         if (!rc)
6240                 *tx_rings = le16_to_cpu(resp->alloc_tx_rings);
6241
6242         hwrm_req_drop(bp, req);
6243         return rc;
6244 }
6245
6246 static bool bnxt_rfs_supported(struct bnxt *bp);
6247
6248 static struct hwrm_func_cfg_input *
6249 __bnxt_hwrm_reserve_pf_rings(struct bnxt *bp, int tx_rings, int rx_rings,
6250                              int ring_grps, int cp_rings, int stats, int vnics)
6251 {
6252         struct hwrm_func_cfg_input *req;
6253         u32 enables = 0;
6254
6255         if (hwrm_req_init(bp, req, HWRM_FUNC_CFG))
6256                 return NULL;
6257
6258         req->fid = cpu_to_le16(0xffff);
6259         enables |= tx_rings ? FUNC_CFG_REQ_ENABLES_NUM_TX_RINGS : 0;
6260         req->num_tx_rings = cpu_to_le16(tx_rings);
6261         if (BNXT_NEW_RM(bp)) {
6262                 enables |= rx_rings ? FUNC_CFG_REQ_ENABLES_NUM_RX_RINGS : 0;
6263                 enables |= stats ? FUNC_CFG_REQ_ENABLES_NUM_STAT_CTXS : 0;
6264                 if (bp->flags & BNXT_FLAG_CHIP_P5) {
6265                         enables |= cp_rings ? FUNC_CFG_REQ_ENABLES_NUM_MSIX : 0;
6266                         enables |= tx_rings + ring_grps ?
6267                                    FUNC_CFG_REQ_ENABLES_NUM_CMPL_RINGS : 0;
6268                         enables |= rx_rings ?
6269                                 FUNC_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS : 0;
6270                 } else {
6271                         enables |= cp_rings ?
6272                                    FUNC_CFG_REQ_ENABLES_NUM_CMPL_RINGS : 0;
6273                         enables |= ring_grps ?
6274                                    FUNC_CFG_REQ_ENABLES_NUM_HW_RING_GRPS |
6275                                    FUNC_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS : 0;
6276                 }
6277                 enables |= vnics ? FUNC_CFG_REQ_ENABLES_NUM_VNICS : 0;
6278
6279                 req->num_rx_rings = cpu_to_le16(rx_rings);
6280                 if (bp->flags & BNXT_FLAG_CHIP_P5) {
6281                         req->num_cmpl_rings = cpu_to_le16(tx_rings + ring_grps);
6282                         req->num_msix = cpu_to_le16(cp_rings);
6283                         req->num_rsscos_ctxs =
6284                                 cpu_to_le16(DIV_ROUND_UP(ring_grps, 64));
6285                 } else {
6286                         req->num_cmpl_rings = cpu_to_le16(cp_rings);
6287                         req->num_hw_ring_grps = cpu_to_le16(ring_grps);
6288                         req->num_rsscos_ctxs = cpu_to_le16(1);
6289                         if (!(bp->flags & BNXT_FLAG_NEW_RSS_CAP) &&
6290                             bnxt_rfs_supported(bp))
6291                                 req->num_rsscos_ctxs =
6292                                         cpu_to_le16(ring_grps + 1);
6293                 }
6294                 req->num_stat_ctxs = cpu_to_le16(stats);
6295                 req->num_vnics = cpu_to_le16(vnics);
6296         }
6297         req->enables = cpu_to_le32(enables);
6298         return req;
6299 }
6300
6301 static struct hwrm_func_vf_cfg_input *
6302 __bnxt_hwrm_reserve_vf_rings(struct bnxt *bp, int tx_rings, int rx_rings,
6303                              int ring_grps, int cp_rings, int stats, int vnics)
6304 {
6305         struct hwrm_func_vf_cfg_input *req;
6306         u32 enables = 0;
6307
6308         if (hwrm_req_init(bp, req, HWRM_FUNC_VF_CFG))
6309                 return NULL;
6310
6311         enables |= tx_rings ? FUNC_VF_CFG_REQ_ENABLES_NUM_TX_RINGS : 0;
6312         enables |= rx_rings ? FUNC_VF_CFG_REQ_ENABLES_NUM_RX_RINGS |
6313                               FUNC_VF_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS : 0;
6314         enables |= stats ? FUNC_VF_CFG_REQ_ENABLES_NUM_STAT_CTXS : 0;
6315         if (bp->flags & BNXT_FLAG_CHIP_P5) {
6316                 enables |= tx_rings + ring_grps ?
6317                            FUNC_VF_CFG_REQ_ENABLES_NUM_CMPL_RINGS : 0;
6318         } else {
6319                 enables |= cp_rings ?
6320                            FUNC_VF_CFG_REQ_ENABLES_NUM_CMPL_RINGS : 0;
6321                 enables |= ring_grps ?
6322                            FUNC_VF_CFG_REQ_ENABLES_NUM_HW_RING_GRPS : 0;
6323         }
6324         enables |= vnics ? FUNC_VF_CFG_REQ_ENABLES_NUM_VNICS : 0;
6325         enables |= FUNC_VF_CFG_REQ_ENABLES_NUM_L2_CTXS;
6326
6327         req->num_l2_ctxs = cpu_to_le16(BNXT_VF_MAX_L2_CTX);
6328         req->num_tx_rings = cpu_to_le16(tx_rings);
6329         req->num_rx_rings = cpu_to_le16(rx_rings);
6330         if (bp->flags & BNXT_FLAG_CHIP_P5) {
6331                 req->num_cmpl_rings = cpu_to_le16(tx_rings + ring_grps);
6332                 req->num_rsscos_ctxs = cpu_to_le16(DIV_ROUND_UP(ring_grps, 64));
6333         } else {
6334                 req->num_cmpl_rings = cpu_to_le16(cp_rings);
6335                 req->num_hw_ring_grps = cpu_to_le16(ring_grps);
6336                 req->num_rsscos_ctxs = cpu_to_le16(BNXT_VF_MAX_RSS_CTX);
6337         }
6338         req->num_stat_ctxs = cpu_to_le16(stats);
6339         req->num_vnics = cpu_to_le16(vnics);
6340
6341         req->enables = cpu_to_le32(enables);
6342         return req;
6343 }
6344
6345 static int
6346 bnxt_hwrm_reserve_pf_rings(struct bnxt *bp, int tx_rings, int rx_rings,
6347                            int ring_grps, int cp_rings, int stats, int vnics)
6348 {
6349         struct hwrm_func_cfg_input *req;
6350         int rc;
6351
6352         req = __bnxt_hwrm_reserve_pf_rings(bp, tx_rings, rx_rings, ring_grps,
6353                                            cp_rings, stats, vnics);
6354         if (!req)
6355                 return -ENOMEM;
6356
6357         if (!req->enables) {
6358                 hwrm_req_drop(bp, req);
6359                 return 0;
6360         }
6361
6362         rc = hwrm_req_send(bp, req);
6363         if (rc)
6364                 return rc;
6365
6366         if (bp->hwrm_spec_code < 0x10601)
6367                 bp->hw_resc.resv_tx_rings = tx_rings;
6368
6369         return bnxt_hwrm_get_rings(bp);
6370 }
6371
6372 static int
6373 bnxt_hwrm_reserve_vf_rings(struct bnxt *bp, int tx_rings, int rx_rings,
6374                            int ring_grps, int cp_rings, int stats, int vnics)
6375 {
6376         struct hwrm_func_vf_cfg_input *req;
6377         int rc;
6378
6379         if (!BNXT_NEW_RM(bp)) {
6380                 bp->hw_resc.resv_tx_rings = tx_rings;
6381                 return 0;
6382         }
6383
6384         req = __bnxt_hwrm_reserve_vf_rings(bp, tx_rings, rx_rings, ring_grps,
6385                                            cp_rings, stats, vnics);
6386         if (!req)
6387                 return -ENOMEM;
6388
6389         rc = hwrm_req_send(bp, req);
6390         if (rc)
6391                 return rc;
6392
6393         return bnxt_hwrm_get_rings(bp);
6394 }
6395
6396 static int bnxt_hwrm_reserve_rings(struct bnxt *bp, int tx, int rx, int grp,
6397                                    int cp, int stat, int vnic)
6398 {
6399         if (BNXT_PF(bp))
6400                 return bnxt_hwrm_reserve_pf_rings(bp, tx, rx, grp, cp, stat,
6401                                                   vnic);
6402         else
6403                 return bnxt_hwrm_reserve_vf_rings(bp, tx, rx, grp, cp, stat,
6404                                                   vnic);
6405 }
6406
6407 int bnxt_nq_rings_in_use(struct bnxt *bp)
6408 {
6409         int cp = bp->cp_nr_rings;
6410         int ulp_msix, ulp_base;
6411
6412         ulp_msix = bnxt_get_ulp_msix_num(bp);
6413         if (ulp_msix) {
6414                 ulp_base = bnxt_get_ulp_msix_base(bp);
6415                 cp += ulp_msix;
6416                 if ((ulp_base + ulp_msix) > cp)
6417                         cp = ulp_base + ulp_msix;
6418         }
6419         return cp;
6420 }
6421
6422 static int bnxt_cp_rings_in_use(struct bnxt *bp)
6423 {
6424         int cp;
6425
6426         if (!(bp->flags & BNXT_FLAG_CHIP_P5))
6427                 return bnxt_nq_rings_in_use(bp);
6428
6429         cp = bp->tx_nr_rings + bp->rx_nr_rings;
6430         return cp;
6431 }
6432
6433 static int bnxt_get_func_stat_ctxs(struct bnxt *bp)
6434 {
6435         int ulp_stat = bnxt_get_ulp_stat_ctxs(bp);
6436         int cp = bp->cp_nr_rings;
6437
6438         if (!ulp_stat)
6439                 return cp;
6440
6441         if (bnxt_nq_rings_in_use(bp) > cp + bnxt_get_ulp_msix_num(bp))
6442                 return bnxt_get_ulp_msix_base(bp) + ulp_stat;
6443
6444         return cp + ulp_stat;
6445 }
6446
6447 /* Check if a default RSS map needs to be setup.  This function is only
6448  * used on older firmware that does not require reserving RX rings.
6449  */
6450 static void bnxt_check_rss_tbl_no_rmgr(struct bnxt *bp)
6451 {
6452         struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
6453
6454         /* The RSS map is valid for RX rings set to resv_rx_rings */
6455         if (hw_resc->resv_rx_rings != bp->rx_nr_rings) {
6456                 hw_resc->resv_rx_rings = bp->rx_nr_rings;
6457                 if (!netif_is_rxfh_configured(bp->dev))
6458                         bnxt_set_dflt_rss_indir_tbl(bp);
6459         }
6460 }
6461
6462 static bool bnxt_need_reserve_rings(struct bnxt *bp)
6463 {
6464         struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
6465         int cp = bnxt_cp_rings_in_use(bp);
6466         int nq = bnxt_nq_rings_in_use(bp);
6467         int rx = bp->rx_nr_rings, stat;
6468         int vnic = 1, grp = rx;
6469
6470         if (hw_resc->resv_tx_rings != bp->tx_nr_rings &&
6471             bp->hwrm_spec_code >= 0x10601)
6472                 return true;
6473
6474         /* Old firmware does not need RX ring reservations but we still
6475          * need to setup a default RSS map when needed.  With new firmware
6476          * we go through RX ring reservations first and then set up the
6477          * RSS map for the successfully reserved RX rings when needed.
6478          */
6479         if (!BNXT_NEW_RM(bp)) {
6480                 bnxt_check_rss_tbl_no_rmgr(bp);
6481                 return false;
6482         }
6483         if ((bp->flags & BNXT_FLAG_RFS) && !(bp->flags & BNXT_FLAG_CHIP_P5))
6484                 vnic = rx + 1;
6485         if (bp->flags & BNXT_FLAG_AGG_RINGS)
6486                 rx <<= 1;
6487         stat = bnxt_get_func_stat_ctxs(bp);
6488         if (hw_resc->resv_rx_rings != rx || hw_resc->resv_cp_rings != cp ||
6489             hw_resc->resv_vnics != vnic || hw_resc->resv_stat_ctxs != stat ||
6490             (hw_resc->resv_hw_ring_grps != grp &&
6491              !(bp->flags & BNXT_FLAG_CHIP_P5)))
6492                 return true;
6493         if ((bp->flags & BNXT_FLAG_CHIP_P5) && BNXT_PF(bp) &&
6494             hw_resc->resv_irqs != nq)
6495                 return true;
6496         return false;
6497 }
6498
6499 static int __bnxt_reserve_rings(struct bnxt *bp)
6500 {
6501         struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
6502         int cp = bnxt_nq_rings_in_use(bp);
6503         int tx = bp->tx_nr_rings;
6504         int rx = bp->rx_nr_rings;
6505         int grp, rx_rings, rc;
6506         int vnic = 1, stat;
6507         bool sh = false;
6508
6509         if (!bnxt_need_reserve_rings(bp))
6510                 return 0;
6511
6512         if (bp->flags & BNXT_FLAG_SHARED_RINGS)
6513                 sh = true;
6514         if ((bp->flags & BNXT_FLAG_RFS) && !(bp->flags & BNXT_FLAG_CHIP_P5))
6515                 vnic = rx + 1;
6516         if (bp->flags & BNXT_FLAG_AGG_RINGS)
6517                 rx <<= 1;
6518         grp = bp->rx_nr_rings;
6519         stat = bnxt_get_func_stat_ctxs(bp);
6520
6521         rc = bnxt_hwrm_reserve_rings(bp, tx, rx, grp, cp, stat, vnic);
6522         if (rc)
6523                 return rc;
6524
6525         tx = hw_resc->resv_tx_rings;
6526         if (BNXT_NEW_RM(bp)) {
6527                 rx = hw_resc->resv_rx_rings;
6528                 cp = hw_resc->resv_irqs;
6529                 grp = hw_resc->resv_hw_ring_grps;
6530                 vnic = hw_resc->resv_vnics;
6531                 stat = hw_resc->resv_stat_ctxs;
6532         }
6533
6534         rx_rings = rx;
6535         if (bp->flags & BNXT_FLAG_AGG_RINGS) {
6536                 if (rx >= 2) {
6537                         rx_rings = rx >> 1;
6538                 } else {
6539                         if (netif_running(bp->dev))
6540                                 return -ENOMEM;
6541
6542                         bp->flags &= ~BNXT_FLAG_AGG_RINGS;
6543                         bp->flags |= BNXT_FLAG_NO_AGG_RINGS;
6544                         bp->dev->hw_features &= ~NETIF_F_LRO;
6545                         bp->dev->features &= ~NETIF_F_LRO;
6546                         bnxt_set_ring_params(bp);
6547                 }
6548         }
6549         rx_rings = min_t(int, rx_rings, grp);
6550         cp = min_t(int, cp, bp->cp_nr_rings);
6551         if (stat > bnxt_get_ulp_stat_ctxs(bp))
6552                 stat -= bnxt_get_ulp_stat_ctxs(bp);
6553         cp = min_t(int, cp, stat);
6554         rc = bnxt_trim_rings(bp, &rx_rings, &tx, cp, sh);
6555         if (bp->flags & BNXT_FLAG_AGG_RINGS)
6556                 rx = rx_rings << 1;
6557         cp = sh ? max_t(int, tx, rx_rings) : tx + rx_rings;
6558         bp->tx_nr_rings = tx;
6559
6560         /* If we cannot reserve all the RX rings, reset the RSS map only
6561          * if absolutely necessary
6562          */
6563         if (rx_rings != bp->rx_nr_rings) {
6564                 netdev_warn(bp->dev, "Able to reserve only %d out of %d requested RX rings\n",
6565                             rx_rings, bp->rx_nr_rings);
6566                 if (netif_is_rxfh_configured(bp->dev) &&
6567                     (bnxt_get_nr_rss_ctxs(bp, bp->rx_nr_rings) !=
6568                      bnxt_get_nr_rss_ctxs(bp, rx_rings) ||
6569                      bnxt_get_max_rss_ring(bp) >= rx_rings)) {
6570                         netdev_warn(bp->dev, "RSS table entries reverting to default\n");
6571                         bp->dev->priv_flags &= ~IFF_RXFH_CONFIGURED;
6572                 }
6573         }
6574         bp->rx_nr_rings = rx_rings;
6575         bp->cp_nr_rings = cp;
6576
6577         if (!tx || !rx || !cp || !grp || !vnic || !stat)
6578                 return -ENOMEM;
6579
6580         if (!netif_is_rxfh_configured(bp->dev))
6581                 bnxt_set_dflt_rss_indir_tbl(bp);
6582
6583         return rc;
6584 }
6585
6586 static int bnxt_hwrm_check_vf_rings(struct bnxt *bp, int tx_rings, int rx_rings,
6587                                     int ring_grps, int cp_rings, int stats,
6588                                     int vnics)
6589 {
6590         struct hwrm_func_vf_cfg_input *req;
6591         u32 flags;
6592
6593         if (!BNXT_NEW_RM(bp))
6594                 return 0;
6595
6596         req = __bnxt_hwrm_reserve_vf_rings(bp, tx_rings, rx_rings, ring_grps,
6597                                            cp_rings, stats, vnics);
6598         flags = FUNC_VF_CFG_REQ_FLAGS_TX_ASSETS_TEST |
6599                 FUNC_VF_CFG_REQ_FLAGS_RX_ASSETS_TEST |
6600                 FUNC_VF_CFG_REQ_FLAGS_CMPL_ASSETS_TEST |
6601                 FUNC_VF_CFG_REQ_FLAGS_STAT_CTX_ASSETS_TEST |
6602                 FUNC_VF_CFG_REQ_FLAGS_VNIC_ASSETS_TEST |
6603                 FUNC_VF_CFG_REQ_FLAGS_RSSCOS_CTX_ASSETS_TEST;
6604         if (!(bp->flags & BNXT_FLAG_CHIP_P5))
6605                 flags |= FUNC_VF_CFG_REQ_FLAGS_RING_GRP_ASSETS_TEST;
6606
6607         req->flags = cpu_to_le32(flags);
6608         return hwrm_req_send_silent(bp, req);
6609 }
6610
6611 static int bnxt_hwrm_check_pf_rings(struct bnxt *bp, int tx_rings, int rx_rings,
6612                                     int ring_grps, int cp_rings, int stats,
6613                                     int vnics)
6614 {
6615         struct hwrm_func_cfg_input *req;
6616         u32 flags;
6617
6618         req = __bnxt_hwrm_reserve_pf_rings(bp, tx_rings, rx_rings, ring_grps,
6619                                            cp_rings, stats, vnics);
6620         flags = FUNC_CFG_REQ_FLAGS_TX_ASSETS_TEST;
6621         if (BNXT_NEW_RM(bp)) {
6622                 flags |= FUNC_CFG_REQ_FLAGS_RX_ASSETS_TEST |
6623                          FUNC_CFG_REQ_FLAGS_CMPL_ASSETS_TEST |
6624                          FUNC_CFG_REQ_FLAGS_STAT_CTX_ASSETS_TEST |
6625                          FUNC_CFG_REQ_FLAGS_VNIC_ASSETS_TEST;
6626                 if (bp->flags & BNXT_FLAG_CHIP_P5)
6627                         flags |= FUNC_CFG_REQ_FLAGS_RSSCOS_CTX_ASSETS_TEST |
6628                                  FUNC_CFG_REQ_FLAGS_NQ_ASSETS_TEST;
6629                 else
6630                         flags |= FUNC_CFG_REQ_FLAGS_RING_GRP_ASSETS_TEST;
6631         }
6632
6633         req->flags = cpu_to_le32(flags);
6634         return hwrm_req_send_silent(bp, req);
6635 }
6636
6637 static int bnxt_hwrm_check_rings(struct bnxt *bp, int tx_rings, int rx_rings,
6638                                  int ring_grps, int cp_rings, int stats,
6639                                  int vnics)
6640 {
6641         if (bp->hwrm_spec_code < 0x10801)
6642                 return 0;
6643
6644         if (BNXT_PF(bp))
6645                 return bnxt_hwrm_check_pf_rings(bp, tx_rings, rx_rings,
6646                                                 ring_grps, cp_rings, stats,
6647                                                 vnics);
6648
6649         return bnxt_hwrm_check_vf_rings(bp, tx_rings, rx_rings, ring_grps,
6650                                         cp_rings, stats, vnics);
6651 }
6652
6653 static void bnxt_hwrm_coal_params_qcaps(struct bnxt *bp)
6654 {
6655         struct bnxt_coal_cap *coal_cap = &bp->coal_cap;
6656         struct hwrm_ring_aggint_qcaps_output *resp;
6657         struct hwrm_ring_aggint_qcaps_input *req;
6658         int rc;
6659
6660         coal_cap->cmpl_params = BNXT_LEGACY_COAL_CMPL_PARAMS;
6661         coal_cap->num_cmpl_dma_aggr_max = 63;
6662         coal_cap->num_cmpl_dma_aggr_during_int_max = 63;
6663         coal_cap->cmpl_aggr_dma_tmr_max = 65535;
6664         coal_cap->cmpl_aggr_dma_tmr_during_int_max = 65535;
6665         coal_cap->int_lat_tmr_min_max = 65535;
6666         coal_cap->int_lat_tmr_max_max = 65535;
6667         coal_cap->num_cmpl_aggr_int_max = 65535;
6668         coal_cap->timer_units = 80;
6669
6670         if (bp->hwrm_spec_code < 0x10902)
6671                 return;
6672
6673         if (hwrm_req_init(bp, req, HWRM_RING_AGGINT_QCAPS))
6674                 return;
6675
6676         resp = hwrm_req_hold(bp, req);
6677         rc = hwrm_req_send_silent(bp, req);
6678         if (!rc) {
6679                 coal_cap->cmpl_params = le32_to_cpu(resp->cmpl_params);
6680                 coal_cap->nq_params = le32_to_cpu(resp->nq_params);
6681                 coal_cap->num_cmpl_dma_aggr_max =
6682                         le16_to_cpu(resp->num_cmpl_dma_aggr_max);
6683                 coal_cap->num_cmpl_dma_aggr_during_int_max =
6684                         le16_to_cpu(resp->num_cmpl_dma_aggr_during_int_max);
6685                 coal_cap->cmpl_aggr_dma_tmr_max =
6686                         le16_to_cpu(resp->cmpl_aggr_dma_tmr_max);
6687                 coal_cap->cmpl_aggr_dma_tmr_during_int_max =
6688                         le16_to_cpu(resp->cmpl_aggr_dma_tmr_during_int_max);
6689                 coal_cap->int_lat_tmr_min_max =
6690                         le16_to_cpu(resp->int_lat_tmr_min_max);
6691                 coal_cap->int_lat_tmr_max_max =
6692                         le16_to_cpu(resp->int_lat_tmr_max_max);
6693                 coal_cap->num_cmpl_aggr_int_max =
6694                         le16_to_cpu(resp->num_cmpl_aggr_int_max);
6695                 coal_cap->timer_units = le16_to_cpu(resp->timer_units);
6696         }
6697         hwrm_req_drop(bp, req);
6698 }
6699
6700 static u16 bnxt_usec_to_coal_tmr(struct bnxt *bp, u16 usec)
6701 {
6702         struct bnxt_coal_cap *coal_cap = &bp->coal_cap;
6703
6704         return usec * 1000 / coal_cap->timer_units;
6705 }
6706
6707 static void bnxt_hwrm_set_coal_params(struct bnxt *bp,
6708         struct bnxt_coal *hw_coal,
6709         struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *req)
6710 {
6711         struct bnxt_coal_cap *coal_cap = &bp->coal_cap;
6712         u16 val, tmr, max, flags = hw_coal->flags;
6713         u32 cmpl_params = coal_cap->cmpl_params;
6714
6715         max = hw_coal->bufs_per_record * 128;
6716         if (hw_coal->budget)
6717                 max = hw_coal->bufs_per_record * hw_coal->budget;
6718         max = min_t(u16, max, coal_cap->num_cmpl_aggr_int_max);
6719
6720         val = clamp_t(u16, hw_coal->coal_bufs, 1, max);
6721         req->num_cmpl_aggr_int = cpu_to_le16(val);
6722
6723         val = min_t(u16, val, coal_cap->num_cmpl_dma_aggr_max);
6724         req->num_cmpl_dma_aggr = cpu_to_le16(val);
6725
6726         val = clamp_t(u16, hw_coal->coal_bufs_irq, 1,
6727                       coal_cap->num_cmpl_dma_aggr_during_int_max);
6728         req->num_cmpl_dma_aggr_during_int = cpu_to_le16(val);
6729
6730         tmr = bnxt_usec_to_coal_tmr(bp, hw_coal->coal_ticks);
6731         tmr = clamp_t(u16, tmr, 1, coal_cap->int_lat_tmr_max_max);
6732         req->int_lat_tmr_max = cpu_to_le16(tmr);
6733
6734         /* min timer set to 1/2 of interrupt timer */
6735         if (cmpl_params & RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_INT_LAT_TMR_MIN) {
6736                 val = tmr / 2;
6737                 val = clamp_t(u16, val, 1, coal_cap->int_lat_tmr_min_max);
6738                 req->int_lat_tmr_min = cpu_to_le16(val);
6739                 req->enables |= cpu_to_le16(BNXT_COAL_CMPL_MIN_TMR_ENABLE);
6740         }
6741
6742         /* buf timer set to 1/4 of interrupt timer */
6743         val = clamp_t(u16, tmr / 4, 1, coal_cap->cmpl_aggr_dma_tmr_max);
6744         req->cmpl_aggr_dma_tmr = cpu_to_le16(val);
6745
6746         if (cmpl_params &
6747             RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_DMA_AGGR_DURING_INT) {
6748                 tmr = bnxt_usec_to_coal_tmr(bp, hw_coal->coal_ticks_irq);
6749                 val = clamp_t(u16, tmr, 1,
6750                               coal_cap->cmpl_aggr_dma_tmr_during_int_max);
6751                 req->cmpl_aggr_dma_tmr_during_int = cpu_to_le16(val);
6752                 req->enables |=
6753                         cpu_to_le16(BNXT_COAL_CMPL_AGGR_TMR_DURING_INT_ENABLE);
6754         }
6755
6756         if ((cmpl_params & RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_RING_IDLE) &&
6757             hw_coal->idle_thresh && hw_coal->coal_ticks < hw_coal->idle_thresh)
6758                 flags |= RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_RING_IDLE;
6759         req->flags = cpu_to_le16(flags);
6760         req->enables |= cpu_to_le16(BNXT_COAL_CMPL_ENABLES);
6761 }
6762
6763 static int __bnxt_hwrm_set_coal_nq(struct bnxt *bp, struct bnxt_napi *bnapi,
6764                                    struct bnxt_coal *hw_coal)
6765 {
6766         struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *req;
6767         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
6768         struct bnxt_coal_cap *coal_cap = &bp->coal_cap;
6769         u32 nq_params = coal_cap->nq_params;
6770         u16 tmr;
6771         int rc;
6772
6773         if (!(nq_params & RING_AGGINT_QCAPS_RESP_NQ_PARAMS_INT_LAT_TMR_MIN))
6774                 return 0;
6775
6776         rc = hwrm_req_init(bp, req, HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS);
6777         if (rc)
6778                 return rc;
6779
6780         req->ring_id = cpu_to_le16(cpr->cp_ring_struct.fw_ring_id);
6781         req->flags =
6782                 cpu_to_le16(RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_IS_NQ);
6783
6784         tmr = bnxt_usec_to_coal_tmr(bp, hw_coal->coal_ticks) / 2;
6785         tmr = clamp_t(u16, tmr, 1, coal_cap->int_lat_tmr_min_max);
6786         req->int_lat_tmr_min = cpu_to_le16(tmr);
6787         req->enables |= cpu_to_le16(BNXT_COAL_CMPL_MIN_TMR_ENABLE);
6788         return hwrm_req_send(bp, req);
6789 }
6790
6791 int bnxt_hwrm_set_ring_coal(struct bnxt *bp, struct bnxt_napi *bnapi)
6792 {
6793         struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *req_rx;
6794         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
6795         struct bnxt_coal coal;
6796         int rc;
6797
6798         /* Tick values in micro seconds.
6799          * 1 coal_buf x bufs_per_record = 1 completion record.
6800          */
6801         memcpy(&coal, &bp->rx_coal, sizeof(struct bnxt_coal));
6802
6803         coal.coal_ticks = cpr->rx_ring_coal.coal_ticks;
6804         coal.coal_bufs = cpr->rx_ring_coal.coal_bufs;
6805
6806         if (!bnapi->rx_ring)
6807                 return -ENODEV;
6808
6809         rc = hwrm_req_init(bp, req_rx, HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS);
6810         if (rc)
6811                 return rc;
6812
6813         bnxt_hwrm_set_coal_params(bp, &coal, req_rx);
6814
6815         req_rx->ring_id = cpu_to_le16(bnxt_cp_ring_for_rx(bp, bnapi->rx_ring));
6816
6817         return hwrm_req_send(bp, req_rx);
6818 }
6819
6820 int bnxt_hwrm_set_coal(struct bnxt *bp)
6821 {
6822         struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *req_rx, *req_tx,
6823                                                            *req;
6824         int i, rc;
6825
6826         rc = hwrm_req_init(bp, req_rx, HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS);
6827         if (rc)
6828                 return rc;
6829
6830         rc = hwrm_req_init(bp, req_tx, HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS);
6831         if (rc) {
6832                 hwrm_req_drop(bp, req_rx);
6833                 return rc;
6834         }
6835
6836         bnxt_hwrm_set_coal_params(bp, &bp->rx_coal, req_rx);
6837         bnxt_hwrm_set_coal_params(bp, &bp->tx_coal, req_tx);
6838
6839         hwrm_req_hold(bp, req_rx);
6840         hwrm_req_hold(bp, req_tx);
6841         for (i = 0; i < bp->cp_nr_rings; i++) {
6842                 struct bnxt_napi *bnapi = bp->bnapi[i];
6843                 struct bnxt_coal *hw_coal;
6844                 u16 ring_id;
6845
6846                 req = req_rx;
6847                 if (!bnapi->rx_ring) {
6848                         ring_id = bnxt_cp_ring_for_tx(bp, bnapi->tx_ring);
6849                         req = req_tx;
6850                 } else {
6851                         ring_id = bnxt_cp_ring_for_rx(bp, bnapi->rx_ring);
6852                 }
6853                 req->ring_id = cpu_to_le16(ring_id);
6854
6855                 rc = hwrm_req_send(bp, req);
6856                 if (rc)
6857                         break;
6858
6859                 if (!(bp->flags & BNXT_FLAG_CHIP_P5))
6860                         continue;
6861
6862                 if (bnapi->rx_ring && bnapi->tx_ring) {
6863                         req = req_tx;
6864                         ring_id = bnxt_cp_ring_for_tx(bp, bnapi->tx_ring);
6865                         req->ring_id = cpu_to_le16(ring_id);
6866                         rc = hwrm_req_send(bp, req);
6867                         if (rc)
6868                                 break;
6869                 }
6870                 if (bnapi->rx_ring)
6871                         hw_coal = &bp->rx_coal;
6872                 else
6873                         hw_coal = &bp->tx_coal;
6874                 __bnxt_hwrm_set_coal_nq(bp, bnapi, hw_coal);
6875         }
6876         hwrm_req_drop(bp, req_rx);
6877         hwrm_req_drop(bp, req_tx);
6878         return rc;
6879 }
6880
6881 static void bnxt_hwrm_stat_ctx_free(struct bnxt *bp)
6882 {
6883         struct hwrm_stat_ctx_clr_stats_input *req0 = NULL;
6884         struct hwrm_stat_ctx_free_input *req;
6885         int i;
6886
6887         if (!bp->bnapi)
6888                 return;
6889
6890         if (BNXT_CHIP_TYPE_NITRO_A0(bp))
6891                 return;
6892
6893         if (hwrm_req_init(bp, req, HWRM_STAT_CTX_FREE))
6894                 return;
6895         if (BNXT_FW_MAJ(bp) <= 20) {
6896                 if (hwrm_req_init(bp, req0, HWRM_STAT_CTX_CLR_STATS)) {
6897                         hwrm_req_drop(bp, req);
6898                         return;
6899                 }
6900                 hwrm_req_hold(bp, req0);
6901         }
6902         hwrm_req_hold(bp, req);
6903         for (i = 0; i < bp->cp_nr_rings; i++) {
6904                 struct bnxt_napi *bnapi = bp->bnapi[i];
6905                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
6906
6907                 if (cpr->hw_stats_ctx_id != INVALID_STATS_CTX_ID) {
6908                         req->stat_ctx_id = cpu_to_le32(cpr->hw_stats_ctx_id);
6909                         if (req0) {
6910                                 req0->stat_ctx_id = req->stat_ctx_id;
6911                                 hwrm_req_send(bp, req0);
6912                         }
6913                         hwrm_req_send(bp, req);
6914
6915                         cpr->hw_stats_ctx_id = INVALID_STATS_CTX_ID;
6916                 }
6917         }
6918         hwrm_req_drop(bp, req);
6919         if (req0)
6920                 hwrm_req_drop(bp, req0);
6921 }
6922
6923 static int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp)
6924 {
6925         struct hwrm_stat_ctx_alloc_output *resp;
6926         struct hwrm_stat_ctx_alloc_input *req;
6927         int rc, i;
6928
6929         if (BNXT_CHIP_TYPE_NITRO_A0(bp))
6930                 return 0;
6931
6932         rc = hwrm_req_init(bp, req, HWRM_STAT_CTX_ALLOC);
6933         if (rc)
6934                 return rc;
6935
6936         req->stats_dma_length = cpu_to_le16(bp->hw_ring_stats_size);
6937         req->update_period_ms = cpu_to_le32(bp->stats_coal_ticks / 1000);
6938
6939         resp = hwrm_req_hold(bp, req);
6940         for (i = 0; i < bp->cp_nr_rings; i++) {
6941                 struct bnxt_napi *bnapi = bp->bnapi[i];
6942                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
6943
6944                 req->stats_dma_addr = cpu_to_le64(cpr->stats.hw_stats_map);
6945
6946                 rc = hwrm_req_send(bp, req);
6947                 if (rc)
6948                         break;
6949
6950                 cpr->hw_stats_ctx_id = le32_to_cpu(resp->stat_ctx_id);
6951
6952                 bp->grp_info[i].fw_stats_ctx = cpr->hw_stats_ctx_id;
6953         }
6954         hwrm_req_drop(bp, req);
6955         return rc;
6956 }
6957
6958 static int bnxt_hwrm_func_qcfg(struct bnxt *bp)
6959 {
6960         struct hwrm_func_qcfg_output *resp;
6961         struct hwrm_func_qcfg_input *req;
6962         u32 min_db_offset = 0;
6963         u16 flags;
6964         int rc;
6965
6966         rc = hwrm_req_init(bp, req, HWRM_FUNC_QCFG);
6967         if (rc)
6968                 return rc;
6969
6970         req->fid = cpu_to_le16(0xffff);
6971         resp = hwrm_req_hold(bp, req);
6972         rc = hwrm_req_send(bp, req);
6973         if (rc)
6974                 goto func_qcfg_exit;
6975
6976 #ifdef CONFIG_BNXT_SRIOV
6977         if (BNXT_VF(bp)) {
6978                 struct bnxt_vf_info *vf = &bp->vf;
6979
6980                 vf->vlan = le16_to_cpu(resp->vlan) & VLAN_VID_MASK;
6981         } else {
6982                 bp->pf.registered_vfs = le16_to_cpu(resp->registered_vfs);
6983         }
6984 #endif
6985         flags = le16_to_cpu(resp->flags);
6986         if (flags & (FUNC_QCFG_RESP_FLAGS_FW_DCBX_AGENT_ENABLED |
6987                      FUNC_QCFG_RESP_FLAGS_FW_LLDP_AGENT_ENABLED)) {
6988                 bp->fw_cap |= BNXT_FW_CAP_LLDP_AGENT;
6989                 if (flags & FUNC_QCFG_RESP_FLAGS_FW_DCBX_AGENT_ENABLED)
6990                         bp->fw_cap |= BNXT_FW_CAP_DCBX_AGENT;
6991         }
6992         if (BNXT_PF(bp) && (flags & FUNC_QCFG_RESP_FLAGS_MULTI_HOST)) {
6993                 bp->flags |= BNXT_FLAG_MULTI_HOST;
6994                 if (bp->fw_cap & BNXT_FW_CAP_PTP_RTC)
6995                         bp->fw_cap &= ~BNXT_FW_CAP_PTP_RTC;
6996         }
6997         if (flags & FUNC_QCFG_RESP_FLAGS_RING_MONITOR_ENABLED)
6998                 bp->fw_cap |= BNXT_FW_CAP_RING_MONITOR;
6999
7000         switch (resp->port_partition_type) {
7001         case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_0:
7002         case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_5:
7003         case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR2_0:
7004                 bp->port_partition_type = resp->port_partition_type;
7005                 break;
7006         }
7007         if (bp->hwrm_spec_code < 0x10707 ||
7008             resp->evb_mode == FUNC_QCFG_RESP_EVB_MODE_VEB)
7009                 bp->br_mode = BRIDGE_MODE_VEB;
7010         else if (resp->evb_mode == FUNC_QCFG_RESP_EVB_MODE_VEPA)
7011                 bp->br_mode = BRIDGE_MODE_VEPA;
7012         else
7013                 bp->br_mode = BRIDGE_MODE_UNDEF;
7014
7015         bp->max_mtu = le16_to_cpu(resp->max_mtu_configured);
7016         if (!bp->max_mtu)
7017                 bp->max_mtu = BNXT_MAX_MTU;
7018
7019         if (bp->db_size)
7020                 goto func_qcfg_exit;
7021
7022         if (bp->flags & BNXT_FLAG_CHIP_P5) {
7023                 if (BNXT_PF(bp))
7024                         min_db_offset = DB_PF_OFFSET_P5;
7025                 else
7026                         min_db_offset = DB_VF_OFFSET_P5;
7027         }
7028         bp->db_size = PAGE_ALIGN(le16_to_cpu(resp->l2_doorbell_bar_size_kb) *
7029                                  1024);
7030         if (!bp->db_size || bp->db_size > pci_resource_len(bp->pdev, 2) ||
7031             bp->db_size <= min_db_offset)
7032                 bp->db_size = pci_resource_len(bp->pdev, 2);
7033
7034 func_qcfg_exit:
7035         hwrm_req_drop(bp, req);
7036         return rc;
7037 }
7038
7039 static void bnxt_init_ctx_initializer(struct bnxt_ctx_mem_info *ctx,
7040                         struct hwrm_func_backing_store_qcaps_output *resp)
7041 {
7042         struct bnxt_mem_init *mem_init;
7043         u16 init_mask;
7044         u8 init_val;
7045         u8 *offset;
7046         int i;
7047
7048         init_val = resp->ctx_kind_initializer;
7049         init_mask = le16_to_cpu(resp->ctx_init_mask);
7050         offset = &resp->qp_init_offset;
7051         mem_init = &ctx->mem_init[BNXT_CTX_MEM_INIT_QP];
7052         for (i = 0; i < BNXT_CTX_MEM_INIT_MAX; i++, mem_init++, offset++) {
7053                 mem_init->init_val = init_val;
7054                 mem_init->offset = BNXT_MEM_INVALID_OFFSET;
7055                 if (!init_mask)
7056                         continue;
7057                 if (i == BNXT_CTX_MEM_INIT_STAT)
7058                         offset = &resp->stat_init_offset;
7059                 if (init_mask & (1 << i))
7060                         mem_init->offset = *offset * 4;
7061                 else
7062                         mem_init->init_val = 0;
7063         }
7064         ctx->mem_init[BNXT_CTX_MEM_INIT_QP].size = ctx->qp_entry_size;
7065         ctx->mem_init[BNXT_CTX_MEM_INIT_SRQ].size = ctx->srq_entry_size;
7066         ctx->mem_init[BNXT_CTX_MEM_INIT_CQ].size = ctx->cq_entry_size;
7067         ctx->mem_init[BNXT_CTX_MEM_INIT_VNIC].size = ctx->vnic_entry_size;
7068         ctx->mem_init[BNXT_CTX_MEM_INIT_STAT].size = ctx->stat_entry_size;
7069         ctx->mem_init[BNXT_CTX_MEM_INIT_MRAV].size = ctx->mrav_entry_size;
7070 }
7071
7072 static int bnxt_hwrm_func_backing_store_qcaps(struct bnxt *bp)
7073 {
7074         struct hwrm_func_backing_store_qcaps_output *resp;
7075         struct hwrm_func_backing_store_qcaps_input *req;
7076         int rc;
7077
7078         if (bp->hwrm_spec_code < 0x10902 || BNXT_VF(bp) || bp->ctx)
7079                 return 0;
7080
7081         rc = hwrm_req_init(bp, req, HWRM_FUNC_BACKING_STORE_QCAPS);
7082         if (rc)
7083                 return rc;
7084
7085         resp = hwrm_req_hold(bp, req);
7086         rc = hwrm_req_send_silent(bp, req);
7087         if (!rc) {
7088                 struct bnxt_ctx_pg_info *ctx_pg;
7089                 struct bnxt_ctx_mem_info *ctx;
7090                 int i, tqm_rings;
7091
7092                 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
7093                 if (!ctx) {
7094                         rc = -ENOMEM;
7095                         goto ctx_err;
7096                 }
7097                 ctx->qp_max_entries = le32_to_cpu(resp->qp_max_entries);
7098                 ctx->qp_min_qp1_entries = le16_to_cpu(resp->qp_min_qp1_entries);
7099                 ctx->qp_max_l2_entries = le16_to_cpu(resp->qp_max_l2_entries);
7100                 ctx->qp_entry_size = le16_to_cpu(resp->qp_entry_size);
7101                 ctx->srq_max_l2_entries = le16_to_cpu(resp->srq_max_l2_entries);
7102                 ctx->srq_max_entries = le32_to_cpu(resp->srq_max_entries);
7103                 ctx->srq_entry_size = le16_to_cpu(resp->srq_entry_size);
7104                 ctx->cq_max_l2_entries = le16_to_cpu(resp->cq_max_l2_entries);
7105                 ctx->cq_max_entries = le32_to_cpu(resp->cq_max_entries);
7106                 ctx->cq_entry_size = le16_to_cpu(resp->cq_entry_size);
7107                 ctx->vnic_max_vnic_entries =
7108                         le16_to_cpu(resp->vnic_max_vnic_entries);
7109                 ctx->vnic_max_ring_table_entries =
7110                         le16_to_cpu(resp->vnic_max_ring_table_entries);
7111                 ctx->vnic_entry_size = le16_to_cpu(resp->vnic_entry_size);
7112                 ctx->stat_max_entries = le32_to_cpu(resp->stat_max_entries);
7113                 ctx->stat_entry_size = le16_to_cpu(resp->stat_entry_size);
7114                 ctx->tqm_entry_size = le16_to_cpu(resp->tqm_entry_size);
7115                 ctx->tqm_min_entries_per_ring =
7116                         le32_to_cpu(resp->tqm_min_entries_per_ring);
7117                 ctx->tqm_max_entries_per_ring =
7118                         le32_to_cpu(resp->tqm_max_entries_per_ring);
7119                 ctx->tqm_entries_multiple = resp->tqm_entries_multiple;
7120                 if (!ctx->tqm_entries_multiple)
7121                         ctx->tqm_entries_multiple = 1;
7122                 ctx->mrav_max_entries = le32_to_cpu(resp->mrav_max_entries);
7123                 ctx->mrav_entry_size = le16_to_cpu(resp->mrav_entry_size);
7124                 ctx->mrav_num_entries_units =
7125                         le16_to_cpu(resp->mrav_num_entries_units);
7126                 ctx->tim_entry_size = le16_to_cpu(resp->tim_entry_size);
7127                 ctx->tim_max_entries = le32_to_cpu(resp->tim_max_entries);
7128
7129                 bnxt_init_ctx_initializer(ctx, resp);
7130
7131                 ctx->tqm_fp_rings_count = resp->tqm_fp_rings_count;
7132                 if (!ctx->tqm_fp_rings_count)
7133                         ctx->tqm_fp_rings_count = bp->max_q;
7134                 else if (ctx->tqm_fp_rings_count > BNXT_MAX_TQM_FP_RINGS)
7135                         ctx->tqm_fp_rings_count = BNXT_MAX_TQM_FP_RINGS;
7136
7137                 tqm_rings = ctx->tqm_fp_rings_count + BNXT_MAX_TQM_SP_RINGS;
7138                 ctx_pg = kcalloc(tqm_rings, sizeof(*ctx_pg), GFP_KERNEL);
7139                 if (!ctx_pg) {
7140                         kfree(ctx);
7141                         rc = -ENOMEM;
7142                         goto ctx_err;
7143                 }
7144                 for (i = 0; i < tqm_rings; i++, ctx_pg++)
7145                         ctx->tqm_mem[i] = ctx_pg;
7146                 bp->ctx = ctx;
7147         } else {
7148                 rc = 0;
7149         }
7150 ctx_err:
7151         hwrm_req_drop(bp, req);
7152         return rc;
7153 }
7154
7155 static void bnxt_hwrm_set_pg_attr(struct bnxt_ring_mem_info *rmem, u8 *pg_attr,
7156                                   __le64 *pg_dir)
7157 {
7158         if (!rmem->nr_pages)
7159                 return;
7160
7161         BNXT_SET_CTX_PAGE_ATTR(*pg_attr);
7162         if (rmem->depth >= 1) {
7163                 if (rmem->depth == 2)
7164                         *pg_attr |= 2;
7165                 else
7166                         *pg_attr |= 1;
7167                 *pg_dir = cpu_to_le64(rmem->pg_tbl_map);
7168         } else {
7169                 *pg_dir = cpu_to_le64(rmem->dma_arr[0]);
7170         }
7171 }
7172
7173 #define FUNC_BACKING_STORE_CFG_REQ_DFLT_ENABLES                 \
7174         (FUNC_BACKING_STORE_CFG_REQ_ENABLES_QP |                \
7175          FUNC_BACKING_STORE_CFG_REQ_ENABLES_SRQ |               \
7176          FUNC_BACKING_STORE_CFG_REQ_ENABLES_CQ |                \
7177          FUNC_BACKING_STORE_CFG_REQ_ENABLES_VNIC |              \
7178          FUNC_BACKING_STORE_CFG_REQ_ENABLES_STAT)
7179
7180 static int bnxt_hwrm_func_backing_store_cfg(struct bnxt *bp, u32 enables)
7181 {
7182         struct hwrm_func_backing_store_cfg_input *req;
7183         struct bnxt_ctx_mem_info *ctx = bp->ctx;
7184         struct bnxt_ctx_pg_info *ctx_pg;
7185         void **__req = (void **)&req;
7186         u32 req_len = sizeof(*req);
7187         __le32 *num_entries;
7188         __le64 *pg_dir;
7189         u32 flags = 0;
7190         u8 *pg_attr;
7191         u32 ena;
7192         int rc;
7193         int i;
7194
7195         if (!ctx)
7196                 return 0;
7197
7198         if (req_len > bp->hwrm_max_ext_req_len)
7199                 req_len = BNXT_BACKING_STORE_CFG_LEGACY_LEN;
7200         rc = __hwrm_req_init(bp, __req, HWRM_FUNC_BACKING_STORE_CFG, req_len);
7201         if (rc)
7202                 return rc;
7203
7204         req->enables = cpu_to_le32(enables);
7205         if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_QP) {
7206                 ctx_pg = &ctx->qp_mem;
7207                 req->qp_num_entries = cpu_to_le32(ctx_pg->entries);
7208                 req->qp_num_qp1_entries = cpu_to_le16(ctx->qp_min_qp1_entries);
7209                 req->qp_num_l2_entries = cpu_to_le16(ctx->qp_max_l2_entries);
7210                 req->qp_entry_size = cpu_to_le16(ctx->qp_entry_size);
7211                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
7212                                       &req->qpc_pg_size_qpc_lvl,
7213                                       &req->qpc_page_dir);
7214         }
7215         if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_SRQ) {
7216                 ctx_pg = &ctx->srq_mem;
7217                 req->srq_num_entries = cpu_to_le32(ctx_pg->entries);
7218                 req->srq_num_l2_entries = cpu_to_le16(ctx->srq_max_l2_entries);
7219                 req->srq_entry_size = cpu_to_le16(ctx->srq_entry_size);
7220                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
7221                                       &req->srq_pg_size_srq_lvl,
7222                                       &req->srq_page_dir);
7223         }
7224         if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_CQ) {
7225                 ctx_pg = &ctx->cq_mem;
7226                 req->cq_num_entries = cpu_to_le32(ctx_pg->entries);
7227                 req->cq_num_l2_entries = cpu_to_le16(ctx->cq_max_l2_entries);
7228                 req->cq_entry_size = cpu_to_le16(ctx->cq_entry_size);
7229                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
7230                                       &req->cq_pg_size_cq_lvl,
7231                                       &req->cq_page_dir);
7232         }
7233         if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_VNIC) {
7234                 ctx_pg = &ctx->vnic_mem;
7235                 req->vnic_num_vnic_entries =
7236                         cpu_to_le16(ctx->vnic_max_vnic_entries);
7237                 req->vnic_num_ring_table_entries =
7238                         cpu_to_le16(ctx->vnic_max_ring_table_entries);
7239                 req->vnic_entry_size = cpu_to_le16(ctx->vnic_entry_size);
7240                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
7241                                       &req->vnic_pg_size_vnic_lvl,
7242                                       &req->vnic_page_dir);
7243         }
7244         if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_STAT) {
7245                 ctx_pg = &ctx->stat_mem;
7246                 req->stat_num_entries = cpu_to_le32(ctx->stat_max_entries);
7247                 req->stat_entry_size = cpu_to_le16(ctx->stat_entry_size);
7248                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
7249                                       &req->stat_pg_size_stat_lvl,
7250                                       &req->stat_page_dir);
7251         }
7252         if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_MRAV) {
7253                 ctx_pg = &ctx->mrav_mem;
7254                 req->mrav_num_entries = cpu_to_le32(ctx_pg->entries);
7255                 if (ctx->mrav_num_entries_units)
7256                         flags |=
7257                         FUNC_BACKING_STORE_CFG_REQ_FLAGS_MRAV_RESERVATION_SPLIT;
7258                 req->mrav_entry_size = cpu_to_le16(ctx->mrav_entry_size);
7259                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
7260                                       &req->mrav_pg_size_mrav_lvl,
7261                                       &req->mrav_page_dir);
7262         }
7263         if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_TIM) {
7264                 ctx_pg = &ctx->tim_mem;
7265                 req->tim_num_entries = cpu_to_le32(ctx_pg->entries);
7266                 req->tim_entry_size = cpu_to_le16(ctx->tim_entry_size);
7267                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
7268                                       &req->tim_pg_size_tim_lvl,
7269                                       &req->tim_page_dir);
7270         }
7271         for (i = 0, num_entries = &req->tqm_sp_num_entries,
7272              pg_attr = &req->tqm_sp_pg_size_tqm_sp_lvl,
7273              pg_dir = &req->tqm_sp_page_dir,
7274              ena = FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_SP;
7275              i < BNXT_MAX_TQM_RINGS;
7276              i++, num_entries++, pg_attr++, pg_dir++, ena <<= 1) {
7277                 if (!(enables & ena))
7278                         continue;
7279
7280                 req->tqm_entry_size = cpu_to_le16(ctx->tqm_entry_size);
7281                 ctx_pg = ctx->tqm_mem[i];
7282                 *num_entries = cpu_to_le32(ctx_pg->entries);
7283                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, pg_attr, pg_dir);
7284         }
7285         req->flags = cpu_to_le32(flags);
7286         return hwrm_req_send(bp, req);
7287 }
7288
7289 static int bnxt_alloc_ctx_mem_blk(struct bnxt *bp,
7290                                   struct bnxt_ctx_pg_info *ctx_pg)
7291 {
7292         struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
7293
7294         rmem->page_size = BNXT_PAGE_SIZE;
7295         rmem->pg_arr = ctx_pg->ctx_pg_arr;
7296         rmem->dma_arr = ctx_pg->ctx_dma_arr;
7297         rmem->flags = BNXT_RMEM_VALID_PTE_FLAG;
7298         if (rmem->depth >= 1)
7299                 rmem->flags |= BNXT_RMEM_USE_FULL_PAGE_FLAG;
7300         return bnxt_alloc_ring(bp, rmem);
7301 }
7302
7303 static int bnxt_alloc_ctx_pg_tbls(struct bnxt *bp,
7304                                   struct bnxt_ctx_pg_info *ctx_pg, u32 mem_size,
7305                                   u8 depth, struct bnxt_mem_init *mem_init)
7306 {
7307         struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
7308         int rc;
7309
7310         if (!mem_size)
7311                 return -EINVAL;
7312
7313         ctx_pg->nr_pages = DIV_ROUND_UP(mem_size, BNXT_PAGE_SIZE);
7314         if (ctx_pg->nr_pages > MAX_CTX_TOTAL_PAGES) {
7315                 ctx_pg->nr_pages = 0;
7316                 return -EINVAL;
7317         }
7318         if (ctx_pg->nr_pages > MAX_CTX_PAGES || depth > 1) {
7319                 int nr_tbls, i;
7320
7321                 rmem->depth = 2;
7322                 ctx_pg->ctx_pg_tbl = kcalloc(MAX_CTX_PAGES, sizeof(ctx_pg),
7323                                              GFP_KERNEL);
7324                 if (!ctx_pg->ctx_pg_tbl)
7325                         return -ENOMEM;
7326                 nr_tbls = DIV_ROUND_UP(ctx_pg->nr_pages, MAX_CTX_PAGES);
7327                 rmem->nr_pages = nr_tbls;
7328                 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg);
7329                 if (rc)
7330                         return rc;
7331                 for (i = 0; i < nr_tbls; i++) {
7332                         struct bnxt_ctx_pg_info *pg_tbl;
7333
7334                         pg_tbl = kzalloc(sizeof(*pg_tbl), GFP_KERNEL);
7335                         if (!pg_tbl)
7336                                 return -ENOMEM;
7337                         ctx_pg->ctx_pg_tbl[i] = pg_tbl;
7338                         rmem = &pg_tbl->ring_mem;
7339                         rmem->pg_tbl = ctx_pg->ctx_pg_arr[i];
7340                         rmem->pg_tbl_map = ctx_pg->ctx_dma_arr[i];
7341                         rmem->depth = 1;
7342                         rmem->nr_pages = MAX_CTX_PAGES;
7343                         rmem->mem_init = mem_init;
7344                         if (i == (nr_tbls - 1)) {
7345                                 int rem = ctx_pg->nr_pages % MAX_CTX_PAGES;
7346
7347                                 if (rem)
7348                                         rmem->nr_pages = rem;
7349                         }
7350                         rc = bnxt_alloc_ctx_mem_blk(bp, pg_tbl);
7351                         if (rc)
7352                                 break;
7353                 }
7354         } else {
7355                 rmem->nr_pages = DIV_ROUND_UP(mem_size, BNXT_PAGE_SIZE);
7356                 if (rmem->nr_pages > 1 || depth)
7357                         rmem->depth = 1;
7358                 rmem->mem_init = mem_init;
7359                 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg);
7360         }
7361         return rc;
7362 }
7363
7364 static void bnxt_free_ctx_pg_tbls(struct bnxt *bp,
7365                                   struct bnxt_ctx_pg_info *ctx_pg)
7366 {
7367         struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
7368
7369         if (rmem->depth > 1 || ctx_pg->nr_pages > MAX_CTX_PAGES ||
7370             ctx_pg->ctx_pg_tbl) {
7371                 int i, nr_tbls = rmem->nr_pages;
7372
7373                 for (i = 0; i < nr_tbls; i++) {
7374                         struct bnxt_ctx_pg_info *pg_tbl;
7375                         struct bnxt_ring_mem_info *rmem2;
7376
7377                         pg_tbl = ctx_pg->ctx_pg_tbl[i];
7378                         if (!pg_tbl)
7379                                 continue;
7380                         rmem2 = &pg_tbl->ring_mem;
7381                         bnxt_free_ring(bp, rmem2);
7382                         ctx_pg->ctx_pg_arr[i] = NULL;
7383                         kfree(pg_tbl);
7384                         ctx_pg->ctx_pg_tbl[i] = NULL;
7385                 }
7386                 kfree(ctx_pg->ctx_pg_tbl);
7387                 ctx_pg->ctx_pg_tbl = NULL;
7388         }
7389         bnxt_free_ring(bp, rmem);
7390         ctx_pg->nr_pages = 0;
7391 }
7392
7393 void bnxt_free_ctx_mem(struct bnxt *bp)
7394 {
7395         struct bnxt_ctx_mem_info *ctx = bp->ctx;
7396         int i;
7397
7398         if (!ctx)
7399                 return;
7400
7401         if (ctx->tqm_mem[0]) {
7402                 for (i = 0; i < ctx->tqm_fp_rings_count + 1; i++)
7403                         bnxt_free_ctx_pg_tbls(bp, ctx->tqm_mem[i]);
7404                 kfree(ctx->tqm_mem[0]);
7405                 ctx->tqm_mem[0] = NULL;
7406         }
7407
7408         bnxt_free_ctx_pg_tbls(bp, &ctx->tim_mem);
7409         bnxt_free_ctx_pg_tbls(bp, &ctx->mrav_mem);
7410         bnxt_free_ctx_pg_tbls(bp, &ctx->stat_mem);
7411         bnxt_free_ctx_pg_tbls(bp, &ctx->vnic_mem);
7412         bnxt_free_ctx_pg_tbls(bp, &ctx->cq_mem);
7413         bnxt_free_ctx_pg_tbls(bp, &ctx->srq_mem);
7414         bnxt_free_ctx_pg_tbls(bp, &ctx->qp_mem);
7415         ctx->flags &= ~BNXT_CTX_FLAG_INITED;
7416 }
7417
7418 static int bnxt_alloc_ctx_mem(struct bnxt *bp)
7419 {
7420         struct bnxt_ctx_pg_info *ctx_pg;
7421         struct bnxt_ctx_mem_info *ctx;
7422         struct bnxt_mem_init *init;
7423         u32 mem_size, ena, entries;
7424         u32 entries_sp, min;
7425         u32 num_mr, num_ah;
7426         u32 extra_srqs = 0;
7427         u32 extra_qps = 0;
7428         u8 pg_lvl = 1;
7429         int i, rc;
7430
7431         rc = bnxt_hwrm_func_backing_store_qcaps(bp);
7432         if (rc) {
7433                 netdev_err(bp->dev, "Failed querying context mem capability, rc = %d.\n",
7434                            rc);
7435                 return rc;
7436         }
7437         ctx = bp->ctx;
7438         if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED))
7439                 return 0;
7440
7441         if ((bp->flags & BNXT_FLAG_ROCE_CAP) && !is_kdump_kernel()) {
7442                 pg_lvl = 2;
7443                 extra_qps = 65536;
7444                 extra_srqs = 8192;
7445         }
7446
7447         ctx_pg = &ctx->qp_mem;
7448         ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries +
7449                           extra_qps;
7450         if (ctx->qp_entry_size) {
7451                 mem_size = ctx->qp_entry_size * ctx_pg->entries;
7452                 init = &ctx->mem_init[BNXT_CTX_MEM_INIT_QP];
7453                 rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, pg_lvl, init);
7454                 if (rc)
7455                         return rc;
7456         }
7457
7458         ctx_pg = &ctx->srq_mem;
7459         ctx_pg->entries = ctx->srq_max_l2_entries + extra_srqs;
7460         if (ctx->srq_entry_size) {
7461                 mem_size = ctx->srq_entry_size * ctx_pg->entries;
7462                 init = &ctx->mem_init[BNXT_CTX_MEM_INIT_SRQ];
7463                 rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, pg_lvl, init);
7464                 if (rc)
7465                         return rc;
7466         }
7467
7468         ctx_pg = &ctx->cq_mem;
7469         ctx_pg->entries = ctx->cq_max_l2_entries + extra_qps * 2;
7470         if (ctx->cq_entry_size) {
7471                 mem_size = ctx->cq_entry_size * ctx_pg->entries;
7472                 init = &ctx->mem_init[BNXT_CTX_MEM_INIT_CQ];
7473                 rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, pg_lvl, init);
7474                 if (rc)
7475                         return rc;
7476         }
7477
7478         ctx_pg = &ctx->vnic_mem;
7479         ctx_pg->entries = ctx->vnic_max_vnic_entries +
7480                           ctx->vnic_max_ring_table_entries;
7481         if (ctx->vnic_entry_size) {
7482                 mem_size = ctx->vnic_entry_size * ctx_pg->entries;
7483                 init = &ctx->mem_init[BNXT_CTX_MEM_INIT_VNIC];
7484                 rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, 1, init);
7485                 if (rc)
7486                         return rc;
7487         }
7488
7489         ctx_pg = &ctx->stat_mem;
7490         ctx_pg->entries = ctx->stat_max_entries;
7491         if (ctx->stat_entry_size) {
7492                 mem_size = ctx->stat_entry_size * ctx_pg->entries;
7493                 init = &ctx->mem_init[BNXT_CTX_MEM_INIT_STAT];
7494                 rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, 1, init);
7495                 if (rc)
7496                         return rc;
7497         }
7498
7499         ena = 0;
7500         if (!(bp->flags & BNXT_FLAG_ROCE_CAP))
7501                 goto skip_rdma;
7502
7503         ctx_pg = &ctx->mrav_mem;
7504         /* 128K extra is needed to accommodate static AH context
7505          * allocation by f/w.
7506          */
7507         num_mr = 1024 * 256;
7508         num_ah = 1024 * 128;
7509         ctx_pg->entries = num_mr + num_ah;
7510         if (ctx->mrav_entry_size) {
7511                 mem_size = ctx->mrav_entry_size * ctx_pg->entries;
7512                 init = &ctx->mem_init[BNXT_CTX_MEM_INIT_MRAV];
7513                 rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, 2, init);
7514                 if (rc)
7515                         return rc;
7516         }
7517         ena = FUNC_BACKING_STORE_CFG_REQ_ENABLES_MRAV;
7518         if (ctx->mrav_num_entries_units)
7519                 ctx_pg->entries =
7520                         ((num_mr / ctx->mrav_num_entries_units) << 16) |
7521                          (num_ah / ctx->mrav_num_entries_units);
7522
7523         ctx_pg = &ctx->tim_mem;
7524         ctx_pg->entries = ctx->qp_mem.entries;
7525         if (ctx->tim_entry_size) {
7526                 mem_size = ctx->tim_entry_size * ctx_pg->entries;
7527                 rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, 1, NULL);
7528                 if (rc)
7529                         return rc;
7530         }
7531         ena |= FUNC_BACKING_STORE_CFG_REQ_ENABLES_TIM;
7532
7533 skip_rdma:
7534         min = ctx->tqm_min_entries_per_ring;
7535         entries_sp = ctx->vnic_max_vnic_entries + ctx->qp_max_l2_entries +
7536                      2 * (extra_qps + ctx->qp_min_qp1_entries) + min;
7537         entries_sp = roundup(entries_sp, ctx->tqm_entries_multiple);
7538         entries = ctx->qp_max_l2_entries + 2 * (extra_qps + ctx->qp_min_qp1_entries);
7539         entries = roundup(entries, ctx->tqm_entries_multiple);
7540         entries = clamp_t(u32, entries, min, ctx->tqm_max_entries_per_ring);
7541         for (i = 0; i < ctx->tqm_fp_rings_count + 1; i++) {
7542                 ctx_pg = ctx->tqm_mem[i];
7543                 ctx_pg->entries = i ? entries : entries_sp;
7544                 if (ctx->tqm_entry_size) {
7545                         mem_size = ctx->tqm_entry_size * ctx_pg->entries;
7546                         rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, 1,
7547                                                     NULL);
7548                         if (rc)
7549                                 return rc;
7550                 }
7551                 ena |= FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_SP << i;
7552         }
7553         ena |= FUNC_BACKING_STORE_CFG_REQ_DFLT_ENABLES;
7554         rc = bnxt_hwrm_func_backing_store_cfg(bp, ena);
7555         if (rc) {
7556                 netdev_err(bp->dev, "Failed configuring context mem, rc = %d.\n",
7557                            rc);
7558                 return rc;
7559         }
7560         ctx->flags |= BNXT_CTX_FLAG_INITED;
7561         return 0;
7562 }
7563
7564 int bnxt_hwrm_func_resc_qcaps(struct bnxt *bp, bool all)
7565 {
7566         struct hwrm_func_resource_qcaps_output *resp;
7567         struct hwrm_func_resource_qcaps_input *req;
7568         struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
7569         int rc;
7570
7571         rc = hwrm_req_init(bp, req, HWRM_FUNC_RESOURCE_QCAPS);
7572         if (rc)
7573                 return rc;
7574
7575         req->fid = cpu_to_le16(0xffff);
7576         resp = hwrm_req_hold(bp, req);
7577         rc = hwrm_req_send_silent(bp, req);
7578         if (rc)
7579                 goto hwrm_func_resc_qcaps_exit;
7580
7581         hw_resc->max_tx_sch_inputs = le16_to_cpu(resp->max_tx_scheduler_inputs);
7582         if (!all)
7583                 goto hwrm_func_resc_qcaps_exit;
7584
7585         hw_resc->min_rsscos_ctxs = le16_to_cpu(resp->min_rsscos_ctx);
7586         hw_resc->max_rsscos_ctxs = le16_to_cpu(resp->max_rsscos_ctx);
7587         hw_resc->min_cp_rings = le16_to_cpu(resp->min_cmpl_rings);
7588         hw_resc->max_cp_rings = le16_to_cpu(resp->max_cmpl_rings);
7589         hw_resc->min_tx_rings = le16_to_cpu(resp->min_tx_rings);
7590         hw_resc->max_tx_rings = le16_to_cpu(resp->max_tx_rings);
7591         hw_resc->min_rx_rings = le16_to_cpu(resp->min_rx_rings);
7592         hw_resc->max_rx_rings = le16_to_cpu(resp->max_rx_rings);
7593         hw_resc->min_hw_ring_grps = le16_to_cpu(resp->min_hw_ring_grps);
7594         hw_resc->max_hw_ring_grps = le16_to_cpu(resp->max_hw_ring_grps);
7595         hw_resc->min_l2_ctxs = le16_to_cpu(resp->min_l2_ctxs);
7596         hw_resc->max_l2_ctxs = le16_to_cpu(resp->max_l2_ctxs);
7597         hw_resc->min_vnics = le16_to_cpu(resp->min_vnics);
7598         hw_resc->max_vnics = le16_to_cpu(resp->max_vnics);
7599         hw_resc->min_stat_ctxs = le16_to_cpu(resp->min_stat_ctx);
7600         hw_resc->max_stat_ctxs = le16_to_cpu(resp->max_stat_ctx);
7601
7602         if (bp->flags & BNXT_FLAG_CHIP_P5) {
7603                 u16 max_msix = le16_to_cpu(resp->max_msix);
7604
7605                 hw_resc->max_nqs = max_msix;
7606                 hw_resc->max_hw_ring_grps = hw_resc->max_rx_rings;
7607         }
7608
7609         if (BNXT_PF(bp)) {
7610                 struct bnxt_pf_info *pf = &bp->pf;
7611
7612                 pf->vf_resv_strategy =
7613                         le16_to_cpu(resp->vf_reservation_strategy);
7614                 if (pf->vf_resv_strategy > BNXT_VF_RESV_STRATEGY_MINIMAL_STATIC)
7615                         pf->vf_resv_strategy = BNXT_VF_RESV_STRATEGY_MAXIMAL;
7616         }
7617 hwrm_func_resc_qcaps_exit:
7618         hwrm_req_drop(bp, req);
7619         return rc;
7620 }
7621
7622 static int __bnxt_hwrm_ptp_qcfg(struct bnxt *bp)
7623 {
7624         struct hwrm_port_mac_ptp_qcfg_output *resp;
7625         struct hwrm_port_mac_ptp_qcfg_input *req;
7626         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
7627         bool phc_cfg;
7628         u8 flags;
7629         int rc;
7630
7631         if (bp->hwrm_spec_code < 0x10801) {
7632                 rc = -ENODEV;
7633                 goto no_ptp;
7634         }
7635
7636         rc = hwrm_req_init(bp, req, HWRM_PORT_MAC_PTP_QCFG);
7637         if (rc)
7638                 goto no_ptp;
7639
7640         req->port_id = cpu_to_le16(bp->pf.port_id);
7641         resp = hwrm_req_hold(bp, req);
7642         rc = hwrm_req_send(bp, req);
7643         if (rc)
7644                 goto exit;
7645
7646         flags = resp->flags;
7647         if (!(flags & PORT_MAC_PTP_QCFG_RESP_FLAGS_HWRM_ACCESS)) {
7648                 rc = -ENODEV;
7649                 goto exit;
7650         }
7651         if (!ptp) {
7652                 ptp = kzalloc(sizeof(*ptp), GFP_KERNEL);
7653                 if (!ptp) {
7654                         rc = -ENOMEM;
7655                         goto exit;
7656                 }
7657                 ptp->bp = bp;
7658                 bp->ptp_cfg = ptp;
7659         }
7660         if (flags & PORT_MAC_PTP_QCFG_RESP_FLAGS_PARTIAL_DIRECT_ACCESS_REF_CLOCK) {
7661                 ptp->refclk_regs[0] = le32_to_cpu(resp->ts_ref_clock_reg_lower);
7662                 ptp->refclk_regs[1] = le32_to_cpu(resp->ts_ref_clock_reg_upper);
7663         } else if (bp->flags & BNXT_FLAG_CHIP_P5) {
7664                 ptp->refclk_regs[0] = BNXT_TS_REG_TIMESYNC_TS0_LOWER;
7665                 ptp->refclk_regs[1] = BNXT_TS_REG_TIMESYNC_TS0_UPPER;
7666         } else {
7667                 rc = -ENODEV;
7668                 goto exit;
7669         }
7670         phc_cfg = (flags & PORT_MAC_PTP_QCFG_RESP_FLAGS_RTC_CONFIGURED) != 0;
7671         rc = bnxt_ptp_init(bp, phc_cfg);
7672         if (rc)
7673                 netdev_warn(bp->dev, "PTP initialization failed.\n");
7674 exit:
7675         hwrm_req_drop(bp, req);
7676         if (!rc)
7677                 return 0;
7678
7679 no_ptp:
7680         bnxt_ptp_clear(bp);
7681         kfree(ptp);
7682         bp->ptp_cfg = NULL;
7683         return rc;
7684 }
7685
7686 static int __bnxt_hwrm_func_qcaps(struct bnxt *bp)
7687 {
7688         struct hwrm_func_qcaps_output *resp;
7689         struct hwrm_func_qcaps_input *req;
7690         struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
7691         u32 flags, flags_ext, flags_ext2;
7692         int rc;
7693
7694         rc = hwrm_req_init(bp, req, HWRM_FUNC_QCAPS);
7695         if (rc)
7696                 return rc;
7697
7698         req->fid = cpu_to_le16(0xffff);
7699         resp = hwrm_req_hold(bp, req);
7700         rc = hwrm_req_send(bp, req);
7701         if (rc)
7702                 goto hwrm_func_qcaps_exit;
7703
7704         flags = le32_to_cpu(resp->flags);
7705         if (flags & FUNC_QCAPS_RESP_FLAGS_ROCE_V1_SUPPORTED)
7706                 bp->flags |= BNXT_FLAG_ROCEV1_CAP;
7707         if (flags & FUNC_QCAPS_RESP_FLAGS_ROCE_V2_SUPPORTED)
7708                 bp->flags |= BNXT_FLAG_ROCEV2_CAP;
7709         if (flags & FUNC_QCAPS_RESP_FLAGS_PCIE_STATS_SUPPORTED)
7710                 bp->fw_cap |= BNXT_FW_CAP_PCIE_STATS_SUPPORTED;
7711         if (flags & FUNC_QCAPS_RESP_FLAGS_HOT_RESET_CAPABLE)
7712                 bp->fw_cap |= BNXT_FW_CAP_HOT_RESET;
7713         if (flags & FUNC_QCAPS_RESP_FLAGS_EXT_STATS_SUPPORTED)
7714                 bp->fw_cap |= BNXT_FW_CAP_EXT_STATS_SUPPORTED;
7715         if (flags &  FUNC_QCAPS_RESP_FLAGS_ERROR_RECOVERY_CAPABLE)
7716                 bp->fw_cap |= BNXT_FW_CAP_ERROR_RECOVERY;
7717         if (flags & FUNC_QCAPS_RESP_FLAGS_ERR_RECOVER_RELOAD)
7718                 bp->fw_cap |= BNXT_FW_CAP_ERR_RECOVER_RELOAD;
7719         if (!(flags & FUNC_QCAPS_RESP_FLAGS_VLAN_ACCELERATION_TX_DISABLED))
7720                 bp->fw_cap |= BNXT_FW_CAP_VLAN_TX_INSERT;
7721         if (flags & FUNC_QCAPS_RESP_FLAGS_DBG_QCAPS_CMD_SUPPORTED)
7722                 bp->fw_cap |= BNXT_FW_CAP_DBG_QCAPS;
7723
7724         flags_ext = le32_to_cpu(resp->flags_ext);
7725         if (flags_ext & FUNC_QCAPS_RESP_FLAGS_EXT_EXT_HW_STATS_SUPPORTED)
7726                 bp->fw_cap |= BNXT_FW_CAP_EXT_HW_STATS_SUPPORTED;
7727         if (BNXT_PF(bp) && (flags_ext & FUNC_QCAPS_RESP_FLAGS_EXT_PTP_PPS_SUPPORTED))
7728                 bp->fw_cap |= BNXT_FW_CAP_PTP_PPS;
7729         if (flags_ext & FUNC_QCAPS_RESP_FLAGS_EXT_PTP_64BIT_RTC_SUPPORTED)
7730                 bp->fw_cap |= BNXT_FW_CAP_PTP_RTC;
7731         if (BNXT_PF(bp) && (flags_ext & FUNC_QCAPS_RESP_FLAGS_EXT_HOT_RESET_IF_SUPPORT))
7732                 bp->fw_cap |= BNXT_FW_CAP_HOT_RESET_IF;
7733         if (BNXT_PF(bp) && (flags_ext & FUNC_QCAPS_RESP_FLAGS_EXT_FW_LIVEPATCH_SUPPORTED))
7734                 bp->fw_cap |= BNXT_FW_CAP_LIVEPATCH;
7735
7736         flags_ext2 = le32_to_cpu(resp->flags_ext2);
7737         if (flags_ext2 & FUNC_QCAPS_RESP_FLAGS_EXT2_RX_ALL_PKTS_TIMESTAMPS_SUPPORTED)
7738                 bp->fw_cap |= BNXT_FW_CAP_RX_ALL_PKT_TS;
7739
7740         bp->tx_push_thresh = 0;
7741         if ((flags & FUNC_QCAPS_RESP_FLAGS_PUSH_MODE_SUPPORTED) &&
7742             BNXT_FW_MAJ(bp) > 217)
7743                 bp->tx_push_thresh = BNXT_TX_PUSH_THRESH;
7744
7745         hw_resc->max_rsscos_ctxs = le16_to_cpu(resp->max_rsscos_ctx);
7746         hw_resc->max_cp_rings = le16_to_cpu(resp->max_cmpl_rings);
7747         hw_resc->max_tx_rings = le16_to_cpu(resp->max_tx_rings);
7748         hw_resc->max_rx_rings = le16_to_cpu(resp->max_rx_rings);
7749         hw_resc->max_hw_ring_grps = le32_to_cpu(resp->max_hw_ring_grps);
7750         if (!hw_resc->max_hw_ring_grps)
7751                 hw_resc->max_hw_ring_grps = hw_resc->max_tx_rings;
7752         hw_resc->max_l2_ctxs = le16_to_cpu(resp->max_l2_ctxs);
7753         hw_resc->max_vnics = le16_to_cpu(resp->max_vnics);
7754         hw_resc->max_stat_ctxs = le16_to_cpu(resp->max_stat_ctx);
7755
7756         if (BNXT_PF(bp)) {
7757                 struct bnxt_pf_info *pf = &bp->pf;
7758
7759                 pf->fw_fid = le16_to_cpu(resp->fid);
7760                 pf->port_id = le16_to_cpu(resp->port_id);
7761                 memcpy(pf->mac_addr, resp->mac_address, ETH_ALEN);
7762                 pf->first_vf_id = le16_to_cpu(resp->first_vf_id);
7763                 pf->max_vfs = le16_to_cpu(resp->max_vfs);
7764                 pf->max_encap_records = le32_to_cpu(resp->max_encap_records);
7765                 pf->max_decap_records = le32_to_cpu(resp->max_decap_records);
7766                 pf->max_tx_em_flows = le32_to_cpu(resp->max_tx_em_flows);
7767                 pf->max_tx_wm_flows = le32_to_cpu(resp->max_tx_wm_flows);
7768                 pf->max_rx_em_flows = le32_to_cpu(resp->max_rx_em_flows);
7769                 pf->max_rx_wm_flows = le32_to_cpu(resp->max_rx_wm_flows);
7770                 bp->flags &= ~BNXT_FLAG_WOL_CAP;
7771                 if (flags & FUNC_QCAPS_RESP_FLAGS_WOL_MAGICPKT_SUPPORTED)
7772                         bp->flags |= BNXT_FLAG_WOL_CAP;
7773                 if (flags & FUNC_QCAPS_RESP_FLAGS_PTP_SUPPORTED) {
7774                         __bnxt_hwrm_ptp_qcfg(bp);
7775                 } else {
7776                         bnxt_ptp_clear(bp);
7777                         kfree(bp->ptp_cfg);
7778                         bp->ptp_cfg = NULL;
7779                 }
7780         } else {
7781 #ifdef CONFIG_BNXT_SRIOV
7782                 struct bnxt_vf_info *vf = &bp->vf;
7783
7784                 vf->fw_fid = le16_to_cpu(resp->fid);
7785                 memcpy(vf->mac_addr, resp->mac_address, ETH_ALEN);
7786 #endif
7787         }
7788
7789 hwrm_func_qcaps_exit:
7790         hwrm_req_drop(bp, req);
7791         return rc;
7792 }
7793
7794 static void bnxt_hwrm_dbg_qcaps(struct bnxt *bp)
7795 {
7796         struct hwrm_dbg_qcaps_output *resp;
7797         struct hwrm_dbg_qcaps_input *req;
7798         int rc;
7799
7800         bp->fw_dbg_cap = 0;
7801         if (!(bp->fw_cap & BNXT_FW_CAP_DBG_QCAPS))
7802                 return;
7803
7804         rc = hwrm_req_init(bp, req, HWRM_DBG_QCAPS);
7805         if (rc)
7806                 return;
7807
7808         req->fid = cpu_to_le16(0xffff);
7809         resp = hwrm_req_hold(bp, req);
7810         rc = hwrm_req_send(bp, req);
7811         if (rc)
7812                 goto hwrm_dbg_qcaps_exit;
7813
7814         bp->fw_dbg_cap = le32_to_cpu(resp->flags);
7815
7816 hwrm_dbg_qcaps_exit:
7817         hwrm_req_drop(bp, req);
7818 }
7819
7820 static int bnxt_hwrm_queue_qportcfg(struct bnxt *bp);
7821
7822 int bnxt_hwrm_func_qcaps(struct bnxt *bp)
7823 {
7824         int rc;
7825
7826         rc = __bnxt_hwrm_func_qcaps(bp);
7827         if (rc)
7828                 return rc;
7829
7830         bnxt_hwrm_dbg_qcaps(bp);
7831
7832         rc = bnxt_hwrm_queue_qportcfg(bp);
7833         if (rc) {
7834                 netdev_err(bp->dev, "hwrm query qportcfg failure rc: %d\n", rc);
7835                 return rc;
7836         }
7837         if (bp->hwrm_spec_code >= 0x10803) {
7838                 rc = bnxt_alloc_ctx_mem(bp);
7839                 if (rc)
7840                         return rc;
7841                 rc = bnxt_hwrm_func_resc_qcaps(bp, true);
7842                 if (!rc)
7843                         bp->fw_cap |= BNXT_FW_CAP_NEW_RM;
7844         }
7845         return 0;
7846 }
7847
7848 static int bnxt_hwrm_cfa_adv_flow_mgnt_qcaps(struct bnxt *bp)
7849 {
7850         struct hwrm_cfa_adv_flow_mgnt_qcaps_output *resp;
7851         struct hwrm_cfa_adv_flow_mgnt_qcaps_input *req;
7852         u32 flags;
7853         int rc;
7854
7855         if (!(bp->fw_cap & BNXT_FW_CAP_CFA_ADV_FLOW))
7856                 return 0;
7857
7858         rc = hwrm_req_init(bp, req, HWRM_CFA_ADV_FLOW_MGNT_QCAPS);
7859         if (rc)
7860                 return rc;
7861
7862         resp = hwrm_req_hold(bp, req);
7863         rc = hwrm_req_send(bp, req);
7864         if (rc)
7865                 goto hwrm_cfa_adv_qcaps_exit;
7866
7867         flags = le32_to_cpu(resp->flags);
7868         if (flags &
7869             CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_RFS_RING_TBL_IDX_V2_SUPPORTED)
7870                 bp->fw_cap |= BNXT_FW_CAP_CFA_RFS_RING_TBL_IDX_V2;
7871
7872 hwrm_cfa_adv_qcaps_exit:
7873         hwrm_req_drop(bp, req);
7874         return rc;
7875 }
7876
7877 static int __bnxt_alloc_fw_health(struct bnxt *bp)
7878 {
7879         if (bp->fw_health)
7880                 return 0;
7881
7882         bp->fw_health = kzalloc(sizeof(*bp->fw_health), GFP_KERNEL);
7883         if (!bp->fw_health)
7884                 return -ENOMEM;
7885
7886         mutex_init(&bp->fw_health->lock);
7887         return 0;
7888 }
7889
7890 static int bnxt_alloc_fw_health(struct bnxt *bp)
7891 {
7892         int rc;
7893
7894         if (!(bp->fw_cap & BNXT_FW_CAP_HOT_RESET) &&
7895             !(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY))
7896                 return 0;
7897
7898         rc = __bnxt_alloc_fw_health(bp);
7899         if (rc) {
7900                 bp->fw_cap &= ~BNXT_FW_CAP_HOT_RESET;
7901                 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
7902                 return rc;
7903         }
7904
7905         return 0;
7906 }
7907
7908 static void __bnxt_map_fw_health_reg(struct bnxt *bp, u32 reg)
7909 {
7910         writel(reg & BNXT_GRC_BASE_MASK, bp->bar0 +
7911                                          BNXT_GRCPF_REG_WINDOW_BASE_OUT +
7912                                          BNXT_FW_HEALTH_WIN_MAP_OFF);
7913 }
7914
7915 static void bnxt_inv_fw_health_reg(struct bnxt *bp)
7916 {
7917         struct bnxt_fw_health *fw_health = bp->fw_health;
7918         u32 reg_type;
7919
7920         if (!fw_health)
7921                 return;
7922
7923         reg_type = BNXT_FW_HEALTH_REG_TYPE(fw_health->regs[BNXT_FW_HEALTH_REG]);
7924         if (reg_type == BNXT_FW_HEALTH_REG_TYPE_GRC)
7925                 fw_health->status_reliable = false;
7926
7927         reg_type = BNXT_FW_HEALTH_REG_TYPE(fw_health->regs[BNXT_FW_RESET_CNT_REG]);
7928         if (reg_type == BNXT_FW_HEALTH_REG_TYPE_GRC)
7929                 fw_health->resets_reliable = false;
7930 }
7931
7932 static void bnxt_try_map_fw_health_reg(struct bnxt *bp)
7933 {
7934         void __iomem *hs;
7935         u32 status_loc;
7936         u32 reg_type;
7937         u32 sig;
7938
7939         if (bp->fw_health)
7940                 bp->fw_health->status_reliable = false;
7941
7942         __bnxt_map_fw_health_reg(bp, HCOMM_STATUS_STRUCT_LOC);
7943         hs = bp->bar0 + BNXT_FW_HEALTH_WIN_OFF(HCOMM_STATUS_STRUCT_LOC);
7944
7945         sig = readl(hs + offsetof(struct hcomm_status, sig_ver));
7946         if ((sig & HCOMM_STATUS_SIGNATURE_MASK) != HCOMM_STATUS_SIGNATURE_VAL) {
7947                 if (!bp->chip_num) {
7948                         __bnxt_map_fw_health_reg(bp, BNXT_GRC_REG_BASE);
7949                         bp->chip_num = readl(bp->bar0 +
7950                                              BNXT_FW_HEALTH_WIN_BASE +
7951                                              BNXT_GRC_REG_CHIP_NUM);
7952                 }
7953                 if (!BNXT_CHIP_P5(bp))
7954                         return;
7955
7956                 status_loc = BNXT_GRC_REG_STATUS_P5 |
7957                              BNXT_FW_HEALTH_REG_TYPE_BAR0;
7958         } else {
7959                 status_loc = readl(hs + offsetof(struct hcomm_status,
7960                                                  fw_status_loc));
7961         }
7962
7963         if (__bnxt_alloc_fw_health(bp)) {
7964                 netdev_warn(bp->dev, "no memory for firmware status checks\n");
7965                 return;
7966         }
7967
7968         bp->fw_health->regs[BNXT_FW_HEALTH_REG] = status_loc;
7969         reg_type = BNXT_FW_HEALTH_REG_TYPE(status_loc);
7970         if (reg_type == BNXT_FW_HEALTH_REG_TYPE_GRC) {
7971                 __bnxt_map_fw_health_reg(bp, status_loc);
7972                 bp->fw_health->mapped_regs[BNXT_FW_HEALTH_REG] =
7973                         BNXT_FW_HEALTH_WIN_OFF(status_loc);
7974         }
7975
7976         bp->fw_health->status_reliable = true;
7977 }
7978
7979 static int bnxt_map_fw_health_regs(struct bnxt *bp)
7980 {
7981         struct bnxt_fw_health *fw_health = bp->fw_health;
7982         u32 reg_base = 0xffffffff;
7983         int i;
7984
7985         bp->fw_health->status_reliable = false;
7986         bp->fw_health->resets_reliable = false;
7987         /* Only pre-map the monitoring GRC registers using window 3 */
7988         for (i = 0; i < 4; i++) {
7989                 u32 reg = fw_health->regs[i];
7990
7991                 if (BNXT_FW_HEALTH_REG_TYPE(reg) != BNXT_FW_HEALTH_REG_TYPE_GRC)
7992                         continue;
7993                 if (reg_base == 0xffffffff)
7994                         reg_base = reg & BNXT_GRC_BASE_MASK;
7995                 if ((reg & BNXT_GRC_BASE_MASK) != reg_base)
7996                         return -ERANGE;
7997                 fw_health->mapped_regs[i] = BNXT_FW_HEALTH_WIN_OFF(reg);
7998         }
7999         bp->fw_health->status_reliable = true;
8000         bp->fw_health->resets_reliable = true;
8001         if (reg_base == 0xffffffff)
8002                 return 0;
8003
8004         __bnxt_map_fw_health_reg(bp, reg_base);
8005         return 0;
8006 }
8007
8008 static void bnxt_remap_fw_health_regs(struct bnxt *bp)
8009 {
8010         if (!bp->fw_health)
8011                 return;
8012
8013         if (bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY) {
8014                 bp->fw_health->status_reliable = true;
8015                 bp->fw_health->resets_reliable = true;
8016         } else {
8017                 bnxt_try_map_fw_health_reg(bp);
8018         }
8019 }
8020
8021 static int bnxt_hwrm_error_recovery_qcfg(struct bnxt *bp)
8022 {
8023         struct bnxt_fw_health *fw_health = bp->fw_health;
8024         struct hwrm_error_recovery_qcfg_output *resp;
8025         struct hwrm_error_recovery_qcfg_input *req;
8026         int rc, i;
8027
8028         if (!(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY))
8029                 return 0;
8030
8031         rc = hwrm_req_init(bp, req, HWRM_ERROR_RECOVERY_QCFG);
8032         if (rc)
8033                 return rc;
8034
8035         resp = hwrm_req_hold(bp, req);
8036         rc = hwrm_req_send(bp, req);
8037         if (rc)
8038                 goto err_recovery_out;
8039         fw_health->flags = le32_to_cpu(resp->flags);
8040         if ((fw_health->flags & ERROR_RECOVERY_QCFG_RESP_FLAGS_CO_CPU) &&
8041             !(bp->fw_cap & BNXT_FW_CAP_KONG_MB_CHNL)) {
8042                 rc = -EINVAL;
8043                 goto err_recovery_out;
8044         }
8045         fw_health->polling_dsecs = le32_to_cpu(resp->driver_polling_freq);
8046         fw_health->master_func_wait_dsecs =
8047                 le32_to_cpu(resp->master_func_wait_period);
8048         fw_health->normal_func_wait_dsecs =
8049                 le32_to_cpu(resp->normal_func_wait_period);
8050         fw_health->post_reset_wait_dsecs =
8051                 le32_to_cpu(resp->master_func_wait_period_after_reset);
8052         fw_health->post_reset_max_wait_dsecs =
8053                 le32_to_cpu(resp->max_bailout_time_after_reset);
8054         fw_health->regs[BNXT_FW_HEALTH_REG] =
8055                 le32_to_cpu(resp->fw_health_status_reg);
8056         fw_health->regs[BNXT_FW_HEARTBEAT_REG] =
8057                 le32_to_cpu(resp->fw_heartbeat_reg);
8058         fw_health->regs[BNXT_FW_RESET_CNT_REG] =
8059                 le32_to_cpu(resp->fw_reset_cnt_reg);
8060         fw_health->regs[BNXT_FW_RESET_INPROG_REG] =
8061                 le32_to_cpu(resp->reset_inprogress_reg);
8062         fw_health->fw_reset_inprog_reg_mask =
8063                 le32_to_cpu(resp->reset_inprogress_reg_mask);
8064         fw_health->fw_reset_seq_cnt = resp->reg_array_cnt;
8065         if (fw_health->fw_reset_seq_cnt >= 16) {
8066                 rc = -EINVAL;
8067                 goto err_recovery_out;
8068         }
8069         for (i = 0; i < fw_health->fw_reset_seq_cnt; i++) {
8070                 fw_health->fw_reset_seq_regs[i] =
8071                         le32_to_cpu(resp->reset_reg[i]);
8072                 fw_health->fw_reset_seq_vals[i] =
8073                         le32_to_cpu(resp->reset_reg_val[i]);
8074                 fw_health->fw_reset_seq_delay_msec[i] =
8075                         resp->delay_after_reset[i];
8076         }
8077 err_recovery_out:
8078         hwrm_req_drop(bp, req);
8079         if (!rc)
8080                 rc = bnxt_map_fw_health_regs(bp);
8081         if (rc)
8082                 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
8083         return rc;
8084 }
8085
8086 static int bnxt_hwrm_func_reset(struct bnxt *bp)
8087 {
8088         struct hwrm_func_reset_input *req;
8089         int rc;
8090
8091         rc = hwrm_req_init(bp, req, HWRM_FUNC_RESET);
8092         if (rc)
8093                 return rc;
8094
8095         req->enables = 0;
8096         hwrm_req_timeout(bp, req, HWRM_RESET_TIMEOUT);
8097         return hwrm_req_send(bp, req);
8098 }
8099
8100 static void bnxt_nvm_cfg_ver_get(struct bnxt *bp)
8101 {
8102         struct hwrm_nvm_get_dev_info_output nvm_info;
8103
8104         if (!bnxt_hwrm_nvm_get_dev_info(bp, &nvm_info))
8105                 snprintf(bp->nvm_cfg_ver, FW_VER_STR_LEN, "%d.%d.%d",
8106                          nvm_info.nvm_cfg_ver_maj, nvm_info.nvm_cfg_ver_min,
8107                          nvm_info.nvm_cfg_ver_upd);
8108 }
8109
8110 static int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
8111 {
8112         struct hwrm_queue_qportcfg_output *resp;
8113         struct hwrm_queue_qportcfg_input *req;
8114         u8 i, j, *qptr;
8115         bool no_rdma;
8116         int rc = 0;
8117
8118         rc = hwrm_req_init(bp, req, HWRM_QUEUE_QPORTCFG);
8119         if (rc)
8120                 return rc;
8121
8122         resp = hwrm_req_hold(bp, req);
8123         rc = hwrm_req_send(bp, req);
8124         if (rc)
8125                 goto qportcfg_exit;
8126
8127         if (!resp->max_configurable_queues) {
8128                 rc = -EINVAL;
8129                 goto qportcfg_exit;
8130         }
8131         bp->max_tc = resp->max_configurable_queues;
8132         bp->max_lltc = resp->max_configurable_lossless_queues;
8133         if (bp->max_tc > BNXT_MAX_QUEUE)
8134                 bp->max_tc = BNXT_MAX_QUEUE;
8135
8136         no_rdma = !(bp->flags & BNXT_FLAG_ROCE_CAP);
8137         qptr = &resp->queue_id0;
8138         for (i = 0, j = 0; i < bp->max_tc; i++) {
8139                 bp->q_info[j].queue_id = *qptr;
8140                 bp->q_ids[i] = *qptr++;
8141                 bp->q_info[j].queue_profile = *qptr++;
8142                 bp->tc_to_qidx[j] = j;
8143                 if (!BNXT_CNPQ(bp->q_info[j].queue_profile) ||
8144                     (no_rdma && BNXT_PF(bp)))
8145                         j++;
8146         }
8147         bp->max_q = bp->max_tc;
8148         bp->max_tc = max_t(u8, j, 1);
8149
8150         if (resp->queue_cfg_info & QUEUE_QPORTCFG_RESP_QUEUE_CFG_INFO_ASYM_CFG)
8151                 bp->max_tc = 1;
8152
8153         if (bp->max_lltc > bp->max_tc)
8154                 bp->max_lltc = bp->max_tc;
8155
8156 qportcfg_exit:
8157         hwrm_req_drop(bp, req);
8158         return rc;
8159 }
8160
8161 static int bnxt_hwrm_poll(struct bnxt *bp)
8162 {
8163         struct hwrm_ver_get_input *req;
8164         int rc;
8165
8166         rc = hwrm_req_init(bp, req, HWRM_VER_GET);
8167         if (rc)
8168                 return rc;
8169
8170         req->hwrm_intf_maj = HWRM_VERSION_MAJOR;
8171         req->hwrm_intf_min = HWRM_VERSION_MINOR;
8172         req->hwrm_intf_upd = HWRM_VERSION_UPDATE;
8173
8174         hwrm_req_flags(bp, req, BNXT_HWRM_CTX_SILENT | BNXT_HWRM_FULL_WAIT);
8175         rc = hwrm_req_send(bp, req);
8176         return rc;
8177 }
8178
8179 static int bnxt_hwrm_ver_get(struct bnxt *bp)
8180 {
8181         struct hwrm_ver_get_output *resp;
8182         struct hwrm_ver_get_input *req;
8183         u16 fw_maj, fw_min, fw_bld, fw_rsv;
8184         u32 dev_caps_cfg, hwrm_ver;
8185         int rc, len;
8186
8187         rc = hwrm_req_init(bp, req, HWRM_VER_GET);
8188         if (rc)
8189                 return rc;
8190
8191         hwrm_req_flags(bp, req, BNXT_HWRM_FULL_WAIT);
8192         bp->hwrm_max_req_len = HWRM_MAX_REQ_LEN;
8193         req->hwrm_intf_maj = HWRM_VERSION_MAJOR;
8194         req->hwrm_intf_min = HWRM_VERSION_MINOR;
8195         req->hwrm_intf_upd = HWRM_VERSION_UPDATE;
8196
8197         resp = hwrm_req_hold(bp, req);
8198         rc = hwrm_req_send(bp, req);
8199         if (rc)
8200                 goto hwrm_ver_get_exit;
8201
8202         memcpy(&bp->ver_resp, resp, sizeof(struct hwrm_ver_get_output));
8203
8204         bp->hwrm_spec_code = resp->hwrm_intf_maj_8b << 16 |
8205                              resp->hwrm_intf_min_8b << 8 |
8206                              resp->hwrm_intf_upd_8b;
8207         if (resp->hwrm_intf_maj_8b < 1) {
8208                 netdev_warn(bp->dev, "HWRM interface %d.%d.%d is older than 1.0.0.\n",
8209                             resp->hwrm_intf_maj_8b, resp->hwrm_intf_min_8b,
8210                             resp->hwrm_intf_upd_8b);
8211                 netdev_warn(bp->dev, "Please update firmware with HWRM interface 1.0.0 or newer.\n");
8212         }
8213
8214         hwrm_ver = HWRM_VERSION_MAJOR << 16 | HWRM_VERSION_MINOR << 8 |
8215                         HWRM_VERSION_UPDATE;
8216
8217         if (bp->hwrm_spec_code > hwrm_ver)
8218                 snprintf(bp->hwrm_ver_supp, FW_VER_STR_LEN, "%d.%d.%d",
8219                          HWRM_VERSION_MAJOR, HWRM_VERSION_MINOR,
8220                          HWRM_VERSION_UPDATE);
8221         else
8222                 snprintf(bp->hwrm_ver_supp, FW_VER_STR_LEN, "%d.%d.%d",
8223                          resp->hwrm_intf_maj_8b, resp->hwrm_intf_min_8b,
8224                          resp->hwrm_intf_upd_8b);
8225
8226         fw_maj = le16_to_cpu(resp->hwrm_fw_major);
8227         if (bp->hwrm_spec_code > 0x10803 && fw_maj) {
8228                 fw_min = le16_to_cpu(resp->hwrm_fw_minor);
8229                 fw_bld = le16_to_cpu(resp->hwrm_fw_build);
8230                 fw_rsv = le16_to_cpu(resp->hwrm_fw_patch);
8231                 len = FW_VER_STR_LEN;
8232         } else {
8233                 fw_maj = resp->hwrm_fw_maj_8b;
8234                 fw_min = resp->hwrm_fw_min_8b;
8235                 fw_bld = resp->hwrm_fw_bld_8b;
8236                 fw_rsv = resp->hwrm_fw_rsvd_8b;
8237                 len = BC_HWRM_STR_LEN;
8238         }
8239         bp->fw_ver_code = BNXT_FW_VER_CODE(fw_maj, fw_min, fw_bld, fw_rsv);
8240         snprintf(bp->fw_ver_str, len, "%d.%d.%d.%d", fw_maj, fw_min, fw_bld,
8241                  fw_rsv);
8242
8243         if (strlen(resp->active_pkg_name)) {
8244                 int fw_ver_len = strlen(bp->fw_ver_str);
8245
8246                 snprintf(bp->fw_ver_str + fw_ver_len,
8247                          FW_VER_STR_LEN - fw_ver_len - 1, "/pkg %s",
8248                          resp->active_pkg_name);
8249                 bp->fw_cap |= BNXT_FW_CAP_PKG_VER;
8250         }
8251
8252         bp->hwrm_cmd_timeout = le16_to_cpu(resp->def_req_timeout);
8253         if (!bp->hwrm_cmd_timeout)
8254                 bp->hwrm_cmd_timeout = DFLT_HWRM_CMD_TIMEOUT;
8255         bp->hwrm_cmd_max_timeout = le16_to_cpu(resp->max_req_timeout) * 1000;
8256         if (!bp->hwrm_cmd_max_timeout)
8257                 bp->hwrm_cmd_max_timeout = HWRM_CMD_MAX_TIMEOUT;
8258         else if (bp->hwrm_cmd_max_timeout > HWRM_CMD_MAX_TIMEOUT)
8259                 netdev_warn(bp->dev, "Device requests max timeout of %d seconds, may trigger hung task watchdog\n",
8260                             bp->hwrm_cmd_max_timeout / 1000);
8261
8262         if (resp->hwrm_intf_maj_8b >= 1) {
8263                 bp->hwrm_max_req_len = le16_to_cpu(resp->max_req_win_len);
8264                 bp->hwrm_max_ext_req_len = le16_to_cpu(resp->max_ext_req_len);
8265         }
8266         if (bp->hwrm_max_ext_req_len < HWRM_MAX_REQ_LEN)
8267                 bp->hwrm_max_ext_req_len = HWRM_MAX_REQ_LEN;
8268
8269         bp->chip_num = le16_to_cpu(resp->chip_num);
8270         bp->chip_rev = resp->chip_rev;
8271         if (bp->chip_num == CHIP_NUM_58700 && !resp->chip_rev &&
8272             !resp->chip_metal)
8273                 bp->flags |= BNXT_FLAG_CHIP_NITRO_A0;
8274
8275         dev_caps_cfg = le32_to_cpu(resp->dev_caps_cfg);
8276         if ((dev_caps_cfg & VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
8277             (dev_caps_cfg & VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_REQUIRED))
8278                 bp->fw_cap |= BNXT_FW_CAP_SHORT_CMD;
8279
8280         if (dev_caps_cfg & VER_GET_RESP_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED)
8281                 bp->fw_cap |= BNXT_FW_CAP_KONG_MB_CHNL;
8282
8283         if (dev_caps_cfg &
8284             VER_GET_RESP_DEV_CAPS_CFG_FLOW_HANDLE_64BIT_SUPPORTED)
8285                 bp->fw_cap |= BNXT_FW_CAP_OVS_64BIT_HANDLE;
8286
8287         if (dev_caps_cfg &
8288             VER_GET_RESP_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED)
8289                 bp->fw_cap |= BNXT_FW_CAP_TRUSTED_VF;
8290
8291         if (dev_caps_cfg &
8292             VER_GET_RESP_DEV_CAPS_CFG_CFA_ADV_FLOW_MGNT_SUPPORTED)
8293                 bp->fw_cap |= BNXT_FW_CAP_CFA_ADV_FLOW;
8294
8295 hwrm_ver_get_exit:
8296         hwrm_req_drop(bp, req);
8297         return rc;
8298 }
8299
8300 int bnxt_hwrm_fw_set_time(struct bnxt *bp)
8301 {
8302         struct hwrm_fw_set_time_input *req;
8303         struct tm tm;
8304         time64_t now = ktime_get_real_seconds();
8305         int rc;
8306
8307         if ((BNXT_VF(bp) && bp->hwrm_spec_code < 0x10901) ||
8308             bp->hwrm_spec_code < 0x10400)
8309                 return -EOPNOTSUPP;
8310
8311         time64_to_tm(now, 0, &tm);
8312         rc = hwrm_req_init(bp, req, HWRM_FW_SET_TIME);
8313         if (rc)
8314                 return rc;
8315
8316         req->year = cpu_to_le16(1900 + tm.tm_year);
8317         req->month = 1 + tm.tm_mon;
8318         req->day = tm.tm_mday;
8319         req->hour = tm.tm_hour;
8320         req->minute = tm.tm_min;
8321         req->second = tm.tm_sec;
8322         return hwrm_req_send(bp, req);
8323 }
8324
8325 static void bnxt_add_one_ctr(u64 hw, u64 *sw, u64 mask)
8326 {
8327         u64 sw_tmp;
8328
8329         hw &= mask;
8330         sw_tmp = (*sw & ~mask) | hw;
8331         if (hw < (*sw & mask))
8332                 sw_tmp += mask + 1;
8333         WRITE_ONCE(*sw, sw_tmp);
8334 }
8335
8336 static void __bnxt_accumulate_stats(__le64 *hw_stats, u64 *sw_stats, u64 *masks,
8337                                     int count, bool ignore_zero)
8338 {
8339         int i;
8340
8341         for (i = 0; i < count; i++) {
8342                 u64 hw = le64_to_cpu(READ_ONCE(hw_stats[i]));
8343
8344                 if (ignore_zero && !hw)
8345                         continue;
8346
8347                 if (masks[i] == -1ULL)
8348                         sw_stats[i] = hw;
8349                 else
8350                         bnxt_add_one_ctr(hw, &sw_stats[i], masks[i]);
8351         }
8352 }
8353
8354 static void bnxt_accumulate_stats(struct bnxt_stats_mem *stats)
8355 {
8356         if (!stats->hw_stats)
8357                 return;
8358
8359         __bnxt_accumulate_stats(stats->hw_stats, stats->sw_stats,
8360                                 stats->hw_masks, stats->len / 8, false);
8361 }
8362
8363 static void bnxt_accumulate_all_stats(struct bnxt *bp)
8364 {
8365         struct bnxt_stats_mem *ring0_stats;
8366         bool ignore_zero = false;
8367         int i;
8368
8369         /* Chip bug.  Counter intermittently becomes 0. */
8370         if (bp->flags & BNXT_FLAG_CHIP_P5)
8371                 ignore_zero = true;
8372
8373         for (i = 0; i < bp->cp_nr_rings; i++) {
8374                 struct bnxt_napi *bnapi = bp->bnapi[i];
8375                 struct bnxt_cp_ring_info *cpr;
8376                 struct bnxt_stats_mem *stats;
8377
8378                 cpr = &bnapi->cp_ring;
8379                 stats = &cpr->stats;
8380                 if (!i)
8381                         ring0_stats = stats;
8382                 __bnxt_accumulate_stats(stats->hw_stats, stats->sw_stats,
8383                                         ring0_stats->hw_masks,
8384                                         ring0_stats->len / 8, ignore_zero);
8385         }
8386         if (bp->flags & BNXT_FLAG_PORT_STATS) {
8387                 struct bnxt_stats_mem *stats = &bp->port_stats;
8388                 __le64 *hw_stats = stats->hw_stats;
8389                 u64 *sw_stats = stats->sw_stats;
8390                 u64 *masks = stats->hw_masks;
8391                 int cnt;
8392
8393                 cnt = sizeof(struct rx_port_stats) / 8;
8394                 __bnxt_accumulate_stats(hw_stats, sw_stats, masks, cnt, false);
8395
8396                 hw_stats += BNXT_TX_PORT_STATS_BYTE_OFFSET / 8;
8397                 sw_stats += BNXT_TX_PORT_STATS_BYTE_OFFSET / 8;
8398                 masks += BNXT_TX_PORT_STATS_BYTE_OFFSET / 8;
8399                 cnt = sizeof(struct tx_port_stats) / 8;
8400                 __bnxt_accumulate_stats(hw_stats, sw_stats, masks, cnt, false);
8401         }
8402         if (bp->flags & BNXT_FLAG_PORT_STATS_EXT) {
8403                 bnxt_accumulate_stats(&bp->rx_port_stats_ext);
8404                 bnxt_accumulate_stats(&bp->tx_port_stats_ext);
8405         }
8406 }
8407
8408 static int bnxt_hwrm_port_qstats(struct bnxt *bp, u8 flags)
8409 {
8410         struct hwrm_port_qstats_input *req;
8411         struct bnxt_pf_info *pf = &bp->pf;
8412         int rc;
8413
8414         if (!(bp->flags & BNXT_FLAG_PORT_STATS))
8415                 return 0;
8416
8417         if (flags && !(bp->fw_cap & BNXT_FW_CAP_EXT_HW_STATS_SUPPORTED))
8418                 return -EOPNOTSUPP;
8419
8420         rc = hwrm_req_init(bp, req, HWRM_PORT_QSTATS);
8421         if (rc)
8422                 return rc;
8423
8424         req->flags = flags;
8425         req->port_id = cpu_to_le16(pf->port_id);
8426         req->tx_stat_host_addr = cpu_to_le64(bp->port_stats.hw_stats_map +
8427                                             BNXT_TX_PORT_STATS_BYTE_OFFSET);
8428         req->rx_stat_host_addr = cpu_to_le64(bp->port_stats.hw_stats_map);
8429         return hwrm_req_send(bp, req);
8430 }
8431
8432 static int bnxt_hwrm_port_qstats_ext(struct bnxt *bp, u8 flags)
8433 {
8434         struct hwrm_queue_pri2cos_qcfg_output *resp_qc;
8435         struct hwrm_queue_pri2cos_qcfg_input *req_qc;
8436         struct hwrm_port_qstats_ext_output *resp_qs;
8437         struct hwrm_port_qstats_ext_input *req_qs;
8438         struct bnxt_pf_info *pf = &bp->pf;
8439         u32 tx_stat_size;
8440         int rc;
8441
8442         if (!(bp->flags & BNXT_FLAG_PORT_STATS_EXT))
8443                 return 0;
8444
8445         if (flags && !(bp->fw_cap & BNXT_FW_CAP_EXT_HW_STATS_SUPPORTED))
8446                 return -EOPNOTSUPP;
8447
8448         rc = hwrm_req_init(bp, req_qs, HWRM_PORT_QSTATS_EXT);
8449         if (rc)
8450                 return rc;
8451
8452         req_qs->flags = flags;
8453         req_qs->port_id = cpu_to_le16(pf->port_id);
8454         req_qs->rx_stat_size = cpu_to_le16(sizeof(struct rx_port_stats_ext));
8455         req_qs->rx_stat_host_addr = cpu_to_le64(bp->rx_port_stats_ext.hw_stats_map);
8456         tx_stat_size = bp->tx_port_stats_ext.hw_stats ?
8457                        sizeof(struct tx_port_stats_ext) : 0;
8458         req_qs->tx_stat_size = cpu_to_le16(tx_stat_size);
8459         req_qs->tx_stat_host_addr = cpu_to_le64(bp->tx_port_stats_ext.hw_stats_map);
8460         resp_qs = hwrm_req_hold(bp, req_qs);
8461         rc = hwrm_req_send(bp, req_qs);
8462         if (!rc) {
8463                 bp->fw_rx_stats_ext_size =
8464                         le16_to_cpu(resp_qs->rx_stat_size) / 8;
8465                 if (BNXT_FW_MAJ(bp) < 220 &&
8466                     bp->fw_rx_stats_ext_size > BNXT_RX_STATS_EXT_NUM_LEGACY)
8467                         bp->fw_rx_stats_ext_size = BNXT_RX_STATS_EXT_NUM_LEGACY;
8468
8469                 bp->fw_tx_stats_ext_size = tx_stat_size ?
8470                         le16_to_cpu(resp_qs->tx_stat_size) / 8 : 0;
8471         } else {
8472                 bp->fw_rx_stats_ext_size = 0;
8473                 bp->fw_tx_stats_ext_size = 0;
8474         }
8475         hwrm_req_drop(bp, req_qs);
8476
8477         if (flags)
8478                 return rc;
8479
8480         if (bp->fw_tx_stats_ext_size <=
8481             offsetof(struct tx_port_stats_ext, pfc_pri0_tx_duration_us) / 8) {
8482                 bp->pri2cos_valid = 0;
8483                 return rc;
8484         }
8485
8486         rc = hwrm_req_init(bp, req_qc, HWRM_QUEUE_PRI2COS_QCFG);
8487         if (rc)
8488                 return rc;
8489
8490         req_qc->flags = cpu_to_le32(QUEUE_PRI2COS_QCFG_REQ_FLAGS_IVLAN);
8491
8492         resp_qc = hwrm_req_hold(bp, req_qc);
8493         rc = hwrm_req_send(bp, req_qc);
8494         if (!rc) {
8495                 u8 *pri2cos;
8496                 int i, j;
8497
8498                 pri2cos = &resp_qc->pri0_cos_queue_id;
8499                 for (i = 0; i < 8; i++) {
8500                         u8 queue_id = pri2cos[i];
8501                         u8 queue_idx;
8502
8503                         /* Per port queue IDs start from 0, 10, 20, etc */
8504                         queue_idx = queue_id % 10;
8505                         if (queue_idx > BNXT_MAX_QUEUE) {
8506                                 bp->pri2cos_valid = false;
8507                                 hwrm_req_drop(bp, req_qc);
8508                                 return rc;
8509                         }
8510                         for (j = 0; j < bp->max_q; j++) {
8511                                 if (bp->q_ids[j] == queue_id)
8512                                         bp->pri2cos_idx[i] = queue_idx;
8513                         }
8514                 }
8515                 bp->pri2cos_valid = true;
8516         }
8517         hwrm_req_drop(bp, req_qc);
8518
8519         return rc;
8520 }
8521
8522 static void bnxt_hwrm_free_tunnel_ports(struct bnxt *bp)
8523 {
8524         bnxt_hwrm_tunnel_dst_port_free(bp,
8525                 TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN);
8526         bnxt_hwrm_tunnel_dst_port_free(bp,
8527                 TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE);
8528 }
8529
8530 static int bnxt_set_tpa(struct bnxt *bp, bool set_tpa)
8531 {
8532         int rc, i;
8533         u32 tpa_flags = 0;
8534
8535         if (set_tpa)
8536                 tpa_flags = bp->flags & BNXT_FLAG_TPA;
8537         else if (BNXT_NO_FW_ACCESS(bp))
8538                 return 0;
8539         for (i = 0; i < bp->nr_vnics; i++) {
8540                 rc = bnxt_hwrm_vnic_set_tpa(bp, i, tpa_flags);
8541                 if (rc) {
8542                         netdev_err(bp->dev, "hwrm vnic set tpa failure rc for vnic %d: %x\n",
8543                                    i, rc);
8544                         return rc;
8545                 }
8546         }
8547         return 0;
8548 }
8549
8550 static void bnxt_hwrm_clear_vnic_rss(struct bnxt *bp)
8551 {
8552         int i;
8553
8554         for (i = 0; i < bp->nr_vnics; i++)
8555                 bnxt_hwrm_vnic_set_rss(bp, i, false);
8556 }
8557
8558 static void bnxt_clear_vnic(struct bnxt *bp)
8559 {
8560         if (!bp->vnic_info)
8561                 return;
8562
8563         bnxt_hwrm_clear_vnic_filter(bp);
8564         if (!(bp->flags & BNXT_FLAG_CHIP_P5)) {
8565                 /* clear all RSS setting before free vnic ctx */
8566                 bnxt_hwrm_clear_vnic_rss(bp);
8567                 bnxt_hwrm_vnic_ctx_free(bp);
8568         }
8569         /* before free the vnic, undo the vnic tpa settings */
8570         if (bp->flags & BNXT_FLAG_TPA)
8571                 bnxt_set_tpa(bp, false);
8572         bnxt_hwrm_vnic_free(bp);
8573         if (bp->flags & BNXT_FLAG_CHIP_P5)
8574                 bnxt_hwrm_vnic_ctx_free(bp);
8575 }
8576
8577 static void bnxt_hwrm_resource_free(struct bnxt *bp, bool close_path,
8578                                     bool irq_re_init)
8579 {
8580         bnxt_clear_vnic(bp);
8581         bnxt_hwrm_ring_free(bp, close_path);
8582         bnxt_hwrm_ring_grp_free(bp);
8583         if (irq_re_init) {
8584                 bnxt_hwrm_stat_ctx_free(bp);
8585                 bnxt_hwrm_free_tunnel_ports(bp);
8586         }
8587 }
8588
8589 static int bnxt_hwrm_set_br_mode(struct bnxt *bp, u16 br_mode)
8590 {
8591         struct hwrm_func_cfg_input *req;
8592         u8 evb_mode;
8593         int rc;
8594
8595         if (br_mode == BRIDGE_MODE_VEB)
8596                 evb_mode = FUNC_CFG_REQ_EVB_MODE_VEB;
8597         else if (br_mode == BRIDGE_MODE_VEPA)
8598                 evb_mode = FUNC_CFG_REQ_EVB_MODE_VEPA;
8599         else
8600                 return -EINVAL;
8601
8602         rc = hwrm_req_init(bp, req, HWRM_FUNC_CFG);
8603         if (rc)
8604                 return rc;
8605
8606         req->fid = cpu_to_le16(0xffff);
8607         req->enables = cpu_to_le32(FUNC_CFG_REQ_ENABLES_EVB_MODE);
8608         req->evb_mode = evb_mode;
8609         return hwrm_req_send(bp, req);
8610 }
8611
8612 static int bnxt_hwrm_set_cache_line_size(struct bnxt *bp, int size)
8613 {
8614         struct hwrm_func_cfg_input *req;
8615         int rc;
8616
8617         if (BNXT_VF(bp) || bp->hwrm_spec_code < 0x10803)
8618                 return 0;
8619
8620         rc = hwrm_req_init(bp, req, HWRM_FUNC_CFG);
8621         if (rc)
8622                 return rc;
8623
8624         req->fid = cpu_to_le16(0xffff);
8625         req->enables = cpu_to_le32(FUNC_CFG_REQ_ENABLES_CACHE_LINESIZE);
8626         req->options = FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_64;
8627         if (size == 128)
8628                 req->options = FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_128;
8629
8630         return hwrm_req_send(bp, req);
8631 }
8632
8633 static int __bnxt_setup_vnic(struct bnxt *bp, u16 vnic_id)
8634 {
8635         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
8636         int rc;
8637
8638         if (vnic->flags & BNXT_VNIC_RFS_NEW_RSS_FLAG)
8639                 goto skip_rss_ctx;
8640
8641         /* allocate context for vnic */
8642         rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic_id, 0);
8643         if (rc) {
8644                 netdev_err(bp->dev, "hwrm vnic %d alloc failure rc: %x\n",
8645                            vnic_id, rc);
8646                 goto vnic_setup_err;
8647         }
8648         bp->rsscos_nr_ctxs++;
8649
8650         if (BNXT_CHIP_TYPE_NITRO_A0(bp)) {
8651                 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic_id, 1);
8652                 if (rc) {
8653                         netdev_err(bp->dev, "hwrm vnic %d cos ctx alloc failure rc: %x\n",
8654                                    vnic_id, rc);
8655                         goto vnic_setup_err;
8656                 }
8657                 bp->rsscos_nr_ctxs++;
8658         }
8659
8660 skip_rss_ctx:
8661         /* configure default vnic, ring grp */
8662         rc = bnxt_hwrm_vnic_cfg(bp, vnic_id);
8663         if (rc) {
8664                 netdev_err(bp->dev, "hwrm vnic %d cfg failure rc: %x\n",
8665                            vnic_id, rc);
8666                 goto vnic_setup_err;
8667         }
8668
8669         /* Enable RSS hashing on vnic */
8670         rc = bnxt_hwrm_vnic_set_rss(bp, vnic_id, true);
8671         if (rc) {
8672                 netdev_err(bp->dev, "hwrm vnic %d set rss failure rc: %x\n",
8673                            vnic_id, rc);
8674                 goto vnic_setup_err;
8675         }
8676
8677         if (bp->flags & BNXT_FLAG_AGG_RINGS) {
8678                 rc = bnxt_hwrm_vnic_set_hds(bp, vnic_id);
8679                 if (rc) {
8680                         netdev_err(bp->dev, "hwrm vnic %d set hds failure rc: %x\n",
8681                                    vnic_id, rc);
8682                 }
8683         }
8684
8685 vnic_setup_err:
8686         return rc;
8687 }
8688
8689 static int __bnxt_setup_vnic_p5(struct bnxt *bp, u16 vnic_id)
8690 {
8691         int rc, i, nr_ctxs;
8692
8693         nr_ctxs = bnxt_get_nr_rss_ctxs(bp, bp->rx_nr_rings);
8694         for (i = 0; i < nr_ctxs; i++) {
8695                 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic_id, i);
8696                 if (rc) {
8697                         netdev_err(bp->dev, "hwrm vnic %d ctx %d alloc failure rc: %x\n",
8698                                    vnic_id, i, rc);
8699                         break;
8700                 }
8701                 bp->rsscos_nr_ctxs++;
8702         }
8703         if (i < nr_ctxs)
8704                 return -ENOMEM;
8705
8706         rc = bnxt_hwrm_vnic_set_rss_p5(bp, vnic_id, true);
8707         if (rc) {
8708                 netdev_err(bp->dev, "hwrm vnic %d set rss failure rc: %d\n",
8709                            vnic_id, rc);
8710                 return rc;
8711         }
8712         rc = bnxt_hwrm_vnic_cfg(bp, vnic_id);
8713         if (rc) {
8714                 netdev_err(bp->dev, "hwrm vnic %d cfg failure rc: %x\n",
8715                            vnic_id, rc);
8716                 return rc;
8717         }
8718         if (bp->flags & BNXT_FLAG_AGG_RINGS) {
8719                 rc = bnxt_hwrm_vnic_set_hds(bp, vnic_id);
8720                 if (rc) {
8721                         netdev_err(bp->dev, "hwrm vnic %d set hds failure rc: %x\n",
8722                                    vnic_id, rc);
8723                 }
8724         }
8725         return rc;
8726 }
8727
8728 static int bnxt_setup_vnic(struct bnxt *bp, u16 vnic_id)
8729 {
8730         if (bp->flags & BNXT_FLAG_CHIP_P5)
8731                 return __bnxt_setup_vnic_p5(bp, vnic_id);
8732         else
8733                 return __bnxt_setup_vnic(bp, vnic_id);
8734 }
8735
8736 static int bnxt_alloc_rfs_vnics(struct bnxt *bp)
8737 {
8738 #ifdef CONFIG_RFS_ACCEL
8739         int i, rc = 0;
8740
8741         if (bp->flags & BNXT_FLAG_CHIP_P5)
8742                 return 0;
8743
8744         for (i = 0; i < bp->rx_nr_rings; i++) {
8745                 struct bnxt_vnic_info *vnic;
8746                 u16 vnic_id = i + 1;
8747                 u16 ring_id = i;
8748
8749                 if (vnic_id >= bp->nr_vnics)
8750                         break;
8751
8752                 vnic = &bp->vnic_info[vnic_id];
8753                 vnic->flags |= BNXT_VNIC_RFS_FLAG;
8754                 if (bp->flags & BNXT_FLAG_NEW_RSS_CAP)
8755                         vnic->flags |= BNXT_VNIC_RFS_NEW_RSS_FLAG;
8756                 rc = bnxt_hwrm_vnic_alloc(bp, vnic_id, ring_id, 1);
8757                 if (rc) {
8758                         netdev_err(bp->dev, "hwrm vnic %d alloc failure rc: %x\n",
8759                                    vnic_id, rc);
8760                         break;
8761                 }
8762                 rc = bnxt_setup_vnic(bp, vnic_id);
8763                 if (rc)
8764                         break;
8765         }
8766         return rc;
8767 #else
8768         return 0;
8769 #endif
8770 }
8771
8772 /* Allow PF, trusted VFs and VFs with default VLAN to be in promiscuous mode */
8773 static bool bnxt_promisc_ok(struct bnxt *bp)
8774 {
8775 #ifdef CONFIG_BNXT_SRIOV
8776         if (BNXT_VF(bp) && !bp->vf.vlan && !bnxt_is_trusted_vf(bp, &bp->vf))
8777                 return false;
8778 #endif
8779         return true;
8780 }
8781
8782 static int bnxt_setup_nitroa0_vnic(struct bnxt *bp)
8783 {
8784         unsigned int rc = 0;
8785
8786         rc = bnxt_hwrm_vnic_alloc(bp, 1, bp->rx_nr_rings - 1, 1);
8787         if (rc) {
8788                 netdev_err(bp->dev, "Cannot allocate special vnic for NS2 A0: %x\n",
8789                            rc);
8790                 return rc;
8791         }
8792
8793         rc = bnxt_hwrm_vnic_cfg(bp, 1);
8794         if (rc) {
8795                 netdev_err(bp->dev, "Cannot allocate special vnic for NS2 A0: %x\n",
8796                            rc);
8797                 return rc;
8798         }
8799         return rc;
8800 }
8801
8802 static int bnxt_cfg_rx_mode(struct bnxt *);
8803 static bool bnxt_mc_list_updated(struct bnxt *, u32 *);
8804
8805 static int bnxt_init_chip(struct bnxt *bp, bool irq_re_init)
8806 {
8807         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
8808         int rc = 0;
8809         unsigned int rx_nr_rings = bp->rx_nr_rings;
8810
8811         if (irq_re_init) {
8812                 rc = bnxt_hwrm_stat_ctx_alloc(bp);
8813                 if (rc) {
8814                         netdev_err(bp->dev, "hwrm stat ctx alloc failure rc: %x\n",
8815                                    rc);
8816                         goto err_out;
8817                 }
8818         }
8819
8820         rc = bnxt_hwrm_ring_alloc(bp);
8821         if (rc) {
8822                 netdev_err(bp->dev, "hwrm ring alloc failure rc: %x\n", rc);
8823                 goto err_out;
8824         }
8825
8826         rc = bnxt_hwrm_ring_grp_alloc(bp);
8827         if (rc) {
8828                 netdev_err(bp->dev, "hwrm_ring_grp alloc failure: %x\n", rc);
8829                 goto err_out;
8830         }
8831
8832         if (BNXT_CHIP_TYPE_NITRO_A0(bp))
8833                 rx_nr_rings--;
8834
8835         /* default vnic 0 */
8836         rc = bnxt_hwrm_vnic_alloc(bp, 0, 0, rx_nr_rings);
8837         if (rc) {
8838                 netdev_err(bp->dev, "hwrm vnic alloc failure rc: %x\n", rc);
8839                 goto err_out;
8840         }
8841
8842         rc = bnxt_setup_vnic(bp, 0);
8843         if (rc)
8844                 goto err_out;
8845         if (bp->fw_cap & BNXT_FW_CAP_RSS_HASH_TYPE_DELTA)
8846                 bnxt_hwrm_update_rss_hash_cfg(bp);
8847
8848         if (bp->flags & BNXT_FLAG_RFS) {
8849                 rc = bnxt_alloc_rfs_vnics(bp);
8850                 if (rc)
8851                         goto err_out;
8852         }
8853
8854         if (bp->flags & BNXT_FLAG_TPA) {
8855                 rc = bnxt_set_tpa(bp, true);
8856                 if (rc)
8857                         goto err_out;
8858         }
8859
8860         if (BNXT_VF(bp))
8861                 bnxt_update_vf_mac(bp);
8862
8863         /* Filter for default vnic 0 */
8864         rc = bnxt_hwrm_set_vnic_filter(bp, 0, 0, bp->dev->dev_addr);
8865         if (rc) {
8866                 if (BNXT_VF(bp) && rc == -ENODEV)
8867                         netdev_err(bp->dev, "Cannot configure L2 filter while PF is unavailable\n");
8868                 else
8869                         netdev_err(bp->dev, "HWRM vnic filter failure rc: %x\n", rc);
8870                 goto err_out;
8871         }
8872         vnic->uc_filter_count = 1;
8873
8874         vnic->rx_mask = 0;
8875         if (test_bit(BNXT_STATE_HALF_OPEN, &bp->state))
8876                 goto skip_rx_mask;
8877
8878         if (bp->dev->flags & IFF_BROADCAST)
8879                 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_BCAST;
8880
8881         if (bp->dev->flags & IFF_PROMISC)
8882                 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS;
8883
8884         if (bp->dev->flags & IFF_ALLMULTI) {
8885                 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST;
8886                 vnic->mc_list_count = 0;
8887         } else if (bp->dev->flags & IFF_MULTICAST) {
8888                 u32 mask = 0;
8889
8890                 bnxt_mc_list_updated(bp, &mask);
8891                 vnic->rx_mask |= mask;
8892         }
8893
8894         rc = bnxt_cfg_rx_mode(bp);
8895         if (rc)
8896                 goto err_out;
8897
8898 skip_rx_mask:
8899         rc = bnxt_hwrm_set_coal(bp);
8900         if (rc)
8901                 netdev_warn(bp->dev, "HWRM set coalescing failure rc: %x\n",
8902                                 rc);
8903
8904         if (BNXT_CHIP_TYPE_NITRO_A0(bp)) {
8905                 rc = bnxt_setup_nitroa0_vnic(bp);
8906                 if (rc)
8907                         netdev_err(bp->dev, "Special vnic setup failure for NS2 A0 rc: %x\n",
8908                                    rc);
8909         }
8910
8911         if (BNXT_VF(bp)) {
8912                 bnxt_hwrm_func_qcfg(bp);
8913                 netdev_update_features(bp->dev);
8914         }
8915
8916         return 0;
8917
8918 err_out:
8919         bnxt_hwrm_resource_free(bp, 0, true);
8920
8921         return rc;
8922 }
8923
8924 static int bnxt_shutdown_nic(struct bnxt *bp, bool irq_re_init)
8925 {
8926         bnxt_hwrm_resource_free(bp, 1, irq_re_init);
8927         return 0;
8928 }
8929
8930 static int bnxt_init_nic(struct bnxt *bp, bool irq_re_init)
8931 {
8932         bnxt_init_cp_rings(bp);
8933         bnxt_init_rx_rings(bp);
8934         bnxt_init_tx_rings(bp);
8935         bnxt_init_ring_grps(bp, irq_re_init);
8936         bnxt_init_vnics(bp);
8937
8938         return bnxt_init_chip(bp, irq_re_init);
8939 }
8940
8941 static int bnxt_set_real_num_queues(struct bnxt *bp)
8942 {
8943         int rc;
8944         struct net_device *dev = bp->dev;
8945
8946         rc = netif_set_real_num_tx_queues(dev, bp->tx_nr_rings -
8947                                           bp->tx_nr_rings_xdp);
8948         if (rc)
8949                 return rc;
8950
8951         rc = netif_set_real_num_rx_queues(dev, bp->rx_nr_rings);
8952         if (rc)
8953                 return rc;
8954
8955 #ifdef CONFIG_RFS_ACCEL
8956         if (bp->flags & BNXT_FLAG_RFS)
8957                 dev->rx_cpu_rmap = alloc_irq_cpu_rmap(bp->rx_nr_rings);
8958 #endif
8959
8960         return rc;
8961 }
8962
8963 static int bnxt_trim_rings(struct bnxt *bp, int *rx, int *tx, int max,
8964                            bool shared)
8965 {
8966         int _rx = *rx, _tx = *tx;
8967
8968         if (shared) {
8969                 *rx = min_t(int, _rx, max);
8970                 *tx = min_t(int, _tx, max);
8971         } else {
8972                 if (max < 2)
8973                         return -ENOMEM;
8974
8975                 while (_rx + _tx > max) {
8976                         if (_rx > _tx && _rx > 1)
8977                                 _rx--;
8978                         else if (_tx > 1)
8979                                 _tx--;
8980                 }
8981                 *rx = _rx;
8982                 *tx = _tx;
8983         }
8984         return 0;
8985 }
8986
8987 static void bnxt_setup_msix(struct bnxt *bp)
8988 {
8989         const int len = sizeof(bp->irq_tbl[0].name);
8990         struct net_device *dev = bp->dev;
8991         int tcs, i;
8992
8993         tcs = netdev_get_num_tc(dev);
8994         if (tcs) {
8995                 int i, off, count;
8996
8997                 for (i = 0; i < tcs; i++) {
8998                         count = bp->tx_nr_rings_per_tc;
8999                         off = i * count;
9000                         netdev_set_tc_queue(dev, i, count, off);
9001                 }
9002         }
9003
9004         for (i = 0; i < bp->cp_nr_rings; i++) {
9005                 int map_idx = bnxt_cp_num_to_irq_num(bp, i);
9006                 char *attr;
9007
9008                 if (bp->flags & BNXT_FLAG_SHARED_RINGS)
9009                         attr = "TxRx";
9010                 else if (i < bp->rx_nr_rings)
9011                         attr = "rx";
9012                 else
9013                         attr = "tx";
9014
9015                 snprintf(bp->irq_tbl[map_idx].name, len, "%s-%s-%d", dev->name,
9016                          attr, i);
9017                 bp->irq_tbl[map_idx].handler = bnxt_msix;
9018         }
9019 }
9020
9021 static void bnxt_setup_inta(struct bnxt *bp)
9022 {
9023         const int len = sizeof(bp->irq_tbl[0].name);
9024
9025         if (netdev_get_num_tc(bp->dev))
9026                 netdev_reset_tc(bp->dev);
9027
9028         snprintf(bp->irq_tbl[0].name, len, "%s-%s-%d", bp->dev->name, "TxRx",
9029                  0);
9030         bp->irq_tbl[0].handler = bnxt_inta;
9031 }
9032
9033 static int bnxt_init_int_mode(struct bnxt *bp);
9034
9035 static int bnxt_setup_int_mode(struct bnxt *bp)
9036 {
9037         int rc;
9038
9039         if (!bp->irq_tbl) {
9040                 rc = bnxt_init_int_mode(bp);
9041                 if (rc || !bp->irq_tbl)
9042                         return rc ?: -ENODEV;
9043         }
9044
9045         if (bp->flags & BNXT_FLAG_USING_MSIX)
9046                 bnxt_setup_msix(bp);
9047         else
9048                 bnxt_setup_inta(bp);
9049
9050         rc = bnxt_set_real_num_queues(bp);
9051         return rc;
9052 }
9053
9054 #ifdef CONFIG_RFS_ACCEL
9055 static unsigned int bnxt_get_max_func_rss_ctxs(struct bnxt *bp)
9056 {
9057         return bp->hw_resc.max_rsscos_ctxs;
9058 }
9059
9060 static unsigned int bnxt_get_max_func_vnics(struct bnxt *bp)
9061 {
9062         return bp->hw_resc.max_vnics;
9063 }
9064 #endif
9065
9066 unsigned int bnxt_get_max_func_stat_ctxs(struct bnxt *bp)
9067 {
9068         return bp->hw_resc.max_stat_ctxs;
9069 }
9070
9071 unsigned int bnxt_get_max_func_cp_rings(struct bnxt *bp)
9072 {
9073         return bp->hw_resc.max_cp_rings;
9074 }
9075
9076 static unsigned int bnxt_get_max_func_cp_rings_for_en(struct bnxt *bp)
9077 {
9078         unsigned int cp = bp->hw_resc.max_cp_rings;
9079
9080         if (!(bp->flags & BNXT_FLAG_CHIP_P5))
9081                 cp -= bnxt_get_ulp_msix_num(bp);
9082
9083         return cp;
9084 }
9085
9086 static unsigned int bnxt_get_max_func_irqs(struct bnxt *bp)
9087 {
9088         struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
9089
9090         if (bp->flags & BNXT_FLAG_CHIP_P5)
9091                 return min_t(unsigned int, hw_resc->max_irqs, hw_resc->max_nqs);
9092
9093         return min_t(unsigned int, hw_resc->max_irqs, hw_resc->max_cp_rings);
9094 }
9095
9096 static void bnxt_set_max_func_irqs(struct bnxt *bp, unsigned int max_irqs)
9097 {
9098         bp->hw_resc.max_irqs = max_irqs;
9099 }
9100
9101 unsigned int bnxt_get_avail_cp_rings_for_en(struct bnxt *bp)
9102 {
9103         unsigned int cp;
9104
9105         cp = bnxt_get_max_func_cp_rings_for_en(bp);
9106         if (bp->flags & BNXT_FLAG_CHIP_P5)
9107                 return cp - bp->rx_nr_rings - bp->tx_nr_rings;
9108         else
9109                 return cp - bp->cp_nr_rings;
9110 }
9111
9112 unsigned int bnxt_get_avail_stat_ctxs_for_en(struct bnxt *bp)
9113 {
9114         return bnxt_get_max_func_stat_ctxs(bp) - bnxt_get_func_stat_ctxs(bp);
9115 }
9116
9117 int bnxt_get_avail_msix(struct bnxt *bp, int num)
9118 {
9119         int max_cp = bnxt_get_max_func_cp_rings(bp);
9120         int max_irq = bnxt_get_max_func_irqs(bp);
9121         int total_req = bp->cp_nr_rings + num;
9122         int max_idx, avail_msix;
9123
9124         max_idx = bp->total_irqs;
9125         if (!(bp->flags & BNXT_FLAG_CHIP_P5))
9126                 max_idx = min_t(int, bp->total_irqs, max_cp);
9127         avail_msix = max_idx - bp->cp_nr_rings;
9128         if (!BNXT_NEW_RM(bp) || avail_msix >= num)
9129                 return avail_msix;
9130
9131         if (max_irq < total_req) {
9132                 num = max_irq - bp->cp_nr_rings;
9133                 if (num <= 0)
9134                         return 0;
9135         }
9136         return num;
9137 }
9138
9139 static int bnxt_get_num_msix(struct bnxt *bp)
9140 {
9141         if (!BNXT_NEW_RM(bp))
9142                 return bnxt_get_max_func_irqs(bp);
9143
9144         return bnxt_nq_rings_in_use(bp);
9145 }
9146
9147 static int bnxt_init_msix(struct bnxt *bp)
9148 {
9149         int i, total_vecs, max, rc = 0, min = 1, ulp_msix;
9150         struct msix_entry *msix_ent;
9151
9152         total_vecs = bnxt_get_num_msix(bp);
9153         max = bnxt_get_max_func_irqs(bp);
9154         if (total_vecs > max)
9155                 total_vecs = max;
9156
9157         if (!total_vecs)
9158                 return 0;
9159
9160         msix_ent = kcalloc(total_vecs, sizeof(struct msix_entry), GFP_KERNEL);
9161         if (!msix_ent)
9162                 return -ENOMEM;
9163
9164         for (i = 0; i < total_vecs; i++) {
9165                 msix_ent[i].entry = i;
9166                 msix_ent[i].vector = 0;
9167         }
9168
9169         if (!(bp->flags & BNXT_FLAG_SHARED_RINGS))
9170                 min = 2;
9171
9172         total_vecs = pci_enable_msix_range(bp->pdev, msix_ent, min, total_vecs);
9173         ulp_msix = bnxt_get_ulp_msix_num(bp);
9174         if (total_vecs < 0 || total_vecs < ulp_msix) {
9175                 rc = -ENODEV;
9176                 goto msix_setup_exit;
9177         }
9178
9179         bp->irq_tbl = kcalloc(total_vecs, sizeof(struct bnxt_irq), GFP_KERNEL);
9180         if (bp->irq_tbl) {
9181                 for (i = 0; i < total_vecs; i++)
9182                         bp->irq_tbl[i].vector = msix_ent[i].vector;
9183
9184                 bp->total_irqs = total_vecs;
9185                 /* Trim rings based upon num of vectors allocated */
9186                 rc = bnxt_trim_rings(bp, &bp->rx_nr_rings, &bp->tx_nr_rings,
9187                                      total_vecs - ulp_msix, min == 1);
9188                 if (rc)
9189                         goto msix_setup_exit;
9190
9191                 bp->cp_nr_rings = (min == 1) ?
9192                                   max_t(int, bp->tx_nr_rings, bp->rx_nr_rings) :
9193                                   bp->tx_nr_rings + bp->rx_nr_rings;
9194
9195         } else {
9196                 rc = -ENOMEM;
9197                 goto msix_setup_exit;
9198         }
9199         bp->flags |= BNXT_FLAG_USING_MSIX;
9200         kfree(msix_ent);
9201         return 0;
9202
9203 msix_setup_exit:
9204         netdev_err(bp->dev, "bnxt_init_msix err: %x\n", rc);
9205         kfree(bp->irq_tbl);
9206         bp->irq_tbl = NULL;
9207         pci_disable_msix(bp->pdev);
9208         kfree(msix_ent);
9209         return rc;
9210 }
9211
9212 static int bnxt_init_inta(struct bnxt *bp)
9213 {
9214         bp->irq_tbl = kzalloc(sizeof(struct bnxt_irq), GFP_KERNEL);
9215         if (!bp->irq_tbl)
9216                 return -ENOMEM;
9217
9218         bp->total_irqs = 1;
9219         bp->rx_nr_rings = 1;
9220         bp->tx_nr_rings = 1;
9221         bp->cp_nr_rings = 1;
9222         bp->flags |= BNXT_FLAG_SHARED_RINGS;
9223         bp->irq_tbl[0].vector = bp->pdev->irq;
9224         return 0;
9225 }
9226
9227 static int bnxt_init_int_mode(struct bnxt *bp)
9228 {
9229         int rc = -ENODEV;
9230
9231         if (bp->flags & BNXT_FLAG_MSIX_CAP)
9232                 rc = bnxt_init_msix(bp);
9233
9234         if (!(bp->flags & BNXT_FLAG_USING_MSIX) && BNXT_PF(bp)) {
9235                 /* fallback to INTA */
9236                 rc = bnxt_init_inta(bp);
9237         }
9238         return rc;
9239 }
9240
9241 static void bnxt_clear_int_mode(struct bnxt *bp)
9242 {
9243         if (bp->flags & BNXT_FLAG_USING_MSIX)
9244                 pci_disable_msix(bp->pdev);
9245
9246         kfree(bp->irq_tbl);
9247         bp->irq_tbl = NULL;
9248         bp->flags &= ~BNXT_FLAG_USING_MSIX;
9249 }
9250
9251 int bnxt_reserve_rings(struct bnxt *bp, bool irq_re_init)
9252 {
9253         int tcs = netdev_get_num_tc(bp->dev);
9254         bool irq_cleared = false;
9255         int rc;
9256
9257         if (!bnxt_need_reserve_rings(bp))
9258                 return 0;
9259
9260         if (irq_re_init && BNXT_NEW_RM(bp) &&
9261             bnxt_get_num_msix(bp) != bp->total_irqs) {
9262                 bnxt_ulp_irq_stop(bp);
9263                 bnxt_clear_int_mode(bp);
9264                 irq_cleared = true;
9265         }
9266         rc = __bnxt_reserve_rings(bp);
9267         if (irq_cleared) {
9268                 if (!rc)
9269                         rc = bnxt_init_int_mode(bp);
9270                 bnxt_ulp_irq_restart(bp, rc);
9271         }
9272         if (rc) {
9273                 netdev_err(bp->dev, "ring reservation/IRQ init failure rc: %d\n", rc);
9274                 return rc;
9275         }
9276         if (tcs && (bp->tx_nr_rings_per_tc * tcs !=
9277                     bp->tx_nr_rings - bp->tx_nr_rings_xdp)) {
9278                 netdev_err(bp->dev, "tx ring reservation failure\n");
9279                 netdev_reset_tc(bp->dev);
9280                 if (bp->tx_nr_rings_xdp)
9281                         bp->tx_nr_rings_per_tc = bp->tx_nr_rings_xdp;
9282                 else
9283                         bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
9284                 return -ENOMEM;
9285         }
9286         return 0;
9287 }
9288
9289 static void bnxt_free_irq(struct bnxt *bp)
9290 {
9291         struct bnxt_irq *irq;
9292         int i;
9293
9294 #ifdef CONFIG_RFS_ACCEL
9295         free_irq_cpu_rmap(bp->dev->rx_cpu_rmap);
9296         bp->dev->rx_cpu_rmap = NULL;
9297 #endif
9298         if (!bp->irq_tbl || !bp->bnapi)
9299                 return;
9300
9301         for (i = 0; i < bp->cp_nr_rings; i++) {
9302                 int map_idx = bnxt_cp_num_to_irq_num(bp, i);
9303
9304                 irq = &bp->irq_tbl[map_idx];
9305                 if (irq->requested) {
9306                         if (irq->have_cpumask) {
9307                                 irq_set_affinity_hint(irq->vector, NULL);
9308                                 free_cpumask_var(irq->cpu_mask);
9309                                 irq->have_cpumask = 0;
9310                         }
9311                         free_irq(irq->vector, bp->bnapi[i]);
9312                 }
9313
9314                 irq->requested = 0;
9315         }
9316 }
9317
9318 static int bnxt_request_irq(struct bnxt *bp)
9319 {
9320         int i, j, rc = 0;
9321         unsigned long flags = 0;
9322 #ifdef CONFIG_RFS_ACCEL
9323         struct cpu_rmap *rmap;
9324 #endif
9325
9326         rc = bnxt_setup_int_mode(bp);
9327         if (rc) {
9328                 netdev_err(bp->dev, "bnxt_setup_int_mode err: %x\n",
9329                            rc);
9330                 return rc;
9331         }
9332 #ifdef CONFIG_RFS_ACCEL
9333         rmap = bp->dev->rx_cpu_rmap;
9334 #endif
9335         if (!(bp->flags & BNXT_FLAG_USING_MSIX))
9336                 flags = IRQF_SHARED;
9337
9338         for (i = 0, j = 0; i < bp->cp_nr_rings; i++) {
9339                 int map_idx = bnxt_cp_num_to_irq_num(bp, i);
9340                 struct bnxt_irq *irq = &bp->irq_tbl[map_idx];
9341
9342 #ifdef CONFIG_RFS_ACCEL
9343                 if (rmap && bp->bnapi[i]->rx_ring) {
9344                         rc = irq_cpu_rmap_add(rmap, irq->vector);
9345                         if (rc)
9346                                 netdev_warn(bp->dev, "failed adding irq rmap for ring %d\n",
9347                                             j);
9348                         j++;
9349                 }
9350 #endif
9351                 rc = request_irq(irq->vector, irq->handler, flags, irq->name,
9352                                  bp->bnapi[i]);
9353                 if (rc)
9354                         break;
9355
9356                 irq->requested = 1;
9357
9358                 if (zalloc_cpumask_var(&irq->cpu_mask, GFP_KERNEL)) {
9359                         int numa_node = dev_to_node(&bp->pdev->dev);
9360
9361                         irq->have_cpumask = 1;
9362                         cpumask_set_cpu(cpumask_local_spread(i, numa_node),
9363                                         irq->cpu_mask);
9364                         rc = irq_set_affinity_hint(irq->vector, irq->cpu_mask);
9365                         if (rc) {
9366                                 netdev_warn(bp->dev,
9367                                             "Set affinity failed, IRQ = %d\n",
9368                                             irq->vector);
9369                                 break;
9370                         }
9371                 }
9372         }
9373         return rc;
9374 }
9375
9376 static void bnxt_del_napi(struct bnxt *bp)
9377 {
9378         int i;
9379
9380         if (!bp->bnapi)
9381                 return;
9382
9383         for (i = 0; i < bp->cp_nr_rings; i++) {
9384                 struct bnxt_napi *bnapi = bp->bnapi[i];
9385
9386                 __netif_napi_del(&bnapi->napi);
9387         }
9388         /* We called __netif_napi_del(), we need
9389          * to respect an RCU grace period before freeing napi structures.
9390          */
9391         synchronize_net();
9392 }
9393
9394 static void bnxt_init_napi(struct bnxt *bp)
9395 {
9396         int i;
9397         unsigned int cp_nr_rings = bp->cp_nr_rings;
9398         struct bnxt_napi *bnapi;
9399
9400         if (bp->flags & BNXT_FLAG_USING_MSIX) {
9401                 int (*poll_fn)(struct napi_struct *, int) = bnxt_poll;
9402
9403                 if (bp->flags & BNXT_FLAG_CHIP_P5)
9404                         poll_fn = bnxt_poll_p5;
9405                 else if (BNXT_CHIP_TYPE_NITRO_A0(bp))
9406                         cp_nr_rings--;
9407                 for (i = 0; i < cp_nr_rings; i++) {
9408                         bnapi = bp->bnapi[i];
9409                         netif_napi_add(bp->dev, &bnapi->napi, poll_fn);
9410                 }
9411                 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) {
9412                         bnapi = bp->bnapi[cp_nr_rings];
9413                         netif_napi_add(bp->dev, &bnapi->napi,
9414                                        bnxt_poll_nitroa0);
9415                 }
9416         } else {
9417                 bnapi = bp->bnapi[0];
9418                 netif_napi_add(bp->dev, &bnapi->napi, bnxt_poll);
9419         }
9420 }
9421
9422 static void bnxt_disable_napi(struct bnxt *bp)
9423 {
9424         int i;
9425
9426         if (!bp->bnapi ||
9427             test_and_set_bit(BNXT_STATE_NAPI_DISABLED, &bp->state))
9428                 return;
9429
9430         for (i = 0; i < bp->cp_nr_rings; i++) {
9431                 struct bnxt_cp_ring_info *cpr = &bp->bnapi[i]->cp_ring;
9432
9433                 napi_disable(&bp->bnapi[i]->napi);
9434                 if (bp->bnapi[i]->rx_ring)
9435                         cancel_work_sync(&cpr->dim.work);
9436         }
9437 }
9438
9439 static void bnxt_enable_napi(struct bnxt *bp)
9440 {
9441         int i;
9442
9443         clear_bit(BNXT_STATE_NAPI_DISABLED, &bp->state);
9444         for (i = 0; i < bp->cp_nr_rings; i++) {
9445                 struct bnxt_napi *bnapi = bp->bnapi[i];
9446                 struct bnxt_cp_ring_info *cpr;
9447
9448                 cpr = &bnapi->cp_ring;
9449                 if (bnapi->in_reset)
9450                         cpr->sw_stats.rx.rx_resets++;
9451                 bnapi->in_reset = false;
9452
9453                 if (bnapi->rx_ring) {
9454                         INIT_WORK(&cpr->dim.work, bnxt_dim_work);
9455                         cpr->dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE;
9456                 }
9457                 napi_enable(&bnapi->napi);
9458         }
9459 }
9460
9461 void bnxt_tx_disable(struct bnxt *bp)
9462 {
9463         int i;
9464         struct bnxt_tx_ring_info *txr;
9465
9466         if (bp->tx_ring) {
9467                 for (i = 0; i < bp->tx_nr_rings; i++) {
9468                         txr = &bp->tx_ring[i];
9469                         WRITE_ONCE(txr->dev_state, BNXT_DEV_STATE_CLOSING);
9470                 }
9471         }
9472         /* Make sure napi polls see @dev_state change */
9473         synchronize_net();
9474         /* Drop carrier first to prevent TX timeout */
9475         netif_carrier_off(bp->dev);
9476         /* Stop all TX queues */
9477         netif_tx_disable(bp->dev);
9478 }
9479
9480 void bnxt_tx_enable(struct bnxt *bp)
9481 {
9482         int i;
9483         struct bnxt_tx_ring_info *txr;
9484
9485         for (i = 0; i < bp->tx_nr_rings; i++) {
9486                 txr = &bp->tx_ring[i];
9487                 WRITE_ONCE(txr->dev_state, 0);
9488         }
9489         /* Make sure napi polls see @dev_state change */
9490         synchronize_net();
9491         netif_tx_wake_all_queues(bp->dev);
9492         if (BNXT_LINK_IS_UP(bp))
9493                 netif_carrier_on(bp->dev);
9494 }
9495
9496 static char *bnxt_report_fec(struct bnxt_link_info *link_info)
9497 {
9498         u8 active_fec = link_info->active_fec_sig_mode &
9499                         PORT_PHY_QCFG_RESP_ACTIVE_FEC_MASK;
9500
9501         switch (active_fec) {
9502         default:
9503         case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_NONE_ACTIVE:
9504                 return "None";
9505         case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_CLAUSE74_ACTIVE:
9506                 return "Clause 74 BaseR";
9507         case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_CLAUSE91_ACTIVE:
9508                 return "Clause 91 RS(528,514)";
9509         case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS544_1XN_ACTIVE:
9510                 return "Clause 91 RS544_1XN";
9511         case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS544_IEEE_ACTIVE:
9512                 return "Clause 91 RS(544,514)";
9513         case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS272_1XN_ACTIVE:
9514                 return "Clause 91 RS272_1XN";
9515         case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS272_IEEE_ACTIVE:
9516                 return "Clause 91 RS(272,257)";
9517         }
9518 }
9519
9520 void bnxt_report_link(struct bnxt *bp)
9521 {
9522         if (BNXT_LINK_IS_UP(bp)) {
9523                 const char *signal = "";
9524                 const char *flow_ctrl;
9525                 const char *duplex;
9526                 u32 speed;
9527                 u16 fec;
9528
9529                 netif_carrier_on(bp->dev);
9530                 speed = bnxt_fw_to_ethtool_speed(bp->link_info.link_speed);
9531                 if (speed == SPEED_UNKNOWN) {
9532                         netdev_info(bp->dev, "NIC Link is Up, speed unknown\n");
9533                         return;
9534                 }
9535                 if (bp->link_info.duplex == BNXT_LINK_DUPLEX_FULL)
9536                         duplex = "full";
9537                 else
9538                         duplex = "half";
9539                 if (bp->link_info.pause == BNXT_LINK_PAUSE_BOTH)
9540                         flow_ctrl = "ON - receive & transmit";
9541                 else if (bp->link_info.pause == BNXT_LINK_PAUSE_TX)
9542                         flow_ctrl = "ON - transmit";
9543                 else if (bp->link_info.pause == BNXT_LINK_PAUSE_RX)
9544                         flow_ctrl = "ON - receive";
9545                 else
9546                         flow_ctrl = "none";
9547                 if (bp->link_info.phy_qcfg_resp.option_flags &
9548                     PORT_PHY_QCFG_RESP_OPTION_FLAGS_SIGNAL_MODE_KNOWN) {
9549                         u8 sig_mode = bp->link_info.active_fec_sig_mode &
9550                                       PORT_PHY_QCFG_RESP_SIGNAL_MODE_MASK;
9551                         switch (sig_mode) {
9552                         case PORT_PHY_QCFG_RESP_SIGNAL_MODE_NRZ:
9553                                 signal = "(NRZ) ";
9554                                 break;
9555                         case PORT_PHY_QCFG_RESP_SIGNAL_MODE_PAM4:
9556                                 signal = "(PAM4) ";
9557                                 break;
9558                         default:
9559                                 break;
9560                         }
9561                 }
9562                 netdev_info(bp->dev, "NIC Link is Up, %u Mbps %s%s duplex, Flow control: %s\n",
9563                             speed, signal, duplex, flow_ctrl);
9564                 if (bp->phy_flags & BNXT_PHY_FL_EEE_CAP)
9565                         netdev_info(bp->dev, "EEE is %s\n",
9566                                     bp->eee.eee_active ? "active" :
9567                                                          "not active");
9568                 fec = bp->link_info.fec_cfg;
9569                 if (!(fec & PORT_PHY_QCFG_RESP_FEC_CFG_FEC_NONE_SUPPORTED))
9570                         netdev_info(bp->dev, "FEC autoneg %s encoding: %s\n",
9571                                     (fec & BNXT_FEC_AUTONEG) ? "on" : "off",
9572                                     bnxt_report_fec(&bp->link_info));
9573         } else {
9574                 netif_carrier_off(bp->dev);
9575                 netdev_err(bp->dev, "NIC Link is Down\n");
9576         }
9577 }
9578
9579 static bool bnxt_phy_qcaps_no_speed(struct hwrm_port_phy_qcaps_output *resp)
9580 {
9581         if (!resp->supported_speeds_auto_mode &&
9582             !resp->supported_speeds_force_mode &&
9583             !resp->supported_pam4_speeds_auto_mode &&
9584             !resp->supported_pam4_speeds_force_mode)
9585                 return true;
9586         return false;
9587 }
9588
9589 static int bnxt_hwrm_phy_qcaps(struct bnxt *bp)
9590 {
9591         struct bnxt_link_info *link_info = &bp->link_info;
9592         struct hwrm_port_phy_qcaps_output *resp;
9593         struct hwrm_port_phy_qcaps_input *req;
9594         int rc = 0;
9595
9596         if (bp->hwrm_spec_code < 0x10201)
9597                 return 0;
9598
9599         rc = hwrm_req_init(bp, req, HWRM_PORT_PHY_QCAPS);
9600         if (rc)
9601                 return rc;
9602
9603         resp = hwrm_req_hold(bp, req);
9604         rc = hwrm_req_send(bp, req);
9605         if (rc)
9606                 goto hwrm_phy_qcaps_exit;
9607
9608         bp->phy_flags = resp->flags | (le16_to_cpu(resp->flags2) << 8);
9609         if (resp->flags & PORT_PHY_QCAPS_RESP_FLAGS_EEE_SUPPORTED) {
9610                 struct ethtool_eee *eee = &bp->eee;
9611                 u16 fw_speeds = le16_to_cpu(resp->supported_speeds_eee_mode);
9612
9613                 eee->supported = _bnxt_fw_to_ethtool_adv_spds(fw_speeds, 0);
9614                 bp->lpi_tmr_lo = le32_to_cpu(resp->tx_lpi_timer_low) &
9615                                  PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_LOW_MASK;
9616                 bp->lpi_tmr_hi = le32_to_cpu(resp->valid_tx_lpi_timer_high) &
9617                                  PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_HIGH_MASK;
9618         }
9619
9620         if (bp->hwrm_spec_code >= 0x10a01) {
9621                 if (bnxt_phy_qcaps_no_speed(resp)) {
9622                         link_info->phy_state = BNXT_PHY_STATE_DISABLED;
9623                         netdev_warn(bp->dev, "Ethernet link disabled\n");
9624                 } else if (link_info->phy_state == BNXT_PHY_STATE_DISABLED) {
9625                         link_info->phy_state = BNXT_PHY_STATE_ENABLED;
9626                         netdev_info(bp->dev, "Ethernet link enabled\n");
9627                         /* Phy re-enabled, reprobe the speeds */
9628                         link_info->support_auto_speeds = 0;
9629                         link_info->support_pam4_auto_speeds = 0;
9630                 }
9631         }
9632         if (resp->supported_speeds_auto_mode)
9633                 link_info->support_auto_speeds =
9634                         le16_to_cpu(resp->supported_speeds_auto_mode);
9635         if (resp->supported_pam4_speeds_auto_mode)
9636                 link_info->support_pam4_auto_speeds =
9637                         le16_to_cpu(resp->supported_pam4_speeds_auto_mode);
9638
9639         bp->port_count = resp->port_cnt;
9640
9641 hwrm_phy_qcaps_exit:
9642         hwrm_req_drop(bp, req);
9643         return rc;
9644 }
9645
9646 static bool bnxt_support_dropped(u16 advertising, u16 supported)
9647 {
9648         u16 diff = advertising ^ supported;
9649
9650         return ((supported | diff) != supported);
9651 }
9652
9653 int bnxt_update_link(struct bnxt *bp, bool chng_link_state)
9654 {
9655         struct bnxt_link_info *link_info = &bp->link_info;
9656         struct hwrm_port_phy_qcfg_output *resp;
9657         struct hwrm_port_phy_qcfg_input *req;
9658         u8 link_state = link_info->link_state;
9659         bool support_changed = false;
9660         int rc;
9661
9662         rc = hwrm_req_init(bp, req, HWRM_PORT_PHY_QCFG);
9663         if (rc)
9664                 return rc;
9665
9666         resp = hwrm_req_hold(bp, req);
9667         rc = hwrm_req_send(bp, req);
9668         if (rc) {
9669                 hwrm_req_drop(bp, req);
9670                 if (BNXT_VF(bp) && rc == -ENODEV) {
9671                         netdev_warn(bp->dev, "Cannot obtain link state while PF unavailable.\n");
9672                         rc = 0;
9673                 }
9674                 return rc;
9675         }
9676
9677         memcpy(&link_info->phy_qcfg_resp, resp, sizeof(*resp));
9678         link_info->phy_link_status = resp->link;
9679         link_info->duplex = resp->duplex_cfg;
9680         if (bp->hwrm_spec_code >= 0x10800)
9681                 link_info->duplex = resp->duplex_state;
9682         link_info->pause = resp->pause;
9683         link_info->auto_mode = resp->auto_mode;
9684         link_info->auto_pause_setting = resp->auto_pause;
9685         link_info->lp_pause = resp->link_partner_adv_pause;
9686         link_info->force_pause_setting = resp->force_pause;
9687         link_info->duplex_setting = resp->duplex_cfg;
9688         if (link_info->phy_link_status == BNXT_LINK_LINK)
9689                 link_info->link_speed = le16_to_cpu(resp->link_speed);
9690         else
9691                 link_info->link_speed = 0;
9692         link_info->force_link_speed = le16_to_cpu(resp->force_link_speed);
9693         link_info->force_pam4_link_speed =
9694                 le16_to_cpu(resp->force_pam4_link_speed);
9695         link_info->support_speeds = le16_to_cpu(resp->support_speeds);
9696         link_info->support_pam4_speeds = le16_to_cpu(resp->support_pam4_speeds);
9697         link_info->auto_link_speeds = le16_to_cpu(resp->auto_link_speed_mask);
9698         link_info->auto_pam4_link_speeds =
9699                 le16_to_cpu(resp->auto_pam4_link_speed_mask);
9700         link_info->lp_auto_link_speeds =
9701                 le16_to_cpu(resp->link_partner_adv_speeds);
9702         link_info->lp_auto_pam4_link_speeds =
9703                 resp->link_partner_pam4_adv_speeds;
9704         link_info->preemphasis = le32_to_cpu(resp->preemphasis);
9705         link_info->phy_ver[0] = resp->phy_maj;
9706         link_info->phy_ver[1] = resp->phy_min;
9707         link_info->phy_ver[2] = resp->phy_bld;
9708         link_info->media_type = resp->media_type;
9709         link_info->phy_type = resp->phy_type;
9710         link_info->transceiver = resp->xcvr_pkg_type;
9711         link_info->phy_addr = resp->eee_config_phy_addr &
9712                               PORT_PHY_QCFG_RESP_PHY_ADDR_MASK;
9713         link_info->module_status = resp->module_status;
9714
9715         if (bp->phy_flags & BNXT_PHY_FL_EEE_CAP) {
9716                 struct ethtool_eee *eee = &bp->eee;
9717                 u16 fw_speeds;
9718
9719                 eee->eee_active = 0;
9720                 if (resp->eee_config_phy_addr &
9721                     PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ACTIVE) {
9722                         eee->eee_active = 1;
9723                         fw_speeds = le16_to_cpu(
9724                                 resp->link_partner_adv_eee_link_speed_mask);
9725                         eee->lp_advertised =
9726                                 _bnxt_fw_to_ethtool_adv_spds(fw_speeds, 0);
9727                 }
9728
9729                 /* Pull initial EEE config */
9730                 if (!chng_link_state) {
9731                         if (resp->eee_config_phy_addr &
9732                             PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ENABLED)
9733                                 eee->eee_enabled = 1;
9734
9735                         fw_speeds = le16_to_cpu(resp->adv_eee_link_speed_mask);
9736                         eee->advertised =
9737                                 _bnxt_fw_to_ethtool_adv_spds(fw_speeds, 0);
9738
9739                         if (resp->eee_config_phy_addr &
9740                             PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_TX_LPI) {
9741                                 __le32 tmr;
9742
9743                                 eee->tx_lpi_enabled = 1;
9744                                 tmr = resp->xcvr_identifier_type_tx_lpi_timer;
9745                                 eee->tx_lpi_timer = le32_to_cpu(tmr) &
9746                                         PORT_PHY_QCFG_RESP_TX_LPI_TIMER_MASK;
9747                         }
9748                 }
9749         }
9750
9751         link_info->fec_cfg = PORT_PHY_QCFG_RESP_FEC_CFG_FEC_NONE_SUPPORTED;
9752         if (bp->hwrm_spec_code >= 0x10504) {
9753                 link_info->fec_cfg = le16_to_cpu(resp->fec_cfg);
9754                 link_info->active_fec_sig_mode = resp->active_fec_signal_mode;
9755         }
9756         /* TODO: need to add more logic to report VF link */
9757         if (chng_link_state) {
9758                 if (link_info->phy_link_status == BNXT_LINK_LINK)
9759                         link_info->link_state = BNXT_LINK_STATE_UP;
9760                 else
9761                         link_info->link_state = BNXT_LINK_STATE_DOWN;
9762                 if (link_state != link_info->link_state)
9763                         bnxt_report_link(bp);
9764         } else {
9765                 /* always link down if not require to update link state */
9766                 link_info->link_state = BNXT_LINK_STATE_DOWN;
9767         }
9768         hwrm_req_drop(bp, req);
9769
9770         if (!BNXT_PHY_CFG_ABLE(bp))
9771                 return 0;
9772
9773         /* Check if any advertised speeds are no longer supported. The caller
9774          * holds the link_lock mutex, so we can modify link_info settings.
9775          */
9776         if (bnxt_support_dropped(link_info->advertising,
9777                                  link_info->support_auto_speeds)) {
9778                 link_info->advertising = link_info->support_auto_speeds;
9779                 support_changed = true;
9780         }
9781         if (bnxt_support_dropped(link_info->advertising_pam4,
9782                                  link_info->support_pam4_auto_speeds)) {
9783                 link_info->advertising_pam4 = link_info->support_pam4_auto_speeds;
9784                 support_changed = true;
9785         }
9786         if (support_changed && (link_info->autoneg & BNXT_AUTONEG_SPEED))
9787                 bnxt_hwrm_set_link_setting(bp, true, false);
9788         return 0;
9789 }
9790
9791 static void bnxt_get_port_module_status(struct bnxt *bp)
9792 {
9793         struct bnxt_link_info *link_info = &bp->link_info;
9794         struct hwrm_port_phy_qcfg_output *resp = &link_info->phy_qcfg_resp;
9795         u8 module_status;
9796
9797         if (bnxt_update_link(bp, true))
9798                 return;
9799
9800         module_status = link_info->module_status;
9801         switch (module_status) {
9802         case PORT_PHY_QCFG_RESP_MODULE_STATUS_DISABLETX:
9803         case PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN:
9804         case PORT_PHY_QCFG_RESP_MODULE_STATUS_WARNINGMSG:
9805                 netdev_warn(bp->dev, "Unqualified SFP+ module detected on port %d\n",
9806                             bp->pf.port_id);
9807                 if (bp->hwrm_spec_code >= 0x10201) {
9808                         netdev_warn(bp->dev, "Module part number %s\n",
9809                                     resp->phy_vendor_partnumber);
9810                 }
9811                 if (module_status == PORT_PHY_QCFG_RESP_MODULE_STATUS_DISABLETX)
9812                         netdev_warn(bp->dev, "TX is disabled\n");
9813                 if (module_status == PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN)
9814                         netdev_warn(bp->dev, "SFP+ module is shutdown\n");
9815         }
9816 }
9817
9818 static void
9819 bnxt_hwrm_set_pause_common(struct bnxt *bp, struct hwrm_port_phy_cfg_input *req)
9820 {
9821         if (bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL) {
9822                 if (bp->hwrm_spec_code >= 0x10201)
9823                         req->auto_pause =
9824                                 PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE;
9825                 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_RX)
9826                         req->auto_pause |= PORT_PHY_CFG_REQ_AUTO_PAUSE_RX;
9827                 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_TX)
9828                         req->auto_pause |= PORT_PHY_CFG_REQ_AUTO_PAUSE_TX;
9829                 req->enables |=
9830                         cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE);
9831         } else {
9832                 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_RX)
9833                         req->force_pause |= PORT_PHY_CFG_REQ_FORCE_PAUSE_RX;
9834                 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_TX)
9835                         req->force_pause |= PORT_PHY_CFG_REQ_FORCE_PAUSE_TX;
9836                 req->enables |=
9837                         cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_FORCE_PAUSE);
9838                 if (bp->hwrm_spec_code >= 0x10201) {
9839                         req->auto_pause = req->force_pause;
9840                         req->enables |= cpu_to_le32(
9841                                 PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE);
9842                 }
9843         }
9844 }
9845
9846 static void bnxt_hwrm_set_link_common(struct bnxt *bp, struct hwrm_port_phy_cfg_input *req)
9847 {
9848         if (bp->link_info.autoneg & BNXT_AUTONEG_SPEED) {
9849                 req->auto_mode |= PORT_PHY_CFG_REQ_AUTO_MODE_SPEED_MASK;
9850                 if (bp->link_info.advertising) {
9851                         req->enables |= cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED_MASK);
9852                         req->auto_link_speed_mask = cpu_to_le16(bp->link_info.advertising);
9853                 }
9854                 if (bp->link_info.advertising_pam4) {
9855                         req->enables |=
9856                                 cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_PAM4_LINK_SPEED_MASK);
9857                         req->auto_link_pam4_speed_mask =
9858                                 cpu_to_le16(bp->link_info.advertising_pam4);
9859                 }
9860                 req->enables |= cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_MODE);
9861                 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_RESTART_AUTONEG);
9862         } else {
9863                 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_FORCE);
9864                 if (bp->link_info.req_signal_mode == BNXT_SIG_MODE_PAM4) {
9865                         req->force_pam4_link_speed = cpu_to_le16(bp->link_info.req_link_speed);
9866                         req->enables |= cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_FORCE_PAM4_LINK_SPEED);
9867                 } else {
9868                         req->force_link_speed = cpu_to_le16(bp->link_info.req_link_speed);
9869                 }
9870         }
9871
9872         /* tell chimp that the setting takes effect immediately */
9873         req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_RESET_PHY);
9874 }
9875
9876 int bnxt_hwrm_set_pause(struct bnxt *bp)
9877 {
9878         struct hwrm_port_phy_cfg_input *req;
9879         int rc;
9880
9881         rc = hwrm_req_init(bp, req, HWRM_PORT_PHY_CFG);
9882         if (rc)
9883                 return rc;
9884
9885         bnxt_hwrm_set_pause_common(bp, req);
9886
9887         if ((bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL) ||
9888             bp->link_info.force_link_chng)
9889                 bnxt_hwrm_set_link_common(bp, req);
9890
9891         rc = hwrm_req_send(bp, req);
9892         if (!rc && !(bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL)) {
9893                 /* since changing of pause setting doesn't trigger any link
9894                  * change event, the driver needs to update the current pause
9895                  * result upon successfully return of the phy_cfg command
9896                  */
9897                 bp->link_info.pause =
9898                 bp->link_info.force_pause_setting = bp->link_info.req_flow_ctrl;
9899                 bp->link_info.auto_pause_setting = 0;
9900                 if (!bp->link_info.force_link_chng)
9901                         bnxt_report_link(bp);
9902         }
9903         bp->link_info.force_link_chng = false;
9904         return rc;
9905 }
9906
9907 static void bnxt_hwrm_set_eee(struct bnxt *bp,
9908                               struct hwrm_port_phy_cfg_input *req)
9909 {
9910         struct ethtool_eee *eee = &bp->eee;
9911
9912         if (eee->eee_enabled) {
9913                 u16 eee_speeds;
9914                 u32 flags = PORT_PHY_CFG_REQ_FLAGS_EEE_ENABLE;
9915
9916                 if (eee->tx_lpi_enabled)
9917                         flags |= PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_ENABLE;
9918                 else
9919                         flags |= PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_DISABLE;
9920
9921                 req->flags |= cpu_to_le32(flags);
9922                 eee_speeds = bnxt_get_fw_auto_link_speeds(eee->advertised);
9923                 req->eee_link_speed_mask = cpu_to_le16(eee_speeds);
9924                 req->tx_lpi_timer = cpu_to_le32(eee->tx_lpi_timer);
9925         } else {
9926                 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_EEE_DISABLE);
9927         }
9928 }
9929
9930 int bnxt_hwrm_set_link_setting(struct bnxt *bp, bool set_pause, bool set_eee)
9931 {
9932         struct hwrm_port_phy_cfg_input *req;
9933         int rc;
9934
9935         rc = hwrm_req_init(bp, req, HWRM_PORT_PHY_CFG);
9936         if (rc)
9937                 return rc;
9938
9939         if (set_pause)
9940                 bnxt_hwrm_set_pause_common(bp, req);
9941
9942         bnxt_hwrm_set_link_common(bp, req);
9943
9944         if (set_eee)
9945                 bnxt_hwrm_set_eee(bp, req);
9946         return hwrm_req_send(bp, req);
9947 }
9948
9949 static int bnxt_hwrm_shutdown_link(struct bnxt *bp)
9950 {
9951         struct hwrm_port_phy_cfg_input *req;
9952         int rc;
9953
9954         if (!BNXT_SINGLE_PF(bp))
9955                 return 0;
9956
9957         if (pci_num_vf(bp->pdev) &&
9958             !(bp->phy_flags & BNXT_PHY_FL_FW_MANAGED_LKDN))
9959                 return 0;
9960
9961         rc = hwrm_req_init(bp, req, HWRM_PORT_PHY_CFG);
9962         if (rc)
9963                 return rc;
9964
9965         req->flags = cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_FORCE_LINK_DWN);
9966         rc = hwrm_req_send(bp, req);
9967         if (!rc) {
9968                 mutex_lock(&bp->link_lock);
9969                 /* Device is not obliged link down in certain scenarios, even
9970                  * when forced. Setting the state unknown is consistent with
9971                  * driver startup and will force link state to be reported
9972                  * during subsequent open based on PORT_PHY_QCFG.
9973                  */
9974                 bp->link_info.link_state = BNXT_LINK_STATE_UNKNOWN;
9975                 mutex_unlock(&bp->link_lock);
9976         }
9977         return rc;
9978 }
9979
9980 static int bnxt_fw_reset_via_optee(struct bnxt *bp)
9981 {
9982 #ifdef CONFIG_TEE_BNXT_FW
9983         int rc = tee_bnxt_fw_load();
9984
9985         if (rc)
9986                 netdev_err(bp->dev, "Failed FW reset via OP-TEE, rc=%d\n", rc);
9987
9988         return rc;
9989 #else
9990         netdev_err(bp->dev, "OP-TEE not supported\n");
9991         return -ENODEV;
9992 #endif
9993 }
9994
9995 static int bnxt_try_recover_fw(struct bnxt *bp)
9996 {
9997         if (bp->fw_health && bp->fw_health->status_reliable) {
9998                 int retry = 0, rc;
9999                 u32 sts;
10000
10001                 do {
10002                         sts = bnxt_fw_health_readl(bp, BNXT_FW_HEALTH_REG);
10003                         rc = bnxt_hwrm_poll(bp);
10004                         if (!BNXT_FW_IS_BOOTING(sts) &&
10005                             !BNXT_FW_IS_RECOVERING(sts))
10006                                 break;
10007                         retry++;
10008                 } while (rc == -EBUSY && retry < BNXT_FW_RETRY);
10009
10010                 if (!BNXT_FW_IS_HEALTHY(sts)) {
10011                         netdev_err(bp->dev,
10012                                    "Firmware not responding, status: 0x%x\n",
10013                                    sts);
10014                         rc = -ENODEV;
10015                 }
10016                 if (sts & FW_STATUS_REG_CRASHED_NO_MASTER) {
10017                         netdev_warn(bp->dev, "Firmware recover via OP-TEE requested\n");
10018                         return bnxt_fw_reset_via_optee(bp);
10019                 }
10020                 return rc;
10021         }
10022
10023         return -ENODEV;
10024 }
10025
10026 static void bnxt_clear_reservations(struct bnxt *bp, bool fw_reset)
10027 {
10028         struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
10029
10030         if (!BNXT_NEW_RM(bp))
10031                 return; /* no resource reservations required */
10032
10033         hw_resc->resv_cp_rings = 0;
10034         hw_resc->resv_stat_ctxs = 0;
10035         hw_resc->resv_irqs = 0;
10036         hw_resc->resv_tx_rings = 0;
10037         hw_resc->resv_rx_rings = 0;
10038         hw_resc->resv_hw_ring_grps = 0;
10039         hw_resc->resv_vnics = 0;
10040         if (!fw_reset) {
10041                 bp->tx_nr_rings = 0;
10042                 bp->rx_nr_rings = 0;
10043         }
10044 }
10045
10046 int bnxt_cancel_reservations(struct bnxt *bp, bool fw_reset)
10047 {
10048         int rc;
10049
10050         if (!BNXT_NEW_RM(bp))
10051                 return 0; /* no resource reservations required */
10052
10053         rc = bnxt_hwrm_func_resc_qcaps(bp, true);
10054         if (rc)
10055                 netdev_err(bp->dev, "resc_qcaps failed\n");
10056
10057         bnxt_clear_reservations(bp, fw_reset);
10058
10059         return rc;
10060 }
10061
10062 static int bnxt_hwrm_if_change(struct bnxt *bp, bool up)
10063 {
10064         struct hwrm_func_drv_if_change_output *resp;
10065         struct hwrm_func_drv_if_change_input *req;
10066         bool fw_reset = !bp->irq_tbl;
10067         bool resc_reinit = false;
10068         int rc, retry = 0;
10069         u32 flags = 0;
10070
10071         if (!(bp->fw_cap & BNXT_FW_CAP_IF_CHANGE))
10072                 return 0;
10073
10074         rc = hwrm_req_init(bp, req, HWRM_FUNC_DRV_IF_CHANGE);
10075         if (rc)
10076                 return rc;
10077
10078         if (up)
10079                 req->flags = cpu_to_le32(FUNC_DRV_IF_CHANGE_REQ_FLAGS_UP);
10080         resp = hwrm_req_hold(bp, req);
10081
10082         hwrm_req_flags(bp, req, BNXT_HWRM_FULL_WAIT);
10083         while (retry < BNXT_FW_IF_RETRY) {
10084                 rc = hwrm_req_send(bp, req);
10085                 if (rc != -EAGAIN)
10086                         break;
10087
10088                 msleep(50);
10089                 retry++;
10090         }
10091
10092         if (rc == -EAGAIN) {
10093                 hwrm_req_drop(bp, req);
10094                 return rc;
10095         } else if (!rc) {
10096                 flags = le32_to_cpu(resp->flags);
10097         } else if (up) {
10098                 rc = bnxt_try_recover_fw(bp);
10099                 fw_reset = true;
10100         }
10101         hwrm_req_drop(bp, req);
10102         if (rc)
10103                 return rc;
10104
10105         if (!up) {
10106                 bnxt_inv_fw_health_reg(bp);
10107                 return 0;
10108         }
10109
10110         if (flags & FUNC_DRV_IF_CHANGE_RESP_FLAGS_RESC_CHANGE)
10111                 resc_reinit = true;
10112         if (flags & FUNC_DRV_IF_CHANGE_RESP_FLAGS_HOT_FW_RESET_DONE ||
10113             test_bit(BNXT_STATE_FW_RESET_DET, &bp->state))
10114                 fw_reset = true;
10115         else
10116                 bnxt_remap_fw_health_regs(bp);
10117
10118         if (test_bit(BNXT_STATE_IN_FW_RESET, &bp->state) && !fw_reset) {
10119                 netdev_err(bp->dev, "RESET_DONE not set during FW reset.\n");
10120                 set_bit(BNXT_STATE_ABORT_ERR, &bp->state);
10121                 return -ENODEV;
10122         }
10123         if (resc_reinit || fw_reset) {
10124                 if (fw_reset) {
10125                         set_bit(BNXT_STATE_FW_RESET_DET, &bp->state);
10126                         if (!test_bit(BNXT_STATE_IN_FW_RESET, &bp->state))
10127                                 bnxt_ulp_stop(bp);
10128                         bnxt_free_ctx_mem(bp);
10129                         kfree(bp->ctx);
10130                         bp->ctx = NULL;
10131                         bnxt_dcb_free(bp);
10132                         rc = bnxt_fw_init_one(bp);
10133                         if (rc) {
10134                                 clear_bit(BNXT_STATE_FW_RESET_DET, &bp->state);
10135                                 set_bit(BNXT_STATE_ABORT_ERR, &bp->state);
10136                                 return rc;
10137                         }
10138                         bnxt_clear_int_mode(bp);
10139                         rc = bnxt_init_int_mode(bp);
10140                         if (rc) {
10141                                 clear_bit(BNXT_STATE_FW_RESET_DET, &bp->state);
10142                                 netdev_err(bp->dev, "init int mode failed\n");
10143                                 return rc;
10144                         }
10145                 }
10146                 rc = bnxt_cancel_reservations(bp, fw_reset);
10147         }
10148         return rc;
10149 }
10150
10151 static int bnxt_hwrm_port_led_qcaps(struct bnxt *bp)
10152 {
10153         struct hwrm_port_led_qcaps_output *resp;
10154         struct hwrm_port_led_qcaps_input *req;
10155         struct bnxt_pf_info *pf = &bp->pf;
10156         int rc;
10157
10158         bp->num_leds = 0;
10159         if (BNXT_VF(bp) || bp->hwrm_spec_code < 0x10601)
10160                 return 0;
10161
10162         rc = hwrm_req_init(bp, req, HWRM_PORT_LED_QCAPS);
10163         if (rc)
10164                 return rc;
10165
10166         req->port_id = cpu_to_le16(pf->port_id);
10167         resp = hwrm_req_hold(bp, req);
10168         rc = hwrm_req_send(bp, req);
10169         if (rc) {
10170                 hwrm_req_drop(bp, req);
10171                 return rc;
10172         }
10173         if (resp->num_leds > 0 && resp->num_leds < BNXT_MAX_LED) {
10174                 int i;
10175
10176                 bp->num_leds = resp->num_leds;
10177                 memcpy(bp->leds, &resp->led0_id, sizeof(bp->leds[0]) *
10178                                                  bp->num_leds);
10179                 for (i = 0; i < bp->num_leds; i++) {
10180                         struct bnxt_led_info *led = &bp->leds[i];
10181                         __le16 caps = led->led_state_caps;
10182
10183                         if (!led->led_group_id ||
10184                             !BNXT_LED_ALT_BLINK_CAP(caps)) {
10185                                 bp->num_leds = 0;
10186                                 break;
10187                         }
10188                 }
10189         }
10190         hwrm_req_drop(bp, req);
10191         return 0;
10192 }
10193
10194 int bnxt_hwrm_alloc_wol_fltr(struct bnxt *bp)
10195 {
10196         struct hwrm_wol_filter_alloc_output *resp;
10197         struct hwrm_wol_filter_alloc_input *req;
10198         int rc;
10199
10200         rc = hwrm_req_init(bp, req, HWRM_WOL_FILTER_ALLOC);
10201         if (rc)
10202                 return rc;
10203
10204         req->port_id = cpu_to_le16(bp->pf.port_id);
10205         req->wol_type = WOL_FILTER_ALLOC_REQ_WOL_TYPE_MAGICPKT;
10206         req->enables = cpu_to_le32(WOL_FILTER_ALLOC_REQ_ENABLES_MAC_ADDRESS);
10207         memcpy(req->mac_address, bp->dev->dev_addr, ETH_ALEN);
10208
10209         resp = hwrm_req_hold(bp, req);
10210         rc = hwrm_req_send(bp, req);
10211         if (!rc)
10212                 bp->wol_filter_id = resp->wol_filter_id;
10213         hwrm_req_drop(bp, req);
10214         return rc;
10215 }
10216
10217 int bnxt_hwrm_free_wol_fltr(struct bnxt *bp)
10218 {
10219         struct hwrm_wol_filter_free_input *req;
10220         int rc;
10221
10222         rc = hwrm_req_init(bp, req, HWRM_WOL_FILTER_FREE);
10223         if (rc)
10224                 return rc;
10225
10226         req->port_id = cpu_to_le16(bp->pf.port_id);
10227         req->enables = cpu_to_le32(WOL_FILTER_FREE_REQ_ENABLES_WOL_FILTER_ID);
10228         req->wol_filter_id = bp->wol_filter_id;
10229
10230         return hwrm_req_send(bp, req);
10231 }
10232
10233 static u16 bnxt_hwrm_get_wol_fltrs(struct bnxt *bp, u16 handle)
10234 {
10235         struct hwrm_wol_filter_qcfg_output *resp;
10236         struct hwrm_wol_filter_qcfg_input *req;
10237         u16 next_handle = 0;
10238         int rc;
10239
10240         rc = hwrm_req_init(bp, req, HWRM_WOL_FILTER_QCFG);
10241         if (rc)
10242                 return rc;
10243
10244         req->port_id = cpu_to_le16(bp->pf.port_id);
10245         req->handle = cpu_to_le16(handle);
10246         resp = hwrm_req_hold(bp, req);
10247         rc = hwrm_req_send(bp, req);
10248         if (!rc) {
10249                 next_handle = le16_to_cpu(resp->next_handle);
10250                 if (next_handle != 0) {
10251                         if (resp->wol_type ==
10252                             WOL_FILTER_ALLOC_REQ_WOL_TYPE_MAGICPKT) {
10253                                 bp->wol = 1;
10254                                 bp->wol_filter_id = resp->wol_filter_id;
10255                         }
10256                 }
10257         }
10258         hwrm_req_drop(bp, req);
10259         return next_handle;
10260 }
10261
10262 static void bnxt_get_wol_settings(struct bnxt *bp)
10263 {
10264         u16 handle = 0;
10265
10266         bp->wol = 0;
10267         if (!BNXT_PF(bp) || !(bp->flags & BNXT_FLAG_WOL_CAP))
10268                 return;
10269
10270         do {
10271                 handle = bnxt_hwrm_get_wol_fltrs(bp, handle);
10272         } while (handle && handle != 0xffff);
10273 }
10274
10275 #ifdef CONFIG_BNXT_HWMON
10276 static ssize_t bnxt_show_temp(struct device *dev,
10277                               struct device_attribute *devattr, char *buf)
10278 {
10279         struct hwrm_temp_monitor_query_output *resp;
10280         struct hwrm_temp_monitor_query_input *req;
10281         struct bnxt *bp = dev_get_drvdata(dev);
10282         u32 len = 0;
10283         int rc;
10284
10285         rc = hwrm_req_init(bp, req, HWRM_TEMP_MONITOR_QUERY);
10286         if (rc)
10287                 return rc;
10288         resp = hwrm_req_hold(bp, req);
10289         rc = hwrm_req_send(bp, req);
10290         if (!rc)
10291                 len = sprintf(buf, "%u\n", resp->temp * 1000); /* display millidegree */
10292         hwrm_req_drop(bp, req);
10293         if (rc)
10294                 return rc;
10295         return len;
10296 }
10297 static SENSOR_DEVICE_ATTR(temp1_input, 0444, bnxt_show_temp, NULL, 0);
10298
10299 static struct attribute *bnxt_attrs[] = {
10300         &sensor_dev_attr_temp1_input.dev_attr.attr,
10301         NULL
10302 };
10303 ATTRIBUTE_GROUPS(bnxt);
10304
10305 static void bnxt_hwmon_close(struct bnxt *bp)
10306 {
10307         if (bp->hwmon_dev) {
10308                 hwmon_device_unregister(bp->hwmon_dev);
10309                 bp->hwmon_dev = NULL;
10310         }
10311 }
10312
10313 static void bnxt_hwmon_open(struct bnxt *bp)
10314 {
10315         struct hwrm_temp_monitor_query_input *req;
10316         struct pci_dev *pdev = bp->pdev;
10317         int rc;
10318
10319         rc = hwrm_req_init(bp, req, HWRM_TEMP_MONITOR_QUERY);
10320         if (!rc)
10321                 rc = hwrm_req_send_silent(bp, req);
10322         if (rc == -EACCES || rc == -EOPNOTSUPP) {
10323                 bnxt_hwmon_close(bp);
10324                 return;
10325         }
10326
10327         if (bp->hwmon_dev)
10328                 return;
10329
10330         bp->hwmon_dev = hwmon_device_register_with_groups(&pdev->dev,
10331                                                           DRV_MODULE_NAME, bp,
10332                                                           bnxt_groups);
10333         if (IS_ERR(bp->hwmon_dev)) {
10334                 bp->hwmon_dev = NULL;
10335                 dev_warn(&pdev->dev, "Cannot register hwmon device\n");
10336         }
10337 }
10338 #else
10339 static void bnxt_hwmon_close(struct bnxt *bp)
10340 {
10341 }
10342
10343 static void bnxt_hwmon_open(struct bnxt *bp)
10344 {
10345 }
10346 #endif
10347
10348 static bool bnxt_eee_config_ok(struct bnxt *bp)
10349 {
10350         struct ethtool_eee *eee = &bp->eee;
10351         struct bnxt_link_info *link_info = &bp->link_info;
10352
10353         if (!(bp->phy_flags & BNXT_PHY_FL_EEE_CAP))
10354                 return true;
10355
10356         if (eee->eee_enabled) {
10357                 u32 advertising =
10358                         _bnxt_fw_to_ethtool_adv_spds(link_info->advertising, 0);
10359
10360                 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) {
10361                         eee->eee_enabled = 0;
10362                         return false;
10363                 }
10364                 if (eee->advertised & ~advertising) {
10365                         eee->advertised = advertising & eee->supported;
10366                         return false;
10367                 }
10368         }
10369         return true;
10370 }
10371
10372 static int bnxt_update_phy_setting(struct bnxt *bp)
10373 {
10374         int rc;
10375         bool update_link = false;
10376         bool update_pause = false;
10377         bool update_eee = false;
10378         struct bnxt_link_info *link_info = &bp->link_info;
10379
10380         rc = bnxt_update_link(bp, true);
10381         if (rc) {
10382                 netdev_err(bp->dev, "failed to update link (rc: %x)\n",
10383                            rc);
10384                 return rc;
10385         }
10386         if (!BNXT_SINGLE_PF(bp))
10387                 return 0;
10388
10389         if ((link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) &&
10390             (link_info->auto_pause_setting & BNXT_LINK_PAUSE_BOTH) !=
10391             link_info->req_flow_ctrl)
10392                 update_pause = true;
10393         if (!(link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) &&
10394             link_info->force_pause_setting != link_info->req_flow_ctrl)
10395                 update_pause = true;
10396         if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) {
10397                 if (BNXT_AUTO_MODE(link_info->auto_mode))
10398                         update_link = true;
10399                 if (link_info->req_signal_mode == BNXT_SIG_MODE_NRZ &&
10400                     link_info->req_link_speed != link_info->force_link_speed)
10401                         update_link = true;
10402                 else if (link_info->req_signal_mode == BNXT_SIG_MODE_PAM4 &&
10403                          link_info->req_link_speed != link_info->force_pam4_link_speed)
10404                         update_link = true;
10405                 if (link_info->req_duplex != link_info->duplex_setting)
10406                         update_link = true;
10407         } else {
10408                 if (link_info->auto_mode == BNXT_LINK_AUTO_NONE)
10409                         update_link = true;
10410                 if (link_info->advertising != link_info->auto_link_speeds ||
10411                     link_info->advertising_pam4 != link_info->auto_pam4_link_speeds)
10412                         update_link = true;
10413         }
10414
10415         /* The last close may have shutdown the link, so need to call
10416          * PHY_CFG to bring it back up.
10417          */
10418         if (!BNXT_LINK_IS_UP(bp))
10419                 update_link = true;
10420
10421         if (!bnxt_eee_config_ok(bp))
10422                 update_eee = true;
10423
10424         if (update_link)
10425                 rc = bnxt_hwrm_set_link_setting(bp, update_pause, update_eee);
10426         else if (update_pause)
10427                 rc = bnxt_hwrm_set_pause(bp);
10428         if (rc) {
10429                 netdev_err(bp->dev, "failed to update phy setting (rc: %x)\n",
10430                            rc);
10431                 return rc;
10432         }
10433
10434         return rc;
10435 }
10436
10437 /* Common routine to pre-map certain register block to different GRC window.
10438  * A PF has 16 4K windows and a VF has 4 4K windows. However, only 15 windows
10439  * in PF and 3 windows in VF that can be customized to map in different
10440  * register blocks.
10441  */
10442 static void bnxt_preset_reg_win(struct bnxt *bp)
10443 {
10444         if (BNXT_PF(bp)) {
10445                 /* CAG registers map to GRC window #4 */
10446                 writel(BNXT_CAG_REG_BASE,
10447                        bp->bar0 + BNXT_GRCPF_REG_WINDOW_BASE_OUT + 12);
10448         }
10449 }
10450
10451 static int bnxt_init_dflt_ring_mode(struct bnxt *bp);
10452
10453 static int bnxt_reinit_after_abort(struct bnxt *bp)
10454 {
10455         int rc;
10456
10457         if (test_bit(BNXT_STATE_IN_FW_RESET, &bp->state))
10458                 return -EBUSY;
10459
10460         if (bp->dev->reg_state == NETREG_UNREGISTERED)
10461                 return -ENODEV;
10462
10463         rc = bnxt_fw_init_one(bp);
10464         if (!rc) {
10465                 bnxt_clear_int_mode(bp);
10466                 rc = bnxt_init_int_mode(bp);
10467                 if (!rc) {
10468                         clear_bit(BNXT_STATE_ABORT_ERR, &bp->state);
10469                         set_bit(BNXT_STATE_FW_RESET_DET, &bp->state);
10470                 }
10471         }
10472         return rc;
10473 }
10474
10475 static int __bnxt_open_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init)
10476 {
10477         int rc = 0;
10478
10479         bnxt_preset_reg_win(bp);
10480         netif_carrier_off(bp->dev);
10481         if (irq_re_init) {
10482                 /* Reserve rings now if none were reserved at driver probe. */
10483                 rc = bnxt_init_dflt_ring_mode(bp);
10484                 if (rc) {
10485                         netdev_err(bp->dev, "Failed to reserve default rings at open\n");
10486                         return rc;
10487                 }
10488         }
10489         rc = bnxt_reserve_rings(bp, irq_re_init);
10490         if (rc)
10491                 return rc;
10492         if ((bp->flags & BNXT_FLAG_RFS) &&
10493             !(bp->flags & BNXT_FLAG_USING_MSIX)) {
10494                 /* disable RFS if falling back to INTA */
10495                 bp->dev->hw_features &= ~NETIF_F_NTUPLE;
10496                 bp->flags &= ~BNXT_FLAG_RFS;
10497         }
10498
10499         rc = bnxt_alloc_mem(bp, irq_re_init);
10500         if (rc) {
10501                 netdev_err(bp->dev, "bnxt_alloc_mem err: %x\n", rc);
10502                 goto open_err_free_mem;
10503         }
10504
10505         if (irq_re_init) {
10506                 bnxt_init_napi(bp);
10507                 rc = bnxt_request_irq(bp);
10508                 if (rc) {
10509                         netdev_err(bp->dev, "bnxt_request_irq err: %x\n", rc);
10510                         goto open_err_irq;
10511                 }
10512         }
10513
10514         rc = bnxt_init_nic(bp, irq_re_init);
10515         if (rc) {
10516                 netdev_err(bp->dev, "bnxt_init_nic err: %x\n", rc);
10517                 goto open_err_irq;
10518         }
10519
10520         bnxt_enable_napi(bp);
10521         bnxt_debug_dev_init(bp);
10522
10523         if (link_re_init) {
10524                 mutex_lock(&bp->link_lock);
10525                 rc = bnxt_update_phy_setting(bp);
10526                 mutex_unlock(&bp->link_lock);
10527                 if (rc) {
10528                         netdev_warn(bp->dev, "failed to update phy settings\n");
10529                         if (BNXT_SINGLE_PF(bp)) {
10530                                 bp->link_info.phy_retry = true;
10531                                 bp->link_info.phy_retry_expires =
10532                                         jiffies + 5 * HZ;
10533                         }
10534                 }
10535         }
10536
10537         if (irq_re_init)
10538                 udp_tunnel_nic_reset_ntf(bp->dev);
10539
10540         if (bp->tx_nr_rings_xdp < num_possible_cpus()) {
10541                 if (!static_key_enabled(&bnxt_xdp_locking_key))
10542                         static_branch_enable(&bnxt_xdp_locking_key);
10543         } else if (static_key_enabled(&bnxt_xdp_locking_key)) {
10544                 static_branch_disable(&bnxt_xdp_locking_key);
10545         }
10546         set_bit(BNXT_STATE_OPEN, &bp->state);
10547         bnxt_enable_int(bp);
10548         /* Enable TX queues */
10549         bnxt_tx_enable(bp);
10550         mod_timer(&bp->timer, jiffies + bp->current_interval);
10551         /* Poll link status and check for SFP+ module status */
10552         mutex_lock(&bp->link_lock);
10553         bnxt_get_port_module_status(bp);
10554         mutex_unlock(&bp->link_lock);
10555
10556         /* VF-reps may need to be re-opened after the PF is re-opened */
10557         if (BNXT_PF(bp))
10558                 bnxt_vf_reps_open(bp);
10559         bnxt_ptp_init_rtc(bp, true);
10560         bnxt_ptp_cfg_tstamp_filters(bp);
10561         return 0;
10562
10563 open_err_irq:
10564         bnxt_del_napi(bp);
10565
10566 open_err_free_mem:
10567         bnxt_free_skbs(bp);
10568         bnxt_free_irq(bp);
10569         bnxt_free_mem(bp, true);
10570         return rc;
10571 }
10572
10573 /* rtnl_lock held */
10574 int bnxt_open_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init)
10575 {
10576         int rc = 0;
10577
10578         if (test_bit(BNXT_STATE_ABORT_ERR, &bp->state))
10579                 rc = -EIO;
10580         if (!rc)
10581                 rc = __bnxt_open_nic(bp, irq_re_init, link_re_init);
10582         if (rc) {
10583                 netdev_err(bp->dev, "nic open fail (rc: %x)\n", rc);
10584                 dev_close(bp->dev);
10585         }
10586         return rc;
10587 }
10588
10589 /* rtnl_lock held, open the NIC half way by allocating all resources, but
10590  * NAPI, IRQ, and TX are not enabled.  This is mainly used for offline
10591  * self tests.
10592  */
10593 int bnxt_half_open_nic(struct bnxt *bp)
10594 {
10595         int rc = 0;
10596
10597         if (test_bit(BNXT_STATE_ABORT_ERR, &bp->state)) {
10598                 netdev_err(bp->dev, "A previous firmware reset has not completed, aborting half open\n");
10599                 rc = -ENODEV;
10600                 goto half_open_err;
10601         }
10602
10603         rc = bnxt_alloc_mem(bp, true);
10604         if (rc) {
10605                 netdev_err(bp->dev, "bnxt_alloc_mem err: %x\n", rc);
10606                 goto half_open_err;
10607         }
10608         set_bit(BNXT_STATE_HALF_OPEN, &bp->state);
10609         rc = bnxt_init_nic(bp, true);
10610         if (rc) {
10611                 clear_bit(BNXT_STATE_HALF_OPEN, &bp->state);
10612                 netdev_err(bp->dev, "bnxt_init_nic err: %x\n", rc);
10613                 goto half_open_err;
10614         }
10615         return 0;
10616
10617 half_open_err:
10618         bnxt_free_skbs(bp);
10619         bnxt_free_mem(bp, true);
10620         dev_close(bp->dev);
10621         return rc;
10622 }
10623
10624 /* rtnl_lock held, this call can only be made after a previous successful
10625  * call to bnxt_half_open_nic().
10626  */
10627 void bnxt_half_close_nic(struct bnxt *bp)
10628 {
10629         bnxt_hwrm_resource_free(bp, false, true);
10630         bnxt_free_skbs(bp);
10631         bnxt_free_mem(bp, true);
10632         clear_bit(BNXT_STATE_HALF_OPEN, &bp->state);
10633 }
10634
10635 void bnxt_reenable_sriov(struct bnxt *bp)
10636 {
10637         if (BNXT_PF(bp)) {
10638                 struct bnxt_pf_info *pf = &bp->pf;
10639                 int n = pf->active_vfs;
10640
10641                 if (n)
10642                         bnxt_cfg_hw_sriov(bp, &n, true);
10643         }
10644 }
10645
10646 static int bnxt_open(struct net_device *dev)
10647 {
10648         struct bnxt *bp = netdev_priv(dev);
10649         int rc;
10650
10651         if (test_bit(BNXT_STATE_ABORT_ERR, &bp->state)) {
10652                 rc = bnxt_reinit_after_abort(bp);
10653                 if (rc) {
10654                         if (rc == -EBUSY)
10655                                 netdev_err(bp->dev, "A previous firmware reset has not completed, aborting\n");
10656                         else
10657                                 netdev_err(bp->dev, "Failed to reinitialize after aborted firmware reset\n");
10658                         return -ENODEV;
10659                 }
10660         }
10661
10662         rc = bnxt_hwrm_if_change(bp, true);
10663         if (rc)
10664                 return rc;
10665
10666         rc = __bnxt_open_nic(bp, true, true);
10667         if (rc) {
10668                 bnxt_hwrm_if_change(bp, false);
10669         } else {
10670                 if (test_and_clear_bit(BNXT_STATE_FW_RESET_DET, &bp->state)) {
10671                         if (!test_bit(BNXT_STATE_IN_FW_RESET, &bp->state)) {
10672                                 bnxt_ulp_start(bp, 0);
10673                                 bnxt_reenable_sriov(bp);
10674                         }
10675                 }
10676                 bnxt_hwmon_open(bp);
10677         }
10678
10679         return rc;
10680 }
10681
10682 static bool bnxt_drv_busy(struct bnxt *bp)
10683 {
10684         return (test_bit(BNXT_STATE_IN_SP_TASK, &bp->state) ||
10685                 test_bit(BNXT_STATE_READ_STATS, &bp->state));
10686 }
10687
10688 static void bnxt_get_ring_stats(struct bnxt *bp,
10689                                 struct rtnl_link_stats64 *stats);
10690
10691 static void __bnxt_close_nic(struct bnxt *bp, bool irq_re_init,
10692                              bool link_re_init)
10693 {
10694         /* Close the VF-reps before closing PF */
10695         if (BNXT_PF(bp))
10696                 bnxt_vf_reps_close(bp);
10697
10698         /* Change device state to avoid TX queue wake up's */
10699         bnxt_tx_disable(bp);
10700
10701         clear_bit(BNXT_STATE_OPEN, &bp->state);
10702         smp_mb__after_atomic();
10703         while (bnxt_drv_busy(bp))
10704                 msleep(20);
10705
10706         /* Flush rings and disable interrupts */
10707         bnxt_shutdown_nic(bp, irq_re_init);
10708
10709         /* TODO CHIMP_FW: Link/PHY related cleanup if (link_re_init) */
10710
10711         bnxt_debug_dev_exit(bp);
10712         bnxt_disable_napi(bp);
10713         del_timer_sync(&bp->timer);
10714         bnxt_free_skbs(bp);
10715
10716         /* Save ring stats before shutdown */
10717         if (bp->bnapi && irq_re_init)
10718                 bnxt_get_ring_stats(bp, &bp->net_stats_prev);
10719         if (irq_re_init) {
10720                 bnxt_free_irq(bp);
10721                 bnxt_del_napi(bp);
10722         }
10723         bnxt_free_mem(bp, irq_re_init);
10724 }
10725
10726 int bnxt_close_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init)
10727 {
10728         int rc = 0;
10729
10730         if (test_bit(BNXT_STATE_IN_FW_RESET, &bp->state)) {
10731                 /* If we get here, it means firmware reset is in progress
10732                  * while we are trying to close.  We can safely proceed with
10733                  * the close because we are holding rtnl_lock().  Some firmware
10734                  * messages may fail as we proceed to close.  We set the
10735                  * ABORT_ERR flag here so that the FW reset thread will later
10736                  * abort when it gets the rtnl_lock() and sees the flag.
10737                  */
10738                 netdev_warn(bp->dev, "FW reset in progress during close, FW reset will be aborted\n");
10739                 set_bit(BNXT_STATE_ABORT_ERR, &bp->state);
10740         }
10741
10742 #ifdef CONFIG_BNXT_SRIOV
10743         if (bp->sriov_cfg) {
10744                 rc = wait_event_interruptible_timeout(bp->sriov_cfg_wait,
10745                                                       !bp->sriov_cfg,
10746                                                       BNXT_SRIOV_CFG_WAIT_TMO);
10747                 if (rc)
10748                         netdev_warn(bp->dev, "timeout waiting for SRIOV config operation to complete!\n");
10749         }
10750 #endif
10751         __bnxt_close_nic(bp, irq_re_init, link_re_init);
10752         return rc;
10753 }
10754
10755 static int bnxt_close(struct net_device *dev)
10756 {
10757         struct bnxt *bp = netdev_priv(dev);
10758
10759         bnxt_hwmon_close(bp);
10760         bnxt_close_nic(bp, true, true);
10761         bnxt_hwrm_shutdown_link(bp);
10762         bnxt_hwrm_if_change(bp, false);
10763         return 0;
10764 }
10765
10766 static int bnxt_hwrm_port_phy_read(struct bnxt *bp, u16 phy_addr, u16 reg,
10767                                    u16 *val)
10768 {
10769         struct hwrm_port_phy_mdio_read_output *resp;
10770         struct hwrm_port_phy_mdio_read_input *req;
10771         int rc;
10772
10773         if (bp->hwrm_spec_code < 0x10a00)
10774                 return -EOPNOTSUPP;
10775
10776         rc = hwrm_req_init(bp, req, HWRM_PORT_PHY_MDIO_READ);
10777         if (rc)
10778                 return rc;
10779
10780         req->port_id = cpu_to_le16(bp->pf.port_id);
10781         req->phy_addr = phy_addr;
10782         req->reg_addr = cpu_to_le16(reg & 0x1f);
10783         if (mdio_phy_id_is_c45(phy_addr)) {
10784                 req->cl45_mdio = 1;
10785                 req->phy_addr = mdio_phy_id_prtad(phy_addr);
10786                 req->dev_addr = mdio_phy_id_devad(phy_addr);
10787                 req->reg_addr = cpu_to_le16(reg);
10788         }
10789
10790         resp = hwrm_req_hold(bp, req);
10791         rc = hwrm_req_send(bp, req);
10792         if (!rc)
10793                 *val = le16_to_cpu(resp->reg_data);
10794         hwrm_req_drop(bp, req);
10795         return rc;
10796 }
10797
10798 static int bnxt_hwrm_port_phy_write(struct bnxt *bp, u16 phy_addr, u16 reg,
10799                                     u16 val)
10800 {
10801         struct hwrm_port_phy_mdio_write_input *req;
10802         int rc;
10803
10804         if (bp->hwrm_spec_code < 0x10a00)
10805                 return -EOPNOTSUPP;
10806
10807         rc = hwrm_req_init(bp, req, HWRM_PORT_PHY_MDIO_WRITE);
10808         if (rc)
10809                 return rc;
10810
10811         req->port_id = cpu_to_le16(bp->pf.port_id);
10812         req->phy_addr = phy_addr;
10813         req->reg_addr = cpu_to_le16(reg & 0x1f);
10814         if (mdio_phy_id_is_c45(phy_addr)) {
10815                 req->cl45_mdio = 1;
10816                 req->phy_addr = mdio_phy_id_prtad(phy_addr);
10817                 req->dev_addr = mdio_phy_id_devad(phy_addr);
10818                 req->reg_addr = cpu_to_le16(reg);
10819         }
10820         req->reg_data = cpu_to_le16(val);
10821
10822         return hwrm_req_send(bp, req);
10823 }
10824
10825 /* rtnl_lock held */
10826 static int bnxt_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
10827 {
10828         struct mii_ioctl_data *mdio = if_mii(ifr);
10829         struct bnxt *bp = netdev_priv(dev);
10830         int rc;
10831
10832         switch (cmd) {
10833         case SIOCGMIIPHY:
10834                 mdio->phy_id = bp->link_info.phy_addr;
10835
10836                 fallthrough;
10837         case SIOCGMIIREG: {
10838                 u16 mii_regval = 0;
10839
10840                 if (!netif_running(dev))
10841                         return -EAGAIN;
10842
10843                 rc = bnxt_hwrm_port_phy_read(bp, mdio->phy_id, mdio->reg_num,
10844                                              &mii_regval);
10845                 mdio->val_out = mii_regval;
10846                 return rc;
10847         }
10848
10849         case SIOCSMIIREG:
10850                 if (!netif_running(dev))
10851                         return -EAGAIN;
10852
10853                 return bnxt_hwrm_port_phy_write(bp, mdio->phy_id, mdio->reg_num,
10854                                                 mdio->val_in);
10855
10856         case SIOCSHWTSTAMP:
10857                 return bnxt_hwtstamp_set(dev, ifr);
10858
10859         case SIOCGHWTSTAMP:
10860                 return bnxt_hwtstamp_get(dev, ifr);
10861
10862         default:
10863                 /* do nothing */
10864                 break;
10865         }
10866         return -EOPNOTSUPP;
10867 }
10868
10869 static void bnxt_get_ring_stats(struct bnxt *bp,
10870                                 struct rtnl_link_stats64 *stats)
10871 {
10872         int i;
10873
10874         for (i = 0; i < bp->cp_nr_rings; i++) {
10875                 struct bnxt_napi *bnapi = bp->bnapi[i];
10876                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
10877                 u64 *sw = cpr->stats.sw_stats;
10878
10879                 stats->rx_packets += BNXT_GET_RING_STATS64(sw, rx_ucast_pkts);
10880                 stats->rx_packets += BNXT_GET_RING_STATS64(sw, rx_mcast_pkts);
10881                 stats->rx_packets += BNXT_GET_RING_STATS64(sw, rx_bcast_pkts);
10882
10883                 stats->tx_packets += BNXT_GET_RING_STATS64(sw, tx_ucast_pkts);
10884                 stats->tx_packets += BNXT_GET_RING_STATS64(sw, tx_mcast_pkts);
10885                 stats->tx_packets += BNXT_GET_RING_STATS64(sw, tx_bcast_pkts);
10886
10887                 stats->rx_bytes += BNXT_GET_RING_STATS64(sw, rx_ucast_bytes);
10888                 stats->rx_bytes += BNXT_GET_RING_STATS64(sw, rx_mcast_bytes);
10889                 stats->rx_bytes += BNXT_GET_RING_STATS64(sw, rx_bcast_bytes);
10890
10891                 stats->tx_bytes += BNXT_GET_RING_STATS64(sw, tx_ucast_bytes);
10892                 stats->tx_bytes += BNXT_GET_RING_STATS64(sw, tx_mcast_bytes);
10893                 stats->tx_bytes += BNXT_GET_RING_STATS64(sw, tx_bcast_bytes);
10894
10895                 stats->rx_missed_errors +=
10896                         BNXT_GET_RING_STATS64(sw, rx_discard_pkts);
10897
10898                 stats->multicast += BNXT_GET_RING_STATS64(sw, rx_mcast_pkts);
10899
10900                 stats->tx_dropped += BNXT_GET_RING_STATS64(sw, tx_error_pkts);
10901
10902                 stats->rx_dropped +=
10903                         cpr->sw_stats.rx.rx_netpoll_discards +
10904                         cpr->sw_stats.rx.rx_oom_discards;
10905         }
10906 }
10907
10908 static void bnxt_add_prev_stats(struct bnxt *bp,
10909                                 struct rtnl_link_stats64 *stats)
10910 {
10911         struct rtnl_link_stats64 *prev_stats = &bp->net_stats_prev;
10912
10913         stats->rx_packets += prev_stats->rx_packets;
10914         stats->tx_packets += prev_stats->tx_packets;
10915         stats->rx_bytes += prev_stats->rx_bytes;
10916         stats->tx_bytes += prev_stats->tx_bytes;
10917         stats->rx_missed_errors += prev_stats->rx_missed_errors;
10918         stats->multicast += prev_stats->multicast;
10919         stats->rx_dropped += prev_stats->rx_dropped;
10920         stats->tx_dropped += prev_stats->tx_dropped;
10921 }
10922
10923 static void
10924 bnxt_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
10925 {
10926         struct bnxt *bp = netdev_priv(dev);
10927
10928         set_bit(BNXT_STATE_READ_STATS, &bp->state);
10929         /* Make sure bnxt_close_nic() sees that we are reading stats before
10930          * we check the BNXT_STATE_OPEN flag.
10931          */
10932         smp_mb__after_atomic();
10933         if (!test_bit(BNXT_STATE_OPEN, &bp->state)) {
10934                 clear_bit(BNXT_STATE_READ_STATS, &bp->state);
10935                 *stats = bp->net_stats_prev;
10936                 return;
10937         }
10938
10939         bnxt_get_ring_stats(bp, stats);
10940         bnxt_add_prev_stats(bp, stats);
10941
10942         if (bp->flags & BNXT_FLAG_PORT_STATS) {
10943                 u64 *rx = bp->port_stats.sw_stats;
10944                 u64 *tx = bp->port_stats.sw_stats +
10945                           BNXT_TX_PORT_STATS_BYTE_OFFSET / 8;
10946
10947                 stats->rx_crc_errors =
10948                         BNXT_GET_RX_PORT_STATS64(rx, rx_fcs_err_frames);
10949                 stats->rx_frame_errors =
10950                         BNXT_GET_RX_PORT_STATS64(rx, rx_align_err_frames);
10951                 stats->rx_length_errors =
10952                         BNXT_GET_RX_PORT_STATS64(rx, rx_undrsz_frames) +
10953                         BNXT_GET_RX_PORT_STATS64(rx, rx_ovrsz_frames) +
10954                         BNXT_GET_RX_PORT_STATS64(rx, rx_runt_frames);
10955                 stats->rx_errors =
10956                         BNXT_GET_RX_PORT_STATS64(rx, rx_false_carrier_frames) +
10957                         BNXT_GET_RX_PORT_STATS64(rx, rx_jbr_frames);
10958                 stats->collisions =
10959                         BNXT_GET_TX_PORT_STATS64(tx, tx_total_collisions);
10960                 stats->tx_fifo_errors =
10961                         BNXT_GET_TX_PORT_STATS64(tx, tx_fifo_underruns);
10962                 stats->tx_errors = BNXT_GET_TX_PORT_STATS64(tx, tx_err);
10963         }
10964         clear_bit(BNXT_STATE_READ_STATS, &bp->state);
10965 }
10966
10967 static bool bnxt_mc_list_updated(struct bnxt *bp, u32 *rx_mask)
10968 {
10969         struct net_device *dev = bp->dev;
10970         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
10971         struct netdev_hw_addr *ha;
10972         u8 *haddr;
10973         int mc_count = 0;
10974         bool update = false;
10975         int off = 0;
10976
10977         netdev_for_each_mc_addr(ha, dev) {
10978                 if (mc_count >= BNXT_MAX_MC_ADDRS) {
10979                         *rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST;
10980                         vnic->mc_list_count = 0;
10981                         return false;
10982                 }
10983                 haddr = ha->addr;
10984                 if (!ether_addr_equal(haddr, vnic->mc_list + off)) {
10985                         memcpy(vnic->mc_list + off, haddr, ETH_ALEN);
10986                         update = true;
10987                 }
10988                 off += ETH_ALEN;
10989                 mc_count++;
10990         }
10991         if (mc_count)
10992                 *rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_MCAST;
10993
10994         if (mc_count != vnic->mc_list_count) {
10995                 vnic->mc_list_count = mc_count;
10996                 update = true;
10997         }
10998         return update;
10999 }
11000
11001 static bool bnxt_uc_list_updated(struct bnxt *bp)
11002 {
11003         struct net_device *dev = bp->dev;
11004         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
11005         struct netdev_hw_addr *ha;
11006         int off = 0;
11007
11008         if (netdev_uc_count(dev) != (vnic->uc_filter_count - 1))
11009                 return true;
11010
11011         netdev_for_each_uc_addr(ha, dev) {
11012                 if (!ether_addr_equal(ha->addr, vnic->uc_list + off))
11013                         return true;
11014
11015                 off += ETH_ALEN;
11016         }
11017         return false;
11018 }
11019
11020 static void bnxt_set_rx_mode(struct net_device *dev)
11021 {
11022         struct bnxt *bp = netdev_priv(dev);
11023         struct bnxt_vnic_info *vnic;
11024         bool mc_update = false;
11025         bool uc_update;
11026         u32 mask;
11027
11028         if (!test_bit(BNXT_STATE_OPEN, &bp->state))
11029                 return;
11030
11031         vnic = &bp->vnic_info[0];
11032         mask = vnic->rx_mask;
11033         mask &= ~(CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS |
11034                   CFA_L2_SET_RX_MASK_REQ_MASK_MCAST |
11035                   CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST |
11036                   CFA_L2_SET_RX_MASK_REQ_MASK_BCAST);
11037
11038         if (dev->flags & IFF_PROMISC)
11039                 mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS;
11040
11041         uc_update = bnxt_uc_list_updated(bp);
11042
11043         if (dev->flags & IFF_BROADCAST)
11044                 mask |= CFA_L2_SET_RX_MASK_REQ_MASK_BCAST;
11045         if (dev->flags & IFF_ALLMULTI) {
11046                 mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST;
11047                 vnic->mc_list_count = 0;
11048         } else if (dev->flags & IFF_MULTICAST) {
11049                 mc_update = bnxt_mc_list_updated(bp, &mask);
11050         }
11051
11052         if (mask != vnic->rx_mask || uc_update || mc_update) {
11053                 vnic->rx_mask = mask;
11054
11055                 set_bit(BNXT_RX_MASK_SP_EVENT, &bp->sp_event);
11056                 bnxt_queue_sp_work(bp);
11057         }
11058 }
11059
11060 static int bnxt_cfg_rx_mode(struct bnxt *bp)
11061 {
11062         struct net_device *dev = bp->dev;
11063         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
11064         struct hwrm_cfa_l2_filter_free_input *req;
11065         struct netdev_hw_addr *ha;
11066         int i, off = 0, rc;
11067         bool uc_update;
11068
11069         netif_addr_lock_bh(dev);
11070         uc_update = bnxt_uc_list_updated(bp);
11071         netif_addr_unlock_bh(dev);
11072
11073         if (!uc_update)
11074                 goto skip_uc;
11075
11076         rc = hwrm_req_init(bp, req, HWRM_CFA_L2_FILTER_FREE);
11077         if (rc)
11078                 return rc;
11079         hwrm_req_hold(bp, req);
11080         for (i = 1; i < vnic->uc_filter_count; i++) {
11081                 req->l2_filter_id = vnic->fw_l2_filter_id[i];
11082
11083                 rc = hwrm_req_send(bp, req);
11084         }
11085         hwrm_req_drop(bp, req);
11086
11087         vnic->uc_filter_count = 1;
11088
11089         netif_addr_lock_bh(dev);
11090         if (netdev_uc_count(dev) > (BNXT_MAX_UC_ADDRS - 1)) {
11091                 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS;
11092         } else {
11093                 netdev_for_each_uc_addr(ha, dev) {
11094                         memcpy(vnic->uc_list + off, ha->addr, ETH_ALEN);
11095                         off += ETH_ALEN;
11096                         vnic->uc_filter_count++;
11097                 }
11098         }
11099         netif_addr_unlock_bh(dev);
11100
11101         for (i = 1, off = 0; i < vnic->uc_filter_count; i++, off += ETH_ALEN) {
11102                 rc = bnxt_hwrm_set_vnic_filter(bp, 0, i, vnic->uc_list + off);
11103                 if (rc) {
11104                         if (BNXT_VF(bp) && rc == -ENODEV) {
11105                                 if (!test_and_set_bit(BNXT_STATE_L2_FILTER_RETRY, &bp->state))
11106                                         netdev_warn(bp->dev, "Cannot configure L2 filters while PF is unavailable, will retry\n");
11107                                 else
11108                                         netdev_dbg(bp->dev, "PF still unavailable while configuring L2 filters.\n");
11109                                 rc = 0;
11110                         } else {
11111                                 netdev_err(bp->dev, "HWRM vnic filter failure rc: %x\n", rc);
11112                         }
11113                         vnic->uc_filter_count = i;
11114                         return rc;
11115                 }
11116         }
11117         if (test_and_clear_bit(BNXT_STATE_L2_FILTER_RETRY, &bp->state))
11118                 netdev_notice(bp->dev, "Retry of L2 filter configuration successful.\n");
11119
11120 skip_uc:
11121         if ((vnic->rx_mask & CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS) &&
11122             !bnxt_promisc_ok(bp))
11123                 vnic->rx_mask &= ~CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS;
11124         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, 0);
11125         if (rc && (vnic->rx_mask & CFA_L2_SET_RX_MASK_REQ_MASK_MCAST)) {
11126                 netdev_info(bp->dev, "Failed setting MC filters rc: %d, turning on ALL_MCAST mode\n",
11127                             rc);
11128                 vnic->rx_mask &= ~CFA_L2_SET_RX_MASK_REQ_MASK_MCAST;
11129                 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST;
11130                 vnic->mc_list_count = 0;
11131                 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, 0);
11132         }
11133         if (rc)
11134                 netdev_err(bp->dev, "HWRM cfa l2 rx mask failure rc: %d\n",
11135                            rc);
11136
11137         return rc;
11138 }
11139
11140 static bool bnxt_can_reserve_rings(struct bnxt *bp)
11141 {
11142 #ifdef CONFIG_BNXT_SRIOV
11143         if (BNXT_NEW_RM(bp) && BNXT_VF(bp)) {
11144                 struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
11145
11146                 /* No minimum rings were provisioned by the PF.  Don't
11147                  * reserve rings by default when device is down.
11148                  */
11149                 if (hw_resc->min_tx_rings || hw_resc->resv_tx_rings)
11150                         return true;
11151
11152                 if (!netif_running(bp->dev))
11153                         return false;
11154         }
11155 #endif
11156         return true;
11157 }
11158
11159 /* If the chip and firmware supports RFS */
11160 static bool bnxt_rfs_supported(struct bnxt *bp)
11161 {
11162         if (bp->flags & BNXT_FLAG_CHIP_P5) {
11163                 if (bp->fw_cap & BNXT_FW_CAP_CFA_RFS_RING_TBL_IDX_V2)
11164                         return true;
11165                 return false;
11166         }
11167         /* 212 firmware is broken for aRFS */
11168         if (BNXT_FW_MAJ(bp) == 212)
11169                 return false;
11170         if (BNXT_PF(bp) && !BNXT_CHIP_TYPE_NITRO_A0(bp))
11171                 return true;
11172         if (bp->flags & BNXT_FLAG_NEW_RSS_CAP)
11173                 return true;
11174         return false;
11175 }
11176
11177 /* If runtime conditions support RFS */
11178 static bool bnxt_rfs_capable(struct bnxt *bp)
11179 {
11180 #ifdef CONFIG_RFS_ACCEL
11181         int vnics, max_vnics, max_rss_ctxs;
11182
11183         if (bp->flags & BNXT_FLAG_CHIP_P5)
11184                 return bnxt_rfs_supported(bp);
11185         if (!(bp->flags & BNXT_FLAG_MSIX_CAP) || !bnxt_can_reserve_rings(bp) || !bp->rx_nr_rings)
11186                 return false;
11187
11188         vnics = 1 + bp->rx_nr_rings;
11189         max_vnics = bnxt_get_max_func_vnics(bp);
11190         max_rss_ctxs = bnxt_get_max_func_rss_ctxs(bp);
11191
11192         /* RSS contexts not a limiting factor */
11193         if (bp->flags & BNXT_FLAG_NEW_RSS_CAP)
11194                 max_rss_ctxs = max_vnics;
11195         if (vnics > max_vnics || vnics > max_rss_ctxs) {
11196                 if (bp->rx_nr_rings > 1)
11197                         netdev_warn(bp->dev,
11198                                     "Not enough resources to support NTUPLE filters, enough resources for up to %d rx rings\n",
11199                                     min(max_rss_ctxs - 1, max_vnics - 1));
11200                 return false;
11201         }
11202
11203         if (!BNXT_NEW_RM(bp))
11204                 return true;
11205
11206         if (vnics == bp->hw_resc.resv_vnics)
11207                 return true;
11208
11209         bnxt_hwrm_reserve_rings(bp, 0, 0, 0, 0, 0, vnics);
11210         if (vnics <= bp->hw_resc.resv_vnics)
11211                 return true;
11212
11213         netdev_warn(bp->dev, "Unable to reserve resources to support NTUPLE filters.\n");
11214         bnxt_hwrm_reserve_rings(bp, 0, 0, 0, 0, 0, 1);
11215         return false;
11216 #else
11217         return false;
11218 #endif
11219 }
11220
11221 static netdev_features_t bnxt_fix_features(struct net_device *dev,
11222                                            netdev_features_t features)
11223 {
11224         struct bnxt *bp = netdev_priv(dev);
11225         netdev_features_t vlan_features;
11226
11227         if ((features & NETIF_F_NTUPLE) && !bnxt_rfs_capable(bp))
11228                 features &= ~NETIF_F_NTUPLE;
11229
11230         if ((bp->flags & BNXT_FLAG_NO_AGG_RINGS) || bp->xdp_prog)
11231                 features &= ~(NETIF_F_LRO | NETIF_F_GRO_HW);
11232
11233         if (!(features & NETIF_F_GRO))
11234                 features &= ~NETIF_F_GRO_HW;
11235
11236         if (features & NETIF_F_GRO_HW)
11237                 features &= ~NETIF_F_LRO;
11238
11239         /* Both CTAG and STAG VLAN accelaration on the RX side have to be
11240          * turned on or off together.
11241          */
11242         vlan_features = features & BNXT_HW_FEATURE_VLAN_ALL_RX;
11243         if (vlan_features != BNXT_HW_FEATURE_VLAN_ALL_RX) {
11244                 if (dev->features & BNXT_HW_FEATURE_VLAN_ALL_RX)
11245                         features &= ~BNXT_HW_FEATURE_VLAN_ALL_RX;
11246                 else if (vlan_features)
11247                         features |= BNXT_HW_FEATURE_VLAN_ALL_RX;
11248         }
11249 #ifdef CONFIG_BNXT_SRIOV
11250         if (BNXT_VF(bp) && bp->vf.vlan)
11251                 features &= ~BNXT_HW_FEATURE_VLAN_ALL_RX;
11252 #endif
11253         return features;
11254 }
11255
11256 static int bnxt_set_features(struct net_device *dev, netdev_features_t features)
11257 {
11258         struct bnxt *bp = netdev_priv(dev);
11259         u32 flags = bp->flags;
11260         u32 changes;
11261         int rc = 0;
11262         bool re_init = false;
11263         bool update_tpa = false;
11264
11265         flags &= ~BNXT_FLAG_ALL_CONFIG_FEATS;
11266         if (features & NETIF_F_GRO_HW)
11267                 flags |= BNXT_FLAG_GRO;
11268         else if (features & NETIF_F_LRO)
11269                 flags |= BNXT_FLAG_LRO;
11270
11271         if (bp->flags & BNXT_FLAG_NO_AGG_RINGS)
11272                 flags &= ~BNXT_FLAG_TPA;
11273
11274         if (features & BNXT_HW_FEATURE_VLAN_ALL_RX)
11275                 flags |= BNXT_FLAG_STRIP_VLAN;
11276
11277         if (features & NETIF_F_NTUPLE)
11278                 flags |= BNXT_FLAG_RFS;
11279
11280         changes = flags ^ bp->flags;
11281         if (changes & BNXT_FLAG_TPA) {
11282                 update_tpa = true;
11283                 if ((bp->flags & BNXT_FLAG_TPA) == 0 ||
11284                     (flags & BNXT_FLAG_TPA) == 0 ||
11285                     (bp->flags & BNXT_FLAG_CHIP_P5))
11286                         re_init = true;
11287         }
11288
11289         if (changes & ~BNXT_FLAG_TPA)
11290                 re_init = true;
11291
11292         if (flags != bp->flags) {
11293                 u32 old_flags = bp->flags;
11294
11295                 if (!test_bit(BNXT_STATE_OPEN, &bp->state)) {
11296                         bp->flags = flags;
11297                         if (update_tpa)
11298                                 bnxt_set_ring_params(bp);
11299                         return rc;
11300                 }
11301
11302                 if (re_init) {
11303                         bnxt_close_nic(bp, false, false);
11304                         bp->flags = flags;
11305                         if (update_tpa)
11306                                 bnxt_set_ring_params(bp);
11307
11308                         return bnxt_open_nic(bp, false, false);
11309                 }
11310                 if (update_tpa) {
11311                         bp->flags = flags;
11312                         rc = bnxt_set_tpa(bp,
11313                                           (flags & BNXT_FLAG_TPA) ?
11314                                           true : false);
11315                         if (rc)
11316                                 bp->flags = old_flags;
11317                 }
11318         }
11319         return rc;
11320 }
11321
11322 static bool bnxt_exthdr_check(struct bnxt *bp, struct sk_buff *skb, int nw_off,
11323                               u8 **nextp)
11324 {
11325         struct ipv6hdr *ip6h = (struct ipv6hdr *)(skb->data + nw_off);
11326         struct hop_jumbo_hdr *jhdr;
11327         int hdr_count = 0;
11328         u8 *nexthdr;
11329         int start;
11330
11331         /* Check that there are at most 2 IPv6 extension headers, no
11332          * fragment header, and each is <= 64 bytes.
11333          */
11334         start = nw_off + sizeof(*ip6h);
11335         nexthdr = &ip6h->nexthdr;
11336         while (ipv6_ext_hdr(*nexthdr)) {
11337                 struct ipv6_opt_hdr *hp;
11338                 int hdrlen;
11339
11340                 if (hdr_count >= 3 || *nexthdr == NEXTHDR_NONE ||
11341                     *nexthdr == NEXTHDR_FRAGMENT)
11342                         return false;
11343                 hp = __skb_header_pointer(NULL, start, sizeof(*hp), skb->data,
11344                                           skb_headlen(skb), NULL);
11345                 if (!hp)
11346                         return false;
11347                 if (*nexthdr == NEXTHDR_AUTH)
11348                         hdrlen = ipv6_authlen(hp);
11349                 else
11350                         hdrlen = ipv6_optlen(hp);
11351
11352                 if (hdrlen > 64)
11353                         return false;
11354
11355                 /* The ext header may be a hop-by-hop header inserted for
11356                  * big TCP purposes. This will be removed before sending
11357                  * from NIC, so do not count it.
11358                  */
11359                 if (*nexthdr == NEXTHDR_HOP) {
11360                         if (likely(skb->len <= GRO_LEGACY_MAX_SIZE))
11361                                 goto increment_hdr;
11362
11363                         jhdr = (struct hop_jumbo_hdr *)hp;
11364                         if (jhdr->tlv_type != IPV6_TLV_JUMBO || jhdr->hdrlen != 0 ||
11365                             jhdr->nexthdr != IPPROTO_TCP)
11366                                 goto increment_hdr;
11367
11368                         goto next_hdr;
11369                 }
11370 increment_hdr:
11371                 hdr_count++;
11372 next_hdr:
11373                 nexthdr = &hp->nexthdr;
11374                 start += hdrlen;
11375         }
11376         if (nextp) {
11377                 /* Caller will check inner protocol */
11378                 if (skb->encapsulation) {
11379                         *nextp = nexthdr;
11380                         return true;
11381                 }
11382                 *nextp = NULL;
11383         }
11384         /* Only support TCP/UDP for non-tunneled ipv6 and inner ipv6 */
11385         return *nexthdr == IPPROTO_TCP || *nexthdr == IPPROTO_UDP;
11386 }
11387
11388 /* For UDP, we can only handle 1 Vxlan port and 1 Geneve port. */
11389 static bool bnxt_udp_tunl_check(struct bnxt *bp, struct sk_buff *skb)
11390 {
11391         struct udphdr *uh = udp_hdr(skb);
11392         __be16 udp_port = uh->dest;
11393
11394         if (udp_port != bp->vxlan_port && udp_port != bp->nge_port)
11395                 return false;
11396         if (skb->inner_protocol_type == ENCAP_TYPE_ETHER) {
11397                 struct ethhdr *eh = inner_eth_hdr(skb);
11398
11399                 switch (eh->h_proto) {
11400                 case htons(ETH_P_IP):
11401                         return true;
11402                 case htons(ETH_P_IPV6):
11403                         return bnxt_exthdr_check(bp, skb,
11404                                                  skb_inner_network_offset(skb),
11405                                                  NULL);
11406                 }
11407         }
11408         return false;
11409 }
11410
11411 static bool bnxt_tunl_check(struct bnxt *bp, struct sk_buff *skb, u8 l4_proto)
11412 {
11413         switch (l4_proto) {
11414         case IPPROTO_UDP:
11415                 return bnxt_udp_tunl_check(bp, skb);
11416         case IPPROTO_IPIP:
11417                 return true;
11418         case IPPROTO_GRE: {
11419                 switch (skb->inner_protocol) {
11420                 default:
11421                         return false;
11422                 case htons(ETH_P_IP):
11423                         return true;
11424                 case htons(ETH_P_IPV6):
11425                         fallthrough;
11426                 }
11427         }
11428         case IPPROTO_IPV6:
11429                 /* Check ext headers of inner ipv6 */
11430                 return bnxt_exthdr_check(bp, skb, skb_inner_network_offset(skb),
11431                                          NULL);
11432         }
11433         return false;
11434 }
11435
11436 static netdev_features_t bnxt_features_check(struct sk_buff *skb,
11437                                              struct net_device *dev,
11438                                              netdev_features_t features)
11439 {
11440         struct bnxt *bp = netdev_priv(dev);
11441         u8 *l4_proto;
11442
11443         features = vlan_features_check(skb, features);
11444         switch (vlan_get_protocol(skb)) {
11445         case htons(ETH_P_IP):
11446                 if (!skb->encapsulation)
11447                         return features;
11448                 l4_proto = &ip_hdr(skb)->protocol;
11449                 if (bnxt_tunl_check(bp, skb, *l4_proto))
11450                         return features;
11451                 break;
11452         case htons(ETH_P_IPV6):
11453                 if (!bnxt_exthdr_check(bp, skb, skb_network_offset(skb),
11454                                        &l4_proto))
11455                         break;
11456                 if (!l4_proto || bnxt_tunl_check(bp, skb, *l4_proto))
11457                         return features;
11458                 break;
11459         }
11460         return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
11461 }
11462
11463 int bnxt_dbg_hwrm_rd_reg(struct bnxt *bp, u32 reg_off, u16 num_words,
11464                          u32 *reg_buf)
11465 {
11466         struct hwrm_dbg_read_direct_output *resp;
11467         struct hwrm_dbg_read_direct_input *req;
11468         __le32 *dbg_reg_buf;
11469         dma_addr_t mapping;
11470         int rc, i;
11471
11472         rc = hwrm_req_init(bp, req, HWRM_DBG_READ_DIRECT);
11473         if (rc)
11474                 return rc;
11475
11476         dbg_reg_buf = hwrm_req_dma_slice(bp, req, num_words * 4,
11477                                          &mapping);
11478         if (!dbg_reg_buf) {
11479                 rc = -ENOMEM;
11480                 goto dbg_rd_reg_exit;
11481         }
11482
11483         req->host_dest_addr = cpu_to_le64(mapping);
11484
11485         resp = hwrm_req_hold(bp, req);
11486         req->read_addr = cpu_to_le32(reg_off + CHIMP_REG_VIEW_ADDR);
11487         req->read_len32 = cpu_to_le32(num_words);
11488
11489         rc = hwrm_req_send(bp, req);
11490         if (rc || resp->error_code) {
11491                 rc = -EIO;
11492                 goto dbg_rd_reg_exit;
11493         }
11494         for (i = 0; i < num_words; i++)
11495                 reg_buf[i] = le32_to_cpu(dbg_reg_buf[i]);
11496
11497 dbg_rd_reg_exit:
11498         hwrm_req_drop(bp, req);
11499         return rc;
11500 }
11501
11502 static int bnxt_dbg_hwrm_ring_info_get(struct bnxt *bp, u8 ring_type,
11503                                        u32 ring_id, u32 *prod, u32 *cons)
11504 {
11505         struct hwrm_dbg_ring_info_get_output *resp;
11506         struct hwrm_dbg_ring_info_get_input *req;
11507         int rc;
11508
11509         rc = hwrm_req_init(bp, req, HWRM_DBG_RING_INFO_GET);
11510         if (rc)
11511                 return rc;
11512
11513         req->ring_type = ring_type;
11514         req->fw_ring_id = cpu_to_le32(ring_id);
11515         resp = hwrm_req_hold(bp, req);
11516         rc = hwrm_req_send(bp, req);
11517         if (!rc) {
11518                 *prod = le32_to_cpu(resp->producer_index);
11519                 *cons = le32_to_cpu(resp->consumer_index);
11520         }
11521         hwrm_req_drop(bp, req);
11522         return rc;
11523 }
11524
11525 static void bnxt_dump_tx_sw_state(struct bnxt_napi *bnapi)
11526 {
11527         struct bnxt_tx_ring_info *txr = bnapi->tx_ring;
11528         int i = bnapi->index;
11529
11530         if (!txr)
11531                 return;
11532
11533         netdev_info(bnapi->bp->dev, "[%d]: tx{fw_ring: %d prod: %x cons: %x}\n",
11534                     i, txr->tx_ring_struct.fw_ring_id, txr->tx_prod,
11535                     txr->tx_cons);
11536 }
11537
11538 static void bnxt_dump_rx_sw_state(struct bnxt_napi *bnapi)
11539 {
11540         struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
11541         int i = bnapi->index;
11542
11543         if (!rxr)
11544                 return;
11545
11546         netdev_info(bnapi->bp->dev, "[%d]: rx{fw_ring: %d prod: %x} rx_agg{fw_ring: %d agg_prod: %x sw_agg_prod: %x}\n",
11547                     i, rxr->rx_ring_struct.fw_ring_id, rxr->rx_prod,
11548                     rxr->rx_agg_ring_struct.fw_ring_id, rxr->rx_agg_prod,
11549                     rxr->rx_sw_agg_prod);
11550 }
11551
11552 static void bnxt_dump_cp_sw_state(struct bnxt_napi *bnapi)
11553 {
11554         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
11555         int i = bnapi->index;
11556
11557         netdev_info(bnapi->bp->dev, "[%d]: cp{fw_ring: %d raw_cons: %x}\n",
11558                     i, cpr->cp_ring_struct.fw_ring_id, cpr->cp_raw_cons);
11559 }
11560
11561 static void bnxt_dbg_dump_states(struct bnxt *bp)
11562 {
11563         int i;
11564         struct bnxt_napi *bnapi;
11565
11566         for (i = 0; i < bp->cp_nr_rings; i++) {
11567                 bnapi = bp->bnapi[i];
11568                 if (netif_msg_drv(bp)) {
11569                         bnxt_dump_tx_sw_state(bnapi);
11570                         bnxt_dump_rx_sw_state(bnapi);
11571                         bnxt_dump_cp_sw_state(bnapi);
11572                 }
11573         }
11574 }
11575
11576 static int bnxt_hwrm_rx_ring_reset(struct bnxt *bp, int ring_nr)
11577 {
11578         struct bnxt_rx_ring_info *rxr = &bp->rx_ring[ring_nr];
11579         struct hwrm_ring_reset_input *req;
11580         struct bnxt_napi *bnapi = rxr->bnapi;
11581         struct bnxt_cp_ring_info *cpr;
11582         u16 cp_ring_id;
11583         int rc;
11584
11585         rc = hwrm_req_init(bp, req, HWRM_RING_RESET);
11586         if (rc)
11587                 return rc;
11588
11589         cpr = &bnapi->cp_ring;
11590         cp_ring_id = cpr->cp_ring_struct.fw_ring_id;
11591         req->cmpl_ring = cpu_to_le16(cp_ring_id);
11592         req->ring_type = RING_RESET_REQ_RING_TYPE_RX_RING_GRP;
11593         req->ring_id = cpu_to_le16(bp->grp_info[bnapi->index].fw_grp_id);
11594         return hwrm_req_send_silent(bp, req);
11595 }
11596
11597 static void bnxt_reset_task(struct bnxt *bp, bool silent)
11598 {
11599         if (!silent)
11600                 bnxt_dbg_dump_states(bp);
11601         if (netif_running(bp->dev)) {
11602                 int rc;
11603
11604                 if (silent) {
11605                         bnxt_close_nic(bp, false, false);
11606                         bnxt_open_nic(bp, false, false);
11607                 } else {
11608                         bnxt_ulp_stop(bp);
11609                         bnxt_close_nic(bp, true, false);
11610                         rc = bnxt_open_nic(bp, true, false);
11611                         bnxt_ulp_start(bp, rc);
11612                 }
11613         }
11614 }
11615
11616 static void bnxt_tx_timeout(struct net_device *dev, unsigned int txqueue)
11617 {
11618         struct bnxt *bp = netdev_priv(dev);
11619
11620         netdev_err(bp->dev,  "TX timeout detected, starting reset task!\n");
11621         set_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event);
11622         bnxt_queue_sp_work(bp);
11623 }
11624
11625 static void bnxt_fw_health_check(struct bnxt *bp)
11626 {
11627         struct bnxt_fw_health *fw_health = bp->fw_health;
11628         u32 val;
11629
11630         if (!fw_health->enabled || test_bit(BNXT_STATE_IN_FW_RESET, &bp->state))
11631                 return;
11632
11633         /* Make sure it is enabled before checking the tmr_counter. */
11634         smp_rmb();
11635         if (fw_health->tmr_counter) {
11636                 fw_health->tmr_counter--;
11637                 return;
11638         }
11639
11640         val = bnxt_fw_health_readl(bp, BNXT_FW_HEARTBEAT_REG);
11641         if (val == fw_health->last_fw_heartbeat) {
11642                 fw_health->arrests++;
11643                 goto fw_reset;
11644         }
11645
11646         fw_health->last_fw_heartbeat = val;
11647
11648         val = bnxt_fw_health_readl(bp, BNXT_FW_RESET_CNT_REG);
11649         if (val != fw_health->last_fw_reset_cnt) {
11650                 fw_health->discoveries++;
11651                 goto fw_reset;
11652         }
11653
11654         fw_health->tmr_counter = fw_health->tmr_multiplier;
11655         return;
11656
11657 fw_reset:
11658         set_bit(BNXT_FW_EXCEPTION_SP_EVENT, &bp->sp_event);
11659         bnxt_queue_sp_work(bp);
11660 }
11661
11662 static void bnxt_timer(struct timer_list *t)
11663 {
11664         struct bnxt *bp = from_timer(bp, t, timer);
11665         struct net_device *dev = bp->dev;
11666
11667         if (!netif_running(dev) || !test_bit(BNXT_STATE_OPEN, &bp->state))
11668                 return;
11669
11670         if (atomic_read(&bp->intr_sem) != 0)
11671                 goto bnxt_restart_timer;
11672
11673         if (bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY)
11674                 bnxt_fw_health_check(bp);
11675
11676         if (BNXT_LINK_IS_UP(bp) && bp->stats_coal_ticks) {
11677                 set_bit(BNXT_PERIODIC_STATS_SP_EVENT, &bp->sp_event);
11678                 bnxt_queue_sp_work(bp);
11679         }
11680
11681         if (bnxt_tc_flower_enabled(bp)) {
11682                 set_bit(BNXT_FLOW_STATS_SP_EVENT, &bp->sp_event);
11683                 bnxt_queue_sp_work(bp);
11684         }
11685
11686 #ifdef CONFIG_RFS_ACCEL
11687         if ((bp->flags & BNXT_FLAG_RFS) && bp->ntp_fltr_count) {
11688                 set_bit(BNXT_RX_NTP_FLTR_SP_EVENT, &bp->sp_event);
11689                 bnxt_queue_sp_work(bp);
11690         }
11691 #endif /*CONFIG_RFS_ACCEL*/
11692
11693         if (bp->link_info.phy_retry) {
11694                 if (time_after(jiffies, bp->link_info.phy_retry_expires)) {
11695                         bp->link_info.phy_retry = false;
11696                         netdev_warn(bp->dev, "failed to update phy settings after maximum retries.\n");
11697                 } else {
11698                         set_bit(BNXT_UPDATE_PHY_SP_EVENT, &bp->sp_event);
11699                         bnxt_queue_sp_work(bp);
11700                 }
11701         }
11702
11703         if (test_bit(BNXT_STATE_L2_FILTER_RETRY, &bp->state)) {
11704                 set_bit(BNXT_RX_MASK_SP_EVENT, &bp->sp_event);
11705                 bnxt_queue_sp_work(bp);
11706         }
11707
11708         if ((bp->flags & BNXT_FLAG_CHIP_P5) && !bp->chip_rev &&
11709             netif_carrier_ok(dev)) {
11710                 set_bit(BNXT_RING_COAL_NOW_SP_EVENT, &bp->sp_event);
11711                 bnxt_queue_sp_work(bp);
11712         }
11713 bnxt_restart_timer:
11714         mod_timer(&bp->timer, jiffies + bp->current_interval);
11715 }
11716
11717 static void bnxt_rtnl_lock_sp(struct bnxt *bp)
11718 {
11719         /* We are called from bnxt_sp_task which has BNXT_STATE_IN_SP_TASK
11720          * set.  If the device is being closed, bnxt_close() may be holding
11721          * rtnl() and waiting for BNXT_STATE_IN_SP_TASK to clear.  So we
11722          * must clear BNXT_STATE_IN_SP_TASK before holding rtnl().
11723          */
11724         clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
11725         rtnl_lock();
11726 }
11727
11728 static void bnxt_rtnl_unlock_sp(struct bnxt *bp)
11729 {
11730         set_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
11731         rtnl_unlock();
11732 }
11733
11734 /* Only called from bnxt_sp_task() */
11735 static void bnxt_reset(struct bnxt *bp, bool silent)
11736 {
11737         bnxt_rtnl_lock_sp(bp);
11738         if (test_bit(BNXT_STATE_OPEN, &bp->state))
11739                 bnxt_reset_task(bp, silent);
11740         bnxt_rtnl_unlock_sp(bp);
11741 }
11742
11743 /* Only called from bnxt_sp_task() */
11744 static void bnxt_rx_ring_reset(struct bnxt *bp)
11745 {
11746         int i;
11747
11748         bnxt_rtnl_lock_sp(bp);
11749         if (!test_bit(BNXT_STATE_OPEN, &bp->state)) {
11750                 bnxt_rtnl_unlock_sp(bp);
11751                 return;
11752         }
11753         /* Disable and flush TPA before resetting the RX ring */
11754         if (bp->flags & BNXT_FLAG_TPA)
11755                 bnxt_set_tpa(bp, false);
11756         for (i = 0; i < bp->rx_nr_rings; i++) {
11757                 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
11758                 struct bnxt_cp_ring_info *cpr;
11759                 int rc;
11760
11761                 if (!rxr->bnapi->in_reset)
11762                         continue;
11763
11764                 rc = bnxt_hwrm_rx_ring_reset(bp, i);
11765                 if (rc) {
11766                         if (rc == -EINVAL || rc == -EOPNOTSUPP)
11767                                 netdev_info_once(bp->dev, "RX ring reset not supported by firmware, falling back to global reset\n");
11768                         else
11769                                 netdev_warn(bp->dev, "RX ring reset failed, rc = %d, falling back to global reset\n",
11770                                             rc);
11771                         bnxt_reset_task(bp, true);
11772                         break;
11773                 }
11774                 bnxt_free_one_rx_ring_skbs(bp, i);
11775                 rxr->rx_prod = 0;
11776                 rxr->rx_agg_prod = 0;
11777                 rxr->rx_sw_agg_prod = 0;
11778                 rxr->rx_next_cons = 0;
11779                 rxr->bnapi->in_reset = false;
11780                 bnxt_alloc_one_rx_ring(bp, i);
11781                 cpr = &rxr->bnapi->cp_ring;
11782                 cpr->sw_stats.rx.rx_resets++;
11783                 if (bp->flags & BNXT_FLAG_AGG_RINGS)
11784                         bnxt_db_write(bp, &rxr->rx_agg_db, rxr->rx_agg_prod);
11785                 bnxt_db_write(bp, &rxr->rx_db, rxr->rx_prod);
11786         }
11787         if (bp->flags & BNXT_FLAG_TPA)
11788                 bnxt_set_tpa(bp, true);
11789         bnxt_rtnl_unlock_sp(bp);
11790 }
11791
11792 static void bnxt_fw_reset_close(struct bnxt *bp)
11793 {
11794         bnxt_ulp_stop(bp);
11795         /* When firmware is in fatal state, quiesce device and disable
11796          * bus master to prevent any potential bad DMAs before freeing
11797          * kernel memory.
11798          */
11799         if (test_bit(BNXT_STATE_FW_FATAL_COND, &bp->state)) {
11800                 u16 val = 0;
11801
11802                 pci_read_config_word(bp->pdev, PCI_SUBSYSTEM_ID, &val);
11803                 if (val == 0xffff)
11804                         bp->fw_reset_min_dsecs = 0;
11805                 bnxt_tx_disable(bp);
11806                 bnxt_disable_napi(bp);
11807                 bnxt_disable_int_sync(bp);
11808                 bnxt_free_irq(bp);
11809                 bnxt_clear_int_mode(bp);
11810                 pci_disable_device(bp->pdev);
11811         }
11812         __bnxt_close_nic(bp, true, false);
11813         bnxt_vf_reps_free(bp);
11814         bnxt_clear_int_mode(bp);
11815         bnxt_hwrm_func_drv_unrgtr(bp);
11816         if (pci_is_enabled(bp->pdev))
11817                 pci_disable_device(bp->pdev);
11818         bnxt_free_ctx_mem(bp);
11819         kfree(bp->ctx);
11820         bp->ctx = NULL;
11821 }
11822
11823 static bool is_bnxt_fw_ok(struct bnxt *bp)
11824 {
11825         struct bnxt_fw_health *fw_health = bp->fw_health;
11826         bool no_heartbeat = false, has_reset = false;
11827         u32 val;
11828
11829         val = bnxt_fw_health_readl(bp, BNXT_FW_HEARTBEAT_REG);
11830         if (val == fw_health->last_fw_heartbeat)
11831                 no_heartbeat = true;
11832
11833         val = bnxt_fw_health_readl(bp, BNXT_FW_RESET_CNT_REG);
11834         if (val != fw_health->last_fw_reset_cnt)
11835                 has_reset = true;
11836
11837         if (!no_heartbeat && has_reset)
11838                 return true;
11839
11840         return false;
11841 }
11842
11843 /* rtnl_lock is acquired before calling this function */
11844 static void bnxt_force_fw_reset(struct bnxt *bp)
11845 {
11846         struct bnxt_fw_health *fw_health = bp->fw_health;
11847         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
11848         u32 wait_dsecs;
11849
11850         if (!test_bit(BNXT_STATE_OPEN, &bp->state) ||
11851             test_bit(BNXT_STATE_IN_FW_RESET, &bp->state))
11852                 return;
11853
11854         if (ptp) {
11855                 spin_lock_bh(&ptp->ptp_lock);
11856                 set_bit(BNXT_STATE_IN_FW_RESET, &bp->state);
11857                 spin_unlock_bh(&ptp->ptp_lock);
11858         } else {
11859                 set_bit(BNXT_STATE_IN_FW_RESET, &bp->state);
11860         }
11861         bnxt_fw_reset_close(bp);
11862         wait_dsecs = fw_health->master_func_wait_dsecs;
11863         if (fw_health->primary) {
11864                 if (fw_health->flags & ERROR_RECOVERY_QCFG_RESP_FLAGS_CO_CPU)
11865                         wait_dsecs = 0;
11866                 bp->fw_reset_state = BNXT_FW_RESET_STATE_RESET_FW;
11867         } else {
11868                 bp->fw_reset_timestamp = jiffies + wait_dsecs * HZ / 10;
11869                 wait_dsecs = fw_health->normal_func_wait_dsecs;
11870                 bp->fw_reset_state = BNXT_FW_RESET_STATE_ENABLE_DEV;
11871         }
11872
11873         bp->fw_reset_min_dsecs = fw_health->post_reset_wait_dsecs;
11874         bp->fw_reset_max_dsecs = fw_health->post_reset_max_wait_dsecs;
11875         bnxt_queue_fw_reset_work(bp, wait_dsecs * HZ / 10);
11876 }
11877
11878 void bnxt_fw_exception(struct bnxt *bp)
11879 {
11880         netdev_warn(bp->dev, "Detected firmware fatal condition, initiating reset\n");
11881         set_bit(BNXT_STATE_FW_FATAL_COND, &bp->state);
11882         bnxt_rtnl_lock_sp(bp);
11883         bnxt_force_fw_reset(bp);
11884         bnxt_rtnl_unlock_sp(bp);
11885 }
11886
11887 /* Returns the number of registered VFs, or 1 if VF configuration is pending, or
11888  * < 0 on error.
11889  */
11890 static int bnxt_get_registered_vfs(struct bnxt *bp)
11891 {
11892 #ifdef CONFIG_BNXT_SRIOV
11893         int rc;
11894
11895         if (!BNXT_PF(bp))
11896                 return 0;
11897
11898         rc = bnxt_hwrm_func_qcfg(bp);
11899         if (rc) {
11900                 netdev_err(bp->dev, "func_qcfg cmd failed, rc = %d\n", rc);
11901                 return rc;
11902         }
11903         if (bp->pf.registered_vfs)
11904                 return bp->pf.registered_vfs;
11905         if (bp->sriov_cfg)
11906                 return 1;
11907 #endif
11908         return 0;
11909 }
11910
11911 void bnxt_fw_reset(struct bnxt *bp)
11912 {
11913         bnxt_rtnl_lock_sp(bp);
11914         if (test_bit(BNXT_STATE_OPEN, &bp->state) &&
11915             !test_bit(BNXT_STATE_IN_FW_RESET, &bp->state)) {
11916                 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
11917                 int n = 0, tmo;
11918
11919                 if (ptp) {
11920                         spin_lock_bh(&ptp->ptp_lock);
11921                         set_bit(BNXT_STATE_IN_FW_RESET, &bp->state);
11922                         spin_unlock_bh(&ptp->ptp_lock);
11923                 } else {
11924                         set_bit(BNXT_STATE_IN_FW_RESET, &bp->state);
11925                 }
11926                 if (bp->pf.active_vfs &&
11927                     !test_bit(BNXT_STATE_FW_FATAL_COND, &bp->state))
11928                         n = bnxt_get_registered_vfs(bp);
11929                 if (n < 0) {
11930                         netdev_err(bp->dev, "Firmware reset aborted, rc = %d\n",
11931                                    n);
11932                         clear_bit(BNXT_STATE_IN_FW_RESET, &bp->state);
11933                         dev_close(bp->dev);
11934                         goto fw_reset_exit;
11935                 } else if (n > 0) {
11936                         u16 vf_tmo_dsecs = n * 10;
11937
11938                         if (bp->fw_reset_max_dsecs < vf_tmo_dsecs)
11939                                 bp->fw_reset_max_dsecs = vf_tmo_dsecs;
11940                         bp->fw_reset_state =
11941                                 BNXT_FW_RESET_STATE_POLL_VF;
11942                         bnxt_queue_fw_reset_work(bp, HZ / 10);
11943                         goto fw_reset_exit;
11944                 }
11945                 bnxt_fw_reset_close(bp);
11946                 if (bp->fw_cap & BNXT_FW_CAP_ERR_RECOVER_RELOAD) {
11947                         bp->fw_reset_state = BNXT_FW_RESET_STATE_POLL_FW_DOWN;
11948                         tmo = HZ / 10;
11949                 } else {
11950                         bp->fw_reset_state = BNXT_FW_RESET_STATE_ENABLE_DEV;
11951                         tmo = bp->fw_reset_min_dsecs * HZ / 10;
11952                 }
11953                 bnxt_queue_fw_reset_work(bp, tmo);
11954         }
11955 fw_reset_exit:
11956         bnxt_rtnl_unlock_sp(bp);
11957 }
11958
11959 static void bnxt_chk_missed_irq(struct bnxt *bp)
11960 {
11961         int i;
11962
11963         if (!(bp->flags & BNXT_FLAG_CHIP_P5))
11964                 return;
11965
11966         for (i = 0; i < bp->cp_nr_rings; i++) {
11967                 struct bnxt_napi *bnapi = bp->bnapi[i];
11968                 struct bnxt_cp_ring_info *cpr;
11969                 u32 fw_ring_id;
11970                 int j;
11971
11972                 if (!bnapi)
11973                         continue;
11974
11975                 cpr = &bnapi->cp_ring;
11976                 for (j = 0; j < 2; j++) {
11977                         struct bnxt_cp_ring_info *cpr2 = cpr->cp_ring_arr[j];
11978                         u32 val[2];
11979
11980                         if (!cpr2 || cpr2->has_more_work ||
11981                             !bnxt_has_work(bp, cpr2))
11982                                 continue;
11983
11984                         if (cpr2->cp_raw_cons != cpr2->last_cp_raw_cons) {
11985                                 cpr2->last_cp_raw_cons = cpr2->cp_raw_cons;
11986                                 continue;
11987                         }
11988                         fw_ring_id = cpr2->cp_ring_struct.fw_ring_id;
11989                         bnxt_dbg_hwrm_ring_info_get(bp,
11990                                 DBG_RING_INFO_GET_REQ_RING_TYPE_L2_CMPL,
11991                                 fw_ring_id, &val[0], &val[1]);
11992                         cpr->sw_stats.cmn.missed_irqs++;
11993                 }
11994         }
11995 }
11996
11997 static void bnxt_cfg_ntp_filters(struct bnxt *);
11998
11999 static void bnxt_init_ethtool_link_settings(struct bnxt *bp)
12000 {
12001         struct bnxt_link_info *link_info = &bp->link_info;
12002
12003         if (BNXT_AUTO_MODE(link_info->auto_mode)) {
12004                 link_info->autoneg = BNXT_AUTONEG_SPEED;
12005                 if (bp->hwrm_spec_code >= 0x10201) {
12006                         if (link_info->auto_pause_setting &
12007                             PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE)
12008                                 link_info->autoneg |= BNXT_AUTONEG_FLOW_CTRL;
12009                 } else {
12010                         link_info->autoneg |= BNXT_AUTONEG_FLOW_CTRL;
12011                 }
12012                 link_info->advertising = link_info->auto_link_speeds;
12013                 link_info->advertising_pam4 = link_info->auto_pam4_link_speeds;
12014         } else {
12015                 link_info->req_link_speed = link_info->force_link_speed;
12016                 link_info->req_signal_mode = BNXT_SIG_MODE_NRZ;
12017                 if (link_info->force_pam4_link_speed) {
12018                         link_info->req_link_speed =
12019                                 link_info->force_pam4_link_speed;
12020                         link_info->req_signal_mode = BNXT_SIG_MODE_PAM4;
12021                 }
12022                 link_info->req_duplex = link_info->duplex_setting;
12023         }
12024         if (link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL)
12025                 link_info->req_flow_ctrl =
12026                         link_info->auto_pause_setting & BNXT_LINK_PAUSE_BOTH;
12027         else
12028                 link_info->req_flow_ctrl = link_info->force_pause_setting;
12029 }
12030
12031 static void bnxt_fw_echo_reply(struct bnxt *bp)
12032 {
12033         struct bnxt_fw_health *fw_health = bp->fw_health;
12034         struct hwrm_func_echo_response_input *req;
12035         int rc;
12036
12037         rc = hwrm_req_init(bp, req, HWRM_FUNC_ECHO_RESPONSE);
12038         if (rc)
12039                 return;
12040         req->event_data1 = cpu_to_le32(fw_health->echo_req_data1);
12041         req->event_data2 = cpu_to_le32(fw_health->echo_req_data2);
12042         hwrm_req_send(bp, req);
12043 }
12044
12045 static void bnxt_sp_task(struct work_struct *work)
12046 {
12047         struct bnxt *bp = container_of(work, struct bnxt, sp_task);
12048
12049         set_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
12050         smp_mb__after_atomic();
12051         if (!test_bit(BNXT_STATE_OPEN, &bp->state)) {
12052                 clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
12053                 return;
12054         }
12055
12056         if (test_and_clear_bit(BNXT_RX_MASK_SP_EVENT, &bp->sp_event))
12057                 bnxt_cfg_rx_mode(bp);
12058
12059         if (test_and_clear_bit(BNXT_RX_NTP_FLTR_SP_EVENT, &bp->sp_event))
12060                 bnxt_cfg_ntp_filters(bp);
12061         if (test_and_clear_bit(BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT, &bp->sp_event))
12062                 bnxt_hwrm_exec_fwd_req(bp);
12063         if (test_and_clear_bit(BNXT_PERIODIC_STATS_SP_EVENT, &bp->sp_event)) {
12064                 bnxt_hwrm_port_qstats(bp, 0);
12065                 bnxt_hwrm_port_qstats_ext(bp, 0);
12066                 bnxt_accumulate_all_stats(bp);
12067         }
12068
12069         if (test_and_clear_bit(BNXT_LINK_CHNG_SP_EVENT, &bp->sp_event)) {
12070                 int rc;
12071
12072                 mutex_lock(&bp->link_lock);
12073                 if (test_and_clear_bit(BNXT_LINK_SPEED_CHNG_SP_EVENT,
12074                                        &bp->sp_event))
12075                         bnxt_hwrm_phy_qcaps(bp);
12076
12077                 rc = bnxt_update_link(bp, true);
12078                 if (rc)
12079                         netdev_err(bp->dev, "SP task can't update link (rc: %x)\n",
12080                                    rc);
12081
12082                 if (test_and_clear_bit(BNXT_LINK_CFG_CHANGE_SP_EVENT,
12083                                        &bp->sp_event))
12084                         bnxt_init_ethtool_link_settings(bp);
12085                 mutex_unlock(&bp->link_lock);
12086         }
12087         if (test_and_clear_bit(BNXT_UPDATE_PHY_SP_EVENT, &bp->sp_event)) {
12088                 int rc;
12089
12090                 mutex_lock(&bp->link_lock);
12091                 rc = bnxt_update_phy_setting(bp);
12092                 mutex_unlock(&bp->link_lock);
12093                 if (rc) {
12094                         netdev_warn(bp->dev, "update phy settings retry failed\n");
12095                 } else {
12096                         bp->link_info.phy_retry = false;
12097                         netdev_info(bp->dev, "update phy settings retry succeeded\n");
12098                 }
12099         }
12100         if (test_and_clear_bit(BNXT_HWRM_PORT_MODULE_SP_EVENT, &bp->sp_event)) {
12101                 mutex_lock(&bp->link_lock);
12102                 bnxt_get_port_module_status(bp);
12103                 mutex_unlock(&bp->link_lock);
12104         }
12105
12106         if (test_and_clear_bit(BNXT_FLOW_STATS_SP_EVENT, &bp->sp_event))
12107                 bnxt_tc_flow_stats_work(bp);
12108
12109         if (test_and_clear_bit(BNXT_RING_COAL_NOW_SP_EVENT, &bp->sp_event))
12110                 bnxt_chk_missed_irq(bp);
12111
12112         if (test_and_clear_bit(BNXT_FW_ECHO_REQUEST_SP_EVENT, &bp->sp_event))
12113                 bnxt_fw_echo_reply(bp);
12114
12115         /* These functions below will clear BNXT_STATE_IN_SP_TASK.  They
12116          * must be the last functions to be called before exiting.
12117          */
12118         if (test_and_clear_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event))
12119                 bnxt_reset(bp, false);
12120
12121         if (test_and_clear_bit(BNXT_RESET_TASK_SILENT_SP_EVENT, &bp->sp_event))
12122                 bnxt_reset(bp, true);
12123
12124         if (test_and_clear_bit(BNXT_RST_RING_SP_EVENT, &bp->sp_event))
12125                 bnxt_rx_ring_reset(bp);
12126
12127         if (test_and_clear_bit(BNXT_FW_RESET_NOTIFY_SP_EVENT, &bp->sp_event)) {
12128                 if (test_bit(BNXT_STATE_FW_FATAL_COND, &bp->state) ||
12129                     test_bit(BNXT_STATE_FW_NON_FATAL_COND, &bp->state))
12130                         bnxt_devlink_health_fw_report(bp);
12131                 else
12132                         bnxt_fw_reset(bp);
12133         }
12134
12135         if (test_and_clear_bit(BNXT_FW_EXCEPTION_SP_EVENT, &bp->sp_event)) {
12136                 if (!is_bnxt_fw_ok(bp))
12137                         bnxt_devlink_health_fw_report(bp);
12138         }
12139
12140         smp_mb__before_atomic();
12141         clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
12142 }
12143
12144 /* Under rtnl_lock */
12145 int bnxt_check_rings(struct bnxt *bp, int tx, int rx, bool sh, int tcs,
12146                      int tx_xdp)
12147 {
12148         int max_rx, max_tx, tx_sets = 1;
12149         int tx_rings_needed, stats;
12150         int rx_rings = rx;
12151         int cp, vnics, rc;
12152
12153         if (tcs)
12154                 tx_sets = tcs;
12155
12156         rc = bnxt_get_max_rings(bp, &max_rx, &max_tx, sh);
12157         if (rc)
12158                 return rc;
12159
12160         if (max_rx < rx)
12161                 return -ENOMEM;
12162
12163         tx_rings_needed = tx * tx_sets + tx_xdp;
12164         if (max_tx < tx_rings_needed)
12165                 return -ENOMEM;
12166
12167         vnics = 1;
12168         if ((bp->flags & (BNXT_FLAG_RFS | BNXT_FLAG_CHIP_P5)) == BNXT_FLAG_RFS)
12169                 vnics += rx_rings;
12170
12171         if (bp->flags & BNXT_FLAG_AGG_RINGS)
12172                 rx_rings <<= 1;
12173         cp = sh ? max_t(int, tx_rings_needed, rx) : tx_rings_needed + rx;
12174         stats = cp;
12175         if (BNXT_NEW_RM(bp)) {
12176                 cp += bnxt_get_ulp_msix_num(bp);
12177                 stats += bnxt_get_ulp_stat_ctxs(bp);
12178         }
12179         return bnxt_hwrm_check_rings(bp, tx_rings_needed, rx_rings, rx, cp,
12180                                      stats, vnics);
12181 }
12182
12183 static void bnxt_unmap_bars(struct bnxt *bp, struct pci_dev *pdev)
12184 {
12185         if (bp->bar2) {
12186                 pci_iounmap(pdev, bp->bar2);
12187                 bp->bar2 = NULL;
12188         }
12189
12190         if (bp->bar1) {
12191                 pci_iounmap(pdev, bp->bar1);
12192                 bp->bar1 = NULL;
12193         }
12194
12195         if (bp->bar0) {
12196                 pci_iounmap(pdev, bp->bar0);
12197                 bp->bar0 = NULL;
12198         }
12199 }
12200
12201 static void bnxt_cleanup_pci(struct bnxt *bp)
12202 {
12203         bnxt_unmap_bars(bp, bp->pdev);
12204         pci_release_regions(bp->pdev);
12205         if (pci_is_enabled(bp->pdev))
12206                 pci_disable_device(bp->pdev);
12207 }
12208
12209 static void bnxt_init_dflt_coal(struct bnxt *bp)
12210 {
12211         struct bnxt_coal_cap *coal_cap = &bp->coal_cap;
12212         struct bnxt_coal *coal;
12213         u16 flags = 0;
12214
12215         if (coal_cap->cmpl_params &
12216             RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_TIMER_RESET)
12217                 flags |= RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET;
12218
12219         /* Tick values in micro seconds.
12220          * 1 coal_buf x bufs_per_record = 1 completion record.
12221          */
12222         coal = &bp->rx_coal;
12223         coal->coal_ticks = 10;
12224         coal->coal_bufs = 30;
12225         coal->coal_ticks_irq = 1;
12226         coal->coal_bufs_irq = 2;
12227         coal->idle_thresh = 50;
12228         coal->bufs_per_record = 2;
12229         coal->budget = 64;              /* NAPI budget */
12230         coal->flags = flags;
12231
12232         coal = &bp->tx_coal;
12233         coal->coal_ticks = 28;
12234         coal->coal_bufs = 30;
12235         coal->coal_ticks_irq = 2;
12236         coal->coal_bufs_irq = 2;
12237         coal->bufs_per_record = 1;
12238         coal->flags = flags;
12239
12240         bp->stats_coal_ticks = BNXT_DEF_STATS_COAL_TICKS;
12241 }
12242
12243 static int bnxt_fw_init_one_p1(struct bnxt *bp)
12244 {
12245         int rc;
12246
12247         bp->fw_cap = 0;
12248         rc = bnxt_hwrm_ver_get(bp);
12249         bnxt_try_map_fw_health_reg(bp);
12250         if (rc) {
12251                 rc = bnxt_try_recover_fw(bp);
12252                 if (rc)
12253                         return rc;
12254                 rc = bnxt_hwrm_ver_get(bp);
12255                 if (rc)
12256                         return rc;
12257         }
12258
12259         bnxt_nvm_cfg_ver_get(bp);
12260
12261         rc = bnxt_hwrm_func_reset(bp);
12262         if (rc)
12263                 return -ENODEV;
12264
12265         bnxt_hwrm_fw_set_time(bp);
12266         return 0;
12267 }
12268
12269 static int bnxt_fw_init_one_p2(struct bnxt *bp)
12270 {
12271         int rc;
12272
12273         /* Get the MAX capabilities for this function */
12274         rc = bnxt_hwrm_func_qcaps(bp);
12275         if (rc) {
12276                 netdev_err(bp->dev, "hwrm query capability failure rc: %x\n",
12277                            rc);
12278                 return -ENODEV;
12279         }
12280
12281         rc = bnxt_hwrm_cfa_adv_flow_mgnt_qcaps(bp);
12282         if (rc)
12283                 netdev_warn(bp->dev, "hwrm query adv flow mgnt failure rc: %d\n",
12284                             rc);
12285
12286         if (bnxt_alloc_fw_health(bp)) {
12287                 netdev_warn(bp->dev, "no memory for firmware error recovery\n");
12288         } else {
12289                 rc = bnxt_hwrm_error_recovery_qcfg(bp);
12290                 if (rc)
12291                         netdev_warn(bp->dev, "hwrm query error recovery failure rc: %d\n",
12292                                     rc);
12293         }
12294
12295         rc = bnxt_hwrm_func_drv_rgtr(bp, NULL, 0, false);
12296         if (rc)
12297                 return -ENODEV;
12298
12299         bnxt_hwrm_func_qcfg(bp);
12300         bnxt_hwrm_vnic_qcaps(bp);
12301         bnxt_hwrm_port_led_qcaps(bp);
12302         bnxt_ethtool_init(bp);
12303         bnxt_dcb_init(bp);
12304         return 0;
12305 }
12306
12307 static void bnxt_set_dflt_rss_hash_type(struct bnxt *bp)
12308 {
12309         bp->flags &= ~BNXT_FLAG_UDP_RSS_CAP;
12310         bp->rss_hash_cfg = VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4 |
12311                            VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4 |
12312                            VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6 |
12313                            VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6;
12314         if (bp->fw_cap & BNXT_FW_CAP_RSS_HASH_TYPE_DELTA)
12315                 bp->rss_hash_delta = bp->rss_hash_cfg;
12316         if (BNXT_CHIP_P4_PLUS(bp) && bp->hwrm_spec_code >= 0x10501) {
12317                 bp->flags |= BNXT_FLAG_UDP_RSS_CAP;
12318                 bp->rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4 |
12319                                     VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6;
12320         }
12321 }
12322
12323 static void bnxt_set_dflt_rfs(struct bnxt *bp)
12324 {
12325         struct net_device *dev = bp->dev;
12326
12327         dev->hw_features &= ~NETIF_F_NTUPLE;
12328         dev->features &= ~NETIF_F_NTUPLE;
12329         bp->flags &= ~BNXT_FLAG_RFS;
12330         if (bnxt_rfs_supported(bp)) {
12331                 dev->hw_features |= NETIF_F_NTUPLE;
12332                 if (bnxt_rfs_capable(bp)) {
12333                         bp->flags |= BNXT_FLAG_RFS;
12334                         dev->features |= NETIF_F_NTUPLE;
12335                 }
12336         }
12337 }
12338
12339 static void bnxt_fw_init_one_p3(struct bnxt *bp)
12340 {
12341         struct pci_dev *pdev = bp->pdev;
12342
12343         bnxt_set_dflt_rss_hash_type(bp);
12344         bnxt_set_dflt_rfs(bp);
12345
12346         bnxt_get_wol_settings(bp);
12347         if (bp->flags & BNXT_FLAG_WOL_CAP)
12348                 device_set_wakeup_enable(&pdev->dev, bp->wol);
12349         else
12350                 device_set_wakeup_capable(&pdev->dev, false);
12351
12352         bnxt_hwrm_set_cache_line_size(bp, cache_line_size());
12353         bnxt_hwrm_coal_params_qcaps(bp);
12354 }
12355
12356 static int bnxt_probe_phy(struct bnxt *bp, bool fw_dflt);
12357
12358 int bnxt_fw_init_one(struct bnxt *bp)
12359 {
12360         int rc;
12361
12362         rc = bnxt_fw_init_one_p1(bp);
12363         if (rc) {
12364                 netdev_err(bp->dev, "Firmware init phase 1 failed\n");
12365                 return rc;
12366         }
12367         rc = bnxt_fw_init_one_p2(bp);
12368         if (rc) {
12369                 netdev_err(bp->dev, "Firmware init phase 2 failed\n");
12370                 return rc;
12371         }
12372         rc = bnxt_probe_phy(bp, false);
12373         if (rc)
12374                 return rc;
12375         rc = bnxt_approve_mac(bp, bp->dev->dev_addr, false);
12376         if (rc)
12377                 return rc;
12378
12379         bnxt_fw_init_one_p3(bp);
12380         return 0;
12381 }
12382
12383 static void bnxt_fw_reset_writel(struct bnxt *bp, int reg_idx)
12384 {
12385         struct bnxt_fw_health *fw_health = bp->fw_health;
12386         u32 reg = fw_health->fw_reset_seq_regs[reg_idx];
12387         u32 val = fw_health->fw_reset_seq_vals[reg_idx];
12388         u32 reg_type, reg_off, delay_msecs;
12389
12390         delay_msecs = fw_health->fw_reset_seq_delay_msec[reg_idx];
12391         reg_type = BNXT_FW_HEALTH_REG_TYPE(reg);
12392         reg_off = BNXT_FW_HEALTH_REG_OFF(reg);
12393         switch (reg_type) {
12394         case BNXT_FW_HEALTH_REG_TYPE_CFG:
12395                 pci_write_config_dword(bp->pdev, reg_off, val);
12396                 break;
12397         case BNXT_FW_HEALTH_REG_TYPE_GRC:
12398                 writel(reg_off & BNXT_GRC_BASE_MASK,
12399                        bp->bar0 + BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
12400                 reg_off = (reg_off & BNXT_GRC_OFFSET_MASK) + 0x2000;
12401                 fallthrough;
12402         case BNXT_FW_HEALTH_REG_TYPE_BAR0:
12403                 writel(val, bp->bar0 + reg_off);
12404                 break;
12405         case BNXT_FW_HEALTH_REG_TYPE_BAR1:
12406                 writel(val, bp->bar1 + reg_off);
12407                 break;
12408         }
12409         if (delay_msecs) {
12410                 pci_read_config_dword(bp->pdev, 0, &val);
12411                 msleep(delay_msecs);
12412         }
12413 }
12414
12415 bool bnxt_hwrm_reset_permitted(struct bnxt *bp)
12416 {
12417         struct hwrm_func_qcfg_output *resp;
12418         struct hwrm_func_qcfg_input *req;
12419         bool result = true; /* firmware will enforce if unknown */
12420
12421         if (~bp->fw_cap & BNXT_FW_CAP_HOT_RESET_IF)
12422                 return result;
12423
12424         if (hwrm_req_init(bp, req, HWRM_FUNC_QCFG))
12425                 return result;
12426
12427         req->fid = cpu_to_le16(0xffff);
12428         resp = hwrm_req_hold(bp, req);
12429         if (!hwrm_req_send(bp, req))
12430                 result = !!(le16_to_cpu(resp->flags) &
12431                             FUNC_QCFG_RESP_FLAGS_HOT_RESET_ALLOWED);
12432         hwrm_req_drop(bp, req);
12433         return result;
12434 }
12435
12436 static void bnxt_reset_all(struct bnxt *bp)
12437 {
12438         struct bnxt_fw_health *fw_health = bp->fw_health;
12439         int i, rc;
12440
12441         if (bp->fw_cap & BNXT_FW_CAP_ERR_RECOVER_RELOAD) {
12442                 bnxt_fw_reset_via_optee(bp);
12443                 bp->fw_reset_timestamp = jiffies;
12444                 return;
12445         }
12446
12447         if (fw_health->flags & ERROR_RECOVERY_QCFG_RESP_FLAGS_HOST) {
12448                 for (i = 0; i < fw_health->fw_reset_seq_cnt; i++)
12449                         bnxt_fw_reset_writel(bp, i);
12450         } else if (fw_health->flags & ERROR_RECOVERY_QCFG_RESP_FLAGS_CO_CPU) {
12451                 struct hwrm_fw_reset_input *req;
12452
12453                 rc = hwrm_req_init(bp, req, HWRM_FW_RESET);
12454                 if (!rc) {
12455                         req->target_id = cpu_to_le16(HWRM_TARGET_ID_KONG);
12456                         req->embedded_proc_type = FW_RESET_REQ_EMBEDDED_PROC_TYPE_CHIP;
12457                         req->selfrst_status = FW_RESET_REQ_SELFRST_STATUS_SELFRSTASAP;
12458                         req->flags = FW_RESET_REQ_FLAGS_RESET_GRACEFUL;
12459                         rc = hwrm_req_send(bp, req);
12460                 }
12461                 if (rc != -ENODEV)
12462                         netdev_warn(bp->dev, "Unable to reset FW rc=%d\n", rc);
12463         }
12464         bp->fw_reset_timestamp = jiffies;
12465 }
12466
12467 static bool bnxt_fw_reset_timeout(struct bnxt *bp)
12468 {
12469         return time_after(jiffies, bp->fw_reset_timestamp +
12470                           (bp->fw_reset_max_dsecs * HZ / 10));
12471 }
12472
12473 static void bnxt_fw_reset_abort(struct bnxt *bp, int rc)
12474 {
12475         clear_bit(BNXT_STATE_IN_FW_RESET, &bp->state);
12476         if (bp->fw_reset_state != BNXT_FW_RESET_STATE_POLL_VF) {
12477                 bnxt_ulp_start(bp, rc);
12478                 bnxt_dl_health_fw_status_update(bp, false);
12479         }
12480         bp->fw_reset_state = 0;
12481         dev_close(bp->dev);
12482 }
12483
12484 static void bnxt_fw_reset_task(struct work_struct *work)
12485 {
12486         struct bnxt *bp = container_of(work, struct bnxt, fw_reset_task.work);
12487         int rc = 0;
12488
12489         if (!test_bit(BNXT_STATE_IN_FW_RESET, &bp->state)) {
12490                 netdev_err(bp->dev, "bnxt_fw_reset_task() called when not in fw reset mode!\n");
12491                 return;
12492         }
12493
12494         switch (bp->fw_reset_state) {
12495         case BNXT_FW_RESET_STATE_POLL_VF: {
12496                 int n = bnxt_get_registered_vfs(bp);
12497                 int tmo;
12498
12499                 if (n < 0) {
12500                         netdev_err(bp->dev, "Firmware reset aborted, subsequent func_qcfg cmd failed, rc = %d, %d msecs since reset timestamp\n",
12501                                    n, jiffies_to_msecs(jiffies -
12502                                    bp->fw_reset_timestamp));
12503                         goto fw_reset_abort;
12504                 } else if (n > 0) {
12505                         if (bnxt_fw_reset_timeout(bp)) {
12506                                 clear_bit(BNXT_STATE_IN_FW_RESET, &bp->state);
12507                                 bp->fw_reset_state = 0;
12508                                 netdev_err(bp->dev, "Firmware reset aborted, bnxt_get_registered_vfs() returns %d\n",
12509                                            n);
12510                                 return;
12511                         }
12512                         bnxt_queue_fw_reset_work(bp, HZ / 10);
12513                         return;
12514                 }
12515                 bp->fw_reset_timestamp = jiffies;
12516                 rtnl_lock();
12517                 if (test_bit(BNXT_STATE_ABORT_ERR, &bp->state)) {
12518                         bnxt_fw_reset_abort(bp, rc);
12519                         rtnl_unlock();
12520                         return;
12521                 }
12522                 bnxt_fw_reset_close(bp);
12523                 if (bp->fw_cap & BNXT_FW_CAP_ERR_RECOVER_RELOAD) {
12524                         bp->fw_reset_state = BNXT_FW_RESET_STATE_POLL_FW_DOWN;
12525                         tmo = HZ / 10;
12526                 } else {
12527                         bp->fw_reset_state = BNXT_FW_RESET_STATE_ENABLE_DEV;
12528                         tmo = bp->fw_reset_min_dsecs * HZ / 10;
12529                 }
12530                 rtnl_unlock();
12531                 bnxt_queue_fw_reset_work(bp, tmo);
12532                 return;
12533         }
12534         case BNXT_FW_RESET_STATE_POLL_FW_DOWN: {
12535                 u32 val;
12536
12537                 val = bnxt_fw_health_readl(bp, BNXT_FW_HEALTH_REG);
12538                 if (!(val & BNXT_FW_STATUS_SHUTDOWN) &&
12539                     !bnxt_fw_reset_timeout(bp)) {
12540                         bnxt_queue_fw_reset_work(bp, HZ / 5);
12541                         return;
12542                 }
12543
12544                 if (!bp->fw_health->primary) {
12545                         u32 wait_dsecs = bp->fw_health->normal_func_wait_dsecs;
12546
12547                         bp->fw_reset_state = BNXT_FW_RESET_STATE_ENABLE_DEV;
12548                         bnxt_queue_fw_reset_work(bp, wait_dsecs * HZ / 10);
12549                         return;
12550                 }
12551                 bp->fw_reset_state = BNXT_FW_RESET_STATE_RESET_FW;
12552         }
12553                 fallthrough;
12554         case BNXT_FW_RESET_STATE_RESET_FW:
12555                 bnxt_reset_all(bp);
12556                 bp->fw_reset_state = BNXT_FW_RESET_STATE_ENABLE_DEV;
12557                 bnxt_queue_fw_reset_work(bp, bp->fw_reset_min_dsecs * HZ / 10);
12558                 return;
12559         case BNXT_FW_RESET_STATE_ENABLE_DEV:
12560                 bnxt_inv_fw_health_reg(bp);
12561                 if (test_bit(BNXT_STATE_FW_FATAL_COND, &bp->state) &&
12562                     !bp->fw_reset_min_dsecs) {
12563                         u16 val;
12564
12565                         pci_read_config_word(bp->pdev, PCI_SUBSYSTEM_ID, &val);
12566                         if (val == 0xffff) {
12567                                 if (bnxt_fw_reset_timeout(bp)) {
12568                                         netdev_err(bp->dev, "Firmware reset aborted, PCI config space invalid\n");
12569                                         rc = -ETIMEDOUT;
12570                                         goto fw_reset_abort;
12571                                 }
12572                                 bnxt_queue_fw_reset_work(bp, HZ / 1000);
12573                                 return;
12574                         }
12575                 }
12576                 clear_bit(BNXT_STATE_FW_FATAL_COND, &bp->state);
12577                 clear_bit(BNXT_STATE_FW_NON_FATAL_COND, &bp->state);
12578                 if (test_and_clear_bit(BNXT_STATE_FW_ACTIVATE_RESET, &bp->state) &&
12579                     !test_bit(BNXT_STATE_FW_ACTIVATE, &bp->state))
12580                         bnxt_dl_remote_reload(bp);
12581                 if (pci_enable_device(bp->pdev)) {
12582                         netdev_err(bp->dev, "Cannot re-enable PCI device\n");
12583                         rc = -ENODEV;
12584                         goto fw_reset_abort;
12585                 }
12586                 pci_set_master(bp->pdev);
12587                 bp->fw_reset_state = BNXT_FW_RESET_STATE_POLL_FW;
12588                 fallthrough;
12589         case BNXT_FW_RESET_STATE_POLL_FW:
12590                 bp->hwrm_cmd_timeout = SHORT_HWRM_CMD_TIMEOUT;
12591                 rc = bnxt_hwrm_poll(bp);
12592                 if (rc) {
12593                         if (bnxt_fw_reset_timeout(bp)) {
12594                                 netdev_err(bp->dev, "Firmware reset aborted\n");
12595                                 goto fw_reset_abort_status;
12596                         }
12597                         bnxt_queue_fw_reset_work(bp, HZ / 5);
12598                         return;
12599                 }
12600                 bp->hwrm_cmd_timeout = DFLT_HWRM_CMD_TIMEOUT;
12601                 bp->fw_reset_state = BNXT_FW_RESET_STATE_OPENING;
12602                 fallthrough;
12603         case BNXT_FW_RESET_STATE_OPENING:
12604                 while (!rtnl_trylock()) {
12605                         bnxt_queue_fw_reset_work(bp, HZ / 10);
12606                         return;
12607                 }
12608                 rc = bnxt_open(bp->dev);
12609                 if (rc) {
12610                         netdev_err(bp->dev, "bnxt_open() failed during FW reset\n");
12611                         bnxt_fw_reset_abort(bp, rc);
12612                         rtnl_unlock();
12613                         return;
12614                 }
12615
12616                 if ((bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY) &&
12617                     bp->fw_health->enabled) {
12618                         bp->fw_health->last_fw_reset_cnt =
12619                                 bnxt_fw_health_readl(bp, BNXT_FW_RESET_CNT_REG);
12620                 }
12621                 bp->fw_reset_state = 0;
12622                 /* Make sure fw_reset_state is 0 before clearing the flag */
12623                 smp_mb__before_atomic();
12624                 clear_bit(BNXT_STATE_IN_FW_RESET, &bp->state);
12625                 bnxt_ulp_start(bp, 0);
12626                 bnxt_reenable_sriov(bp);
12627                 bnxt_vf_reps_alloc(bp);
12628                 bnxt_vf_reps_open(bp);
12629                 bnxt_ptp_reapply_pps(bp);
12630                 clear_bit(BNXT_STATE_FW_ACTIVATE, &bp->state);
12631                 if (test_and_clear_bit(BNXT_STATE_RECOVER, &bp->state)) {
12632                         bnxt_dl_health_fw_recovery_done(bp);
12633                         bnxt_dl_health_fw_status_update(bp, true);
12634                 }
12635                 rtnl_unlock();
12636                 break;
12637         }
12638         return;
12639
12640 fw_reset_abort_status:
12641         if (bp->fw_health->status_reliable ||
12642             (bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY)) {
12643                 u32 sts = bnxt_fw_health_readl(bp, BNXT_FW_HEALTH_REG);
12644
12645                 netdev_err(bp->dev, "fw_health_status 0x%x\n", sts);
12646         }
12647 fw_reset_abort:
12648         rtnl_lock();
12649         bnxt_fw_reset_abort(bp, rc);
12650         rtnl_unlock();
12651 }
12652
12653 static int bnxt_init_board(struct pci_dev *pdev, struct net_device *dev)
12654 {
12655         int rc;
12656         struct bnxt *bp = netdev_priv(dev);
12657
12658         SET_NETDEV_DEV(dev, &pdev->dev);
12659
12660         /* enable device (incl. PCI PM wakeup), and bus-mastering */
12661         rc = pci_enable_device(pdev);
12662         if (rc) {
12663                 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
12664                 goto init_err;
12665         }
12666
12667         if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
12668                 dev_err(&pdev->dev,
12669                         "Cannot find PCI device base address, aborting\n");
12670                 rc = -ENODEV;
12671                 goto init_err_disable;
12672         }
12673
12674         rc = pci_request_regions(pdev, DRV_MODULE_NAME);
12675         if (rc) {
12676                 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n");
12677                 goto init_err_disable;
12678         }
12679
12680         if (dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)) != 0 &&
12681             dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)) != 0) {
12682                 dev_err(&pdev->dev, "System does not support DMA, aborting\n");
12683                 rc = -EIO;
12684                 goto init_err_release;
12685         }
12686
12687         pci_set_master(pdev);
12688
12689         bp->dev = dev;
12690         bp->pdev = pdev;
12691
12692         /* Doorbell BAR bp->bar1 is mapped after bnxt_fw_init_one_p2()
12693          * determines the BAR size.
12694          */
12695         bp->bar0 = pci_ioremap_bar(pdev, 0);
12696         if (!bp->bar0) {
12697                 dev_err(&pdev->dev, "Cannot map device registers, aborting\n");
12698                 rc = -ENOMEM;
12699                 goto init_err_release;
12700         }
12701
12702         bp->bar2 = pci_ioremap_bar(pdev, 4);
12703         if (!bp->bar2) {
12704                 dev_err(&pdev->dev, "Cannot map bar4 registers, aborting\n");
12705                 rc = -ENOMEM;
12706                 goto init_err_release;
12707         }
12708
12709         INIT_WORK(&bp->sp_task, bnxt_sp_task);
12710         INIT_DELAYED_WORK(&bp->fw_reset_task, bnxt_fw_reset_task);
12711
12712         spin_lock_init(&bp->ntp_fltr_lock);
12713 #if BITS_PER_LONG == 32
12714         spin_lock_init(&bp->db_lock);
12715 #endif
12716
12717         bp->rx_ring_size = BNXT_DEFAULT_RX_RING_SIZE;
12718         bp->tx_ring_size = BNXT_DEFAULT_TX_RING_SIZE;
12719
12720         timer_setup(&bp->timer, bnxt_timer, 0);
12721         bp->current_interval = BNXT_TIMER_INTERVAL;
12722
12723         bp->vxlan_fw_dst_port_id = INVALID_HW_RING_ID;
12724         bp->nge_fw_dst_port_id = INVALID_HW_RING_ID;
12725
12726         clear_bit(BNXT_STATE_OPEN, &bp->state);
12727         return 0;
12728
12729 init_err_release:
12730         bnxt_unmap_bars(bp, pdev);
12731         pci_release_regions(pdev);
12732
12733 init_err_disable:
12734         pci_disable_device(pdev);
12735
12736 init_err:
12737         return rc;
12738 }
12739
12740 /* rtnl_lock held */
12741 static int bnxt_change_mac_addr(struct net_device *dev, void *p)
12742 {
12743         struct sockaddr *addr = p;
12744         struct bnxt *bp = netdev_priv(dev);
12745         int rc = 0;
12746
12747         if (!is_valid_ether_addr(addr->sa_data))
12748                 return -EADDRNOTAVAIL;
12749
12750         if (ether_addr_equal(addr->sa_data, dev->dev_addr))
12751                 return 0;
12752
12753         rc = bnxt_approve_mac(bp, addr->sa_data, true);
12754         if (rc)
12755                 return rc;
12756
12757         eth_hw_addr_set(dev, addr->sa_data);
12758         if (netif_running(dev)) {
12759                 bnxt_close_nic(bp, false, false);
12760                 rc = bnxt_open_nic(bp, false, false);
12761         }
12762
12763         return rc;
12764 }
12765
12766 /* rtnl_lock held */
12767 static int bnxt_change_mtu(struct net_device *dev, int new_mtu)
12768 {
12769         struct bnxt *bp = netdev_priv(dev);
12770
12771         if (netif_running(dev))
12772                 bnxt_close_nic(bp, true, false);
12773
12774         dev->mtu = new_mtu;
12775         bnxt_set_ring_params(bp);
12776
12777         if (netif_running(dev))
12778                 return bnxt_open_nic(bp, true, false);
12779
12780         return 0;
12781 }
12782
12783 int bnxt_setup_mq_tc(struct net_device *dev, u8 tc)
12784 {
12785         struct bnxt *bp = netdev_priv(dev);
12786         bool sh = false;
12787         int rc;
12788
12789         if (tc > bp->max_tc) {
12790                 netdev_err(dev, "Too many traffic classes requested: %d. Max supported is %d.\n",
12791                            tc, bp->max_tc);
12792                 return -EINVAL;
12793         }
12794
12795         if (netdev_get_num_tc(dev) == tc)
12796                 return 0;
12797
12798         if (bp->flags & BNXT_FLAG_SHARED_RINGS)
12799                 sh = true;
12800
12801         rc = bnxt_check_rings(bp, bp->tx_nr_rings_per_tc, bp->rx_nr_rings,
12802                               sh, tc, bp->tx_nr_rings_xdp);
12803         if (rc)
12804                 return rc;
12805
12806         /* Needs to close the device and do hw resource re-allocations */
12807         if (netif_running(bp->dev))
12808                 bnxt_close_nic(bp, true, false);
12809
12810         if (tc) {
12811                 bp->tx_nr_rings = bp->tx_nr_rings_per_tc * tc;
12812                 netdev_set_num_tc(dev, tc);
12813         } else {
12814                 bp->tx_nr_rings = bp->tx_nr_rings_per_tc;
12815                 netdev_reset_tc(dev);
12816         }
12817         bp->tx_nr_rings += bp->tx_nr_rings_xdp;
12818         bp->cp_nr_rings = sh ? max_t(int, bp->tx_nr_rings, bp->rx_nr_rings) :
12819                                bp->tx_nr_rings + bp->rx_nr_rings;
12820
12821         if (netif_running(bp->dev))
12822                 return bnxt_open_nic(bp, true, false);
12823
12824         return 0;
12825 }
12826
12827 static int bnxt_setup_tc_block_cb(enum tc_setup_type type, void *type_data,
12828                                   void *cb_priv)
12829 {
12830         struct bnxt *bp = cb_priv;
12831
12832         if (!bnxt_tc_flower_enabled(bp) ||
12833             !tc_cls_can_offload_and_chain0(bp->dev, type_data))
12834                 return -EOPNOTSUPP;
12835
12836         switch (type) {
12837         case TC_SETUP_CLSFLOWER:
12838                 return bnxt_tc_setup_flower(bp, bp->pf.fw_fid, type_data);
12839         default:
12840                 return -EOPNOTSUPP;
12841         }
12842 }
12843
12844 LIST_HEAD(bnxt_block_cb_list);
12845
12846 static int bnxt_setup_tc(struct net_device *dev, enum tc_setup_type type,
12847                          void *type_data)
12848 {
12849         struct bnxt *bp = netdev_priv(dev);
12850
12851         switch (type) {
12852         case TC_SETUP_BLOCK:
12853                 return flow_block_cb_setup_simple(type_data,
12854                                                   &bnxt_block_cb_list,
12855                                                   bnxt_setup_tc_block_cb,
12856                                                   bp, bp, true);
12857         case TC_SETUP_QDISC_MQPRIO: {
12858                 struct tc_mqprio_qopt *mqprio = type_data;
12859
12860                 mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS;
12861
12862                 return bnxt_setup_mq_tc(dev, mqprio->num_tc);
12863         }
12864         default:
12865                 return -EOPNOTSUPP;
12866         }
12867 }
12868
12869 #ifdef CONFIG_RFS_ACCEL
12870 static bool bnxt_fltr_match(struct bnxt_ntuple_filter *f1,
12871                             struct bnxt_ntuple_filter *f2)
12872 {
12873         struct flow_keys *keys1 = &f1->fkeys;
12874         struct flow_keys *keys2 = &f2->fkeys;
12875
12876         if (keys1->basic.n_proto != keys2->basic.n_proto ||
12877             keys1->basic.ip_proto != keys2->basic.ip_proto)
12878                 return false;
12879
12880         if (keys1->basic.n_proto == htons(ETH_P_IP)) {
12881                 if (keys1->addrs.v4addrs.src != keys2->addrs.v4addrs.src ||
12882                     keys1->addrs.v4addrs.dst != keys2->addrs.v4addrs.dst)
12883                         return false;
12884         } else {
12885                 if (memcmp(&keys1->addrs.v6addrs.src, &keys2->addrs.v6addrs.src,
12886                            sizeof(keys1->addrs.v6addrs.src)) ||
12887                     memcmp(&keys1->addrs.v6addrs.dst, &keys2->addrs.v6addrs.dst,
12888                            sizeof(keys1->addrs.v6addrs.dst)))
12889                         return false;
12890         }
12891
12892         if (keys1->ports.ports == keys2->ports.ports &&
12893             keys1->control.flags == keys2->control.flags &&
12894             ether_addr_equal(f1->src_mac_addr, f2->src_mac_addr) &&
12895             ether_addr_equal(f1->dst_mac_addr, f2->dst_mac_addr))
12896                 return true;
12897
12898         return false;
12899 }
12900
12901 static int bnxt_rx_flow_steer(struct net_device *dev, const struct sk_buff *skb,
12902                               u16 rxq_index, u32 flow_id)
12903 {
12904         struct bnxt *bp = netdev_priv(dev);
12905         struct bnxt_ntuple_filter *fltr, *new_fltr;
12906         struct flow_keys *fkeys;
12907         struct ethhdr *eth = (struct ethhdr *)skb_mac_header(skb);
12908         int rc = 0, idx, bit_id, l2_idx = 0;
12909         struct hlist_head *head;
12910         u32 flags;
12911
12912         if (!ether_addr_equal(dev->dev_addr, eth->h_dest)) {
12913                 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
12914                 int off = 0, j;
12915
12916                 netif_addr_lock_bh(dev);
12917                 for (j = 0; j < vnic->uc_filter_count; j++, off += ETH_ALEN) {
12918                         if (ether_addr_equal(eth->h_dest,
12919                                              vnic->uc_list + off)) {
12920                                 l2_idx = j + 1;
12921                                 break;
12922                         }
12923                 }
12924                 netif_addr_unlock_bh(dev);
12925                 if (!l2_idx)
12926                         return -EINVAL;
12927         }
12928         new_fltr = kzalloc(sizeof(*new_fltr), GFP_ATOMIC);
12929         if (!new_fltr)
12930                 return -ENOMEM;
12931
12932         fkeys = &new_fltr->fkeys;
12933         if (!skb_flow_dissect_flow_keys(skb, fkeys, 0)) {
12934                 rc = -EPROTONOSUPPORT;
12935                 goto err_free;
12936         }
12937
12938         if ((fkeys->basic.n_proto != htons(ETH_P_IP) &&
12939              fkeys->basic.n_proto != htons(ETH_P_IPV6)) ||
12940             ((fkeys->basic.ip_proto != IPPROTO_TCP) &&
12941              (fkeys->basic.ip_proto != IPPROTO_UDP))) {
12942                 rc = -EPROTONOSUPPORT;
12943                 goto err_free;
12944         }
12945         if (fkeys->basic.n_proto == htons(ETH_P_IPV6) &&
12946             bp->hwrm_spec_code < 0x10601) {
12947                 rc = -EPROTONOSUPPORT;
12948                 goto err_free;
12949         }
12950         flags = fkeys->control.flags;
12951         if (((flags & FLOW_DIS_ENCAPSULATION) &&
12952              bp->hwrm_spec_code < 0x10601) || (flags & FLOW_DIS_IS_FRAGMENT)) {
12953                 rc = -EPROTONOSUPPORT;
12954                 goto err_free;
12955         }
12956
12957         memcpy(new_fltr->dst_mac_addr, eth->h_dest, ETH_ALEN);
12958         memcpy(new_fltr->src_mac_addr, eth->h_source, ETH_ALEN);
12959
12960         idx = skb_get_hash_raw(skb) & BNXT_NTP_FLTR_HASH_MASK;
12961         head = &bp->ntp_fltr_hash_tbl[idx];
12962         rcu_read_lock();
12963         hlist_for_each_entry_rcu(fltr, head, hash) {
12964                 if (bnxt_fltr_match(fltr, new_fltr)) {
12965                         rc = fltr->sw_id;
12966                         rcu_read_unlock();
12967                         goto err_free;
12968                 }
12969         }
12970         rcu_read_unlock();
12971
12972         spin_lock_bh(&bp->ntp_fltr_lock);
12973         bit_id = bitmap_find_free_region(bp->ntp_fltr_bmap,
12974                                          BNXT_NTP_FLTR_MAX_FLTR, 0);
12975         if (bit_id < 0) {
12976                 spin_unlock_bh(&bp->ntp_fltr_lock);
12977                 rc = -ENOMEM;
12978                 goto err_free;
12979         }
12980
12981         new_fltr->sw_id = (u16)bit_id;
12982         new_fltr->flow_id = flow_id;
12983         new_fltr->l2_fltr_idx = l2_idx;
12984         new_fltr->rxq = rxq_index;
12985         hlist_add_head_rcu(&new_fltr->hash, head);
12986         bp->ntp_fltr_count++;
12987         spin_unlock_bh(&bp->ntp_fltr_lock);
12988
12989         set_bit(BNXT_RX_NTP_FLTR_SP_EVENT, &bp->sp_event);
12990         bnxt_queue_sp_work(bp);
12991
12992         return new_fltr->sw_id;
12993
12994 err_free:
12995         kfree(new_fltr);
12996         return rc;
12997 }
12998
12999 static void bnxt_cfg_ntp_filters(struct bnxt *bp)
13000 {
13001         int i;
13002
13003         for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) {
13004                 struct hlist_head *head;
13005                 struct hlist_node *tmp;
13006                 struct bnxt_ntuple_filter *fltr;
13007                 int rc;
13008
13009                 head = &bp->ntp_fltr_hash_tbl[i];
13010                 hlist_for_each_entry_safe(fltr, tmp, head, hash) {
13011                         bool del = false;
13012
13013                         if (test_bit(BNXT_FLTR_VALID, &fltr->state)) {
13014                                 if (rps_may_expire_flow(bp->dev, fltr->rxq,
13015                                                         fltr->flow_id,
13016                                                         fltr->sw_id)) {
13017                                         bnxt_hwrm_cfa_ntuple_filter_free(bp,
13018                                                                          fltr);
13019                                         del = true;
13020                                 }
13021                         } else {
13022                                 rc = bnxt_hwrm_cfa_ntuple_filter_alloc(bp,
13023                                                                        fltr);
13024                                 if (rc)
13025                                         del = true;
13026                                 else
13027                                         set_bit(BNXT_FLTR_VALID, &fltr->state);
13028                         }
13029
13030                         if (del) {
13031                                 spin_lock_bh(&bp->ntp_fltr_lock);
13032                                 hlist_del_rcu(&fltr->hash);
13033                                 bp->ntp_fltr_count--;
13034                                 spin_unlock_bh(&bp->ntp_fltr_lock);
13035                                 synchronize_rcu();
13036                                 clear_bit(fltr->sw_id, bp->ntp_fltr_bmap);
13037                                 kfree(fltr);
13038                         }
13039                 }
13040         }
13041         if (test_and_clear_bit(BNXT_HWRM_PF_UNLOAD_SP_EVENT, &bp->sp_event))
13042                 netdev_info(bp->dev, "Receive PF driver unload event!\n");
13043 }
13044
13045 #else
13046
13047 static void bnxt_cfg_ntp_filters(struct bnxt *bp)
13048 {
13049 }
13050
13051 #endif /* CONFIG_RFS_ACCEL */
13052
13053 static int bnxt_udp_tunnel_sync(struct net_device *netdev, unsigned int table)
13054 {
13055         struct bnxt *bp = netdev_priv(netdev);
13056         struct udp_tunnel_info ti;
13057         unsigned int cmd;
13058
13059         udp_tunnel_nic_get_port(netdev, table, 0, &ti);
13060         if (ti.type == UDP_TUNNEL_TYPE_VXLAN)
13061                 cmd = TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN;
13062         else
13063                 cmd = TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE;
13064
13065         if (ti.port)
13066                 return bnxt_hwrm_tunnel_dst_port_alloc(bp, ti.port, cmd);
13067
13068         return bnxt_hwrm_tunnel_dst_port_free(bp, cmd);
13069 }
13070
13071 static const struct udp_tunnel_nic_info bnxt_udp_tunnels = {
13072         .sync_table     = bnxt_udp_tunnel_sync,
13073         .flags          = UDP_TUNNEL_NIC_INFO_MAY_SLEEP |
13074                           UDP_TUNNEL_NIC_INFO_OPEN_ONLY,
13075         .tables         = {
13076                 { .n_entries = 1, .tunnel_types = UDP_TUNNEL_TYPE_VXLAN,  },
13077                 { .n_entries = 1, .tunnel_types = UDP_TUNNEL_TYPE_GENEVE, },
13078         },
13079 };
13080
13081 static int bnxt_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq,
13082                                struct net_device *dev, u32 filter_mask,
13083                                int nlflags)
13084 {
13085         struct bnxt *bp = netdev_priv(dev);
13086
13087         return ndo_dflt_bridge_getlink(skb, pid, seq, dev, bp->br_mode, 0, 0,
13088                                        nlflags, filter_mask, NULL);
13089 }
13090
13091 static int bnxt_bridge_setlink(struct net_device *dev, struct nlmsghdr *nlh,
13092                                u16 flags, struct netlink_ext_ack *extack)
13093 {
13094         struct bnxt *bp = netdev_priv(dev);
13095         struct nlattr *attr, *br_spec;
13096         int rem, rc = 0;
13097
13098         if (bp->hwrm_spec_code < 0x10708 || !BNXT_SINGLE_PF(bp))
13099                 return -EOPNOTSUPP;
13100
13101         br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC);
13102         if (!br_spec)
13103                 return -EINVAL;
13104
13105         nla_for_each_nested(attr, br_spec, rem) {
13106                 u16 mode;
13107
13108                 if (nla_type(attr) != IFLA_BRIDGE_MODE)
13109                         continue;
13110
13111                 if (nla_len(attr) < sizeof(mode))
13112                         return -EINVAL;
13113
13114                 mode = nla_get_u16(attr);
13115                 if (mode == bp->br_mode)
13116                         break;
13117
13118                 rc = bnxt_hwrm_set_br_mode(bp, mode);
13119                 if (!rc)
13120                         bp->br_mode = mode;
13121                 break;
13122         }
13123         return rc;
13124 }
13125
13126 int bnxt_get_port_parent_id(struct net_device *dev,
13127                             struct netdev_phys_item_id *ppid)
13128 {
13129         struct bnxt *bp = netdev_priv(dev);
13130
13131         if (bp->eswitch_mode != DEVLINK_ESWITCH_MODE_SWITCHDEV)
13132                 return -EOPNOTSUPP;
13133
13134         /* The PF and it's VF-reps only support the switchdev framework */
13135         if (!BNXT_PF(bp) || !(bp->flags & BNXT_FLAG_DSN_VALID))
13136                 return -EOPNOTSUPP;
13137
13138         ppid->id_len = sizeof(bp->dsn);
13139         memcpy(ppid->id, bp->dsn, ppid->id_len);
13140
13141         return 0;
13142 }
13143
13144 static const struct net_device_ops bnxt_netdev_ops = {
13145         .ndo_open               = bnxt_open,
13146         .ndo_start_xmit         = bnxt_start_xmit,
13147         .ndo_stop               = bnxt_close,
13148         .ndo_get_stats64        = bnxt_get_stats64,
13149         .ndo_set_rx_mode        = bnxt_set_rx_mode,
13150         .ndo_eth_ioctl          = bnxt_ioctl,
13151         .ndo_validate_addr      = eth_validate_addr,
13152         .ndo_set_mac_address    = bnxt_change_mac_addr,
13153         .ndo_change_mtu         = bnxt_change_mtu,
13154         .ndo_fix_features       = bnxt_fix_features,
13155         .ndo_set_features       = bnxt_set_features,
13156         .ndo_features_check     = bnxt_features_check,
13157         .ndo_tx_timeout         = bnxt_tx_timeout,
13158 #ifdef CONFIG_BNXT_SRIOV
13159         .ndo_get_vf_config      = bnxt_get_vf_config,
13160         .ndo_set_vf_mac         = bnxt_set_vf_mac,
13161         .ndo_set_vf_vlan        = bnxt_set_vf_vlan,
13162         .ndo_set_vf_rate        = bnxt_set_vf_bw,
13163         .ndo_set_vf_link_state  = bnxt_set_vf_link_state,
13164         .ndo_set_vf_spoofchk    = bnxt_set_vf_spoofchk,
13165         .ndo_set_vf_trust       = bnxt_set_vf_trust,
13166 #endif
13167         .ndo_setup_tc           = bnxt_setup_tc,
13168 #ifdef CONFIG_RFS_ACCEL
13169         .ndo_rx_flow_steer      = bnxt_rx_flow_steer,
13170 #endif
13171         .ndo_bpf                = bnxt_xdp,
13172         .ndo_xdp_xmit           = bnxt_xdp_xmit,
13173         .ndo_bridge_getlink     = bnxt_bridge_getlink,
13174         .ndo_bridge_setlink     = bnxt_bridge_setlink,
13175 };
13176
13177 static void bnxt_remove_one(struct pci_dev *pdev)
13178 {
13179         struct net_device *dev = pci_get_drvdata(pdev);
13180         struct bnxt *bp = netdev_priv(dev);
13181
13182         if (BNXT_PF(bp))
13183                 bnxt_sriov_disable(bp);
13184
13185         bnxt_rdma_aux_device_uninit(bp);
13186
13187         bnxt_ptp_clear(bp);
13188         unregister_netdev(dev);
13189         clear_bit(BNXT_STATE_IN_FW_RESET, &bp->state);
13190         /* Flush any pending tasks */
13191         cancel_work_sync(&bp->sp_task);
13192         cancel_delayed_work_sync(&bp->fw_reset_task);
13193         bp->sp_event = 0;
13194
13195         bnxt_dl_fw_reporters_destroy(bp);
13196         bnxt_dl_unregister(bp);
13197         bnxt_shutdown_tc(bp);
13198
13199         bnxt_clear_int_mode(bp);
13200         bnxt_hwrm_func_drv_unrgtr(bp);
13201         bnxt_free_hwrm_resources(bp);
13202         bnxt_ethtool_free(bp);
13203         bnxt_dcb_free(bp);
13204         kfree(bp->ptp_cfg);
13205         bp->ptp_cfg = NULL;
13206         kfree(bp->fw_health);
13207         bp->fw_health = NULL;
13208         bnxt_cleanup_pci(bp);
13209         bnxt_free_ctx_mem(bp);
13210         kfree(bp->ctx);
13211         bp->ctx = NULL;
13212         kfree(bp->rss_indir_tbl);
13213         bp->rss_indir_tbl = NULL;
13214         bnxt_free_port_stats(bp);
13215         free_netdev(dev);
13216 }
13217
13218 static int bnxt_probe_phy(struct bnxt *bp, bool fw_dflt)
13219 {
13220         int rc = 0;
13221         struct bnxt_link_info *link_info = &bp->link_info;
13222
13223         bp->phy_flags = 0;
13224         rc = bnxt_hwrm_phy_qcaps(bp);
13225         if (rc) {
13226                 netdev_err(bp->dev, "Probe phy can't get phy capabilities (rc: %x)\n",
13227                            rc);
13228                 return rc;
13229         }
13230         if (bp->phy_flags & BNXT_PHY_FL_NO_FCS)
13231                 bp->dev->priv_flags |= IFF_SUPP_NOFCS;
13232         else
13233                 bp->dev->priv_flags &= ~IFF_SUPP_NOFCS;
13234         if (!fw_dflt)
13235                 return 0;
13236
13237         mutex_lock(&bp->link_lock);
13238         rc = bnxt_update_link(bp, false);
13239         if (rc) {
13240                 mutex_unlock(&bp->link_lock);
13241                 netdev_err(bp->dev, "Probe phy can't update link (rc: %x)\n",
13242                            rc);
13243                 return rc;
13244         }
13245
13246         /* Older firmware does not have supported_auto_speeds, so assume
13247          * that all supported speeds can be autonegotiated.
13248          */
13249         if (link_info->auto_link_speeds && !link_info->support_auto_speeds)
13250                 link_info->support_auto_speeds = link_info->support_speeds;
13251
13252         bnxt_init_ethtool_link_settings(bp);
13253         mutex_unlock(&bp->link_lock);
13254         return 0;
13255 }
13256
13257 static int bnxt_get_max_irq(struct pci_dev *pdev)
13258 {
13259         u16 ctrl;
13260
13261         if (!pdev->msix_cap)
13262                 return 1;
13263
13264         pci_read_config_word(pdev, pdev->msix_cap + PCI_MSIX_FLAGS, &ctrl);
13265         return (ctrl & PCI_MSIX_FLAGS_QSIZE) + 1;
13266 }
13267
13268 static void _bnxt_get_max_rings(struct bnxt *bp, int *max_rx, int *max_tx,
13269                                 int *max_cp)
13270 {
13271         struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
13272         int max_ring_grps = 0, max_irq;
13273
13274         *max_tx = hw_resc->max_tx_rings;
13275         *max_rx = hw_resc->max_rx_rings;
13276         *max_cp = bnxt_get_max_func_cp_rings_for_en(bp);
13277         max_irq = min_t(int, bnxt_get_max_func_irqs(bp) -
13278                         bnxt_get_ulp_msix_num(bp),
13279                         hw_resc->max_stat_ctxs - bnxt_get_ulp_stat_ctxs(bp));
13280         if (!(bp->flags & BNXT_FLAG_CHIP_P5))
13281                 *max_cp = min_t(int, *max_cp, max_irq);
13282         max_ring_grps = hw_resc->max_hw_ring_grps;
13283         if (BNXT_CHIP_TYPE_NITRO_A0(bp) && BNXT_PF(bp)) {
13284                 *max_cp -= 1;
13285                 *max_rx -= 2;
13286         }
13287         if (bp->flags & BNXT_FLAG_AGG_RINGS)
13288                 *max_rx >>= 1;
13289         if (bp->flags & BNXT_FLAG_CHIP_P5) {
13290                 bnxt_trim_rings(bp, max_rx, max_tx, *max_cp, false);
13291                 /* On P5 chips, max_cp output param should be available NQs */
13292                 *max_cp = max_irq;
13293         }
13294         *max_rx = min_t(int, *max_rx, max_ring_grps);
13295 }
13296
13297 int bnxt_get_max_rings(struct bnxt *bp, int *max_rx, int *max_tx, bool shared)
13298 {
13299         int rx, tx, cp;
13300
13301         _bnxt_get_max_rings(bp, &rx, &tx, &cp);
13302         *max_rx = rx;
13303         *max_tx = tx;
13304         if (!rx || !tx || !cp)
13305                 return -ENOMEM;
13306
13307         return bnxt_trim_rings(bp, max_rx, max_tx, cp, shared);
13308 }
13309
13310 static int bnxt_get_dflt_rings(struct bnxt *bp, int *max_rx, int *max_tx,
13311                                bool shared)
13312 {
13313         int rc;
13314
13315         rc = bnxt_get_max_rings(bp, max_rx, max_tx, shared);
13316         if (rc && (bp->flags & BNXT_FLAG_AGG_RINGS)) {
13317                 /* Not enough rings, try disabling agg rings. */
13318                 bp->flags &= ~BNXT_FLAG_AGG_RINGS;
13319                 rc = bnxt_get_max_rings(bp, max_rx, max_tx, shared);
13320                 if (rc) {
13321                         /* set BNXT_FLAG_AGG_RINGS back for consistency */
13322                         bp->flags |= BNXT_FLAG_AGG_RINGS;
13323                         return rc;
13324                 }
13325                 bp->flags |= BNXT_FLAG_NO_AGG_RINGS;
13326                 bp->dev->hw_features &= ~(NETIF_F_LRO | NETIF_F_GRO_HW);
13327                 bp->dev->features &= ~(NETIF_F_LRO | NETIF_F_GRO_HW);
13328                 bnxt_set_ring_params(bp);
13329         }
13330
13331         if (bp->flags & BNXT_FLAG_ROCE_CAP) {
13332                 int max_cp, max_stat, max_irq;
13333
13334                 /* Reserve minimum resources for RoCE */
13335                 max_cp = bnxt_get_max_func_cp_rings(bp);
13336                 max_stat = bnxt_get_max_func_stat_ctxs(bp);
13337                 max_irq = bnxt_get_max_func_irqs(bp);
13338                 if (max_cp <= BNXT_MIN_ROCE_CP_RINGS ||
13339                     max_irq <= BNXT_MIN_ROCE_CP_RINGS ||
13340                     max_stat <= BNXT_MIN_ROCE_STAT_CTXS)
13341                         return 0;
13342
13343                 max_cp -= BNXT_MIN_ROCE_CP_RINGS;
13344                 max_irq -= BNXT_MIN_ROCE_CP_RINGS;
13345                 max_stat -= BNXT_MIN_ROCE_STAT_CTXS;
13346                 max_cp = min_t(int, max_cp, max_irq);
13347                 max_cp = min_t(int, max_cp, max_stat);
13348                 rc = bnxt_trim_rings(bp, max_rx, max_tx, max_cp, shared);
13349                 if (rc)
13350                         rc = 0;
13351         }
13352         return rc;
13353 }
13354
13355 /* In initial default shared ring setting, each shared ring must have a
13356  * RX/TX ring pair.
13357  */
13358 static void bnxt_trim_dflt_sh_rings(struct bnxt *bp)
13359 {
13360         bp->cp_nr_rings = min_t(int, bp->tx_nr_rings_per_tc, bp->rx_nr_rings);
13361         bp->rx_nr_rings = bp->cp_nr_rings;
13362         bp->tx_nr_rings_per_tc = bp->cp_nr_rings;
13363         bp->tx_nr_rings = bp->tx_nr_rings_per_tc;
13364 }
13365
13366 static int bnxt_set_dflt_rings(struct bnxt *bp, bool sh)
13367 {
13368         int dflt_rings, max_rx_rings, max_tx_rings, rc;
13369
13370         if (!bnxt_can_reserve_rings(bp))
13371                 return 0;
13372
13373         if (sh)
13374                 bp->flags |= BNXT_FLAG_SHARED_RINGS;
13375         dflt_rings = is_kdump_kernel() ? 1 : netif_get_num_default_rss_queues();
13376         /* Reduce default rings on multi-port cards so that total default
13377          * rings do not exceed CPU count.
13378          */
13379         if (bp->port_count > 1) {
13380                 int max_rings =
13381                         max_t(int, num_online_cpus() / bp->port_count, 1);
13382
13383                 dflt_rings = min_t(int, dflt_rings, max_rings);
13384         }
13385         rc = bnxt_get_dflt_rings(bp, &max_rx_rings, &max_tx_rings, sh);
13386         if (rc)
13387                 return rc;
13388         bp->rx_nr_rings = min_t(int, dflt_rings, max_rx_rings);
13389         bp->tx_nr_rings_per_tc = min_t(int, dflt_rings, max_tx_rings);
13390         if (sh)
13391                 bnxt_trim_dflt_sh_rings(bp);
13392         else
13393                 bp->cp_nr_rings = bp->tx_nr_rings_per_tc + bp->rx_nr_rings;
13394         bp->tx_nr_rings = bp->tx_nr_rings_per_tc;
13395
13396         rc = __bnxt_reserve_rings(bp);
13397         if (rc && rc != -ENODEV)
13398                 netdev_warn(bp->dev, "Unable to reserve tx rings\n");
13399         bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
13400         if (sh)
13401                 bnxt_trim_dflt_sh_rings(bp);
13402
13403         /* Rings may have been trimmed, re-reserve the trimmed rings. */
13404         if (bnxt_need_reserve_rings(bp)) {
13405                 rc = __bnxt_reserve_rings(bp);
13406                 if (rc && rc != -ENODEV)
13407                         netdev_warn(bp->dev, "2nd rings reservation failed.\n");
13408                 bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
13409         }
13410         if (BNXT_CHIP_TYPE_NITRO_A0(bp)) {
13411                 bp->rx_nr_rings++;
13412                 bp->cp_nr_rings++;
13413         }
13414         if (rc) {
13415                 bp->tx_nr_rings = 0;
13416                 bp->rx_nr_rings = 0;
13417         }
13418         return rc;
13419 }
13420
13421 static int bnxt_init_dflt_ring_mode(struct bnxt *bp)
13422 {
13423         int rc;
13424
13425         if (bp->tx_nr_rings)
13426                 return 0;
13427
13428         bnxt_ulp_irq_stop(bp);
13429         bnxt_clear_int_mode(bp);
13430         rc = bnxt_set_dflt_rings(bp, true);
13431         if (rc) {
13432                 if (BNXT_VF(bp) && rc == -ENODEV)
13433                         netdev_err(bp->dev, "Cannot configure VF rings while PF is unavailable.\n");
13434                 else
13435                         netdev_err(bp->dev, "Not enough rings available.\n");
13436                 goto init_dflt_ring_err;
13437         }
13438         rc = bnxt_init_int_mode(bp);
13439         if (rc)
13440                 goto init_dflt_ring_err;
13441
13442         bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
13443
13444         bnxt_set_dflt_rfs(bp);
13445
13446 init_dflt_ring_err:
13447         bnxt_ulp_irq_restart(bp, rc);
13448         return rc;
13449 }
13450
13451 int bnxt_restore_pf_fw_resources(struct bnxt *bp)
13452 {
13453         int rc;
13454
13455         ASSERT_RTNL();
13456         bnxt_hwrm_func_qcaps(bp);
13457
13458         if (netif_running(bp->dev))
13459                 __bnxt_close_nic(bp, true, false);
13460
13461         bnxt_ulp_irq_stop(bp);
13462         bnxt_clear_int_mode(bp);
13463         rc = bnxt_init_int_mode(bp);
13464         bnxt_ulp_irq_restart(bp, rc);
13465
13466         if (netif_running(bp->dev)) {
13467                 if (rc)
13468                         dev_close(bp->dev);
13469                 else
13470                         rc = bnxt_open_nic(bp, true, false);
13471         }
13472
13473         return rc;
13474 }
13475
13476 static int bnxt_init_mac_addr(struct bnxt *bp)
13477 {
13478         int rc = 0;
13479
13480         if (BNXT_PF(bp)) {
13481                 eth_hw_addr_set(bp->dev, bp->pf.mac_addr);
13482         } else {
13483 #ifdef CONFIG_BNXT_SRIOV
13484                 struct bnxt_vf_info *vf = &bp->vf;
13485                 bool strict_approval = true;
13486
13487                 if (is_valid_ether_addr(vf->mac_addr)) {
13488                         /* overwrite netdev dev_addr with admin VF MAC */
13489                         eth_hw_addr_set(bp->dev, vf->mac_addr);
13490                         /* Older PF driver or firmware may not approve this
13491                          * correctly.
13492                          */
13493                         strict_approval = false;
13494                 } else {
13495                         eth_hw_addr_random(bp->dev);
13496                 }
13497                 rc = bnxt_approve_mac(bp, bp->dev->dev_addr, strict_approval);
13498 #endif
13499         }
13500         return rc;
13501 }
13502
13503 static void bnxt_vpd_read_info(struct bnxt *bp)
13504 {
13505         struct pci_dev *pdev = bp->pdev;
13506         unsigned int vpd_size, kw_len;
13507         int pos, size;
13508         u8 *vpd_data;
13509
13510         vpd_data = pci_vpd_alloc(pdev, &vpd_size);
13511         if (IS_ERR(vpd_data)) {
13512                 pci_warn(pdev, "Unable to read VPD\n");
13513                 return;
13514         }
13515
13516         pos = pci_vpd_find_ro_info_keyword(vpd_data, vpd_size,
13517                                            PCI_VPD_RO_KEYWORD_PARTNO, &kw_len);
13518         if (pos < 0)
13519                 goto read_sn;
13520
13521         size = min_t(int, kw_len, BNXT_VPD_FLD_LEN - 1);
13522         memcpy(bp->board_partno, &vpd_data[pos], size);
13523
13524 read_sn:
13525         pos = pci_vpd_find_ro_info_keyword(vpd_data, vpd_size,
13526                                            PCI_VPD_RO_KEYWORD_SERIALNO,
13527                                            &kw_len);
13528         if (pos < 0)
13529                 goto exit;
13530
13531         size = min_t(int, kw_len, BNXT_VPD_FLD_LEN - 1);
13532         memcpy(bp->board_serialno, &vpd_data[pos], size);
13533 exit:
13534         kfree(vpd_data);
13535 }
13536
13537 static int bnxt_pcie_dsn_get(struct bnxt *bp, u8 dsn[])
13538 {
13539         struct pci_dev *pdev = bp->pdev;
13540         u64 qword;
13541
13542         qword = pci_get_dsn(pdev);
13543         if (!qword) {
13544                 netdev_info(bp->dev, "Unable to read adapter's DSN\n");
13545                 return -EOPNOTSUPP;
13546         }
13547
13548         put_unaligned_le64(qword, dsn);
13549
13550         bp->flags |= BNXT_FLAG_DSN_VALID;
13551         return 0;
13552 }
13553
13554 static int bnxt_map_db_bar(struct bnxt *bp)
13555 {
13556         if (!bp->db_size)
13557                 return -ENODEV;
13558         bp->bar1 = pci_iomap(bp->pdev, 2, bp->db_size);
13559         if (!bp->bar1)
13560                 return -ENOMEM;
13561         return 0;
13562 }
13563
13564 void bnxt_print_device_info(struct bnxt *bp)
13565 {
13566         netdev_info(bp->dev, "%s found at mem %lx, node addr %pM\n",
13567                     board_info[bp->board_idx].name,
13568                     (long)pci_resource_start(bp->pdev, 0), bp->dev->dev_addr);
13569
13570         pcie_print_link_status(bp->pdev);
13571 }
13572
13573 static int bnxt_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
13574 {
13575         struct net_device *dev;
13576         struct bnxt *bp;
13577         int rc, max_irqs;
13578
13579         if (pci_is_bridge(pdev))
13580                 return -ENODEV;
13581
13582         /* Clear any pending DMA transactions from crash kernel
13583          * while loading driver in capture kernel.
13584          */
13585         if (is_kdump_kernel()) {
13586                 pci_clear_master(pdev);
13587                 pcie_flr(pdev);
13588         }
13589
13590         max_irqs = bnxt_get_max_irq(pdev);
13591         dev = alloc_etherdev_mq(sizeof(*bp), max_irqs);
13592         if (!dev)
13593                 return -ENOMEM;
13594
13595         bp = netdev_priv(dev);
13596         bp->board_idx = ent->driver_data;
13597         bp->msg_enable = BNXT_DEF_MSG_ENABLE;
13598         bnxt_set_max_func_irqs(bp, max_irqs);
13599
13600         if (bnxt_vf_pciid(bp->board_idx))
13601                 bp->flags |= BNXT_FLAG_VF;
13602
13603         /* No devlink port registration in case of a VF */
13604         if (BNXT_PF(bp))
13605                 SET_NETDEV_DEVLINK_PORT(dev, &bp->dl_port);
13606
13607         if (pdev->msix_cap)
13608                 bp->flags |= BNXT_FLAG_MSIX_CAP;
13609
13610         rc = bnxt_init_board(pdev, dev);
13611         if (rc < 0)
13612                 goto init_err_free;
13613
13614         dev->netdev_ops = &bnxt_netdev_ops;
13615         dev->watchdog_timeo = BNXT_TX_TIMEOUT;
13616         dev->ethtool_ops = &bnxt_ethtool_ops;
13617         pci_set_drvdata(pdev, dev);
13618
13619         rc = bnxt_alloc_hwrm_resources(bp);
13620         if (rc)
13621                 goto init_err_pci_clean;
13622
13623         mutex_init(&bp->hwrm_cmd_lock);
13624         mutex_init(&bp->link_lock);
13625
13626         rc = bnxt_fw_init_one_p1(bp);
13627         if (rc)
13628                 goto init_err_pci_clean;
13629
13630         if (BNXT_PF(bp))
13631                 bnxt_vpd_read_info(bp);
13632
13633         if (BNXT_CHIP_P5(bp)) {
13634                 bp->flags |= BNXT_FLAG_CHIP_P5;
13635                 if (BNXT_CHIP_SR2(bp))
13636                         bp->flags |= BNXT_FLAG_CHIP_SR2;
13637         }
13638
13639         rc = bnxt_alloc_rss_indir_tbl(bp);
13640         if (rc)
13641                 goto init_err_pci_clean;
13642
13643         rc = bnxt_fw_init_one_p2(bp);
13644         if (rc)
13645                 goto init_err_pci_clean;
13646
13647         rc = bnxt_map_db_bar(bp);
13648         if (rc) {
13649                 dev_err(&pdev->dev, "Cannot map doorbell BAR rc = %d, aborting\n",
13650                         rc);
13651                 goto init_err_pci_clean;
13652         }
13653
13654         dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG |
13655                            NETIF_F_TSO | NETIF_F_TSO6 |
13656                            NETIF_F_GSO_UDP_TUNNEL | NETIF_F_GSO_GRE |
13657                            NETIF_F_GSO_IPXIP4 |
13658                            NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_GSO_GRE_CSUM |
13659                            NETIF_F_GSO_PARTIAL | NETIF_F_RXHASH |
13660                            NETIF_F_RXCSUM | NETIF_F_GRO;
13661
13662         if (BNXT_SUPPORTS_TPA(bp))
13663                 dev->hw_features |= NETIF_F_LRO;
13664
13665         dev->hw_enc_features =
13666                         NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG |
13667                         NETIF_F_TSO | NETIF_F_TSO6 |
13668                         NETIF_F_GSO_UDP_TUNNEL | NETIF_F_GSO_GRE |
13669                         NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_GSO_GRE_CSUM |
13670                         NETIF_F_GSO_IPXIP4 | NETIF_F_GSO_PARTIAL;
13671         dev->udp_tunnel_nic_info = &bnxt_udp_tunnels;
13672
13673         dev->gso_partial_features = NETIF_F_GSO_UDP_TUNNEL_CSUM |
13674                                     NETIF_F_GSO_GRE_CSUM;
13675         dev->vlan_features = dev->hw_features | NETIF_F_HIGHDMA;
13676         if (bp->fw_cap & BNXT_FW_CAP_VLAN_RX_STRIP)
13677                 dev->hw_features |= BNXT_HW_FEATURE_VLAN_ALL_RX;
13678         if (bp->fw_cap & BNXT_FW_CAP_VLAN_TX_INSERT)
13679                 dev->hw_features |= BNXT_HW_FEATURE_VLAN_ALL_TX;
13680         if (BNXT_SUPPORTS_TPA(bp))
13681                 dev->hw_features |= NETIF_F_GRO_HW;
13682         dev->features |= dev->hw_features | NETIF_F_HIGHDMA;
13683         if (dev->features & NETIF_F_GRO_HW)
13684                 dev->features &= ~NETIF_F_LRO;
13685         dev->priv_flags |= IFF_UNICAST_FLT;
13686
13687         netif_set_tso_max_size(dev, GSO_MAX_SIZE);
13688
13689         dev->xdp_features = NETDEV_XDP_ACT_BASIC | NETDEV_XDP_ACT_REDIRECT |
13690                             NETDEV_XDP_ACT_RX_SG;
13691
13692 #ifdef CONFIG_BNXT_SRIOV
13693         init_waitqueue_head(&bp->sriov_cfg_wait);
13694 #endif
13695         if (BNXT_SUPPORTS_TPA(bp)) {
13696                 bp->gro_func = bnxt_gro_func_5730x;
13697                 if (BNXT_CHIP_P4(bp))
13698                         bp->gro_func = bnxt_gro_func_5731x;
13699                 else if (BNXT_CHIP_P5(bp))
13700                         bp->gro_func = bnxt_gro_func_5750x;
13701         }
13702         if (!BNXT_CHIP_P4_PLUS(bp))
13703                 bp->flags |= BNXT_FLAG_DOUBLE_DB;
13704
13705         rc = bnxt_init_mac_addr(bp);
13706         if (rc) {
13707                 dev_err(&pdev->dev, "Unable to initialize mac address.\n");
13708                 rc = -EADDRNOTAVAIL;
13709                 goto init_err_pci_clean;
13710         }
13711
13712         if (BNXT_PF(bp)) {
13713                 /* Read the adapter's DSN to use as the eswitch switch_id */
13714                 rc = bnxt_pcie_dsn_get(bp, bp->dsn);
13715         }
13716
13717         /* MTU range: 60 - FW defined max */
13718         dev->min_mtu = ETH_ZLEN;
13719         dev->max_mtu = bp->max_mtu;
13720
13721         rc = bnxt_probe_phy(bp, true);
13722         if (rc)
13723                 goto init_err_pci_clean;
13724
13725         bnxt_set_rx_skb_mode(bp, false);
13726         bnxt_set_tpa_flags(bp);
13727         bnxt_set_ring_params(bp);
13728         rc = bnxt_set_dflt_rings(bp, true);
13729         if (rc) {
13730                 if (BNXT_VF(bp) && rc == -ENODEV) {
13731                         netdev_err(bp->dev, "Cannot configure VF rings while PF is unavailable.\n");
13732                 } else {
13733                         netdev_err(bp->dev, "Not enough rings available.\n");
13734                         rc = -ENOMEM;
13735                 }
13736                 goto init_err_pci_clean;
13737         }
13738
13739         bnxt_fw_init_one_p3(bp);
13740
13741         bnxt_init_dflt_coal(bp);
13742
13743         if (dev->hw_features & BNXT_HW_FEATURE_VLAN_ALL_RX)
13744                 bp->flags |= BNXT_FLAG_STRIP_VLAN;
13745
13746         rc = bnxt_init_int_mode(bp);
13747         if (rc)
13748                 goto init_err_pci_clean;
13749
13750         /* No TC has been set yet and rings may have been trimmed due to
13751          * limited MSIX, so we re-initialize the TX rings per TC.
13752          */
13753         bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
13754
13755         if (BNXT_PF(bp)) {
13756                 if (!bnxt_pf_wq) {
13757                         bnxt_pf_wq =
13758                                 create_singlethread_workqueue("bnxt_pf_wq");
13759                         if (!bnxt_pf_wq) {
13760                                 dev_err(&pdev->dev, "Unable to create workqueue.\n");
13761                                 rc = -ENOMEM;
13762                                 goto init_err_pci_clean;
13763                         }
13764                 }
13765                 rc = bnxt_init_tc(bp);
13766                 if (rc)
13767                         netdev_err(dev, "Failed to initialize TC flower offload, err = %d.\n",
13768                                    rc);
13769         }
13770
13771         bnxt_inv_fw_health_reg(bp);
13772         rc = bnxt_dl_register(bp);
13773         if (rc)
13774                 goto init_err_dl;
13775
13776         rc = register_netdev(dev);
13777         if (rc)
13778                 goto init_err_cleanup;
13779
13780         bnxt_dl_fw_reporters_create(bp);
13781
13782         bnxt_rdma_aux_device_init(bp);
13783
13784         bnxt_print_device_info(bp);
13785
13786         pci_save_state(pdev);
13787
13788         return 0;
13789 init_err_cleanup:
13790         bnxt_dl_unregister(bp);
13791 init_err_dl:
13792         bnxt_shutdown_tc(bp);
13793         bnxt_clear_int_mode(bp);
13794
13795 init_err_pci_clean:
13796         bnxt_hwrm_func_drv_unrgtr(bp);
13797         bnxt_free_hwrm_resources(bp);
13798         bnxt_ethtool_free(bp);
13799         bnxt_ptp_clear(bp);
13800         kfree(bp->ptp_cfg);
13801         bp->ptp_cfg = NULL;
13802         kfree(bp->fw_health);
13803         bp->fw_health = NULL;
13804         bnxt_cleanup_pci(bp);
13805         bnxt_free_ctx_mem(bp);
13806         kfree(bp->ctx);
13807         bp->ctx = NULL;
13808         kfree(bp->rss_indir_tbl);
13809         bp->rss_indir_tbl = NULL;
13810
13811 init_err_free:
13812         free_netdev(dev);
13813         return rc;
13814 }
13815
13816 static void bnxt_shutdown(struct pci_dev *pdev)
13817 {
13818         struct net_device *dev = pci_get_drvdata(pdev);
13819         struct bnxt *bp;
13820
13821         if (!dev)
13822                 return;
13823
13824         rtnl_lock();
13825         bp = netdev_priv(dev);
13826         if (!bp)
13827                 goto shutdown_exit;
13828
13829         if (netif_running(dev))
13830                 dev_close(dev);
13831
13832         bnxt_clear_int_mode(bp);
13833         pci_disable_device(pdev);
13834
13835         if (system_state == SYSTEM_POWER_OFF) {
13836                 pci_wake_from_d3(pdev, bp->wol);
13837                 pci_set_power_state(pdev, PCI_D3hot);
13838         }
13839
13840 shutdown_exit:
13841         rtnl_unlock();
13842 }
13843
13844 #ifdef CONFIG_PM_SLEEP
13845 static int bnxt_suspend(struct device *device)
13846 {
13847         struct net_device *dev = dev_get_drvdata(device);
13848         struct bnxt *bp = netdev_priv(dev);
13849         int rc = 0;
13850
13851         rtnl_lock();
13852         bnxt_ulp_stop(bp);
13853         if (netif_running(dev)) {
13854                 netif_device_detach(dev);
13855                 rc = bnxt_close(dev);
13856         }
13857         bnxt_hwrm_func_drv_unrgtr(bp);
13858         pci_disable_device(bp->pdev);
13859         bnxt_free_ctx_mem(bp);
13860         kfree(bp->ctx);
13861         bp->ctx = NULL;
13862         rtnl_unlock();
13863         return rc;
13864 }
13865
13866 static int bnxt_resume(struct device *device)
13867 {
13868         struct net_device *dev = dev_get_drvdata(device);
13869         struct bnxt *bp = netdev_priv(dev);
13870         int rc = 0;
13871
13872         rtnl_lock();
13873         rc = pci_enable_device(bp->pdev);
13874         if (rc) {
13875                 netdev_err(dev, "Cannot re-enable PCI device during resume, err = %d\n",
13876                            rc);
13877                 goto resume_exit;
13878         }
13879         pci_set_master(bp->pdev);
13880         if (bnxt_hwrm_ver_get(bp)) {
13881                 rc = -ENODEV;
13882                 goto resume_exit;
13883         }
13884         rc = bnxt_hwrm_func_reset(bp);
13885         if (rc) {
13886                 rc = -EBUSY;
13887                 goto resume_exit;
13888         }
13889
13890         rc = bnxt_hwrm_func_qcaps(bp);
13891         if (rc)
13892                 goto resume_exit;
13893
13894         if (bnxt_hwrm_func_drv_rgtr(bp, NULL, 0, false)) {
13895                 rc = -ENODEV;
13896                 goto resume_exit;
13897         }
13898
13899         bnxt_get_wol_settings(bp);
13900         if (netif_running(dev)) {
13901                 rc = bnxt_open(dev);
13902                 if (!rc)
13903                         netif_device_attach(dev);
13904         }
13905
13906 resume_exit:
13907         bnxt_ulp_start(bp, rc);
13908         if (!rc)
13909                 bnxt_reenable_sriov(bp);
13910         rtnl_unlock();
13911         return rc;
13912 }
13913
13914 static SIMPLE_DEV_PM_OPS(bnxt_pm_ops, bnxt_suspend, bnxt_resume);
13915 #define BNXT_PM_OPS (&bnxt_pm_ops)
13916
13917 #else
13918
13919 #define BNXT_PM_OPS NULL
13920
13921 #endif /* CONFIG_PM_SLEEP */
13922
13923 /**
13924  * bnxt_io_error_detected - called when PCI error is detected
13925  * @pdev: Pointer to PCI device
13926  * @state: The current pci connection state
13927  *
13928  * This function is called after a PCI bus error affecting
13929  * this device has been detected.
13930  */
13931 static pci_ers_result_t bnxt_io_error_detected(struct pci_dev *pdev,
13932                                                pci_channel_state_t state)
13933 {
13934         struct net_device *netdev = pci_get_drvdata(pdev);
13935         struct bnxt *bp = netdev_priv(netdev);
13936
13937         netdev_info(netdev, "PCI I/O error detected\n");
13938
13939         rtnl_lock();
13940         netif_device_detach(netdev);
13941
13942         bnxt_ulp_stop(bp);
13943
13944         if (state == pci_channel_io_perm_failure) {
13945                 rtnl_unlock();
13946                 return PCI_ERS_RESULT_DISCONNECT;
13947         }
13948
13949         if (state == pci_channel_io_frozen)
13950                 set_bit(BNXT_STATE_PCI_CHANNEL_IO_FROZEN, &bp->state);
13951
13952         if (netif_running(netdev))
13953                 bnxt_close(netdev);
13954
13955         if (pci_is_enabled(pdev))
13956                 pci_disable_device(pdev);
13957         bnxt_free_ctx_mem(bp);
13958         kfree(bp->ctx);
13959         bp->ctx = NULL;
13960         rtnl_unlock();
13961
13962         /* Request a slot slot reset. */
13963         return PCI_ERS_RESULT_NEED_RESET;
13964 }
13965
13966 /**
13967  * bnxt_io_slot_reset - called after the pci bus has been reset.
13968  * @pdev: Pointer to PCI device
13969  *
13970  * Restart the card from scratch, as if from a cold-boot.
13971  * At this point, the card has exprienced a hard reset,
13972  * followed by fixups by BIOS, and has its config space
13973  * set up identically to what it was at cold boot.
13974  */
13975 static pci_ers_result_t bnxt_io_slot_reset(struct pci_dev *pdev)
13976 {
13977         pci_ers_result_t result = PCI_ERS_RESULT_DISCONNECT;
13978         struct net_device *netdev = pci_get_drvdata(pdev);
13979         struct bnxt *bp = netdev_priv(netdev);
13980         int retry = 0;
13981         int err = 0;
13982         int off;
13983
13984         netdev_info(bp->dev, "PCI Slot Reset\n");
13985
13986         rtnl_lock();
13987
13988         if (pci_enable_device(pdev)) {
13989                 dev_err(&pdev->dev,
13990                         "Cannot re-enable PCI device after reset.\n");
13991         } else {
13992                 pci_set_master(pdev);
13993                 /* Upon fatal error, our device internal logic that latches to
13994                  * BAR value is getting reset and will restore only upon
13995                  * rewritting the BARs.
13996                  *
13997                  * As pci_restore_state() does not re-write the BARs if the
13998                  * value is same as saved value earlier, driver needs to
13999                  * write the BARs to 0 to force restore, in case of fatal error.
14000                  */
14001                 if (test_and_clear_bit(BNXT_STATE_PCI_CHANNEL_IO_FROZEN,
14002                                        &bp->state)) {
14003                         for (off = PCI_BASE_ADDRESS_0;
14004                              off <= PCI_BASE_ADDRESS_5; off += 4)
14005                                 pci_write_config_dword(bp->pdev, off, 0);
14006                 }
14007                 pci_restore_state(pdev);
14008                 pci_save_state(pdev);
14009
14010                 bnxt_inv_fw_health_reg(bp);
14011                 bnxt_try_map_fw_health_reg(bp);
14012
14013                 /* In some PCIe AER scenarios, firmware may take up to
14014                  * 10 seconds to become ready in the worst case.
14015                  */
14016                 do {
14017                         err = bnxt_try_recover_fw(bp);
14018                         if (!err)
14019                                 break;
14020                         retry++;
14021                 } while (retry < BNXT_FW_SLOT_RESET_RETRY);
14022
14023                 if (err) {
14024                         dev_err(&pdev->dev, "Firmware not ready\n");
14025                         goto reset_exit;
14026                 }
14027
14028                 err = bnxt_hwrm_func_reset(bp);
14029                 if (!err)
14030                         result = PCI_ERS_RESULT_RECOVERED;
14031
14032                 bnxt_ulp_irq_stop(bp);
14033                 bnxt_clear_int_mode(bp);
14034                 err = bnxt_init_int_mode(bp);
14035                 bnxt_ulp_irq_restart(bp, err);
14036         }
14037
14038 reset_exit:
14039         bnxt_clear_reservations(bp, true);
14040         rtnl_unlock();
14041
14042         return result;
14043 }
14044
14045 /**
14046  * bnxt_io_resume - called when traffic can start flowing again.
14047  * @pdev: Pointer to PCI device
14048  *
14049  * This callback is called when the error recovery driver tells
14050  * us that its OK to resume normal operation.
14051  */
14052 static void bnxt_io_resume(struct pci_dev *pdev)
14053 {
14054         struct net_device *netdev = pci_get_drvdata(pdev);
14055         struct bnxt *bp = netdev_priv(netdev);
14056         int err;
14057
14058         netdev_info(bp->dev, "PCI Slot Resume\n");
14059         rtnl_lock();
14060
14061         err = bnxt_hwrm_func_qcaps(bp);
14062         if (!err && netif_running(netdev))
14063                 err = bnxt_open(netdev);
14064
14065         bnxt_ulp_start(bp, err);
14066         if (!err) {
14067                 bnxt_reenable_sriov(bp);
14068                 netif_device_attach(netdev);
14069         }
14070
14071         rtnl_unlock();
14072 }
14073
14074 static const struct pci_error_handlers bnxt_err_handler = {
14075         .error_detected = bnxt_io_error_detected,
14076         .slot_reset     = bnxt_io_slot_reset,
14077         .resume         = bnxt_io_resume
14078 };
14079
14080 static struct pci_driver bnxt_pci_driver = {
14081         .name           = DRV_MODULE_NAME,
14082         .id_table       = bnxt_pci_tbl,
14083         .probe          = bnxt_init_one,
14084         .remove         = bnxt_remove_one,
14085         .shutdown       = bnxt_shutdown,
14086         .driver.pm      = BNXT_PM_OPS,
14087         .err_handler    = &bnxt_err_handler,
14088 #if defined(CONFIG_BNXT_SRIOV)
14089         .sriov_configure = bnxt_sriov_configure,
14090 #endif
14091 };
14092
14093 static int __init bnxt_init(void)
14094 {
14095         int err;
14096
14097         bnxt_debug_init();
14098         err = pci_register_driver(&bnxt_pci_driver);
14099         if (err) {
14100                 bnxt_debug_exit();
14101                 return err;
14102         }
14103
14104         return 0;
14105 }
14106
14107 static void __exit bnxt_exit(void)
14108 {
14109         pci_unregister_driver(&bnxt_pci_driver);
14110         if (bnxt_pf_wq)
14111                 destroy_workqueue(bnxt_pf_wq);
14112         bnxt_debug_exit();
14113 }
14114
14115 module_init(bnxt_init);
14116 module_exit(bnxt_exit);