1 /* Broadcom NetXtreme-C/E network driver.
3 * Copyright (c) 2014-2016 Broadcom Corporation
4 * Copyright (c) 2016-2019 Broadcom Limited
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation.
11 #include <linux/module.h>
13 #include <linux/stringify.h>
14 #include <linux/kernel.h>
15 #include <linux/timer.h>
16 #include <linux/errno.h>
17 #include <linux/ioport.h>
18 #include <linux/slab.h>
19 #include <linux/vmalloc.h>
20 #include <linux/interrupt.h>
21 #include <linux/pci.h>
22 #include <linux/netdevice.h>
23 #include <linux/etherdevice.h>
24 #include <linux/skbuff.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/bitops.h>
28 #include <linux/irq.h>
29 #include <linux/delay.h>
30 #include <asm/byteorder.h>
32 #include <linux/time.h>
33 #include <linux/mii.h>
34 #include <linux/mdio.h>
36 #include <linux/if_vlan.h>
37 #include <linux/if_bridge.h>
38 #include <linux/rtc.h>
39 #include <linux/bpf.h>
43 #include <net/checksum.h>
44 #include <net/ip6_checksum.h>
45 #include <net/udp_tunnel.h>
46 #include <linux/workqueue.h>
47 #include <linux/prefetch.h>
48 #include <linux/cache.h>
49 #include <linux/log2.h>
50 #include <linux/aer.h>
51 #include <linux/bitmap.h>
52 #include <linux/cpu_rmap.h>
53 #include <linux/cpumask.h>
54 #include <net/pkt_cls.h>
55 #include <linux/hwmon.h>
56 #include <linux/hwmon-sysfs.h>
57 #include <net/page_pool.h>
62 #include "bnxt_sriov.h"
63 #include "bnxt_ethtool.h"
68 #include "bnxt_devlink.h"
69 #include "bnxt_debugfs.h"
71 #define BNXT_TX_TIMEOUT (5 * HZ)
72 #define BNXT_DEF_MSG_ENABLE (NETIF_MSG_DRV | NETIF_MSG_HW)
74 MODULE_LICENSE("GPL");
75 MODULE_DESCRIPTION("Broadcom BCM573xx network driver");
77 #define BNXT_RX_OFFSET (NET_SKB_PAD + NET_IP_ALIGN)
78 #define BNXT_RX_DMA_OFFSET NET_SKB_PAD
79 #define BNXT_RX_COPY_THRESH 256
81 #define BNXT_TX_PUSH_THRESH 164
128 /* indexed by enum above */
129 static const struct {
132 [BCM57301] = { "Broadcom BCM57301 NetXtreme-C 10Gb Ethernet" },
133 [BCM57302] = { "Broadcom BCM57302 NetXtreme-C 10Gb/25Gb Ethernet" },
134 [BCM57304] = { "Broadcom BCM57304 NetXtreme-C 10Gb/25Gb/40Gb/50Gb Ethernet" },
135 [BCM57417_NPAR] = { "Broadcom BCM57417 NetXtreme-E Ethernet Partition" },
136 [BCM58700] = { "Broadcom BCM58700 Nitro 1Gb/2.5Gb/10Gb Ethernet" },
137 [BCM57311] = { "Broadcom BCM57311 NetXtreme-C 10Gb Ethernet" },
138 [BCM57312] = { "Broadcom BCM57312 NetXtreme-C 10Gb/25Gb Ethernet" },
139 [BCM57402] = { "Broadcom BCM57402 NetXtreme-E 10Gb Ethernet" },
140 [BCM57404] = { "Broadcom BCM57404 NetXtreme-E 10Gb/25Gb Ethernet" },
141 [BCM57406] = { "Broadcom BCM57406 NetXtreme-E 10GBase-T Ethernet" },
142 [BCM57402_NPAR] = { "Broadcom BCM57402 NetXtreme-E Ethernet Partition" },
143 [BCM57407] = { "Broadcom BCM57407 NetXtreme-E 10GBase-T Ethernet" },
144 [BCM57412] = { "Broadcom BCM57412 NetXtreme-E 10Gb Ethernet" },
145 [BCM57414] = { "Broadcom BCM57414 NetXtreme-E 10Gb/25Gb Ethernet" },
146 [BCM57416] = { "Broadcom BCM57416 NetXtreme-E 10GBase-T Ethernet" },
147 [BCM57417] = { "Broadcom BCM57417 NetXtreme-E 10GBase-T Ethernet" },
148 [BCM57412_NPAR] = { "Broadcom BCM57412 NetXtreme-E Ethernet Partition" },
149 [BCM57314] = { "Broadcom BCM57314 NetXtreme-C 10Gb/25Gb/40Gb/50Gb Ethernet" },
150 [BCM57417_SFP] = { "Broadcom BCM57417 NetXtreme-E 10Gb/25Gb Ethernet" },
151 [BCM57416_SFP] = { "Broadcom BCM57416 NetXtreme-E 10Gb Ethernet" },
152 [BCM57404_NPAR] = { "Broadcom BCM57404 NetXtreme-E Ethernet Partition" },
153 [BCM57406_NPAR] = { "Broadcom BCM57406 NetXtreme-E Ethernet Partition" },
154 [BCM57407_SFP] = { "Broadcom BCM57407 NetXtreme-E 25Gb Ethernet" },
155 [BCM57407_NPAR] = { "Broadcom BCM57407 NetXtreme-E Ethernet Partition" },
156 [BCM57414_NPAR] = { "Broadcom BCM57414 NetXtreme-E Ethernet Partition" },
157 [BCM57416_NPAR] = { "Broadcom BCM57416 NetXtreme-E Ethernet Partition" },
158 [BCM57452] = { "Broadcom BCM57452 NetXtreme-E 10Gb/25Gb/40Gb/50Gb Ethernet" },
159 [BCM57454] = { "Broadcom BCM57454 NetXtreme-E 10Gb/25Gb/40Gb/50Gb/100Gb Ethernet" },
160 [BCM5745x_NPAR] = { "Broadcom BCM5745x NetXtreme-E Ethernet Partition" },
161 [BCM57508] = { "Broadcom BCM57508 NetXtreme-E 10Gb/25Gb/50Gb/100Gb/200Gb Ethernet" },
162 [BCM57504] = { "Broadcom BCM57504 NetXtreme-E 10Gb/25Gb/50Gb/100Gb/200Gb Ethernet" },
163 [BCM57502] = { "Broadcom BCM57502 NetXtreme-E 10Gb/25Gb/50Gb Ethernet" },
164 [BCM57508_NPAR] = { "Broadcom BCM57508 NetXtreme-E Ethernet Partition" },
165 [BCM57504_NPAR] = { "Broadcom BCM57504 NetXtreme-E Ethernet Partition" },
166 [BCM57502_NPAR] = { "Broadcom BCM57502 NetXtreme-E Ethernet Partition" },
167 [BCM58802] = { "Broadcom BCM58802 NetXtreme-S 10Gb/25Gb/40Gb/50Gb Ethernet" },
168 [BCM58804] = { "Broadcom BCM58804 NetXtreme-S 10Gb/25Gb/40Gb/50Gb/100Gb Ethernet" },
169 [BCM58808] = { "Broadcom BCM58808 NetXtreme-S 10Gb/25Gb/40Gb/50Gb/100Gb Ethernet" },
170 [NETXTREME_E_VF] = { "Broadcom NetXtreme-E Ethernet Virtual Function" },
171 [NETXTREME_C_VF] = { "Broadcom NetXtreme-C Ethernet Virtual Function" },
172 [NETXTREME_S_VF] = { "Broadcom NetXtreme-S Ethernet Virtual Function" },
173 [NETXTREME_E_P5_VF] = { "Broadcom BCM5750X NetXtreme-E Ethernet Virtual Function" },
176 static const struct pci_device_id bnxt_pci_tbl[] = {
177 { PCI_VDEVICE(BROADCOM, 0x1604), .driver_data = BCM5745x_NPAR },
178 { PCI_VDEVICE(BROADCOM, 0x1605), .driver_data = BCM5745x_NPAR },
179 { PCI_VDEVICE(BROADCOM, 0x1614), .driver_data = BCM57454 },
180 { PCI_VDEVICE(BROADCOM, 0x16c0), .driver_data = BCM57417_NPAR },
181 { PCI_VDEVICE(BROADCOM, 0x16c8), .driver_data = BCM57301 },
182 { PCI_VDEVICE(BROADCOM, 0x16c9), .driver_data = BCM57302 },
183 { PCI_VDEVICE(BROADCOM, 0x16ca), .driver_data = BCM57304 },
184 { PCI_VDEVICE(BROADCOM, 0x16cc), .driver_data = BCM57417_NPAR },
185 { PCI_VDEVICE(BROADCOM, 0x16cd), .driver_data = BCM58700 },
186 { PCI_VDEVICE(BROADCOM, 0x16ce), .driver_data = BCM57311 },
187 { PCI_VDEVICE(BROADCOM, 0x16cf), .driver_data = BCM57312 },
188 { PCI_VDEVICE(BROADCOM, 0x16d0), .driver_data = BCM57402 },
189 { PCI_VDEVICE(BROADCOM, 0x16d1), .driver_data = BCM57404 },
190 { PCI_VDEVICE(BROADCOM, 0x16d2), .driver_data = BCM57406 },
191 { PCI_VDEVICE(BROADCOM, 0x16d4), .driver_data = BCM57402_NPAR },
192 { PCI_VDEVICE(BROADCOM, 0x16d5), .driver_data = BCM57407 },
193 { PCI_VDEVICE(BROADCOM, 0x16d6), .driver_data = BCM57412 },
194 { PCI_VDEVICE(BROADCOM, 0x16d7), .driver_data = BCM57414 },
195 { PCI_VDEVICE(BROADCOM, 0x16d8), .driver_data = BCM57416 },
196 { PCI_VDEVICE(BROADCOM, 0x16d9), .driver_data = BCM57417 },
197 { PCI_VDEVICE(BROADCOM, 0x16de), .driver_data = BCM57412_NPAR },
198 { PCI_VDEVICE(BROADCOM, 0x16df), .driver_data = BCM57314 },
199 { PCI_VDEVICE(BROADCOM, 0x16e2), .driver_data = BCM57417_SFP },
200 { PCI_VDEVICE(BROADCOM, 0x16e3), .driver_data = BCM57416_SFP },
201 { PCI_VDEVICE(BROADCOM, 0x16e7), .driver_data = BCM57404_NPAR },
202 { PCI_VDEVICE(BROADCOM, 0x16e8), .driver_data = BCM57406_NPAR },
203 { PCI_VDEVICE(BROADCOM, 0x16e9), .driver_data = BCM57407_SFP },
204 { PCI_VDEVICE(BROADCOM, 0x16ea), .driver_data = BCM57407_NPAR },
205 { PCI_VDEVICE(BROADCOM, 0x16eb), .driver_data = BCM57412_NPAR },
206 { PCI_VDEVICE(BROADCOM, 0x16ec), .driver_data = BCM57414_NPAR },
207 { PCI_VDEVICE(BROADCOM, 0x16ed), .driver_data = BCM57414_NPAR },
208 { PCI_VDEVICE(BROADCOM, 0x16ee), .driver_data = BCM57416_NPAR },
209 { PCI_VDEVICE(BROADCOM, 0x16ef), .driver_data = BCM57416_NPAR },
210 { PCI_VDEVICE(BROADCOM, 0x16f0), .driver_data = BCM58808 },
211 { PCI_VDEVICE(BROADCOM, 0x16f1), .driver_data = BCM57452 },
212 { PCI_VDEVICE(BROADCOM, 0x1750), .driver_data = BCM57508 },
213 { PCI_VDEVICE(BROADCOM, 0x1751), .driver_data = BCM57504 },
214 { PCI_VDEVICE(BROADCOM, 0x1752), .driver_data = BCM57502 },
215 { PCI_VDEVICE(BROADCOM, 0x1800), .driver_data = BCM57508_NPAR },
216 { PCI_VDEVICE(BROADCOM, 0x1801), .driver_data = BCM57504_NPAR },
217 { PCI_VDEVICE(BROADCOM, 0x1802), .driver_data = BCM57502_NPAR },
218 { PCI_VDEVICE(BROADCOM, 0x1803), .driver_data = BCM57508_NPAR },
219 { PCI_VDEVICE(BROADCOM, 0x1804), .driver_data = BCM57504_NPAR },
220 { PCI_VDEVICE(BROADCOM, 0x1805), .driver_data = BCM57502_NPAR },
221 { PCI_VDEVICE(BROADCOM, 0xd802), .driver_data = BCM58802 },
222 { PCI_VDEVICE(BROADCOM, 0xd804), .driver_data = BCM58804 },
223 #ifdef CONFIG_BNXT_SRIOV
224 { PCI_VDEVICE(BROADCOM, 0x1606), .driver_data = NETXTREME_E_VF },
225 { PCI_VDEVICE(BROADCOM, 0x1609), .driver_data = NETXTREME_E_VF },
226 { PCI_VDEVICE(BROADCOM, 0x16c1), .driver_data = NETXTREME_E_VF },
227 { PCI_VDEVICE(BROADCOM, 0x16cb), .driver_data = NETXTREME_C_VF },
228 { PCI_VDEVICE(BROADCOM, 0x16d3), .driver_data = NETXTREME_E_VF },
229 { PCI_VDEVICE(BROADCOM, 0x16dc), .driver_data = NETXTREME_E_VF },
230 { PCI_VDEVICE(BROADCOM, 0x16e1), .driver_data = NETXTREME_C_VF },
231 { PCI_VDEVICE(BROADCOM, 0x16e5), .driver_data = NETXTREME_C_VF },
232 { PCI_VDEVICE(BROADCOM, 0x1806), .driver_data = NETXTREME_E_P5_VF },
233 { PCI_VDEVICE(BROADCOM, 0x1807), .driver_data = NETXTREME_E_P5_VF },
234 { PCI_VDEVICE(BROADCOM, 0xd800), .driver_data = NETXTREME_S_VF },
239 MODULE_DEVICE_TABLE(pci, bnxt_pci_tbl);
241 static const u16 bnxt_vf_req_snif[] = {
245 HWRM_CFA_L2_FILTER_ALLOC,
248 static const u16 bnxt_async_events_arr[] = {
249 ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE,
250 ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CHANGE,
251 ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD,
252 ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED,
253 ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE,
254 ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE,
255 ASYNC_EVENT_CMPL_EVENT_ID_PORT_PHY_CFG_CHANGE,
256 ASYNC_EVENT_CMPL_EVENT_ID_RESET_NOTIFY,
257 ASYNC_EVENT_CMPL_EVENT_ID_ERROR_RECOVERY,
258 ASYNC_EVENT_CMPL_EVENT_ID_RING_MONITOR_MSG,
261 static struct workqueue_struct *bnxt_pf_wq;
263 static bool bnxt_vf_pciid(enum board_idx idx)
265 return (idx == NETXTREME_C_VF || idx == NETXTREME_E_VF ||
266 idx == NETXTREME_S_VF || idx == NETXTREME_E_P5_VF);
269 #define DB_CP_REARM_FLAGS (DB_KEY_CP | DB_IDX_VALID)
270 #define DB_CP_FLAGS (DB_KEY_CP | DB_IDX_VALID | DB_IRQ_DIS)
271 #define DB_CP_IRQ_DIS_FLAGS (DB_KEY_CP | DB_IRQ_DIS)
273 #define BNXT_CP_DB_IRQ_DIS(db) \
274 writel(DB_CP_IRQ_DIS_FLAGS, db)
276 #define BNXT_DB_CQ(db, idx) \
277 writel(DB_CP_FLAGS | RING_CMP(idx), (db)->doorbell)
279 #define BNXT_DB_NQ_P5(db, idx) \
280 writeq((db)->db_key64 | DBR_TYPE_NQ | RING_CMP(idx), (db)->doorbell)
282 #define BNXT_DB_CQ_ARM(db, idx) \
283 writel(DB_CP_REARM_FLAGS | RING_CMP(idx), (db)->doorbell)
285 #define BNXT_DB_NQ_ARM_P5(db, idx) \
286 writeq((db)->db_key64 | DBR_TYPE_NQ_ARM | RING_CMP(idx), (db)->doorbell)
288 static void bnxt_db_nq(struct bnxt *bp, struct bnxt_db_info *db, u32 idx)
290 if (bp->flags & BNXT_FLAG_CHIP_P5)
291 BNXT_DB_NQ_P5(db, idx);
296 static void bnxt_db_nq_arm(struct bnxt *bp, struct bnxt_db_info *db, u32 idx)
298 if (bp->flags & BNXT_FLAG_CHIP_P5)
299 BNXT_DB_NQ_ARM_P5(db, idx);
301 BNXT_DB_CQ_ARM(db, idx);
304 static void bnxt_db_cq(struct bnxt *bp, struct bnxt_db_info *db, u32 idx)
306 if (bp->flags & BNXT_FLAG_CHIP_P5)
307 writeq(db->db_key64 | DBR_TYPE_CQ_ARMALL | RING_CMP(idx),
313 const u16 bnxt_lhint_arr[] = {
314 TX_BD_FLAGS_LHINT_512_AND_SMALLER,
315 TX_BD_FLAGS_LHINT_512_TO_1023,
316 TX_BD_FLAGS_LHINT_1024_TO_2047,
317 TX_BD_FLAGS_LHINT_1024_TO_2047,
318 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
319 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
320 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
321 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
322 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
323 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
324 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
325 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
326 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
327 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
328 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
329 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
330 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
331 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
332 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
335 static u16 bnxt_xmit_get_cfa_action(struct sk_buff *skb)
337 struct metadata_dst *md_dst = skb_metadata_dst(skb);
339 if (!md_dst || md_dst->type != METADATA_HW_PORT_MUX)
342 return md_dst->u.port_info.port_id;
345 static netdev_tx_t bnxt_start_xmit(struct sk_buff *skb, struct net_device *dev)
347 struct bnxt *bp = netdev_priv(dev);
349 struct tx_bd_ext *txbd1;
350 struct netdev_queue *txq;
353 unsigned int length, pad = 0;
354 u32 len, free_size, vlan_tag_flags, cfa_action, flags;
356 struct pci_dev *pdev = bp->pdev;
357 struct bnxt_tx_ring_info *txr;
358 struct bnxt_sw_tx_bd *tx_buf;
360 i = skb_get_queue_mapping(skb);
361 if (unlikely(i >= bp->tx_nr_rings)) {
362 dev_kfree_skb_any(skb);
366 txq = netdev_get_tx_queue(dev, i);
367 txr = &bp->tx_ring[bp->tx_ring_map[i]];
370 free_size = bnxt_tx_avail(bp, txr);
371 if (unlikely(free_size < skb_shinfo(skb)->nr_frags + 2)) {
372 netif_tx_stop_queue(txq);
373 return NETDEV_TX_BUSY;
377 len = skb_headlen(skb);
378 last_frag = skb_shinfo(skb)->nr_frags;
380 txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
382 txbd->tx_bd_opaque = prod;
384 tx_buf = &txr->tx_buf_ring[prod];
386 tx_buf->nr_frags = last_frag;
389 cfa_action = bnxt_xmit_get_cfa_action(skb);
390 if (skb_vlan_tag_present(skb)) {
391 vlan_tag_flags = TX_BD_CFA_META_KEY_VLAN |
392 skb_vlan_tag_get(skb);
393 /* Currently supports 8021Q, 8021AD vlan offloads
394 * QINQ1, QINQ2, QINQ3 vlan headers are deprecated
396 if (skb->vlan_proto == htons(ETH_P_8021Q))
397 vlan_tag_flags |= 1 << TX_BD_CFA_META_TPID_SHIFT;
400 if (free_size == bp->tx_ring_size && length <= bp->tx_push_thresh) {
401 struct tx_push_buffer *tx_push_buf = txr->tx_push;
402 struct tx_push_bd *tx_push = &tx_push_buf->push_bd;
403 struct tx_bd_ext *tx_push1 = &tx_push->txbd2;
404 void __iomem *db = txr->tx_db.doorbell;
405 void *pdata = tx_push_buf->data;
409 /* Set COAL_NOW to be ready quickly for the next push */
410 tx_push->tx_bd_len_flags_type =
411 cpu_to_le32((length << TX_BD_LEN_SHIFT) |
412 TX_BD_TYPE_LONG_TX_BD |
413 TX_BD_FLAGS_LHINT_512_AND_SMALLER |
414 TX_BD_FLAGS_COAL_NOW |
415 TX_BD_FLAGS_PACKET_END |
416 (2 << TX_BD_FLAGS_BD_CNT_SHIFT));
418 if (skb->ip_summed == CHECKSUM_PARTIAL)
419 tx_push1->tx_bd_hsize_lflags =
420 cpu_to_le32(TX_BD_FLAGS_TCP_UDP_CHKSUM);
422 tx_push1->tx_bd_hsize_lflags = 0;
424 tx_push1->tx_bd_cfa_meta = cpu_to_le32(vlan_tag_flags);
425 tx_push1->tx_bd_cfa_action =
426 cpu_to_le32(cfa_action << TX_BD_CFA_ACTION_SHIFT);
428 end = pdata + length;
429 end = PTR_ALIGN(end, 8) - 1;
432 skb_copy_from_linear_data(skb, pdata, len);
434 for (j = 0; j < last_frag; j++) {
435 skb_frag_t *frag = &skb_shinfo(skb)->frags[j];
438 fptr = skb_frag_address_safe(frag);
442 memcpy(pdata, fptr, skb_frag_size(frag));
443 pdata += skb_frag_size(frag);
446 txbd->tx_bd_len_flags_type = tx_push->tx_bd_len_flags_type;
447 txbd->tx_bd_haddr = txr->data_mapping;
448 prod = NEXT_TX(prod);
449 txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
450 memcpy(txbd, tx_push1, sizeof(*txbd));
451 prod = NEXT_TX(prod);
453 cpu_to_le32(DB_KEY_TX_PUSH | DB_LONG_TX_PUSH | prod);
457 netdev_tx_sent_queue(txq, skb->len);
458 wmb(); /* Sync is_push and byte queue before pushing data */
460 push_len = (length + sizeof(*tx_push) + 7) / 8;
462 __iowrite64_copy(db, tx_push_buf, 16);
463 __iowrite32_copy(db + 4, tx_push_buf + 1,
464 (push_len - 16) << 1);
466 __iowrite64_copy(db, tx_push_buf, push_len);
473 if (length < BNXT_MIN_PKT_SIZE) {
474 pad = BNXT_MIN_PKT_SIZE - length;
475 if (skb_pad(skb, pad)) {
476 /* SKB already freed. */
480 length = BNXT_MIN_PKT_SIZE;
483 mapping = dma_map_single(&pdev->dev, skb->data, len, DMA_TO_DEVICE);
485 if (unlikely(dma_mapping_error(&pdev->dev, mapping))) {
486 dev_kfree_skb_any(skb);
491 dma_unmap_addr_set(tx_buf, mapping, mapping);
492 flags = (len << TX_BD_LEN_SHIFT) | TX_BD_TYPE_LONG_TX_BD |
493 ((last_frag + 2) << TX_BD_FLAGS_BD_CNT_SHIFT);
495 txbd->tx_bd_haddr = cpu_to_le64(mapping);
497 prod = NEXT_TX(prod);
498 txbd1 = (struct tx_bd_ext *)
499 &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
501 txbd1->tx_bd_hsize_lflags = 0;
502 if (skb_is_gso(skb)) {
505 if (skb->encapsulation)
506 hdr_len = skb_inner_network_offset(skb) +
507 skb_inner_network_header_len(skb) +
508 inner_tcp_hdrlen(skb);
510 hdr_len = skb_transport_offset(skb) +
513 txbd1->tx_bd_hsize_lflags = cpu_to_le32(TX_BD_FLAGS_LSO |
515 (hdr_len << (TX_BD_HSIZE_SHIFT - 1)));
516 length = skb_shinfo(skb)->gso_size;
517 txbd1->tx_bd_mss = cpu_to_le32(length);
519 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
520 txbd1->tx_bd_hsize_lflags =
521 cpu_to_le32(TX_BD_FLAGS_TCP_UDP_CHKSUM);
522 txbd1->tx_bd_mss = 0;
526 if (unlikely(length >= ARRAY_SIZE(bnxt_lhint_arr))) {
527 dev_warn_ratelimited(&pdev->dev, "Dropped oversize %d bytes TX packet.\n",
532 flags |= bnxt_lhint_arr[length];
533 txbd->tx_bd_len_flags_type = cpu_to_le32(flags);
535 txbd1->tx_bd_cfa_meta = cpu_to_le32(vlan_tag_flags);
536 txbd1->tx_bd_cfa_action =
537 cpu_to_le32(cfa_action << TX_BD_CFA_ACTION_SHIFT);
538 for (i = 0; i < last_frag; i++) {
539 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
541 prod = NEXT_TX(prod);
542 txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
544 len = skb_frag_size(frag);
545 mapping = skb_frag_dma_map(&pdev->dev, frag, 0, len,
548 if (unlikely(dma_mapping_error(&pdev->dev, mapping)))
551 tx_buf = &txr->tx_buf_ring[prod];
552 dma_unmap_addr_set(tx_buf, mapping, mapping);
554 txbd->tx_bd_haddr = cpu_to_le64(mapping);
556 flags = len << TX_BD_LEN_SHIFT;
557 txbd->tx_bd_len_flags_type = cpu_to_le32(flags);
561 txbd->tx_bd_len_flags_type =
562 cpu_to_le32(((len + pad) << TX_BD_LEN_SHIFT) | flags |
563 TX_BD_FLAGS_PACKET_END);
565 netdev_tx_sent_queue(txq, skb->len);
567 /* Sync BD data before updating doorbell */
570 prod = NEXT_TX(prod);
573 if (!netdev_xmit_more() || netif_xmit_stopped(txq))
574 bnxt_db_write(bp, &txr->tx_db, prod);
578 if (unlikely(bnxt_tx_avail(bp, txr) <= MAX_SKB_FRAGS + 1)) {
579 if (netdev_xmit_more() && !tx_buf->is_push)
580 bnxt_db_write(bp, &txr->tx_db, prod);
582 netif_tx_stop_queue(txq);
584 /* netif_tx_stop_queue() must be done before checking
585 * tx index in bnxt_tx_avail() below, because in
586 * bnxt_tx_int(), we update tx index before checking for
587 * netif_tx_queue_stopped().
590 if (bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh)
591 netif_tx_wake_queue(txq);
598 /* start back at beginning and unmap skb */
600 tx_buf = &txr->tx_buf_ring[prod];
602 dma_unmap_single(&pdev->dev, dma_unmap_addr(tx_buf, mapping),
603 skb_headlen(skb), PCI_DMA_TODEVICE);
604 prod = NEXT_TX(prod);
606 /* unmap remaining mapped pages */
607 for (i = 0; i < last_frag; i++) {
608 prod = NEXT_TX(prod);
609 tx_buf = &txr->tx_buf_ring[prod];
610 dma_unmap_page(&pdev->dev, dma_unmap_addr(tx_buf, mapping),
611 skb_frag_size(&skb_shinfo(skb)->frags[i]),
615 dev_kfree_skb_any(skb);
619 static void bnxt_tx_int(struct bnxt *bp, struct bnxt_napi *bnapi, int nr_pkts)
621 struct bnxt_tx_ring_info *txr = bnapi->tx_ring;
622 struct netdev_queue *txq = netdev_get_tx_queue(bp->dev, txr->txq_index);
623 u16 cons = txr->tx_cons;
624 struct pci_dev *pdev = bp->pdev;
626 unsigned int tx_bytes = 0;
628 for (i = 0; i < nr_pkts; i++) {
629 struct bnxt_sw_tx_bd *tx_buf;
633 tx_buf = &txr->tx_buf_ring[cons];
634 cons = NEXT_TX(cons);
638 if (tx_buf->is_push) {
643 dma_unmap_single(&pdev->dev, dma_unmap_addr(tx_buf, mapping),
644 skb_headlen(skb), PCI_DMA_TODEVICE);
645 last = tx_buf->nr_frags;
647 for (j = 0; j < last; j++) {
648 cons = NEXT_TX(cons);
649 tx_buf = &txr->tx_buf_ring[cons];
652 dma_unmap_addr(tx_buf, mapping),
653 skb_frag_size(&skb_shinfo(skb)->frags[j]),
658 cons = NEXT_TX(cons);
660 tx_bytes += skb->len;
661 dev_kfree_skb_any(skb);
664 netdev_tx_completed_queue(txq, nr_pkts, tx_bytes);
667 /* Need to make the tx_cons update visible to bnxt_start_xmit()
668 * before checking for netif_tx_queue_stopped(). Without the
669 * memory barrier, there is a small possibility that bnxt_start_xmit()
670 * will miss it and cause the queue to be stopped forever.
674 if (unlikely(netif_tx_queue_stopped(txq)) &&
675 (bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh)) {
676 __netif_tx_lock(txq, smp_processor_id());
677 if (netif_tx_queue_stopped(txq) &&
678 bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh &&
679 txr->dev_state != BNXT_DEV_STATE_CLOSING)
680 netif_tx_wake_queue(txq);
681 __netif_tx_unlock(txq);
685 static struct page *__bnxt_alloc_rx_page(struct bnxt *bp, dma_addr_t *mapping,
686 struct bnxt_rx_ring_info *rxr,
689 struct device *dev = &bp->pdev->dev;
692 page = page_pool_dev_alloc_pages(rxr->page_pool);
696 *mapping = dma_map_page_attrs(dev, page, 0, PAGE_SIZE, bp->rx_dir,
697 DMA_ATTR_WEAK_ORDERING);
698 if (dma_mapping_error(dev, *mapping)) {
699 page_pool_recycle_direct(rxr->page_pool, page);
702 *mapping += bp->rx_dma_offset;
706 static inline u8 *__bnxt_alloc_rx_data(struct bnxt *bp, dma_addr_t *mapping,
710 struct pci_dev *pdev = bp->pdev;
712 data = kmalloc(bp->rx_buf_size, gfp);
716 *mapping = dma_map_single_attrs(&pdev->dev, data + bp->rx_dma_offset,
717 bp->rx_buf_use_size, bp->rx_dir,
718 DMA_ATTR_WEAK_ORDERING);
720 if (dma_mapping_error(&pdev->dev, *mapping)) {
727 int bnxt_alloc_rx_data(struct bnxt *bp, struct bnxt_rx_ring_info *rxr,
730 struct rx_bd *rxbd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
731 struct bnxt_sw_rx_bd *rx_buf = &rxr->rx_buf_ring[prod];
734 if (BNXT_RX_PAGE_MODE(bp)) {
736 __bnxt_alloc_rx_page(bp, &mapping, rxr, gfp);
742 rx_buf->data_ptr = page_address(page) + bp->rx_offset;
744 u8 *data = __bnxt_alloc_rx_data(bp, &mapping, gfp);
750 rx_buf->data_ptr = data + bp->rx_offset;
752 rx_buf->mapping = mapping;
754 rxbd->rx_bd_haddr = cpu_to_le64(mapping);
758 void bnxt_reuse_rx_data(struct bnxt_rx_ring_info *rxr, u16 cons, void *data)
760 u16 prod = rxr->rx_prod;
761 struct bnxt_sw_rx_bd *cons_rx_buf, *prod_rx_buf;
762 struct rx_bd *cons_bd, *prod_bd;
764 prod_rx_buf = &rxr->rx_buf_ring[prod];
765 cons_rx_buf = &rxr->rx_buf_ring[cons];
767 prod_rx_buf->data = data;
768 prod_rx_buf->data_ptr = cons_rx_buf->data_ptr;
770 prod_rx_buf->mapping = cons_rx_buf->mapping;
772 prod_bd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
773 cons_bd = &rxr->rx_desc_ring[RX_RING(cons)][RX_IDX(cons)];
775 prod_bd->rx_bd_haddr = cons_bd->rx_bd_haddr;
778 static inline u16 bnxt_find_next_agg_idx(struct bnxt_rx_ring_info *rxr, u16 idx)
780 u16 next, max = rxr->rx_agg_bmap_size;
782 next = find_next_zero_bit(rxr->rx_agg_bmap, max, idx);
784 next = find_first_zero_bit(rxr->rx_agg_bmap, max);
788 static inline int bnxt_alloc_rx_page(struct bnxt *bp,
789 struct bnxt_rx_ring_info *rxr,
793 &rxr->rx_agg_desc_ring[RX_RING(prod)][RX_IDX(prod)];
794 struct bnxt_sw_rx_agg_bd *rx_agg_buf;
795 struct pci_dev *pdev = bp->pdev;
798 u16 sw_prod = rxr->rx_sw_agg_prod;
799 unsigned int offset = 0;
801 if (PAGE_SIZE > BNXT_RX_PAGE_SIZE) {
804 page = alloc_page(gfp);
808 rxr->rx_page_offset = 0;
810 offset = rxr->rx_page_offset;
811 rxr->rx_page_offset += BNXT_RX_PAGE_SIZE;
812 if (rxr->rx_page_offset == PAGE_SIZE)
817 page = alloc_page(gfp);
822 mapping = dma_map_page_attrs(&pdev->dev, page, offset,
823 BNXT_RX_PAGE_SIZE, PCI_DMA_FROMDEVICE,
824 DMA_ATTR_WEAK_ORDERING);
825 if (dma_mapping_error(&pdev->dev, mapping)) {
830 if (unlikely(test_bit(sw_prod, rxr->rx_agg_bmap)))
831 sw_prod = bnxt_find_next_agg_idx(rxr, sw_prod);
833 __set_bit(sw_prod, rxr->rx_agg_bmap);
834 rx_agg_buf = &rxr->rx_agg_ring[sw_prod];
835 rxr->rx_sw_agg_prod = NEXT_RX_AGG(sw_prod);
837 rx_agg_buf->page = page;
838 rx_agg_buf->offset = offset;
839 rx_agg_buf->mapping = mapping;
840 rxbd->rx_bd_haddr = cpu_to_le64(mapping);
841 rxbd->rx_bd_opaque = sw_prod;
845 static struct rx_agg_cmp *bnxt_get_agg(struct bnxt *bp,
846 struct bnxt_cp_ring_info *cpr,
847 u16 cp_cons, u16 curr)
849 struct rx_agg_cmp *agg;
851 cp_cons = RING_CMP(ADV_RAW_CMP(cp_cons, curr));
852 agg = (struct rx_agg_cmp *)
853 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
857 static struct rx_agg_cmp *bnxt_get_tpa_agg_p5(struct bnxt *bp,
858 struct bnxt_rx_ring_info *rxr,
859 u16 agg_id, u16 curr)
861 struct bnxt_tpa_info *tpa_info = &rxr->rx_tpa[agg_id];
863 return &tpa_info->agg_arr[curr];
866 static void bnxt_reuse_rx_agg_bufs(struct bnxt_cp_ring_info *cpr, u16 idx,
867 u16 start, u32 agg_bufs, bool tpa)
869 struct bnxt_napi *bnapi = cpr->bnapi;
870 struct bnxt *bp = bnapi->bp;
871 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
872 u16 prod = rxr->rx_agg_prod;
873 u16 sw_prod = rxr->rx_sw_agg_prod;
877 if ((bp->flags & BNXT_FLAG_CHIP_P5) && tpa)
880 for (i = 0; i < agg_bufs; i++) {
882 struct rx_agg_cmp *agg;
883 struct bnxt_sw_rx_agg_bd *cons_rx_buf, *prod_rx_buf;
884 struct rx_bd *prod_bd;
888 agg = bnxt_get_tpa_agg_p5(bp, rxr, idx, start + i);
890 agg = bnxt_get_agg(bp, cpr, idx, start + i);
891 cons = agg->rx_agg_cmp_opaque;
892 __clear_bit(cons, rxr->rx_agg_bmap);
894 if (unlikely(test_bit(sw_prod, rxr->rx_agg_bmap)))
895 sw_prod = bnxt_find_next_agg_idx(rxr, sw_prod);
897 __set_bit(sw_prod, rxr->rx_agg_bmap);
898 prod_rx_buf = &rxr->rx_agg_ring[sw_prod];
899 cons_rx_buf = &rxr->rx_agg_ring[cons];
901 /* It is possible for sw_prod to be equal to cons, so
902 * set cons_rx_buf->page to NULL first.
904 page = cons_rx_buf->page;
905 cons_rx_buf->page = NULL;
906 prod_rx_buf->page = page;
907 prod_rx_buf->offset = cons_rx_buf->offset;
909 prod_rx_buf->mapping = cons_rx_buf->mapping;
911 prod_bd = &rxr->rx_agg_desc_ring[RX_RING(prod)][RX_IDX(prod)];
913 prod_bd->rx_bd_haddr = cpu_to_le64(cons_rx_buf->mapping);
914 prod_bd->rx_bd_opaque = sw_prod;
916 prod = NEXT_RX_AGG(prod);
917 sw_prod = NEXT_RX_AGG(sw_prod);
919 rxr->rx_agg_prod = prod;
920 rxr->rx_sw_agg_prod = sw_prod;
923 static struct sk_buff *bnxt_rx_page_skb(struct bnxt *bp,
924 struct bnxt_rx_ring_info *rxr,
925 u16 cons, void *data, u8 *data_ptr,
927 unsigned int offset_and_len)
929 unsigned int payload = offset_and_len >> 16;
930 unsigned int len = offset_and_len & 0xffff;
932 struct page *page = data;
933 u16 prod = rxr->rx_prod;
937 err = bnxt_alloc_rx_data(bp, rxr, prod, GFP_ATOMIC);
939 bnxt_reuse_rx_data(rxr, cons, data);
942 dma_addr -= bp->rx_dma_offset;
943 dma_unmap_page_attrs(&bp->pdev->dev, dma_addr, PAGE_SIZE, bp->rx_dir,
944 DMA_ATTR_WEAK_ORDERING);
945 page_pool_release_page(rxr->page_pool, page);
947 if (unlikely(!payload))
948 payload = eth_get_headlen(bp->dev, data_ptr, len);
950 skb = napi_alloc_skb(&rxr->bnapi->napi, payload);
956 off = (void *)data_ptr - page_address(page);
957 skb_add_rx_frag(skb, 0, page, off, len, PAGE_SIZE);
958 memcpy(skb->data - NET_IP_ALIGN, data_ptr - NET_IP_ALIGN,
959 payload + NET_IP_ALIGN);
961 frag = &skb_shinfo(skb)->frags[0];
962 skb_frag_size_sub(frag, payload);
963 skb_frag_off_add(frag, payload);
964 skb->data_len -= payload;
965 skb->tail += payload;
970 static struct sk_buff *bnxt_rx_skb(struct bnxt *bp,
971 struct bnxt_rx_ring_info *rxr, u16 cons,
972 void *data, u8 *data_ptr,
974 unsigned int offset_and_len)
976 u16 prod = rxr->rx_prod;
980 err = bnxt_alloc_rx_data(bp, rxr, prod, GFP_ATOMIC);
982 bnxt_reuse_rx_data(rxr, cons, data);
986 skb = build_skb(data, 0);
987 dma_unmap_single_attrs(&bp->pdev->dev, dma_addr, bp->rx_buf_use_size,
988 bp->rx_dir, DMA_ATTR_WEAK_ORDERING);
994 skb_reserve(skb, bp->rx_offset);
995 skb_put(skb, offset_and_len & 0xffff);
999 static struct sk_buff *bnxt_rx_pages(struct bnxt *bp,
1000 struct bnxt_cp_ring_info *cpr,
1001 struct sk_buff *skb, u16 idx,
1002 u32 agg_bufs, bool tpa)
1004 struct bnxt_napi *bnapi = cpr->bnapi;
1005 struct pci_dev *pdev = bp->pdev;
1006 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
1007 u16 prod = rxr->rx_agg_prod;
1008 bool p5_tpa = false;
1011 if ((bp->flags & BNXT_FLAG_CHIP_P5) && tpa)
1014 for (i = 0; i < agg_bufs; i++) {
1016 struct rx_agg_cmp *agg;
1017 struct bnxt_sw_rx_agg_bd *cons_rx_buf;
1022 agg = bnxt_get_tpa_agg_p5(bp, rxr, idx, i);
1024 agg = bnxt_get_agg(bp, cpr, idx, i);
1025 cons = agg->rx_agg_cmp_opaque;
1026 frag_len = (le32_to_cpu(agg->rx_agg_cmp_len_flags_type) &
1027 RX_AGG_CMP_LEN) >> RX_AGG_CMP_LEN_SHIFT;
1029 cons_rx_buf = &rxr->rx_agg_ring[cons];
1030 skb_fill_page_desc(skb, i, cons_rx_buf->page,
1031 cons_rx_buf->offset, frag_len);
1032 __clear_bit(cons, rxr->rx_agg_bmap);
1034 /* It is possible for bnxt_alloc_rx_page() to allocate
1035 * a sw_prod index that equals the cons index, so we
1036 * need to clear the cons entry now.
1038 mapping = cons_rx_buf->mapping;
1039 page = cons_rx_buf->page;
1040 cons_rx_buf->page = NULL;
1042 if (bnxt_alloc_rx_page(bp, rxr, prod, GFP_ATOMIC) != 0) {
1043 struct skb_shared_info *shinfo;
1044 unsigned int nr_frags;
1046 shinfo = skb_shinfo(skb);
1047 nr_frags = --shinfo->nr_frags;
1048 __skb_frag_set_page(&shinfo->frags[nr_frags], NULL);
1052 cons_rx_buf->page = page;
1054 /* Update prod since possibly some pages have been
1055 * allocated already.
1057 rxr->rx_agg_prod = prod;
1058 bnxt_reuse_rx_agg_bufs(cpr, idx, i, agg_bufs - i, tpa);
1062 dma_unmap_page_attrs(&pdev->dev, mapping, BNXT_RX_PAGE_SIZE,
1064 DMA_ATTR_WEAK_ORDERING);
1066 skb->data_len += frag_len;
1067 skb->len += frag_len;
1068 skb->truesize += PAGE_SIZE;
1070 prod = NEXT_RX_AGG(prod);
1072 rxr->rx_agg_prod = prod;
1076 static int bnxt_agg_bufs_valid(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1077 u8 agg_bufs, u32 *raw_cons)
1080 struct rx_agg_cmp *agg;
1082 *raw_cons = ADV_RAW_CMP(*raw_cons, agg_bufs);
1083 last = RING_CMP(*raw_cons);
1084 agg = (struct rx_agg_cmp *)
1085 &cpr->cp_desc_ring[CP_RING(last)][CP_IDX(last)];
1086 return RX_AGG_CMP_VALID(agg, *raw_cons);
1089 static inline struct sk_buff *bnxt_copy_skb(struct bnxt_napi *bnapi, u8 *data,
1093 struct bnxt *bp = bnapi->bp;
1094 struct pci_dev *pdev = bp->pdev;
1095 struct sk_buff *skb;
1097 skb = napi_alloc_skb(&bnapi->napi, len);
1101 dma_sync_single_for_cpu(&pdev->dev, mapping, bp->rx_copy_thresh,
1104 memcpy(skb->data - NET_IP_ALIGN, data - NET_IP_ALIGN,
1105 len + NET_IP_ALIGN);
1107 dma_sync_single_for_device(&pdev->dev, mapping, bp->rx_copy_thresh,
1114 static int bnxt_discard_rx(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1115 u32 *raw_cons, void *cmp)
1117 struct rx_cmp *rxcmp = cmp;
1118 u32 tmp_raw_cons = *raw_cons;
1119 u8 cmp_type, agg_bufs = 0;
1121 cmp_type = RX_CMP_TYPE(rxcmp);
1123 if (cmp_type == CMP_TYPE_RX_L2_CMP) {
1124 agg_bufs = (le32_to_cpu(rxcmp->rx_cmp_misc_v1) &
1126 RX_CMP_AGG_BUFS_SHIFT;
1127 } else if (cmp_type == CMP_TYPE_RX_L2_TPA_END_CMP) {
1128 struct rx_tpa_end_cmp *tpa_end = cmp;
1130 if (bp->flags & BNXT_FLAG_CHIP_P5)
1133 agg_bufs = TPA_END_AGG_BUFS(tpa_end);
1137 if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, &tmp_raw_cons))
1140 *raw_cons = tmp_raw_cons;
1144 static void bnxt_queue_fw_reset_work(struct bnxt *bp, unsigned long delay)
1146 if (!(test_bit(BNXT_STATE_IN_FW_RESET, &bp->state)))
1150 queue_delayed_work(bnxt_pf_wq, &bp->fw_reset_task, delay);
1152 schedule_delayed_work(&bp->fw_reset_task, delay);
1155 static void bnxt_queue_sp_work(struct bnxt *bp)
1158 queue_work(bnxt_pf_wq, &bp->sp_task);
1160 schedule_work(&bp->sp_task);
1163 static void bnxt_sched_reset(struct bnxt *bp, struct bnxt_rx_ring_info *rxr)
1165 if (!rxr->bnapi->in_reset) {
1166 rxr->bnapi->in_reset = true;
1167 if (bp->flags & BNXT_FLAG_CHIP_P5)
1168 set_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event);
1170 set_bit(BNXT_RST_RING_SP_EVENT, &bp->sp_event);
1171 bnxt_queue_sp_work(bp);
1173 rxr->rx_next_cons = 0xffff;
1176 static u16 bnxt_alloc_agg_idx(struct bnxt_rx_ring_info *rxr, u16 agg_id)
1178 struct bnxt_tpa_idx_map *map = rxr->rx_tpa_idx_map;
1179 u16 idx = agg_id & MAX_TPA_P5_MASK;
1181 if (test_bit(idx, map->agg_idx_bmap))
1182 idx = find_first_zero_bit(map->agg_idx_bmap,
1183 BNXT_AGG_IDX_BMAP_SIZE);
1184 __set_bit(idx, map->agg_idx_bmap);
1185 map->agg_id_tbl[agg_id] = idx;
1189 static void bnxt_free_agg_idx(struct bnxt_rx_ring_info *rxr, u16 idx)
1191 struct bnxt_tpa_idx_map *map = rxr->rx_tpa_idx_map;
1193 __clear_bit(idx, map->agg_idx_bmap);
1196 static u16 bnxt_lookup_agg_idx(struct bnxt_rx_ring_info *rxr, u16 agg_id)
1198 struct bnxt_tpa_idx_map *map = rxr->rx_tpa_idx_map;
1200 return map->agg_id_tbl[agg_id];
1203 static void bnxt_tpa_start(struct bnxt *bp, struct bnxt_rx_ring_info *rxr,
1204 struct rx_tpa_start_cmp *tpa_start,
1205 struct rx_tpa_start_cmp_ext *tpa_start1)
1207 struct bnxt_sw_rx_bd *cons_rx_buf, *prod_rx_buf;
1208 struct bnxt_tpa_info *tpa_info;
1209 u16 cons, prod, agg_id;
1210 struct rx_bd *prod_bd;
1213 if (bp->flags & BNXT_FLAG_CHIP_P5) {
1214 agg_id = TPA_START_AGG_ID_P5(tpa_start);
1215 agg_id = bnxt_alloc_agg_idx(rxr, agg_id);
1217 agg_id = TPA_START_AGG_ID(tpa_start);
1219 cons = tpa_start->rx_tpa_start_cmp_opaque;
1220 prod = rxr->rx_prod;
1221 cons_rx_buf = &rxr->rx_buf_ring[cons];
1222 prod_rx_buf = &rxr->rx_buf_ring[prod];
1223 tpa_info = &rxr->rx_tpa[agg_id];
1225 if (unlikely(cons != rxr->rx_next_cons ||
1226 TPA_START_ERROR(tpa_start))) {
1227 netdev_warn(bp->dev, "TPA cons %x, expected cons %x, error code %x\n",
1228 cons, rxr->rx_next_cons,
1229 TPA_START_ERROR_CODE(tpa_start1));
1230 bnxt_sched_reset(bp, rxr);
1233 /* Store cfa_code in tpa_info to use in tpa_end
1234 * completion processing.
1236 tpa_info->cfa_code = TPA_START_CFA_CODE(tpa_start1);
1237 prod_rx_buf->data = tpa_info->data;
1238 prod_rx_buf->data_ptr = tpa_info->data_ptr;
1240 mapping = tpa_info->mapping;
1241 prod_rx_buf->mapping = mapping;
1243 prod_bd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
1245 prod_bd->rx_bd_haddr = cpu_to_le64(mapping);
1247 tpa_info->data = cons_rx_buf->data;
1248 tpa_info->data_ptr = cons_rx_buf->data_ptr;
1249 cons_rx_buf->data = NULL;
1250 tpa_info->mapping = cons_rx_buf->mapping;
1253 le32_to_cpu(tpa_start->rx_tpa_start_cmp_len_flags_type) >>
1254 RX_TPA_START_CMP_LEN_SHIFT;
1255 if (likely(TPA_START_HASH_VALID(tpa_start))) {
1256 u32 hash_type = TPA_START_HASH_TYPE(tpa_start);
1258 tpa_info->hash_type = PKT_HASH_TYPE_L4;
1259 tpa_info->gso_type = SKB_GSO_TCPV4;
1260 /* RSS profiles 1 and 3 with extract code 0 for inner 4-tuple */
1261 if (hash_type == 3 || TPA_START_IS_IPV6(tpa_start1))
1262 tpa_info->gso_type = SKB_GSO_TCPV6;
1263 tpa_info->rss_hash =
1264 le32_to_cpu(tpa_start->rx_tpa_start_cmp_rss_hash);
1266 tpa_info->hash_type = PKT_HASH_TYPE_NONE;
1267 tpa_info->gso_type = 0;
1268 if (netif_msg_rx_err(bp))
1269 netdev_warn(bp->dev, "TPA packet without valid hash\n");
1271 tpa_info->flags2 = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_flags2);
1272 tpa_info->metadata = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_metadata);
1273 tpa_info->hdr_info = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_hdr_info);
1274 tpa_info->agg_count = 0;
1276 rxr->rx_prod = NEXT_RX(prod);
1277 cons = NEXT_RX(cons);
1278 rxr->rx_next_cons = NEXT_RX(cons);
1279 cons_rx_buf = &rxr->rx_buf_ring[cons];
1281 bnxt_reuse_rx_data(rxr, cons, cons_rx_buf->data);
1282 rxr->rx_prod = NEXT_RX(rxr->rx_prod);
1283 cons_rx_buf->data = NULL;
1286 static void bnxt_abort_tpa(struct bnxt_cp_ring_info *cpr, u16 idx, u32 agg_bufs)
1289 bnxt_reuse_rx_agg_bufs(cpr, idx, 0, agg_bufs, true);
1293 static void bnxt_gro_tunnel(struct sk_buff *skb, __be16 ip_proto)
1295 struct udphdr *uh = NULL;
1297 if (ip_proto == htons(ETH_P_IP)) {
1298 struct iphdr *iph = (struct iphdr *)skb->data;
1300 if (iph->protocol == IPPROTO_UDP)
1301 uh = (struct udphdr *)(iph + 1);
1303 struct ipv6hdr *iph = (struct ipv6hdr *)skb->data;
1305 if (iph->nexthdr == IPPROTO_UDP)
1306 uh = (struct udphdr *)(iph + 1);
1310 skb_shinfo(skb)->gso_type |= SKB_GSO_UDP_TUNNEL_CSUM;
1312 skb_shinfo(skb)->gso_type |= SKB_GSO_UDP_TUNNEL;
1317 static struct sk_buff *bnxt_gro_func_5731x(struct bnxt_tpa_info *tpa_info,
1318 int payload_off, int tcp_ts,
1319 struct sk_buff *skb)
1324 u16 outer_ip_off, inner_ip_off, inner_mac_off;
1325 u32 hdr_info = tpa_info->hdr_info;
1326 bool loopback = false;
1328 inner_ip_off = BNXT_TPA_INNER_L3_OFF(hdr_info);
1329 inner_mac_off = BNXT_TPA_INNER_L2_OFF(hdr_info);
1330 outer_ip_off = BNXT_TPA_OUTER_L3_OFF(hdr_info);
1332 /* If the packet is an internal loopback packet, the offsets will
1333 * have an extra 4 bytes.
1335 if (inner_mac_off == 4) {
1337 } else if (inner_mac_off > 4) {
1338 __be16 proto = *((__be16 *)(skb->data + inner_ip_off -
1341 /* We only support inner iPv4/ipv6. If we don't see the
1342 * correct protocol ID, it must be a loopback packet where
1343 * the offsets are off by 4.
1345 if (proto != htons(ETH_P_IP) && proto != htons(ETH_P_IPV6))
1349 /* internal loopback packet, subtract all offsets by 4 */
1355 nw_off = inner_ip_off - ETH_HLEN;
1356 skb_set_network_header(skb, nw_off);
1357 if (tpa_info->flags2 & RX_TPA_START_CMP_FLAGS2_IP_TYPE) {
1358 struct ipv6hdr *iph = ipv6_hdr(skb);
1360 skb_set_transport_header(skb, nw_off + sizeof(struct ipv6hdr));
1361 len = skb->len - skb_transport_offset(skb);
1363 th->check = ~tcp_v6_check(len, &iph->saddr, &iph->daddr, 0);
1365 struct iphdr *iph = ip_hdr(skb);
1367 skb_set_transport_header(skb, nw_off + sizeof(struct iphdr));
1368 len = skb->len - skb_transport_offset(skb);
1370 th->check = ~tcp_v4_check(len, iph->saddr, iph->daddr, 0);
1373 if (inner_mac_off) { /* tunnel */
1374 __be16 proto = *((__be16 *)(skb->data + outer_ip_off -
1377 bnxt_gro_tunnel(skb, proto);
1383 static struct sk_buff *bnxt_gro_func_5750x(struct bnxt_tpa_info *tpa_info,
1384 int payload_off, int tcp_ts,
1385 struct sk_buff *skb)
1388 u16 outer_ip_off, inner_ip_off, inner_mac_off;
1389 u32 hdr_info = tpa_info->hdr_info;
1390 int iphdr_len, nw_off;
1392 inner_ip_off = BNXT_TPA_INNER_L3_OFF(hdr_info);
1393 inner_mac_off = BNXT_TPA_INNER_L2_OFF(hdr_info);
1394 outer_ip_off = BNXT_TPA_OUTER_L3_OFF(hdr_info);
1396 nw_off = inner_ip_off - ETH_HLEN;
1397 skb_set_network_header(skb, nw_off);
1398 iphdr_len = (tpa_info->flags2 & RX_TPA_START_CMP_FLAGS2_IP_TYPE) ?
1399 sizeof(struct ipv6hdr) : sizeof(struct iphdr);
1400 skb_set_transport_header(skb, nw_off + iphdr_len);
1402 if (inner_mac_off) { /* tunnel */
1403 __be16 proto = *((__be16 *)(skb->data + outer_ip_off -
1406 bnxt_gro_tunnel(skb, proto);
1412 #define BNXT_IPV4_HDR_SIZE (sizeof(struct iphdr) + sizeof(struct tcphdr))
1413 #define BNXT_IPV6_HDR_SIZE (sizeof(struct ipv6hdr) + sizeof(struct tcphdr))
1415 static struct sk_buff *bnxt_gro_func_5730x(struct bnxt_tpa_info *tpa_info,
1416 int payload_off, int tcp_ts,
1417 struct sk_buff *skb)
1421 int len, nw_off, tcp_opt_len = 0;
1426 if (tpa_info->gso_type == SKB_GSO_TCPV4) {
1429 nw_off = payload_off - BNXT_IPV4_HDR_SIZE - tcp_opt_len -
1431 skb_set_network_header(skb, nw_off);
1433 skb_set_transport_header(skb, nw_off + sizeof(struct iphdr));
1434 len = skb->len - skb_transport_offset(skb);
1436 th->check = ~tcp_v4_check(len, iph->saddr, iph->daddr, 0);
1437 } else if (tpa_info->gso_type == SKB_GSO_TCPV6) {
1438 struct ipv6hdr *iph;
1440 nw_off = payload_off - BNXT_IPV6_HDR_SIZE - tcp_opt_len -
1442 skb_set_network_header(skb, nw_off);
1443 iph = ipv6_hdr(skb);
1444 skb_set_transport_header(skb, nw_off + sizeof(struct ipv6hdr));
1445 len = skb->len - skb_transport_offset(skb);
1447 th->check = ~tcp_v6_check(len, &iph->saddr, &iph->daddr, 0);
1449 dev_kfree_skb_any(skb);
1453 if (nw_off) /* tunnel */
1454 bnxt_gro_tunnel(skb, skb->protocol);
1459 static inline struct sk_buff *bnxt_gro_skb(struct bnxt *bp,
1460 struct bnxt_tpa_info *tpa_info,
1461 struct rx_tpa_end_cmp *tpa_end,
1462 struct rx_tpa_end_cmp_ext *tpa_end1,
1463 struct sk_buff *skb)
1469 segs = TPA_END_TPA_SEGS(tpa_end);
1473 NAPI_GRO_CB(skb)->count = segs;
1474 skb_shinfo(skb)->gso_size =
1475 le32_to_cpu(tpa_end1->rx_tpa_end_cmp_seg_len);
1476 skb_shinfo(skb)->gso_type = tpa_info->gso_type;
1477 if (bp->flags & BNXT_FLAG_CHIP_P5)
1478 payload_off = TPA_END_PAYLOAD_OFF_P5(tpa_end1);
1480 payload_off = TPA_END_PAYLOAD_OFF(tpa_end);
1481 skb = bp->gro_func(tpa_info, payload_off, TPA_END_GRO_TS(tpa_end), skb);
1483 tcp_gro_complete(skb);
1488 /* Given the cfa_code of a received packet determine which
1489 * netdev (vf-rep or PF) the packet is destined to.
1491 static struct net_device *bnxt_get_pkt_dev(struct bnxt *bp, u16 cfa_code)
1493 struct net_device *dev = bnxt_get_vf_rep(bp, cfa_code);
1495 /* if vf-rep dev is NULL, the must belongs to the PF */
1496 return dev ? dev : bp->dev;
1499 static inline struct sk_buff *bnxt_tpa_end(struct bnxt *bp,
1500 struct bnxt_cp_ring_info *cpr,
1502 struct rx_tpa_end_cmp *tpa_end,
1503 struct rx_tpa_end_cmp_ext *tpa_end1,
1506 struct bnxt_napi *bnapi = cpr->bnapi;
1507 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
1508 u8 *data_ptr, agg_bufs;
1510 struct bnxt_tpa_info *tpa_info;
1512 struct sk_buff *skb;
1513 u16 idx = 0, agg_id;
1517 if (unlikely(bnapi->in_reset)) {
1518 int rc = bnxt_discard_rx(bp, cpr, raw_cons, tpa_end);
1521 return ERR_PTR(-EBUSY);
1525 if (bp->flags & BNXT_FLAG_CHIP_P5) {
1526 agg_id = TPA_END_AGG_ID_P5(tpa_end);
1527 agg_id = bnxt_lookup_agg_idx(rxr, agg_id);
1528 agg_bufs = TPA_END_AGG_BUFS_P5(tpa_end1);
1529 tpa_info = &rxr->rx_tpa[agg_id];
1530 if (unlikely(agg_bufs != tpa_info->agg_count)) {
1531 netdev_warn(bp->dev, "TPA end agg_buf %d != expected agg_bufs %d\n",
1532 agg_bufs, tpa_info->agg_count);
1533 agg_bufs = tpa_info->agg_count;
1535 tpa_info->agg_count = 0;
1536 *event |= BNXT_AGG_EVENT;
1537 bnxt_free_agg_idx(rxr, agg_id);
1539 gro = !!(bp->flags & BNXT_FLAG_GRO);
1541 agg_id = TPA_END_AGG_ID(tpa_end);
1542 agg_bufs = TPA_END_AGG_BUFS(tpa_end);
1543 tpa_info = &rxr->rx_tpa[agg_id];
1544 idx = RING_CMP(*raw_cons);
1546 if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, raw_cons))
1547 return ERR_PTR(-EBUSY);
1549 *event |= BNXT_AGG_EVENT;
1550 idx = NEXT_CMP(idx);
1552 gro = !!TPA_END_GRO(tpa_end);
1554 data = tpa_info->data;
1555 data_ptr = tpa_info->data_ptr;
1557 len = tpa_info->len;
1558 mapping = tpa_info->mapping;
1560 if (unlikely(agg_bufs > MAX_SKB_FRAGS || TPA_END_ERRORS(tpa_end1))) {
1561 bnxt_abort_tpa(cpr, idx, agg_bufs);
1562 if (agg_bufs > MAX_SKB_FRAGS)
1563 netdev_warn(bp->dev, "TPA frags %d exceeded MAX_SKB_FRAGS %d\n",
1564 agg_bufs, (int)MAX_SKB_FRAGS);
1568 if (len <= bp->rx_copy_thresh) {
1569 skb = bnxt_copy_skb(bnapi, data_ptr, len, mapping);
1571 bnxt_abort_tpa(cpr, idx, agg_bufs);
1576 dma_addr_t new_mapping;
1578 new_data = __bnxt_alloc_rx_data(bp, &new_mapping, GFP_ATOMIC);
1580 bnxt_abort_tpa(cpr, idx, agg_bufs);
1584 tpa_info->data = new_data;
1585 tpa_info->data_ptr = new_data + bp->rx_offset;
1586 tpa_info->mapping = new_mapping;
1588 skb = build_skb(data, 0);
1589 dma_unmap_single_attrs(&bp->pdev->dev, mapping,
1590 bp->rx_buf_use_size, bp->rx_dir,
1591 DMA_ATTR_WEAK_ORDERING);
1595 bnxt_abort_tpa(cpr, idx, agg_bufs);
1598 skb_reserve(skb, bp->rx_offset);
1603 skb = bnxt_rx_pages(bp, cpr, skb, idx, agg_bufs, true);
1605 /* Page reuse already handled by bnxt_rx_pages(). */
1611 eth_type_trans(skb, bnxt_get_pkt_dev(bp, tpa_info->cfa_code));
1613 if (tpa_info->hash_type != PKT_HASH_TYPE_NONE)
1614 skb_set_hash(skb, tpa_info->rss_hash, tpa_info->hash_type);
1616 if ((tpa_info->flags2 & RX_CMP_FLAGS2_META_FORMAT_VLAN) &&
1617 (skb->dev->features & BNXT_HW_FEATURE_VLAN_ALL_RX)) {
1618 u16 vlan_proto = tpa_info->metadata >>
1619 RX_CMP_FLAGS2_METADATA_TPID_SFT;
1620 u16 vtag = tpa_info->metadata & RX_CMP_FLAGS2_METADATA_TCI_MASK;
1622 __vlan_hwaccel_put_tag(skb, htons(vlan_proto), vtag);
1625 skb_checksum_none_assert(skb);
1626 if (likely(tpa_info->flags2 & RX_TPA_START_CMP_FLAGS2_L4_CS_CALC)) {
1627 skb->ip_summed = CHECKSUM_UNNECESSARY;
1629 (tpa_info->flags2 & RX_CMP_FLAGS2_T_L4_CS_CALC) >> 3;
1633 skb = bnxt_gro_skb(bp, tpa_info, tpa_end, tpa_end1, skb);
1638 static void bnxt_tpa_agg(struct bnxt *bp, struct bnxt_rx_ring_info *rxr,
1639 struct rx_agg_cmp *rx_agg)
1641 u16 agg_id = TPA_AGG_AGG_ID(rx_agg);
1642 struct bnxt_tpa_info *tpa_info;
1644 agg_id = bnxt_lookup_agg_idx(rxr, agg_id);
1645 tpa_info = &rxr->rx_tpa[agg_id];
1646 BUG_ON(tpa_info->agg_count >= MAX_SKB_FRAGS);
1647 tpa_info->agg_arr[tpa_info->agg_count++] = *rx_agg;
1650 static void bnxt_deliver_skb(struct bnxt *bp, struct bnxt_napi *bnapi,
1651 struct sk_buff *skb)
1653 if (skb->dev != bp->dev) {
1654 /* this packet belongs to a vf-rep */
1655 bnxt_vf_rep_rx(bp, skb);
1658 skb_record_rx_queue(skb, bnapi->index);
1659 napi_gro_receive(&bnapi->napi, skb);
1662 /* returns the following:
1663 * 1 - 1 packet successfully received
1664 * 0 - successful TPA_START, packet not completed yet
1665 * -EBUSY - completion ring does not have all the agg buffers yet
1666 * -ENOMEM - packet aborted due to out of memory
1667 * -EIO - packet aborted due to hw error indicated in BD
1669 static int bnxt_rx_pkt(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1670 u32 *raw_cons, u8 *event)
1672 struct bnxt_napi *bnapi = cpr->bnapi;
1673 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
1674 struct net_device *dev = bp->dev;
1675 struct rx_cmp *rxcmp;
1676 struct rx_cmp_ext *rxcmp1;
1677 u32 tmp_raw_cons = *raw_cons;
1678 u16 cfa_code, cons, prod, cp_cons = RING_CMP(tmp_raw_cons);
1679 struct bnxt_sw_rx_bd *rx_buf;
1681 u8 *data_ptr, agg_bufs, cmp_type;
1682 dma_addr_t dma_addr;
1683 struct sk_buff *skb;
1688 rxcmp = (struct rx_cmp *)
1689 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1691 cmp_type = RX_CMP_TYPE(rxcmp);
1693 if (cmp_type == CMP_TYPE_RX_TPA_AGG_CMP) {
1694 bnxt_tpa_agg(bp, rxr, (struct rx_agg_cmp *)rxcmp);
1695 goto next_rx_no_prod_no_len;
1698 tmp_raw_cons = NEXT_RAW_CMP(tmp_raw_cons);
1699 cp_cons = RING_CMP(tmp_raw_cons);
1700 rxcmp1 = (struct rx_cmp_ext *)
1701 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1703 if (!RX_CMP_VALID(rxcmp1, tmp_raw_cons))
1706 prod = rxr->rx_prod;
1708 if (cmp_type == CMP_TYPE_RX_L2_TPA_START_CMP) {
1709 bnxt_tpa_start(bp, rxr, (struct rx_tpa_start_cmp *)rxcmp,
1710 (struct rx_tpa_start_cmp_ext *)rxcmp1);
1712 *event |= BNXT_RX_EVENT;
1713 goto next_rx_no_prod_no_len;
1715 } else if (cmp_type == CMP_TYPE_RX_L2_TPA_END_CMP) {
1716 skb = bnxt_tpa_end(bp, cpr, &tmp_raw_cons,
1717 (struct rx_tpa_end_cmp *)rxcmp,
1718 (struct rx_tpa_end_cmp_ext *)rxcmp1, event);
1725 bnxt_deliver_skb(bp, bnapi, skb);
1728 *event |= BNXT_RX_EVENT;
1729 goto next_rx_no_prod_no_len;
1732 cons = rxcmp->rx_cmp_opaque;
1733 if (unlikely(cons != rxr->rx_next_cons)) {
1734 int rc1 = bnxt_discard_rx(bp, cpr, raw_cons, rxcmp);
1736 /* 0xffff is forced error, don't print it */
1737 if (rxr->rx_next_cons != 0xffff)
1738 netdev_warn(bp->dev, "RX cons %x != expected cons %x\n",
1739 cons, rxr->rx_next_cons);
1740 bnxt_sched_reset(bp, rxr);
1743 rx_buf = &rxr->rx_buf_ring[cons];
1744 data = rx_buf->data;
1745 data_ptr = rx_buf->data_ptr;
1748 misc = le32_to_cpu(rxcmp->rx_cmp_misc_v1);
1749 agg_bufs = (misc & RX_CMP_AGG_BUFS) >> RX_CMP_AGG_BUFS_SHIFT;
1752 if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, &tmp_raw_cons))
1755 cp_cons = NEXT_CMP(cp_cons);
1756 *event |= BNXT_AGG_EVENT;
1758 *event |= BNXT_RX_EVENT;
1760 rx_buf->data = NULL;
1761 if (rxcmp1->rx_cmp_cfa_code_errors_v2 & RX_CMP_L2_ERRORS) {
1762 u32 rx_err = le32_to_cpu(rxcmp1->rx_cmp_cfa_code_errors_v2);
1764 bnxt_reuse_rx_data(rxr, cons, data);
1766 bnxt_reuse_rx_agg_bufs(cpr, cp_cons, 0, agg_bufs,
1770 if (rx_err & RX_CMPL_ERRORS_BUFFER_ERROR_MASK) {
1771 bnapi->cp_ring.sw_stats.rx.rx_buf_errors++;
1772 if (!(bp->flags & BNXT_FLAG_CHIP_P5) &&
1773 !(bp->fw_cap & BNXT_FW_CAP_RING_MONITOR)) {
1774 netdev_warn_once(bp->dev, "RX buffer error %x\n",
1776 bnxt_sched_reset(bp, rxr);
1779 goto next_rx_no_len;
1782 len = le32_to_cpu(rxcmp->rx_cmp_len_flags_type) >> RX_CMP_LEN_SHIFT;
1783 dma_addr = rx_buf->mapping;
1785 if (bnxt_rx_xdp(bp, rxr, cons, data, &data_ptr, &len, event)) {
1790 if (len <= bp->rx_copy_thresh) {
1791 skb = bnxt_copy_skb(bnapi, data_ptr, len, dma_addr);
1792 bnxt_reuse_rx_data(rxr, cons, data);
1795 bnxt_reuse_rx_agg_bufs(cpr, cp_cons, 0,
1803 if (rx_buf->data_ptr == data_ptr)
1804 payload = misc & RX_CMP_PAYLOAD_OFFSET;
1807 skb = bp->rx_skb_func(bp, rxr, cons, data, data_ptr, dma_addr,
1816 skb = bnxt_rx_pages(bp, cpr, skb, cp_cons, agg_bufs, false);
1823 if (RX_CMP_HASH_VALID(rxcmp)) {
1824 u32 hash_type = RX_CMP_HASH_TYPE(rxcmp);
1825 enum pkt_hash_types type = PKT_HASH_TYPE_L4;
1827 /* RSS profiles 1 and 3 with extract code 0 for inner 4-tuple */
1828 if (hash_type != 1 && hash_type != 3)
1829 type = PKT_HASH_TYPE_L3;
1830 skb_set_hash(skb, le32_to_cpu(rxcmp->rx_cmp_rss_hash), type);
1833 cfa_code = RX_CMP_CFA_CODE(rxcmp1);
1834 skb->protocol = eth_type_trans(skb, bnxt_get_pkt_dev(bp, cfa_code));
1836 if ((rxcmp1->rx_cmp_flags2 &
1837 cpu_to_le32(RX_CMP_FLAGS2_META_FORMAT_VLAN)) &&
1838 (skb->dev->features & BNXT_HW_FEATURE_VLAN_ALL_RX)) {
1839 u32 meta_data = le32_to_cpu(rxcmp1->rx_cmp_meta_data);
1840 u16 vtag = meta_data & RX_CMP_FLAGS2_METADATA_TCI_MASK;
1841 u16 vlan_proto = meta_data >> RX_CMP_FLAGS2_METADATA_TPID_SFT;
1843 __vlan_hwaccel_put_tag(skb, htons(vlan_proto), vtag);
1846 skb_checksum_none_assert(skb);
1847 if (RX_CMP_L4_CS_OK(rxcmp1)) {
1848 if (dev->features & NETIF_F_RXCSUM) {
1849 skb->ip_summed = CHECKSUM_UNNECESSARY;
1850 skb->csum_level = RX_CMP_ENCAP(rxcmp1);
1853 if (rxcmp1->rx_cmp_cfa_code_errors_v2 & RX_CMP_L4_CS_ERR_BITS) {
1854 if (dev->features & NETIF_F_RXCSUM)
1855 bnapi->cp_ring.sw_stats.rx.rx_l4_csum_errors++;
1859 bnxt_deliver_skb(bp, bnapi, skb);
1863 cpr->rx_packets += 1;
1864 cpr->rx_bytes += len;
1867 rxr->rx_prod = NEXT_RX(prod);
1868 rxr->rx_next_cons = NEXT_RX(cons);
1870 next_rx_no_prod_no_len:
1871 *raw_cons = tmp_raw_cons;
1876 /* In netpoll mode, if we are using a combined completion ring, we need to
1877 * discard the rx packets and recycle the buffers.
1879 static int bnxt_force_rx_discard(struct bnxt *bp,
1880 struct bnxt_cp_ring_info *cpr,
1881 u32 *raw_cons, u8 *event)
1883 u32 tmp_raw_cons = *raw_cons;
1884 struct rx_cmp_ext *rxcmp1;
1885 struct rx_cmp *rxcmp;
1889 cp_cons = RING_CMP(tmp_raw_cons);
1890 rxcmp = (struct rx_cmp *)
1891 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1893 tmp_raw_cons = NEXT_RAW_CMP(tmp_raw_cons);
1894 cp_cons = RING_CMP(tmp_raw_cons);
1895 rxcmp1 = (struct rx_cmp_ext *)
1896 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1898 if (!RX_CMP_VALID(rxcmp1, tmp_raw_cons))
1901 cmp_type = RX_CMP_TYPE(rxcmp);
1902 if (cmp_type == CMP_TYPE_RX_L2_CMP) {
1903 rxcmp1->rx_cmp_cfa_code_errors_v2 |=
1904 cpu_to_le32(RX_CMPL_ERRORS_CRC_ERROR);
1905 } else if (cmp_type == CMP_TYPE_RX_L2_TPA_END_CMP) {
1906 struct rx_tpa_end_cmp_ext *tpa_end1;
1908 tpa_end1 = (struct rx_tpa_end_cmp_ext *)rxcmp1;
1909 tpa_end1->rx_tpa_end_cmp_errors_v2 |=
1910 cpu_to_le32(RX_TPA_END_CMP_ERRORS);
1912 return bnxt_rx_pkt(bp, cpr, raw_cons, event);
1915 u32 bnxt_fw_health_readl(struct bnxt *bp, int reg_idx)
1917 struct bnxt_fw_health *fw_health = bp->fw_health;
1918 u32 reg = fw_health->regs[reg_idx];
1919 u32 reg_type, reg_off, val = 0;
1921 reg_type = BNXT_FW_HEALTH_REG_TYPE(reg);
1922 reg_off = BNXT_FW_HEALTH_REG_OFF(reg);
1924 case BNXT_FW_HEALTH_REG_TYPE_CFG:
1925 pci_read_config_dword(bp->pdev, reg_off, &val);
1927 case BNXT_FW_HEALTH_REG_TYPE_GRC:
1928 reg_off = fw_health->mapped_regs[reg_idx];
1930 case BNXT_FW_HEALTH_REG_TYPE_BAR0:
1931 val = readl(bp->bar0 + reg_off);
1933 case BNXT_FW_HEALTH_REG_TYPE_BAR1:
1934 val = readl(bp->bar1 + reg_off);
1937 if (reg_idx == BNXT_FW_RESET_INPROG_REG)
1938 val &= fw_health->fw_reset_inprog_reg_mask;
1942 static u16 bnxt_agg_ring_id_to_grp_idx(struct bnxt *bp, u16 ring_id)
1946 for (i = 0; i < bp->rx_nr_rings; i++) {
1947 u16 grp_idx = bp->rx_ring[i].bnapi->index;
1948 struct bnxt_ring_grp_info *grp_info;
1950 grp_info = &bp->grp_info[grp_idx];
1951 if (grp_info->agg_fw_ring_id == ring_id)
1954 return INVALID_HW_RING_ID;
1957 #define BNXT_GET_EVENT_PORT(data) \
1959 ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK)
1961 #define BNXT_EVENT_RING_TYPE(data2) \
1963 ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_MASK)
1965 #define BNXT_EVENT_RING_TYPE_RX(data2) \
1966 (BNXT_EVENT_RING_TYPE(data2) == \
1967 ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_RX)
1969 static int bnxt_async_event_process(struct bnxt *bp,
1970 struct hwrm_async_event_cmpl *cmpl)
1972 u16 event_id = le16_to_cpu(cmpl->event_id);
1973 u32 data1 = le32_to_cpu(cmpl->event_data1);
1974 u32 data2 = le32_to_cpu(cmpl->event_data2);
1976 /* TODO CHIMP_FW: Define event id's for link change, error etc */
1978 case ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE: {
1979 struct bnxt_link_info *link_info = &bp->link_info;
1982 goto async_event_process_exit;
1984 /* print unsupported speed warning in forced speed mode only */
1985 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED) &&
1986 (data1 & 0x20000)) {
1987 u16 fw_speed = link_info->force_link_speed;
1988 u32 speed = bnxt_fw_to_ethtool_speed(fw_speed);
1990 if (speed != SPEED_UNKNOWN)
1991 netdev_warn(bp->dev, "Link speed %d no longer supported\n",
1994 set_bit(BNXT_LINK_SPEED_CHNG_SP_EVENT, &bp->sp_event);
1997 case ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CHANGE:
1998 case ASYNC_EVENT_CMPL_EVENT_ID_PORT_PHY_CFG_CHANGE:
1999 set_bit(BNXT_LINK_CFG_CHANGE_SP_EVENT, &bp->sp_event);
2001 case ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE:
2002 set_bit(BNXT_LINK_CHNG_SP_EVENT, &bp->sp_event);
2004 case ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD:
2005 set_bit(BNXT_HWRM_PF_UNLOAD_SP_EVENT, &bp->sp_event);
2007 case ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED: {
2008 u16 port_id = BNXT_GET_EVENT_PORT(data1);
2013 if (bp->pf.port_id != port_id)
2016 set_bit(BNXT_HWRM_PORT_MODULE_SP_EVENT, &bp->sp_event);
2019 case ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE:
2021 goto async_event_process_exit;
2022 set_bit(BNXT_RESET_TASK_SILENT_SP_EVENT, &bp->sp_event);
2024 case ASYNC_EVENT_CMPL_EVENT_ID_RESET_NOTIFY:
2025 if (netif_msg_hw(bp))
2026 netdev_warn(bp->dev, "Received RESET_NOTIFY event, data1: 0x%x, data2: 0x%x\n",
2029 goto async_event_process_exit;
2031 bp->fw_reset_timestamp = jiffies;
2032 bp->fw_reset_min_dsecs = cmpl->timestamp_lo;
2033 if (!bp->fw_reset_min_dsecs)
2034 bp->fw_reset_min_dsecs = BNXT_DFLT_FW_RST_MIN_DSECS;
2035 bp->fw_reset_max_dsecs = le16_to_cpu(cmpl->timestamp_hi);
2036 if (!bp->fw_reset_max_dsecs)
2037 bp->fw_reset_max_dsecs = BNXT_DFLT_FW_RST_MAX_DSECS;
2038 if (EVENT_DATA1_RESET_NOTIFY_FATAL(data1)) {
2039 netdev_warn(bp->dev, "Firmware fatal reset event received\n");
2040 set_bit(BNXT_STATE_FW_FATAL_COND, &bp->state);
2042 netdev_warn(bp->dev, "Firmware non-fatal reset event received, max wait time %d msec\n",
2043 bp->fw_reset_max_dsecs * 100);
2045 set_bit(BNXT_FW_RESET_NOTIFY_SP_EVENT, &bp->sp_event);
2047 case ASYNC_EVENT_CMPL_EVENT_ID_ERROR_RECOVERY: {
2048 struct bnxt_fw_health *fw_health = bp->fw_health;
2051 goto async_event_process_exit;
2053 fw_health->enabled = EVENT_DATA1_RECOVERY_ENABLED(data1);
2054 fw_health->master = EVENT_DATA1_RECOVERY_MASTER_FUNC(data1);
2055 if (!fw_health->enabled)
2058 if (netif_msg_drv(bp))
2059 netdev_info(bp->dev, "Error recovery info: error recovery[%d], master[%d], reset count[0x%x], health status: 0x%x\n",
2060 fw_health->enabled, fw_health->master,
2061 bnxt_fw_health_readl(bp,
2062 BNXT_FW_RESET_CNT_REG),
2063 bnxt_fw_health_readl(bp,
2064 BNXT_FW_HEALTH_REG));
2065 fw_health->tmr_multiplier =
2066 DIV_ROUND_UP(fw_health->polling_dsecs * HZ,
2067 bp->current_interval * 10);
2068 fw_health->tmr_counter = fw_health->tmr_multiplier;
2069 fw_health->last_fw_heartbeat =
2070 bnxt_fw_health_readl(bp, BNXT_FW_HEARTBEAT_REG);
2071 fw_health->last_fw_reset_cnt =
2072 bnxt_fw_health_readl(bp, BNXT_FW_RESET_CNT_REG);
2073 goto async_event_process_exit;
2075 case ASYNC_EVENT_CMPL_EVENT_ID_RING_MONITOR_MSG: {
2076 struct bnxt_rx_ring_info *rxr;
2079 if (bp->flags & BNXT_FLAG_CHIP_P5)
2080 goto async_event_process_exit;
2082 netdev_warn(bp->dev, "Ring monitor event, ring type %lu id 0x%x\n",
2083 BNXT_EVENT_RING_TYPE(data2), data1);
2084 if (!BNXT_EVENT_RING_TYPE_RX(data2))
2085 goto async_event_process_exit;
2087 grp_idx = bnxt_agg_ring_id_to_grp_idx(bp, data1);
2088 if (grp_idx == INVALID_HW_RING_ID) {
2089 netdev_warn(bp->dev, "Unknown RX agg ring id 0x%x\n",
2091 goto async_event_process_exit;
2093 rxr = bp->bnapi[grp_idx]->rx_ring;
2094 bnxt_sched_reset(bp, rxr);
2095 goto async_event_process_exit;
2098 goto async_event_process_exit;
2100 bnxt_queue_sp_work(bp);
2101 async_event_process_exit:
2102 bnxt_ulp_async_events(bp, cmpl);
2106 static int bnxt_hwrm_handler(struct bnxt *bp, struct tx_cmp *txcmp)
2108 u16 cmpl_type = TX_CMP_TYPE(txcmp), vf_id, seq_id;
2109 struct hwrm_cmpl *h_cmpl = (struct hwrm_cmpl *)txcmp;
2110 struct hwrm_fwd_req_cmpl *fwd_req_cmpl =
2111 (struct hwrm_fwd_req_cmpl *)txcmp;
2113 switch (cmpl_type) {
2114 case CMPL_BASE_TYPE_HWRM_DONE:
2115 seq_id = le16_to_cpu(h_cmpl->sequence_id);
2116 if (seq_id == bp->hwrm_intr_seq_id)
2117 bp->hwrm_intr_seq_id = (u16)~bp->hwrm_intr_seq_id;
2119 netdev_err(bp->dev, "Invalid hwrm seq id %d\n", seq_id);
2122 case CMPL_BASE_TYPE_HWRM_FWD_REQ:
2123 vf_id = le16_to_cpu(fwd_req_cmpl->source_id);
2125 if ((vf_id < bp->pf.first_vf_id) ||
2126 (vf_id >= bp->pf.first_vf_id + bp->pf.active_vfs)) {
2127 netdev_err(bp->dev, "Msg contains invalid VF id %x\n",
2132 set_bit(vf_id - bp->pf.first_vf_id, bp->pf.vf_event_bmap);
2133 set_bit(BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT, &bp->sp_event);
2134 bnxt_queue_sp_work(bp);
2137 case CMPL_BASE_TYPE_HWRM_ASYNC_EVENT:
2138 bnxt_async_event_process(bp,
2139 (struct hwrm_async_event_cmpl *)txcmp);
2148 static irqreturn_t bnxt_msix(int irq, void *dev_instance)
2150 struct bnxt_napi *bnapi = dev_instance;
2151 struct bnxt *bp = bnapi->bp;
2152 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
2153 u32 cons = RING_CMP(cpr->cp_raw_cons);
2156 prefetch(&cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]);
2157 napi_schedule(&bnapi->napi);
2161 static inline int bnxt_has_work(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2163 u32 raw_cons = cpr->cp_raw_cons;
2164 u16 cons = RING_CMP(raw_cons);
2165 struct tx_cmp *txcmp;
2167 txcmp = &cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)];
2169 return TX_CMP_VALID(txcmp, raw_cons);
2172 static irqreturn_t bnxt_inta(int irq, void *dev_instance)
2174 struct bnxt_napi *bnapi = dev_instance;
2175 struct bnxt *bp = bnapi->bp;
2176 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
2177 u32 cons = RING_CMP(cpr->cp_raw_cons);
2180 prefetch(&cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]);
2182 if (!bnxt_has_work(bp, cpr)) {
2183 int_status = readl(bp->bar0 + BNXT_CAG_REG_LEGACY_INT_STATUS);
2184 /* return if erroneous interrupt */
2185 if (!(int_status & (0x10000 << cpr->cp_ring_struct.fw_ring_id)))
2189 /* disable ring IRQ */
2190 BNXT_CP_DB_IRQ_DIS(cpr->cp_db.doorbell);
2192 /* Return here if interrupt is shared and is disabled. */
2193 if (unlikely(atomic_read(&bp->intr_sem) != 0))
2196 napi_schedule(&bnapi->napi);
2200 static int __bnxt_poll_work(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
2203 struct bnxt_napi *bnapi = cpr->bnapi;
2204 u32 raw_cons = cpr->cp_raw_cons;
2209 struct tx_cmp *txcmp;
2211 cpr->has_more_work = 0;
2212 cpr->had_work_done = 1;
2216 cons = RING_CMP(raw_cons);
2217 txcmp = &cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)];
2219 if (!TX_CMP_VALID(txcmp, raw_cons))
2222 /* The valid test of the entry must be done first before
2223 * reading any further.
2226 if (TX_CMP_TYPE(txcmp) == CMP_TYPE_TX_L2_CMP) {
2228 /* return full budget so NAPI will complete. */
2229 if (unlikely(tx_pkts > bp->tx_wake_thresh)) {
2231 raw_cons = NEXT_RAW_CMP(raw_cons);
2233 cpr->has_more_work = 1;
2236 } else if ((TX_CMP_TYPE(txcmp) & 0x30) == 0x10) {
2238 rc = bnxt_rx_pkt(bp, cpr, &raw_cons, &event);
2240 rc = bnxt_force_rx_discard(bp, cpr, &raw_cons,
2242 if (likely(rc >= 0))
2244 /* Increment rx_pkts when rc is -ENOMEM to count towards
2245 * the NAPI budget. Otherwise, we may potentially loop
2246 * here forever if we consistently cannot allocate
2249 else if (rc == -ENOMEM && budget)
2251 else if (rc == -EBUSY) /* partial completion */
2253 } else if (unlikely((TX_CMP_TYPE(txcmp) ==
2254 CMPL_BASE_TYPE_HWRM_DONE) ||
2255 (TX_CMP_TYPE(txcmp) ==
2256 CMPL_BASE_TYPE_HWRM_FWD_REQ) ||
2257 (TX_CMP_TYPE(txcmp) ==
2258 CMPL_BASE_TYPE_HWRM_ASYNC_EVENT))) {
2259 bnxt_hwrm_handler(bp, txcmp);
2261 raw_cons = NEXT_RAW_CMP(raw_cons);
2263 if (rx_pkts && rx_pkts == budget) {
2264 cpr->has_more_work = 1;
2269 if (event & BNXT_REDIRECT_EVENT)
2272 if (event & BNXT_TX_EVENT) {
2273 struct bnxt_tx_ring_info *txr = bnapi->tx_ring;
2274 u16 prod = txr->tx_prod;
2276 /* Sync BD data before updating doorbell */
2279 bnxt_db_write_relaxed(bp, &txr->tx_db, prod);
2282 cpr->cp_raw_cons = raw_cons;
2283 bnapi->tx_pkts += tx_pkts;
2284 bnapi->events |= event;
2288 static void __bnxt_poll_work_done(struct bnxt *bp, struct bnxt_napi *bnapi)
2290 if (bnapi->tx_pkts) {
2291 bnapi->tx_int(bp, bnapi, bnapi->tx_pkts);
2295 if ((bnapi->events & BNXT_RX_EVENT) && !(bnapi->in_reset)) {
2296 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
2298 if (bnapi->events & BNXT_AGG_EVENT)
2299 bnxt_db_write(bp, &rxr->rx_agg_db, rxr->rx_agg_prod);
2300 bnxt_db_write(bp, &rxr->rx_db, rxr->rx_prod);
2305 static int bnxt_poll_work(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
2308 struct bnxt_napi *bnapi = cpr->bnapi;
2311 rx_pkts = __bnxt_poll_work(bp, cpr, budget);
2313 /* ACK completion ring before freeing tx ring and producing new
2314 * buffers in rx/agg rings to prevent overflowing the completion
2317 bnxt_db_cq(bp, &cpr->cp_db, cpr->cp_raw_cons);
2319 __bnxt_poll_work_done(bp, bnapi);
2323 static int bnxt_poll_nitroa0(struct napi_struct *napi, int budget)
2325 struct bnxt_napi *bnapi = container_of(napi, struct bnxt_napi, napi);
2326 struct bnxt *bp = bnapi->bp;
2327 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
2328 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
2329 struct tx_cmp *txcmp;
2330 struct rx_cmp_ext *rxcmp1;
2331 u32 cp_cons, tmp_raw_cons;
2332 u32 raw_cons = cpr->cp_raw_cons;
2339 cp_cons = RING_CMP(raw_cons);
2340 txcmp = &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
2342 if (!TX_CMP_VALID(txcmp, raw_cons))
2345 if ((TX_CMP_TYPE(txcmp) & 0x30) == 0x10) {
2346 tmp_raw_cons = NEXT_RAW_CMP(raw_cons);
2347 cp_cons = RING_CMP(tmp_raw_cons);
2348 rxcmp1 = (struct rx_cmp_ext *)
2349 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
2351 if (!RX_CMP_VALID(rxcmp1, tmp_raw_cons))
2354 /* force an error to recycle the buffer */
2355 rxcmp1->rx_cmp_cfa_code_errors_v2 |=
2356 cpu_to_le32(RX_CMPL_ERRORS_CRC_ERROR);
2358 rc = bnxt_rx_pkt(bp, cpr, &raw_cons, &event);
2359 if (likely(rc == -EIO) && budget)
2361 else if (rc == -EBUSY) /* partial completion */
2363 } else if (unlikely(TX_CMP_TYPE(txcmp) ==
2364 CMPL_BASE_TYPE_HWRM_DONE)) {
2365 bnxt_hwrm_handler(bp, txcmp);
2368 "Invalid completion received on special ring\n");
2370 raw_cons = NEXT_RAW_CMP(raw_cons);
2372 if (rx_pkts == budget)
2376 cpr->cp_raw_cons = raw_cons;
2377 BNXT_DB_CQ(&cpr->cp_db, cpr->cp_raw_cons);
2378 bnxt_db_write(bp, &rxr->rx_db, rxr->rx_prod);
2380 if (event & BNXT_AGG_EVENT)
2381 bnxt_db_write(bp, &rxr->rx_agg_db, rxr->rx_agg_prod);
2383 if (!bnxt_has_work(bp, cpr) && rx_pkts < budget) {
2384 napi_complete_done(napi, rx_pkts);
2385 BNXT_DB_CQ_ARM(&cpr->cp_db, cpr->cp_raw_cons);
2390 static int bnxt_poll(struct napi_struct *napi, int budget)
2392 struct bnxt_napi *bnapi = container_of(napi, struct bnxt_napi, napi);
2393 struct bnxt *bp = bnapi->bp;
2394 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
2398 work_done += bnxt_poll_work(bp, cpr, budget - work_done);
2400 if (work_done >= budget) {
2402 BNXT_DB_CQ_ARM(&cpr->cp_db, cpr->cp_raw_cons);
2406 if (!bnxt_has_work(bp, cpr)) {
2407 if (napi_complete_done(napi, work_done))
2408 BNXT_DB_CQ_ARM(&cpr->cp_db, cpr->cp_raw_cons);
2412 if (bp->flags & BNXT_FLAG_DIM) {
2413 struct dim_sample dim_sample = {};
2415 dim_update_sample(cpr->event_ctr,
2419 net_dim(&cpr->dim, dim_sample);
2424 static int __bnxt_poll_cqs(struct bnxt *bp, struct bnxt_napi *bnapi, int budget)
2426 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
2427 int i, work_done = 0;
2429 for (i = 0; i < 2; i++) {
2430 struct bnxt_cp_ring_info *cpr2 = cpr->cp_ring_arr[i];
2433 work_done += __bnxt_poll_work(bp, cpr2,
2434 budget - work_done);
2435 cpr->has_more_work |= cpr2->has_more_work;
2441 static void __bnxt_poll_cqs_done(struct bnxt *bp, struct bnxt_napi *bnapi,
2444 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
2447 for (i = 0; i < 2; i++) {
2448 struct bnxt_cp_ring_info *cpr2 = cpr->cp_ring_arr[i];
2449 struct bnxt_db_info *db;
2451 if (cpr2 && cpr2->had_work_done) {
2453 writeq(db->db_key64 | dbr_type |
2454 RING_CMP(cpr2->cp_raw_cons), db->doorbell);
2455 cpr2->had_work_done = 0;
2458 __bnxt_poll_work_done(bp, bnapi);
2461 static int bnxt_poll_p5(struct napi_struct *napi, int budget)
2463 struct bnxt_napi *bnapi = container_of(napi, struct bnxt_napi, napi);
2464 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
2465 u32 raw_cons = cpr->cp_raw_cons;
2466 struct bnxt *bp = bnapi->bp;
2467 struct nqe_cn *nqcmp;
2471 if (cpr->has_more_work) {
2472 cpr->has_more_work = 0;
2473 work_done = __bnxt_poll_cqs(bp, bnapi, budget);
2476 cons = RING_CMP(raw_cons);
2477 nqcmp = &cpr->nq_desc_ring[CP_RING(cons)][CP_IDX(cons)];
2479 if (!NQ_CMP_VALID(nqcmp, raw_cons)) {
2480 if (cpr->has_more_work)
2483 __bnxt_poll_cqs_done(bp, bnapi, DBR_TYPE_CQ_ARMALL);
2484 cpr->cp_raw_cons = raw_cons;
2485 if (napi_complete_done(napi, work_done))
2486 BNXT_DB_NQ_ARM_P5(&cpr->cp_db,
2491 /* The valid test of the entry must be done first before
2492 * reading any further.
2496 if (nqcmp->type == cpu_to_le16(NQ_CN_TYPE_CQ_NOTIFICATION)) {
2497 u32 idx = le32_to_cpu(nqcmp->cq_handle_low);
2498 struct bnxt_cp_ring_info *cpr2;
2500 cpr2 = cpr->cp_ring_arr[idx];
2501 work_done += __bnxt_poll_work(bp, cpr2,
2502 budget - work_done);
2503 cpr->has_more_work |= cpr2->has_more_work;
2505 bnxt_hwrm_handler(bp, (struct tx_cmp *)nqcmp);
2507 raw_cons = NEXT_RAW_CMP(raw_cons);
2509 __bnxt_poll_cqs_done(bp, bnapi, DBR_TYPE_CQ);
2510 if (raw_cons != cpr->cp_raw_cons) {
2511 cpr->cp_raw_cons = raw_cons;
2512 BNXT_DB_NQ_P5(&cpr->cp_db, raw_cons);
2517 static void bnxt_free_tx_skbs(struct bnxt *bp)
2520 struct pci_dev *pdev = bp->pdev;
2525 max_idx = bp->tx_nr_pages * TX_DESC_CNT;
2526 for (i = 0; i < bp->tx_nr_rings; i++) {
2527 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
2530 for (j = 0; j < max_idx;) {
2531 struct bnxt_sw_tx_bd *tx_buf = &txr->tx_buf_ring[j];
2532 struct sk_buff *skb;
2535 if (i < bp->tx_nr_rings_xdp &&
2536 tx_buf->action == XDP_REDIRECT) {
2537 dma_unmap_single(&pdev->dev,
2538 dma_unmap_addr(tx_buf, mapping),
2539 dma_unmap_len(tx_buf, len),
2541 xdp_return_frame(tx_buf->xdpf);
2543 tx_buf->xdpf = NULL;
2556 if (tx_buf->is_push) {
2562 dma_unmap_single(&pdev->dev,
2563 dma_unmap_addr(tx_buf, mapping),
2567 last = tx_buf->nr_frags;
2569 for (k = 0; k < last; k++, j++) {
2570 int ring_idx = j & bp->tx_ring_mask;
2571 skb_frag_t *frag = &skb_shinfo(skb)->frags[k];
2573 tx_buf = &txr->tx_buf_ring[ring_idx];
2576 dma_unmap_addr(tx_buf, mapping),
2577 skb_frag_size(frag), PCI_DMA_TODEVICE);
2581 netdev_tx_reset_queue(netdev_get_tx_queue(bp->dev, i));
2585 static void bnxt_free_one_rx_ring_skbs(struct bnxt *bp, int ring_nr)
2587 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[ring_nr];
2588 struct pci_dev *pdev = bp->pdev;
2589 struct bnxt_tpa_idx_map *map;
2590 int i, max_idx, max_agg_idx;
2592 max_idx = bp->rx_nr_pages * RX_DESC_CNT;
2593 max_agg_idx = bp->rx_agg_nr_pages * RX_DESC_CNT;
2595 goto skip_rx_tpa_free;
2597 for (i = 0; i < bp->max_tpa; i++) {
2598 struct bnxt_tpa_info *tpa_info = &rxr->rx_tpa[i];
2599 u8 *data = tpa_info->data;
2604 dma_unmap_single_attrs(&pdev->dev, tpa_info->mapping,
2605 bp->rx_buf_use_size, bp->rx_dir,
2606 DMA_ATTR_WEAK_ORDERING);
2608 tpa_info->data = NULL;
2614 for (i = 0; i < max_idx; i++) {
2615 struct bnxt_sw_rx_bd *rx_buf = &rxr->rx_buf_ring[i];
2616 dma_addr_t mapping = rx_buf->mapping;
2617 void *data = rx_buf->data;
2622 rx_buf->data = NULL;
2623 if (BNXT_RX_PAGE_MODE(bp)) {
2624 mapping -= bp->rx_dma_offset;
2625 dma_unmap_page_attrs(&pdev->dev, mapping, PAGE_SIZE,
2627 DMA_ATTR_WEAK_ORDERING);
2628 page_pool_recycle_direct(rxr->page_pool, data);
2630 dma_unmap_single_attrs(&pdev->dev, mapping,
2631 bp->rx_buf_use_size, bp->rx_dir,
2632 DMA_ATTR_WEAK_ORDERING);
2636 for (i = 0; i < max_agg_idx; i++) {
2637 struct bnxt_sw_rx_agg_bd *rx_agg_buf = &rxr->rx_agg_ring[i];
2638 struct page *page = rx_agg_buf->page;
2643 dma_unmap_page_attrs(&pdev->dev, rx_agg_buf->mapping,
2644 BNXT_RX_PAGE_SIZE, PCI_DMA_FROMDEVICE,
2645 DMA_ATTR_WEAK_ORDERING);
2647 rx_agg_buf->page = NULL;
2648 __clear_bit(i, rxr->rx_agg_bmap);
2653 __free_page(rxr->rx_page);
2654 rxr->rx_page = NULL;
2656 map = rxr->rx_tpa_idx_map;
2658 memset(map->agg_idx_bmap, 0, sizeof(map->agg_idx_bmap));
2661 static void bnxt_free_rx_skbs(struct bnxt *bp)
2668 for (i = 0; i < bp->rx_nr_rings; i++)
2669 bnxt_free_one_rx_ring_skbs(bp, i);
2672 static void bnxt_free_skbs(struct bnxt *bp)
2674 bnxt_free_tx_skbs(bp);
2675 bnxt_free_rx_skbs(bp);
2678 static void bnxt_free_ring(struct bnxt *bp, struct bnxt_ring_mem_info *rmem)
2680 struct pci_dev *pdev = bp->pdev;
2683 for (i = 0; i < rmem->nr_pages; i++) {
2684 if (!rmem->pg_arr[i])
2687 dma_free_coherent(&pdev->dev, rmem->page_size,
2688 rmem->pg_arr[i], rmem->dma_arr[i]);
2690 rmem->pg_arr[i] = NULL;
2693 size_t pg_tbl_size = rmem->nr_pages * 8;
2695 if (rmem->flags & BNXT_RMEM_USE_FULL_PAGE_FLAG)
2696 pg_tbl_size = rmem->page_size;
2697 dma_free_coherent(&pdev->dev, pg_tbl_size,
2698 rmem->pg_tbl, rmem->pg_tbl_map);
2699 rmem->pg_tbl = NULL;
2701 if (rmem->vmem_size && *rmem->vmem) {
2707 static int bnxt_alloc_ring(struct bnxt *bp, struct bnxt_ring_mem_info *rmem)
2709 struct pci_dev *pdev = bp->pdev;
2713 if (rmem->flags & (BNXT_RMEM_VALID_PTE_FLAG | BNXT_RMEM_RING_PTE_FLAG))
2714 valid_bit = PTU_PTE_VALID;
2715 if ((rmem->nr_pages > 1 || rmem->depth > 0) && !rmem->pg_tbl) {
2716 size_t pg_tbl_size = rmem->nr_pages * 8;
2718 if (rmem->flags & BNXT_RMEM_USE_FULL_PAGE_FLAG)
2719 pg_tbl_size = rmem->page_size;
2720 rmem->pg_tbl = dma_alloc_coherent(&pdev->dev, pg_tbl_size,
2727 for (i = 0; i < rmem->nr_pages; i++) {
2728 u64 extra_bits = valid_bit;
2730 rmem->pg_arr[i] = dma_alloc_coherent(&pdev->dev,
2734 if (!rmem->pg_arr[i])
2738 memset(rmem->pg_arr[i], rmem->init_val,
2740 if (rmem->nr_pages > 1 || rmem->depth > 0) {
2741 if (i == rmem->nr_pages - 2 &&
2742 (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
2743 extra_bits |= PTU_PTE_NEXT_TO_LAST;
2744 else if (i == rmem->nr_pages - 1 &&
2745 (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
2746 extra_bits |= PTU_PTE_LAST;
2748 cpu_to_le64(rmem->dma_arr[i] | extra_bits);
2752 if (rmem->vmem_size) {
2753 *rmem->vmem = vzalloc(rmem->vmem_size);
2760 static void bnxt_free_tpa_info(struct bnxt *bp)
2764 for (i = 0; i < bp->rx_nr_rings; i++) {
2765 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
2767 kfree(rxr->rx_tpa_idx_map);
2768 rxr->rx_tpa_idx_map = NULL;
2770 kfree(rxr->rx_tpa[0].agg_arr);
2771 rxr->rx_tpa[0].agg_arr = NULL;
2778 static int bnxt_alloc_tpa_info(struct bnxt *bp)
2780 int i, j, total_aggs = 0;
2782 bp->max_tpa = MAX_TPA;
2783 if (bp->flags & BNXT_FLAG_CHIP_P5) {
2784 if (!bp->max_tpa_v2)
2786 bp->max_tpa = max_t(u16, bp->max_tpa_v2, MAX_TPA_P5);
2787 total_aggs = bp->max_tpa * MAX_SKB_FRAGS;
2790 for (i = 0; i < bp->rx_nr_rings; i++) {
2791 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
2792 struct rx_agg_cmp *agg;
2794 rxr->rx_tpa = kcalloc(bp->max_tpa, sizeof(struct bnxt_tpa_info),
2799 if (!(bp->flags & BNXT_FLAG_CHIP_P5))
2801 agg = kcalloc(total_aggs, sizeof(*agg), GFP_KERNEL);
2802 rxr->rx_tpa[0].agg_arr = agg;
2805 for (j = 1; j < bp->max_tpa; j++)
2806 rxr->rx_tpa[j].agg_arr = agg + j * MAX_SKB_FRAGS;
2807 rxr->rx_tpa_idx_map = kzalloc(sizeof(*rxr->rx_tpa_idx_map),
2809 if (!rxr->rx_tpa_idx_map)
2815 static void bnxt_free_rx_rings(struct bnxt *bp)
2822 bnxt_free_tpa_info(bp);
2823 for (i = 0; i < bp->rx_nr_rings; i++) {
2824 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
2825 struct bnxt_ring_struct *ring;
2828 bpf_prog_put(rxr->xdp_prog);
2830 if (xdp_rxq_info_is_reg(&rxr->xdp_rxq))
2831 xdp_rxq_info_unreg(&rxr->xdp_rxq);
2833 page_pool_destroy(rxr->page_pool);
2834 rxr->page_pool = NULL;
2836 kfree(rxr->rx_agg_bmap);
2837 rxr->rx_agg_bmap = NULL;
2839 ring = &rxr->rx_ring_struct;
2840 bnxt_free_ring(bp, &ring->ring_mem);
2842 ring = &rxr->rx_agg_ring_struct;
2843 bnxt_free_ring(bp, &ring->ring_mem);
2847 static int bnxt_alloc_rx_page_pool(struct bnxt *bp,
2848 struct bnxt_rx_ring_info *rxr)
2850 struct page_pool_params pp = { 0 };
2852 pp.pool_size = bp->rx_ring_size;
2853 pp.nid = dev_to_node(&bp->pdev->dev);
2854 pp.dev = &bp->pdev->dev;
2855 pp.dma_dir = DMA_BIDIRECTIONAL;
2857 rxr->page_pool = page_pool_create(&pp);
2858 if (IS_ERR(rxr->page_pool)) {
2859 int err = PTR_ERR(rxr->page_pool);
2861 rxr->page_pool = NULL;
2867 static int bnxt_alloc_rx_rings(struct bnxt *bp)
2869 int i, rc = 0, agg_rings = 0;
2874 if (bp->flags & BNXT_FLAG_AGG_RINGS)
2877 for (i = 0; i < bp->rx_nr_rings; i++) {
2878 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
2879 struct bnxt_ring_struct *ring;
2881 ring = &rxr->rx_ring_struct;
2883 rc = bnxt_alloc_rx_page_pool(bp, rxr);
2887 rc = xdp_rxq_info_reg(&rxr->xdp_rxq, bp->dev, i, 0);
2891 rc = xdp_rxq_info_reg_mem_model(&rxr->xdp_rxq,
2895 xdp_rxq_info_unreg(&rxr->xdp_rxq);
2899 rc = bnxt_alloc_ring(bp, &ring->ring_mem);
2907 ring = &rxr->rx_agg_ring_struct;
2908 rc = bnxt_alloc_ring(bp, &ring->ring_mem);
2913 rxr->rx_agg_bmap_size = bp->rx_agg_ring_mask + 1;
2914 mem_size = rxr->rx_agg_bmap_size / 8;
2915 rxr->rx_agg_bmap = kzalloc(mem_size, GFP_KERNEL);
2916 if (!rxr->rx_agg_bmap)
2920 if (bp->flags & BNXT_FLAG_TPA)
2921 rc = bnxt_alloc_tpa_info(bp);
2925 static void bnxt_free_tx_rings(struct bnxt *bp)
2928 struct pci_dev *pdev = bp->pdev;
2933 for (i = 0; i < bp->tx_nr_rings; i++) {
2934 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
2935 struct bnxt_ring_struct *ring;
2938 dma_free_coherent(&pdev->dev, bp->tx_push_size,
2939 txr->tx_push, txr->tx_push_mapping);
2940 txr->tx_push = NULL;
2943 ring = &txr->tx_ring_struct;
2945 bnxt_free_ring(bp, &ring->ring_mem);
2949 static int bnxt_alloc_tx_rings(struct bnxt *bp)
2952 struct pci_dev *pdev = bp->pdev;
2954 bp->tx_push_size = 0;
2955 if (bp->tx_push_thresh) {
2958 push_size = L1_CACHE_ALIGN(sizeof(struct tx_push_bd) +
2959 bp->tx_push_thresh);
2961 if (push_size > 256) {
2963 bp->tx_push_thresh = 0;
2966 bp->tx_push_size = push_size;
2969 for (i = 0, j = 0; i < bp->tx_nr_rings; i++) {
2970 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
2971 struct bnxt_ring_struct *ring;
2974 ring = &txr->tx_ring_struct;
2976 rc = bnxt_alloc_ring(bp, &ring->ring_mem);
2980 ring->grp_idx = txr->bnapi->index;
2981 if (bp->tx_push_size) {
2984 /* One pre-allocated DMA buffer to backup
2987 txr->tx_push = dma_alloc_coherent(&pdev->dev,
2989 &txr->tx_push_mapping,
2995 mapping = txr->tx_push_mapping +
2996 sizeof(struct tx_push_bd);
2997 txr->data_mapping = cpu_to_le64(mapping);
2999 qidx = bp->tc_to_qidx[j];
3000 ring->queue_id = bp->q_info[qidx].queue_id;
3001 if (i < bp->tx_nr_rings_xdp)
3003 if (i % bp->tx_nr_rings_per_tc == (bp->tx_nr_rings_per_tc - 1))
3009 static void bnxt_free_cp_rings(struct bnxt *bp)
3016 for (i = 0; i < bp->cp_nr_rings; i++) {
3017 struct bnxt_napi *bnapi = bp->bnapi[i];
3018 struct bnxt_cp_ring_info *cpr;
3019 struct bnxt_ring_struct *ring;
3025 cpr = &bnapi->cp_ring;
3026 ring = &cpr->cp_ring_struct;
3028 bnxt_free_ring(bp, &ring->ring_mem);
3030 for (j = 0; j < 2; j++) {
3031 struct bnxt_cp_ring_info *cpr2 = cpr->cp_ring_arr[j];
3034 ring = &cpr2->cp_ring_struct;
3035 bnxt_free_ring(bp, &ring->ring_mem);
3037 cpr->cp_ring_arr[j] = NULL;
3043 static struct bnxt_cp_ring_info *bnxt_alloc_cp_sub_ring(struct bnxt *bp)
3045 struct bnxt_ring_mem_info *rmem;
3046 struct bnxt_ring_struct *ring;
3047 struct bnxt_cp_ring_info *cpr;
3050 cpr = kzalloc(sizeof(*cpr), GFP_KERNEL);
3054 ring = &cpr->cp_ring_struct;
3055 rmem = &ring->ring_mem;
3056 rmem->nr_pages = bp->cp_nr_pages;
3057 rmem->page_size = HW_CMPD_RING_SIZE;
3058 rmem->pg_arr = (void **)cpr->cp_desc_ring;
3059 rmem->dma_arr = cpr->cp_desc_mapping;
3060 rmem->flags = BNXT_RMEM_RING_PTE_FLAG;
3061 rc = bnxt_alloc_ring(bp, rmem);
3063 bnxt_free_ring(bp, rmem);
3070 static int bnxt_alloc_cp_rings(struct bnxt *bp)
3072 bool sh = !!(bp->flags & BNXT_FLAG_SHARED_RINGS);
3073 int i, rc, ulp_base_vec, ulp_msix;
3075 ulp_msix = bnxt_get_ulp_msix_num(bp);
3076 ulp_base_vec = bnxt_get_ulp_msix_base(bp);
3077 for (i = 0; i < bp->cp_nr_rings; i++) {
3078 struct bnxt_napi *bnapi = bp->bnapi[i];
3079 struct bnxt_cp_ring_info *cpr;
3080 struct bnxt_ring_struct *ring;
3085 cpr = &bnapi->cp_ring;
3087 ring = &cpr->cp_ring_struct;
3089 rc = bnxt_alloc_ring(bp, &ring->ring_mem);
3093 if (ulp_msix && i >= ulp_base_vec)
3094 ring->map_idx = i + ulp_msix;
3098 if (!(bp->flags & BNXT_FLAG_CHIP_P5))
3101 if (i < bp->rx_nr_rings) {
3102 struct bnxt_cp_ring_info *cpr2 =
3103 bnxt_alloc_cp_sub_ring(bp);
3105 cpr->cp_ring_arr[BNXT_RX_HDL] = cpr2;
3108 cpr2->bnapi = bnapi;
3110 if ((sh && i < bp->tx_nr_rings) ||
3111 (!sh && i >= bp->rx_nr_rings)) {
3112 struct bnxt_cp_ring_info *cpr2 =
3113 bnxt_alloc_cp_sub_ring(bp);
3115 cpr->cp_ring_arr[BNXT_TX_HDL] = cpr2;
3118 cpr2->bnapi = bnapi;
3124 static void bnxt_init_ring_struct(struct bnxt *bp)
3128 for (i = 0; i < bp->cp_nr_rings; i++) {
3129 struct bnxt_napi *bnapi = bp->bnapi[i];
3130 struct bnxt_ring_mem_info *rmem;
3131 struct bnxt_cp_ring_info *cpr;
3132 struct bnxt_rx_ring_info *rxr;
3133 struct bnxt_tx_ring_info *txr;
3134 struct bnxt_ring_struct *ring;
3139 cpr = &bnapi->cp_ring;
3140 ring = &cpr->cp_ring_struct;
3141 rmem = &ring->ring_mem;
3142 rmem->nr_pages = bp->cp_nr_pages;
3143 rmem->page_size = HW_CMPD_RING_SIZE;
3144 rmem->pg_arr = (void **)cpr->cp_desc_ring;
3145 rmem->dma_arr = cpr->cp_desc_mapping;
3146 rmem->vmem_size = 0;
3148 rxr = bnapi->rx_ring;
3152 ring = &rxr->rx_ring_struct;
3153 rmem = &ring->ring_mem;
3154 rmem->nr_pages = bp->rx_nr_pages;
3155 rmem->page_size = HW_RXBD_RING_SIZE;
3156 rmem->pg_arr = (void **)rxr->rx_desc_ring;
3157 rmem->dma_arr = rxr->rx_desc_mapping;
3158 rmem->vmem_size = SW_RXBD_RING_SIZE * bp->rx_nr_pages;
3159 rmem->vmem = (void **)&rxr->rx_buf_ring;
3161 ring = &rxr->rx_agg_ring_struct;
3162 rmem = &ring->ring_mem;
3163 rmem->nr_pages = bp->rx_agg_nr_pages;
3164 rmem->page_size = HW_RXBD_RING_SIZE;
3165 rmem->pg_arr = (void **)rxr->rx_agg_desc_ring;
3166 rmem->dma_arr = rxr->rx_agg_desc_mapping;
3167 rmem->vmem_size = SW_RXBD_AGG_RING_SIZE * bp->rx_agg_nr_pages;
3168 rmem->vmem = (void **)&rxr->rx_agg_ring;
3171 txr = bnapi->tx_ring;
3175 ring = &txr->tx_ring_struct;
3176 rmem = &ring->ring_mem;
3177 rmem->nr_pages = bp->tx_nr_pages;
3178 rmem->page_size = HW_RXBD_RING_SIZE;
3179 rmem->pg_arr = (void **)txr->tx_desc_ring;
3180 rmem->dma_arr = txr->tx_desc_mapping;
3181 rmem->vmem_size = SW_TXBD_RING_SIZE * bp->tx_nr_pages;
3182 rmem->vmem = (void **)&txr->tx_buf_ring;
3186 static void bnxt_init_rxbd_pages(struct bnxt_ring_struct *ring, u32 type)
3190 struct rx_bd **rx_buf_ring;
3192 rx_buf_ring = (struct rx_bd **)ring->ring_mem.pg_arr;
3193 for (i = 0, prod = 0; i < ring->ring_mem.nr_pages; i++) {
3197 rxbd = rx_buf_ring[i];
3201 for (j = 0; j < RX_DESC_CNT; j++, rxbd++, prod++) {
3202 rxbd->rx_bd_len_flags_type = cpu_to_le32(type);
3203 rxbd->rx_bd_opaque = prod;
3208 static int bnxt_alloc_one_rx_ring(struct bnxt *bp, int ring_nr)
3210 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[ring_nr];
3211 struct net_device *dev = bp->dev;
3215 prod = rxr->rx_prod;
3216 for (i = 0; i < bp->rx_ring_size; i++) {
3217 if (bnxt_alloc_rx_data(bp, rxr, prod, GFP_KERNEL)) {
3218 netdev_warn(dev, "init'ed rx ring %d with %d/%d skbs only\n",
3219 ring_nr, i, bp->rx_ring_size);
3222 prod = NEXT_RX(prod);
3224 rxr->rx_prod = prod;
3226 if (!(bp->flags & BNXT_FLAG_AGG_RINGS))
3229 prod = rxr->rx_agg_prod;
3230 for (i = 0; i < bp->rx_agg_ring_size; i++) {
3231 if (bnxt_alloc_rx_page(bp, rxr, prod, GFP_KERNEL)) {
3232 netdev_warn(dev, "init'ed rx ring %d with %d/%d pages only\n",
3233 ring_nr, i, bp->rx_ring_size);
3236 prod = NEXT_RX_AGG(prod);
3238 rxr->rx_agg_prod = prod;
3244 for (i = 0; i < bp->max_tpa; i++) {
3245 data = __bnxt_alloc_rx_data(bp, &mapping, GFP_KERNEL);
3249 rxr->rx_tpa[i].data = data;
3250 rxr->rx_tpa[i].data_ptr = data + bp->rx_offset;
3251 rxr->rx_tpa[i].mapping = mapping;
3257 static int bnxt_init_one_rx_ring(struct bnxt *bp, int ring_nr)
3259 struct bnxt_rx_ring_info *rxr;
3260 struct bnxt_ring_struct *ring;
3263 type = (bp->rx_buf_use_size << RX_BD_LEN_SHIFT) |
3264 RX_BD_TYPE_RX_PACKET_BD | RX_BD_FLAGS_EOP;
3266 if (NET_IP_ALIGN == 2)
3267 type |= RX_BD_FLAGS_SOP;
3269 rxr = &bp->rx_ring[ring_nr];
3270 ring = &rxr->rx_ring_struct;
3271 bnxt_init_rxbd_pages(ring, type);
3273 if (BNXT_RX_PAGE_MODE(bp) && bp->xdp_prog) {
3274 bpf_prog_add(bp->xdp_prog, 1);
3275 rxr->xdp_prog = bp->xdp_prog;
3277 ring->fw_ring_id = INVALID_HW_RING_ID;
3279 ring = &rxr->rx_agg_ring_struct;
3280 ring->fw_ring_id = INVALID_HW_RING_ID;
3282 if ((bp->flags & BNXT_FLAG_AGG_RINGS)) {
3283 type = ((u32)BNXT_RX_PAGE_SIZE << RX_BD_LEN_SHIFT) |
3284 RX_BD_TYPE_RX_AGG_BD | RX_BD_FLAGS_SOP;
3286 bnxt_init_rxbd_pages(ring, type);
3289 return bnxt_alloc_one_rx_ring(bp, ring_nr);
3292 static void bnxt_init_cp_rings(struct bnxt *bp)
3296 for (i = 0; i < bp->cp_nr_rings; i++) {
3297 struct bnxt_cp_ring_info *cpr = &bp->bnapi[i]->cp_ring;
3298 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct;
3300 ring->fw_ring_id = INVALID_HW_RING_ID;
3301 cpr->rx_ring_coal.coal_ticks = bp->rx_coal.coal_ticks;
3302 cpr->rx_ring_coal.coal_bufs = bp->rx_coal.coal_bufs;
3303 for (j = 0; j < 2; j++) {
3304 struct bnxt_cp_ring_info *cpr2 = cpr->cp_ring_arr[j];
3309 ring = &cpr2->cp_ring_struct;
3310 ring->fw_ring_id = INVALID_HW_RING_ID;
3311 cpr2->rx_ring_coal.coal_ticks = bp->rx_coal.coal_ticks;
3312 cpr2->rx_ring_coal.coal_bufs = bp->rx_coal.coal_bufs;
3317 static int bnxt_init_rx_rings(struct bnxt *bp)
3321 if (BNXT_RX_PAGE_MODE(bp)) {
3322 bp->rx_offset = NET_IP_ALIGN + XDP_PACKET_HEADROOM;
3323 bp->rx_dma_offset = XDP_PACKET_HEADROOM;
3325 bp->rx_offset = BNXT_RX_OFFSET;
3326 bp->rx_dma_offset = BNXT_RX_DMA_OFFSET;
3329 for (i = 0; i < bp->rx_nr_rings; i++) {
3330 rc = bnxt_init_one_rx_ring(bp, i);
3338 static int bnxt_init_tx_rings(struct bnxt *bp)
3342 bp->tx_wake_thresh = max_t(int, bp->tx_ring_size / 2,
3345 for (i = 0; i < bp->tx_nr_rings; i++) {
3346 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
3347 struct bnxt_ring_struct *ring = &txr->tx_ring_struct;
3349 ring->fw_ring_id = INVALID_HW_RING_ID;
3355 static void bnxt_free_ring_grps(struct bnxt *bp)
3357 kfree(bp->grp_info);
3358 bp->grp_info = NULL;
3361 static int bnxt_init_ring_grps(struct bnxt *bp, bool irq_re_init)
3366 bp->grp_info = kcalloc(bp->cp_nr_rings,
3367 sizeof(struct bnxt_ring_grp_info),
3372 for (i = 0; i < bp->cp_nr_rings; i++) {
3374 bp->grp_info[i].fw_stats_ctx = INVALID_HW_RING_ID;
3375 bp->grp_info[i].fw_grp_id = INVALID_HW_RING_ID;
3376 bp->grp_info[i].rx_fw_ring_id = INVALID_HW_RING_ID;
3377 bp->grp_info[i].agg_fw_ring_id = INVALID_HW_RING_ID;
3378 bp->grp_info[i].cp_fw_ring_id = INVALID_HW_RING_ID;
3383 static void bnxt_free_vnics(struct bnxt *bp)
3385 kfree(bp->vnic_info);
3386 bp->vnic_info = NULL;
3390 static int bnxt_alloc_vnics(struct bnxt *bp)
3394 #ifdef CONFIG_RFS_ACCEL
3395 if ((bp->flags & (BNXT_FLAG_RFS | BNXT_FLAG_CHIP_P5)) == BNXT_FLAG_RFS)
3396 num_vnics += bp->rx_nr_rings;
3399 if (BNXT_CHIP_TYPE_NITRO_A0(bp))
3402 bp->vnic_info = kcalloc(num_vnics, sizeof(struct bnxt_vnic_info),
3407 bp->nr_vnics = num_vnics;
3411 static void bnxt_init_vnics(struct bnxt *bp)
3415 for (i = 0; i < bp->nr_vnics; i++) {
3416 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3419 vnic->fw_vnic_id = INVALID_HW_RING_ID;
3420 for (j = 0; j < BNXT_MAX_CTX_PER_VNIC; j++)
3421 vnic->fw_rss_cos_lb_ctx[j] = INVALID_HW_RING_ID;
3423 vnic->fw_l2_ctx_id = INVALID_HW_RING_ID;
3425 if (bp->vnic_info[i].rss_hash_key) {
3427 prandom_bytes(vnic->rss_hash_key,
3430 memcpy(vnic->rss_hash_key,
3431 bp->vnic_info[0].rss_hash_key,
3437 static int bnxt_calc_nr_ring_pages(u32 ring_size, int desc_per_pg)
3441 pages = ring_size / desc_per_pg;
3448 while (pages & (pages - 1))
3454 void bnxt_set_tpa_flags(struct bnxt *bp)
3456 bp->flags &= ~BNXT_FLAG_TPA;
3457 if (bp->flags & BNXT_FLAG_NO_AGG_RINGS)
3459 if (bp->dev->features & NETIF_F_LRO)
3460 bp->flags |= BNXT_FLAG_LRO;
3461 else if (bp->dev->features & NETIF_F_GRO_HW)
3462 bp->flags |= BNXT_FLAG_GRO;
3465 /* bp->rx_ring_size, bp->tx_ring_size, dev->mtu, BNXT_FLAG_{G|L}RO flags must
3468 void bnxt_set_ring_params(struct bnxt *bp)
3470 u32 ring_size, rx_size, rx_space, max_rx_cmpl;
3471 u32 agg_factor = 0, agg_ring_size = 0;
3473 /* 8 for CRC and VLAN */
3474 rx_size = SKB_DATA_ALIGN(bp->dev->mtu + ETH_HLEN + NET_IP_ALIGN + 8);
3476 rx_space = rx_size + NET_SKB_PAD +
3477 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
3479 bp->rx_copy_thresh = BNXT_RX_COPY_THRESH;
3480 ring_size = bp->rx_ring_size;
3481 bp->rx_agg_ring_size = 0;
3482 bp->rx_agg_nr_pages = 0;
3484 if (bp->flags & BNXT_FLAG_TPA)
3485 agg_factor = min_t(u32, 4, 65536 / BNXT_RX_PAGE_SIZE);
3487 bp->flags &= ~BNXT_FLAG_JUMBO;
3488 if (rx_space > PAGE_SIZE && !(bp->flags & BNXT_FLAG_NO_AGG_RINGS)) {
3491 bp->flags |= BNXT_FLAG_JUMBO;
3492 jumbo_factor = PAGE_ALIGN(bp->dev->mtu - 40) >> PAGE_SHIFT;
3493 if (jumbo_factor > agg_factor)
3494 agg_factor = jumbo_factor;
3496 agg_ring_size = ring_size * agg_factor;
3498 if (agg_ring_size) {
3499 bp->rx_agg_nr_pages = bnxt_calc_nr_ring_pages(agg_ring_size,
3501 if (bp->rx_agg_nr_pages > MAX_RX_AGG_PAGES) {
3502 u32 tmp = agg_ring_size;
3504 bp->rx_agg_nr_pages = MAX_RX_AGG_PAGES;
3505 agg_ring_size = MAX_RX_AGG_PAGES * RX_DESC_CNT - 1;
3506 netdev_warn(bp->dev, "rx agg ring size %d reduced to %d.\n",
3507 tmp, agg_ring_size);
3509 bp->rx_agg_ring_size = agg_ring_size;
3510 bp->rx_agg_ring_mask = (bp->rx_agg_nr_pages * RX_DESC_CNT) - 1;
3511 rx_size = SKB_DATA_ALIGN(BNXT_RX_COPY_THRESH + NET_IP_ALIGN);
3512 rx_space = rx_size + NET_SKB_PAD +
3513 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
3516 bp->rx_buf_use_size = rx_size;
3517 bp->rx_buf_size = rx_space;
3519 bp->rx_nr_pages = bnxt_calc_nr_ring_pages(ring_size, RX_DESC_CNT);
3520 bp->rx_ring_mask = (bp->rx_nr_pages * RX_DESC_CNT) - 1;
3522 ring_size = bp->tx_ring_size;
3523 bp->tx_nr_pages = bnxt_calc_nr_ring_pages(ring_size, TX_DESC_CNT);
3524 bp->tx_ring_mask = (bp->tx_nr_pages * TX_DESC_CNT) - 1;
3526 max_rx_cmpl = bp->rx_ring_size;
3527 /* MAX TPA needs to be added because TPA_START completions are
3528 * immediately recycled, so the TPA completions are not bound by
3531 if (bp->flags & BNXT_FLAG_TPA)
3532 max_rx_cmpl += bp->max_tpa;
3533 /* RX and TPA completions are 32-byte, all others are 16-byte */
3534 ring_size = max_rx_cmpl * 2 + agg_ring_size + bp->tx_ring_size;
3535 bp->cp_ring_size = ring_size;
3537 bp->cp_nr_pages = bnxt_calc_nr_ring_pages(ring_size, CP_DESC_CNT);
3538 if (bp->cp_nr_pages > MAX_CP_PAGES) {
3539 bp->cp_nr_pages = MAX_CP_PAGES;
3540 bp->cp_ring_size = MAX_CP_PAGES * CP_DESC_CNT - 1;
3541 netdev_warn(bp->dev, "completion ring size %d reduced to %d.\n",
3542 ring_size, bp->cp_ring_size);
3544 bp->cp_bit = bp->cp_nr_pages * CP_DESC_CNT;
3545 bp->cp_ring_mask = bp->cp_bit - 1;
3548 /* Changing allocation mode of RX rings.
3549 * TODO: Update when extending xdp_rxq_info to support allocation modes.
3551 int bnxt_set_rx_skb_mode(struct bnxt *bp, bool page_mode)
3554 if (bp->dev->mtu > BNXT_MAX_PAGE_MODE_MTU)
3557 min_t(u16, bp->max_mtu, BNXT_MAX_PAGE_MODE_MTU);
3558 bp->flags &= ~BNXT_FLAG_AGG_RINGS;
3559 bp->flags |= BNXT_FLAG_NO_AGG_RINGS | BNXT_FLAG_RX_PAGE_MODE;
3560 bp->rx_dir = DMA_BIDIRECTIONAL;
3561 bp->rx_skb_func = bnxt_rx_page_skb;
3562 /* Disable LRO or GRO_HW */
3563 netdev_update_features(bp->dev);
3565 bp->dev->max_mtu = bp->max_mtu;
3566 bp->flags &= ~BNXT_FLAG_RX_PAGE_MODE;
3567 bp->rx_dir = DMA_FROM_DEVICE;
3568 bp->rx_skb_func = bnxt_rx_skb;
3573 static void bnxt_free_vnic_attributes(struct bnxt *bp)
3576 struct bnxt_vnic_info *vnic;
3577 struct pci_dev *pdev = bp->pdev;
3582 for (i = 0; i < bp->nr_vnics; i++) {
3583 vnic = &bp->vnic_info[i];
3585 kfree(vnic->fw_grp_ids);
3586 vnic->fw_grp_ids = NULL;
3588 kfree(vnic->uc_list);
3589 vnic->uc_list = NULL;
3591 if (vnic->mc_list) {
3592 dma_free_coherent(&pdev->dev, vnic->mc_list_size,
3593 vnic->mc_list, vnic->mc_list_mapping);
3594 vnic->mc_list = NULL;
3597 if (vnic->rss_table) {
3598 dma_free_coherent(&pdev->dev, vnic->rss_table_size,
3600 vnic->rss_table_dma_addr);
3601 vnic->rss_table = NULL;
3604 vnic->rss_hash_key = NULL;
3609 static int bnxt_alloc_vnic_attributes(struct bnxt *bp)
3611 int i, rc = 0, size;
3612 struct bnxt_vnic_info *vnic;
3613 struct pci_dev *pdev = bp->pdev;
3616 for (i = 0; i < bp->nr_vnics; i++) {
3617 vnic = &bp->vnic_info[i];
3619 if (vnic->flags & BNXT_VNIC_UCAST_FLAG) {
3620 int mem_size = (BNXT_MAX_UC_ADDRS - 1) * ETH_ALEN;
3623 vnic->uc_list = kmalloc(mem_size, GFP_KERNEL);
3624 if (!vnic->uc_list) {
3631 if (vnic->flags & BNXT_VNIC_MCAST_FLAG) {
3632 vnic->mc_list_size = BNXT_MAX_MC_ADDRS * ETH_ALEN;
3634 dma_alloc_coherent(&pdev->dev,
3636 &vnic->mc_list_mapping,
3638 if (!vnic->mc_list) {
3644 if (bp->flags & BNXT_FLAG_CHIP_P5)
3645 goto vnic_skip_grps;
3647 if (vnic->flags & BNXT_VNIC_RSS_FLAG)
3648 max_rings = bp->rx_nr_rings;
3652 vnic->fw_grp_ids = kcalloc(max_rings, sizeof(u16), GFP_KERNEL);
3653 if (!vnic->fw_grp_ids) {
3658 if ((bp->flags & BNXT_FLAG_NEW_RSS_CAP) &&
3659 !(vnic->flags & BNXT_VNIC_RSS_FLAG))
3662 /* Allocate rss table and hash key */
3663 size = L1_CACHE_ALIGN(HW_HASH_INDEX_SIZE * sizeof(u16));
3664 if (bp->flags & BNXT_FLAG_CHIP_P5)
3665 size = L1_CACHE_ALIGN(BNXT_MAX_RSS_TABLE_SIZE_P5);
3667 vnic->rss_table_size = size + HW_HASH_KEY_SIZE;
3668 vnic->rss_table = dma_alloc_coherent(&pdev->dev,
3669 vnic->rss_table_size,
3670 &vnic->rss_table_dma_addr,
3672 if (!vnic->rss_table) {
3677 vnic->rss_hash_key = ((void *)vnic->rss_table) + size;
3678 vnic->rss_hash_key_dma_addr = vnic->rss_table_dma_addr + size;
3686 static void bnxt_free_hwrm_resources(struct bnxt *bp)
3688 struct pci_dev *pdev = bp->pdev;
3690 if (bp->hwrm_cmd_resp_addr) {
3691 dma_free_coherent(&pdev->dev, PAGE_SIZE, bp->hwrm_cmd_resp_addr,
3692 bp->hwrm_cmd_resp_dma_addr);
3693 bp->hwrm_cmd_resp_addr = NULL;
3696 if (bp->hwrm_cmd_kong_resp_addr) {
3697 dma_free_coherent(&pdev->dev, PAGE_SIZE,
3698 bp->hwrm_cmd_kong_resp_addr,
3699 bp->hwrm_cmd_kong_resp_dma_addr);
3700 bp->hwrm_cmd_kong_resp_addr = NULL;
3704 static int bnxt_alloc_kong_hwrm_resources(struct bnxt *bp)
3706 struct pci_dev *pdev = bp->pdev;
3708 if (bp->hwrm_cmd_kong_resp_addr)
3711 bp->hwrm_cmd_kong_resp_addr =
3712 dma_alloc_coherent(&pdev->dev, PAGE_SIZE,
3713 &bp->hwrm_cmd_kong_resp_dma_addr,
3715 if (!bp->hwrm_cmd_kong_resp_addr)
3721 static int bnxt_alloc_hwrm_resources(struct bnxt *bp)
3723 struct pci_dev *pdev = bp->pdev;
3725 bp->hwrm_cmd_resp_addr = dma_alloc_coherent(&pdev->dev, PAGE_SIZE,
3726 &bp->hwrm_cmd_resp_dma_addr,
3728 if (!bp->hwrm_cmd_resp_addr)
3734 static void bnxt_free_hwrm_short_cmd_req(struct bnxt *bp)
3736 if (bp->hwrm_short_cmd_req_addr) {
3737 struct pci_dev *pdev = bp->pdev;
3739 dma_free_coherent(&pdev->dev, bp->hwrm_max_ext_req_len,
3740 bp->hwrm_short_cmd_req_addr,
3741 bp->hwrm_short_cmd_req_dma_addr);
3742 bp->hwrm_short_cmd_req_addr = NULL;
3746 static int bnxt_alloc_hwrm_short_cmd_req(struct bnxt *bp)
3748 struct pci_dev *pdev = bp->pdev;
3750 if (bp->hwrm_short_cmd_req_addr)
3753 bp->hwrm_short_cmd_req_addr =
3754 dma_alloc_coherent(&pdev->dev, bp->hwrm_max_ext_req_len,
3755 &bp->hwrm_short_cmd_req_dma_addr,
3757 if (!bp->hwrm_short_cmd_req_addr)
3763 static void bnxt_free_stats_mem(struct bnxt *bp, struct bnxt_stats_mem *stats)
3765 kfree(stats->hw_masks);
3766 stats->hw_masks = NULL;
3767 kfree(stats->sw_stats);
3768 stats->sw_stats = NULL;
3769 if (stats->hw_stats) {
3770 dma_free_coherent(&bp->pdev->dev, stats->len, stats->hw_stats,
3771 stats->hw_stats_map);
3772 stats->hw_stats = NULL;
3776 static int bnxt_alloc_stats_mem(struct bnxt *bp, struct bnxt_stats_mem *stats,
3779 stats->hw_stats = dma_alloc_coherent(&bp->pdev->dev, stats->len,
3780 &stats->hw_stats_map, GFP_KERNEL);
3781 if (!stats->hw_stats)
3784 stats->sw_stats = kzalloc(stats->len, GFP_KERNEL);
3785 if (!stats->sw_stats)
3789 stats->hw_masks = kzalloc(stats->len, GFP_KERNEL);
3790 if (!stats->hw_masks)
3796 bnxt_free_stats_mem(bp, stats);
3800 static void bnxt_fill_masks(u64 *mask_arr, u64 mask, int count)
3804 for (i = 0; i < count; i++)
3808 static void bnxt_copy_hw_masks(u64 *mask_arr, __le64 *hw_mask_arr, int count)
3812 for (i = 0; i < count; i++)
3813 mask_arr[i] = le64_to_cpu(hw_mask_arr[i]);
3816 static int bnxt_hwrm_func_qstat_ext(struct bnxt *bp,
3817 struct bnxt_stats_mem *stats)
3819 struct hwrm_func_qstats_ext_output *resp = bp->hwrm_cmd_resp_addr;
3820 struct hwrm_func_qstats_ext_input req = {0};
3824 if (!(bp->fw_cap & BNXT_FW_CAP_EXT_HW_STATS_SUPPORTED) ||
3825 !(bp->flags & BNXT_FLAG_CHIP_P5))
3828 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QSTATS_EXT, -1, -1);
3829 req.fid = cpu_to_le16(0xffff);
3830 req.flags = FUNC_QSTATS_EXT_REQ_FLAGS_COUNTER_MASK;
3831 mutex_lock(&bp->hwrm_cmd_lock);
3832 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3836 hw_masks = &resp->rx_ucast_pkts;
3837 bnxt_copy_hw_masks(stats->hw_masks, hw_masks, stats->len / 8);
3840 mutex_unlock(&bp->hwrm_cmd_lock);
3844 static int bnxt_hwrm_port_qstats(struct bnxt *bp, u8 flags);
3845 static int bnxt_hwrm_port_qstats_ext(struct bnxt *bp, u8 flags);
3847 static void bnxt_init_stats(struct bnxt *bp)
3849 struct bnxt_napi *bnapi = bp->bnapi[0];
3850 struct bnxt_cp_ring_info *cpr;
3851 struct bnxt_stats_mem *stats;
3852 __le64 *rx_stats, *tx_stats;
3853 int rc, rx_count, tx_count;
3854 u64 *rx_masks, *tx_masks;
3858 cpr = &bnapi->cp_ring;
3859 stats = &cpr->stats;
3860 rc = bnxt_hwrm_func_qstat_ext(bp, stats);
3862 if (bp->flags & BNXT_FLAG_CHIP_P5)
3863 mask = (1ULL << 48) - 1;
3866 bnxt_fill_masks(stats->hw_masks, mask, stats->len / 8);
3868 if (bp->flags & BNXT_FLAG_PORT_STATS) {
3869 stats = &bp->port_stats;
3870 rx_stats = stats->hw_stats;
3871 rx_masks = stats->hw_masks;
3872 rx_count = sizeof(struct rx_port_stats) / 8;
3873 tx_stats = rx_stats + BNXT_TX_PORT_STATS_BYTE_OFFSET / 8;
3874 tx_masks = rx_masks + BNXT_TX_PORT_STATS_BYTE_OFFSET / 8;
3875 tx_count = sizeof(struct tx_port_stats) / 8;
3877 flags = PORT_QSTATS_REQ_FLAGS_COUNTER_MASK;
3878 rc = bnxt_hwrm_port_qstats(bp, flags);
3880 mask = (1ULL << 40) - 1;
3882 bnxt_fill_masks(rx_masks, mask, rx_count);
3883 bnxt_fill_masks(tx_masks, mask, tx_count);
3885 bnxt_copy_hw_masks(rx_masks, rx_stats, rx_count);
3886 bnxt_copy_hw_masks(tx_masks, tx_stats, tx_count);
3887 bnxt_hwrm_port_qstats(bp, 0);
3890 if (bp->flags & BNXT_FLAG_PORT_STATS_EXT) {
3891 stats = &bp->rx_port_stats_ext;
3892 rx_stats = stats->hw_stats;
3893 rx_masks = stats->hw_masks;
3894 rx_count = sizeof(struct rx_port_stats_ext) / 8;
3895 stats = &bp->tx_port_stats_ext;
3896 tx_stats = stats->hw_stats;
3897 tx_masks = stats->hw_masks;
3898 tx_count = sizeof(struct tx_port_stats_ext) / 8;
3900 flags = PORT_QSTATS_EXT_REQ_FLAGS_COUNTER_MASK;
3901 rc = bnxt_hwrm_port_qstats_ext(bp, flags);
3903 mask = (1ULL << 40) - 1;
3905 bnxt_fill_masks(rx_masks, mask, rx_count);
3907 bnxt_fill_masks(tx_masks, mask, tx_count);
3909 bnxt_copy_hw_masks(rx_masks, rx_stats, rx_count);
3911 bnxt_copy_hw_masks(tx_masks, tx_stats,
3913 bnxt_hwrm_port_qstats_ext(bp, 0);
3918 static void bnxt_free_port_stats(struct bnxt *bp)
3920 bp->flags &= ~BNXT_FLAG_PORT_STATS;
3921 bp->flags &= ~BNXT_FLAG_PORT_STATS_EXT;
3923 bnxt_free_stats_mem(bp, &bp->port_stats);
3924 bnxt_free_stats_mem(bp, &bp->rx_port_stats_ext);
3925 bnxt_free_stats_mem(bp, &bp->tx_port_stats_ext);
3928 static void bnxt_free_ring_stats(struct bnxt *bp)
3935 for (i = 0; i < bp->cp_nr_rings; i++) {
3936 struct bnxt_napi *bnapi = bp->bnapi[i];
3937 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
3939 bnxt_free_stats_mem(bp, &cpr->stats);
3943 static int bnxt_alloc_stats(struct bnxt *bp)
3948 size = bp->hw_ring_stats_size;
3950 for (i = 0; i < bp->cp_nr_rings; i++) {
3951 struct bnxt_napi *bnapi = bp->bnapi[i];
3952 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
3954 cpr->stats.len = size;
3955 rc = bnxt_alloc_stats_mem(bp, &cpr->stats, !i);
3959 cpr->hw_stats_ctx_id = INVALID_STATS_CTX_ID;
3962 if (BNXT_VF(bp) || bp->chip_num == CHIP_NUM_58700)
3965 if (bp->port_stats.hw_stats)
3966 goto alloc_ext_stats;
3968 bp->port_stats.len = BNXT_PORT_STATS_SIZE;
3969 rc = bnxt_alloc_stats_mem(bp, &bp->port_stats, true);
3973 bp->flags |= BNXT_FLAG_PORT_STATS;
3976 /* Display extended statistics only if FW supports it */
3977 if (bp->hwrm_spec_code < 0x10804 || bp->hwrm_spec_code == 0x10900)
3978 if (!(bp->fw_cap & BNXT_FW_CAP_EXT_STATS_SUPPORTED))
3981 if (bp->rx_port_stats_ext.hw_stats)
3982 goto alloc_tx_ext_stats;
3984 bp->rx_port_stats_ext.len = sizeof(struct rx_port_stats_ext);
3985 rc = bnxt_alloc_stats_mem(bp, &bp->rx_port_stats_ext, true);
3986 /* Extended stats are optional */
3991 if (bp->tx_port_stats_ext.hw_stats)
3994 if (bp->hwrm_spec_code >= 0x10902 ||
3995 (bp->fw_cap & BNXT_FW_CAP_EXT_STATS_SUPPORTED)) {
3996 bp->tx_port_stats_ext.len = sizeof(struct tx_port_stats_ext);
3997 rc = bnxt_alloc_stats_mem(bp, &bp->tx_port_stats_ext, true);
3998 /* Extended stats are optional */
4002 bp->flags |= BNXT_FLAG_PORT_STATS_EXT;
4006 static void bnxt_clear_ring_indices(struct bnxt *bp)
4013 for (i = 0; i < bp->cp_nr_rings; i++) {
4014 struct bnxt_napi *bnapi = bp->bnapi[i];
4015 struct bnxt_cp_ring_info *cpr;
4016 struct bnxt_rx_ring_info *rxr;
4017 struct bnxt_tx_ring_info *txr;
4022 cpr = &bnapi->cp_ring;
4023 cpr->cp_raw_cons = 0;
4025 txr = bnapi->tx_ring;
4031 rxr = bnapi->rx_ring;
4034 rxr->rx_agg_prod = 0;
4035 rxr->rx_sw_agg_prod = 0;
4036 rxr->rx_next_cons = 0;
4041 static void bnxt_free_ntp_fltrs(struct bnxt *bp, bool irq_reinit)
4043 #ifdef CONFIG_RFS_ACCEL
4046 /* Under rtnl_lock and all our NAPIs have been disabled. It's
4047 * safe to delete the hash table.
4049 for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) {
4050 struct hlist_head *head;
4051 struct hlist_node *tmp;
4052 struct bnxt_ntuple_filter *fltr;
4054 head = &bp->ntp_fltr_hash_tbl[i];
4055 hlist_for_each_entry_safe(fltr, tmp, head, hash) {
4056 hlist_del(&fltr->hash);
4061 kfree(bp->ntp_fltr_bmap);
4062 bp->ntp_fltr_bmap = NULL;
4064 bp->ntp_fltr_count = 0;
4068 static int bnxt_alloc_ntp_fltrs(struct bnxt *bp)
4070 #ifdef CONFIG_RFS_ACCEL
4073 if (!(bp->flags & BNXT_FLAG_RFS))
4076 for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++)
4077 INIT_HLIST_HEAD(&bp->ntp_fltr_hash_tbl[i]);
4079 bp->ntp_fltr_count = 0;
4080 bp->ntp_fltr_bmap = kcalloc(BITS_TO_LONGS(BNXT_NTP_FLTR_MAX_FLTR),
4084 if (!bp->ntp_fltr_bmap)
4093 static void bnxt_free_mem(struct bnxt *bp, bool irq_re_init)
4095 bnxt_free_vnic_attributes(bp);
4096 bnxt_free_tx_rings(bp);
4097 bnxt_free_rx_rings(bp);
4098 bnxt_free_cp_rings(bp);
4099 bnxt_free_ntp_fltrs(bp, irq_re_init);
4101 bnxt_free_ring_stats(bp);
4102 if (!(bp->fw_cap & BNXT_FW_CAP_PORT_STATS_NO_RESET) ||
4103 test_bit(BNXT_STATE_IN_FW_RESET, &bp->state))
4104 bnxt_free_port_stats(bp);
4105 bnxt_free_ring_grps(bp);
4106 bnxt_free_vnics(bp);
4107 kfree(bp->tx_ring_map);
4108 bp->tx_ring_map = NULL;
4116 bnxt_clear_ring_indices(bp);
4120 static int bnxt_alloc_mem(struct bnxt *bp, bool irq_re_init)
4122 int i, j, rc, size, arr_size;
4126 /* Allocate bnapi mem pointer array and mem block for
4129 arr_size = L1_CACHE_ALIGN(sizeof(struct bnxt_napi *) *
4131 size = L1_CACHE_ALIGN(sizeof(struct bnxt_napi));
4132 bnapi = kzalloc(arr_size + size * bp->cp_nr_rings, GFP_KERNEL);
4138 for (i = 0; i < bp->cp_nr_rings; i++, bnapi += size) {
4139 bp->bnapi[i] = bnapi;
4140 bp->bnapi[i]->index = i;
4141 bp->bnapi[i]->bp = bp;
4142 if (bp->flags & BNXT_FLAG_CHIP_P5) {
4143 struct bnxt_cp_ring_info *cpr =
4144 &bp->bnapi[i]->cp_ring;
4146 cpr->cp_ring_struct.ring_mem.flags =
4147 BNXT_RMEM_RING_PTE_FLAG;
4151 bp->rx_ring = kcalloc(bp->rx_nr_rings,
4152 sizeof(struct bnxt_rx_ring_info),
4157 for (i = 0; i < bp->rx_nr_rings; i++) {
4158 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
4160 if (bp->flags & BNXT_FLAG_CHIP_P5) {
4161 rxr->rx_ring_struct.ring_mem.flags =
4162 BNXT_RMEM_RING_PTE_FLAG;
4163 rxr->rx_agg_ring_struct.ring_mem.flags =
4164 BNXT_RMEM_RING_PTE_FLAG;
4166 rxr->bnapi = bp->bnapi[i];
4167 bp->bnapi[i]->rx_ring = &bp->rx_ring[i];
4170 bp->tx_ring = kcalloc(bp->tx_nr_rings,
4171 sizeof(struct bnxt_tx_ring_info),
4176 bp->tx_ring_map = kcalloc(bp->tx_nr_rings, sizeof(u16),
4179 if (!bp->tx_ring_map)
4182 if (bp->flags & BNXT_FLAG_SHARED_RINGS)
4185 j = bp->rx_nr_rings;
4187 for (i = 0; i < bp->tx_nr_rings; i++, j++) {
4188 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
4190 if (bp->flags & BNXT_FLAG_CHIP_P5)
4191 txr->tx_ring_struct.ring_mem.flags =
4192 BNXT_RMEM_RING_PTE_FLAG;
4193 txr->bnapi = bp->bnapi[j];
4194 bp->bnapi[j]->tx_ring = txr;
4195 bp->tx_ring_map[i] = bp->tx_nr_rings_xdp + i;
4196 if (i >= bp->tx_nr_rings_xdp) {
4197 txr->txq_index = i - bp->tx_nr_rings_xdp;
4198 bp->bnapi[j]->tx_int = bnxt_tx_int;
4200 bp->bnapi[j]->flags |= BNXT_NAPI_FLAG_XDP;
4201 bp->bnapi[j]->tx_int = bnxt_tx_int_xdp;
4205 rc = bnxt_alloc_stats(bp);
4208 bnxt_init_stats(bp);
4210 rc = bnxt_alloc_ntp_fltrs(bp);
4214 rc = bnxt_alloc_vnics(bp);
4219 bnxt_init_ring_struct(bp);
4221 rc = bnxt_alloc_rx_rings(bp);
4225 rc = bnxt_alloc_tx_rings(bp);
4229 rc = bnxt_alloc_cp_rings(bp);
4233 bp->vnic_info[0].flags |= BNXT_VNIC_RSS_FLAG | BNXT_VNIC_MCAST_FLAG |
4234 BNXT_VNIC_UCAST_FLAG;
4235 rc = bnxt_alloc_vnic_attributes(bp);
4241 bnxt_free_mem(bp, true);
4245 static void bnxt_disable_int(struct bnxt *bp)
4252 for (i = 0; i < bp->cp_nr_rings; i++) {
4253 struct bnxt_napi *bnapi = bp->bnapi[i];
4254 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
4255 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct;
4257 if (ring->fw_ring_id != INVALID_HW_RING_ID)
4258 bnxt_db_nq(bp, &cpr->cp_db, cpr->cp_raw_cons);
4262 static int bnxt_cp_num_to_irq_num(struct bnxt *bp, int n)
4264 struct bnxt_napi *bnapi = bp->bnapi[n];
4265 struct bnxt_cp_ring_info *cpr;
4267 cpr = &bnapi->cp_ring;
4268 return cpr->cp_ring_struct.map_idx;
4271 static void bnxt_disable_int_sync(struct bnxt *bp)
4275 atomic_inc(&bp->intr_sem);
4277 bnxt_disable_int(bp);
4278 for (i = 0; i < bp->cp_nr_rings; i++) {
4279 int map_idx = bnxt_cp_num_to_irq_num(bp, i);
4281 synchronize_irq(bp->irq_tbl[map_idx].vector);
4285 static void bnxt_enable_int(struct bnxt *bp)
4289 atomic_set(&bp->intr_sem, 0);
4290 for (i = 0; i < bp->cp_nr_rings; i++) {
4291 struct bnxt_napi *bnapi = bp->bnapi[i];
4292 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
4294 bnxt_db_nq_arm(bp, &cpr->cp_db, cpr->cp_raw_cons);
4298 void bnxt_hwrm_cmd_hdr_init(struct bnxt *bp, void *request, u16 req_type,
4299 u16 cmpl_ring, u16 target_id)
4301 struct input *req = request;
4303 req->req_type = cpu_to_le16(req_type);
4304 req->cmpl_ring = cpu_to_le16(cmpl_ring);
4305 req->target_id = cpu_to_le16(target_id);
4306 if (bnxt_kong_hwrm_message(bp, req))
4307 req->resp_addr = cpu_to_le64(bp->hwrm_cmd_kong_resp_dma_addr);
4309 req->resp_addr = cpu_to_le64(bp->hwrm_cmd_resp_dma_addr);
4312 static int bnxt_hwrm_to_stderr(u32 hwrm_err)
4315 case HWRM_ERR_CODE_SUCCESS:
4317 case HWRM_ERR_CODE_RESOURCE_LOCKED:
4319 case HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED:
4321 case HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR:
4323 case HWRM_ERR_CODE_INVALID_PARAMS:
4324 case HWRM_ERR_CODE_INVALID_FLAGS:
4325 case HWRM_ERR_CODE_INVALID_ENABLES:
4326 case HWRM_ERR_CODE_UNSUPPORTED_TLV:
4327 case HWRM_ERR_CODE_UNSUPPORTED_OPTION_ERR:
4329 case HWRM_ERR_CODE_NO_BUFFER:
4331 case HWRM_ERR_CODE_HOT_RESET_PROGRESS:
4332 case HWRM_ERR_CODE_BUSY:
4334 case HWRM_ERR_CODE_CMD_NOT_SUPPORTED:
4341 static int bnxt_hwrm_do_send_msg(struct bnxt *bp, void *msg, u32 msg_len,
4342 int timeout, bool silent)
4344 int i, intr_process, rc, tmo_count;
4345 struct input *req = msg;
4348 u16 cp_ring_id, len = 0;
4349 struct hwrm_err_output *resp = bp->hwrm_cmd_resp_addr;
4350 u16 max_req_len = BNXT_HWRM_MAX_REQ_LEN;
4351 struct hwrm_short_input short_input = {0};
4352 u32 doorbell_offset = BNXT_GRCPF_REG_CHIMP_COMM_TRIGGER;
4353 u32 bar_offset = BNXT_GRCPF_REG_CHIMP_COMM;
4354 u16 dst = BNXT_HWRM_CHNL_CHIMP;
4356 if (BNXT_NO_FW_ACCESS(bp) &&
4357 le16_to_cpu(req->req_type) != HWRM_FUNC_RESET)
4360 if (msg_len > BNXT_HWRM_MAX_REQ_LEN) {
4361 if (msg_len > bp->hwrm_max_ext_req_len ||
4362 !bp->hwrm_short_cmd_req_addr)
4366 if (bnxt_hwrm_kong_chnl(bp, req)) {
4367 dst = BNXT_HWRM_CHNL_KONG;
4368 bar_offset = BNXT_GRCPF_REG_KONG_COMM;
4369 doorbell_offset = BNXT_GRCPF_REG_KONG_COMM_TRIGGER;
4370 resp = bp->hwrm_cmd_kong_resp_addr;
4373 memset(resp, 0, PAGE_SIZE);
4374 cp_ring_id = le16_to_cpu(req->cmpl_ring);
4375 intr_process = (cp_ring_id == INVALID_HW_RING_ID) ? 0 : 1;
4377 req->seq_id = cpu_to_le16(bnxt_get_hwrm_seq_id(bp, dst));
4378 /* currently supports only one outstanding message */
4380 bp->hwrm_intr_seq_id = le16_to_cpu(req->seq_id);
4382 if ((bp->fw_cap & BNXT_FW_CAP_SHORT_CMD) ||
4383 msg_len > BNXT_HWRM_MAX_REQ_LEN) {
4384 void *short_cmd_req = bp->hwrm_short_cmd_req_addr;
4387 /* Set boundary for maximum extended request length for short
4388 * cmd format. If passed up from device use the max supported
4389 * internal req length.
4391 max_msg_len = bp->hwrm_max_ext_req_len;
4393 memcpy(short_cmd_req, req, msg_len);
4394 if (msg_len < max_msg_len)
4395 memset(short_cmd_req + msg_len, 0,
4396 max_msg_len - msg_len);
4398 short_input.req_type = req->req_type;
4399 short_input.signature =
4400 cpu_to_le16(SHORT_REQ_SIGNATURE_SHORT_CMD);
4401 short_input.size = cpu_to_le16(msg_len);
4402 short_input.req_addr =
4403 cpu_to_le64(bp->hwrm_short_cmd_req_dma_addr);
4405 data = (u32 *)&short_input;
4406 msg_len = sizeof(short_input);
4408 /* Sync memory write before updating doorbell */
4411 max_req_len = BNXT_HWRM_SHORT_REQ_LEN;
4414 /* Write request msg to hwrm channel */
4415 __iowrite32_copy(bp->bar0 + bar_offset, data, msg_len / 4);
4417 for (i = msg_len; i < max_req_len; i += 4)
4418 writel(0, bp->bar0 + bar_offset + i);
4420 /* Ring channel doorbell */
4421 writel(1, bp->bar0 + doorbell_offset);
4423 if (!pci_is_enabled(bp->pdev))
4427 timeout = DFLT_HWRM_CMD_TIMEOUT;
4428 /* convert timeout to usec */
4432 /* Short timeout for the first few iterations:
4433 * number of loops = number of loops for short timeout +
4434 * number of loops for standard timeout.
4436 tmo_count = HWRM_SHORT_TIMEOUT_COUNTER;
4437 timeout = timeout - HWRM_SHORT_MIN_TIMEOUT * HWRM_SHORT_TIMEOUT_COUNTER;
4438 tmo_count += DIV_ROUND_UP(timeout, HWRM_MIN_TIMEOUT);
4441 u16 seq_id = bp->hwrm_intr_seq_id;
4443 /* Wait until hwrm response cmpl interrupt is processed */
4444 while (bp->hwrm_intr_seq_id != (u16)~seq_id &&
4446 /* Abort the wait for completion if the FW health
4449 if (test_bit(BNXT_STATE_FW_FATAL_COND, &bp->state))
4451 /* on first few passes, just barely sleep */
4452 if (i < HWRM_SHORT_TIMEOUT_COUNTER)
4453 usleep_range(HWRM_SHORT_MIN_TIMEOUT,
4454 HWRM_SHORT_MAX_TIMEOUT);
4456 usleep_range(HWRM_MIN_TIMEOUT,
4460 if (bp->hwrm_intr_seq_id != (u16)~seq_id) {
4462 netdev_err(bp->dev, "Resp cmpl intr err msg: 0x%x\n",
4463 le16_to_cpu(req->req_type));
4466 len = le16_to_cpu(resp->resp_len);
4467 valid = ((u8 *)resp) + len - 1;
4471 /* Check if response len is updated */
4472 for (i = 0; i < tmo_count; i++) {
4473 /* Abort the wait for completion if the FW health
4476 if (test_bit(BNXT_STATE_FW_FATAL_COND, &bp->state))
4478 len = le16_to_cpu(resp->resp_len);
4481 /* on first few passes, just barely sleep */
4482 if (i < HWRM_SHORT_TIMEOUT_COUNTER)
4483 usleep_range(HWRM_SHORT_MIN_TIMEOUT,
4484 HWRM_SHORT_MAX_TIMEOUT);
4486 usleep_range(HWRM_MIN_TIMEOUT,
4490 if (i >= tmo_count) {
4492 netdev_err(bp->dev, "Error (timeout: %d) msg {0x%x 0x%x} len:%d\n",
4493 HWRM_TOTAL_TIMEOUT(i),
4494 le16_to_cpu(req->req_type),
4495 le16_to_cpu(req->seq_id), len);
4499 /* Last byte of resp contains valid bit */
4500 valid = ((u8 *)resp) + len - 1;
4501 for (j = 0; j < HWRM_VALID_BIT_DELAY_USEC; j++) {
4502 /* make sure we read from updated DMA memory */
4509 if (j >= HWRM_VALID_BIT_DELAY_USEC) {
4511 netdev_err(bp->dev, "Error (timeout: %d) msg {0x%x 0x%x} len:%d v:%d\n",
4512 HWRM_TOTAL_TIMEOUT(i),
4513 le16_to_cpu(req->req_type),
4514 le16_to_cpu(req->seq_id), len,
4520 /* Zero valid bit for compatibility. Valid bit in an older spec
4521 * may become a new field in a newer spec. We must make sure that
4522 * a new field not implemented by old spec will read zero.
4525 rc = le16_to_cpu(resp->error_code);
4527 netdev_err(bp->dev, "hwrm req_type 0x%x seq id 0x%x error 0x%x\n",
4528 le16_to_cpu(resp->req_type),
4529 le16_to_cpu(resp->seq_id), rc);
4530 return bnxt_hwrm_to_stderr(rc);
4533 int _hwrm_send_message(struct bnxt *bp, void *msg, u32 msg_len, int timeout)
4535 return bnxt_hwrm_do_send_msg(bp, msg, msg_len, timeout, false);
4538 int _hwrm_send_message_silent(struct bnxt *bp, void *msg, u32 msg_len,
4541 return bnxt_hwrm_do_send_msg(bp, msg, msg_len, timeout, true);
4544 int hwrm_send_message(struct bnxt *bp, void *msg, u32 msg_len, int timeout)
4548 mutex_lock(&bp->hwrm_cmd_lock);
4549 rc = _hwrm_send_message(bp, msg, msg_len, timeout);
4550 mutex_unlock(&bp->hwrm_cmd_lock);
4554 int hwrm_send_message_silent(struct bnxt *bp, void *msg, u32 msg_len,
4559 mutex_lock(&bp->hwrm_cmd_lock);
4560 rc = bnxt_hwrm_do_send_msg(bp, msg, msg_len, timeout, true);
4561 mutex_unlock(&bp->hwrm_cmd_lock);
4565 int bnxt_hwrm_func_drv_rgtr(struct bnxt *bp, unsigned long *bmap, int bmap_size,
4568 struct hwrm_func_drv_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
4569 struct hwrm_func_drv_rgtr_input req = {0};
4570 DECLARE_BITMAP(async_events_bmap, 256);
4571 u32 *events = (u32 *)async_events_bmap;
4575 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_RGTR, -1, -1);
4578 cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_OS_TYPE |
4579 FUNC_DRV_RGTR_REQ_ENABLES_VER |
4580 FUNC_DRV_RGTR_REQ_ENABLES_ASYNC_EVENT_FWD);
4582 req.os_type = cpu_to_le16(FUNC_DRV_RGTR_REQ_OS_TYPE_LINUX);
4583 flags = FUNC_DRV_RGTR_REQ_FLAGS_16BIT_VER_MODE;
4584 if (bp->fw_cap & BNXT_FW_CAP_HOT_RESET)
4585 flags |= FUNC_DRV_RGTR_REQ_FLAGS_HOT_RESET_SUPPORT;
4586 if (bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY)
4587 flags |= FUNC_DRV_RGTR_REQ_FLAGS_ERROR_RECOVERY_SUPPORT |
4588 FUNC_DRV_RGTR_REQ_FLAGS_MASTER_SUPPORT;
4589 req.flags = cpu_to_le32(flags);
4590 req.ver_maj_8b = DRV_VER_MAJ;
4591 req.ver_min_8b = DRV_VER_MIN;
4592 req.ver_upd_8b = DRV_VER_UPD;
4593 req.ver_maj = cpu_to_le16(DRV_VER_MAJ);
4594 req.ver_min = cpu_to_le16(DRV_VER_MIN);
4595 req.ver_upd = cpu_to_le16(DRV_VER_UPD);
4601 memset(data, 0, sizeof(data));
4602 for (i = 0; i < ARRAY_SIZE(bnxt_vf_req_snif); i++) {
4603 u16 cmd = bnxt_vf_req_snif[i];
4604 unsigned int bit, idx;
4608 data[idx] |= 1 << bit;
4611 for (i = 0; i < 8; i++)
4612 req.vf_req_fwd[i] = cpu_to_le32(data[i]);
4615 cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_VF_REQ_FWD);
4618 if (bp->fw_cap & BNXT_FW_CAP_OVS_64BIT_HANDLE)
4619 req.flags |= cpu_to_le32(
4620 FUNC_DRV_RGTR_REQ_FLAGS_FLOW_HANDLE_64BIT_MODE);
4622 memset(async_events_bmap, 0, sizeof(async_events_bmap));
4623 for (i = 0; i < ARRAY_SIZE(bnxt_async_events_arr); i++) {
4624 u16 event_id = bnxt_async_events_arr[i];
4626 if (event_id == ASYNC_EVENT_CMPL_EVENT_ID_ERROR_RECOVERY &&
4627 !(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY))
4629 __set_bit(bnxt_async_events_arr[i], async_events_bmap);
4631 if (bmap && bmap_size) {
4632 for (i = 0; i < bmap_size; i++) {
4633 if (test_bit(i, bmap))
4634 __set_bit(i, async_events_bmap);
4637 for (i = 0; i < 8; i++)
4638 req.async_event_fwd[i] |= cpu_to_le32(events[i]);
4642 cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_ASYNC_EVENT_FWD);
4644 mutex_lock(&bp->hwrm_cmd_lock);
4645 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4647 set_bit(BNXT_STATE_DRV_REGISTERED, &bp->state);
4649 cpu_to_le32(FUNC_DRV_RGTR_RESP_FLAGS_IF_CHANGE_SUPPORTED))
4650 bp->fw_cap |= BNXT_FW_CAP_IF_CHANGE;
4652 mutex_unlock(&bp->hwrm_cmd_lock);
4656 static int bnxt_hwrm_func_drv_unrgtr(struct bnxt *bp)
4658 struct hwrm_func_drv_unrgtr_input req = {0};
4660 if (!test_and_clear_bit(BNXT_STATE_DRV_REGISTERED, &bp->state))
4663 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_UNRGTR, -1, -1);
4664 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4667 static int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, u8 tunnel_type)
4670 struct hwrm_tunnel_dst_port_free_input req = {0};
4672 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_TUNNEL_DST_PORT_FREE, -1, -1);
4673 req.tunnel_type = tunnel_type;
4675 switch (tunnel_type) {
4676 case TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN:
4677 req.tunnel_dst_port_id = cpu_to_le16(bp->vxlan_fw_dst_port_id);
4678 bp->vxlan_fw_dst_port_id = INVALID_HW_RING_ID;
4680 case TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE:
4681 req.tunnel_dst_port_id = cpu_to_le16(bp->nge_fw_dst_port_id);
4682 bp->nge_fw_dst_port_id = INVALID_HW_RING_ID;
4688 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4690 netdev_err(bp->dev, "hwrm_tunnel_dst_port_free failed. rc:%d\n",
4695 static int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, __be16 port,
4699 struct hwrm_tunnel_dst_port_alloc_input req = {0};
4700 struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr;
4702 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_TUNNEL_DST_PORT_ALLOC, -1, -1);
4704 req.tunnel_type = tunnel_type;
4705 req.tunnel_dst_port_val = port;
4707 mutex_lock(&bp->hwrm_cmd_lock);
4708 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4710 netdev_err(bp->dev, "hwrm_tunnel_dst_port_alloc failed. rc:%d\n",
4715 switch (tunnel_type) {
4716 case TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN:
4717 bp->vxlan_fw_dst_port_id =
4718 le16_to_cpu(resp->tunnel_dst_port_id);
4720 case TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_GENEVE:
4721 bp->nge_fw_dst_port_id = le16_to_cpu(resp->tunnel_dst_port_id);
4728 mutex_unlock(&bp->hwrm_cmd_lock);
4732 static int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp, u16 vnic_id)
4734 struct hwrm_cfa_l2_set_rx_mask_input req = {0};
4735 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
4737 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_SET_RX_MASK, -1, -1);
4738 req.vnic_id = cpu_to_le32(vnic->fw_vnic_id);
4740 req.num_mc_entries = cpu_to_le32(vnic->mc_list_count);
4741 req.mc_tbl_addr = cpu_to_le64(vnic->mc_list_mapping);
4742 req.mask = cpu_to_le32(vnic->rx_mask);
4743 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4746 #ifdef CONFIG_RFS_ACCEL
4747 static int bnxt_hwrm_cfa_ntuple_filter_free(struct bnxt *bp,
4748 struct bnxt_ntuple_filter *fltr)
4750 struct hwrm_cfa_ntuple_filter_free_input req = {0};
4752 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_NTUPLE_FILTER_FREE, -1, -1);
4753 req.ntuple_filter_id = fltr->filter_id;
4754 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4757 #define BNXT_NTP_FLTR_FLAGS \
4758 (CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID | \
4759 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_ETHERTYPE | \
4760 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_MACADDR | \
4761 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IPADDR_TYPE | \
4762 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR | \
4763 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR_MASK | \
4764 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR | \
4765 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR_MASK | \
4766 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IP_PROTOCOL | \
4767 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT | \
4768 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT_MASK | \
4769 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT | \
4770 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT_MASK | \
4771 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_ID)
4773 #define BNXT_NTP_TUNNEL_FLTR_FLAG \
4774 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE
4776 static int bnxt_hwrm_cfa_ntuple_filter_alloc(struct bnxt *bp,
4777 struct bnxt_ntuple_filter *fltr)
4779 struct hwrm_cfa_ntuple_filter_alloc_input req = {0};
4780 struct hwrm_cfa_ntuple_filter_alloc_output *resp;
4781 struct flow_keys *keys = &fltr->fkeys;
4782 struct bnxt_vnic_info *vnic;
4786 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_NTUPLE_FILTER_ALLOC, -1, -1);
4787 req.l2_filter_id = bp->vnic_info[0].fw_l2_filter_id[fltr->l2_fltr_idx];
4789 if (bp->fw_cap & BNXT_FW_CAP_CFA_RFS_RING_TBL_IDX_V2) {
4790 flags = CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_DEST_RFS_RING_IDX;
4791 req.dst_id = cpu_to_le16(fltr->rxq);
4793 vnic = &bp->vnic_info[fltr->rxq + 1];
4794 req.dst_id = cpu_to_le16(vnic->fw_vnic_id);
4796 req.flags = cpu_to_le32(flags);
4797 req.enables = cpu_to_le32(BNXT_NTP_FLTR_FLAGS);
4799 req.ethertype = htons(ETH_P_IP);
4800 memcpy(req.src_macaddr, fltr->src_mac_addr, ETH_ALEN);
4801 req.ip_addr_type = CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV4;
4802 req.ip_protocol = keys->basic.ip_proto;
4804 if (keys->basic.n_proto == htons(ETH_P_IPV6)) {
4807 req.ethertype = htons(ETH_P_IPV6);
4809 CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6;
4810 *(struct in6_addr *)&req.src_ipaddr[0] =
4811 keys->addrs.v6addrs.src;
4812 *(struct in6_addr *)&req.dst_ipaddr[0] =
4813 keys->addrs.v6addrs.dst;
4814 for (i = 0; i < 4; i++) {
4815 req.src_ipaddr_mask[i] = cpu_to_be32(0xffffffff);
4816 req.dst_ipaddr_mask[i] = cpu_to_be32(0xffffffff);
4819 req.src_ipaddr[0] = keys->addrs.v4addrs.src;
4820 req.src_ipaddr_mask[0] = cpu_to_be32(0xffffffff);
4821 req.dst_ipaddr[0] = keys->addrs.v4addrs.dst;
4822 req.dst_ipaddr_mask[0] = cpu_to_be32(0xffffffff);
4824 if (keys->control.flags & FLOW_DIS_ENCAPSULATION) {
4825 req.enables |= cpu_to_le32(BNXT_NTP_TUNNEL_FLTR_FLAG);
4827 CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL;
4830 req.src_port = keys->ports.src;
4831 req.src_port_mask = cpu_to_be16(0xffff);
4832 req.dst_port = keys->ports.dst;
4833 req.dst_port_mask = cpu_to_be16(0xffff);
4835 mutex_lock(&bp->hwrm_cmd_lock);
4836 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4838 resp = bnxt_get_hwrm_resp_addr(bp, &req);
4839 fltr->filter_id = resp->ntuple_filter_id;
4841 mutex_unlock(&bp->hwrm_cmd_lock);
4846 static int bnxt_hwrm_set_vnic_filter(struct bnxt *bp, u16 vnic_id, u16 idx,
4850 struct hwrm_cfa_l2_filter_alloc_input req = {0};
4851 struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
4853 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_FILTER_ALLOC, -1, -1);
4854 req.flags = cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX);
4855 if (!BNXT_CHIP_TYPE_NITRO_A0(bp))
4857 cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_FLAGS_OUTERMOST);
4858 req.dst_id = cpu_to_le16(bp->vnic_info[vnic_id].fw_vnic_id);
4860 cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR |
4861 CFA_L2_FILTER_ALLOC_REQ_ENABLES_DST_ID |
4862 CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR_MASK);
4863 memcpy(req.l2_addr, mac_addr, ETH_ALEN);
4864 req.l2_addr_mask[0] = 0xff;
4865 req.l2_addr_mask[1] = 0xff;
4866 req.l2_addr_mask[2] = 0xff;
4867 req.l2_addr_mask[3] = 0xff;
4868 req.l2_addr_mask[4] = 0xff;
4869 req.l2_addr_mask[5] = 0xff;
4871 mutex_lock(&bp->hwrm_cmd_lock);
4872 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4874 bp->vnic_info[vnic_id].fw_l2_filter_id[idx] =
4876 mutex_unlock(&bp->hwrm_cmd_lock);
4880 static int bnxt_hwrm_clear_vnic_filter(struct bnxt *bp)
4882 u16 i, j, num_of_vnics = 1; /* only vnic 0 supported */
4885 /* Any associated ntuple filters will also be cleared by firmware. */
4886 mutex_lock(&bp->hwrm_cmd_lock);
4887 for (i = 0; i < num_of_vnics; i++) {
4888 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
4890 for (j = 0; j < vnic->uc_filter_count; j++) {
4891 struct hwrm_cfa_l2_filter_free_input req = {0};
4893 bnxt_hwrm_cmd_hdr_init(bp, &req,
4894 HWRM_CFA_L2_FILTER_FREE, -1, -1);
4896 req.l2_filter_id = vnic->fw_l2_filter_id[j];
4898 rc = _hwrm_send_message(bp, &req, sizeof(req),
4901 vnic->uc_filter_count = 0;
4903 mutex_unlock(&bp->hwrm_cmd_lock);
4908 static int bnxt_hwrm_vnic_set_tpa(struct bnxt *bp, u16 vnic_id, u32 tpa_flags)
4910 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
4911 u16 max_aggs = VNIC_TPA_CFG_REQ_MAX_AGGS_MAX;
4912 struct hwrm_vnic_tpa_cfg_input req = {0};
4914 if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
4917 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_TPA_CFG, -1, -1);
4920 u16 mss = bp->dev->mtu - 40;
4921 u32 nsegs, n, segs = 0, flags;
4923 flags = VNIC_TPA_CFG_REQ_FLAGS_TPA |
4924 VNIC_TPA_CFG_REQ_FLAGS_ENCAP_TPA |
4925 VNIC_TPA_CFG_REQ_FLAGS_RSC_WND_UPDATE |
4926 VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_ECN |
4927 VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_SAME_GRE_SEQ;
4928 if (tpa_flags & BNXT_FLAG_GRO)
4929 flags |= VNIC_TPA_CFG_REQ_FLAGS_GRO;
4931 req.flags = cpu_to_le32(flags);
4934 cpu_to_le32(VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_SEGS |
4935 VNIC_TPA_CFG_REQ_ENABLES_MAX_AGGS |
4936 VNIC_TPA_CFG_REQ_ENABLES_MIN_AGG_LEN);
4938 /* Number of segs are log2 units, and first packet is not
4939 * included as part of this units.
4941 if (mss <= BNXT_RX_PAGE_SIZE) {
4942 n = BNXT_RX_PAGE_SIZE / mss;
4943 nsegs = (MAX_SKB_FRAGS - 1) * n;
4945 n = mss / BNXT_RX_PAGE_SIZE;
4946 if (mss & (BNXT_RX_PAGE_SIZE - 1))
4948 nsegs = (MAX_SKB_FRAGS - n) / n;
4951 if (bp->flags & BNXT_FLAG_CHIP_P5) {
4952 segs = MAX_TPA_SEGS_P5;
4953 max_aggs = bp->max_tpa;
4955 segs = ilog2(nsegs);
4957 req.max_agg_segs = cpu_to_le16(segs);
4958 req.max_aggs = cpu_to_le16(max_aggs);
4960 req.min_agg_len = cpu_to_le32(512);
4962 req.vnic_id = cpu_to_le16(vnic->fw_vnic_id);
4964 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4967 static u16 bnxt_cp_ring_from_grp(struct bnxt *bp, struct bnxt_ring_struct *ring)
4969 struct bnxt_ring_grp_info *grp_info;
4971 grp_info = &bp->grp_info[ring->grp_idx];
4972 return grp_info->cp_fw_ring_id;
4975 static u16 bnxt_cp_ring_for_rx(struct bnxt *bp, struct bnxt_rx_ring_info *rxr)
4977 if (bp->flags & BNXT_FLAG_CHIP_P5) {
4978 struct bnxt_napi *bnapi = rxr->bnapi;
4979 struct bnxt_cp_ring_info *cpr;
4981 cpr = bnapi->cp_ring.cp_ring_arr[BNXT_RX_HDL];
4982 return cpr->cp_ring_struct.fw_ring_id;
4984 return bnxt_cp_ring_from_grp(bp, &rxr->rx_ring_struct);
4988 static u16 bnxt_cp_ring_for_tx(struct bnxt *bp, struct bnxt_tx_ring_info *txr)
4990 if (bp->flags & BNXT_FLAG_CHIP_P5) {
4991 struct bnxt_napi *bnapi = txr->bnapi;
4992 struct bnxt_cp_ring_info *cpr;
4994 cpr = bnapi->cp_ring.cp_ring_arr[BNXT_TX_HDL];
4995 return cpr->cp_ring_struct.fw_ring_id;
4997 return bnxt_cp_ring_from_grp(bp, &txr->tx_ring_struct);
5001 static int bnxt_alloc_rss_indir_tbl(struct bnxt *bp)
5005 if (bp->flags & BNXT_FLAG_CHIP_P5)
5006 entries = BNXT_MAX_RSS_TABLE_ENTRIES_P5;
5008 entries = HW_HASH_INDEX_SIZE;
5010 bp->rss_indir_tbl_entries = entries;
5011 bp->rss_indir_tbl = kmalloc_array(entries, sizeof(*bp->rss_indir_tbl),
5013 if (!bp->rss_indir_tbl)
5018 static void bnxt_set_dflt_rss_indir_tbl(struct bnxt *bp)
5020 u16 max_rings, max_entries, pad, i;
5022 if (!bp->rx_nr_rings)
5025 if (BNXT_CHIP_TYPE_NITRO_A0(bp))
5026 max_rings = bp->rx_nr_rings - 1;
5028 max_rings = bp->rx_nr_rings;
5030 max_entries = bnxt_get_rxfh_indir_size(bp->dev);
5032 for (i = 0; i < max_entries; i++)
5033 bp->rss_indir_tbl[i] = ethtool_rxfh_indir_default(i, max_rings);
5035 pad = bp->rss_indir_tbl_entries - max_entries;
5037 memset(&bp->rss_indir_tbl[i], 0, pad * sizeof(u16));
5040 static u16 bnxt_get_max_rss_ring(struct bnxt *bp)
5042 u16 i, tbl_size, max_ring = 0;
5044 if (!bp->rss_indir_tbl)
5047 tbl_size = bnxt_get_rxfh_indir_size(bp->dev);
5048 for (i = 0; i < tbl_size; i++)
5049 max_ring = max(max_ring, bp->rss_indir_tbl[i]);
5053 int bnxt_get_nr_rss_ctxs(struct bnxt *bp, int rx_rings)
5055 if (bp->flags & BNXT_FLAG_CHIP_P5)
5056 return DIV_ROUND_UP(rx_rings, BNXT_RSS_TABLE_ENTRIES_P5);
5057 if (BNXT_CHIP_TYPE_NITRO_A0(bp))
5062 static void __bnxt_fill_hw_rss_tbl(struct bnxt *bp, struct bnxt_vnic_info *vnic)
5064 bool no_rss = !(vnic->flags & BNXT_VNIC_RSS_FLAG);
5067 /* Fill the RSS indirection table with ring group ids */
5068 for (i = 0, j = 0; i < HW_HASH_INDEX_SIZE; i++) {
5070 j = bp->rss_indir_tbl[i];
5071 vnic->rss_table[i] = cpu_to_le16(vnic->fw_grp_ids[j]);
5075 static void __bnxt_fill_hw_rss_tbl_p5(struct bnxt *bp,
5076 struct bnxt_vnic_info *vnic)
5078 __le16 *ring_tbl = vnic->rss_table;
5079 struct bnxt_rx_ring_info *rxr;
5082 tbl_size = bnxt_get_rxfh_indir_size(bp->dev);
5084 for (i = 0; i < tbl_size; i++) {
5087 j = bp->rss_indir_tbl[i];
5088 rxr = &bp->rx_ring[j];
5090 ring_id = rxr->rx_ring_struct.fw_ring_id;
5091 *ring_tbl++ = cpu_to_le16(ring_id);
5092 ring_id = bnxt_cp_ring_for_rx(bp, rxr);
5093 *ring_tbl++ = cpu_to_le16(ring_id);
5097 static void bnxt_fill_hw_rss_tbl(struct bnxt *bp, struct bnxt_vnic_info *vnic)
5099 if (bp->flags & BNXT_FLAG_CHIP_P5)
5100 __bnxt_fill_hw_rss_tbl_p5(bp, vnic);
5102 __bnxt_fill_hw_rss_tbl(bp, vnic);
5105 static int bnxt_hwrm_vnic_set_rss(struct bnxt *bp, u16 vnic_id, bool set_rss)
5107 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
5108 struct hwrm_vnic_rss_cfg_input req = {0};
5110 if ((bp->flags & BNXT_FLAG_CHIP_P5) ||
5111 vnic->fw_rss_cos_lb_ctx[0] == INVALID_HW_RING_ID)
5114 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_CFG, -1, -1);
5116 bnxt_fill_hw_rss_tbl(bp, vnic);
5117 req.hash_type = cpu_to_le32(bp->rss_hash_cfg);
5118 req.hash_mode_flags = VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_DEFAULT;
5119 req.ring_grp_tbl_addr = cpu_to_le64(vnic->rss_table_dma_addr);
5120 req.hash_key_tbl_addr =
5121 cpu_to_le64(vnic->rss_hash_key_dma_addr);
5123 req.rss_ctx_idx = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[0]);
5124 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5127 static int bnxt_hwrm_vnic_set_rss_p5(struct bnxt *bp, u16 vnic_id, bool set_rss)
5129 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
5130 struct hwrm_vnic_rss_cfg_input req = {0};
5131 dma_addr_t ring_tbl_map;
5134 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_CFG, -1, -1);
5135 req.vnic_id = cpu_to_le16(vnic->fw_vnic_id);
5137 hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5140 bnxt_fill_hw_rss_tbl(bp, vnic);
5141 req.hash_type = cpu_to_le32(bp->rss_hash_cfg);
5142 req.hash_mode_flags = VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_DEFAULT;
5143 req.hash_key_tbl_addr = cpu_to_le64(vnic->rss_hash_key_dma_addr);
5144 ring_tbl_map = vnic->rss_table_dma_addr;
5145 nr_ctxs = bnxt_get_nr_rss_ctxs(bp, bp->rx_nr_rings);
5146 for (i = 0; i < nr_ctxs; ring_tbl_map += BNXT_RSS_TABLE_SIZE_P5, i++) {
5149 req.ring_grp_tbl_addr = cpu_to_le64(ring_tbl_map);
5150 req.ring_table_pair_index = i;
5151 req.rss_ctx_idx = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[i]);
5152 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5159 static int bnxt_hwrm_vnic_set_hds(struct bnxt *bp, u16 vnic_id)
5161 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
5162 struct hwrm_vnic_plcmodes_cfg_input req = {0};
5164 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_PLCMODES_CFG, -1, -1);
5165 req.flags = cpu_to_le32(VNIC_PLCMODES_CFG_REQ_FLAGS_JUMBO_PLACEMENT |
5166 VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV4 |
5167 VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV6);
5169 cpu_to_le32(VNIC_PLCMODES_CFG_REQ_ENABLES_JUMBO_THRESH_VALID |
5170 VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_THRESHOLD_VALID);
5171 /* thresholds not implemented in firmware yet */
5172 req.jumbo_thresh = cpu_to_le16(bp->rx_copy_thresh);
5173 req.hds_threshold = cpu_to_le16(bp->rx_copy_thresh);
5174 req.vnic_id = cpu_to_le32(vnic->fw_vnic_id);
5175 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5178 static void bnxt_hwrm_vnic_ctx_free_one(struct bnxt *bp, u16 vnic_id,
5181 struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {0};
5183 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_COS_LB_CTX_FREE, -1, -1);
5184 req.rss_cos_lb_ctx_id =
5185 cpu_to_le16(bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[ctx_idx]);
5187 hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5188 bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[ctx_idx] = INVALID_HW_RING_ID;
5191 static void bnxt_hwrm_vnic_ctx_free(struct bnxt *bp)
5195 for (i = 0; i < bp->nr_vnics; i++) {
5196 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
5198 for (j = 0; j < BNXT_MAX_CTX_PER_VNIC; j++) {
5199 if (vnic->fw_rss_cos_lb_ctx[j] != INVALID_HW_RING_ID)
5200 bnxt_hwrm_vnic_ctx_free_one(bp, i, j);
5203 bp->rsscos_nr_ctxs = 0;
5206 static int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp, u16 vnic_id, u16 ctx_idx)
5209 struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {0};
5210 struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp =
5211 bp->hwrm_cmd_resp_addr;
5213 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_COS_LB_CTX_ALLOC, -1,
5216 mutex_lock(&bp->hwrm_cmd_lock);
5217 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5219 bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[ctx_idx] =
5220 le16_to_cpu(resp->rss_cos_lb_ctx_id);
5221 mutex_unlock(&bp->hwrm_cmd_lock);
5226 static u32 bnxt_get_roce_vnic_mode(struct bnxt *bp)
5228 if (bp->flags & BNXT_FLAG_ROCE_MIRROR_CAP)
5229 return VNIC_CFG_REQ_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_MODE;
5230 return VNIC_CFG_REQ_FLAGS_ROCE_DUAL_VNIC_MODE;
5233 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, u16 vnic_id)
5235 unsigned int ring = 0, grp_idx;
5236 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
5237 struct hwrm_vnic_cfg_input req = {0};
5240 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_CFG, -1, -1);
5242 if (bp->flags & BNXT_FLAG_CHIP_P5) {
5243 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[0];
5245 req.default_rx_ring_id =
5246 cpu_to_le16(rxr->rx_ring_struct.fw_ring_id);
5247 req.default_cmpl_ring_id =
5248 cpu_to_le16(bnxt_cp_ring_for_rx(bp, rxr));
5250 cpu_to_le32(VNIC_CFG_REQ_ENABLES_DEFAULT_RX_RING_ID |
5251 VNIC_CFG_REQ_ENABLES_DEFAULT_CMPL_RING_ID);
5254 req.enables = cpu_to_le32(VNIC_CFG_REQ_ENABLES_DFLT_RING_GRP);
5255 /* Only RSS support for now TBD: COS & LB */
5256 if (vnic->fw_rss_cos_lb_ctx[0] != INVALID_HW_RING_ID) {
5257 req.rss_rule = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[0]);
5258 req.enables |= cpu_to_le32(VNIC_CFG_REQ_ENABLES_RSS_RULE |
5259 VNIC_CFG_REQ_ENABLES_MRU);
5260 } else if (vnic->flags & BNXT_VNIC_RFS_NEW_RSS_FLAG) {
5262 cpu_to_le16(bp->vnic_info[0].fw_rss_cos_lb_ctx[0]);
5263 req.enables |= cpu_to_le32(VNIC_CFG_REQ_ENABLES_RSS_RULE |
5264 VNIC_CFG_REQ_ENABLES_MRU);
5265 req.flags |= cpu_to_le32(VNIC_CFG_REQ_FLAGS_RSS_DFLT_CR_MODE);
5267 req.rss_rule = cpu_to_le16(0xffff);
5270 if (BNXT_CHIP_TYPE_NITRO_A0(bp) &&
5271 (vnic->fw_rss_cos_lb_ctx[0] != INVALID_HW_RING_ID)) {
5272 req.cos_rule = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[1]);
5273 req.enables |= cpu_to_le32(VNIC_CFG_REQ_ENABLES_COS_RULE);
5275 req.cos_rule = cpu_to_le16(0xffff);
5278 if (vnic->flags & BNXT_VNIC_RSS_FLAG)
5280 else if (vnic->flags & BNXT_VNIC_RFS_FLAG)
5282 else if ((vnic_id == 1) && BNXT_CHIP_TYPE_NITRO_A0(bp))
5283 ring = bp->rx_nr_rings - 1;
5285 grp_idx = bp->rx_ring[ring].bnapi->index;
5286 req.dflt_ring_grp = cpu_to_le16(bp->grp_info[grp_idx].fw_grp_id);
5287 req.lb_rule = cpu_to_le16(0xffff);
5289 req.mru = cpu_to_le16(bp->dev->mtu + ETH_HLEN + VLAN_HLEN);
5291 req.vnic_id = cpu_to_le16(vnic->fw_vnic_id);
5292 #ifdef CONFIG_BNXT_SRIOV
5294 def_vlan = bp->vf.vlan;
5296 if ((bp->flags & BNXT_FLAG_STRIP_VLAN) || def_vlan)
5297 req.flags |= cpu_to_le32(VNIC_CFG_REQ_FLAGS_VLAN_STRIP_MODE);
5298 if (!vnic_id && bnxt_ulp_registered(bp->edev, BNXT_ROCE_ULP))
5299 req.flags |= cpu_to_le32(bnxt_get_roce_vnic_mode(bp));
5301 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5304 static void bnxt_hwrm_vnic_free_one(struct bnxt *bp, u16 vnic_id)
5306 if (bp->vnic_info[vnic_id].fw_vnic_id != INVALID_HW_RING_ID) {
5307 struct hwrm_vnic_free_input req = {0};
5309 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_FREE, -1, -1);
5311 cpu_to_le32(bp->vnic_info[vnic_id].fw_vnic_id);
5313 hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5314 bp->vnic_info[vnic_id].fw_vnic_id = INVALID_HW_RING_ID;
5318 static void bnxt_hwrm_vnic_free(struct bnxt *bp)
5322 for (i = 0; i < bp->nr_vnics; i++)
5323 bnxt_hwrm_vnic_free_one(bp, i);
5326 static int bnxt_hwrm_vnic_alloc(struct bnxt *bp, u16 vnic_id,
5327 unsigned int start_rx_ring_idx,
5328 unsigned int nr_rings)
5331 unsigned int i, j, grp_idx, end_idx = start_rx_ring_idx + nr_rings;
5332 struct hwrm_vnic_alloc_input req = {0};
5333 struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
5334 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
5336 if (bp->flags & BNXT_FLAG_CHIP_P5)
5337 goto vnic_no_ring_grps;
5339 /* map ring groups to this vnic */
5340 for (i = start_rx_ring_idx, j = 0; i < end_idx; i++, j++) {
5341 grp_idx = bp->rx_ring[i].bnapi->index;
5342 if (bp->grp_info[grp_idx].fw_grp_id == INVALID_HW_RING_ID) {
5343 netdev_err(bp->dev, "Not enough ring groups avail:%x req:%x\n",
5347 vnic->fw_grp_ids[j] = bp->grp_info[grp_idx].fw_grp_id;
5351 for (i = 0; i < BNXT_MAX_CTX_PER_VNIC; i++)
5352 vnic->fw_rss_cos_lb_ctx[i] = INVALID_HW_RING_ID;
5354 req.flags = cpu_to_le32(VNIC_ALLOC_REQ_FLAGS_DEFAULT);
5356 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_ALLOC, -1, -1);
5358 mutex_lock(&bp->hwrm_cmd_lock);
5359 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5361 vnic->fw_vnic_id = le32_to_cpu(resp->vnic_id);
5362 mutex_unlock(&bp->hwrm_cmd_lock);
5366 static int bnxt_hwrm_vnic_qcaps(struct bnxt *bp)
5368 struct hwrm_vnic_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
5369 struct hwrm_vnic_qcaps_input req = {0};
5372 bp->hw_ring_stats_size = sizeof(struct ctx_hw_stats);
5373 bp->flags &= ~(BNXT_FLAG_NEW_RSS_CAP | BNXT_FLAG_ROCE_MIRROR_CAP);
5374 if (bp->hwrm_spec_code < 0x10600)
5377 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_QCAPS, -1, -1);
5378 mutex_lock(&bp->hwrm_cmd_lock);
5379 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5381 u32 flags = le32_to_cpu(resp->flags);
5383 if (!(bp->flags & BNXT_FLAG_CHIP_P5) &&
5384 (flags & VNIC_QCAPS_RESP_FLAGS_RSS_DFLT_CR_CAP))
5385 bp->flags |= BNXT_FLAG_NEW_RSS_CAP;
5387 VNIC_QCAPS_RESP_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_CAP)
5388 bp->flags |= BNXT_FLAG_ROCE_MIRROR_CAP;
5390 /* Older P5 fw before EXT_HW_STATS support did not set
5391 * VLAN_STRIP_CAP properly.
5393 if ((flags & VNIC_QCAPS_RESP_FLAGS_VLAN_STRIP_CAP) ||
5394 (BNXT_CHIP_P5_THOR(bp) &&
5395 !(bp->fw_cap & BNXT_FW_CAP_EXT_HW_STATS_SUPPORTED)))
5396 bp->fw_cap |= BNXT_FW_CAP_VLAN_RX_STRIP;
5397 bp->max_tpa_v2 = le16_to_cpu(resp->max_aggs_supported);
5398 if (bp->max_tpa_v2) {
5399 if (BNXT_CHIP_P5_THOR(bp))
5400 bp->hw_ring_stats_size = BNXT_RING_STATS_SIZE_P5;
5402 bp->hw_ring_stats_size = BNXT_RING_STATS_SIZE_P5_SR2;
5405 mutex_unlock(&bp->hwrm_cmd_lock);
5409 static int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp)
5414 if (bp->flags & BNXT_FLAG_CHIP_P5)
5417 mutex_lock(&bp->hwrm_cmd_lock);
5418 for (i = 0; i < bp->rx_nr_rings; i++) {
5419 struct hwrm_ring_grp_alloc_input req = {0};
5420 struct hwrm_ring_grp_alloc_output *resp =
5421 bp->hwrm_cmd_resp_addr;
5422 unsigned int grp_idx = bp->rx_ring[i].bnapi->index;
5424 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_GRP_ALLOC, -1, -1);
5426 req.cr = cpu_to_le16(bp->grp_info[grp_idx].cp_fw_ring_id);
5427 req.rr = cpu_to_le16(bp->grp_info[grp_idx].rx_fw_ring_id);
5428 req.ar = cpu_to_le16(bp->grp_info[grp_idx].agg_fw_ring_id);
5429 req.sc = cpu_to_le16(bp->grp_info[grp_idx].fw_stats_ctx);
5431 rc = _hwrm_send_message(bp, &req, sizeof(req),
5436 bp->grp_info[grp_idx].fw_grp_id =
5437 le32_to_cpu(resp->ring_group_id);
5439 mutex_unlock(&bp->hwrm_cmd_lock);
5443 static void bnxt_hwrm_ring_grp_free(struct bnxt *bp)
5446 struct hwrm_ring_grp_free_input req = {0};
5448 if (!bp->grp_info || (bp->flags & BNXT_FLAG_CHIP_P5))
5451 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_GRP_FREE, -1, -1);
5453 mutex_lock(&bp->hwrm_cmd_lock);
5454 for (i = 0; i < bp->cp_nr_rings; i++) {
5455 if (bp->grp_info[i].fw_grp_id == INVALID_HW_RING_ID)
5458 cpu_to_le32(bp->grp_info[i].fw_grp_id);
5460 _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5461 bp->grp_info[i].fw_grp_id = INVALID_HW_RING_ID;
5463 mutex_unlock(&bp->hwrm_cmd_lock);
5466 static int hwrm_ring_alloc_send_msg(struct bnxt *bp,
5467 struct bnxt_ring_struct *ring,
5468 u32 ring_type, u32 map_index)
5470 int rc = 0, err = 0;
5471 struct hwrm_ring_alloc_input req = {0};
5472 struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr;
5473 struct bnxt_ring_mem_info *rmem = &ring->ring_mem;
5474 struct bnxt_ring_grp_info *grp_info;
5477 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_ALLOC, -1, -1);
5480 if (rmem->nr_pages > 1) {
5481 req.page_tbl_addr = cpu_to_le64(rmem->pg_tbl_map);
5482 /* Page size is in log2 units */
5483 req.page_size = BNXT_PAGE_SHIFT;
5484 req.page_tbl_depth = 1;
5486 req.page_tbl_addr = cpu_to_le64(rmem->dma_arr[0]);
5489 /* Association of ring index with doorbell index and MSIX number */
5490 req.logical_id = cpu_to_le16(map_index);
5492 switch (ring_type) {
5493 case HWRM_RING_ALLOC_TX: {
5494 struct bnxt_tx_ring_info *txr;
5496 txr = container_of(ring, struct bnxt_tx_ring_info,
5498 req.ring_type = RING_ALLOC_REQ_RING_TYPE_TX;
5499 /* Association of transmit ring with completion ring */
5500 grp_info = &bp->grp_info[ring->grp_idx];
5501 req.cmpl_ring_id = cpu_to_le16(bnxt_cp_ring_for_tx(bp, txr));
5502 req.length = cpu_to_le32(bp->tx_ring_mask + 1);
5503 req.stat_ctx_id = cpu_to_le32(grp_info->fw_stats_ctx);
5504 req.queue_id = cpu_to_le16(ring->queue_id);
5507 case HWRM_RING_ALLOC_RX:
5508 req.ring_type = RING_ALLOC_REQ_RING_TYPE_RX;
5509 req.length = cpu_to_le32(bp->rx_ring_mask + 1);
5510 if (bp->flags & BNXT_FLAG_CHIP_P5) {
5513 /* Association of rx ring with stats context */
5514 grp_info = &bp->grp_info[ring->grp_idx];
5515 req.rx_buf_size = cpu_to_le16(bp->rx_buf_use_size);
5516 req.stat_ctx_id = cpu_to_le32(grp_info->fw_stats_ctx);
5517 req.enables |= cpu_to_le32(
5518 RING_ALLOC_REQ_ENABLES_RX_BUF_SIZE_VALID);
5519 if (NET_IP_ALIGN == 2)
5520 flags = RING_ALLOC_REQ_FLAGS_RX_SOP_PAD;
5521 req.flags = cpu_to_le16(flags);
5524 case HWRM_RING_ALLOC_AGG:
5525 if (bp->flags & BNXT_FLAG_CHIP_P5) {
5526 req.ring_type = RING_ALLOC_REQ_RING_TYPE_RX_AGG;
5527 /* Association of agg ring with rx ring */
5528 grp_info = &bp->grp_info[ring->grp_idx];
5529 req.rx_ring_id = cpu_to_le16(grp_info->rx_fw_ring_id);
5530 req.rx_buf_size = cpu_to_le16(BNXT_RX_PAGE_SIZE);
5531 req.stat_ctx_id = cpu_to_le32(grp_info->fw_stats_ctx);
5532 req.enables |= cpu_to_le32(
5533 RING_ALLOC_REQ_ENABLES_RX_RING_ID_VALID |
5534 RING_ALLOC_REQ_ENABLES_RX_BUF_SIZE_VALID);
5536 req.ring_type = RING_ALLOC_REQ_RING_TYPE_RX;
5538 req.length = cpu_to_le32(bp->rx_agg_ring_mask + 1);
5540 case HWRM_RING_ALLOC_CMPL:
5541 req.ring_type = RING_ALLOC_REQ_RING_TYPE_L2_CMPL;
5542 req.length = cpu_to_le32(bp->cp_ring_mask + 1);
5543 if (bp->flags & BNXT_FLAG_CHIP_P5) {
5544 /* Association of cp ring with nq */
5545 grp_info = &bp->grp_info[map_index];
5546 req.nq_ring_id = cpu_to_le16(grp_info->cp_fw_ring_id);
5547 req.cq_handle = cpu_to_le64(ring->handle);
5548 req.enables |= cpu_to_le32(
5549 RING_ALLOC_REQ_ENABLES_NQ_RING_ID_VALID);
5550 } else if (bp->flags & BNXT_FLAG_USING_MSIX) {
5551 req.int_mode = RING_ALLOC_REQ_INT_MODE_MSIX;
5554 case HWRM_RING_ALLOC_NQ:
5555 req.ring_type = RING_ALLOC_REQ_RING_TYPE_NQ;
5556 req.length = cpu_to_le32(bp->cp_ring_mask + 1);
5557 if (bp->flags & BNXT_FLAG_USING_MSIX)
5558 req.int_mode = RING_ALLOC_REQ_INT_MODE_MSIX;
5561 netdev_err(bp->dev, "hwrm alloc invalid ring type %d\n",
5566 mutex_lock(&bp->hwrm_cmd_lock);
5567 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5568 err = le16_to_cpu(resp->error_code);
5569 ring_id = le16_to_cpu(resp->ring_id);
5570 mutex_unlock(&bp->hwrm_cmd_lock);
5573 netdev_err(bp->dev, "hwrm_ring_alloc type %d failed. rc:%x err:%x\n",
5574 ring_type, rc, err);
5577 ring->fw_ring_id = ring_id;
5581 static int bnxt_hwrm_set_async_event_cr(struct bnxt *bp, int idx)
5586 struct hwrm_func_cfg_input req = {0};
5588 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_CFG, -1, -1);
5589 req.fid = cpu_to_le16(0xffff);
5590 req.enables = cpu_to_le32(FUNC_CFG_REQ_ENABLES_ASYNC_EVENT_CR);
5591 req.async_event_cr = cpu_to_le16(idx);
5592 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5594 struct hwrm_func_vf_cfg_input req = {0};
5596 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_VF_CFG, -1, -1);
5598 cpu_to_le32(FUNC_VF_CFG_REQ_ENABLES_ASYNC_EVENT_CR);
5599 req.async_event_cr = cpu_to_le16(idx);
5600 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5605 static void bnxt_set_db(struct bnxt *bp, struct bnxt_db_info *db, u32 ring_type,
5606 u32 map_idx, u32 xid)
5608 if (bp->flags & BNXT_FLAG_CHIP_P5) {
5610 db->doorbell = bp->bar1 + DB_PF_OFFSET_P5;
5612 db->doorbell = bp->bar1 + DB_VF_OFFSET_P5;
5613 switch (ring_type) {
5614 case HWRM_RING_ALLOC_TX:
5615 db->db_key64 = DBR_PATH_L2 | DBR_TYPE_SQ;
5617 case HWRM_RING_ALLOC_RX:
5618 case HWRM_RING_ALLOC_AGG:
5619 db->db_key64 = DBR_PATH_L2 | DBR_TYPE_SRQ;
5621 case HWRM_RING_ALLOC_CMPL:
5622 db->db_key64 = DBR_PATH_L2;
5624 case HWRM_RING_ALLOC_NQ:
5625 db->db_key64 = DBR_PATH_L2;
5628 db->db_key64 |= (u64)xid << DBR_XID_SFT;
5630 db->doorbell = bp->bar1 + map_idx * 0x80;
5631 switch (ring_type) {
5632 case HWRM_RING_ALLOC_TX:
5633 db->db_key32 = DB_KEY_TX;
5635 case HWRM_RING_ALLOC_RX:
5636 case HWRM_RING_ALLOC_AGG:
5637 db->db_key32 = DB_KEY_RX;
5639 case HWRM_RING_ALLOC_CMPL:
5640 db->db_key32 = DB_KEY_CP;
5646 static int bnxt_hwrm_ring_alloc(struct bnxt *bp)
5648 bool agg_rings = !!(bp->flags & BNXT_FLAG_AGG_RINGS);
5652 if (bp->flags & BNXT_FLAG_CHIP_P5)
5653 type = HWRM_RING_ALLOC_NQ;
5655 type = HWRM_RING_ALLOC_CMPL;
5656 for (i = 0; i < bp->cp_nr_rings; i++) {
5657 struct bnxt_napi *bnapi = bp->bnapi[i];
5658 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
5659 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct;
5660 u32 map_idx = ring->map_idx;
5661 unsigned int vector;
5663 vector = bp->irq_tbl[map_idx].vector;
5664 disable_irq_nosync(vector);
5665 rc = hwrm_ring_alloc_send_msg(bp, ring, type, map_idx);
5670 bnxt_set_db(bp, &cpr->cp_db, type, map_idx, ring->fw_ring_id);
5671 bnxt_db_nq(bp, &cpr->cp_db, cpr->cp_raw_cons);
5673 bp->grp_info[i].cp_fw_ring_id = ring->fw_ring_id;
5676 rc = bnxt_hwrm_set_async_event_cr(bp, ring->fw_ring_id);
5678 netdev_warn(bp->dev, "Failed to set async event completion ring.\n");
5682 type = HWRM_RING_ALLOC_TX;
5683 for (i = 0; i < bp->tx_nr_rings; i++) {
5684 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
5685 struct bnxt_ring_struct *ring;
5688 if (bp->flags & BNXT_FLAG_CHIP_P5) {
5689 struct bnxt_napi *bnapi = txr->bnapi;
5690 struct bnxt_cp_ring_info *cpr, *cpr2;
5691 u32 type2 = HWRM_RING_ALLOC_CMPL;
5693 cpr = &bnapi->cp_ring;
5694 cpr2 = cpr->cp_ring_arr[BNXT_TX_HDL];
5695 ring = &cpr2->cp_ring_struct;
5696 ring->handle = BNXT_TX_HDL;
5697 map_idx = bnapi->index;
5698 rc = hwrm_ring_alloc_send_msg(bp, ring, type2, map_idx);
5701 bnxt_set_db(bp, &cpr2->cp_db, type2, map_idx,
5703 bnxt_db_cq(bp, &cpr2->cp_db, cpr2->cp_raw_cons);
5705 ring = &txr->tx_ring_struct;
5707 rc = hwrm_ring_alloc_send_msg(bp, ring, type, map_idx);
5710 bnxt_set_db(bp, &txr->tx_db, type, map_idx, ring->fw_ring_id);
5713 type = HWRM_RING_ALLOC_RX;
5714 for (i = 0; i < bp->rx_nr_rings; i++) {
5715 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
5716 struct bnxt_ring_struct *ring = &rxr->rx_ring_struct;
5717 struct bnxt_napi *bnapi = rxr->bnapi;
5718 u32 map_idx = bnapi->index;
5720 rc = hwrm_ring_alloc_send_msg(bp, ring, type, map_idx);
5723 bnxt_set_db(bp, &rxr->rx_db, type, map_idx, ring->fw_ring_id);
5724 /* If we have agg rings, post agg buffers first. */
5726 bnxt_db_write(bp, &rxr->rx_db, rxr->rx_prod);
5727 bp->grp_info[map_idx].rx_fw_ring_id = ring->fw_ring_id;
5728 if (bp->flags & BNXT_FLAG_CHIP_P5) {
5729 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
5730 u32 type2 = HWRM_RING_ALLOC_CMPL;
5731 struct bnxt_cp_ring_info *cpr2;
5733 cpr2 = cpr->cp_ring_arr[BNXT_RX_HDL];
5734 ring = &cpr2->cp_ring_struct;
5735 ring->handle = BNXT_RX_HDL;
5736 rc = hwrm_ring_alloc_send_msg(bp, ring, type2, map_idx);
5739 bnxt_set_db(bp, &cpr2->cp_db, type2, map_idx,
5741 bnxt_db_cq(bp, &cpr2->cp_db, cpr2->cp_raw_cons);
5746 type = HWRM_RING_ALLOC_AGG;
5747 for (i = 0; i < bp->rx_nr_rings; i++) {
5748 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
5749 struct bnxt_ring_struct *ring =
5750 &rxr->rx_agg_ring_struct;
5751 u32 grp_idx = ring->grp_idx;
5752 u32 map_idx = grp_idx + bp->rx_nr_rings;
5754 rc = hwrm_ring_alloc_send_msg(bp, ring, type, map_idx);
5758 bnxt_set_db(bp, &rxr->rx_agg_db, type, map_idx,
5760 bnxt_db_write(bp, &rxr->rx_agg_db, rxr->rx_agg_prod);
5761 bnxt_db_write(bp, &rxr->rx_db, rxr->rx_prod);
5762 bp->grp_info[grp_idx].agg_fw_ring_id = ring->fw_ring_id;
5769 static int hwrm_ring_free_send_msg(struct bnxt *bp,
5770 struct bnxt_ring_struct *ring,
5771 u32 ring_type, int cmpl_ring_id)
5774 struct hwrm_ring_free_input req = {0};
5775 struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;
5778 if (BNXT_NO_FW_ACCESS(bp))
5781 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_FREE, cmpl_ring_id, -1);
5782 req.ring_type = ring_type;
5783 req.ring_id = cpu_to_le16(ring->fw_ring_id);
5785 mutex_lock(&bp->hwrm_cmd_lock);
5786 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5787 error_code = le16_to_cpu(resp->error_code);
5788 mutex_unlock(&bp->hwrm_cmd_lock);
5790 if (rc || error_code) {
5791 netdev_err(bp->dev, "hwrm_ring_free type %d failed. rc:%x err:%x\n",
5792 ring_type, rc, error_code);
5798 static void bnxt_hwrm_ring_free(struct bnxt *bp, bool close_path)
5806 for (i = 0; i < bp->tx_nr_rings; i++) {
5807 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
5808 struct bnxt_ring_struct *ring = &txr->tx_ring_struct;
5810 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
5811 u32 cmpl_ring_id = bnxt_cp_ring_for_tx(bp, txr);
5813 hwrm_ring_free_send_msg(bp, ring,
5814 RING_FREE_REQ_RING_TYPE_TX,
5815 close_path ? cmpl_ring_id :
5816 INVALID_HW_RING_ID);
5817 ring->fw_ring_id = INVALID_HW_RING_ID;
5821 for (i = 0; i < bp->rx_nr_rings; i++) {
5822 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
5823 struct bnxt_ring_struct *ring = &rxr->rx_ring_struct;
5824 u32 grp_idx = rxr->bnapi->index;
5826 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
5827 u32 cmpl_ring_id = bnxt_cp_ring_for_rx(bp, rxr);
5829 hwrm_ring_free_send_msg(bp, ring,
5830 RING_FREE_REQ_RING_TYPE_RX,
5831 close_path ? cmpl_ring_id :
5832 INVALID_HW_RING_ID);
5833 ring->fw_ring_id = INVALID_HW_RING_ID;
5834 bp->grp_info[grp_idx].rx_fw_ring_id =
5839 if (bp->flags & BNXT_FLAG_CHIP_P5)
5840 type = RING_FREE_REQ_RING_TYPE_RX_AGG;
5842 type = RING_FREE_REQ_RING_TYPE_RX;
5843 for (i = 0; i < bp->rx_nr_rings; i++) {
5844 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
5845 struct bnxt_ring_struct *ring = &rxr->rx_agg_ring_struct;
5846 u32 grp_idx = rxr->bnapi->index;
5848 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
5849 u32 cmpl_ring_id = bnxt_cp_ring_for_rx(bp, rxr);
5851 hwrm_ring_free_send_msg(bp, ring, type,
5852 close_path ? cmpl_ring_id :
5853 INVALID_HW_RING_ID);
5854 ring->fw_ring_id = INVALID_HW_RING_ID;
5855 bp->grp_info[grp_idx].agg_fw_ring_id =
5860 /* The completion rings are about to be freed. After that the
5861 * IRQ doorbell will not work anymore. So we need to disable
5864 bnxt_disable_int_sync(bp);
5866 if (bp->flags & BNXT_FLAG_CHIP_P5)
5867 type = RING_FREE_REQ_RING_TYPE_NQ;
5869 type = RING_FREE_REQ_RING_TYPE_L2_CMPL;
5870 for (i = 0; i < bp->cp_nr_rings; i++) {
5871 struct bnxt_napi *bnapi = bp->bnapi[i];
5872 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
5873 struct bnxt_ring_struct *ring;
5876 for (j = 0; j < 2; j++) {
5877 struct bnxt_cp_ring_info *cpr2 = cpr->cp_ring_arr[j];
5880 ring = &cpr2->cp_ring_struct;
5881 if (ring->fw_ring_id == INVALID_HW_RING_ID)
5883 hwrm_ring_free_send_msg(bp, ring,
5884 RING_FREE_REQ_RING_TYPE_L2_CMPL,
5885 INVALID_HW_RING_ID);
5886 ring->fw_ring_id = INVALID_HW_RING_ID;
5889 ring = &cpr->cp_ring_struct;
5890 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
5891 hwrm_ring_free_send_msg(bp, ring, type,
5892 INVALID_HW_RING_ID);
5893 ring->fw_ring_id = INVALID_HW_RING_ID;
5894 bp->grp_info[i].cp_fw_ring_id = INVALID_HW_RING_ID;
5899 static int bnxt_trim_rings(struct bnxt *bp, int *rx, int *tx, int max,
5902 static int bnxt_hwrm_get_rings(struct bnxt *bp)
5904 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
5905 struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
5906 struct hwrm_func_qcfg_input req = {0};
5909 if (bp->hwrm_spec_code < 0x10601)
5912 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCFG, -1, -1);
5913 req.fid = cpu_to_le16(0xffff);
5914 mutex_lock(&bp->hwrm_cmd_lock);
5915 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5917 mutex_unlock(&bp->hwrm_cmd_lock);
5921 hw_resc->resv_tx_rings = le16_to_cpu(resp->alloc_tx_rings);
5922 if (BNXT_NEW_RM(bp)) {
5925 hw_resc->resv_rx_rings = le16_to_cpu(resp->alloc_rx_rings);
5926 hw_resc->resv_hw_ring_grps =
5927 le32_to_cpu(resp->alloc_hw_ring_grps);
5928 hw_resc->resv_vnics = le16_to_cpu(resp->alloc_vnics);
5929 cp = le16_to_cpu(resp->alloc_cmpl_rings);
5930 stats = le16_to_cpu(resp->alloc_stat_ctx);
5931 hw_resc->resv_irqs = cp;
5932 if (bp->flags & BNXT_FLAG_CHIP_P5) {
5933 int rx = hw_resc->resv_rx_rings;
5934 int tx = hw_resc->resv_tx_rings;
5936 if (bp->flags & BNXT_FLAG_AGG_RINGS)
5938 if (cp < (rx + tx)) {
5939 bnxt_trim_rings(bp, &rx, &tx, cp, false);
5940 if (bp->flags & BNXT_FLAG_AGG_RINGS)
5942 hw_resc->resv_rx_rings = rx;
5943 hw_resc->resv_tx_rings = tx;
5945 hw_resc->resv_irqs = le16_to_cpu(resp->alloc_msix);
5946 hw_resc->resv_hw_ring_grps = rx;
5948 hw_resc->resv_cp_rings = cp;
5949 hw_resc->resv_stat_ctxs = stats;
5951 mutex_unlock(&bp->hwrm_cmd_lock);
5955 /* Caller must hold bp->hwrm_cmd_lock */
5956 int __bnxt_hwrm_get_tx_rings(struct bnxt *bp, u16 fid, int *tx_rings)
5958 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
5959 struct hwrm_func_qcfg_input req = {0};
5962 if (bp->hwrm_spec_code < 0x10601)
5965 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCFG, -1, -1);
5966 req.fid = cpu_to_le16(fid);
5967 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5969 *tx_rings = le16_to_cpu(resp->alloc_tx_rings);
5974 static bool bnxt_rfs_supported(struct bnxt *bp);
5977 __bnxt_hwrm_reserve_pf_rings(struct bnxt *bp, struct hwrm_func_cfg_input *req,
5978 int tx_rings, int rx_rings, int ring_grps,
5979 int cp_rings, int stats, int vnics)
5983 bnxt_hwrm_cmd_hdr_init(bp, req, HWRM_FUNC_CFG, -1, -1);
5984 req->fid = cpu_to_le16(0xffff);
5985 enables |= tx_rings ? FUNC_CFG_REQ_ENABLES_NUM_TX_RINGS : 0;
5986 req->num_tx_rings = cpu_to_le16(tx_rings);
5987 if (BNXT_NEW_RM(bp)) {
5988 enables |= rx_rings ? FUNC_CFG_REQ_ENABLES_NUM_RX_RINGS : 0;
5989 enables |= stats ? FUNC_CFG_REQ_ENABLES_NUM_STAT_CTXS : 0;
5990 if (bp->flags & BNXT_FLAG_CHIP_P5) {
5991 enables |= cp_rings ? FUNC_CFG_REQ_ENABLES_NUM_MSIX : 0;
5992 enables |= tx_rings + ring_grps ?
5993 FUNC_CFG_REQ_ENABLES_NUM_CMPL_RINGS : 0;
5994 enables |= rx_rings ?
5995 FUNC_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS : 0;
5997 enables |= cp_rings ?
5998 FUNC_CFG_REQ_ENABLES_NUM_CMPL_RINGS : 0;
5999 enables |= ring_grps ?
6000 FUNC_CFG_REQ_ENABLES_NUM_HW_RING_GRPS |
6001 FUNC_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS : 0;
6003 enables |= vnics ? FUNC_CFG_REQ_ENABLES_NUM_VNICS : 0;
6005 req->num_rx_rings = cpu_to_le16(rx_rings);
6006 if (bp->flags & BNXT_FLAG_CHIP_P5) {
6007 req->num_cmpl_rings = cpu_to_le16(tx_rings + ring_grps);
6008 req->num_msix = cpu_to_le16(cp_rings);
6009 req->num_rsscos_ctxs =
6010 cpu_to_le16(DIV_ROUND_UP(ring_grps, 64));
6012 req->num_cmpl_rings = cpu_to_le16(cp_rings);
6013 req->num_hw_ring_grps = cpu_to_le16(ring_grps);
6014 req->num_rsscos_ctxs = cpu_to_le16(1);
6015 if (!(bp->flags & BNXT_FLAG_NEW_RSS_CAP) &&
6016 bnxt_rfs_supported(bp))
6017 req->num_rsscos_ctxs =
6018 cpu_to_le16(ring_grps + 1);
6020 req->num_stat_ctxs = cpu_to_le16(stats);
6021 req->num_vnics = cpu_to_le16(vnics);
6023 req->enables = cpu_to_le32(enables);
6027 __bnxt_hwrm_reserve_vf_rings(struct bnxt *bp,
6028 struct hwrm_func_vf_cfg_input *req, int tx_rings,
6029 int rx_rings, int ring_grps, int cp_rings,
6030 int stats, int vnics)
6034 bnxt_hwrm_cmd_hdr_init(bp, req, HWRM_FUNC_VF_CFG, -1, -1);
6035 enables |= tx_rings ? FUNC_VF_CFG_REQ_ENABLES_NUM_TX_RINGS : 0;
6036 enables |= rx_rings ? FUNC_VF_CFG_REQ_ENABLES_NUM_RX_RINGS |
6037 FUNC_VF_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS : 0;
6038 enables |= stats ? FUNC_VF_CFG_REQ_ENABLES_NUM_STAT_CTXS : 0;
6039 if (bp->flags & BNXT_FLAG_CHIP_P5) {
6040 enables |= tx_rings + ring_grps ?
6041 FUNC_VF_CFG_REQ_ENABLES_NUM_CMPL_RINGS : 0;
6043 enables |= cp_rings ?
6044 FUNC_VF_CFG_REQ_ENABLES_NUM_CMPL_RINGS : 0;
6045 enables |= ring_grps ?
6046 FUNC_VF_CFG_REQ_ENABLES_NUM_HW_RING_GRPS : 0;
6048 enables |= vnics ? FUNC_VF_CFG_REQ_ENABLES_NUM_VNICS : 0;
6049 enables |= FUNC_VF_CFG_REQ_ENABLES_NUM_L2_CTXS;
6051 req->num_l2_ctxs = cpu_to_le16(BNXT_VF_MAX_L2_CTX);
6052 req->num_tx_rings = cpu_to_le16(tx_rings);
6053 req->num_rx_rings = cpu_to_le16(rx_rings);
6054 if (bp->flags & BNXT_FLAG_CHIP_P5) {
6055 req->num_cmpl_rings = cpu_to_le16(tx_rings + ring_grps);
6056 req->num_rsscos_ctxs = cpu_to_le16(DIV_ROUND_UP(ring_grps, 64));
6058 req->num_cmpl_rings = cpu_to_le16(cp_rings);
6059 req->num_hw_ring_grps = cpu_to_le16(ring_grps);
6060 req->num_rsscos_ctxs = cpu_to_le16(BNXT_VF_MAX_RSS_CTX);
6062 req->num_stat_ctxs = cpu_to_le16(stats);
6063 req->num_vnics = cpu_to_le16(vnics);
6065 req->enables = cpu_to_le32(enables);
6069 bnxt_hwrm_reserve_pf_rings(struct bnxt *bp, int tx_rings, int rx_rings,
6070 int ring_grps, int cp_rings, int stats, int vnics)
6072 struct hwrm_func_cfg_input req = {0};
6075 __bnxt_hwrm_reserve_pf_rings(bp, &req, tx_rings, rx_rings, ring_grps,
6076 cp_rings, stats, vnics);
6080 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6084 if (bp->hwrm_spec_code < 0x10601)
6085 bp->hw_resc.resv_tx_rings = tx_rings;
6087 return bnxt_hwrm_get_rings(bp);
6091 bnxt_hwrm_reserve_vf_rings(struct bnxt *bp, int tx_rings, int rx_rings,
6092 int ring_grps, int cp_rings, int stats, int vnics)
6094 struct hwrm_func_vf_cfg_input req = {0};
6097 if (!BNXT_NEW_RM(bp)) {
6098 bp->hw_resc.resv_tx_rings = tx_rings;
6102 __bnxt_hwrm_reserve_vf_rings(bp, &req, tx_rings, rx_rings, ring_grps,
6103 cp_rings, stats, vnics);
6104 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6108 return bnxt_hwrm_get_rings(bp);
6111 static int bnxt_hwrm_reserve_rings(struct bnxt *bp, int tx, int rx, int grp,
6112 int cp, int stat, int vnic)
6115 return bnxt_hwrm_reserve_pf_rings(bp, tx, rx, grp, cp, stat,
6118 return bnxt_hwrm_reserve_vf_rings(bp, tx, rx, grp, cp, stat,
6122 int bnxt_nq_rings_in_use(struct bnxt *bp)
6124 int cp = bp->cp_nr_rings;
6125 int ulp_msix, ulp_base;
6127 ulp_msix = bnxt_get_ulp_msix_num(bp);
6129 ulp_base = bnxt_get_ulp_msix_base(bp);
6131 if ((ulp_base + ulp_msix) > cp)
6132 cp = ulp_base + ulp_msix;
6137 static int bnxt_cp_rings_in_use(struct bnxt *bp)
6141 if (!(bp->flags & BNXT_FLAG_CHIP_P5))
6142 return bnxt_nq_rings_in_use(bp);
6144 cp = bp->tx_nr_rings + bp->rx_nr_rings;
6148 static int bnxt_get_func_stat_ctxs(struct bnxt *bp)
6150 int ulp_stat = bnxt_get_ulp_stat_ctxs(bp);
6151 int cp = bp->cp_nr_rings;
6156 if (bnxt_nq_rings_in_use(bp) > cp + bnxt_get_ulp_msix_num(bp))
6157 return bnxt_get_ulp_msix_base(bp) + ulp_stat;
6159 return cp + ulp_stat;
6162 /* Check if a default RSS map needs to be setup. This function is only
6163 * used on older firmware that does not require reserving RX rings.
6165 static void bnxt_check_rss_tbl_no_rmgr(struct bnxt *bp)
6167 struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
6169 /* The RSS map is valid for RX rings set to resv_rx_rings */
6170 if (hw_resc->resv_rx_rings != bp->rx_nr_rings) {
6171 hw_resc->resv_rx_rings = bp->rx_nr_rings;
6172 if (!netif_is_rxfh_configured(bp->dev))
6173 bnxt_set_dflt_rss_indir_tbl(bp);
6177 static bool bnxt_need_reserve_rings(struct bnxt *bp)
6179 struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
6180 int cp = bnxt_cp_rings_in_use(bp);
6181 int nq = bnxt_nq_rings_in_use(bp);
6182 int rx = bp->rx_nr_rings, stat;
6183 int vnic = 1, grp = rx;
6185 if (hw_resc->resv_tx_rings != bp->tx_nr_rings &&
6186 bp->hwrm_spec_code >= 0x10601)
6189 /* Old firmware does not need RX ring reservations but we still
6190 * need to setup a default RSS map when needed. With new firmware
6191 * we go through RX ring reservations first and then set up the
6192 * RSS map for the successfully reserved RX rings when needed.
6194 if (!BNXT_NEW_RM(bp)) {
6195 bnxt_check_rss_tbl_no_rmgr(bp);
6198 if ((bp->flags & BNXT_FLAG_RFS) && !(bp->flags & BNXT_FLAG_CHIP_P5))
6200 if (bp->flags & BNXT_FLAG_AGG_RINGS)
6202 stat = bnxt_get_func_stat_ctxs(bp);
6203 if (hw_resc->resv_rx_rings != rx || hw_resc->resv_cp_rings != cp ||
6204 hw_resc->resv_vnics != vnic || hw_resc->resv_stat_ctxs != stat ||
6205 (hw_resc->resv_hw_ring_grps != grp &&
6206 !(bp->flags & BNXT_FLAG_CHIP_P5)))
6208 if ((bp->flags & BNXT_FLAG_CHIP_P5) && BNXT_PF(bp) &&
6209 hw_resc->resv_irqs != nq)
6214 static int __bnxt_reserve_rings(struct bnxt *bp)
6216 struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
6217 int cp = bnxt_nq_rings_in_use(bp);
6218 int tx = bp->tx_nr_rings;
6219 int rx = bp->rx_nr_rings;
6220 int grp, rx_rings, rc;
6224 if (!bnxt_need_reserve_rings(bp))
6227 if (bp->flags & BNXT_FLAG_SHARED_RINGS)
6229 if ((bp->flags & BNXT_FLAG_RFS) && !(bp->flags & BNXT_FLAG_CHIP_P5))
6231 if (bp->flags & BNXT_FLAG_AGG_RINGS)
6233 grp = bp->rx_nr_rings;
6234 stat = bnxt_get_func_stat_ctxs(bp);
6236 rc = bnxt_hwrm_reserve_rings(bp, tx, rx, grp, cp, stat, vnic);
6240 tx = hw_resc->resv_tx_rings;
6241 if (BNXT_NEW_RM(bp)) {
6242 rx = hw_resc->resv_rx_rings;
6243 cp = hw_resc->resv_irqs;
6244 grp = hw_resc->resv_hw_ring_grps;
6245 vnic = hw_resc->resv_vnics;
6246 stat = hw_resc->resv_stat_ctxs;
6250 if (bp->flags & BNXT_FLAG_AGG_RINGS) {
6254 if (netif_running(bp->dev))
6257 bp->flags &= ~BNXT_FLAG_AGG_RINGS;
6258 bp->flags |= BNXT_FLAG_NO_AGG_RINGS;
6259 bp->dev->hw_features &= ~NETIF_F_LRO;
6260 bp->dev->features &= ~NETIF_F_LRO;
6261 bnxt_set_ring_params(bp);
6264 rx_rings = min_t(int, rx_rings, grp);
6265 cp = min_t(int, cp, bp->cp_nr_rings);
6266 if (stat > bnxt_get_ulp_stat_ctxs(bp))
6267 stat -= bnxt_get_ulp_stat_ctxs(bp);
6268 cp = min_t(int, cp, stat);
6269 rc = bnxt_trim_rings(bp, &rx_rings, &tx, cp, sh);
6270 if (bp->flags & BNXT_FLAG_AGG_RINGS)
6272 cp = sh ? max_t(int, tx, rx_rings) : tx + rx_rings;
6273 bp->tx_nr_rings = tx;
6275 /* If we cannot reserve all the RX rings, reset the RSS map only
6276 * if absolutely necessary
6278 if (rx_rings != bp->rx_nr_rings) {
6279 netdev_warn(bp->dev, "Able to reserve only %d out of %d requested RX rings\n",
6280 rx_rings, bp->rx_nr_rings);
6281 if ((bp->dev->priv_flags & IFF_RXFH_CONFIGURED) &&
6282 (bnxt_get_nr_rss_ctxs(bp, bp->rx_nr_rings) !=
6283 bnxt_get_nr_rss_ctxs(bp, rx_rings) ||
6284 bnxt_get_max_rss_ring(bp) >= rx_rings)) {
6285 netdev_warn(bp->dev, "RSS table entries reverting to default\n");
6286 bp->dev->priv_flags &= ~IFF_RXFH_CONFIGURED;
6289 bp->rx_nr_rings = rx_rings;
6290 bp->cp_nr_rings = cp;
6292 if (!tx || !rx || !cp || !grp || !vnic || !stat)
6295 if (!netif_is_rxfh_configured(bp->dev))
6296 bnxt_set_dflt_rss_indir_tbl(bp);
6301 static int bnxt_hwrm_check_vf_rings(struct bnxt *bp, int tx_rings, int rx_rings,
6302 int ring_grps, int cp_rings, int stats,
6305 struct hwrm_func_vf_cfg_input req = {0};
6308 if (!BNXT_NEW_RM(bp))
6311 __bnxt_hwrm_reserve_vf_rings(bp, &req, tx_rings, rx_rings, ring_grps,
6312 cp_rings, stats, vnics);
6313 flags = FUNC_VF_CFG_REQ_FLAGS_TX_ASSETS_TEST |
6314 FUNC_VF_CFG_REQ_FLAGS_RX_ASSETS_TEST |
6315 FUNC_VF_CFG_REQ_FLAGS_CMPL_ASSETS_TEST |
6316 FUNC_VF_CFG_REQ_FLAGS_STAT_CTX_ASSETS_TEST |
6317 FUNC_VF_CFG_REQ_FLAGS_VNIC_ASSETS_TEST |
6318 FUNC_VF_CFG_REQ_FLAGS_RSSCOS_CTX_ASSETS_TEST;
6319 if (!(bp->flags & BNXT_FLAG_CHIP_P5))
6320 flags |= FUNC_VF_CFG_REQ_FLAGS_RING_GRP_ASSETS_TEST;
6322 req.flags = cpu_to_le32(flags);
6323 return hwrm_send_message_silent(bp, &req, sizeof(req),
6327 static int bnxt_hwrm_check_pf_rings(struct bnxt *bp, int tx_rings, int rx_rings,
6328 int ring_grps, int cp_rings, int stats,
6331 struct hwrm_func_cfg_input req = {0};
6334 __bnxt_hwrm_reserve_pf_rings(bp, &req, tx_rings, rx_rings, ring_grps,
6335 cp_rings, stats, vnics);
6336 flags = FUNC_CFG_REQ_FLAGS_TX_ASSETS_TEST;
6337 if (BNXT_NEW_RM(bp)) {
6338 flags |= FUNC_CFG_REQ_FLAGS_RX_ASSETS_TEST |
6339 FUNC_CFG_REQ_FLAGS_CMPL_ASSETS_TEST |
6340 FUNC_CFG_REQ_FLAGS_STAT_CTX_ASSETS_TEST |
6341 FUNC_CFG_REQ_FLAGS_VNIC_ASSETS_TEST;
6342 if (bp->flags & BNXT_FLAG_CHIP_P5)
6343 flags |= FUNC_CFG_REQ_FLAGS_RSSCOS_CTX_ASSETS_TEST |
6344 FUNC_CFG_REQ_FLAGS_NQ_ASSETS_TEST;
6346 flags |= FUNC_CFG_REQ_FLAGS_RING_GRP_ASSETS_TEST;
6349 req.flags = cpu_to_le32(flags);
6350 return hwrm_send_message_silent(bp, &req, sizeof(req),
6354 static int bnxt_hwrm_check_rings(struct bnxt *bp, int tx_rings, int rx_rings,
6355 int ring_grps, int cp_rings, int stats,
6358 if (bp->hwrm_spec_code < 0x10801)
6362 return bnxt_hwrm_check_pf_rings(bp, tx_rings, rx_rings,
6363 ring_grps, cp_rings, stats,
6366 return bnxt_hwrm_check_vf_rings(bp, tx_rings, rx_rings, ring_grps,
6367 cp_rings, stats, vnics);
6370 static void bnxt_hwrm_coal_params_qcaps(struct bnxt *bp)
6372 struct hwrm_ring_aggint_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
6373 struct bnxt_coal_cap *coal_cap = &bp->coal_cap;
6374 struct hwrm_ring_aggint_qcaps_input req = {0};
6377 coal_cap->cmpl_params = BNXT_LEGACY_COAL_CMPL_PARAMS;
6378 coal_cap->num_cmpl_dma_aggr_max = 63;
6379 coal_cap->num_cmpl_dma_aggr_during_int_max = 63;
6380 coal_cap->cmpl_aggr_dma_tmr_max = 65535;
6381 coal_cap->cmpl_aggr_dma_tmr_during_int_max = 65535;
6382 coal_cap->int_lat_tmr_min_max = 65535;
6383 coal_cap->int_lat_tmr_max_max = 65535;
6384 coal_cap->num_cmpl_aggr_int_max = 65535;
6385 coal_cap->timer_units = 80;
6387 if (bp->hwrm_spec_code < 0x10902)
6390 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_AGGINT_QCAPS, -1, -1);
6391 mutex_lock(&bp->hwrm_cmd_lock);
6392 rc = _hwrm_send_message_silent(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6394 coal_cap->cmpl_params = le32_to_cpu(resp->cmpl_params);
6395 coal_cap->nq_params = le32_to_cpu(resp->nq_params);
6396 coal_cap->num_cmpl_dma_aggr_max =
6397 le16_to_cpu(resp->num_cmpl_dma_aggr_max);
6398 coal_cap->num_cmpl_dma_aggr_during_int_max =
6399 le16_to_cpu(resp->num_cmpl_dma_aggr_during_int_max);
6400 coal_cap->cmpl_aggr_dma_tmr_max =
6401 le16_to_cpu(resp->cmpl_aggr_dma_tmr_max);
6402 coal_cap->cmpl_aggr_dma_tmr_during_int_max =
6403 le16_to_cpu(resp->cmpl_aggr_dma_tmr_during_int_max);
6404 coal_cap->int_lat_tmr_min_max =
6405 le16_to_cpu(resp->int_lat_tmr_min_max);
6406 coal_cap->int_lat_tmr_max_max =
6407 le16_to_cpu(resp->int_lat_tmr_max_max);
6408 coal_cap->num_cmpl_aggr_int_max =
6409 le16_to_cpu(resp->num_cmpl_aggr_int_max);
6410 coal_cap->timer_units = le16_to_cpu(resp->timer_units);
6412 mutex_unlock(&bp->hwrm_cmd_lock);
6415 static u16 bnxt_usec_to_coal_tmr(struct bnxt *bp, u16 usec)
6417 struct bnxt_coal_cap *coal_cap = &bp->coal_cap;
6419 return usec * 1000 / coal_cap->timer_units;
6422 static void bnxt_hwrm_set_coal_params(struct bnxt *bp,
6423 struct bnxt_coal *hw_coal,
6424 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *req)
6426 struct bnxt_coal_cap *coal_cap = &bp->coal_cap;
6427 u32 cmpl_params = coal_cap->cmpl_params;
6428 u16 val, tmr, max, flags = 0;
6430 max = hw_coal->bufs_per_record * 128;
6431 if (hw_coal->budget)
6432 max = hw_coal->bufs_per_record * hw_coal->budget;
6433 max = min_t(u16, max, coal_cap->num_cmpl_aggr_int_max);
6435 val = clamp_t(u16, hw_coal->coal_bufs, 1, max);
6436 req->num_cmpl_aggr_int = cpu_to_le16(val);
6438 val = min_t(u16, val, coal_cap->num_cmpl_dma_aggr_max);
6439 req->num_cmpl_dma_aggr = cpu_to_le16(val);
6441 val = clamp_t(u16, hw_coal->coal_bufs_irq, 1,
6442 coal_cap->num_cmpl_dma_aggr_during_int_max);
6443 req->num_cmpl_dma_aggr_during_int = cpu_to_le16(val);
6445 tmr = bnxt_usec_to_coal_tmr(bp, hw_coal->coal_ticks);
6446 tmr = clamp_t(u16, tmr, 1, coal_cap->int_lat_tmr_max_max);
6447 req->int_lat_tmr_max = cpu_to_le16(tmr);
6449 /* min timer set to 1/2 of interrupt timer */
6450 if (cmpl_params & RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_INT_LAT_TMR_MIN) {
6452 val = clamp_t(u16, val, 1, coal_cap->int_lat_tmr_min_max);
6453 req->int_lat_tmr_min = cpu_to_le16(val);
6454 req->enables |= cpu_to_le16(BNXT_COAL_CMPL_MIN_TMR_ENABLE);
6457 /* buf timer set to 1/4 of interrupt timer */
6458 val = clamp_t(u16, tmr / 4, 1, coal_cap->cmpl_aggr_dma_tmr_max);
6459 req->cmpl_aggr_dma_tmr = cpu_to_le16(val);
6462 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_DMA_AGGR_DURING_INT) {
6463 tmr = bnxt_usec_to_coal_tmr(bp, hw_coal->coal_ticks_irq);
6464 val = clamp_t(u16, tmr, 1,
6465 coal_cap->cmpl_aggr_dma_tmr_during_int_max);
6466 req->cmpl_aggr_dma_tmr_during_int = cpu_to_le16(val);
6468 cpu_to_le16(BNXT_COAL_CMPL_AGGR_TMR_DURING_INT_ENABLE);
6471 if (cmpl_params & RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_TIMER_RESET)
6472 flags |= RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET;
6473 if ((cmpl_params & RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_RING_IDLE) &&
6474 hw_coal->idle_thresh && hw_coal->coal_ticks < hw_coal->idle_thresh)
6475 flags |= RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_RING_IDLE;
6476 req->flags = cpu_to_le16(flags);
6477 req->enables |= cpu_to_le16(BNXT_COAL_CMPL_ENABLES);
6480 /* Caller holds bp->hwrm_cmd_lock */
6481 static int __bnxt_hwrm_set_coal_nq(struct bnxt *bp, struct bnxt_napi *bnapi,
6482 struct bnxt_coal *hw_coal)
6484 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req = {0};
6485 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
6486 struct bnxt_coal_cap *coal_cap = &bp->coal_cap;
6487 u32 nq_params = coal_cap->nq_params;
6490 if (!(nq_params & RING_AGGINT_QCAPS_RESP_NQ_PARAMS_INT_LAT_TMR_MIN))
6493 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS,
6495 req.ring_id = cpu_to_le16(cpr->cp_ring_struct.fw_ring_id);
6497 cpu_to_le16(RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_IS_NQ);
6499 tmr = bnxt_usec_to_coal_tmr(bp, hw_coal->coal_ticks) / 2;
6500 tmr = clamp_t(u16, tmr, 1, coal_cap->int_lat_tmr_min_max);
6501 req.int_lat_tmr_min = cpu_to_le16(tmr);
6502 req.enables |= cpu_to_le16(BNXT_COAL_CMPL_MIN_TMR_ENABLE);
6503 return _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6506 int bnxt_hwrm_set_ring_coal(struct bnxt *bp, struct bnxt_napi *bnapi)
6508 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req_rx = {0};
6509 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
6510 struct bnxt_coal coal;
6512 /* Tick values in micro seconds.
6513 * 1 coal_buf x bufs_per_record = 1 completion record.
6515 memcpy(&coal, &bp->rx_coal, sizeof(struct bnxt_coal));
6517 coal.coal_ticks = cpr->rx_ring_coal.coal_ticks;
6518 coal.coal_bufs = cpr->rx_ring_coal.coal_bufs;
6520 if (!bnapi->rx_ring)
6523 bnxt_hwrm_cmd_hdr_init(bp, &req_rx,
6524 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS, -1, -1);
6526 bnxt_hwrm_set_coal_params(bp, &coal, &req_rx);
6528 req_rx.ring_id = cpu_to_le16(bnxt_cp_ring_for_rx(bp, bnapi->rx_ring));
6530 return hwrm_send_message(bp, &req_rx, sizeof(req_rx),
6534 int bnxt_hwrm_set_coal(struct bnxt *bp)
6537 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req_rx = {0},
6540 bnxt_hwrm_cmd_hdr_init(bp, &req_rx,
6541 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS, -1, -1);
6542 bnxt_hwrm_cmd_hdr_init(bp, &req_tx,
6543 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS, -1, -1);
6545 bnxt_hwrm_set_coal_params(bp, &bp->rx_coal, &req_rx);
6546 bnxt_hwrm_set_coal_params(bp, &bp->tx_coal, &req_tx);
6548 mutex_lock(&bp->hwrm_cmd_lock);
6549 for (i = 0; i < bp->cp_nr_rings; i++) {
6550 struct bnxt_napi *bnapi = bp->bnapi[i];
6551 struct bnxt_coal *hw_coal;
6555 if (!bnapi->rx_ring) {
6556 ring_id = bnxt_cp_ring_for_tx(bp, bnapi->tx_ring);
6559 ring_id = bnxt_cp_ring_for_rx(bp, bnapi->rx_ring);
6561 req->ring_id = cpu_to_le16(ring_id);
6563 rc = _hwrm_send_message(bp, req, sizeof(*req),
6568 if (!(bp->flags & BNXT_FLAG_CHIP_P5))
6571 if (bnapi->rx_ring && bnapi->tx_ring) {
6573 ring_id = bnxt_cp_ring_for_tx(bp, bnapi->tx_ring);
6574 req->ring_id = cpu_to_le16(ring_id);
6575 rc = _hwrm_send_message(bp, req, sizeof(*req),
6581 hw_coal = &bp->rx_coal;
6583 hw_coal = &bp->tx_coal;
6584 __bnxt_hwrm_set_coal_nq(bp, bnapi, hw_coal);
6586 mutex_unlock(&bp->hwrm_cmd_lock);
6590 static void bnxt_hwrm_stat_ctx_free(struct bnxt *bp)
6592 struct hwrm_stat_ctx_clr_stats_input req0 = {0};
6593 struct hwrm_stat_ctx_free_input req = {0};
6599 if (BNXT_CHIP_TYPE_NITRO_A0(bp))
6602 bnxt_hwrm_cmd_hdr_init(bp, &req0, HWRM_STAT_CTX_CLR_STATS, -1, -1);
6603 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_STAT_CTX_FREE, -1, -1);
6605 mutex_lock(&bp->hwrm_cmd_lock);
6606 for (i = 0; i < bp->cp_nr_rings; i++) {
6607 struct bnxt_napi *bnapi = bp->bnapi[i];
6608 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
6610 if (cpr->hw_stats_ctx_id != INVALID_STATS_CTX_ID) {
6611 req.stat_ctx_id = cpu_to_le32(cpr->hw_stats_ctx_id);
6612 if (BNXT_FW_MAJ(bp) <= 20) {
6613 req0.stat_ctx_id = req.stat_ctx_id;
6614 _hwrm_send_message(bp, &req0, sizeof(req0),
6617 _hwrm_send_message(bp, &req, sizeof(req),
6620 cpr->hw_stats_ctx_id = INVALID_STATS_CTX_ID;
6623 mutex_unlock(&bp->hwrm_cmd_lock);
6626 static int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp)
6629 struct hwrm_stat_ctx_alloc_input req = {0};
6630 struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;
6632 if (BNXT_CHIP_TYPE_NITRO_A0(bp))
6635 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_STAT_CTX_ALLOC, -1, -1);
6637 req.stats_dma_length = cpu_to_le16(bp->hw_ring_stats_size);
6638 req.update_period_ms = cpu_to_le32(bp->stats_coal_ticks / 1000);
6640 mutex_lock(&bp->hwrm_cmd_lock);
6641 for (i = 0; i < bp->cp_nr_rings; i++) {
6642 struct bnxt_napi *bnapi = bp->bnapi[i];
6643 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
6645 req.stats_dma_addr = cpu_to_le64(cpr->stats.hw_stats_map);
6647 rc = _hwrm_send_message(bp, &req, sizeof(req),
6652 cpr->hw_stats_ctx_id = le32_to_cpu(resp->stat_ctx_id);
6654 bp->grp_info[i].fw_stats_ctx = cpr->hw_stats_ctx_id;
6656 mutex_unlock(&bp->hwrm_cmd_lock);
6660 static int bnxt_hwrm_func_qcfg(struct bnxt *bp)
6662 struct hwrm_func_qcfg_input req = {0};
6663 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
6664 u32 min_db_offset = 0;
6668 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCFG, -1, -1);
6669 req.fid = cpu_to_le16(0xffff);
6670 mutex_lock(&bp->hwrm_cmd_lock);
6671 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6673 goto func_qcfg_exit;
6675 #ifdef CONFIG_BNXT_SRIOV
6677 struct bnxt_vf_info *vf = &bp->vf;
6679 vf->vlan = le16_to_cpu(resp->vlan) & VLAN_VID_MASK;
6681 bp->pf.registered_vfs = le16_to_cpu(resp->registered_vfs);
6684 flags = le16_to_cpu(resp->flags);
6685 if (flags & (FUNC_QCFG_RESP_FLAGS_FW_DCBX_AGENT_ENABLED |
6686 FUNC_QCFG_RESP_FLAGS_FW_LLDP_AGENT_ENABLED)) {
6687 bp->fw_cap |= BNXT_FW_CAP_LLDP_AGENT;
6688 if (flags & FUNC_QCFG_RESP_FLAGS_FW_DCBX_AGENT_ENABLED)
6689 bp->fw_cap |= BNXT_FW_CAP_DCBX_AGENT;
6691 if (BNXT_PF(bp) && (flags & FUNC_QCFG_RESP_FLAGS_MULTI_HOST))
6692 bp->flags |= BNXT_FLAG_MULTI_HOST;
6693 if (flags & FUNC_QCFG_RESP_FLAGS_RING_MONITOR_ENABLED)
6694 bp->fw_cap |= BNXT_FW_CAP_RING_MONITOR;
6696 switch (resp->port_partition_type) {
6697 case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_0:
6698 case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_5:
6699 case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR2_0:
6700 bp->port_partition_type = resp->port_partition_type;
6703 if (bp->hwrm_spec_code < 0x10707 ||
6704 resp->evb_mode == FUNC_QCFG_RESP_EVB_MODE_VEB)
6705 bp->br_mode = BRIDGE_MODE_VEB;
6706 else if (resp->evb_mode == FUNC_QCFG_RESP_EVB_MODE_VEPA)
6707 bp->br_mode = BRIDGE_MODE_VEPA;
6709 bp->br_mode = BRIDGE_MODE_UNDEF;
6711 bp->max_mtu = le16_to_cpu(resp->max_mtu_configured);
6713 bp->max_mtu = BNXT_MAX_MTU;
6716 goto func_qcfg_exit;
6718 if (bp->flags & BNXT_FLAG_CHIP_P5) {
6720 min_db_offset = DB_PF_OFFSET_P5;
6722 min_db_offset = DB_VF_OFFSET_P5;
6724 bp->db_size = PAGE_ALIGN(le16_to_cpu(resp->l2_doorbell_bar_size_kb) *
6726 if (!bp->db_size || bp->db_size > pci_resource_len(bp->pdev, 2) ||
6727 bp->db_size <= min_db_offset)
6728 bp->db_size = pci_resource_len(bp->pdev, 2);
6731 mutex_unlock(&bp->hwrm_cmd_lock);
6735 static int bnxt_hwrm_func_backing_store_qcaps(struct bnxt *bp)
6737 struct hwrm_func_backing_store_qcaps_input req = {0};
6738 struct hwrm_func_backing_store_qcaps_output *resp =
6739 bp->hwrm_cmd_resp_addr;
6742 if (bp->hwrm_spec_code < 0x10902 || BNXT_VF(bp) || bp->ctx)
6745 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_BACKING_STORE_QCAPS, -1, -1);
6746 mutex_lock(&bp->hwrm_cmd_lock);
6747 rc = _hwrm_send_message_silent(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6749 struct bnxt_ctx_pg_info *ctx_pg;
6750 struct bnxt_ctx_mem_info *ctx;
6753 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
6758 ctx->qp_max_entries = le32_to_cpu(resp->qp_max_entries);
6759 ctx->qp_min_qp1_entries = le16_to_cpu(resp->qp_min_qp1_entries);
6760 ctx->qp_max_l2_entries = le16_to_cpu(resp->qp_max_l2_entries);
6761 ctx->qp_entry_size = le16_to_cpu(resp->qp_entry_size);
6762 ctx->srq_max_l2_entries = le16_to_cpu(resp->srq_max_l2_entries);
6763 ctx->srq_max_entries = le32_to_cpu(resp->srq_max_entries);
6764 ctx->srq_entry_size = le16_to_cpu(resp->srq_entry_size);
6765 ctx->cq_max_l2_entries = le16_to_cpu(resp->cq_max_l2_entries);
6766 ctx->cq_max_entries = le32_to_cpu(resp->cq_max_entries);
6767 ctx->cq_entry_size = le16_to_cpu(resp->cq_entry_size);
6768 ctx->vnic_max_vnic_entries =
6769 le16_to_cpu(resp->vnic_max_vnic_entries);
6770 ctx->vnic_max_ring_table_entries =
6771 le16_to_cpu(resp->vnic_max_ring_table_entries);
6772 ctx->vnic_entry_size = le16_to_cpu(resp->vnic_entry_size);
6773 ctx->stat_max_entries = le32_to_cpu(resp->stat_max_entries);
6774 ctx->stat_entry_size = le16_to_cpu(resp->stat_entry_size);
6775 ctx->tqm_entry_size = le16_to_cpu(resp->tqm_entry_size);
6776 ctx->tqm_min_entries_per_ring =
6777 le32_to_cpu(resp->tqm_min_entries_per_ring);
6778 ctx->tqm_max_entries_per_ring =
6779 le32_to_cpu(resp->tqm_max_entries_per_ring);
6780 ctx->tqm_entries_multiple = resp->tqm_entries_multiple;
6781 if (!ctx->tqm_entries_multiple)
6782 ctx->tqm_entries_multiple = 1;
6783 ctx->mrav_max_entries = le32_to_cpu(resp->mrav_max_entries);
6784 ctx->mrav_entry_size = le16_to_cpu(resp->mrav_entry_size);
6785 ctx->mrav_num_entries_units =
6786 le16_to_cpu(resp->mrav_num_entries_units);
6787 ctx->tim_entry_size = le16_to_cpu(resp->tim_entry_size);
6788 ctx->tim_max_entries = le32_to_cpu(resp->tim_max_entries);
6789 ctx->ctx_kind_initializer = resp->ctx_kind_initializer;
6790 ctx->tqm_fp_rings_count = resp->tqm_fp_rings_count;
6791 if (!ctx->tqm_fp_rings_count)
6792 ctx->tqm_fp_rings_count = bp->max_q;
6793 else if (ctx->tqm_fp_rings_count > BNXT_MAX_TQM_FP_RINGS)
6794 ctx->tqm_fp_rings_count = BNXT_MAX_TQM_FP_RINGS;
6796 tqm_rings = ctx->tqm_fp_rings_count + BNXT_MAX_TQM_SP_RINGS;
6797 ctx_pg = kcalloc(tqm_rings, sizeof(*ctx_pg), GFP_KERNEL);
6803 for (i = 0; i < tqm_rings; i++, ctx_pg++)
6804 ctx->tqm_mem[i] = ctx_pg;
6810 mutex_unlock(&bp->hwrm_cmd_lock);
6814 static void bnxt_hwrm_set_pg_attr(struct bnxt_ring_mem_info *rmem, u8 *pg_attr,
6819 if (BNXT_PAGE_SHIFT == 13)
6821 else if (BNXT_PAGE_SIZE == 16)
6825 if (rmem->depth >= 1) {
6826 if (rmem->depth == 2)
6830 *pg_dir = cpu_to_le64(rmem->pg_tbl_map);
6832 *pg_dir = cpu_to_le64(rmem->dma_arr[0]);
6836 #define FUNC_BACKING_STORE_CFG_REQ_DFLT_ENABLES \
6837 (FUNC_BACKING_STORE_CFG_REQ_ENABLES_QP | \
6838 FUNC_BACKING_STORE_CFG_REQ_ENABLES_SRQ | \
6839 FUNC_BACKING_STORE_CFG_REQ_ENABLES_CQ | \
6840 FUNC_BACKING_STORE_CFG_REQ_ENABLES_VNIC | \
6841 FUNC_BACKING_STORE_CFG_REQ_ENABLES_STAT)
6843 static int bnxt_hwrm_func_backing_store_cfg(struct bnxt *bp, u32 enables)
6845 struct hwrm_func_backing_store_cfg_input req = {0};
6846 struct bnxt_ctx_mem_info *ctx = bp->ctx;
6847 struct bnxt_ctx_pg_info *ctx_pg;
6848 __le32 *num_entries;
6858 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_BACKING_STORE_CFG, -1, -1);
6859 req.enables = cpu_to_le32(enables);
6861 if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_QP) {
6862 ctx_pg = &ctx->qp_mem;
6863 req.qp_num_entries = cpu_to_le32(ctx_pg->entries);
6864 req.qp_num_qp1_entries = cpu_to_le16(ctx->qp_min_qp1_entries);
6865 req.qp_num_l2_entries = cpu_to_le16(ctx->qp_max_l2_entries);
6866 req.qp_entry_size = cpu_to_le16(ctx->qp_entry_size);
6867 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
6868 &req.qpc_pg_size_qpc_lvl,
6871 if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_SRQ) {
6872 ctx_pg = &ctx->srq_mem;
6873 req.srq_num_entries = cpu_to_le32(ctx_pg->entries);
6874 req.srq_num_l2_entries = cpu_to_le16(ctx->srq_max_l2_entries);
6875 req.srq_entry_size = cpu_to_le16(ctx->srq_entry_size);
6876 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
6877 &req.srq_pg_size_srq_lvl,
6880 if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_CQ) {
6881 ctx_pg = &ctx->cq_mem;
6882 req.cq_num_entries = cpu_to_le32(ctx_pg->entries);
6883 req.cq_num_l2_entries = cpu_to_le16(ctx->cq_max_l2_entries);
6884 req.cq_entry_size = cpu_to_le16(ctx->cq_entry_size);
6885 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, &req.cq_pg_size_cq_lvl,
6888 if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_VNIC) {
6889 ctx_pg = &ctx->vnic_mem;
6890 req.vnic_num_vnic_entries =
6891 cpu_to_le16(ctx->vnic_max_vnic_entries);
6892 req.vnic_num_ring_table_entries =
6893 cpu_to_le16(ctx->vnic_max_ring_table_entries);
6894 req.vnic_entry_size = cpu_to_le16(ctx->vnic_entry_size);
6895 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
6896 &req.vnic_pg_size_vnic_lvl,
6897 &req.vnic_page_dir);
6899 if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_STAT) {
6900 ctx_pg = &ctx->stat_mem;
6901 req.stat_num_entries = cpu_to_le32(ctx->stat_max_entries);
6902 req.stat_entry_size = cpu_to_le16(ctx->stat_entry_size);
6903 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
6904 &req.stat_pg_size_stat_lvl,
6905 &req.stat_page_dir);
6907 if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_MRAV) {
6908 ctx_pg = &ctx->mrav_mem;
6909 req.mrav_num_entries = cpu_to_le32(ctx_pg->entries);
6910 if (ctx->mrav_num_entries_units)
6912 FUNC_BACKING_STORE_CFG_REQ_FLAGS_MRAV_RESERVATION_SPLIT;
6913 req.mrav_entry_size = cpu_to_le16(ctx->mrav_entry_size);
6914 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
6915 &req.mrav_pg_size_mrav_lvl,
6916 &req.mrav_page_dir);
6918 if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_TIM) {
6919 ctx_pg = &ctx->tim_mem;
6920 req.tim_num_entries = cpu_to_le32(ctx_pg->entries);
6921 req.tim_entry_size = cpu_to_le16(ctx->tim_entry_size);
6922 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
6923 &req.tim_pg_size_tim_lvl,
6926 for (i = 0, num_entries = &req.tqm_sp_num_entries,
6927 pg_attr = &req.tqm_sp_pg_size_tqm_sp_lvl,
6928 pg_dir = &req.tqm_sp_page_dir,
6929 ena = FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_SP;
6930 i < BNXT_MAX_TQM_RINGS;
6931 i++, num_entries++, pg_attr++, pg_dir++, ena <<= 1) {
6932 if (!(enables & ena))
6935 req.tqm_entry_size = cpu_to_le16(ctx->tqm_entry_size);
6936 ctx_pg = ctx->tqm_mem[i];
6937 *num_entries = cpu_to_le32(ctx_pg->entries);
6938 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, pg_attr, pg_dir);
6940 req.flags = cpu_to_le32(flags);
6941 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6944 static int bnxt_alloc_ctx_mem_blk(struct bnxt *bp,
6945 struct bnxt_ctx_pg_info *ctx_pg)
6947 struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
6949 rmem->page_size = BNXT_PAGE_SIZE;
6950 rmem->pg_arr = ctx_pg->ctx_pg_arr;
6951 rmem->dma_arr = ctx_pg->ctx_dma_arr;
6952 rmem->flags = BNXT_RMEM_VALID_PTE_FLAG;
6953 if (rmem->depth >= 1)
6954 rmem->flags |= BNXT_RMEM_USE_FULL_PAGE_FLAG;
6955 return bnxt_alloc_ring(bp, rmem);
6958 static int bnxt_alloc_ctx_pg_tbls(struct bnxt *bp,
6959 struct bnxt_ctx_pg_info *ctx_pg, u32 mem_size,
6960 u8 depth, bool use_init_val)
6962 struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
6968 ctx_pg->nr_pages = DIV_ROUND_UP(mem_size, BNXT_PAGE_SIZE);
6969 if (ctx_pg->nr_pages > MAX_CTX_TOTAL_PAGES) {
6970 ctx_pg->nr_pages = 0;
6973 if (ctx_pg->nr_pages > MAX_CTX_PAGES || depth > 1) {
6977 ctx_pg->ctx_pg_tbl = kcalloc(MAX_CTX_PAGES, sizeof(ctx_pg),
6979 if (!ctx_pg->ctx_pg_tbl)
6981 nr_tbls = DIV_ROUND_UP(ctx_pg->nr_pages, MAX_CTX_PAGES);
6982 rmem->nr_pages = nr_tbls;
6983 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg);
6986 for (i = 0; i < nr_tbls; i++) {
6987 struct bnxt_ctx_pg_info *pg_tbl;
6989 pg_tbl = kzalloc(sizeof(*pg_tbl), GFP_KERNEL);
6992 ctx_pg->ctx_pg_tbl[i] = pg_tbl;
6993 rmem = &pg_tbl->ring_mem;
6994 rmem->pg_tbl = ctx_pg->ctx_pg_arr[i];
6995 rmem->pg_tbl_map = ctx_pg->ctx_dma_arr[i];
6997 rmem->nr_pages = MAX_CTX_PAGES;
6999 rmem->init_val = bp->ctx->ctx_kind_initializer;
7000 if (i == (nr_tbls - 1)) {
7001 int rem = ctx_pg->nr_pages % MAX_CTX_PAGES;
7004 rmem->nr_pages = rem;
7006 rc = bnxt_alloc_ctx_mem_blk(bp, pg_tbl);
7011 rmem->nr_pages = DIV_ROUND_UP(mem_size, BNXT_PAGE_SIZE);
7012 if (rmem->nr_pages > 1 || depth)
7015 rmem->init_val = bp->ctx->ctx_kind_initializer;
7016 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg);
7021 static void bnxt_free_ctx_pg_tbls(struct bnxt *bp,
7022 struct bnxt_ctx_pg_info *ctx_pg)
7024 struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
7026 if (rmem->depth > 1 || ctx_pg->nr_pages > MAX_CTX_PAGES ||
7027 ctx_pg->ctx_pg_tbl) {
7028 int i, nr_tbls = rmem->nr_pages;
7030 for (i = 0; i < nr_tbls; i++) {
7031 struct bnxt_ctx_pg_info *pg_tbl;
7032 struct bnxt_ring_mem_info *rmem2;
7034 pg_tbl = ctx_pg->ctx_pg_tbl[i];
7037 rmem2 = &pg_tbl->ring_mem;
7038 bnxt_free_ring(bp, rmem2);
7039 ctx_pg->ctx_pg_arr[i] = NULL;
7041 ctx_pg->ctx_pg_tbl[i] = NULL;
7043 kfree(ctx_pg->ctx_pg_tbl);
7044 ctx_pg->ctx_pg_tbl = NULL;
7046 bnxt_free_ring(bp, rmem);
7047 ctx_pg->nr_pages = 0;
7050 static void bnxt_free_ctx_mem(struct bnxt *bp)
7052 struct bnxt_ctx_mem_info *ctx = bp->ctx;
7058 if (ctx->tqm_mem[0]) {
7059 for (i = 0; i < ctx->tqm_fp_rings_count + 1; i++)
7060 bnxt_free_ctx_pg_tbls(bp, ctx->tqm_mem[i]);
7061 kfree(ctx->tqm_mem[0]);
7062 ctx->tqm_mem[0] = NULL;
7065 bnxt_free_ctx_pg_tbls(bp, &ctx->tim_mem);
7066 bnxt_free_ctx_pg_tbls(bp, &ctx->mrav_mem);
7067 bnxt_free_ctx_pg_tbls(bp, &ctx->stat_mem);
7068 bnxt_free_ctx_pg_tbls(bp, &ctx->vnic_mem);
7069 bnxt_free_ctx_pg_tbls(bp, &ctx->cq_mem);
7070 bnxt_free_ctx_pg_tbls(bp, &ctx->srq_mem);
7071 bnxt_free_ctx_pg_tbls(bp, &ctx->qp_mem);
7072 ctx->flags &= ~BNXT_CTX_FLAG_INITED;
7075 static int bnxt_alloc_ctx_mem(struct bnxt *bp)
7077 struct bnxt_ctx_pg_info *ctx_pg;
7078 struct bnxt_ctx_mem_info *ctx;
7079 u32 mem_size, ena, entries;
7080 u32 entries_sp, min;
7087 rc = bnxt_hwrm_func_backing_store_qcaps(bp);
7089 netdev_err(bp->dev, "Failed querying context mem capability, rc = %d.\n",
7094 if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED))
7097 if ((bp->flags & BNXT_FLAG_ROCE_CAP) && !is_kdump_kernel()) {
7103 ctx_pg = &ctx->qp_mem;
7104 ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries +
7106 mem_size = ctx->qp_entry_size * ctx_pg->entries;
7107 rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, pg_lvl, true);
7111 ctx_pg = &ctx->srq_mem;
7112 ctx_pg->entries = ctx->srq_max_l2_entries + extra_srqs;
7113 mem_size = ctx->srq_entry_size * ctx_pg->entries;
7114 rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, pg_lvl, true);
7118 ctx_pg = &ctx->cq_mem;
7119 ctx_pg->entries = ctx->cq_max_l2_entries + extra_qps * 2;
7120 mem_size = ctx->cq_entry_size * ctx_pg->entries;
7121 rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, pg_lvl, true);
7125 ctx_pg = &ctx->vnic_mem;
7126 ctx_pg->entries = ctx->vnic_max_vnic_entries +
7127 ctx->vnic_max_ring_table_entries;
7128 mem_size = ctx->vnic_entry_size * ctx_pg->entries;
7129 rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, 1, true);
7133 ctx_pg = &ctx->stat_mem;
7134 ctx_pg->entries = ctx->stat_max_entries;
7135 mem_size = ctx->stat_entry_size * ctx_pg->entries;
7136 rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, 1, true);
7141 if (!(bp->flags & BNXT_FLAG_ROCE_CAP))
7144 ctx_pg = &ctx->mrav_mem;
7145 /* 128K extra is needed to accommodate static AH context
7146 * allocation by f/w.
7148 num_mr = 1024 * 256;
7149 num_ah = 1024 * 128;
7150 ctx_pg->entries = num_mr + num_ah;
7151 mem_size = ctx->mrav_entry_size * ctx_pg->entries;
7152 rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, 2, true);
7155 ena = FUNC_BACKING_STORE_CFG_REQ_ENABLES_MRAV;
7156 if (ctx->mrav_num_entries_units)
7158 ((num_mr / ctx->mrav_num_entries_units) << 16) |
7159 (num_ah / ctx->mrav_num_entries_units);
7161 ctx_pg = &ctx->tim_mem;
7162 ctx_pg->entries = ctx->qp_mem.entries;
7163 mem_size = ctx->tim_entry_size * ctx_pg->entries;
7164 rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, 1, false);
7167 ena |= FUNC_BACKING_STORE_CFG_REQ_ENABLES_TIM;
7170 min = ctx->tqm_min_entries_per_ring;
7171 entries_sp = ctx->vnic_max_vnic_entries + ctx->qp_max_l2_entries +
7172 2 * (extra_qps + ctx->qp_min_qp1_entries) + min;
7173 entries_sp = roundup(entries_sp, ctx->tqm_entries_multiple);
7174 entries = ctx->qp_max_l2_entries + extra_qps + ctx->qp_min_qp1_entries;
7175 entries = roundup(entries, ctx->tqm_entries_multiple);
7176 entries = clamp_t(u32, entries, min, ctx->tqm_max_entries_per_ring);
7177 for (i = 0; i < ctx->tqm_fp_rings_count + 1; i++) {
7178 ctx_pg = ctx->tqm_mem[i];
7179 ctx_pg->entries = i ? entries : entries_sp;
7180 mem_size = ctx->tqm_entry_size * ctx_pg->entries;
7181 rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, 1, false);
7184 ena |= FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_SP << i;
7186 ena |= FUNC_BACKING_STORE_CFG_REQ_DFLT_ENABLES;
7187 rc = bnxt_hwrm_func_backing_store_cfg(bp, ena);
7189 netdev_err(bp->dev, "Failed configuring context mem, rc = %d.\n",
7193 ctx->flags |= BNXT_CTX_FLAG_INITED;
7197 int bnxt_hwrm_func_resc_qcaps(struct bnxt *bp, bool all)
7199 struct hwrm_func_resource_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
7200 struct hwrm_func_resource_qcaps_input req = {0};
7201 struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
7204 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_RESOURCE_QCAPS, -1, -1);
7205 req.fid = cpu_to_le16(0xffff);
7207 mutex_lock(&bp->hwrm_cmd_lock);
7208 rc = _hwrm_send_message_silent(bp, &req, sizeof(req),
7211 goto hwrm_func_resc_qcaps_exit;
7213 hw_resc->max_tx_sch_inputs = le16_to_cpu(resp->max_tx_scheduler_inputs);
7215 goto hwrm_func_resc_qcaps_exit;
7217 hw_resc->min_rsscos_ctxs = le16_to_cpu(resp->min_rsscos_ctx);
7218 hw_resc->max_rsscos_ctxs = le16_to_cpu(resp->max_rsscos_ctx);
7219 hw_resc->min_cp_rings = le16_to_cpu(resp->min_cmpl_rings);
7220 hw_resc->max_cp_rings = le16_to_cpu(resp->max_cmpl_rings);
7221 hw_resc->min_tx_rings = le16_to_cpu(resp->min_tx_rings);
7222 hw_resc->max_tx_rings = le16_to_cpu(resp->max_tx_rings);
7223 hw_resc->min_rx_rings = le16_to_cpu(resp->min_rx_rings);
7224 hw_resc->max_rx_rings = le16_to_cpu(resp->max_rx_rings);
7225 hw_resc->min_hw_ring_grps = le16_to_cpu(resp->min_hw_ring_grps);
7226 hw_resc->max_hw_ring_grps = le16_to_cpu(resp->max_hw_ring_grps);
7227 hw_resc->min_l2_ctxs = le16_to_cpu(resp->min_l2_ctxs);
7228 hw_resc->max_l2_ctxs = le16_to_cpu(resp->max_l2_ctxs);
7229 hw_resc->min_vnics = le16_to_cpu(resp->min_vnics);
7230 hw_resc->max_vnics = le16_to_cpu(resp->max_vnics);
7231 hw_resc->min_stat_ctxs = le16_to_cpu(resp->min_stat_ctx);
7232 hw_resc->max_stat_ctxs = le16_to_cpu(resp->max_stat_ctx);
7234 if (bp->flags & BNXT_FLAG_CHIP_P5) {
7235 u16 max_msix = le16_to_cpu(resp->max_msix);
7237 hw_resc->max_nqs = max_msix;
7238 hw_resc->max_hw_ring_grps = hw_resc->max_rx_rings;
7242 struct bnxt_pf_info *pf = &bp->pf;
7244 pf->vf_resv_strategy =
7245 le16_to_cpu(resp->vf_reservation_strategy);
7246 if (pf->vf_resv_strategy > BNXT_VF_RESV_STRATEGY_MINIMAL_STATIC)
7247 pf->vf_resv_strategy = BNXT_VF_RESV_STRATEGY_MAXIMAL;
7249 hwrm_func_resc_qcaps_exit:
7250 mutex_unlock(&bp->hwrm_cmd_lock);
7254 static int __bnxt_hwrm_func_qcaps(struct bnxt *bp)
7257 struct hwrm_func_qcaps_input req = {0};
7258 struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
7259 struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
7260 u32 flags, flags_ext;
7262 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCAPS, -1, -1);
7263 req.fid = cpu_to_le16(0xffff);
7265 mutex_lock(&bp->hwrm_cmd_lock);
7266 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
7268 goto hwrm_func_qcaps_exit;
7270 flags = le32_to_cpu(resp->flags);
7271 if (flags & FUNC_QCAPS_RESP_FLAGS_ROCE_V1_SUPPORTED)
7272 bp->flags |= BNXT_FLAG_ROCEV1_CAP;
7273 if (flags & FUNC_QCAPS_RESP_FLAGS_ROCE_V2_SUPPORTED)
7274 bp->flags |= BNXT_FLAG_ROCEV2_CAP;
7275 if (flags & FUNC_QCAPS_RESP_FLAGS_PCIE_STATS_SUPPORTED)
7276 bp->fw_cap |= BNXT_FW_CAP_PCIE_STATS_SUPPORTED;
7277 if (flags & FUNC_QCAPS_RESP_FLAGS_HOT_RESET_CAPABLE)
7278 bp->fw_cap |= BNXT_FW_CAP_HOT_RESET;
7279 if (flags & FUNC_QCAPS_RESP_FLAGS_EXT_STATS_SUPPORTED)
7280 bp->fw_cap |= BNXT_FW_CAP_EXT_STATS_SUPPORTED;
7281 if (flags & FUNC_QCAPS_RESP_FLAGS_ERROR_RECOVERY_CAPABLE)
7282 bp->fw_cap |= BNXT_FW_CAP_ERROR_RECOVERY;
7283 if (flags & FUNC_QCAPS_RESP_FLAGS_ERR_RECOVER_RELOAD)
7284 bp->fw_cap |= BNXT_FW_CAP_ERR_RECOVER_RELOAD;
7285 if (!(flags & FUNC_QCAPS_RESP_FLAGS_VLAN_ACCELERATION_TX_DISABLED))
7286 bp->fw_cap |= BNXT_FW_CAP_VLAN_TX_INSERT;
7288 flags_ext = le32_to_cpu(resp->flags_ext);
7289 if (flags_ext & FUNC_QCAPS_RESP_FLAGS_EXT_EXT_HW_STATS_SUPPORTED)
7290 bp->fw_cap |= BNXT_FW_CAP_EXT_HW_STATS_SUPPORTED;
7292 bp->tx_push_thresh = 0;
7293 if ((flags & FUNC_QCAPS_RESP_FLAGS_PUSH_MODE_SUPPORTED) &&
7294 BNXT_FW_MAJ(bp) > 217)
7295 bp->tx_push_thresh = BNXT_TX_PUSH_THRESH;
7297 hw_resc->max_rsscos_ctxs = le16_to_cpu(resp->max_rsscos_ctx);
7298 hw_resc->max_cp_rings = le16_to_cpu(resp->max_cmpl_rings);
7299 hw_resc->max_tx_rings = le16_to_cpu(resp->max_tx_rings);
7300 hw_resc->max_rx_rings = le16_to_cpu(resp->max_rx_rings);
7301 hw_resc->max_hw_ring_grps = le32_to_cpu(resp->max_hw_ring_grps);
7302 if (!hw_resc->max_hw_ring_grps)
7303 hw_resc->max_hw_ring_grps = hw_resc->max_tx_rings;
7304 hw_resc->max_l2_ctxs = le16_to_cpu(resp->max_l2_ctxs);
7305 hw_resc->max_vnics = le16_to_cpu(resp->max_vnics);
7306 hw_resc->max_stat_ctxs = le16_to_cpu(resp->max_stat_ctx);
7309 struct bnxt_pf_info *pf = &bp->pf;
7311 pf->fw_fid = le16_to_cpu(resp->fid);
7312 pf->port_id = le16_to_cpu(resp->port_id);
7313 memcpy(pf->mac_addr, resp->mac_address, ETH_ALEN);
7314 pf->first_vf_id = le16_to_cpu(resp->first_vf_id);
7315 pf->max_vfs = le16_to_cpu(resp->max_vfs);
7316 pf->max_encap_records = le32_to_cpu(resp->max_encap_records);
7317 pf->max_decap_records = le32_to_cpu(resp->max_decap_records);
7318 pf->max_tx_em_flows = le32_to_cpu(resp->max_tx_em_flows);
7319 pf->max_tx_wm_flows = le32_to_cpu(resp->max_tx_wm_flows);
7320 pf->max_rx_em_flows = le32_to_cpu(resp->max_rx_em_flows);
7321 pf->max_rx_wm_flows = le32_to_cpu(resp->max_rx_wm_flows);
7322 bp->flags &= ~BNXT_FLAG_WOL_CAP;
7323 if (flags & FUNC_QCAPS_RESP_FLAGS_WOL_MAGICPKT_SUPPORTED)
7324 bp->flags |= BNXT_FLAG_WOL_CAP;
7326 #ifdef CONFIG_BNXT_SRIOV
7327 struct bnxt_vf_info *vf = &bp->vf;
7329 vf->fw_fid = le16_to_cpu(resp->fid);
7330 memcpy(vf->mac_addr, resp->mac_address, ETH_ALEN);
7334 hwrm_func_qcaps_exit:
7335 mutex_unlock(&bp->hwrm_cmd_lock);
7339 static int bnxt_hwrm_queue_qportcfg(struct bnxt *bp);
7341 static int bnxt_hwrm_func_qcaps(struct bnxt *bp)
7345 rc = __bnxt_hwrm_func_qcaps(bp);
7348 rc = bnxt_hwrm_queue_qportcfg(bp);
7350 netdev_err(bp->dev, "hwrm query qportcfg failure rc: %d\n", rc);
7353 if (bp->hwrm_spec_code >= 0x10803) {
7354 rc = bnxt_alloc_ctx_mem(bp);
7357 rc = bnxt_hwrm_func_resc_qcaps(bp, true);
7359 bp->fw_cap |= BNXT_FW_CAP_NEW_RM;
7364 static int bnxt_hwrm_cfa_adv_flow_mgnt_qcaps(struct bnxt *bp)
7366 struct hwrm_cfa_adv_flow_mgnt_qcaps_input req = {0};
7367 struct hwrm_cfa_adv_flow_mgnt_qcaps_output *resp;
7371 if (!(bp->fw_cap & BNXT_FW_CAP_CFA_ADV_FLOW))
7374 resp = bp->hwrm_cmd_resp_addr;
7375 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_ADV_FLOW_MGNT_QCAPS, -1, -1);
7377 mutex_lock(&bp->hwrm_cmd_lock);
7378 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
7380 goto hwrm_cfa_adv_qcaps_exit;
7382 flags = le32_to_cpu(resp->flags);
7384 CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_RFS_RING_TBL_IDX_V2_SUPPORTED)
7385 bp->fw_cap |= BNXT_FW_CAP_CFA_RFS_RING_TBL_IDX_V2;
7387 hwrm_cfa_adv_qcaps_exit:
7388 mutex_unlock(&bp->hwrm_cmd_lock);
7392 static int __bnxt_alloc_fw_health(struct bnxt *bp)
7397 bp->fw_health = kzalloc(sizeof(*bp->fw_health), GFP_KERNEL);
7404 static int bnxt_alloc_fw_health(struct bnxt *bp)
7408 if (!(bp->fw_cap & BNXT_FW_CAP_HOT_RESET) &&
7409 !(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY))
7412 rc = __bnxt_alloc_fw_health(bp);
7414 bp->fw_cap &= ~BNXT_FW_CAP_HOT_RESET;
7415 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
7422 static void __bnxt_map_fw_health_reg(struct bnxt *bp, u32 reg)
7424 writel(reg & BNXT_GRC_BASE_MASK, bp->bar0 +
7425 BNXT_GRCPF_REG_WINDOW_BASE_OUT +
7426 BNXT_FW_HEALTH_WIN_MAP_OFF);
7429 static void bnxt_try_map_fw_health_reg(struct bnxt *bp)
7436 __bnxt_map_fw_health_reg(bp, HCOMM_STATUS_STRUCT_LOC);
7437 hs = bp->bar0 + BNXT_FW_HEALTH_WIN_OFF(HCOMM_STATUS_STRUCT_LOC);
7439 sig = readl(hs + offsetof(struct hcomm_status, sig_ver));
7440 if ((sig & HCOMM_STATUS_SIGNATURE_MASK) != HCOMM_STATUS_SIGNATURE_VAL) {
7442 bp->fw_health->status_reliable = false;
7446 if (__bnxt_alloc_fw_health(bp)) {
7447 netdev_warn(bp->dev, "no memory for firmware status checks\n");
7451 status_loc = readl(hs + offsetof(struct hcomm_status, fw_status_loc));
7452 bp->fw_health->regs[BNXT_FW_HEALTH_REG] = status_loc;
7453 reg_type = BNXT_FW_HEALTH_REG_TYPE(status_loc);
7454 if (reg_type == BNXT_FW_HEALTH_REG_TYPE_GRC) {
7455 __bnxt_map_fw_health_reg(bp, status_loc);
7456 bp->fw_health->mapped_regs[BNXT_FW_HEALTH_REG] =
7457 BNXT_FW_HEALTH_WIN_OFF(status_loc);
7460 bp->fw_health->status_reliable = true;
7463 static int bnxt_map_fw_health_regs(struct bnxt *bp)
7465 struct bnxt_fw_health *fw_health = bp->fw_health;
7466 u32 reg_base = 0xffffffff;
7469 /* Only pre-map the monitoring GRC registers using window 3 */
7470 for (i = 0; i < 4; i++) {
7471 u32 reg = fw_health->regs[i];
7473 if (BNXT_FW_HEALTH_REG_TYPE(reg) != BNXT_FW_HEALTH_REG_TYPE_GRC)
7475 if (reg_base == 0xffffffff)
7476 reg_base = reg & BNXT_GRC_BASE_MASK;
7477 if ((reg & BNXT_GRC_BASE_MASK) != reg_base)
7479 fw_health->mapped_regs[i] = BNXT_FW_HEALTH_WIN_OFF(reg);
7481 if (reg_base == 0xffffffff)
7484 __bnxt_map_fw_health_reg(bp, reg_base);
7488 static int bnxt_hwrm_error_recovery_qcfg(struct bnxt *bp)
7490 struct hwrm_error_recovery_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
7491 struct bnxt_fw_health *fw_health = bp->fw_health;
7492 struct hwrm_error_recovery_qcfg_input req = {0};
7495 if (!(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY))
7498 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_ERROR_RECOVERY_QCFG, -1, -1);
7499 mutex_lock(&bp->hwrm_cmd_lock);
7500 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
7502 goto err_recovery_out;
7503 fw_health->flags = le32_to_cpu(resp->flags);
7504 if ((fw_health->flags & ERROR_RECOVERY_QCFG_RESP_FLAGS_CO_CPU) &&
7505 !(bp->fw_cap & BNXT_FW_CAP_KONG_MB_CHNL)) {
7507 goto err_recovery_out;
7509 fw_health->polling_dsecs = le32_to_cpu(resp->driver_polling_freq);
7510 fw_health->master_func_wait_dsecs =
7511 le32_to_cpu(resp->master_func_wait_period);
7512 fw_health->normal_func_wait_dsecs =
7513 le32_to_cpu(resp->normal_func_wait_period);
7514 fw_health->post_reset_wait_dsecs =
7515 le32_to_cpu(resp->master_func_wait_period_after_reset);
7516 fw_health->post_reset_max_wait_dsecs =
7517 le32_to_cpu(resp->max_bailout_time_after_reset);
7518 fw_health->regs[BNXT_FW_HEALTH_REG] =
7519 le32_to_cpu(resp->fw_health_status_reg);
7520 fw_health->regs[BNXT_FW_HEARTBEAT_REG] =
7521 le32_to_cpu(resp->fw_heartbeat_reg);
7522 fw_health->regs[BNXT_FW_RESET_CNT_REG] =
7523 le32_to_cpu(resp->fw_reset_cnt_reg);
7524 fw_health->regs[BNXT_FW_RESET_INPROG_REG] =
7525 le32_to_cpu(resp->reset_inprogress_reg);
7526 fw_health->fw_reset_inprog_reg_mask =
7527 le32_to_cpu(resp->reset_inprogress_reg_mask);
7528 fw_health->fw_reset_seq_cnt = resp->reg_array_cnt;
7529 if (fw_health->fw_reset_seq_cnt >= 16) {
7531 goto err_recovery_out;
7533 for (i = 0; i < fw_health->fw_reset_seq_cnt; i++) {
7534 fw_health->fw_reset_seq_regs[i] =
7535 le32_to_cpu(resp->reset_reg[i]);
7536 fw_health->fw_reset_seq_vals[i] =
7537 le32_to_cpu(resp->reset_reg_val[i]);
7538 fw_health->fw_reset_seq_delay_msec[i] =
7539 resp->delay_after_reset[i];
7542 mutex_unlock(&bp->hwrm_cmd_lock);
7544 rc = bnxt_map_fw_health_regs(bp);
7546 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
7550 static int bnxt_hwrm_func_reset(struct bnxt *bp)
7552 struct hwrm_func_reset_input req = {0};
7554 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_RESET, -1, -1);
7557 return hwrm_send_message(bp, &req, sizeof(req), HWRM_RESET_TIMEOUT);
7560 static void bnxt_nvm_cfg_ver_get(struct bnxt *bp)
7562 struct hwrm_nvm_get_dev_info_output nvm_info;
7564 if (!bnxt_hwrm_nvm_get_dev_info(bp, &nvm_info))
7565 snprintf(bp->nvm_cfg_ver, FW_VER_STR_LEN, "%d.%d.%d",
7566 nvm_info.nvm_cfg_ver_maj, nvm_info.nvm_cfg_ver_min,
7567 nvm_info.nvm_cfg_ver_upd);
7570 static int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
7573 struct hwrm_queue_qportcfg_input req = {0};
7574 struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
7578 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_QUEUE_QPORTCFG, -1, -1);
7580 mutex_lock(&bp->hwrm_cmd_lock);
7581 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
7585 if (!resp->max_configurable_queues) {
7589 bp->max_tc = resp->max_configurable_queues;
7590 bp->max_lltc = resp->max_configurable_lossless_queues;
7591 if (bp->max_tc > BNXT_MAX_QUEUE)
7592 bp->max_tc = BNXT_MAX_QUEUE;
7594 no_rdma = !(bp->flags & BNXT_FLAG_ROCE_CAP);
7595 qptr = &resp->queue_id0;
7596 for (i = 0, j = 0; i < bp->max_tc; i++) {
7597 bp->q_info[j].queue_id = *qptr;
7598 bp->q_ids[i] = *qptr++;
7599 bp->q_info[j].queue_profile = *qptr++;
7600 bp->tc_to_qidx[j] = j;
7601 if (!BNXT_CNPQ(bp->q_info[j].queue_profile) ||
7602 (no_rdma && BNXT_PF(bp)))
7605 bp->max_q = bp->max_tc;
7606 bp->max_tc = max_t(u8, j, 1);
7608 if (resp->queue_cfg_info & QUEUE_QPORTCFG_RESP_QUEUE_CFG_INFO_ASYM_CFG)
7611 if (bp->max_lltc > bp->max_tc)
7612 bp->max_lltc = bp->max_tc;
7615 mutex_unlock(&bp->hwrm_cmd_lock);
7619 static int __bnxt_hwrm_ver_get(struct bnxt *bp, bool silent)
7621 struct hwrm_ver_get_input req = {0};
7624 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VER_GET, -1, -1);
7625 req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
7626 req.hwrm_intf_min = HWRM_VERSION_MINOR;
7627 req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
7629 rc = bnxt_hwrm_do_send_msg(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT,
7634 static int bnxt_hwrm_ver_get(struct bnxt *bp)
7636 struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
7637 u16 fw_maj, fw_min, fw_bld, fw_rsv;
7638 u32 dev_caps_cfg, hwrm_ver;
7641 bp->hwrm_max_req_len = HWRM_MAX_REQ_LEN;
7642 mutex_lock(&bp->hwrm_cmd_lock);
7643 rc = __bnxt_hwrm_ver_get(bp, false);
7645 goto hwrm_ver_get_exit;
7647 memcpy(&bp->ver_resp, resp, sizeof(struct hwrm_ver_get_output));
7649 bp->hwrm_spec_code = resp->hwrm_intf_maj_8b << 16 |
7650 resp->hwrm_intf_min_8b << 8 |
7651 resp->hwrm_intf_upd_8b;
7652 if (resp->hwrm_intf_maj_8b < 1) {
7653 netdev_warn(bp->dev, "HWRM interface %d.%d.%d is older than 1.0.0.\n",
7654 resp->hwrm_intf_maj_8b, resp->hwrm_intf_min_8b,
7655 resp->hwrm_intf_upd_8b);
7656 netdev_warn(bp->dev, "Please update firmware with HWRM interface 1.0.0 or newer.\n");
7659 hwrm_ver = HWRM_VERSION_MAJOR << 16 | HWRM_VERSION_MINOR << 8 |
7660 HWRM_VERSION_UPDATE;
7662 if (bp->hwrm_spec_code > hwrm_ver)
7663 snprintf(bp->hwrm_ver_supp, FW_VER_STR_LEN, "%d.%d.%d",
7664 HWRM_VERSION_MAJOR, HWRM_VERSION_MINOR,
7665 HWRM_VERSION_UPDATE);
7667 snprintf(bp->hwrm_ver_supp, FW_VER_STR_LEN, "%d.%d.%d",
7668 resp->hwrm_intf_maj_8b, resp->hwrm_intf_min_8b,
7669 resp->hwrm_intf_upd_8b);
7671 fw_maj = le16_to_cpu(resp->hwrm_fw_major);
7672 if (bp->hwrm_spec_code > 0x10803 && fw_maj) {
7673 fw_min = le16_to_cpu(resp->hwrm_fw_minor);
7674 fw_bld = le16_to_cpu(resp->hwrm_fw_build);
7675 fw_rsv = le16_to_cpu(resp->hwrm_fw_patch);
7676 len = FW_VER_STR_LEN;
7678 fw_maj = resp->hwrm_fw_maj_8b;
7679 fw_min = resp->hwrm_fw_min_8b;
7680 fw_bld = resp->hwrm_fw_bld_8b;
7681 fw_rsv = resp->hwrm_fw_rsvd_8b;
7682 len = BC_HWRM_STR_LEN;
7684 bp->fw_ver_code = BNXT_FW_VER_CODE(fw_maj, fw_min, fw_bld, fw_rsv);
7685 snprintf(bp->fw_ver_str, len, "%d.%d.%d.%d", fw_maj, fw_min, fw_bld,
7688 if (strlen(resp->active_pkg_name)) {
7689 int fw_ver_len = strlen(bp->fw_ver_str);
7691 snprintf(bp->fw_ver_str + fw_ver_len,
7692 FW_VER_STR_LEN - fw_ver_len - 1, "/pkg %s",
7693 resp->active_pkg_name);
7694 bp->fw_cap |= BNXT_FW_CAP_PKG_VER;
7697 bp->hwrm_cmd_timeout = le16_to_cpu(resp->def_req_timeout);
7698 if (!bp->hwrm_cmd_timeout)
7699 bp->hwrm_cmd_timeout = DFLT_HWRM_CMD_TIMEOUT;
7701 if (resp->hwrm_intf_maj_8b >= 1) {
7702 bp->hwrm_max_req_len = le16_to_cpu(resp->max_req_win_len);
7703 bp->hwrm_max_ext_req_len = le16_to_cpu(resp->max_ext_req_len);
7705 if (bp->hwrm_max_ext_req_len < HWRM_MAX_REQ_LEN)
7706 bp->hwrm_max_ext_req_len = HWRM_MAX_REQ_LEN;
7708 bp->chip_num = le16_to_cpu(resp->chip_num);
7709 bp->chip_rev = resp->chip_rev;
7710 if (bp->chip_num == CHIP_NUM_58700 && !resp->chip_rev &&
7712 bp->flags |= BNXT_FLAG_CHIP_NITRO_A0;
7714 dev_caps_cfg = le32_to_cpu(resp->dev_caps_cfg);
7715 if ((dev_caps_cfg & VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
7716 (dev_caps_cfg & VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_REQUIRED))
7717 bp->fw_cap |= BNXT_FW_CAP_SHORT_CMD;
7719 if (dev_caps_cfg & VER_GET_RESP_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED)
7720 bp->fw_cap |= BNXT_FW_CAP_KONG_MB_CHNL;
7723 VER_GET_RESP_DEV_CAPS_CFG_FLOW_HANDLE_64BIT_SUPPORTED)
7724 bp->fw_cap |= BNXT_FW_CAP_OVS_64BIT_HANDLE;
7727 VER_GET_RESP_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED)
7728 bp->fw_cap |= BNXT_FW_CAP_TRUSTED_VF;
7731 VER_GET_RESP_DEV_CAPS_CFG_CFA_ADV_FLOW_MGNT_SUPPORTED)
7732 bp->fw_cap |= BNXT_FW_CAP_CFA_ADV_FLOW;
7735 mutex_unlock(&bp->hwrm_cmd_lock);
7739 int bnxt_hwrm_fw_set_time(struct bnxt *bp)
7741 struct hwrm_fw_set_time_input req = {0};
7743 time64_t now = ktime_get_real_seconds();
7745 if ((BNXT_VF(bp) && bp->hwrm_spec_code < 0x10901) ||
7746 bp->hwrm_spec_code < 0x10400)
7749 time64_to_tm(now, 0, &tm);
7750 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FW_SET_TIME, -1, -1);
7751 req.year = cpu_to_le16(1900 + tm.tm_year);
7752 req.month = 1 + tm.tm_mon;
7753 req.day = tm.tm_mday;
7754 req.hour = tm.tm_hour;
7755 req.minute = tm.tm_min;
7756 req.second = tm.tm_sec;
7757 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
7760 static void bnxt_add_one_ctr(u64 hw, u64 *sw, u64 mask)
7765 sw_tmp = (*sw & ~mask) | hw;
7766 if (hw < (*sw & mask))
7768 WRITE_ONCE(*sw, sw_tmp);
7771 static void __bnxt_accumulate_stats(__le64 *hw_stats, u64 *sw_stats, u64 *masks,
7772 int count, bool ignore_zero)
7776 for (i = 0; i < count; i++) {
7777 u64 hw = le64_to_cpu(READ_ONCE(hw_stats[i]));
7779 if (ignore_zero && !hw)
7782 if (masks[i] == -1ULL)
7785 bnxt_add_one_ctr(hw, &sw_stats[i], masks[i]);
7789 static void bnxt_accumulate_stats(struct bnxt_stats_mem *stats)
7791 if (!stats->hw_stats)
7794 __bnxt_accumulate_stats(stats->hw_stats, stats->sw_stats,
7795 stats->hw_masks, stats->len / 8, false);
7798 static void bnxt_accumulate_all_stats(struct bnxt *bp)
7800 struct bnxt_stats_mem *ring0_stats;
7801 bool ignore_zero = false;
7804 /* Chip bug. Counter intermittently becomes 0. */
7805 if (bp->flags & BNXT_FLAG_CHIP_P5)
7808 for (i = 0; i < bp->cp_nr_rings; i++) {
7809 struct bnxt_napi *bnapi = bp->bnapi[i];
7810 struct bnxt_cp_ring_info *cpr;
7811 struct bnxt_stats_mem *stats;
7813 cpr = &bnapi->cp_ring;
7814 stats = &cpr->stats;
7816 ring0_stats = stats;
7817 __bnxt_accumulate_stats(stats->hw_stats, stats->sw_stats,
7818 ring0_stats->hw_masks,
7819 ring0_stats->len / 8, ignore_zero);
7821 if (bp->flags & BNXT_FLAG_PORT_STATS) {
7822 struct bnxt_stats_mem *stats = &bp->port_stats;
7823 __le64 *hw_stats = stats->hw_stats;
7824 u64 *sw_stats = stats->sw_stats;
7825 u64 *masks = stats->hw_masks;
7828 cnt = sizeof(struct rx_port_stats) / 8;
7829 __bnxt_accumulate_stats(hw_stats, sw_stats, masks, cnt, false);
7831 hw_stats += BNXT_TX_PORT_STATS_BYTE_OFFSET / 8;
7832 sw_stats += BNXT_TX_PORT_STATS_BYTE_OFFSET / 8;
7833 masks += BNXT_TX_PORT_STATS_BYTE_OFFSET / 8;
7834 cnt = sizeof(struct tx_port_stats) / 8;
7835 __bnxt_accumulate_stats(hw_stats, sw_stats, masks, cnt, false);
7837 if (bp->flags & BNXT_FLAG_PORT_STATS_EXT) {
7838 bnxt_accumulate_stats(&bp->rx_port_stats_ext);
7839 bnxt_accumulate_stats(&bp->tx_port_stats_ext);
7843 static int bnxt_hwrm_port_qstats(struct bnxt *bp, u8 flags)
7845 struct bnxt_pf_info *pf = &bp->pf;
7846 struct hwrm_port_qstats_input req = {0};
7848 if (!(bp->flags & BNXT_FLAG_PORT_STATS))
7851 if (flags && !(bp->fw_cap & BNXT_FW_CAP_EXT_HW_STATS_SUPPORTED))
7855 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_QSTATS, -1, -1);
7856 req.port_id = cpu_to_le16(pf->port_id);
7857 req.tx_stat_host_addr = cpu_to_le64(bp->port_stats.hw_stats_map +
7858 BNXT_TX_PORT_STATS_BYTE_OFFSET);
7859 req.rx_stat_host_addr = cpu_to_le64(bp->port_stats.hw_stats_map);
7860 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
7863 static int bnxt_hwrm_port_qstats_ext(struct bnxt *bp, u8 flags)
7865 struct hwrm_port_qstats_ext_output *resp = bp->hwrm_cmd_resp_addr;
7866 struct hwrm_queue_pri2cos_qcfg_input req2 = {0};
7867 struct hwrm_port_qstats_ext_input req = {0};
7868 struct bnxt_pf_info *pf = &bp->pf;
7872 if (!(bp->flags & BNXT_FLAG_PORT_STATS_EXT))
7875 if (flags && !(bp->fw_cap & BNXT_FW_CAP_EXT_HW_STATS_SUPPORTED))
7878 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_QSTATS_EXT, -1, -1);
7880 req.port_id = cpu_to_le16(pf->port_id);
7881 req.rx_stat_size = cpu_to_le16(sizeof(struct rx_port_stats_ext));
7882 req.rx_stat_host_addr = cpu_to_le64(bp->rx_port_stats_ext.hw_stats_map);
7883 tx_stat_size = bp->tx_port_stats_ext.hw_stats ?
7884 sizeof(struct tx_port_stats_ext) : 0;
7885 req.tx_stat_size = cpu_to_le16(tx_stat_size);
7886 req.tx_stat_host_addr = cpu_to_le64(bp->tx_port_stats_ext.hw_stats_map);
7887 mutex_lock(&bp->hwrm_cmd_lock);
7888 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
7890 bp->fw_rx_stats_ext_size = le16_to_cpu(resp->rx_stat_size) / 8;
7891 bp->fw_tx_stats_ext_size = tx_stat_size ?
7892 le16_to_cpu(resp->tx_stat_size) / 8 : 0;
7894 bp->fw_rx_stats_ext_size = 0;
7895 bp->fw_tx_stats_ext_size = 0;
7900 if (bp->fw_tx_stats_ext_size <=
7901 offsetof(struct tx_port_stats_ext, pfc_pri0_tx_duration_us) / 8) {
7902 mutex_unlock(&bp->hwrm_cmd_lock);
7903 bp->pri2cos_valid = 0;
7907 bnxt_hwrm_cmd_hdr_init(bp, &req2, HWRM_QUEUE_PRI2COS_QCFG, -1, -1);
7908 req2.flags = cpu_to_le32(QUEUE_PRI2COS_QCFG_REQ_FLAGS_IVLAN);
7910 rc = _hwrm_send_message(bp, &req2, sizeof(req2), HWRM_CMD_TIMEOUT);
7912 struct hwrm_queue_pri2cos_qcfg_output *resp2;
7916 resp2 = bp->hwrm_cmd_resp_addr;
7917 pri2cos = &resp2->pri0_cos_queue_id;
7918 for (i = 0; i < 8; i++) {
7919 u8 queue_id = pri2cos[i];
7922 /* Per port queue IDs start from 0, 10, 20, etc */
7923 queue_idx = queue_id % 10;
7924 if (queue_idx > BNXT_MAX_QUEUE) {
7925 bp->pri2cos_valid = false;
7928 for (j = 0; j < bp->max_q; j++) {
7929 if (bp->q_ids[j] == queue_id)
7930 bp->pri2cos_idx[i] = queue_idx;
7933 bp->pri2cos_valid = 1;
7936 mutex_unlock(&bp->hwrm_cmd_lock);
7940 static void bnxt_hwrm_free_tunnel_ports(struct bnxt *bp)
7942 if (bp->vxlan_fw_dst_port_id != INVALID_HW_RING_ID)
7943 bnxt_hwrm_tunnel_dst_port_free(
7944 bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN);
7945 if (bp->nge_fw_dst_port_id != INVALID_HW_RING_ID)
7946 bnxt_hwrm_tunnel_dst_port_free(
7947 bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE);
7950 static int bnxt_set_tpa(struct bnxt *bp, bool set_tpa)
7956 tpa_flags = bp->flags & BNXT_FLAG_TPA;
7957 else if (BNXT_NO_FW_ACCESS(bp))
7959 for (i = 0; i < bp->nr_vnics; i++) {
7960 rc = bnxt_hwrm_vnic_set_tpa(bp, i, tpa_flags);
7962 netdev_err(bp->dev, "hwrm vnic set tpa failure rc for vnic %d: %x\n",
7970 static void bnxt_hwrm_clear_vnic_rss(struct bnxt *bp)
7974 for (i = 0; i < bp->nr_vnics; i++)
7975 bnxt_hwrm_vnic_set_rss(bp, i, false);
7978 static void bnxt_clear_vnic(struct bnxt *bp)
7983 bnxt_hwrm_clear_vnic_filter(bp);
7984 if (!(bp->flags & BNXT_FLAG_CHIP_P5)) {
7985 /* clear all RSS setting before free vnic ctx */
7986 bnxt_hwrm_clear_vnic_rss(bp);
7987 bnxt_hwrm_vnic_ctx_free(bp);
7989 /* before free the vnic, undo the vnic tpa settings */
7990 if (bp->flags & BNXT_FLAG_TPA)
7991 bnxt_set_tpa(bp, false);
7992 bnxt_hwrm_vnic_free(bp);
7993 if (bp->flags & BNXT_FLAG_CHIP_P5)
7994 bnxt_hwrm_vnic_ctx_free(bp);
7997 static void bnxt_hwrm_resource_free(struct bnxt *bp, bool close_path,
8000 bnxt_clear_vnic(bp);
8001 bnxt_hwrm_ring_free(bp, close_path);
8002 bnxt_hwrm_ring_grp_free(bp);
8004 bnxt_hwrm_stat_ctx_free(bp);
8005 bnxt_hwrm_free_tunnel_ports(bp);
8009 static int bnxt_hwrm_set_br_mode(struct bnxt *bp, u16 br_mode)
8011 struct hwrm_func_cfg_input req = {0};
8013 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_CFG, -1, -1);
8014 req.fid = cpu_to_le16(0xffff);
8015 req.enables = cpu_to_le32(FUNC_CFG_REQ_ENABLES_EVB_MODE);
8016 if (br_mode == BRIDGE_MODE_VEB)
8017 req.evb_mode = FUNC_CFG_REQ_EVB_MODE_VEB;
8018 else if (br_mode == BRIDGE_MODE_VEPA)
8019 req.evb_mode = FUNC_CFG_REQ_EVB_MODE_VEPA;
8022 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
8025 static int bnxt_hwrm_set_cache_line_size(struct bnxt *bp, int size)
8027 struct hwrm_func_cfg_input req = {0};
8029 if (BNXT_VF(bp) || bp->hwrm_spec_code < 0x10803)
8032 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_CFG, -1, -1);
8033 req.fid = cpu_to_le16(0xffff);
8034 req.enables = cpu_to_le32(FUNC_CFG_REQ_ENABLES_CACHE_LINESIZE);
8035 req.options = FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_64;
8037 req.options = FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_128;
8039 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
8042 static int __bnxt_setup_vnic(struct bnxt *bp, u16 vnic_id)
8044 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
8047 if (vnic->flags & BNXT_VNIC_RFS_NEW_RSS_FLAG)
8050 /* allocate context for vnic */
8051 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic_id, 0);
8053 netdev_err(bp->dev, "hwrm vnic %d alloc failure rc: %x\n",
8055 goto vnic_setup_err;
8057 bp->rsscos_nr_ctxs++;
8059 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) {
8060 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic_id, 1);
8062 netdev_err(bp->dev, "hwrm vnic %d cos ctx alloc failure rc: %x\n",
8064 goto vnic_setup_err;
8066 bp->rsscos_nr_ctxs++;
8070 /* configure default vnic, ring grp */
8071 rc = bnxt_hwrm_vnic_cfg(bp, vnic_id);
8073 netdev_err(bp->dev, "hwrm vnic %d cfg failure rc: %x\n",
8075 goto vnic_setup_err;
8078 /* Enable RSS hashing on vnic */
8079 rc = bnxt_hwrm_vnic_set_rss(bp, vnic_id, true);
8081 netdev_err(bp->dev, "hwrm vnic %d set rss failure rc: %x\n",
8083 goto vnic_setup_err;
8086 if (bp->flags & BNXT_FLAG_AGG_RINGS) {
8087 rc = bnxt_hwrm_vnic_set_hds(bp, vnic_id);
8089 netdev_err(bp->dev, "hwrm vnic %d set hds failure rc: %x\n",
8098 static int __bnxt_setup_vnic_p5(struct bnxt *bp, u16 vnic_id)
8102 nr_ctxs = bnxt_get_nr_rss_ctxs(bp, bp->rx_nr_rings);
8103 for (i = 0; i < nr_ctxs; i++) {
8104 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic_id, i);
8106 netdev_err(bp->dev, "hwrm vnic %d ctx %d alloc failure rc: %x\n",
8110 bp->rsscos_nr_ctxs++;
8115 rc = bnxt_hwrm_vnic_set_rss_p5(bp, vnic_id, true);
8117 netdev_err(bp->dev, "hwrm vnic %d set rss failure rc: %d\n",
8121 rc = bnxt_hwrm_vnic_cfg(bp, vnic_id);
8123 netdev_err(bp->dev, "hwrm vnic %d cfg failure rc: %x\n",
8127 if (bp->flags & BNXT_FLAG_AGG_RINGS) {
8128 rc = bnxt_hwrm_vnic_set_hds(bp, vnic_id);
8130 netdev_err(bp->dev, "hwrm vnic %d set hds failure rc: %x\n",
8137 static int bnxt_setup_vnic(struct bnxt *bp, u16 vnic_id)
8139 if (bp->flags & BNXT_FLAG_CHIP_P5)
8140 return __bnxt_setup_vnic_p5(bp, vnic_id);
8142 return __bnxt_setup_vnic(bp, vnic_id);
8145 static int bnxt_alloc_rfs_vnics(struct bnxt *bp)
8147 #ifdef CONFIG_RFS_ACCEL
8150 if (bp->flags & BNXT_FLAG_CHIP_P5)
8153 for (i = 0; i < bp->rx_nr_rings; i++) {
8154 struct bnxt_vnic_info *vnic;
8155 u16 vnic_id = i + 1;
8158 if (vnic_id >= bp->nr_vnics)
8161 vnic = &bp->vnic_info[vnic_id];
8162 vnic->flags |= BNXT_VNIC_RFS_FLAG;
8163 if (bp->flags & BNXT_FLAG_NEW_RSS_CAP)
8164 vnic->flags |= BNXT_VNIC_RFS_NEW_RSS_FLAG;
8165 rc = bnxt_hwrm_vnic_alloc(bp, vnic_id, ring_id, 1);
8167 netdev_err(bp->dev, "hwrm vnic %d alloc failure rc: %x\n",
8171 rc = bnxt_setup_vnic(bp, vnic_id);
8181 /* Allow PF and VF with default VLAN to be in promiscuous mode */
8182 static bool bnxt_promisc_ok(struct bnxt *bp)
8184 #ifdef CONFIG_BNXT_SRIOV
8185 if (BNXT_VF(bp) && !bp->vf.vlan)
8191 static int bnxt_setup_nitroa0_vnic(struct bnxt *bp)
8193 unsigned int rc = 0;
8195 rc = bnxt_hwrm_vnic_alloc(bp, 1, bp->rx_nr_rings - 1, 1);
8197 netdev_err(bp->dev, "Cannot allocate special vnic for NS2 A0: %x\n",
8202 rc = bnxt_hwrm_vnic_cfg(bp, 1);
8204 netdev_err(bp->dev, "Cannot allocate special vnic for NS2 A0: %x\n",
8211 static int bnxt_cfg_rx_mode(struct bnxt *);
8212 static bool bnxt_mc_list_updated(struct bnxt *, u32 *);
8214 static int bnxt_init_chip(struct bnxt *bp, bool irq_re_init)
8216 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
8218 unsigned int rx_nr_rings = bp->rx_nr_rings;
8221 rc = bnxt_hwrm_stat_ctx_alloc(bp);
8223 netdev_err(bp->dev, "hwrm stat ctx alloc failure rc: %x\n",
8229 rc = bnxt_hwrm_ring_alloc(bp);
8231 netdev_err(bp->dev, "hwrm ring alloc failure rc: %x\n", rc);
8235 rc = bnxt_hwrm_ring_grp_alloc(bp);
8237 netdev_err(bp->dev, "hwrm_ring_grp alloc failure: %x\n", rc);
8241 if (BNXT_CHIP_TYPE_NITRO_A0(bp))
8244 /* default vnic 0 */
8245 rc = bnxt_hwrm_vnic_alloc(bp, 0, 0, rx_nr_rings);
8247 netdev_err(bp->dev, "hwrm vnic alloc failure rc: %x\n", rc);
8251 rc = bnxt_setup_vnic(bp, 0);
8255 if (bp->flags & BNXT_FLAG_RFS) {
8256 rc = bnxt_alloc_rfs_vnics(bp);
8261 if (bp->flags & BNXT_FLAG_TPA) {
8262 rc = bnxt_set_tpa(bp, true);
8268 bnxt_update_vf_mac(bp);
8270 /* Filter for default vnic 0 */
8271 rc = bnxt_hwrm_set_vnic_filter(bp, 0, 0, bp->dev->dev_addr);
8273 netdev_err(bp->dev, "HWRM vnic filter failure rc: %x\n", rc);
8276 vnic->uc_filter_count = 1;
8279 if (bp->dev->flags & IFF_BROADCAST)
8280 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_BCAST;
8282 if ((bp->dev->flags & IFF_PROMISC) && bnxt_promisc_ok(bp))
8283 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS;
8285 if (bp->dev->flags & IFF_ALLMULTI) {
8286 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST;
8287 vnic->mc_list_count = 0;
8291 bnxt_mc_list_updated(bp, &mask);
8292 vnic->rx_mask |= mask;
8295 rc = bnxt_cfg_rx_mode(bp);
8299 rc = bnxt_hwrm_set_coal(bp);
8301 netdev_warn(bp->dev, "HWRM set coalescing failure rc: %x\n",
8304 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) {
8305 rc = bnxt_setup_nitroa0_vnic(bp);
8307 netdev_err(bp->dev, "Special vnic setup failure for NS2 A0 rc: %x\n",
8312 bnxt_hwrm_func_qcfg(bp);
8313 netdev_update_features(bp->dev);
8319 bnxt_hwrm_resource_free(bp, 0, true);
8324 static int bnxt_shutdown_nic(struct bnxt *bp, bool irq_re_init)
8326 bnxt_hwrm_resource_free(bp, 1, irq_re_init);
8330 static int bnxt_init_nic(struct bnxt *bp, bool irq_re_init)
8332 bnxt_init_cp_rings(bp);
8333 bnxt_init_rx_rings(bp);
8334 bnxt_init_tx_rings(bp);
8335 bnxt_init_ring_grps(bp, irq_re_init);
8336 bnxt_init_vnics(bp);
8338 return bnxt_init_chip(bp, irq_re_init);
8341 static int bnxt_set_real_num_queues(struct bnxt *bp)
8344 struct net_device *dev = bp->dev;
8346 rc = netif_set_real_num_tx_queues(dev, bp->tx_nr_rings -
8347 bp->tx_nr_rings_xdp);
8351 rc = netif_set_real_num_rx_queues(dev, bp->rx_nr_rings);
8355 #ifdef CONFIG_RFS_ACCEL
8356 if (bp->flags & BNXT_FLAG_RFS)
8357 dev->rx_cpu_rmap = alloc_irq_cpu_rmap(bp->rx_nr_rings);
8363 static int bnxt_trim_rings(struct bnxt *bp, int *rx, int *tx, int max,
8366 int _rx = *rx, _tx = *tx;
8369 *rx = min_t(int, _rx, max);
8370 *tx = min_t(int, _tx, max);
8375 while (_rx + _tx > max) {
8376 if (_rx > _tx && _rx > 1)
8387 static void bnxt_setup_msix(struct bnxt *bp)
8389 const int len = sizeof(bp->irq_tbl[0].name);
8390 struct net_device *dev = bp->dev;
8393 tcs = netdev_get_num_tc(dev);
8397 for (i = 0; i < tcs; i++) {
8398 count = bp->tx_nr_rings_per_tc;
8400 netdev_set_tc_queue(dev, i, count, off);
8404 for (i = 0; i < bp->cp_nr_rings; i++) {
8405 int map_idx = bnxt_cp_num_to_irq_num(bp, i);
8408 if (bp->flags & BNXT_FLAG_SHARED_RINGS)
8410 else if (i < bp->rx_nr_rings)
8415 snprintf(bp->irq_tbl[map_idx].name, len, "%s-%s-%d", dev->name,
8417 bp->irq_tbl[map_idx].handler = bnxt_msix;
8421 static void bnxt_setup_inta(struct bnxt *bp)
8423 const int len = sizeof(bp->irq_tbl[0].name);
8425 if (netdev_get_num_tc(bp->dev))
8426 netdev_reset_tc(bp->dev);
8428 snprintf(bp->irq_tbl[0].name, len, "%s-%s-%d", bp->dev->name, "TxRx",
8430 bp->irq_tbl[0].handler = bnxt_inta;
8433 static int bnxt_setup_int_mode(struct bnxt *bp)
8437 if (bp->flags & BNXT_FLAG_USING_MSIX)
8438 bnxt_setup_msix(bp);
8440 bnxt_setup_inta(bp);
8442 rc = bnxt_set_real_num_queues(bp);
8446 #ifdef CONFIG_RFS_ACCEL
8447 static unsigned int bnxt_get_max_func_rss_ctxs(struct bnxt *bp)
8449 return bp->hw_resc.max_rsscos_ctxs;
8452 static unsigned int bnxt_get_max_func_vnics(struct bnxt *bp)
8454 return bp->hw_resc.max_vnics;
8458 unsigned int bnxt_get_max_func_stat_ctxs(struct bnxt *bp)
8460 return bp->hw_resc.max_stat_ctxs;
8463 unsigned int bnxt_get_max_func_cp_rings(struct bnxt *bp)
8465 return bp->hw_resc.max_cp_rings;
8468 static unsigned int bnxt_get_max_func_cp_rings_for_en(struct bnxt *bp)
8470 unsigned int cp = bp->hw_resc.max_cp_rings;
8472 if (!(bp->flags & BNXT_FLAG_CHIP_P5))
8473 cp -= bnxt_get_ulp_msix_num(bp);
8478 static unsigned int bnxt_get_max_func_irqs(struct bnxt *bp)
8480 struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
8482 if (bp->flags & BNXT_FLAG_CHIP_P5)
8483 return min_t(unsigned int, hw_resc->max_irqs, hw_resc->max_nqs);
8485 return min_t(unsigned int, hw_resc->max_irqs, hw_resc->max_cp_rings);
8488 static void bnxt_set_max_func_irqs(struct bnxt *bp, unsigned int max_irqs)
8490 bp->hw_resc.max_irqs = max_irqs;
8493 unsigned int bnxt_get_avail_cp_rings_for_en(struct bnxt *bp)
8497 cp = bnxt_get_max_func_cp_rings_for_en(bp);
8498 if (bp->flags & BNXT_FLAG_CHIP_P5)
8499 return cp - bp->rx_nr_rings - bp->tx_nr_rings;
8501 return cp - bp->cp_nr_rings;
8504 unsigned int bnxt_get_avail_stat_ctxs_for_en(struct bnxt *bp)
8506 return bnxt_get_max_func_stat_ctxs(bp) - bnxt_get_func_stat_ctxs(bp);
8509 int bnxt_get_avail_msix(struct bnxt *bp, int num)
8511 int max_cp = bnxt_get_max_func_cp_rings(bp);
8512 int max_irq = bnxt_get_max_func_irqs(bp);
8513 int total_req = bp->cp_nr_rings + num;
8514 int max_idx, avail_msix;
8516 max_idx = bp->total_irqs;
8517 if (!(bp->flags & BNXT_FLAG_CHIP_P5))
8518 max_idx = min_t(int, bp->total_irqs, max_cp);
8519 avail_msix = max_idx - bp->cp_nr_rings;
8520 if (!BNXT_NEW_RM(bp) || avail_msix >= num)
8523 if (max_irq < total_req) {
8524 num = max_irq - bp->cp_nr_rings;
8531 static int bnxt_get_num_msix(struct bnxt *bp)
8533 if (!BNXT_NEW_RM(bp))
8534 return bnxt_get_max_func_irqs(bp);
8536 return bnxt_nq_rings_in_use(bp);
8539 static int bnxt_init_msix(struct bnxt *bp)
8541 int i, total_vecs, max, rc = 0, min = 1, ulp_msix;
8542 struct msix_entry *msix_ent;
8544 total_vecs = bnxt_get_num_msix(bp);
8545 max = bnxt_get_max_func_irqs(bp);
8546 if (total_vecs > max)
8552 msix_ent = kcalloc(total_vecs, sizeof(struct msix_entry), GFP_KERNEL);
8556 for (i = 0; i < total_vecs; i++) {
8557 msix_ent[i].entry = i;
8558 msix_ent[i].vector = 0;
8561 if (!(bp->flags & BNXT_FLAG_SHARED_RINGS))
8564 total_vecs = pci_enable_msix_range(bp->pdev, msix_ent, min, total_vecs);
8565 ulp_msix = bnxt_get_ulp_msix_num(bp);
8566 if (total_vecs < 0 || total_vecs < ulp_msix) {
8568 goto msix_setup_exit;
8571 bp->irq_tbl = kcalloc(total_vecs, sizeof(struct bnxt_irq), GFP_KERNEL);
8573 for (i = 0; i < total_vecs; i++)
8574 bp->irq_tbl[i].vector = msix_ent[i].vector;
8576 bp->total_irqs = total_vecs;
8577 /* Trim rings based upon num of vectors allocated */
8578 rc = bnxt_trim_rings(bp, &bp->rx_nr_rings, &bp->tx_nr_rings,
8579 total_vecs - ulp_msix, min == 1);
8581 goto msix_setup_exit;
8583 bp->cp_nr_rings = (min == 1) ?
8584 max_t(int, bp->tx_nr_rings, bp->rx_nr_rings) :
8585 bp->tx_nr_rings + bp->rx_nr_rings;
8589 goto msix_setup_exit;
8591 bp->flags |= BNXT_FLAG_USING_MSIX;
8596 netdev_err(bp->dev, "bnxt_init_msix err: %x\n", rc);
8599 pci_disable_msix(bp->pdev);
8604 static int bnxt_init_inta(struct bnxt *bp)
8606 bp->irq_tbl = kzalloc(sizeof(struct bnxt_irq), GFP_KERNEL);
8611 bp->rx_nr_rings = 1;
8612 bp->tx_nr_rings = 1;
8613 bp->cp_nr_rings = 1;
8614 bp->flags |= BNXT_FLAG_SHARED_RINGS;
8615 bp->irq_tbl[0].vector = bp->pdev->irq;
8619 static int bnxt_init_int_mode(struct bnxt *bp)
8623 if (bp->flags & BNXT_FLAG_MSIX_CAP)
8624 rc = bnxt_init_msix(bp);
8626 if (!(bp->flags & BNXT_FLAG_USING_MSIX) && BNXT_PF(bp)) {
8627 /* fallback to INTA */
8628 rc = bnxt_init_inta(bp);
8633 static void bnxt_clear_int_mode(struct bnxt *bp)
8635 if (bp->flags & BNXT_FLAG_USING_MSIX)
8636 pci_disable_msix(bp->pdev);
8640 bp->flags &= ~BNXT_FLAG_USING_MSIX;
8643 int bnxt_reserve_rings(struct bnxt *bp, bool irq_re_init)
8645 int tcs = netdev_get_num_tc(bp->dev);
8646 bool irq_cleared = false;
8649 if (!bnxt_need_reserve_rings(bp))
8652 if (irq_re_init && BNXT_NEW_RM(bp) &&
8653 bnxt_get_num_msix(bp) != bp->total_irqs) {
8654 bnxt_ulp_irq_stop(bp);
8655 bnxt_clear_int_mode(bp);
8658 rc = __bnxt_reserve_rings(bp);
8661 rc = bnxt_init_int_mode(bp);
8662 bnxt_ulp_irq_restart(bp, rc);
8665 netdev_err(bp->dev, "ring reservation/IRQ init failure rc: %d\n", rc);
8668 if (tcs && (bp->tx_nr_rings_per_tc * tcs != bp->tx_nr_rings)) {
8669 netdev_err(bp->dev, "tx ring reservation failure\n");
8670 netdev_reset_tc(bp->dev);
8671 bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
8677 static void bnxt_free_irq(struct bnxt *bp)
8679 struct bnxt_irq *irq;
8682 #ifdef CONFIG_RFS_ACCEL
8683 free_irq_cpu_rmap(bp->dev->rx_cpu_rmap);
8684 bp->dev->rx_cpu_rmap = NULL;
8686 if (!bp->irq_tbl || !bp->bnapi)
8689 for (i = 0; i < bp->cp_nr_rings; i++) {
8690 int map_idx = bnxt_cp_num_to_irq_num(bp, i);
8692 irq = &bp->irq_tbl[map_idx];
8693 if (irq->requested) {
8694 if (irq->have_cpumask) {
8695 irq_set_affinity_hint(irq->vector, NULL);
8696 free_cpumask_var(irq->cpu_mask);
8697 irq->have_cpumask = 0;
8699 free_irq(irq->vector, bp->bnapi[i]);
8706 static int bnxt_request_irq(struct bnxt *bp)
8709 unsigned long flags = 0;
8710 #ifdef CONFIG_RFS_ACCEL
8711 struct cpu_rmap *rmap;
8714 rc = bnxt_setup_int_mode(bp);
8716 netdev_err(bp->dev, "bnxt_setup_int_mode err: %x\n",
8720 #ifdef CONFIG_RFS_ACCEL
8721 rmap = bp->dev->rx_cpu_rmap;
8723 if (!(bp->flags & BNXT_FLAG_USING_MSIX))
8724 flags = IRQF_SHARED;
8726 for (i = 0, j = 0; i < bp->cp_nr_rings; i++) {
8727 int map_idx = bnxt_cp_num_to_irq_num(bp, i);
8728 struct bnxt_irq *irq = &bp->irq_tbl[map_idx];
8730 #ifdef CONFIG_RFS_ACCEL
8731 if (rmap && bp->bnapi[i]->rx_ring) {
8732 rc = irq_cpu_rmap_add(rmap, irq->vector);
8734 netdev_warn(bp->dev, "failed adding irq rmap for ring %d\n",
8739 rc = request_irq(irq->vector, irq->handler, flags, irq->name,
8746 if (zalloc_cpumask_var(&irq->cpu_mask, GFP_KERNEL)) {
8747 int numa_node = dev_to_node(&bp->pdev->dev);
8749 irq->have_cpumask = 1;
8750 cpumask_set_cpu(cpumask_local_spread(i, numa_node),
8752 rc = irq_set_affinity_hint(irq->vector, irq->cpu_mask);
8754 netdev_warn(bp->dev,
8755 "Set affinity failed, IRQ = %d\n",
8764 static void bnxt_del_napi(struct bnxt *bp)
8771 for (i = 0; i < bp->cp_nr_rings; i++) {
8772 struct bnxt_napi *bnapi = bp->bnapi[i];
8774 __netif_napi_del(&bnapi->napi);
8776 /* We called __netif_napi_del(), we need
8777 * to respect an RCU grace period before freeing napi structures.
8782 static void bnxt_init_napi(struct bnxt *bp)
8785 unsigned int cp_nr_rings = bp->cp_nr_rings;
8786 struct bnxt_napi *bnapi;
8788 if (bp->flags & BNXT_FLAG_USING_MSIX) {
8789 int (*poll_fn)(struct napi_struct *, int) = bnxt_poll;
8791 if (bp->flags & BNXT_FLAG_CHIP_P5)
8792 poll_fn = bnxt_poll_p5;
8793 else if (BNXT_CHIP_TYPE_NITRO_A0(bp))
8795 for (i = 0; i < cp_nr_rings; i++) {
8796 bnapi = bp->bnapi[i];
8797 netif_napi_add(bp->dev, &bnapi->napi, poll_fn, 64);
8799 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) {
8800 bnapi = bp->bnapi[cp_nr_rings];
8801 netif_napi_add(bp->dev, &bnapi->napi,
8802 bnxt_poll_nitroa0, 64);
8805 bnapi = bp->bnapi[0];
8806 netif_napi_add(bp->dev, &bnapi->napi, bnxt_poll, 64);
8810 static void bnxt_disable_napi(struct bnxt *bp)
8817 for (i = 0; i < bp->cp_nr_rings; i++) {
8818 struct bnxt_cp_ring_info *cpr = &bp->bnapi[i]->cp_ring;
8820 if (bp->bnapi[i]->rx_ring)
8821 cancel_work_sync(&cpr->dim.work);
8823 napi_disable(&bp->bnapi[i]->napi);
8827 static void bnxt_enable_napi(struct bnxt *bp)
8831 for (i = 0; i < bp->cp_nr_rings; i++) {
8832 struct bnxt_napi *bnapi = bp->bnapi[i];
8833 struct bnxt_cp_ring_info *cpr;
8835 cpr = &bnapi->cp_ring;
8836 if (bnapi->in_reset)
8837 cpr->sw_stats.rx.rx_resets++;
8838 bnapi->in_reset = false;
8840 if (bnapi->rx_ring) {
8841 INIT_WORK(&cpr->dim.work, bnxt_dim_work);
8842 cpr->dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE;
8844 napi_enable(&bnapi->napi);
8848 void bnxt_tx_disable(struct bnxt *bp)
8851 struct bnxt_tx_ring_info *txr;
8854 for (i = 0; i < bp->tx_nr_rings; i++) {
8855 txr = &bp->tx_ring[i];
8856 txr->dev_state = BNXT_DEV_STATE_CLOSING;
8859 /* Stop all TX queues */
8860 netif_tx_disable(bp->dev);
8861 netif_carrier_off(bp->dev);
8864 void bnxt_tx_enable(struct bnxt *bp)
8867 struct bnxt_tx_ring_info *txr;
8869 for (i = 0; i < bp->tx_nr_rings; i++) {
8870 txr = &bp->tx_ring[i];
8873 netif_tx_wake_all_queues(bp->dev);
8874 if (bp->link_info.link_up)
8875 netif_carrier_on(bp->dev);
8878 static char *bnxt_report_fec(struct bnxt_link_info *link_info)
8880 u8 active_fec = link_info->active_fec_sig_mode &
8881 PORT_PHY_QCFG_RESP_ACTIVE_FEC_MASK;
8883 switch (active_fec) {
8885 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_NONE_ACTIVE:
8887 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_CLAUSE74_ACTIVE:
8888 return "Clause 74 BaseR";
8889 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_CLAUSE91_ACTIVE:
8890 return "Clause 91 RS(528,514)";
8891 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS544_1XN_ACTIVE:
8892 return "Clause 91 RS544_1XN";
8893 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS544_IEEE_ACTIVE:
8894 return "Clause 91 RS(544,514)";
8895 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS272_1XN_ACTIVE:
8896 return "Clause 91 RS272_1XN";
8897 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS272_IEEE_ACTIVE:
8898 return "Clause 91 RS(272,257)";
8902 static void bnxt_report_link(struct bnxt *bp)
8904 if (bp->link_info.link_up) {
8906 const char *flow_ctrl;
8910 netif_carrier_on(bp->dev);
8911 speed = bnxt_fw_to_ethtool_speed(bp->link_info.link_speed);
8912 if (speed == SPEED_UNKNOWN) {
8913 netdev_info(bp->dev, "NIC Link is Up, speed unknown\n");
8916 if (bp->link_info.duplex == BNXT_LINK_DUPLEX_FULL)
8920 if (bp->link_info.pause == BNXT_LINK_PAUSE_BOTH)
8921 flow_ctrl = "ON - receive & transmit";
8922 else if (bp->link_info.pause == BNXT_LINK_PAUSE_TX)
8923 flow_ctrl = "ON - transmit";
8924 else if (bp->link_info.pause == BNXT_LINK_PAUSE_RX)
8925 flow_ctrl = "ON - receive";
8928 netdev_info(bp->dev, "NIC Link is Up, %u Mbps %s duplex, Flow control: %s\n",
8929 speed, duplex, flow_ctrl);
8930 if (bp->flags & BNXT_FLAG_EEE_CAP)
8931 netdev_info(bp->dev, "EEE is %s\n",
8932 bp->eee.eee_active ? "active" :
8934 fec = bp->link_info.fec_cfg;
8935 if (!(fec & PORT_PHY_QCFG_RESP_FEC_CFG_FEC_NONE_SUPPORTED))
8936 netdev_info(bp->dev, "FEC autoneg %s encoding: %s\n",
8937 (fec & BNXT_FEC_AUTONEG) ? "on" : "off",
8938 bnxt_report_fec(&bp->link_info));
8940 netif_carrier_off(bp->dev);
8941 netdev_err(bp->dev, "NIC Link is Down\n");
8945 static bool bnxt_phy_qcaps_no_speed(struct hwrm_port_phy_qcaps_output *resp)
8947 if (!resp->supported_speeds_auto_mode &&
8948 !resp->supported_speeds_force_mode &&
8949 !resp->supported_pam4_speeds_auto_mode &&
8950 !resp->supported_pam4_speeds_force_mode)
8955 static int bnxt_hwrm_phy_qcaps(struct bnxt *bp)
8958 struct hwrm_port_phy_qcaps_input req = {0};
8959 struct hwrm_port_phy_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
8960 struct bnxt_link_info *link_info = &bp->link_info;
8962 bp->flags &= ~BNXT_FLAG_EEE_CAP;
8964 bp->test_info->flags &= ~(BNXT_TEST_FL_EXT_LPBK |
8965 BNXT_TEST_FL_AN_PHY_LPBK);
8966 if (bp->hwrm_spec_code < 0x10201)
8969 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_QCAPS, -1, -1);
8971 mutex_lock(&bp->hwrm_cmd_lock);
8972 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
8974 goto hwrm_phy_qcaps_exit;
8976 if (resp->flags & PORT_PHY_QCAPS_RESP_FLAGS_EEE_SUPPORTED) {
8977 struct ethtool_eee *eee = &bp->eee;
8978 u16 fw_speeds = le16_to_cpu(resp->supported_speeds_eee_mode);
8980 bp->flags |= BNXT_FLAG_EEE_CAP;
8981 eee->supported = _bnxt_fw_to_ethtool_adv_spds(fw_speeds, 0);
8982 bp->lpi_tmr_lo = le32_to_cpu(resp->tx_lpi_timer_low) &
8983 PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_LOW_MASK;
8984 bp->lpi_tmr_hi = le32_to_cpu(resp->valid_tx_lpi_timer_high) &
8985 PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_HIGH_MASK;
8987 if (resp->flags & PORT_PHY_QCAPS_RESP_FLAGS_EXTERNAL_LPBK_SUPPORTED) {
8989 bp->test_info->flags |= BNXT_TEST_FL_EXT_LPBK;
8991 if (resp->flags & PORT_PHY_QCAPS_RESP_FLAGS_AUTONEG_LPBK_SUPPORTED) {
8993 bp->test_info->flags |= BNXT_TEST_FL_AN_PHY_LPBK;
8995 if (resp->flags & PORT_PHY_QCAPS_RESP_FLAGS_SHARED_PHY_CFG_SUPPORTED) {
8997 bp->fw_cap |= BNXT_FW_CAP_SHARED_PORT_CFG;
8999 if (resp->flags & PORT_PHY_QCAPS_RESP_FLAGS_CUMULATIVE_COUNTERS_ON_RESET)
9000 bp->fw_cap |= BNXT_FW_CAP_PORT_STATS_NO_RESET;
9002 if (bp->hwrm_spec_code >= 0x10a01) {
9003 if (bnxt_phy_qcaps_no_speed(resp)) {
9004 link_info->phy_state = BNXT_PHY_STATE_DISABLED;
9005 netdev_warn(bp->dev, "Ethernet link disabled\n");
9006 } else if (link_info->phy_state == BNXT_PHY_STATE_DISABLED) {
9007 link_info->phy_state = BNXT_PHY_STATE_ENABLED;
9008 netdev_info(bp->dev, "Ethernet link enabled\n");
9009 /* Phy re-enabled, reprobe the speeds */
9010 link_info->support_auto_speeds = 0;
9011 link_info->support_pam4_auto_speeds = 0;
9014 if (resp->supported_speeds_auto_mode)
9015 link_info->support_auto_speeds =
9016 le16_to_cpu(resp->supported_speeds_auto_mode);
9017 if (resp->supported_pam4_speeds_auto_mode)
9018 link_info->support_pam4_auto_speeds =
9019 le16_to_cpu(resp->supported_pam4_speeds_auto_mode);
9021 bp->port_count = resp->port_cnt;
9023 hwrm_phy_qcaps_exit:
9024 mutex_unlock(&bp->hwrm_cmd_lock);
9028 static bool bnxt_support_dropped(u16 advertising, u16 supported)
9030 u16 diff = advertising ^ supported;
9032 return ((supported | diff) != supported);
9035 int bnxt_update_link(struct bnxt *bp, bool chng_link_state)
9038 struct bnxt_link_info *link_info = &bp->link_info;
9039 struct hwrm_port_phy_qcfg_input req = {0};
9040 struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
9041 u8 link_up = link_info->link_up;
9042 bool support_changed = false;
9044 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_QCFG, -1, -1);
9046 mutex_lock(&bp->hwrm_cmd_lock);
9047 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
9049 mutex_unlock(&bp->hwrm_cmd_lock);
9053 memcpy(&link_info->phy_qcfg_resp, resp, sizeof(*resp));
9054 link_info->phy_link_status = resp->link;
9055 link_info->duplex = resp->duplex_cfg;
9056 if (bp->hwrm_spec_code >= 0x10800)
9057 link_info->duplex = resp->duplex_state;
9058 link_info->pause = resp->pause;
9059 link_info->auto_mode = resp->auto_mode;
9060 link_info->auto_pause_setting = resp->auto_pause;
9061 link_info->lp_pause = resp->link_partner_adv_pause;
9062 link_info->force_pause_setting = resp->force_pause;
9063 link_info->duplex_setting = resp->duplex_cfg;
9064 if (link_info->phy_link_status == BNXT_LINK_LINK)
9065 link_info->link_speed = le16_to_cpu(resp->link_speed);
9067 link_info->link_speed = 0;
9068 link_info->force_link_speed = le16_to_cpu(resp->force_link_speed);
9069 link_info->force_pam4_link_speed =
9070 le16_to_cpu(resp->force_pam4_link_speed);
9071 link_info->support_speeds = le16_to_cpu(resp->support_speeds);
9072 link_info->support_pam4_speeds = le16_to_cpu(resp->support_pam4_speeds);
9073 link_info->auto_link_speeds = le16_to_cpu(resp->auto_link_speed_mask);
9074 link_info->auto_pam4_link_speeds =
9075 le16_to_cpu(resp->auto_pam4_link_speed_mask);
9076 link_info->lp_auto_link_speeds =
9077 le16_to_cpu(resp->link_partner_adv_speeds);
9078 link_info->lp_auto_pam4_link_speeds =
9079 resp->link_partner_pam4_adv_speeds;
9080 link_info->preemphasis = le32_to_cpu(resp->preemphasis);
9081 link_info->phy_ver[0] = resp->phy_maj;
9082 link_info->phy_ver[1] = resp->phy_min;
9083 link_info->phy_ver[2] = resp->phy_bld;
9084 link_info->media_type = resp->media_type;
9085 link_info->phy_type = resp->phy_type;
9086 link_info->transceiver = resp->xcvr_pkg_type;
9087 link_info->phy_addr = resp->eee_config_phy_addr &
9088 PORT_PHY_QCFG_RESP_PHY_ADDR_MASK;
9089 link_info->module_status = resp->module_status;
9091 if (bp->flags & BNXT_FLAG_EEE_CAP) {
9092 struct ethtool_eee *eee = &bp->eee;
9095 eee->eee_active = 0;
9096 if (resp->eee_config_phy_addr &
9097 PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ACTIVE) {
9098 eee->eee_active = 1;
9099 fw_speeds = le16_to_cpu(
9100 resp->link_partner_adv_eee_link_speed_mask);
9101 eee->lp_advertised =
9102 _bnxt_fw_to_ethtool_adv_spds(fw_speeds, 0);
9105 /* Pull initial EEE config */
9106 if (!chng_link_state) {
9107 if (resp->eee_config_phy_addr &
9108 PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ENABLED)
9109 eee->eee_enabled = 1;
9111 fw_speeds = le16_to_cpu(resp->adv_eee_link_speed_mask);
9113 _bnxt_fw_to_ethtool_adv_spds(fw_speeds, 0);
9115 if (resp->eee_config_phy_addr &
9116 PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_TX_LPI) {
9119 eee->tx_lpi_enabled = 1;
9120 tmr = resp->xcvr_identifier_type_tx_lpi_timer;
9121 eee->tx_lpi_timer = le32_to_cpu(tmr) &
9122 PORT_PHY_QCFG_RESP_TX_LPI_TIMER_MASK;
9127 link_info->fec_cfg = PORT_PHY_QCFG_RESP_FEC_CFG_FEC_NONE_SUPPORTED;
9128 if (bp->hwrm_spec_code >= 0x10504) {
9129 link_info->fec_cfg = le16_to_cpu(resp->fec_cfg);
9130 link_info->active_fec_sig_mode = resp->active_fec_signal_mode;
9132 /* TODO: need to add more logic to report VF link */
9133 if (chng_link_state) {
9134 if (link_info->phy_link_status == BNXT_LINK_LINK)
9135 link_info->link_up = 1;
9137 link_info->link_up = 0;
9138 if (link_up != link_info->link_up)
9139 bnxt_report_link(bp);
9141 /* alwasy link down if not require to update link state */
9142 link_info->link_up = 0;
9144 mutex_unlock(&bp->hwrm_cmd_lock);
9146 if (!BNXT_PHY_CFG_ABLE(bp))
9149 /* Check if any advertised speeds are no longer supported. The caller
9150 * holds the link_lock mutex, so we can modify link_info settings.
9152 if (bnxt_support_dropped(link_info->advertising,
9153 link_info->support_auto_speeds)) {
9154 link_info->advertising = link_info->support_auto_speeds;
9155 support_changed = true;
9157 if (bnxt_support_dropped(link_info->advertising_pam4,
9158 link_info->support_pam4_auto_speeds)) {
9159 link_info->advertising_pam4 = link_info->support_pam4_auto_speeds;
9160 support_changed = true;
9162 if (support_changed && (link_info->autoneg & BNXT_AUTONEG_SPEED))
9163 bnxt_hwrm_set_link_setting(bp, true, false);
9167 static void bnxt_get_port_module_status(struct bnxt *bp)
9169 struct bnxt_link_info *link_info = &bp->link_info;
9170 struct hwrm_port_phy_qcfg_output *resp = &link_info->phy_qcfg_resp;
9173 if (bnxt_update_link(bp, true))
9176 module_status = link_info->module_status;
9177 switch (module_status) {
9178 case PORT_PHY_QCFG_RESP_MODULE_STATUS_DISABLETX:
9179 case PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN:
9180 case PORT_PHY_QCFG_RESP_MODULE_STATUS_WARNINGMSG:
9181 netdev_warn(bp->dev, "Unqualified SFP+ module detected on port %d\n",
9183 if (bp->hwrm_spec_code >= 0x10201) {
9184 netdev_warn(bp->dev, "Module part number %s\n",
9185 resp->phy_vendor_partnumber);
9187 if (module_status == PORT_PHY_QCFG_RESP_MODULE_STATUS_DISABLETX)
9188 netdev_warn(bp->dev, "TX is disabled\n");
9189 if (module_status == PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN)
9190 netdev_warn(bp->dev, "SFP+ module is shutdown\n");
9195 bnxt_hwrm_set_pause_common(struct bnxt *bp, struct hwrm_port_phy_cfg_input *req)
9197 if (bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL) {
9198 if (bp->hwrm_spec_code >= 0x10201)
9200 PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE;
9201 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_RX)
9202 req->auto_pause |= PORT_PHY_CFG_REQ_AUTO_PAUSE_RX;
9203 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_TX)
9204 req->auto_pause |= PORT_PHY_CFG_REQ_AUTO_PAUSE_TX;
9206 cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE);
9208 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_RX)
9209 req->force_pause |= PORT_PHY_CFG_REQ_FORCE_PAUSE_RX;
9210 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_TX)
9211 req->force_pause |= PORT_PHY_CFG_REQ_FORCE_PAUSE_TX;
9213 cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_FORCE_PAUSE);
9214 if (bp->hwrm_spec_code >= 0x10201) {
9215 req->auto_pause = req->force_pause;
9216 req->enables |= cpu_to_le32(
9217 PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE);
9222 static void bnxt_hwrm_set_link_common(struct bnxt *bp, struct hwrm_port_phy_cfg_input *req)
9224 if (bp->link_info.autoneg & BNXT_AUTONEG_SPEED) {
9225 req->auto_mode |= PORT_PHY_CFG_REQ_AUTO_MODE_SPEED_MASK;
9226 if (bp->link_info.advertising) {
9227 req->enables |= cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED_MASK);
9228 req->auto_link_speed_mask = cpu_to_le16(bp->link_info.advertising);
9230 if (bp->link_info.advertising_pam4) {
9232 cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_PAM4_LINK_SPEED_MASK);
9233 req->auto_link_pam4_speed_mask =
9234 cpu_to_le16(bp->link_info.advertising_pam4);
9236 req->enables |= cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_MODE);
9237 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_RESTART_AUTONEG);
9239 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_FORCE);
9240 if (bp->link_info.req_signal_mode == BNXT_SIG_MODE_PAM4) {
9241 req->force_pam4_link_speed = cpu_to_le16(bp->link_info.req_link_speed);
9242 req->enables |= cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_FORCE_PAM4_LINK_SPEED);
9244 req->force_link_speed = cpu_to_le16(bp->link_info.req_link_speed);
9248 /* tell chimp that the setting takes effect immediately */
9249 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_RESET_PHY);
9252 int bnxt_hwrm_set_pause(struct bnxt *bp)
9254 struct hwrm_port_phy_cfg_input req = {0};
9257 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1);
9258 bnxt_hwrm_set_pause_common(bp, &req);
9260 if ((bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL) ||
9261 bp->link_info.force_link_chng)
9262 bnxt_hwrm_set_link_common(bp, &req);
9264 mutex_lock(&bp->hwrm_cmd_lock);
9265 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
9266 if (!rc && !(bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL)) {
9267 /* since changing of pause setting doesn't trigger any link
9268 * change event, the driver needs to update the current pause
9269 * result upon successfully return of the phy_cfg command
9271 bp->link_info.pause =
9272 bp->link_info.force_pause_setting = bp->link_info.req_flow_ctrl;
9273 bp->link_info.auto_pause_setting = 0;
9274 if (!bp->link_info.force_link_chng)
9275 bnxt_report_link(bp);
9277 bp->link_info.force_link_chng = false;
9278 mutex_unlock(&bp->hwrm_cmd_lock);
9282 static void bnxt_hwrm_set_eee(struct bnxt *bp,
9283 struct hwrm_port_phy_cfg_input *req)
9285 struct ethtool_eee *eee = &bp->eee;
9287 if (eee->eee_enabled) {
9289 u32 flags = PORT_PHY_CFG_REQ_FLAGS_EEE_ENABLE;
9291 if (eee->tx_lpi_enabled)
9292 flags |= PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_ENABLE;
9294 flags |= PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_DISABLE;
9296 req->flags |= cpu_to_le32(flags);
9297 eee_speeds = bnxt_get_fw_auto_link_speeds(eee->advertised);
9298 req->eee_link_speed_mask = cpu_to_le16(eee_speeds);
9299 req->tx_lpi_timer = cpu_to_le32(eee->tx_lpi_timer);
9301 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_EEE_DISABLE);
9305 int bnxt_hwrm_set_link_setting(struct bnxt *bp, bool set_pause, bool set_eee)
9307 struct hwrm_port_phy_cfg_input req = {0};
9309 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1);
9311 bnxt_hwrm_set_pause_common(bp, &req);
9313 bnxt_hwrm_set_link_common(bp, &req);
9316 bnxt_hwrm_set_eee(bp, &req);
9317 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
9320 static int bnxt_hwrm_shutdown_link(struct bnxt *bp)
9322 struct hwrm_port_phy_cfg_input req = {0};
9324 if (!BNXT_SINGLE_PF(bp))
9327 if (pci_num_vf(bp->pdev))
9330 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1);
9331 req.flags = cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_FORCE_LINK_DWN);
9332 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
9335 static int bnxt_fw_init_one(struct bnxt *bp);
9337 static int bnxt_hwrm_if_change(struct bnxt *bp, bool up)
9339 struct hwrm_func_drv_if_change_output *resp = bp->hwrm_cmd_resp_addr;
9340 struct hwrm_func_drv_if_change_input req = {0};
9341 bool resc_reinit = false, fw_reset = false;
9345 if (!(bp->fw_cap & BNXT_FW_CAP_IF_CHANGE))
9348 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_IF_CHANGE, -1, -1);
9350 req.flags = cpu_to_le32(FUNC_DRV_IF_CHANGE_REQ_FLAGS_UP);
9351 mutex_lock(&bp->hwrm_cmd_lock);
9352 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
9354 flags = le32_to_cpu(resp->flags);
9355 mutex_unlock(&bp->hwrm_cmd_lock);
9362 if (flags & FUNC_DRV_IF_CHANGE_RESP_FLAGS_RESC_CHANGE)
9364 if (flags & FUNC_DRV_IF_CHANGE_RESP_FLAGS_HOT_FW_RESET_DONE)
9367 if (test_bit(BNXT_STATE_IN_FW_RESET, &bp->state) && !fw_reset) {
9368 netdev_err(bp->dev, "RESET_DONE not set during FW reset.\n");
9371 if (resc_reinit || fw_reset) {
9373 if (!test_bit(BNXT_STATE_IN_FW_RESET, &bp->state))
9375 bnxt_free_ctx_mem(bp);
9379 rc = bnxt_fw_init_one(bp);
9381 set_bit(BNXT_STATE_ABORT_ERR, &bp->state);
9384 bnxt_clear_int_mode(bp);
9385 rc = bnxt_init_int_mode(bp);
9387 netdev_err(bp->dev, "init int mode failed\n");
9390 set_bit(BNXT_STATE_FW_RESET_DET, &bp->state);
9392 if (BNXT_NEW_RM(bp)) {
9393 struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
9395 rc = bnxt_hwrm_func_resc_qcaps(bp, true);
9396 hw_resc->resv_cp_rings = 0;
9397 hw_resc->resv_stat_ctxs = 0;
9398 hw_resc->resv_irqs = 0;
9399 hw_resc->resv_tx_rings = 0;
9400 hw_resc->resv_rx_rings = 0;
9401 hw_resc->resv_hw_ring_grps = 0;
9402 hw_resc->resv_vnics = 0;
9404 bp->tx_nr_rings = 0;
9405 bp->rx_nr_rings = 0;
9412 static int bnxt_hwrm_port_led_qcaps(struct bnxt *bp)
9414 struct hwrm_port_led_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
9415 struct hwrm_port_led_qcaps_input req = {0};
9416 struct bnxt_pf_info *pf = &bp->pf;
9420 if (BNXT_VF(bp) || bp->hwrm_spec_code < 0x10601)
9423 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_LED_QCAPS, -1, -1);
9424 req.port_id = cpu_to_le16(pf->port_id);
9425 mutex_lock(&bp->hwrm_cmd_lock);
9426 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
9428 mutex_unlock(&bp->hwrm_cmd_lock);
9431 if (resp->num_leds > 0 && resp->num_leds < BNXT_MAX_LED) {
9434 bp->num_leds = resp->num_leds;
9435 memcpy(bp->leds, &resp->led0_id, sizeof(bp->leds[0]) *
9437 for (i = 0; i < bp->num_leds; i++) {
9438 struct bnxt_led_info *led = &bp->leds[i];
9439 __le16 caps = led->led_state_caps;
9441 if (!led->led_group_id ||
9442 !BNXT_LED_ALT_BLINK_CAP(caps)) {
9448 mutex_unlock(&bp->hwrm_cmd_lock);
9452 int bnxt_hwrm_alloc_wol_fltr(struct bnxt *bp)
9454 struct hwrm_wol_filter_alloc_input req = {0};
9455 struct hwrm_wol_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
9458 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_WOL_FILTER_ALLOC, -1, -1);
9459 req.port_id = cpu_to_le16(bp->pf.port_id);
9460 req.wol_type = WOL_FILTER_ALLOC_REQ_WOL_TYPE_MAGICPKT;
9461 req.enables = cpu_to_le32(WOL_FILTER_ALLOC_REQ_ENABLES_MAC_ADDRESS);
9462 memcpy(req.mac_address, bp->dev->dev_addr, ETH_ALEN);
9463 mutex_lock(&bp->hwrm_cmd_lock);
9464 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
9466 bp->wol_filter_id = resp->wol_filter_id;
9467 mutex_unlock(&bp->hwrm_cmd_lock);
9471 int bnxt_hwrm_free_wol_fltr(struct bnxt *bp)
9473 struct hwrm_wol_filter_free_input req = {0};
9475 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_WOL_FILTER_FREE, -1, -1);
9476 req.port_id = cpu_to_le16(bp->pf.port_id);
9477 req.enables = cpu_to_le32(WOL_FILTER_FREE_REQ_ENABLES_WOL_FILTER_ID);
9478 req.wol_filter_id = bp->wol_filter_id;
9479 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
9482 static u16 bnxt_hwrm_get_wol_fltrs(struct bnxt *bp, u16 handle)
9484 struct hwrm_wol_filter_qcfg_input req = {0};
9485 struct hwrm_wol_filter_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
9486 u16 next_handle = 0;
9489 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_WOL_FILTER_QCFG, -1, -1);
9490 req.port_id = cpu_to_le16(bp->pf.port_id);
9491 req.handle = cpu_to_le16(handle);
9492 mutex_lock(&bp->hwrm_cmd_lock);
9493 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
9495 next_handle = le16_to_cpu(resp->next_handle);
9496 if (next_handle != 0) {
9497 if (resp->wol_type ==
9498 WOL_FILTER_ALLOC_REQ_WOL_TYPE_MAGICPKT) {
9500 bp->wol_filter_id = resp->wol_filter_id;
9504 mutex_unlock(&bp->hwrm_cmd_lock);
9508 static void bnxt_get_wol_settings(struct bnxt *bp)
9513 if (!BNXT_PF(bp) || !(bp->flags & BNXT_FLAG_WOL_CAP))
9517 handle = bnxt_hwrm_get_wol_fltrs(bp, handle);
9518 } while (handle && handle != 0xffff);
9521 #ifdef CONFIG_BNXT_HWMON
9522 static ssize_t bnxt_show_temp(struct device *dev,
9523 struct device_attribute *devattr, char *buf)
9525 struct hwrm_temp_monitor_query_input req = {0};
9526 struct hwrm_temp_monitor_query_output *resp;
9527 struct bnxt *bp = dev_get_drvdata(dev);
9531 resp = bp->hwrm_cmd_resp_addr;
9532 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_TEMP_MONITOR_QUERY, -1, -1);
9533 mutex_lock(&bp->hwrm_cmd_lock);
9534 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
9536 len = sprintf(buf, "%u\n", resp->temp * 1000); /* display millidegree */
9537 mutex_unlock(&bp->hwrm_cmd_lock);
9540 static SENSOR_DEVICE_ATTR(temp1_input, 0444, bnxt_show_temp, NULL, 0);
9542 static struct attribute *bnxt_attrs[] = {
9543 &sensor_dev_attr_temp1_input.dev_attr.attr,
9546 ATTRIBUTE_GROUPS(bnxt);
9548 static void bnxt_hwmon_close(struct bnxt *bp)
9550 if (bp->hwmon_dev) {
9551 hwmon_device_unregister(bp->hwmon_dev);
9552 bp->hwmon_dev = NULL;
9556 static void bnxt_hwmon_open(struct bnxt *bp)
9558 struct hwrm_temp_monitor_query_input req = {0};
9559 struct pci_dev *pdev = bp->pdev;
9562 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_TEMP_MONITOR_QUERY, -1, -1);
9563 rc = hwrm_send_message_silent(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
9564 if (rc == -EACCES || rc == -EOPNOTSUPP) {
9565 bnxt_hwmon_close(bp);
9572 bp->hwmon_dev = hwmon_device_register_with_groups(&pdev->dev,
9573 DRV_MODULE_NAME, bp,
9575 if (IS_ERR(bp->hwmon_dev)) {
9576 bp->hwmon_dev = NULL;
9577 dev_warn(&pdev->dev, "Cannot register hwmon device\n");
9581 static void bnxt_hwmon_close(struct bnxt *bp)
9585 static void bnxt_hwmon_open(struct bnxt *bp)
9590 static bool bnxt_eee_config_ok(struct bnxt *bp)
9592 struct ethtool_eee *eee = &bp->eee;
9593 struct bnxt_link_info *link_info = &bp->link_info;
9595 if (!(bp->flags & BNXT_FLAG_EEE_CAP))
9598 if (eee->eee_enabled) {
9600 _bnxt_fw_to_ethtool_adv_spds(link_info->advertising, 0);
9602 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) {
9603 eee->eee_enabled = 0;
9606 if (eee->advertised & ~advertising) {
9607 eee->advertised = advertising & eee->supported;
9614 static int bnxt_update_phy_setting(struct bnxt *bp)
9617 bool update_link = false;
9618 bool update_pause = false;
9619 bool update_eee = false;
9620 struct bnxt_link_info *link_info = &bp->link_info;
9622 rc = bnxt_update_link(bp, true);
9624 netdev_err(bp->dev, "failed to update link (rc: %x)\n",
9628 if (!BNXT_SINGLE_PF(bp))
9631 if ((link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) &&
9632 (link_info->auto_pause_setting & BNXT_LINK_PAUSE_BOTH) !=
9633 link_info->req_flow_ctrl)
9634 update_pause = true;
9635 if (!(link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) &&
9636 link_info->force_pause_setting != link_info->req_flow_ctrl)
9637 update_pause = true;
9638 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) {
9639 if (BNXT_AUTO_MODE(link_info->auto_mode))
9641 if (link_info->req_signal_mode == BNXT_SIG_MODE_NRZ &&
9642 link_info->req_link_speed != link_info->force_link_speed)
9644 else if (link_info->req_signal_mode == BNXT_SIG_MODE_PAM4 &&
9645 link_info->req_link_speed != link_info->force_pam4_link_speed)
9647 if (link_info->req_duplex != link_info->duplex_setting)
9650 if (link_info->auto_mode == BNXT_LINK_AUTO_NONE)
9652 if (link_info->advertising != link_info->auto_link_speeds ||
9653 link_info->advertising_pam4 != link_info->auto_pam4_link_speeds)
9657 /* The last close may have shutdown the link, so need to call
9658 * PHY_CFG to bring it back up.
9660 if (!bp->link_info.link_up)
9663 if (!bnxt_eee_config_ok(bp))
9667 rc = bnxt_hwrm_set_link_setting(bp, update_pause, update_eee);
9668 else if (update_pause)
9669 rc = bnxt_hwrm_set_pause(bp);
9671 netdev_err(bp->dev, "failed to update phy setting (rc: %x)\n",
9679 /* Common routine to pre-map certain register block to different GRC window.
9680 * A PF has 16 4K windows and a VF has 4 4K windows. However, only 15 windows
9681 * in PF and 3 windows in VF that can be customized to map in different
9684 static void bnxt_preset_reg_win(struct bnxt *bp)
9687 /* CAG registers map to GRC window #4 */
9688 writel(BNXT_CAG_REG_BASE,
9689 bp->bar0 + BNXT_GRCPF_REG_WINDOW_BASE_OUT + 12);
9693 static int bnxt_init_dflt_ring_mode(struct bnxt *bp);
9695 static int __bnxt_open_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init)
9699 bnxt_preset_reg_win(bp);
9700 netif_carrier_off(bp->dev);
9702 /* Reserve rings now if none were reserved at driver probe. */
9703 rc = bnxt_init_dflt_ring_mode(bp);
9705 netdev_err(bp->dev, "Failed to reserve default rings at open\n");
9709 rc = bnxt_reserve_rings(bp, irq_re_init);
9712 if ((bp->flags & BNXT_FLAG_RFS) &&
9713 !(bp->flags & BNXT_FLAG_USING_MSIX)) {
9714 /* disable RFS if falling back to INTA */
9715 bp->dev->hw_features &= ~NETIF_F_NTUPLE;
9716 bp->flags &= ~BNXT_FLAG_RFS;
9719 rc = bnxt_alloc_mem(bp, irq_re_init);
9721 netdev_err(bp->dev, "bnxt_alloc_mem err: %x\n", rc);
9722 goto open_err_free_mem;
9727 rc = bnxt_request_irq(bp);
9729 netdev_err(bp->dev, "bnxt_request_irq err: %x\n", rc);
9734 rc = bnxt_init_nic(bp, irq_re_init);
9736 netdev_err(bp->dev, "bnxt_init_nic err: %x\n", rc);
9740 bnxt_enable_napi(bp);
9741 bnxt_debug_dev_init(bp);
9744 mutex_lock(&bp->link_lock);
9745 rc = bnxt_update_phy_setting(bp);
9746 mutex_unlock(&bp->link_lock);
9748 netdev_warn(bp->dev, "failed to update phy settings\n");
9749 if (BNXT_SINGLE_PF(bp)) {
9750 bp->link_info.phy_retry = true;
9751 bp->link_info.phy_retry_expires =
9758 udp_tunnel_nic_reset_ntf(bp->dev);
9760 set_bit(BNXT_STATE_OPEN, &bp->state);
9761 bnxt_enable_int(bp);
9762 /* Enable TX queues */
9764 mod_timer(&bp->timer, jiffies + bp->current_interval);
9765 /* Poll link status and check for SFP+ module status */
9766 bnxt_get_port_module_status(bp);
9768 /* VF-reps may need to be re-opened after the PF is re-opened */
9770 bnxt_vf_reps_open(bp);
9779 bnxt_free_mem(bp, true);
9783 /* rtnl_lock held */
9784 int bnxt_open_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init)
9788 if (test_bit(BNXT_STATE_ABORT_ERR, &bp->state))
9791 rc = __bnxt_open_nic(bp, irq_re_init, link_re_init);
9793 netdev_err(bp->dev, "nic open fail (rc: %x)\n", rc);
9799 /* rtnl_lock held, open the NIC half way by allocating all resources, but
9800 * NAPI, IRQ, and TX are not enabled. This is mainly used for offline
9803 int bnxt_half_open_nic(struct bnxt *bp)
9807 rc = bnxt_alloc_mem(bp, false);
9809 netdev_err(bp->dev, "bnxt_alloc_mem err: %x\n", rc);
9812 rc = bnxt_init_nic(bp, false);
9814 netdev_err(bp->dev, "bnxt_init_nic err: %x\n", rc);
9821 bnxt_free_mem(bp, false);
9826 /* rtnl_lock held, this call can only be made after a previous successful
9827 * call to bnxt_half_open_nic().
9829 void bnxt_half_close_nic(struct bnxt *bp)
9831 bnxt_hwrm_resource_free(bp, false, false);
9833 bnxt_free_mem(bp, false);
9836 static void bnxt_reenable_sriov(struct bnxt *bp)
9839 struct bnxt_pf_info *pf = &bp->pf;
9840 int n = pf->active_vfs;
9843 bnxt_cfg_hw_sriov(bp, &n, true);
9847 static int bnxt_open(struct net_device *dev)
9849 struct bnxt *bp = netdev_priv(dev);
9852 if (test_bit(BNXT_STATE_ABORT_ERR, &bp->state)) {
9853 netdev_err(bp->dev, "A previous firmware reset did not complete, aborting\n");
9857 rc = bnxt_hwrm_if_change(bp, true);
9860 rc = __bnxt_open_nic(bp, true, true);
9862 bnxt_hwrm_if_change(bp, false);
9864 if (test_and_clear_bit(BNXT_STATE_FW_RESET_DET, &bp->state)) {
9865 if (!test_bit(BNXT_STATE_IN_FW_RESET, &bp->state)) {
9866 bnxt_ulp_start(bp, 0);
9867 bnxt_reenable_sriov(bp);
9870 bnxt_hwmon_open(bp);
9876 static bool bnxt_drv_busy(struct bnxt *bp)
9878 return (test_bit(BNXT_STATE_IN_SP_TASK, &bp->state) ||
9879 test_bit(BNXT_STATE_READ_STATS, &bp->state));
9882 static void bnxt_get_ring_stats(struct bnxt *bp,
9883 struct rtnl_link_stats64 *stats);
9885 static void __bnxt_close_nic(struct bnxt *bp, bool irq_re_init,
9888 /* Close the VF-reps before closing PF */
9890 bnxt_vf_reps_close(bp);
9892 /* Change device state to avoid TX queue wake up's */
9893 bnxt_tx_disable(bp);
9895 clear_bit(BNXT_STATE_OPEN, &bp->state);
9896 smp_mb__after_atomic();
9897 while (bnxt_drv_busy(bp))
9900 /* Flush rings and and disable interrupts */
9901 bnxt_shutdown_nic(bp, irq_re_init);
9903 /* TODO CHIMP_FW: Link/PHY related cleanup if (link_re_init) */
9905 bnxt_debug_dev_exit(bp);
9906 bnxt_disable_napi(bp);
9907 del_timer_sync(&bp->timer);
9910 /* Save ring stats before shutdown */
9911 if (bp->bnapi && irq_re_init)
9912 bnxt_get_ring_stats(bp, &bp->net_stats_prev);
9917 bnxt_free_mem(bp, irq_re_init);
9920 int bnxt_close_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init)
9924 if (test_bit(BNXT_STATE_IN_FW_RESET, &bp->state)) {
9925 /* If we get here, it means firmware reset is in progress
9926 * while we are trying to close. We can safely proceed with
9927 * the close because we are holding rtnl_lock(). Some firmware
9928 * messages may fail as we proceed to close. We set the
9929 * ABORT_ERR flag here so that the FW reset thread will later
9930 * abort when it gets the rtnl_lock() and sees the flag.
9932 netdev_warn(bp->dev, "FW reset in progress during close, FW reset will be aborted\n");
9933 set_bit(BNXT_STATE_ABORT_ERR, &bp->state);
9936 #ifdef CONFIG_BNXT_SRIOV
9937 if (bp->sriov_cfg) {
9938 rc = wait_event_interruptible_timeout(bp->sriov_cfg_wait,
9940 BNXT_SRIOV_CFG_WAIT_TMO);
9942 netdev_warn(bp->dev, "timeout waiting for SRIOV config operation to complete!\n");
9945 __bnxt_close_nic(bp, irq_re_init, link_re_init);
9949 static int bnxt_close(struct net_device *dev)
9951 struct bnxt *bp = netdev_priv(dev);
9953 bnxt_hwmon_close(bp);
9954 bnxt_close_nic(bp, true, true);
9955 bnxt_hwrm_shutdown_link(bp);
9956 bnxt_hwrm_if_change(bp, false);
9960 static int bnxt_hwrm_port_phy_read(struct bnxt *bp, u16 phy_addr, u16 reg,
9963 struct hwrm_port_phy_mdio_read_output *resp = bp->hwrm_cmd_resp_addr;
9964 struct hwrm_port_phy_mdio_read_input req = {0};
9967 if (bp->hwrm_spec_code < 0x10a00)
9970 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_MDIO_READ, -1, -1);
9971 req.port_id = cpu_to_le16(bp->pf.port_id);
9972 req.phy_addr = phy_addr;
9973 req.reg_addr = cpu_to_le16(reg & 0x1f);
9974 if (mdio_phy_id_is_c45(phy_addr)) {
9976 req.phy_addr = mdio_phy_id_prtad(phy_addr);
9977 req.dev_addr = mdio_phy_id_devad(phy_addr);
9978 req.reg_addr = cpu_to_le16(reg);
9981 mutex_lock(&bp->hwrm_cmd_lock);
9982 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
9984 *val = le16_to_cpu(resp->reg_data);
9985 mutex_unlock(&bp->hwrm_cmd_lock);
9989 static int bnxt_hwrm_port_phy_write(struct bnxt *bp, u16 phy_addr, u16 reg,
9992 struct hwrm_port_phy_mdio_write_input req = {0};
9994 if (bp->hwrm_spec_code < 0x10a00)
9997 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_MDIO_WRITE, -1, -1);
9998 req.port_id = cpu_to_le16(bp->pf.port_id);
9999 req.phy_addr = phy_addr;
10000 req.reg_addr = cpu_to_le16(reg & 0x1f);
10001 if (mdio_phy_id_is_c45(phy_addr)) {
10003 req.phy_addr = mdio_phy_id_prtad(phy_addr);
10004 req.dev_addr = mdio_phy_id_devad(phy_addr);
10005 req.reg_addr = cpu_to_le16(reg);
10007 req.reg_data = cpu_to_le16(val);
10009 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
10012 /* rtnl_lock held */
10013 static int bnxt_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
10015 struct mii_ioctl_data *mdio = if_mii(ifr);
10016 struct bnxt *bp = netdev_priv(dev);
10021 mdio->phy_id = bp->link_info.phy_addr;
10024 case SIOCGMIIREG: {
10025 u16 mii_regval = 0;
10027 if (!netif_running(dev))
10030 rc = bnxt_hwrm_port_phy_read(bp, mdio->phy_id, mdio->reg_num,
10032 mdio->val_out = mii_regval;
10037 if (!netif_running(dev))
10040 return bnxt_hwrm_port_phy_write(bp, mdio->phy_id, mdio->reg_num,
10047 return -EOPNOTSUPP;
10050 static void bnxt_get_ring_stats(struct bnxt *bp,
10051 struct rtnl_link_stats64 *stats)
10055 for (i = 0; i < bp->cp_nr_rings; i++) {
10056 struct bnxt_napi *bnapi = bp->bnapi[i];
10057 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
10058 u64 *sw = cpr->stats.sw_stats;
10060 stats->rx_packets += BNXT_GET_RING_STATS64(sw, rx_ucast_pkts);
10061 stats->rx_packets += BNXT_GET_RING_STATS64(sw, rx_mcast_pkts);
10062 stats->rx_packets += BNXT_GET_RING_STATS64(sw, rx_bcast_pkts);
10064 stats->tx_packets += BNXT_GET_RING_STATS64(sw, tx_ucast_pkts);
10065 stats->tx_packets += BNXT_GET_RING_STATS64(sw, tx_mcast_pkts);
10066 stats->tx_packets += BNXT_GET_RING_STATS64(sw, tx_bcast_pkts);
10068 stats->rx_bytes += BNXT_GET_RING_STATS64(sw, rx_ucast_bytes);
10069 stats->rx_bytes += BNXT_GET_RING_STATS64(sw, rx_mcast_bytes);
10070 stats->rx_bytes += BNXT_GET_RING_STATS64(sw, rx_bcast_bytes);
10072 stats->tx_bytes += BNXT_GET_RING_STATS64(sw, tx_ucast_bytes);
10073 stats->tx_bytes += BNXT_GET_RING_STATS64(sw, tx_mcast_bytes);
10074 stats->tx_bytes += BNXT_GET_RING_STATS64(sw, tx_bcast_bytes);
10076 stats->rx_missed_errors +=
10077 BNXT_GET_RING_STATS64(sw, rx_discard_pkts);
10079 stats->multicast += BNXT_GET_RING_STATS64(sw, rx_mcast_pkts);
10081 stats->tx_dropped += BNXT_GET_RING_STATS64(sw, tx_error_pkts);
10085 static void bnxt_add_prev_stats(struct bnxt *bp,
10086 struct rtnl_link_stats64 *stats)
10088 struct rtnl_link_stats64 *prev_stats = &bp->net_stats_prev;
10090 stats->rx_packets += prev_stats->rx_packets;
10091 stats->tx_packets += prev_stats->tx_packets;
10092 stats->rx_bytes += prev_stats->rx_bytes;
10093 stats->tx_bytes += prev_stats->tx_bytes;
10094 stats->rx_missed_errors += prev_stats->rx_missed_errors;
10095 stats->multicast += prev_stats->multicast;
10096 stats->tx_dropped += prev_stats->tx_dropped;
10100 bnxt_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
10102 struct bnxt *bp = netdev_priv(dev);
10104 set_bit(BNXT_STATE_READ_STATS, &bp->state);
10105 /* Make sure bnxt_close_nic() sees that we are reading stats before
10106 * we check the BNXT_STATE_OPEN flag.
10108 smp_mb__after_atomic();
10109 if (!test_bit(BNXT_STATE_OPEN, &bp->state)) {
10110 clear_bit(BNXT_STATE_READ_STATS, &bp->state);
10111 *stats = bp->net_stats_prev;
10115 bnxt_get_ring_stats(bp, stats);
10116 bnxt_add_prev_stats(bp, stats);
10118 if (bp->flags & BNXT_FLAG_PORT_STATS) {
10119 u64 *rx = bp->port_stats.sw_stats;
10120 u64 *tx = bp->port_stats.sw_stats +
10121 BNXT_TX_PORT_STATS_BYTE_OFFSET / 8;
10123 stats->rx_crc_errors =
10124 BNXT_GET_RX_PORT_STATS64(rx, rx_fcs_err_frames);
10125 stats->rx_frame_errors =
10126 BNXT_GET_RX_PORT_STATS64(rx, rx_align_err_frames);
10127 stats->rx_length_errors =
10128 BNXT_GET_RX_PORT_STATS64(rx, rx_undrsz_frames) +
10129 BNXT_GET_RX_PORT_STATS64(rx, rx_ovrsz_frames) +
10130 BNXT_GET_RX_PORT_STATS64(rx, rx_runt_frames);
10132 BNXT_GET_RX_PORT_STATS64(rx, rx_false_carrier_frames) +
10133 BNXT_GET_RX_PORT_STATS64(rx, rx_jbr_frames);
10134 stats->collisions =
10135 BNXT_GET_TX_PORT_STATS64(tx, tx_total_collisions);
10136 stats->tx_fifo_errors =
10137 BNXT_GET_TX_PORT_STATS64(tx, tx_fifo_underruns);
10138 stats->tx_errors = BNXT_GET_TX_PORT_STATS64(tx, tx_err);
10140 clear_bit(BNXT_STATE_READ_STATS, &bp->state);
10143 static bool bnxt_mc_list_updated(struct bnxt *bp, u32 *rx_mask)
10145 struct net_device *dev = bp->dev;
10146 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
10147 struct netdev_hw_addr *ha;
10150 bool update = false;
10153 netdev_for_each_mc_addr(ha, dev) {
10154 if (mc_count >= BNXT_MAX_MC_ADDRS) {
10155 *rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST;
10156 vnic->mc_list_count = 0;
10160 if (!ether_addr_equal(haddr, vnic->mc_list + off)) {
10161 memcpy(vnic->mc_list + off, haddr, ETH_ALEN);
10168 *rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_MCAST;
10170 if (mc_count != vnic->mc_list_count) {
10171 vnic->mc_list_count = mc_count;
10177 static bool bnxt_uc_list_updated(struct bnxt *bp)
10179 struct net_device *dev = bp->dev;
10180 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
10181 struct netdev_hw_addr *ha;
10184 if (netdev_uc_count(dev) != (vnic->uc_filter_count - 1))
10187 netdev_for_each_uc_addr(ha, dev) {
10188 if (!ether_addr_equal(ha->addr, vnic->uc_list + off))
10196 static void bnxt_set_rx_mode(struct net_device *dev)
10198 struct bnxt *bp = netdev_priv(dev);
10199 struct bnxt_vnic_info *vnic;
10200 bool mc_update = false;
10204 if (!test_bit(BNXT_STATE_OPEN, &bp->state))
10207 vnic = &bp->vnic_info[0];
10208 mask = vnic->rx_mask;
10209 mask &= ~(CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS |
10210 CFA_L2_SET_RX_MASK_REQ_MASK_MCAST |
10211 CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST |
10212 CFA_L2_SET_RX_MASK_REQ_MASK_BCAST);
10214 if ((dev->flags & IFF_PROMISC) && bnxt_promisc_ok(bp))
10215 mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS;
10217 uc_update = bnxt_uc_list_updated(bp);
10219 if (dev->flags & IFF_BROADCAST)
10220 mask |= CFA_L2_SET_RX_MASK_REQ_MASK_BCAST;
10221 if (dev->flags & IFF_ALLMULTI) {
10222 mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST;
10223 vnic->mc_list_count = 0;
10225 mc_update = bnxt_mc_list_updated(bp, &mask);
10228 if (mask != vnic->rx_mask || uc_update || mc_update) {
10229 vnic->rx_mask = mask;
10231 set_bit(BNXT_RX_MASK_SP_EVENT, &bp->sp_event);
10232 bnxt_queue_sp_work(bp);
10236 static int bnxt_cfg_rx_mode(struct bnxt *bp)
10238 struct net_device *dev = bp->dev;
10239 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
10240 struct netdev_hw_addr *ha;
10241 int i, off = 0, rc;
10244 netif_addr_lock_bh(dev);
10245 uc_update = bnxt_uc_list_updated(bp);
10246 netif_addr_unlock_bh(dev);
10251 mutex_lock(&bp->hwrm_cmd_lock);
10252 for (i = 1; i < vnic->uc_filter_count; i++) {
10253 struct hwrm_cfa_l2_filter_free_input req = {0};
10255 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_FILTER_FREE, -1,
10258 req.l2_filter_id = vnic->fw_l2_filter_id[i];
10260 rc = _hwrm_send_message(bp, &req, sizeof(req),
10263 mutex_unlock(&bp->hwrm_cmd_lock);
10265 vnic->uc_filter_count = 1;
10267 netif_addr_lock_bh(dev);
10268 if (netdev_uc_count(dev) > (BNXT_MAX_UC_ADDRS - 1)) {
10269 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS;
10271 netdev_for_each_uc_addr(ha, dev) {
10272 memcpy(vnic->uc_list + off, ha->addr, ETH_ALEN);
10274 vnic->uc_filter_count++;
10277 netif_addr_unlock_bh(dev);
10279 for (i = 1, off = 0; i < vnic->uc_filter_count; i++, off += ETH_ALEN) {
10280 rc = bnxt_hwrm_set_vnic_filter(bp, 0, i, vnic->uc_list + off);
10282 netdev_err(bp->dev, "HWRM vnic filter failure rc: %x\n",
10284 vnic->uc_filter_count = i;
10290 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, 0);
10291 if (rc && vnic->mc_list_count) {
10292 netdev_info(bp->dev, "Failed setting MC filters rc: %d, turning on ALL_MCAST mode\n",
10294 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST;
10295 vnic->mc_list_count = 0;
10296 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, 0);
10299 netdev_err(bp->dev, "HWRM cfa l2 rx mask failure rc: %d\n",
10305 static bool bnxt_can_reserve_rings(struct bnxt *bp)
10307 #ifdef CONFIG_BNXT_SRIOV
10308 if (BNXT_NEW_RM(bp) && BNXT_VF(bp)) {
10309 struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
10311 /* No minimum rings were provisioned by the PF. Don't
10312 * reserve rings by default when device is down.
10314 if (hw_resc->min_tx_rings || hw_resc->resv_tx_rings)
10317 if (!netif_running(bp->dev))
10324 /* If the chip and firmware supports RFS */
10325 static bool bnxt_rfs_supported(struct bnxt *bp)
10327 if (bp->flags & BNXT_FLAG_CHIP_P5) {
10328 if (bp->fw_cap & BNXT_FW_CAP_CFA_RFS_RING_TBL_IDX_V2)
10332 if (BNXT_PF(bp) && !BNXT_CHIP_TYPE_NITRO_A0(bp))
10334 if (bp->flags & BNXT_FLAG_NEW_RSS_CAP)
10339 /* If runtime conditions support RFS */
10340 static bool bnxt_rfs_capable(struct bnxt *bp)
10342 #ifdef CONFIG_RFS_ACCEL
10343 int vnics, max_vnics, max_rss_ctxs;
10345 if (bp->flags & BNXT_FLAG_CHIP_P5)
10346 return bnxt_rfs_supported(bp);
10347 if (!(bp->flags & BNXT_FLAG_MSIX_CAP) || !bnxt_can_reserve_rings(bp))
10350 vnics = 1 + bp->rx_nr_rings;
10351 max_vnics = bnxt_get_max_func_vnics(bp);
10352 max_rss_ctxs = bnxt_get_max_func_rss_ctxs(bp);
10354 /* RSS contexts not a limiting factor */
10355 if (bp->flags & BNXT_FLAG_NEW_RSS_CAP)
10356 max_rss_ctxs = max_vnics;
10357 if (vnics > max_vnics || vnics > max_rss_ctxs) {
10358 if (bp->rx_nr_rings > 1)
10359 netdev_warn(bp->dev,
10360 "Not enough resources to support NTUPLE filters, enough resources for up to %d rx rings\n",
10361 min(max_rss_ctxs - 1, max_vnics - 1));
10365 if (!BNXT_NEW_RM(bp))
10368 if (vnics == bp->hw_resc.resv_vnics)
10371 bnxt_hwrm_reserve_rings(bp, 0, 0, 0, 0, 0, vnics);
10372 if (vnics <= bp->hw_resc.resv_vnics)
10375 netdev_warn(bp->dev, "Unable to reserve resources to support NTUPLE filters.\n");
10376 bnxt_hwrm_reserve_rings(bp, 0, 0, 0, 0, 0, 1);
10383 static netdev_features_t bnxt_fix_features(struct net_device *dev,
10384 netdev_features_t features)
10386 struct bnxt *bp = netdev_priv(dev);
10387 netdev_features_t vlan_features;
10389 if ((features & NETIF_F_NTUPLE) && !bnxt_rfs_capable(bp))
10390 features &= ~NETIF_F_NTUPLE;
10392 if (bp->flags & BNXT_FLAG_NO_AGG_RINGS)
10393 features &= ~(NETIF_F_LRO | NETIF_F_GRO_HW);
10395 if (!(features & NETIF_F_GRO))
10396 features &= ~NETIF_F_GRO_HW;
10398 if (features & NETIF_F_GRO_HW)
10399 features &= ~NETIF_F_LRO;
10401 /* Both CTAG and STAG VLAN accelaration on the RX side have to be
10402 * turned on or off together.
10404 vlan_features = features & BNXT_HW_FEATURE_VLAN_ALL_RX;
10405 if (vlan_features != BNXT_HW_FEATURE_VLAN_ALL_RX) {
10406 if (dev->features & BNXT_HW_FEATURE_VLAN_ALL_RX)
10407 features &= ~BNXT_HW_FEATURE_VLAN_ALL_RX;
10408 else if (vlan_features)
10409 features |= BNXT_HW_FEATURE_VLAN_ALL_RX;
10411 #ifdef CONFIG_BNXT_SRIOV
10412 if (BNXT_VF(bp) && bp->vf.vlan)
10413 features &= ~BNXT_HW_FEATURE_VLAN_ALL_RX;
10418 static int bnxt_set_features(struct net_device *dev, netdev_features_t features)
10420 struct bnxt *bp = netdev_priv(dev);
10421 u32 flags = bp->flags;
10424 bool re_init = false;
10425 bool update_tpa = false;
10427 flags &= ~BNXT_FLAG_ALL_CONFIG_FEATS;
10428 if (features & NETIF_F_GRO_HW)
10429 flags |= BNXT_FLAG_GRO;
10430 else if (features & NETIF_F_LRO)
10431 flags |= BNXT_FLAG_LRO;
10433 if (bp->flags & BNXT_FLAG_NO_AGG_RINGS)
10434 flags &= ~BNXT_FLAG_TPA;
10436 if (features & BNXT_HW_FEATURE_VLAN_ALL_RX)
10437 flags |= BNXT_FLAG_STRIP_VLAN;
10439 if (features & NETIF_F_NTUPLE)
10440 flags |= BNXT_FLAG_RFS;
10442 changes = flags ^ bp->flags;
10443 if (changes & BNXT_FLAG_TPA) {
10445 if ((bp->flags & BNXT_FLAG_TPA) == 0 ||
10446 (flags & BNXT_FLAG_TPA) == 0 ||
10447 (bp->flags & BNXT_FLAG_CHIP_P5))
10451 if (changes & ~BNXT_FLAG_TPA)
10454 if (flags != bp->flags) {
10455 u32 old_flags = bp->flags;
10457 if (!test_bit(BNXT_STATE_OPEN, &bp->state)) {
10460 bnxt_set_ring_params(bp);
10465 bnxt_close_nic(bp, false, false);
10468 bnxt_set_ring_params(bp);
10470 return bnxt_open_nic(bp, false, false);
10474 rc = bnxt_set_tpa(bp,
10475 (flags & BNXT_FLAG_TPA) ?
10478 bp->flags = old_flags;
10484 int bnxt_dbg_hwrm_rd_reg(struct bnxt *bp, u32 reg_off, u16 num_words,
10487 struct hwrm_dbg_read_direct_output *resp = bp->hwrm_cmd_resp_addr;
10488 struct hwrm_dbg_read_direct_input req = {0};
10489 __le32 *dbg_reg_buf;
10490 dma_addr_t mapping;
10493 dbg_reg_buf = dma_alloc_coherent(&bp->pdev->dev, num_words * 4,
10494 &mapping, GFP_KERNEL);
10497 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_DBG_READ_DIRECT, -1, -1);
10498 req.host_dest_addr = cpu_to_le64(mapping);
10499 req.read_addr = cpu_to_le32(reg_off + CHIMP_REG_VIEW_ADDR);
10500 req.read_len32 = cpu_to_le32(num_words);
10501 mutex_lock(&bp->hwrm_cmd_lock);
10502 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
10503 if (rc || resp->error_code) {
10505 goto dbg_rd_reg_exit;
10507 for (i = 0; i < num_words; i++)
10508 reg_buf[i] = le32_to_cpu(dbg_reg_buf[i]);
10511 mutex_unlock(&bp->hwrm_cmd_lock);
10512 dma_free_coherent(&bp->pdev->dev, num_words * 4, dbg_reg_buf, mapping);
10516 static int bnxt_dbg_hwrm_ring_info_get(struct bnxt *bp, u8 ring_type,
10517 u32 ring_id, u32 *prod, u32 *cons)
10519 struct hwrm_dbg_ring_info_get_output *resp = bp->hwrm_cmd_resp_addr;
10520 struct hwrm_dbg_ring_info_get_input req = {0};
10523 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_DBG_RING_INFO_GET, -1, -1);
10524 req.ring_type = ring_type;
10525 req.fw_ring_id = cpu_to_le32(ring_id);
10526 mutex_lock(&bp->hwrm_cmd_lock);
10527 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
10529 *prod = le32_to_cpu(resp->producer_index);
10530 *cons = le32_to_cpu(resp->consumer_index);
10532 mutex_unlock(&bp->hwrm_cmd_lock);
10536 static void bnxt_dump_tx_sw_state(struct bnxt_napi *bnapi)
10538 struct bnxt_tx_ring_info *txr = bnapi->tx_ring;
10539 int i = bnapi->index;
10544 netdev_info(bnapi->bp->dev, "[%d]: tx{fw_ring: %d prod: %x cons: %x}\n",
10545 i, txr->tx_ring_struct.fw_ring_id, txr->tx_prod,
10549 static void bnxt_dump_rx_sw_state(struct bnxt_napi *bnapi)
10551 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
10552 int i = bnapi->index;
10557 netdev_info(bnapi->bp->dev, "[%d]: rx{fw_ring: %d prod: %x} rx_agg{fw_ring: %d agg_prod: %x sw_agg_prod: %x}\n",
10558 i, rxr->rx_ring_struct.fw_ring_id, rxr->rx_prod,
10559 rxr->rx_agg_ring_struct.fw_ring_id, rxr->rx_agg_prod,
10560 rxr->rx_sw_agg_prod);
10563 static void bnxt_dump_cp_sw_state(struct bnxt_napi *bnapi)
10565 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
10566 int i = bnapi->index;
10568 netdev_info(bnapi->bp->dev, "[%d]: cp{fw_ring: %d raw_cons: %x}\n",
10569 i, cpr->cp_ring_struct.fw_ring_id, cpr->cp_raw_cons);
10572 static void bnxt_dbg_dump_states(struct bnxt *bp)
10575 struct bnxt_napi *bnapi;
10577 for (i = 0; i < bp->cp_nr_rings; i++) {
10578 bnapi = bp->bnapi[i];
10579 if (netif_msg_drv(bp)) {
10580 bnxt_dump_tx_sw_state(bnapi);
10581 bnxt_dump_rx_sw_state(bnapi);
10582 bnxt_dump_cp_sw_state(bnapi);
10587 static int bnxt_hwrm_rx_ring_reset(struct bnxt *bp, int ring_nr)
10589 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[ring_nr];
10590 struct hwrm_ring_reset_input req = {0};
10591 struct bnxt_napi *bnapi = rxr->bnapi;
10592 struct bnxt_cp_ring_info *cpr;
10595 cpr = &bnapi->cp_ring;
10596 cp_ring_id = cpr->cp_ring_struct.fw_ring_id;
10597 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_RESET, cp_ring_id, -1);
10598 req.ring_type = RING_RESET_REQ_RING_TYPE_RX_RING_GRP;
10599 req.ring_id = cpu_to_le16(bp->grp_info[bnapi->index].fw_grp_id);
10600 return hwrm_send_message_silent(bp, &req, sizeof(req),
10604 static void bnxt_reset_task(struct bnxt *bp, bool silent)
10607 bnxt_dbg_dump_states(bp);
10608 if (netif_running(bp->dev)) {
10612 bnxt_close_nic(bp, false, false);
10613 bnxt_open_nic(bp, false, false);
10616 bnxt_close_nic(bp, true, false);
10617 rc = bnxt_open_nic(bp, true, false);
10618 bnxt_ulp_start(bp, rc);
10623 static void bnxt_tx_timeout(struct net_device *dev, unsigned int txqueue)
10625 struct bnxt *bp = netdev_priv(dev);
10627 netdev_err(bp->dev, "TX timeout detected, starting reset task!\n");
10628 set_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event);
10629 bnxt_queue_sp_work(bp);
10632 static void bnxt_fw_health_check(struct bnxt *bp)
10634 struct bnxt_fw_health *fw_health = bp->fw_health;
10637 if (!fw_health->enabled || test_bit(BNXT_STATE_IN_FW_RESET, &bp->state))
10640 if (fw_health->tmr_counter) {
10641 fw_health->tmr_counter--;
10645 val = bnxt_fw_health_readl(bp, BNXT_FW_HEARTBEAT_REG);
10646 if (val == fw_health->last_fw_heartbeat)
10649 fw_health->last_fw_heartbeat = val;
10651 val = bnxt_fw_health_readl(bp, BNXT_FW_RESET_CNT_REG);
10652 if (val != fw_health->last_fw_reset_cnt)
10655 fw_health->tmr_counter = fw_health->tmr_multiplier;
10659 set_bit(BNXT_FW_EXCEPTION_SP_EVENT, &bp->sp_event);
10660 bnxt_queue_sp_work(bp);
10663 static void bnxt_timer(struct timer_list *t)
10665 struct bnxt *bp = from_timer(bp, t, timer);
10666 struct net_device *dev = bp->dev;
10668 if (!netif_running(dev) || !test_bit(BNXT_STATE_OPEN, &bp->state))
10671 if (atomic_read(&bp->intr_sem) != 0)
10672 goto bnxt_restart_timer;
10674 if (bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY)
10675 bnxt_fw_health_check(bp);
10677 if (bp->link_info.link_up && bp->stats_coal_ticks) {
10678 set_bit(BNXT_PERIODIC_STATS_SP_EVENT, &bp->sp_event);
10679 bnxt_queue_sp_work(bp);
10682 if (bnxt_tc_flower_enabled(bp)) {
10683 set_bit(BNXT_FLOW_STATS_SP_EVENT, &bp->sp_event);
10684 bnxt_queue_sp_work(bp);
10687 #ifdef CONFIG_RFS_ACCEL
10688 if ((bp->flags & BNXT_FLAG_RFS) && bp->ntp_fltr_count) {
10689 set_bit(BNXT_RX_NTP_FLTR_SP_EVENT, &bp->sp_event);
10690 bnxt_queue_sp_work(bp);
10692 #endif /*CONFIG_RFS_ACCEL*/
10694 if (bp->link_info.phy_retry) {
10695 if (time_after(jiffies, bp->link_info.phy_retry_expires)) {
10696 bp->link_info.phy_retry = false;
10697 netdev_warn(bp->dev, "failed to update phy settings after maximum retries.\n");
10699 set_bit(BNXT_UPDATE_PHY_SP_EVENT, &bp->sp_event);
10700 bnxt_queue_sp_work(bp);
10704 if ((bp->flags & BNXT_FLAG_CHIP_P5) && !bp->chip_rev &&
10705 netif_carrier_ok(dev)) {
10706 set_bit(BNXT_RING_COAL_NOW_SP_EVENT, &bp->sp_event);
10707 bnxt_queue_sp_work(bp);
10709 bnxt_restart_timer:
10710 mod_timer(&bp->timer, jiffies + bp->current_interval);
10713 static void bnxt_rtnl_lock_sp(struct bnxt *bp)
10715 /* We are called from bnxt_sp_task which has BNXT_STATE_IN_SP_TASK
10716 * set. If the device is being closed, bnxt_close() may be holding
10717 * rtnl() and waiting for BNXT_STATE_IN_SP_TASK to clear. So we
10718 * must clear BNXT_STATE_IN_SP_TASK before holding rtnl().
10720 clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
10724 static void bnxt_rtnl_unlock_sp(struct bnxt *bp)
10726 set_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
10730 /* Only called from bnxt_sp_task() */
10731 static void bnxt_reset(struct bnxt *bp, bool silent)
10733 bnxt_rtnl_lock_sp(bp);
10734 if (test_bit(BNXT_STATE_OPEN, &bp->state))
10735 bnxt_reset_task(bp, silent);
10736 bnxt_rtnl_unlock_sp(bp);
10739 /* Only called from bnxt_sp_task() */
10740 static void bnxt_rx_ring_reset(struct bnxt *bp)
10744 bnxt_rtnl_lock_sp(bp);
10745 if (!test_bit(BNXT_STATE_OPEN, &bp->state)) {
10746 bnxt_rtnl_unlock_sp(bp);
10749 /* Disable and flush TPA before resetting the RX ring */
10750 if (bp->flags & BNXT_FLAG_TPA)
10751 bnxt_set_tpa(bp, false);
10752 for (i = 0; i < bp->rx_nr_rings; i++) {
10753 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
10754 struct bnxt_cp_ring_info *cpr;
10757 if (!rxr->bnapi->in_reset)
10760 rc = bnxt_hwrm_rx_ring_reset(bp, i);
10762 if (rc == -EINVAL || rc == -EOPNOTSUPP)
10763 netdev_info_once(bp->dev, "RX ring reset not supported by firmware, falling back to global reset\n");
10765 netdev_warn(bp->dev, "RX ring reset failed, rc = %d, falling back to global reset\n",
10767 bnxt_reset_task(bp, true);
10770 bnxt_free_one_rx_ring_skbs(bp, i);
10772 rxr->rx_agg_prod = 0;
10773 rxr->rx_sw_agg_prod = 0;
10774 rxr->rx_next_cons = 0;
10775 rxr->bnapi->in_reset = false;
10776 bnxt_alloc_one_rx_ring(bp, i);
10777 cpr = &rxr->bnapi->cp_ring;
10778 cpr->sw_stats.rx.rx_resets++;
10779 if (bp->flags & BNXT_FLAG_AGG_RINGS)
10780 bnxt_db_write(bp, &rxr->rx_agg_db, rxr->rx_agg_prod);
10781 bnxt_db_write(bp, &rxr->rx_db, rxr->rx_prod);
10783 if (bp->flags & BNXT_FLAG_TPA)
10784 bnxt_set_tpa(bp, true);
10785 bnxt_rtnl_unlock_sp(bp);
10788 static void bnxt_fw_reset_close(struct bnxt *bp)
10791 /* When firmware is fatal state, disable PCI device to prevent
10792 * any potential bad DMAs before freeing kernel memory.
10794 if (test_bit(BNXT_STATE_FW_FATAL_COND, &bp->state))
10795 pci_disable_device(bp->pdev);
10796 __bnxt_close_nic(bp, true, false);
10797 bnxt_clear_int_mode(bp);
10798 bnxt_hwrm_func_drv_unrgtr(bp);
10799 if (pci_is_enabled(bp->pdev))
10800 pci_disable_device(bp->pdev);
10801 bnxt_free_ctx_mem(bp);
10806 static bool is_bnxt_fw_ok(struct bnxt *bp)
10808 struct bnxt_fw_health *fw_health = bp->fw_health;
10809 bool no_heartbeat = false, has_reset = false;
10812 val = bnxt_fw_health_readl(bp, BNXT_FW_HEARTBEAT_REG);
10813 if (val == fw_health->last_fw_heartbeat)
10814 no_heartbeat = true;
10816 val = bnxt_fw_health_readl(bp, BNXT_FW_RESET_CNT_REG);
10817 if (val != fw_health->last_fw_reset_cnt)
10820 if (!no_heartbeat && has_reset)
10826 /* rtnl_lock is acquired before calling this function */
10827 static void bnxt_force_fw_reset(struct bnxt *bp)
10829 struct bnxt_fw_health *fw_health = bp->fw_health;
10832 if (!test_bit(BNXT_STATE_OPEN, &bp->state) ||
10833 test_bit(BNXT_STATE_IN_FW_RESET, &bp->state))
10836 set_bit(BNXT_STATE_IN_FW_RESET, &bp->state);
10837 bnxt_fw_reset_close(bp);
10838 wait_dsecs = fw_health->master_func_wait_dsecs;
10839 if (fw_health->master) {
10840 if (fw_health->flags & ERROR_RECOVERY_QCFG_RESP_FLAGS_CO_CPU)
10842 bp->fw_reset_state = BNXT_FW_RESET_STATE_RESET_FW;
10844 bp->fw_reset_timestamp = jiffies + wait_dsecs * HZ / 10;
10845 wait_dsecs = fw_health->normal_func_wait_dsecs;
10846 bp->fw_reset_state = BNXT_FW_RESET_STATE_ENABLE_DEV;
10849 bp->fw_reset_min_dsecs = fw_health->post_reset_wait_dsecs;
10850 bp->fw_reset_max_dsecs = fw_health->post_reset_max_wait_dsecs;
10851 bnxt_queue_fw_reset_work(bp, wait_dsecs * HZ / 10);
10854 void bnxt_fw_exception(struct bnxt *bp)
10856 netdev_warn(bp->dev, "Detected firmware fatal condition, initiating reset\n");
10857 set_bit(BNXT_STATE_FW_FATAL_COND, &bp->state);
10858 bnxt_rtnl_lock_sp(bp);
10859 bnxt_force_fw_reset(bp);
10860 bnxt_rtnl_unlock_sp(bp);
10863 /* Returns the number of registered VFs, or 1 if VF configuration is pending, or
10866 static int bnxt_get_registered_vfs(struct bnxt *bp)
10868 #ifdef CONFIG_BNXT_SRIOV
10874 rc = bnxt_hwrm_func_qcfg(bp);
10876 netdev_err(bp->dev, "func_qcfg cmd failed, rc = %d\n", rc);
10879 if (bp->pf.registered_vfs)
10880 return bp->pf.registered_vfs;
10887 void bnxt_fw_reset(struct bnxt *bp)
10889 bnxt_rtnl_lock_sp(bp);
10890 if (test_bit(BNXT_STATE_OPEN, &bp->state) &&
10891 !test_bit(BNXT_STATE_IN_FW_RESET, &bp->state)) {
10894 set_bit(BNXT_STATE_IN_FW_RESET, &bp->state);
10895 if (bp->pf.active_vfs &&
10896 !test_bit(BNXT_STATE_FW_FATAL_COND, &bp->state))
10897 n = bnxt_get_registered_vfs(bp);
10899 netdev_err(bp->dev, "Firmware reset aborted, rc = %d\n",
10901 clear_bit(BNXT_STATE_IN_FW_RESET, &bp->state);
10902 dev_close(bp->dev);
10903 goto fw_reset_exit;
10904 } else if (n > 0) {
10905 u16 vf_tmo_dsecs = n * 10;
10907 if (bp->fw_reset_max_dsecs < vf_tmo_dsecs)
10908 bp->fw_reset_max_dsecs = vf_tmo_dsecs;
10909 bp->fw_reset_state =
10910 BNXT_FW_RESET_STATE_POLL_VF;
10911 bnxt_queue_fw_reset_work(bp, HZ / 10);
10912 goto fw_reset_exit;
10914 bnxt_fw_reset_close(bp);
10915 if (bp->fw_cap & BNXT_FW_CAP_ERR_RECOVER_RELOAD) {
10916 bp->fw_reset_state = BNXT_FW_RESET_STATE_POLL_FW_DOWN;
10919 bp->fw_reset_state = BNXT_FW_RESET_STATE_ENABLE_DEV;
10920 tmo = bp->fw_reset_min_dsecs * HZ / 10;
10922 bnxt_queue_fw_reset_work(bp, tmo);
10925 bnxt_rtnl_unlock_sp(bp);
10928 static void bnxt_chk_missed_irq(struct bnxt *bp)
10932 if (!(bp->flags & BNXT_FLAG_CHIP_P5))
10935 for (i = 0; i < bp->cp_nr_rings; i++) {
10936 struct bnxt_napi *bnapi = bp->bnapi[i];
10937 struct bnxt_cp_ring_info *cpr;
10944 cpr = &bnapi->cp_ring;
10945 for (j = 0; j < 2; j++) {
10946 struct bnxt_cp_ring_info *cpr2 = cpr->cp_ring_arr[j];
10949 if (!cpr2 || cpr2->has_more_work ||
10950 !bnxt_has_work(bp, cpr2))
10953 if (cpr2->cp_raw_cons != cpr2->last_cp_raw_cons) {
10954 cpr2->last_cp_raw_cons = cpr2->cp_raw_cons;
10957 fw_ring_id = cpr2->cp_ring_struct.fw_ring_id;
10958 bnxt_dbg_hwrm_ring_info_get(bp,
10959 DBG_RING_INFO_GET_REQ_RING_TYPE_L2_CMPL,
10960 fw_ring_id, &val[0], &val[1]);
10961 cpr->sw_stats.cmn.missed_irqs++;
10966 static void bnxt_cfg_ntp_filters(struct bnxt *);
10968 static void bnxt_init_ethtool_link_settings(struct bnxt *bp)
10970 struct bnxt_link_info *link_info = &bp->link_info;
10972 if (BNXT_AUTO_MODE(link_info->auto_mode)) {
10973 link_info->autoneg = BNXT_AUTONEG_SPEED;
10974 if (bp->hwrm_spec_code >= 0x10201) {
10975 if (link_info->auto_pause_setting &
10976 PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE)
10977 link_info->autoneg |= BNXT_AUTONEG_FLOW_CTRL;
10979 link_info->autoneg |= BNXT_AUTONEG_FLOW_CTRL;
10981 link_info->advertising = link_info->auto_link_speeds;
10982 link_info->advertising_pam4 = link_info->auto_pam4_link_speeds;
10984 link_info->req_link_speed = link_info->force_link_speed;
10985 link_info->req_signal_mode = BNXT_SIG_MODE_NRZ;
10986 if (link_info->force_pam4_link_speed) {
10987 link_info->req_link_speed =
10988 link_info->force_pam4_link_speed;
10989 link_info->req_signal_mode = BNXT_SIG_MODE_PAM4;
10991 link_info->req_duplex = link_info->duplex_setting;
10993 if (link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL)
10994 link_info->req_flow_ctrl =
10995 link_info->auto_pause_setting & BNXT_LINK_PAUSE_BOTH;
10997 link_info->req_flow_ctrl = link_info->force_pause_setting;
11000 static void bnxt_sp_task(struct work_struct *work)
11002 struct bnxt *bp = container_of(work, struct bnxt, sp_task);
11004 set_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
11005 smp_mb__after_atomic();
11006 if (!test_bit(BNXT_STATE_OPEN, &bp->state)) {
11007 clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
11011 if (test_and_clear_bit(BNXT_RX_MASK_SP_EVENT, &bp->sp_event))
11012 bnxt_cfg_rx_mode(bp);
11014 if (test_and_clear_bit(BNXT_RX_NTP_FLTR_SP_EVENT, &bp->sp_event))
11015 bnxt_cfg_ntp_filters(bp);
11016 if (test_and_clear_bit(BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT, &bp->sp_event))
11017 bnxt_hwrm_exec_fwd_req(bp);
11018 if (test_and_clear_bit(BNXT_PERIODIC_STATS_SP_EVENT, &bp->sp_event)) {
11019 bnxt_hwrm_port_qstats(bp, 0);
11020 bnxt_hwrm_port_qstats_ext(bp, 0);
11021 bnxt_accumulate_all_stats(bp);
11024 if (test_and_clear_bit(BNXT_LINK_CHNG_SP_EVENT, &bp->sp_event)) {
11027 mutex_lock(&bp->link_lock);
11028 if (test_and_clear_bit(BNXT_LINK_SPEED_CHNG_SP_EVENT,
11030 bnxt_hwrm_phy_qcaps(bp);
11032 rc = bnxt_update_link(bp, true);
11034 netdev_err(bp->dev, "SP task can't update link (rc: %x)\n",
11037 if (test_and_clear_bit(BNXT_LINK_CFG_CHANGE_SP_EVENT,
11039 bnxt_init_ethtool_link_settings(bp);
11040 mutex_unlock(&bp->link_lock);
11042 if (test_and_clear_bit(BNXT_UPDATE_PHY_SP_EVENT, &bp->sp_event)) {
11045 mutex_lock(&bp->link_lock);
11046 rc = bnxt_update_phy_setting(bp);
11047 mutex_unlock(&bp->link_lock);
11049 netdev_warn(bp->dev, "update phy settings retry failed\n");
11051 bp->link_info.phy_retry = false;
11052 netdev_info(bp->dev, "update phy settings retry succeeded\n");
11055 if (test_and_clear_bit(BNXT_HWRM_PORT_MODULE_SP_EVENT, &bp->sp_event)) {
11056 mutex_lock(&bp->link_lock);
11057 bnxt_get_port_module_status(bp);
11058 mutex_unlock(&bp->link_lock);
11061 if (test_and_clear_bit(BNXT_FLOW_STATS_SP_EVENT, &bp->sp_event))
11062 bnxt_tc_flow_stats_work(bp);
11064 if (test_and_clear_bit(BNXT_RING_COAL_NOW_SP_EVENT, &bp->sp_event))
11065 bnxt_chk_missed_irq(bp);
11067 /* These functions below will clear BNXT_STATE_IN_SP_TASK. They
11068 * must be the last functions to be called before exiting.
11070 if (test_and_clear_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event))
11071 bnxt_reset(bp, false);
11073 if (test_and_clear_bit(BNXT_RESET_TASK_SILENT_SP_EVENT, &bp->sp_event))
11074 bnxt_reset(bp, true);
11076 if (test_and_clear_bit(BNXT_RST_RING_SP_EVENT, &bp->sp_event))
11077 bnxt_rx_ring_reset(bp);
11079 if (test_and_clear_bit(BNXT_FW_RESET_NOTIFY_SP_EVENT, &bp->sp_event))
11080 bnxt_devlink_health_report(bp, BNXT_FW_RESET_NOTIFY_SP_EVENT);
11082 if (test_and_clear_bit(BNXT_FW_EXCEPTION_SP_EVENT, &bp->sp_event)) {
11083 if (!is_bnxt_fw_ok(bp))
11084 bnxt_devlink_health_report(bp,
11085 BNXT_FW_EXCEPTION_SP_EVENT);
11088 smp_mb__before_atomic();
11089 clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
11092 /* Under rtnl_lock */
11093 int bnxt_check_rings(struct bnxt *bp, int tx, int rx, bool sh, int tcs,
11096 int max_rx, max_tx, tx_sets = 1;
11097 int tx_rings_needed, stats;
11104 rc = bnxt_get_max_rings(bp, &max_rx, &max_tx, sh);
11111 tx_rings_needed = tx * tx_sets + tx_xdp;
11112 if (max_tx < tx_rings_needed)
11116 if ((bp->flags & (BNXT_FLAG_RFS | BNXT_FLAG_CHIP_P5)) == BNXT_FLAG_RFS)
11119 if (bp->flags & BNXT_FLAG_AGG_RINGS)
11121 cp = sh ? max_t(int, tx_rings_needed, rx) : tx_rings_needed + rx;
11123 if (BNXT_NEW_RM(bp)) {
11124 cp += bnxt_get_ulp_msix_num(bp);
11125 stats += bnxt_get_ulp_stat_ctxs(bp);
11127 return bnxt_hwrm_check_rings(bp, tx_rings_needed, rx_rings, rx, cp,
11131 static void bnxt_unmap_bars(struct bnxt *bp, struct pci_dev *pdev)
11134 pci_iounmap(pdev, bp->bar2);
11139 pci_iounmap(pdev, bp->bar1);
11144 pci_iounmap(pdev, bp->bar0);
11149 static void bnxt_cleanup_pci(struct bnxt *bp)
11151 bnxt_unmap_bars(bp, bp->pdev);
11152 pci_release_regions(bp->pdev);
11153 if (pci_is_enabled(bp->pdev))
11154 pci_disable_device(bp->pdev);
11157 static void bnxt_init_dflt_coal(struct bnxt *bp)
11159 struct bnxt_coal *coal;
11161 /* Tick values in micro seconds.
11162 * 1 coal_buf x bufs_per_record = 1 completion record.
11164 coal = &bp->rx_coal;
11165 coal->coal_ticks = 10;
11166 coal->coal_bufs = 30;
11167 coal->coal_ticks_irq = 1;
11168 coal->coal_bufs_irq = 2;
11169 coal->idle_thresh = 50;
11170 coal->bufs_per_record = 2;
11171 coal->budget = 64; /* NAPI budget */
11173 coal = &bp->tx_coal;
11174 coal->coal_ticks = 28;
11175 coal->coal_bufs = 30;
11176 coal->coal_ticks_irq = 2;
11177 coal->coal_bufs_irq = 2;
11178 coal->bufs_per_record = 1;
11180 bp->stats_coal_ticks = BNXT_DEF_STATS_COAL_TICKS;
11183 static int bnxt_fw_reset_via_optee(struct bnxt *bp)
11185 #ifdef CONFIG_TEE_BNXT_FW
11186 int rc = tee_bnxt_fw_load();
11189 netdev_err(bp->dev, "Failed FW reset via OP-TEE, rc=%d\n", rc);
11193 netdev_err(bp->dev, "OP-TEE not supported\n");
11198 static int bnxt_fw_init_one_p1(struct bnxt *bp)
11203 rc = bnxt_hwrm_ver_get(bp);
11204 bnxt_try_map_fw_health_reg(bp);
11206 if (bp->fw_health && bp->fw_health->status_reliable) {
11207 u32 sts = bnxt_fw_health_readl(bp, BNXT_FW_HEALTH_REG);
11209 netdev_err(bp->dev,
11210 "Firmware not responding, status: 0x%x\n",
11212 if (sts & FW_STATUS_REG_CRASHED_NO_MASTER) {
11213 netdev_warn(bp->dev, "Firmware recover via OP-TEE requested\n");
11214 rc = bnxt_fw_reset_via_optee(bp);
11216 rc = bnxt_hwrm_ver_get(bp);
11223 if (bp->fw_cap & BNXT_FW_CAP_KONG_MB_CHNL) {
11224 rc = bnxt_alloc_kong_hwrm_resources(bp);
11226 bp->fw_cap &= ~BNXT_FW_CAP_KONG_MB_CHNL;
11229 if ((bp->fw_cap & BNXT_FW_CAP_SHORT_CMD) ||
11230 bp->hwrm_max_ext_req_len > BNXT_HWRM_MAX_REQ_LEN) {
11231 rc = bnxt_alloc_hwrm_short_cmd_req(bp);
11235 bnxt_nvm_cfg_ver_get(bp);
11237 rc = bnxt_hwrm_func_reset(bp);
11241 bnxt_hwrm_fw_set_time(bp);
11245 static int bnxt_fw_init_one_p2(struct bnxt *bp)
11249 /* Get the MAX capabilities for this function */
11250 rc = bnxt_hwrm_func_qcaps(bp);
11252 netdev_err(bp->dev, "hwrm query capability failure rc: %x\n",
11257 rc = bnxt_hwrm_cfa_adv_flow_mgnt_qcaps(bp);
11259 netdev_warn(bp->dev, "hwrm query adv flow mgnt failure rc: %d\n",
11262 if (bnxt_alloc_fw_health(bp)) {
11263 netdev_warn(bp->dev, "no memory for firmware error recovery\n");
11265 rc = bnxt_hwrm_error_recovery_qcfg(bp);
11267 netdev_warn(bp->dev, "hwrm query error recovery failure rc: %d\n",
11271 rc = bnxt_hwrm_func_drv_rgtr(bp, NULL, 0, false);
11275 bnxt_hwrm_func_qcfg(bp);
11276 bnxt_hwrm_vnic_qcaps(bp);
11277 bnxt_hwrm_port_led_qcaps(bp);
11278 bnxt_ethtool_init(bp);
11283 static void bnxt_set_dflt_rss_hash_type(struct bnxt *bp)
11285 bp->flags &= ~BNXT_FLAG_UDP_RSS_CAP;
11286 bp->rss_hash_cfg = VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4 |
11287 VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4 |
11288 VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6 |
11289 VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6;
11290 if (BNXT_CHIP_P4_PLUS(bp) && bp->hwrm_spec_code >= 0x10501) {
11291 bp->flags |= BNXT_FLAG_UDP_RSS_CAP;
11292 bp->rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4 |
11293 VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6;
11297 static void bnxt_set_dflt_rfs(struct bnxt *bp)
11299 struct net_device *dev = bp->dev;
11301 dev->hw_features &= ~NETIF_F_NTUPLE;
11302 dev->features &= ~NETIF_F_NTUPLE;
11303 bp->flags &= ~BNXT_FLAG_RFS;
11304 if (bnxt_rfs_supported(bp)) {
11305 dev->hw_features |= NETIF_F_NTUPLE;
11306 if (bnxt_rfs_capable(bp)) {
11307 bp->flags |= BNXT_FLAG_RFS;
11308 dev->features |= NETIF_F_NTUPLE;
11313 static void bnxt_fw_init_one_p3(struct bnxt *bp)
11315 struct pci_dev *pdev = bp->pdev;
11317 bnxt_set_dflt_rss_hash_type(bp);
11318 bnxt_set_dflt_rfs(bp);
11320 bnxt_get_wol_settings(bp);
11321 if (bp->flags & BNXT_FLAG_WOL_CAP)
11322 device_set_wakeup_enable(&pdev->dev, bp->wol);
11324 device_set_wakeup_capable(&pdev->dev, false);
11326 bnxt_hwrm_set_cache_line_size(bp, cache_line_size());
11327 bnxt_hwrm_coal_params_qcaps(bp);
11330 static int bnxt_fw_init_one(struct bnxt *bp)
11334 rc = bnxt_fw_init_one_p1(bp);
11336 netdev_err(bp->dev, "Firmware init phase 1 failed\n");
11339 rc = bnxt_fw_init_one_p2(bp);
11341 netdev_err(bp->dev, "Firmware init phase 2 failed\n");
11344 rc = bnxt_approve_mac(bp, bp->dev->dev_addr, false);
11348 /* In case fw capabilities have changed, destroy the unneeded
11349 * reporters and create newly capable ones.
11351 bnxt_dl_fw_reporters_destroy(bp, false);
11352 bnxt_dl_fw_reporters_create(bp);
11353 bnxt_fw_init_one_p3(bp);
11357 static void bnxt_fw_reset_writel(struct bnxt *bp, int reg_idx)
11359 struct bnxt_fw_health *fw_health = bp->fw_health;
11360 u32 reg = fw_health->fw_reset_seq_regs[reg_idx];
11361 u32 val = fw_health->fw_reset_seq_vals[reg_idx];
11362 u32 reg_type, reg_off, delay_msecs;
11364 delay_msecs = fw_health->fw_reset_seq_delay_msec[reg_idx];
11365 reg_type = BNXT_FW_HEALTH_REG_TYPE(reg);
11366 reg_off = BNXT_FW_HEALTH_REG_OFF(reg);
11367 switch (reg_type) {
11368 case BNXT_FW_HEALTH_REG_TYPE_CFG:
11369 pci_write_config_dword(bp->pdev, reg_off, val);
11371 case BNXT_FW_HEALTH_REG_TYPE_GRC:
11372 writel(reg_off & BNXT_GRC_BASE_MASK,
11373 bp->bar0 + BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
11374 reg_off = (reg_off & BNXT_GRC_OFFSET_MASK) + 0x2000;
11376 case BNXT_FW_HEALTH_REG_TYPE_BAR0:
11377 writel(val, bp->bar0 + reg_off);
11379 case BNXT_FW_HEALTH_REG_TYPE_BAR1:
11380 writel(val, bp->bar1 + reg_off);
11384 pci_read_config_dword(bp->pdev, 0, &val);
11385 msleep(delay_msecs);
11389 static void bnxt_reset_all(struct bnxt *bp)
11391 struct bnxt_fw_health *fw_health = bp->fw_health;
11394 if (bp->fw_cap & BNXT_FW_CAP_ERR_RECOVER_RELOAD) {
11395 bnxt_fw_reset_via_optee(bp);
11396 bp->fw_reset_timestamp = jiffies;
11400 if (fw_health->flags & ERROR_RECOVERY_QCFG_RESP_FLAGS_HOST) {
11401 for (i = 0; i < fw_health->fw_reset_seq_cnt; i++)
11402 bnxt_fw_reset_writel(bp, i);
11403 } else if (fw_health->flags & ERROR_RECOVERY_QCFG_RESP_FLAGS_CO_CPU) {
11404 struct hwrm_fw_reset_input req = {0};
11406 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FW_RESET, -1, -1);
11407 req.resp_addr = cpu_to_le64(bp->hwrm_cmd_kong_resp_dma_addr);
11408 req.embedded_proc_type = FW_RESET_REQ_EMBEDDED_PROC_TYPE_CHIP;
11409 req.selfrst_status = FW_RESET_REQ_SELFRST_STATUS_SELFRSTASAP;
11410 req.flags = FW_RESET_REQ_FLAGS_RESET_GRACEFUL;
11411 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
11413 netdev_warn(bp->dev, "Unable to reset FW rc=%d\n", rc);
11415 bp->fw_reset_timestamp = jiffies;
11418 static void bnxt_fw_reset_task(struct work_struct *work)
11420 struct bnxt *bp = container_of(work, struct bnxt, fw_reset_task.work);
11423 if (!test_bit(BNXT_STATE_IN_FW_RESET, &bp->state)) {
11424 netdev_err(bp->dev, "bnxt_fw_reset_task() called when not in fw reset mode!\n");
11428 switch (bp->fw_reset_state) {
11429 case BNXT_FW_RESET_STATE_POLL_VF: {
11430 int n = bnxt_get_registered_vfs(bp);
11434 netdev_err(bp->dev, "Firmware reset aborted, subsequent func_qcfg cmd failed, rc = %d, %d msecs since reset timestamp\n",
11435 n, jiffies_to_msecs(jiffies -
11436 bp->fw_reset_timestamp));
11437 goto fw_reset_abort;
11438 } else if (n > 0) {
11439 if (time_after(jiffies, bp->fw_reset_timestamp +
11440 (bp->fw_reset_max_dsecs * HZ / 10))) {
11441 clear_bit(BNXT_STATE_IN_FW_RESET, &bp->state);
11442 bp->fw_reset_state = 0;
11443 netdev_err(bp->dev, "Firmware reset aborted, bnxt_get_registered_vfs() returns %d\n",
11447 bnxt_queue_fw_reset_work(bp, HZ / 10);
11450 bp->fw_reset_timestamp = jiffies;
11452 bnxt_fw_reset_close(bp);
11453 if (bp->fw_cap & BNXT_FW_CAP_ERR_RECOVER_RELOAD) {
11454 bp->fw_reset_state = BNXT_FW_RESET_STATE_POLL_FW_DOWN;
11457 bp->fw_reset_state = BNXT_FW_RESET_STATE_ENABLE_DEV;
11458 tmo = bp->fw_reset_min_dsecs * HZ / 10;
11461 bnxt_queue_fw_reset_work(bp, tmo);
11464 case BNXT_FW_RESET_STATE_POLL_FW_DOWN: {
11467 val = bnxt_fw_health_readl(bp, BNXT_FW_HEALTH_REG);
11468 if (!(val & BNXT_FW_STATUS_SHUTDOWN) &&
11469 !time_after(jiffies, bp->fw_reset_timestamp +
11470 (bp->fw_reset_max_dsecs * HZ / 10))) {
11471 bnxt_queue_fw_reset_work(bp, HZ / 5);
11475 if (!bp->fw_health->master) {
11476 u32 wait_dsecs = bp->fw_health->normal_func_wait_dsecs;
11478 bp->fw_reset_state = BNXT_FW_RESET_STATE_ENABLE_DEV;
11479 bnxt_queue_fw_reset_work(bp, wait_dsecs * HZ / 10);
11482 bp->fw_reset_state = BNXT_FW_RESET_STATE_RESET_FW;
11485 case BNXT_FW_RESET_STATE_RESET_FW:
11486 bnxt_reset_all(bp);
11487 bp->fw_reset_state = BNXT_FW_RESET_STATE_ENABLE_DEV;
11488 bnxt_queue_fw_reset_work(bp, bp->fw_reset_min_dsecs * HZ / 10);
11490 case BNXT_FW_RESET_STATE_ENABLE_DEV:
11491 if (test_bit(BNXT_STATE_FW_FATAL_COND, &bp->state)) {
11494 val = bnxt_fw_health_readl(bp,
11495 BNXT_FW_RESET_INPROG_REG);
11497 netdev_warn(bp->dev, "FW reset inprog %x after min wait time.\n",
11500 clear_bit(BNXT_STATE_FW_FATAL_COND, &bp->state);
11501 if (pci_enable_device(bp->pdev)) {
11502 netdev_err(bp->dev, "Cannot re-enable PCI device\n");
11503 goto fw_reset_abort;
11505 pci_set_master(bp->pdev);
11506 bp->fw_reset_state = BNXT_FW_RESET_STATE_POLL_FW;
11508 case BNXT_FW_RESET_STATE_POLL_FW:
11509 bp->hwrm_cmd_timeout = SHORT_HWRM_CMD_TIMEOUT;
11510 rc = __bnxt_hwrm_ver_get(bp, true);
11512 if (time_after(jiffies, bp->fw_reset_timestamp +
11513 (bp->fw_reset_max_dsecs * HZ / 10))) {
11514 netdev_err(bp->dev, "Firmware reset aborted\n");
11515 goto fw_reset_abort_status;
11517 bnxt_queue_fw_reset_work(bp, HZ / 5);
11520 bp->hwrm_cmd_timeout = DFLT_HWRM_CMD_TIMEOUT;
11521 bp->fw_reset_state = BNXT_FW_RESET_STATE_OPENING;
11523 case BNXT_FW_RESET_STATE_OPENING:
11524 while (!rtnl_trylock()) {
11525 bnxt_queue_fw_reset_work(bp, HZ / 10);
11528 rc = bnxt_open(bp->dev);
11530 netdev_err(bp->dev, "bnxt_open_nic() failed\n");
11531 clear_bit(BNXT_STATE_IN_FW_RESET, &bp->state);
11532 dev_close(bp->dev);
11535 bp->fw_reset_state = 0;
11536 /* Make sure fw_reset_state is 0 before clearing the flag */
11537 smp_mb__before_atomic();
11538 clear_bit(BNXT_STATE_IN_FW_RESET, &bp->state);
11539 bnxt_ulp_start(bp, rc);
11541 bnxt_reenable_sriov(bp);
11542 bnxt_dl_health_recovery_done(bp);
11543 bnxt_dl_health_status_update(bp, true);
11549 fw_reset_abort_status:
11550 if (bp->fw_health->status_reliable ||
11551 (bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY)) {
11552 u32 sts = bnxt_fw_health_readl(bp, BNXT_FW_HEALTH_REG);
11554 netdev_err(bp->dev, "fw_health_status 0x%x\n", sts);
11557 clear_bit(BNXT_STATE_IN_FW_RESET, &bp->state);
11558 if (bp->fw_reset_state != BNXT_FW_RESET_STATE_POLL_VF)
11559 bnxt_dl_health_status_update(bp, false);
11560 bp->fw_reset_state = 0;
11562 dev_close(bp->dev);
11566 static int bnxt_init_board(struct pci_dev *pdev, struct net_device *dev)
11569 struct bnxt *bp = netdev_priv(dev);
11571 SET_NETDEV_DEV(dev, &pdev->dev);
11573 /* enable device (incl. PCI PM wakeup), and bus-mastering */
11574 rc = pci_enable_device(pdev);
11576 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
11580 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
11581 dev_err(&pdev->dev,
11582 "Cannot find PCI device base address, aborting\n");
11584 goto init_err_disable;
11587 rc = pci_request_regions(pdev, DRV_MODULE_NAME);
11589 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n");
11590 goto init_err_disable;
11593 if (dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)) != 0 &&
11594 dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)) != 0) {
11595 dev_err(&pdev->dev, "System does not support DMA, aborting\n");
11597 goto init_err_release;
11600 pci_set_master(pdev);
11605 /* Doorbell BAR bp->bar1 is mapped after bnxt_fw_init_one_p2()
11606 * determines the BAR size.
11608 bp->bar0 = pci_ioremap_bar(pdev, 0);
11610 dev_err(&pdev->dev, "Cannot map device registers, aborting\n");
11612 goto init_err_release;
11615 bp->bar2 = pci_ioremap_bar(pdev, 4);
11617 dev_err(&pdev->dev, "Cannot map bar4 registers, aborting\n");
11619 goto init_err_release;
11622 pci_enable_pcie_error_reporting(pdev);
11624 INIT_WORK(&bp->sp_task, bnxt_sp_task);
11625 INIT_DELAYED_WORK(&bp->fw_reset_task, bnxt_fw_reset_task);
11627 spin_lock_init(&bp->ntp_fltr_lock);
11628 #if BITS_PER_LONG == 32
11629 spin_lock_init(&bp->db_lock);
11632 bp->rx_ring_size = BNXT_DEFAULT_RX_RING_SIZE;
11633 bp->tx_ring_size = BNXT_DEFAULT_TX_RING_SIZE;
11635 bnxt_init_dflt_coal(bp);
11637 timer_setup(&bp->timer, bnxt_timer, 0);
11638 bp->current_interval = BNXT_TIMER_INTERVAL;
11640 bp->vxlan_fw_dst_port_id = INVALID_HW_RING_ID;
11641 bp->nge_fw_dst_port_id = INVALID_HW_RING_ID;
11643 clear_bit(BNXT_STATE_OPEN, &bp->state);
11647 bnxt_unmap_bars(bp, pdev);
11648 pci_release_regions(pdev);
11651 pci_disable_device(pdev);
11657 /* rtnl_lock held */
11658 static int bnxt_change_mac_addr(struct net_device *dev, void *p)
11660 struct sockaddr *addr = p;
11661 struct bnxt *bp = netdev_priv(dev);
11664 if (!is_valid_ether_addr(addr->sa_data))
11665 return -EADDRNOTAVAIL;
11667 if (ether_addr_equal(addr->sa_data, dev->dev_addr))
11670 rc = bnxt_approve_mac(bp, addr->sa_data, true);
11674 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
11675 if (netif_running(dev)) {
11676 bnxt_close_nic(bp, false, false);
11677 rc = bnxt_open_nic(bp, false, false);
11683 /* rtnl_lock held */
11684 static int bnxt_change_mtu(struct net_device *dev, int new_mtu)
11686 struct bnxt *bp = netdev_priv(dev);
11688 if (netif_running(dev))
11689 bnxt_close_nic(bp, true, false);
11691 dev->mtu = new_mtu;
11692 bnxt_set_ring_params(bp);
11694 if (netif_running(dev))
11695 return bnxt_open_nic(bp, true, false);
11700 int bnxt_setup_mq_tc(struct net_device *dev, u8 tc)
11702 struct bnxt *bp = netdev_priv(dev);
11706 if (tc > bp->max_tc) {
11707 netdev_err(dev, "Too many traffic classes requested: %d. Max supported is %d.\n",
11712 if (netdev_get_num_tc(dev) == tc)
11715 if (bp->flags & BNXT_FLAG_SHARED_RINGS)
11718 rc = bnxt_check_rings(bp, bp->tx_nr_rings_per_tc, bp->rx_nr_rings,
11719 sh, tc, bp->tx_nr_rings_xdp);
11723 /* Needs to close the device and do hw resource re-allocations */
11724 if (netif_running(bp->dev))
11725 bnxt_close_nic(bp, true, false);
11728 bp->tx_nr_rings = bp->tx_nr_rings_per_tc * tc;
11729 netdev_set_num_tc(dev, tc);
11731 bp->tx_nr_rings = bp->tx_nr_rings_per_tc;
11732 netdev_reset_tc(dev);
11734 bp->tx_nr_rings += bp->tx_nr_rings_xdp;
11735 bp->cp_nr_rings = sh ? max_t(int, bp->tx_nr_rings, bp->rx_nr_rings) :
11736 bp->tx_nr_rings + bp->rx_nr_rings;
11738 if (netif_running(bp->dev))
11739 return bnxt_open_nic(bp, true, false);
11744 static int bnxt_setup_tc_block_cb(enum tc_setup_type type, void *type_data,
11747 struct bnxt *bp = cb_priv;
11749 if (!bnxt_tc_flower_enabled(bp) ||
11750 !tc_cls_can_offload_and_chain0(bp->dev, type_data))
11751 return -EOPNOTSUPP;
11754 case TC_SETUP_CLSFLOWER:
11755 return bnxt_tc_setup_flower(bp, bp->pf.fw_fid, type_data);
11757 return -EOPNOTSUPP;
11761 LIST_HEAD(bnxt_block_cb_list);
11763 static int bnxt_setup_tc(struct net_device *dev, enum tc_setup_type type,
11766 struct bnxt *bp = netdev_priv(dev);
11769 case TC_SETUP_BLOCK:
11770 return flow_block_cb_setup_simple(type_data,
11771 &bnxt_block_cb_list,
11772 bnxt_setup_tc_block_cb,
11774 case TC_SETUP_QDISC_MQPRIO: {
11775 struct tc_mqprio_qopt *mqprio = type_data;
11777 mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS;
11779 return bnxt_setup_mq_tc(dev, mqprio->num_tc);
11782 return -EOPNOTSUPP;
11786 #ifdef CONFIG_RFS_ACCEL
11787 static bool bnxt_fltr_match(struct bnxt_ntuple_filter *f1,
11788 struct bnxt_ntuple_filter *f2)
11790 struct flow_keys *keys1 = &f1->fkeys;
11791 struct flow_keys *keys2 = &f2->fkeys;
11793 if (keys1->basic.n_proto != keys2->basic.n_proto ||
11794 keys1->basic.ip_proto != keys2->basic.ip_proto)
11797 if (keys1->basic.n_proto == htons(ETH_P_IP)) {
11798 if (keys1->addrs.v4addrs.src != keys2->addrs.v4addrs.src ||
11799 keys1->addrs.v4addrs.dst != keys2->addrs.v4addrs.dst)
11802 if (memcmp(&keys1->addrs.v6addrs.src, &keys2->addrs.v6addrs.src,
11803 sizeof(keys1->addrs.v6addrs.src)) ||
11804 memcmp(&keys1->addrs.v6addrs.dst, &keys2->addrs.v6addrs.dst,
11805 sizeof(keys1->addrs.v6addrs.dst)))
11809 if (keys1->ports.ports == keys2->ports.ports &&
11810 keys1->control.flags == keys2->control.flags &&
11811 ether_addr_equal(f1->src_mac_addr, f2->src_mac_addr) &&
11812 ether_addr_equal(f1->dst_mac_addr, f2->dst_mac_addr))
11818 static int bnxt_rx_flow_steer(struct net_device *dev, const struct sk_buff *skb,
11819 u16 rxq_index, u32 flow_id)
11821 struct bnxt *bp = netdev_priv(dev);
11822 struct bnxt_ntuple_filter *fltr, *new_fltr;
11823 struct flow_keys *fkeys;
11824 struct ethhdr *eth = (struct ethhdr *)skb_mac_header(skb);
11825 int rc = 0, idx, bit_id, l2_idx = 0;
11826 struct hlist_head *head;
11829 if (!ether_addr_equal(dev->dev_addr, eth->h_dest)) {
11830 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
11833 netif_addr_lock_bh(dev);
11834 for (j = 0; j < vnic->uc_filter_count; j++, off += ETH_ALEN) {
11835 if (ether_addr_equal(eth->h_dest,
11836 vnic->uc_list + off)) {
11841 netif_addr_unlock_bh(dev);
11845 new_fltr = kzalloc(sizeof(*new_fltr), GFP_ATOMIC);
11849 fkeys = &new_fltr->fkeys;
11850 if (!skb_flow_dissect_flow_keys(skb, fkeys, 0)) {
11851 rc = -EPROTONOSUPPORT;
11855 if ((fkeys->basic.n_proto != htons(ETH_P_IP) &&
11856 fkeys->basic.n_proto != htons(ETH_P_IPV6)) ||
11857 ((fkeys->basic.ip_proto != IPPROTO_TCP) &&
11858 (fkeys->basic.ip_proto != IPPROTO_UDP))) {
11859 rc = -EPROTONOSUPPORT;
11862 if (fkeys->basic.n_proto == htons(ETH_P_IPV6) &&
11863 bp->hwrm_spec_code < 0x10601) {
11864 rc = -EPROTONOSUPPORT;
11867 flags = fkeys->control.flags;
11868 if (((flags & FLOW_DIS_ENCAPSULATION) &&
11869 bp->hwrm_spec_code < 0x10601) || (flags & FLOW_DIS_IS_FRAGMENT)) {
11870 rc = -EPROTONOSUPPORT;
11874 memcpy(new_fltr->dst_mac_addr, eth->h_dest, ETH_ALEN);
11875 memcpy(new_fltr->src_mac_addr, eth->h_source, ETH_ALEN);
11877 idx = skb_get_hash_raw(skb) & BNXT_NTP_FLTR_HASH_MASK;
11878 head = &bp->ntp_fltr_hash_tbl[idx];
11880 hlist_for_each_entry_rcu(fltr, head, hash) {
11881 if (bnxt_fltr_match(fltr, new_fltr)) {
11889 spin_lock_bh(&bp->ntp_fltr_lock);
11890 bit_id = bitmap_find_free_region(bp->ntp_fltr_bmap,
11891 BNXT_NTP_FLTR_MAX_FLTR, 0);
11893 spin_unlock_bh(&bp->ntp_fltr_lock);
11898 new_fltr->sw_id = (u16)bit_id;
11899 new_fltr->flow_id = flow_id;
11900 new_fltr->l2_fltr_idx = l2_idx;
11901 new_fltr->rxq = rxq_index;
11902 hlist_add_head_rcu(&new_fltr->hash, head);
11903 bp->ntp_fltr_count++;
11904 spin_unlock_bh(&bp->ntp_fltr_lock);
11906 set_bit(BNXT_RX_NTP_FLTR_SP_EVENT, &bp->sp_event);
11907 bnxt_queue_sp_work(bp);
11909 return new_fltr->sw_id;
11916 static void bnxt_cfg_ntp_filters(struct bnxt *bp)
11920 for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) {
11921 struct hlist_head *head;
11922 struct hlist_node *tmp;
11923 struct bnxt_ntuple_filter *fltr;
11926 head = &bp->ntp_fltr_hash_tbl[i];
11927 hlist_for_each_entry_safe(fltr, tmp, head, hash) {
11930 if (test_bit(BNXT_FLTR_VALID, &fltr->state)) {
11931 if (rps_may_expire_flow(bp->dev, fltr->rxq,
11934 bnxt_hwrm_cfa_ntuple_filter_free(bp,
11939 rc = bnxt_hwrm_cfa_ntuple_filter_alloc(bp,
11944 set_bit(BNXT_FLTR_VALID, &fltr->state);
11948 spin_lock_bh(&bp->ntp_fltr_lock);
11949 hlist_del_rcu(&fltr->hash);
11950 bp->ntp_fltr_count--;
11951 spin_unlock_bh(&bp->ntp_fltr_lock);
11953 clear_bit(fltr->sw_id, bp->ntp_fltr_bmap);
11958 if (test_and_clear_bit(BNXT_HWRM_PF_UNLOAD_SP_EVENT, &bp->sp_event))
11959 netdev_info(bp->dev, "Receive PF driver unload event!\n");
11964 static void bnxt_cfg_ntp_filters(struct bnxt *bp)
11968 #endif /* CONFIG_RFS_ACCEL */
11970 static int bnxt_udp_tunnel_sync(struct net_device *netdev, unsigned int table)
11972 struct bnxt *bp = netdev_priv(netdev);
11973 struct udp_tunnel_info ti;
11976 udp_tunnel_nic_get_port(netdev, table, 0, &ti);
11977 if (ti.type == UDP_TUNNEL_TYPE_VXLAN)
11978 cmd = TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN;
11980 cmd = TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE;
11983 return bnxt_hwrm_tunnel_dst_port_alloc(bp, ti.port, cmd);
11985 return bnxt_hwrm_tunnel_dst_port_free(bp, cmd);
11988 static const struct udp_tunnel_nic_info bnxt_udp_tunnels = {
11989 .sync_table = bnxt_udp_tunnel_sync,
11990 .flags = UDP_TUNNEL_NIC_INFO_MAY_SLEEP |
11991 UDP_TUNNEL_NIC_INFO_OPEN_ONLY,
11993 { .n_entries = 1, .tunnel_types = UDP_TUNNEL_TYPE_VXLAN, },
11994 { .n_entries = 1, .tunnel_types = UDP_TUNNEL_TYPE_GENEVE, },
11998 static int bnxt_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq,
11999 struct net_device *dev, u32 filter_mask,
12002 struct bnxt *bp = netdev_priv(dev);
12004 return ndo_dflt_bridge_getlink(skb, pid, seq, dev, bp->br_mode, 0, 0,
12005 nlflags, filter_mask, NULL);
12008 static int bnxt_bridge_setlink(struct net_device *dev, struct nlmsghdr *nlh,
12009 u16 flags, struct netlink_ext_ack *extack)
12011 struct bnxt *bp = netdev_priv(dev);
12012 struct nlattr *attr, *br_spec;
12015 if (bp->hwrm_spec_code < 0x10708 || !BNXT_SINGLE_PF(bp))
12016 return -EOPNOTSUPP;
12018 br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC);
12022 nla_for_each_nested(attr, br_spec, rem) {
12025 if (nla_type(attr) != IFLA_BRIDGE_MODE)
12028 if (nla_len(attr) < sizeof(mode))
12031 mode = nla_get_u16(attr);
12032 if (mode == bp->br_mode)
12035 rc = bnxt_hwrm_set_br_mode(bp, mode);
12037 bp->br_mode = mode;
12043 int bnxt_get_port_parent_id(struct net_device *dev,
12044 struct netdev_phys_item_id *ppid)
12046 struct bnxt *bp = netdev_priv(dev);
12048 if (bp->eswitch_mode != DEVLINK_ESWITCH_MODE_SWITCHDEV)
12049 return -EOPNOTSUPP;
12051 /* The PF and it's VF-reps only support the switchdev framework */
12052 if (!BNXT_PF(bp) || !(bp->flags & BNXT_FLAG_DSN_VALID))
12053 return -EOPNOTSUPP;
12055 ppid->id_len = sizeof(bp->dsn);
12056 memcpy(ppid->id, bp->dsn, ppid->id_len);
12061 static struct devlink_port *bnxt_get_devlink_port(struct net_device *dev)
12063 struct bnxt *bp = netdev_priv(dev);
12065 return &bp->dl_port;
12068 static const struct net_device_ops bnxt_netdev_ops = {
12069 .ndo_open = bnxt_open,
12070 .ndo_start_xmit = bnxt_start_xmit,
12071 .ndo_stop = bnxt_close,
12072 .ndo_get_stats64 = bnxt_get_stats64,
12073 .ndo_set_rx_mode = bnxt_set_rx_mode,
12074 .ndo_do_ioctl = bnxt_ioctl,
12075 .ndo_validate_addr = eth_validate_addr,
12076 .ndo_set_mac_address = bnxt_change_mac_addr,
12077 .ndo_change_mtu = bnxt_change_mtu,
12078 .ndo_fix_features = bnxt_fix_features,
12079 .ndo_set_features = bnxt_set_features,
12080 .ndo_tx_timeout = bnxt_tx_timeout,
12081 #ifdef CONFIG_BNXT_SRIOV
12082 .ndo_get_vf_config = bnxt_get_vf_config,
12083 .ndo_set_vf_mac = bnxt_set_vf_mac,
12084 .ndo_set_vf_vlan = bnxt_set_vf_vlan,
12085 .ndo_set_vf_rate = bnxt_set_vf_bw,
12086 .ndo_set_vf_link_state = bnxt_set_vf_link_state,
12087 .ndo_set_vf_spoofchk = bnxt_set_vf_spoofchk,
12088 .ndo_set_vf_trust = bnxt_set_vf_trust,
12090 .ndo_setup_tc = bnxt_setup_tc,
12091 #ifdef CONFIG_RFS_ACCEL
12092 .ndo_rx_flow_steer = bnxt_rx_flow_steer,
12094 .ndo_bpf = bnxt_xdp,
12095 .ndo_xdp_xmit = bnxt_xdp_xmit,
12096 .ndo_bridge_getlink = bnxt_bridge_getlink,
12097 .ndo_bridge_setlink = bnxt_bridge_setlink,
12098 .ndo_get_devlink_port = bnxt_get_devlink_port,
12101 static void bnxt_remove_one(struct pci_dev *pdev)
12103 struct net_device *dev = pci_get_drvdata(pdev);
12104 struct bnxt *bp = netdev_priv(dev);
12107 bnxt_sriov_disable(bp);
12110 devlink_port_type_clear(&bp->dl_port);
12111 pci_disable_pcie_error_reporting(pdev);
12112 unregister_netdev(dev);
12113 clear_bit(BNXT_STATE_IN_FW_RESET, &bp->state);
12114 /* Flush any pending tasks */
12115 cancel_work_sync(&bp->sp_task);
12116 cancel_delayed_work_sync(&bp->fw_reset_task);
12119 bnxt_dl_fw_reporters_destroy(bp, true);
12120 bnxt_dl_unregister(bp);
12121 bnxt_shutdown_tc(bp);
12123 bnxt_clear_int_mode(bp);
12124 bnxt_hwrm_func_drv_unrgtr(bp);
12125 bnxt_free_hwrm_resources(bp);
12126 bnxt_free_hwrm_short_cmd_req(bp);
12127 bnxt_ethtool_free(bp);
12131 kfree(bp->fw_health);
12132 bp->fw_health = NULL;
12133 bnxt_cleanup_pci(bp);
12134 bnxt_free_ctx_mem(bp);
12137 kfree(bp->rss_indir_tbl);
12138 bp->rss_indir_tbl = NULL;
12139 bnxt_free_port_stats(bp);
12143 static int bnxt_probe_phy(struct bnxt *bp, bool fw_dflt)
12146 struct bnxt_link_info *link_info = &bp->link_info;
12148 rc = bnxt_hwrm_phy_qcaps(bp);
12150 netdev_err(bp->dev, "Probe phy can't get phy capabilities (rc: %x)\n",
12157 rc = bnxt_update_link(bp, false);
12159 netdev_err(bp->dev, "Probe phy can't update link (rc: %x)\n",
12164 /* Older firmware does not have supported_auto_speeds, so assume
12165 * that all supported speeds can be autonegotiated.
12167 if (link_info->auto_link_speeds && !link_info->support_auto_speeds)
12168 link_info->support_auto_speeds = link_info->support_speeds;
12170 bnxt_init_ethtool_link_settings(bp);
12174 static int bnxt_get_max_irq(struct pci_dev *pdev)
12178 if (!pdev->msix_cap)
12181 pci_read_config_word(pdev, pdev->msix_cap + PCI_MSIX_FLAGS, &ctrl);
12182 return (ctrl & PCI_MSIX_FLAGS_QSIZE) + 1;
12185 static void _bnxt_get_max_rings(struct bnxt *bp, int *max_rx, int *max_tx,
12188 struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
12189 int max_ring_grps = 0, max_irq;
12191 *max_tx = hw_resc->max_tx_rings;
12192 *max_rx = hw_resc->max_rx_rings;
12193 *max_cp = bnxt_get_max_func_cp_rings_for_en(bp);
12194 max_irq = min_t(int, bnxt_get_max_func_irqs(bp) -
12195 bnxt_get_ulp_msix_num(bp),
12196 hw_resc->max_stat_ctxs - bnxt_get_ulp_stat_ctxs(bp));
12197 if (!(bp->flags & BNXT_FLAG_CHIP_P5))
12198 *max_cp = min_t(int, *max_cp, max_irq);
12199 max_ring_grps = hw_resc->max_hw_ring_grps;
12200 if (BNXT_CHIP_TYPE_NITRO_A0(bp) && BNXT_PF(bp)) {
12204 if (bp->flags & BNXT_FLAG_AGG_RINGS)
12206 if (bp->flags & BNXT_FLAG_CHIP_P5) {
12207 bnxt_trim_rings(bp, max_rx, max_tx, *max_cp, false);
12208 /* On P5 chips, max_cp output param should be available NQs */
12211 *max_rx = min_t(int, *max_rx, max_ring_grps);
12214 int bnxt_get_max_rings(struct bnxt *bp, int *max_rx, int *max_tx, bool shared)
12218 _bnxt_get_max_rings(bp, &rx, &tx, &cp);
12221 if (!rx || !tx || !cp)
12224 return bnxt_trim_rings(bp, max_rx, max_tx, cp, shared);
12227 static int bnxt_get_dflt_rings(struct bnxt *bp, int *max_rx, int *max_tx,
12232 rc = bnxt_get_max_rings(bp, max_rx, max_tx, shared);
12233 if (rc && (bp->flags & BNXT_FLAG_AGG_RINGS)) {
12234 /* Not enough rings, try disabling agg rings. */
12235 bp->flags &= ~BNXT_FLAG_AGG_RINGS;
12236 rc = bnxt_get_max_rings(bp, max_rx, max_tx, shared);
12238 /* set BNXT_FLAG_AGG_RINGS back for consistency */
12239 bp->flags |= BNXT_FLAG_AGG_RINGS;
12242 bp->flags |= BNXT_FLAG_NO_AGG_RINGS;
12243 bp->dev->hw_features &= ~(NETIF_F_LRO | NETIF_F_GRO_HW);
12244 bp->dev->features &= ~(NETIF_F_LRO | NETIF_F_GRO_HW);
12245 bnxt_set_ring_params(bp);
12248 if (bp->flags & BNXT_FLAG_ROCE_CAP) {
12249 int max_cp, max_stat, max_irq;
12251 /* Reserve minimum resources for RoCE */
12252 max_cp = bnxt_get_max_func_cp_rings(bp);
12253 max_stat = bnxt_get_max_func_stat_ctxs(bp);
12254 max_irq = bnxt_get_max_func_irqs(bp);
12255 if (max_cp <= BNXT_MIN_ROCE_CP_RINGS ||
12256 max_irq <= BNXT_MIN_ROCE_CP_RINGS ||
12257 max_stat <= BNXT_MIN_ROCE_STAT_CTXS)
12260 max_cp -= BNXT_MIN_ROCE_CP_RINGS;
12261 max_irq -= BNXT_MIN_ROCE_CP_RINGS;
12262 max_stat -= BNXT_MIN_ROCE_STAT_CTXS;
12263 max_cp = min_t(int, max_cp, max_irq);
12264 max_cp = min_t(int, max_cp, max_stat);
12265 rc = bnxt_trim_rings(bp, max_rx, max_tx, max_cp, shared);
12272 /* In initial default shared ring setting, each shared ring must have a
12275 static void bnxt_trim_dflt_sh_rings(struct bnxt *bp)
12277 bp->cp_nr_rings = min_t(int, bp->tx_nr_rings_per_tc, bp->rx_nr_rings);
12278 bp->rx_nr_rings = bp->cp_nr_rings;
12279 bp->tx_nr_rings_per_tc = bp->cp_nr_rings;
12280 bp->tx_nr_rings = bp->tx_nr_rings_per_tc;
12283 static int bnxt_set_dflt_rings(struct bnxt *bp, bool sh)
12285 int dflt_rings, max_rx_rings, max_tx_rings, rc;
12287 if (!bnxt_can_reserve_rings(bp))
12291 bp->flags |= BNXT_FLAG_SHARED_RINGS;
12292 dflt_rings = is_kdump_kernel() ? 1 : netif_get_num_default_rss_queues();
12293 /* Reduce default rings on multi-port cards so that total default
12294 * rings do not exceed CPU count.
12296 if (bp->port_count > 1) {
12298 max_t(int, num_online_cpus() / bp->port_count, 1);
12300 dflt_rings = min_t(int, dflt_rings, max_rings);
12302 rc = bnxt_get_dflt_rings(bp, &max_rx_rings, &max_tx_rings, sh);
12305 bp->rx_nr_rings = min_t(int, dflt_rings, max_rx_rings);
12306 bp->tx_nr_rings_per_tc = min_t(int, dflt_rings, max_tx_rings);
12308 bnxt_trim_dflt_sh_rings(bp);
12310 bp->cp_nr_rings = bp->tx_nr_rings_per_tc + bp->rx_nr_rings;
12311 bp->tx_nr_rings = bp->tx_nr_rings_per_tc;
12313 rc = __bnxt_reserve_rings(bp);
12315 netdev_warn(bp->dev, "Unable to reserve tx rings\n");
12316 bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
12318 bnxt_trim_dflt_sh_rings(bp);
12320 /* Rings may have been trimmed, re-reserve the trimmed rings. */
12321 if (bnxt_need_reserve_rings(bp)) {
12322 rc = __bnxt_reserve_rings(bp);
12324 netdev_warn(bp->dev, "2nd rings reservation failed.\n");
12325 bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
12327 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) {
12332 bp->tx_nr_rings = 0;
12333 bp->rx_nr_rings = 0;
12338 static int bnxt_init_dflt_ring_mode(struct bnxt *bp)
12342 if (bp->tx_nr_rings)
12345 bnxt_ulp_irq_stop(bp);
12346 bnxt_clear_int_mode(bp);
12347 rc = bnxt_set_dflt_rings(bp, true);
12349 netdev_err(bp->dev, "Not enough rings available.\n");
12350 goto init_dflt_ring_err;
12352 rc = bnxt_init_int_mode(bp);
12354 goto init_dflt_ring_err;
12356 bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
12357 if (bnxt_rfs_supported(bp) && bnxt_rfs_capable(bp)) {
12358 bp->flags |= BNXT_FLAG_RFS;
12359 bp->dev->features |= NETIF_F_NTUPLE;
12361 init_dflt_ring_err:
12362 bnxt_ulp_irq_restart(bp, rc);
12366 int bnxt_restore_pf_fw_resources(struct bnxt *bp)
12371 bnxt_hwrm_func_qcaps(bp);
12373 if (netif_running(bp->dev))
12374 __bnxt_close_nic(bp, true, false);
12376 bnxt_ulp_irq_stop(bp);
12377 bnxt_clear_int_mode(bp);
12378 rc = bnxt_init_int_mode(bp);
12379 bnxt_ulp_irq_restart(bp, rc);
12381 if (netif_running(bp->dev)) {
12383 dev_close(bp->dev);
12385 rc = bnxt_open_nic(bp, true, false);
12391 static int bnxt_init_mac_addr(struct bnxt *bp)
12396 memcpy(bp->dev->dev_addr, bp->pf.mac_addr, ETH_ALEN);
12398 #ifdef CONFIG_BNXT_SRIOV
12399 struct bnxt_vf_info *vf = &bp->vf;
12400 bool strict_approval = true;
12402 if (is_valid_ether_addr(vf->mac_addr)) {
12403 /* overwrite netdev dev_addr with admin VF MAC */
12404 memcpy(bp->dev->dev_addr, vf->mac_addr, ETH_ALEN);
12405 /* Older PF driver or firmware may not approve this
12408 strict_approval = false;
12410 eth_hw_addr_random(bp->dev);
12412 rc = bnxt_approve_mac(bp, bp->dev->dev_addr, strict_approval);
12418 #define BNXT_VPD_LEN 512
12419 static void bnxt_vpd_read_info(struct bnxt *bp)
12421 struct pci_dev *pdev = bp->pdev;
12422 int i, len, pos, ro_size, size;
12426 vpd_data = kmalloc(BNXT_VPD_LEN, GFP_KERNEL);
12430 vpd_size = pci_read_vpd(pdev, 0, BNXT_VPD_LEN, vpd_data);
12431 if (vpd_size <= 0) {
12432 netdev_err(bp->dev, "Unable to read VPD\n");
12436 i = pci_vpd_find_tag(vpd_data, 0, vpd_size, PCI_VPD_LRDT_RO_DATA);
12438 netdev_err(bp->dev, "VPD READ-Only not found\n");
12442 ro_size = pci_vpd_lrdt_size(&vpd_data[i]);
12443 i += PCI_VPD_LRDT_TAG_SIZE;
12444 if (i + ro_size > vpd_size)
12447 pos = pci_vpd_find_info_keyword(vpd_data, i, ro_size,
12448 PCI_VPD_RO_KEYWORD_PARTNO);
12452 len = pci_vpd_info_field_size(&vpd_data[pos]);
12453 pos += PCI_VPD_INFO_FLD_HDR_SIZE;
12454 if (len + pos > vpd_size)
12457 size = min(len, BNXT_VPD_FLD_LEN - 1);
12458 memcpy(bp->board_partno, &vpd_data[pos], size);
12461 pos = pci_vpd_find_info_keyword(vpd_data, i, ro_size,
12462 PCI_VPD_RO_KEYWORD_SERIALNO);
12466 len = pci_vpd_info_field_size(&vpd_data[pos]);
12467 pos += PCI_VPD_INFO_FLD_HDR_SIZE;
12468 if (len + pos > vpd_size)
12471 size = min(len, BNXT_VPD_FLD_LEN - 1);
12472 memcpy(bp->board_serialno, &vpd_data[pos], size);
12477 static int bnxt_pcie_dsn_get(struct bnxt *bp, u8 dsn[])
12479 struct pci_dev *pdev = bp->pdev;
12482 qword = pci_get_dsn(pdev);
12484 netdev_info(bp->dev, "Unable to read adapter's DSN\n");
12485 return -EOPNOTSUPP;
12488 put_unaligned_le64(qword, dsn);
12490 bp->flags |= BNXT_FLAG_DSN_VALID;
12494 static int bnxt_map_db_bar(struct bnxt *bp)
12498 bp->bar1 = pci_iomap(bp->pdev, 2, bp->db_size);
12504 static int bnxt_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
12506 struct net_device *dev;
12510 if (pci_is_bridge(pdev))
12513 /* Clear any pending DMA transactions from crash kernel
12514 * while loading driver in capture kernel.
12516 if (is_kdump_kernel()) {
12517 pci_clear_master(pdev);
12521 max_irqs = bnxt_get_max_irq(pdev);
12522 dev = alloc_etherdev_mq(sizeof(*bp), max_irqs);
12526 bp = netdev_priv(dev);
12527 bp->msg_enable = BNXT_DEF_MSG_ENABLE;
12528 bnxt_set_max_func_irqs(bp, max_irqs);
12530 if (bnxt_vf_pciid(ent->driver_data))
12531 bp->flags |= BNXT_FLAG_VF;
12533 if (pdev->msix_cap)
12534 bp->flags |= BNXT_FLAG_MSIX_CAP;
12536 rc = bnxt_init_board(pdev, dev);
12538 goto init_err_free;
12540 dev->netdev_ops = &bnxt_netdev_ops;
12541 dev->watchdog_timeo = BNXT_TX_TIMEOUT;
12542 dev->ethtool_ops = &bnxt_ethtool_ops;
12543 pci_set_drvdata(pdev, dev);
12546 bnxt_vpd_read_info(bp);
12548 rc = bnxt_alloc_hwrm_resources(bp);
12550 goto init_err_pci_clean;
12552 mutex_init(&bp->hwrm_cmd_lock);
12553 mutex_init(&bp->link_lock);
12555 rc = bnxt_fw_init_one_p1(bp);
12557 goto init_err_pci_clean;
12559 if (BNXT_CHIP_P5(bp)) {
12560 bp->flags |= BNXT_FLAG_CHIP_P5;
12561 if (BNXT_CHIP_SR2(bp))
12562 bp->flags |= BNXT_FLAG_CHIP_SR2;
12565 rc = bnxt_alloc_rss_indir_tbl(bp);
12567 goto init_err_pci_clean;
12569 rc = bnxt_fw_init_one_p2(bp);
12571 goto init_err_pci_clean;
12573 rc = bnxt_map_db_bar(bp);
12575 dev_err(&pdev->dev, "Cannot map doorbell BAR rc = %d, aborting\n",
12577 goto init_err_pci_clean;
12580 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG |
12581 NETIF_F_TSO | NETIF_F_TSO6 |
12582 NETIF_F_GSO_UDP_TUNNEL | NETIF_F_GSO_GRE |
12583 NETIF_F_GSO_IPXIP4 |
12584 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_GSO_GRE_CSUM |
12585 NETIF_F_GSO_PARTIAL | NETIF_F_RXHASH |
12586 NETIF_F_RXCSUM | NETIF_F_GRO;
12588 if (BNXT_SUPPORTS_TPA(bp))
12589 dev->hw_features |= NETIF_F_LRO;
12591 dev->hw_enc_features =
12592 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG |
12593 NETIF_F_TSO | NETIF_F_TSO6 |
12594 NETIF_F_GSO_UDP_TUNNEL | NETIF_F_GSO_GRE |
12595 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_GSO_GRE_CSUM |
12596 NETIF_F_GSO_IPXIP4 | NETIF_F_GSO_PARTIAL;
12597 dev->udp_tunnel_nic_info = &bnxt_udp_tunnels;
12599 dev->gso_partial_features = NETIF_F_GSO_UDP_TUNNEL_CSUM |
12600 NETIF_F_GSO_GRE_CSUM;
12601 dev->vlan_features = dev->hw_features | NETIF_F_HIGHDMA;
12602 if (bp->fw_cap & BNXT_FW_CAP_VLAN_RX_STRIP)
12603 dev->hw_features |= BNXT_HW_FEATURE_VLAN_ALL_RX;
12604 if (bp->fw_cap & BNXT_FW_CAP_VLAN_TX_INSERT)
12605 dev->hw_features |= BNXT_HW_FEATURE_VLAN_ALL_TX;
12606 if (BNXT_SUPPORTS_TPA(bp))
12607 dev->hw_features |= NETIF_F_GRO_HW;
12608 dev->features |= dev->hw_features | NETIF_F_HIGHDMA;
12609 if (dev->features & NETIF_F_GRO_HW)
12610 dev->features &= ~NETIF_F_LRO;
12611 dev->priv_flags |= IFF_UNICAST_FLT;
12613 #ifdef CONFIG_BNXT_SRIOV
12614 init_waitqueue_head(&bp->sriov_cfg_wait);
12615 mutex_init(&bp->sriov_lock);
12617 if (BNXT_SUPPORTS_TPA(bp)) {
12618 bp->gro_func = bnxt_gro_func_5730x;
12619 if (BNXT_CHIP_P4(bp))
12620 bp->gro_func = bnxt_gro_func_5731x;
12621 else if (BNXT_CHIP_P5(bp))
12622 bp->gro_func = bnxt_gro_func_5750x;
12624 if (!BNXT_CHIP_P4_PLUS(bp))
12625 bp->flags |= BNXT_FLAG_DOUBLE_DB;
12627 bp->ulp_probe = bnxt_ulp_probe;
12629 rc = bnxt_init_mac_addr(bp);
12631 dev_err(&pdev->dev, "Unable to initialize mac address.\n");
12632 rc = -EADDRNOTAVAIL;
12633 goto init_err_pci_clean;
12637 /* Read the adapter's DSN to use as the eswitch switch_id */
12638 rc = bnxt_pcie_dsn_get(bp, bp->dsn);
12641 /* MTU range: 60 - FW defined max */
12642 dev->min_mtu = ETH_ZLEN;
12643 dev->max_mtu = bp->max_mtu;
12645 rc = bnxt_probe_phy(bp, true);
12647 goto init_err_pci_clean;
12649 bnxt_set_rx_skb_mode(bp, false);
12650 bnxt_set_tpa_flags(bp);
12651 bnxt_set_ring_params(bp);
12652 rc = bnxt_set_dflt_rings(bp, true);
12654 netdev_err(bp->dev, "Not enough rings available.\n");
12656 goto init_err_pci_clean;
12659 bnxt_fw_init_one_p3(bp);
12661 if (dev->hw_features & BNXT_HW_FEATURE_VLAN_ALL_RX)
12662 bp->flags |= BNXT_FLAG_STRIP_VLAN;
12664 rc = bnxt_init_int_mode(bp);
12666 goto init_err_pci_clean;
12668 /* No TC has been set yet and rings may have been trimmed due to
12669 * limited MSIX, so we re-initialize the TX rings per TC.
12671 bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
12676 create_singlethread_workqueue("bnxt_pf_wq");
12678 dev_err(&pdev->dev, "Unable to create workqueue.\n");
12680 goto init_err_pci_clean;
12683 rc = bnxt_init_tc(bp);
12685 netdev_err(dev, "Failed to initialize TC flower offload, err = %d.\n",
12689 bnxt_dl_register(bp);
12691 rc = register_netdev(dev);
12693 goto init_err_cleanup;
12696 devlink_port_type_eth_set(&bp->dl_port, bp->dev);
12697 bnxt_dl_fw_reporters_create(bp);
12699 netdev_info(dev, "%s found at mem %lx, node addr %pM\n",
12700 board_info[ent->driver_data].name,
12701 (long)pci_resource_start(pdev, 0), dev->dev_addr);
12702 pcie_print_link_status(pdev);
12704 pci_save_state(pdev);
12708 bnxt_dl_unregister(bp);
12709 bnxt_shutdown_tc(bp);
12710 bnxt_clear_int_mode(bp);
12712 init_err_pci_clean:
12713 bnxt_hwrm_func_drv_unrgtr(bp);
12714 bnxt_free_hwrm_short_cmd_req(bp);
12715 bnxt_free_hwrm_resources(bp);
12716 kfree(bp->fw_health);
12717 bp->fw_health = NULL;
12718 bnxt_cleanup_pci(bp);
12719 bnxt_free_ctx_mem(bp);
12722 kfree(bp->rss_indir_tbl);
12723 bp->rss_indir_tbl = NULL;
12730 static void bnxt_shutdown(struct pci_dev *pdev)
12732 struct net_device *dev = pci_get_drvdata(pdev);
12739 bp = netdev_priv(dev);
12741 goto shutdown_exit;
12743 if (netif_running(dev))
12746 bnxt_ulp_shutdown(bp);
12747 bnxt_clear_int_mode(bp);
12748 pci_disable_device(pdev);
12750 if (system_state == SYSTEM_POWER_OFF) {
12751 pci_wake_from_d3(pdev, bp->wol);
12752 pci_set_power_state(pdev, PCI_D3hot);
12759 #ifdef CONFIG_PM_SLEEP
12760 static int bnxt_suspend(struct device *device)
12762 struct net_device *dev = dev_get_drvdata(device);
12763 struct bnxt *bp = netdev_priv(dev);
12768 if (netif_running(dev)) {
12769 netif_device_detach(dev);
12770 rc = bnxt_close(dev);
12772 bnxt_hwrm_func_drv_unrgtr(bp);
12773 pci_disable_device(bp->pdev);
12774 bnxt_free_ctx_mem(bp);
12781 static int bnxt_resume(struct device *device)
12783 struct net_device *dev = dev_get_drvdata(device);
12784 struct bnxt *bp = netdev_priv(dev);
12788 rc = pci_enable_device(bp->pdev);
12790 netdev_err(dev, "Cannot re-enable PCI device during resume, err = %d\n",
12794 pci_set_master(bp->pdev);
12795 if (bnxt_hwrm_ver_get(bp)) {
12799 rc = bnxt_hwrm_func_reset(bp);
12805 rc = bnxt_hwrm_func_qcaps(bp);
12809 if (bnxt_hwrm_func_drv_rgtr(bp, NULL, 0, false)) {
12814 bnxt_get_wol_settings(bp);
12815 if (netif_running(dev)) {
12816 rc = bnxt_open(dev);
12818 netif_device_attach(dev);
12822 bnxt_ulp_start(bp, rc);
12824 bnxt_reenable_sriov(bp);
12829 static SIMPLE_DEV_PM_OPS(bnxt_pm_ops, bnxt_suspend, bnxt_resume);
12830 #define BNXT_PM_OPS (&bnxt_pm_ops)
12834 #define BNXT_PM_OPS NULL
12836 #endif /* CONFIG_PM_SLEEP */
12839 * bnxt_io_error_detected - called when PCI error is detected
12840 * @pdev: Pointer to PCI device
12841 * @state: The current pci connection state
12843 * This function is called after a PCI bus error affecting
12844 * this device has been detected.
12846 static pci_ers_result_t bnxt_io_error_detected(struct pci_dev *pdev,
12847 pci_channel_state_t state)
12849 struct net_device *netdev = pci_get_drvdata(pdev);
12850 struct bnxt *bp = netdev_priv(netdev);
12852 netdev_info(netdev, "PCI I/O error detected\n");
12855 netif_device_detach(netdev);
12859 if (state == pci_channel_io_perm_failure) {
12861 return PCI_ERS_RESULT_DISCONNECT;
12864 if (state == pci_channel_io_frozen)
12865 set_bit(BNXT_STATE_PCI_CHANNEL_IO_FROZEN, &bp->state);
12867 if (netif_running(netdev))
12868 bnxt_close(netdev);
12870 pci_disable_device(pdev);
12871 bnxt_free_ctx_mem(bp);
12876 /* Request a slot slot reset. */
12877 return PCI_ERS_RESULT_NEED_RESET;
12881 * bnxt_io_slot_reset - called after the pci bus has been reset.
12882 * @pdev: Pointer to PCI device
12884 * Restart the card from scratch, as if from a cold-boot.
12885 * At this point, the card has exprienced a hard reset,
12886 * followed by fixups by BIOS, and has its config space
12887 * set up identically to what it was at cold boot.
12889 static pci_ers_result_t bnxt_io_slot_reset(struct pci_dev *pdev)
12891 pci_ers_result_t result = PCI_ERS_RESULT_DISCONNECT;
12892 struct net_device *netdev = pci_get_drvdata(pdev);
12893 struct bnxt *bp = netdev_priv(netdev);
12896 netdev_info(bp->dev, "PCI Slot Reset\n");
12900 if (pci_enable_device(pdev)) {
12901 dev_err(&pdev->dev,
12902 "Cannot re-enable PCI device after reset.\n");
12904 pci_set_master(pdev);
12905 /* Upon fatal error, our device internal logic that latches to
12906 * BAR value is getting reset and will restore only upon
12907 * rewritting the BARs.
12909 * As pci_restore_state() does not re-write the BARs if the
12910 * value is same as saved value earlier, driver needs to
12911 * write the BARs to 0 to force restore, in case of fatal error.
12913 if (test_and_clear_bit(BNXT_STATE_PCI_CHANNEL_IO_FROZEN,
12915 for (off = PCI_BASE_ADDRESS_0;
12916 off <= PCI_BASE_ADDRESS_5; off += 4)
12917 pci_write_config_dword(bp->pdev, off, 0);
12919 pci_restore_state(pdev);
12920 pci_save_state(pdev);
12922 err = bnxt_hwrm_func_reset(bp);
12924 result = PCI_ERS_RESULT_RECOVERED;
12933 * bnxt_io_resume - called when traffic can start flowing again.
12934 * @pdev: Pointer to PCI device
12936 * This callback is called when the error recovery driver tells
12937 * us that its OK to resume normal operation.
12939 static void bnxt_io_resume(struct pci_dev *pdev)
12941 struct net_device *netdev = pci_get_drvdata(pdev);
12942 struct bnxt *bp = netdev_priv(netdev);
12945 netdev_info(bp->dev, "PCI Slot Resume\n");
12948 err = bnxt_hwrm_func_qcaps(bp);
12949 if (!err && netif_running(netdev))
12950 err = bnxt_open(netdev);
12952 bnxt_ulp_start(bp, err);
12954 bnxt_reenable_sriov(bp);
12955 netif_device_attach(netdev);
12961 static const struct pci_error_handlers bnxt_err_handler = {
12962 .error_detected = bnxt_io_error_detected,
12963 .slot_reset = bnxt_io_slot_reset,
12964 .resume = bnxt_io_resume
12967 static struct pci_driver bnxt_pci_driver = {
12968 .name = DRV_MODULE_NAME,
12969 .id_table = bnxt_pci_tbl,
12970 .probe = bnxt_init_one,
12971 .remove = bnxt_remove_one,
12972 .shutdown = bnxt_shutdown,
12973 .driver.pm = BNXT_PM_OPS,
12974 .err_handler = &bnxt_err_handler,
12975 #if defined(CONFIG_BNXT_SRIOV)
12976 .sriov_configure = bnxt_sriov_configure,
12980 static int __init bnxt_init(void)
12983 return pci_register_driver(&bnxt_pci_driver);
12986 static void __exit bnxt_exit(void)
12988 pci_unregister_driver(&bnxt_pci_driver);
12990 destroy_workqueue(bnxt_pf_wq);
12994 module_init(bnxt_init);
12995 module_exit(bnxt_exit);