1 /* Broadcom NetXtreme-C/E network driver.
3 * Copyright (c) 2014-2016 Broadcom Corporation
4 * Copyright (c) 2016-2017 Broadcom Limited
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation.
11 #include <linux/module.h>
13 #include <linux/stringify.h>
14 #include <linux/kernel.h>
15 #include <linux/timer.h>
16 #include <linux/errno.h>
17 #include <linux/ioport.h>
18 #include <linux/slab.h>
19 #include <linux/vmalloc.h>
20 #include <linux/interrupt.h>
21 #include <linux/pci.h>
22 #include <linux/netdevice.h>
23 #include <linux/etherdevice.h>
24 #include <linux/skbuff.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/bitops.h>
28 #include <linux/irq.h>
29 #include <linux/delay.h>
30 #include <asm/byteorder.h>
32 #include <linux/time.h>
33 #include <linux/mii.h>
35 #include <linux/if_vlan.h>
36 #include <linux/if_bridge.h>
37 #include <linux/rtc.h>
38 #include <linux/bpf.h>
42 #include <net/checksum.h>
43 #include <net/ip6_checksum.h>
44 #include <net/udp_tunnel.h>
45 #include <linux/workqueue.h>
46 #include <linux/prefetch.h>
47 #include <linux/cache.h>
48 #include <linux/log2.h>
49 #include <linux/aer.h>
50 #include <linux/bitmap.h>
51 #include <linux/cpu_rmap.h>
52 #include <linux/cpumask.h>
53 #include <net/pkt_cls.h>
58 #include "bnxt_sriov.h"
59 #include "bnxt_ethtool.h"
64 #include "bnxt_devlink.h"
66 #define BNXT_TX_TIMEOUT (5 * HZ)
68 static const char version[] =
69 "Broadcom NetXtreme-C/E driver " DRV_MODULE_NAME " v" DRV_MODULE_VERSION "\n";
71 MODULE_LICENSE("GPL");
72 MODULE_DESCRIPTION("Broadcom BCM573xx network driver");
73 MODULE_VERSION(DRV_MODULE_VERSION);
75 #define BNXT_RX_OFFSET (NET_SKB_PAD + NET_IP_ALIGN)
76 #define BNXT_RX_DMA_OFFSET NET_SKB_PAD
77 #define BNXT_RX_COPY_THRESH 256
79 #define BNXT_TX_PUSH_THRESH 164
118 /* indexed by enum above */
119 static const struct {
122 [BCM57301] = { "Broadcom BCM57301 NetXtreme-C 10Gb Ethernet" },
123 [BCM57302] = { "Broadcom BCM57302 NetXtreme-C 10Gb/25Gb Ethernet" },
124 [BCM57304] = { "Broadcom BCM57304 NetXtreme-C 10Gb/25Gb/40Gb/50Gb Ethernet" },
125 [BCM57417_NPAR] = { "Broadcom BCM57417 NetXtreme-E Ethernet Partition" },
126 [BCM58700] = { "Broadcom BCM58700 Nitro 1Gb/2.5Gb/10Gb Ethernet" },
127 [BCM57311] = { "Broadcom BCM57311 NetXtreme-C 10Gb Ethernet" },
128 [BCM57312] = { "Broadcom BCM57312 NetXtreme-C 10Gb/25Gb Ethernet" },
129 [BCM57402] = { "Broadcom BCM57402 NetXtreme-E 10Gb Ethernet" },
130 [BCM57404] = { "Broadcom BCM57404 NetXtreme-E 10Gb/25Gb Ethernet" },
131 [BCM57406] = { "Broadcom BCM57406 NetXtreme-E 10GBase-T Ethernet" },
132 [BCM57402_NPAR] = { "Broadcom BCM57402 NetXtreme-E Ethernet Partition" },
133 [BCM57407] = { "Broadcom BCM57407 NetXtreme-E 10GBase-T Ethernet" },
134 [BCM57412] = { "Broadcom BCM57412 NetXtreme-E 10Gb Ethernet" },
135 [BCM57414] = { "Broadcom BCM57414 NetXtreme-E 10Gb/25Gb Ethernet" },
136 [BCM57416] = { "Broadcom BCM57416 NetXtreme-E 10GBase-T Ethernet" },
137 [BCM57417] = { "Broadcom BCM57417 NetXtreme-E 10GBase-T Ethernet" },
138 [BCM57412_NPAR] = { "Broadcom BCM57412 NetXtreme-E Ethernet Partition" },
139 [BCM57314] = { "Broadcom BCM57314 NetXtreme-C 10Gb/25Gb/40Gb/50Gb Ethernet" },
140 [BCM57417_SFP] = { "Broadcom BCM57417 NetXtreme-E 10Gb/25Gb Ethernet" },
141 [BCM57416_SFP] = { "Broadcom BCM57416 NetXtreme-E 10Gb Ethernet" },
142 [BCM57404_NPAR] = { "Broadcom BCM57404 NetXtreme-E Ethernet Partition" },
143 [BCM57406_NPAR] = { "Broadcom BCM57406 NetXtreme-E Ethernet Partition" },
144 [BCM57407_SFP] = { "Broadcom BCM57407 NetXtreme-E 25Gb Ethernet" },
145 [BCM57407_NPAR] = { "Broadcom BCM57407 NetXtreme-E Ethernet Partition" },
146 [BCM57414_NPAR] = { "Broadcom BCM57414 NetXtreme-E Ethernet Partition" },
147 [BCM57416_NPAR] = { "Broadcom BCM57416 NetXtreme-E Ethernet Partition" },
148 [BCM57452] = { "Broadcom BCM57452 NetXtreme-E 10Gb/25Gb/40Gb/50Gb Ethernet" },
149 [BCM57454] = { "Broadcom BCM57454 NetXtreme-E 10Gb/25Gb/40Gb/50Gb/100Gb Ethernet" },
150 [BCM58802] = { "Broadcom BCM58802 NetXtreme-S 10Gb/25Gb/40Gb/50Gb Ethernet" },
151 [BCM58804] = { "Broadcom BCM58804 NetXtreme-S 10Gb/25Gb/40Gb/50Gb/100Gb Ethernet" },
152 [BCM58808] = { "Broadcom BCM58808 NetXtreme-S 10Gb/25Gb/40Gb/50Gb/100Gb Ethernet" },
153 [NETXTREME_E_VF] = { "Broadcom NetXtreme-E Ethernet Virtual Function" },
154 [NETXTREME_C_VF] = { "Broadcom NetXtreme-C Ethernet Virtual Function" },
155 [NETXTREME_S_VF] = { "Broadcom NetXtreme-S Ethernet Virtual Function" },
158 static const struct pci_device_id bnxt_pci_tbl[] = {
159 { PCI_VDEVICE(BROADCOM, 0x1614), .driver_data = BCM57454 },
160 { PCI_VDEVICE(BROADCOM, 0x16c0), .driver_data = BCM57417_NPAR },
161 { PCI_VDEVICE(BROADCOM, 0x16c8), .driver_data = BCM57301 },
162 { PCI_VDEVICE(BROADCOM, 0x16c9), .driver_data = BCM57302 },
163 { PCI_VDEVICE(BROADCOM, 0x16ca), .driver_data = BCM57304 },
164 { PCI_VDEVICE(BROADCOM, 0x16cc), .driver_data = BCM57417_NPAR },
165 { PCI_VDEVICE(BROADCOM, 0x16cd), .driver_data = BCM58700 },
166 { PCI_VDEVICE(BROADCOM, 0x16ce), .driver_data = BCM57311 },
167 { PCI_VDEVICE(BROADCOM, 0x16cf), .driver_data = BCM57312 },
168 { PCI_VDEVICE(BROADCOM, 0x16d0), .driver_data = BCM57402 },
169 { PCI_VDEVICE(BROADCOM, 0x16d1), .driver_data = BCM57404 },
170 { PCI_VDEVICE(BROADCOM, 0x16d2), .driver_data = BCM57406 },
171 { PCI_VDEVICE(BROADCOM, 0x16d4), .driver_data = BCM57402_NPAR },
172 { PCI_VDEVICE(BROADCOM, 0x16d5), .driver_data = BCM57407 },
173 { PCI_VDEVICE(BROADCOM, 0x16d6), .driver_data = BCM57412 },
174 { PCI_VDEVICE(BROADCOM, 0x16d7), .driver_data = BCM57414 },
175 { PCI_VDEVICE(BROADCOM, 0x16d8), .driver_data = BCM57416 },
176 { PCI_VDEVICE(BROADCOM, 0x16d9), .driver_data = BCM57417 },
177 { PCI_VDEVICE(BROADCOM, 0x16de), .driver_data = BCM57412_NPAR },
178 { PCI_VDEVICE(BROADCOM, 0x16df), .driver_data = BCM57314 },
179 { PCI_VDEVICE(BROADCOM, 0x16e2), .driver_data = BCM57417_SFP },
180 { PCI_VDEVICE(BROADCOM, 0x16e3), .driver_data = BCM57416_SFP },
181 { PCI_VDEVICE(BROADCOM, 0x16e7), .driver_data = BCM57404_NPAR },
182 { PCI_VDEVICE(BROADCOM, 0x16e8), .driver_data = BCM57406_NPAR },
183 { PCI_VDEVICE(BROADCOM, 0x16e9), .driver_data = BCM57407_SFP },
184 { PCI_VDEVICE(BROADCOM, 0x16ea), .driver_data = BCM57407_NPAR },
185 { PCI_VDEVICE(BROADCOM, 0x16eb), .driver_data = BCM57412_NPAR },
186 { PCI_VDEVICE(BROADCOM, 0x16ec), .driver_data = BCM57414_NPAR },
187 { PCI_VDEVICE(BROADCOM, 0x16ed), .driver_data = BCM57414_NPAR },
188 { PCI_VDEVICE(BROADCOM, 0x16ee), .driver_data = BCM57416_NPAR },
189 { PCI_VDEVICE(BROADCOM, 0x16ef), .driver_data = BCM57416_NPAR },
190 { PCI_VDEVICE(BROADCOM, 0x16f0), .driver_data = BCM58808 },
191 { PCI_VDEVICE(BROADCOM, 0x16f1), .driver_data = BCM57452 },
192 { PCI_VDEVICE(BROADCOM, 0xd802), .driver_data = BCM58802 },
193 { PCI_VDEVICE(BROADCOM, 0xd804), .driver_data = BCM58804 },
194 #ifdef CONFIG_BNXT_SRIOV
195 { PCI_VDEVICE(BROADCOM, 0x1606), .driver_data = NETXTREME_E_VF },
196 { PCI_VDEVICE(BROADCOM, 0x1609), .driver_data = NETXTREME_E_VF },
197 { PCI_VDEVICE(BROADCOM, 0x16c1), .driver_data = NETXTREME_E_VF },
198 { PCI_VDEVICE(BROADCOM, 0x16cb), .driver_data = NETXTREME_C_VF },
199 { PCI_VDEVICE(BROADCOM, 0x16d3), .driver_data = NETXTREME_E_VF },
200 { PCI_VDEVICE(BROADCOM, 0x16dc), .driver_data = NETXTREME_E_VF },
201 { PCI_VDEVICE(BROADCOM, 0x16e1), .driver_data = NETXTREME_C_VF },
202 { PCI_VDEVICE(BROADCOM, 0x16e5), .driver_data = NETXTREME_C_VF },
203 { PCI_VDEVICE(BROADCOM, 0xd800), .driver_data = NETXTREME_S_VF },
208 MODULE_DEVICE_TABLE(pci, bnxt_pci_tbl);
210 static const u16 bnxt_vf_req_snif[] = {
213 HWRM_CFA_L2_FILTER_ALLOC,
216 static const u16 bnxt_async_events_arr[] = {
217 ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE,
218 ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD,
219 ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED,
220 ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE,
221 ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE,
224 static struct workqueue_struct *bnxt_pf_wq;
226 static bool bnxt_vf_pciid(enum board_idx idx)
228 return (idx == NETXTREME_C_VF || idx == NETXTREME_E_VF ||
229 idx == NETXTREME_S_VF);
232 #define DB_CP_REARM_FLAGS (DB_KEY_CP | DB_IDX_VALID)
233 #define DB_CP_FLAGS (DB_KEY_CP | DB_IDX_VALID | DB_IRQ_DIS)
234 #define DB_CP_IRQ_DIS_FLAGS (DB_KEY_CP | DB_IRQ_DIS)
236 #define BNXT_CP_DB_REARM(db, raw_cons) \
237 writel(DB_CP_REARM_FLAGS | RING_CMP(raw_cons), db)
239 #define BNXT_CP_DB(db, raw_cons) \
240 writel(DB_CP_FLAGS | RING_CMP(raw_cons), db)
242 #define BNXT_CP_DB_IRQ_DIS(db) \
243 writel(DB_CP_IRQ_DIS_FLAGS, db)
245 const u16 bnxt_lhint_arr[] = {
246 TX_BD_FLAGS_LHINT_512_AND_SMALLER,
247 TX_BD_FLAGS_LHINT_512_TO_1023,
248 TX_BD_FLAGS_LHINT_1024_TO_2047,
249 TX_BD_FLAGS_LHINT_1024_TO_2047,
250 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
251 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
252 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
253 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
254 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
255 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
256 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
257 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
258 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
259 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
260 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
261 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
262 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
263 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
264 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
267 static u16 bnxt_xmit_get_cfa_action(struct sk_buff *skb)
269 struct metadata_dst *md_dst = skb_metadata_dst(skb);
271 if (!md_dst || md_dst->type != METADATA_HW_PORT_MUX)
274 return md_dst->u.port_info.port_id;
277 static netdev_tx_t bnxt_start_xmit(struct sk_buff *skb, struct net_device *dev)
279 struct bnxt *bp = netdev_priv(dev);
281 struct tx_bd_ext *txbd1;
282 struct netdev_queue *txq;
285 unsigned int length, pad = 0;
286 u32 len, free_size, vlan_tag_flags, cfa_action, flags;
288 struct pci_dev *pdev = bp->pdev;
289 struct bnxt_tx_ring_info *txr;
290 struct bnxt_sw_tx_bd *tx_buf;
292 i = skb_get_queue_mapping(skb);
293 if (unlikely(i >= bp->tx_nr_rings)) {
294 dev_kfree_skb_any(skb);
298 txq = netdev_get_tx_queue(dev, i);
299 txr = &bp->tx_ring[bp->tx_ring_map[i]];
302 free_size = bnxt_tx_avail(bp, txr);
303 if (unlikely(free_size < skb_shinfo(skb)->nr_frags + 2)) {
304 netif_tx_stop_queue(txq);
305 return NETDEV_TX_BUSY;
309 len = skb_headlen(skb);
310 last_frag = skb_shinfo(skb)->nr_frags;
312 txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
314 txbd->tx_bd_opaque = prod;
316 tx_buf = &txr->tx_buf_ring[prod];
318 tx_buf->nr_frags = last_frag;
321 cfa_action = bnxt_xmit_get_cfa_action(skb);
322 if (skb_vlan_tag_present(skb)) {
323 vlan_tag_flags = TX_BD_CFA_META_KEY_VLAN |
324 skb_vlan_tag_get(skb);
325 /* Currently supports 8021Q, 8021AD vlan offloads
326 * QINQ1, QINQ2, QINQ3 vlan headers are deprecated
328 if (skb->vlan_proto == htons(ETH_P_8021Q))
329 vlan_tag_flags |= 1 << TX_BD_CFA_META_TPID_SHIFT;
332 if (free_size == bp->tx_ring_size && length <= bp->tx_push_thresh) {
333 struct tx_push_buffer *tx_push_buf = txr->tx_push;
334 struct tx_push_bd *tx_push = &tx_push_buf->push_bd;
335 struct tx_bd_ext *tx_push1 = &tx_push->txbd2;
336 void *pdata = tx_push_buf->data;
340 /* Set COAL_NOW to be ready quickly for the next push */
341 tx_push->tx_bd_len_flags_type =
342 cpu_to_le32((length << TX_BD_LEN_SHIFT) |
343 TX_BD_TYPE_LONG_TX_BD |
344 TX_BD_FLAGS_LHINT_512_AND_SMALLER |
345 TX_BD_FLAGS_COAL_NOW |
346 TX_BD_FLAGS_PACKET_END |
347 (2 << TX_BD_FLAGS_BD_CNT_SHIFT));
349 if (skb->ip_summed == CHECKSUM_PARTIAL)
350 tx_push1->tx_bd_hsize_lflags =
351 cpu_to_le32(TX_BD_FLAGS_TCP_UDP_CHKSUM);
353 tx_push1->tx_bd_hsize_lflags = 0;
355 tx_push1->tx_bd_cfa_meta = cpu_to_le32(vlan_tag_flags);
356 tx_push1->tx_bd_cfa_action =
357 cpu_to_le32(cfa_action << TX_BD_CFA_ACTION_SHIFT);
359 end = pdata + length;
360 end = PTR_ALIGN(end, 8) - 1;
363 skb_copy_from_linear_data(skb, pdata, len);
365 for (j = 0; j < last_frag; j++) {
366 skb_frag_t *frag = &skb_shinfo(skb)->frags[j];
369 fptr = skb_frag_address_safe(frag);
373 memcpy(pdata, fptr, skb_frag_size(frag));
374 pdata += skb_frag_size(frag);
377 txbd->tx_bd_len_flags_type = tx_push->tx_bd_len_flags_type;
378 txbd->tx_bd_haddr = txr->data_mapping;
379 prod = NEXT_TX(prod);
380 txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
381 memcpy(txbd, tx_push1, sizeof(*txbd));
382 prod = NEXT_TX(prod);
384 cpu_to_le32(DB_KEY_TX_PUSH | DB_LONG_TX_PUSH | prod);
388 netdev_tx_sent_queue(txq, skb->len);
389 wmb(); /* Sync is_push and byte queue before pushing data */
391 push_len = (length + sizeof(*tx_push) + 7) / 8;
393 __iowrite64_copy(txr->tx_doorbell, tx_push_buf, 16);
394 __iowrite32_copy(txr->tx_doorbell + 4, tx_push_buf + 1,
395 (push_len - 16) << 1);
397 __iowrite64_copy(txr->tx_doorbell, tx_push_buf,
405 if (length < BNXT_MIN_PKT_SIZE) {
406 pad = BNXT_MIN_PKT_SIZE - length;
407 if (skb_pad(skb, pad)) {
408 /* SKB already freed. */
412 length = BNXT_MIN_PKT_SIZE;
415 mapping = dma_map_single(&pdev->dev, skb->data, len, DMA_TO_DEVICE);
417 if (unlikely(dma_mapping_error(&pdev->dev, mapping))) {
418 dev_kfree_skb_any(skb);
423 dma_unmap_addr_set(tx_buf, mapping, mapping);
424 flags = (len << TX_BD_LEN_SHIFT) | TX_BD_TYPE_LONG_TX_BD |
425 ((last_frag + 2) << TX_BD_FLAGS_BD_CNT_SHIFT);
427 txbd->tx_bd_haddr = cpu_to_le64(mapping);
429 prod = NEXT_TX(prod);
430 txbd1 = (struct tx_bd_ext *)
431 &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
433 txbd1->tx_bd_hsize_lflags = 0;
434 if (skb_is_gso(skb)) {
437 if (skb->encapsulation)
438 hdr_len = skb_inner_network_offset(skb) +
439 skb_inner_network_header_len(skb) +
440 inner_tcp_hdrlen(skb);
442 hdr_len = skb_transport_offset(skb) +
445 txbd1->tx_bd_hsize_lflags = cpu_to_le32(TX_BD_FLAGS_LSO |
447 (hdr_len << (TX_BD_HSIZE_SHIFT - 1)));
448 length = skb_shinfo(skb)->gso_size;
449 txbd1->tx_bd_mss = cpu_to_le32(length);
451 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
452 txbd1->tx_bd_hsize_lflags =
453 cpu_to_le32(TX_BD_FLAGS_TCP_UDP_CHKSUM);
454 txbd1->tx_bd_mss = 0;
458 flags |= bnxt_lhint_arr[length];
459 txbd->tx_bd_len_flags_type = cpu_to_le32(flags);
461 txbd1->tx_bd_cfa_meta = cpu_to_le32(vlan_tag_flags);
462 txbd1->tx_bd_cfa_action =
463 cpu_to_le32(cfa_action << TX_BD_CFA_ACTION_SHIFT);
464 for (i = 0; i < last_frag; i++) {
465 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
467 prod = NEXT_TX(prod);
468 txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
470 len = skb_frag_size(frag);
471 mapping = skb_frag_dma_map(&pdev->dev, frag, 0, len,
474 if (unlikely(dma_mapping_error(&pdev->dev, mapping)))
477 tx_buf = &txr->tx_buf_ring[prod];
478 dma_unmap_addr_set(tx_buf, mapping, mapping);
480 txbd->tx_bd_haddr = cpu_to_le64(mapping);
482 flags = len << TX_BD_LEN_SHIFT;
483 txbd->tx_bd_len_flags_type = cpu_to_le32(flags);
487 txbd->tx_bd_len_flags_type =
488 cpu_to_le32(((len + pad) << TX_BD_LEN_SHIFT) | flags |
489 TX_BD_FLAGS_PACKET_END);
491 netdev_tx_sent_queue(txq, skb->len);
493 /* Sync BD data before updating doorbell */
496 prod = NEXT_TX(prod);
499 if (!skb->xmit_more || netif_xmit_stopped(txq))
500 bnxt_db_write(bp, txr->tx_doorbell, DB_KEY_TX | prod);
506 if (unlikely(bnxt_tx_avail(bp, txr) <= MAX_SKB_FRAGS + 1)) {
507 if (skb->xmit_more && !tx_buf->is_push)
508 bnxt_db_write(bp, txr->tx_doorbell, DB_KEY_TX | prod);
510 netif_tx_stop_queue(txq);
512 /* netif_tx_stop_queue() must be done before checking
513 * tx index in bnxt_tx_avail() below, because in
514 * bnxt_tx_int(), we update tx index before checking for
515 * netif_tx_queue_stopped().
518 if (bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh)
519 netif_tx_wake_queue(txq);
526 /* start back at beginning and unmap skb */
528 tx_buf = &txr->tx_buf_ring[prod];
530 dma_unmap_single(&pdev->dev, dma_unmap_addr(tx_buf, mapping),
531 skb_headlen(skb), PCI_DMA_TODEVICE);
532 prod = NEXT_TX(prod);
534 /* unmap remaining mapped pages */
535 for (i = 0; i < last_frag; i++) {
536 prod = NEXT_TX(prod);
537 tx_buf = &txr->tx_buf_ring[prod];
538 dma_unmap_page(&pdev->dev, dma_unmap_addr(tx_buf, mapping),
539 skb_frag_size(&skb_shinfo(skb)->frags[i]),
543 dev_kfree_skb_any(skb);
547 static void bnxt_tx_int(struct bnxt *bp, struct bnxt_napi *bnapi, int nr_pkts)
549 struct bnxt_tx_ring_info *txr = bnapi->tx_ring;
550 struct netdev_queue *txq = netdev_get_tx_queue(bp->dev, txr->txq_index);
551 u16 cons = txr->tx_cons;
552 struct pci_dev *pdev = bp->pdev;
554 unsigned int tx_bytes = 0;
556 for (i = 0; i < nr_pkts; i++) {
557 struct bnxt_sw_tx_bd *tx_buf;
561 tx_buf = &txr->tx_buf_ring[cons];
562 cons = NEXT_TX(cons);
566 if (tx_buf->is_push) {
571 dma_unmap_single(&pdev->dev, dma_unmap_addr(tx_buf, mapping),
572 skb_headlen(skb), PCI_DMA_TODEVICE);
573 last = tx_buf->nr_frags;
575 for (j = 0; j < last; j++) {
576 cons = NEXT_TX(cons);
577 tx_buf = &txr->tx_buf_ring[cons];
580 dma_unmap_addr(tx_buf, mapping),
581 skb_frag_size(&skb_shinfo(skb)->frags[j]),
586 cons = NEXT_TX(cons);
588 tx_bytes += skb->len;
589 dev_kfree_skb_any(skb);
592 netdev_tx_completed_queue(txq, nr_pkts, tx_bytes);
595 /* Need to make the tx_cons update visible to bnxt_start_xmit()
596 * before checking for netif_tx_queue_stopped(). Without the
597 * memory barrier, there is a small possibility that bnxt_start_xmit()
598 * will miss it and cause the queue to be stopped forever.
602 if (unlikely(netif_tx_queue_stopped(txq)) &&
603 (bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh)) {
604 __netif_tx_lock(txq, smp_processor_id());
605 if (netif_tx_queue_stopped(txq) &&
606 bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh &&
607 txr->dev_state != BNXT_DEV_STATE_CLOSING)
608 netif_tx_wake_queue(txq);
609 __netif_tx_unlock(txq);
613 static struct page *__bnxt_alloc_rx_page(struct bnxt *bp, dma_addr_t *mapping,
616 struct device *dev = &bp->pdev->dev;
619 page = alloc_page(gfp);
623 *mapping = dma_map_page_attrs(dev, page, 0, PAGE_SIZE, bp->rx_dir,
624 DMA_ATTR_WEAK_ORDERING);
625 if (dma_mapping_error(dev, *mapping)) {
629 *mapping += bp->rx_dma_offset;
633 static inline u8 *__bnxt_alloc_rx_data(struct bnxt *bp, dma_addr_t *mapping,
637 struct pci_dev *pdev = bp->pdev;
639 data = kmalloc(bp->rx_buf_size, gfp);
643 *mapping = dma_map_single_attrs(&pdev->dev, data + bp->rx_dma_offset,
644 bp->rx_buf_use_size, bp->rx_dir,
645 DMA_ATTR_WEAK_ORDERING);
647 if (dma_mapping_error(&pdev->dev, *mapping)) {
654 int bnxt_alloc_rx_data(struct bnxt *bp, struct bnxt_rx_ring_info *rxr,
657 struct rx_bd *rxbd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
658 struct bnxt_sw_rx_bd *rx_buf = &rxr->rx_buf_ring[prod];
661 if (BNXT_RX_PAGE_MODE(bp)) {
662 struct page *page = __bnxt_alloc_rx_page(bp, &mapping, gfp);
668 rx_buf->data_ptr = page_address(page) + bp->rx_offset;
670 u8 *data = __bnxt_alloc_rx_data(bp, &mapping, gfp);
676 rx_buf->data_ptr = data + bp->rx_offset;
678 rx_buf->mapping = mapping;
680 rxbd->rx_bd_haddr = cpu_to_le64(mapping);
684 void bnxt_reuse_rx_data(struct bnxt_rx_ring_info *rxr, u16 cons, void *data)
686 u16 prod = rxr->rx_prod;
687 struct bnxt_sw_rx_bd *cons_rx_buf, *prod_rx_buf;
688 struct rx_bd *cons_bd, *prod_bd;
690 prod_rx_buf = &rxr->rx_buf_ring[prod];
691 cons_rx_buf = &rxr->rx_buf_ring[cons];
693 prod_rx_buf->data = data;
694 prod_rx_buf->data_ptr = cons_rx_buf->data_ptr;
696 prod_rx_buf->mapping = cons_rx_buf->mapping;
698 prod_bd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
699 cons_bd = &rxr->rx_desc_ring[RX_RING(cons)][RX_IDX(cons)];
701 prod_bd->rx_bd_haddr = cons_bd->rx_bd_haddr;
704 static inline u16 bnxt_find_next_agg_idx(struct bnxt_rx_ring_info *rxr, u16 idx)
706 u16 next, max = rxr->rx_agg_bmap_size;
708 next = find_next_zero_bit(rxr->rx_agg_bmap, max, idx);
710 next = find_first_zero_bit(rxr->rx_agg_bmap, max);
714 static inline int bnxt_alloc_rx_page(struct bnxt *bp,
715 struct bnxt_rx_ring_info *rxr,
719 &rxr->rx_agg_desc_ring[RX_RING(prod)][RX_IDX(prod)];
720 struct bnxt_sw_rx_agg_bd *rx_agg_buf;
721 struct pci_dev *pdev = bp->pdev;
724 u16 sw_prod = rxr->rx_sw_agg_prod;
725 unsigned int offset = 0;
727 if (PAGE_SIZE > BNXT_RX_PAGE_SIZE) {
730 page = alloc_page(gfp);
734 rxr->rx_page_offset = 0;
736 offset = rxr->rx_page_offset;
737 rxr->rx_page_offset += BNXT_RX_PAGE_SIZE;
738 if (rxr->rx_page_offset == PAGE_SIZE)
743 page = alloc_page(gfp);
748 mapping = dma_map_page_attrs(&pdev->dev, page, offset,
749 BNXT_RX_PAGE_SIZE, PCI_DMA_FROMDEVICE,
750 DMA_ATTR_WEAK_ORDERING);
751 if (dma_mapping_error(&pdev->dev, mapping)) {
756 if (unlikely(test_bit(sw_prod, rxr->rx_agg_bmap)))
757 sw_prod = bnxt_find_next_agg_idx(rxr, sw_prod);
759 __set_bit(sw_prod, rxr->rx_agg_bmap);
760 rx_agg_buf = &rxr->rx_agg_ring[sw_prod];
761 rxr->rx_sw_agg_prod = NEXT_RX_AGG(sw_prod);
763 rx_agg_buf->page = page;
764 rx_agg_buf->offset = offset;
765 rx_agg_buf->mapping = mapping;
766 rxbd->rx_bd_haddr = cpu_to_le64(mapping);
767 rxbd->rx_bd_opaque = sw_prod;
771 static void bnxt_reuse_rx_agg_bufs(struct bnxt_napi *bnapi, u16 cp_cons,
774 struct bnxt *bp = bnapi->bp;
775 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
776 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
777 u16 prod = rxr->rx_agg_prod;
778 u16 sw_prod = rxr->rx_sw_agg_prod;
781 for (i = 0; i < agg_bufs; i++) {
783 struct rx_agg_cmp *agg;
784 struct bnxt_sw_rx_agg_bd *cons_rx_buf, *prod_rx_buf;
785 struct rx_bd *prod_bd;
788 agg = (struct rx_agg_cmp *)
789 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
790 cons = agg->rx_agg_cmp_opaque;
791 __clear_bit(cons, rxr->rx_agg_bmap);
793 if (unlikely(test_bit(sw_prod, rxr->rx_agg_bmap)))
794 sw_prod = bnxt_find_next_agg_idx(rxr, sw_prod);
796 __set_bit(sw_prod, rxr->rx_agg_bmap);
797 prod_rx_buf = &rxr->rx_agg_ring[sw_prod];
798 cons_rx_buf = &rxr->rx_agg_ring[cons];
800 /* It is possible for sw_prod to be equal to cons, so
801 * set cons_rx_buf->page to NULL first.
803 page = cons_rx_buf->page;
804 cons_rx_buf->page = NULL;
805 prod_rx_buf->page = page;
806 prod_rx_buf->offset = cons_rx_buf->offset;
808 prod_rx_buf->mapping = cons_rx_buf->mapping;
810 prod_bd = &rxr->rx_agg_desc_ring[RX_RING(prod)][RX_IDX(prod)];
812 prod_bd->rx_bd_haddr = cpu_to_le64(cons_rx_buf->mapping);
813 prod_bd->rx_bd_opaque = sw_prod;
815 prod = NEXT_RX_AGG(prod);
816 sw_prod = NEXT_RX_AGG(sw_prod);
817 cp_cons = NEXT_CMP(cp_cons);
819 rxr->rx_agg_prod = prod;
820 rxr->rx_sw_agg_prod = sw_prod;
823 static struct sk_buff *bnxt_rx_page_skb(struct bnxt *bp,
824 struct bnxt_rx_ring_info *rxr,
825 u16 cons, void *data, u8 *data_ptr,
827 unsigned int offset_and_len)
829 unsigned int payload = offset_and_len >> 16;
830 unsigned int len = offset_and_len & 0xffff;
831 struct skb_frag_struct *frag;
832 struct page *page = data;
833 u16 prod = rxr->rx_prod;
837 err = bnxt_alloc_rx_data(bp, rxr, prod, GFP_ATOMIC);
839 bnxt_reuse_rx_data(rxr, cons, data);
842 dma_addr -= bp->rx_dma_offset;
843 dma_unmap_page_attrs(&bp->pdev->dev, dma_addr, PAGE_SIZE, bp->rx_dir,
844 DMA_ATTR_WEAK_ORDERING);
846 if (unlikely(!payload))
847 payload = eth_get_headlen(data_ptr, len);
849 skb = napi_alloc_skb(&rxr->bnapi->napi, payload);
855 off = (void *)data_ptr - page_address(page);
856 skb_add_rx_frag(skb, 0, page, off, len, PAGE_SIZE);
857 memcpy(skb->data - NET_IP_ALIGN, data_ptr - NET_IP_ALIGN,
858 payload + NET_IP_ALIGN);
860 frag = &skb_shinfo(skb)->frags[0];
861 skb_frag_size_sub(frag, payload);
862 frag->page_offset += payload;
863 skb->data_len -= payload;
864 skb->tail += payload;
869 static struct sk_buff *bnxt_rx_skb(struct bnxt *bp,
870 struct bnxt_rx_ring_info *rxr, u16 cons,
871 void *data, u8 *data_ptr,
873 unsigned int offset_and_len)
875 u16 prod = rxr->rx_prod;
879 err = bnxt_alloc_rx_data(bp, rxr, prod, GFP_ATOMIC);
881 bnxt_reuse_rx_data(rxr, cons, data);
885 skb = build_skb(data, 0);
886 dma_unmap_single_attrs(&bp->pdev->dev, dma_addr, bp->rx_buf_use_size,
887 bp->rx_dir, DMA_ATTR_WEAK_ORDERING);
893 skb_reserve(skb, bp->rx_offset);
894 skb_put(skb, offset_and_len & 0xffff);
898 static struct sk_buff *bnxt_rx_pages(struct bnxt *bp, struct bnxt_napi *bnapi,
899 struct sk_buff *skb, u16 cp_cons,
902 struct pci_dev *pdev = bp->pdev;
903 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
904 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
905 u16 prod = rxr->rx_agg_prod;
908 for (i = 0; i < agg_bufs; i++) {
910 struct rx_agg_cmp *agg;
911 struct bnxt_sw_rx_agg_bd *cons_rx_buf;
915 agg = (struct rx_agg_cmp *)
916 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
917 cons = agg->rx_agg_cmp_opaque;
918 frag_len = (le32_to_cpu(agg->rx_agg_cmp_len_flags_type) &
919 RX_AGG_CMP_LEN) >> RX_AGG_CMP_LEN_SHIFT;
921 cons_rx_buf = &rxr->rx_agg_ring[cons];
922 skb_fill_page_desc(skb, i, cons_rx_buf->page,
923 cons_rx_buf->offset, frag_len);
924 __clear_bit(cons, rxr->rx_agg_bmap);
926 /* It is possible for bnxt_alloc_rx_page() to allocate
927 * a sw_prod index that equals the cons index, so we
928 * need to clear the cons entry now.
930 mapping = cons_rx_buf->mapping;
931 page = cons_rx_buf->page;
932 cons_rx_buf->page = NULL;
934 if (bnxt_alloc_rx_page(bp, rxr, prod, GFP_ATOMIC) != 0) {
935 struct skb_shared_info *shinfo;
936 unsigned int nr_frags;
938 shinfo = skb_shinfo(skb);
939 nr_frags = --shinfo->nr_frags;
940 __skb_frag_set_page(&shinfo->frags[nr_frags], NULL);
944 cons_rx_buf->page = page;
946 /* Update prod since possibly some pages have been
949 rxr->rx_agg_prod = prod;
950 bnxt_reuse_rx_agg_bufs(bnapi, cp_cons, agg_bufs - i);
954 dma_unmap_page_attrs(&pdev->dev, mapping, BNXT_RX_PAGE_SIZE,
956 DMA_ATTR_WEAK_ORDERING);
958 skb->data_len += frag_len;
959 skb->len += frag_len;
960 skb->truesize += PAGE_SIZE;
962 prod = NEXT_RX_AGG(prod);
963 cp_cons = NEXT_CMP(cp_cons);
965 rxr->rx_agg_prod = prod;
969 static int bnxt_agg_bufs_valid(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
970 u8 agg_bufs, u32 *raw_cons)
973 struct rx_agg_cmp *agg;
975 *raw_cons = ADV_RAW_CMP(*raw_cons, agg_bufs);
976 last = RING_CMP(*raw_cons);
977 agg = (struct rx_agg_cmp *)
978 &cpr->cp_desc_ring[CP_RING(last)][CP_IDX(last)];
979 return RX_AGG_CMP_VALID(agg, *raw_cons);
982 static inline struct sk_buff *bnxt_copy_skb(struct bnxt_napi *bnapi, u8 *data,
986 struct bnxt *bp = bnapi->bp;
987 struct pci_dev *pdev = bp->pdev;
990 skb = napi_alloc_skb(&bnapi->napi, len);
994 dma_sync_single_for_cpu(&pdev->dev, mapping, bp->rx_copy_thresh,
997 memcpy(skb->data - NET_IP_ALIGN, data - NET_IP_ALIGN,
1000 dma_sync_single_for_device(&pdev->dev, mapping, bp->rx_copy_thresh,
1007 static int bnxt_discard_rx(struct bnxt *bp, struct bnxt_napi *bnapi,
1008 u32 *raw_cons, void *cmp)
1010 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1011 struct rx_cmp *rxcmp = cmp;
1012 u32 tmp_raw_cons = *raw_cons;
1013 u8 cmp_type, agg_bufs = 0;
1015 cmp_type = RX_CMP_TYPE(rxcmp);
1017 if (cmp_type == CMP_TYPE_RX_L2_CMP) {
1018 agg_bufs = (le32_to_cpu(rxcmp->rx_cmp_misc_v1) &
1020 RX_CMP_AGG_BUFS_SHIFT;
1021 } else if (cmp_type == CMP_TYPE_RX_L2_TPA_END_CMP) {
1022 struct rx_tpa_end_cmp *tpa_end = cmp;
1024 agg_bufs = (le32_to_cpu(tpa_end->rx_tpa_end_cmp_misc_v1) &
1025 RX_TPA_END_CMP_AGG_BUFS) >>
1026 RX_TPA_END_CMP_AGG_BUFS_SHIFT;
1030 if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, &tmp_raw_cons))
1033 *raw_cons = tmp_raw_cons;
1037 static void bnxt_queue_sp_work(struct bnxt *bp)
1040 queue_work(bnxt_pf_wq, &bp->sp_task);
1042 schedule_work(&bp->sp_task);
1045 static void bnxt_cancel_sp_work(struct bnxt *bp)
1048 flush_workqueue(bnxt_pf_wq);
1050 cancel_work_sync(&bp->sp_task);
1053 static void bnxt_sched_reset(struct bnxt *bp, struct bnxt_rx_ring_info *rxr)
1055 if (!rxr->bnapi->in_reset) {
1056 rxr->bnapi->in_reset = true;
1057 set_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event);
1058 bnxt_queue_sp_work(bp);
1060 rxr->rx_next_cons = 0xffff;
1063 static void bnxt_tpa_start(struct bnxt *bp, struct bnxt_rx_ring_info *rxr,
1064 struct rx_tpa_start_cmp *tpa_start,
1065 struct rx_tpa_start_cmp_ext *tpa_start1)
1067 u8 agg_id = TPA_START_AGG_ID(tpa_start);
1069 struct bnxt_tpa_info *tpa_info;
1070 struct bnxt_sw_rx_bd *cons_rx_buf, *prod_rx_buf;
1071 struct rx_bd *prod_bd;
1074 cons = tpa_start->rx_tpa_start_cmp_opaque;
1075 prod = rxr->rx_prod;
1076 cons_rx_buf = &rxr->rx_buf_ring[cons];
1077 prod_rx_buf = &rxr->rx_buf_ring[prod];
1078 tpa_info = &rxr->rx_tpa[agg_id];
1080 if (unlikely(cons != rxr->rx_next_cons)) {
1081 bnxt_sched_reset(bp, rxr);
1084 /* Store cfa_code in tpa_info to use in tpa_end
1085 * completion processing.
1087 tpa_info->cfa_code = TPA_START_CFA_CODE(tpa_start1);
1088 prod_rx_buf->data = tpa_info->data;
1089 prod_rx_buf->data_ptr = tpa_info->data_ptr;
1091 mapping = tpa_info->mapping;
1092 prod_rx_buf->mapping = mapping;
1094 prod_bd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
1096 prod_bd->rx_bd_haddr = cpu_to_le64(mapping);
1098 tpa_info->data = cons_rx_buf->data;
1099 tpa_info->data_ptr = cons_rx_buf->data_ptr;
1100 cons_rx_buf->data = NULL;
1101 tpa_info->mapping = cons_rx_buf->mapping;
1104 le32_to_cpu(tpa_start->rx_tpa_start_cmp_len_flags_type) >>
1105 RX_TPA_START_CMP_LEN_SHIFT;
1106 if (likely(TPA_START_HASH_VALID(tpa_start))) {
1107 u32 hash_type = TPA_START_HASH_TYPE(tpa_start);
1109 tpa_info->hash_type = PKT_HASH_TYPE_L4;
1110 tpa_info->gso_type = SKB_GSO_TCPV4;
1111 /* RSS profiles 1 and 3 with extract code 0 for inner 4-tuple */
1113 tpa_info->gso_type = SKB_GSO_TCPV6;
1114 tpa_info->rss_hash =
1115 le32_to_cpu(tpa_start->rx_tpa_start_cmp_rss_hash);
1117 tpa_info->hash_type = PKT_HASH_TYPE_NONE;
1118 tpa_info->gso_type = 0;
1119 if (netif_msg_rx_err(bp))
1120 netdev_warn(bp->dev, "TPA packet without valid hash\n");
1122 tpa_info->flags2 = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_flags2);
1123 tpa_info->metadata = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_metadata);
1124 tpa_info->hdr_info = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_hdr_info);
1126 rxr->rx_prod = NEXT_RX(prod);
1127 cons = NEXT_RX(cons);
1128 rxr->rx_next_cons = NEXT_RX(cons);
1129 cons_rx_buf = &rxr->rx_buf_ring[cons];
1131 bnxt_reuse_rx_data(rxr, cons, cons_rx_buf->data);
1132 rxr->rx_prod = NEXT_RX(rxr->rx_prod);
1133 cons_rx_buf->data = NULL;
1136 static void bnxt_abort_tpa(struct bnxt *bp, struct bnxt_napi *bnapi,
1137 u16 cp_cons, u32 agg_bufs)
1140 bnxt_reuse_rx_agg_bufs(bnapi, cp_cons, agg_bufs);
1143 static struct sk_buff *bnxt_gro_func_5731x(struct bnxt_tpa_info *tpa_info,
1144 int payload_off, int tcp_ts,
1145 struct sk_buff *skb)
1150 u16 outer_ip_off, inner_ip_off, inner_mac_off;
1151 u32 hdr_info = tpa_info->hdr_info;
1152 bool loopback = false;
1154 inner_ip_off = BNXT_TPA_INNER_L3_OFF(hdr_info);
1155 inner_mac_off = BNXT_TPA_INNER_L2_OFF(hdr_info);
1156 outer_ip_off = BNXT_TPA_OUTER_L3_OFF(hdr_info);
1158 /* If the packet is an internal loopback packet, the offsets will
1159 * have an extra 4 bytes.
1161 if (inner_mac_off == 4) {
1163 } else if (inner_mac_off > 4) {
1164 __be16 proto = *((__be16 *)(skb->data + inner_ip_off -
1167 /* We only support inner iPv4/ipv6. If we don't see the
1168 * correct protocol ID, it must be a loopback packet where
1169 * the offsets are off by 4.
1171 if (proto != htons(ETH_P_IP) && proto != htons(ETH_P_IPV6))
1175 /* internal loopback packet, subtract all offsets by 4 */
1181 nw_off = inner_ip_off - ETH_HLEN;
1182 skb_set_network_header(skb, nw_off);
1183 if (tpa_info->flags2 & RX_TPA_START_CMP_FLAGS2_IP_TYPE) {
1184 struct ipv6hdr *iph = ipv6_hdr(skb);
1186 skb_set_transport_header(skb, nw_off + sizeof(struct ipv6hdr));
1187 len = skb->len - skb_transport_offset(skb);
1189 th->check = ~tcp_v6_check(len, &iph->saddr, &iph->daddr, 0);
1191 struct iphdr *iph = ip_hdr(skb);
1193 skb_set_transport_header(skb, nw_off + sizeof(struct iphdr));
1194 len = skb->len - skb_transport_offset(skb);
1196 th->check = ~tcp_v4_check(len, iph->saddr, iph->daddr, 0);
1199 if (inner_mac_off) { /* tunnel */
1200 struct udphdr *uh = NULL;
1201 __be16 proto = *((__be16 *)(skb->data + outer_ip_off -
1204 if (proto == htons(ETH_P_IP)) {
1205 struct iphdr *iph = (struct iphdr *)skb->data;
1207 if (iph->protocol == IPPROTO_UDP)
1208 uh = (struct udphdr *)(iph + 1);
1210 struct ipv6hdr *iph = (struct ipv6hdr *)skb->data;
1212 if (iph->nexthdr == IPPROTO_UDP)
1213 uh = (struct udphdr *)(iph + 1);
1217 skb_shinfo(skb)->gso_type |=
1218 SKB_GSO_UDP_TUNNEL_CSUM;
1220 skb_shinfo(skb)->gso_type |= SKB_GSO_UDP_TUNNEL;
1227 #define BNXT_IPV4_HDR_SIZE (sizeof(struct iphdr) + sizeof(struct tcphdr))
1228 #define BNXT_IPV6_HDR_SIZE (sizeof(struct ipv6hdr) + sizeof(struct tcphdr))
1230 static struct sk_buff *bnxt_gro_func_5730x(struct bnxt_tpa_info *tpa_info,
1231 int payload_off, int tcp_ts,
1232 struct sk_buff *skb)
1236 int len, nw_off, tcp_opt_len = 0;
1241 if (tpa_info->gso_type == SKB_GSO_TCPV4) {
1244 nw_off = payload_off - BNXT_IPV4_HDR_SIZE - tcp_opt_len -
1246 skb_set_network_header(skb, nw_off);
1248 skb_set_transport_header(skb, nw_off + sizeof(struct iphdr));
1249 len = skb->len - skb_transport_offset(skb);
1251 th->check = ~tcp_v4_check(len, iph->saddr, iph->daddr, 0);
1252 } else if (tpa_info->gso_type == SKB_GSO_TCPV6) {
1253 struct ipv6hdr *iph;
1255 nw_off = payload_off - BNXT_IPV6_HDR_SIZE - tcp_opt_len -
1257 skb_set_network_header(skb, nw_off);
1258 iph = ipv6_hdr(skb);
1259 skb_set_transport_header(skb, nw_off + sizeof(struct ipv6hdr));
1260 len = skb->len - skb_transport_offset(skb);
1262 th->check = ~tcp_v6_check(len, &iph->saddr, &iph->daddr, 0);
1264 dev_kfree_skb_any(skb);
1268 if (nw_off) { /* tunnel */
1269 struct udphdr *uh = NULL;
1271 if (skb->protocol == htons(ETH_P_IP)) {
1272 struct iphdr *iph = (struct iphdr *)skb->data;
1274 if (iph->protocol == IPPROTO_UDP)
1275 uh = (struct udphdr *)(iph + 1);
1277 struct ipv6hdr *iph = (struct ipv6hdr *)skb->data;
1279 if (iph->nexthdr == IPPROTO_UDP)
1280 uh = (struct udphdr *)(iph + 1);
1284 skb_shinfo(skb)->gso_type |=
1285 SKB_GSO_UDP_TUNNEL_CSUM;
1287 skb_shinfo(skb)->gso_type |= SKB_GSO_UDP_TUNNEL;
1294 static inline struct sk_buff *bnxt_gro_skb(struct bnxt *bp,
1295 struct bnxt_tpa_info *tpa_info,
1296 struct rx_tpa_end_cmp *tpa_end,
1297 struct rx_tpa_end_cmp_ext *tpa_end1,
1298 struct sk_buff *skb)
1304 segs = TPA_END_TPA_SEGS(tpa_end);
1308 NAPI_GRO_CB(skb)->count = segs;
1309 skb_shinfo(skb)->gso_size =
1310 le32_to_cpu(tpa_end1->rx_tpa_end_cmp_seg_len);
1311 skb_shinfo(skb)->gso_type = tpa_info->gso_type;
1312 payload_off = (le32_to_cpu(tpa_end->rx_tpa_end_cmp_misc_v1) &
1313 RX_TPA_END_CMP_PAYLOAD_OFFSET) >>
1314 RX_TPA_END_CMP_PAYLOAD_OFFSET_SHIFT;
1315 skb = bp->gro_func(tpa_info, payload_off, TPA_END_GRO_TS(tpa_end), skb);
1317 tcp_gro_complete(skb);
1322 /* Given the cfa_code of a received packet determine which
1323 * netdev (vf-rep or PF) the packet is destined to.
1325 static struct net_device *bnxt_get_pkt_dev(struct bnxt *bp, u16 cfa_code)
1327 struct net_device *dev = bnxt_get_vf_rep(bp, cfa_code);
1329 /* if vf-rep dev is NULL, the must belongs to the PF */
1330 return dev ? dev : bp->dev;
1333 static inline struct sk_buff *bnxt_tpa_end(struct bnxt *bp,
1334 struct bnxt_napi *bnapi,
1336 struct rx_tpa_end_cmp *tpa_end,
1337 struct rx_tpa_end_cmp_ext *tpa_end1,
1340 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1341 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
1342 u8 agg_id = TPA_END_AGG_ID(tpa_end);
1343 u8 *data_ptr, agg_bufs;
1344 u16 cp_cons = RING_CMP(*raw_cons);
1346 struct bnxt_tpa_info *tpa_info;
1348 struct sk_buff *skb;
1351 if (unlikely(bnapi->in_reset)) {
1352 int rc = bnxt_discard_rx(bp, bnapi, raw_cons, tpa_end);
1355 return ERR_PTR(-EBUSY);
1359 tpa_info = &rxr->rx_tpa[agg_id];
1360 data = tpa_info->data;
1361 data_ptr = tpa_info->data_ptr;
1363 len = tpa_info->len;
1364 mapping = tpa_info->mapping;
1366 agg_bufs = (le32_to_cpu(tpa_end->rx_tpa_end_cmp_misc_v1) &
1367 RX_TPA_END_CMP_AGG_BUFS) >> RX_TPA_END_CMP_AGG_BUFS_SHIFT;
1370 if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, raw_cons))
1371 return ERR_PTR(-EBUSY);
1373 *event |= BNXT_AGG_EVENT;
1374 cp_cons = NEXT_CMP(cp_cons);
1377 if (unlikely(agg_bufs > MAX_SKB_FRAGS || TPA_END_ERRORS(tpa_end1))) {
1378 bnxt_abort_tpa(bp, bnapi, cp_cons, agg_bufs);
1379 if (agg_bufs > MAX_SKB_FRAGS)
1380 netdev_warn(bp->dev, "TPA frags %d exceeded MAX_SKB_FRAGS %d\n",
1381 agg_bufs, (int)MAX_SKB_FRAGS);
1385 if (len <= bp->rx_copy_thresh) {
1386 skb = bnxt_copy_skb(bnapi, data_ptr, len, mapping);
1388 bnxt_abort_tpa(bp, bnapi, cp_cons, agg_bufs);
1393 dma_addr_t new_mapping;
1395 new_data = __bnxt_alloc_rx_data(bp, &new_mapping, GFP_ATOMIC);
1397 bnxt_abort_tpa(bp, bnapi, cp_cons, agg_bufs);
1401 tpa_info->data = new_data;
1402 tpa_info->data_ptr = new_data + bp->rx_offset;
1403 tpa_info->mapping = new_mapping;
1405 skb = build_skb(data, 0);
1406 dma_unmap_single_attrs(&bp->pdev->dev, mapping,
1407 bp->rx_buf_use_size, bp->rx_dir,
1408 DMA_ATTR_WEAK_ORDERING);
1412 bnxt_abort_tpa(bp, bnapi, cp_cons, agg_bufs);
1415 skb_reserve(skb, bp->rx_offset);
1420 skb = bnxt_rx_pages(bp, bnapi, skb, cp_cons, agg_bufs);
1422 /* Page reuse already handled by bnxt_rx_pages(). */
1428 eth_type_trans(skb, bnxt_get_pkt_dev(bp, tpa_info->cfa_code));
1430 if (tpa_info->hash_type != PKT_HASH_TYPE_NONE)
1431 skb_set_hash(skb, tpa_info->rss_hash, tpa_info->hash_type);
1433 if ((tpa_info->flags2 & RX_CMP_FLAGS2_META_FORMAT_VLAN) &&
1434 (skb->dev->features & NETIF_F_HW_VLAN_CTAG_RX)) {
1435 u16 vlan_proto = tpa_info->metadata >>
1436 RX_CMP_FLAGS2_METADATA_TPID_SFT;
1437 u16 vtag = tpa_info->metadata & RX_CMP_FLAGS2_METADATA_VID_MASK;
1439 __vlan_hwaccel_put_tag(skb, htons(vlan_proto), vtag);
1442 skb_checksum_none_assert(skb);
1443 if (likely(tpa_info->flags2 & RX_TPA_START_CMP_FLAGS2_L4_CS_CALC)) {
1444 skb->ip_summed = CHECKSUM_UNNECESSARY;
1446 (tpa_info->flags2 & RX_CMP_FLAGS2_T_L4_CS_CALC) >> 3;
1449 if (TPA_END_GRO(tpa_end))
1450 skb = bnxt_gro_skb(bp, tpa_info, tpa_end, tpa_end1, skb);
1455 static void bnxt_deliver_skb(struct bnxt *bp, struct bnxt_napi *bnapi,
1456 struct sk_buff *skb)
1458 if (skb->dev != bp->dev) {
1459 /* this packet belongs to a vf-rep */
1460 bnxt_vf_rep_rx(bp, skb);
1463 skb_record_rx_queue(skb, bnapi->index);
1464 napi_gro_receive(&bnapi->napi, skb);
1467 /* returns the following:
1468 * 1 - 1 packet successfully received
1469 * 0 - successful TPA_START, packet not completed yet
1470 * -EBUSY - completion ring does not have all the agg buffers yet
1471 * -ENOMEM - packet aborted due to out of memory
1472 * -EIO - packet aborted due to hw error indicated in BD
1474 static int bnxt_rx_pkt(struct bnxt *bp, struct bnxt_napi *bnapi, u32 *raw_cons,
1477 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1478 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
1479 struct net_device *dev = bp->dev;
1480 struct rx_cmp *rxcmp;
1481 struct rx_cmp_ext *rxcmp1;
1482 u32 tmp_raw_cons = *raw_cons;
1483 u16 cfa_code, cons, prod, cp_cons = RING_CMP(tmp_raw_cons);
1484 struct bnxt_sw_rx_bd *rx_buf;
1486 u8 *data_ptr, agg_bufs, cmp_type;
1487 dma_addr_t dma_addr;
1488 struct sk_buff *skb;
1493 rxcmp = (struct rx_cmp *)
1494 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1496 tmp_raw_cons = NEXT_RAW_CMP(tmp_raw_cons);
1497 cp_cons = RING_CMP(tmp_raw_cons);
1498 rxcmp1 = (struct rx_cmp_ext *)
1499 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1501 if (!RX_CMP_VALID(rxcmp1, tmp_raw_cons))
1504 cmp_type = RX_CMP_TYPE(rxcmp);
1506 prod = rxr->rx_prod;
1508 if (cmp_type == CMP_TYPE_RX_L2_TPA_START_CMP) {
1509 bnxt_tpa_start(bp, rxr, (struct rx_tpa_start_cmp *)rxcmp,
1510 (struct rx_tpa_start_cmp_ext *)rxcmp1);
1512 *event |= BNXT_RX_EVENT;
1513 goto next_rx_no_prod;
1515 } else if (cmp_type == CMP_TYPE_RX_L2_TPA_END_CMP) {
1516 skb = bnxt_tpa_end(bp, bnapi, &tmp_raw_cons,
1517 (struct rx_tpa_end_cmp *)rxcmp,
1518 (struct rx_tpa_end_cmp_ext *)rxcmp1, event);
1525 bnxt_deliver_skb(bp, bnapi, skb);
1528 *event |= BNXT_RX_EVENT;
1529 goto next_rx_no_prod;
1532 cons = rxcmp->rx_cmp_opaque;
1533 rx_buf = &rxr->rx_buf_ring[cons];
1534 data = rx_buf->data;
1535 data_ptr = rx_buf->data_ptr;
1536 if (unlikely(cons != rxr->rx_next_cons)) {
1537 int rc1 = bnxt_discard_rx(bp, bnapi, raw_cons, rxcmp);
1539 bnxt_sched_reset(bp, rxr);
1544 misc = le32_to_cpu(rxcmp->rx_cmp_misc_v1);
1545 agg_bufs = (misc & RX_CMP_AGG_BUFS) >> RX_CMP_AGG_BUFS_SHIFT;
1548 if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, &tmp_raw_cons))
1551 cp_cons = NEXT_CMP(cp_cons);
1552 *event |= BNXT_AGG_EVENT;
1554 *event |= BNXT_RX_EVENT;
1556 rx_buf->data = NULL;
1557 if (rxcmp1->rx_cmp_cfa_code_errors_v2 & RX_CMP_L2_ERRORS) {
1558 bnxt_reuse_rx_data(rxr, cons, data);
1560 bnxt_reuse_rx_agg_bufs(bnapi, cp_cons, agg_bufs);
1566 len = le32_to_cpu(rxcmp->rx_cmp_len_flags_type) >> RX_CMP_LEN_SHIFT;
1567 dma_addr = rx_buf->mapping;
1569 if (bnxt_rx_xdp(bp, rxr, cons, data, &data_ptr, &len, event)) {
1574 if (len <= bp->rx_copy_thresh) {
1575 skb = bnxt_copy_skb(bnapi, data_ptr, len, dma_addr);
1576 bnxt_reuse_rx_data(rxr, cons, data);
1584 if (rx_buf->data_ptr == data_ptr)
1585 payload = misc & RX_CMP_PAYLOAD_OFFSET;
1588 skb = bp->rx_skb_func(bp, rxr, cons, data, data_ptr, dma_addr,
1597 skb = bnxt_rx_pages(bp, bnapi, skb, cp_cons, agg_bufs);
1604 if (RX_CMP_HASH_VALID(rxcmp)) {
1605 u32 hash_type = RX_CMP_HASH_TYPE(rxcmp);
1606 enum pkt_hash_types type = PKT_HASH_TYPE_L4;
1608 /* RSS profiles 1 and 3 with extract code 0 for inner 4-tuple */
1609 if (hash_type != 1 && hash_type != 3)
1610 type = PKT_HASH_TYPE_L3;
1611 skb_set_hash(skb, le32_to_cpu(rxcmp->rx_cmp_rss_hash), type);
1614 cfa_code = RX_CMP_CFA_CODE(rxcmp1);
1615 skb->protocol = eth_type_trans(skb, bnxt_get_pkt_dev(bp, cfa_code));
1617 if ((rxcmp1->rx_cmp_flags2 &
1618 cpu_to_le32(RX_CMP_FLAGS2_META_FORMAT_VLAN)) &&
1619 (skb->dev->features & NETIF_F_HW_VLAN_CTAG_RX)) {
1620 u32 meta_data = le32_to_cpu(rxcmp1->rx_cmp_meta_data);
1621 u16 vtag = meta_data & RX_CMP_FLAGS2_METADATA_VID_MASK;
1622 u16 vlan_proto = meta_data >> RX_CMP_FLAGS2_METADATA_TPID_SFT;
1624 __vlan_hwaccel_put_tag(skb, htons(vlan_proto), vtag);
1627 skb_checksum_none_assert(skb);
1628 if (RX_CMP_L4_CS_OK(rxcmp1)) {
1629 if (dev->features & NETIF_F_RXCSUM) {
1630 skb->ip_summed = CHECKSUM_UNNECESSARY;
1631 skb->csum_level = RX_CMP_ENCAP(rxcmp1);
1634 if (rxcmp1->rx_cmp_cfa_code_errors_v2 & RX_CMP_L4_CS_ERR_BITS) {
1635 if (dev->features & NETIF_F_RXCSUM)
1636 cpr->rx_l4_csum_errors++;
1640 bnxt_deliver_skb(bp, bnapi, skb);
1644 rxr->rx_prod = NEXT_RX(prod);
1645 rxr->rx_next_cons = NEXT_RX(cons);
1648 *raw_cons = tmp_raw_cons;
1653 /* In netpoll mode, if we are using a combined completion ring, we need to
1654 * discard the rx packets and recycle the buffers.
1656 static int bnxt_force_rx_discard(struct bnxt *bp, struct bnxt_napi *bnapi,
1657 u32 *raw_cons, u8 *event)
1659 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1660 u32 tmp_raw_cons = *raw_cons;
1661 struct rx_cmp_ext *rxcmp1;
1662 struct rx_cmp *rxcmp;
1666 cp_cons = RING_CMP(tmp_raw_cons);
1667 rxcmp = (struct rx_cmp *)
1668 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1670 tmp_raw_cons = NEXT_RAW_CMP(tmp_raw_cons);
1671 cp_cons = RING_CMP(tmp_raw_cons);
1672 rxcmp1 = (struct rx_cmp_ext *)
1673 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1675 if (!RX_CMP_VALID(rxcmp1, tmp_raw_cons))
1678 cmp_type = RX_CMP_TYPE(rxcmp);
1679 if (cmp_type == CMP_TYPE_RX_L2_CMP) {
1680 rxcmp1->rx_cmp_cfa_code_errors_v2 |=
1681 cpu_to_le32(RX_CMPL_ERRORS_CRC_ERROR);
1682 } else if (cmp_type == CMP_TYPE_RX_L2_TPA_END_CMP) {
1683 struct rx_tpa_end_cmp_ext *tpa_end1;
1685 tpa_end1 = (struct rx_tpa_end_cmp_ext *)rxcmp1;
1686 tpa_end1->rx_tpa_end_cmp_errors_v2 |=
1687 cpu_to_le32(RX_TPA_END_CMP_ERRORS);
1689 return bnxt_rx_pkt(bp, bnapi, raw_cons, event);
1692 #define BNXT_GET_EVENT_PORT(data) \
1694 ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK)
1696 static int bnxt_async_event_process(struct bnxt *bp,
1697 struct hwrm_async_event_cmpl *cmpl)
1699 u16 event_id = le16_to_cpu(cmpl->event_id);
1701 /* TODO CHIMP_FW: Define event id's for link change, error etc */
1703 case ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE: {
1704 u32 data1 = le32_to_cpu(cmpl->event_data1);
1705 struct bnxt_link_info *link_info = &bp->link_info;
1708 goto async_event_process_exit;
1709 if (data1 & 0x20000) {
1710 u16 fw_speed = link_info->force_link_speed;
1711 u32 speed = bnxt_fw_to_ethtool_speed(fw_speed);
1713 netdev_warn(bp->dev, "Link speed %d no longer supported\n",
1716 set_bit(BNXT_LINK_SPEED_CHNG_SP_EVENT, &bp->sp_event);
1719 case ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE:
1720 set_bit(BNXT_LINK_CHNG_SP_EVENT, &bp->sp_event);
1722 case ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD:
1723 set_bit(BNXT_HWRM_PF_UNLOAD_SP_EVENT, &bp->sp_event);
1725 case ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED: {
1726 u32 data1 = le32_to_cpu(cmpl->event_data1);
1727 u16 port_id = BNXT_GET_EVENT_PORT(data1);
1732 if (bp->pf.port_id != port_id)
1735 set_bit(BNXT_HWRM_PORT_MODULE_SP_EVENT, &bp->sp_event);
1738 case ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE:
1740 goto async_event_process_exit;
1741 set_bit(BNXT_RESET_TASK_SILENT_SP_EVENT, &bp->sp_event);
1744 goto async_event_process_exit;
1746 bnxt_queue_sp_work(bp);
1747 async_event_process_exit:
1748 bnxt_ulp_async_events(bp, cmpl);
1752 static int bnxt_hwrm_handler(struct bnxt *bp, struct tx_cmp *txcmp)
1754 u16 cmpl_type = TX_CMP_TYPE(txcmp), vf_id, seq_id;
1755 struct hwrm_cmpl *h_cmpl = (struct hwrm_cmpl *)txcmp;
1756 struct hwrm_fwd_req_cmpl *fwd_req_cmpl =
1757 (struct hwrm_fwd_req_cmpl *)txcmp;
1759 switch (cmpl_type) {
1760 case CMPL_BASE_TYPE_HWRM_DONE:
1761 seq_id = le16_to_cpu(h_cmpl->sequence_id);
1762 if (seq_id == bp->hwrm_intr_seq_id)
1763 bp->hwrm_intr_seq_id = HWRM_SEQ_ID_INVALID;
1765 netdev_err(bp->dev, "Invalid hwrm seq id %d\n", seq_id);
1768 case CMPL_BASE_TYPE_HWRM_FWD_REQ:
1769 vf_id = le16_to_cpu(fwd_req_cmpl->source_id);
1771 if ((vf_id < bp->pf.first_vf_id) ||
1772 (vf_id >= bp->pf.first_vf_id + bp->pf.active_vfs)) {
1773 netdev_err(bp->dev, "Msg contains invalid VF id %x\n",
1778 set_bit(vf_id - bp->pf.first_vf_id, bp->pf.vf_event_bmap);
1779 set_bit(BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT, &bp->sp_event);
1780 bnxt_queue_sp_work(bp);
1783 case CMPL_BASE_TYPE_HWRM_ASYNC_EVENT:
1784 bnxt_async_event_process(bp,
1785 (struct hwrm_async_event_cmpl *)txcmp);
1794 static irqreturn_t bnxt_msix(int irq, void *dev_instance)
1796 struct bnxt_napi *bnapi = dev_instance;
1797 struct bnxt *bp = bnapi->bp;
1798 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1799 u32 cons = RING_CMP(cpr->cp_raw_cons);
1801 prefetch(&cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]);
1802 napi_schedule(&bnapi->napi);
1806 static inline int bnxt_has_work(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1808 u32 raw_cons = cpr->cp_raw_cons;
1809 u16 cons = RING_CMP(raw_cons);
1810 struct tx_cmp *txcmp;
1812 txcmp = &cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)];
1814 return TX_CMP_VALID(txcmp, raw_cons);
1817 static irqreturn_t bnxt_inta(int irq, void *dev_instance)
1819 struct bnxt_napi *bnapi = dev_instance;
1820 struct bnxt *bp = bnapi->bp;
1821 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1822 u32 cons = RING_CMP(cpr->cp_raw_cons);
1825 prefetch(&cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]);
1827 if (!bnxt_has_work(bp, cpr)) {
1828 int_status = readl(bp->bar0 + BNXT_CAG_REG_LEGACY_INT_STATUS);
1829 /* return if erroneous interrupt */
1830 if (!(int_status & (0x10000 << cpr->cp_ring_struct.fw_ring_id)))
1834 /* disable ring IRQ */
1835 BNXT_CP_DB_IRQ_DIS(cpr->cp_doorbell);
1837 /* Return here if interrupt is shared and is disabled. */
1838 if (unlikely(atomic_read(&bp->intr_sem) != 0))
1841 napi_schedule(&bnapi->napi);
1845 static int bnxt_poll_work(struct bnxt *bp, struct bnxt_napi *bnapi, int budget)
1847 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1848 u32 raw_cons = cpr->cp_raw_cons;
1853 struct tx_cmp *txcmp;
1858 cons = RING_CMP(raw_cons);
1859 txcmp = &cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)];
1861 if (!TX_CMP_VALID(txcmp, raw_cons))
1864 /* The valid test of the entry must be done first before
1865 * reading any further.
1868 if (TX_CMP_TYPE(txcmp) == CMP_TYPE_TX_L2_CMP) {
1870 /* return full budget so NAPI will complete. */
1871 if (unlikely(tx_pkts > bp->tx_wake_thresh))
1873 } else if ((TX_CMP_TYPE(txcmp) & 0x30) == 0x10) {
1875 rc = bnxt_rx_pkt(bp, bnapi, &raw_cons, &event);
1877 rc = bnxt_force_rx_discard(bp, bnapi, &raw_cons,
1879 if (likely(rc >= 0))
1881 /* Increment rx_pkts when rc is -ENOMEM to count towards
1882 * the NAPI budget. Otherwise, we may potentially loop
1883 * here forever if we consistently cannot allocate
1886 else if (rc == -ENOMEM && budget)
1888 else if (rc == -EBUSY) /* partial completion */
1890 } else if (unlikely((TX_CMP_TYPE(txcmp) ==
1891 CMPL_BASE_TYPE_HWRM_DONE) ||
1892 (TX_CMP_TYPE(txcmp) ==
1893 CMPL_BASE_TYPE_HWRM_FWD_REQ) ||
1894 (TX_CMP_TYPE(txcmp) ==
1895 CMPL_BASE_TYPE_HWRM_ASYNC_EVENT))) {
1896 bnxt_hwrm_handler(bp, txcmp);
1898 raw_cons = NEXT_RAW_CMP(raw_cons);
1900 if (rx_pkts == budget)
1904 if (event & BNXT_TX_EVENT) {
1905 struct bnxt_tx_ring_info *txr = bnapi->tx_ring;
1906 void __iomem *db = txr->tx_doorbell;
1907 u16 prod = txr->tx_prod;
1909 /* Sync BD data before updating doorbell */
1912 bnxt_db_write(bp, db, DB_KEY_TX | prod);
1915 cpr->cp_raw_cons = raw_cons;
1916 /* ACK completion ring before freeing tx ring and producing new
1917 * buffers in rx/agg rings to prevent overflowing the completion
1920 BNXT_CP_DB(cpr->cp_doorbell, cpr->cp_raw_cons);
1923 bnapi->tx_int(bp, bnapi, tx_pkts);
1925 if (event & BNXT_RX_EVENT) {
1926 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
1928 bnxt_db_write(bp, rxr->rx_doorbell, DB_KEY_RX | rxr->rx_prod);
1929 if (event & BNXT_AGG_EVENT)
1930 bnxt_db_write(bp, rxr->rx_agg_doorbell,
1931 DB_KEY_RX | rxr->rx_agg_prod);
1936 static int bnxt_poll_nitroa0(struct napi_struct *napi, int budget)
1938 struct bnxt_napi *bnapi = container_of(napi, struct bnxt_napi, napi);
1939 struct bnxt *bp = bnapi->bp;
1940 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1941 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
1942 struct tx_cmp *txcmp;
1943 struct rx_cmp_ext *rxcmp1;
1944 u32 cp_cons, tmp_raw_cons;
1945 u32 raw_cons = cpr->cp_raw_cons;
1952 cp_cons = RING_CMP(raw_cons);
1953 txcmp = &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1955 if (!TX_CMP_VALID(txcmp, raw_cons))
1958 if ((TX_CMP_TYPE(txcmp) & 0x30) == 0x10) {
1959 tmp_raw_cons = NEXT_RAW_CMP(raw_cons);
1960 cp_cons = RING_CMP(tmp_raw_cons);
1961 rxcmp1 = (struct rx_cmp_ext *)
1962 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1964 if (!RX_CMP_VALID(rxcmp1, tmp_raw_cons))
1967 /* force an error to recycle the buffer */
1968 rxcmp1->rx_cmp_cfa_code_errors_v2 |=
1969 cpu_to_le32(RX_CMPL_ERRORS_CRC_ERROR);
1971 rc = bnxt_rx_pkt(bp, bnapi, &raw_cons, &event);
1972 if (likely(rc == -EIO) && budget)
1974 else if (rc == -EBUSY) /* partial completion */
1976 } else if (unlikely(TX_CMP_TYPE(txcmp) ==
1977 CMPL_BASE_TYPE_HWRM_DONE)) {
1978 bnxt_hwrm_handler(bp, txcmp);
1981 "Invalid completion received on special ring\n");
1983 raw_cons = NEXT_RAW_CMP(raw_cons);
1985 if (rx_pkts == budget)
1989 cpr->cp_raw_cons = raw_cons;
1990 BNXT_CP_DB(cpr->cp_doorbell, cpr->cp_raw_cons);
1991 bnxt_db_write(bp, rxr->rx_doorbell, DB_KEY_RX | rxr->rx_prod);
1993 if (event & BNXT_AGG_EVENT)
1994 bnxt_db_write(bp, rxr->rx_agg_doorbell,
1995 DB_KEY_RX | rxr->rx_agg_prod);
1997 if (!bnxt_has_work(bp, cpr) && rx_pkts < budget) {
1998 napi_complete_done(napi, rx_pkts);
1999 BNXT_CP_DB_REARM(cpr->cp_doorbell, cpr->cp_raw_cons);
2004 static int bnxt_poll(struct napi_struct *napi, int budget)
2006 struct bnxt_napi *bnapi = container_of(napi, struct bnxt_napi, napi);
2007 struct bnxt *bp = bnapi->bp;
2008 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
2012 work_done += bnxt_poll_work(bp, bnapi, budget - work_done);
2014 if (work_done >= budget)
2017 if (!bnxt_has_work(bp, cpr)) {
2018 if (napi_complete_done(napi, work_done))
2019 BNXT_CP_DB_REARM(cpr->cp_doorbell,
2028 static void bnxt_free_tx_skbs(struct bnxt *bp)
2031 struct pci_dev *pdev = bp->pdev;
2036 max_idx = bp->tx_nr_pages * TX_DESC_CNT;
2037 for (i = 0; i < bp->tx_nr_rings; i++) {
2038 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
2041 for (j = 0; j < max_idx;) {
2042 struct bnxt_sw_tx_bd *tx_buf = &txr->tx_buf_ring[j];
2043 struct sk_buff *skb = tx_buf->skb;
2053 if (tx_buf->is_push) {
2059 dma_unmap_single(&pdev->dev,
2060 dma_unmap_addr(tx_buf, mapping),
2064 last = tx_buf->nr_frags;
2066 for (k = 0; k < last; k++, j++) {
2067 int ring_idx = j & bp->tx_ring_mask;
2068 skb_frag_t *frag = &skb_shinfo(skb)->frags[k];
2070 tx_buf = &txr->tx_buf_ring[ring_idx];
2073 dma_unmap_addr(tx_buf, mapping),
2074 skb_frag_size(frag), PCI_DMA_TODEVICE);
2078 netdev_tx_reset_queue(netdev_get_tx_queue(bp->dev, i));
2082 static void bnxt_free_rx_skbs(struct bnxt *bp)
2084 int i, max_idx, max_agg_idx;
2085 struct pci_dev *pdev = bp->pdev;
2090 max_idx = bp->rx_nr_pages * RX_DESC_CNT;
2091 max_agg_idx = bp->rx_agg_nr_pages * RX_DESC_CNT;
2092 for (i = 0; i < bp->rx_nr_rings; i++) {
2093 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
2097 for (j = 0; j < MAX_TPA; j++) {
2098 struct bnxt_tpa_info *tpa_info =
2100 u8 *data = tpa_info->data;
2105 dma_unmap_single_attrs(&pdev->dev,
2107 bp->rx_buf_use_size,
2109 DMA_ATTR_WEAK_ORDERING);
2111 tpa_info->data = NULL;
2117 for (j = 0; j < max_idx; j++) {
2118 struct bnxt_sw_rx_bd *rx_buf = &rxr->rx_buf_ring[j];
2119 dma_addr_t mapping = rx_buf->mapping;
2120 void *data = rx_buf->data;
2125 rx_buf->data = NULL;
2127 if (BNXT_RX_PAGE_MODE(bp)) {
2128 mapping -= bp->rx_dma_offset;
2129 dma_unmap_page_attrs(&pdev->dev, mapping,
2130 PAGE_SIZE, bp->rx_dir,
2131 DMA_ATTR_WEAK_ORDERING);
2134 dma_unmap_single_attrs(&pdev->dev, mapping,
2135 bp->rx_buf_use_size,
2137 DMA_ATTR_WEAK_ORDERING);
2142 for (j = 0; j < max_agg_idx; j++) {
2143 struct bnxt_sw_rx_agg_bd *rx_agg_buf =
2144 &rxr->rx_agg_ring[j];
2145 struct page *page = rx_agg_buf->page;
2150 dma_unmap_page_attrs(&pdev->dev, rx_agg_buf->mapping,
2153 DMA_ATTR_WEAK_ORDERING);
2155 rx_agg_buf->page = NULL;
2156 __clear_bit(j, rxr->rx_agg_bmap);
2161 __free_page(rxr->rx_page);
2162 rxr->rx_page = NULL;
2167 static void bnxt_free_skbs(struct bnxt *bp)
2169 bnxt_free_tx_skbs(bp);
2170 bnxt_free_rx_skbs(bp);
2173 static void bnxt_free_ring(struct bnxt *bp, struct bnxt_ring_struct *ring)
2175 struct pci_dev *pdev = bp->pdev;
2178 for (i = 0; i < ring->nr_pages; i++) {
2179 if (!ring->pg_arr[i])
2182 dma_free_coherent(&pdev->dev, ring->page_size,
2183 ring->pg_arr[i], ring->dma_arr[i]);
2185 ring->pg_arr[i] = NULL;
2188 dma_free_coherent(&pdev->dev, ring->nr_pages * 8,
2189 ring->pg_tbl, ring->pg_tbl_map);
2190 ring->pg_tbl = NULL;
2192 if (ring->vmem_size && *ring->vmem) {
2198 static int bnxt_alloc_ring(struct bnxt *bp, struct bnxt_ring_struct *ring)
2201 struct pci_dev *pdev = bp->pdev;
2203 if (ring->nr_pages > 1) {
2204 ring->pg_tbl = dma_alloc_coherent(&pdev->dev,
2212 for (i = 0; i < ring->nr_pages; i++) {
2213 ring->pg_arr[i] = dma_alloc_coherent(&pdev->dev,
2217 if (!ring->pg_arr[i])
2220 if (ring->nr_pages > 1)
2221 ring->pg_tbl[i] = cpu_to_le64(ring->dma_arr[i]);
2224 if (ring->vmem_size) {
2225 *ring->vmem = vzalloc(ring->vmem_size);
2232 static void bnxt_free_rx_rings(struct bnxt *bp)
2239 for (i = 0; i < bp->rx_nr_rings; i++) {
2240 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
2241 struct bnxt_ring_struct *ring;
2244 bpf_prog_put(rxr->xdp_prog);
2249 kfree(rxr->rx_agg_bmap);
2250 rxr->rx_agg_bmap = NULL;
2252 ring = &rxr->rx_ring_struct;
2253 bnxt_free_ring(bp, ring);
2255 ring = &rxr->rx_agg_ring_struct;
2256 bnxt_free_ring(bp, ring);
2260 static int bnxt_alloc_rx_rings(struct bnxt *bp)
2262 int i, rc, agg_rings = 0, tpa_rings = 0;
2267 if (bp->flags & BNXT_FLAG_AGG_RINGS)
2270 if (bp->flags & BNXT_FLAG_TPA)
2273 for (i = 0; i < bp->rx_nr_rings; i++) {
2274 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
2275 struct bnxt_ring_struct *ring;
2277 ring = &rxr->rx_ring_struct;
2279 rc = bnxt_alloc_ring(bp, ring);
2286 ring = &rxr->rx_agg_ring_struct;
2287 rc = bnxt_alloc_ring(bp, ring);
2291 rxr->rx_agg_bmap_size = bp->rx_agg_ring_mask + 1;
2292 mem_size = rxr->rx_agg_bmap_size / 8;
2293 rxr->rx_agg_bmap = kzalloc(mem_size, GFP_KERNEL);
2294 if (!rxr->rx_agg_bmap)
2298 rxr->rx_tpa = kcalloc(MAX_TPA,
2299 sizeof(struct bnxt_tpa_info),
2309 static void bnxt_free_tx_rings(struct bnxt *bp)
2312 struct pci_dev *pdev = bp->pdev;
2317 for (i = 0; i < bp->tx_nr_rings; i++) {
2318 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
2319 struct bnxt_ring_struct *ring;
2322 dma_free_coherent(&pdev->dev, bp->tx_push_size,
2323 txr->tx_push, txr->tx_push_mapping);
2324 txr->tx_push = NULL;
2327 ring = &txr->tx_ring_struct;
2329 bnxt_free_ring(bp, ring);
2333 static int bnxt_alloc_tx_rings(struct bnxt *bp)
2336 struct pci_dev *pdev = bp->pdev;
2338 bp->tx_push_size = 0;
2339 if (bp->tx_push_thresh) {
2342 push_size = L1_CACHE_ALIGN(sizeof(struct tx_push_bd) +
2343 bp->tx_push_thresh);
2345 if (push_size > 256) {
2347 bp->tx_push_thresh = 0;
2350 bp->tx_push_size = push_size;
2353 for (i = 0, j = 0; i < bp->tx_nr_rings; i++) {
2354 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
2355 struct bnxt_ring_struct *ring;
2357 ring = &txr->tx_ring_struct;
2359 rc = bnxt_alloc_ring(bp, ring);
2363 if (bp->tx_push_size) {
2366 /* One pre-allocated DMA buffer to backup
2369 txr->tx_push = dma_alloc_coherent(&pdev->dev,
2371 &txr->tx_push_mapping,
2377 mapping = txr->tx_push_mapping +
2378 sizeof(struct tx_push_bd);
2379 txr->data_mapping = cpu_to_le64(mapping);
2381 memset(txr->tx_push, 0, sizeof(struct tx_push_bd));
2383 ring->queue_id = bp->q_info[j].queue_id;
2384 if (i < bp->tx_nr_rings_xdp)
2386 if (i % bp->tx_nr_rings_per_tc == (bp->tx_nr_rings_per_tc - 1))
2392 static void bnxt_free_cp_rings(struct bnxt *bp)
2399 for (i = 0; i < bp->cp_nr_rings; i++) {
2400 struct bnxt_napi *bnapi = bp->bnapi[i];
2401 struct bnxt_cp_ring_info *cpr;
2402 struct bnxt_ring_struct *ring;
2407 cpr = &bnapi->cp_ring;
2408 ring = &cpr->cp_ring_struct;
2410 bnxt_free_ring(bp, ring);
2414 static int bnxt_alloc_cp_rings(struct bnxt *bp)
2418 for (i = 0; i < bp->cp_nr_rings; i++) {
2419 struct bnxt_napi *bnapi = bp->bnapi[i];
2420 struct bnxt_cp_ring_info *cpr;
2421 struct bnxt_ring_struct *ring;
2426 cpr = &bnapi->cp_ring;
2427 ring = &cpr->cp_ring_struct;
2429 rc = bnxt_alloc_ring(bp, ring);
2436 static void bnxt_init_ring_struct(struct bnxt *bp)
2440 for (i = 0; i < bp->cp_nr_rings; i++) {
2441 struct bnxt_napi *bnapi = bp->bnapi[i];
2442 struct bnxt_cp_ring_info *cpr;
2443 struct bnxt_rx_ring_info *rxr;
2444 struct bnxt_tx_ring_info *txr;
2445 struct bnxt_ring_struct *ring;
2450 cpr = &bnapi->cp_ring;
2451 ring = &cpr->cp_ring_struct;
2452 ring->nr_pages = bp->cp_nr_pages;
2453 ring->page_size = HW_CMPD_RING_SIZE;
2454 ring->pg_arr = (void **)cpr->cp_desc_ring;
2455 ring->dma_arr = cpr->cp_desc_mapping;
2456 ring->vmem_size = 0;
2458 rxr = bnapi->rx_ring;
2462 ring = &rxr->rx_ring_struct;
2463 ring->nr_pages = bp->rx_nr_pages;
2464 ring->page_size = HW_RXBD_RING_SIZE;
2465 ring->pg_arr = (void **)rxr->rx_desc_ring;
2466 ring->dma_arr = rxr->rx_desc_mapping;
2467 ring->vmem_size = SW_RXBD_RING_SIZE * bp->rx_nr_pages;
2468 ring->vmem = (void **)&rxr->rx_buf_ring;
2470 ring = &rxr->rx_agg_ring_struct;
2471 ring->nr_pages = bp->rx_agg_nr_pages;
2472 ring->page_size = HW_RXBD_RING_SIZE;
2473 ring->pg_arr = (void **)rxr->rx_agg_desc_ring;
2474 ring->dma_arr = rxr->rx_agg_desc_mapping;
2475 ring->vmem_size = SW_RXBD_AGG_RING_SIZE * bp->rx_agg_nr_pages;
2476 ring->vmem = (void **)&rxr->rx_agg_ring;
2479 txr = bnapi->tx_ring;
2483 ring = &txr->tx_ring_struct;
2484 ring->nr_pages = bp->tx_nr_pages;
2485 ring->page_size = HW_RXBD_RING_SIZE;
2486 ring->pg_arr = (void **)txr->tx_desc_ring;
2487 ring->dma_arr = txr->tx_desc_mapping;
2488 ring->vmem_size = SW_TXBD_RING_SIZE * bp->tx_nr_pages;
2489 ring->vmem = (void **)&txr->tx_buf_ring;
2493 static void bnxt_init_rxbd_pages(struct bnxt_ring_struct *ring, u32 type)
2497 struct rx_bd **rx_buf_ring;
2499 rx_buf_ring = (struct rx_bd **)ring->pg_arr;
2500 for (i = 0, prod = 0; i < ring->nr_pages; i++) {
2504 rxbd = rx_buf_ring[i];
2508 for (j = 0; j < RX_DESC_CNT; j++, rxbd++, prod++) {
2509 rxbd->rx_bd_len_flags_type = cpu_to_le32(type);
2510 rxbd->rx_bd_opaque = prod;
2515 static int bnxt_init_one_rx_ring(struct bnxt *bp, int ring_nr)
2517 struct net_device *dev = bp->dev;
2518 struct bnxt_rx_ring_info *rxr;
2519 struct bnxt_ring_struct *ring;
2523 type = (bp->rx_buf_use_size << RX_BD_LEN_SHIFT) |
2524 RX_BD_TYPE_RX_PACKET_BD | RX_BD_FLAGS_EOP;
2526 if (NET_IP_ALIGN == 2)
2527 type |= RX_BD_FLAGS_SOP;
2529 rxr = &bp->rx_ring[ring_nr];
2530 ring = &rxr->rx_ring_struct;
2531 bnxt_init_rxbd_pages(ring, type);
2533 if (BNXT_RX_PAGE_MODE(bp) && bp->xdp_prog) {
2534 rxr->xdp_prog = bpf_prog_add(bp->xdp_prog, 1);
2535 if (IS_ERR(rxr->xdp_prog)) {
2536 int rc = PTR_ERR(rxr->xdp_prog);
2538 rxr->xdp_prog = NULL;
2542 prod = rxr->rx_prod;
2543 for (i = 0; i < bp->rx_ring_size; i++) {
2544 if (bnxt_alloc_rx_data(bp, rxr, prod, GFP_KERNEL) != 0) {
2545 netdev_warn(dev, "init'ed rx ring %d with %d/%d skbs only\n",
2546 ring_nr, i, bp->rx_ring_size);
2549 prod = NEXT_RX(prod);
2551 rxr->rx_prod = prod;
2552 ring->fw_ring_id = INVALID_HW_RING_ID;
2554 ring = &rxr->rx_agg_ring_struct;
2555 ring->fw_ring_id = INVALID_HW_RING_ID;
2557 if (!(bp->flags & BNXT_FLAG_AGG_RINGS))
2560 type = ((u32)BNXT_RX_PAGE_SIZE << RX_BD_LEN_SHIFT) |
2561 RX_BD_TYPE_RX_AGG_BD | RX_BD_FLAGS_SOP;
2563 bnxt_init_rxbd_pages(ring, type);
2565 prod = rxr->rx_agg_prod;
2566 for (i = 0; i < bp->rx_agg_ring_size; i++) {
2567 if (bnxt_alloc_rx_page(bp, rxr, prod, GFP_KERNEL) != 0) {
2568 netdev_warn(dev, "init'ed rx ring %d with %d/%d pages only\n",
2569 ring_nr, i, bp->rx_ring_size);
2572 prod = NEXT_RX_AGG(prod);
2574 rxr->rx_agg_prod = prod;
2576 if (bp->flags & BNXT_FLAG_TPA) {
2581 for (i = 0; i < MAX_TPA; i++) {
2582 data = __bnxt_alloc_rx_data(bp, &mapping,
2587 rxr->rx_tpa[i].data = data;
2588 rxr->rx_tpa[i].data_ptr = data + bp->rx_offset;
2589 rxr->rx_tpa[i].mapping = mapping;
2592 netdev_err(bp->dev, "No resource allocated for LRO/GRO\n");
2600 static void bnxt_init_cp_rings(struct bnxt *bp)
2604 for (i = 0; i < bp->cp_nr_rings; i++) {
2605 struct bnxt_cp_ring_info *cpr = &bp->bnapi[i]->cp_ring;
2606 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct;
2608 ring->fw_ring_id = INVALID_HW_RING_ID;
2612 static int bnxt_init_rx_rings(struct bnxt *bp)
2616 if (BNXT_RX_PAGE_MODE(bp)) {
2617 bp->rx_offset = NET_IP_ALIGN + XDP_PACKET_HEADROOM;
2618 bp->rx_dma_offset = XDP_PACKET_HEADROOM;
2620 bp->rx_offset = BNXT_RX_OFFSET;
2621 bp->rx_dma_offset = BNXT_RX_DMA_OFFSET;
2624 for (i = 0; i < bp->rx_nr_rings; i++) {
2625 rc = bnxt_init_one_rx_ring(bp, i);
2633 static int bnxt_init_tx_rings(struct bnxt *bp)
2637 bp->tx_wake_thresh = max_t(int, bp->tx_ring_size / 2,
2640 for (i = 0; i < bp->tx_nr_rings; i++) {
2641 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
2642 struct bnxt_ring_struct *ring = &txr->tx_ring_struct;
2644 ring->fw_ring_id = INVALID_HW_RING_ID;
2650 static void bnxt_free_ring_grps(struct bnxt *bp)
2652 kfree(bp->grp_info);
2653 bp->grp_info = NULL;
2656 static int bnxt_init_ring_grps(struct bnxt *bp, bool irq_re_init)
2661 bp->grp_info = kcalloc(bp->cp_nr_rings,
2662 sizeof(struct bnxt_ring_grp_info),
2667 for (i = 0; i < bp->cp_nr_rings; i++) {
2669 bp->grp_info[i].fw_stats_ctx = INVALID_HW_RING_ID;
2670 bp->grp_info[i].fw_grp_id = INVALID_HW_RING_ID;
2671 bp->grp_info[i].rx_fw_ring_id = INVALID_HW_RING_ID;
2672 bp->grp_info[i].agg_fw_ring_id = INVALID_HW_RING_ID;
2673 bp->grp_info[i].cp_fw_ring_id = INVALID_HW_RING_ID;
2678 static void bnxt_free_vnics(struct bnxt *bp)
2680 kfree(bp->vnic_info);
2681 bp->vnic_info = NULL;
2685 static int bnxt_alloc_vnics(struct bnxt *bp)
2689 #ifdef CONFIG_RFS_ACCEL
2690 if (bp->flags & BNXT_FLAG_RFS)
2691 num_vnics += bp->rx_nr_rings;
2694 if (BNXT_CHIP_TYPE_NITRO_A0(bp))
2697 bp->vnic_info = kcalloc(num_vnics, sizeof(struct bnxt_vnic_info),
2702 bp->nr_vnics = num_vnics;
2706 static void bnxt_init_vnics(struct bnxt *bp)
2710 for (i = 0; i < bp->nr_vnics; i++) {
2711 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2713 vnic->fw_vnic_id = INVALID_HW_RING_ID;
2714 vnic->fw_rss_cos_lb_ctx[0] = INVALID_HW_RING_ID;
2715 vnic->fw_rss_cos_lb_ctx[1] = INVALID_HW_RING_ID;
2716 vnic->fw_l2_ctx_id = INVALID_HW_RING_ID;
2718 if (bp->vnic_info[i].rss_hash_key) {
2720 prandom_bytes(vnic->rss_hash_key,
2723 memcpy(vnic->rss_hash_key,
2724 bp->vnic_info[0].rss_hash_key,
2730 static int bnxt_calc_nr_ring_pages(u32 ring_size, int desc_per_pg)
2734 pages = ring_size / desc_per_pg;
2741 while (pages & (pages - 1))
2747 void bnxt_set_tpa_flags(struct bnxt *bp)
2749 bp->flags &= ~BNXT_FLAG_TPA;
2750 if (bp->flags & BNXT_FLAG_NO_AGG_RINGS)
2752 if (bp->dev->features & NETIF_F_LRO)
2753 bp->flags |= BNXT_FLAG_LRO;
2754 if (bp->dev->features & NETIF_F_GRO)
2755 bp->flags |= BNXT_FLAG_GRO;
2758 /* bp->rx_ring_size, bp->tx_ring_size, dev->mtu, BNXT_FLAG_{G|L}RO flags must
2761 void bnxt_set_ring_params(struct bnxt *bp)
2763 u32 ring_size, rx_size, rx_space;
2764 u32 agg_factor = 0, agg_ring_size = 0;
2766 /* 8 for CRC and VLAN */
2767 rx_size = SKB_DATA_ALIGN(bp->dev->mtu + ETH_HLEN + NET_IP_ALIGN + 8);
2769 rx_space = rx_size + NET_SKB_PAD +
2770 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
2772 bp->rx_copy_thresh = BNXT_RX_COPY_THRESH;
2773 ring_size = bp->rx_ring_size;
2774 bp->rx_agg_ring_size = 0;
2775 bp->rx_agg_nr_pages = 0;
2777 if (bp->flags & BNXT_FLAG_TPA)
2778 agg_factor = min_t(u32, 4, 65536 / BNXT_RX_PAGE_SIZE);
2780 bp->flags &= ~BNXT_FLAG_JUMBO;
2781 if (rx_space > PAGE_SIZE && !(bp->flags & BNXT_FLAG_NO_AGG_RINGS)) {
2784 bp->flags |= BNXT_FLAG_JUMBO;
2785 jumbo_factor = PAGE_ALIGN(bp->dev->mtu - 40) >> PAGE_SHIFT;
2786 if (jumbo_factor > agg_factor)
2787 agg_factor = jumbo_factor;
2789 agg_ring_size = ring_size * agg_factor;
2791 if (agg_ring_size) {
2792 bp->rx_agg_nr_pages = bnxt_calc_nr_ring_pages(agg_ring_size,
2794 if (bp->rx_agg_nr_pages > MAX_RX_AGG_PAGES) {
2795 u32 tmp = agg_ring_size;
2797 bp->rx_agg_nr_pages = MAX_RX_AGG_PAGES;
2798 agg_ring_size = MAX_RX_AGG_PAGES * RX_DESC_CNT - 1;
2799 netdev_warn(bp->dev, "rx agg ring size %d reduced to %d.\n",
2800 tmp, agg_ring_size);
2802 bp->rx_agg_ring_size = agg_ring_size;
2803 bp->rx_agg_ring_mask = (bp->rx_agg_nr_pages * RX_DESC_CNT) - 1;
2804 rx_size = SKB_DATA_ALIGN(BNXT_RX_COPY_THRESH + NET_IP_ALIGN);
2805 rx_space = rx_size + NET_SKB_PAD +
2806 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
2809 bp->rx_buf_use_size = rx_size;
2810 bp->rx_buf_size = rx_space;
2812 bp->rx_nr_pages = bnxt_calc_nr_ring_pages(ring_size, RX_DESC_CNT);
2813 bp->rx_ring_mask = (bp->rx_nr_pages * RX_DESC_CNT) - 1;
2815 ring_size = bp->tx_ring_size;
2816 bp->tx_nr_pages = bnxt_calc_nr_ring_pages(ring_size, TX_DESC_CNT);
2817 bp->tx_ring_mask = (bp->tx_nr_pages * TX_DESC_CNT) - 1;
2819 ring_size = bp->rx_ring_size * (2 + agg_factor) + bp->tx_ring_size;
2820 bp->cp_ring_size = ring_size;
2822 bp->cp_nr_pages = bnxt_calc_nr_ring_pages(ring_size, CP_DESC_CNT);
2823 if (bp->cp_nr_pages > MAX_CP_PAGES) {
2824 bp->cp_nr_pages = MAX_CP_PAGES;
2825 bp->cp_ring_size = MAX_CP_PAGES * CP_DESC_CNT - 1;
2826 netdev_warn(bp->dev, "completion ring size %d reduced to %d.\n",
2827 ring_size, bp->cp_ring_size);
2829 bp->cp_bit = bp->cp_nr_pages * CP_DESC_CNT;
2830 bp->cp_ring_mask = bp->cp_bit - 1;
2833 int bnxt_set_rx_skb_mode(struct bnxt *bp, bool page_mode)
2836 if (bp->dev->mtu > BNXT_MAX_PAGE_MODE_MTU)
2839 min_t(u16, bp->max_mtu, BNXT_MAX_PAGE_MODE_MTU);
2840 bp->flags &= ~BNXT_FLAG_AGG_RINGS;
2841 bp->flags |= BNXT_FLAG_NO_AGG_RINGS | BNXT_FLAG_RX_PAGE_MODE;
2842 bp->dev->hw_features &= ~NETIF_F_LRO;
2843 bp->dev->features &= ~NETIF_F_LRO;
2844 bp->rx_dir = DMA_BIDIRECTIONAL;
2845 bp->rx_skb_func = bnxt_rx_page_skb;
2847 bp->dev->max_mtu = bp->max_mtu;
2848 bp->flags &= ~BNXT_FLAG_RX_PAGE_MODE;
2849 bp->rx_dir = DMA_FROM_DEVICE;
2850 bp->rx_skb_func = bnxt_rx_skb;
2855 static void bnxt_free_vnic_attributes(struct bnxt *bp)
2858 struct bnxt_vnic_info *vnic;
2859 struct pci_dev *pdev = bp->pdev;
2864 for (i = 0; i < bp->nr_vnics; i++) {
2865 vnic = &bp->vnic_info[i];
2867 kfree(vnic->fw_grp_ids);
2868 vnic->fw_grp_ids = NULL;
2870 kfree(vnic->uc_list);
2871 vnic->uc_list = NULL;
2873 if (vnic->mc_list) {
2874 dma_free_coherent(&pdev->dev, vnic->mc_list_size,
2875 vnic->mc_list, vnic->mc_list_mapping);
2876 vnic->mc_list = NULL;
2879 if (vnic->rss_table) {
2880 dma_free_coherent(&pdev->dev, PAGE_SIZE,
2882 vnic->rss_table_dma_addr);
2883 vnic->rss_table = NULL;
2886 vnic->rss_hash_key = NULL;
2891 static int bnxt_alloc_vnic_attributes(struct bnxt *bp)
2893 int i, rc = 0, size;
2894 struct bnxt_vnic_info *vnic;
2895 struct pci_dev *pdev = bp->pdev;
2898 for (i = 0; i < bp->nr_vnics; i++) {
2899 vnic = &bp->vnic_info[i];
2901 if (vnic->flags & BNXT_VNIC_UCAST_FLAG) {
2902 int mem_size = (BNXT_MAX_UC_ADDRS - 1) * ETH_ALEN;
2905 vnic->uc_list = kmalloc(mem_size, GFP_KERNEL);
2906 if (!vnic->uc_list) {
2913 if (vnic->flags & BNXT_VNIC_MCAST_FLAG) {
2914 vnic->mc_list_size = BNXT_MAX_MC_ADDRS * ETH_ALEN;
2916 dma_alloc_coherent(&pdev->dev,
2918 &vnic->mc_list_mapping,
2920 if (!vnic->mc_list) {
2926 if (vnic->flags & BNXT_VNIC_RSS_FLAG)
2927 max_rings = bp->rx_nr_rings;
2931 vnic->fw_grp_ids = kcalloc(max_rings, sizeof(u16), GFP_KERNEL);
2932 if (!vnic->fw_grp_ids) {
2937 if ((bp->flags & BNXT_FLAG_NEW_RSS_CAP) &&
2938 !(vnic->flags & BNXT_VNIC_RSS_FLAG))
2941 /* Allocate rss table and hash key */
2942 vnic->rss_table = dma_alloc_coherent(&pdev->dev, PAGE_SIZE,
2943 &vnic->rss_table_dma_addr,
2945 if (!vnic->rss_table) {
2950 size = L1_CACHE_ALIGN(HW_HASH_INDEX_SIZE * sizeof(u16));
2952 vnic->rss_hash_key = ((void *)vnic->rss_table) + size;
2953 vnic->rss_hash_key_dma_addr = vnic->rss_table_dma_addr + size;
2961 static void bnxt_free_hwrm_resources(struct bnxt *bp)
2963 struct pci_dev *pdev = bp->pdev;
2965 dma_free_coherent(&pdev->dev, PAGE_SIZE, bp->hwrm_cmd_resp_addr,
2966 bp->hwrm_cmd_resp_dma_addr);
2968 bp->hwrm_cmd_resp_addr = NULL;
2969 if (bp->hwrm_dbg_resp_addr) {
2970 dma_free_coherent(&pdev->dev, HWRM_DBG_REG_BUF_SIZE,
2971 bp->hwrm_dbg_resp_addr,
2972 bp->hwrm_dbg_resp_dma_addr);
2974 bp->hwrm_dbg_resp_addr = NULL;
2978 static int bnxt_alloc_hwrm_resources(struct bnxt *bp)
2980 struct pci_dev *pdev = bp->pdev;
2982 bp->hwrm_cmd_resp_addr = dma_alloc_coherent(&pdev->dev, PAGE_SIZE,
2983 &bp->hwrm_cmd_resp_dma_addr,
2985 if (!bp->hwrm_cmd_resp_addr)
2987 bp->hwrm_dbg_resp_addr = dma_alloc_coherent(&pdev->dev,
2988 HWRM_DBG_REG_BUF_SIZE,
2989 &bp->hwrm_dbg_resp_dma_addr,
2991 if (!bp->hwrm_dbg_resp_addr)
2992 netdev_warn(bp->dev, "fail to alloc debug register dma mem\n");
2997 static void bnxt_free_hwrm_short_cmd_req(struct bnxt *bp)
2999 if (bp->hwrm_short_cmd_req_addr) {
3000 struct pci_dev *pdev = bp->pdev;
3002 dma_free_coherent(&pdev->dev, BNXT_HWRM_MAX_REQ_LEN,
3003 bp->hwrm_short_cmd_req_addr,
3004 bp->hwrm_short_cmd_req_dma_addr);
3005 bp->hwrm_short_cmd_req_addr = NULL;
3009 static int bnxt_alloc_hwrm_short_cmd_req(struct bnxt *bp)
3011 struct pci_dev *pdev = bp->pdev;
3013 bp->hwrm_short_cmd_req_addr =
3014 dma_alloc_coherent(&pdev->dev, BNXT_HWRM_MAX_REQ_LEN,
3015 &bp->hwrm_short_cmd_req_dma_addr,
3017 if (!bp->hwrm_short_cmd_req_addr)
3023 static void bnxt_free_stats(struct bnxt *bp)
3026 struct pci_dev *pdev = bp->pdev;
3028 if (bp->hw_rx_port_stats) {
3029 dma_free_coherent(&pdev->dev, bp->hw_port_stats_size,
3030 bp->hw_rx_port_stats,
3031 bp->hw_rx_port_stats_map);
3032 bp->hw_rx_port_stats = NULL;
3033 bp->flags &= ~BNXT_FLAG_PORT_STATS;
3039 size = sizeof(struct ctx_hw_stats);
3041 for (i = 0; i < bp->cp_nr_rings; i++) {
3042 struct bnxt_napi *bnapi = bp->bnapi[i];
3043 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
3045 if (cpr->hw_stats) {
3046 dma_free_coherent(&pdev->dev, size, cpr->hw_stats,
3048 cpr->hw_stats = NULL;
3053 static int bnxt_alloc_stats(struct bnxt *bp)
3056 struct pci_dev *pdev = bp->pdev;
3058 size = sizeof(struct ctx_hw_stats);
3060 for (i = 0; i < bp->cp_nr_rings; i++) {
3061 struct bnxt_napi *bnapi = bp->bnapi[i];
3062 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
3064 cpr->hw_stats = dma_alloc_coherent(&pdev->dev, size,
3070 cpr->hw_stats_ctx_id = INVALID_STATS_CTX_ID;
3073 if (BNXT_PF(bp) && bp->chip_num != CHIP_NUM_58700) {
3074 bp->hw_port_stats_size = sizeof(struct rx_port_stats) +
3075 sizeof(struct tx_port_stats) + 1024;
3077 bp->hw_rx_port_stats =
3078 dma_alloc_coherent(&pdev->dev, bp->hw_port_stats_size,
3079 &bp->hw_rx_port_stats_map,
3081 if (!bp->hw_rx_port_stats)
3084 bp->hw_tx_port_stats = (void *)(bp->hw_rx_port_stats + 1) +
3086 bp->hw_tx_port_stats_map = bp->hw_rx_port_stats_map +
3087 sizeof(struct rx_port_stats) + 512;
3088 bp->flags |= BNXT_FLAG_PORT_STATS;
3093 static void bnxt_clear_ring_indices(struct bnxt *bp)
3100 for (i = 0; i < bp->cp_nr_rings; i++) {
3101 struct bnxt_napi *bnapi = bp->bnapi[i];
3102 struct bnxt_cp_ring_info *cpr;
3103 struct bnxt_rx_ring_info *rxr;
3104 struct bnxt_tx_ring_info *txr;
3109 cpr = &bnapi->cp_ring;
3110 cpr->cp_raw_cons = 0;
3112 txr = bnapi->tx_ring;
3118 rxr = bnapi->rx_ring;
3121 rxr->rx_agg_prod = 0;
3122 rxr->rx_sw_agg_prod = 0;
3123 rxr->rx_next_cons = 0;
3128 static void bnxt_free_ntp_fltrs(struct bnxt *bp, bool irq_reinit)
3130 #ifdef CONFIG_RFS_ACCEL
3133 /* Under rtnl_lock and all our NAPIs have been disabled. It's
3134 * safe to delete the hash table.
3136 for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) {
3137 struct hlist_head *head;
3138 struct hlist_node *tmp;
3139 struct bnxt_ntuple_filter *fltr;
3141 head = &bp->ntp_fltr_hash_tbl[i];
3142 hlist_for_each_entry_safe(fltr, tmp, head, hash) {
3143 hlist_del(&fltr->hash);
3148 kfree(bp->ntp_fltr_bmap);
3149 bp->ntp_fltr_bmap = NULL;
3151 bp->ntp_fltr_count = 0;
3155 static int bnxt_alloc_ntp_fltrs(struct bnxt *bp)
3157 #ifdef CONFIG_RFS_ACCEL
3160 if (!(bp->flags & BNXT_FLAG_RFS))
3163 for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++)
3164 INIT_HLIST_HEAD(&bp->ntp_fltr_hash_tbl[i]);
3166 bp->ntp_fltr_count = 0;
3167 bp->ntp_fltr_bmap = kcalloc(BITS_TO_LONGS(BNXT_NTP_FLTR_MAX_FLTR),
3171 if (!bp->ntp_fltr_bmap)
3180 static void bnxt_free_mem(struct bnxt *bp, bool irq_re_init)
3182 bnxt_free_vnic_attributes(bp);
3183 bnxt_free_tx_rings(bp);
3184 bnxt_free_rx_rings(bp);
3185 bnxt_free_cp_rings(bp);
3186 bnxt_free_ntp_fltrs(bp, irq_re_init);
3188 bnxt_free_stats(bp);
3189 bnxt_free_ring_grps(bp);
3190 bnxt_free_vnics(bp);
3191 kfree(bp->tx_ring_map);
3192 bp->tx_ring_map = NULL;
3200 bnxt_clear_ring_indices(bp);
3204 static int bnxt_alloc_mem(struct bnxt *bp, bool irq_re_init)
3206 int i, j, rc, size, arr_size;
3210 /* Allocate bnapi mem pointer array and mem block for
3213 arr_size = L1_CACHE_ALIGN(sizeof(struct bnxt_napi *) *
3215 size = L1_CACHE_ALIGN(sizeof(struct bnxt_napi));
3216 bnapi = kzalloc(arr_size + size * bp->cp_nr_rings, GFP_KERNEL);
3222 for (i = 0; i < bp->cp_nr_rings; i++, bnapi += size) {
3223 bp->bnapi[i] = bnapi;
3224 bp->bnapi[i]->index = i;
3225 bp->bnapi[i]->bp = bp;
3228 bp->rx_ring = kcalloc(bp->rx_nr_rings,
3229 sizeof(struct bnxt_rx_ring_info),
3234 for (i = 0; i < bp->rx_nr_rings; i++) {
3235 bp->rx_ring[i].bnapi = bp->bnapi[i];
3236 bp->bnapi[i]->rx_ring = &bp->rx_ring[i];
3239 bp->tx_ring = kcalloc(bp->tx_nr_rings,
3240 sizeof(struct bnxt_tx_ring_info),
3245 bp->tx_ring_map = kcalloc(bp->tx_nr_rings, sizeof(u16),
3248 if (!bp->tx_ring_map)
3251 if (bp->flags & BNXT_FLAG_SHARED_RINGS)
3254 j = bp->rx_nr_rings;
3256 for (i = 0; i < bp->tx_nr_rings; i++, j++) {
3257 bp->tx_ring[i].bnapi = bp->bnapi[j];
3258 bp->bnapi[j]->tx_ring = &bp->tx_ring[i];
3259 bp->tx_ring_map[i] = bp->tx_nr_rings_xdp + i;
3260 if (i >= bp->tx_nr_rings_xdp) {
3261 bp->tx_ring[i].txq_index = i -
3262 bp->tx_nr_rings_xdp;
3263 bp->bnapi[j]->tx_int = bnxt_tx_int;
3265 bp->bnapi[j]->flags |= BNXT_NAPI_FLAG_XDP;
3266 bp->bnapi[j]->tx_int = bnxt_tx_int_xdp;
3270 rc = bnxt_alloc_stats(bp);
3274 rc = bnxt_alloc_ntp_fltrs(bp);
3278 rc = bnxt_alloc_vnics(bp);
3283 bnxt_init_ring_struct(bp);
3285 rc = bnxt_alloc_rx_rings(bp);
3289 rc = bnxt_alloc_tx_rings(bp);
3293 rc = bnxt_alloc_cp_rings(bp);
3297 bp->vnic_info[0].flags |= BNXT_VNIC_RSS_FLAG | BNXT_VNIC_MCAST_FLAG |
3298 BNXT_VNIC_UCAST_FLAG;
3299 rc = bnxt_alloc_vnic_attributes(bp);
3305 bnxt_free_mem(bp, true);
3309 static void bnxt_disable_int(struct bnxt *bp)
3316 for (i = 0; i < bp->cp_nr_rings; i++) {
3317 struct bnxt_napi *bnapi = bp->bnapi[i];
3318 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
3319 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct;
3321 if (ring->fw_ring_id != INVALID_HW_RING_ID)
3322 BNXT_CP_DB(cpr->cp_doorbell, cpr->cp_raw_cons);
3326 static void bnxt_disable_int_sync(struct bnxt *bp)
3330 atomic_inc(&bp->intr_sem);
3332 bnxt_disable_int(bp);
3333 for (i = 0; i < bp->cp_nr_rings; i++)
3334 synchronize_irq(bp->irq_tbl[i].vector);
3337 static void bnxt_enable_int(struct bnxt *bp)
3341 atomic_set(&bp->intr_sem, 0);
3342 for (i = 0; i < bp->cp_nr_rings; i++) {
3343 struct bnxt_napi *bnapi = bp->bnapi[i];
3344 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
3346 BNXT_CP_DB_REARM(cpr->cp_doorbell, cpr->cp_raw_cons);
3350 void bnxt_hwrm_cmd_hdr_init(struct bnxt *bp, void *request, u16 req_type,
3351 u16 cmpl_ring, u16 target_id)
3353 struct input *req = request;
3355 req->req_type = cpu_to_le16(req_type);
3356 req->cmpl_ring = cpu_to_le16(cmpl_ring);
3357 req->target_id = cpu_to_le16(target_id);
3358 req->resp_addr = cpu_to_le64(bp->hwrm_cmd_resp_dma_addr);
3361 static int bnxt_hwrm_do_send_msg(struct bnxt *bp, void *msg, u32 msg_len,
3362 int timeout, bool silent)
3364 int i, intr_process, rc, tmo_count;
3365 struct input *req = msg;
3367 __le32 *resp_len, *valid;
3368 u16 cp_ring_id, len = 0;
3369 struct hwrm_err_output *resp = bp->hwrm_cmd_resp_addr;
3370 u16 max_req_len = BNXT_HWRM_MAX_REQ_LEN;
3371 struct hwrm_short_input short_input = {0};
3373 req->seq_id = cpu_to_le16(bp->hwrm_cmd_seq++);
3374 memset(resp, 0, PAGE_SIZE);
3375 cp_ring_id = le16_to_cpu(req->cmpl_ring);
3376 intr_process = (cp_ring_id == INVALID_HW_RING_ID) ? 0 : 1;
3378 if (bp->flags & BNXT_FLAG_SHORT_CMD) {
3379 void *short_cmd_req = bp->hwrm_short_cmd_req_addr;
3381 memcpy(short_cmd_req, req, msg_len);
3382 memset(short_cmd_req + msg_len, 0, BNXT_HWRM_MAX_REQ_LEN -
3385 short_input.req_type = req->req_type;
3386 short_input.signature =
3387 cpu_to_le16(SHORT_REQ_SIGNATURE_SHORT_CMD);
3388 short_input.size = cpu_to_le16(msg_len);
3389 short_input.req_addr =
3390 cpu_to_le64(bp->hwrm_short_cmd_req_dma_addr);
3392 data = (u32 *)&short_input;
3393 msg_len = sizeof(short_input);
3395 /* Sync memory write before updating doorbell */
3398 max_req_len = BNXT_HWRM_SHORT_REQ_LEN;
3401 /* Write request msg to hwrm channel */
3402 __iowrite32_copy(bp->bar0, data, msg_len / 4);
3404 for (i = msg_len; i < max_req_len; i += 4)
3405 writel(0, bp->bar0 + i);
3407 /* currently supports only one outstanding message */
3409 bp->hwrm_intr_seq_id = le16_to_cpu(req->seq_id);
3411 /* Ring channel doorbell */
3412 writel(1, bp->bar0 + 0x100);
3415 timeout = DFLT_HWRM_CMD_TIMEOUT;
3418 tmo_count = timeout * 40;
3420 /* Wait until hwrm response cmpl interrupt is processed */
3421 while (bp->hwrm_intr_seq_id != HWRM_SEQ_ID_INVALID &&
3423 usleep_range(25, 40);
3426 if (bp->hwrm_intr_seq_id != HWRM_SEQ_ID_INVALID) {
3427 netdev_err(bp->dev, "Resp cmpl intr err msg: 0x%x\n",
3428 le16_to_cpu(req->req_type));
3432 /* Check if response len is updated */
3433 resp_len = bp->hwrm_cmd_resp_addr + HWRM_RESP_LEN_OFFSET;
3434 for (i = 0; i < tmo_count; i++) {
3435 len = (le32_to_cpu(*resp_len) & HWRM_RESP_LEN_MASK) >>
3439 usleep_range(25, 40);
3442 if (i >= tmo_count) {
3443 netdev_err(bp->dev, "Error (timeout: %d) msg {0x%x 0x%x} len:%d\n",
3444 timeout, le16_to_cpu(req->req_type),
3445 le16_to_cpu(req->seq_id), len);
3449 /* Last word of resp contains valid bit */
3450 valid = bp->hwrm_cmd_resp_addr + len - 4;
3451 for (i = 0; i < 5; i++) {
3452 if (le32_to_cpu(*valid) & HWRM_RESP_VALID_MASK)
3458 netdev_err(bp->dev, "Error (timeout: %d) msg {0x%x 0x%x} len:%d v:%d\n",
3459 timeout, le16_to_cpu(req->req_type),
3460 le16_to_cpu(req->seq_id), len, *valid);
3465 rc = le16_to_cpu(resp->error_code);
3467 netdev_err(bp->dev, "hwrm req_type 0x%x seq id 0x%x error 0x%x\n",
3468 le16_to_cpu(resp->req_type),
3469 le16_to_cpu(resp->seq_id), rc);
3473 int _hwrm_send_message(struct bnxt *bp, void *msg, u32 msg_len, int timeout)
3475 return bnxt_hwrm_do_send_msg(bp, msg, msg_len, timeout, false);
3478 int _hwrm_send_message_silent(struct bnxt *bp, void *msg, u32 msg_len,
3481 return bnxt_hwrm_do_send_msg(bp, msg, msg_len, timeout, true);
3484 int hwrm_send_message(struct bnxt *bp, void *msg, u32 msg_len, int timeout)
3488 mutex_lock(&bp->hwrm_cmd_lock);
3489 rc = _hwrm_send_message(bp, msg, msg_len, timeout);
3490 mutex_unlock(&bp->hwrm_cmd_lock);
3494 int hwrm_send_message_silent(struct bnxt *bp, void *msg, u32 msg_len,
3499 mutex_lock(&bp->hwrm_cmd_lock);
3500 rc = bnxt_hwrm_do_send_msg(bp, msg, msg_len, timeout, true);
3501 mutex_unlock(&bp->hwrm_cmd_lock);
3505 int bnxt_hwrm_func_rgtr_async_events(struct bnxt *bp, unsigned long *bmap,
3508 struct hwrm_func_drv_rgtr_input req = {0};
3509 DECLARE_BITMAP(async_events_bmap, 256);
3510 u32 *events = (u32 *)async_events_bmap;
3513 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_RGTR, -1, -1);
3516 cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_ASYNC_EVENT_FWD);
3518 memset(async_events_bmap, 0, sizeof(async_events_bmap));
3519 for (i = 0; i < ARRAY_SIZE(bnxt_async_events_arr); i++)
3520 __set_bit(bnxt_async_events_arr[i], async_events_bmap);
3522 if (bmap && bmap_size) {
3523 for (i = 0; i < bmap_size; i++) {
3524 if (test_bit(i, bmap))
3525 __set_bit(i, async_events_bmap);
3529 for (i = 0; i < 8; i++)
3530 req.async_event_fwd[i] |= cpu_to_le32(events[i]);
3532 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3535 static int bnxt_hwrm_func_drv_rgtr(struct bnxt *bp)
3537 struct hwrm_func_drv_rgtr_input req = {0};
3539 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_RGTR, -1, -1);
3542 cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_OS_TYPE |
3543 FUNC_DRV_RGTR_REQ_ENABLES_VER);
3545 req.os_type = cpu_to_le16(FUNC_DRV_RGTR_REQ_OS_TYPE_LINUX);
3546 req.ver_maj = DRV_VER_MAJ;
3547 req.ver_min = DRV_VER_MIN;
3548 req.ver_upd = DRV_VER_UPD;
3554 memset(data, 0, sizeof(data));
3555 for (i = 0; i < ARRAY_SIZE(bnxt_vf_req_snif); i++) {
3556 u16 cmd = bnxt_vf_req_snif[i];
3557 unsigned int bit, idx;
3561 data[idx] |= 1 << bit;
3564 for (i = 0; i < 8; i++)
3565 req.vf_req_fwd[i] = cpu_to_le32(data[i]);
3568 cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_VF_REQ_FWD);
3571 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3574 static int bnxt_hwrm_func_drv_unrgtr(struct bnxt *bp)
3576 struct hwrm_func_drv_unrgtr_input req = {0};
3578 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_UNRGTR, -1, -1);
3579 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3582 static int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, u8 tunnel_type)
3585 struct hwrm_tunnel_dst_port_free_input req = {0};
3587 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_TUNNEL_DST_PORT_FREE, -1, -1);
3588 req.tunnel_type = tunnel_type;
3590 switch (tunnel_type) {
3591 case TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN:
3592 req.tunnel_dst_port_id = bp->vxlan_fw_dst_port_id;
3594 case TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE:
3595 req.tunnel_dst_port_id = bp->nge_fw_dst_port_id;
3601 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3603 netdev_err(bp->dev, "hwrm_tunnel_dst_port_free failed. rc:%d\n",
3608 static int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, __be16 port,
3612 struct hwrm_tunnel_dst_port_alloc_input req = {0};
3613 struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3615 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_TUNNEL_DST_PORT_ALLOC, -1, -1);
3617 req.tunnel_type = tunnel_type;
3618 req.tunnel_dst_port_val = port;
3620 mutex_lock(&bp->hwrm_cmd_lock);
3621 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3623 netdev_err(bp->dev, "hwrm_tunnel_dst_port_alloc failed. rc:%d\n",
3628 switch (tunnel_type) {
3629 case TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN:
3630 bp->vxlan_fw_dst_port_id = resp->tunnel_dst_port_id;
3632 case TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_GENEVE:
3633 bp->nge_fw_dst_port_id = resp->tunnel_dst_port_id;
3640 mutex_unlock(&bp->hwrm_cmd_lock);
3644 static int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp, u16 vnic_id)
3646 struct hwrm_cfa_l2_set_rx_mask_input req = {0};
3647 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
3649 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_SET_RX_MASK, -1, -1);
3650 req.vnic_id = cpu_to_le32(vnic->fw_vnic_id);
3652 req.num_mc_entries = cpu_to_le32(vnic->mc_list_count);
3653 req.mc_tbl_addr = cpu_to_le64(vnic->mc_list_mapping);
3654 req.mask = cpu_to_le32(vnic->rx_mask);
3655 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3658 #ifdef CONFIG_RFS_ACCEL
3659 static int bnxt_hwrm_cfa_ntuple_filter_free(struct bnxt *bp,
3660 struct bnxt_ntuple_filter *fltr)
3662 struct hwrm_cfa_ntuple_filter_free_input req = {0};
3664 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_NTUPLE_FILTER_FREE, -1, -1);
3665 req.ntuple_filter_id = fltr->filter_id;
3666 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3669 #define BNXT_NTP_FLTR_FLAGS \
3670 (CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID | \
3671 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_ETHERTYPE | \
3672 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_MACADDR | \
3673 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IPADDR_TYPE | \
3674 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR | \
3675 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR_MASK | \
3676 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR | \
3677 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR_MASK | \
3678 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IP_PROTOCOL | \
3679 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT | \
3680 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT_MASK | \
3681 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT | \
3682 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT_MASK | \
3683 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_ID)
3685 #define BNXT_NTP_TUNNEL_FLTR_FLAG \
3686 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE
3688 static int bnxt_hwrm_cfa_ntuple_filter_alloc(struct bnxt *bp,
3689 struct bnxt_ntuple_filter *fltr)
3692 struct hwrm_cfa_ntuple_filter_alloc_input req = {0};
3693 struct hwrm_cfa_ntuple_filter_alloc_output *resp =
3694 bp->hwrm_cmd_resp_addr;
3695 struct flow_keys *keys = &fltr->fkeys;
3696 struct bnxt_vnic_info *vnic = &bp->vnic_info[fltr->rxq + 1];
3698 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_NTUPLE_FILTER_ALLOC, -1, -1);
3699 req.l2_filter_id = bp->vnic_info[0].fw_l2_filter_id[fltr->l2_fltr_idx];
3701 req.enables = cpu_to_le32(BNXT_NTP_FLTR_FLAGS);
3703 req.ethertype = htons(ETH_P_IP);
3704 memcpy(req.src_macaddr, fltr->src_mac_addr, ETH_ALEN);
3705 req.ip_addr_type = CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV4;
3706 req.ip_protocol = keys->basic.ip_proto;
3708 if (keys->basic.n_proto == htons(ETH_P_IPV6)) {
3711 req.ethertype = htons(ETH_P_IPV6);
3713 CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6;
3714 *(struct in6_addr *)&req.src_ipaddr[0] =
3715 keys->addrs.v6addrs.src;
3716 *(struct in6_addr *)&req.dst_ipaddr[0] =
3717 keys->addrs.v6addrs.dst;
3718 for (i = 0; i < 4; i++) {
3719 req.src_ipaddr_mask[i] = cpu_to_be32(0xffffffff);
3720 req.dst_ipaddr_mask[i] = cpu_to_be32(0xffffffff);
3723 req.src_ipaddr[0] = keys->addrs.v4addrs.src;
3724 req.src_ipaddr_mask[0] = cpu_to_be32(0xffffffff);
3725 req.dst_ipaddr[0] = keys->addrs.v4addrs.dst;
3726 req.dst_ipaddr_mask[0] = cpu_to_be32(0xffffffff);
3728 if (keys->control.flags & FLOW_DIS_ENCAPSULATION) {
3729 req.enables |= cpu_to_le32(BNXT_NTP_TUNNEL_FLTR_FLAG);
3731 CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL;
3734 req.src_port = keys->ports.src;
3735 req.src_port_mask = cpu_to_be16(0xffff);
3736 req.dst_port = keys->ports.dst;
3737 req.dst_port_mask = cpu_to_be16(0xffff);
3739 req.dst_id = cpu_to_le16(vnic->fw_vnic_id);
3740 mutex_lock(&bp->hwrm_cmd_lock);
3741 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3743 fltr->filter_id = resp->ntuple_filter_id;
3744 mutex_unlock(&bp->hwrm_cmd_lock);
3749 static int bnxt_hwrm_set_vnic_filter(struct bnxt *bp, u16 vnic_id, u16 idx,
3753 struct hwrm_cfa_l2_filter_alloc_input req = {0};
3754 struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3756 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_FILTER_ALLOC, -1, -1);
3757 req.flags = cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX);
3758 if (!BNXT_CHIP_TYPE_NITRO_A0(bp))
3760 cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_FLAGS_OUTERMOST);
3761 req.dst_id = cpu_to_le16(bp->vnic_info[vnic_id].fw_vnic_id);
3763 cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR |
3764 CFA_L2_FILTER_ALLOC_REQ_ENABLES_DST_ID |
3765 CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR_MASK);
3766 memcpy(req.l2_addr, mac_addr, ETH_ALEN);
3767 req.l2_addr_mask[0] = 0xff;
3768 req.l2_addr_mask[1] = 0xff;
3769 req.l2_addr_mask[2] = 0xff;
3770 req.l2_addr_mask[3] = 0xff;
3771 req.l2_addr_mask[4] = 0xff;
3772 req.l2_addr_mask[5] = 0xff;
3774 mutex_lock(&bp->hwrm_cmd_lock);
3775 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3777 bp->vnic_info[vnic_id].fw_l2_filter_id[idx] =
3779 mutex_unlock(&bp->hwrm_cmd_lock);
3783 static int bnxt_hwrm_clear_vnic_filter(struct bnxt *bp)
3785 u16 i, j, num_of_vnics = 1; /* only vnic 0 supported */
3788 /* Any associated ntuple filters will also be cleared by firmware. */
3789 mutex_lock(&bp->hwrm_cmd_lock);
3790 for (i = 0; i < num_of_vnics; i++) {
3791 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3793 for (j = 0; j < vnic->uc_filter_count; j++) {
3794 struct hwrm_cfa_l2_filter_free_input req = {0};
3796 bnxt_hwrm_cmd_hdr_init(bp, &req,
3797 HWRM_CFA_L2_FILTER_FREE, -1, -1);
3799 req.l2_filter_id = vnic->fw_l2_filter_id[j];
3801 rc = _hwrm_send_message(bp, &req, sizeof(req),
3804 vnic->uc_filter_count = 0;
3806 mutex_unlock(&bp->hwrm_cmd_lock);
3811 static int bnxt_hwrm_vnic_set_tpa(struct bnxt *bp, u16 vnic_id, u32 tpa_flags)
3813 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
3814 struct hwrm_vnic_tpa_cfg_input req = {0};
3816 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_TPA_CFG, -1, -1);
3819 u16 mss = bp->dev->mtu - 40;
3820 u32 nsegs, n, segs = 0, flags;
3822 flags = VNIC_TPA_CFG_REQ_FLAGS_TPA |
3823 VNIC_TPA_CFG_REQ_FLAGS_ENCAP_TPA |
3824 VNIC_TPA_CFG_REQ_FLAGS_RSC_WND_UPDATE |
3825 VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_ECN |
3826 VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_SAME_GRE_SEQ;
3827 if (tpa_flags & BNXT_FLAG_GRO)
3828 flags |= VNIC_TPA_CFG_REQ_FLAGS_GRO;
3830 req.flags = cpu_to_le32(flags);
3833 cpu_to_le32(VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_SEGS |
3834 VNIC_TPA_CFG_REQ_ENABLES_MAX_AGGS |
3835 VNIC_TPA_CFG_REQ_ENABLES_MIN_AGG_LEN);
3837 /* Number of segs are log2 units, and first packet is not
3838 * included as part of this units.
3840 if (mss <= BNXT_RX_PAGE_SIZE) {
3841 n = BNXT_RX_PAGE_SIZE / mss;
3842 nsegs = (MAX_SKB_FRAGS - 1) * n;
3844 n = mss / BNXT_RX_PAGE_SIZE;
3845 if (mss & (BNXT_RX_PAGE_SIZE - 1))
3847 nsegs = (MAX_SKB_FRAGS - n) / n;
3850 segs = ilog2(nsegs);
3851 req.max_agg_segs = cpu_to_le16(segs);
3852 req.max_aggs = cpu_to_le16(VNIC_TPA_CFG_REQ_MAX_AGGS_MAX);
3854 req.min_agg_len = cpu_to_le32(512);
3856 req.vnic_id = cpu_to_le16(vnic->fw_vnic_id);
3858 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3861 static int bnxt_hwrm_vnic_set_rss(struct bnxt *bp, u16 vnic_id, bool set_rss)
3863 u32 i, j, max_rings;
3864 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
3865 struct hwrm_vnic_rss_cfg_input req = {0};
3867 if (vnic->fw_rss_cos_lb_ctx[0] == INVALID_HW_RING_ID)
3870 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_CFG, -1, -1);
3872 req.hash_type = cpu_to_le32(bp->rss_hash_cfg);
3873 if (vnic->flags & BNXT_VNIC_RSS_FLAG) {
3874 if (BNXT_CHIP_TYPE_NITRO_A0(bp))
3875 max_rings = bp->rx_nr_rings - 1;
3877 max_rings = bp->rx_nr_rings;
3882 /* Fill the RSS indirection table with ring group ids */
3883 for (i = 0, j = 0; i < HW_HASH_INDEX_SIZE; i++, j++) {
3886 vnic->rss_table[i] = cpu_to_le16(vnic->fw_grp_ids[j]);
3889 req.ring_grp_tbl_addr = cpu_to_le64(vnic->rss_table_dma_addr);
3890 req.hash_key_tbl_addr =
3891 cpu_to_le64(vnic->rss_hash_key_dma_addr);
3893 req.rss_ctx_idx = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[0]);
3894 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3897 static int bnxt_hwrm_vnic_set_hds(struct bnxt *bp, u16 vnic_id)
3899 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
3900 struct hwrm_vnic_plcmodes_cfg_input req = {0};
3902 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_PLCMODES_CFG, -1, -1);
3903 req.flags = cpu_to_le32(VNIC_PLCMODES_CFG_REQ_FLAGS_JUMBO_PLACEMENT |
3904 VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV4 |
3905 VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV6);
3907 cpu_to_le32(VNIC_PLCMODES_CFG_REQ_ENABLES_JUMBO_THRESH_VALID |
3908 VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_THRESHOLD_VALID);
3909 /* thresholds not implemented in firmware yet */
3910 req.jumbo_thresh = cpu_to_le16(bp->rx_copy_thresh);
3911 req.hds_threshold = cpu_to_le16(bp->rx_copy_thresh);
3912 req.vnic_id = cpu_to_le32(vnic->fw_vnic_id);
3913 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3916 static void bnxt_hwrm_vnic_ctx_free_one(struct bnxt *bp, u16 vnic_id,
3919 struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {0};
3921 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_COS_LB_CTX_FREE, -1, -1);
3922 req.rss_cos_lb_ctx_id =
3923 cpu_to_le16(bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[ctx_idx]);
3925 hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3926 bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[ctx_idx] = INVALID_HW_RING_ID;
3929 static void bnxt_hwrm_vnic_ctx_free(struct bnxt *bp)
3933 for (i = 0; i < bp->nr_vnics; i++) {
3934 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3936 for (j = 0; j < BNXT_MAX_CTX_PER_VNIC; j++) {
3937 if (vnic->fw_rss_cos_lb_ctx[j] != INVALID_HW_RING_ID)
3938 bnxt_hwrm_vnic_ctx_free_one(bp, i, j);
3941 bp->rsscos_nr_ctxs = 0;
3944 static int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp, u16 vnic_id, u16 ctx_idx)
3947 struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {0};
3948 struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp =
3949 bp->hwrm_cmd_resp_addr;
3951 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_COS_LB_CTX_ALLOC, -1,
3954 mutex_lock(&bp->hwrm_cmd_lock);
3955 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3957 bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[ctx_idx] =
3958 le16_to_cpu(resp->rss_cos_lb_ctx_id);
3959 mutex_unlock(&bp->hwrm_cmd_lock);
3964 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, u16 vnic_id)
3966 unsigned int ring = 0, grp_idx;
3967 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
3968 struct hwrm_vnic_cfg_input req = {0};
3971 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_CFG, -1, -1);
3973 req.enables = cpu_to_le32(VNIC_CFG_REQ_ENABLES_DFLT_RING_GRP);
3974 /* Only RSS support for now TBD: COS & LB */
3975 if (vnic->fw_rss_cos_lb_ctx[0] != INVALID_HW_RING_ID) {
3976 req.rss_rule = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[0]);
3977 req.enables |= cpu_to_le32(VNIC_CFG_REQ_ENABLES_RSS_RULE |
3978 VNIC_CFG_REQ_ENABLES_MRU);
3979 } else if (vnic->flags & BNXT_VNIC_RFS_NEW_RSS_FLAG) {
3981 cpu_to_le16(bp->vnic_info[0].fw_rss_cos_lb_ctx[0]);
3982 req.enables |= cpu_to_le32(VNIC_CFG_REQ_ENABLES_RSS_RULE |
3983 VNIC_CFG_REQ_ENABLES_MRU);
3984 req.flags |= cpu_to_le32(VNIC_CFG_REQ_FLAGS_RSS_DFLT_CR_MODE);
3986 req.rss_rule = cpu_to_le16(0xffff);
3989 if (BNXT_CHIP_TYPE_NITRO_A0(bp) &&
3990 (vnic->fw_rss_cos_lb_ctx[0] != INVALID_HW_RING_ID)) {
3991 req.cos_rule = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[1]);
3992 req.enables |= cpu_to_le32(VNIC_CFG_REQ_ENABLES_COS_RULE);
3994 req.cos_rule = cpu_to_le16(0xffff);
3997 if (vnic->flags & BNXT_VNIC_RSS_FLAG)
3999 else if (vnic->flags & BNXT_VNIC_RFS_FLAG)
4001 else if ((vnic_id == 1) && BNXT_CHIP_TYPE_NITRO_A0(bp))
4002 ring = bp->rx_nr_rings - 1;
4004 grp_idx = bp->rx_ring[ring].bnapi->index;
4005 req.vnic_id = cpu_to_le16(vnic->fw_vnic_id);
4006 req.dflt_ring_grp = cpu_to_le16(bp->grp_info[grp_idx].fw_grp_id);
4008 req.lb_rule = cpu_to_le16(0xffff);
4009 req.mru = cpu_to_le16(bp->dev->mtu + ETH_HLEN + ETH_FCS_LEN +
4012 #ifdef CONFIG_BNXT_SRIOV
4014 def_vlan = bp->vf.vlan;
4016 if ((bp->flags & BNXT_FLAG_STRIP_VLAN) || def_vlan)
4017 req.flags |= cpu_to_le32(VNIC_CFG_REQ_FLAGS_VLAN_STRIP_MODE);
4018 if (!vnic_id && bnxt_ulp_registered(bp->edev, BNXT_ROCE_ULP))
4020 cpu_to_le32(VNIC_CFG_REQ_FLAGS_ROCE_DUAL_VNIC_MODE);
4022 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4025 static int bnxt_hwrm_vnic_free_one(struct bnxt *bp, u16 vnic_id)
4029 if (bp->vnic_info[vnic_id].fw_vnic_id != INVALID_HW_RING_ID) {
4030 struct hwrm_vnic_free_input req = {0};
4032 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_FREE, -1, -1);
4034 cpu_to_le32(bp->vnic_info[vnic_id].fw_vnic_id);
4036 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4039 bp->vnic_info[vnic_id].fw_vnic_id = INVALID_HW_RING_ID;
4044 static void bnxt_hwrm_vnic_free(struct bnxt *bp)
4048 for (i = 0; i < bp->nr_vnics; i++)
4049 bnxt_hwrm_vnic_free_one(bp, i);
4052 static int bnxt_hwrm_vnic_alloc(struct bnxt *bp, u16 vnic_id,
4053 unsigned int start_rx_ring_idx,
4054 unsigned int nr_rings)
4057 unsigned int i, j, grp_idx, end_idx = start_rx_ring_idx + nr_rings;
4058 struct hwrm_vnic_alloc_input req = {0};
4059 struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
4061 /* map ring groups to this vnic */
4062 for (i = start_rx_ring_idx, j = 0; i < end_idx; i++, j++) {
4063 grp_idx = bp->rx_ring[i].bnapi->index;
4064 if (bp->grp_info[grp_idx].fw_grp_id == INVALID_HW_RING_ID) {
4065 netdev_err(bp->dev, "Not enough ring groups avail:%x req:%x\n",
4069 bp->vnic_info[vnic_id].fw_grp_ids[j] =
4070 bp->grp_info[grp_idx].fw_grp_id;
4073 bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[0] = INVALID_HW_RING_ID;
4074 bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[1] = INVALID_HW_RING_ID;
4076 req.flags = cpu_to_le32(VNIC_ALLOC_REQ_FLAGS_DEFAULT);
4078 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_ALLOC, -1, -1);
4080 mutex_lock(&bp->hwrm_cmd_lock);
4081 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4083 bp->vnic_info[vnic_id].fw_vnic_id = le32_to_cpu(resp->vnic_id);
4084 mutex_unlock(&bp->hwrm_cmd_lock);
4088 static int bnxt_hwrm_vnic_qcaps(struct bnxt *bp)
4090 struct hwrm_vnic_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
4091 struct hwrm_vnic_qcaps_input req = {0};
4094 if (bp->hwrm_spec_code < 0x10600)
4097 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_QCAPS, -1, -1);
4098 mutex_lock(&bp->hwrm_cmd_lock);
4099 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4102 cpu_to_le32(VNIC_QCAPS_RESP_FLAGS_RSS_DFLT_CR_CAP))
4103 bp->flags |= BNXT_FLAG_NEW_RSS_CAP;
4105 mutex_unlock(&bp->hwrm_cmd_lock);
4109 static int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp)
4114 mutex_lock(&bp->hwrm_cmd_lock);
4115 for (i = 0; i < bp->rx_nr_rings; i++) {
4116 struct hwrm_ring_grp_alloc_input req = {0};
4117 struct hwrm_ring_grp_alloc_output *resp =
4118 bp->hwrm_cmd_resp_addr;
4119 unsigned int grp_idx = bp->rx_ring[i].bnapi->index;
4121 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_GRP_ALLOC, -1, -1);
4123 req.cr = cpu_to_le16(bp->grp_info[grp_idx].cp_fw_ring_id);
4124 req.rr = cpu_to_le16(bp->grp_info[grp_idx].rx_fw_ring_id);
4125 req.ar = cpu_to_le16(bp->grp_info[grp_idx].agg_fw_ring_id);
4126 req.sc = cpu_to_le16(bp->grp_info[grp_idx].fw_stats_ctx);
4128 rc = _hwrm_send_message(bp, &req, sizeof(req),
4133 bp->grp_info[grp_idx].fw_grp_id =
4134 le32_to_cpu(resp->ring_group_id);
4136 mutex_unlock(&bp->hwrm_cmd_lock);
4140 static int bnxt_hwrm_ring_grp_free(struct bnxt *bp)
4144 struct hwrm_ring_grp_free_input req = {0};
4149 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_GRP_FREE, -1, -1);
4151 mutex_lock(&bp->hwrm_cmd_lock);
4152 for (i = 0; i < bp->cp_nr_rings; i++) {
4153 if (bp->grp_info[i].fw_grp_id == INVALID_HW_RING_ID)
4156 cpu_to_le32(bp->grp_info[i].fw_grp_id);
4158 rc = _hwrm_send_message(bp, &req, sizeof(req),
4162 bp->grp_info[i].fw_grp_id = INVALID_HW_RING_ID;
4164 mutex_unlock(&bp->hwrm_cmd_lock);
4168 static int hwrm_ring_alloc_send_msg(struct bnxt *bp,
4169 struct bnxt_ring_struct *ring,
4170 u32 ring_type, u32 map_index,
4173 int rc = 0, err = 0;
4174 struct hwrm_ring_alloc_input req = {0};
4175 struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr;
4178 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_ALLOC, -1, -1);
4181 if (ring->nr_pages > 1) {
4182 req.page_tbl_addr = cpu_to_le64(ring->pg_tbl_map);
4183 /* Page size is in log2 units */
4184 req.page_size = BNXT_PAGE_SHIFT;
4185 req.page_tbl_depth = 1;
4187 req.page_tbl_addr = cpu_to_le64(ring->dma_arr[0]);
4190 /* Association of ring index with doorbell index and MSIX number */
4191 req.logical_id = cpu_to_le16(map_index);
4193 switch (ring_type) {
4194 case HWRM_RING_ALLOC_TX:
4195 req.ring_type = RING_ALLOC_REQ_RING_TYPE_TX;
4196 /* Association of transmit ring with completion ring */
4198 cpu_to_le16(bp->grp_info[map_index].cp_fw_ring_id);
4199 req.length = cpu_to_le32(bp->tx_ring_mask + 1);
4200 req.stat_ctx_id = cpu_to_le32(stats_ctx_id);
4201 req.queue_id = cpu_to_le16(ring->queue_id);
4203 case HWRM_RING_ALLOC_RX:
4204 req.ring_type = RING_ALLOC_REQ_RING_TYPE_RX;
4205 req.length = cpu_to_le32(bp->rx_ring_mask + 1);
4207 case HWRM_RING_ALLOC_AGG:
4208 req.ring_type = RING_ALLOC_REQ_RING_TYPE_RX;
4209 req.length = cpu_to_le32(bp->rx_agg_ring_mask + 1);
4211 case HWRM_RING_ALLOC_CMPL:
4212 req.ring_type = RING_ALLOC_REQ_RING_TYPE_L2_CMPL;
4213 req.length = cpu_to_le32(bp->cp_ring_mask + 1);
4214 if (bp->flags & BNXT_FLAG_USING_MSIX)
4215 req.int_mode = RING_ALLOC_REQ_INT_MODE_MSIX;
4218 netdev_err(bp->dev, "hwrm alloc invalid ring type %d\n",
4223 mutex_lock(&bp->hwrm_cmd_lock);
4224 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4225 err = le16_to_cpu(resp->error_code);
4226 ring_id = le16_to_cpu(resp->ring_id);
4227 mutex_unlock(&bp->hwrm_cmd_lock);
4230 switch (ring_type) {
4231 case RING_FREE_REQ_RING_TYPE_L2_CMPL:
4232 netdev_err(bp->dev, "hwrm_ring_alloc cp failed. rc:%x err:%x\n",
4236 case RING_FREE_REQ_RING_TYPE_RX:
4237 netdev_err(bp->dev, "hwrm_ring_alloc rx failed. rc:%x err:%x\n",
4241 case RING_FREE_REQ_RING_TYPE_TX:
4242 netdev_err(bp->dev, "hwrm_ring_alloc tx failed. rc:%x err:%x\n",
4247 netdev_err(bp->dev, "Invalid ring\n");
4251 ring->fw_ring_id = ring_id;
4255 static int bnxt_hwrm_set_async_event_cr(struct bnxt *bp, int idx)
4260 struct hwrm_func_cfg_input req = {0};
4262 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_CFG, -1, -1);
4263 req.fid = cpu_to_le16(0xffff);
4264 req.enables = cpu_to_le32(FUNC_CFG_REQ_ENABLES_ASYNC_EVENT_CR);
4265 req.async_event_cr = cpu_to_le16(idx);
4266 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4268 struct hwrm_func_vf_cfg_input req = {0};
4270 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_VF_CFG, -1, -1);
4272 cpu_to_le32(FUNC_VF_CFG_REQ_ENABLES_ASYNC_EVENT_CR);
4273 req.async_event_cr = cpu_to_le16(idx);
4274 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4279 static int bnxt_hwrm_ring_alloc(struct bnxt *bp)
4283 for (i = 0; i < bp->cp_nr_rings; i++) {
4284 struct bnxt_napi *bnapi = bp->bnapi[i];
4285 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
4286 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct;
4288 cpr->cp_doorbell = bp->bar1 + i * 0x80;
4289 rc = hwrm_ring_alloc_send_msg(bp, ring, HWRM_RING_ALLOC_CMPL, i,
4290 INVALID_STATS_CTX_ID);
4293 BNXT_CP_DB(cpr->cp_doorbell, cpr->cp_raw_cons);
4294 bp->grp_info[i].cp_fw_ring_id = ring->fw_ring_id;
4297 rc = bnxt_hwrm_set_async_event_cr(bp, ring->fw_ring_id);
4299 netdev_warn(bp->dev, "Failed to set async event completion ring.\n");
4303 for (i = 0; i < bp->tx_nr_rings; i++) {
4304 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
4305 struct bnxt_ring_struct *ring = &txr->tx_ring_struct;
4306 u32 map_idx = txr->bnapi->index;
4307 u16 fw_stats_ctx = bp->grp_info[map_idx].fw_stats_ctx;
4309 rc = hwrm_ring_alloc_send_msg(bp, ring, HWRM_RING_ALLOC_TX,
4310 map_idx, fw_stats_ctx);
4313 txr->tx_doorbell = bp->bar1 + map_idx * 0x80;
4316 for (i = 0; i < bp->rx_nr_rings; i++) {
4317 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
4318 struct bnxt_ring_struct *ring = &rxr->rx_ring_struct;
4319 u32 map_idx = rxr->bnapi->index;
4321 rc = hwrm_ring_alloc_send_msg(bp, ring, HWRM_RING_ALLOC_RX,
4322 map_idx, INVALID_STATS_CTX_ID);
4325 rxr->rx_doorbell = bp->bar1 + map_idx * 0x80;
4326 writel(DB_KEY_RX | rxr->rx_prod, rxr->rx_doorbell);
4327 bp->grp_info[map_idx].rx_fw_ring_id = ring->fw_ring_id;
4330 if (bp->flags & BNXT_FLAG_AGG_RINGS) {
4331 for (i = 0; i < bp->rx_nr_rings; i++) {
4332 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
4333 struct bnxt_ring_struct *ring =
4334 &rxr->rx_agg_ring_struct;
4335 u32 grp_idx = rxr->bnapi->index;
4336 u32 map_idx = grp_idx + bp->rx_nr_rings;
4338 rc = hwrm_ring_alloc_send_msg(bp, ring,
4339 HWRM_RING_ALLOC_AGG,
4341 INVALID_STATS_CTX_ID);
4345 rxr->rx_agg_doorbell = bp->bar1 + map_idx * 0x80;
4346 writel(DB_KEY_RX | rxr->rx_agg_prod,
4347 rxr->rx_agg_doorbell);
4348 bp->grp_info[grp_idx].agg_fw_ring_id = ring->fw_ring_id;
4355 static int hwrm_ring_free_send_msg(struct bnxt *bp,
4356 struct bnxt_ring_struct *ring,
4357 u32 ring_type, int cmpl_ring_id)
4360 struct hwrm_ring_free_input req = {0};
4361 struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;
4364 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_FREE, cmpl_ring_id, -1);
4365 req.ring_type = ring_type;
4366 req.ring_id = cpu_to_le16(ring->fw_ring_id);
4368 mutex_lock(&bp->hwrm_cmd_lock);
4369 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4370 error_code = le16_to_cpu(resp->error_code);
4371 mutex_unlock(&bp->hwrm_cmd_lock);
4373 if (rc || error_code) {
4374 switch (ring_type) {
4375 case RING_FREE_REQ_RING_TYPE_L2_CMPL:
4376 netdev_err(bp->dev, "hwrm_ring_free cp failed. rc:%d\n",
4379 case RING_FREE_REQ_RING_TYPE_RX:
4380 netdev_err(bp->dev, "hwrm_ring_free rx failed. rc:%d\n",
4383 case RING_FREE_REQ_RING_TYPE_TX:
4384 netdev_err(bp->dev, "hwrm_ring_free tx failed. rc:%d\n",
4388 netdev_err(bp->dev, "Invalid ring\n");
4395 static void bnxt_hwrm_ring_free(struct bnxt *bp, bool close_path)
4402 for (i = 0; i < bp->tx_nr_rings; i++) {
4403 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
4404 struct bnxt_ring_struct *ring = &txr->tx_ring_struct;
4405 u32 grp_idx = txr->bnapi->index;
4406 u32 cmpl_ring_id = bp->grp_info[grp_idx].cp_fw_ring_id;
4408 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
4409 hwrm_ring_free_send_msg(bp, ring,
4410 RING_FREE_REQ_RING_TYPE_TX,
4411 close_path ? cmpl_ring_id :
4412 INVALID_HW_RING_ID);
4413 ring->fw_ring_id = INVALID_HW_RING_ID;
4417 for (i = 0; i < bp->rx_nr_rings; i++) {
4418 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
4419 struct bnxt_ring_struct *ring = &rxr->rx_ring_struct;
4420 u32 grp_idx = rxr->bnapi->index;
4421 u32 cmpl_ring_id = bp->grp_info[grp_idx].cp_fw_ring_id;
4423 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
4424 hwrm_ring_free_send_msg(bp, ring,
4425 RING_FREE_REQ_RING_TYPE_RX,
4426 close_path ? cmpl_ring_id :
4427 INVALID_HW_RING_ID);
4428 ring->fw_ring_id = INVALID_HW_RING_ID;
4429 bp->grp_info[grp_idx].rx_fw_ring_id =
4434 for (i = 0; i < bp->rx_nr_rings; i++) {
4435 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
4436 struct bnxt_ring_struct *ring = &rxr->rx_agg_ring_struct;
4437 u32 grp_idx = rxr->bnapi->index;
4438 u32 cmpl_ring_id = bp->grp_info[grp_idx].cp_fw_ring_id;
4440 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
4441 hwrm_ring_free_send_msg(bp, ring,
4442 RING_FREE_REQ_RING_TYPE_RX,
4443 close_path ? cmpl_ring_id :
4444 INVALID_HW_RING_ID);
4445 ring->fw_ring_id = INVALID_HW_RING_ID;
4446 bp->grp_info[grp_idx].agg_fw_ring_id =
4451 /* The completion rings are about to be freed. After that the
4452 * IRQ doorbell will not work anymore. So we need to disable
4455 bnxt_disable_int_sync(bp);
4457 for (i = 0; i < bp->cp_nr_rings; i++) {
4458 struct bnxt_napi *bnapi = bp->bnapi[i];
4459 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
4460 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct;
4462 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
4463 hwrm_ring_free_send_msg(bp, ring,
4464 RING_FREE_REQ_RING_TYPE_L2_CMPL,
4465 INVALID_HW_RING_ID);
4466 ring->fw_ring_id = INVALID_HW_RING_ID;
4467 bp->grp_info[i].cp_fw_ring_id = INVALID_HW_RING_ID;
4472 /* Caller must hold bp->hwrm_cmd_lock */
4473 int __bnxt_hwrm_get_tx_rings(struct bnxt *bp, u16 fid, int *tx_rings)
4475 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
4476 struct hwrm_func_qcfg_input req = {0};
4479 if (bp->hwrm_spec_code < 0x10601)
4482 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCFG, -1, -1);
4483 req.fid = cpu_to_le16(fid);
4484 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4486 *tx_rings = le16_to_cpu(resp->alloc_tx_rings);
4491 static int bnxt_hwrm_reserve_tx_rings(struct bnxt *bp, int *tx_rings)
4493 struct hwrm_func_cfg_input req = {0};
4496 if (bp->hwrm_spec_code < 0x10601)
4502 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_CFG, -1, -1);
4503 req.fid = cpu_to_le16(0xffff);
4504 req.enables = cpu_to_le32(FUNC_CFG_REQ_ENABLES_NUM_TX_RINGS);
4505 req.num_tx_rings = cpu_to_le16(*tx_rings);
4506 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4510 mutex_lock(&bp->hwrm_cmd_lock);
4511 rc = __bnxt_hwrm_get_tx_rings(bp, 0xffff, tx_rings);
4512 mutex_unlock(&bp->hwrm_cmd_lock);
4514 bp->tx_reserved_rings = *tx_rings;
4518 static int bnxt_hwrm_check_tx_rings(struct bnxt *bp, int tx_rings)
4520 struct hwrm_func_cfg_input req = {0};
4523 if (bp->hwrm_spec_code < 0x10801)
4529 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_CFG, -1, -1);
4530 req.fid = cpu_to_le16(0xffff);
4531 req.flags = cpu_to_le32(FUNC_CFG_REQ_FLAGS_TX_ASSETS_TEST);
4532 req.enables = cpu_to_le32(FUNC_CFG_REQ_ENABLES_NUM_TX_RINGS);
4533 req.num_tx_rings = cpu_to_le16(tx_rings);
4534 rc = hwrm_send_message_silent(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4540 static void bnxt_hwrm_set_coal_params(struct bnxt_coal *hw_coal,
4541 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *req)
4543 u16 val, tmr, max, flags;
4545 max = hw_coal->bufs_per_record * 128;
4546 if (hw_coal->budget)
4547 max = hw_coal->bufs_per_record * hw_coal->budget;
4549 val = clamp_t(u16, hw_coal->coal_bufs, 1, max);
4550 req->num_cmpl_aggr_int = cpu_to_le16(val);
4552 /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
4553 val = min_t(u16, val, 63);
4554 req->num_cmpl_dma_aggr = cpu_to_le16(val);
4556 /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
4557 val = clamp_t(u16, hw_coal->coal_bufs_irq, 1, 63);
4558 req->num_cmpl_dma_aggr_during_int = cpu_to_le16(val);
4560 tmr = BNXT_USEC_TO_COAL_TIMER(hw_coal->coal_ticks);
4561 tmr = max_t(u16, tmr, 1);
4562 req->int_lat_tmr_max = cpu_to_le16(tmr);
4564 /* min timer set to 1/2 of interrupt timer */
4566 req->int_lat_tmr_min = cpu_to_le16(val);
4568 /* buf timer set to 1/4 of interrupt timer */
4569 val = max_t(u16, tmr / 4, 1);
4570 req->cmpl_aggr_dma_tmr = cpu_to_le16(val);
4572 tmr = BNXT_USEC_TO_COAL_TIMER(hw_coal->coal_ticks_irq);
4573 tmr = max_t(u16, tmr, 1);
4574 req->cmpl_aggr_dma_tmr_during_int = cpu_to_le16(tmr);
4576 flags = RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET;
4577 if (hw_coal->idle_thresh && hw_coal->coal_ticks < hw_coal->idle_thresh)
4578 flags |= RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_RING_IDLE;
4579 req->flags = cpu_to_le16(flags);
4582 int bnxt_hwrm_set_coal(struct bnxt *bp)
4585 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req_rx = {0},
4588 bnxt_hwrm_cmd_hdr_init(bp, &req_rx,
4589 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS, -1, -1);
4590 bnxt_hwrm_cmd_hdr_init(bp, &req_tx,
4591 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS, -1, -1);
4593 bnxt_hwrm_set_coal_params(&bp->rx_coal, &req_rx);
4594 bnxt_hwrm_set_coal_params(&bp->tx_coal, &req_tx);
4596 mutex_lock(&bp->hwrm_cmd_lock);
4597 for (i = 0; i < bp->cp_nr_rings; i++) {
4598 struct bnxt_napi *bnapi = bp->bnapi[i];
4601 if (!bnapi->rx_ring)
4603 req->ring_id = cpu_to_le16(bp->grp_info[i].cp_fw_ring_id);
4605 rc = _hwrm_send_message(bp, req, sizeof(*req),
4610 mutex_unlock(&bp->hwrm_cmd_lock);
4614 static int bnxt_hwrm_stat_ctx_free(struct bnxt *bp)
4617 struct hwrm_stat_ctx_free_input req = {0};
4622 if (BNXT_CHIP_TYPE_NITRO_A0(bp))
4625 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_STAT_CTX_FREE, -1, -1);
4627 mutex_lock(&bp->hwrm_cmd_lock);
4628 for (i = 0; i < bp->cp_nr_rings; i++) {
4629 struct bnxt_napi *bnapi = bp->bnapi[i];
4630 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
4632 if (cpr->hw_stats_ctx_id != INVALID_STATS_CTX_ID) {
4633 req.stat_ctx_id = cpu_to_le32(cpr->hw_stats_ctx_id);
4635 rc = _hwrm_send_message(bp, &req, sizeof(req),
4640 cpr->hw_stats_ctx_id = INVALID_STATS_CTX_ID;
4643 mutex_unlock(&bp->hwrm_cmd_lock);
4647 static int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp)
4650 struct hwrm_stat_ctx_alloc_input req = {0};
4651 struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;
4653 if (BNXT_CHIP_TYPE_NITRO_A0(bp))
4656 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_STAT_CTX_ALLOC, -1, -1);
4658 req.update_period_ms = cpu_to_le32(bp->stats_coal_ticks / 1000);
4660 mutex_lock(&bp->hwrm_cmd_lock);
4661 for (i = 0; i < bp->cp_nr_rings; i++) {
4662 struct bnxt_napi *bnapi = bp->bnapi[i];
4663 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
4665 req.stats_dma_addr = cpu_to_le64(cpr->hw_stats_map);
4667 rc = _hwrm_send_message(bp, &req, sizeof(req),
4672 cpr->hw_stats_ctx_id = le32_to_cpu(resp->stat_ctx_id);
4674 bp->grp_info[i].fw_stats_ctx = cpr->hw_stats_ctx_id;
4676 mutex_unlock(&bp->hwrm_cmd_lock);
4680 static int bnxt_hwrm_func_qcfg(struct bnxt *bp)
4682 struct hwrm_func_qcfg_input req = {0};
4683 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
4687 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCFG, -1, -1);
4688 req.fid = cpu_to_le16(0xffff);
4689 mutex_lock(&bp->hwrm_cmd_lock);
4690 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4692 goto func_qcfg_exit;
4694 #ifdef CONFIG_BNXT_SRIOV
4696 struct bnxt_vf_info *vf = &bp->vf;
4698 vf->vlan = le16_to_cpu(resp->vlan) & VLAN_VID_MASK;
4701 flags = le16_to_cpu(resp->flags);
4702 if (flags & (FUNC_QCFG_RESP_FLAGS_FW_DCBX_AGENT_ENABLED |
4703 FUNC_QCFG_RESP_FLAGS_FW_LLDP_AGENT_ENABLED)) {
4704 bp->flags |= BNXT_FLAG_FW_LLDP_AGENT;
4705 if (flags & FUNC_QCFG_RESP_FLAGS_FW_DCBX_AGENT_ENABLED)
4706 bp->flags |= BNXT_FLAG_FW_DCBX_AGENT;
4708 if (BNXT_PF(bp) && (flags & FUNC_QCFG_RESP_FLAGS_MULTI_HOST))
4709 bp->flags |= BNXT_FLAG_MULTI_HOST;
4711 switch (resp->port_partition_type) {
4712 case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_0:
4713 case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_5:
4714 case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR2_0:
4715 bp->port_partition_type = resp->port_partition_type;
4718 if (bp->hwrm_spec_code < 0x10707 ||
4719 resp->evb_mode == FUNC_QCFG_RESP_EVB_MODE_VEB)
4720 bp->br_mode = BRIDGE_MODE_VEB;
4721 else if (resp->evb_mode == FUNC_QCFG_RESP_EVB_MODE_VEPA)
4722 bp->br_mode = BRIDGE_MODE_VEPA;
4724 bp->br_mode = BRIDGE_MODE_UNDEF;
4726 bp->max_mtu = le16_to_cpu(resp->max_mtu_configured);
4728 bp->max_mtu = BNXT_MAX_MTU;
4731 mutex_unlock(&bp->hwrm_cmd_lock);
4735 static int bnxt_hwrm_func_qcaps(struct bnxt *bp)
4738 struct hwrm_func_qcaps_input req = {0};
4739 struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
4741 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCAPS, -1, -1);
4742 req.fid = cpu_to_le16(0xffff);
4744 mutex_lock(&bp->hwrm_cmd_lock);
4745 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4747 goto hwrm_func_qcaps_exit;
4749 if (resp->flags & cpu_to_le32(FUNC_QCAPS_RESP_FLAGS_ROCE_V1_SUPPORTED))
4750 bp->flags |= BNXT_FLAG_ROCEV1_CAP;
4751 if (resp->flags & cpu_to_le32(FUNC_QCAPS_RESP_FLAGS_ROCE_V2_SUPPORTED))
4752 bp->flags |= BNXT_FLAG_ROCEV2_CAP;
4754 bp->tx_push_thresh = 0;
4756 cpu_to_le32(FUNC_QCAPS_RESP_FLAGS_PUSH_MODE_SUPPORTED))
4757 bp->tx_push_thresh = BNXT_TX_PUSH_THRESH;
4760 struct bnxt_pf_info *pf = &bp->pf;
4762 pf->fw_fid = le16_to_cpu(resp->fid);
4763 pf->port_id = le16_to_cpu(resp->port_id);
4764 bp->dev->dev_port = pf->port_id;
4765 memcpy(pf->mac_addr, resp->mac_address, ETH_ALEN);
4766 pf->max_rsscos_ctxs = le16_to_cpu(resp->max_rsscos_ctx);
4767 pf->max_cp_rings = le16_to_cpu(resp->max_cmpl_rings);
4768 pf->max_tx_rings = le16_to_cpu(resp->max_tx_rings);
4769 pf->max_rx_rings = le16_to_cpu(resp->max_rx_rings);
4770 pf->max_hw_ring_grps = le32_to_cpu(resp->max_hw_ring_grps);
4771 if (!pf->max_hw_ring_grps)
4772 pf->max_hw_ring_grps = pf->max_tx_rings;
4773 pf->max_l2_ctxs = le16_to_cpu(resp->max_l2_ctxs);
4774 pf->max_vnics = le16_to_cpu(resp->max_vnics);
4775 pf->max_stat_ctxs = le16_to_cpu(resp->max_stat_ctx);
4776 pf->first_vf_id = le16_to_cpu(resp->first_vf_id);
4777 pf->max_vfs = le16_to_cpu(resp->max_vfs);
4778 pf->max_encap_records = le32_to_cpu(resp->max_encap_records);
4779 pf->max_decap_records = le32_to_cpu(resp->max_decap_records);
4780 pf->max_tx_em_flows = le32_to_cpu(resp->max_tx_em_flows);
4781 pf->max_tx_wm_flows = le32_to_cpu(resp->max_tx_wm_flows);
4782 pf->max_rx_em_flows = le32_to_cpu(resp->max_rx_em_flows);
4783 pf->max_rx_wm_flows = le32_to_cpu(resp->max_rx_wm_flows);
4785 cpu_to_le32(FUNC_QCAPS_RESP_FLAGS_WOL_MAGICPKT_SUPPORTED))
4786 bp->flags |= BNXT_FLAG_WOL_CAP;
4788 #ifdef CONFIG_BNXT_SRIOV
4789 struct bnxt_vf_info *vf = &bp->vf;
4791 vf->fw_fid = le16_to_cpu(resp->fid);
4793 vf->max_rsscos_ctxs = le16_to_cpu(resp->max_rsscos_ctx);
4794 vf->max_cp_rings = le16_to_cpu(resp->max_cmpl_rings);
4795 vf->max_tx_rings = le16_to_cpu(resp->max_tx_rings);
4796 vf->max_rx_rings = le16_to_cpu(resp->max_rx_rings);
4797 vf->max_hw_ring_grps = le32_to_cpu(resp->max_hw_ring_grps);
4798 if (!vf->max_hw_ring_grps)
4799 vf->max_hw_ring_grps = vf->max_tx_rings;
4800 vf->max_l2_ctxs = le16_to_cpu(resp->max_l2_ctxs);
4801 vf->max_vnics = le16_to_cpu(resp->max_vnics);
4802 vf->max_stat_ctxs = le16_to_cpu(resp->max_stat_ctx);
4804 memcpy(vf->mac_addr, resp->mac_address, ETH_ALEN);
4808 hwrm_func_qcaps_exit:
4809 mutex_unlock(&bp->hwrm_cmd_lock);
4813 static int bnxt_hwrm_func_reset(struct bnxt *bp)
4815 struct hwrm_func_reset_input req = {0};
4817 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_RESET, -1, -1);
4820 return hwrm_send_message(bp, &req, sizeof(req), HWRM_RESET_TIMEOUT);
4823 static int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
4826 struct hwrm_queue_qportcfg_input req = {0};
4827 struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
4830 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_QUEUE_QPORTCFG, -1, -1);
4832 mutex_lock(&bp->hwrm_cmd_lock);
4833 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4837 if (!resp->max_configurable_queues) {
4841 bp->max_tc = resp->max_configurable_queues;
4842 bp->max_lltc = resp->max_configurable_lossless_queues;
4843 if (bp->max_tc > BNXT_MAX_QUEUE)
4844 bp->max_tc = BNXT_MAX_QUEUE;
4846 if (resp->queue_cfg_info & QUEUE_QPORTCFG_RESP_QUEUE_CFG_INFO_ASYM_CFG)
4849 if (bp->max_lltc > bp->max_tc)
4850 bp->max_lltc = bp->max_tc;
4852 qptr = &resp->queue_id0;
4853 for (i = 0; i < bp->max_tc; i++) {
4854 bp->q_info[i].queue_id = *qptr++;
4855 bp->q_info[i].queue_profile = *qptr++;
4859 mutex_unlock(&bp->hwrm_cmd_lock);
4863 static int bnxt_hwrm_ver_get(struct bnxt *bp)
4866 struct hwrm_ver_get_input req = {0};
4867 struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
4870 bp->hwrm_max_req_len = HWRM_MAX_REQ_LEN;
4871 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VER_GET, -1, -1);
4872 req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
4873 req.hwrm_intf_min = HWRM_VERSION_MINOR;
4874 req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
4875 mutex_lock(&bp->hwrm_cmd_lock);
4876 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4878 goto hwrm_ver_get_exit;
4880 memcpy(&bp->ver_resp, resp, sizeof(struct hwrm_ver_get_output));
4882 bp->hwrm_spec_code = resp->hwrm_intf_maj << 16 |
4883 resp->hwrm_intf_min << 8 | resp->hwrm_intf_upd;
4884 if (resp->hwrm_intf_maj < 1) {
4885 netdev_warn(bp->dev, "HWRM interface %d.%d.%d is older than 1.0.0.\n",
4886 resp->hwrm_intf_maj, resp->hwrm_intf_min,
4887 resp->hwrm_intf_upd);
4888 netdev_warn(bp->dev, "Please update firmware with HWRM interface 1.0.0 or newer.\n");
4890 snprintf(bp->fw_ver_str, BC_HWRM_STR_LEN, "%d.%d.%d.%d",
4891 resp->hwrm_fw_maj, resp->hwrm_fw_min, resp->hwrm_fw_bld,
4892 resp->hwrm_fw_rsvd);
4894 bp->hwrm_cmd_timeout = le16_to_cpu(resp->def_req_timeout);
4895 if (!bp->hwrm_cmd_timeout)
4896 bp->hwrm_cmd_timeout = DFLT_HWRM_CMD_TIMEOUT;
4898 if (resp->hwrm_intf_maj >= 1)
4899 bp->hwrm_max_req_len = le16_to_cpu(resp->max_req_win_len);
4901 bp->chip_num = le16_to_cpu(resp->chip_num);
4902 if (bp->chip_num == CHIP_NUM_58700 && !resp->chip_rev &&
4904 bp->flags |= BNXT_FLAG_CHIP_NITRO_A0;
4906 dev_caps_cfg = le32_to_cpu(resp->dev_caps_cfg);
4907 if ((dev_caps_cfg & VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
4908 (dev_caps_cfg & VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_REQUIRED))
4909 bp->flags |= BNXT_FLAG_SHORT_CMD;
4912 mutex_unlock(&bp->hwrm_cmd_lock);
4916 int bnxt_hwrm_fw_set_time(struct bnxt *bp)
4918 struct hwrm_fw_set_time_input req = {0};
4920 time64_t now = ktime_get_real_seconds();
4922 if (bp->hwrm_spec_code < 0x10400)
4925 time64_to_tm(now, 0, &tm);
4926 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FW_SET_TIME, -1, -1);
4927 req.year = cpu_to_le16(1900 + tm.tm_year);
4928 req.month = 1 + tm.tm_mon;
4929 req.day = tm.tm_mday;
4930 req.hour = tm.tm_hour;
4931 req.minute = tm.tm_min;
4932 req.second = tm.tm_sec;
4933 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4936 static int bnxt_hwrm_port_qstats(struct bnxt *bp)
4939 struct bnxt_pf_info *pf = &bp->pf;
4940 struct hwrm_port_qstats_input req = {0};
4942 if (!(bp->flags & BNXT_FLAG_PORT_STATS))
4945 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_QSTATS, -1, -1);
4946 req.port_id = cpu_to_le16(pf->port_id);
4947 req.tx_stat_host_addr = cpu_to_le64(bp->hw_tx_port_stats_map);
4948 req.rx_stat_host_addr = cpu_to_le64(bp->hw_rx_port_stats_map);
4949 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4953 static void bnxt_hwrm_free_tunnel_ports(struct bnxt *bp)
4955 if (bp->vxlan_port_cnt) {
4956 bnxt_hwrm_tunnel_dst_port_free(
4957 bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN);
4959 bp->vxlan_port_cnt = 0;
4960 if (bp->nge_port_cnt) {
4961 bnxt_hwrm_tunnel_dst_port_free(
4962 bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE);
4964 bp->nge_port_cnt = 0;
4967 static int bnxt_set_tpa(struct bnxt *bp, bool set_tpa)
4973 tpa_flags = bp->flags & BNXT_FLAG_TPA;
4974 for (i = 0; i < bp->nr_vnics; i++) {
4975 rc = bnxt_hwrm_vnic_set_tpa(bp, i, tpa_flags);
4977 netdev_err(bp->dev, "hwrm vnic set tpa failure rc for vnic %d: %x\n",
4985 static void bnxt_hwrm_clear_vnic_rss(struct bnxt *bp)
4989 for (i = 0; i < bp->nr_vnics; i++)
4990 bnxt_hwrm_vnic_set_rss(bp, i, false);
4993 static void bnxt_hwrm_resource_free(struct bnxt *bp, bool close_path,
4996 if (bp->vnic_info) {
4997 bnxt_hwrm_clear_vnic_filter(bp);
4998 /* clear all RSS setting before free vnic ctx */
4999 bnxt_hwrm_clear_vnic_rss(bp);
5000 bnxt_hwrm_vnic_ctx_free(bp);
5001 /* before free the vnic, undo the vnic tpa settings */
5002 if (bp->flags & BNXT_FLAG_TPA)
5003 bnxt_set_tpa(bp, false);
5004 bnxt_hwrm_vnic_free(bp);
5006 bnxt_hwrm_ring_free(bp, close_path);
5007 bnxt_hwrm_ring_grp_free(bp);
5009 bnxt_hwrm_stat_ctx_free(bp);
5010 bnxt_hwrm_free_tunnel_ports(bp);
5014 static int bnxt_hwrm_set_br_mode(struct bnxt *bp, u16 br_mode)
5016 struct hwrm_func_cfg_input req = {0};
5019 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_CFG, -1, -1);
5020 req.fid = cpu_to_le16(0xffff);
5021 req.enables = cpu_to_le32(FUNC_CFG_REQ_ENABLES_EVB_MODE);
5022 if (br_mode == BRIDGE_MODE_VEB)
5023 req.evb_mode = FUNC_CFG_REQ_EVB_MODE_VEB;
5024 else if (br_mode == BRIDGE_MODE_VEPA)
5025 req.evb_mode = FUNC_CFG_REQ_EVB_MODE_VEPA;
5028 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5034 static int bnxt_setup_vnic(struct bnxt *bp, u16 vnic_id)
5036 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
5039 if (vnic->flags & BNXT_VNIC_RFS_NEW_RSS_FLAG)
5042 /* allocate context for vnic */
5043 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic_id, 0);
5045 netdev_err(bp->dev, "hwrm vnic %d alloc failure rc: %x\n",
5047 goto vnic_setup_err;
5049 bp->rsscos_nr_ctxs++;
5051 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) {
5052 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic_id, 1);
5054 netdev_err(bp->dev, "hwrm vnic %d cos ctx alloc failure rc: %x\n",
5056 goto vnic_setup_err;
5058 bp->rsscos_nr_ctxs++;
5062 /* configure default vnic, ring grp */
5063 rc = bnxt_hwrm_vnic_cfg(bp, vnic_id);
5065 netdev_err(bp->dev, "hwrm vnic %d cfg failure rc: %x\n",
5067 goto vnic_setup_err;
5070 /* Enable RSS hashing on vnic */
5071 rc = bnxt_hwrm_vnic_set_rss(bp, vnic_id, true);
5073 netdev_err(bp->dev, "hwrm vnic %d set rss failure rc: %x\n",
5075 goto vnic_setup_err;
5078 if (bp->flags & BNXT_FLAG_AGG_RINGS) {
5079 rc = bnxt_hwrm_vnic_set_hds(bp, vnic_id);
5081 netdev_err(bp->dev, "hwrm vnic %d set hds failure rc: %x\n",
5090 static int bnxt_alloc_rfs_vnics(struct bnxt *bp)
5092 #ifdef CONFIG_RFS_ACCEL
5095 for (i = 0; i < bp->rx_nr_rings; i++) {
5096 struct bnxt_vnic_info *vnic;
5097 u16 vnic_id = i + 1;
5100 if (vnic_id >= bp->nr_vnics)
5103 vnic = &bp->vnic_info[vnic_id];
5104 vnic->flags |= BNXT_VNIC_RFS_FLAG;
5105 if (bp->flags & BNXT_FLAG_NEW_RSS_CAP)
5106 vnic->flags |= BNXT_VNIC_RFS_NEW_RSS_FLAG;
5107 rc = bnxt_hwrm_vnic_alloc(bp, vnic_id, ring_id, 1);
5109 netdev_err(bp->dev, "hwrm vnic %d alloc failure rc: %x\n",
5113 rc = bnxt_setup_vnic(bp, vnic_id);
5123 /* Allow PF and VF with default VLAN to be in promiscuous mode */
5124 static bool bnxt_promisc_ok(struct bnxt *bp)
5126 #ifdef CONFIG_BNXT_SRIOV
5127 if (BNXT_VF(bp) && !bp->vf.vlan)
5133 static int bnxt_setup_nitroa0_vnic(struct bnxt *bp)
5135 unsigned int rc = 0;
5137 rc = bnxt_hwrm_vnic_alloc(bp, 1, bp->rx_nr_rings - 1, 1);
5139 netdev_err(bp->dev, "Cannot allocate special vnic for NS2 A0: %x\n",
5144 rc = bnxt_hwrm_vnic_cfg(bp, 1);
5146 netdev_err(bp->dev, "Cannot allocate special vnic for NS2 A0: %x\n",
5153 static int bnxt_cfg_rx_mode(struct bnxt *);
5154 static bool bnxt_mc_list_updated(struct bnxt *, u32 *);
5156 static int bnxt_init_chip(struct bnxt *bp, bool irq_re_init)
5158 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
5160 unsigned int rx_nr_rings = bp->rx_nr_rings;
5163 rc = bnxt_hwrm_stat_ctx_alloc(bp);
5165 netdev_err(bp->dev, "hwrm stat ctx alloc failure rc: %x\n",
5169 if (bp->tx_reserved_rings != bp->tx_nr_rings) {
5170 int tx = bp->tx_nr_rings;
5172 if (bnxt_hwrm_reserve_tx_rings(bp, &tx) ||
5173 tx < bp->tx_nr_rings) {
5180 rc = bnxt_hwrm_ring_alloc(bp);
5182 netdev_err(bp->dev, "hwrm ring alloc failure rc: %x\n", rc);
5186 rc = bnxt_hwrm_ring_grp_alloc(bp);
5188 netdev_err(bp->dev, "hwrm_ring_grp alloc failure: %x\n", rc);
5192 if (BNXT_CHIP_TYPE_NITRO_A0(bp))
5195 /* default vnic 0 */
5196 rc = bnxt_hwrm_vnic_alloc(bp, 0, 0, rx_nr_rings);
5198 netdev_err(bp->dev, "hwrm vnic alloc failure rc: %x\n", rc);
5202 rc = bnxt_setup_vnic(bp, 0);
5206 if (bp->flags & BNXT_FLAG_RFS) {
5207 rc = bnxt_alloc_rfs_vnics(bp);
5212 if (bp->flags & BNXT_FLAG_TPA) {
5213 rc = bnxt_set_tpa(bp, true);
5219 bnxt_update_vf_mac(bp);
5221 /* Filter for default vnic 0 */
5222 rc = bnxt_hwrm_set_vnic_filter(bp, 0, 0, bp->dev->dev_addr);
5224 netdev_err(bp->dev, "HWRM vnic filter failure rc: %x\n", rc);
5227 vnic->uc_filter_count = 1;
5229 vnic->rx_mask = CFA_L2_SET_RX_MASK_REQ_MASK_BCAST;
5231 if ((bp->dev->flags & IFF_PROMISC) && bnxt_promisc_ok(bp))
5232 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS;
5234 if (bp->dev->flags & IFF_ALLMULTI) {
5235 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST;
5236 vnic->mc_list_count = 0;
5240 bnxt_mc_list_updated(bp, &mask);
5241 vnic->rx_mask |= mask;
5244 rc = bnxt_cfg_rx_mode(bp);
5248 rc = bnxt_hwrm_set_coal(bp);
5250 netdev_warn(bp->dev, "HWRM set coalescing failure rc: %x\n",
5253 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) {
5254 rc = bnxt_setup_nitroa0_vnic(bp);
5256 netdev_err(bp->dev, "Special vnic setup failure for NS2 A0 rc: %x\n",
5261 bnxt_hwrm_func_qcfg(bp);
5262 netdev_update_features(bp->dev);
5268 bnxt_hwrm_resource_free(bp, 0, true);
5273 static int bnxt_shutdown_nic(struct bnxt *bp, bool irq_re_init)
5275 bnxt_hwrm_resource_free(bp, 1, irq_re_init);
5279 static int bnxt_init_nic(struct bnxt *bp, bool irq_re_init)
5281 bnxt_init_cp_rings(bp);
5282 bnxt_init_rx_rings(bp);
5283 bnxt_init_tx_rings(bp);
5284 bnxt_init_ring_grps(bp, irq_re_init);
5285 bnxt_init_vnics(bp);
5287 return bnxt_init_chip(bp, irq_re_init);
5290 static int bnxt_set_real_num_queues(struct bnxt *bp)
5293 struct net_device *dev = bp->dev;
5295 rc = netif_set_real_num_tx_queues(dev, bp->tx_nr_rings -
5296 bp->tx_nr_rings_xdp);
5300 rc = netif_set_real_num_rx_queues(dev, bp->rx_nr_rings);
5304 #ifdef CONFIG_RFS_ACCEL
5305 if (bp->flags & BNXT_FLAG_RFS)
5306 dev->rx_cpu_rmap = alloc_irq_cpu_rmap(bp->rx_nr_rings);
5312 static int bnxt_trim_rings(struct bnxt *bp, int *rx, int *tx, int max,
5315 int _rx = *rx, _tx = *tx;
5318 *rx = min_t(int, _rx, max);
5319 *tx = min_t(int, _tx, max);
5324 while (_rx + _tx > max) {
5325 if (_rx > _tx && _rx > 1)
5336 static void bnxt_setup_msix(struct bnxt *bp)
5338 const int len = sizeof(bp->irq_tbl[0].name);
5339 struct net_device *dev = bp->dev;
5342 tcs = netdev_get_num_tc(dev);
5346 for (i = 0; i < tcs; i++) {
5347 count = bp->tx_nr_rings_per_tc;
5349 netdev_set_tc_queue(dev, i, count, off);
5353 for (i = 0; i < bp->cp_nr_rings; i++) {
5356 if (bp->flags & BNXT_FLAG_SHARED_RINGS)
5358 else if (i < bp->rx_nr_rings)
5363 snprintf(bp->irq_tbl[i].name, len, "%s-%s-%d", dev->name, attr,
5365 bp->irq_tbl[i].handler = bnxt_msix;
5369 static void bnxt_setup_inta(struct bnxt *bp)
5371 const int len = sizeof(bp->irq_tbl[0].name);
5373 if (netdev_get_num_tc(bp->dev))
5374 netdev_reset_tc(bp->dev);
5376 snprintf(bp->irq_tbl[0].name, len, "%s-%s-%d", bp->dev->name, "TxRx",
5378 bp->irq_tbl[0].handler = bnxt_inta;
5381 static int bnxt_setup_int_mode(struct bnxt *bp)
5385 if (bp->flags & BNXT_FLAG_USING_MSIX)
5386 bnxt_setup_msix(bp);
5388 bnxt_setup_inta(bp);
5390 rc = bnxt_set_real_num_queues(bp);
5394 #ifdef CONFIG_RFS_ACCEL
5395 static unsigned int bnxt_get_max_func_rss_ctxs(struct bnxt *bp)
5397 #if defined(CONFIG_BNXT_SRIOV)
5399 return bp->vf.max_rsscos_ctxs;
5401 return bp->pf.max_rsscos_ctxs;
5404 static unsigned int bnxt_get_max_func_vnics(struct bnxt *bp)
5406 #if defined(CONFIG_BNXT_SRIOV)
5408 return bp->vf.max_vnics;
5410 return bp->pf.max_vnics;
5414 unsigned int bnxt_get_max_func_stat_ctxs(struct bnxt *bp)
5416 #if defined(CONFIG_BNXT_SRIOV)
5418 return bp->vf.max_stat_ctxs;
5420 return bp->pf.max_stat_ctxs;
5423 void bnxt_set_max_func_stat_ctxs(struct bnxt *bp, unsigned int max)
5425 #if defined(CONFIG_BNXT_SRIOV)
5427 bp->vf.max_stat_ctxs = max;
5430 bp->pf.max_stat_ctxs = max;
5433 unsigned int bnxt_get_max_func_cp_rings(struct bnxt *bp)
5435 #if defined(CONFIG_BNXT_SRIOV)
5437 return bp->vf.max_cp_rings;
5439 return bp->pf.max_cp_rings;
5442 void bnxt_set_max_func_cp_rings(struct bnxt *bp, unsigned int max)
5444 #if defined(CONFIG_BNXT_SRIOV)
5446 bp->vf.max_cp_rings = max;
5449 bp->pf.max_cp_rings = max;
5452 static unsigned int bnxt_get_max_func_irqs(struct bnxt *bp)
5454 #if defined(CONFIG_BNXT_SRIOV)
5456 return min_t(unsigned int, bp->vf.max_irqs,
5457 bp->vf.max_cp_rings);
5459 return min_t(unsigned int, bp->pf.max_irqs, bp->pf.max_cp_rings);
5462 void bnxt_set_max_func_irqs(struct bnxt *bp, unsigned int max_irqs)
5464 #if defined(CONFIG_BNXT_SRIOV)
5466 bp->vf.max_irqs = max_irqs;
5469 bp->pf.max_irqs = max_irqs;
5472 static int bnxt_init_msix(struct bnxt *bp)
5474 int i, total_vecs, rc = 0, min = 1;
5475 struct msix_entry *msix_ent;
5477 total_vecs = bnxt_get_max_func_irqs(bp);
5478 msix_ent = kcalloc(total_vecs, sizeof(struct msix_entry), GFP_KERNEL);
5482 for (i = 0; i < total_vecs; i++) {
5483 msix_ent[i].entry = i;
5484 msix_ent[i].vector = 0;
5487 if (!(bp->flags & BNXT_FLAG_SHARED_RINGS))
5490 total_vecs = pci_enable_msix_range(bp->pdev, msix_ent, min, total_vecs);
5491 if (total_vecs < 0) {
5493 goto msix_setup_exit;
5496 bp->irq_tbl = kcalloc(total_vecs, sizeof(struct bnxt_irq), GFP_KERNEL);
5498 for (i = 0; i < total_vecs; i++)
5499 bp->irq_tbl[i].vector = msix_ent[i].vector;
5501 bp->total_irqs = total_vecs;
5502 /* Trim rings based upon num of vectors allocated */
5503 rc = bnxt_trim_rings(bp, &bp->rx_nr_rings, &bp->tx_nr_rings,
5504 total_vecs, min == 1);
5506 goto msix_setup_exit;
5508 bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
5509 bp->cp_nr_rings = (min == 1) ?
5510 max_t(int, bp->tx_nr_rings, bp->rx_nr_rings) :
5511 bp->tx_nr_rings + bp->rx_nr_rings;
5515 goto msix_setup_exit;
5517 bp->flags |= BNXT_FLAG_USING_MSIX;
5522 netdev_err(bp->dev, "bnxt_init_msix err: %x\n", rc);
5525 pci_disable_msix(bp->pdev);
5530 static int bnxt_init_inta(struct bnxt *bp)
5532 bp->irq_tbl = kcalloc(1, sizeof(struct bnxt_irq), GFP_KERNEL);
5537 bp->rx_nr_rings = 1;
5538 bp->tx_nr_rings = 1;
5539 bp->cp_nr_rings = 1;
5540 bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
5541 bp->flags |= BNXT_FLAG_SHARED_RINGS;
5542 bp->irq_tbl[0].vector = bp->pdev->irq;
5546 static int bnxt_init_int_mode(struct bnxt *bp)
5550 if (bp->flags & BNXT_FLAG_MSIX_CAP)
5551 rc = bnxt_init_msix(bp);
5553 if (!(bp->flags & BNXT_FLAG_USING_MSIX) && BNXT_PF(bp)) {
5554 /* fallback to INTA */
5555 rc = bnxt_init_inta(bp);
5560 static void bnxt_clear_int_mode(struct bnxt *bp)
5562 if (bp->flags & BNXT_FLAG_USING_MSIX)
5563 pci_disable_msix(bp->pdev);
5567 bp->flags &= ~BNXT_FLAG_USING_MSIX;
5570 static void bnxt_free_irq(struct bnxt *bp)
5572 struct bnxt_irq *irq;
5575 #ifdef CONFIG_RFS_ACCEL
5576 free_irq_cpu_rmap(bp->dev->rx_cpu_rmap);
5577 bp->dev->rx_cpu_rmap = NULL;
5582 for (i = 0; i < bp->cp_nr_rings; i++) {
5583 irq = &bp->irq_tbl[i];
5584 if (irq->requested) {
5585 if (irq->have_cpumask) {
5586 irq_set_affinity_hint(irq->vector, NULL);
5587 free_cpumask_var(irq->cpu_mask);
5588 irq->have_cpumask = 0;
5590 free_irq(irq->vector, bp->bnapi[i]);
5597 static int bnxt_request_irq(struct bnxt *bp)
5600 unsigned long flags = 0;
5601 #ifdef CONFIG_RFS_ACCEL
5602 struct cpu_rmap *rmap = bp->dev->rx_cpu_rmap;
5605 if (!(bp->flags & BNXT_FLAG_USING_MSIX))
5606 flags = IRQF_SHARED;
5608 for (i = 0, j = 0; i < bp->cp_nr_rings; i++) {
5609 struct bnxt_irq *irq = &bp->irq_tbl[i];
5610 #ifdef CONFIG_RFS_ACCEL
5611 if (rmap && bp->bnapi[i]->rx_ring) {
5612 rc = irq_cpu_rmap_add(rmap, irq->vector);
5614 netdev_warn(bp->dev, "failed adding irq rmap for ring %d\n",
5619 rc = request_irq(irq->vector, irq->handler, flags, irq->name,
5626 if (zalloc_cpumask_var(&irq->cpu_mask, GFP_KERNEL)) {
5627 int numa_node = dev_to_node(&bp->pdev->dev);
5629 irq->have_cpumask = 1;
5630 cpumask_set_cpu(cpumask_local_spread(i, numa_node),
5632 rc = irq_set_affinity_hint(irq->vector, irq->cpu_mask);
5634 netdev_warn(bp->dev,
5635 "Set affinity failed, IRQ = %d\n",
5644 static void bnxt_del_napi(struct bnxt *bp)
5651 for (i = 0; i < bp->cp_nr_rings; i++) {
5652 struct bnxt_napi *bnapi = bp->bnapi[i];
5654 napi_hash_del(&bnapi->napi);
5655 netif_napi_del(&bnapi->napi);
5657 /* We called napi_hash_del() before netif_napi_del(), we need
5658 * to respect an RCU grace period before freeing napi structures.
5663 static void bnxt_init_napi(struct bnxt *bp)
5666 unsigned int cp_nr_rings = bp->cp_nr_rings;
5667 struct bnxt_napi *bnapi;
5669 if (bp->flags & BNXT_FLAG_USING_MSIX) {
5670 if (BNXT_CHIP_TYPE_NITRO_A0(bp))
5672 for (i = 0; i < cp_nr_rings; i++) {
5673 bnapi = bp->bnapi[i];
5674 netif_napi_add(bp->dev, &bnapi->napi,
5677 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) {
5678 bnapi = bp->bnapi[cp_nr_rings];
5679 netif_napi_add(bp->dev, &bnapi->napi,
5680 bnxt_poll_nitroa0, 64);
5683 bnapi = bp->bnapi[0];
5684 netif_napi_add(bp->dev, &bnapi->napi, bnxt_poll, 64);
5688 static void bnxt_disable_napi(struct bnxt *bp)
5695 for (i = 0; i < bp->cp_nr_rings; i++)
5696 napi_disable(&bp->bnapi[i]->napi);
5699 static void bnxt_enable_napi(struct bnxt *bp)
5703 for (i = 0; i < bp->cp_nr_rings; i++) {
5704 bp->bnapi[i]->in_reset = false;
5705 napi_enable(&bp->bnapi[i]->napi);
5709 void bnxt_tx_disable(struct bnxt *bp)
5712 struct bnxt_tx_ring_info *txr;
5715 for (i = 0; i < bp->tx_nr_rings; i++) {
5716 txr = &bp->tx_ring[i];
5717 txr->dev_state = BNXT_DEV_STATE_CLOSING;
5720 /* Stop all TX queues */
5721 netif_tx_disable(bp->dev);
5722 netif_carrier_off(bp->dev);
5725 void bnxt_tx_enable(struct bnxt *bp)
5728 struct bnxt_tx_ring_info *txr;
5730 for (i = 0; i < bp->tx_nr_rings; i++) {
5731 txr = &bp->tx_ring[i];
5734 netif_tx_wake_all_queues(bp->dev);
5735 if (bp->link_info.link_up)
5736 netif_carrier_on(bp->dev);
5739 static void bnxt_report_link(struct bnxt *bp)
5741 if (bp->link_info.link_up) {
5743 const char *flow_ctrl;
5747 netif_carrier_on(bp->dev);
5748 if (bp->link_info.duplex == BNXT_LINK_DUPLEX_FULL)
5752 if (bp->link_info.pause == BNXT_LINK_PAUSE_BOTH)
5753 flow_ctrl = "ON - receive & transmit";
5754 else if (bp->link_info.pause == BNXT_LINK_PAUSE_TX)
5755 flow_ctrl = "ON - transmit";
5756 else if (bp->link_info.pause == BNXT_LINK_PAUSE_RX)
5757 flow_ctrl = "ON - receive";
5760 speed = bnxt_fw_to_ethtool_speed(bp->link_info.link_speed);
5761 netdev_info(bp->dev, "NIC Link is Up, %u Mbps %s duplex, Flow control: %s\n",
5762 speed, duplex, flow_ctrl);
5763 if (bp->flags & BNXT_FLAG_EEE_CAP)
5764 netdev_info(bp->dev, "EEE is %s\n",
5765 bp->eee.eee_active ? "active" :
5767 fec = bp->link_info.fec_cfg;
5768 if (!(fec & PORT_PHY_QCFG_RESP_FEC_CFG_FEC_NONE_SUPPORTED))
5769 netdev_info(bp->dev, "FEC autoneg %s encodings: %s\n",
5770 (fec & BNXT_FEC_AUTONEG) ? "on" : "off",
5771 (fec & BNXT_FEC_ENC_BASE_R) ? "BaseR" :
5772 (fec & BNXT_FEC_ENC_RS) ? "RS" : "None");
5774 netif_carrier_off(bp->dev);
5775 netdev_err(bp->dev, "NIC Link is Down\n");
5779 static int bnxt_hwrm_phy_qcaps(struct bnxt *bp)
5782 struct hwrm_port_phy_qcaps_input req = {0};
5783 struct hwrm_port_phy_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
5784 struct bnxt_link_info *link_info = &bp->link_info;
5786 if (bp->hwrm_spec_code < 0x10201)
5789 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_QCAPS, -1, -1);
5791 mutex_lock(&bp->hwrm_cmd_lock);
5792 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5794 goto hwrm_phy_qcaps_exit;
5796 if (resp->flags & PORT_PHY_QCAPS_RESP_FLAGS_EEE_SUPPORTED) {
5797 struct ethtool_eee *eee = &bp->eee;
5798 u16 fw_speeds = le16_to_cpu(resp->supported_speeds_eee_mode);
5800 bp->flags |= BNXT_FLAG_EEE_CAP;
5801 eee->supported = _bnxt_fw_to_ethtool_adv_spds(fw_speeds, 0);
5802 bp->lpi_tmr_lo = le32_to_cpu(resp->tx_lpi_timer_low) &
5803 PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_LOW_MASK;
5804 bp->lpi_tmr_hi = le32_to_cpu(resp->valid_tx_lpi_timer_high) &
5805 PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_HIGH_MASK;
5807 if (resp->supported_speeds_auto_mode)
5808 link_info->support_auto_speeds =
5809 le16_to_cpu(resp->supported_speeds_auto_mode);
5811 bp->port_count = resp->port_cnt;
5813 hwrm_phy_qcaps_exit:
5814 mutex_unlock(&bp->hwrm_cmd_lock);
5818 static int bnxt_update_link(struct bnxt *bp, bool chng_link_state)
5821 struct bnxt_link_info *link_info = &bp->link_info;
5822 struct hwrm_port_phy_qcfg_input req = {0};
5823 struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
5824 u8 link_up = link_info->link_up;
5827 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_QCFG, -1, -1);
5829 mutex_lock(&bp->hwrm_cmd_lock);
5830 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5832 mutex_unlock(&bp->hwrm_cmd_lock);
5836 memcpy(&link_info->phy_qcfg_resp, resp, sizeof(*resp));
5837 link_info->phy_link_status = resp->link;
5838 link_info->duplex = resp->duplex_cfg;
5839 if (bp->hwrm_spec_code >= 0x10800)
5840 link_info->duplex = resp->duplex_state;
5841 link_info->pause = resp->pause;
5842 link_info->auto_mode = resp->auto_mode;
5843 link_info->auto_pause_setting = resp->auto_pause;
5844 link_info->lp_pause = resp->link_partner_adv_pause;
5845 link_info->force_pause_setting = resp->force_pause;
5846 link_info->duplex_setting = resp->duplex_cfg;
5847 if (link_info->phy_link_status == BNXT_LINK_LINK)
5848 link_info->link_speed = le16_to_cpu(resp->link_speed);
5850 link_info->link_speed = 0;
5851 link_info->force_link_speed = le16_to_cpu(resp->force_link_speed);
5852 link_info->support_speeds = le16_to_cpu(resp->support_speeds);
5853 link_info->auto_link_speeds = le16_to_cpu(resp->auto_link_speed_mask);
5854 link_info->lp_auto_link_speeds =
5855 le16_to_cpu(resp->link_partner_adv_speeds);
5856 link_info->preemphasis = le32_to_cpu(resp->preemphasis);
5857 link_info->phy_ver[0] = resp->phy_maj;
5858 link_info->phy_ver[1] = resp->phy_min;
5859 link_info->phy_ver[2] = resp->phy_bld;
5860 link_info->media_type = resp->media_type;
5861 link_info->phy_type = resp->phy_type;
5862 link_info->transceiver = resp->xcvr_pkg_type;
5863 link_info->phy_addr = resp->eee_config_phy_addr &
5864 PORT_PHY_QCFG_RESP_PHY_ADDR_MASK;
5865 link_info->module_status = resp->module_status;
5867 if (bp->flags & BNXT_FLAG_EEE_CAP) {
5868 struct ethtool_eee *eee = &bp->eee;
5871 eee->eee_active = 0;
5872 if (resp->eee_config_phy_addr &
5873 PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ACTIVE) {
5874 eee->eee_active = 1;
5875 fw_speeds = le16_to_cpu(
5876 resp->link_partner_adv_eee_link_speed_mask);
5877 eee->lp_advertised =
5878 _bnxt_fw_to_ethtool_adv_spds(fw_speeds, 0);
5881 /* Pull initial EEE config */
5882 if (!chng_link_state) {
5883 if (resp->eee_config_phy_addr &
5884 PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ENABLED)
5885 eee->eee_enabled = 1;
5887 fw_speeds = le16_to_cpu(resp->adv_eee_link_speed_mask);
5889 _bnxt_fw_to_ethtool_adv_spds(fw_speeds, 0);
5891 if (resp->eee_config_phy_addr &
5892 PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_TX_LPI) {
5895 eee->tx_lpi_enabled = 1;
5896 tmr = resp->xcvr_identifier_type_tx_lpi_timer;
5897 eee->tx_lpi_timer = le32_to_cpu(tmr) &
5898 PORT_PHY_QCFG_RESP_TX_LPI_TIMER_MASK;
5903 link_info->fec_cfg = PORT_PHY_QCFG_RESP_FEC_CFG_FEC_NONE_SUPPORTED;
5904 if (bp->hwrm_spec_code >= 0x10504)
5905 link_info->fec_cfg = le16_to_cpu(resp->fec_cfg);
5907 /* TODO: need to add more logic to report VF link */
5908 if (chng_link_state) {
5909 if (link_info->phy_link_status == BNXT_LINK_LINK)
5910 link_info->link_up = 1;
5912 link_info->link_up = 0;
5913 if (link_up != link_info->link_up)
5914 bnxt_report_link(bp);
5916 /* alwasy link down if not require to update link state */
5917 link_info->link_up = 0;
5919 mutex_unlock(&bp->hwrm_cmd_lock);
5921 diff = link_info->support_auto_speeds ^ link_info->advertising;
5922 if ((link_info->support_auto_speeds | diff) !=
5923 link_info->support_auto_speeds) {
5924 /* An advertised speed is no longer supported, so we need to
5925 * update the advertisement settings. Caller holds RTNL
5926 * so we can modify link settings.
5928 link_info->advertising = link_info->support_auto_speeds;
5929 if (link_info->autoneg & BNXT_AUTONEG_SPEED)
5930 bnxt_hwrm_set_link_setting(bp, true, false);
5935 static void bnxt_get_port_module_status(struct bnxt *bp)
5937 struct bnxt_link_info *link_info = &bp->link_info;
5938 struct hwrm_port_phy_qcfg_output *resp = &link_info->phy_qcfg_resp;
5941 if (bnxt_update_link(bp, true))
5944 module_status = link_info->module_status;
5945 switch (module_status) {
5946 case PORT_PHY_QCFG_RESP_MODULE_STATUS_DISABLETX:
5947 case PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN:
5948 case PORT_PHY_QCFG_RESP_MODULE_STATUS_WARNINGMSG:
5949 netdev_warn(bp->dev, "Unqualified SFP+ module detected on port %d\n",
5951 if (bp->hwrm_spec_code >= 0x10201) {
5952 netdev_warn(bp->dev, "Module part number %s\n",
5953 resp->phy_vendor_partnumber);
5955 if (module_status == PORT_PHY_QCFG_RESP_MODULE_STATUS_DISABLETX)
5956 netdev_warn(bp->dev, "TX is disabled\n");
5957 if (module_status == PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN)
5958 netdev_warn(bp->dev, "SFP+ module is shutdown\n");
5963 bnxt_hwrm_set_pause_common(struct bnxt *bp, struct hwrm_port_phy_cfg_input *req)
5965 if (bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL) {
5966 if (bp->hwrm_spec_code >= 0x10201)
5968 PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE;
5969 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_RX)
5970 req->auto_pause |= PORT_PHY_CFG_REQ_AUTO_PAUSE_RX;
5971 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_TX)
5972 req->auto_pause |= PORT_PHY_CFG_REQ_AUTO_PAUSE_TX;
5974 cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE);
5976 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_RX)
5977 req->force_pause |= PORT_PHY_CFG_REQ_FORCE_PAUSE_RX;
5978 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_TX)
5979 req->force_pause |= PORT_PHY_CFG_REQ_FORCE_PAUSE_TX;
5981 cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_FORCE_PAUSE);
5982 if (bp->hwrm_spec_code >= 0x10201) {
5983 req->auto_pause = req->force_pause;
5984 req->enables |= cpu_to_le32(
5985 PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE);
5990 static void bnxt_hwrm_set_link_common(struct bnxt *bp,
5991 struct hwrm_port_phy_cfg_input *req)
5993 u8 autoneg = bp->link_info.autoneg;
5994 u16 fw_link_speed = bp->link_info.req_link_speed;
5995 u16 advertising = bp->link_info.advertising;
5997 if (autoneg & BNXT_AUTONEG_SPEED) {
5999 PORT_PHY_CFG_REQ_AUTO_MODE_SPEED_MASK;
6001 req->enables |= cpu_to_le32(
6002 PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED_MASK);
6003 req->auto_link_speed_mask = cpu_to_le16(advertising);
6005 req->enables |= cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_MODE);
6007 cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_RESTART_AUTONEG);
6009 req->force_link_speed = cpu_to_le16(fw_link_speed);
6010 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_FORCE);
6013 /* tell chimp that the setting takes effect immediately */
6014 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_RESET_PHY);
6017 int bnxt_hwrm_set_pause(struct bnxt *bp)
6019 struct hwrm_port_phy_cfg_input req = {0};
6022 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1);
6023 bnxt_hwrm_set_pause_common(bp, &req);
6025 if ((bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL) ||
6026 bp->link_info.force_link_chng)
6027 bnxt_hwrm_set_link_common(bp, &req);
6029 mutex_lock(&bp->hwrm_cmd_lock);
6030 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6031 if (!rc && !(bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL)) {
6032 /* since changing of pause setting doesn't trigger any link
6033 * change event, the driver needs to update the current pause
6034 * result upon successfully return of the phy_cfg command
6036 bp->link_info.pause =
6037 bp->link_info.force_pause_setting = bp->link_info.req_flow_ctrl;
6038 bp->link_info.auto_pause_setting = 0;
6039 if (!bp->link_info.force_link_chng)
6040 bnxt_report_link(bp);
6042 bp->link_info.force_link_chng = false;
6043 mutex_unlock(&bp->hwrm_cmd_lock);
6047 static void bnxt_hwrm_set_eee(struct bnxt *bp,
6048 struct hwrm_port_phy_cfg_input *req)
6050 struct ethtool_eee *eee = &bp->eee;
6052 if (eee->eee_enabled) {
6054 u32 flags = PORT_PHY_CFG_REQ_FLAGS_EEE_ENABLE;
6056 if (eee->tx_lpi_enabled)
6057 flags |= PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_ENABLE;
6059 flags |= PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_DISABLE;
6061 req->flags |= cpu_to_le32(flags);
6062 eee_speeds = bnxt_get_fw_auto_link_speeds(eee->advertised);
6063 req->eee_link_speed_mask = cpu_to_le16(eee_speeds);
6064 req->tx_lpi_timer = cpu_to_le32(eee->tx_lpi_timer);
6066 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_EEE_DISABLE);
6070 int bnxt_hwrm_set_link_setting(struct bnxt *bp, bool set_pause, bool set_eee)
6072 struct hwrm_port_phy_cfg_input req = {0};
6074 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1);
6076 bnxt_hwrm_set_pause_common(bp, &req);
6078 bnxt_hwrm_set_link_common(bp, &req);
6081 bnxt_hwrm_set_eee(bp, &req);
6082 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6085 static int bnxt_hwrm_shutdown_link(struct bnxt *bp)
6087 struct hwrm_port_phy_cfg_input req = {0};
6089 if (!BNXT_SINGLE_PF(bp))
6092 if (pci_num_vf(bp->pdev))
6095 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1);
6096 req.flags = cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_FORCE_LINK_DWN);
6097 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6100 static int bnxt_hwrm_port_led_qcaps(struct bnxt *bp)
6102 struct hwrm_port_led_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
6103 struct hwrm_port_led_qcaps_input req = {0};
6104 struct bnxt_pf_info *pf = &bp->pf;
6107 if (BNXT_VF(bp) || bp->hwrm_spec_code < 0x10601)
6110 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_LED_QCAPS, -1, -1);
6111 req.port_id = cpu_to_le16(pf->port_id);
6112 mutex_lock(&bp->hwrm_cmd_lock);
6113 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6115 mutex_unlock(&bp->hwrm_cmd_lock);
6118 if (resp->num_leds > 0 && resp->num_leds < BNXT_MAX_LED) {
6121 bp->num_leds = resp->num_leds;
6122 memcpy(bp->leds, &resp->led0_id, sizeof(bp->leds[0]) *
6124 for (i = 0; i < bp->num_leds; i++) {
6125 struct bnxt_led_info *led = &bp->leds[i];
6126 __le16 caps = led->led_state_caps;
6128 if (!led->led_group_id ||
6129 !BNXT_LED_ALT_BLINK_CAP(caps)) {
6135 mutex_unlock(&bp->hwrm_cmd_lock);
6139 int bnxt_hwrm_alloc_wol_fltr(struct bnxt *bp)
6141 struct hwrm_wol_filter_alloc_input req = {0};
6142 struct hwrm_wol_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
6145 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_WOL_FILTER_ALLOC, -1, -1);
6146 req.port_id = cpu_to_le16(bp->pf.port_id);
6147 req.wol_type = WOL_FILTER_ALLOC_REQ_WOL_TYPE_MAGICPKT;
6148 req.enables = cpu_to_le32(WOL_FILTER_ALLOC_REQ_ENABLES_MAC_ADDRESS);
6149 memcpy(req.mac_address, bp->dev->dev_addr, ETH_ALEN);
6150 mutex_lock(&bp->hwrm_cmd_lock);
6151 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6153 bp->wol_filter_id = resp->wol_filter_id;
6154 mutex_unlock(&bp->hwrm_cmd_lock);
6158 int bnxt_hwrm_free_wol_fltr(struct bnxt *bp)
6160 struct hwrm_wol_filter_free_input req = {0};
6163 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_WOL_FILTER_FREE, -1, -1);
6164 req.port_id = cpu_to_le16(bp->pf.port_id);
6165 req.enables = cpu_to_le32(WOL_FILTER_FREE_REQ_ENABLES_WOL_FILTER_ID);
6166 req.wol_filter_id = bp->wol_filter_id;
6167 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6171 static u16 bnxt_hwrm_get_wol_fltrs(struct bnxt *bp, u16 handle)
6173 struct hwrm_wol_filter_qcfg_input req = {0};
6174 struct hwrm_wol_filter_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
6175 u16 next_handle = 0;
6178 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_WOL_FILTER_QCFG, -1, -1);
6179 req.port_id = cpu_to_le16(bp->pf.port_id);
6180 req.handle = cpu_to_le16(handle);
6181 mutex_lock(&bp->hwrm_cmd_lock);
6182 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6184 next_handle = le16_to_cpu(resp->next_handle);
6185 if (next_handle != 0) {
6186 if (resp->wol_type ==
6187 WOL_FILTER_ALLOC_REQ_WOL_TYPE_MAGICPKT) {
6189 bp->wol_filter_id = resp->wol_filter_id;
6193 mutex_unlock(&bp->hwrm_cmd_lock);
6197 static void bnxt_get_wol_settings(struct bnxt *bp)
6201 if (!BNXT_PF(bp) || !(bp->flags & BNXT_FLAG_WOL_CAP))
6205 handle = bnxt_hwrm_get_wol_fltrs(bp, handle);
6206 } while (handle && handle != 0xffff);
6209 static bool bnxt_eee_config_ok(struct bnxt *bp)
6211 struct ethtool_eee *eee = &bp->eee;
6212 struct bnxt_link_info *link_info = &bp->link_info;
6214 if (!(bp->flags & BNXT_FLAG_EEE_CAP))
6217 if (eee->eee_enabled) {
6219 _bnxt_fw_to_ethtool_adv_spds(link_info->advertising, 0);
6221 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) {
6222 eee->eee_enabled = 0;
6225 if (eee->advertised & ~advertising) {
6226 eee->advertised = advertising & eee->supported;
6233 static int bnxt_update_phy_setting(struct bnxt *bp)
6236 bool update_link = false;
6237 bool update_pause = false;
6238 bool update_eee = false;
6239 struct bnxt_link_info *link_info = &bp->link_info;
6241 rc = bnxt_update_link(bp, true);
6243 netdev_err(bp->dev, "failed to update link (rc: %x)\n",
6247 if (!BNXT_SINGLE_PF(bp))
6250 if ((link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) &&
6251 (link_info->auto_pause_setting & BNXT_LINK_PAUSE_BOTH) !=
6252 link_info->req_flow_ctrl)
6253 update_pause = true;
6254 if (!(link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) &&
6255 link_info->force_pause_setting != link_info->req_flow_ctrl)
6256 update_pause = true;
6257 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) {
6258 if (BNXT_AUTO_MODE(link_info->auto_mode))
6260 if (link_info->req_link_speed != link_info->force_link_speed)
6262 if (link_info->req_duplex != link_info->duplex_setting)
6265 if (link_info->auto_mode == BNXT_LINK_AUTO_NONE)
6267 if (link_info->advertising != link_info->auto_link_speeds)
6271 /* The last close may have shutdown the link, so need to call
6272 * PHY_CFG to bring it back up.
6274 if (!netif_carrier_ok(bp->dev))
6277 if (!bnxt_eee_config_ok(bp))
6281 rc = bnxt_hwrm_set_link_setting(bp, update_pause, update_eee);
6282 else if (update_pause)
6283 rc = bnxt_hwrm_set_pause(bp);
6285 netdev_err(bp->dev, "failed to update phy setting (rc: %x)\n",
6293 /* Common routine to pre-map certain register block to different GRC window.
6294 * A PF has 16 4K windows and a VF has 4 4K windows. However, only 15 windows
6295 * in PF and 3 windows in VF that can be customized to map in different
6298 static void bnxt_preset_reg_win(struct bnxt *bp)
6301 /* CAG registers map to GRC window #4 */
6302 writel(BNXT_CAG_REG_BASE,
6303 bp->bar0 + BNXT_GRCPF_REG_WINDOW_BASE_OUT + 12);
6307 static int __bnxt_open_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init)
6311 bnxt_preset_reg_win(bp);
6312 netif_carrier_off(bp->dev);
6314 rc = bnxt_setup_int_mode(bp);
6316 netdev_err(bp->dev, "bnxt_setup_int_mode err: %x\n",
6321 if ((bp->flags & BNXT_FLAG_RFS) &&
6322 !(bp->flags & BNXT_FLAG_USING_MSIX)) {
6323 /* disable RFS if falling back to INTA */
6324 bp->dev->hw_features &= ~NETIF_F_NTUPLE;
6325 bp->flags &= ~BNXT_FLAG_RFS;
6328 rc = bnxt_alloc_mem(bp, irq_re_init);
6330 netdev_err(bp->dev, "bnxt_alloc_mem err: %x\n", rc);
6331 goto open_err_free_mem;
6336 rc = bnxt_request_irq(bp);
6338 netdev_err(bp->dev, "bnxt_request_irq err: %x\n", rc);
6343 bnxt_enable_napi(bp);
6345 rc = bnxt_init_nic(bp, irq_re_init);
6347 netdev_err(bp->dev, "bnxt_init_nic err: %x\n", rc);
6352 mutex_lock(&bp->link_lock);
6353 rc = bnxt_update_phy_setting(bp);
6354 mutex_unlock(&bp->link_lock);
6356 netdev_warn(bp->dev, "failed to update phy settings\n");
6360 udp_tunnel_get_rx_info(bp->dev);
6362 set_bit(BNXT_STATE_OPEN, &bp->state);
6363 bnxt_enable_int(bp);
6364 /* Enable TX queues */
6366 mod_timer(&bp->timer, jiffies + bp->current_interval);
6367 /* Poll link status and check for SFP+ module status */
6368 bnxt_get_port_module_status(bp);
6370 /* VF-reps may need to be re-opened after the PF is re-opened */
6372 bnxt_vf_reps_open(bp);
6376 bnxt_disable_napi(bp);
6382 bnxt_free_mem(bp, true);
6386 /* rtnl_lock held */
6387 int bnxt_open_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init)
6391 rc = __bnxt_open_nic(bp, irq_re_init, link_re_init);
6393 netdev_err(bp->dev, "nic open fail (rc: %x)\n", rc);
6399 /* rtnl_lock held, open the NIC half way by allocating all resources, but
6400 * NAPI, IRQ, and TX are not enabled. This is mainly used for offline
6403 int bnxt_half_open_nic(struct bnxt *bp)
6407 rc = bnxt_alloc_mem(bp, false);
6409 netdev_err(bp->dev, "bnxt_alloc_mem err: %x\n", rc);
6412 rc = bnxt_init_nic(bp, false);
6414 netdev_err(bp->dev, "bnxt_init_nic err: %x\n", rc);
6421 bnxt_free_mem(bp, false);
6426 /* rtnl_lock held, this call can only be made after a previous successful
6427 * call to bnxt_half_open_nic().
6429 void bnxt_half_close_nic(struct bnxt *bp)
6431 bnxt_hwrm_resource_free(bp, false, false);
6433 bnxt_free_mem(bp, false);
6436 static int bnxt_open(struct net_device *dev)
6438 struct bnxt *bp = netdev_priv(dev);
6440 return __bnxt_open_nic(bp, true, true);
6443 static bool bnxt_drv_busy(struct bnxt *bp)
6445 return (test_bit(BNXT_STATE_IN_SP_TASK, &bp->state) ||
6446 test_bit(BNXT_STATE_READ_STATS, &bp->state));
6449 int bnxt_close_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init)
6453 #ifdef CONFIG_BNXT_SRIOV
6454 if (bp->sriov_cfg) {
6455 rc = wait_event_interruptible_timeout(bp->sriov_cfg_wait,
6457 BNXT_SRIOV_CFG_WAIT_TMO);
6459 netdev_warn(bp->dev, "timeout waiting for SRIOV config operation to complete!\n");
6462 /* Close the VF-reps before closing PF */
6464 bnxt_vf_reps_close(bp);
6466 /* Change device state to avoid TX queue wake up's */
6467 bnxt_tx_disable(bp);
6469 clear_bit(BNXT_STATE_OPEN, &bp->state);
6470 smp_mb__after_atomic();
6471 while (bnxt_drv_busy(bp))
6474 /* Flush rings and and disable interrupts */
6475 bnxt_shutdown_nic(bp, irq_re_init);
6477 /* TODO CHIMP_FW: Link/PHY related cleanup if (link_re_init) */
6479 bnxt_disable_napi(bp);
6480 del_timer_sync(&bp->timer);
6487 bnxt_free_mem(bp, irq_re_init);
6491 static int bnxt_close(struct net_device *dev)
6493 struct bnxt *bp = netdev_priv(dev);
6495 bnxt_close_nic(bp, true, true);
6496 bnxt_hwrm_shutdown_link(bp);
6500 /* rtnl_lock held */
6501 static int bnxt_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
6507 if (!netif_running(dev))
6514 if (!netif_running(dev))
6527 bnxt_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
6530 struct bnxt *bp = netdev_priv(dev);
6532 set_bit(BNXT_STATE_READ_STATS, &bp->state);
6533 /* Make sure bnxt_close_nic() sees that we are reading stats before
6534 * we check the BNXT_STATE_OPEN flag.
6536 smp_mb__after_atomic();
6537 if (!test_bit(BNXT_STATE_OPEN, &bp->state)) {
6538 clear_bit(BNXT_STATE_READ_STATS, &bp->state);
6542 /* TODO check if we need to synchronize with bnxt_close path */
6543 for (i = 0; i < bp->cp_nr_rings; i++) {
6544 struct bnxt_napi *bnapi = bp->bnapi[i];
6545 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
6546 struct ctx_hw_stats *hw_stats = cpr->hw_stats;
6548 stats->rx_packets += le64_to_cpu(hw_stats->rx_ucast_pkts);
6549 stats->rx_packets += le64_to_cpu(hw_stats->rx_mcast_pkts);
6550 stats->rx_packets += le64_to_cpu(hw_stats->rx_bcast_pkts);
6552 stats->tx_packets += le64_to_cpu(hw_stats->tx_ucast_pkts);
6553 stats->tx_packets += le64_to_cpu(hw_stats->tx_mcast_pkts);
6554 stats->tx_packets += le64_to_cpu(hw_stats->tx_bcast_pkts);
6556 stats->rx_bytes += le64_to_cpu(hw_stats->rx_ucast_bytes);
6557 stats->rx_bytes += le64_to_cpu(hw_stats->rx_mcast_bytes);
6558 stats->rx_bytes += le64_to_cpu(hw_stats->rx_bcast_bytes);
6560 stats->tx_bytes += le64_to_cpu(hw_stats->tx_ucast_bytes);
6561 stats->tx_bytes += le64_to_cpu(hw_stats->tx_mcast_bytes);
6562 stats->tx_bytes += le64_to_cpu(hw_stats->tx_bcast_bytes);
6564 stats->rx_missed_errors +=
6565 le64_to_cpu(hw_stats->rx_discard_pkts);
6567 stats->multicast += le64_to_cpu(hw_stats->rx_mcast_pkts);
6569 stats->tx_dropped += le64_to_cpu(hw_stats->tx_drop_pkts);
6572 if (bp->flags & BNXT_FLAG_PORT_STATS) {
6573 struct rx_port_stats *rx = bp->hw_rx_port_stats;
6574 struct tx_port_stats *tx = bp->hw_tx_port_stats;
6576 stats->rx_crc_errors = le64_to_cpu(rx->rx_fcs_err_frames);
6577 stats->rx_frame_errors = le64_to_cpu(rx->rx_align_err_frames);
6578 stats->rx_length_errors = le64_to_cpu(rx->rx_undrsz_frames) +
6579 le64_to_cpu(rx->rx_ovrsz_frames) +
6580 le64_to_cpu(rx->rx_runt_frames);
6581 stats->rx_errors = le64_to_cpu(rx->rx_false_carrier_frames) +
6582 le64_to_cpu(rx->rx_jbr_frames);
6583 stats->collisions = le64_to_cpu(tx->tx_total_collisions);
6584 stats->tx_fifo_errors = le64_to_cpu(tx->tx_fifo_underruns);
6585 stats->tx_errors = le64_to_cpu(tx->tx_err);
6587 clear_bit(BNXT_STATE_READ_STATS, &bp->state);
6590 static bool bnxt_mc_list_updated(struct bnxt *bp, u32 *rx_mask)
6592 struct net_device *dev = bp->dev;
6593 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
6594 struct netdev_hw_addr *ha;
6597 bool update = false;
6600 netdev_for_each_mc_addr(ha, dev) {
6601 if (mc_count >= BNXT_MAX_MC_ADDRS) {
6602 *rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST;
6603 vnic->mc_list_count = 0;
6607 if (!ether_addr_equal(haddr, vnic->mc_list + off)) {
6608 memcpy(vnic->mc_list + off, haddr, ETH_ALEN);
6615 *rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_MCAST;
6617 if (mc_count != vnic->mc_list_count) {
6618 vnic->mc_list_count = mc_count;
6624 static bool bnxt_uc_list_updated(struct bnxt *bp)
6626 struct net_device *dev = bp->dev;
6627 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
6628 struct netdev_hw_addr *ha;
6631 if (netdev_uc_count(dev) != (vnic->uc_filter_count - 1))
6634 netdev_for_each_uc_addr(ha, dev) {
6635 if (!ether_addr_equal(ha->addr, vnic->uc_list + off))
6643 static void bnxt_set_rx_mode(struct net_device *dev)
6645 struct bnxt *bp = netdev_priv(dev);
6646 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
6647 u32 mask = vnic->rx_mask;
6648 bool mc_update = false;
6651 if (!netif_running(dev))
6654 mask &= ~(CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS |
6655 CFA_L2_SET_RX_MASK_REQ_MASK_MCAST |
6656 CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST);
6658 if ((dev->flags & IFF_PROMISC) && bnxt_promisc_ok(bp))
6659 mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS;
6661 uc_update = bnxt_uc_list_updated(bp);
6663 if (dev->flags & IFF_ALLMULTI) {
6664 mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST;
6665 vnic->mc_list_count = 0;
6667 mc_update = bnxt_mc_list_updated(bp, &mask);
6670 if (mask != vnic->rx_mask || uc_update || mc_update) {
6671 vnic->rx_mask = mask;
6673 set_bit(BNXT_RX_MASK_SP_EVENT, &bp->sp_event);
6674 bnxt_queue_sp_work(bp);
6678 static int bnxt_cfg_rx_mode(struct bnxt *bp)
6680 struct net_device *dev = bp->dev;
6681 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
6682 struct netdev_hw_addr *ha;
6686 netif_addr_lock_bh(dev);
6687 uc_update = bnxt_uc_list_updated(bp);
6688 netif_addr_unlock_bh(dev);
6693 mutex_lock(&bp->hwrm_cmd_lock);
6694 for (i = 1; i < vnic->uc_filter_count; i++) {
6695 struct hwrm_cfa_l2_filter_free_input req = {0};
6697 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_FILTER_FREE, -1,
6700 req.l2_filter_id = vnic->fw_l2_filter_id[i];
6702 rc = _hwrm_send_message(bp, &req, sizeof(req),
6705 mutex_unlock(&bp->hwrm_cmd_lock);
6707 vnic->uc_filter_count = 1;
6709 netif_addr_lock_bh(dev);
6710 if (netdev_uc_count(dev) > (BNXT_MAX_UC_ADDRS - 1)) {
6711 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS;
6713 netdev_for_each_uc_addr(ha, dev) {
6714 memcpy(vnic->uc_list + off, ha->addr, ETH_ALEN);
6716 vnic->uc_filter_count++;
6719 netif_addr_unlock_bh(dev);
6721 for (i = 1, off = 0; i < vnic->uc_filter_count; i++, off += ETH_ALEN) {
6722 rc = bnxt_hwrm_set_vnic_filter(bp, 0, i, vnic->uc_list + off);
6724 netdev_err(bp->dev, "HWRM vnic filter failure rc: %x\n",
6726 vnic->uc_filter_count = i;
6732 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, 0);
6734 netdev_err(bp->dev, "HWRM cfa l2 rx mask failure rc: %x\n",
6740 /* If the chip and firmware supports RFS */
6741 static bool bnxt_rfs_supported(struct bnxt *bp)
6743 if (BNXT_PF(bp) && !BNXT_CHIP_TYPE_NITRO_A0(bp))
6745 if (bp->flags & BNXT_FLAG_NEW_RSS_CAP)
6750 /* If runtime conditions support RFS */
6751 static bool bnxt_rfs_capable(struct bnxt *bp)
6753 #ifdef CONFIG_RFS_ACCEL
6754 int vnics, max_vnics, max_rss_ctxs;
6756 if (!(bp->flags & BNXT_FLAG_MSIX_CAP))
6759 vnics = 1 + bp->rx_nr_rings;
6760 max_vnics = bnxt_get_max_func_vnics(bp);
6761 max_rss_ctxs = bnxt_get_max_func_rss_ctxs(bp);
6763 /* RSS contexts not a limiting factor */
6764 if (bp->flags & BNXT_FLAG_NEW_RSS_CAP)
6765 max_rss_ctxs = max_vnics;
6766 if (vnics > max_vnics || vnics > max_rss_ctxs) {
6767 netdev_warn(bp->dev,
6768 "Not enough resources to support NTUPLE filters, enough resources for up to %d rx rings\n",
6769 min(max_rss_ctxs - 1, max_vnics - 1));
6779 static netdev_features_t bnxt_fix_features(struct net_device *dev,
6780 netdev_features_t features)
6782 struct bnxt *bp = netdev_priv(dev);
6784 if ((features & NETIF_F_NTUPLE) && !bnxt_rfs_capable(bp))
6785 features &= ~NETIF_F_NTUPLE;
6787 /* Both CTAG and STAG VLAN accelaration on the RX side have to be
6788 * turned on or off together.
6790 if ((features & (NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_STAG_RX)) !=
6791 (NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_STAG_RX)) {
6792 if (dev->features & NETIF_F_HW_VLAN_CTAG_RX)
6793 features &= ~(NETIF_F_HW_VLAN_CTAG_RX |
6794 NETIF_F_HW_VLAN_STAG_RX);
6796 features |= NETIF_F_HW_VLAN_CTAG_RX |
6797 NETIF_F_HW_VLAN_STAG_RX;
6799 #ifdef CONFIG_BNXT_SRIOV
6802 features &= ~(NETIF_F_HW_VLAN_CTAG_RX |
6803 NETIF_F_HW_VLAN_STAG_RX);
6810 static int bnxt_set_features(struct net_device *dev, netdev_features_t features)
6812 struct bnxt *bp = netdev_priv(dev);
6813 u32 flags = bp->flags;
6816 bool re_init = false;
6817 bool update_tpa = false;
6819 flags &= ~BNXT_FLAG_ALL_CONFIG_FEATS;
6820 if ((features & NETIF_F_GRO) && !BNXT_CHIP_TYPE_NITRO_A0(bp))
6821 flags |= BNXT_FLAG_GRO;
6822 if (features & NETIF_F_LRO)
6823 flags |= BNXT_FLAG_LRO;
6825 if (bp->flags & BNXT_FLAG_NO_AGG_RINGS)
6826 flags &= ~BNXT_FLAG_TPA;
6828 if (features & NETIF_F_HW_VLAN_CTAG_RX)
6829 flags |= BNXT_FLAG_STRIP_VLAN;
6831 if (features & NETIF_F_NTUPLE)
6832 flags |= BNXT_FLAG_RFS;
6834 changes = flags ^ bp->flags;
6835 if (changes & BNXT_FLAG_TPA) {
6837 if ((bp->flags & BNXT_FLAG_TPA) == 0 ||
6838 (flags & BNXT_FLAG_TPA) == 0)
6842 if (changes & ~BNXT_FLAG_TPA)
6845 if (flags != bp->flags) {
6846 u32 old_flags = bp->flags;
6850 if (!test_bit(BNXT_STATE_OPEN, &bp->state)) {
6852 bnxt_set_ring_params(bp);
6857 bnxt_close_nic(bp, false, false);
6859 bnxt_set_ring_params(bp);
6861 return bnxt_open_nic(bp, false, false);
6864 rc = bnxt_set_tpa(bp,
6865 (flags & BNXT_FLAG_TPA) ?
6868 bp->flags = old_flags;
6874 static void bnxt_dump_tx_sw_state(struct bnxt_napi *bnapi)
6876 struct bnxt_tx_ring_info *txr = bnapi->tx_ring;
6877 int i = bnapi->index;
6882 netdev_info(bnapi->bp->dev, "[%d]: tx{fw_ring: %d prod: %x cons: %x}\n",
6883 i, txr->tx_ring_struct.fw_ring_id, txr->tx_prod,
6887 static void bnxt_dump_rx_sw_state(struct bnxt_napi *bnapi)
6889 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
6890 int i = bnapi->index;
6895 netdev_info(bnapi->bp->dev, "[%d]: rx{fw_ring: %d prod: %x} rx_agg{fw_ring: %d agg_prod: %x sw_agg_prod: %x}\n",
6896 i, rxr->rx_ring_struct.fw_ring_id, rxr->rx_prod,
6897 rxr->rx_agg_ring_struct.fw_ring_id, rxr->rx_agg_prod,
6898 rxr->rx_sw_agg_prod);
6901 static void bnxt_dump_cp_sw_state(struct bnxt_napi *bnapi)
6903 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
6904 int i = bnapi->index;
6906 netdev_info(bnapi->bp->dev, "[%d]: cp{fw_ring: %d raw_cons: %x}\n",
6907 i, cpr->cp_ring_struct.fw_ring_id, cpr->cp_raw_cons);
6910 static void bnxt_dbg_dump_states(struct bnxt *bp)
6913 struct bnxt_napi *bnapi;
6915 for (i = 0; i < bp->cp_nr_rings; i++) {
6916 bnapi = bp->bnapi[i];
6917 if (netif_msg_drv(bp)) {
6918 bnxt_dump_tx_sw_state(bnapi);
6919 bnxt_dump_rx_sw_state(bnapi);
6920 bnxt_dump_cp_sw_state(bnapi);
6925 static void bnxt_reset_task(struct bnxt *bp, bool silent)
6928 bnxt_dbg_dump_states(bp);
6929 if (netif_running(bp->dev)) {
6934 bnxt_close_nic(bp, false, false);
6935 rc = bnxt_open_nic(bp, false, false);
6941 static void bnxt_tx_timeout(struct net_device *dev)
6943 struct bnxt *bp = netdev_priv(dev);
6945 netdev_err(bp->dev, "TX timeout detected, starting reset task!\n");
6946 set_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event);
6947 bnxt_queue_sp_work(bp);
6950 #ifdef CONFIG_NET_POLL_CONTROLLER
6951 static void bnxt_poll_controller(struct net_device *dev)
6953 struct bnxt *bp = netdev_priv(dev);
6956 /* Only process tx rings/combined rings in netpoll mode. */
6957 for (i = 0; i < bp->tx_nr_rings; i++) {
6958 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
6960 napi_schedule(&txr->bnapi->napi);
6965 static void bnxt_timer(struct timer_list *t)
6967 struct bnxt *bp = from_timer(bp, t, timer);
6968 struct net_device *dev = bp->dev;
6970 if (!netif_running(dev))
6973 if (atomic_read(&bp->intr_sem) != 0)
6974 goto bnxt_restart_timer;
6976 if (bp->link_info.link_up && (bp->flags & BNXT_FLAG_PORT_STATS) &&
6977 bp->stats_coal_ticks) {
6978 set_bit(BNXT_PERIODIC_STATS_SP_EVENT, &bp->sp_event);
6979 bnxt_queue_sp_work(bp);
6982 if (bnxt_tc_flower_enabled(bp)) {
6983 set_bit(BNXT_FLOW_STATS_SP_EVENT, &bp->sp_event);
6984 bnxt_queue_sp_work(bp);
6987 mod_timer(&bp->timer, jiffies + bp->current_interval);
6990 static void bnxt_rtnl_lock_sp(struct bnxt *bp)
6992 /* We are called from bnxt_sp_task which has BNXT_STATE_IN_SP_TASK
6993 * set. If the device is being closed, bnxt_close() may be holding
6994 * rtnl() and waiting for BNXT_STATE_IN_SP_TASK to clear. So we
6995 * must clear BNXT_STATE_IN_SP_TASK before holding rtnl().
6997 clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
7001 static void bnxt_rtnl_unlock_sp(struct bnxt *bp)
7003 set_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
7007 /* Only called from bnxt_sp_task() */
7008 static void bnxt_reset(struct bnxt *bp, bool silent)
7010 bnxt_rtnl_lock_sp(bp);
7011 if (test_bit(BNXT_STATE_OPEN, &bp->state))
7012 bnxt_reset_task(bp, silent);
7013 bnxt_rtnl_unlock_sp(bp);
7016 static void bnxt_cfg_ntp_filters(struct bnxt *);
7018 static void bnxt_sp_task(struct work_struct *work)
7020 struct bnxt *bp = container_of(work, struct bnxt, sp_task);
7022 set_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
7023 smp_mb__after_atomic();
7024 if (!test_bit(BNXT_STATE_OPEN, &bp->state)) {
7025 clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
7029 if (test_and_clear_bit(BNXT_RX_MASK_SP_EVENT, &bp->sp_event))
7030 bnxt_cfg_rx_mode(bp);
7032 if (test_and_clear_bit(BNXT_RX_NTP_FLTR_SP_EVENT, &bp->sp_event))
7033 bnxt_cfg_ntp_filters(bp);
7034 if (test_and_clear_bit(BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT, &bp->sp_event))
7035 bnxt_hwrm_exec_fwd_req(bp);
7036 if (test_and_clear_bit(BNXT_VXLAN_ADD_PORT_SP_EVENT, &bp->sp_event)) {
7037 bnxt_hwrm_tunnel_dst_port_alloc(
7039 TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN);
7041 if (test_and_clear_bit(BNXT_VXLAN_DEL_PORT_SP_EVENT, &bp->sp_event)) {
7042 bnxt_hwrm_tunnel_dst_port_free(
7043 bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN);
7045 if (test_and_clear_bit(BNXT_GENEVE_ADD_PORT_SP_EVENT, &bp->sp_event)) {
7046 bnxt_hwrm_tunnel_dst_port_alloc(
7048 TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE);
7050 if (test_and_clear_bit(BNXT_GENEVE_DEL_PORT_SP_EVENT, &bp->sp_event)) {
7051 bnxt_hwrm_tunnel_dst_port_free(
7052 bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE);
7054 if (test_and_clear_bit(BNXT_PERIODIC_STATS_SP_EVENT, &bp->sp_event))
7055 bnxt_hwrm_port_qstats(bp);
7057 if (test_and_clear_bit(BNXT_LINK_CHNG_SP_EVENT, &bp->sp_event)) {
7060 mutex_lock(&bp->link_lock);
7061 if (test_and_clear_bit(BNXT_LINK_SPEED_CHNG_SP_EVENT,
7063 bnxt_hwrm_phy_qcaps(bp);
7065 rc = bnxt_update_link(bp, true);
7066 mutex_unlock(&bp->link_lock);
7068 netdev_err(bp->dev, "SP task can't update link (rc: %x)\n",
7071 if (test_and_clear_bit(BNXT_HWRM_PORT_MODULE_SP_EVENT, &bp->sp_event)) {
7072 mutex_lock(&bp->link_lock);
7073 bnxt_get_port_module_status(bp);
7074 mutex_unlock(&bp->link_lock);
7077 if (test_and_clear_bit(BNXT_FLOW_STATS_SP_EVENT, &bp->sp_event))
7078 bnxt_tc_flow_stats_work(bp);
7080 /* These functions below will clear BNXT_STATE_IN_SP_TASK. They
7081 * must be the last functions to be called before exiting.
7083 if (test_and_clear_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event))
7084 bnxt_reset(bp, false);
7086 if (test_and_clear_bit(BNXT_RESET_TASK_SILENT_SP_EVENT, &bp->sp_event))
7087 bnxt_reset(bp, true);
7089 smp_mb__before_atomic();
7090 clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
7093 /* Under rtnl_lock */
7094 int bnxt_check_rings(struct bnxt *bp, int tx, int rx, bool sh, int tcs,
7097 int max_rx, max_tx, tx_sets = 1;
7098 int tx_rings_needed;
7104 rc = bnxt_get_max_rings(bp, &max_rx, &max_tx, sh);
7111 tx_rings_needed = tx * tx_sets + tx_xdp;
7112 if (max_tx < tx_rings_needed)
7115 return bnxt_hwrm_check_tx_rings(bp, tx_rings_needed);
7118 static void bnxt_unmap_bars(struct bnxt *bp, struct pci_dev *pdev)
7121 pci_iounmap(pdev, bp->bar2);
7126 pci_iounmap(pdev, bp->bar1);
7131 pci_iounmap(pdev, bp->bar0);
7136 static void bnxt_cleanup_pci(struct bnxt *bp)
7138 bnxt_unmap_bars(bp, bp->pdev);
7139 pci_release_regions(bp->pdev);
7140 pci_disable_device(bp->pdev);
7143 static void bnxt_init_dflt_coal(struct bnxt *bp)
7145 struct bnxt_coal *coal;
7147 /* Tick values in micro seconds.
7148 * 1 coal_buf x bufs_per_record = 1 completion record.
7150 coal = &bp->rx_coal;
7151 coal->coal_ticks = 14;
7152 coal->coal_bufs = 30;
7153 coal->coal_ticks_irq = 1;
7154 coal->coal_bufs_irq = 2;
7155 coal->idle_thresh = 25;
7156 coal->bufs_per_record = 2;
7157 coal->budget = 64; /* NAPI budget */
7159 coal = &bp->tx_coal;
7160 coal->coal_ticks = 28;
7161 coal->coal_bufs = 30;
7162 coal->coal_ticks_irq = 2;
7163 coal->coal_bufs_irq = 2;
7164 coal->bufs_per_record = 1;
7166 bp->stats_coal_ticks = BNXT_DEF_STATS_COAL_TICKS;
7169 static int bnxt_init_board(struct pci_dev *pdev, struct net_device *dev)
7172 struct bnxt *bp = netdev_priv(dev);
7174 SET_NETDEV_DEV(dev, &pdev->dev);
7176 /* enable device (incl. PCI PM wakeup), and bus-mastering */
7177 rc = pci_enable_device(pdev);
7179 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
7183 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
7185 "Cannot find PCI device base address, aborting\n");
7187 goto init_err_disable;
7190 rc = pci_request_regions(pdev, DRV_MODULE_NAME);
7192 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n");
7193 goto init_err_disable;
7196 if (dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)) != 0 &&
7197 dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)) != 0) {
7198 dev_err(&pdev->dev, "System does not support DMA, aborting\n");
7199 goto init_err_disable;
7202 pci_set_master(pdev);
7207 bp->bar0 = pci_ioremap_bar(pdev, 0);
7209 dev_err(&pdev->dev, "Cannot map device registers, aborting\n");
7211 goto init_err_release;
7214 bp->bar1 = pci_ioremap_bar(pdev, 2);
7216 dev_err(&pdev->dev, "Cannot map doorbell registers, aborting\n");
7218 goto init_err_release;
7221 bp->bar2 = pci_ioremap_bar(pdev, 4);
7223 dev_err(&pdev->dev, "Cannot map bar4 registers, aborting\n");
7225 goto init_err_release;
7228 pci_enable_pcie_error_reporting(pdev);
7230 INIT_WORK(&bp->sp_task, bnxt_sp_task);
7232 spin_lock_init(&bp->ntp_fltr_lock);
7234 bp->rx_ring_size = BNXT_DEFAULT_RX_RING_SIZE;
7235 bp->tx_ring_size = BNXT_DEFAULT_TX_RING_SIZE;
7237 bnxt_init_dflt_coal(bp);
7239 timer_setup(&bp->timer, bnxt_timer, 0);
7240 bp->current_interval = BNXT_TIMER_INTERVAL;
7242 clear_bit(BNXT_STATE_OPEN, &bp->state);
7246 bnxt_unmap_bars(bp, pdev);
7247 pci_release_regions(pdev);
7250 pci_disable_device(pdev);
7256 /* rtnl_lock held */
7257 static int bnxt_change_mac_addr(struct net_device *dev, void *p)
7259 struct sockaddr *addr = p;
7260 struct bnxt *bp = netdev_priv(dev);
7263 if (!is_valid_ether_addr(addr->sa_data))
7264 return -EADDRNOTAVAIL;
7266 if (ether_addr_equal(addr->sa_data, dev->dev_addr))
7269 rc = bnxt_approve_mac(bp, addr->sa_data);
7273 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
7274 if (netif_running(dev)) {
7275 bnxt_close_nic(bp, false, false);
7276 rc = bnxt_open_nic(bp, false, false);
7282 /* rtnl_lock held */
7283 static int bnxt_change_mtu(struct net_device *dev, int new_mtu)
7285 struct bnxt *bp = netdev_priv(dev);
7287 if (netif_running(dev))
7288 bnxt_close_nic(bp, false, false);
7291 bnxt_set_ring_params(bp);
7293 if (netif_running(dev))
7294 return bnxt_open_nic(bp, false, false);
7299 int bnxt_setup_mq_tc(struct net_device *dev, u8 tc)
7301 struct bnxt *bp = netdev_priv(dev);
7305 if (tc > bp->max_tc) {
7306 netdev_err(dev, "Too many traffic classes requested: %d. Max supported is %d.\n",
7311 if (netdev_get_num_tc(dev) == tc)
7314 if (bp->flags & BNXT_FLAG_SHARED_RINGS)
7317 rc = bnxt_check_rings(bp, bp->tx_nr_rings_per_tc, bp->rx_nr_rings,
7318 sh, tc, bp->tx_nr_rings_xdp);
7322 /* Needs to close the device and do hw resource re-allocations */
7323 if (netif_running(bp->dev))
7324 bnxt_close_nic(bp, true, false);
7327 bp->tx_nr_rings = bp->tx_nr_rings_per_tc * tc;
7328 netdev_set_num_tc(dev, tc);
7330 bp->tx_nr_rings = bp->tx_nr_rings_per_tc;
7331 netdev_reset_tc(dev);
7333 bp->tx_nr_rings += bp->tx_nr_rings_xdp;
7334 bp->cp_nr_rings = sh ? max_t(int, bp->tx_nr_rings, bp->rx_nr_rings) :
7335 bp->tx_nr_rings + bp->rx_nr_rings;
7336 bp->num_stat_ctxs = bp->cp_nr_rings;
7338 if (netif_running(bp->dev))
7339 return bnxt_open_nic(bp, true, false);
7344 static int bnxt_setup_tc_block_cb(enum tc_setup_type type, void *type_data,
7347 struct bnxt *bp = cb_priv;
7349 if (!bnxt_tc_flower_enabled(bp) || !tc_can_offload(bp->dev))
7353 case TC_SETUP_CLSFLOWER:
7354 return bnxt_tc_setup_flower(bp, bp->pf.fw_fid, type_data);
7360 static int bnxt_setup_tc_block(struct net_device *dev,
7361 struct tc_block_offload *f)
7363 struct bnxt *bp = netdev_priv(dev);
7365 if (f->binder_type != TCF_BLOCK_BINDER_TYPE_CLSACT_INGRESS)
7368 switch (f->command) {
7370 return tcf_block_cb_register(f->block, bnxt_setup_tc_block_cb,
7372 case TC_BLOCK_UNBIND:
7373 tcf_block_cb_unregister(f->block, bnxt_setup_tc_block_cb, bp);
7380 static int bnxt_setup_tc(struct net_device *dev, enum tc_setup_type type,
7384 case TC_SETUP_BLOCK:
7385 return bnxt_setup_tc_block(dev, type_data);
7386 case TC_SETUP_QDISC_MQPRIO: {
7387 struct tc_mqprio_qopt *mqprio = type_data;
7389 mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS;
7391 return bnxt_setup_mq_tc(dev, mqprio->num_tc);
7398 #ifdef CONFIG_RFS_ACCEL
7399 static bool bnxt_fltr_match(struct bnxt_ntuple_filter *f1,
7400 struct bnxt_ntuple_filter *f2)
7402 struct flow_keys *keys1 = &f1->fkeys;
7403 struct flow_keys *keys2 = &f2->fkeys;
7405 if (keys1->addrs.v4addrs.src == keys2->addrs.v4addrs.src &&
7406 keys1->addrs.v4addrs.dst == keys2->addrs.v4addrs.dst &&
7407 keys1->ports.ports == keys2->ports.ports &&
7408 keys1->basic.ip_proto == keys2->basic.ip_proto &&
7409 keys1->basic.n_proto == keys2->basic.n_proto &&
7410 keys1->control.flags == keys2->control.flags &&
7411 ether_addr_equal(f1->src_mac_addr, f2->src_mac_addr) &&
7412 ether_addr_equal(f1->dst_mac_addr, f2->dst_mac_addr))
7418 static int bnxt_rx_flow_steer(struct net_device *dev, const struct sk_buff *skb,
7419 u16 rxq_index, u32 flow_id)
7421 struct bnxt *bp = netdev_priv(dev);
7422 struct bnxt_ntuple_filter *fltr, *new_fltr;
7423 struct flow_keys *fkeys;
7424 struct ethhdr *eth = (struct ethhdr *)skb_mac_header(skb);
7425 int rc = 0, idx, bit_id, l2_idx = 0;
7426 struct hlist_head *head;
7428 if (!ether_addr_equal(dev->dev_addr, eth->h_dest)) {
7429 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
7432 netif_addr_lock_bh(dev);
7433 for (j = 0; j < vnic->uc_filter_count; j++, off += ETH_ALEN) {
7434 if (ether_addr_equal(eth->h_dest,
7435 vnic->uc_list + off)) {
7440 netif_addr_unlock_bh(dev);
7444 new_fltr = kzalloc(sizeof(*new_fltr), GFP_ATOMIC);
7448 fkeys = &new_fltr->fkeys;
7449 if (!skb_flow_dissect_flow_keys(skb, fkeys, 0)) {
7450 rc = -EPROTONOSUPPORT;
7454 if ((fkeys->basic.n_proto != htons(ETH_P_IP) &&
7455 fkeys->basic.n_proto != htons(ETH_P_IPV6)) ||
7456 ((fkeys->basic.ip_proto != IPPROTO_TCP) &&
7457 (fkeys->basic.ip_proto != IPPROTO_UDP))) {
7458 rc = -EPROTONOSUPPORT;
7461 if (fkeys->basic.n_proto == htons(ETH_P_IPV6) &&
7462 bp->hwrm_spec_code < 0x10601) {
7463 rc = -EPROTONOSUPPORT;
7466 if ((fkeys->control.flags & FLOW_DIS_ENCAPSULATION) &&
7467 bp->hwrm_spec_code < 0x10601) {
7468 rc = -EPROTONOSUPPORT;
7472 memcpy(new_fltr->dst_mac_addr, eth->h_dest, ETH_ALEN);
7473 memcpy(new_fltr->src_mac_addr, eth->h_source, ETH_ALEN);
7475 idx = skb_get_hash_raw(skb) & BNXT_NTP_FLTR_HASH_MASK;
7476 head = &bp->ntp_fltr_hash_tbl[idx];
7478 hlist_for_each_entry_rcu(fltr, head, hash) {
7479 if (bnxt_fltr_match(fltr, new_fltr)) {
7487 spin_lock_bh(&bp->ntp_fltr_lock);
7488 bit_id = bitmap_find_free_region(bp->ntp_fltr_bmap,
7489 BNXT_NTP_FLTR_MAX_FLTR, 0);
7491 spin_unlock_bh(&bp->ntp_fltr_lock);
7496 new_fltr->sw_id = (u16)bit_id;
7497 new_fltr->flow_id = flow_id;
7498 new_fltr->l2_fltr_idx = l2_idx;
7499 new_fltr->rxq = rxq_index;
7500 hlist_add_head_rcu(&new_fltr->hash, head);
7501 bp->ntp_fltr_count++;
7502 spin_unlock_bh(&bp->ntp_fltr_lock);
7504 set_bit(BNXT_RX_NTP_FLTR_SP_EVENT, &bp->sp_event);
7505 bnxt_queue_sp_work(bp);
7507 return new_fltr->sw_id;
7514 static void bnxt_cfg_ntp_filters(struct bnxt *bp)
7518 for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) {
7519 struct hlist_head *head;
7520 struct hlist_node *tmp;
7521 struct bnxt_ntuple_filter *fltr;
7524 head = &bp->ntp_fltr_hash_tbl[i];
7525 hlist_for_each_entry_safe(fltr, tmp, head, hash) {
7528 if (test_bit(BNXT_FLTR_VALID, &fltr->state)) {
7529 if (rps_may_expire_flow(bp->dev, fltr->rxq,
7532 bnxt_hwrm_cfa_ntuple_filter_free(bp,
7537 rc = bnxt_hwrm_cfa_ntuple_filter_alloc(bp,
7542 set_bit(BNXT_FLTR_VALID, &fltr->state);
7546 spin_lock_bh(&bp->ntp_fltr_lock);
7547 hlist_del_rcu(&fltr->hash);
7548 bp->ntp_fltr_count--;
7549 spin_unlock_bh(&bp->ntp_fltr_lock);
7551 clear_bit(fltr->sw_id, bp->ntp_fltr_bmap);
7556 if (test_and_clear_bit(BNXT_HWRM_PF_UNLOAD_SP_EVENT, &bp->sp_event))
7557 netdev_info(bp->dev, "Receive PF driver unload event!");
7562 static void bnxt_cfg_ntp_filters(struct bnxt *bp)
7566 #endif /* CONFIG_RFS_ACCEL */
7568 static void bnxt_udp_tunnel_add(struct net_device *dev,
7569 struct udp_tunnel_info *ti)
7571 struct bnxt *bp = netdev_priv(dev);
7573 if (ti->sa_family != AF_INET6 && ti->sa_family != AF_INET)
7576 if (!netif_running(dev))
7580 case UDP_TUNNEL_TYPE_VXLAN:
7581 if (bp->vxlan_port_cnt && bp->vxlan_port != ti->port)
7584 bp->vxlan_port_cnt++;
7585 if (bp->vxlan_port_cnt == 1) {
7586 bp->vxlan_port = ti->port;
7587 set_bit(BNXT_VXLAN_ADD_PORT_SP_EVENT, &bp->sp_event);
7588 bnxt_queue_sp_work(bp);
7591 case UDP_TUNNEL_TYPE_GENEVE:
7592 if (bp->nge_port_cnt && bp->nge_port != ti->port)
7596 if (bp->nge_port_cnt == 1) {
7597 bp->nge_port = ti->port;
7598 set_bit(BNXT_GENEVE_ADD_PORT_SP_EVENT, &bp->sp_event);
7605 bnxt_queue_sp_work(bp);
7608 static void bnxt_udp_tunnel_del(struct net_device *dev,
7609 struct udp_tunnel_info *ti)
7611 struct bnxt *bp = netdev_priv(dev);
7613 if (ti->sa_family != AF_INET6 && ti->sa_family != AF_INET)
7616 if (!netif_running(dev))
7620 case UDP_TUNNEL_TYPE_VXLAN:
7621 if (!bp->vxlan_port_cnt || bp->vxlan_port != ti->port)
7623 bp->vxlan_port_cnt--;
7625 if (bp->vxlan_port_cnt != 0)
7628 set_bit(BNXT_VXLAN_DEL_PORT_SP_EVENT, &bp->sp_event);
7630 case UDP_TUNNEL_TYPE_GENEVE:
7631 if (!bp->nge_port_cnt || bp->nge_port != ti->port)
7635 if (bp->nge_port_cnt != 0)
7638 set_bit(BNXT_GENEVE_DEL_PORT_SP_EVENT, &bp->sp_event);
7644 bnxt_queue_sp_work(bp);
7647 static int bnxt_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq,
7648 struct net_device *dev, u32 filter_mask,
7651 struct bnxt *bp = netdev_priv(dev);
7653 return ndo_dflt_bridge_getlink(skb, pid, seq, dev, bp->br_mode, 0, 0,
7654 nlflags, filter_mask, NULL);
7657 static int bnxt_bridge_setlink(struct net_device *dev, struct nlmsghdr *nlh,
7660 struct bnxt *bp = netdev_priv(dev);
7661 struct nlattr *attr, *br_spec;
7664 if (bp->hwrm_spec_code < 0x10708 || !BNXT_SINGLE_PF(bp))
7667 br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC);
7671 nla_for_each_nested(attr, br_spec, rem) {
7674 if (nla_type(attr) != IFLA_BRIDGE_MODE)
7677 if (nla_len(attr) < sizeof(mode))
7680 mode = nla_get_u16(attr);
7681 if (mode == bp->br_mode)
7684 rc = bnxt_hwrm_set_br_mode(bp, mode);
7692 static int bnxt_get_phys_port_name(struct net_device *dev, char *buf,
7695 struct bnxt *bp = netdev_priv(dev);
7698 /* The PF and it's VF-reps only support the switchdev framework */
7702 rc = snprintf(buf, len, "p%d", bp->pf.port_id);
7709 int bnxt_port_attr_get(struct bnxt *bp, struct switchdev_attr *attr)
7711 if (bp->eswitch_mode != DEVLINK_ESWITCH_MODE_SWITCHDEV)
7714 /* The PF and it's VF-reps only support the switchdev framework */
7719 case SWITCHDEV_ATTR_ID_PORT_PARENT_ID:
7720 /* In SRIOV each PF-pool (PF + child VFs) serves as a
7721 * switching domain, the PF's perm mac-addr can be used
7722 * as the unique parent-id
7724 attr->u.ppid.id_len = ETH_ALEN;
7725 ether_addr_copy(attr->u.ppid.id, bp->pf.mac_addr);
7733 static int bnxt_swdev_port_attr_get(struct net_device *dev,
7734 struct switchdev_attr *attr)
7736 return bnxt_port_attr_get(netdev_priv(dev), attr);
7739 static const struct switchdev_ops bnxt_switchdev_ops = {
7740 .switchdev_port_attr_get = bnxt_swdev_port_attr_get
7743 static const struct net_device_ops bnxt_netdev_ops = {
7744 .ndo_open = bnxt_open,
7745 .ndo_start_xmit = bnxt_start_xmit,
7746 .ndo_stop = bnxt_close,
7747 .ndo_get_stats64 = bnxt_get_stats64,
7748 .ndo_set_rx_mode = bnxt_set_rx_mode,
7749 .ndo_do_ioctl = bnxt_ioctl,
7750 .ndo_validate_addr = eth_validate_addr,
7751 .ndo_set_mac_address = bnxt_change_mac_addr,
7752 .ndo_change_mtu = bnxt_change_mtu,
7753 .ndo_fix_features = bnxt_fix_features,
7754 .ndo_set_features = bnxt_set_features,
7755 .ndo_tx_timeout = bnxt_tx_timeout,
7756 #ifdef CONFIG_BNXT_SRIOV
7757 .ndo_get_vf_config = bnxt_get_vf_config,
7758 .ndo_set_vf_mac = bnxt_set_vf_mac,
7759 .ndo_set_vf_vlan = bnxt_set_vf_vlan,
7760 .ndo_set_vf_rate = bnxt_set_vf_bw,
7761 .ndo_set_vf_link_state = bnxt_set_vf_link_state,
7762 .ndo_set_vf_spoofchk = bnxt_set_vf_spoofchk,
7764 #ifdef CONFIG_NET_POLL_CONTROLLER
7765 .ndo_poll_controller = bnxt_poll_controller,
7767 .ndo_setup_tc = bnxt_setup_tc,
7768 #ifdef CONFIG_RFS_ACCEL
7769 .ndo_rx_flow_steer = bnxt_rx_flow_steer,
7771 .ndo_udp_tunnel_add = bnxt_udp_tunnel_add,
7772 .ndo_udp_tunnel_del = bnxt_udp_tunnel_del,
7773 .ndo_bpf = bnxt_xdp,
7774 .ndo_bridge_getlink = bnxt_bridge_getlink,
7775 .ndo_bridge_setlink = bnxt_bridge_setlink,
7776 .ndo_get_phys_port_name = bnxt_get_phys_port_name
7779 static void bnxt_remove_one(struct pci_dev *pdev)
7781 struct net_device *dev = pci_get_drvdata(pdev);
7782 struct bnxt *bp = netdev_priv(dev);
7785 bnxt_sriov_disable(bp);
7786 bnxt_dl_unregister(bp);
7789 pci_disable_pcie_error_reporting(pdev);
7790 unregister_netdev(dev);
7791 bnxt_shutdown_tc(bp);
7792 bnxt_cancel_sp_work(bp);
7795 bnxt_clear_int_mode(bp);
7796 bnxt_hwrm_func_drv_unrgtr(bp);
7797 bnxt_free_hwrm_resources(bp);
7798 bnxt_free_hwrm_short_cmd_req(bp);
7799 bnxt_ethtool_free(bp);
7804 bpf_prog_put(bp->xdp_prog);
7805 bnxt_cleanup_pci(bp);
7809 static int bnxt_probe_phy(struct bnxt *bp)
7812 struct bnxt_link_info *link_info = &bp->link_info;
7814 rc = bnxt_hwrm_phy_qcaps(bp);
7816 netdev_err(bp->dev, "Probe phy can't get phy capabilities (rc: %x)\n",
7820 mutex_init(&bp->link_lock);
7822 rc = bnxt_update_link(bp, false);
7824 netdev_err(bp->dev, "Probe phy can't update link (rc: %x)\n",
7829 /* Older firmware does not have supported_auto_speeds, so assume
7830 * that all supported speeds can be autonegotiated.
7832 if (link_info->auto_link_speeds && !link_info->support_auto_speeds)
7833 link_info->support_auto_speeds = link_info->support_speeds;
7835 /*initialize the ethool setting copy with NVM settings */
7836 if (BNXT_AUTO_MODE(link_info->auto_mode)) {
7837 link_info->autoneg = BNXT_AUTONEG_SPEED;
7838 if (bp->hwrm_spec_code >= 0x10201) {
7839 if (link_info->auto_pause_setting &
7840 PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE)
7841 link_info->autoneg |= BNXT_AUTONEG_FLOW_CTRL;
7843 link_info->autoneg |= BNXT_AUTONEG_FLOW_CTRL;
7845 link_info->advertising = link_info->auto_link_speeds;
7847 link_info->req_link_speed = link_info->force_link_speed;
7848 link_info->req_duplex = link_info->duplex_setting;
7850 if (link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL)
7851 link_info->req_flow_ctrl =
7852 link_info->auto_pause_setting & BNXT_LINK_PAUSE_BOTH;
7854 link_info->req_flow_ctrl = link_info->force_pause_setting;
7858 static int bnxt_get_max_irq(struct pci_dev *pdev)
7862 if (!pdev->msix_cap)
7865 pci_read_config_word(pdev, pdev->msix_cap + PCI_MSIX_FLAGS, &ctrl);
7866 return (ctrl & PCI_MSIX_FLAGS_QSIZE) + 1;
7869 static void _bnxt_get_max_rings(struct bnxt *bp, int *max_rx, int *max_tx,
7872 int max_ring_grps = 0;
7874 #ifdef CONFIG_BNXT_SRIOV
7876 *max_tx = bp->vf.max_tx_rings;
7877 *max_rx = bp->vf.max_rx_rings;
7878 *max_cp = min_t(int, bp->vf.max_irqs, bp->vf.max_cp_rings);
7879 *max_cp = min_t(int, *max_cp, bp->vf.max_stat_ctxs);
7880 max_ring_grps = bp->vf.max_hw_ring_grps;
7884 *max_tx = bp->pf.max_tx_rings;
7885 *max_rx = bp->pf.max_rx_rings;
7886 *max_cp = min_t(int, bp->pf.max_irqs, bp->pf.max_cp_rings);
7887 *max_cp = min_t(int, *max_cp, bp->pf.max_stat_ctxs);
7888 max_ring_grps = bp->pf.max_hw_ring_grps;
7890 if (BNXT_CHIP_TYPE_NITRO_A0(bp) && BNXT_PF(bp)) {
7894 if (bp->flags & BNXT_FLAG_AGG_RINGS)
7896 *max_rx = min_t(int, *max_rx, max_ring_grps);
7899 int bnxt_get_max_rings(struct bnxt *bp, int *max_rx, int *max_tx, bool shared)
7903 _bnxt_get_max_rings(bp, &rx, &tx, &cp);
7904 if (!rx || !tx || !cp)
7909 return bnxt_trim_rings(bp, max_rx, max_tx, cp, shared);
7912 static int bnxt_get_dflt_rings(struct bnxt *bp, int *max_rx, int *max_tx,
7917 rc = bnxt_get_max_rings(bp, max_rx, max_tx, shared);
7918 if (rc && (bp->flags & BNXT_FLAG_AGG_RINGS)) {
7919 /* Not enough rings, try disabling agg rings. */
7920 bp->flags &= ~BNXT_FLAG_AGG_RINGS;
7921 rc = bnxt_get_max_rings(bp, max_rx, max_tx, shared);
7924 bp->flags |= BNXT_FLAG_NO_AGG_RINGS;
7925 bp->dev->hw_features &= ~NETIF_F_LRO;
7926 bp->dev->features &= ~NETIF_F_LRO;
7927 bnxt_set_ring_params(bp);
7930 if (bp->flags & BNXT_FLAG_ROCE_CAP) {
7931 int max_cp, max_stat, max_irq;
7933 /* Reserve minimum resources for RoCE */
7934 max_cp = bnxt_get_max_func_cp_rings(bp);
7935 max_stat = bnxt_get_max_func_stat_ctxs(bp);
7936 max_irq = bnxt_get_max_func_irqs(bp);
7937 if (max_cp <= BNXT_MIN_ROCE_CP_RINGS ||
7938 max_irq <= BNXT_MIN_ROCE_CP_RINGS ||
7939 max_stat <= BNXT_MIN_ROCE_STAT_CTXS)
7942 max_cp -= BNXT_MIN_ROCE_CP_RINGS;
7943 max_irq -= BNXT_MIN_ROCE_CP_RINGS;
7944 max_stat -= BNXT_MIN_ROCE_STAT_CTXS;
7945 max_cp = min_t(int, max_cp, max_irq);
7946 max_cp = min_t(int, max_cp, max_stat);
7947 rc = bnxt_trim_rings(bp, max_rx, max_tx, max_cp, shared);
7954 static int bnxt_set_dflt_rings(struct bnxt *bp, bool sh)
7956 int dflt_rings, max_rx_rings, max_tx_rings, rc;
7959 bp->flags |= BNXT_FLAG_SHARED_RINGS;
7960 dflt_rings = netif_get_num_default_rss_queues();
7961 /* Reduce default rings to reduce memory usage on multi-port cards */
7962 if (bp->port_count > 1)
7963 dflt_rings = min_t(int, dflt_rings, 4);
7964 rc = bnxt_get_dflt_rings(bp, &max_rx_rings, &max_tx_rings, sh);
7967 bp->rx_nr_rings = min_t(int, dflt_rings, max_rx_rings);
7968 bp->tx_nr_rings_per_tc = min_t(int, dflt_rings, max_tx_rings);
7970 rc = bnxt_hwrm_reserve_tx_rings(bp, &bp->tx_nr_rings_per_tc);
7972 netdev_warn(bp->dev, "Unable to reserve tx rings\n");
7974 bp->tx_nr_rings = bp->tx_nr_rings_per_tc;
7975 bp->cp_nr_rings = sh ? max_t(int, bp->tx_nr_rings, bp->rx_nr_rings) :
7976 bp->tx_nr_rings + bp->rx_nr_rings;
7977 bp->num_stat_ctxs = bp->cp_nr_rings;
7978 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) {
7985 void bnxt_restore_pf_fw_resources(struct bnxt *bp)
7988 bnxt_hwrm_func_qcaps(bp);
7989 bnxt_subtract_ulp_resources(bp, BNXT_ROCE_ULP);
7992 static int bnxt_init_mac_addr(struct bnxt *bp)
7997 memcpy(bp->dev->dev_addr, bp->pf.mac_addr, ETH_ALEN);
7999 #ifdef CONFIG_BNXT_SRIOV
8000 struct bnxt_vf_info *vf = &bp->vf;
8002 if (is_valid_ether_addr(vf->mac_addr)) {
8003 /* overwrite netdev dev_adr with admin VF MAC */
8004 memcpy(bp->dev->dev_addr, vf->mac_addr, ETH_ALEN);
8006 eth_hw_addr_random(bp->dev);
8007 rc = bnxt_approve_mac(bp, bp->dev->dev_addr);
8014 static void bnxt_parse_log_pcie_link(struct bnxt *bp)
8016 enum pcie_link_width width = PCIE_LNK_WIDTH_UNKNOWN;
8017 enum pci_bus_speed speed = PCI_SPEED_UNKNOWN;
8019 if (pcie_get_minimum_link(pci_physfn(bp->pdev), &speed, &width) ||
8020 speed == PCI_SPEED_UNKNOWN || width == PCIE_LNK_WIDTH_UNKNOWN)
8021 netdev_info(bp->dev, "Failed to determine PCIe Link Info\n");
8023 netdev_info(bp->dev, "PCIe: Speed %s Width x%d\n",
8024 speed == PCIE_SPEED_2_5GT ? "2.5GT/s" :
8025 speed == PCIE_SPEED_5_0GT ? "5.0GT/s" :
8026 speed == PCIE_SPEED_8_0GT ? "8.0GT/s" :
8030 static int bnxt_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
8032 static int version_printed;
8033 struct net_device *dev;
8037 if (pci_is_bridge(pdev))
8040 if (version_printed++ == 0)
8041 pr_info("%s", version);
8043 max_irqs = bnxt_get_max_irq(pdev);
8044 dev = alloc_etherdev_mq(sizeof(*bp), max_irqs);
8048 bp = netdev_priv(dev);
8050 if (bnxt_vf_pciid(ent->driver_data))
8051 bp->flags |= BNXT_FLAG_VF;
8054 bp->flags |= BNXT_FLAG_MSIX_CAP;
8056 rc = bnxt_init_board(pdev, dev);
8060 dev->netdev_ops = &bnxt_netdev_ops;
8061 dev->watchdog_timeo = BNXT_TX_TIMEOUT;
8062 dev->ethtool_ops = &bnxt_ethtool_ops;
8063 SWITCHDEV_SET_OPS(dev, &bnxt_switchdev_ops);
8064 pci_set_drvdata(pdev, dev);
8066 rc = bnxt_alloc_hwrm_resources(bp);
8068 goto init_err_pci_clean;
8070 mutex_init(&bp->hwrm_cmd_lock);
8071 rc = bnxt_hwrm_ver_get(bp);
8073 goto init_err_pci_clean;
8075 if (bp->flags & BNXT_FLAG_SHORT_CMD) {
8076 rc = bnxt_alloc_hwrm_short_cmd_req(bp);
8078 goto init_err_pci_clean;
8081 rc = bnxt_hwrm_func_reset(bp);
8083 goto init_err_pci_clean;
8085 bnxt_hwrm_fw_set_time(bp);
8087 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG |
8088 NETIF_F_TSO | NETIF_F_TSO6 |
8089 NETIF_F_GSO_UDP_TUNNEL | NETIF_F_GSO_GRE |
8090 NETIF_F_GSO_IPXIP4 |
8091 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_GSO_GRE_CSUM |
8092 NETIF_F_GSO_PARTIAL | NETIF_F_RXHASH |
8093 NETIF_F_RXCSUM | NETIF_F_GRO;
8095 if (!BNXT_CHIP_TYPE_NITRO_A0(bp))
8096 dev->hw_features |= NETIF_F_LRO;
8098 dev->hw_enc_features =
8099 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG |
8100 NETIF_F_TSO | NETIF_F_TSO6 |
8101 NETIF_F_GSO_UDP_TUNNEL | NETIF_F_GSO_GRE |
8102 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_GSO_GRE_CSUM |
8103 NETIF_F_GSO_IPXIP4 | NETIF_F_GSO_PARTIAL;
8104 dev->gso_partial_features = NETIF_F_GSO_UDP_TUNNEL_CSUM |
8105 NETIF_F_GSO_GRE_CSUM;
8106 dev->vlan_features = dev->hw_features | NETIF_F_HIGHDMA;
8107 dev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX |
8108 NETIF_F_HW_VLAN_STAG_RX | NETIF_F_HW_VLAN_STAG_TX;
8109 dev->features |= dev->hw_features | NETIF_F_HIGHDMA;
8110 dev->priv_flags |= IFF_UNICAST_FLT;
8112 #ifdef CONFIG_BNXT_SRIOV
8113 init_waitqueue_head(&bp->sriov_cfg_wait);
8114 mutex_init(&bp->sriov_lock);
8116 bp->gro_func = bnxt_gro_func_5730x;
8117 if (BNXT_CHIP_P4_PLUS(bp))
8118 bp->gro_func = bnxt_gro_func_5731x;
8120 bp->flags |= BNXT_FLAG_DOUBLE_DB;
8122 rc = bnxt_hwrm_func_drv_rgtr(bp);
8124 goto init_err_pci_clean;
8126 rc = bnxt_hwrm_func_rgtr_async_events(bp, NULL, 0);
8128 goto init_err_pci_clean;
8130 bp->ulp_probe = bnxt_ulp_probe;
8132 /* Get the MAX capabilities for this function */
8133 rc = bnxt_hwrm_func_qcaps(bp);
8135 netdev_err(bp->dev, "hwrm query capability failure rc: %x\n",
8138 goto init_err_pci_clean;
8140 rc = bnxt_init_mac_addr(bp);
8142 dev_err(&pdev->dev, "Unable to initialize mac address.\n");
8143 rc = -EADDRNOTAVAIL;
8144 goto init_err_pci_clean;
8146 rc = bnxt_hwrm_queue_qportcfg(bp);
8148 netdev_err(bp->dev, "hwrm query qportcfg failure rc: %x\n",
8151 goto init_err_pci_clean;
8154 bnxt_hwrm_func_qcfg(bp);
8155 bnxt_hwrm_port_led_qcaps(bp);
8156 bnxt_ethtool_init(bp);
8159 /* MTU range: 60 - FW defined max */
8160 dev->min_mtu = ETH_ZLEN;
8161 dev->max_mtu = bp->max_mtu;
8163 rc = bnxt_probe_phy(bp);
8165 goto init_err_pci_clean;
8167 bnxt_set_rx_skb_mode(bp, false);
8168 bnxt_set_tpa_flags(bp);
8169 bnxt_set_ring_params(bp);
8170 bnxt_set_max_func_irqs(bp, max_irqs);
8171 rc = bnxt_set_dflt_rings(bp, true);
8173 netdev_err(bp->dev, "Not enough rings available.\n");
8175 goto init_err_pci_clean;
8178 /* Default RSS hash cfg. */
8179 bp->rss_hash_cfg = VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4 |
8180 VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4 |
8181 VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6 |
8182 VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6;
8183 if (BNXT_CHIP_P4_PLUS(bp) && bp->hwrm_spec_code >= 0x10501) {
8184 bp->flags |= BNXT_FLAG_UDP_RSS_CAP;
8185 bp->rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4 |
8186 VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6;
8189 bnxt_hwrm_vnic_qcaps(bp);
8190 if (bnxt_rfs_supported(bp)) {
8191 dev->hw_features |= NETIF_F_NTUPLE;
8192 if (bnxt_rfs_capable(bp)) {
8193 bp->flags |= BNXT_FLAG_RFS;
8194 dev->features |= NETIF_F_NTUPLE;
8198 if (dev->hw_features & NETIF_F_HW_VLAN_CTAG_RX)
8199 bp->flags |= BNXT_FLAG_STRIP_VLAN;
8201 rc = bnxt_init_int_mode(bp);
8203 goto init_err_pci_clean;
8205 bnxt_get_wol_settings(bp);
8206 if (bp->flags & BNXT_FLAG_WOL_CAP)
8207 device_set_wakeup_enable(&pdev->dev, bp->wol);
8209 device_set_wakeup_capable(&pdev->dev, false);
8214 create_singlethread_workqueue("bnxt_pf_wq");
8216 dev_err(&pdev->dev, "Unable to create workqueue.\n");
8217 goto init_err_pci_clean;
8223 rc = register_netdev(dev);
8225 goto init_err_cleanup_tc;
8228 bnxt_dl_register(bp);
8230 netdev_info(dev, "%s found at mem %lx, node addr %pM\n",
8231 board_info[ent->driver_data].name,
8232 (long)pci_resource_start(pdev, 0), dev->dev_addr);
8234 bnxt_parse_log_pcie_link(bp);
8238 init_err_cleanup_tc:
8239 bnxt_shutdown_tc(bp);
8240 bnxt_clear_int_mode(bp);
8243 bnxt_cleanup_pci(bp);
8250 static void bnxt_shutdown(struct pci_dev *pdev)
8252 struct net_device *dev = pci_get_drvdata(pdev);
8259 bp = netdev_priv(dev);
8263 if (netif_running(dev))
8266 bnxt_ulp_shutdown(bp);
8268 if (system_state == SYSTEM_POWER_OFF) {
8269 bnxt_clear_int_mode(bp);
8270 pci_wake_from_d3(pdev, bp->wol);
8271 pci_set_power_state(pdev, PCI_D3hot);
8278 #ifdef CONFIG_PM_SLEEP
8279 static int bnxt_suspend(struct device *device)
8281 struct pci_dev *pdev = to_pci_dev(device);
8282 struct net_device *dev = pci_get_drvdata(pdev);
8283 struct bnxt *bp = netdev_priv(dev);
8287 if (netif_running(dev)) {
8288 netif_device_detach(dev);
8289 rc = bnxt_close(dev);
8291 bnxt_hwrm_func_drv_unrgtr(bp);
8296 static int bnxt_resume(struct device *device)
8298 struct pci_dev *pdev = to_pci_dev(device);
8299 struct net_device *dev = pci_get_drvdata(pdev);
8300 struct bnxt *bp = netdev_priv(dev);
8304 if (bnxt_hwrm_ver_get(bp) || bnxt_hwrm_func_drv_rgtr(bp)) {
8308 rc = bnxt_hwrm_func_reset(bp);
8313 bnxt_get_wol_settings(bp);
8314 if (netif_running(dev)) {
8315 rc = bnxt_open(dev);
8317 netif_device_attach(dev);
8325 static SIMPLE_DEV_PM_OPS(bnxt_pm_ops, bnxt_suspend, bnxt_resume);
8326 #define BNXT_PM_OPS (&bnxt_pm_ops)
8330 #define BNXT_PM_OPS NULL
8332 #endif /* CONFIG_PM_SLEEP */
8335 * bnxt_io_error_detected - called when PCI error is detected
8336 * @pdev: Pointer to PCI device
8337 * @state: The current pci connection state
8339 * This function is called after a PCI bus error affecting
8340 * this device has been detected.
8342 static pci_ers_result_t bnxt_io_error_detected(struct pci_dev *pdev,
8343 pci_channel_state_t state)
8345 struct net_device *netdev = pci_get_drvdata(pdev);
8346 struct bnxt *bp = netdev_priv(netdev);
8348 netdev_info(netdev, "PCI I/O error detected\n");
8351 netif_device_detach(netdev);
8355 if (state == pci_channel_io_perm_failure) {
8357 return PCI_ERS_RESULT_DISCONNECT;
8360 if (netif_running(netdev))
8363 pci_disable_device(pdev);
8366 /* Request a slot slot reset. */
8367 return PCI_ERS_RESULT_NEED_RESET;
8371 * bnxt_io_slot_reset - called after the pci bus has been reset.
8372 * @pdev: Pointer to PCI device
8374 * Restart the card from scratch, as if from a cold-boot.
8375 * At this point, the card has exprienced a hard reset,
8376 * followed by fixups by BIOS, and has its config space
8377 * set up identically to what it was at cold boot.
8379 static pci_ers_result_t bnxt_io_slot_reset(struct pci_dev *pdev)
8381 struct net_device *netdev = pci_get_drvdata(pdev);
8382 struct bnxt *bp = netdev_priv(netdev);
8384 pci_ers_result_t result = PCI_ERS_RESULT_DISCONNECT;
8386 netdev_info(bp->dev, "PCI Slot Reset\n");
8390 if (pci_enable_device(pdev)) {
8392 "Cannot re-enable PCI device after reset.\n");
8394 pci_set_master(pdev);
8396 err = bnxt_hwrm_func_reset(bp);
8397 if (!err && netif_running(netdev))
8398 err = bnxt_open(netdev);
8401 result = PCI_ERS_RESULT_RECOVERED;
8406 if (result != PCI_ERS_RESULT_RECOVERED && netif_running(netdev))
8411 err = pci_cleanup_aer_uncorrect_error_status(pdev);
8414 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n",
8415 err); /* non-fatal, continue */
8418 return PCI_ERS_RESULT_RECOVERED;
8422 * bnxt_io_resume - called when traffic can start flowing again.
8423 * @pdev: Pointer to PCI device
8425 * This callback is called when the error recovery driver tells
8426 * us that its OK to resume normal operation.
8428 static void bnxt_io_resume(struct pci_dev *pdev)
8430 struct net_device *netdev = pci_get_drvdata(pdev);
8434 netif_device_attach(netdev);
8439 static const struct pci_error_handlers bnxt_err_handler = {
8440 .error_detected = bnxt_io_error_detected,
8441 .slot_reset = bnxt_io_slot_reset,
8442 .resume = bnxt_io_resume
8445 static struct pci_driver bnxt_pci_driver = {
8446 .name = DRV_MODULE_NAME,
8447 .id_table = bnxt_pci_tbl,
8448 .probe = bnxt_init_one,
8449 .remove = bnxt_remove_one,
8450 .shutdown = bnxt_shutdown,
8451 .driver.pm = BNXT_PM_OPS,
8452 .err_handler = &bnxt_err_handler,
8453 #if defined(CONFIG_BNXT_SRIOV)
8454 .sriov_configure = bnxt_sriov_configure,
8458 static int __init bnxt_init(void)
8460 return pci_register_driver(&bnxt_pci_driver);
8463 static void __exit bnxt_exit(void)
8465 pci_unregister_driver(&bnxt_pci_driver);
8467 destroy_workqueue(bnxt_pf_wq);
8470 module_init(bnxt_init);
8471 module_exit(bnxt_exit);