drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c

   1 /* bnx2x_main.c: Broadcom Everest network driver.
   2  *
   3  * Copyright (c) 2007-2013 Broadcom Corporation
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation.
   8  *
   9  * Maintained by: Eilon Greenstein <eilong@broadcom.com>
  10  * Written by: Eliezer Tamir
  11  * Based on code from Michael Chan's bnx2 driver
  12  * UDP CSUM errata workaround by Arik Gendelman
  13  * Slowpath and fastpath rework by Vladislav Zolotarov
  14  * Statistics and Link management by Yitchak Gertner
  15  *
  16  */
  17
  18 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  19
  20 #include <linux/module.h>
  21 #include <linux/moduleparam.h>
  22 #include <linux/kernel.h>
  23 #include <linux/device.h>  /* for dev_info() */
  24 #include <linux/timer.h>
  25 #include <linux/errno.h>
  26 #include <linux/ioport.h>
  27 #include <linux/slab.h>
  28 #include <linux/interrupt.h>
  29 #include <linux/pci.h>
  30 #include <linux/init.h>
  31 #include <linux/netdevice.h>
  32 #include <linux/etherdevice.h>
  33 #include <linux/skbuff.h>
  34 #include <linux/dma-mapping.h>
  35 #include <linux/bitops.h>
  36 #include <linux/irq.h>
  37 #include <linux/delay.h>
  38 #include <asm/byteorder.h>
  39 #include <linux/time.h>
  40 #include <linux/ethtool.h>
  41 #include <linux/mii.h>
  42 #include <linux/if_vlan.h>
  43 #include <net/ip.h>
  44 #include <net/ipv6.h>
  45 #include <net/tcp.h>
  46 #include <net/checksum.h>
  47 #include <net/ip6_checksum.h>
  48 #include <linux/workqueue.h>
  49 #include <linux/crc32.h>
  50 #include <linux/crc32c.h>
  51 #include <linux/prefetch.h>
  52 #include <linux/zlib.h>
  53 #include <linux/io.h>
  54 #include <linux/semaphore.h>
  55 #include <linux/stringify.h>
  56 #include <linux/vmalloc.h>
  57
  58 #include "bnx2x.h"
  59 #include "bnx2x_init.h"
  60 #include "bnx2x_init_ops.h"
  61 #include "bnx2x_cmn.h"
  62 #include "bnx2x_vfpf.h"
  63 #include "bnx2x_dcb.h"
  64 #include "bnx2x_sp.h"
  65
  66 #include <linux/firmware.h>
  67 #include "bnx2x_fw_file_hdr.h"
  68 /* FW files */
  69 #define FW_FILE_VERSION                                 \
  70         __stringify(BCM_5710_FW_MAJOR_VERSION) "."      \
  71         __stringify(BCM_5710_FW_MINOR_VERSION) "."      \
  72         __stringify(BCM_5710_FW_REVISION_VERSION) "."   \
  73         __stringify(BCM_5710_FW_ENGINEERING_VERSION)
  74 #define FW_FILE_NAME_E1         "bnx2x/bnx2x-e1-" FW_FILE_VERSION ".fw"
  75 #define FW_FILE_NAME_E1H        "bnx2x/bnx2x-e1h-" FW_FILE_VERSION ".fw"
  76 #define FW_FILE_NAME_E2         "bnx2x/bnx2x-e2-" FW_FILE_VERSION ".fw"
  77
  78 /* Time in jiffies before concluding the transmitter is hung */
  79 #define TX_TIMEOUT              (5*HZ)
  80
  81 static char version[] =
  82         "Broadcom NetXtreme II 5771x/578xx 10/20-Gigabit Ethernet Driver "
  83         DRV_MODULE_NAME " " DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
  84
  85 MODULE_AUTHOR("Eliezer Tamir");
  86 MODULE_DESCRIPTION("Broadcom NetXtreme II "
  87                    "BCM57710/57711/57711E/"
  88                    "57712/57712_MF/57800/57800_MF/57810/57810_MF/"
  89                    "57840/57840_MF Driver");
  90 MODULE_LICENSE("GPL");
  91 MODULE_VERSION(DRV_MODULE_VERSION);
  92 MODULE_FIRMWARE(FW_FILE_NAME_E1);
  93 MODULE_FIRMWARE(FW_FILE_NAME_E1H);
  94 MODULE_FIRMWARE(FW_FILE_NAME_E2);
  95
  96
  97 int num_queues;
  98 module_param(num_queues, int, 0);
  99 MODULE_PARM_DESC(num_queues,
 100                  " Set number of queues (default is as a number of CPUs)");
 101
 102 static int disable_tpa;
 103 module_param(disable_tpa, int, 0);
 104 MODULE_PARM_DESC(disable_tpa, " Disable the TPA (LRO) feature");
 105
 106 #define INT_MODE_INTx                   1
 107 #define INT_MODE_MSI                    2
 108 int int_mode;
 109 module_param(int_mode, int, 0);
 110 MODULE_PARM_DESC(int_mode, " Force interrupt mode other than MSI-X "
 111                                 "(1 INT#x; 2 MSI)");
 112
 113 static int dropless_fc;
 114 module_param(dropless_fc, int, 0);
 115 MODULE_PARM_DESC(dropless_fc, " Pause on exhausted host ring");
 116
 117 static int mrrs = -1;
 118 module_param(mrrs, int, 0);
 119 MODULE_PARM_DESC(mrrs, " Force Max Read Req Size (0..3) (for debug)");
 120
 121 static int debug;
 122 module_param(debug, int, 0);
 123 MODULE_PARM_DESC(debug, " Default debug msglevel");
 124
 125
 126
 127 struct workqueue_struct *bnx2x_wq;
 128
 129 struct bnx2x_mac_vals {
 130         u32 xmac_addr;
 131         u32 xmac_val;
 132         u32 emac_addr;
 133         u32 emac_val;
 134         u32 umac_addr;
 135         u32 umac_val;
 136         u32 bmac_addr;
 137         u32 bmac_val[2];
 138 };
 139
 140 enum bnx2x_board_type {
 141         BCM57710 = 0,
 142         BCM57711,
 143         BCM57711E,
 144         BCM57712,
 145         BCM57712_MF,
 146         BCM57712_VF,
 147         BCM57800,
 148         BCM57800_MF,
 149         BCM57800_VF,
 150         BCM57810,
 151         BCM57810_MF,
 152         BCM57810_VF,
 153         BCM57840_4_10,
 154         BCM57840_2_20,
 155         BCM57840_MF,
 156         BCM57840_VF,
 157         BCM57811,
 158         BCM57811_MF,
 159         BCM57840_O,
 160         BCM57840_MFO,
 161         BCM57811_VF
 162 };
 163
 164 /* indexed by board_type, above */
 165 static struct {
 166         char *name;
 167 } board_info[] = {
 168         [BCM57710]      = { "Broadcom NetXtreme II BCM57710 10 Gigabit PCIe [Everest]" },
 169         [BCM57711]      = { "Broadcom NetXtreme II BCM57711 10 Gigabit PCIe" },
 170         [BCM57711E]     = { "Broadcom NetXtreme II BCM57711E 10 Gigabit PCIe" },
 171         [BCM57712]      = { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet" },
 172         [BCM57712_MF]   = { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet Multi Function" },
 173         [BCM57712_VF]   = { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet Virtual Function" },
 174         [BCM57800]      = { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet" },
 175         [BCM57800_MF]   = { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet Multi Function" },
 176         [BCM57800_VF]   = { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet Virtual Function" },
 177         [BCM57810]      = { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet" },
 178         [BCM57810_MF]   = { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet Multi Function" },
 179         [BCM57810_VF]   = { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet Virtual Function" },
 180         [BCM57840_4_10] = { "Broadcom NetXtreme II BCM57840 10 Gigabit Ethernet" },
 181         [BCM57840_2_20] = { "Broadcom NetXtreme II BCM57840 20 Gigabit Ethernet" },
 182         [BCM57840_MF]   = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Multi Function" },
 183         [BCM57840_VF]   = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Virtual Function" },
 184         [BCM57811]      = { "Broadcom NetXtreme II BCM57811 10 Gigabit Ethernet" },
 185         [BCM57811_MF]   = { "Broadcom NetXtreme II BCM57811 10 Gigabit Ethernet Multi Function" },
 186         [BCM57840_O]    = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet" },
 187         [BCM57840_MFO]  = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Multi Function" },
 188         [BCM57811_VF]   = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Virtual Function" }
 189 };
 190
 191 #ifndef PCI_DEVICE_ID_NX2_57710
 192 #define PCI_DEVICE_ID_NX2_57710         CHIP_NUM_57710
 193 #endif
 194 #ifndef PCI_DEVICE_ID_NX2_57711
 195 #define PCI_DEVICE_ID_NX2_57711         CHIP_NUM_57711
 196 #endif
 197 #ifndef PCI_DEVICE_ID_NX2_57711E
 198 #define PCI_DEVICE_ID_NX2_57711E        CHIP_NUM_57711E
 199 #endif
 200 #ifndef PCI_DEVICE_ID_NX2_57712
 201 #define PCI_DEVICE_ID_NX2_57712         CHIP_NUM_57712
 202 #endif
 203 #ifndef PCI_DEVICE_ID_NX2_57712_MF
 204 #define PCI_DEVICE_ID_NX2_57712_MF      CHIP_NUM_57712_MF
 205 #endif
 206 #ifndef PCI_DEVICE_ID_NX2_57712_VF
 207 #define PCI_DEVICE_ID_NX2_57712_VF      CHIP_NUM_57712_VF
 208 #endif
 209 #ifndef PCI_DEVICE_ID_NX2_57800
 210 #define PCI_DEVICE_ID_NX2_57800         CHIP_NUM_57800
 211 #endif
 212 #ifndef PCI_DEVICE_ID_NX2_57800_MF
 213 #define PCI_DEVICE_ID_NX2_57800_MF      CHIP_NUM_57800_MF
 214 #endif
 215 #ifndef PCI_DEVICE_ID_NX2_57800_VF
 216 #define PCI_DEVICE_ID_NX2_57800_VF      CHIP_NUM_57800_VF
 217 #endif
 218 #ifndef PCI_DEVICE_ID_NX2_57810
 219 #define PCI_DEVICE_ID_NX2_57810         CHIP_NUM_57810
 220 #endif
 221 #ifndef PCI_DEVICE_ID_NX2_57810_MF
 222 #define PCI_DEVICE_ID_NX2_57810_MF      CHIP_NUM_57810_MF
 223 #endif
 224 #ifndef PCI_DEVICE_ID_NX2_57840_O
 225 #define PCI_DEVICE_ID_NX2_57840_O       CHIP_NUM_57840_OBSOLETE
 226 #endif
 227 #ifndef PCI_DEVICE_ID_NX2_57810_VF
 228 #define PCI_DEVICE_ID_NX2_57810_VF      CHIP_NUM_57810_VF
 229 #endif
 230 #ifndef PCI_DEVICE_ID_NX2_57840_4_10
 231 #define PCI_DEVICE_ID_NX2_57840_4_10    CHIP_NUM_57840_4_10
 232 #endif
 233 #ifndef PCI_DEVICE_ID_NX2_57840_2_20
 234 #define PCI_DEVICE_ID_NX2_57840_2_20    CHIP_NUM_57840_2_20
 235 #endif
 236 #ifndef PCI_DEVICE_ID_NX2_57840_MFO
 237 #define PCI_DEVICE_ID_NX2_57840_MFO     CHIP_NUM_57840_MF_OBSOLETE
 238 #endif
 239 #ifndef PCI_DEVICE_ID_NX2_57840_MF
 240 #define PCI_DEVICE_ID_NX2_57840_MF      CHIP_NUM_57840_MF
 241 #endif
 242 #ifndef PCI_DEVICE_ID_NX2_57840_VF
 243 #define PCI_DEVICE_ID_NX2_57840_VF      CHIP_NUM_57840_VF
 244 #endif
 245 #ifndef PCI_DEVICE_ID_NX2_57811
 246 #define PCI_DEVICE_ID_NX2_57811         CHIP_NUM_57811
 247 #endif
 248 #ifndef PCI_DEVICE_ID_NX2_57811_MF
 249 #define PCI_DEVICE_ID_NX2_57811_MF      CHIP_NUM_57811_MF
 250 #endif
 251 #ifndef PCI_DEVICE_ID_NX2_57811_VF
 252 #define PCI_DEVICE_ID_NX2_57811_VF      CHIP_NUM_57811_VF
 253 #endif
 254
 255 static DEFINE_PCI_DEVICE_TABLE(bnx2x_pci_tbl) = {
 256         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57710), BCM57710 },
 257         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711), BCM57711 },
 258         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711E), BCM57711E },
 259         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712), BCM57712 },
 260         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712_MF), BCM57712_MF },
 261         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712_VF), BCM57712_VF },
 262         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800), BCM57800 },
 263         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800_MF), BCM57800_MF },
 264         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800_VF), BCM57800_VF },
 265         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810), BCM57810 },
 266         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810_MF), BCM57810_MF },
 267         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_O), BCM57840_O },
 268         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_4_10), BCM57840_4_10 },
 269         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_2_20), BCM57840_2_20 },
 270         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810_VF), BCM57810_VF },
 271         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_MFO), BCM57840_MFO },
 272         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_MF), BCM57840_MF },
 273         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_VF), BCM57840_VF },
 274         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811), BCM57811 },
 275         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811_MF), BCM57811_MF },
 276         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811_VF), BCM57811_VF },
 277         { 0 }
 278 };
 279
 280 MODULE_DEVICE_TABLE(pci, bnx2x_pci_tbl);
 281
 282 /* Global resources for unloading a previously loaded device */
 283 #define BNX2X_PREV_WAIT_NEEDED 1
 284 static DEFINE_SEMAPHORE(bnx2x_prev_sem);
 285 static LIST_HEAD(bnx2x_prev_list);
 286 /****************************************************************************
 287 * General service functions
 288 ****************************************************************************/
 289
 290 static void __storm_memset_dma_mapping(struct bnx2x *bp,
 291                                        u32 addr, dma_addr_t mapping)
 292 {
 293         REG_WR(bp,  addr, U64_LO(mapping));
 294         REG_WR(bp,  addr + 4, U64_HI(mapping));
 295 }
 296
 297 static void storm_memset_spq_addr(struct bnx2x *bp,
 298                                   dma_addr_t mapping, u16 abs_fid)
 299 {
 300         u32 addr = XSEM_REG_FAST_MEMORY +
 301                         XSTORM_SPQ_PAGE_BASE_OFFSET(abs_fid);
 302
 303         __storm_memset_dma_mapping(bp, addr, mapping);
 304 }
 305
 306 static void storm_memset_vf_to_pf(struct bnx2x *bp, u16 abs_fid,
 307                                   u16 pf_id)
 308 {
 309         REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_VF_TO_PF_OFFSET(abs_fid),
 310                 pf_id);
 311         REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_VF_TO_PF_OFFSET(abs_fid),
 312                 pf_id);
 313         REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_VF_TO_PF_OFFSET(abs_fid),
 314                 pf_id);
 315         REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_VF_TO_PF_OFFSET(abs_fid),
 316                 pf_id);
 317 }
 318
 319 static void storm_memset_func_en(struct bnx2x *bp, u16 abs_fid,
 320                                  u8 enable)
 321 {
 322         REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(abs_fid),
 323                 enable);
 324         REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(abs_fid),
 325                 enable);
 326         REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(abs_fid),
 327                 enable);
 328         REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(abs_fid),
 329                 enable);
 330 }
 331
 332 static void storm_memset_eq_data(struct bnx2x *bp,
 333                                  struct event_ring_data *eq_data,
 334                                 u16 pfid)
 335 {
 336         size_t size = sizeof(struct event_ring_data);
 337
 338         u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_DATA_OFFSET(pfid);
 339
 340         __storm_memset_struct(bp, addr, size, (u32 *)eq_data);
 341 }
 342
 343 static void storm_memset_eq_prod(struct bnx2x *bp, u16 eq_prod,
 344                                  u16 pfid)
 345 {
 346         u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_PROD_OFFSET(pfid);
 347         REG_WR16(bp, addr, eq_prod);
 348 }
 349
 350 /* used only at init
 351  * locking is done by mcp
 352  */
 353 static void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val)
 354 {
 355         pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
 356         pci_write_config_dword(bp->pdev, PCICFG_GRC_DATA, val);
 357         pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
 358                                PCICFG_VENDOR_ID_OFFSET);
 359 }
 360
 361 static u32 bnx2x_reg_rd_ind(struct bnx2x *bp, u32 addr)
 362 {
 363         u32 val;
 364
 365         pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
 366         pci_read_config_dword(bp->pdev, PCICFG_GRC_DATA, &val);
 367         pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
 368                                PCICFG_VENDOR_ID_OFFSET);
 369
 370         return val;
 371 }
 372
 373 #define DMAE_DP_SRC_GRC         "grc src_addr [%08x]"
 374 #define DMAE_DP_SRC_PCI         "pci src_addr [%x:%08x]"
 375 #define DMAE_DP_DST_GRC         "grc dst_addr [%08x]"
 376 #define DMAE_DP_DST_PCI         "pci dst_addr [%x:%08x]"
 377 #define DMAE_DP_DST_NONE        "dst_addr [none]"
 378
 379 void bnx2x_dp_dmae(struct bnx2x *bp, struct dmae_command *dmae, int msglvl)
 380 {
 381         u32 src_type = dmae->opcode & DMAE_COMMAND_SRC;
 382
 383         switch (dmae->opcode & DMAE_COMMAND_DST) {
 384         case DMAE_CMD_DST_PCI:
 385                 if (src_type == DMAE_CMD_SRC_PCI)
 386                         DP(msglvl, "DMAE: opcode 0x%08x\n"
 387                            "src [%x:%08x], len [%d*4], dst [%x:%08x]\n"
 388                            "comp_addr [%x:%08x], comp_val 0x%08x\n",
 389                            dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
 390                            dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo,
 391                            dmae->comp_addr_hi, dmae->comp_addr_lo,
 392                            dmae->comp_val);
 393                 else
 394                         DP(msglvl, "DMAE: opcode 0x%08x\n"
 395                            "src [%08x], len [%d*4], dst [%x:%08x]\n"
 396                            "comp_addr [%x:%08x], comp_val 0x%08x\n",
 397                            dmae->opcode, dmae->src_addr_lo >> 2,
 398                            dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo,
 399                            dmae->comp_addr_hi, dmae->comp_addr_lo,
 400                            dmae->comp_val);
 401                 break;
 402         case DMAE_CMD_DST_GRC:
 403                 if (src_type == DMAE_CMD_SRC_PCI)
 404                         DP(msglvl, "DMAE: opcode 0x%08x\n"
 405                            "src [%x:%08x], len [%d*4], dst_addr [%08x]\n"
 406                            "comp_addr [%x:%08x], comp_val 0x%08x\n",
 407                            dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
 408                            dmae->len, dmae->dst_addr_lo >> 2,
 409                            dmae->comp_addr_hi, dmae->comp_addr_lo,
 410                            dmae->comp_val);
 411                 else
 412                         DP(msglvl, "DMAE: opcode 0x%08x\n"
 413                            "src [%08x], len [%d*4], dst [%08x]\n"
 414                            "comp_addr [%x:%08x], comp_val 0x%08x\n",
 415                            dmae->opcode, dmae->src_addr_lo >> 2,
 416                            dmae->len, dmae->dst_addr_lo >> 2,
 417                            dmae->comp_addr_hi, dmae->comp_addr_lo,
 418                            dmae->comp_val);
 419                 break;
 420         default:
 421                 if (src_type == DMAE_CMD_SRC_PCI)
 422                         DP(msglvl, "DMAE: opcode 0x%08x\n"
 423                            "src_addr [%x:%08x]  len [%d * 4]  dst_addr [none]\n"
 424                            "comp_addr [%x:%08x]  comp_val 0x%08x\n",
 425                            dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
 426                            dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo,
 427                            dmae->comp_val);
 428                 else
 429                         DP(msglvl, "DMAE: opcode 0x%08x\n"
 430                            "src_addr [%08x]  len [%d * 4]  dst_addr [none]\n"
 431                            "comp_addr [%x:%08x]  comp_val 0x%08x\n",
 432                            dmae->opcode, dmae->src_addr_lo >> 2,
 433                            dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo,
 434                            dmae->comp_val);
 435                 break;
 436         }
 437 }
 438
 439 /* copy command into DMAE command memory and set DMAE command go */
 440 void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx)
 441 {
 442         u32 cmd_offset;
 443         int i;
 444
 445         cmd_offset = (DMAE_REG_CMD_MEM + sizeof(struct dmae_command) * idx);
 446         for (i = 0; i < (sizeof(struct dmae_command)/4); i++) {
 447                 REG_WR(bp, cmd_offset + i*4, *(((u32 *)dmae) + i));
 448         }
 449         REG_WR(bp, dmae_reg_go_c[idx], 1);
 450 }
 451
 452 u32 bnx2x_dmae_opcode_add_comp(u32 opcode, u8 comp_type)
 453 {
 454         return opcode | ((comp_type << DMAE_COMMAND_C_DST_SHIFT) |
 455                            DMAE_CMD_C_ENABLE);
 456 }
 457
 458 u32 bnx2x_dmae_opcode_clr_src_reset(u32 opcode)
 459 {
 460         return opcode & ~DMAE_CMD_SRC_RESET;
 461 }
 462
 463 u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type,
 464                              bool with_comp, u8 comp_type)
 465 {
 466         u32 opcode = 0;
 467
 468         opcode |= ((src_type << DMAE_COMMAND_SRC_SHIFT) |
 469                    (dst_type << DMAE_COMMAND_DST_SHIFT));
 470
 471         opcode |= (DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET);
 472
 473         opcode |= (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0);
 474         opcode |= ((BP_VN(bp) << DMAE_CMD_E1HVN_SHIFT) |
 475                    (BP_VN(bp) << DMAE_COMMAND_DST_VN_SHIFT));
 476         opcode |= (DMAE_COM_SET_ERR << DMAE_COMMAND_ERR_POLICY_SHIFT);
 477
 478 #ifdef __BIG_ENDIAN
 479         opcode |= DMAE_CMD_ENDIANITY_B_DW_SWAP;
 480 #else
 481         opcode |= DMAE_CMD_ENDIANITY_DW_SWAP;
 482 #endif
 483         if (with_comp)
 484                 opcode = bnx2x_dmae_opcode_add_comp(opcode, comp_type);
 485         return opcode;
 486 }
 487
 488 void bnx2x_prep_dmae_with_comp(struct bnx2x *bp,
 489                                       struct dmae_command *dmae,
 490                                       u8 src_type, u8 dst_type)
 491 {
 492         memset(dmae, 0, sizeof(struct dmae_command));
 493
 494         /* set the opcode */
 495         dmae->opcode = bnx2x_dmae_opcode(bp, src_type, dst_type,
 496                                          true, DMAE_COMP_PCI);
 497
 498         /* fill in the completion parameters */
 499         dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_comp));
 500         dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_comp));
 501         dmae->comp_val = DMAE_COMP_VAL;
 502 }
 503
 504 /* issue a dmae command over the init-channel and wait for completion */
 505 int bnx2x_issue_dmae_with_comp(struct bnx2x *bp, struct dmae_command *dmae)
 506 {
 507         u32 *wb_comp = bnx2x_sp(bp, wb_comp);
 508         int cnt = CHIP_REV_IS_SLOW(bp) ? (400000) : 4000;
 509         int rc = 0;
 510
 511         /*
 512          * Lock the dmae channel. Disable BHs to prevent a dead-lock
 513          * as long as this code is called both from syscall context and
 514          * from ndo_set_rx_mode() flow that may be called from BH.
 515          */
 516         spin_lock_bh(&bp->dmae_lock);
 517
 518         /* reset completion */
 519         *wb_comp = 0;
 520
 521         /* post the command on the channel used for initializations */
 522         bnx2x_post_dmae(bp, dmae, INIT_DMAE_C(bp));
 523
 524         /* wait for completion */
 525         udelay(5);
 526         while ((*wb_comp & ~DMAE_PCI_ERR_FLAG) != DMAE_COMP_VAL) {
 527
 528                 if (!cnt ||
 529                     (bp->recovery_state != BNX2X_RECOVERY_DONE &&
 530                      bp->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) {
 531                         BNX2X_ERR("DMAE timeout!\n");
 532                         rc = DMAE_TIMEOUT;
 533                         goto unlock;
 534                 }
 535                 cnt--;
 536                 udelay(50);
 537         }
 538         if (*wb_comp & DMAE_PCI_ERR_FLAG) {
 539                 BNX2X_ERR("DMAE PCI error!\n");
 540                 rc = DMAE_PCI_ERROR;
 541         }
 542
 543 unlock:
 544         spin_unlock_bh(&bp->dmae_lock);
 545         return rc;
 546 }
 547
 548 void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
 549                       u32 len32)
 550 {
 551         struct dmae_command dmae;
 552
 553         if (!bp->dmae_ready) {
 554                 u32 *data = bnx2x_sp(bp, wb_data[0]);
 555
 556                 if (CHIP_IS_E1(bp))
 557                         bnx2x_init_ind_wr(bp, dst_addr, data, len32);
 558                 else
 559                         bnx2x_init_str_wr(bp, dst_addr, data, len32);
 560                 return;
 561         }
 562
 563         /* set opcode and fixed command fields */
 564         bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_PCI, DMAE_DST_GRC);
 565
 566         /* fill in addresses and len */
 567         dmae.src_addr_lo = U64_LO(dma_addr);
 568         dmae.src_addr_hi = U64_HI(dma_addr);
 569         dmae.dst_addr_lo = dst_addr >> 2;
 570         dmae.dst_addr_hi = 0;
 571         dmae.len = len32;
 572
 573         /* issue the command and wait for completion */
 574         bnx2x_issue_dmae_with_comp(bp, &dmae);
 575 }
 576
 577 void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32)
 578 {
 579         struct dmae_command dmae;
 580
 581         if (!bp->dmae_ready) {
 582                 u32 *data = bnx2x_sp(bp, wb_data[0]);
 583                 int i;
 584
 585                 if (CHIP_IS_E1(bp))
 586                         for (i = 0; i < len32; i++)
 587                                 data[i] = bnx2x_reg_rd_ind(bp, src_addr + i*4);
 588                 else
 589                         for (i = 0; i < len32; i++)
 590                                 data[i] = REG_RD(bp, src_addr + i*4);
 591
 592                 return;
 593         }
 594
 595         /* set opcode and fixed command fields */
 596         bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_GRC, DMAE_DST_PCI);
 597
 598         /* fill in addresses and len */
 599         dmae.src_addr_lo = src_addr >> 2;
 600         dmae.src_addr_hi = 0;
 601         dmae.dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_data));
 602         dmae.dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_data));
 603         dmae.len = len32;
 604
 605         /* issue the command and wait for completion */
 606         bnx2x_issue_dmae_with_comp(bp, &dmae);
 607 }
 608
 609 static void bnx2x_write_dmae_phys_len(struct bnx2x *bp, dma_addr_t phys_addr,
 610                                       u32 addr, u32 len)
 611 {
 612         int dmae_wr_max = DMAE_LEN32_WR_MAX(bp);
 613         int offset = 0;
 614
 615         while (len > dmae_wr_max) {
 616                 bnx2x_write_dmae(bp, phys_addr + offset,
 617                                  addr + offset, dmae_wr_max);
 618                 offset += dmae_wr_max * 4;
 619                 len -= dmae_wr_max;
 620         }
 621
 622         bnx2x_write_dmae(bp, phys_addr + offset, addr + offset, len);
 623 }
 624
 625 static int bnx2x_mc_assert(struct bnx2x *bp)
 626 {
 627         char last_idx;
 628         int i, rc = 0;
 629         u32 row0, row1, row2, row3;
 630
 631         /* XSTORM */
 632         last_idx = REG_RD8(bp, BAR_XSTRORM_INTMEM +
 633                            XSTORM_ASSERT_LIST_INDEX_OFFSET);
 634         if (last_idx)
 635                 BNX2X_ERR("XSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
 636
 637         /* print the asserts */
 638         for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
 639
 640                 row0 = REG_RD(bp, BAR_XSTRORM_INTMEM +
 641                               XSTORM_ASSERT_LIST_OFFSET(i));
 642                 row1 = REG_RD(bp, BAR_XSTRORM_INTMEM +
 643                               XSTORM_ASSERT_LIST_OFFSET(i) + 4);
 644                 row2 = REG_RD(bp, BAR_XSTRORM_INTMEM +
 645                               XSTORM_ASSERT_LIST_OFFSET(i) + 8);
 646                 row3 = REG_RD(bp, BAR_XSTRORM_INTMEM +
 647                               XSTORM_ASSERT_LIST_OFFSET(i) + 12);
 648
 649                 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
 650                         BNX2X_ERR("XSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
 651                                   i, row3, row2, row1, row0);
 652                         rc++;
 653                 } else {
 654                         break;
 655                 }
 656         }
 657
 658         /* TSTORM */
 659         last_idx = REG_RD8(bp, BAR_TSTRORM_INTMEM +
 660                            TSTORM_ASSERT_LIST_INDEX_OFFSET);
 661         if (last_idx)
 662                 BNX2X_ERR("TSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
 663
 664         /* print the asserts */
 665         for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
 666
 667                 row0 = REG_RD(bp, BAR_TSTRORM_INTMEM +
 668                               TSTORM_ASSERT_LIST_OFFSET(i));
 669                 row1 = REG_RD(bp, BAR_TSTRORM_INTMEM +
 670                               TSTORM_ASSERT_LIST_OFFSET(i) + 4);
 671                 row2 = REG_RD(bp, BAR_TSTRORM_INTMEM +
 672                               TSTORM_ASSERT_LIST_OFFSET(i) + 8);
 673                 row3 = REG_RD(bp, BAR_TSTRORM_INTMEM +
 674                               TSTORM_ASSERT_LIST_OFFSET(i) + 12);
 675
 676                 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
 677                         BNX2X_ERR("TSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
 678                                   i, row3, row2, row1, row0);
 679                         rc++;
 680                 } else {
 681                         break;
 682                 }
 683         }
 684
 685         /* CSTORM */
 686         last_idx = REG_RD8(bp, BAR_CSTRORM_INTMEM +
 687                            CSTORM_ASSERT_LIST_INDEX_OFFSET);
 688         if (last_idx)
 689                 BNX2X_ERR("CSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
 690
 691         /* print the asserts */
 692         for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
 693
 694                 row0 = REG_RD(bp, BAR_CSTRORM_INTMEM +
 695                               CSTORM_ASSERT_LIST_OFFSET(i));
 696                 row1 = REG_RD(bp, BAR_CSTRORM_INTMEM +
 697                               CSTORM_ASSERT_LIST_OFFSET(i) + 4);
 698                 row2 = REG_RD(bp, BAR_CSTRORM_INTMEM +
 699                               CSTORM_ASSERT_LIST_OFFSET(i) + 8);
 700                 row3 = REG_RD(bp, BAR_CSTRORM_INTMEM +
 701                               CSTORM_ASSERT_LIST_OFFSET(i) + 12);
 702
 703                 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
 704                         BNX2X_ERR("CSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
 705                                   i, row3, row2, row1, row0);
 706                         rc++;
 707                 } else {
 708                         break;
 709                 }
 710         }
 711
 712         /* USTORM */
 713         last_idx = REG_RD8(bp, BAR_USTRORM_INTMEM +
 714                            USTORM_ASSERT_LIST_INDEX_OFFSET);
 715         if (last_idx)
 716                 BNX2X_ERR("USTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
 717
 718         /* print the asserts */
 719         for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
 720
 721                 row0 = REG_RD(bp, BAR_USTRORM_INTMEM +
 722                               USTORM_ASSERT_LIST_OFFSET(i));
 723                 row1 = REG_RD(bp, BAR_USTRORM_INTMEM +
 724                               USTORM_ASSERT_LIST_OFFSET(i) + 4);
 725                 row2 = REG_RD(bp, BAR_USTRORM_INTMEM +
 726                               USTORM_ASSERT_LIST_OFFSET(i) + 8);
 727                 row3 = REG_RD(bp, BAR_USTRORM_INTMEM +
 728                               USTORM_ASSERT_LIST_OFFSET(i) + 12);
 729
 730                 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
 731                         BNX2X_ERR("USTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
 732                                   i, row3, row2, row1, row0);
 733                         rc++;
 734                 } else {
 735                         break;
 736                 }
 737         }
 738
 739         return rc;
 740 }
 741
 742 void bnx2x_fw_dump_lvl(struct bnx2x *bp, const char *lvl)
 743 {
 744         u32 addr, val;
 745         u32 mark, offset;
 746         __be32 data[9];
 747         int word;
 748         u32 trace_shmem_base;
 749         if (BP_NOMCP(bp)) {
 750                 BNX2X_ERR("NO MCP - can not dump\n");
 751                 return;
 752         }
 753         netdev_printk(lvl, bp->dev, "bc %d.%d.%d\n",
 754                 (bp->common.bc_ver & 0xff0000) >> 16,
 755                 (bp->common.bc_ver & 0xff00) >> 8,
 756                 (bp->common.bc_ver & 0xff));
 757
 758         val = REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER);
 759         if (val == REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER))
 760                 BNX2X_ERR("%s" "MCP PC at 0x%x\n", lvl, val);
 761
 762         if (BP_PATH(bp) == 0)
 763                 trace_shmem_base = bp->common.shmem_base;
 764         else
 765                 trace_shmem_base = SHMEM2_RD(bp, other_shmem_base_addr);
 766         addr = trace_shmem_base - 0x800;
 767
 768         /* validate TRCB signature */
 769         mark = REG_RD(bp, addr);
 770         if (mark != MFW_TRACE_SIGNATURE) {
 771                 BNX2X_ERR("Trace buffer signature is missing.");
 772                 return ;
 773         }
 774
 775         /* read cyclic buffer pointer */
 776         addr += 4;
 777         mark = REG_RD(bp, addr);
 778         mark = (CHIP_IS_E1x(bp) ? MCP_REG_MCPR_SCRATCH : MCP_A_REG_MCPR_SCRATCH)
 779                         + ((mark + 0x3) & ~0x3) - 0x08000000;
 780         printk("%s" "begin fw dump (mark 0x%x)\n", lvl, mark);
 781
 782         printk("%s", lvl);
 783
 784         /* dump buffer after the mark */
 785         for (offset = mark; offset <= trace_shmem_base; offset += 0x8*4) {
 786                 for (word = 0; word < 8; word++)
 787                         data[word] = htonl(REG_RD(bp, offset + 4*word));
 788                 data[8] = 0x0;
 789                 pr_cont("%s", (char *)data);
 790         }
 791
 792         /* dump buffer before the mark */
 793         for (offset = addr + 4; offset <= mark; offset += 0x8*4) {
 794                 for (word = 0; word < 8; word++)
 795                         data[word] = htonl(REG_RD(bp, offset + 4*word));
 796                 data[8] = 0x0;
 797                 pr_cont("%s", (char *)data);
 798         }
 799         printk("%s" "end of fw dump\n", lvl);
 800 }
 801
 802 static void bnx2x_fw_dump(struct bnx2x *bp)
 803 {
 804         bnx2x_fw_dump_lvl(bp, KERN_ERR);
 805 }
 806
 807 static void bnx2x_hc_int_disable(struct bnx2x *bp)
 808 {
 809         int port = BP_PORT(bp);
 810         u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
 811         u32 val = REG_RD(bp, addr);
 812
 813         /* in E1 we must use only PCI configuration space to disable
 814          * MSI/MSIX capablility
 815          * It's forbitten to disable IGU_PF_CONF_MSI_MSIX_EN in HC block
 816          */
 817         if (CHIP_IS_E1(bp)) {
 818                 /* Since IGU_PF_CONF_MSI_MSIX_EN still always on
 819                  * Use mask register to prevent from HC sending interrupts
 820                  * after we exit the function
 821                  */
 822                 REG_WR(bp, HC_REG_INT_MASK + port*4, 0);
 823
 824                 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
 825                          HC_CONFIG_0_REG_INT_LINE_EN_0 |
 826                          HC_CONFIG_0_REG_ATTN_BIT_EN_0);
 827         } else
 828                 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
 829                          HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
 830                          HC_CONFIG_0_REG_INT_LINE_EN_0 |
 831                          HC_CONFIG_0_REG_ATTN_BIT_EN_0);
 832
 833         DP(NETIF_MSG_IFDOWN,
 834            "write %x to HC %d (addr 0x%x)\n",
 835            val, port, addr);
 836
 837         /* flush all outstanding writes */
 838         mmiowb();
 839
 840         REG_WR(bp, addr, val);
 841         if (REG_RD(bp, addr) != val)
 842                 BNX2X_ERR("BUG! proper val not read from IGU!\n");
 843 }
 844
 845 static void bnx2x_igu_int_disable(struct bnx2x *bp)
 846 {
 847         u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
 848
 849         val &= ~(IGU_PF_CONF_MSI_MSIX_EN |
 850                  IGU_PF_CONF_INT_LINE_EN |
 851                  IGU_PF_CONF_ATTN_BIT_EN);
 852
 853         DP(NETIF_MSG_IFDOWN, "write %x to IGU\n", val);
 854
 855         /* flush all outstanding writes */
 856         mmiowb();
 857
 858         REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
 859         if (REG_RD(bp, IGU_REG_PF_CONFIGURATION) != val)
 860                 BNX2X_ERR("BUG! proper val not read from IGU!\n");
 861 }
 862
 863 static void bnx2x_int_disable(struct bnx2x *bp)
 864 {
 865         if (bp->common.int_block == INT_BLOCK_HC)
 866                 bnx2x_hc_int_disable(bp);
 867         else
 868                 bnx2x_igu_int_disable(bp);
 869 }
 870
 871 void bnx2x_panic_dump(struct bnx2x *bp, bool disable_int)
 872 {
 873         int i;
 874         u16 j;
 875         struct hc_sp_status_block_data sp_sb_data;
 876         int func = BP_FUNC(bp);
 877 #ifdef BNX2X_STOP_ON_ERROR
 878         u16 start = 0, end = 0;
 879         u8 cos;
 880 #endif
 881         if (disable_int)
 882                 bnx2x_int_disable(bp);
 883
 884         bp->stats_state = STATS_STATE_DISABLED;
 885         bp->eth_stats.unrecoverable_error++;
 886         DP(BNX2X_MSG_STATS, "stats_state - DISABLED\n");
 887
 888         BNX2X_ERR("begin crash dump -----------------\n");
 889
 890         /* Indices */
 891         /* Common */
 892         BNX2X_ERR("def_idx(0x%x)  def_att_idx(0x%x)  attn_state(0x%x)  spq_prod_idx(0x%x) next_stats_cnt(0x%x)\n",
 893                   bp->def_idx, bp->def_att_idx, bp->attn_state,
 894                   bp->spq_prod_idx, bp->stats_counter);
 895         BNX2X_ERR("DSB: attn bits(0x%x)  ack(0x%x)  id(0x%x)  idx(0x%x)\n",
 896                   bp->def_status_blk->atten_status_block.attn_bits,
 897                   bp->def_status_blk->atten_status_block.attn_bits_ack,
 898                   bp->def_status_blk->atten_status_block.status_block_id,
 899                   bp->def_status_blk->atten_status_block.attn_bits_index);
 900         BNX2X_ERR("     def (");
 901         for (i = 0; i < HC_SP_SB_MAX_INDICES; i++)
 902                 pr_cont("0x%x%s",
 903                         bp->def_status_blk->sp_sb.index_values[i],
 904                         (i == HC_SP_SB_MAX_INDICES - 1) ? ")  " : " ");
 905
 906         for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++)
 907                 *((u32 *)&sp_sb_data + i) = REG_RD(bp, BAR_CSTRORM_INTMEM +
 908                         CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) +
 909                         i*sizeof(u32));
 910
 911         pr_cont("igu_sb_id(0x%x)  igu_seg_id(0x%x) pf_id(0x%x)  vnic_id(0x%x)  vf_id(0x%x)  vf_valid (0x%x) state(0x%x)\n",
 912                sp_sb_data.igu_sb_id,
 913                sp_sb_data.igu_seg_id,
 914                sp_sb_data.p_func.pf_id,
 915                sp_sb_data.p_func.vnic_id,
 916                sp_sb_data.p_func.vf_id,
 917                sp_sb_data.p_func.vf_valid,
 918                sp_sb_data.state);
 919
 920
 921         for_each_eth_queue(bp, i) {
 922                 struct bnx2x_fastpath *fp = &bp->fp[i];
 923                 int loop;
 924                 struct hc_status_block_data_e2 sb_data_e2;
 925                 struct hc_status_block_data_e1x sb_data_e1x;
 926                 struct hc_status_block_sm  *hc_sm_p =
 927                         CHIP_IS_E1x(bp) ?
 928                         sb_data_e1x.common.state_machine :
 929                         sb_data_e2.common.state_machine;
 930                 struct hc_index_data *hc_index_p =
 931                         CHIP_IS_E1x(bp) ?
 932                         sb_data_e1x.index_data :
 933                         sb_data_e2.index_data;
 934                 u8 data_size, cos;
 935                 u32 *sb_data_p;
 936                 struct bnx2x_fp_txdata txdata;
 937
 938                 /* Rx */
 939                 BNX2X_ERR("fp%d: rx_bd_prod(0x%x)  rx_bd_cons(0x%x)  rx_comp_prod(0x%x)  rx_comp_cons(0x%x)  *rx_cons_sb(0x%x)\n",
 940                           i, fp->rx_bd_prod, fp->rx_bd_cons,
 941                           fp->rx_comp_prod,
 942                           fp->rx_comp_cons, le16_to_cpu(*fp->rx_cons_sb));
 943                 BNX2X_ERR("     rx_sge_prod(0x%x)  last_max_sge(0x%x)  fp_hc_idx(0x%x)\n",
 944                           fp->rx_sge_prod, fp->last_max_sge,
 945                           le16_to_cpu(fp->fp_hc_idx));
 946
 947                 /* Tx */
 948                 for_each_cos_in_tx_queue(fp, cos)
 949                 {
 950                         txdata = *fp->txdata_ptr[cos];
 951                         BNX2X_ERR("fp%d: tx_pkt_prod(0x%x)  tx_pkt_cons(0x%x)  tx_bd_prod(0x%x)  tx_bd_cons(0x%x)  *tx_cons_sb(0x%x)\n",
 952                                   i, txdata.tx_pkt_prod,
 953                                   txdata.tx_pkt_cons, txdata.tx_bd_prod,
 954                                   txdata.tx_bd_cons,
 955                                   le16_to_cpu(*txdata.tx_cons_sb));
 956                 }
 957
 958                 loop = CHIP_IS_E1x(bp) ?
 959                         HC_SB_MAX_INDICES_E1X : HC_SB_MAX_INDICES_E2;
 960
 961                 /* host sb data */
 962
 963                 if (IS_FCOE_FP(fp))
 964                         continue;
 965
 966                 BNX2X_ERR("     run indexes (");
 967                 for (j = 0; j < HC_SB_MAX_SM; j++)
 968                         pr_cont("0x%x%s",
 969                                fp->sb_running_index[j],
 970                                (j == HC_SB_MAX_SM - 1) ? ")" : " ");
 971
 972                 BNX2X_ERR("     indexes (");
 973                 for (j = 0; j < loop; j++)
 974                         pr_cont("0x%x%s",
 975                                fp->sb_index_values[j],
 976                                (j == loop - 1) ? ")" : " ");
 977                 /* fw sb data */
 978                 data_size = CHIP_IS_E1x(bp) ?
 979                         sizeof(struct hc_status_block_data_e1x) :
 980                         sizeof(struct hc_status_block_data_e2);
 981                 data_size /= sizeof(u32);
 982                 sb_data_p = CHIP_IS_E1x(bp) ?
 983                         (u32 *)&sb_data_e1x :
 984                         (u32 *)&sb_data_e2;
 985                 /* copy sb data in here */
 986                 for (j = 0; j < data_size; j++)
 987                         *(sb_data_p + j) = REG_RD(bp, BAR_CSTRORM_INTMEM +
 988                                 CSTORM_STATUS_BLOCK_DATA_OFFSET(fp->fw_sb_id) +
 989                                 j * sizeof(u32));
 990
 991                 if (!CHIP_IS_E1x(bp)) {
 992                         pr_cont("pf_id(0x%x)  vf_id(0x%x)  vf_valid(0x%x) vnic_id(0x%x)  same_igu_sb_1b(0x%x) state(0x%x)\n",
 993                                 sb_data_e2.common.p_func.pf_id,
 994                                 sb_data_e2.common.p_func.vf_id,
 995                                 sb_data_e2.common.p_func.vf_valid,
 996                                 sb_data_e2.common.p_func.vnic_id,
 997                                 sb_data_e2.common.same_igu_sb_1b,
 998                                 sb_data_e2.common.state);
 999                 } else {
1000                         pr_cont("pf_id(0x%x)  vf_id(0x%x)  vf_valid(0x%x) vnic_id(0x%x)  same_igu_sb_1b(0x%x) state(0x%x)\n",
1001                                 sb_data_e1x.common.p_func.pf_id,
1002                                 sb_data_e1x.common.p_func.vf_id,
1003                                 sb_data_e1x.common.p_func.vf_valid,
1004                                 sb_data_e1x.common.p_func.vnic_id,
1005                                 sb_data_e1x.common.same_igu_sb_1b,
1006                                 sb_data_e1x.common.state);
1007                 }
1008
1009                 /* SB_SMs data */
1010                 for (j = 0; j < HC_SB_MAX_SM; j++) {
1011                         pr_cont("SM[%d] __flags (0x%x) igu_sb_id (0x%x)  igu_seg_id(0x%x) time_to_expire (0x%x) timer_value(0x%x)\n",
1012                                 j, hc_sm_p[j].__flags,
1013                                 hc_sm_p[j].igu_sb_id,
1014                                 hc_sm_p[j].igu_seg_id,
1015                                 hc_sm_p[j].time_to_expire,
1016                                 hc_sm_p[j].timer_value);
1017                 }
1018
1019                 /* Indecies data */
1020                 for (j = 0; j < loop; j++) {
1021                         pr_cont("INDEX[%d] flags (0x%x) timeout (0x%x)\n", j,
1022                                hc_index_p[j].flags,
1023                                hc_index_p[j].timeout);
1024                 }
1025         }
1026
1027 #ifdef BNX2X_STOP_ON_ERROR
1028
1029         /* event queue */
1030         for (i = 0; i < NUM_EQ_DESC; i++) {
1031                 u32 *data = (u32 *)&bp->eq_ring[i].message.data;
1032
1033                 BNX2X_ERR("event queue [%d]: header: opcode %d, error %d\n",
1034                           i, bp->eq_ring[i].message.opcode,
1035                           bp->eq_ring[i].message.error);
1036                 BNX2X_ERR("data: %x %x %x\n", data[0], data[1], data[2]);
1037         }
1038
1039         /* Rings */
1040         /* Rx */
1041         for_each_valid_rx_queue(bp, i) {
1042                 struct bnx2x_fastpath *fp = &bp->fp[i];
1043
1044                 start = RX_BD(le16_to_cpu(*fp->rx_cons_sb) - 10);
1045                 end = RX_BD(le16_to_cpu(*fp->rx_cons_sb) + 503);
1046                 for (j = start; j != end; j = RX_BD(j + 1)) {
1047                         u32 *rx_bd = (u32 *)&fp->rx_desc_ring[j];
1048                         struct sw_rx_bd *sw_bd = &fp->rx_buf_ring[j];
1049
1050                         BNX2X_ERR("fp%d: rx_bd[%x]=[%x:%x]  sw_bd=[%p]\n",
1051                                   i, j, rx_bd[1], rx_bd[0], sw_bd->data);
1052                 }
1053
1054                 start = RX_SGE(fp->rx_sge_prod);
1055                 end = RX_SGE(fp->last_max_sge);
1056                 for (j = start; j != end; j = RX_SGE(j + 1)) {
1057                         u32 *rx_sge = (u32 *)&fp->rx_sge_ring[j];
1058                         struct sw_rx_page *sw_page = &fp->rx_page_ring[j];
1059
1060                         BNX2X_ERR("fp%d: rx_sge[%x]=[%x:%x]  sw_page=[%p]\n",
1061                                   i, j, rx_sge[1], rx_sge[0], sw_page->page);
1062                 }
1063
1064                 start = RCQ_BD(fp->rx_comp_cons - 10);
1065                 end = RCQ_BD(fp->rx_comp_cons + 503);
1066                 for (j = start; j != end; j = RCQ_BD(j + 1)) {
1067                         u32 *cqe = (u32 *)&fp->rx_comp_ring[j];
1068
1069                         BNX2X_ERR("fp%d: cqe[%x]=[%x:%x:%x:%x]\n",
1070                                   i, j, cqe[0], cqe[1], cqe[2], cqe[3]);
1071                 }
1072         }
1073
1074         /* Tx */
1075         for_each_valid_tx_queue(bp, i) {
1076                 struct bnx2x_fastpath *fp = &bp->fp[i];
1077                 for_each_cos_in_tx_queue(fp, cos) {
1078                         struct bnx2x_fp_txdata *txdata = fp->txdata_ptr[cos];
1079
1080                         start = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) - 10);
1081                         end = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) + 245);
1082                         for (j = start; j != end; j = TX_BD(j + 1)) {
1083                                 struct sw_tx_bd *sw_bd =
1084                                         &txdata->tx_buf_ring[j];
1085
1086                                 BNX2X_ERR("fp%d: txdata %d, packet[%x]=[%p,%x]\n",
1087                                           i, cos, j, sw_bd->skb,
1088                                           sw_bd->first_bd);
1089                         }
1090
1091                         start = TX_BD(txdata->tx_bd_cons - 10);
1092                         end = TX_BD(txdata->tx_bd_cons + 254);
1093                         for (j = start; j != end; j = TX_BD(j + 1)) {
1094                                 u32 *tx_bd = (u32 *)&txdata->tx_desc_ring[j];
1095
1096                                 BNX2X_ERR("fp%d: txdata %d, tx_bd[%x]=[%x:%x:%x:%x]\n",
1097                                           i, cos, j, tx_bd[0], tx_bd[1],
1098                                           tx_bd[2], tx_bd[3]);
1099                         }
1100                 }
1101         }
1102 #endif
1103         bnx2x_fw_dump(bp);
1104         bnx2x_mc_assert(bp);
1105         BNX2X_ERR("end crash dump -----------------\n");
1106 }
1107
1108 /*
1109  * FLR Support for E2
1110  *
1111  * bnx2x_pf_flr_clnup() is called during nic_load in the per function HW
1112  * initialization.
1113  */
1114 #define FLR_WAIT_USEC           10000   /* 10 miliseconds */
1115 #define FLR_WAIT_INTERVAL       50      /* usec */
1116 #define FLR_POLL_CNT            (FLR_WAIT_USEC/FLR_WAIT_INTERVAL) /* 200 */
1117
1118 struct pbf_pN_buf_regs {
1119         int pN;
1120         u32 init_crd;
1121         u32 crd;
1122         u32 crd_freed;
1123 };
1124
1125 struct pbf_pN_cmd_regs {
1126         int pN;
1127         u32 lines_occup;
1128         u32 lines_freed;
1129 };
1130
1131 static void bnx2x_pbf_pN_buf_flushed(struct bnx2x *bp,
1132                                      struct pbf_pN_buf_regs *regs,
1133                                      u32 poll_count)
1134 {
1135         u32 init_crd, crd, crd_start, crd_freed, crd_freed_start;
1136         u32 cur_cnt = poll_count;
1137
1138         crd_freed = crd_freed_start = REG_RD(bp, regs->crd_freed);
1139         crd = crd_start = REG_RD(bp, regs->crd);
1140         init_crd = REG_RD(bp, regs->init_crd);
1141
1142         DP(BNX2X_MSG_SP, "INIT CREDIT[%d] : %x\n", regs->pN, init_crd);
1143         DP(BNX2X_MSG_SP, "CREDIT[%d]      : s:%x\n", regs->pN, crd);
1144         DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: s:%x\n", regs->pN, crd_freed);
1145
1146         while ((crd != init_crd) && ((u32)SUB_S32(crd_freed, crd_freed_start) <
1147                (init_crd - crd_start))) {
1148                 if (cur_cnt--) {
1149                         udelay(FLR_WAIT_INTERVAL);
1150                         crd = REG_RD(bp, regs->crd);
1151                         crd_freed = REG_RD(bp, regs->crd_freed);
1152                 } else {
1153                         DP(BNX2X_MSG_SP, "PBF tx buffer[%d] timed out\n",
1154                            regs->pN);
1155                         DP(BNX2X_MSG_SP, "CREDIT[%d]      : c:%x\n",
1156                            regs->pN, crd);
1157                         DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: c:%x\n",
1158                            regs->pN, crd_freed);
1159                         break;
1160                 }
1161         }
1162         DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF tx buffer[%d]\n",
1163            poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN);
1164 }
1165
1166 static void bnx2x_pbf_pN_cmd_flushed(struct bnx2x *bp,
1167                                      struct pbf_pN_cmd_regs *regs,
1168                                      u32 poll_count)
1169 {
1170         u32 occup, to_free, freed, freed_start;
1171         u32 cur_cnt = poll_count;
1172
1173         occup = to_free = REG_RD(bp, regs->lines_occup);
1174         freed = freed_start = REG_RD(bp, regs->lines_freed);
1175
1176         DP(BNX2X_MSG_SP, "OCCUPANCY[%d]   : s:%x\n", regs->pN, occup);
1177         DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n", regs->pN, freed);
1178
1179         while (occup && ((u32)SUB_S32(freed, freed_start) < to_free)) {
1180                 if (cur_cnt--) {
1181                         udelay(FLR_WAIT_INTERVAL);
1182                         occup = REG_RD(bp, regs->lines_occup);
1183                         freed = REG_RD(bp, regs->lines_freed);
1184                 } else {
1185                         DP(BNX2X_MSG_SP, "PBF cmd queue[%d] timed out\n",
1186                            regs->pN);
1187                         DP(BNX2X_MSG_SP, "OCCUPANCY[%d]   : s:%x\n",
1188                            regs->pN, occup);
1189                         DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n",
1190                            regs->pN, freed);
1191                         break;
1192                 }
1193         }
1194         DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF cmd queue[%d]\n",
1195            poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN);
1196 }
1197
1198 static u32 bnx2x_flr_clnup_reg_poll(struct bnx2x *bp, u32 reg,
1199                                     u32 expected, u32 poll_count)
1200 {
1201         u32 cur_cnt = poll_count;
1202         u32 val;
1203
1204         while ((val = REG_RD(bp, reg)) != expected && cur_cnt--)
1205                 udelay(FLR_WAIT_INTERVAL);
1206
1207         return val;
1208 }
1209
1210 int bnx2x_flr_clnup_poll_hw_counter(struct bnx2x *bp, u32 reg,
1211                                     char *msg, u32 poll_cnt)
1212 {
1213         u32 val = bnx2x_flr_clnup_reg_poll(bp, reg, 0, poll_cnt);
1214         if (val != 0) {
1215                 BNX2X_ERR("%s usage count=%d\n", msg, val);
1216                 return 1;
1217         }
1218         return 0;
1219 }
1220
1221 /* Common routines with VF FLR cleanup */
1222 u32 bnx2x_flr_clnup_poll_count(struct bnx2x *bp)
1223 {
1224         /* adjust polling timeout */
1225         if (CHIP_REV_IS_EMUL(bp))
1226                 return FLR_POLL_CNT * 2000;
1227
1228         if (CHIP_REV_IS_FPGA(bp))
1229                 return FLR_POLL_CNT * 120;
1230
1231         return FLR_POLL_CNT;
1232 }
1233
1234 void bnx2x_tx_hw_flushed(struct bnx2x *bp, u32 poll_count)
1235 {
1236         struct pbf_pN_cmd_regs cmd_regs[] = {
1237                 {0, (CHIP_IS_E3B0(bp)) ?
1238                         PBF_REG_TQ_OCCUPANCY_Q0 :
1239                         PBF_REG_P0_TQ_OCCUPANCY,
1240                     (CHIP_IS_E3B0(bp)) ?
1241                         PBF_REG_TQ_LINES_FREED_CNT_Q0 :
1242                         PBF_REG_P0_TQ_LINES_FREED_CNT},
1243                 {1, (CHIP_IS_E3B0(bp)) ?
1244                         PBF_REG_TQ_OCCUPANCY_Q1 :
1245                         PBF_REG_P1_TQ_OCCUPANCY,
1246                     (CHIP_IS_E3B0(bp)) ?
1247                         PBF_REG_TQ_LINES_FREED_CNT_Q1 :
1248                         PBF_REG_P1_TQ_LINES_FREED_CNT},
1249                 {4, (CHIP_IS_E3B0(bp)) ?
1250                         PBF_REG_TQ_OCCUPANCY_LB_Q :
1251                         PBF_REG_P4_TQ_OCCUPANCY,
1252                     (CHIP_IS_E3B0(bp)) ?
1253                         PBF_REG_TQ_LINES_FREED_CNT_LB_Q :
1254                         PBF_REG_P4_TQ_LINES_FREED_CNT}
1255         };
1256
1257         struct pbf_pN_buf_regs buf_regs[] = {
1258                 {0, (CHIP_IS_E3B0(bp)) ?
1259                         PBF_REG_INIT_CRD_Q0 :
1260                         PBF_REG_P0_INIT_CRD ,
1261                     (CHIP_IS_E3B0(bp)) ?
1262                         PBF_REG_CREDIT_Q0 :
1263                         PBF_REG_P0_CREDIT,
1264                     (CHIP_IS_E3B0(bp)) ?
1265                         PBF_REG_INTERNAL_CRD_FREED_CNT_Q0 :
1266                         PBF_REG_P0_INTERNAL_CRD_FREED_CNT},
1267                 {1, (CHIP_IS_E3B0(bp)) ?
1268                         PBF_REG_INIT_CRD_Q1 :
1269                         PBF_REG_P1_INIT_CRD,
1270                     (CHIP_IS_E3B0(bp)) ?
1271                         PBF_REG_CREDIT_Q1 :
1272                         PBF_REG_P1_CREDIT,
1273                     (CHIP_IS_E3B0(bp)) ?
1274                         PBF_REG_INTERNAL_CRD_FREED_CNT_Q1 :
1275                         PBF_REG_P1_INTERNAL_CRD_FREED_CNT},
1276                 {4, (CHIP_IS_E3B0(bp)) ?
1277                         PBF_REG_INIT_CRD_LB_Q :
1278                         PBF_REG_P4_INIT_CRD,
1279                     (CHIP_IS_E3B0(bp)) ?
1280                         PBF_REG_CREDIT_LB_Q :
1281                         PBF_REG_P4_CREDIT,
1282                     (CHIP_IS_E3B0(bp)) ?
1283                         PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q :
1284                         PBF_REG_P4_INTERNAL_CRD_FREED_CNT},
1285         };
1286
1287         int i;
1288
1289         /* Verify the command queues are flushed P0, P1, P4 */
1290         for (i = 0; i < ARRAY_SIZE(cmd_regs); i++)
1291                 bnx2x_pbf_pN_cmd_flushed(bp, &cmd_regs[i], poll_count);
1292
1293
1294         /* Verify the transmission buffers are flushed P0, P1, P4 */
1295         for (i = 0; i < ARRAY_SIZE(buf_regs); i++)
1296                 bnx2x_pbf_pN_buf_flushed(bp, &buf_regs[i], poll_count);
1297 }
1298
1299 #define OP_GEN_PARAM(param) \
1300         (((param) << SDM_OP_GEN_COMP_PARAM_SHIFT) & SDM_OP_GEN_COMP_PARAM)
1301
1302 #define OP_GEN_TYPE(type) \
1303         (((type) << SDM_OP_GEN_COMP_TYPE_SHIFT) & SDM_OP_GEN_COMP_TYPE)
1304
1305 #define OP_GEN_AGG_VECT(index) \
1306         (((index) << SDM_OP_GEN_AGG_VECT_IDX_SHIFT) & SDM_OP_GEN_AGG_VECT_IDX)
1307
1308
1309 int bnx2x_send_final_clnup(struct bnx2x *bp, u8 clnup_func, u32 poll_cnt)
1310 {
1311         u32 op_gen_command = 0;
1312
1313         u32 comp_addr = BAR_CSTRORM_INTMEM +
1314                         CSTORM_FINAL_CLEANUP_COMPLETE_OFFSET(clnup_func);
1315         int ret = 0;
1316
1317         if (REG_RD(bp, comp_addr)) {
1318                 BNX2X_ERR("Cleanup complete was not 0 before sending\n");
1319                 return 1;
1320         }
1321
1322         op_gen_command |= OP_GEN_PARAM(XSTORM_AGG_INT_FINAL_CLEANUP_INDEX);
1323         op_gen_command |= OP_GEN_TYPE(XSTORM_AGG_INT_FINAL_CLEANUP_COMP_TYPE);
1324         op_gen_command |= OP_GEN_AGG_VECT(clnup_func);
1325         op_gen_command |= 1 << SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT;
1326
1327         DP(BNX2X_MSG_SP, "sending FW Final cleanup\n");
1328         REG_WR(bp, XSDM_REG_OPERATION_GEN, op_gen_command);
1329
1330         if (bnx2x_flr_clnup_reg_poll(bp, comp_addr, 1, poll_cnt) != 1) {
1331                 BNX2X_ERR("FW final cleanup did not succeed\n");
1332                 DP(BNX2X_MSG_SP, "At timeout completion address contained %x\n",
1333                    (REG_RD(bp, comp_addr)));
1334                 bnx2x_panic();
1335                 return 1;
1336         }
1337         /* Zero completion for nxt FLR */
1338         REG_WR(bp, comp_addr, 0);
1339
1340         return ret;
1341 }
1342
1343 u8 bnx2x_is_pcie_pending(struct pci_dev *dev)
1344 {
1345         u16 status;
1346
1347         pcie_capability_read_word(dev, PCI_EXP_DEVSTA, &status);
1348         return status & PCI_EXP_DEVSTA_TRPND;
1349 }
1350
1351 /* PF FLR specific routines
1352 */
1353 static int bnx2x_poll_hw_usage_counters(struct bnx2x *bp, u32 poll_cnt)
1354 {
1355
1356         /* wait for CFC PF usage-counter to zero (includes all the VFs) */
1357         if (bnx2x_flr_clnup_poll_hw_counter(bp,
1358                         CFC_REG_NUM_LCIDS_INSIDE_PF,
1359                         "CFC PF usage counter timed out",
1360                         poll_cnt))
1361                 return 1;
1362
1363
1364         /* Wait for DQ PF usage-counter to zero (until DQ cleanup) */
1365         if (bnx2x_flr_clnup_poll_hw_counter(bp,
1366                         DORQ_REG_PF_USAGE_CNT,
1367                         "DQ PF usage counter timed out",
1368                         poll_cnt))
1369                 return 1;
1370
1371         /* Wait for QM PF usage-counter to zero (until DQ cleanup) */
1372         if (bnx2x_flr_clnup_poll_hw_counter(bp,
1373                         QM_REG_PF_USG_CNT_0 + 4*BP_FUNC(bp),
1374                         "QM PF usage counter timed out",
1375                         poll_cnt))
1376                 return 1;
1377
1378         /* Wait for Timer PF usage-counters to zero (until DQ cleanup) */
1379         if (bnx2x_flr_clnup_poll_hw_counter(bp,
1380                         TM_REG_LIN0_VNIC_UC + 4*BP_PORT(bp),
1381                         "Timers VNIC usage counter timed out",
1382                         poll_cnt))
1383                 return 1;
1384         if (bnx2x_flr_clnup_poll_hw_counter(bp,
1385                         TM_REG_LIN0_NUM_SCANS + 4*BP_PORT(bp),
1386                         "Timers NUM_SCANS usage counter timed out",
1387                         poll_cnt))
1388                 return 1;
1389
1390         /* Wait DMAE PF usage counter to zero */
1391         if (bnx2x_flr_clnup_poll_hw_counter(bp,
1392                         dmae_reg_go_c[INIT_DMAE_C(bp)],
1393                         "DMAE dommand register timed out",
1394                         poll_cnt))
1395                 return 1;
1396
1397         return 0;
1398 }
1399
1400 static void bnx2x_hw_enable_status(struct bnx2x *bp)
1401 {
1402         u32 val;
1403
1404         val = REG_RD(bp, CFC_REG_WEAK_ENABLE_PF);
1405         DP(BNX2X_MSG_SP, "CFC_REG_WEAK_ENABLE_PF is 0x%x\n", val);
1406
1407         val = REG_RD(bp, PBF_REG_DISABLE_PF);
1408         DP(BNX2X_MSG_SP, "PBF_REG_DISABLE_PF is 0x%x\n", val);
1409
1410         val = REG_RD(bp, IGU_REG_PCI_PF_MSI_EN);
1411         DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSI_EN is 0x%x\n", val);
1412
1413         val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_EN);
1414         DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_EN is 0x%x\n", val);
1415
1416         val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_FUNC_MASK);
1417         DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_FUNC_MASK is 0x%x\n", val);
1418
1419         val = REG_RD(bp, PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR);
1420         DP(BNX2X_MSG_SP, "PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR is 0x%x\n", val);
1421
1422         val = REG_RD(bp, PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR);
1423         DP(BNX2X_MSG_SP, "PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR is 0x%x\n", val);
1424
1425         val = REG_RD(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
1426         DP(BNX2X_MSG_SP, "PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER is 0x%x\n",
1427            val);
1428 }
1429
1430 static int bnx2x_pf_flr_clnup(struct bnx2x *bp)
1431 {
1432         u32 poll_cnt = bnx2x_flr_clnup_poll_count(bp);
1433
1434         DP(BNX2X_MSG_SP, "Cleanup after FLR PF[%d]\n", BP_ABS_FUNC(bp));
1435
1436         /* Re-enable PF target read access */
1437         REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
1438
1439         /* Poll HW usage counters */
1440         DP(BNX2X_MSG_SP, "Polling usage counters\n");
1441         if (bnx2x_poll_hw_usage_counters(bp, poll_cnt))
1442                 return -EBUSY;
1443
1444         /* Zero the igu 'trailing edge' and 'leading edge' */
1445
1446         /* Send the FW cleanup command */
1447         if (bnx2x_send_final_clnup(bp, (u8)BP_FUNC(bp), poll_cnt))
1448                 return -EBUSY;
1449
1450         /* ATC cleanup */
1451
1452         /* Verify TX hw is flushed */
1453         bnx2x_tx_hw_flushed(bp, poll_cnt);
1454
1455         /* Wait 100ms (not adjusted according to platform) */
1456         msleep(100);
1457
1458         /* Verify no pending pci transactions */
1459         if (bnx2x_is_pcie_pending(bp->pdev))
1460                 BNX2X_ERR("PCIE Transactions still pending\n");
1461
1462         /* Debug */
1463         bnx2x_hw_enable_status(bp);
1464
1465         /*
1466          * Master enable - Due to WB DMAE writes performed before this
1467          * register is re-initialized as part of the regular function init
1468          */
1469         REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
1470
1471         return 0;
1472 }
1473
1474 static void bnx2x_hc_int_enable(struct bnx2x *bp)
1475 {
1476         int port = BP_PORT(bp);
1477         u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
1478         u32 val = REG_RD(bp, addr);
1479         bool msix = (bp->flags & USING_MSIX_FLAG) ? true : false;
1480         bool single_msix = (bp->flags & USING_SINGLE_MSIX_FLAG) ? true : false;
1481         bool msi = (bp->flags & USING_MSI_FLAG) ? true : false;
1482
1483         if (msix) {
1484                 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1485                          HC_CONFIG_0_REG_INT_LINE_EN_0);
1486                 val |= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1487                         HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1488                 if (single_msix)
1489                         val |= HC_CONFIG_0_REG_SINGLE_ISR_EN_0;
1490         } else if (msi) {
1491                 val &= ~HC_CONFIG_0_REG_INT_LINE_EN_0;
1492                 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1493                         HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1494                         HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1495         } else {
1496                 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1497                         HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1498                         HC_CONFIG_0_REG_INT_LINE_EN_0 |
1499                         HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1500
1501                 if (!CHIP_IS_E1(bp)) {
1502                         DP(NETIF_MSG_IFUP,
1503                            "write %x to HC %d (addr 0x%x)\n", val, port, addr);
1504
1505                         REG_WR(bp, addr, val);
1506
1507                         val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0;
1508                 }
1509         }
1510
1511         if (CHIP_IS_E1(bp))
1512                 REG_WR(bp, HC_REG_INT_MASK + port*4, 0x1FFFF);
1513
1514         DP(NETIF_MSG_IFUP,
1515            "write %x to HC %d (addr 0x%x) mode %s\n", val, port, addr,
1516            (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
1517
1518         REG_WR(bp, addr, val);
1519         /*
1520          * Ensure that HC_CONFIG is written before leading/trailing edge config
1521          */
1522         mmiowb();
1523         barrier();
1524
1525         if (!CHIP_IS_E1(bp)) {
1526                 /* init leading/trailing edge */
1527                 if (IS_MF(bp)) {
1528                         val = (0xee0f | (1 << (BP_VN(bp) + 4)));
1529                         if (bp->port.pmf)
1530                                 /* enable nig and gpio3 attention */
1531                                 val |= 0x1100;
1532                 } else
1533                         val = 0xffff;
1534
1535                 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
1536                 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
1537         }
1538
1539         /* Make sure that interrupts are indeed enabled from here on */
1540         mmiowb();
1541 }
1542
1543 static void bnx2x_igu_int_enable(struct bnx2x *bp)
1544 {
1545         u32 val;
1546         bool msix = (bp->flags & USING_MSIX_FLAG) ? true : false;
1547         bool single_msix = (bp->flags & USING_SINGLE_MSIX_FLAG) ? true : false;
1548         bool msi = (bp->flags & USING_MSI_FLAG) ? true : false;
1549
1550         val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
1551
1552         if (msix) {
1553                 val &= ~(IGU_PF_CONF_INT_LINE_EN |
1554                          IGU_PF_CONF_SINGLE_ISR_EN);
1555                 val |= (IGU_PF_CONF_MSI_MSIX_EN |
1556                         IGU_PF_CONF_ATTN_BIT_EN);
1557
1558                 if (single_msix)
1559                         val |= IGU_PF_CONF_SINGLE_ISR_EN;
1560         } else if (msi) {
1561                 val &= ~IGU_PF_CONF_INT_LINE_EN;
1562                 val |= (IGU_PF_CONF_MSI_MSIX_EN |
1563                         IGU_PF_CONF_ATTN_BIT_EN |
1564                         IGU_PF_CONF_SINGLE_ISR_EN);
1565         } else {
1566                 val &= ~IGU_PF_CONF_MSI_MSIX_EN;
1567                 val |= (IGU_PF_CONF_INT_LINE_EN |
1568                         IGU_PF_CONF_ATTN_BIT_EN |
1569                         IGU_PF_CONF_SINGLE_ISR_EN);
1570         }
1571
1572         /* Clean previous status - need to configure igu prior to ack*/
1573         if ((!msix) || single_msix) {
1574                 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
1575                 bnx2x_ack_int(bp);
1576         }
1577
1578         val |= IGU_PF_CONF_FUNC_EN;
1579
1580         DP(NETIF_MSG_IFUP, "write 0x%x to IGU  mode %s\n",
1581            val, (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
1582
1583         REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
1584
1585         if (val & IGU_PF_CONF_INT_LINE_EN)
1586                 pci_intx(bp->pdev, true);
1587
1588         barrier();
1589
1590         /* init leading/trailing edge */
1591         if (IS_MF(bp)) {
1592                 val = (0xee0f | (1 << (BP_VN(bp) + 4)));
1593                 if (bp->port.pmf)
1594                         /* enable nig and gpio3 attention */
1595                         val |= 0x1100;
1596         } else
1597                 val = 0xffff;
1598
1599         REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
1600         REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
1601
1602         /* Make sure that interrupts are indeed enabled from here on */
1603         mmiowb();
1604 }
1605
1606 void bnx2x_int_enable(struct bnx2x *bp)
1607 {
1608         if (bp->common.int_block == INT_BLOCK_HC)
1609                 bnx2x_hc_int_enable(bp);
1610         else
1611                 bnx2x_igu_int_enable(bp);
1612 }
1613
1614 void bnx2x_int_disable_sync(struct bnx2x *bp, int disable_hw)
1615 {
1616         int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
1617         int i, offset;
1618
1619         if (disable_hw)
1620                 /* prevent the HW from sending interrupts */
1621                 bnx2x_int_disable(bp);
1622
1623         /* make sure all ISRs are done */
1624         if (msix) {
1625                 synchronize_irq(bp->msix_table[0].vector);
1626                 offset = 1;
1627                 if (CNIC_SUPPORT(bp))
1628                         offset++;
1629                 for_each_eth_queue(bp, i)
1630                         synchronize_irq(bp->msix_table[offset++].vector);
1631         } else
1632                 synchronize_irq(bp->pdev->irq);
1633
1634         /* make sure sp_task is not running */
1635         cancel_delayed_work(&bp->sp_task);
1636         cancel_delayed_work(&bp->period_task);
1637         flush_workqueue(bnx2x_wq);
1638 }
1639
1640 /* fast path */
1641
1642 /*
1643  * General service functions
1644  */
1645
1646 /* Return true if succeeded to acquire the lock */
1647 static bool bnx2x_trylock_hw_lock(struct bnx2x *bp, u32 resource)
1648 {
1649         u32 lock_status;
1650         u32 resource_bit = (1 << resource);
1651         int func = BP_FUNC(bp);
1652         u32 hw_lock_control_reg;
1653
1654         DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
1655            "Trying to take a lock on resource %d\n", resource);
1656
1657         /* Validating that the resource is within range */
1658         if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1659                 DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
1660                    "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1661                    resource, HW_LOCK_MAX_RESOURCE_VALUE);
1662                 return false;
1663         }
1664
1665         if (func <= 5)
1666                 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1667         else
1668                 hw_lock_control_reg =
1669                                 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1670
1671         /* Try to acquire the lock */
1672         REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
1673         lock_status = REG_RD(bp, hw_lock_control_reg);
1674         if (lock_status & resource_bit)
1675                 return true;
1676
1677         DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
1678            "Failed to get a lock on resource %d\n", resource);
1679         return false;
1680 }
1681
1682 /**
1683  * bnx2x_get_leader_lock_resource - get the recovery leader resource id
1684  *
1685  * @bp: driver handle
1686  *
1687  * Returns the recovery leader resource id according to the engine this function
1688  * belongs to. Currently only only 2 engines is supported.
1689  */
1690 static int bnx2x_get_leader_lock_resource(struct bnx2x *bp)
1691 {
1692         if (BP_PATH(bp))
1693                 return HW_LOCK_RESOURCE_RECOVERY_LEADER_1;
1694         else
1695                 return HW_LOCK_RESOURCE_RECOVERY_LEADER_0;
1696 }
1697
1698 /**
1699  * bnx2x_trylock_leader_lock- try to acquire a leader lock.
1700  *
1701  * @bp: driver handle
1702  *
1703  * Tries to acquire a leader lock for current engine.
1704  */
1705 static bool bnx2x_trylock_leader_lock(struct bnx2x *bp)
1706 {
1707         return bnx2x_trylock_hw_lock(bp, bnx2x_get_leader_lock_resource(bp));
1708 }
1709
1710 static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err);
1711
1712 /* schedule the sp task and mark that interrupt occurred (runs from ISR) */
1713 static int bnx2x_schedule_sp_task(struct bnx2x *bp)
1714 {
1715         /* Set the interrupt occurred bit for the sp-task to recognize it
1716          * must ack the interrupt and transition according to the IGU
1717          * state machine.
1718          */
1719         atomic_set(&bp->interrupt_occurred, 1);
1720
1721         /* The sp_task must execute only after this bit
1722          * is set, otherwise we will get out of sync and miss all
1723          * further interrupts. Hence, the barrier.
1724          */
1725         smp_wmb();
1726
1727         /* schedule sp_task to workqueue */
1728         return queue_delayed_work(bnx2x_wq, &bp->sp_task, 0);
1729 }
1730
1731 void bnx2x_sp_event(struct bnx2x_fastpath *fp, union eth_rx_cqe *rr_cqe)
1732 {
1733         struct bnx2x *bp = fp->bp;
1734         int cid = SW_CID(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1735         int command = CQE_CMD(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1736         enum bnx2x_queue_cmd drv_cmd = BNX2X_Q_CMD_MAX;
1737         struct bnx2x_queue_sp_obj *q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
1738
1739         DP(BNX2X_MSG_SP,
1740            "fp %d  cid %d  got ramrod #%d  state is %x  type is %d\n",
1741            fp->index, cid, command, bp->state,
1742            rr_cqe->ramrod_cqe.ramrod_type);
1743
1744         /* If cid is within VF range, replace the slowpath object with the
1745          * one corresponding to this VF
1746          */
1747         if (cid >= BNX2X_FIRST_VF_CID  &&
1748             cid < BNX2X_FIRST_VF_CID + BNX2X_VF_CIDS)
1749                 bnx2x_iov_set_queue_sp_obj(bp, cid, &q_obj);
1750
1751         switch (command) {
1752         case (RAMROD_CMD_ID_ETH_CLIENT_UPDATE):
1753                 DP(BNX2X_MSG_SP, "got UPDATE ramrod. CID %d\n", cid);
1754                 drv_cmd = BNX2X_Q_CMD_UPDATE;
1755                 break;
1756
1757         case (RAMROD_CMD_ID_ETH_CLIENT_SETUP):
1758                 DP(BNX2X_MSG_SP, "got MULTI[%d] setup ramrod\n", cid);
1759                 drv_cmd = BNX2X_Q_CMD_SETUP;
1760                 break;
1761
1762         case (RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP):
1763                 DP(BNX2X_MSG_SP, "got MULTI[%d] tx-only setup ramrod\n", cid);
1764                 drv_cmd = BNX2X_Q_CMD_SETUP_TX_ONLY;
1765                 break;
1766
1767         case (RAMROD_CMD_ID_ETH_HALT):
1768                 DP(BNX2X_MSG_SP, "got MULTI[%d] halt ramrod\n", cid);
1769                 drv_cmd = BNX2X_Q_CMD_HALT;
1770                 break;
1771
1772         case (RAMROD_CMD_ID_ETH_TERMINATE):
1773                 DP(BNX2X_MSG_SP, "got MULTI[%d] teminate ramrod\n", cid);
1774                 drv_cmd = BNX2X_Q_CMD_TERMINATE;
1775                 break;
1776
1777         case (RAMROD_CMD_ID_ETH_EMPTY):
1778                 DP(BNX2X_MSG_SP, "got MULTI[%d] empty ramrod\n", cid);
1779                 drv_cmd = BNX2X_Q_CMD_EMPTY;
1780                 break;
1781
1782         default:
1783                 BNX2X_ERR("unexpected MC reply (%d) on fp[%d]\n",
1784                           command, fp->index);
1785                 return;
1786         }
1787
1788         if ((drv_cmd != BNX2X_Q_CMD_MAX) &&
1789             q_obj->complete_cmd(bp, q_obj, drv_cmd))
1790                 /* q_obj->complete_cmd() failure means that this was
1791                  * an unexpected completion.
1792                  *
1793                  * In this case we don't want to increase the bp->spq_left
1794                  * because apparently we haven't sent this command the first
1795                  * place.
1796                  */
1797 #ifdef BNX2X_STOP_ON_ERROR
1798                 bnx2x_panic();
1799 #else
1800                 return;
1801 #endif
1802         /* SRIOV: reschedule any 'in_progress' operations */
1803         bnx2x_iov_sp_event(bp, cid, true);
1804
1805         smp_mb__before_atomic_inc();
1806         atomic_inc(&bp->cq_spq_left);
1807         /* push the change in bp->spq_left and towards the memory */
1808         smp_mb__after_atomic_inc();
1809
1810         DP(BNX2X_MSG_SP, "bp->cq_spq_left %x\n", atomic_read(&bp->cq_spq_left));
1811
1812         if ((drv_cmd == BNX2X_Q_CMD_UPDATE) && (IS_FCOE_FP(fp)) &&
1813             (!!test_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state))) {
1814                 /* if Q update ramrod is completed for last Q in AFEX vif set
1815                  * flow, then ACK MCP at the end
1816                  *
1817                  * mark pending ACK to MCP bit.
1818                  * prevent case that both bits are cleared.
1819                  * At the end of load/unload driver checks that
1820                  * sp_state is cleared, and this order prevents
1821                  * races
1822                  */
1823                 smp_mb__before_clear_bit();
1824                 set_bit(BNX2X_AFEX_PENDING_VIFSET_MCP_ACK, &bp->sp_state);
1825                 wmb();
1826                 clear_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state);
1827                 smp_mb__after_clear_bit();
1828
1829                 /* schedule the sp task as mcp ack is required */
1830                 bnx2x_schedule_sp_task(bp);
1831         }
1832
1833         return;
1834 }
1835
1836 irqreturn_t bnx2x_interrupt(int irq, void *dev_instance)
1837 {
1838         struct bnx2x *bp = netdev_priv(dev_instance);
1839         u16 status = bnx2x_ack_int(bp);
1840         u16 mask;
1841         int i;
1842         u8 cos;
1843
1844         /* Return here if interrupt is shared and it's not for us */
1845         if (unlikely(status == 0)) {
1846                 DP(NETIF_MSG_INTR, "not our interrupt!\n");
1847                 return IRQ_NONE;
1848         }
1849         DP(NETIF_MSG_INTR, "got an interrupt  status 0x%x\n", status);
1850
1851 #ifdef BNX2X_STOP_ON_ERROR
1852         if (unlikely(bp->panic))
1853                 return IRQ_HANDLED;
1854 #endif
1855
1856         for_each_eth_queue(bp, i) {
1857                 struct bnx2x_fastpath *fp = &bp->fp[i];
1858
1859                 mask = 0x2 << (fp->index + CNIC_SUPPORT(bp));
1860                 if (status & mask) {
1861                         /* Handle Rx or Tx according to SB id */
1862                         prefetch(fp->rx_cons_sb);
1863                         for_each_cos_in_tx_queue(fp, cos)
1864                                 prefetch(fp->txdata_ptr[cos]->tx_cons_sb);
1865                         prefetch(&fp->sb_running_index[SM_RX_ID]);
1866                         napi_schedule(&bnx2x_fp(bp, fp->index, napi));
1867                         status &= ~mask;
1868                 }
1869         }
1870
1871         if (CNIC_SUPPORT(bp)) {
1872                 mask = 0x2;
1873                 if (status & (mask | 0x1)) {
1874                         struct cnic_ops *c_ops = NULL;
1875
1876                         rcu_read_lock();
1877                         c_ops = rcu_dereference(bp->cnic_ops);
1878                         if (c_ops && (bp->cnic_eth_dev.drv_state &
1879                                       CNIC_DRV_STATE_HANDLES_IRQ))
1880                                 c_ops->cnic_handler(bp->cnic_data, NULL);
1881                         rcu_read_unlock();
1882
1883                         status &= ~mask;
1884                 }
1885         }
1886
1887         if (unlikely(status & 0x1)) {
1888
1889                 /* schedule sp task to perform default status block work, ack
1890                  * attentions and enable interrupts.
1891                  */
1892                 bnx2x_schedule_sp_task(bp);
1893
1894                 status &= ~0x1;
1895                 if (!status)
1896                         return IRQ_HANDLED;
1897         }
1898
1899         if (unlikely(status))
1900                 DP(NETIF_MSG_INTR, "got an unknown interrupt! (status 0x%x)\n",
1901                    status);
1902
1903         return IRQ_HANDLED;
1904 }
1905
1906 /* Link */
1907
1908 /*
1909  * General service functions
1910  */
1911
1912 int bnx2x_acquire_hw_lock(struct bnx2x *bp, u32 resource)
1913 {
1914         u32 lock_status;
1915         u32 resource_bit = (1 << resource);
1916         int func = BP_FUNC(bp);
1917         u32 hw_lock_control_reg;
1918         int cnt;
1919
1920         /* Validating that the resource is within range */
1921         if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1922                 BNX2X_ERR("resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1923                    resource, HW_LOCK_MAX_RESOURCE_VALUE);
1924                 return -EINVAL;
1925         }
1926
1927         if (func <= 5) {
1928                 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1929         } else {
1930                 hw_lock_control_reg =
1931                                 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1932         }
1933
1934         /* Validating that the resource is not already taken */
1935         lock_status = REG_RD(bp, hw_lock_control_reg);
1936         if (lock_status & resource_bit) {
1937                 BNX2X_ERR("lock_status 0x%x  resource_bit 0x%x\n",
1938                    lock_status, resource_bit);
1939                 return -EEXIST;
1940         }
1941
1942         /* Try for 5 second every 5ms */
1943         for (cnt = 0; cnt < 1000; cnt++) {
1944                 /* Try to acquire the lock */
1945                 REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
1946                 lock_status = REG_RD(bp, hw_lock_control_reg);
1947                 if (lock_status & resource_bit)
1948                         return 0;
1949
1950                 msleep(5);
1951         }
1952         BNX2X_ERR("Timeout\n");
1953         return -EAGAIN;
1954 }
1955
1956 int bnx2x_release_leader_lock(struct bnx2x *bp)
1957 {
1958         return bnx2x_release_hw_lock(bp, bnx2x_get_leader_lock_resource(bp));
1959 }
1960
1961 int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource)
1962 {
1963         u32 lock_status;
1964         u32 resource_bit = (1 << resource);
1965         int func = BP_FUNC(bp);
1966         u32 hw_lock_control_reg;
1967
1968         /* Validating that the resource is within range */
1969         if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1970                 BNX2X_ERR("resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1971                    resource, HW_LOCK_MAX_RESOURCE_VALUE);
1972                 return -EINVAL;
1973         }
1974
1975         if (func <= 5) {
1976                 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1977         } else {
1978                 hw_lock_control_reg =
1979                                 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1980         }
1981
1982         /* Validating that the resource is currently taken */
1983         lock_status = REG_RD(bp, hw_lock_control_reg);
1984         if (!(lock_status & resource_bit)) {
1985                 BNX2X_ERR("lock_status 0x%x resource_bit 0x%x. unlock was called but lock wasn't taken!\n",
1986                    lock_status, resource_bit);
1987                 return -EFAULT;
1988         }
1989
1990         REG_WR(bp, hw_lock_control_reg, resource_bit);
1991         return 0;
1992 }
1993
1994
1995 int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port)
1996 {
1997         /* The GPIO should be swapped if swap register is set and active */
1998         int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
1999                          REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
2000         int gpio_shift = gpio_num +
2001                         (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
2002         u32 gpio_mask = (1 << gpio_shift);
2003         u32 gpio_reg;
2004         int value;
2005
2006         if (gpio_num > MISC_REGISTERS_GPIO_3) {
2007                 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
2008                 return -EINVAL;
2009         }
2010
2011         /* read GPIO value */
2012         gpio_reg = REG_RD(bp, MISC_REG_GPIO);
2013
2014         /* get the requested pin value */
2015         if ((gpio_reg & gpio_mask) == gpio_mask)
2016                 value = 1;
2017         else
2018                 value = 0;
2019
2020         DP(NETIF_MSG_LINK, "pin %d  value 0x%x\n", gpio_num, value);
2021
2022         return value;
2023 }
2024
2025 int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
2026 {
2027         /* The GPIO should be swapped if swap register is set and active */
2028         int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
2029                          REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
2030         int gpio_shift = gpio_num +
2031                         (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
2032         u32 gpio_mask = (1 << gpio_shift);
2033         u32 gpio_reg;
2034
2035         if (gpio_num > MISC_REGISTERS_GPIO_3) {
2036                 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
2037                 return -EINVAL;
2038         }
2039
2040         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2041         /* read GPIO and mask except the float bits */
2042         gpio_reg = (REG_RD(bp, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT);
2043
2044         switch (mode) {
2045         case MISC_REGISTERS_GPIO_OUTPUT_LOW:
2046                 DP(NETIF_MSG_LINK,
2047                    "Set GPIO %d (shift %d) -> output low\n",
2048                    gpio_num, gpio_shift);
2049                 /* clear FLOAT and set CLR */
2050                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
2051                 gpio_reg |=  (gpio_mask << MISC_REGISTERS_GPIO_CLR_POS);
2052                 break;
2053
2054         case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
2055                 DP(NETIF_MSG_LINK,
2056                    "Set GPIO %d (shift %d) -> output high\n",
2057                    gpio_num, gpio_shift);
2058                 /* clear FLOAT and set SET */
2059                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
2060                 gpio_reg |=  (gpio_mask << MISC_REGISTERS_GPIO_SET_POS);
2061                 break;
2062
2063         case MISC_REGISTERS_GPIO_INPUT_HI_Z:
2064                 DP(NETIF_MSG_LINK,
2065                    "Set GPIO %d (shift %d) -> input\n",
2066                    gpio_num, gpio_shift);
2067                 /* set FLOAT */
2068                 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
2069                 break;
2070
2071         default:
2072                 break;
2073         }
2074
2075         REG_WR(bp, MISC_REG_GPIO, gpio_reg);
2076         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2077
2078         return 0;
2079 }
2080
2081 int bnx2x_set_mult_gpio(struct bnx2x *bp, u8 pins, u32 mode)
2082 {
2083         u32 gpio_reg = 0;
2084         int rc = 0;
2085
2086         /* Any port swapping should be handled by caller. */
2087
2088         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2089         /* read GPIO and mask except the float bits */
2090         gpio_reg = REG_RD(bp, MISC_REG_GPIO);
2091         gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_FLOAT_POS);
2092         gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_CLR_POS);
2093         gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_SET_POS);
2094
2095         switch (mode) {
2096         case MISC_REGISTERS_GPIO_OUTPUT_LOW:
2097                 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output low\n", pins);
2098                 /* set CLR */
2099                 gpio_reg |= (pins << MISC_REGISTERS_GPIO_CLR_POS);
2100                 break;
2101
2102         case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
2103                 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output high\n", pins);
2104                 /* set SET */
2105                 gpio_reg |= (pins << MISC_REGISTERS_GPIO_SET_POS);
2106                 break;
2107
2108         case MISC_REGISTERS_GPIO_INPUT_HI_Z:
2109                 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> input\n", pins);
2110                 /* set FLOAT */
2111                 gpio_reg |= (pins << MISC_REGISTERS_GPIO_FLOAT_POS);
2112                 break;
2113
2114         default:
2115                 BNX2X_ERR("Invalid GPIO mode assignment %d\n", mode);
2116                 rc = -EINVAL;
2117                 break;
2118         }
2119
2120         if (rc == 0)
2121                 REG_WR(bp, MISC_REG_GPIO, gpio_reg);
2122
2123         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2124
2125         return rc;
2126 }
2127
2128 int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
2129 {
2130         /* The GPIO should be swapped if swap register is set and active */
2131         int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
2132                          REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
2133         int gpio_shift = gpio_num +
2134                         (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
2135         u32 gpio_mask = (1 << gpio_shift);
2136         u32 gpio_reg;
2137
2138         if (gpio_num > MISC_REGISTERS_GPIO_3) {
2139                 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
2140                 return -EINVAL;
2141         }
2142
2143         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2144         /* read GPIO int */
2145         gpio_reg = REG_RD(bp, MISC_REG_GPIO_INT);
2146
2147         switch (mode) {
2148         case MISC_REGISTERS_GPIO_INT_OUTPUT_CLR:
2149                 DP(NETIF_MSG_LINK,
2150                    "Clear GPIO INT %d (shift %d) -> output low\n",
2151                    gpio_num, gpio_shift);
2152                 /* clear SET and set CLR */
2153                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
2154                 gpio_reg |=  (gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
2155                 break;
2156
2157         case MISC_REGISTERS_GPIO_INT_OUTPUT_SET:
2158                 DP(NETIF_MSG_LINK,
2159                    "Set GPIO INT %d (shift %d) -> output high\n",
2160                    gpio_num, gpio_shift);
2161                 /* clear CLR and set SET */
2162                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
2163                 gpio_reg |=  (gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
2164                 break;
2165
2166         default:
2167                 break;
2168         }
2169
2170         REG_WR(bp, MISC_REG_GPIO_INT, gpio_reg);
2171         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2172
2173         return 0;
2174 }
2175
2176 static int bnx2x_set_spio(struct bnx2x *bp, int spio, u32 mode)
2177 {
2178         u32 spio_reg;
2179
2180         /* Only 2 SPIOs are configurable */
2181         if ((spio != MISC_SPIO_SPIO4) && (spio != MISC_SPIO_SPIO5)) {
2182                 BNX2X_ERR("Invalid SPIO 0x%x\n", spio);
2183                 return -EINVAL;
2184         }
2185
2186         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
2187         /* read SPIO and mask except the float bits */
2188         spio_reg = (REG_RD(bp, MISC_REG_SPIO) & MISC_SPIO_FLOAT);
2189
2190         switch (mode) {
2191         case MISC_SPIO_OUTPUT_LOW:
2192                 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> output low\n", spio);
2193                 /* clear FLOAT and set CLR */
2194                 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);
2195                 spio_reg |=  (spio << MISC_SPIO_CLR_POS);
2196                 break;
2197
2198         case MISC_SPIO_OUTPUT_HIGH:
2199                 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> output high\n", spio);
2200                 /* clear FLOAT and set SET */
2201                 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);
2202                 spio_reg |=  (spio << MISC_SPIO_SET_POS);
2203                 break;
2204
2205         case MISC_SPIO_INPUT_HI_Z:
2206                 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> input\n", spio);
2207                 /* set FLOAT */
2208                 spio_reg |= (spio << MISC_SPIO_FLOAT_POS);
2209                 break;
2210
2211         default:
2212                 break;
2213         }
2214
2215         REG_WR(bp, MISC_REG_SPIO, spio_reg);
2216         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
2217
2218         return 0;
2219 }
2220
2221 void bnx2x_calc_fc_adv(struct bnx2x *bp)
2222 {
2223         u8 cfg_idx = bnx2x_get_link_cfg_idx(bp);
2224         switch (bp->link_vars.ieee_fc &
2225                 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) {
2226         case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE:
2227                 bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
2228                                                    ADVERTISED_Pause);
2229                 break;
2230
2231         case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH:
2232                 bp->port.advertising[cfg_idx] |= (ADVERTISED_Asym_Pause |
2233                                                   ADVERTISED_Pause);
2234                 break;
2235
2236         case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC:
2237                 bp->port.advertising[cfg_idx] |= ADVERTISED_Asym_Pause;
2238                 break;
2239
2240         default:
2241                 bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
2242                                                    ADVERTISED_Pause);
2243                 break;
2244         }
2245 }
2246
2247 static void bnx2x_set_requested_fc(struct bnx2x *bp)
2248 {
2249         /* Initialize link parameters structure variables
2250          * It is recommended to turn off RX FC for jumbo frames
2251          *  for better performance
2252          */
2253         if (CHIP_IS_E1x(bp) && (bp->dev->mtu > 5000))
2254                 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_TX;
2255         else
2256                 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_BOTH;
2257 }
2258
2259 int bnx2x_initial_phy_init(struct bnx2x *bp, int load_mode)
2260 {
2261         int rc, cfx_idx = bnx2x_get_link_cfg_idx(bp);
2262         u16 req_line_speed = bp->link_params.req_line_speed[cfx_idx];
2263
2264         if (!BP_NOMCP(bp)) {
2265                 bnx2x_set_requested_fc(bp);
2266                 bnx2x_acquire_phy_lock(bp);
2267
2268                 if (load_mode == LOAD_DIAG) {
2269                         struct link_params *lp = &bp->link_params;
2270                         lp->loopback_mode = LOOPBACK_XGXS;
2271                         /* do PHY loopback at 10G speed, if possible */
2272                         if (lp->req_line_speed[cfx_idx] < SPEED_10000) {
2273                                 if (lp->speed_cap_mask[cfx_idx] &
2274                                     PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
2275                                         lp->req_line_speed[cfx_idx] =
2276                                         SPEED_10000;
2277                                 else
2278                                         lp->req_line_speed[cfx_idx] =
2279                                         SPEED_1000;
2280                         }
2281                 }
2282
2283                 if (load_mode == LOAD_LOOPBACK_EXT) {
2284                         struct link_params *lp = &bp->link_params;
2285                         lp->loopback_mode = LOOPBACK_EXT;
2286                 }
2287
2288                 rc = bnx2x_phy_init(&bp->link_params, &bp->link_vars);
2289
2290                 bnx2x_release_phy_lock(bp);
2291
2292                 bnx2x_calc_fc_adv(bp);
2293
2294                 if (bp->link_vars.link_up) {
2295                         bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2296                         bnx2x_link_report(bp);
2297                 }
2298                 queue_delayed_work(bnx2x_wq, &bp->period_task, 0);
2299                 bp->link_params.req_line_speed[cfx_idx] = req_line_speed;
2300                 return rc;
2301         }
2302         BNX2X_ERR("Bootcode is missing - can not initialize link\n");
2303         return -EINVAL;
2304 }
2305
2306 void bnx2x_link_set(struct bnx2x *bp)
2307 {
2308         if (!BP_NOMCP(bp)) {
2309                 bnx2x_acquire_phy_lock(bp);
2310                 bnx2x_phy_init(&bp->link_params, &bp->link_vars);
2311                 bnx2x_release_phy_lock(bp);
2312
2313                 bnx2x_calc_fc_adv(bp);
2314         } else
2315                 BNX2X_ERR("Bootcode is missing - can not set link\n");
2316 }
2317
2318 static void bnx2x__link_reset(struct bnx2x *bp)
2319 {
2320         if (!BP_NOMCP(bp)) {
2321                 bnx2x_acquire_phy_lock(bp);
2322                 bnx2x_lfa_reset(&bp->link_params, &bp->link_vars);
2323                 bnx2x_release_phy_lock(bp);
2324         } else
2325                 BNX2X_ERR("Bootcode is missing - can not reset link\n");
2326 }
2327
2328 void bnx2x_force_link_reset(struct bnx2x *bp)
2329 {
2330         bnx2x_acquire_phy_lock(bp);
2331         bnx2x_link_reset(&bp->link_params, &bp->link_vars, 1);
2332         bnx2x_release_phy_lock(bp);
2333 }
2334
2335 u8 bnx2x_link_test(struct bnx2x *bp, u8 is_serdes)
2336 {
2337         u8 rc = 0;
2338
2339         if (!BP_NOMCP(bp)) {
2340                 bnx2x_acquire_phy_lock(bp);
2341                 rc = bnx2x_test_link(&bp->link_params, &bp->link_vars,
2342                                      is_serdes);
2343                 bnx2x_release_phy_lock(bp);
2344         } else
2345                 BNX2X_ERR("Bootcode is missing - can not test link\n");
2346
2347         return rc;
2348 }
2349
2350
2351 /* Calculates the sum of vn_min_rates.
2352    It's needed for further normalizing of the min_rates.
2353    Returns:
2354      sum of vn_min_rates.
2355        or
2356      0 - if all the min_rates are 0.
2357      In the later case fainess algorithm should be deactivated.
2358      If not all min_rates are zero then those that are zeroes will be set to 1.
2359  */
2360 static void bnx2x_calc_vn_min(struct bnx2x *bp,
2361                                       struct cmng_init_input *input)
2362 {
2363         int all_zero = 1;
2364         int vn;
2365
2366         for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
2367                 u32 vn_cfg = bp->mf_config[vn];
2368                 u32 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
2369                                    FUNC_MF_CFG_MIN_BW_SHIFT) * 100;
2370
2371                 /* Skip hidden vns */
2372                 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE)
2373                         vn_min_rate = 0;
2374                 /* If min rate is zero - set it to 1 */
2375                 else if (!vn_min_rate)
2376                         vn_min_rate = DEF_MIN_RATE;
2377                 else
2378                         all_zero = 0;
2379
2380                 input->vnic_min_rate[vn] = vn_min_rate;
2381         }
2382
2383         /* if ETS or all min rates are zeros - disable fairness */
2384         if (BNX2X_IS_ETS_ENABLED(bp)) {
2385                 input->flags.cmng_enables &=
2386                                         ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2387                 DP(NETIF_MSG_IFUP, "Fairness will be disabled due to ETS\n");
2388         } else if (all_zero) {
2389                 input->flags.cmng_enables &=
2390                                         ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2391                 DP(NETIF_MSG_IFUP,
2392                    "All MIN values are zeroes fairness will be disabled\n");
2393         } else
2394                 input->flags.cmng_enables |=
2395                                         CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2396 }
2397
2398 static void bnx2x_calc_vn_max(struct bnx2x *bp, int vn,
2399                                     struct cmng_init_input *input)
2400 {
2401         u16 vn_max_rate;
2402         u32 vn_cfg = bp->mf_config[vn];
2403
2404         if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE)
2405                 vn_max_rate = 0;
2406         else {
2407                 u32 maxCfg = bnx2x_extract_max_cfg(bp, vn_cfg);
2408
2409                 if (IS_MF_SI(bp)) {
2410                         /* maxCfg in percents of linkspeed */
2411                         vn_max_rate = (bp->link_vars.line_speed * maxCfg) / 100;
2412                 } else /* SD modes */
2413                         /* maxCfg is absolute in 100Mb units */
2414                         vn_max_rate = maxCfg * 100;
2415         }
2416
2417         DP(NETIF_MSG_IFUP, "vn %d: vn_max_rate %d\n", vn, vn_max_rate);
2418
2419         input->vnic_max_rate[vn] = vn_max_rate;
2420 }
2421
2422
2423 static int bnx2x_get_cmng_fns_mode(struct bnx2x *bp)
2424 {
2425         if (CHIP_REV_IS_SLOW(bp))
2426                 return CMNG_FNS_NONE;
2427         if (IS_MF(bp))
2428                 return CMNG_FNS_MINMAX;
2429
2430         return CMNG_FNS_NONE;
2431 }
2432
2433 void bnx2x_read_mf_cfg(struct bnx2x *bp)
2434 {
2435         int vn, n = (CHIP_MODE_IS_4_PORT(bp) ? 2 : 1);
2436
2437         if (BP_NOMCP(bp))
2438                 return; /* what should be the default bvalue in this case */
2439
2440         /* For 2 port configuration the absolute function number formula
2441          * is:
2442          *      abs_func = 2 * vn + BP_PORT + BP_PATH
2443          *
2444          *      and there are 4 functions per port
2445          *
2446          * For 4 port configuration it is
2447          *      abs_func = 4 * vn + 2 * BP_PORT + BP_PATH
2448          *
2449          *      and there are 2 functions per port
2450          */
2451         for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
2452                 int /*abs*/func = n * (2 * vn + BP_PORT(bp)) + BP_PATH(bp);
2453
2454                 if (func >= E1H_FUNC_MAX)
2455                         break;
2456
2457                 bp->mf_config[vn] =
2458                         MF_CFG_RD(bp, func_mf_config[func].config);
2459         }
2460         if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) {
2461                 DP(NETIF_MSG_IFUP, "mf_cfg function disabled\n");
2462                 bp->flags |= MF_FUNC_DIS;
2463         } else {
2464                 DP(NETIF_MSG_IFUP, "mf_cfg function enabled\n");
2465                 bp->flags &= ~MF_FUNC_DIS;
2466         }
2467 }
2468
2469 static void bnx2x_cmng_fns_init(struct bnx2x *bp, u8 read_cfg, u8 cmng_type)
2470 {
2471         struct cmng_init_input input;
2472         memset(&input, 0, sizeof(struct cmng_init_input));
2473
2474         input.port_rate = bp->link_vars.line_speed;
2475
2476         if (cmng_type == CMNG_FNS_MINMAX) {
2477                 int vn;
2478
2479                 /* read mf conf from shmem */
2480                 if (read_cfg)
2481                         bnx2x_read_mf_cfg(bp);
2482
2483                 /* vn_weight_sum and enable fairness if not 0 */
2484                 bnx2x_calc_vn_min(bp, &input);
2485
2486                 /* calculate and set min-max rate for each vn */
2487                 if (bp->port.pmf)
2488                         for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++)
2489                                 bnx2x_calc_vn_max(bp, vn, &input);
2490
2491                 /* always enable rate shaping and fairness */
2492                 input.flags.cmng_enables |=
2493                                         CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN;
2494
2495                 bnx2x_init_cmng(&input, &bp->cmng);
2496                 return;
2497         }
2498
2499         /* rate shaping and fairness are disabled */
2500         DP(NETIF_MSG_IFUP,
2501            "rate shaping and fairness are disabled\n");
2502 }
2503
2504 static void storm_memset_cmng(struct bnx2x *bp,
2505                               struct cmng_init *cmng,
2506                               u8 port)
2507 {
2508         int vn;
2509         size_t size = sizeof(struct cmng_struct_per_port);
2510
2511         u32 addr = BAR_XSTRORM_INTMEM +
2512                         XSTORM_CMNG_PER_PORT_VARS_OFFSET(port);
2513
2514         __storm_memset_struct(bp, addr, size, (u32 *)&cmng->port);
2515
2516         for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
2517                 int func = func_by_vn(bp, vn);
2518
2519                 addr = BAR_XSTRORM_INTMEM +
2520                        XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(func);
2521                 size = sizeof(struct rate_shaping_vars_per_vn);
2522                 __storm_memset_struct(bp, addr, size,
2523                                       (u32 *)&cmng->vnic.vnic_max_rate[vn]);
2524
2525                 addr = BAR_XSTRORM_INTMEM +
2526                        XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(func);
2527                 size = sizeof(struct fairness_vars_per_vn);
2528                 __storm_memset_struct(bp, addr, size,
2529                                       (u32 *)&cmng->vnic.vnic_min_rate[vn]);
2530         }
2531 }
2532
2533 /* This function is called upon link interrupt */
2534 static void bnx2x_link_attn(struct bnx2x *bp)
2535 {
2536         /* Make sure that we are synced with the current statistics */
2537         bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2538
2539         bnx2x_link_update(&bp->link_params, &bp->link_vars);
2540
2541         if (bp->link_vars.link_up) {
2542
2543                 /* dropless flow control */
2544                 if (!CHIP_IS_E1(bp) && bp->dropless_fc) {
2545                         int port = BP_PORT(bp);
2546                         u32 pause_enabled = 0;
2547
2548                         if (bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_TX)
2549                                 pause_enabled = 1;
2550
2551                         REG_WR(bp, BAR_USTRORM_INTMEM +
2552                                USTORM_ETH_PAUSE_ENABLED_OFFSET(port),
2553                                pause_enabled);
2554                 }
2555
2556                 if (bp->link_vars.mac_type != MAC_TYPE_EMAC) {
2557                         struct host_port_stats *pstats;
2558
2559                         pstats = bnx2x_sp(bp, port_stats);
2560                         /* reset old mac stats */
2561                         memset(&(pstats->mac_stx[0]), 0,
2562                                sizeof(struct mac_stx));
2563                 }
2564                 if (bp->state == BNX2X_STATE_OPEN)
2565                         bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2566         }
2567
2568         if (bp->link_vars.link_up && bp->link_vars.line_speed) {
2569                 int cmng_fns = bnx2x_get_cmng_fns_mode(bp);
2570
2571                 if (cmng_fns != CMNG_FNS_NONE) {
2572                         bnx2x_cmng_fns_init(bp, false, cmng_fns);
2573                         storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
2574                 } else
2575                         /* rate shaping and fairness are disabled */
2576                         DP(NETIF_MSG_IFUP,
2577                            "single function mode without fairness\n");
2578         }
2579
2580         __bnx2x_link_report(bp);
2581
2582         if (IS_MF(bp))
2583                 bnx2x_link_sync_notify(bp);
2584 }
2585
2586 void bnx2x__link_status_update(struct bnx2x *bp)
2587 {
2588         if (bp->state != BNX2X_STATE_OPEN)
2589                 return;
2590
2591         /* read updated dcb configuration */
2592         if (IS_PF(bp)) {
2593                 bnx2x_dcbx_pmf_update(bp);
2594                 bnx2x_link_status_update(&bp->link_params, &bp->link_vars);
2595                 if (bp->link_vars.link_up)
2596                         bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2597                 else
2598                         bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2599                         /* indicate link status */
2600                 bnx2x_link_report(bp);
2601
2602         } else { /* VF */
2603                 bp->port.supported[0] |= (SUPPORTED_10baseT_Half |
2604                                           SUPPORTED_10baseT_Full |
2605                                           SUPPORTED_100baseT_Half |
2606                                           SUPPORTED_100baseT_Full |
2607                                           SUPPORTED_1000baseT_Full |
2608                                           SUPPORTED_2500baseX_Full |
2609                                           SUPPORTED_10000baseT_Full |
2610                                           SUPPORTED_TP |
2611                                           SUPPORTED_FIBRE |
2612                                           SUPPORTED_Autoneg |
2613                                           SUPPORTED_Pause |
2614                                           SUPPORTED_Asym_Pause);
2615                 bp->port.advertising[0] = bp->port.supported[0];
2616
2617                 bp->link_params.bp = bp;
2618                 bp->link_params.port = BP_PORT(bp);
2619                 bp->link_params.req_duplex[0] = DUPLEX_FULL;
2620                 bp->link_params.req_flow_ctrl[0] = BNX2X_FLOW_CTRL_NONE;
2621                 bp->link_params.req_line_speed[0] = SPEED_10000;
2622                 bp->link_params.speed_cap_mask[0] = 0x7f0000;
2623                 bp->link_params.switch_cfg = SWITCH_CFG_10G;
2624                 bp->link_vars.mac_type = MAC_TYPE_BMAC;
2625                 bp->link_vars.line_speed = SPEED_10000;
2626                 bp->link_vars.link_status =
2627                         (LINK_STATUS_LINK_UP |
2628                          LINK_STATUS_SPEED_AND_DUPLEX_10GTFD);
2629                 bp->link_vars.link_up = 1;
2630                 bp->link_vars.duplex = DUPLEX_FULL;
2631                 bp->link_vars.flow_ctrl = BNX2X_FLOW_CTRL_NONE;
2632                 __bnx2x_link_report(bp);
2633                 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2634         }
2635 }
2636
2637 static int bnx2x_afex_func_update(struct bnx2x *bp, u16 vifid,
2638                                   u16 vlan_val, u8 allowed_prio)
2639 {
2640         struct bnx2x_func_state_params func_params = {NULL};
2641         struct bnx2x_func_afex_update_params *f_update_params =
2642                 &func_params.params.afex_update;
2643
2644         func_params.f_obj = &bp->func_obj;
2645         func_params.cmd = BNX2X_F_CMD_AFEX_UPDATE;
2646
2647         /* no need to wait for RAMROD completion, so don't
2648          * set RAMROD_COMP_WAIT flag
2649          */
2650
2651         f_update_params->vif_id = vifid;
2652         f_update_params->afex_default_vlan = vlan_val;
2653         f_update_params->allowed_priorities = allowed_prio;
2654
2655         /* if ramrod can not be sent, response to MCP immediately */
2656         if (bnx2x_func_state_change(bp, &func_params) < 0)
2657                 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
2658
2659         return 0;
2660 }
2661
2662 static int bnx2x_afex_handle_vif_list_cmd(struct bnx2x *bp, u8 cmd_type,
2663                                           u16 vif_index, u8 func_bit_map)
2664 {
2665         struct bnx2x_func_state_params func_params = {NULL};
2666         struct bnx2x_func_afex_viflists_params *update_params =
2667                 &func_params.params.afex_viflists;
2668         int rc;
2669         u32 drv_msg_code;
2670
2671         /* validate only LIST_SET and LIST_GET are received from switch */
2672         if ((cmd_type != VIF_LIST_RULE_GET) && (cmd_type != VIF_LIST_RULE_SET))
2673                 BNX2X_ERR("BUG! afex_handle_vif_list_cmd invalid type 0x%x\n",
2674                           cmd_type);
2675
2676         func_params.f_obj = &bp->func_obj;
2677         func_params.cmd = BNX2X_F_CMD_AFEX_VIFLISTS;
2678
2679         /* set parameters according to cmd_type */
2680         update_params->afex_vif_list_command = cmd_type;
2681         update_params->vif_list_index = vif_index;
2682         update_params->func_bit_map =
2683                 (cmd_type == VIF_LIST_RULE_GET) ? 0 : func_bit_map;
2684         update_params->func_to_clear = 0;
2685         drv_msg_code =
2686                 (cmd_type == VIF_LIST_RULE_GET) ?
2687                 DRV_MSG_CODE_AFEX_LISTGET_ACK :
2688                 DRV_MSG_CODE_AFEX_LISTSET_ACK;
2689
2690         /* if ramrod can not be sent, respond to MCP immediately for
2691          * SET and GET requests (other are not triggered from MCP)
2692          */
2693         rc = bnx2x_func_state_change(bp, &func_params);
2694         if (rc < 0)
2695                 bnx2x_fw_command(bp, drv_msg_code, 0);
2696
2697         return 0;
2698 }
2699
2700 static void bnx2x_handle_afex_cmd(struct bnx2x *bp, u32 cmd)
2701 {
2702         struct afex_stats afex_stats;
2703         u32 func = BP_ABS_FUNC(bp);
2704         u32 mf_config;
2705         u16 vlan_val;
2706         u32 vlan_prio;
2707         u16 vif_id;
2708         u8 allowed_prio;
2709         u8 vlan_mode;
2710         u32 addr_to_write, vifid, addrs, stats_type, i;
2711
2712         if (cmd & DRV_STATUS_AFEX_LISTGET_REQ) {
2713                 vifid = SHMEM2_RD(bp, afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
2714                 DP(BNX2X_MSG_MCP,
2715                    "afex: got MCP req LISTGET_REQ for vifid 0x%x\n", vifid);
2716                 bnx2x_afex_handle_vif_list_cmd(bp, VIF_LIST_RULE_GET, vifid, 0);
2717         }
2718
2719         if (cmd & DRV_STATUS_AFEX_LISTSET_REQ) {
2720                 vifid = SHMEM2_RD(bp, afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
2721                 addrs = SHMEM2_RD(bp, afex_param2_to_driver[BP_FW_MB_IDX(bp)]);
2722                 DP(BNX2X_MSG_MCP,
2723                    "afex: got MCP req LISTSET_REQ for vifid 0x%x addrs 0x%x\n",
2724                    vifid, addrs);
2725                 bnx2x_afex_handle_vif_list_cmd(bp, VIF_LIST_RULE_SET, vifid,
2726                                                addrs);
2727         }
2728
2729         if (cmd & DRV_STATUS_AFEX_STATSGET_REQ) {
2730                 addr_to_write = SHMEM2_RD(bp,
2731                         afex_scratchpad_addr_to_write[BP_FW_MB_IDX(bp)]);
2732                 stats_type = SHMEM2_RD(bp,
2733                         afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
2734
2735                 DP(BNX2X_MSG_MCP,
2736                    "afex: got MCP req STATSGET_REQ, write to addr 0x%x\n",
2737                    addr_to_write);
2738
2739                 bnx2x_afex_collect_stats(bp, (void *)&afex_stats, stats_type);
2740
2741                 /* write response to scratchpad, for MCP */
2742                 for (i = 0; i < (sizeof(struct afex_stats)/sizeof(u32)); i++)
2743                         REG_WR(bp, addr_to_write + i*sizeof(u32),
2744                                *(((u32 *)(&afex_stats))+i));
2745
2746                 /* send ack message to MCP */
2747                 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_STATSGET_ACK, 0);
2748         }
2749
2750         if (cmd & DRV_STATUS_AFEX_VIFSET_REQ) {
2751                 mf_config = MF_CFG_RD(bp, func_mf_config[func].config);
2752                 bp->mf_config[BP_VN(bp)] = mf_config;
2753                 DP(BNX2X_MSG_MCP,
2754                    "afex: got MCP req VIFSET_REQ, mf_config 0x%x\n",
2755                    mf_config);
2756
2757                 /* if VIF_SET is "enabled" */
2758                 if (!(mf_config & FUNC_MF_CFG_FUNC_DISABLED)) {
2759                         /* set rate limit directly to internal RAM */
2760                         struct cmng_init_input cmng_input;
2761                         struct rate_shaping_vars_per_vn m_rs_vn;
2762                         size_t size = sizeof(struct rate_shaping_vars_per_vn);
2763                         u32 addr = BAR_XSTRORM_INTMEM +
2764                             XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(BP_FUNC(bp));
2765
2766                         bp->mf_config[BP_VN(bp)] = mf_config;
2767
2768                         bnx2x_calc_vn_max(bp, BP_VN(bp), &cmng_input);
2769                         m_rs_vn.vn_counter.rate =
2770                                 cmng_input.vnic_max_rate[BP_VN(bp)];
2771                         m_rs_vn.vn_counter.quota =
2772                                 (m_rs_vn.vn_counter.rate *
2773                                  RS_PERIODIC_TIMEOUT_USEC) / 8;
2774
2775                         __storm_memset_struct(bp, addr, size, (u32 *)&m_rs_vn);
2776
2777                         /* read relevant values from mf_cfg struct in shmem */
2778                         vif_id =
2779                                 (MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
2780                                  FUNC_MF_CFG_E1HOV_TAG_MASK) >>
2781                                 FUNC_MF_CFG_E1HOV_TAG_SHIFT;
2782                         vlan_val =
2783                                 (MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
2784                                  FUNC_MF_CFG_AFEX_VLAN_MASK) >>
2785                                 FUNC_MF_CFG_AFEX_VLAN_SHIFT;
2786                         vlan_prio = (mf_config &
2787                                      FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK) >>
2788                                     FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT;
2789                         vlan_val |= (vlan_prio << VLAN_PRIO_SHIFT);
2790                         vlan_mode =
2791                                 (MF_CFG_RD(bp,
2792                                            func_mf_config[func].afex_config) &
2793                                  FUNC_MF_CFG_AFEX_VLAN_MODE_MASK) >>
2794                                 FUNC_MF_CFG_AFEX_VLAN_MODE_SHIFT;
2795                         allowed_prio =
2796                                 (MF_CFG_RD(bp,
2797                                            func_mf_config[func].afex_config) &
2798                                  FUNC_MF_CFG_AFEX_COS_FILTER_MASK) >>
2799                                 FUNC_MF_CFG_AFEX_COS_FILTER_SHIFT;
2800
2801                         /* send ramrod to FW, return in case of failure */
2802                         if (bnx2x_afex_func_update(bp, vif_id, vlan_val,
2803                                                    allowed_prio))
2804                                 return;
2805
2806                         bp->afex_def_vlan_tag = vlan_val;
2807                         bp->afex_vlan_mode = vlan_mode;
2808                 } else {
2809                         /* notify link down because BP->flags is disabled */
2810                         bnx2x_link_report(bp);
2811
2812                         /* send INVALID VIF ramrod to FW */
2813                         bnx2x_afex_func_update(bp, 0xFFFF, 0, 0);
2814
2815                         /* Reset the default afex VLAN */
2816                         bp->afex_def_vlan_tag = -1;
2817                 }
2818         }
2819 }
2820
2821 static void bnx2x_pmf_update(struct bnx2x *bp)
2822 {
2823         int port = BP_PORT(bp);
2824         u32 val;
2825
2826         bp->port.pmf = 1;
2827         DP(BNX2X_MSG_MCP, "pmf %d\n", bp->port.pmf);
2828
2829         /*
2830          * We need the mb() to ensure the ordering between the writing to
2831          * bp->port.pmf here and reading it from the bnx2x_periodic_task().
2832          */
2833         smp_mb();
2834
2835         /* queue a periodic task */
2836         queue_delayed_work(bnx2x_wq, &bp->period_task, 0);
2837
2838         bnx2x_dcbx_pmf_update(bp);
2839
2840         /* enable nig attention */
2841         val = (0xff0f | (1 << (BP_VN(bp) + 4)));
2842         if (bp->common.int_block == INT_BLOCK_HC) {
2843                 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
2844                 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
2845         } else if (!CHIP_IS_E1x(bp)) {
2846                 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
2847                 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
2848         }
2849
2850         bnx2x_stats_handle(bp, STATS_EVENT_PMF);
2851 }
2852
2853 /* end of Link */
2854
2855 /* slow path */
2856
2857 /*
2858  * General service functions
2859  */
2860
2861 /* send the MCP a request, block until there is a reply */
2862 u32 bnx2x_fw_command(struct bnx2x *bp, u32 command, u32 param)
2863 {
2864         int mb_idx = BP_FW_MB_IDX(bp);
2865         u32 seq;
2866         u32 rc = 0;
2867         u32 cnt = 1;
2868         u8 delay = CHIP_REV_IS_SLOW(bp) ? 100 : 10;
2869
2870         mutex_lock(&bp->fw_mb_mutex);
2871         seq = ++bp->fw_seq;
2872         SHMEM_WR(bp, func_mb[mb_idx].drv_mb_param, param);
2873         SHMEM_WR(bp, func_mb[mb_idx].drv_mb_header, (command | seq));
2874
2875         DP(BNX2X_MSG_MCP, "wrote command (%x) to FW MB param 0x%08x\n",
2876                         (command | seq), param);
2877
2878         do {
2879                 /* let the FW do it's magic ... */
2880                 msleep(delay);
2881
2882                 rc = SHMEM_RD(bp, func_mb[mb_idx].fw_mb_header);
2883
2884                 /* Give the FW up to 5 second (500*10ms) */
2885         } while ((seq != (rc & FW_MSG_SEQ_NUMBER_MASK)) && (cnt++ < 500));
2886
2887         DP(BNX2X_MSG_MCP, "[after %d ms] read (%x) seq is (%x) from FW MB\n",
2888            cnt*delay, rc, seq);
2889
2890         /* is this a reply to our command? */
2891         if (seq == (rc & FW_MSG_SEQ_NUMBER_MASK))
2892                 rc &= FW_MSG_CODE_MASK;
2893         else {
2894                 /* FW BUG! */
2895                 BNX2X_ERR("FW failed to respond!\n");
2896                 bnx2x_fw_dump(bp);
2897                 rc = 0;
2898         }
2899         mutex_unlock(&bp->fw_mb_mutex);
2900
2901         return rc;
2902 }
2903
2904
2905 static void storm_memset_func_cfg(struct bnx2x *bp,
2906                                  struct tstorm_eth_function_common_config *tcfg,
2907                                  u16 abs_fid)
2908 {
2909         size_t size = sizeof(struct tstorm_eth_function_common_config);
2910
2911         u32 addr = BAR_TSTRORM_INTMEM +
2912                         TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(abs_fid);
2913
2914         __storm_memset_struct(bp, addr, size, (u32 *)tcfg);
2915 }
2916
2917 void bnx2x_func_init(struct bnx2x *bp, struct bnx2x_func_init_params *p)
2918 {
2919         if (CHIP_IS_E1x(bp)) {
2920                 struct tstorm_eth_function_common_config tcfg = {0};
2921
2922                 storm_memset_func_cfg(bp, &tcfg, p->func_id);
2923         }
2924
2925         /* Enable the function in the FW */
2926         storm_memset_vf_to_pf(bp, p->func_id, p->pf_id);
2927         storm_memset_func_en(bp, p->func_id, 1);
2928
2929         /* spq */
2930         if (p->func_flgs & FUNC_FLG_SPQ) {
2931                 storm_memset_spq_addr(bp, p->spq_map, p->func_id);
2932                 REG_WR(bp, XSEM_REG_FAST_MEMORY +
2933                        XSTORM_SPQ_PROD_OFFSET(p->func_id), p->spq_prod);
2934         }
2935 }
2936
2937 /**
2938  * bnx2x_get_tx_only_flags - Return common flags
2939  *
2940  * @bp          device handle
2941  * @fp          queue handle
2942  * @zero_stats  TRUE if statistics zeroing is needed
2943  *
2944  * Return the flags that are common for the Tx-only and not normal connections.
2945  */
2946 static unsigned long bnx2x_get_common_flags(struct bnx2x *bp,
2947                                             struct bnx2x_fastpath *fp,
2948                                             bool zero_stats)
2949 {
2950         unsigned long flags = 0;
2951
2952         /* PF driver will always initialize the Queue to an ACTIVE state */
2953         __set_bit(BNX2X_Q_FLG_ACTIVE, &flags);
2954
2955         /* tx only connections collect statistics (on the same index as the
2956          * parent connection). The statistics are zeroed when the parent
2957          * connection is initialized.
2958          */
2959
2960         __set_bit(BNX2X_Q_FLG_STATS, &flags);
2961         if (zero_stats)
2962                 __set_bit(BNX2X_Q_FLG_ZERO_STATS, &flags);
2963
2964         __set_bit(BNX2X_Q_FLG_PCSUM_ON_PKT, &flags);
2965
2966 #ifdef BNX2X_STOP_ON_ERROR
2967         __set_bit(BNX2X_Q_FLG_TX_SEC, &flags);
2968 #endif
2969
2970         return flags;
2971 }
2972
2973 static unsigned long bnx2x_get_q_flags(struct bnx2x *bp,
2974                                        struct bnx2x_fastpath *fp,
2975                                        bool leading)
2976 {
2977         unsigned long flags = 0;
2978
2979         /* calculate other queue flags */
2980         if (IS_MF_SD(bp))
2981                 __set_bit(BNX2X_Q_FLG_OV, &flags);
2982
2983         if (IS_FCOE_FP(fp)) {
2984                 __set_bit(BNX2X_Q_FLG_FCOE, &flags);
2985                 /* For FCoE - force usage of default priority (for afex) */
2986                 __set_bit(BNX2X_Q_FLG_FORCE_DEFAULT_PRI, &flags);
2987         }
2988
2989         if (!fp->disable_tpa) {
2990                 __set_bit(BNX2X_Q_FLG_TPA, &flags);
2991                 __set_bit(BNX2X_Q_FLG_TPA_IPV6, &flags);
2992                 if (fp->mode == TPA_MODE_GRO)
2993                         __set_bit(BNX2X_Q_FLG_TPA_GRO, &flags);
2994         }
2995
2996         if (leading) {
2997                 __set_bit(BNX2X_Q_FLG_LEADING_RSS, &flags);
2998                 __set_bit(BNX2X_Q_FLG_MCAST, &flags);
2999         }
3000
3001         /* Always set HW VLAN stripping */
3002         __set_bit(BNX2X_Q_FLG_VLAN, &flags);
3003
3004         /* configure silent vlan removal */
3005         if (IS_MF_AFEX(bp))
3006                 __set_bit(BNX2X_Q_FLG_SILENT_VLAN_REM, &flags);
3007
3008
3009         return flags | bnx2x_get_common_flags(bp, fp, true);
3010 }
3011
3012 static void bnx2x_pf_q_prep_general(struct bnx2x *bp,
3013         struct bnx2x_fastpath *fp, struct bnx2x_general_setup_params *gen_init,
3014         u8 cos)
3015 {
3016         gen_init->stat_id = bnx2x_stats_id(fp);
3017         gen_init->spcl_id = fp->cl_id;
3018
3019         /* Always use mini-jumbo MTU for FCoE L2 ring */
3020         if (IS_FCOE_FP(fp))
3021                 gen_init->mtu = BNX2X_FCOE_MINI_JUMBO_MTU;
3022         else
3023                 gen_init->mtu = bp->dev->mtu;
3024
3025         gen_init->cos = cos;
3026 }
3027
3028 static void bnx2x_pf_rx_q_prep(struct bnx2x *bp,
3029         struct bnx2x_fastpath *fp, struct rxq_pause_params *pause,
3030         struct bnx2x_rxq_setup_params *rxq_init)
3031 {
3032         u8 max_sge = 0;
3033         u16 sge_sz = 0;
3034         u16 tpa_agg_size = 0;
3035
3036         if (!fp->disable_tpa) {
3037                 pause->sge_th_lo = SGE_TH_LO(bp);
3038                 pause->sge_th_hi = SGE_TH_HI(bp);
3039
3040                 /* validate SGE ring has enough to cross high threshold */
3041                 WARN_ON(bp->dropless_fc &&
3042                                 pause->sge_th_hi + FW_PREFETCH_CNT >
3043                                 MAX_RX_SGE_CNT * NUM_RX_SGE_PAGES);
3044
3045                 tpa_agg_size = TPA_AGG_SIZE;
3046                 max_sge = SGE_PAGE_ALIGN(bp->dev->mtu) >>
3047                         SGE_PAGE_SHIFT;
3048                 max_sge = ((max_sge + PAGES_PER_SGE - 1) &
3049                           (~(PAGES_PER_SGE-1))) >> PAGES_PER_SGE_SHIFT;
3050                 sge_sz = (u16)min_t(u32, SGE_PAGES, 0xffff);
3051         }
3052
3053         /* pause - not for e1 */
3054         if (!CHIP_IS_E1(bp)) {
3055                 pause->bd_th_lo = BD_TH_LO(bp);
3056                 pause->bd_th_hi = BD_TH_HI(bp);
3057
3058                 pause->rcq_th_lo = RCQ_TH_LO(bp);
3059                 pause->rcq_th_hi = RCQ_TH_HI(bp);
3060                 /*
3061                  * validate that rings have enough entries to cross
3062                  * high thresholds
3063                  */
3064                 WARN_ON(bp->dropless_fc &&
3065                                 pause->bd_th_hi + FW_PREFETCH_CNT >
3066                                 bp->rx_ring_size);
3067                 WARN_ON(bp->dropless_fc &&
3068                                 pause->rcq_th_hi + FW_PREFETCH_CNT >
3069                                 NUM_RCQ_RINGS * MAX_RCQ_DESC_CNT);
3070
3071                 pause->pri_map = 1;
3072         }
3073
3074         /* rxq setup */
3075         rxq_init->dscr_map = fp->rx_desc_mapping;
3076         rxq_init->sge_map = fp->rx_sge_mapping;
3077         rxq_init->rcq_map = fp->rx_comp_mapping;
3078         rxq_init->rcq_np_map = fp->rx_comp_mapping + BCM_PAGE_SIZE;
3079
3080         /* This should be a maximum number of data bytes that may be
3081          * placed on the BD (not including paddings).
3082          */
3083         rxq_init->buf_sz = fp->rx_buf_size - BNX2X_FW_RX_ALIGN_START -
3084                 BNX2X_FW_RX_ALIGN_END - IP_HEADER_ALIGNMENT_PADDING;
3085
3086         rxq_init->cl_qzone_id = fp->cl_qzone_id;
3087         rxq_init->tpa_agg_sz = tpa_agg_size;
3088         rxq_init->sge_buf_sz = sge_sz;
3089         rxq_init->max_sges_pkt = max_sge;
3090         rxq_init->rss_engine_id = BP_FUNC(bp);
3091         rxq_init->mcast_engine_id = BP_FUNC(bp);
3092
3093         /* Maximum number or simultaneous TPA aggregation for this Queue.
3094          *
3095          * For PF Clients it should be the maximum available number.
3096          * VF driver(s) may want to define it to a smaller value.
3097          */
3098         rxq_init->max_tpa_queues = MAX_AGG_QS(bp);
3099
3100         rxq_init->cache_line_log = BNX2X_RX_ALIGN_SHIFT;
3101         rxq_init->fw_sb_id = fp->fw_sb_id;
3102
3103         if (IS_FCOE_FP(fp))
3104                 rxq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS;
3105         else
3106                 rxq_init->sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
3107         /* configure silent vlan removal
3108          * if multi function mode is afex, then mask default vlan
3109          */
3110         if (IS_MF_AFEX(bp)) {
3111                 rxq_init->silent_removal_value = bp->afex_def_vlan_tag;
3112                 rxq_init->silent_removal_mask = VLAN_VID_MASK;
3113         }
3114 }
3115
3116 static void bnx2x_pf_tx_q_prep(struct bnx2x *bp,
3117         struct bnx2x_fastpath *fp, struct bnx2x_txq_setup_params *txq_init,
3118         u8 cos)
3119 {
3120         txq_init->dscr_map = fp->txdata_ptr[cos]->tx_desc_mapping;
3121         txq_init->sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS + cos;
3122         txq_init->traffic_type = LLFC_TRAFFIC_TYPE_NW;
3123         txq_init->fw_sb_id = fp->fw_sb_id;
3124
3125         /*
3126          * set the tss leading client id for TX classfication ==
3127          * leading RSS client id
3128          */
3129         txq_init->tss_leading_cl_id = bnx2x_fp(bp, 0, cl_id);
3130
3131         if (IS_FCOE_FP(fp)) {
3132                 txq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS;
3133                 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_FCOE;
3134         }
3135 }
3136
3137 static void bnx2x_pf_init(struct bnx2x *bp)
3138 {
3139         struct bnx2x_func_init_params func_init = {0};
3140         struct event_ring_data eq_data = { {0} };
3141         u16 flags;
3142
3143         if (!CHIP_IS_E1x(bp)) {
3144                 /* reset IGU PF statistics: MSIX + ATTN */
3145                 /* PF */
3146                 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
3147                            BNX2X_IGU_STAS_MSG_VF_CNT*4 +
3148                            (CHIP_MODE_IS_4_PORT(bp) ?
3149                                 BP_FUNC(bp) : BP_VN(bp))*4, 0);
3150                 /* ATTN */
3151                 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
3152                            BNX2X_IGU_STAS_MSG_VF_CNT*4 +
3153                            BNX2X_IGU_STAS_MSG_PF_CNT*4 +
3154                            (CHIP_MODE_IS_4_PORT(bp) ?
3155                                 BP_FUNC(bp) : BP_VN(bp))*4, 0);
3156         }
3157
3158         /* function setup flags */
3159         flags = (FUNC_FLG_STATS | FUNC_FLG_LEADING | FUNC_FLG_SPQ);
3160
3161         /* This flag is relevant for E1x only.
3162          * E2 doesn't have a TPA configuration in a function level.
3163          */
3164         flags |= (bp->flags & TPA_ENABLE_FLAG) ? FUNC_FLG_TPA : 0;
3165
3166         func_init.func_flgs = flags;
3167         func_init.pf_id = BP_FUNC(bp);
3168         func_init.func_id = BP_FUNC(bp);
3169         func_init.spq_map = bp->spq_mapping;
3170         func_init.spq_prod = bp->spq_prod_idx;
3171
3172         bnx2x_func_init(bp, &func_init);
3173
3174         memset(&(bp->cmng), 0, sizeof(struct cmng_struct_per_port));
3175
3176         /*
3177          * Congestion management values depend on the link rate
3178          * There is no active link so initial link rate is set to 10 Gbps.
3179          * When the link comes up The congestion management values are
3180          * re-calculated according to the actual link rate.
3181          */
3182         bp->link_vars.line_speed = SPEED_10000;
3183         bnx2x_cmng_fns_init(bp, true, bnx2x_get_cmng_fns_mode(bp));
3184
3185         /* Only the PMF sets the HW */
3186         if (bp->port.pmf)
3187                 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
3188
3189         /* init Event Queue - PCI bus guarantees correct endianity*/
3190         eq_data.base_addr.hi = U64_HI(bp->eq_mapping);
3191         eq_data.base_addr.lo = U64_LO(bp->eq_mapping);
3192         eq_data.producer = bp->eq_prod;
3193         eq_data.index_id = HC_SP_INDEX_EQ_CONS;
3194         eq_data.sb_id = DEF_SB_ID;
3195         storm_memset_eq_data(bp, &eq_data, BP_FUNC(bp));
3196 }
3197
3198
3199 static void bnx2x_e1h_disable(struct bnx2x *bp)
3200 {
3201         int port = BP_PORT(bp);
3202
3203         bnx2x_tx_disable(bp);
3204
3205         REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
3206 }
3207
3208 static void bnx2x_e1h_enable(struct bnx2x *bp)
3209 {
3210         int port = BP_PORT(bp);
3211
3212         REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1);
3213
3214         /* Tx queue should be only reenabled */
3215         netif_tx_wake_all_queues(bp->dev);
3216
3217         /*
3218          * Should not call netif_carrier_on since it will be called if the link
3219          * is up when checking for link state
3220          */
3221 }
3222
3223 #define DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED 3
3224
3225 static void bnx2x_drv_info_ether_stat(struct bnx2x *bp)
3226 {
3227         struct eth_stats_info *ether_stat =
3228                 &bp->slowpath->drv_info_to_mcp.ether_stat;
3229         struct bnx2x_vlan_mac_obj *mac_obj =
3230                 &bp->sp_objs->mac_obj;
3231         int i;
3232
3233         strlcpy(ether_stat->version, DRV_MODULE_VERSION,
3234                 ETH_STAT_INFO_VERSION_LEN);
3235
3236         /* get DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED macs, placing them in the
3237          * mac_local field in ether_stat struct. The base address is offset by 2
3238          * bytes to account for the field being 8 bytes but a mac address is
3239          * only 6 bytes. Likewise, the stride for the get_n_elements function is
3240          * 2 bytes to compensate from the 6 bytes of a mac to the 8 bytes
3241          * allocated by the ether_stat struct, so the macs will land in their
3242          * proper positions.
3243          */
3244         for (i = 0; i < DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED; i++)
3245                 memset(ether_stat->mac_local + i, 0,
3246                        sizeof(ether_stat->mac_local[0]));
3247         mac_obj->get_n_elements(bp, &bp->sp_objs[0].mac_obj,
3248                                 DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED,
3249                                 ether_stat->mac_local + MAC_PAD, MAC_PAD,
3250                                 ETH_ALEN);
3251         ether_stat->mtu_size = bp->dev->mtu;
3252         if (bp->dev->features & NETIF_F_RXCSUM)
3253                 ether_stat->feature_flags |= FEATURE_ETH_CHKSUM_OFFLOAD_MASK;
3254         if (bp->dev->features & NETIF_F_TSO)
3255                 ether_stat->feature_flags |= FEATURE_ETH_LSO_MASK;
3256         ether_stat->feature_flags |= bp->common.boot_mode;
3257
3258         ether_stat->promiscuous_mode = (bp->dev->flags & IFF_PROMISC) ? 1 : 0;
3259
3260         ether_stat->txq_size = bp->tx_ring_size;
3261         ether_stat->rxq_size = bp->rx_ring_size;
3262 }
3263
3264 static void bnx2x_drv_info_fcoe_stat(struct bnx2x *bp)
3265 {
3266         struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app;
3267         struct fcoe_stats_info *fcoe_stat =
3268                 &bp->slowpath->drv_info_to_mcp.fcoe_stat;
3269
3270         if (!CNIC_LOADED(bp))
3271                 return;
3272
3273         memcpy(fcoe_stat->mac_local + MAC_PAD, bp->fip_mac, ETH_ALEN);
3274
3275         fcoe_stat->qos_priority =
3276                 app->traffic_type_priority[LLFC_TRAFFIC_TYPE_FCOE];
3277
3278         /* insert FCoE stats from ramrod response */
3279         if (!NO_FCOE(bp)) {
3280                 struct tstorm_per_queue_stats *fcoe_q_tstorm_stats =
3281                         &bp->fw_stats_data->queue_stats[FCOE_IDX(bp)].
3282                         tstorm_queue_statistics;
3283
3284                 struct xstorm_per_queue_stats *fcoe_q_xstorm_stats =
3285                         &bp->fw_stats_data->queue_stats[FCOE_IDX(bp)].
3286                         xstorm_queue_statistics;
3287
3288                 struct fcoe_statistics_params *fw_fcoe_stat =
3289                         &bp->fw_stats_data->fcoe;
3290
3291                 ADD_64_LE(fcoe_stat->rx_bytes_hi, LE32_0,
3292                           fcoe_stat->rx_bytes_lo,
3293                           fw_fcoe_stat->rx_stat0.fcoe_rx_byte_cnt);
3294
3295                 ADD_64_LE(fcoe_stat->rx_bytes_hi,
3296                           fcoe_q_tstorm_stats->rcv_ucast_bytes.hi,
3297                           fcoe_stat->rx_bytes_lo,
3298                           fcoe_q_tstorm_stats->rcv_ucast_bytes.lo);
3299
3300                 ADD_64_LE(fcoe_stat->rx_bytes_hi,
3301                           fcoe_q_tstorm_stats->rcv_bcast_bytes.hi,
3302                           fcoe_stat->rx_bytes_lo,
3303                           fcoe_q_tstorm_stats->rcv_bcast_bytes.lo);
3304
3305                 ADD_64_LE(fcoe_stat->rx_bytes_hi,
3306                           fcoe_q_tstorm_stats->rcv_mcast_bytes.hi,
3307                           fcoe_stat->rx_bytes_lo,
3308                           fcoe_q_tstorm_stats->rcv_mcast_bytes.lo);
3309
3310                 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3311                           fcoe_stat->rx_frames_lo,
3312                           fw_fcoe_stat->rx_stat0.fcoe_rx_pkt_cnt);
3313
3314                 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3315                           fcoe_stat->rx_frames_lo,
3316                           fcoe_q_tstorm_stats->rcv_ucast_pkts);
3317
3318                 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3319                           fcoe_stat->rx_frames_lo,
3320                           fcoe_q_tstorm_stats->rcv_bcast_pkts);
3321
3322                 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3323                           fcoe_stat->rx_frames_lo,
3324                           fcoe_q_tstorm_stats->rcv_mcast_pkts);
3325
3326                 ADD_64_LE(fcoe_stat->tx_bytes_hi, LE32_0,
3327                           fcoe_stat->tx_bytes_lo,
3328                           fw_fcoe_stat->tx_stat.fcoe_tx_byte_cnt);
3329
3330                 ADD_64_LE(fcoe_stat->tx_bytes_hi,
3331                           fcoe_q_xstorm_stats->ucast_bytes_sent.hi,
3332                           fcoe_stat->tx_bytes_lo,
3333                           fcoe_q_xstorm_stats->ucast_bytes_sent.lo);
3334
3335                 ADD_64_LE(fcoe_stat->tx_bytes_hi,
3336                           fcoe_q_xstorm_stats->bcast_bytes_sent.hi,
3337                           fcoe_stat->tx_bytes_lo,
3338                           fcoe_q_xstorm_stats->bcast_bytes_sent.lo);
3339
3340                 ADD_64_LE(fcoe_stat->tx_bytes_hi,
3341                           fcoe_q_xstorm_stats->mcast_bytes_sent.hi,
3342                           fcoe_stat->tx_bytes_lo,
3343                           fcoe_q_xstorm_stats->mcast_bytes_sent.lo);
3344
3345                 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3346                           fcoe_stat->tx_frames_lo,
3347                           fw_fcoe_stat->tx_stat.fcoe_tx_pkt_cnt);
3348
3349                 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3350                           fcoe_stat->tx_frames_lo,
3351                           fcoe_q_xstorm_stats->ucast_pkts_sent);
3352
3353                 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3354                           fcoe_stat->tx_frames_lo,
3355                           fcoe_q_xstorm_stats->bcast_pkts_sent);
3356
3357                 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3358                           fcoe_stat->tx_frames_lo,
3359                           fcoe_q_xstorm_stats->mcast_pkts_sent);
3360         }
3361
3362         /* ask L5 driver to add data to the struct */
3363         bnx2x_cnic_notify(bp, CNIC_CTL_FCOE_STATS_GET_CMD);
3364 }
3365
3366 static void bnx2x_drv_info_iscsi_stat(struct bnx2x *bp)
3367 {
3368         struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app;
3369         struct iscsi_stats_info *iscsi_stat =
3370                 &bp->slowpath->drv_info_to_mcp.iscsi_stat;
3371
3372         if (!CNIC_LOADED(bp))
3373                 return;
3374
3375         memcpy(iscsi_stat->mac_local + MAC_PAD, bp->cnic_eth_dev.iscsi_mac,
3376                ETH_ALEN);
3377
3378         iscsi_stat->qos_priority =
3379                 app->traffic_type_priority[LLFC_TRAFFIC_TYPE_ISCSI];
3380
3381         /* ask L5 driver to add data to the struct */
3382         bnx2x_cnic_notify(bp, CNIC_CTL_ISCSI_STATS_GET_CMD);
3383 }
3384
3385 /* called due to MCP event (on pmf):
3386  *      reread new bandwidth configuration
3387  *      configure FW
3388  *      notify others function about the change
3389  */
3390 static void bnx2x_config_mf_bw(struct bnx2x *bp)
3391 {
3392         if (bp->link_vars.link_up) {
3393                 bnx2x_cmng_fns_init(bp, true, CMNG_FNS_MINMAX);
3394                 bnx2x_link_sync_notify(bp);
3395         }
3396         storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
3397 }
3398
3399 static void bnx2x_set_mf_bw(struct bnx2x *bp)
3400 {
3401         bnx2x_config_mf_bw(bp);
3402         bnx2x_fw_command(bp, DRV_MSG_CODE_SET_MF_BW_ACK, 0);
3403 }
3404
3405 static void bnx2x_handle_eee_event(struct bnx2x *bp)
3406 {
3407         DP(BNX2X_MSG_MCP, "EEE - LLDP event\n");
3408         bnx2x_fw_command(bp, DRV_MSG_CODE_EEE_RESULTS_ACK, 0);
3409 }
3410
3411 static void bnx2x_handle_drv_info_req(struct bnx2x *bp)
3412 {
3413         enum drv_info_opcode op_code;
3414         u32 drv_info_ctl = SHMEM2_RD(bp, drv_info_control);
3415
3416         /* if drv_info version supported by MFW doesn't match - send NACK */
3417         if ((drv_info_ctl & DRV_INFO_CONTROL_VER_MASK) != DRV_INFO_CUR_VER) {
3418                 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0);
3419                 return;
3420         }
3421
3422         op_code = (drv_info_ctl & DRV_INFO_CONTROL_OP_CODE_MASK) >>
3423                   DRV_INFO_CONTROL_OP_CODE_SHIFT;
3424
3425         memset(&bp->slowpath->drv_info_to_mcp, 0,
3426                sizeof(union drv_info_to_mcp));
3427
3428         switch (op_code) {
3429         case ETH_STATS_OPCODE:
3430                 bnx2x_drv_info_ether_stat(bp);
3431                 break;
3432         case FCOE_STATS_OPCODE:
3433                 bnx2x_drv_info_fcoe_stat(bp);
3434                 break;
3435         case ISCSI_STATS_OPCODE:
3436                 bnx2x_drv_info_iscsi_stat(bp);
3437                 break;
3438         default:
3439                 /* if op code isn't supported - send NACK */
3440                 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0);
3441                 return;
3442         }
3443
3444         /* if we got drv_info attn from MFW then these fields are defined in
3445          * shmem2 for sure
3446          */
3447         SHMEM2_WR(bp, drv_info_host_addr_lo,
3448                 U64_LO(bnx2x_sp_mapping(bp, drv_info_to_mcp)));
3449         SHMEM2_WR(bp, drv_info_host_addr_hi,
3450                 U64_HI(bnx2x_sp_mapping(bp, drv_info_to_mcp)));
3451
3452         bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_ACK, 0);
3453 }
3454
3455 static void bnx2x_dcc_event(struct bnx2x *bp, u32 dcc_event)
3456 {
3457         DP(BNX2X_MSG_MCP, "dcc_event 0x%x\n", dcc_event);
3458
3459         if (dcc_event & DRV_STATUS_DCC_DISABLE_ENABLE_PF) {
3460
3461                 /*
3462                  * This is the only place besides the function initialization
3463                  * where the bp->flags can change so it is done without any
3464                  * locks
3465                  */
3466                 if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) {
3467                         DP(BNX2X_MSG_MCP, "mf_cfg function disabled\n");
3468                         bp->flags |= MF_FUNC_DIS;
3469
3470                         bnx2x_e1h_disable(bp);
3471                 } else {
3472                         DP(BNX2X_MSG_MCP, "mf_cfg function enabled\n");
3473                         bp->flags &= ~MF_FUNC_DIS;
3474
3475                         bnx2x_e1h_enable(bp);
3476                 }
3477                 dcc_event &= ~DRV_STATUS_DCC_DISABLE_ENABLE_PF;
3478         }
3479         if (dcc_event & DRV_STATUS_DCC_BANDWIDTH_ALLOCATION) {
3480                 bnx2x_config_mf_bw(bp);
3481                 dcc_event &= ~DRV_STATUS_DCC_BANDWIDTH_ALLOCATION;
3482         }
3483
3484         /* Report results to MCP */
3485         if (dcc_event)
3486                 bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_FAILURE, 0);
3487         else
3488                 bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_OK, 0);
3489 }
3490
3491 /* must be called under the spq lock */
3492 static struct eth_spe *bnx2x_sp_get_next(struct bnx2x *bp)
3493 {
3494         struct eth_spe *next_spe = bp->spq_prod_bd;
3495
3496         if (bp->spq_prod_bd == bp->spq_last_bd) {
3497                 bp->spq_prod_bd = bp->spq;
3498                 bp->spq_prod_idx = 0;
3499                 DP(BNX2X_MSG_SP, "end of spq\n");
3500         } else {
3501                 bp->spq_prod_bd++;
3502                 bp->spq_prod_idx++;
3503         }
3504         return next_spe;
3505 }
3506
3507 /* must be called under the spq lock */
3508 static void bnx2x_sp_prod_update(struct bnx2x *bp)
3509 {
3510         int func = BP_FUNC(bp);
3511
3512         /*
3513          * Make sure that BD data is updated before writing the producer:
3514          * BD data is written to the memory, the producer is read from the
3515          * memory, thus we need a full memory barrier to ensure the ordering.
3516          */
3517         mb();
3518
3519         REG_WR16(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func),
3520                  bp->spq_prod_idx);
3521         mmiowb();
3522 }
3523
3524 /**
3525  * bnx2x_is_contextless_ramrod - check if the current command ends on EQ
3526  *
3527  * @cmd:        command to check
3528  * @cmd_type:   command type
3529  */
3530 static bool bnx2x_is_contextless_ramrod(int cmd, int cmd_type)
3531 {
3532         if ((cmd_type == NONE_CONNECTION_TYPE) ||
3533             (cmd == RAMROD_CMD_ID_ETH_FORWARD_SETUP) ||
3534             (cmd == RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES) ||
3535             (cmd == RAMROD_CMD_ID_ETH_FILTER_RULES) ||
3536             (cmd == RAMROD_CMD_ID_ETH_MULTICAST_RULES) ||
3537             (cmd == RAMROD_CMD_ID_ETH_SET_MAC) ||
3538             (cmd == RAMROD_CMD_ID_ETH_RSS_UPDATE))
3539                 return true;
3540         else
3541                 return false;
3542
3543 }
3544
3545
3546 /**
3547  * bnx2x_sp_post - place a single command on an SP ring
3548  *
3549  * @bp:         driver handle
3550  * @command:    command to place (e.g. SETUP, FILTER_RULES, etc.)
3551  * @cid:        SW CID the command is related to
3552  * @data_hi:    command private data address (high 32 bits)
3553  * @data_lo:    command private data address (low 32 bits)
3554  * @cmd_type:   command type (e.g. NONE, ETH)
3555  *
3556  * SP data is handled as if it's always an address pair, thus data fields are
3557  * not swapped to little endian in upper functions. Instead this function swaps
3558  * data as if it's two u32 fields.
3559  */
3560 int bnx2x_sp_post(struct bnx2x *bp, int command, int cid,
3561                   u32 data_hi, u32 data_lo, int cmd_type)
3562 {
3563         struct eth_spe *spe;
3564         u16 type;
3565         bool common = bnx2x_is_contextless_ramrod(command, cmd_type);
3566
3567 #ifdef BNX2X_STOP_ON_ERROR
3568         if (unlikely(bp->panic)) {
3569                 BNX2X_ERR("Can't post SP when there is panic\n");
3570                 return -EIO;
3571         }
3572 #endif
3573
3574         spin_lock_bh(&bp->spq_lock);
3575
3576         if (common) {
3577                 if (!atomic_read(&bp->eq_spq_left)) {
3578                         BNX2X_ERR("BUG! EQ ring full!\n");
3579                         spin_unlock_bh(&bp->spq_lock);
3580                         bnx2x_panic();
3581                         return -EBUSY;
3582                 }
3583         } else if (!atomic_read(&bp->cq_spq_left)) {
3584                         BNX2X_ERR("BUG! SPQ ring full!\n");
3585                         spin_unlock_bh(&bp->spq_lock);
3586                         bnx2x_panic();
3587                         return -EBUSY;
3588         }
3589
3590         spe = bnx2x_sp_get_next(bp);
3591
3592         /* CID needs port number to be encoded int it */
3593         spe->hdr.conn_and_cmd_data =
3594                         cpu_to_le32((command << SPE_HDR_CMD_ID_SHIFT) |
3595                                     HW_CID(bp, cid));
3596
3597         type = (cmd_type << SPE_HDR_CONN_TYPE_SHIFT) & SPE_HDR_CONN_TYPE;
3598
3599         type |= ((BP_FUNC(bp) << SPE_HDR_FUNCTION_ID_SHIFT) &
3600                  SPE_HDR_FUNCTION_ID);
3601
3602         spe->hdr.type = cpu_to_le16(type);
3603
3604         spe->data.update_data_addr.hi = cpu_to_le32(data_hi);
3605         spe->data.update_data_addr.lo = cpu_to_le32(data_lo);
3606
3607         /*
3608          * It's ok if the actual decrement is issued towards the memory
3609          * somewhere between the spin_lock and spin_unlock. Thus no
3610          * more explict memory barrier is needed.
3611          */
3612         if (common)
3613                 atomic_dec(&bp->eq_spq_left);
3614         else
3615                 atomic_dec(&bp->cq_spq_left);
3616
3617
3618         DP(BNX2X_MSG_SP,
3619            "SPQE[%x] (%x:%x)  (cmd, common?) (%d,%d)  hw_cid %x  data (%x:%x) type(0x%x) left (CQ, EQ) (%x,%x)\n",
3620            bp->spq_prod_idx, (u32)U64_HI(bp->spq_mapping),
3621            (u32)(U64_LO(bp->spq_mapping) +
3622            (void *)bp->spq_prod_bd - (void *)bp->spq), command, common,
3623            HW_CID(bp, cid), data_hi, data_lo, type,
3624            atomic_read(&bp->cq_spq_left), atomic_read(&bp->eq_spq_left));
3625
3626         bnx2x_sp_prod_update(bp);
3627         spin_unlock_bh(&bp->spq_lock);
3628         return 0;
3629 }
3630
3631 /* acquire split MCP access lock register */
3632 static int bnx2x_acquire_alr(struct bnx2x *bp)
3633 {
3634         u32 j, val;
3635         int rc = 0;
3636
3637         might_sleep();
3638         for (j = 0; j < 1000; j++) {
3639                 val = (1UL << 31);
3640                 REG_WR(bp, GRCBASE_MCP + 0x9c, val);
3641                 val = REG_RD(bp, GRCBASE_MCP + 0x9c);
3642                 if (val & (1L << 31))
3643                         break;
3644
3645                 msleep(5);
3646         }
3647         if (!(val & (1L << 31))) {
3648                 BNX2X_ERR("Cannot acquire MCP access lock register\n");
3649                 rc = -EBUSY;
3650         }
3651
3652         return rc;
3653 }
3654
3655 /* release split MCP access lock register */
3656 static void bnx2x_release_alr(struct bnx2x *bp)
3657 {
3658         REG_WR(bp, GRCBASE_MCP + 0x9c, 0);
3659 }
3660
3661 #define BNX2X_DEF_SB_ATT_IDX    0x0001
3662 #define BNX2X_DEF_SB_IDX        0x0002
3663
3664 static u16 bnx2x_update_dsb_idx(struct bnx2x *bp)
3665 {
3666         struct host_sp_status_block *def_sb = bp->def_status_blk;
3667         u16 rc = 0;
3668
3669         barrier(); /* status block is written to by the chip */
3670         if (bp->def_att_idx != def_sb->atten_status_block.attn_bits_index) {
3671                 bp->def_att_idx = def_sb->atten_status_block.attn_bits_index;
3672                 rc |= BNX2X_DEF_SB_ATT_IDX;
3673         }
3674
3675         if (bp->def_idx != def_sb->sp_sb.running_index) {
3676                 bp->def_idx = def_sb->sp_sb.running_index;
3677                 rc |= BNX2X_DEF_SB_IDX;
3678         }
3679
3680         /* Do not reorder: indecies reading should complete before handling */
3681         barrier();
3682         return rc;
3683 }
3684
3685 /*
3686  * slow path service functions
3687  */
3688
3689 static void bnx2x_attn_int_asserted(struct bnx2x *bp, u32 asserted)
3690 {
3691         int port = BP_PORT(bp);
3692         u32 aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
3693                               MISC_REG_AEU_MASK_ATTN_FUNC_0;
3694         u32 nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 :
3695                                        NIG_REG_MASK_INTERRUPT_PORT0;
3696         u32 aeu_mask;
3697         u32 nig_mask = 0;
3698         u32 reg_addr;
3699
3700         if (bp->attn_state & asserted)
3701                 BNX2X_ERR("IGU ERROR\n");
3702
3703         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
3704         aeu_mask = REG_RD(bp, aeu_addr);
3705
3706         DP(NETIF_MSG_HW, "aeu_mask %x  newly asserted %x\n",
3707            aeu_mask, asserted);
3708         aeu_mask &= ~(asserted & 0x3ff);
3709         DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
3710
3711         REG_WR(bp, aeu_addr, aeu_mask);
3712         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
3713
3714         DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
3715         bp->attn_state |= asserted;
3716         DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
3717
3718         if (asserted & ATTN_HARD_WIRED_MASK) {
3719                 if (asserted & ATTN_NIG_FOR_FUNC) {
3720
3721                         bnx2x_acquire_phy_lock(bp);
3722
3723                         /* save nig interrupt mask */
3724                         nig_mask = REG_RD(bp, nig_int_mask_addr);
3725
3726                         /* If nig_mask is not set, no need to call the update
3727                          * function.
3728                          */
3729                         if (nig_mask) {
3730                                 REG_WR(bp, nig_int_mask_addr, 0);
3731
3732                                 bnx2x_link_attn(bp);
3733                         }
3734
3735                         /* handle unicore attn? */
3736                 }
3737                 if (asserted & ATTN_SW_TIMER_4_FUNC)
3738                         DP(NETIF_MSG_HW, "ATTN_SW_TIMER_4_FUNC!\n");
3739
3740                 if (asserted & GPIO_2_FUNC)
3741                         DP(NETIF_MSG_HW, "GPIO_2_FUNC!\n");
3742
3743                 if (asserted & GPIO_3_FUNC)
3744                         DP(NETIF_MSG_HW, "GPIO_3_FUNC!\n");
3745
3746                 if (asserted & GPIO_4_FUNC)
3747                         DP(NETIF_MSG_HW, "GPIO_4_FUNC!\n");
3748
3749                 if (port == 0) {
3750                         if (asserted & ATTN_GENERAL_ATTN_1) {
3751                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_1!\n");
3752                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_1, 0x0);
3753                         }
3754                         if (asserted & ATTN_GENERAL_ATTN_2) {
3755                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_2!\n");
3756                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_2, 0x0);
3757                         }
3758                         if (asserted & ATTN_GENERAL_ATTN_3) {
3759                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_3!\n");
3760                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_3, 0x0);
3761                         }
3762                 } else {
3763                         if (asserted & ATTN_GENERAL_ATTN_4) {
3764                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_4!\n");
3765                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_4, 0x0);
3766                         }
3767                         if (asserted & ATTN_GENERAL_ATTN_5) {
3768                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_5!\n");
3769                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_5, 0x0);
3770                         }
3771                         if (asserted & ATTN_GENERAL_ATTN_6) {
3772                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_6!\n");
3773                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_6, 0x0);
3774                         }
3775                 }
3776
3777         } /* if hardwired */
3778
3779         if (bp->common.int_block == INT_BLOCK_HC)
3780                 reg_addr = (HC_REG_COMMAND_REG + port*32 +
3781                             COMMAND_REG_ATTN_BITS_SET);
3782         else
3783                 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_SET_UPPER*8);
3784
3785         DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", asserted,
3786            (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
3787         REG_WR(bp, reg_addr, asserted);
3788
3789         /* now set back the mask */
3790         if (asserted & ATTN_NIG_FOR_FUNC) {
3791                 /* Verify that IGU ack through BAR was written before restoring
3792                  * NIG mask. This loop should exit after 2-3 iterations max.
3793                  */
3794                 if (bp->common.int_block != INT_BLOCK_HC) {
3795                         u32 cnt = 0, igu_acked;
3796                         do {
3797                                 igu_acked = REG_RD(bp,
3798                                                    IGU_REG_ATTENTION_ACK_BITS);
3799                         } while (((igu_acked & ATTN_NIG_FOR_FUNC) == 0) &&
3800                                  (++cnt < MAX_IGU_ATTN_ACK_TO));
3801                         if (!igu_acked)
3802                                 DP(NETIF_MSG_HW,
3803                                    "Failed to verify IGU ack on time\n");
3804                         barrier();
3805                 }
3806                 REG_WR(bp, nig_int_mask_addr, nig_mask);
3807                 bnx2x_release_phy_lock(bp);
3808         }
3809 }
3810
3811 static void bnx2x_fan_failure(struct bnx2x *bp)
3812 {
3813         int port = BP_PORT(bp);
3814         u32 ext_phy_config;
3815         /* mark the failure */
3816         ext_phy_config =
3817                 SHMEM_RD(bp,
3818                          dev_info.port_hw_config[port].external_phy_config);
3819
3820         ext_phy_config &= ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK;
3821         ext_phy_config |= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE;
3822         SHMEM_WR(bp, dev_info.port_hw_config[port].external_phy_config,
3823                  ext_phy_config);
3824
3825         /* log the failure */
3826         netdev_err(bp->dev, "Fan Failure on Network Controller has caused the driver to shutdown the card to prevent permanent damage.\n"
3827                             "Please contact OEM Support for assistance\n");
3828
3829         /*
3830          * Schedule device reset (unload)
3831          * This is due to some boards consuming sufficient power when driver is
3832          * up to overheat if fan fails.
3833          */
3834         smp_mb__before_clear_bit();
3835         set_bit(BNX2X_SP_RTNL_FAN_FAILURE, &bp->sp_rtnl_state);
3836         smp_mb__after_clear_bit();
3837         schedule_delayed_work(&bp->sp_rtnl_task, 0);
3838
3839 }
3840
3841 static void bnx2x_attn_int_deasserted0(struct bnx2x *bp, u32 attn)
3842 {
3843         int port = BP_PORT(bp);
3844         int reg_offset;
3845         u32 val;
3846
3847         reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
3848                              MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
3849
3850         if (attn & AEU_INPUTS_ATTN_BITS_SPIO5) {
3851
3852                 val = REG_RD(bp, reg_offset);
3853                 val &= ~AEU_INPUTS_ATTN_BITS_SPIO5;
3854                 REG_WR(bp, reg_offset, val);
3855
3856                 BNX2X_ERR("SPIO5 hw attention\n");
3857
3858                 /* Fan failure attention */
3859                 bnx2x_hw_reset_phy(&bp->link_params);
3860                 bnx2x_fan_failure(bp);
3861         }
3862
3863         if ((attn & bp->link_vars.aeu_int_mask) && bp->port.pmf) {
3864                 bnx2x_acquire_phy_lock(bp);
3865                 bnx2x_handle_module_detect_int(&bp->link_params);
3866                 bnx2x_release_phy_lock(bp);
3867         }
3868
3869         if (attn & HW_INTERRUT_ASSERT_SET_0) {
3870
3871                 val = REG_RD(bp, reg_offset);
3872                 val &= ~(attn & HW_INTERRUT_ASSERT_SET_0);
3873                 REG_WR(bp, reg_offset, val);
3874
3875                 BNX2X_ERR("FATAL HW block attention set0 0x%x\n",
3876                           (u32)(attn & HW_INTERRUT_ASSERT_SET_0));
3877                 bnx2x_panic();
3878         }
3879 }
3880
3881 static void bnx2x_attn_int_deasserted1(struct bnx2x *bp, u32 attn)
3882 {
3883         u32 val;
3884
3885         if (attn & AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT) {
3886
3887                 val = REG_RD(bp, DORQ_REG_DORQ_INT_STS_CLR);
3888                 BNX2X_ERR("DB hw attention 0x%x\n", val);
3889                 /* DORQ discard attention */
3890                 if (val & 0x2)
3891                         BNX2X_ERR("FATAL error from DORQ\n");
3892         }
3893
3894         if (attn & HW_INTERRUT_ASSERT_SET_1) {
3895
3896                 int port = BP_PORT(bp);
3897                 int reg_offset;
3898
3899                 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 :
3900                                      MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1);
3901
3902                 val = REG_RD(bp, reg_offset);
3903                 val &= ~(attn & HW_INTERRUT_ASSERT_SET_1);
3904                 REG_WR(bp, reg_offset, val);
3905
3906                 BNX2X_ERR("FATAL HW block attention set1 0x%x\n",
3907                           (u32)(attn & HW_INTERRUT_ASSERT_SET_1));
3908                 bnx2x_panic();
3909         }
3910 }
3911
3912 static void bnx2x_attn_int_deasserted2(struct bnx2x *bp, u32 attn)
3913 {
3914         u32 val;
3915
3916         if (attn & AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT) {
3917
3918                 val = REG_RD(bp, CFC_REG_CFC_INT_STS_CLR);
3919                 BNX2X_ERR("CFC hw attention 0x%x\n", val);
3920                 /* CFC error attention */
3921                 if (val & 0x2)
3922                         BNX2X_ERR("FATAL error from CFC\n");
3923         }
3924
3925         if (attn & AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT) {
3926                 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_0);
3927                 BNX2X_ERR("PXP hw attention-0 0x%x\n", val);
3928                 /* RQ_USDMDP_FIFO_OVERFLOW */
3929                 if (val & 0x18000)
3930                         BNX2X_ERR("FATAL error from PXP\n");
3931
3932                 if (!CHIP_IS_E1x(bp)) {
3933                         val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_1);
3934                         BNX2X_ERR("PXP hw attention-1 0x%x\n", val);
3935                 }
3936         }
3937
3938         if (attn & HW_INTERRUT_ASSERT_SET_2) {
3939
3940                 int port = BP_PORT(bp);
3941                 int reg_offset;
3942
3943                 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 :
3944                                      MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2);
3945
3946                 val = REG_RD(bp, reg_offset);
3947                 val &= ~(attn & HW_INTERRUT_ASSERT_SET_2);
3948                 REG_WR(bp, reg_offset, val);
3949
3950                 BNX2X_ERR("FATAL HW block attention set2 0x%x\n",
3951                           (u32)(attn & HW_INTERRUT_ASSERT_SET_2));
3952                 bnx2x_panic();
3953         }
3954 }
3955
3956 static void bnx2x_attn_int_deasserted3(struct bnx2x *bp, u32 attn)
3957 {
3958         u32 val;
3959
3960         if (attn & EVEREST_GEN_ATTN_IN_USE_MASK) {
3961
3962                 if (attn & BNX2X_PMF_LINK_ASSERT) {
3963                         int func = BP_FUNC(bp);
3964
3965                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
3966                         bnx2x_read_mf_cfg(bp);
3967                         bp->mf_config[BP_VN(bp)] = MF_CFG_RD(bp,
3968                                         func_mf_config[BP_ABS_FUNC(bp)].config);
3969                         val = SHMEM_RD(bp,
3970                                        func_mb[BP_FW_MB_IDX(bp)].drv_status);
3971                         if (val & DRV_STATUS_DCC_EVENT_MASK)
3972                                 bnx2x_dcc_event(bp,
3973                                             (val & DRV_STATUS_DCC_EVENT_MASK));
3974
3975                         if (val & DRV_STATUS_SET_MF_BW)
3976                                 bnx2x_set_mf_bw(bp);
3977
3978                         if (val & DRV_STATUS_DRV_INFO_REQ)
3979                                 bnx2x_handle_drv_info_req(bp);
3980
3981                         if (val & DRV_STATUS_VF_DISABLED)
3982                                 bnx2x_vf_handle_flr_event(bp);
3983
3984                         if ((bp->port.pmf == 0) && (val & DRV_STATUS_PMF))
3985                                 bnx2x_pmf_update(bp);
3986
3987                         if (bp->port.pmf &&
3988                             (val & DRV_STATUS_DCBX_NEGOTIATION_RESULTS) &&
3989                                 bp->dcbx_enabled > 0)
3990                                 /* start dcbx state machine */
3991                                 bnx2x_dcbx_set_params(bp,
3992                                         BNX2X_DCBX_STATE_NEG_RECEIVED);
3993                         if (val & DRV_STATUS_AFEX_EVENT_MASK)
3994                                 bnx2x_handle_afex_cmd(bp,
3995                                         val & DRV_STATUS_AFEX_EVENT_MASK);
3996                         if (val & DRV_STATUS_EEE_NEGOTIATION_RESULTS)
3997                                 bnx2x_handle_eee_event(bp);
3998                         if (bp->link_vars.periodic_flags &
3999                             PERIODIC_FLAGS_LINK_EVENT) {
4000                                 /*  sync with link */
4001                                 bnx2x_acquire_phy_lock(bp);
4002                                 bp->link_vars.periodic_flags &=
4003                                         ~PERIODIC_FLAGS_LINK_EVENT;
4004                                 bnx2x_release_phy_lock(bp);
4005                                 if (IS_MF(bp))
4006                                         bnx2x_link_sync_notify(bp);
4007                                 bnx2x_link_report(bp);
4008                         }
4009                         /* Always call it here: bnx2x_link_report() will
4010                          * prevent the link indication duplication.
4011                          */
4012                         bnx2x__link_status_update(bp);
4013                 } else if (attn & BNX2X_MC_ASSERT_BITS) {
4014
4015                         BNX2X_ERR("MC assert!\n");
4016                         bnx2x_mc_assert(bp);
4017                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_10, 0);
4018                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_9, 0);
4019                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_8, 0);
4020                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_7, 0);
4021                         bnx2x_panic();
4022
4023                 } else if (attn & BNX2X_MCP_ASSERT) {
4024
4025                         BNX2X_ERR("MCP assert!\n");
4026                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_11, 0);
4027                         bnx2x_fw_dump(bp);
4028
4029                 } else
4030                         BNX2X_ERR("Unknown HW assert! (attn 0x%x)\n", attn);
4031         }
4032
4033         if (attn & EVEREST_LATCHED_ATTN_IN_USE_MASK) {
4034                 BNX2X_ERR("LATCHED attention 0x%08x (masked)\n", attn);
4035                 if (attn & BNX2X_GRC_TIMEOUT) {
4036                         val = CHIP_IS_E1(bp) ? 0 :
4037                                         REG_RD(bp, MISC_REG_GRC_TIMEOUT_ATTN);
4038                         BNX2X_ERR("GRC time-out 0x%08x\n", val);
4039                 }
4040                 if (attn & BNX2X_GRC_RSV) {
4041                         val = CHIP_IS_E1(bp) ? 0 :
4042                                         REG_RD(bp, MISC_REG_GRC_RSV_ATTN);
4043                         BNX2X_ERR("GRC reserved 0x%08x\n", val);
4044                 }
4045                 REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff);
4046         }
4047 }
4048
4049 /*
4050  * Bits map:
4051  * 0-7   - Engine0 load counter.
4052  * 8-15  - Engine1 load counter.
4053  * 16    - Engine0 RESET_IN_PROGRESS bit.
4054  * 17    - Engine1 RESET_IN_PROGRESS bit.
4055  * 18    - Engine0 ONE_IS_LOADED. Set when there is at least one active function
4056  *         on the engine
4057  * 19    - Engine1 ONE_IS_LOADED.
4058  * 20    - Chip reset flow bit. When set none-leader must wait for both engines
4059  *         leader to complete (check for both RESET_IN_PROGRESS bits and not for
4060  *         just the one belonging to its engine).
4061  *
4062  */
4063 #define BNX2X_RECOVERY_GLOB_REG         MISC_REG_GENERIC_POR_1
4064
4065 #define BNX2X_PATH0_LOAD_CNT_MASK       0x000000ff
4066 #define BNX2X_PATH0_LOAD_CNT_SHIFT      0
4067 #define BNX2X_PATH1_LOAD_CNT_MASK       0x0000ff00
4068 #define BNX2X_PATH1_LOAD_CNT_SHIFT      8
4069 #define BNX2X_PATH0_RST_IN_PROG_BIT     0x00010000
4070 #define BNX2X_PATH1_RST_IN_PROG_BIT     0x00020000
4071 #define BNX2X_GLOBAL_RESET_BIT          0x00040000
4072
4073 /*
4074  * Set the GLOBAL_RESET bit.
4075  *
4076  * Should be run under rtnl lock
4077  */
4078 void bnx2x_set_reset_global(struct bnx2x *bp)
4079 {
4080         u32 val;
4081         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4082         val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4083         REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val | BNX2X_GLOBAL_RESET_BIT);
4084         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4085 }
4086
4087 /*
4088  * Clear the GLOBAL_RESET bit.
4089  *
4090  * Should be run under rtnl lock
4091  */
4092 static void bnx2x_clear_reset_global(struct bnx2x *bp)
4093 {
4094         u32 val;
4095         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4096         val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4097         REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val & (~BNX2X_GLOBAL_RESET_BIT));
4098         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4099 }
4100
4101 /*
4102  * Checks the GLOBAL_RESET bit.
4103  *
4104  * should be run under rtnl lock
4105  */
4106 static bool bnx2x_reset_is_global(struct bnx2x *bp)
4107 {
4108         u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4109
4110         DP(NETIF_MSG_HW, "GEN_REG_VAL=0x%08x\n", val);
4111         return (val & BNX2X_GLOBAL_RESET_BIT) ? true : false;
4112 }
4113
4114 /*
4115  * Clear RESET_IN_PROGRESS bit for the current engine.
4116  *
4117  * Should be run under rtnl lock
4118  */
4119 static void bnx2x_set_reset_done(struct bnx2x *bp)
4120 {
4121         u32 val;
4122         u32 bit = BP_PATH(bp) ?
4123                 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
4124         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4125         val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4126
4127         /* Clear the bit */
4128         val &= ~bit;
4129         REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
4130
4131         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4132 }
4133
4134 /*
4135  * Set RESET_IN_PROGRESS for the current engine.
4136  *
4137  * should be run under rtnl lock
4138  */
4139 void bnx2x_set_reset_in_progress(struct bnx2x *bp)
4140 {
4141         u32 val;
4142         u32 bit = BP_PATH(bp) ?
4143                 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
4144         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4145         val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4146
4147         /* Set the bit */
4148         val |= bit;
4149         REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
4150         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4151 }
4152
4153 /*
4154  * Checks the RESET_IN_PROGRESS bit for the given engine.
4155  * should be run under rtnl lock
4156  */
4157 bool bnx2x_reset_is_done(struct bnx2x *bp, int engine)
4158 {
4159         u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4160         u32 bit = engine ?
4161                 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
4162
4163         /* return false if bit is set */
4164         return (val & bit) ? false : true;
4165 }
4166
4167 /*
4168  * set pf load for the current pf.
4169  *
4170  * should be run under rtnl lock
4171  */
4172 void bnx2x_set_pf_load(struct bnx2x *bp)
4173 {
4174         u32 val1, val;
4175         u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
4176                              BNX2X_PATH0_LOAD_CNT_MASK;
4177         u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
4178                              BNX2X_PATH0_LOAD_CNT_SHIFT;
4179
4180         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4181         val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4182
4183         DP(NETIF_MSG_IFUP, "Old GEN_REG_VAL=0x%08x\n", val);
4184
4185         /* get the current counter value */
4186         val1 = (val & mask) >> shift;
4187
4188         /* set bit of that PF */
4189         val1 |= (1 << bp->pf_num);
4190
4191         /* clear the old value */
4192         val &= ~mask;
4193
4194         /* set the new one */
4195         val |= ((val1 << shift) & mask);
4196
4197         REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
4198         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4199 }
4200
4201 /**
4202  * bnx2x_clear_pf_load - clear pf load mark
4203  *
4204  * @bp:         driver handle
4205  *
4206  * Should be run under rtnl lock.
4207  * Decrements the load counter for the current engine. Returns
4208  * whether other functions are still loaded
4209  */
4210 bool bnx2x_clear_pf_load(struct bnx2x *bp)
4211 {
4212         u32 val1, val;
4213         u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
4214                              BNX2X_PATH0_LOAD_CNT_MASK;
4215         u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
4216                              BNX2X_PATH0_LOAD_CNT_SHIFT;
4217
4218         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4219         val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4220         DP(NETIF_MSG_IFDOWN, "Old GEN_REG_VAL=0x%08x\n", val);
4221
4222         /* get the current counter value */
4223         val1 = (val & mask) >> shift;
4224
4225         /* clear bit of that PF */
4226         val1 &= ~(1 << bp->pf_num);
4227
4228         /* clear the old value */
4229         val &= ~mask;
4230
4231         /* set the new one */
4232         val |= ((val1 << shift) & mask);
4233
4234         REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
4235         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4236         return val1 != 0;
4237 }
4238
4239 /*
4240  * Read the load status for the current engine.
4241  *
4242  * should be run under rtnl lock
4243  */
4244 static bool bnx2x_get_load_status(struct bnx2x *bp, int engine)
4245 {
4246         u32 mask = (engine ? BNX2X_PATH1_LOAD_CNT_MASK :
4247                              BNX2X_PATH0_LOAD_CNT_MASK);
4248         u32 shift = (engine ? BNX2X_PATH1_LOAD_CNT_SHIFT :
4249                              BNX2X_PATH0_LOAD_CNT_SHIFT);
4250         u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4251
4252         DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "GLOB_REG=0x%08x\n", val);
4253
4254         val = (val & mask) >> shift;
4255
4256         DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "load mask for engine %d = 0x%x\n",
4257            engine, val);
4258
4259         return val != 0;
4260 }
4261
4262 static void _print_next_block(int idx, const char *blk)
4263 {
4264         pr_cont("%s%s", idx ? ", " : "", blk);
4265 }
4266
4267 static int bnx2x_check_blocks_with_parity0(u32 sig, int par_num,
4268                                            bool print)
4269 {
4270         int i = 0;
4271         u32 cur_bit = 0;
4272         for (i = 0; sig; i++) {
4273                 cur_bit = ((u32)0x1 << i);
4274                 if (sig & cur_bit) {
4275                         switch (cur_bit) {
4276                         case AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR:
4277                                 if (print)
4278                                         _print_next_block(par_num++, "BRB");
4279                                 break;
4280                         case AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR:
4281                                 if (print)
4282                                         _print_next_block(par_num++, "PARSER");
4283                                 break;
4284                         case AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR:
4285                                 if (print)
4286                                         _print_next_block(par_num++, "TSDM");
4287                                 break;
4288                         case AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR:
4289                                 if (print)
4290                                         _print_next_block(par_num++,
4291                                                           "SEARCHER");
4292                                 break;
4293                         case AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR:
4294                                 if (print)
4295                                         _print_next_block(par_num++, "TCM");
4296                                 break;
4297                         case AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR:
4298                                 if (print)
4299                                         _print_next_block(par_num++, "TSEMI");
4300                                 break;
4301                         case AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR:
4302                                 if (print)
4303                                         _print_next_block(par_num++, "XPB");
4304                                 break;
4305                         }
4306
4307                         /* Clear the bit */
4308                         sig &= ~cur_bit;
4309                 }
4310         }
4311
4312         return par_num;
4313 }
4314
4315 static int bnx2x_check_blocks_with_parity1(u32 sig, int par_num,
4316                                            bool *global, bool print)
4317 {
4318         int i = 0;
4319         u32 cur_bit = 0;
4320         for (i = 0; sig; i++) {
4321                 cur_bit = ((u32)0x1 << i);
4322                 if (sig & cur_bit) {
4323                         switch (cur_bit) {
4324                         case AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR:
4325                                 if (print)
4326                                         _print_next_block(par_num++, "PBF");
4327                                 break;
4328                         case AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR:
4329                                 if (print)
4330                                         _print_next_block(par_num++, "QM");
4331                                 break;
4332                         case AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR:
4333                                 if (print)
4334                                         _print_next_block(par_num++, "TM");
4335                                 break;
4336                         case AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR:
4337                                 if (print)
4338                                         _print_next_block(par_num++, "XSDM");
4339                                 break;
4340                         case AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR:
4341                                 if (print)
4342                                         _print_next_block(par_num++, "XCM");
4343                                 break;
4344                         case AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR:
4345                                 if (print)
4346                                         _print_next_block(par_num++, "XSEMI");
4347                                 break;
4348                         case AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR:
4349                                 if (print)
4350                                         _print_next_block(par_num++,
4351                                                           "DOORBELLQ");
4352                                 break;
4353                         case AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR:
4354                                 if (print)
4355                                         _print_next_block(par_num++, "NIG");
4356                                 break;
4357                         case AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR:
4358                                 if (print)
4359                                         _print_next_block(par_num++,
4360                                                           "VAUX PCI CORE");
4361                                 *global = true;
4362                                 break;
4363                         case AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR:
4364                                 if (print)
4365                                         _print_next_block(par_num++, "DEBUG");
4366                                 break;
4367                         case AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR:
4368                                 if (print)
4369                                         _print_next_block(par_num++, "USDM");
4370                                 break;
4371                         case AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR:
4372                                 if (print)
4373                                         _print_next_block(par_num++, "UCM");
4374                                 break;
4375                         case AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR:
4376                                 if (print)
4377                                         _print_next_block(par_num++, "USEMI");
4378                                 break;
4379                         case AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR:
4380                                 if (print)
4381                                         _print_next_block(par_num++, "UPB");
4382                                 break;
4383                         case AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR:
4384                                 if (print)
4385                                         _print_next_block(par_num++, "CSDM");
4386                                 break;
4387                         case AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR:
4388                                 if (print)
4389                                         _print_next_block(par_num++, "CCM");
4390                                 break;
4391                         }
4392
4393                         /* Clear the bit */
4394                         sig &= ~cur_bit;
4395                 }
4396         }
4397
4398         return par_num;
4399 }
4400
4401 static int bnx2x_check_blocks_with_parity2(u32 sig, int par_num,
4402                                            bool print)
4403 {
4404         int i = 0;
4405         u32 cur_bit = 0;
4406         for (i = 0; sig; i++) {
4407                 cur_bit = ((u32)0x1 << i);
4408                 if (sig & cur_bit) {
4409                         switch (cur_bit) {
4410                         case AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR:
4411                                 if (print)
4412                                         _print_next_block(par_num++, "CSEMI");
4413                                 break;
4414                         case AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR:
4415                                 if (print)
4416                                         _print_next_block(par_num++, "PXP");
4417                                 break;
4418                         case AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR:
4419                                 if (print)
4420                                         _print_next_block(par_num++,
4421                                         "PXPPCICLOCKCLIENT");
4422                                 break;
4423                         case AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR:
4424                                 if (print)
4425                                         _print_next_block(par_num++, "CFC");
4426                                 break;
4427                         case AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR:
4428                                 if (print)
4429                                         _print_next_block(par_num++, "CDU");
4430                                 break;
4431                         case AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR:
4432                                 if (print)
4433                                         _print_next_block(par_num++, "DMAE");
4434                                 break;
4435                         case AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR:
4436                                 if (print)
4437                                         _print_next_block(par_num++, "IGU");
4438                                 break;
4439                         case AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR:
4440                                 if (print)
4441                                         _print_next_block(par_num++, "MISC");
4442                                 break;
4443                         }
4444
4445                         /* Clear the bit */
4446                         sig &= ~cur_bit;
4447                 }
4448         }
4449
4450         return par_num;
4451 }
4452
4453 static int bnx2x_check_blocks_with_parity3(u32 sig, int par_num,
4454                                            bool *global, bool print)
4455 {
4456         int i = 0;
4457         u32 cur_bit = 0;
4458         for (i = 0; sig; i++) {
4459                 cur_bit = ((u32)0x1 << i);
4460                 if (sig & cur_bit) {
4461                         switch (cur_bit) {
4462                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY:
4463                                 if (print)
4464                                         _print_next_block(par_num++, "MCP ROM");
4465                                 *global = true;
4466                                 break;
4467                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY:
4468                                 if (print)
4469                                         _print_next_block(par_num++,
4470                                                           "MCP UMP RX");
4471                                 *global = true;
4472                                 break;
4473                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY:
4474                                 if (print)
4475                                         _print_next_block(par_num++,
4476                                                           "MCP UMP TX");
4477                                 *global = true;
4478                                 break;
4479                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY:
4480                                 if (print)
4481                                         _print_next_block(par_num++,
4482                                                           "MCP SCPAD");
4483                                 *global = true;
4484                                 break;
4485                         }
4486
4487                         /* Clear the bit */
4488                         sig &= ~cur_bit;
4489                 }
4490         }
4491
4492         return par_num;
4493 }
4494
4495 static int bnx2x_check_blocks_with_parity4(u32 sig, int par_num,
4496                                            bool print)
4497 {
4498         int i = 0;
4499         u32 cur_bit = 0;
4500         for (i = 0; sig; i++) {
4501                 cur_bit = ((u32)0x1 << i);
4502                 if (sig & cur_bit) {
4503                         switch (cur_bit) {
4504                         case AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR:
4505                                 if (print)
4506                                         _print_next_block(par_num++, "PGLUE_B");
4507                                 break;
4508                         case AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR:
4509                                 if (print)
4510                                         _print_next_block(par_num++, "ATC");
4511                                 break;
4512                         }
4513
4514                         /* Clear the bit */
4515                         sig &= ~cur_bit;
4516                 }
4517         }
4518
4519         return par_num;
4520 }
4521
4522 static bool bnx2x_parity_attn(struct bnx2x *bp, bool *global, bool print,
4523                               u32 *sig)
4524 {
4525         if ((sig[0] & HW_PRTY_ASSERT_SET_0) ||
4526             (sig[1] & HW_PRTY_ASSERT_SET_1) ||
4527             (sig[2] & HW_PRTY_ASSERT_SET_2) ||
4528             (sig[3] & HW_PRTY_ASSERT_SET_3) ||
4529             (sig[4] & HW_PRTY_ASSERT_SET_4)) {
4530                 int par_num = 0;
4531                 DP(NETIF_MSG_HW, "Was parity error: HW block parity attention:\n"
4532                                  "[0]:0x%08x [1]:0x%08x [2]:0x%08x [3]:0x%08x [4]:0x%08x\n",
4533                           sig[0] & HW_PRTY_ASSERT_SET_0,
4534                           sig[1] & HW_PRTY_ASSERT_SET_1,
4535                           sig[2] & HW_PRTY_ASSERT_SET_2,
4536                           sig[3] & HW_PRTY_ASSERT_SET_3,
4537                           sig[4] & HW_PRTY_ASSERT_SET_4);
4538                 if (print)
4539                         netdev_err(bp->dev,
4540                                    "Parity errors detected in blocks: ");
4541                 par_num = bnx2x_check_blocks_with_parity0(
4542                         sig[0] & HW_PRTY_ASSERT_SET_0, par_num, print);
4543                 par_num = bnx2x_check_blocks_with_parity1(
4544                         sig[1] & HW_PRTY_ASSERT_SET_1, par_num, global, print);
4545                 par_num = bnx2x_check_blocks_with_parity2(
4546                         sig[2] & HW_PRTY_ASSERT_SET_2, par_num, print);
4547                 par_num = bnx2x_check_blocks_with_parity3(
4548                         sig[3] & HW_PRTY_ASSERT_SET_3, par_num, global, print);
4549                 par_num = bnx2x_check_blocks_with_parity4(
4550                         sig[4] & HW_PRTY_ASSERT_SET_4, par_num, print);
4551
4552                 if (print)
4553                         pr_cont("\n");
4554
4555                 return true;
4556         } else
4557                 return false;
4558 }
4559
4560 /**
4561  * bnx2x_chk_parity_attn - checks for parity attentions.
4562  *
4563  * @bp:         driver handle
4564  * @global:     true if there was a global attention
4565  * @print:      show parity attention in syslog
4566  */
4567 bool bnx2x_chk_parity_attn(struct bnx2x *bp, bool *global, bool print)
4568 {
4569         struct attn_route attn = { {0} };
4570         int port = BP_PORT(bp);
4571
4572         attn.sig[0] = REG_RD(bp,
4573                 MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 +
4574                              port*4);
4575         attn.sig[1] = REG_RD(bp,
4576                 MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 +
4577                              port*4);
4578         attn.sig[2] = REG_RD(bp,
4579                 MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 +
4580                              port*4);
4581         attn.sig[3] = REG_RD(bp,
4582                 MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 +
4583                              port*4);
4584
4585         if (!CHIP_IS_E1x(bp))
4586                 attn.sig[4] = REG_RD(bp,
4587                         MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 +
4588                                      port*4);
4589
4590         return bnx2x_parity_attn(bp, global, print, attn.sig);
4591 }
4592
4593
4594 static void bnx2x_attn_int_deasserted4(struct bnx2x *bp, u32 attn)
4595 {
4596         u32 val;
4597         if (attn & AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT) {
4598
4599                 val = REG_RD(bp, PGLUE_B_REG_PGLUE_B_INT_STS_CLR);
4600                 BNX2X_ERR("PGLUE hw attention 0x%x\n", val);
4601                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR)
4602                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR\n");
4603                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR)
4604                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR\n");
4605                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN)
4606                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN\n");
4607                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN)
4608                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN\n");
4609                 if (val &
4610                     PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN)
4611                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN\n");
4612                 if (val &
4613                     PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN)
4614                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN\n");
4615                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN)
4616                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN\n");
4617                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN)
4618                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN\n");
4619                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW)
4620                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW\n");
4621         }
4622         if (attn & AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT) {
4623                 val = REG_RD(bp, ATC_REG_ATC_INT_STS_CLR);
4624                 BNX2X_ERR("ATC hw attention 0x%x\n", val);
4625                 if (val & ATC_ATC_INT_STS_REG_ADDRESS_ERROR)
4626                         BNX2X_ERR("ATC_ATC_INT_STS_REG_ADDRESS_ERROR\n");
4627                 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND)
4628                         BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND\n");
4629                 if (val & ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS)
4630                         BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS\n");
4631                 if (val & ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT)
4632                         BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT\n");
4633                 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR)
4634                         BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR\n");
4635                 if (val & ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU)
4636                         BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU\n");
4637         }
4638
4639         if (attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
4640                     AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)) {
4641                 BNX2X_ERR("FATAL parity attention set4 0x%x\n",
4642                 (u32)(attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
4643                     AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)));
4644         }
4645
4646 }
4647
4648 static void bnx2x_attn_int_deasserted(struct bnx2x *bp, u32 deasserted)
4649 {
4650         struct attn_route attn, *group_mask;
4651         int port = BP_PORT(bp);
4652         int index;
4653         u32 reg_addr;
4654         u32 val;
4655         u32 aeu_mask;
4656         bool global = false;
4657
4658         /* need to take HW lock because MCP or other port might also
4659            try to handle this event */
4660         bnx2x_acquire_alr(bp);
4661
4662         if (bnx2x_chk_parity_attn(bp, &global, true)) {
4663 #ifndef BNX2X_STOP_ON_ERROR
4664                 bp->recovery_state = BNX2X_RECOVERY_INIT;
4665                 schedule_delayed_work(&bp->sp_rtnl_task, 0);
4666                 /* Disable HW interrupts */
4667                 bnx2x_int_disable(bp);
4668                 /* In case of parity errors don't handle attentions so that
4669                  * other function would "see" parity errors.
4670                  */
4671 #else
4672                 bnx2x_panic();
4673 #endif
4674                 bnx2x_release_alr(bp);
4675                 return;
4676         }
4677
4678         attn.sig[0] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port*4);
4679         attn.sig[1] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port*4);
4680         attn.sig[2] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port*4);
4681         attn.sig[3] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port*4);
4682         if (!CHIP_IS_E1x(bp))
4683                 attn.sig[4] =
4684                       REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port*4);
4685         else
4686                 attn.sig[4] = 0;
4687
4688         DP(NETIF_MSG_HW, "attn: %08x %08x %08x %08x %08x\n",
4689            attn.sig[0], attn.sig[1], attn.sig[2], attn.sig[3], attn.sig[4]);
4690
4691         for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
4692                 if (deasserted & (1 << index)) {
4693                         group_mask = &bp->attn_group[index];
4694
4695                         DP(NETIF_MSG_HW, "group[%d]: %08x %08x %08x %08x %08x\n",
4696                            index,
4697                            group_mask->sig[0], group_mask->sig[1],
4698                            group_mask->sig[2], group_mask->sig[3],
4699                            group_mask->sig[4]);
4700
4701                         bnx2x_attn_int_deasserted4(bp,
4702                                         attn.sig[4] & group_mask->sig[4]);
4703                         bnx2x_attn_int_deasserted3(bp,
4704                                         attn.sig[3] & group_mask->sig[3]);
4705                         bnx2x_attn_int_deasserted1(bp,
4706                                         attn.sig[1] & group_mask->sig[1]);
4707                         bnx2x_attn_int_deasserted2(bp,
4708                                         attn.sig[2] & group_mask->sig[2]);
4709                         bnx2x_attn_int_deasserted0(bp,
4710                                         attn.sig[0] & group_mask->sig[0]);
4711                 }
4712         }
4713
4714         bnx2x_release_alr(bp);
4715
4716         if (bp->common.int_block == INT_BLOCK_HC)
4717                 reg_addr = (HC_REG_COMMAND_REG + port*32 +
4718                             COMMAND_REG_ATTN_BITS_CLR);
4719         else
4720                 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_CLR_UPPER*8);
4721
4722         val = ~deasserted;
4723         DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", val,
4724            (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
4725         REG_WR(bp, reg_addr, val);
4726
4727         if (~bp->attn_state & deasserted)
4728                 BNX2X_ERR("IGU ERROR\n");
4729
4730         reg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
4731                           MISC_REG_AEU_MASK_ATTN_FUNC_0;
4732
4733         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
4734         aeu_mask = REG_RD(bp, reg_addr);
4735
4736         DP(NETIF_MSG_HW, "aeu_mask %x  newly deasserted %x\n",
4737            aeu_mask, deasserted);
4738         aeu_mask |= (deasserted & 0x3ff);
4739         DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
4740
4741         REG_WR(bp, reg_addr, aeu_mask);
4742         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
4743
4744         DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
4745         bp->attn_state &= ~deasserted;
4746         DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
4747 }
4748
4749 static void bnx2x_attn_int(struct bnx2x *bp)
4750 {
4751         /* read local copy of bits */
4752         u32 attn_bits = le32_to_cpu(bp->def_status_blk->atten_status_block.
4753                                                                 attn_bits);
4754         u32 attn_ack = le32_to_cpu(bp->def_status_blk->atten_status_block.
4755                                                                 attn_bits_ack);
4756         u32 attn_state = bp->attn_state;
4757
4758         /* look for changed bits */
4759         u32 asserted   =  attn_bits & ~attn_ack & ~attn_state;
4760         u32 deasserted = ~attn_bits &  attn_ack &  attn_state;
4761
4762         DP(NETIF_MSG_HW,
4763            "attn_bits %x  attn_ack %x  asserted %x  deasserted %x\n",
4764            attn_bits, attn_ack, asserted, deasserted);
4765
4766         if (~(attn_bits ^ attn_ack) & (attn_bits ^ attn_state))
4767                 BNX2X_ERR("BAD attention state\n");
4768
4769         /* handle bits that were raised */
4770         if (asserted)
4771                 bnx2x_attn_int_asserted(bp, asserted);
4772
4773         if (deasserted)
4774                 bnx2x_attn_int_deasserted(bp, deasserted);
4775 }
4776
4777 void bnx2x_igu_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 segment,
4778                       u16 index, u8 op, u8 update)
4779 {
4780         u32 igu_addr = bp->igu_base_addr;
4781         igu_addr += (IGU_CMD_INT_ACK_BASE + igu_sb_id)*8;
4782         bnx2x_igu_ack_sb_gen(bp, igu_sb_id, segment, index, op, update,
4783                              igu_addr);
4784 }
4785
4786 static void bnx2x_update_eq_prod(struct bnx2x *bp, u16 prod)
4787 {
4788         /* No memory barriers */
4789         storm_memset_eq_prod(bp, prod, BP_FUNC(bp));
4790         mmiowb(); /* keep prod updates ordered */
4791 }
4792
4793 static int  bnx2x_cnic_handle_cfc_del(struct bnx2x *bp, u32 cid,
4794                                       union event_ring_elem *elem)
4795 {
4796         u8 err = elem->message.error;
4797
4798         if (!bp->cnic_eth_dev.starting_cid  ||
4799             (cid < bp->cnic_eth_dev.starting_cid &&
4800             cid != bp->cnic_eth_dev.iscsi_l2_cid))
4801                 return 1;
4802
4803         DP(BNX2X_MSG_SP, "got delete ramrod for CNIC CID %d\n", cid);
4804
4805         if (unlikely(err)) {
4806
4807                 BNX2X_ERR("got delete ramrod for CNIC CID %d with error!\n",
4808                           cid);
4809                 bnx2x_panic_dump(bp, false);
4810         }
4811         bnx2x_cnic_cfc_comp(bp, cid, err);
4812         return 0;
4813 }
4814
4815 static void bnx2x_handle_mcast_eqe(struct bnx2x *bp)
4816 {
4817         struct bnx2x_mcast_ramrod_params rparam;
4818         int rc;
4819
4820         memset(&rparam, 0, sizeof(rparam));
4821
4822         rparam.mcast_obj = &bp->mcast_obj;
4823
4824         netif_addr_lock_bh(bp->dev);
4825
4826         /* Clear pending state for the last command */
4827         bp->mcast_obj.raw.clear_pending(&bp->mcast_obj.raw);
4828
4829         /* If there are pending mcast commands - send them */
4830         if (bp->mcast_obj.check_pending(&bp->mcast_obj)) {
4831                 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_CONT);
4832                 if (rc < 0)
4833                         BNX2X_ERR("Failed to send pending mcast commands: %d\n",
4834                                   rc);
4835         }
4836
4837         netif_addr_unlock_bh(bp->dev);
4838 }
4839
4840 static void bnx2x_handle_classification_eqe(struct bnx2x *bp,
4841                                             union event_ring_elem *elem)
4842 {
4843         unsigned long ramrod_flags = 0;
4844         int rc = 0;
4845         u32 cid = elem->message.data.eth_event.echo & BNX2X_SWCID_MASK;
4846         struct bnx2x_vlan_mac_obj *vlan_mac_obj;
4847
4848         /* Always push next commands out, don't wait here */
4849         __set_bit(RAMROD_CONT, &ramrod_flags);
4850
4851         switch (le32_to_cpu((__force __le32)elem->message.data.eth_event.echo)
4852                             >> BNX2X_SWCID_SHIFT) {
4853         case BNX2X_FILTER_MAC_PENDING:
4854                 DP(BNX2X_MSG_SP, "Got SETUP_MAC completions\n");
4855                 if (CNIC_LOADED(bp) && (cid == BNX2X_ISCSI_ETH_CID(bp)))
4856                         vlan_mac_obj = &bp->iscsi_l2_mac_obj;
4857                 else
4858                         vlan_mac_obj = &bp->sp_objs[cid].mac_obj;
4859
4860                 break;
4861         case BNX2X_FILTER_MCAST_PENDING:
4862                 DP(BNX2X_MSG_SP, "Got SETUP_MCAST completions\n");
4863                 /* This is only relevant for 57710 where multicast MACs are
4864                  * configured as unicast MACs using the same ramrod.
4865                  */
4866                 bnx2x_handle_mcast_eqe(bp);
4867                 return;
4868         default:
4869                 BNX2X_ERR("Unsupported classification command: %d\n",
4870                           elem->message.data.eth_event.echo);
4871                 return;
4872         }
4873
4874         rc = vlan_mac_obj->complete(bp, vlan_mac_obj, elem, &ramrod_flags);
4875
4876         if (rc < 0)
4877                 BNX2X_ERR("Failed to schedule new commands: %d\n", rc);
4878         else if (rc > 0)
4879                 DP(BNX2X_MSG_SP, "Scheduled next pending commands...\n");
4880
4881 }
4882
4883 static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start);
4884
4885 static void bnx2x_handle_rx_mode_eqe(struct bnx2x *bp)
4886 {
4887         netif_addr_lock_bh(bp->dev);
4888
4889         clear_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state);
4890
4891         /* Send rx_mode command again if was requested */
4892         if (test_and_clear_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state))
4893                 bnx2x_set_storm_rx_mode(bp);
4894         else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED,
4895                                     &bp->sp_state))
4896                 bnx2x_set_iscsi_eth_rx_mode(bp, true);
4897         else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED,
4898                                     &bp->sp_state))
4899                 bnx2x_set_iscsi_eth_rx_mode(bp, false);
4900
4901         netif_addr_unlock_bh(bp->dev);
4902 }
4903
4904 static void bnx2x_after_afex_vif_lists(struct bnx2x *bp,
4905                                               union event_ring_elem *elem)
4906 {
4907         if (elem->message.data.vif_list_event.echo == VIF_LIST_RULE_GET) {
4908                 DP(BNX2X_MSG_SP,
4909                    "afex: ramrod completed VIF LIST_GET, addrs 0x%x\n",
4910                    elem->message.data.vif_list_event.func_bit_map);
4911                 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_LISTGET_ACK,
4912                         elem->message.data.vif_list_event.func_bit_map);
4913         } else if (elem->message.data.vif_list_event.echo ==
4914                    VIF_LIST_RULE_SET) {
4915                 DP(BNX2X_MSG_SP, "afex: ramrod completed VIF LIST_SET\n");
4916                 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_LISTSET_ACK, 0);
4917         }
4918 }
4919
4920 /* called with rtnl_lock */
4921 static void bnx2x_after_function_update(struct bnx2x *bp)
4922 {
4923         int q, rc;
4924         struct bnx2x_fastpath *fp;
4925         struct bnx2x_queue_state_params queue_params = {NULL};
4926         struct bnx2x_queue_update_params *q_update_params =
4927                 &queue_params.params.update;
4928
4929         /* Send Q update command with afex vlan removal values for all Qs */
4930         queue_params.cmd = BNX2X_Q_CMD_UPDATE;
4931
4932         /* set silent vlan removal values according to vlan mode */
4933         __set_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM_CHNG,
4934                   &q_update_params->update_flags);
4935         __set_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM,
4936                   &q_update_params->update_flags);
4937         __set_bit(RAMROD_COMP_WAIT, &queue_params.ramrod_flags);
4938
4939         /* in access mode mark mask and value are 0 to strip all vlans */
4940         if (bp->afex_vlan_mode == FUNC_MF_CFG_AFEX_VLAN_ACCESS_MODE) {
4941                 q_update_params->silent_removal_value = 0;
4942                 q_update_params->silent_removal_mask = 0;
4943         } else {
4944                 q_update_params->silent_removal_value =
4945                         (bp->afex_def_vlan_tag & VLAN_VID_MASK);
4946                 q_update_params->silent_removal_mask = VLAN_VID_MASK;
4947         }
4948
4949         for_each_eth_queue(bp, q) {
4950                 /* Set the appropriate Queue object */
4951                 fp = &bp->fp[q];
4952                 queue_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
4953
4954                 /* send the ramrod */
4955                 rc = bnx2x_queue_state_change(bp, &queue_params);
4956                 if (rc < 0)
4957                         BNX2X_ERR("Failed to config silent vlan rem for Q %d\n",
4958                                   q);
4959         }
4960
4961         if (!NO_FCOE(bp)) {
4962                 fp = &bp->fp[FCOE_IDX(bp)];
4963                 queue_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
4964
4965                 /* clear pending completion bit */
4966                 __clear_bit(RAMROD_COMP_WAIT, &queue_params.ramrod_flags);
4967
4968                 /* mark latest Q bit */
4969                 smp_mb__before_clear_bit();
4970                 set_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state);
4971                 smp_mb__after_clear_bit();
4972
4973                 /* send Q update ramrod for FCoE Q */
4974                 rc = bnx2x_queue_state_change(bp, &queue_params);
4975                 if (rc < 0)
4976                         BNX2X_ERR("Failed to config silent vlan rem for Q %d\n",
4977                                   q);
4978         } else {
4979                 /* If no FCoE ring - ACK MCP now */
4980                 bnx2x_link_report(bp);
4981                 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
4982         }
4983 }
4984
4985 static struct bnx2x_queue_sp_obj *bnx2x_cid_to_q_obj(
4986         struct bnx2x *bp, u32 cid)
4987 {
4988         DP(BNX2X_MSG_SP, "retrieving fp from cid %d\n", cid);
4989
4990         if (CNIC_LOADED(bp) && (cid == BNX2X_FCOE_ETH_CID(bp)))
4991                 return &bnx2x_fcoe_sp_obj(bp, q_obj);
4992         else
4993                 return &bp->sp_objs[CID_TO_FP(cid, bp)].q_obj;
4994 }
4995
4996 static void bnx2x_eq_int(struct bnx2x *bp)
4997 {
4998         u16 hw_cons, sw_cons, sw_prod;
4999         union event_ring_elem *elem;
5000         u8 echo;
5001         u32 cid;
5002         u8 opcode;
5003         int rc, spqe_cnt = 0;
5004         struct bnx2x_queue_sp_obj *q_obj;
5005         struct bnx2x_func_sp_obj *f_obj = &bp->func_obj;
5006         struct bnx2x_raw_obj *rss_raw = &bp->rss_conf_obj.raw;
5007
5008         hw_cons = le16_to_cpu(*bp->eq_cons_sb);
5009
5010         /* The hw_cos range is 1-255, 257 - the sw_cons range is 0-254, 256.
5011          * when we get the the next-page we nned to adjust so the loop
5012          * condition below will be met. The next element is the size of a
5013          * regular element and hence incrementing by 1
5014          */
5015         if ((hw_cons & EQ_DESC_MAX_PAGE) == EQ_DESC_MAX_PAGE)
5016                 hw_cons++;
5017
5018         /* This function may never run in parallel with itself for a
5019          * specific bp, thus there is no need in "paired" read memory
5020          * barrier here.
5021          */
5022         sw_cons = bp->eq_cons;
5023         sw_prod = bp->eq_prod;
5024
5025         DP(BNX2X_MSG_SP, "EQ:  hw_cons %u  sw_cons %u bp->eq_spq_left %x\n",
5026                         hw_cons, sw_cons, atomic_read(&bp->eq_spq_left));
5027
5028         for (; sw_cons != hw_cons;
5029               sw_prod = NEXT_EQ_IDX(sw_prod), sw_cons = NEXT_EQ_IDX(sw_cons)) {
5030
5031                 elem = &bp->eq_ring[EQ_DESC(sw_cons)];
5032
5033                 rc = bnx2x_iov_eq_sp_event(bp, elem);
5034                 if (!rc) {
5035                         DP(BNX2X_MSG_IOV, "bnx2x_iov_eq_sp_event returned %d\n",
5036                            rc);
5037                         goto next_spqe;
5038                 }
5039
5040                 /* elem CID originates from FW; actually LE */
5041                 cid = SW_CID((__force __le32)
5042                              elem->message.data.cfc_del_event.cid);
5043                 opcode = elem->message.opcode;
5044
5045                 /* handle eq element */
5046                 switch (opcode) {
5047                 case EVENT_RING_OPCODE_VF_PF_CHANNEL:
5048                         DP(BNX2X_MSG_IOV, "vf pf channel element on eq\n");
5049                         bnx2x_vf_mbx(bp, &elem->message.data.vf_pf_event);
5050                         continue;
5051
5052                 case EVENT_RING_OPCODE_STAT_QUERY:
5053                         DP(BNX2X_MSG_SP | BNX2X_MSG_STATS,
5054                            "got statistics comp event %d\n",
5055                            bp->stats_comp++);
5056                         /* nothing to do with stats comp */
5057                         goto next_spqe;
5058
5059                 case EVENT_RING_OPCODE_CFC_DEL:
5060                         /* handle according to cid range */
5061                         /*
5062                          * we may want to verify here that the bp state is
5063                          * HALTING
5064                          */
5065                         DP(BNX2X_MSG_SP,
5066                            "got delete ramrod for MULTI[%d]\n", cid);
5067
5068                         if (CNIC_LOADED(bp) &&
5069                             !bnx2x_cnic_handle_cfc_del(bp, cid, elem))
5070                                 goto next_spqe;
5071
5072                         q_obj = bnx2x_cid_to_q_obj(bp, cid);
5073
5074                         if (q_obj->complete_cmd(bp, q_obj, BNX2X_Q_CMD_CFC_DEL))
5075                                 break;
5076
5077
5078
5079                         goto next_spqe;
5080
5081                 case EVENT_RING_OPCODE_STOP_TRAFFIC:
5082                         DP(BNX2X_MSG_SP | BNX2X_MSG_DCB, "got STOP TRAFFIC\n");
5083                         if (f_obj->complete_cmd(bp, f_obj,
5084                                                 BNX2X_F_CMD_TX_STOP))
5085                                 break;
5086                         bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_PAUSED);
5087                         goto next_spqe;
5088
5089                 case EVENT_RING_OPCODE_START_TRAFFIC:
5090                         DP(BNX2X_MSG_SP | BNX2X_MSG_DCB, "got START TRAFFIC\n");
5091                         if (f_obj->complete_cmd(bp, f_obj,
5092                                                 BNX2X_F_CMD_TX_START))
5093                                 break;
5094                         bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_RELEASED);
5095                         goto next_spqe;
5096
5097                 case EVENT_RING_OPCODE_FUNCTION_UPDATE:
5098                         echo = elem->message.data.function_update_event.echo;
5099                         if (echo == SWITCH_UPDATE) {
5100                                 DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
5101                                    "got FUNC_SWITCH_UPDATE ramrod\n");
5102                                 if (f_obj->complete_cmd(
5103                                         bp, f_obj, BNX2X_F_CMD_SWITCH_UPDATE))
5104                                         break;
5105
5106                         } else {
5107                                 DP(BNX2X_MSG_SP | BNX2X_MSG_MCP,
5108                                    "AFEX: ramrod completed FUNCTION_UPDATE\n");
5109                                 f_obj->complete_cmd(bp, f_obj,
5110                                                     BNX2X_F_CMD_AFEX_UPDATE);
5111
5112                                 /* We will perform the Queues update from
5113                                  * sp_rtnl task as all Queue SP operations
5114                                  * should run under rtnl_lock.
5115                                  */
5116                                 smp_mb__before_clear_bit();
5117                                 set_bit(BNX2X_SP_RTNL_AFEX_F_UPDATE,
5118                                         &bp->sp_rtnl_state);
5119                                 smp_mb__after_clear_bit();
5120
5121                                 schedule_delayed_work(&bp->sp_rtnl_task, 0);
5122                         }
5123
5124                         goto next_spqe;
5125
5126                 case EVENT_RING_OPCODE_AFEX_VIF_LISTS:
5127                         f_obj->complete_cmd(bp, f_obj,
5128                                             BNX2X_F_CMD_AFEX_VIFLISTS);
5129                         bnx2x_after_afex_vif_lists(bp, elem);
5130                         goto next_spqe;
5131                 case EVENT_RING_OPCODE_FUNCTION_START:
5132                         DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
5133                            "got FUNC_START ramrod\n");
5134                         if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_START))
5135                                 break;
5136
5137                         goto next_spqe;
5138
5139                 case EVENT_RING_OPCODE_FUNCTION_STOP:
5140                         DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
5141                            "got FUNC_STOP ramrod\n");
5142                         if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_STOP))
5143                                 break;
5144
5145                         goto next_spqe;
5146                 }
5147
5148                 switch (opcode | bp->state) {
5149                 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
5150                       BNX2X_STATE_OPEN):
5151                 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
5152                       BNX2X_STATE_OPENING_WAIT4_PORT):
5153                         cid = elem->message.data.eth_event.echo &
5154                                 BNX2X_SWCID_MASK;
5155                         DP(BNX2X_MSG_SP, "got RSS_UPDATE ramrod. CID %d\n",
5156                            cid);
5157                         rss_raw->clear_pending(rss_raw);
5158                         break;
5159
5160                 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_OPEN):
5161                 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_DIAG):
5162                 case (EVENT_RING_OPCODE_SET_MAC |
5163                       BNX2X_STATE_CLOSING_WAIT4_HALT):
5164                 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
5165                       BNX2X_STATE_OPEN):
5166                 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
5167                       BNX2X_STATE_DIAG):
5168                 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
5169                       BNX2X_STATE_CLOSING_WAIT4_HALT):
5170                         DP(BNX2X_MSG_SP, "got (un)set mac ramrod\n");
5171                         bnx2x_handle_classification_eqe(bp, elem);
5172                         break;
5173
5174                 case (EVENT_RING_OPCODE_MULTICAST_RULES |
5175                       BNX2X_STATE_OPEN):
5176                 case (EVENT_RING_OPCODE_MULTICAST_RULES |
5177                       BNX2X_STATE_DIAG):
5178                 case (EVENT_RING_OPCODE_MULTICAST_RULES |
5179                       BNX2X_STATE_CLOSING_WAIT4_HALT):
5180                         DP(BNX2X_MSG_SP, "got mcast ramrod\n");
5181                         bnx2x_handle_mcast_eqe(bp);
5182                         break;
5183
5184                 case (EVENT_RING_OPCODE_FILTERS_RULES |
5185                       BNX2X_STATE_OPEN):
5186                 case (EVENT_RING_OPCODE_FILTERS_RULES |
5187                       BNX2X_STATE_DIAG):
5188                 case (EVENT_RING_OPCODE_FILTERS_RULES |
5189                       BNX2X_STATE_CLOSING_WAIT4_HALT):
5190                         DP(BNX2X_MSG_SP, "got rx_mode ramrod\n");
5191                         bnx2x_handle_rx_mode_eqe(bp);
5192                         break;
5193                 default:
5194                         /* unknown event log error and continue */
5195                         BNX2X_ERR("Unknown EQ event %d, bp->state 0x%x\n",
5196                                   elem->message.opcode, bp->state);
5197                 }
5198 next_spqe:
5199                 spqe_cnt++;
5200         } /* for */
5201
5202         smp_mb__before_atomic_inc();
5203         atomic_add(spqe_cnt, &bp->eq_spq_left);
5204
5205         bp->eq_cons = sw_cons;
5206         bp->eq_prod = sw_prod;
5207         /* Make sure that above mem writes were issued towards the memory */
5208         smp_wmb();
5209
5210         /* update producer */
5211         bnx2x_update_eq_prod(bp, bp->eq_prod);
5212 }
5213
5214 static void bnx2x_sp_task(struct work_struct *work)
5215 {
5216         struct bnx2x *bp = container_of(work, struct bnx2x, sp_task.work);
5217
5218         DP(BNX2X_MSG_SP, "sp task invoked\n");
5219
5220         /* make sure the atomic interupt_occurred has been written */
5221         smp_rmb();
5222         if (atomic_read(&bp->interrupt_occurred)) {
5223
5224                 /* what work needs to be performed? */
5225                 u16 status = bnx2x_update_dsb_idx(bp);
5226
5227                 DP(BNX2X_MSG_SP, "status %x\n", status);
5228                 DP(BNX2X_MSG_SP, "setting interrupt_occurred to 0\n");
5229                 atomic_set(&bp->interrupt_occurred, 0);
5230
5231                 /* HW attentions */
5232                 if (status & BNX2X_DEF_SB_ATT_IDX) {
5233                         bnx2x_attn_int(bp);
5234                         status &= ~BNX2X_DEF_SB_ATT_IDX;
5235                 }
5236
5237                 /* SP events: STAT_QUERY and others */
5238                 if (status & BNX2X_DEF_SB_IDX) {
5239                         struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp);
5240
5241                 if (FCOE_INIT(bp) &&
5242                             (bnx2x_has_rx_work(fp) || bnx2x_has_tx_work(fp))) {
5243                                 /* Prevent local bottom-halves from running as
5244                                  * we are going to change the local NAPI list.
5245                                  */
5246                                 local_bh_disable();
5247                                 napi_schedule(&bnx2x_fcoe(bp, napi));
5248                                 local_bh_enable();
5249                         }
5250
5251                         /* Handle EQ completions */
5252                         bnx2x_eq_int(bp);
5253                         bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID,
5254                                      le16_to_cpu(bp->def_idx), IGU_INT_NOP, 1);
5255
5256                         status &= ~BNX2X_DEF_SB_IDX;
5257                 }
5258
5259                 /* if status is non zero then perhaps something went wrong */
5260                 if (unlikely(status))
5261                         DP(BNX2X_MSG_SP,
5262                            "got an unknown interrupt! (status 0x%x)\n", status);
5263
5264                 /* ack status block only if something was actually handled */
5265                 bnx2x_ack_sb(bp, bp->igu_dsb_id, ATTENTION_ID,
5266                              le16_to_cpu(bp->def_att_idx), IGU_INT_ENABLE, 1);
5267
5268         }
5269
5270         /* must be called after the EQ processing (since eq leads to sriov
5271          * ramrod completion flows).
5272          * This flow may have been scheduled by the arrival of a ramrod
5273          * completion, or by the sriov code rescheduling itself.
5274          */
5275         bnx2x_iov_sp_task(bp);
5276
5277         /* afex - poll to check if VIFSET_ACK should be sent to MFW */
5278         if (test_and_clear_bit(BNX2X_AFEX_PENDING_VIFSET_MCP_ACK,
5279                                &bp->sp_state)) {
5280                 bnx2x_link_report(bp);
5281                 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
5282         }
5283 }
5284
5285 irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance)
5286 {
5287         struct net_device *dev = dev_instance;
5288         struct bnx2x *bp = netdev_priv(dev);
5289
5290         bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0,
5291                      IGU_INT_DISABLE, 0);
5292
5293 #ifdef BNX2X_STOP_ON_ERROR
5294         if (unlikely(bp->panic))
5295                 return IRQ_HANDLED;
5296 #endif
5297
5298         if (CNIC_LOADED(bp)) {
5299                 struct cnic_ops *c_ops;
5300
5301                 rcu_read_lock();
5302                 c_ops = rcu_dereference(bp->cnic_ops);
5303                 if (c_ops)
5304                         c_ops->cnic_handler(bp->cnic_data, NULL);
5305                 rcu_read_unlock();
5306         }
5307
5308         /* schedule sp task to perform default status block work, ack
5309          * attentions and enable interrupts.
5310          */
5311         bnx2x_schedule_sp_task(bp);
5312
5313         return IRQ_HANDLED;
5314 }
5315
5316 /* end of slow path */
5317
5318
5319 void bnx2x_drv_pulse(struct bnx2x *bp)
5320 {
5321         SHMEM_WR(bp, func_mb[BP_FW_MB_IDX(bp)].drv_pulse_mb,
5322                  bp->fw_drv_pulse_wr_seq);
5323 }
5324
5325 static void bnx2x_timer(unsigned long data)
5326 {
5327         struct bnx2x *bp = (struct bnx2x *) data;
5328
5329         if (!netif_running(bp->dev))
5330                 return;
5331
5332         if (IS_PF(bp) &&
5333             !BP_NOMCP(bp)) {
5334                 int mb_idx = BP_FW_MB_IDX(bp);
5335                 u32 drv_pulse;
5336                 u32 mcp_pulse;
5337
5338                 ++bp->fw_drv_pulse_wr_seq;
5339                 bp->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK;
5340                 /* TBD - add SYSTEM_TIME */
5341                 drv_pulse = bp->fw_drv_pulse_wr_seq;
5342                 bnx2x_drv_pulse(bp);
5343
5344                 mcp_pulse = (SHMEM_RD(bp, func_mb[mb_idx].mcp_pulse_mb) &
5345                              MCP_PULSE_SEQ_MASK);
5346                 /* The delta between driver pulse and mcp response
5347                  * should be 1 (before mcp response) or 0 (after mcp response)
5348                  */
5349                 if ((drv_pulse != mcp_pulse) &&
5350                     (drv_pulse != ((mcp_pulse + 1) & MCP_PULSE_SEQ_MASK))) {
5351                         /* someone lost a heartbeat... */
5352                         BNX2X_ERR("drv_pulse (0x%x) != mcp_pulse (0x%x)\n",
5353                                   drv_pulse, mcp_pulse);
5354                 }
5355         }
5356
5357         if (bp->state == BNX2X_STATE_OPEN)
5358                 bnx2x_stats_handle(bp, STATS_EVENT_UPDATE);
5359
5360         /* sample pf vf bulletin board for new posts from pf */
5361         if (IS_VF(bp))
5362                 bnx2x_sample_bulletin(bp);
5363
5364         mod_timer(&bp->timer, jiffies + bp->current_interval);
5365 }
5366
5367 /* end of Statistics */
5368
5369 /* nic init */
5370
5371 /*
5372  * nic init service functions
5373  */
5374
5375 static void bnx2x_fill(struct bnx2x *bp, u32 addr, int fill, u32 len)
5376 {
5377         u32 i;
5378         if (!(len%4) && !(addr%4))
5379                 for (i = 0; i < len; i += 4)
5380                         REG_WR(bp, addr + i, fill);
5381         else
5382                 for (i = 0; i < len; i++)
5383                         REG_WR8(bp, addr + i, fill);
5384
5385 }
5386
5387 /* helper: writes FP SP data to FW - data_size in dwords */
5388 static void bnx2x_wr_fp_sb_data(struct bnx2x *bp,
5389                                 int fw_sb_id,
5390                                 u32 *sb_data_p,
5391                                 u32 data_size)
5392 {
5393         int index;
5394         for (index = 0; index < data_size; index++)
5395                 REG_WR(bp, BAR_CSTRORM_INTMEM +
5396                         CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) +
5397                         sizeof(u32)*index,
5398                         *(sb_data_p + index));
5399 }
5400
5401 static void bnx2x_zero_fp_sb(struct bnx2x *bp, int fw_sb_id)
5402 {
5403         u32 *sb_data_p;
5404         u32 data_size = 0;
5405         struct hc_status_block_data_e2 sb_data_e2;
5406         struct hc_status_block_data_e1x sb_data_e1x;
5407
5408         /* disable the function first */
5409         if (!CHIP_IS_E1x(bp)) {
5410                 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
5411                 sb_data_e2.common.state = SB_DISABLED;
5412                 sb_data_e2.common.p_func.vf_valid = false;
5413                 sb_data_p = (u32 *)&sb_data_e2;
5414                 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
5415         } else {
5416                 memset(&sb_data_e1x, 0,
5417                        sizeof(struct hc_status_block_data_e1x));
5418                 sb_data_e1x.common.state = SB_DISABLED;
5419                 sb_data_e1x.common.p_func.vf_valid = false;
5420                 sb_data_p = (u32 *)&sb_data_e1x;
5421                 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
5422         }
5423         bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
5424
5425         bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5426                         CSTORM_STATUS_BLOCK_OFFSET(fw_sb_id), 0,
5427                         CSTORM_STATUS_BLOCK_SIZE);
5428         bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5429                         CSTORM_SYNC_BLOCK_OFFSET(fw_sb_id), 0,
5430                         CSTORM_SYNC_BLOCK_SIZE);
5431 }
5432
5433 /* helper:  writes SP SB data to FW */
5434 static void bnx2x_wr_sp_sb_data(struct bnx2x *bp,
5435                 struct hc_sp_status_block_data *sp_sb_data)
5436 {
5437         int func = BP_FUNC(bp);
5438         int i;
5439         for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++)
5440                 REG_WR(bp, BAR_CSTRORM_INTMEM +
5441                         CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) +
5442                         i*sizeof(u32),
5443                         *((u32 *)sp_sb_data + i));
5444 }
5445
5446 static void bnx2x_zero_sp_sb(struct bnx2x *bp)
5447 {
5448         int func = BP_FUNC(bp);
5449         struct hc_sp_status_block_data sp_sb_data;
5450         memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
5451
5452         sp_sb_data.state = SB_DISABLED;
5453         sp_sb_data.p_func.vf_valid = false;
5454
5455         bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
5456
5457         bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5458                         CSTORM_SP_STATUS_BLOCK_OFFSET(func), 0,
5459                         CSTORM_SP_STATUS_BLOCK_SIZE);
5460         bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5461                         CSTORM_SP_SYNC_BLOCK_OFFSET(func), 0,
5462                         CSTORM_SP_SYNC_BLOCK_SIZE);
5463
5464 }
5465
5466
5467 static void bnx2x_setup_ndsb_state_machine(struct hc_status_block_sm *hc_sm,
5468                                            int igu_sb_id, int igu_seg_id)
5469 {
5470         hc_sm->igu_sb_id = igu_sb_id;
5471         hc_sm->igu_seg_id = igu_seg_id;
5472         hc_sm->timer_value = 0xFF;
5473         hc_sm->time_to_expire = 0xFFFFFFFF;
5474 }
5475
5476
5477 /* allocates state machine ids. */
5478 static void bnx2x_map_sb_state_machines(struct hc_index_data *index_data)
5479 {
5480         /* zero out state machine indices */
5481         /* rx indices */
5482         index_data[HC_INDEX_ETH_RX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
5483
5484         /* tx indices */
5485         index_data[HC_INDEX_OOO_TX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
5486         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags &= ~HC_INDEX_DATA_SM_ID;
5487         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags &= ~HC_INDEX_DATA_SM_ID;
5488         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags &= ~HC_INDEX_DATA_SM_ID;
5489
5490         /* map indices */
5491         /* rx indices */
5492         index_data[HC_INDEX_ETH_RX_CQ_CONS].flags |=
5493                 SM_RX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5494
5495         /* tx indices */
5496         index_data[HC_INDEX_OOO_TX_CQ_CONS].flags |=
5497                 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5498         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags |=
5499                 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5500         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags |=
5501                 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5502         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags |=
5503                 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5504 }
5505
5506 void bnx2x_init_sb(struct bnx2x *bp, dma_addr_t mapping, int vfid,
5507                           u8 vf_valid, int fw_sb_id, int igu_sb_id)
5508 {
5509         int igu_seg_id;
5510
5511         struct hc_status_block_data_e2 sb_data_e2;
5512         struct hc_status_block_data_e1x sb_data_e1x;
5513         struct hc_status_block_sm  *hc_sm_p;
5514         int data_size;
5515         u32 *sb_data_p;
5516
5517         if (CHIP_INT_MODE_IS_BC(bp))
5518                 igu_seg_id = HC_SEG_ACCESS_NORM;
5519         else
5520                 igu_seg_id = IGU_SEG_ACCESS_NORM;
5521
5522         bnx2x_zero_fp_sb(bp, fw_sb_id);
5523
5524         if (!CHIP_IS_E1x(bp)) {
5525                 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
5526                 sb_data_e2.common.state = SB_ENABLED;
5527                 sb_data_e2.common.p_func.pf_id = BP_FUNC(bp);
5528                 sb_data_e2.common.p_func.vf_id = vfid;
5529                 sb_data_e2.common.p_func.vf_valid = vf_valid;
5530                 sb_data_e2.common.p_func.vnic_id = BP_VN(bp);
5531                 sb_data_e2.common.same_igu_sb_1b = true;
5532                 sb_data_e2.common.host_sb_addr.hi = U64_HI(mapping);
5533                 sb_data_e2.common.host_sb_addr.lo = U64_LO(mapping);
5534                 hc_sm_p = sb_data_e2.common.state_machine;
5535                 sb_data_p = (u32 *)&sb_data_e2;
5536                 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
5537                 bnx2x_map_sb_state_machines(sb_data_e2.index_data);
5538         } else {
5539                 memset(&sb_data_e1x, 0,
5540                        sizeof(struct hc_status_block_data_e1x));
5541                 sb_data_e1x.common.state = SB_ENABLED;
5542                 sb_data_e1x.common.p_func.pf_id = BP_FUNC(bp);
5543                 sb_data_e1x.common.p_func.vf_id = 0xff;
5544                 sb_data_e1x.common.p_func.vf_valid = false;
5545                 sb_data_e1x.common.p_func.vnic_id = BP_VN(bp);
5546                 sb_data_e1x.common.same_igu_sb_1b = true;
5547                 sb_data_e1x.common.host_sb_addr.hi = U64_HI(mapping);
5548                 sb_data_e1x.common.host_sb_addr.lo = U64_LO(mapping);
5549                 hc_sm_p = sb_data_e1x.common.state_machine;
5550                 sb_data_p = (u32 *)&sb_data_e1x;
5551                 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
5552                 bnx2x_map_sb_state_machines(sb_data_e1x.index_data);
5553         }
5554
5555         bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_RX_ID],
5556                                        igu_sb_id, igu_seg_id);
5557         bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_TX_ID],
5558                                        igu_sb_id, igu_seg_id);
5559
5560         DP(NETIF_MSG_IFUP, "Init FW SB %d\n", fw_sb_id);
5561
5562         /* write indices to HW - PCI guarantees endianity of regpairs */
5563         bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
5564 }
5565
5566 static void bnx2x_update_coalesce_sb(struct bnx2x *bp, u8 fw_sb_id,
5567                                      u16 tx_usec, u16 rx_usec)
5568 {
5569         bnx2x_update_coalesce_sb_index(bp, fw_sb_id, HC_INDEX_ETH_RX_CQ_CONS,
5570                                     false, rx_usec);
5571         bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
5572                                        HC_INDEX_ETH_TX_CQ_CONS_COS0, false,
5573                                        tx_usec);
5574         bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
5575                                        HC_INDEX_ETH_TX_CQ_CONS_COS1, false,
5576                                        tx_usec);
5577         bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
5578                                        HC_INDEX_ETH_TX_CQ_CONS_COS2, false,
5579                                        tx_usec);
5580 }
5581
5582 static void bnx2x_init_def_sb(struct bnx2x *bp)
5583 {
5584         struct host_sp_status_block *def_sb = bp->def_status_blk;
5585         dma_addr_t mapping = bp->def_status_blk_mapping;
5586         int igu_sp_sb_index;
5587         int igu_seg_id;
5588         int port = BP_PORT(bp);
5589         int func = BP_FUNC(bp);
5590         int reg_offset, reg_offset_en5;
5591         u64 section;
5592         int index;
5593         struct hc_sp_status_block_data sp_sb_data;
5594         memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
5595
5596         if (CHIP_INT_MODE_IS_BC(bp)) {
5597                 igu_sp_sb_index = DEF_SB_IGU_ID;
5598                 igu_seg_id = HC_SEG_ACCESS_DEF;
5599         } else {
5600                 igu_sp_sb_index = bp->igu_dsb_id;
5601                 igu_seg_id = IGU_SEG_ACCESS_DEF;
5602         }
5603
5604         /* ATTN */
5605         section = ((u64)mapping) + offsetof(struct host_sp_status_block,
5606                                             atten_status_block);
5607         def_sb->atten_status_block.status_block_id = igu_sp_sb_index;
5608
5609         bp->attn_state = 0;
5610
5611         reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
5612                              MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
5613         reg_offset_en5 = (port ? MISC_REG_AEU_ENABLE5_FUNC_1_OUT_0 :
5614                                  MISC_REG_AEU_ENABLE5_FUNC_0_OUT_0);
5615         for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
5616                 int sindex;
5617                 /* take care of sig[0]..sig[4] */
5618                 for (sindex = 0; sindex < 4; sindex++)
5619                         bp->attn_group[index].sig[sindex] =
5620                            REG_RD(bp, reg_offset + sindex*0x4 + 0x10*index);
5621
5622                 if (!CHIP_IS_E1x(bp))
5623                         /*
5624                          * enable5 is separate from the rest of the registers,
5625                          * and therefore the address skip is 4
5626                          * and not 16 between the different groups
5627                          */
5628                         bp->attn_group[index].sig[4] = REG_RD(bp,
5629                                         reg_offset_en5 + 0x4*index);
5630                 else
5631                         bp->attn_group[index].sig[4] = 0;
5632         }
5633
5634         if (bp->common.int_block == INT_BLOCK_HC) {
5635                 reg_offset = (port ? HC_REG_ATTN_MSG1_ADDR_L :
5636                                      HC_REG_ATTN_MSG0_ADDR_L);
5637
5638                 REG_WR(bp, reg_offset, U64_LO(section));
5639                 REG_WR(bp, reg_offset + 4, U64_HI(section));
5640         } else if (!CHIP_IS_E1x(bp)) {
5641                 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_L, U64_LO(section));
5642                 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_H, U64_HI(section));
5643         }
5644
5645         section = ((u64)mapping) + offsetof(struct host_sp_status_block,
5646                                             sp_sb);
5647
5648         bnx2x_zero_sp_sb(bp);
5649
5650         /* PCI guarantees endianity of regpairs */
5651         sp_sb_data.state                = SB_ENABLED;
5652         sp_sb_data.host_sb_addr.lo      = U64_LO(section);
5653         sp_sb_data.host_sb_addr.hi      = U64_HI(section);
5654         sp_sb_data.igu_sb_id            = igu_sp_sb_index;
5655         sp_sb_data.igu_seg_id           = igu_seg_id;
5656         sp_sb_data.p_func.pf_id         = func;
5657         sp_sb_data.p_func.vnic_id       = BP_VN(bp);
5658         sp_sb_data.p_func.vf_id         = 0xff;
5659
5660         bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
5661
5662         bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0);
5663 }
5664
5665 void bnx2x_update_coalesce(struct bnx2x *bp)
5666 {
5667         int i;
5668
5669         for_each_eth_queue(bp, i)
5670                 bnx2x_update_coalesce_sb(bp, bp->fp[i].fw_sb_id,
5671                                          bp->tx_ticks, bp->rx_ticks);
5672 }
5673
5674 static void bnx2x_init_sp_ring(struct bnx2x *bp)
5675 {
5676         spin_lock_init(&bp->spq_lock);
5677         atomic_set(&bp->cq_spq_left, MAX_SPQ_PENDING);
5678
5679         bp->spq_prod_idx = 0;
5680         bp->dsb_sp_prod = BNX2X_SP_DSB_INDEX;
5681         bp->spq_prod_bd = bp->spq;
5682         bp->spq_last_bd = bp->spq_prod_bd + MAX_SP_DESC_CNT;
5683 }
5684
5685 static void bnx2x_init_eq_ring(struct bnx2x *bp)
5686 {
5687         int i;
5688         for (i = 1; i <= NUM_EQ_PAGES; i++) {
5689                 union event_ring_elem *elem =
5690                         &bp->eq_ring[EQ_DESC_CNT_PAGE * i - 1];
5691
5692                 elem->next_page.addr.hi =
5693                         cpu_to_le32(U64_HI(bp->eq_mapping +
5694                                    BCM_PAGE_SIZE * (i % NUM_EQ_PAGES)));
5695                 elem->next_page.addr.lo =
5696                         cpu_to_le32(U64_LO(bp->eq_mapping +
5697                                    BCM_PAGE_SIZE*(i % NUM_EQ_PAGES)));
5698         }
5699         bp->eq_cons = 0;
5700         bp->eq_prod = NUM_EQ_DESC;
5701         bp->eq_cons_sb = BNX2X_EQ_INDEX;
5702         /* we want a warning message before it gets rought... */
5703         atomic_set(&bp->eq_spq_left,
5704                 min_t(int, MAX_SP_DESC_CNT - MAX_SPQ_PENDING, NUM_EQ_DESC) - 1);
5705 }
5706
5707 /* called with netif_addr_lock_bh() */
5708 int bnx2x_set_q_rx_mode(struct bnx2x *bp, u8 cl_id,
5709                         unsigned long rx_mode_flags,
5710                         unsigned long rx_accept_flags,
5711                         unsigned long tx_accept_flags,
5712                         unsigned long ramrod_flags)
5713 {
5714         struct bnx2x_rx_mode_ramrod_params ramrod_param;
5715         int rc;
5716
5717         memset(&ramrod_param, 0, sizeof(ramrod_param));
5718
5719         /* Prepare ramrod parameters */
5720         ramrod_param.cid = 0;
5721         ramrod_param.cl_id = cl_id;
5722         ramrod_param.rx_mode_obj = &bp->rx_mode_obj;
5723         ramrod_param.func_id = BP_FUNC(bp);
5724
5725         ramrod_param.pstate = &bp->sp_state;
5726         ramrod_param.state = BNX2X_FILTER_RX_MODE_PENDING;
5727
5728         ramrod_param.rdata = bnx2x_sp(bp, rx_mode_rdata);
5729         ramrod_param.rdata_mapping = bnx2x_sp_mapping(bp, rx_mode_rdata);
5730
5731         set_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state);
5732
5733         ramrod_param.ramrod_flags = ramrod_flags;
5734         ramrod_param.rx_mode_flags = rx_mode_flags;
5735
5736         ramrod_param.rx_accept_flags = rx_accept_flags;
5737         ramrod_param.tx_accept_flags = tx_accept_flags;
5738
5739         rc = bnx2x_config_rx_mode(bp, &ramrod_param);
5740         if (rc < 0) {
5741                 BNX2X_ERR("Set rx_mode %d failed\n", bp->rx_mode);
5742                 return rc;
5743         }
5744
5745         return 0;
5746 }
5747
5748 static int bnx2x_fill_accept_flags(struct bnx2x *bp, u32 rx_mode,
5749                                    unsigned long *rx_accept_flags,
5750                                    unsigned long *tx_accept_flags)
5751 {
5752         /* Clear the flags first */
5753         *rx_accept_flags = 0;
5754         *tx_accept_flags = 0;
5755
5756         switch (rx_mode) {
5757         case BNX2X_RX_MODE_NONE:
5758                 /*
5759                  * 'drop all' supersedes any accept flags that may have been
5760                  * passed to the function.
5761                  */
5762                 break;
5763         case BNX2X_RX_MODE_NORMAL:
5764                 __set_bit(BNX2X_ACCEPT_UNICAST, rx_accept_flags);
5765                 __set_bit(BNX2X_ACCEPT_MULTICAST, rx_accept_flags);
5766                 __set_bit(BNX2X_ACCEPT_BROADCAST, rx_accept_flags);
5767
5768                 /* internal switching mode */
5769                 __set_bit(BNX2X_ACCEPT_UNICAST, tx_accept_flags);
5770                 __set_bit(BNX2X_ACCEPT_MULTICAST, tx_accept_flags);
5771                 __set_bit(BNX2X_ACCEPT_BROADCAST, tx_accept_flags);
5772
5773                 break;
5774         case BNX2X_RX_MODE_ALLMULTI:
5775                 __set_bit(BNX2X_ACCEPT_UNICAST, rx_accept_flags);
5776                 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, rx_accept_flags);
5777                 __set_bit(BNX2X_ACCEPT_BROADCAST, rx_accept_flags);
5778
5779                 /* internal switching mode */
5780                 __set_bit(BNX2X_ACCEPT_UNICAST, tx_accept_flags);
5781                 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, tx_accept_flags);
5782                 __set_bit(BNX2X_ACCEPT_BROADCAST, tx_accept_flags);
5783
5784                 break;
5785         case BNX2X_RX_MODE_PROMISC:
5786                 /* According to deffinition of SI mode, iface in promisc mode
5787                  * should receive matched and unmatched (in resolution of port)
5788                  * unicast packets.
5789                  */
5790                 __set_bit(BNX2X_ACCEPT_UNMATCHED, rx_accept_flags);
5791                 __set_bit(BNX2X_ACCEPT_UNICAST, rx_accept_flags);
5792                 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, rx_accept_flags);
5793                 __set_bit(BNX2X_ACCEPT_BROADCAST, rx_accept_flags);
5794
5795                 /* internal switching mode */
5796                 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, tx_accept_flags);
5797                 __set_bit(BNX2X_ACCEPT_BROADCAST, tx_accept_flags);
5798
5799                 if (IS_MF_SI(bp))
5800                         __set_bit(BNX2X_ACCEPT_ALL_UNICAST, tx_accept_flags);
5801                 else
5802                         __set_bit(BNX2X_ACCEPT_UNICAST, tx_accept_flags);
5803
5804                 break;
5805         default:
5806                 BNX2X_ERR("Unknown rx_mode: %d\n", rx_mode);
5807                 return -EINVAL;
5808         }
5809
5810         /* Set ACCEPT_ANY_VLAN as we do not enable filtering by VLAN */
5811         if (bp->rx_mode != BNX2X_RX_MODE_NONE) {
5812                 __set_bit(BNX2X_ACCEPT_ANY_VLAN, rx_accept_flags);
5813                 __set_bit(BNX2X_ACCEPT_ANY_VLAN, tx_accept_flags);
5814         }
5815
5816         return 0;
5817 }
5818
5819 /* called with netif_addr_lock_bh() */
5820 int bnx2x_set_storm_rx_mode(struct bnx2x *bp)
5821 {
5822         unsigned long rx_mode_flags = 0, ramrod_flags = 0;
5823         unsigned long rx_accept_flags = 0, tx_accept_flags = 0;
5824         int rc;
5825
5826         if (!NO_FCOE(bp))
5827                 /* Configure rx_mode of FCoE Queue */
5828                 __set_bit(BNX2X_RX_MODE_FCOE_ETH, &rx_mode_flags);
5829
5830         rc = bnx2x_fill_accept_flags(bp, bp->rx_mode, &rx_accept_flags,
5831                                      &tx_accept_flags);
5832         if (rc)
5833                 return rc;
5834
5835         __set_bit(RAMROD_RX, &ramrod_flags);
5836         __set_bit(RAMROD_TX, &ramrod_flags);
5837
5838         return bnx2x_set_q_rx_mode(bp, bp->fp->cl_id, rx_mode_flags,
5839                                    rx_accept_flags, tx_accept_flags,
5840                                    ramrod_flags);
5841 }
5842
5843 static void bnx2x_init_internal_common(struct bnx2x *bp)
5844 {
5845         int i;
5846
5847         if (IS_MF_SI(bp))
5848                 /*
5849                  * In switch independent mode, the TSTORM needs to accept
5850                  * packets that failed classification, since approximate match
5851                  * mac addresses aren't written to NIG LLH
5852                  */
5853                 REG_WR8(bp, BAR_TSTRORM_INTMEM +
5854                             TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET, 2);
5855         else if (!CHIP_IS_E1(bp)) /* 57710 doesn't support MF */
5856                 REG_WR8(bp, BAR_TSTRORM_INTMEM +
5857                             TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET, 0);
5858
5859         /* Zero this manually as its initialization is
5860            currently missing in the initTool */
5861         for (i = 0; i < (USTORM_AGG_DATA_SIZE >> 2); i++)
5862                 REG_WR(bp, BAR_USTRORM_INTMEM +
5863                        USTORM_AGG_DATA_OFFSET + i * 4, 0);
5864         if (!CHIP_IS_E1x(bp)) {
5865                 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_IGU_MODE_OFFSET,
5866                         CHIP_INT_MODE_IS_BC(bp) ?
5867                         HC_IGU_BC_MODE : HC_IGU_NBC_MODE);
5868         }
5869 }
5870
5871 static void bnx2x_init_internal(struct bnx2x *bp, u32 load_code)
5872 {
5873         switch (load_code) {
5874         case FW_MSG_CODE_DRV_LOAD_COMMON:
5875         case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP:
5876                 bnx2x_init_internal_common(bp);
5877                 /* no break */
5878
5879         case FW_MSG_CODE_DRV_LOAD_PORT:
5880                 /* nothing to do */
5881                 /* no break */
5882
5883         case FW_MSG_CODE_DRV_LOAD_FUNCTION:
5884                 /* internal memory per function is
5885                    initialized inside bnx2x_pf_init */
5886                 break;
5887
5888         default:
5889                 BNX2X_ERR("Unknown load_code (0x%x) from MCP\n", load_code);
5890                 break;
5891         }
5892 }
5893
5894 static inline u8 bnx2x_fp_igu_sb_id(struct bnx2x_fastpath *fp)
5895 {
5896         return fp->bp->igu_base_sb + fp->index + CNIC_SUPPORT(fp->bp);
5897 }
5898
5899 static inline u8 bnx2x_fp_fw_sb_id(struct bnx2x_fastpath *fp)
5900 {
5901         return fp->bp->base_fw_ndsb + fp->index + CNIC_SUPPORT(fp->bp);
5902 }
5903
5904 static u8 bnx2x_fp_cl_id(struct bnx2x_fastpath *fp)
5905 {
5906         if (CHIP_IS_E1x(fp->bp))
5907                 return BP_L_ID(fp->bp) + fp->index;
5908         else    /* We want Client ID to be the same as IGU SB ID for 57712 */
5909                 return bnx2x_fp_igu_sb_id(fp);
5910 }
5911
5912 static void bnx2x_init_eth_fp(struct bnx2x *bp, int fp_idx)
5913 {
5914         struct bnx2x_fastpath *fp = &bp->fp[fp_idx];
5915         u8 cos;
5916         unsigned long q_type = 0;
5917         u32 cids[BNX2X_MULTI_TX_COS] = { 0 };
5918         fp->rx_queue = fp_idx;
5919         fp->cid = fp_idx;
5920         fp->cl_id = bnx2x_fp_cl_id(fp);
5921         fp->fw_sb_id = bnx2x_fp_fw_sb_id(fp);
5922         fp->igu_sb_id = bnx2x_fp_igu_sb_id(fp);
5923         /* qZone id equals to FW (per path) client id */
5924         fp->cl_qzone_id  = bnx2x_fp_qzone_id(fp);
5925
5926         /* init shortcut */
5927         fp->ustorm_rx_prods_offset = bnx2x_rx_ustorm_prods_offset(fp);
5928
5929         /* Setup SB indicies */
5930         fp->rx_cons_sb = BNX2X_RX_SB_INDEX;
5931
5932         /* Configure Queue State object */
5933         __set_bit(BNX2X_Q_TYPE_HAS_RX, &q_type);
5934         __set_bit(BNX2X_Q_TYPE_HAS_TX, &q_type);
5935
5936         BUG_ON(fp->max_cos > BNX2X_MULTI_TX_COS);
5937
5938         /* init tx data */
5939         for_each_cos_in_tx_queue(fp, cos) {
5940                 bnx2x_init_txdata(bp, fp->txdata_ptr[cos],
5941                                   CID_COS_TO_TX_ONLY_CID(fp->cid, cos, bp),
5942                                   FP_COS_TO_TXQ(fp, cos, bp),
5943                                   BNX2X_TX_SB_INDEX_BASE + cos, fp);
5944                 cids[cos] = fp->txdata_ptr[cos]->cid;
5945         }
5946
5947         /* nothing more for vf to do here */
5948         if (IS_VF(bp))
5949                 return;
5950
5951         bnx2x_init_sb(bp, fp->status_blk_mapping, BNX2X_VF_ID_INVALID, false,
5952                       fp->fw_sb_id, fp->igu_sb_id);
5953         bnx2x_update_fpsb_idx(fp);
5954         bnx2x_init_queue_obj(bp, &bnx2x_sp_obj(bp, fp).q_obj, fp->cl_id, cids,
5955                              fp->max_cos, BP_FUNC(bp), bnx2x_sp(bp, q_rdata),
5956                              bnx2x_sp_mapping(bp, q_rdata), q_type);
5957
5958         /**
5959          * Configure classification DBs: Always enable Tx switching
5960          */
5961         bnx2x_init_vlan_mac_fp_objs(fp, BNX2X_OBJ_TYPE_RX_TX);
5962
5963         DP(NETIF_MSG_IFUP,
5964            "queue[%d]:  bnx2x_init_sb(%p,%p)  cl_id %d  fw_sb %d  igu_sb %d\n",
5965            fp_idx, bp, fp->status_blk.e2_sb, fp->cl_id, fp->fw_sb_id,
5966            fp->igu_sb_id);
5967 }
5968
5969 static void bnx2x_init_tx_ring_one(struct bnx2x_fp_txdata *txdata)
5970 {
5971         int i;
5972
5973         for (i = 1; i <= NUM_TX_RINGS; i++) {
5974                 struct eth_tx_next_bd *tx_next_bd =
5975                         &txdata->tx_desc_ring[TX_DESC_CNT * i - 1].next_bd;
5976
5977                 tx_next_bd->addr_hi =
5978                         cpu_to_le32(U64_HI(txdata->tx_desc_mapping +
5979                                     BCM_PAGE_SIZE*(i % NUM_TX_RINGS)));
5980                 tx_next_bd->addr_lo =
5981                         cpu_to_le32(U64_LO(txdata->tx_desc_mapping +
5982                                     BCM_PAGE_SIZE*(i % NUM_TX_RINGS)));
5983         }
5984
5985         SET_FLAG(txdata->tx_db.data.header.header, DOORBELL_HDR_DB_TYPE, 1);
5986         txdata->tx_db.data.zero_fill1 = 0;
5987         txdata->tx_db.data.prod = 0;
5988
5989         txdata->tx_pkt_prod = 0;
5990         txdata->tx_pkt_cons = 0;
5991         txdata->tx_bd_prod = 0;
5992         txdata->tx_bd_cons = 0;
5993         txdata->tx_pkt = 0;
5994 }
5995
5996 static void bnx2x_init_tx_rings_cnic(struct bnx2x *bp)
5997 {
5998         int i;
5999
6000         for_each_tx_queue_cnic(bp, i)
6001                 bnx2x_init_tx_ring_one(bp->fp[i].txdata_ptr[0]);
6002 }
6003 static void bnx2x_init_tx_rings(struct bnx2x *bp)
6004 {
6005         int i;
6006         u8 cos;
6007
6008         for_each_eth_queue(bp, i)
6009                 for_each_cos_in_tx_queue(&bp->fp[i], cos)
6010                         bnx2x_init_tx_ring_one(bp->fp[i].txdata_ptr[cos]);
6011 }
6012
6013 void bnx2x_nic_init_cnic(struct bnx2x *bp)
6014 {
6015         if (!NO_FCOE(bp))
6016                 bnx2x_init_fcoe_fp(bp);
6017
6018         bnx2x_init_sb(bp, bp->cnic_sb_mapping,
6019                       BNX2X_VF_ID_INVALID, false,
6020                       bnx2x_cnic_fw_sb_id(bp), bnx2x_cnic_igu_sb_id(bp));
6021
6022         /* ensure status block indices were read */
6023         rmb();
6024         bnx2x_init_rx_rings_cnic(bp);
6025         bnx2x_init_tx_rings_cnic(bp);
6026
6027         /* flush all */
6028         mb();
6029         mmiowb();
6030 }
6031
6032 void bnx2x_nic_init(struct bnx2x *bp, u32 load_code)
6033 {
6034         int i;
6035
6036         for_each_eth_queue(bp, i)
6037                 bnx2x_init_eth_fp(bp, i);
6038
6039         /* ensure status block indices were read */
6040         rmb();
6041         bnx2x_init_rx_rings(bp);
6042         bnx2x_init_tx_rings(bp);
6043
6044         if (IS_VF(bp))
6045                 return;
6046
6047         /* Initialize MOD_ABS interrupts */
6048         bnx2x_init_mod_abs_int(bp, &bp->link_vars, bp->common.chip_id,
6049                                bp->common.shmem_base, bp->common.shmem2_base,
6050                                BP_PORT(bp));
6051
6052         bnx2x_init_def_sb(bp);
6053         bnx2x_update_dsb_idx(bp);
6054         bnx2x_init_sp_ring(bp);
6055         bnx2x_init_eq_ring(bp);
6056         bnx2x_init_internal(bp, load_code);
6057         bnx2x_pf_init(bp);
6058         bnx2x_stats_init(bp);
6059
6060         /* flush all before enabling interrupts */
6061         mb();
6062         mmiowb();
6063
6064         bnx2x_int_enable(bp);
6065
6066         /* Check for SPIO5 */
6067         bnx2x_attn_int_deasserted0(bp,
6068                 REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + BP_PORT(bp)*4) &
6069                                    AEU_INPUTS_ATTN_BITS_SPIO5);
6070 }
6071
6072 /* end of nic init */
6073
6074 /*
6075  * gzip service functions
6076  */
6077
6078 static int bnx2x_gunzip_init(struct bnx2x *bp)
6079 {
6080         bp->gunzip_buf = dma_alloc_coherent(&bp->pdev->dev, FW_BUF_SIZE,
6081                                             &bp->gunzip_mapping, GFP_KERNEL);
6082         if (bp->gunzip_buf  == NULL)
6083                 goto gunzip_nomem1;
6084
6085         bp->strm = kmalloc(sizeof(*bp->strm), GFP_KERNEL);
6086         if (bp->strm  == NULL)
6087                 goto gunzip_nomem2;
6088
6089         bp->strm->workspace = vmalloc(zlib_inflate_workspacesize());
6090         if (bp->strm->workspace == NULL)
6091                 goto gunzip_nomem3;
6092
6093         return 0;
6094
6095 gunzip_nomem3:
6096         kfree(bp->strm);
6097         bp->strm = NULL;
6098
6099 gunzip_nomem2:
6100         dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf,
6101                           bp->gunzip_mapping);
6102         bp->gunzip_buf = NULL;
6103
6104 gunzip_nomem1:
6105         BNX2X_ERR("Cannot allocate firmware buffer for un-compression\n");
6106         return -ENOMEM;
6107 }
6108
6109 static void bnx2x_gunzip_end(struct bnx2x *bp)
6110 {
6111         if (bp->strm) {
6112                 vfree(bp->strm->workspace);
6113                 kfree(bp->strm);
6114                 bp->strm = NULL;
6115         }
6116
6117         if (bp->gunzip_buf) {
6118                 dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf,
6119                                   bp->gunzip_mapping);
6120                 bp->gunzip_buf = NULL;
6121         }
6122 }
6123
6124 static int bnx2x_gunzip(struct bnx2x *bp, const u8 *zbuf, int len)
6125 {
6126         int n, rc;
6127
6128         /* check gzip header */
6129         if ((zbuf[0] != 0x1f) || (zbuf[1] != 0x8b) || (zbuf[2] != Z_DEFLATED)) {
6130                 BNX2X_ERR("Bad gzip header\n");
6131                 return -EINVAL;
6132         }
6133
6134         n = 10;
6135
6136 #define FNAME                           0x8
6137
6138         if (zbuf[3] & FNAME)
6139                 while ((zbuf[n++] != 0) && (n < len));
6140
6141         bp->strm->next_in = (typeof(bp->strm->next_in))zbuf + n;
6142         bp->strm->avail_in = len - n;
6143         bp->strm->next_out = bp->gunzip_buf;
6144         bp->strm->avail_out = FW_BUF_SIZE;
6145
6146         rc = zlib_inflateInit2(bp->strm, -MAX_WBITS);
6147         if (rc != Z_OK)
6148                 return rc;
6149
6150         rc = zlib_inflate(bp->strm, Z_FINISH);
6151         if ((rc != Z_OK) && (rc != Z_STREAM_END))
6152                 netdev_err(bp->dev, "Firmware decompression error: %s\n",
6153                            bp->strm->msg);
6154
6155         bp->gunzip_outlen = (FW_BUF_SIZE - bp->strm->avail_out);
6156         if (bp->gunzip_outlen & 0x3)
6157                 netdev_err(bp->dev,
6158                            "Firmware decompression error: gunzip_outlen (%d) not aligned\n",
6159                                 bp->gunzip_outlen);
6160         bp->gunzip_outlen >>= 2;
6161
6162         zlib_inflateEnd(bp->strm);
6163
6164         if (rc == Z_STREAM_END)
6165                 return 0;
6166
6167         return rc;
6168 }
6169
6170 /* nic load/unload */
6171
6172 /*
6173  * General service functions
6174  */
6175
6176 /* send a NIG loopback debug packet */
6177 static void bnx2x_lb_pckt(struct bnx2x *bp)
6178 {
6179         u32 wb_write[3];
6180
6181         /* Ethernet source and destination addresses */
6182         wb_write[0] = 0x55555555;
6183         wb_write[1] = 0x55555555;
6184         wb_write[2] = 0x20;             /* SOP */
6185         REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
6186
6187         /* NON-IP protocol */
6188         wb_write[0] = 0x09000000;
6189         wb_write[1] = 0x55555555;
6190         wb_write[2] = 0x10;             /* EOP, eop_bvalid = 0 */
6191         REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
6192 }
6193
6194 /* some of the internal memories
6195  * are not directly readable from the driver
6196  * to test them we send debug packets
6197  */
6198 static int bnx2x_int_mem_test(struct bnx2x *bp)
6199 {
6200         int factor;
6201         int count, i;
6202         u32 val = 0;
6203
6204         if (CHIP_REV_IS_FPGA(bp))
6205                 factor = 120;
6206         else if (CHIP_REV_IS_EMUL(bp))
6207                 factor = 200;
6208         else
6209                 factor = 1;
6210
6211         /* Disable inputs of parser neighbor blocks */
6212         REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
6213         REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
6214         REG_WR(bp, CFC_REG_DEBUG0, 0x1);
6215         REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
6216
6217         /*  Write 0 to parser credits for CFC search request */
6218         REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
6219
6220         /* send Ethernet packet */
6221         bnx2x_lb_pckt(bp);
6222
6223         /* TODO do i reset NIG statistic? */
6224         /* Wait until NIG register shows 1 packet of size 0x10 */
6225         count = 1000 * factor;
6226         while (count) {
6227
6228                 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
6229                 val = *bnx2x_sp(bp, wb_data[0]);
6230                 if (val == 0x10)
6231                         break;
6232
6233                 msleep(10);
6234                 count--;
6235         }
6236         if (val != 0x10) {
6237                 BNX2X_ERR("NIG timeout  val = 0x%x\n", val);
6238                 return -1;
6239         }
6240
6241         /* Wait until PRS register shows 1 packet */
6242         count = 1000 * factor;
6243         while (count) {
6244                 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
6245                 if (val == 1)
6246                         break;
6247
6248                 msleep(10);
6249                 count--;
6250         }
6251         if (val != 0x1) {
6252                 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
6253                 return -2;
6254         }
6255
6256         /* Reset and init BRB, PRS */
6257         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
6258         msleep(50);
6259         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
6260         msleep(50);
6261         bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
6262         bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
6263
6264         DP(NETIF_MSG_HW, "part2\n");
6265
6266         /* Disable inputs of parser neighbor blocks */
6267         REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
6268         REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
6269         REG_WR(bp, CFC_REG_DEBUG0, 0x1);
6270         REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
6271
6272         /* Write 0 to parser credits for CFC search request */
6273         REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
6274
6275         /* send 10 Ethernet packets */
6276         for (i = 0; i < 10; i++)
6277                 bnx2x_lb_pckt(bp);
6278
6279         /* Wait until NIG register shows 10 + 1
6280            packets of size 11*0x10 = 0xb0 */
6281         count = 1000 * factor;
6282         while (count) {
6283
6284                 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
6285                 val = *bnx2x_sp(bp, wb_data[0]);
6286                 if (val == 0xb0)
6287                         break;
6288
6289                 msleep(10);
6290                 count--;
6291         }
6292         if (val != 0xb0) {
6293                 BNX2X_ERR("NIG timeout  val = 0x%x\n", val);
6294                 return -3;
6295         }
6296
6297         /* Wait until PRS register shows 2 packets */
6298         val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
6299         if (val != 2)
6300                 BNX2X_ERR("PRS timeout  val = 0x%x\n", val);
6301
6302         /* Write 1 to parser credits for CFC search request */
6303         REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x1);
6304
6305         /* Wait until PRS register shows 3 packets */
6306         msleep(10 * factor);
6307         /* Wait until NIG register shows 1 packet of size 0x10 */
6308         val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
6309         if (val != 3)
6310                 BNX2X_ERR("PRS timeout  val = 0x%x\n", val);
6311
6312         /* clear NIG EOP FIFO */
6313         for (i = 0; i < 11; i++)
6314                 REG_RD(bp, NIG_REG_INGRESS_EOP_LB_FIFO);
6315         val = REG_RD(bp, NIG_REG_INGRESS_EOP_LB_EMPTY);
6316         if (val != 1) {
6317                 BNX2X_ERR("clear of NIG failed\n");
6318                 return -4;
6319         }
6320
6321         /* Reset and init BRB, PRS, NIG */
6322         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
6323         msleep(50);
6324         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
6325         msleep(50);
6326         bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
6327         bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
6328         if (!CNIC_SUPPORT(bp))
6329                 /* set NIC mode */
6330                 REG_WR(bp, PRS_REG_NIC_MODE, 1);
6331
6332         /* Enable inputs of parser neighbor blocks */
6333         REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x7fffffff);
6334         REG_WR(bp, TCM_REG_PRS_IFEN, 0x1);
6335         REG_WR(bp, CFC_REG_DEBUG0, 0x0);
6336         REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x1);
6337
6338         DP(NETIF_MSG_HW, "done\n");
6339
6340         return 0; /* OK */
6341 }
6342
6343 static void bnx2x_enable_blocks_attention(struct bnx2x *bp)
6344 {
6345         u32 val;
6346
6347         REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
6348         if (!CHIP_IS_E1x(bp))
6349                 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0x40);
6350         else
6351                 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0);
6352         REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
6353         REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
6354         /*
6355          * mask read length error interrupts in brb for parser
6356          * (parsing unit and 'checksum and crc' unit)
6357          * these errors are legal (PU reads fixed length and CAC can cause
6358          * read length error on truncated packets)
6359          */
6360         REG_WR(bp, BRB1_REG_BRB1_INT_MASK, 0xFC00);
6361         REG_WR(bp, QM_REG_QM_INT_MASK, 0);
6362         REG_WR(bp, TM_REG_TM_INT_MASK, 0);
6363         REG_WR(bp, XSDM_REG_XSDM_INT_MASK_0, 0);
6364         REG_WR(bp, XSDM_REG_XSDM_INT_MASK_1, 0);
6365         REG_WR(bp, XCM_REG_XCM_INT_MASK, 0);
6366 /*      REG_WR(bp, XSEM_REG_XSEM_INT_MASK_0, 0); */
6367 /*      REG_WR(bp, XSEM_REG_XSEM_INT_MASK_1, 0); */
6368         REG_WR(bp, USDM_REG_USDM_INT_MASK_0, 0);
6369         REG_WR(bp, USDM_REG_USDM_INT_MASK_1, 0);
6370         REG_WR(bp, UCM_REG_UCM_INT_MASK, 0);
6371 /*      REG_WR(bp, USEM_REG_USEM_INT_MASK_0, 0); */
6372 /*      REG_WR(bp, USEM_REG_USEM_INT_MASK_1, 0); */
6373         REG_WR(bp, GRCBASE_UPB + PB_REG_PB_INT_MASK, 0);
6374         REG_WR(bp, CSDM_REG_CSDM_INT_MASK_0, 0);
6375         REG_WR(bp, CSDM_REG_CSDM_INT_MASK_1, 0);
6376         REG_WR(bp, CCM_REG_CCM_INT_MASK, 0);
6377 /*      REG_WR(bp, CSEM_REG_CSEM_INT_MASK_0, 0); */
6378 /*      REG_WR(bp, CSEM_REG_CSEM_INT_MASK_1, 0); */
6379
6380         val = PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT  |
6381                 PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF |
6382                 PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN;
6383         if (!CHIP_IS_E1x(bp))
6384                 val |= PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED |
6385                         PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED;
6386         REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, val);
6387
6388         REG_WR(bp, TSDM_REG_TSDM_INT_MASK_0, 0);
6389         REG_WR(bp, TSDM_REG_TSDM_INT_MASK_1, 0);
6390         REG_WR(bp, TCM_REG_TCM_INT_MASK, 0);
6391 /*      REG_WR(bp, TSEM_REG_TSEM_INT_MASK_0, 0); */
6392
6393         if (!CHIP_IS_E1x(bp))
6394                 /* enable VFC attentions: bits 11 and 12, bits 31:13 reserved */
6395                 REG_WR(bp, TSEM_REG_TSEM_INT_MASK_1, 0x07ff);
6396
6397         REG_WR(bp, CDU_REG_CDU_INT_MASK, 0);
6398         REG_WR(bp, DMAE_REG_DMAE_INT_MASK, 0);
6399 /*      REG_WR(bp, MISC_REG_MISC_INT_MASK, 0); */
6400         REG_WR(bp, PBF_REG_PBF_INT_MASK, 0x18);         /* bit 3,4 masked */
6401 }
6402
6403 static void bnx2x_reset_common(struct bnx2x *bp)
6404 {
6405         u32 val = 0x1400;
6406
6407         /* reset_common */
6408         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
6409                0xd3ffff7f);
6410
6411         if (CHIP_IS_E3(bp)) {
6412                 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
6413                 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
6414         }
6415
6416         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, val);
6417 }
6418
6419 static void bnx2x_setup_dmae(struct bnx2x *bp)
6420 {
6421         bp->dmae_ready = 0;
6422         spin_lock_init(&bp->dmae_lock);
6423 }
6424
6425 static void bnx2x_init_pxp(struct bnx2x *bp)
6426 {
6427         u16 devctl;
6428         int r_order, w_order;
6429
6430         pcie_capability_read_word(bp->pdev, PCI_EXP_DEVCTL, &devctl);
6431         DP(NETIF_MSG_HW, "read 0x%x from devctl\n", devctl);
6432         w_order = ((devctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5);
6433         if (bp->mrrs == -1)
6434                 r_order = ((devctl & PCI_EXP_DEVCTL_READRQ) >> 12);
6435         else {
6436                 DP(NETIF_MSG_HW, "force read order to %d\n", bp->mrrs);
6437                 r_order = bp->mrrs;
6438         }
6439
6440         bnx2x_init_pxp_arb(bp, r_order, w_order);
6441 }
6442
6443 static void bnx2x_setup_fan_failure_detection(struct bnx2x *bp)
6444 {
6445         int is_required;
6446         u32 val;
6447         int port;
6448
6449         if (BP_NOMCP(bp))
6450                 return;
6451
6452         is_required = 0;
6453         val = SHMEM_RD(bp, dev_info.shared_hw_config.config2) &
6454               SHARED_HW_CFG_FAN_FAILURE_MASK;
6455
6456         if (val == SHARED_HW_CFG_FAN_FAILURE_ENABLED)
6457                 is_required = 1;
6458
6459         /*
6460          * The fan failure mechanism is usually related to the PHY type since
6461          * the power consumption of the board is affected by the PHY. Currently,
6462          * fan is required for most designs with SFX7101, BCM8727 and BCM8481.
6463          */
6464         else if (val == SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE)
6465                 for (port = PORT_0; port < PORT_MAX; port++) {
6466                         is_required |=
6467                                 bnx2x_fan_failure_det_req(
6468                                         bp,
6469                                         bp->common.shmem_base,
6470                                         bp->common.shmem2_base,
6471                                         port);
6472                 }
6473
6474         DP(NETIF_MSG_HW, "fan detection setting: %d\n", is_required);
6475
6476         if (is_required == 0)
6477                 return;
6478
6479         /* Fan failure is indicated by SPIO 5 */
6480         bnx2x_set_spio(bp, MISC_SPIO_SPIO5, MISC_SPIO_INPUT_HI_Z);
6481
6482         /* set to active low mode */
6483         val = REG_RD(bp, MISC_REG_SPIO_INT);
6484         val |= (MISC_SPIO_SPIO5 << MISC_SPIO_INT_OLD_SET_POS);
6485         REG_WR(bp, MISC_REG_SPIO_INT, val);
6486
6487         /* enable interrupt to signal the IGU */
6488         val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);
6489         val |= MISC_SPIO_SPIO5;
6490         REG_WR(bp, MISC_REG_SPIO_EVENT_EN, val);
6491 }
6492
6493 void bnx2x_pf_disable(struct bnx2x *bp)
6494 {
6495         u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
6496         val &= ~IGU_PF_CONF_FUNC_EN;
6497
6498         REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
6499         REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
6500         REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 0);
6501 }
6502
6503 static void bnx2x__common_init_phy(struct bnx2x *bp)
6504 {
6505         u32 shmem_base[2], shmem2_base[2];
6506         /* Avoid common init in case MFW supports LFA */
6507         if (SHMEM2_RD(bp, size) >
6508             (u32)offsetof(struct shmem2_region, lfa_host_addr[BP_PORT(bp)]))
6509                 return;
6510         shmem_base[0] =  bp->common.shmem_base;
6511         shmem2_base[0] = bp->common.shmem2_base;
6512         if (!CHIP_IS_E1x(bp)) {
6513                 shmem_base[1] =
6514                         SHMEM2_RD(bp, other_shmem_base_addr);
6515                 shmem2_base[1] =
6516                         SHMEM2_RD(bp, other_shmem2_base_addr);
6517         }
6518         bnx2x_acquire_phy_lock(bp);
6519         bnx2x_common_init_phy(bp, shmem_base, shmem2_base,
6520                               bp->common.chip_id);
6521         bnx2x_release_phy_lock(bp);
6522 }
6523
6524 /**
6525  * bnx2x_init_hw_common - initialize the HW at the COMMON phase.
6526  *
6527  * @bp:         driver handle
6528  */
6529 static int bnx2x_init_hw_common(struct bnx2x *bp)
6530 {
6531         u32 val;
6532
6533         DP(NETIF_MSG_HW, "starting common init  func %d\n", BP_ABS_FUNC(bp));
6534
6535         /*
6536          * take the RESET lock to protect undi_unload flow from accessing
6537          * registers while we're resetting the chip
6538          */
6539         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
6540
6541         bnx2x_reset_common(bp);
6542         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0xffffffff);
6543
6544         val = 0xfffc;
6545         if (CHIP_IS_E3(bp)) {
6546                 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
6547                 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
6548         }
6549         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, val);
6550
6551         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
6552
6553         bnx2x_init_block(bp, BLOCK_MISC, PHASE_COMMON);
6554
6555         if (!CHIP_IS_E1x(bp)) {
6556                 u8 abs_func_id;
6557
6558                 /**
6559                  * 4-port mode or 2-port mode we need to turn of master-enable
6560                  * for everyone, after that, turn it back on for self.
6561                  * so, we disregard multi-function or not, and always disable
6562                  * for all functions on the given path, this means 0,2,4,6 for
6563                  * path 0 and 1,3,5,7 for path 1
6564                  */
6565                 for (abs_func_id = BP_PATH(bp);
6566                      abs_func_id < E2_FUNC_MAX*2; abs_func_id += 2) {
6567                         if (abs_func_id == BP_ABS_FUNC(bp)) {
6568                                 REG_WR(bp,
6569                                     PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER,
6570                                     1);
6571                                 continue;
6572                         }
6573
6574                         bnx2x_pretend_func(bp, abs_func_id);
6575                         /* clear pf enable */
6576                         bnx2x_pf_disable(bp);
6577                         bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
6578                 }
6579         }
6580
6581         bnx2x_init_block(bp, BLOCK_PXP, PHASE_COMMON);
6582         if (CHIP_IS_E1(bp)) {
6583                 /* enable HW interrupt from PXP on USDM overflow
6584                    bit 16 on INT_MASK_0 */
6585                 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
6586         }
6587
6588         bnx2x_init_block(bp, BLOCK_PXP2, PHASE_COMMON);
6589         bnx2x_init_pxp(bp);
6590
6591 #ifdef __BIG_ENDIAN
6592         REG_WR(bp, PXP2_REG_RQ_QM_ENDIAN_M, 1);
6593         REG_WR(bp, PXP2_REG_RQ_TM_ENDIAN_M, 1);
6594         REG_WR(bp, PXP2_REG_RQ_SRC_ENDIAN_M, 1);
6595         REG_WR(bp, PXP2_REG_RQ_CDU_ENDIAN_M, 1);
6596         REG_WR(bp, PXP2_REG_RQ_DBG_ENDIAN_M, 1);
6597         /* make sure this value is 0 */
6598         REG_WR(bp, PXP2_REG_RQ_HC_ENDIAN_M, 0);
6599
6600 /*      REG_WR(bp, PXP2_REG_RD_PBF_SWAP_MODE, 1); */
6601         REG_WR(bp, PXP2_REG_RD_QM_SWAP_MODE, 1);
6602         REG_WR(bp, PXP2_REG_RD_TM_SWAP_MODE, 1);
6603         REG_WR(bp, PXP2_REG_RD_SRC_SWAP_MODE, 1);
6604         REG_WR(bp, PXP2_REG_RD_CDURD_SWAP_MODE, 1);
6605 #endif
6606
6607         bnx2x_ilt_init_page_size(bp, INITOP_SET);
6608
6609         if (CHIP_REV_IS_FPGA(bp) && CHIP_IS_E1H(bp))
6610                 REG_WR(bp, PXP2_REG_PGL_TAGS_LIMIT, 0x1);
6611
6612         /* let the HW do it's magic ... */
6613         msleep(100);
6614         /* finish PXP init */
6615         val = REG_RD(bp, PXP2_REG_RQ_CFG_DONE);
6616         if (val != 1) {
6617                 BNX2X_ERR("PXP2 CFG failed\n");
6618                 return -EBUSY;
6619         }
6620         val = REG_RD(bp, PXP2_REG_RD_INIT_DONE);
6621         if (val != 1) {
6622                 BNX2X_ERR("PXP2 RD_INIT failed\n");
6623                 return -EBUSY;
6624         }
6625
6626         /* Timers bug workaround E2 only. We need to set the entire ILT to
6627          * have entries with value "0" and valid bit on.
6628          * This needs to be done by the first PF that is loaded in a path
6629          * (i.e. common phase)
6630          */
6631         if (!CHIP_IS_E1x(bp)) {
6632 /* In E2 there is a bug in the timers block that can cause function 6 / 7
6633  * (i.e. vnic3) to start even if it is marked as "scan-off".
6634  * This occurs when a different function (func2,3) is being marked
6635  * as "scan-off". Real-life scenario for example: if a driver is being
6636  * load-unloaded while func6,7 are down. This will cause the timer to access
6637  * the ilt, translate to a logical address and send a request to read/write.
6638  * Since the ilt for the function that is down is not valid, this will cause
6639  * a translation error which is unrecoverable.
6640  * The Workaround is intended to make sure that when this happens nothing fatal
6641  * will occur. The workaround:
6642  *      1.  First PF driver which loads on a path will:
6643  *              a.  After taking the chip out of reset, by using pretend,
6644  *                  it will write "0" to the following registers of
6645  *                  the other vnics.
6646  *                  REG_WR(pdev, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
6647  *                  REG_WR(pdev, CFC_REG_WEAK_ENABLE_PF,0);
6648  *                  REG_WR(pdev, CFC_REG_STRONG_ENABLE_PF,0);
6649  *                  And for itself it will write '1' to
6650  *                  PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER to enable
6651  *                  dmae-operations (writing to pram for example.)
6652  *                  note: can be done for only function 6,7 but cleaner this
6653  *                        way.
6654  *              b.  Write zero+valid to the entire ILT.
6655  *              c.  Init the first_timers_ilt_entry, last_timers_ilt_entry of
6656  *                  VNIC3 (of that port). The range allocated will be the
6657  *                  entire ILT. This is needed to prevent  ILT range error.
6658  *      2.  Any PF driver load flow:
6659  *              a.  ILT update with the physical addresses of the allocated
6660  *                  logical pages.
6661  *              b.  Wait 20msec. - note that this timeout is needed to make
6662  *                  sure there are no requests in one of the PXP internal
6663  *                  queues with "old" ILT addresses.
6664  *              c.  PF enable in the PGLC.
6665  *              d.  Clear the was_error of the PF in the PGLC. (could have
6666  *                  occurred while driver was down)
6667  *              e.  PF enable in the CFC (WEAK + STRONG)
6668  *              f.  Timers scan enable
6669  *      3.  PF driver unload flow:
6670  *              a.  Clear the Timers scan_en.
6671  *              b.  Polling for scan_on=0 for that PF.
6672  *              c.  Clear the PF enable bit in the PXP.
6673  *              d.  Clear the PF enable in the CFC (WEAK + STRONG)
6674  *              e.  Write zero+valid to all ILT entries (The valid bit must
6675  *                  stay set)
6676  *              f.  If this is VNIC 3 of a port then also init
6677  *                  first_timers_ilt_entry to zero and last_timers_ilt_entry
6678  *                  to the last enrty in the ILT.
6679  *
6680  *      Notes:
6681  *      Currently the PF error in the PGLC is non recoverable.
6682  *      In the future the there will be a recovery routine for this error.
6683  *      Currently attention is masked.
6684  *      Having an MCP lock on the load/unload process does not guarantee that
6685  *      there is no Timer disable during Func6/7 enable. This is because the
6686  *      Timers scan is currently being cleared by the MCP on FLR.
6687  *      Step 2.d can be done only for PF6/7 and the driver can also check if
6688  *      there is error before clearing it. But the flow above is simpler and
6689  *      more general.
6690  *      All ILT entries are written by zero+valid and not just PF6/7
6691  *      ILT entries since in the future the ILT entries allocation for
6692  *      PF-s might be dynamic.
6693  */
6694                 struct ilt_client_info ilt_cli;
6695                 struct bnx2x_ilt ilt;
6696                 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
6697                 memset(&ilt, 0, sizeof(struct bnx2x_ilt));
6698
6699                 /* initialize dummy TM client */
6700                 ilt_cli.start = 0;
6701                 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
6702                 ilt_cli.client_num = ILT_CLIENT_TM;
6703
6704                 /* Step 1: set zeroes to all ilt page entries with valid bit on
6705                  * Step 2: set the timers first/last ilt entry to point
6706                  * to the entire range to prevent ILT range error for 3rd/4th
6707                  * vnic (this code assumes existence of the vnic)
6708                  *
6709                  * both steps performed by call to bnx2x_ilt_client_init_op()
6710                  * with dummy TM client
6711                  *
6712                  * we must use pretend since PXP2_REG_RQ_##blk##_FIRST_ILT
6713                  * and his brother are split registers
6714                  */
6715                 bnx2x_pretend_func(bp, (BP_PATH(bp) + 6));
6716                 bnx2x_ilt_client_init_op_ilt(bp, &ilt, &ilt_cli, INITOP_CLEAR);
6717                 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
6718
6719                 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN, BNX2X_PXP_DRAM_ALIGN);
6720                 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_RD, BNX2X_PXP_DRAM_ALIGN);
6721                 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_SEL, 1);
6722         }
6723
6724         REG_WR(bp, PXP2_REG_RQ_DISABLE_INPUTS, 0);
6725         REG_WR(bp, PXP2_REG_RD_DISABLE_INPUTS, 0);
6726
6727         if (!CHIP_IS_E1x(bp)) {
6728                 int factor = CHIP_REV_IS_EMUL(bp) ? 1000 :
6729                                 (CHIP_REV_IS_FPGA(bp) ? 400 : 0);
6730                 bnx2x_init_block(bp, BLOCK_PGLUE_B, PHASE_COMMON);
6731
6732                 bnx2x_init_block(bp, BLOCK_ATC, PHASE_COMMON);
6733
6734                 /* let the HW do it's magic ... */
6735                 do {
6736                         msleep(200);
6737                         val = REG_RD(bp, ATC_REG_ATC_INIT_DONE);
6738                 } while (factor-- && (val != 1));
6739
6740                 if (val != 1) {
6741                         BNX2X_ERR("ATC_INIT failed\n");
6742                         return -EBUSY;
6743                 }
6744         }
6745
6746         bnx2x_init_block(bp, BLOCK_DMAE, PHASE_COMMON);
6747
6748         bnx2x_iov_init_dmae(bp);
6749
6750         /* clean the DMAE memory */
6751         bp->dmae_ready = 1;
6752         bnx2x_init_fill(bp, TSEM_REG_PRAM, 0, 8, 1);
6753
6754         bnx2x_init_block(bp, BLOCK_TCM, PHASE_COMMON);
6755
6756         bnx2x_init_block(bp, BLOCK_UCM, PHASE_COMMON);
6757
6758         bnx2x_init_block(bp, BLOCK_CCM, PHASE_COMMON);
6759
6760         bnx2x_init_block(bp, BLOCK_XCM, PHASE_COMMON);
6761
6762         bnx2x_read_dmae(bp, XSEM_REG_PASSIVE_BUFFER, 3);
6763         bnx2x_read_dmae(bp, CSEM_REG_PASSIVE_BUFFER, 3);
6764         bnx2x_read_dmae(bp, TSEM_REG_PASSIVE_BUFFER, 3);
6765         bnx2x_read_dmae(bp, USEM_REG_PASSIVE_BUFFER, 3);
6766
6767         bnx2x_init_block(bp, BLOCK_QM, PHASE_COMMON);
6768
6769
6770         /* QM queues pointers table */
6771         bnx2x_qm_init_ptr_table(bp, bp->qm_cid_count, INITOP_SET);
6772
6773         /* soft reset pulse */
6774         REG_WR(bp, QM_REG_SOFT_RESET, 1);
6775         REG_WR(bp, QM_REG_SOFT_RESET, 0);
6776
6777         if (CNIC_SUPPORT(bp))
6778                 bnx2x_init_block(bp, BLOCK_TM, PHASE_COMMON);
6779
6780         bnx2x_init_block(bp, BLOCK_DORQ, PHASE_COMMON);
6781         REG_WR(bp, DORQ_REG_DPM_CID_OFST, BNX2X_DB_SHIFT);
6782         if (!CHIP_REV_IS_SLOW(bp))
6783                 /* enable hw interrupt from doorbell Q */
6784                 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
6785
6786         bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
6787
6788         bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
6789         REG_WR(bp, PRS_REG_A_PRSU_20, 0xf);
6790
6791         if (!CHIP_IS_E1(bp))
6792                 REG_WR(bp, PRS_REG_E1HOV_MODE, bp->path_has_ovlan);
6793
6794         if (!CHIP_IS_E1x(bp) && !CHIP_IS_E3B0(bp)) {
6795                 if (IS_MF_AFEX(bp)) {
6796                         /* configure that VNTag and VLAN headers must be
6797                          * received in afex mode
6798                          */
6799                         REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC, 0xE);
6800                         REG_WR(bp, PRS_REG_MUST_HAVE_HDRS, 0xA);
6801                         REG_WR(bp, PRS_REG_HDRS_AFTER_TAG_0, 0x6);
6802                         REG_WR(bp, PRS_REG_TAG_ETHERTYPE_0, 0x8926);
6803                         REG_WR(bp, PRS_REG_TAG_LEN_0, 0x4);
6804                 } else {
6805                         /* Bit-map indicating which L2 hdrs may appear
6806                          * after the basic Ethernet header
6807                          */
6808                         REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC,
6809                                bp->path_has_ovlan ? 7 : 6);
6810                 }
6811         }
6812
6813         bnx2x_init_block(bp, BLOCK_TSDM, PHASE_COMMON);
6814         bnx2x_init_block(bp, BLOCK_CSDM, PHASE_COMMON);
6815         bnx2x_init_block(bp, BLOCK_USDM, PHASE_COMMON);
6816         bnx2x_init_block(bp, BLOCK_XSDM, PHASE_COMMON);
6817
6818         if (!CHIP_IS_E1x(bp)) {
6819                 /* reset VFC memories */
6820                 REG_WR(bp, TSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
6821                            VFC_MEMORIES_RST_REG_CAM_RST |
6822                            VFC_MEMORIES_RST_REG_RAM_RST);
6823                 REG_WR(bp, XSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
6824                            VFC_MEMORIES_RST_REG_CAM_RST |
6825                            VFC_MEMORIES_RST_REG_RAM_RST);
6826
6827                 msleep(20);
6828         }
6829
6830         bnx2x_init_block(bp, BLOCK_TSEM, PHASE_COMMON);
6831         bnx2x_init_block(bp, BLOCK_USEM, PHASE_COMMON);
6832         bnx2x_init_block(bp, BLOCK_CSEM, PHASE_COMMON);
6833         bnx2x_init_block(bp, BLOCK_XSEM, PHASE_COMMON);
6834
6835         /* sync semi rtc */
6836         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
6837                0x80000000);
6838         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET,
6839                0x80000000);
6840
6841         bnx2x_init_block(bp, BLOCK_UPB, PHASE_COMMON);
6842         bnx2x_init_block(bp, BLOCK_XPB, PHASE_COMMON);
6843         bnx2x_init_block(bp, BLOCK_PBF, PHASE_COMMON);
6844
6845         if (!CHIP_IS_E1x(bp)) {
6846                 if (IS_MF_AFEX(bp)) {
6847                         /* configure that VNTag and VLAN headers must be
6848                          * sent in afex mode
6849                          */
6850                         REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC, 0xE);
6851                         REG_WR(bp, PBF_REG_MUST_HAVE_HDRS, 0xA);
6852                         REG_WR(bp, PBF_REG_HDRS_AFTER_TAG_0, 0x6);
6853                         REG_WR(bp, PBF_REG_TAG_ETHERTYPE_0, 0x8926);
6854                         REG_WR(bp, PBF_REG_TAG_LEN_0, 0x4);
6855                 } else {
6856                         REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC,
6857                                bp->path_has_ovlan ? 7 : 6);
6858                 }
6859         }
6860
6861         REG_WR(bp, SRC_REG_SOFT_RST, 1);
6862
6863         bnx2x_init_block(bp, BLOCK_SRC, PHASE_COMMON);
6864
6865         if (CNIC_SUPPORT(bp)) {
6866                 REG_WR(bp, SRC_REG_KEYSEARCH_0, 0x63285672);
6867                 REG_WR(bp, SRC_REG_KEYSEARCH_1, 0x24b8f2cc);
6868                 REG_WR(bp, SRC_REG_KEYSEARCH_2, 0x223aef9b);
6869                 REG_WR(bp, SRC_REG_KEYSEARCH_3, 0x26001e3a);
6870                 REG_WR(bp, SRC_REG_KEYSEARCH_4, 0x7ae91116);
6871                 REG_WR(bp, SRC_REG_KEYSEARCH_5, 0x5ce5230b);
6872                 REG_WR(bp, SRC_REG_KEYSEARCH_6, 0x298d8adf);
6873                 REG_WR(bp, SRC_REG_KEYSEARCH_7, 0x6eb0ff09);
6874                 REG_WR(bp, SRC_REG_KEYSEARCH_8, 0x1830f82f);
6875                 REG_WR(bp, SRC_REG_KEYSEARCH_9, 0x01e46be7);
6876         }
6877         REG_WR(bp, SRC_REG_SOFT_RST, 0);
6878
6879         if (sizeof(union cdu_context) != 1024)
6880                 /* we currently assume that a context is 1024 bytes */
6881                 dev_alert(&bp->pdev->dev,
6882                           "please adjust the size of cdu_context(%ld)\n",
6883                           (long)sizeof(union cdu_context));
6884
6885         bnx2x_init_block(bp, BLOCK_CDU, PHASE_COMMON);
6886         val = (4 << 24) + (0 << 12) + 1024;
6887         REG_WR(bp, CDU_REG_CDU_GLOBAL_PARAMS, val);
6888
6889         bnx2x_init_block(bp, BLOCK_CFC, PHASE_COMMON);
6890         REG_WR(bp, CFC_REG_INIT_REG, 0x7FF);
6891         /* enable context validation interrupt from CFC */
6892         REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
6893
6894         /* set the thresholds to prevent CFC/CDU race */
6895         REG_WR(bp, CFC_REG_DEBUG0, 0x20020000);
6896
6897         bnx2x_init_block(bp, BLOCK_HC, PHASE_COMMON);
6898
6899         if (!CHIP_IS_E1x(bp) && BP_NOMCP(bp))
6900                 REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x36);
6901
6902         bnx2x_init_block(bp, BLOCK_IGU, PHASE_COMMON);
6903         bnx2x_init_block(bp, BLOCK_MISC_AEU, PHASE_COMMON);
6904
6905         /* Reset PCIE errors for debug */
6906         REG_WR(bp, 0x2814, 0xffffffff);
6907         REG_WR(bp, 0x3820, 0xffffffff);
6908
6909         if (!CHIP_IS_E1x(bp)) {
6910                 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_CONTROL_5,
6911                            (PXPCS_TL_CONTROL_5_ERR_UNSPPORT1 |
6912                                 PXPCS_TL_CONTROL_5_ERR_UNSPPORT));
6913                 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC345_STAT,
6914                            (PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4 |
6915                                 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3 |
6916                                 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2));
6917                 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC678_STAT,
6918                            (PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7 |
6919                                 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6 |
6920                                 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5));
6921         }
6922
6923         bnx2x_init_block(bp, BLOCK_NIG, PHASE_COMMON);
6924         if (!CHIP_IS_E1(bp)) {
6925                 /* in E3 this done in per-port section */
6926                 if (!CHIP_IS_E3(bp))
6927                         REG_WR(bp, NIG_REG_LLH_MF_MODE, IS_MF(bp));
6928         }
6929         if (CHIP_IS_E1H(bp))
6930                 /* not applicable for E2 (and above ...) */
6931                 REG_WR(bp, NIG_REG_LLH_E1HOV_MODE, IS_MF_SD(bp));
6932
6933         if (CHIP_REV_IS_SLOW(bp))
6934                 msleep(200);
6935
6936         /* finish CFC init */
6937         val = reg_poll(bp, CFC_REG_LL_INIT_DONE, 1, 100, 10);
6938         if (val != 1) {
6939                 BNX2X_ERR("CFC LL_INIT failed\n");
6940                 return -EBUSY;
6941         }
6942         val = reg_poll(bp, CFC_REG_AC_INIT_DONE, 1, 100, 10);
6943         if (val != 1) {
6944                 BNX2X_ERR("CFC AC_INIT failed\n");
6945                 return -EBUSY;
6946         }
6947         val = reg_poll(bp, CFC_REG_CAM_INIT_DONE, 1, 100, 10);
6948         if (val != 1) {
6949                 BNX2X_ERR("CFC CAM_INIT failed\n");
6950                 return -EBUSY;
6951         }
6952         REG_WR(bp, CFC_REG_DEBUG0, 0);
6953
6954         if (CHIP_IS_E1(bp)) {
6955                 /* read NIG statistic
6956                    to see if this is our first up since powerup */
6957                 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
6958                 val = *bnx2x_sp(bp, wb_data[0]);
6959
6960                 /* do internal memory self test */
6961                 if ((val == 0) && bnx2x_int_mem_test(bp)) {
6962                         BNX2X_ERR("internal mem self test failed\n");
6963                         return -EBUSY;
6964                 }
6965         }
6966
6967         bnx2x_setup_fan_failure_detection(bp);
6968
6969         /* clear PXP2 attentions */
6970         REG_RD(bp, PXP2_REG_PXP2_INT_STS_CLR_0);
6971
6972         bnx2x_enable_blocks_attention(bp);
6973         bnx2x_enable_blocks_parity(bp);
6974
6975         if (!BP_NOMCP(bp)) {
6976                 if (CHIP_IS_E1x(bp))
6977                         bnx2x__common_init_phy(bp);
6978         } else
6979                 BNX2X_ERR("Bootcode is missing - can not initialize link\n");
6980
6981         return 0;
6982 }
6983
6984 /**
6985  * bnx2x_init_hw_common_chip - init HW at the COMMON_CHIP phase.
6986  *
6987  * @bp:         driver handle
6988  */
6989 static int bnx2x_init_hw_common_chip(struct bnx2x *bp)
6990 {
6991         int rc = bnx2x_init_hw_common(bp);
6992
6993         if (rc)
6994                 return rc;
6995
6996         /* In E2 2-PORT mode, same ext phy is used for the two paths */
6997         if (!BP_NOMCP(bp))
6998                 bnx2x__common_init_phy(bp);
6999
7000         return 0;
7001 }
7002
7003 static int bnx2x_init_hw_port(struct bnx2x *bp)
7004 {
7005         int port = BP_PORT(bp);
7006         int init_phase = port ? PHASE_PORT1 : PHASE_PORT0;
7007         u32 low, high;
7008         u32 val;
7009
7010
7011         DP(NETIF_MSG_HW, "starting port init  port %d\n", port);
7012
7013         REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
7014
7015         bnx2x_init_block(bp, BLOCK_MISC, init_phase);
7016         bnx2x_init_block(bp, BLOCK_PXP, init_phase);
7017         bnx2x_init_block(bp, BLOCK_PXP2, init_phase);
7018
7019         /* Timers bug workaround: disables the pf_master bit in pglue at
7020          * common phase, we need to enable it here before any dmae access are
7021          * attempted. Therefore we manually added the enable-master to the
7022          * port phase (it also happens in the function phase)
7023          */
7024         if (!CHIP_IS_E1x(bp))
7025                 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
7026
7027         bnx2x_init_block(bp, BLOCK_ATC, init_phase);
7028         bnx2x_init_block(bp, BLOCK_DMAE, init_phase);
7029         bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase);
7030         bnx2x_init_block(bp, BLOCK_QM, init_phase);
7031
7032         bnx2x_init_block(bp, BLOCK_TCM, init_phase);
7033         bnx2x_init_block(bp, BLOCK_UCM, init_phase);
7034         bnx2x_init_block(bp, BLOCK_CCM, init_phase);
7035         bnx2x_init_block(bp, BLOCK_XCM, init_phase);
7036
7037         /* QM cid (connection) count */
7038         bnx2x_qm_init_cid_count(bp, bp->qm_cid_count, INITOP_SET);
7039
7040         if (CNIC_SUPPORT(bp)) {
7041                 bnx2x_init_block(bp, BLOCK_TM, init_phase);
7042                 REG_WR(bp, TM_REG_LIN0_SCAN_TIME + port*4, 20);
7043                 REG_WR(bp, TM_REG_LIN0_MAX_ACTIVE_CID + port*4, 31);
7044         }
7045
7046         bnx2x_init_block(bp, BLOCK_DORQ, init_phase);
7047
7048         bnx2x_init_block(bp, BLOCK_BRB1, init_phase);
7049
7050         if (CHIP_IS_E1(bp) || CHIP_IS_E1H(bp)) {
7051
7052                 if (IS_MF(bp))
7053                         low = ((bp->flags & ONE_PORT_FLAG) ? 160 : 246);
7054                 else if (bp->dev->mtu > 4096) {
7055                         if (bp->flags & ONE_PORT_FLAG)
7056                                 low = 160;
7057                         else {
7058                                 val = bp->dev->mtu;
7059                                 /* (24*1024 + val*4)/256 */
7060                                 low = 96 + (val/64) +
7061                                                 ((val % 64) ? 1 : 0);
7062                         }
7063                 } else
7064                         low = ((bp->flags & ONE_PORT_FLAG) ? 80 : 160);
7065                 high = low + 56;        /* 14*1024/256 */
7066                 REG_WR(bp, BRB1_REG_PAUSE_LOW_THRESHOLD_0 + port*4, low);
7067                 REG_WR(bp, BRB1_REG_PAUSE_HIGH_THRESHOLD_0 + port*4, high);
7068         }
7069
7070         if (CHIP_MODE_IS_4_PORT(bp))
7071                 REG_WR(bp, (BP_PORT(bp) ?
7072                             BRB1_REG_MAC_GUARANTIED_1 :
7073                             BRB1_REG_MAC_GUARANTIED_0), 40);
7074
7075
7076         bnx2x_init_block(bp, BLOCK_PRS, init_phase);
7077         if (CHIP_IS_E3B0(bp)) {
7078                 if (IS_MF_AFEX(bp)) {
7079                         /* configure headers for AFEX mode */
7080                         REG_WR(bp, BP_PORT(bp) ?
7081                                PRS_REG_HDRS_AFTER_BASIC_PORT_1 :
7082                                PRS_REG_HDRS_AFTER_BASIC_PORT_0, 0xE);
7083                         REG_WR(bp, BP_PORT(bp) ?
7084                                PRS_REG_HDRS_AFTER_TAG_0_PORT_1 :
7085                                PRS_REG_HDRS_AFTER_TAG_0_PORT_0, 0x6);
7086                         REG_WR(bp, BP_PORT(bp) ?
7087                                PRS_REG_MUST_HAVE_HDRS_PORT_1 :
7088                                PRS_REG_MUST_HAVE_HDRS_PORT_0, 0xA);
7089                 } else {
7090                         /* Ovlan exists only if we are in multi-function +
7091                          * switch-dependent mode, in switch-independent there
7092                          * is no ovlan headers
7093                          */
7094                         REG_WR(bp, BP_PORT(bp) ?
7095                                PRS_REG_HDRS_AFTER_BASIC_PORT_1 :
7096                                PRS_REG_HDRS_AFTER_BASIC_PORT_0,
7097                                (bp->path_has_ovlan ? 7 : 6));
7098                 }
7099         }
7100
7101         bnx2x_init_block(bp, BLOCK_TSDM, init_phase);
7102         bnx2x_init_block(bp, BLOCK_CSDM, init_phase);
7103         bnx2x_init_block(bp, BLOCK_USDM, init_phase);
7104         bnx2x_init_block(bp, BLOCK_XSDM, init_phase);
7105
7106         bnx2x_init_block(bp, BLOCK_TSEM, init_phase);
7107         bnx2x_init_block(bp, BLOCK_USEM, init_phase);
7108         bnx2x_init_block(bp, BLOCK_CSEM, init_phase);
7109         bnx2x_init_block(bp, BLOCK_XSEM, init_phase);
7110
7111         bnx2x_init_block(bp, BLOCK_UPB, init_phase);
7112         bnx2x_init_block(bp, BLOCK_XPB, init_phase);
7113
7114         bnx2x_init_block(bp, BLOCK_PBF, init_phase);
7115
7116         if (CHIP_IS_E1x(bp)) {
7117                 /* configure PBF to work without PAUSE mtu 9000 */
7118                 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0);
7119
7120                 /* update threshold */
7121                 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, (9040/16));
7122                 /* update init credit */
7123                 REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, (9040/16) + 553 - 22);
7124
7125                 /* probe changes */
7126                 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 1);
7127                 udelay(50);
7128                 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0);
7129         }
7130
7131         if (CNIC_SUPPORT(bp))
7132                 bnx2x_init_block(bp, BLOCK_SRC, init_phase);
7133
7134         bnx2x_init_block(bp, BLOCK_CDU, init_phase);
7135         bnx2x_init_block(bp, BLOCK_CFC, init_phase);
7136
7137         if (CHIP_IS_E1(bp)) {
7138                 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
7139                 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
7140         }
7141         bnx2x_init_block(bp, BLOCK_HC, init_phase);
7142
7143         bnx2x_init_block(bp, BLOCK_IGU, init_phase);
7144
7145         bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase);
7146         /* init aeu_mask_attn_func_0/1:
7147          *  - SF mode: bits 3-7 are masked. only bits 0-2 are in use
7148          *  - MF mode: bit 3 is masked. bits 0-2 are in use as in SF
7149          *             bits 4-7 are used for "per vn group attention" */
7150         val = IS_MF(bp) ? 0xF7 : 0x7;
7151         /* Enable DCBX attention for all but E1 */
7152         val |= CHIP_IS_E1(bp) ? 0 : 0x10;
7153         REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, val);
7154
7155         bnx2x_init_block(bp, BLOCK_NIG, init_phase);
7156
7157         if (!CHIP_IS_E1x(bp)) {
7158                 /* Bit-map indicating which L2 hdrs may appear after the
7159                  * basic Ethernet header
7160                  */
7161                 if (IS_MF_AFEX(bp))
7162                         REG_WR(bp, BP_PORT(bp) ?
7163                                NIG_REG_P1_HDRS_AFTER_BASIC :
7164                                NIG_REG_P0_HDRS_AFTER_BASIC, 0xE);
7165                 else
7166                         REG_WR(bp, BP_PORT(bp) ?
7167                                NIG_REG_P1_HDRS_AFTER_BASIC :
7168                                NIG_REG_P0_HDRS_AFTER_BASIC,
7169                                IS_MF_SD(bp) ? 7 : 6);
7170
7171                 if (CHIP_IS_E3(bp))
7172                         REG_WR(bp, BP_PORT(bp) ?
7173                                    NIG_REG_LLH1_MF_MODE :
7174                                    NIG_REG_LLH_MF_MODE, IS_MF(bp));
7175         }
7176         if (!CHIP_IS_E3(bp))
7177                 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1);
7178
7179         if (!CHIP_IS_E1(bp)) {
7180                 /* 0x2 disable mf_ov, 0x1 enable */
7181                 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK_MF + port*4,
7182                        (IS_MF_SD(bp) ? 0x1 : 0x2));
7183
7184                 if (!CHIP_IS_E1x(bp)) {
7185                         val = 0;
7186                         switch (bp->mf_mode) {
7187                         case MULTI_FUNCTION_SD:
7188                                 val = 1;
7189                                 break;
7190                         case MULTI_FUNCTION_SI:
7191                         case MULTI_FUNCTION_AFEX:
7192                                 val = 2;
7193                                 break;
7194                         }
7195
7196                         REG_WR(bp, (BP_PORT(bp) ? NIG_REG_LLH1_CLS_TYPE :
7197                                                   NIG_REG_LLH0_CLS_TYPE), val);
7198                 }
7199                 {
7200                         REG_WR(bp, NIG_REG_LLFC_ENABLE_0 + port*4, 0);
7201                         REG_WR(bp, NIG_REG_LLFC_OUT_EN_0 + port*4, 0);
7202                         REG_WR(bp, NIG_REG_PAUSE_ENABLE_0 + port*4, 1);
7203                 }
7204         }
7205
7206         /* If SPIO5 is set to generate interrupts, enable it for this port */
7207         val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);
7208         if (val & MISC_SPIO_SPIO5) {
7209                 u32 reg_addr = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
7210                                        MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
7211                 val = REG_RD(bp, reg_addr);
7212                 val |= AEU_INPUTS_ATTN_BITS_SPIO5;
7213                 REG_WR(bp, reg_addr, val);
7214         }
7215
7216         return 0;
7217 }
7218
7219 static void bnx2x_ilt_wr(struct bnx2x *bp, u32 index, dma_addr_t addr)
7220 {
7221         int reg;
7222         u32 wb_write[2];
7223
7224         if (CHIP_IS_E1(bp))
7225                 reg = PXP2_REG_RQ_ONCHIP_AT + index*8;
7226         else
7227                 reg = PXP2_REG_RQ_ONCHIP_AT_B0 + index*8;
7228
7229         wb_write[0] = ONCHIP_ADDR1(addr);
7230         wb_write[1] = ONCHIP_ADDR2(addr);
7231         REG_WR_DMAE(bp, reg, wb_write, 2);
7232 }
7233
7234 void bnx2x_igu_clear_sb_gen(struct bnx2x *bp, u8 func, u8 idu_sb_id, bool is_pf)
7235 {
7236         u32 data, ctl, cnt = 100;
7237         u32 igu_addr_data = IGU_REG_COMMAND_REG_32LSB_DATA;
7238         u32 igu_addr_ctl = IGU_REG_COMMAND_REG_CTRL;
7239         u32 igu_addr_ack = IGU_REG_CSTORM_TYPE_0_SB_CLEANUP + (idu_sb_id/32)*4;
7240         u32 sb_bit =  1 << (idu_sb_id%32);
7241         u32 func_encode = func | (is_pf ? 1 : 0) << IGU_FID_ENCODE_IS_PF_SHIFT;
7242         u32 addr_encode = IGU_CMD_E2_PROD_UPD_BASE + idu_sb_id;
7243
7244         /* Not supported in BC mode */
7245         if (CHIP_INT_MODE_IS_BC(bp))
7246                 return;
7247
7248         data = (IGU_USE_REGISTER_cstorm_type_0_sb_cleanup
7249                         << IGU_REGULAR_CLEANUP_TYPE_SHIFT)      |
7250                 IGU_REGULAR_CLEANUP_SET                         |
7251                 IGU_REGULAR_BCLEANUP;
7252
7253         ctl = addr_encode << IGU_CTRL_REG_ADDRESS_SHIFT         |
7254               func_encode << IGU_CTRL_REG_FID_SHIFT             |
7255               IGU_CTRL_CMD_TYPE_WR << IGU_CTRL_REG_TYPE_SHIFT;
7256
7257         DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n",
7258                          data, igu_addr_data);
7259         REG_WR(bp, igu_addr_data, data);
7260         mmiowb();
7261         barrier();
7262         DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n",
7263                           ctl, igu_addr_ctl);
7264         REG_WR(bp, igu_addr_ctl, ctl);
7265         mmiowb();
7266         barrier();
7267
7268         /* wait for clean up to finish */
7269         while (!(REG_RD(bp, igu_addr_ack) & sb_bit) && --cnt)
7270                 msleep(20);
7271
7272
7273         if (!(REG_RD(bp, igu_addr_ack) & sb_bit)) {
7274                 DP(NETIF_MSG_HW,
7275                    "Unable to finish IGU cleanup: idu_sb_id %d offset %d bit %d (cnt %d)\n",
7276                           idu_sb_id, idu_sb_id/32, idu_sb_id%32, cnt);
7277         }
7278 }
7279
7280 static void bnx2x_igu_clear_sb(struct bnx2x *bp, u8 idu_sb_id)
7281 {
7282         bnx2x_igu_clear_sb_gen(bp, BP_FUNC(bp), idu_sb_id, true /*PF*/);
7283 }
7284
7285 static void bnx2x_clear_func_ilt(struct bnx2x *bp, u32 func)
7286 {
7287         u32 i, base = FUNC_ILT_BASE(func);
7288         for (i = base; i < base + ILT_PER_FUNC; i++)
7289                 bnx2x_ilt_wr(bp, i, 0);
7290 }
7291
7292
7293 static void bnx2x_init_searcher(struct bnx2x *bp)
7294 {
7295         int port = BP_PORT(bp);
7296         bnx2x_src_init_t2(bp, bp->t2, bp->t2_mapping, SRC_CONN_NUM);
7297         /* T1 hash bits value determines the T1 number of entries */
7298         REG_WR(bp, SRC_REG_NUMBER_HASH_BITS0 + port*4, SRC_HASH_BITS);
7299 }
7300
7301 static inline int bnx2x_func_switch_update(struct bnx2x *bp, int suspend)
7302 {
7303         int rc;
7304         struct bnx2x_func_state_params func_params = {NULL};
7305         struct bnx2x_func_switch_update_params *switch_update_params =
7306                 &func_params.params.switch_update;
7307
7308         /* Prepare parameters for function state transitions */
7309         __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
7310         __set_bit(RAMROD_RETRY, &func_params.ramrod_flags);
7311
7312         func_params.f_obj = &bp->func_obj;
7313         func_params.cmd = BNX2X_F_CMD_SWITCH_UPDATE;
7314
7315         /* Function parameters */
7316         switch_update_params->suspend = suspend;
7317
7318         rc = bnx2x_func_state_change(bp, &func_params);
7319
7320         return rc;
7321 }
7322
7323 static int bnx2x_reset_nic_mode(struct bnx2x *bp)
7324 {
7325         int rc, i, port = BP_PORT(bp);
7326         int vlan_en = 0, mac_en[NUM_MACS];
7327
7328
7329         /* Close input from network */
7330         if (bp->mf_mode == SINGLE_FUNCTION) {
7331                 bnx2x_set_rx_filter(&bp->link_params, 0);
7332         } else {
7333                 vlan_en = REG_RD(bp, port ? NIG_REG_LLH1_FUNC_EN :
7334                                    NIG_REG_LLH0_FUNC_EN);
7335                 REG_WR(bp, port ? NIG_REG_LLH1_FUNC_EN :
7336                           NIG_REG_LLH0_FUNC_EN, 0);
7337                 for (i = 0; i < NUM_MACS; i++) {
7338                         mac_en[i] = REG_RD(bp, port ?
7339                                              (NIG_REG_LLH1_FUNC_MEM_ENABLE +
7340                                               4 * i) :
7341                                              (NIG_REG_LLH0_FUNC_MEM_ENABLE +
7342                                               4 * i));
7343                         REG_WR(bp, port ? (NIG_REG_LLH1_FUNC_MEM_ENABLE +
7344                                               4 * i) :
7345                                   (NIG_REG_LLH0_FUNC_MEM_ENABLE + 4 * i), 0);
7346                 }
7347         }
7348
7349         /* Close BMC to host */
7350         REG_WR(bp, port ? NIG_REG_P0_TX_MNG_HOST_ENABLE :
7351                NIG_REG_P1_TX_MNG_HOST_ENABLE, 0);
7352
7353         /* Suspend Tx switching to the PF. Completion of this ramrod
7354          * further guarantees that all the packets of that PF / child
7355          * VFs in BRB were processed by the Parser, so it is safe to
7356          * change the NIC_MODE register.
7357          */
7358         rc = bnx2x_func_switch_update(bp, 1);
7359         if (rc) {
7360                 BNX2X_ERR("Can't suspend tx-switching!\n");
7361                 return rc;
7362         }
7363
7364         /* Change NIC_MODE register */
7365         REG_WR(bp, PRS_REG_NIC_MODE, 0);
7366
7367         /* Open input from network */
7368         if (bp->mf_mode == SINGLE_FUNCTION) {
7369                 bnx2x_set_rx_filter(&bp->link_params, 1);
7370         } else {
7371                 REG_WR(bp, port ? NIG_REG_LLH1_FUNC_EN :
7372                           NIG_REG_LLH0_FUNC_EN, vlan_en);
7373                 for (i = 0; i < NUM_MACS; i++) {
7374                         REG_WR(bp, port ? (NIG_REG_LLH1_FUNC_MEM_ENABLE +
7375                                               4 * i) :
7376                                   (NIG_REG_LLH0_FUNC_MEM_ENABLE + 4 * i),
7377                                   mac_en[i]);
7378                 }
7379         }
7380
7381         /* Enable BMC to host */
7382         REG_WR(bp, port ? NIG_REG_P0_TX_MNG_HOST_ENABLE :
7383                NIG_REG_P1_TX_MNG_HOST_ENABLE, 1);
7384
7385         /* Resume Tx switching to the PF */
7386         rc = bnx2x_func_switch_update(bp, 0);
7387         if (rc) {
7388                 BNX2X_ERR("Can't resume tx-switching!\n");
7389                 return rc;
7390         }
7391
7392         DP(NETIF_MSG_IFUP, "NIC MODE disabled\n");
7393         return 0;
7394 }
7395
7396 int bnx2x_init_hw_func_cnic(struct bnx2x *bp)
7397 {
7398         int rc;
7399
7400         bnx2x_ilt_init_op_cnic(bp, INITOP_SET);
7401
7402         if (CONFIGURE_NIC_MODE(bp)) {
7403                 /* Configrue searcher as part of function hw init */
7404                 bnx2x_init_searcher(bp);
7405
7406                 /* Reset NIC mode */
7407                 rc = bnx2x_reset_nic_mode(bp);
7408                 if (rc)
7409                         BNX2X_ERR("Can't change NIC mode!\n");
7410                 return rc;
7411         }
7412
7413         return 0;
7414 }
7415
7416 static int bnx2x_init_hw_func(struct bnx2x *bp)
7417 {
7418         int port = BP_PORT(bp);
7419         int func = BP_FUNC(bp);
7420         int init_phase = PHASE_PF0 + func;
7421         struct bnx2x_ilt *ilt = BP_ILT(bp);
7422         u16 cdu_ilt_start;
7423         u32 addr, val;
7424         u32 main_mem_base, main_mem_size, main_mem_prty_clr;
7425         int i, main_mem_width, rc;
7426
7427         DP(NETIF_MSG_HW, "starting func init  func %d\n", func);
7428
7429         /* FLR cleanup - hmmm */
7430         if (!CHIP_IS_E1x(bp)) {
7431                 rc = bnx2x_pf_flr_clnup(bp);
7432                 if (rc) {
7433                         bnx2x_fw_dump(bp);
7434                         return rc;
7435                 }
7436         }
7437
7438         /* set MSI reconfigure capability */
7439         if (bp->common.int_block == INT_BLOCK_HC) {
7440                 addr = (port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0);
7441                 val = REG_RD(bp, addr);
7442                 val |= HC_CONFIG_0_REG_MSI_ATTN_EN_0;
7443                 REG_WR(bp, addr, val);
7444         }
7445
7446         bnx2x_init_block(bp, BLOCK_PXP, init_phase);
7447         bnx2x_init_block(bp, BLOCK_PXP2, init_phase);
7448
7449         ilt = BP_ILT(bp);
7450         cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start;
7451
7452         if (IS_SRIOV(bp))
7453                 cdu_ilt_start += BNX2X_FIRST_VF_CID/ILT_PAGE_CIDS;
7454         cdu_ilt_start = bnx2x_iov_init_ilt(bp, cdu_ilt_start);
7455
7456         /* since BNX2X_FIRST_VF_CID > 0 the PF L2 cids precedes
7457          * those of the VFs, so start line should be reset
7458          */
7459         cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start;
7460         for (i = 0; i < L2_ILT_LINES(bp); i++) {
7461                 ilt->lines[cdu_ilt_start + i].page = bp->context[i].vcxt;
7462                 ilt->lines[cdu_ilt_start + i].page_mapping =
7463                         bp->context[i].cxt_mapping;
7464                 ilt->lines[cdu_ilt_start + i].size = bp->context[i].size;
7465         }
7466
7467         bnx2x_ilt_init_op(bp, INITOP_SET);
7468
7469         if (!CONFIGURE_NIC_MODE(bp)) {
7470                 bnx2x_init_searcher(bp);
7471                 REG_WR(bp, PRS_REG_NIC_MODE, 0);
7472                 DP(NETIF_MSG_IFUP, "NIC MODE disabled\n");
7473         } else {
7474                 /* Set NIC mode */
7475                 REG_WR(bp, PRS_REG_NIC_MODE, 1);
7476                 DP(NETIF_MSG_IFUP, "NIC MODE configrued\n");
7477
7478         }
7479
7480         if (!CHIP_IS_E1x(bp)) {
7481                 u32 pf_conf = IGU_PF_CONF_FUNC_EN;
7482
7483                 /* Turn on a single ISR mode in IGU if driver is going to use
7484                  * INT#x or MSI
7485                  */
7486                 if (!(bp->flags & USING_MSIX_FLAG))
7487                         pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN;
7488                 /*
7489                  * Timers workaround bug: function init part.
7490                  * Need to wait 20msec after initializing ILT,
7491                  * needed to make sure there are no requests in
7492                  * one of the PXP internal queues with "old" ILT addresses
7493                  */
7494                 msleep(20);
7495                 /*
7496                  * Master enable - Due to WB DMAE writes performed before this
7497                  * register is re-initialized as part of the regular function
7498                  * init
7499                  */
7500                 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
7501                 /* Enable the function in IGU */
7502                 REG_WR(bp, IGU_REG_PF_CONFIGURATION, pf_conf);
7503         }
7504
7505         bp->dmae_ready = 1;
7506
7507         bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase);
7508
7509         if (!CHIP_IS_E1x(bp))
7510                 REG_WR(bp, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR, func);
7511
7512         bnx2x_init_block(bp, BLOCK_ATC, init_phase);
7513         bnx2x_init_block(bp, BLOCK_DMAE, init_phase);
7514         bnx2x_init_block(bp, BLOCK_NIG, init_phase);
7515         bnx2x_init_block(bp, BLOCK_SRC, init_phase);
7516         bnx2x_init_block(bp, BLOCK_MISC, init_phase);
7517         bnx2x_init_block(bp, BLOCK_TCM, init_phase);
7518         bnx2x_init_block(bp, BLOCK_UCM, init_phase);
7519         bnx2x_init_block(bp, BLOCK_CCM, init_phase);
7520         bnx2x_init_block(bp, BLOCK_XCM, init_phase);
7521         bnx2x_init_block(bp, BLOCK_TSEM, init_phase);
7522         bnx2x_init_block(bp, BLOCK_USEM, init_phase);
7523         bnx2x_init_block(bp, BLOCK_CSEM, init_phase);
7524         bnx2x_init_block(bp, BLOCK_XSEM, init_phase);
7525
7526         if (!CHIP_IS_E1x(bp))
7527                 REG_WR(bp, QM_REG_PF_EN, 1);
7528
7529         if (!CHIP_IS_E1x(bp)) {
7530                 REG_WR(bp, TSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
7531                 REG_WR(bp, USEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
7532                 REG_WR(bp, CSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
7533                 REG_WR(bp, XSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
7534         }
7535         bnx2x_init_block(bp, BLOCK_QM, init_phase);
7536
7537         bnx2x_init_block(bp, BLOCK_TM, init_phase);
7538         bnx2x_init_block(bp, BLOCK_DORQ, init_phase);
7539
7540         bnx2x_iov_init_dq(bp);
7541
7542         bnx2x_init_block(bp, BLOCK_BRB1, init_phase);
7543         bnx2x_init_block(bp, BLOCK_PRS, init_phase);
7544         bnx2x_init_block(bp, BLOCK_TSDM, init_phase);
7545         bnx2x_init_block(bp, BLOCK_CSDM, init_phase);
7546         bnx2x_init_block(bp, BLOCK_USDM, init_phase);
7547         bnx2x_init_block(bp, BLOCK_XSDM, init_phase);
7548         bnx2x_init_block(bp, BLOCK_UPB, init_phase);
7549         bnx2x_init_block(bp, BLOCK_XPB, init_phase);
7550         bnx2x_init_block(bp, BLOCK_PBF, init_phase);
7551         if (!CHIP_IS_E1x(bp))
7552                 REG_WR(bp, PBF_REG_DISABLE_PF, 0);
7553
7554         bnx2x_init_block(bp, BLOCK_CDU, init_phase);
7555
7556         bnx2x_init_block(bp, BLOCK_CFC, init_phase);
7557
7558         if (!CHIP_IS_E1x(bp))
7559                 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 1);
7560
7561         if (IS_MF(bp)) {
7562                 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1);
7563                 REG_WR(bp, NIG_REG_LLH0_FUNC_VLAN_ID + port*8, bp->mf_ov);
7564         }
7565
7566         bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase);
7567
7568         /* HC init per function */
7569         if (bp->common.int_block == INT_BLOCK_HC) {
7570                 if (CHIP_IS_E1H(bp)) {
7571                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
7572
7573                         REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
7574                         REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
7575                 }
7576                 bnx2x_init_block(bp, BLOCK_HC, init_phase);
7577
7578         } else {
7579                 int num_segs, sb_idx, prod_offset;
7580
7581                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
7582
7583                 if (!CHIP_IS_E1x(bp)) {
7584                         REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0);
7585                         REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0);
7586                 }
7587
7588                 bnx2x_init_block(bp, BLOCK_IGU, init_phase);
7589
7590                 if (!CHIP_IS_E1x(bp)) {
7591                         int dsb_idx = 0;
7592                         /**
7593                          * Producer memory:
7594                          * E2 mode: address 0-135 match to the mapping memory;
7595                          * 136 - PF0 default prod; 137 - PF1 default prod;
7596                          * 138 - PF2 default prod; 139 - PF3 default prod;
7597                          * 140 - PF0 attn prod;    141 - PF1 attn prod;
7598                          * 142 - PF2 attn prod;    143 - PF3 attn prod;
7599                          * 144-147 reserved.
7600                          *
7601                          * E1.5 mode - In backward compatible mode;
7602                          * for non default SB; each even line in the memory
7603                          * holds the U producer and each odd line hold
7604                          * the C producer. The first 128 producers are for
7605                          * NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The last 20
7606                          * producers are for the DSB for each PF.
7607                          * Each PF has five segments: (the order inside each
7608                          * segment is PF0; PF1; PF2; PF3) - 128-131 U prods;
7609                          * 132-135 C prods; 136-139 X prods; 140-143 T prods;
7610                          * 144-147 attn prods;
7611                          */
7612                         /* non-default-status-blocks */
7613                         num_segs = CHIP_INT_MODE_IS_BC(bp) ?
7614                                 IGU_BC_NDSB_NUM_SEGS : IGU_NORM_NDSB_NUM_SEGS;
7615                         for (sb_idx = 0; sb_idx < bp->igu_sb_cnt; sb_idx++) {
7616                                 prod_offset = (bp->igu_base_sb + sb_idx) *
7617                                         num_segs;
7618
7619                                 for (i = 0; i < num_segs; i++) {
7620                                         addr = IGU_REG_PROD_CONS_MEMORY +
7621                                                         (prod_offset + i) * 4;
7622                                         REG_WR(bp, addr, 0);
7623                                 }
7624                                 /* send consumer update with value 0 */
7625                                 bnx2x_ack_sb(bp, bp->igu_base_sb + sb_idx,
7626                                              USTORM_ID, 0, IGU_INT_NOP, 1);
7627                                 bnx2x_igu_clear_sb(bp,
7628                                                    bp->igu_base_sb + sb_idx);
7629                         }
7630
7631                         /* default-status-blocks */
7632                         num_segs = CHIP_INT_MODE_IS_BC(bp) ?
7633                                 IGU_BC_DSB_NUM_SEGS : IGU_NORM_DSB_NUM_SEGS;
7634
7635                         if (CHIP_MODE_IS_4_PORT(bp))
7636                                 dsb_idx = BP_FUNC(bp);
7637                         else
7638                                 dsb_idx = BP_VN(bp);
7639
7640                         prod_offset = (CHIP_INT_MODE_IS_BC(bp) ?
7641                                        IGU_BC_BASE_DSB_PROD + dsb_idx :
7642                                        IGU_NORM_BASE_DSB_PROD + dsb_idx);
7643
7644                         /*
7645                          * igu prods come in chunks of E1HVN_MAX (4) -
7646                          * does not matters what is the current chip mode
7647                          */
7648                         for (i = 0; i < (num_segs * E1HVN_MAX);
7649                              i += E1HVN_MAX) {
7650                                 addr = IGU_REG_PROD_CONS_MEMORY +
7651                                                         (prod_offset + i)*4;
7652                                 REG_WR(bp, addr, 0);
7653                         }
7654                         /* send consumer update with 0 */
7655                         if (CHIP_INT_MODE_IS_BC(bp)) {
7656                                 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7657                                              USTORM_ID, 0, IGU_INT_NOP, 1);
7658                                 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7659                                              CSTORM_ID, 0, IGU_INT_NOP, 1);
7660                                 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7661                                              XSTORM_ID, 0, IGU_INT_NOP, 1);
7662                                 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7663                                              TSTORM_ID, 0, IGU_INT_NOP, 1);
7664                                 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7665                                              ATTENTION_ID, 0, IGU_INT_NOP, 1);
7666                         } else {
7667                                 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7668                                              USTORM_ID, 0, IGU_INT_NOP, 1);
7669                                 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7670                                              ATTENTION_ID, 0, IGU_INT_NOP, 1);
7671                         }
7672                         bnx2x_igu_clear_sb(bp, bp->igu_dsb_id);
7673
7674                         /* !!! these should become driver const once
7675                            rf-tool supports split-68 const */
7676                         REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_LSB, 0);
7677                         REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_MSB, 0);
7678                         REG_WR(bp, IGU_REG_SB_MASK_LSB, 0);
7679                         REG_WR(bp, IGU_REG_SB_MASK_MSB, 0);
7680                         REG_WR(bp, IGU_REG_PBA_STATUS_LSB, 0);
7681                         REG_WR(bp, IGU_REG_PBA_STATUS_MSB, 0);
7682                 }
7683         }
7684
7685         /* Reset PCIE errors for debug */
7686         REG_WR(bp, 0x2114, 0xffffffff);
7687         REG_WR(bp, 0x2120, 0xffffffff);
7688
7689         if (CHIP_IS_E1x(bp)) {
7690                 main_mem_size = HC_REG_MAIN_MEMORY_SIZE / 2; /*dwords*/
7691                 main_mem_base = HC_REG_MAIN_MEMORY +
7692                                 BP_PORT(bp) * (main_mem_size * 4);
7693                 main_mem_prty_clr = HC_REG_HC_PRTY_STS_CLR;
7694                 main_mem_width = 8;
7695
7696                 val = REG_RD(bp, main_mem_prty_clr);
7697                 if (val)
7698                         DP(NETIF_MSG_HW,
7699                            "Hmmm... Parity errors in HC block during function init (0x%x)!\n",
7700                            val);
7701
7702                 /* Clear "false" parity errors in MSI-X table */
7703                 for (i = main_mem_base;
7704                      i < main_mem_base + main_mem_size * 4;
7705                      i += main_mem_width) {
7706                         bnx2x_read_dmae(bp, i, main_mem_width / 4);
7707                         bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data),
7708                                          i, main_mem_width / 4);
7709                 }
7710                 /* Clear HC parity attention */
7711                 REG_RD(bp, main_mem_prty_clr);
7712         }
7713
7714 #ifdef BNX2X_STOP_ON_ERROR
7715         /* Enable STORMs SP logging */
7716         REG_WR8(bp, BAR_USTRORM_INTMEM +
7717                USTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
7718         REG_WR8(bp, BAR_TSTRORM_INTMEM +
7719                TSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
7720         REG_WR8(bp, BAR_CSTRORM_INTMEM +
7721                CSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
7722         REG_WR8(bp, BAR_XSTRORM_INTMEM +
7723                XSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
7724 #endif
7725
7726         bnx2x_phy_probe(&bp->link_params);
7727
7728         return 0;
7729 }
7730
7731
7732 void bnx2x_free_mem_cnic(struct bnx2x *bp)
7733 {
7734         bnx2x_ilt_mem_op_cnic(bp, ILT_MEMOP_FREE);
7735
7736         if (!CHIP_IS_E1x(bp))
7737                 BNX2X_PCI_FREE(bp->cnic_sb.e2_sb, bp->cnic_sb_mapping,
7738                                sizeof(struct host_hc_status_block_e2));
7739         else
7740                 BNX2X_PCI_FREE(bp->cnic_sb.e1x_sb, bp->cnic_sb_mapping,
7741                                sizeof(struct host_hc_status_block_e1x));
7742
7743         BNX2X_PCI_FREE(bp->t2, bp->t2_mapping, SRC_T2_SZ);
7744 }
7745
7746 void bnx2x_free_mem(struct bnx2x *bp)
7747 {
7748         int i;
7749
7750         BNX2X_PCI_FREE(bp->def_status_blk, bp->def_status_blk_mapping,
7751                        sizeof(struct host_sp_status_block));
7752
7753         BNX2X_PCI_FREE(bp->fw_stats, bp->fw_stats_mapping,
7754                        bp->fw_stats_data_sz + bp->fw_stats_req_sz);
7755
7756         BNX2X_PCI_FREE(bp->slowpath, bp->slowpath_mapping,
7757                        sizeof(struct bnx2x_slowpath));
7758
7759         for (i = 0; i < L2_ILT_LINES(bp); i++)
7760                 BNX2X_PCI_FREE(bp->context[i].vcxt, bp->context[i].cxt_mapping,
7761                                bp->context[i].size);
7762         bnx2x_ilt_mem_op(bp, ILT_MEMOP_FREE);
7763
7764         BNX2X_FREE(bp->ilt->lines);
7765
7766         BNX2X_PCI_FREE(bp->spq, bp->spq_mapping, BCM_PAGE_SIZE);
7767
7768         BNX2X_PCI_FREE(bp->eq_ring, bp->eq_mapping,
7769                        BCM_PAGE_SIZE * NUM_EQ_PAGES);
7770
7771         bnx2x_iov_free_mem(bp);
7772 }
7773
7774
7775 int bnx2x_alloc_mem_cnic(struct bnx2x *bp)
7776 {
7777         if (!CHIP_IS_E1x(bp))
7778                 /* size = the status block + ramrod buffers */
7779                 BNX2X_PCI_ALLOC(bp->cnic_sb.e2_sb, &bp->cnic_sb_mapping,
7780                                 sizeof(struct host_hc_status_block_e2));
7781         else
7782                 BNX2X_PCI_ALLOC(bp->cnic_sb.e1x_sb,
7783                                 &bp->cnic_sb_mapping,
7784                                 sizeof(struct
7785                                        host_hc_status_block_e1x));
7786
7787         if (CONFIGURE_NIC_MODE(bp))
7788                 /* allocate searcher T2 table, as it wan't allocated before */
7789                 BNX2X_PCI_ALLOC(bp->t2, &bp->t2_mapping, SRC_T2_SZ);
7790
7791         /* write address to which L5 should insert its values */
7792         bp->cnic_eth_dev.addr_drv_info_to_mcp =
7793                 &bp->slowpath->drv_info_to_mcp;
7794
7795         if (bnx2x_ilt_mem_op_cnic(bp, ILT_MEMOP_ALLOC))
7796                 goto alloc_mem_err;
7797
7798         return 0;
7799
7800 alloc_mem_err:
7801         bnx2x_free_mem_cnic(bp);
7802         BNX2X_ERR("Can't allocate memory\n");
7803         return -ENOMEM;
7804 }
7805
7806 int bnx2x_alloc_mem(struct bnx2x *bp)
7807 {
7808         int i, allocated, context_size;
7809
7810         if (!CONFIGURE_NIC_MODE(bp))
7811                 /* allocate searcher T2 table */
7812                 BNX2X_PCI_ALLOC(bp->t2, &bp->t2_mapping, SRC_T2_SZ);
7813
7814         BNX2X_PCI_ALLOC(bp->def_status_blk, &bp->def_status_blk_mapping,
7815                         sizeof(struct host_sp_status_block));
7816
7817         BNX2X_PCI_ALLOC(bp->slowpath, &bp->slowpath_mapping,
7818                         sizeof(struct bnx2x_slowpath));
7819
7820         /* Allocate memory for CDU context:
7821          * This memory is allocated separately and not in the generic ILT
7822          * functions because CDU differs in few aspects:
7823          * 1. There are multiple entities allocating memory for context -
7824          * 'regular' driver, CNIC and SRIOV driver. Each separately controls
7825          * its own ILT lines.
7826          * 2. Since CDU page-size is not a single 4KB page (which is the case
7827          * for the other ILT clients), to be efficient we want to support
7828          * allocation of sub-page-size in the last entry.
7829          * 3. Context pointers are used by the driver to pass to FW / update
7830          * the context (for the other ILT clients the pointers are used just to
7831          * free the memory during unload).
7832          */
7833         context_size = sizeof(union cdu_context) * BNX2X_L2_CID_COUNT(bp);
7834
7835         for (i = 0, allocated = 0; allocated < context_size; i++) {
7836                 bp->context[i].size = min(CDU_ILT_PAGE_SZ,
7837                                           (context_size - allocated));
7838                 BNX2X_PCI_ALLOC(bp->context[i].vcxt,
7839                                 &bp->context[i].cxt_mapping,
7840                                 bp->context[i].size);
7841                 allocated += bp->context[i].size;
7842         }
7843         BNX2X_ALLOC(bp->ilt->lines, sizeof(struct ilt_line) * ILT_MAX_LINES);
7844
7845         if (bnx2x_ilt_mem_op(bp, ILT_MEMOP_ALLOC))
7846                 goto alloc_mem_err;
7847
7848         if (bnx2x_iov_alloc_mem(bp))
7849                 goto alloc_mem_err;
7850
7851         /* Slow path ring */
7852         BNX2X_PCI_ALLOC(bp->spq, &bp->spq_mapping, BCM_PAGE_SIZE);
7853
7854         /* EQ */
7855         BNX2X_PCI_ALLOC(bp->eq_ring, &bp->eq_mapping,
7856                         BCM_PAGE_SIZE * NUM_EQ_PAGES);
7857
7858         return 0;
7859
7860 alloc_mem_err:
7861         bnx2x_free_mem(bp);
7862         BNX2X_ERR("Can't allocate memory\n");
7863         return -ENOMEM;
7864 }
7865
7866 /*
7867  * Init service functions
7868  */
7869
7870 int bnx2x_set_mac_one(struct bnx2x *bp, u8 *mac,
7871                       struct bnx2x_vlan_mac_obj *obj, bool set,
7872                       int mac_type, unsigned long *ramrod_flags)
7873 {
7874         int rc;
7875         struct bnx2x_vlan_mac_ramrod_params ramrod_param;
7876
7877         memset(&ramrod_param, 0, sizeof(ramrod_param));
7878
7879         /* Fill general parameters */
7880         ramrod_param.vlan_mac_obj = obj;
7881         ramrod_param.ramrod_flags = *ramrod_flags;
7882
7883         /* Fill a user request section if needed */
7884         if (!test_bit(RAMROD_CONT, ramrod_flags)) {
7885                 memcpy(ramrod_param.user_req.u.mac.mac, mac, ETH_ALEN);
7886
7887                 __set_bit(mac_type, &ramrod_param.user_req.vlan_mac_flags);
7888
7889                 /* Set the command: ADD or DEL */
7890                 if (set)
7891                         ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_ADD;
7892                 else
7893                         ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_DEL;
7894         }
7895
7896         rc = bnx2x_config_vlan_mac(bp, &ramrod_param);
7897
7898         if (rc == -EEXIST) {
7899                 DP(BNX2X_MSG_SP, "Failed to schedule ADD operations: %d\n", rc);
7900                 /* do not treat adding same MAC as error */
7901                 rc = 0;
7902         } else if (rc < 0)
7903                 BNX2X_ERR("%s MAC failed\n", (set ? "Set" : "Del"));
7904
7905         return rc;
7906 }
7907
7908 int bnx2x_del_all_macs(struct bnx2x *bp,
7909                        struct bnx2x_vlan_mac_obj *mac_obj,
7910                        int mac_type, bool wait_for_comp)
7911 {
7912         int rc;
7913         unsigned long ramrod_flags = 0, vlan_mac_flags = 0;
7914
7915         /* Wait for completion of requested */
7916         if (wait_for_comp)
7917                 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
7918
7919         /* Set the mac type of addresses we want to clear */
7920         __set_bit(mac_type, &vlan_mac_flags);
7921
7922         rc = mac_obj->delete_all(bp, mac_obj, &vlan_mac_flags, &ramrod_flags);
7923         if (rc < 0)
7924                 BNX2X_ERR("Failed to delete MACs: %d\n", rc);
7925
7926         return rc;
7927 }
7928
7929 int bnx2x_set_eth_mac(struct bnx2x *bp, bool set)
7930 {
7931         unsigned long ramrod_flags = 0;
7932
7933         if (is_zero_ether_addr(bp->dev->dev_addr) &&
7934             (IS_MF_STORAGE_SD(bp) || IS_MF_FCOE_AFEX(bp))) {
7935                 DP(NETIF_MSG_IFUP | NETIF_MSG_IFDOWN,
7936                    "Ignoring Zero MAC for STORAGE SD mode\n");
7937                 return 0;
7938         }
7939
7940         DP(NETIF_MSG_IFUP, "Adding Eth MAC\n");
7941
7942         __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
7943         /* Eth MAC is set on RSS leading client (fp[0]) */
7944         return bnx2x_set_mac_one(bp, bp->dev->dev_addr, &bp->sp_objs->mac_obj,
7945                                  set, BNX2X_ETH_MAC, &ramrod_flags);
7946 }
7947
7948 int bnx2x_setup_leading(struct bnx2x *bp)
7949 {
7950         return bnx2x_setup_queue(bp, &bp->fp[0], 1);
7951 }
7952
7953 /**
7954  * bnx2x_set_int_mode - configure interrupt mode
7955  *
7956  * @bp:         driver handle
7957  *
7958  * In case of MSI-X it will also try to enable MSI-X.
7959  */
7960 int bnx2x_set_int_mode(struct bnx2x *bp)
7961 {
7962         int rc = 0;
7963
7964         if (IS_VF(bp) && int_mode != BNX2X_INT_MODE_MSIX)
7965                 return -EINVAL;
7966
7967         switch (int_mode) {
7968         case BNX2X_INT_MODE_MSIX:
7969                 /* attempt to enable msix */
7970                 rc = bnx2x_enable_msix(bp);
7971
7972                 /* msix attained */
7973                 if (!rc)
7974                         return 0;
7975
7976                 /* vfs use only msix */
7977                 if (rc && IS_VF(bp))
7978                         return rc;
7979
7980                 /* failed to enable multiple MSI-X */
7981                 BNX2X_DEV_INFO("Failed to enable multiple MSI-X (%d), set number of queues to %d\n",
7982                                bp->num_queues,
7983                                1 + bp->num_cnic_queues);
7984
7985                 /* falling through... */
7986         case BNX2X_INT_MODE_MSI:
7987                 bnx2x_enable_msi(bp);
7988
7989                 /* falling through... */
7990         case BNX2X_INT_MODE_INTX:
7991                 bp->num_ethernet_queues = 1;
7992                 bp->num_queues = bp->num_ethernet_queues + bp->num_cnic_queues;
7993                 BNX2X_DEV_INFO("set number of queues to 1\n");
7994                 break;
7995         default:
7996                 BNX2X_DEV_INFO("unknown value in int_mode module parameter\n");
7997                 return -EINVAL;
7998         }
7999         return 0;
8000 }
8001
8002 /* must be called prior to any HW initializations */
8003 static inline u16 bnx2x_cid_ilt_lines(struct bnx2x *bp)
8004 {
8005         if (IS_SRIOV(bp))
8006                 return (BNX2X_FIRST_VF_CID + BNX2X_VF_CIDS)/ILT_PAGE_CIDS;
8007         return L2_ILT_LINES(bp);
8008 }
8009
8010 void bnx2x_ilt_set_info(struct bnx2x *bp)
8011 {
8012         struct ilt_client_info *ilt_client;
8013         struct bnx2x_ilt *ilt = BP_ILT(bp);
8014         u16 line = 0;
8015
8016         ilt->start_line = FUNC_ILT_BASE(BP_FUNC(bp));
8017         DP(BNX2X_MSG_SP, "ilt starts at line %d\n", ilt->start_line);
8018
8019         /* CDU */
8020         ilt_client = &ilt->clients[ILT_CLIENT_CDU];
8021         ilt_client->client_num = ILT_CLIENT_CDU;
8022         ilt_client->page_size = CDU_ILT_PAGE_SZ;
8023         ilt_client->flags = ILT_CLIENT_SKIP_MEM;
8024         ilt_client->start = line;
8025         line += bnx2x_cid_ilt_lines(bp);
8026
8027         if (CNIC_SUPPORT(bp))
8028                 line += CNIC_ILT_LINES;
8029         ilt_client->end = line - 1;
8030
8031         DP(NETIF_MSG_IFUP, "ilt client[CDU]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
8032            ilt_client->start,
8033            ilt_client->end,
8034            ilt_client->page_size,
8035            ilt_client->flags,
8036            ilog2(ilt_client->page_size >> 12));
8037
8038         /* QM */
8039         if (QM_INIT(bp->qm_cid_count)) {
8040                 ilt_client = &ilt->clients[ILT_CLIENT_QM];
8041                 ilt_client->client_num = ILT_CLIENT_QM;
8042                 ilt_client->page_size = QM_ILT_PAGE_SZ;
8043                 ilt_client->flags = 0;
8044                 ilt_client->start = line;
8045
8046                 /* 4 bytes for each cid */
8047                 line += DIV_ROUND_UP(bp->qm_cid_count * QM_QUEUES_PER_FUNC * 4,
8048                                                          QM_ILT_PAGE_SZ);
8049
8050                 ilt_client->end = line - 1;
8051
8052                 DP(NETIF_MSG_IFUP,
8053                    "ilt client[QM]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
8054                    ilt_client->start,
8055                    ilt_client->end,
8056                    ilt_client->page_size,
8057                    ilt_client->flags,
8058                    ilog2(ilt_client->page_size >> 12));
8059
8060         }
8061
8062         if (CNIC_SUPPORT(bp)) {
8063                 /* SRC */
8064                 ilt_client = &ilt->clients[ILT_CLIENT_SRC];
8065                 ilt_client->client_num = ILT_CLIENT_SRC;
8066                 ilt_client->page_size = SRC_ILT_PAGE_SZ;
8067                 ilt_client->flags = 0;
8068                 ilt_client->start = line;
8069                 line += SRC_ILT_LINES;
8070                 ilt_client->end = line - 1;
8071
8072                 DP(NETIF_MSG_IFUP,
8073                    "ilt client[SRC]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
8074                    ilt_client->start,
8075                    ilt_client->end,
8076                    ilt_client->page_size,
8077                    ilt_client->flags,
8078                    ilog2(ilt_client->page_size >> 12));
8079
8080                 /* TM */
8081                 ilt_client = &ilt->clients[ILT_CLIENT_TM];
8082                 ilt_client->client_num = ILT_CLIENT_TM;
8083                 ilt_client->page_size = TM_ILT_PAGE_SZ;
8084                 ilt_client->flags = 0;
8085                 ilt_client->start = line;
8086                 line += TM_ILT_LINES;
8087                 ilt_client->end = line - 1;
8088
8089                 DP(NETIF_MSG_IFUP,
8090                    "ilt client[TM]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
8091                    ilt_client->start,
8092                    ilt_client->end,
8093                    ilt_client->page_size,
8094                    ilt_client->flags,
8095                    ilog2(ilt_client->page_size >> 12));
8096         }
8097
8098         BUG_ON(line > ILT_MAX_LINES);
8099 }
8100
8101 /**
8102  * bnx2x_pf_q_prep_init - prepare INIT transition parameters
8103  *
8104  * @bp:                 driver handle
8105  * @fp:                 pointer to fastpath
8106  * @init_params:        pointer to parameters structure
8107  *
8108  * parameters configured:
8109  *      - HC configuration
8110  *      - Queue's CDU context
8111  */
8112 static void bnx2x_pf_q_prep_init(struct bnx2x *bp,
8113         struct bnx2x_fastpath *fp, struct bnx2x_queue_init_params *init_params)
8114 {
8115
8116         u8 cos;
8117         int cxt_index, cxt_offset;
8118
8119         /* FCoE Queue uses Default SB, thus has no HC capabilities */
8120         if (!IS_FCOE_FP(fp)) {
8121                 __set_bit(BNX2X_Q_FLG_HC, &init_params->rx.flags);
8122                 __set_bit(BNX2X_Q_FLG_HC, &init_params->tx.flags);
8123
8124                 /* If HC is supporterd, enable host coalescing in the transition
8125                  * to INIT state.
8126                  */
8127                 __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->rx.flags);
8128                 __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->tx.flags);
8129
8130                 /* HC rate */
8131                 init_params->rx.hc_rate = bp->rx_ticks ?
8132                         (1000000 / bp->rx_ticks) : 0;
8133                 init_params->tx.hc_rate = bp->tx_ticks ?
8134                         (1000000 / bp->tx_ticks) : 0;
8135
8136                 /* FW SB ID */
8137                 init_params->rx.fw_sb_id = init_params->tx.fw_sb_id =
8138                         fp->fw_sb_id;
8139
8140                 /*
8141                  * CQ index among the SB indices: FCoE clients uses the default
8142                  * SB, therefore it's different.
8143                  */
8144                 init_params->rx.sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
8145                 init_params->tx.sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS;
8146         }
8147
8148         /* set maximum number of COSs supported by this queue */
8149         init_params->max_cos = fp->max_cos;
8150
8151         DP(NETIF_MSG_IFUP, "fp: %d setting queue params max cos to: %d\n",
8152             fp->index, init_params->max_cos);
8153
8154         /* set the context pointers queue object */
8155         for (cos = FIRST_TX_COS_INDEX; cos < init_params->max_cos; cos++) {
8156                 cxt_index = fp->txdata_ptr[cos]->cid / ILT_PAGE_CIDS;
8157                 cxt_offset = fp->txdata_ptr[cos]->cid - (cxt_index *
8158                                 ILT_PAGE_CIDS);
8159                 init_params->cxts[cos] =
8160                         &bp->context[cxt_index].vcxt[cxt_offset].eth;
8161         }
8162 }
8163
8164 static int bnx2x_setup_tx_only(struct bnx2x *bp, struct bnx2x_fastpath *fp,
8165                         struct bnx2x_queue_state_params *q_params,
8166                         struct bnx2x_queue_setup_tx_only_params *tx_only_params,
8167                         int tx_index, bool leading)
8168 {
8169         memset(tx_only_params, 0, sizeof(*tx_only_params));
8170
8171         /* Set the command */
8172         q_params->cmd = BNX2X_Q_CMD_SETUP_TX_ONLY;
8173
8174         /* Set tx-only QUEUE flags: don't zero statistics */
8175         tx_only_params->flags = bnx2x_get_common_flags(bp, fp, false);
8176
8177         /* choose the index of the cid to send the slow path on */
8178         tx_only_params->cid_index = tx_index;
8179
8180         /* Set general TX_ONLY_SETUP parameters */
8181         bnx2x_pf_q_prep_general(bp, fp, &tx_only_params->gen_params, tx_index);
8182
8183         /* Set Tx TX_ONLY_SETUP parameters */
8184         bnx2x_pf_tx_q_prep(bp, fp, &tx_only_params->txq_params, tx_index);
8185
8186         DP(NETIF_MSG_IFUP,
8187            "preparing to send tx-only ramrod for connection: cos %d, primary cid %d, cid %d, client id %d, sp-client id %d, flags %lx\n",
8188            tx_index, q_params->q_obj->cids[FIRST_TX_COS_INDEX],
8189            q_params->q_obj->cids[tx_index], q_params->q_obj->cl_id,
8190            tx_only_params->gen_params.spcl_id, tx_only_params->flags);
8191
8192         /* send the ramrod */
8193         return bnx2x_queue_state_change(bp, q_params);
8194 }
8195
8196
8197 /**
8198  * bnx2x_setup_queue - setup queue
8199  *
8200  * @bp:         driver handle
8201  * @fp:         pointer to fastpath
8202  * @leading:    is leading
8203  *
8204  * This function performs 2 steps in a Queue state machine
8205  *      actually: 1) RESET->INIT 2) INIT->SETUP
8206  */
8207
8208 int bnx2x_setup_queue(struct bnx2x *bp, struct bnx2x_fastpath *fp,
8209                        bool leading)
8210 {
8211         struct bnx2x_queue_state_params q_params = {NULL};
8212         struct bnx2x_queue_setup_params *setup_params =
8213                                                 &q_params.params.setup;
8214         struct bnx2x_queue_setup_tx_only_params *tx_only_params =
8215                                                 &q_params.params.tx_only;
8216         int rc;
8217         u8 tx_index;
8218
8219         DP(NETIF_MSG_IFUP, "setting up queue %d\n", fp->index);
8220
8221         /* reset IGU state skip FCoE L2 queue */
8222         if (!IS_FCOE_FP(fp))
8223                 bnx2x_ack_sb(bp, fp->igu_sb_id, USTORM_ID, 0,
8224                              IGU_INT_ENABLE, 0);
8225
8226         q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
8227         /* We want to wait for completion in this context */
8228         __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
8229
8230         /* Prepare the INIT parameters */
8231         bnx2x_pf_q_prep_init(bp, fp, &q_params.params.init);
8232
8233         /* Set the command */
8234         q_params.cmd = BNX2X_Q_CMD_INIT;
8235
8236         /* Change the state to INIT */
8237         rc = bnx2x_queue_state_change(bp, &q_params);
8238         if (rc) {
8239                 BNX2X_ERR("Queue(%d) INIT failed\n", fp->index);
8240                 return rc;
8241         }
8242
8243         DP(NETIF_MSG_IFUP, "init complete\n");
8244
8245
8246         /* Now move the Queue to the SETUP state... */
8247         memset(setup_params, 0, sizeof(*setup_params));
8248
8249         /* Set QUEUE flags */
8250         setup_params->flags = bnx2x_get_q_flags(bp, fp, leading);
8251
8252         /* Set general SETUP parameters */
8253         bnx2x_pf_q_prep_general(bp, fp, &setup_params->gen_params,
8254                                 FIRST_TX_COS_INDEX);
8255
8256         bnx2x_pf_rx_q_prep(bp, fp, &setup_params->pause_params,
8257                             &setup_params->rxq_params);
8258
8259         bnx2x_pf_tx_q_prep(bp, fp, &setup_params->txq_params,
8260                            FIRST_TX_COS_INDEX);
8261
8262         /* Set the command */
8263         q_params.cmd = BNX2X_Q_CMD_SETUP;
8264
8265         if (IS_FCOE_FP(fp))
8266                 bp->fcoe_init = true;
8267
8268         /* Change the state to SETUP */
8269         rc = bnx2x_queue_state_change(bp, &q_params);
8270         if (rc) {
8271                 BNX2X_ERR("Queue(%d) SETUP failed\n", fp->index);
8272                 return rc;
8273         }
8274
8275         /* loop through the relevant tx-only indices */
8276         for (tx_index = FIRST_TX_ONLY_COS_INDEX;
8277               tx_index < fp->max_cos;
8278               tx_index++) {
8279
8280                 /* prepare and send tx-only ramrod*/
8281                 rc = bnx2x_setup_tx_only(bp, fp, &q_params,
8282                                           tx_only_params, tx_index, leading);
8283                 if (rc) {
8284                         BNX2X_ERR("Queue(%d.%d) TX_ONLY_SETUP failed\n",
8285                                   fp->index, tx_index);
8286                         return rc;
8287                 }
8288         }
8289
8290         return rc;
8291 }
8292
8293 static int bnx2x_stop_queue(struct bnx2x *bp, int index)
8294 {
8295         struct bnx2x_fastpath *fp = &bp->fp[index];
8296         struct bnx2x_fp_txdata *txdata;
8297         struct bnx2x_queue_state_params q_params = {NULL};
8298         int rc, tx_index;
8299
8300         DP(NETIF_MSG_IFDOWN, "stopping queue %d cid %d\n", index, fp->cid);
8301
8302         q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
8303         /* We want to wait for completion in this context */
8304         __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
8305
8306
8307         /* close tx-only connections */
8308         for (tx_index = FIRST_TX_ONLY_COS_INDEX;
8309              tx_index < fp->max_cos;
8310              tx_index++){
8311
8312                 /* ascertain this is a normal queue*/
8313                 txdata = fp->txdata_ptr[tx_index];
8314
8315                 DP(NETIF_MSG_IFDOWN, "stopping tx-only queue %d\n",
8316                                                         txdata->txq_index);
8317
8318                 /* send halt terminate on tx-only connection */
8319                 q_params.cmd = BNX2X_Q_CMD_TERMINATE;
8320                 memset(&q_params.params.terminate, 0,
8321                        sizeof(q_params.params.terminate));
8322                 q_params.params.terminate.cid_index = tx_index;
8323
8324                 rc = bnx2x_queue_state_change(bp, &q_params);
8325                 if (rc)
8326                         return rc;
8327
8328                 /* send halt terminate on tx-only connection */
8329                 q_params.cmd = BNX2X_Q_CMD_CFC_DEL;
8330                 memset(&q_params.params.cfc_del, 0,
8331                        sizeof(q_params.params.cfc_del));
8332                 q_params.params.cfc_del.cid_index = tx_index;
8333                 rc = bnx2x_queue_state_change(bp, &q_params);
8334                 if (rc)
8335                         return rc;
8336         }
8337         /* Stop the primary connection: */
8338         /* ...halt the connection */
8339         q_params.cmd = BNX2X_Q_CMD_HALT;
8340         rc = bnx2x_queue_state_change(bp, &q_params);
8341         if (rc)
8342                 return rc;
8343
8344         /* ...terminate the connection */
8345         q_params.cmd = BNX2X_Q_CMD_TERMINATE;
8346         memset(&q_params.params.terminate, 0,
8347                sizeof(q_params.params.terminate));
8348         q_params.params.terminate.cid_index = FIRST_TX_COS_INDEX;
8349         rc = bnx2x_queue_state_change(bp, &q_params);
8350         if (rc)
8351                 return rc;
8352         /* ...delete cfc entry */
8353         q_params.cmd = BNX2X_Q_CMD_CFC_DEL;
8354         memset(&q_params.params.cfc_del, 0,
8355                sizeof(q_params.params.cfc_del));
8356         q_params.params.cfc_del.cid_index = FIRST_TX_COS_INDEX;
8357         return bnx2x_queue_state_change(bp, &q_params);
8358 }
8359
8360
8361 static void bnx2x_reset_func(struct bnx2x *bp)
8362 {
8363         int port = BP_PORT(bp);
8364         int func = BP_FUNC(bp);
8365         int i;
8366
8367         /* Disable the function in the FW */
8368         REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(func), 0);
8369         REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(func), 0);
8370         REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(func), 0);
8371         REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(func), 0);
8372
8373         /* FP SBs */
8374         for_each_eth_queue(bp, i) {
8375                 struct bnx2x_fastpath *fp = &bp->fp[i];
8376                 REG_WR8(bp, BAR_CSTRORM_INTMEM +
8377                            CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(fp->fw_sb_id),
8378                            SB_DISABLED);
8379         }
8380
8381         if (CNIC_LOADED(bp))
8382                 /* CNIC SB */
8383                 REG_WR8(bp, BAR_CSTRORM_INTMEM +
8384                         CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET
8385                         (bnx2x_cnic_fw_sb_id(bp)), SB_DISABLED);
8386
8387         /* SP SB */
8388         REG_WR8(bp, BAR_CSTRORM_INTMEM +
8389                 CSTORM_SP_STATUS_BLOCK_DATA_STATE_OFFSET(func),
8390                 SB_DISABLED);
8391
8392         for (i = 0; i < XSTORM_SPQ_DATA_SIZE / 4; i++)
8393                 REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_DATA_OFFSET(func),
8394                        0);
8395
8396         /* Configure IGU */
8397         if (bp->common.int_block == INT_BLOCK_HC) {
8398                 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
8399                 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
8400         } else {
8401                 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0);
8402                 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0);
8403         }
8404
8405         if (CNIC_LOADED(bp)) {
8406                 /* Disable Timer scan */
8407                 REG_WR(bp, TM_REG_EN_LINEAR0_TIMER + port*4, 0);
8408                 /*
8409                  * Wait for at least 10ms and up to 2 second for the timers
8410                  * scan to complete
8411                  */
8412                 for (i = 0; i < 200; i++) {
8413                         msleep(10);
8414                         if (!REG_RD(bp, TM_REG_LIN0_SCAN_ON + port*4))
8415                                 break;
8416                 }
8417         }
8418         /* Clear ILT */
8419         bnx2x_clear_func_ilt(bp, func);
8420
8421         /* Timers workaround bug for E2: if this is vnic-3,
8422          * we need to set the entire ilt range for this timers.
8423          */
8424         if (!CHIP_IS_E1x(bp) && BP_VN(bp) == 3) {
8425                 struct ilt_client_info ilt_cli;
8426                 /* use dummy TM client */
8427                 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
8428                 ilt_cli.start = 0;
8429                 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
8430                 ilt_cli.client_num = ILT_CLIENT_TM;
8431
8432                 bnx2x_ilt_boundry_init_op(bp, &ilt_cli, 0, INITOP_CLEAR);
8433         }
8434
8435         /* this assumes that reset_port() called before reset_func()*/
8436         if (!CHIP_IS_E1x(bp))
8437                 bnx2x_pf_disable(bp);
8438
8439         bp->dmae_ready = 0;
8440 }
8441
8442 static void bnx2x_reset_port(struct bnx2x *bp)
8443 {
8444         int port = BP_PORT(bp);
8445         u32 val;
8446
8447         /* Reset physical Link */
8448         bnx2x__link_reset(bp);
8449
8450         REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
8451
8452         /* Do not rcv packets to BRB */
8453         REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK + port*4, 0x0);
8454         /* Do not direct rcv packets that are not for MCP to the BRB */
8455         REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_NOT_MCP :
8456                            NIG_REG_LLH0_BRB1_NOT_MCP), 0x0);
8457
8458         /* Configure AEU */
8459         REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, 0);
8460
8461         msleep(100);
8462         /* Check for BRB port occupancy */
8463         val = REG_RD(bp, BRB1_REG_PORT_NUM_OCC_BLOCKS_0 + port*4);
8464         if (val)
8465                 DP(NETIF_MSG_IFDOWN,
8466                    "BRB1 is not empty  %d blocks are occupied\n", val);
8467
8468         /* TODO: Close Doorbell port? */
8469 }
8470
8471 static int bnx2x_reset_hw(struct bnx2x *bp, u32 load_code)
8472 {
8473         struct bnx2x_func_state_params func_params = {NULL};
8474
8475         /* Prepare parameters for function state transitions */
8476         __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
8477
8478         func_params.f_obj = &bp->func_obj;
8479         func_params.cmd = BNX2X_F_CMD_HW_RESET;
8480
8481         func_params.params.hw_init.load_phase = load_code;
8482
8483         return bnx2x_func_state_change(bp, &func_params);
8484 }
8485
8486 static int bnx2x_func_stop(struct bnx2x *bp)
8487 {
8488         struct bnx2x_func_state_params func_params = {NULL};
8489         int rc;
8490
8491         /* Prepare parameters for function state transitions */
8492         __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
8493         func_params.f_obj = &bp->func_obj;
8494         func_params.cmd = BNX2X_F_CMD_STOP;
8495
8496         /*
8497          * Try to stop the function the 'good way'. If fails (in case
8498          * of a parity error during bnx2x_chip_cleanup()) and we are
8499          * not in a debug mode, perform a state transaction in order to
8500          * enable further HW_RESET transaction.
8501          */
8502         rc = bnx2x_func_state_change(bp, &func_params);
8503         if (rc) {
8504 #ifdef BNX2X_STOP_ON_ERROR
8505                 return rc;
8506 #else
8507                 BNX2X_ERR("FUNC_STOP ramrod failed. Running a dry transaction\n");
8508                 __set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags);
8509                 return bnx2x_func_state_change(bp, &func_params);
8510 #endif
8511         }
8512
8513         return 0;
8514 }
8515
8516 /**
8517  * bnx2x_send_unload_req - request unload mode from the MCP.
8518  *
8519  * @bp:                 driver handle
8520  * @unload_mode:        requested function's unload mode
8521  *
8522  * Return unload mode returned by the MCP: COMMON, PORT or FUNC.
8523  */
8524 u32 bnx2x_send_unload_req(struct bnx2x *bp, int unload_mode)
8525 {
8526         u32 reset_code = 0;
8527         int port = BP_PORT(bp);
8528
8529         /* Select the UNLOAD request mode */
8530         if (unload_mode == UNLOAD_NORMAL)
8531                 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
8532
8533         else if (bp->flags & NO_WOL_FLAG)
8534                 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP;
8535
8536         else if (bp->wol) {
8537                 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
8538                 u8 *mac_addr = bp->dev->dev_addr;
8539                 u32 val;
8540                 u16 pmc;
8541
8542                 /* The mac address is written to entries 1-4 to
8543                  * preserve entry 0 which is used by the PMF
8544                  */
8545                 u8 entry = (BP_VN(bp) + 1)*8;
8546
8547                 val = (mac_addr[0] << 8) | mac_addr[1];
8548                 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry, val);
8549
8550                 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
8551                       (mac_addr[4] << 8) | mac_addr[5];
8552                 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry + 4, val);
8553
8554                 /* Enable the PME and clear the status */
8555                 pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, &pmc);
8556                 pmc |= PCI_PM_CTRL_PME_ENABLE | PCI_PM_CTRL_PME_STATUS;
8557                 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, pmc);
8558
8559                 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_EN;
8560
8561         } else
8562                 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
8563
8564         /* Send the request to the MCP */
8565         if (!BP_NOMCP(bp))
8566                 reset_code = bnx2x_fw_command(bp, reset_code, 0);
8567         else {
8568                 int path = BP_PATH(bp);
8569
8570                 DP(NETIF_MSG_IFDOWN, "NO MCP - load counts[%d]      %d, %d, %d\n",
8571                    path, load_count[path][0], load_count[path][1],
8572                    load_count[path][2]);
8573                 load_count[path][0]--;
8574                 load_count[path][1 + port]--;
8575                 DP(NETIF_MSG_IFDOWN, "NO MCP - new load counts[%d]  %d, %d, %d\n",
8576                    path, load_count[path][0], load_count[path][1],
8577                    load_count[path][2]);
8578                 if (load_count[path][0] == 0)
8579                         reset_code = FW_MSG_CODE_DRV_UNLOAD_COMMON;
8580                 else if (load_count[path][1 + port] == 0)
8581                         reset_code = FW_MSG_CODE_DRV_UNLOAD_PORT;
8582                 else
8583                         reset_code = FW_MSG_CODE_DRV_UNLOAD_FUNCTION;
8584         }
8585
8586         return reset_code;
8587 }
8588
8589 /**
8590  * bnx2x_send_unload_done - send UNLOAD_DONE command to the MCP.
8591  *
8592  * @bp:         driver handle
8593  * @keep_link:          true iff link should be kept up
8594  */
8595 void bnx2x_send_unload_done(struct bnx2x *bp, bool keep_link)
8596 {
8597         u32 reset_param = keep_link ? DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET : 0;
8598
8599         /* Report UNLOAD_DONE to MCP */
8600         if (!BP_NOMCP(bp))
8601                 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, reset_param);
8602 }
8603
8604 static int bnx2x_func_wait_started(struct bnx2x *bp)
8605 {
8606         int tout = 50;
8607         int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
8608
8609         if (!bp->port.pmf)
8610                 return 0;
8611
8612         /*
8613          * (assumption: No Attention from MCP at this stage)
8614          * PMF probably in the middle of TXdisable/enable transaction
8615          * 1. Sync IRS for default SB
8616          * 2. Sync SP queue - this guarantes us that attention handling started
8617          * 3. Wait, that TXdisable/enable transaction completes
8618          *
8619          * 1+2 guranty that if DCBx attention was scheduled it already changed
8620          * pending bit of transaction from STARTED-->TX_STOPPED, if we alredy
8621          * received complettion for the transaction the state is TX_STOPPED.
8622          * State will return to STARTED after completion of TX_STOPPED-->STARTED
8623          * transaction.
8624          */
8625
8626         /* make sure default SB ISR is done */
8627         if (msix)
8628                 synchronize_irq(bp->msix_table[0].vector);
8629         else
8630                 synchronize_irq(bp->pdev->irq);
8631
8632         flush_workqueue(bnx2x_wq);
8633
8634         while (bnx2x_func_get_state(bp, &bp->func_obj) !=
8635                                 BNX2X_F_STATE_STARTED && tout--)
8636                 msleep(20);
8637
8638         if (bnx2x_func_get_state(bp, &bp->func_obj) !=
8639                                                 BNX2X_F_STATE_STARTED) {
8640 #ifdef BNX2X_STOP_ON_ERROR
8641                 BNX2X_ERR("Wrong function state\n");
8642                 return -EBUSY;
8643 #else
8644                 /*
8645                  * Failed to complete the transaction in a "good way"
8646                  * Force both transactions with CLR bit
8647                  */
8648                 struct bnx2x_func_state_params func_params = {NULL};
8649
8650                 DP(NETIF_MSG_IFDOWN,
8651                    "Hmmm... unexpected function state! Forcing STARTED-->TX_ST0PPED-->STARTED\n");
8652
8653                 func_params.f_obj = &bp->func_obj;
8654                 __set_bit(RAMROD_DRV_CLR_ONLY,
8655                                         &func_params.ramrod_flags);
8656
8657                 /* STARTED-->TX_ST0PPED */
8658                 func_params.cmd = BNX2X_F_CMD_TX_STOP;
8659                 bnx2x_func_state_change(bp, &func_params);
8660
8661                 /* TX_ST0PPED-->STARTED */
8662                 func_params.cmd = BNX2X_F_CMD_TX_START;
8663                 return bnx2x_func_state_change(bp, &func_params);
8664 #endif
8665         }
8666
8667         return 0;
8668 }
8669
8670 void bnx2x_chip_cleanup(struct bnx2x *bp, int unload_mode, bool keep_link)
8671 {
8672         int port = BP_PORT(bp);
8673         int i, rc = 0;
8674         u8 cos;
8675         struct bnx2x_mcast_ramrod_params rparam = {NULL};
8676         u32 reset_code;
8677
8678         /* Wait until tx fastpath tasks complete */
8679         for_each_tx_queue(bp, i) {
8680                 struct bnx2x_fastpath *fp = &bp->fp[i];
8681
8682                 for_each_cos_in_tx_queue(fp, cos)
8683                         rc = bnx2x_clean_tx_queue(bp, fp->txdata_ptr[cos]);
8684 #ifdef BNX2X_STOP_ON_ERROR
8685                 if (rc)
8686                         return;
8687 #endif
8688         }
8689
8690         /* Give HW time to discard old tx messages */
8691         usleep_range(1000, 2000);
8692
8693         /* Clean all ETH MACs */
8694         rc = bnx2x_del_all_macs(bp, &bp->sp_objs[0].mac_obj, BNX2X_ETH_MAC,
8695                                 false);
8696         if (rc < 0)
8697                 BNX2X_ERR("Failed to delete all ETH macs: %d\n", rc);
8698
8699         /* Clean up UC list  */
8700         rc = bnx2x_del_all_macs(bp, &bp->sp_objs[0].mac_obj, BNX2X_UC_LIST_MAC,
8701                                 true);
8702         if (rc < 0)
8703                 BNX2X_ERR("Failed to schedule DEL commands for UC MACs list: %d\n",
8704                           rc);
8705
8706         /* Disable LLH */
8707         if (!CHIP_IS_E1(bp))
8708                 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
8709
8710         /* Set "drop all" (stop Rx).
8711          * We need to take a netif_addr_lock() here in order to prevent
8712          * a race between the completion code and this code.
8713          */
8714         netif_addr_lock_bh(bp->dev);
8715         /* Schedule the rx_mode command */
8716         if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state))
8717                 set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state);
8718         else
8719                 bnx2x_set_storm_rx_mode(bp);
8720
8721         /* Cleanup multicast configuration */
8722         rparam.mcast_obj = &bp->mcast_obj;
8723         rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL);
8724         if (rc < 0)
8725                 BNX2X_ERR("Failed to send DEL multicast command: %d\n", rc);
8726
8727         netif_addr_unlock_bh(bp->dev);
8728
8729         bnx2x_iov_chip_cleanup(bp);
8730
8731
8732         /*
8733          * Send the UNLOAD_REQUEST to the MCP. This will return if
8734          * this function should perform FUNC, PORT or COMMON HW
8735          * reset.
8736          */
8737         reset_code = bnx2x_send_unload_req(bp, unload_mode);
8738
8739         /*
8740          * (assumption: No Attention from MCP at this stage)
8741          * PMF probably in the middle of TXdisable/enable transaction
8742          */
8743         rc = bnx2x_func_wait_started(bp);
8744         if (rc) {
8745                 BNX2X_ERR("bnx2x_func_wait_started failed\n");
8746 #ifdef BNX2X_STOP_ON_ERROR
8747                 return;
8748 #endif
8749         }
8750
8751         /* Close multi and leading connections
8752          * Completions for ramrods are collected in a synchronous way
8753          */
8754         for_each_eth_queue(bp, i)
8755                 if (bnx2x_stop_queue(bp, i))
8756 #ifdef BNX2X_STOP_ON_ERROR
8757                         return;
8758 #else
8759                         goto unload_error;
8760 #endif
8761
8762         if (CNIC_LOADED(bp)) {
8763                 for_each_cnic_queue(bp, i)
8764                         if (bnx2x_stop_queue(bp, i))
8765 #ifdef BNX2X_STOP_ON_ERROR
8766                                 return;
8767 #else
8768                                 goto unload_error;
8769 #endif
8770         }
8771
8772         /* If SP settings didn't get completed so far - something
8773          * very wrong has happen.
8774          */
8775         if (!bnx2x_wait_sp_comp(bp, ~0x0UL))
8776                 BNX2X_ERR("Hmmm... Common slow path ramrods got stuck!\n");
8777
8778 #ifndef BNX2X_STOP_ON_ERROR
8779 unload_error:
8780 #endif
8781         rc = bnx2x_func_stop(bp);
8782         if (rc) {
8783                 BNX2X_ERR("Function stop failed!\n");
8784 #ifdef BNX2X_STOP_ON_ERROR
8785                 return;
8786 #endif
8787         }
8788
8789         /* Disable HW interrupts, NAPI */
8790         bnx2x_netif_stop(bp, 1);
8791         /* Delete all NAPI objects */
8792         bnx2x_del_all_napi(bp);
8793         if (CNIC_LOADED(bp))
8794                 bnx2x_del_all_napi_cnic(bp);
8795
8796         /* Release IRQs */
8797         bnx2x_free_irq(bp);
8798
8799         /* Reset the chip */
8800         rc = bnx2x_reset_hw(bp, reset_code);
8801         if (rc)
8802                 BNX2X_ERR("HW_RESET failed\n");
8803
8804
8805         /* Report UNLOAD_DONE to MCP */
8806         bnx2x_send_unload_done(bp, keep_link);
8807 }
8808
8809 void bnx2x_disable_close_the_gate(struct bnx2x *bp)
8810 {
8811         u32 val;
8812
8813         DP(NETIF_MSG_IFDOWN, "Disabling \"close the gates\"\n");
8814
8815         if (CHIP_IS_E1(bp)) {
8816                 int port = BP_PORT(bp);
8817                 u32 addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
8818                         MISC_REG_AEU_MASK_ATTN_FUNC_0;
8819
8820                 val = REG_RD(bp, addr);
8821                 val &= ~(0x300);
8822                 REG_WR(bp, addr, val);
8823         } else {
8824                 val = REG_RD(bp, MISC_REG_AEU_GENERAL_MASK);
8825                 val &= ~(MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK |
8826                          MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK);
8827                 REG_WR(bp, MISC_REG_AEU_GENERAL_MASK, val);
8828         }
8829 }
8830
8831 /* Close gates #2, #3 and #4: */
8832 static void bnx2x_set_234_gates(struct bnx2x *bp, bool close)
8833 {
8834         u32 val;
8835
8836         /* Gates #2 and #4a are closed/opened for "not E1" only */
8837         if (!CHIP_IS_E1(bp)) {
8838                 /* #4 */
8839                 REG_WR(bp, PXP_REG_HST_DISCARD_DOORBELLS, !!close);
8840                 /* #2 */
8841                 REG_WR(bp, PXP_REG_HST_DISCARD_INTERNAL_WRITES, !!close);
8842         }
8843
8844         /* #3 */
8845         if (CHIP_IS_E1x(bp)) {
8846                 /* Prevent interrupts from HC on both ports */
8847                 val = REG_RD(bp, HC_REG_CONFIG_1);
8848                 REG_WR(bp, HC_REG_CONFIG_1,
8849                        (!close) ? (val | HC_CONFIG_1_REG_BLOCK_DISABLE_1) :
8850                        (val & ~(u32)HC_CONFIG_1_REG_BLOCK_DISABLE_1));
8851
8852                 val = REG_RD(bp, HC_REG_CONFIG_0);
8853                 REG_WR(bp, HC_REG_CONFIG_0,
8854                        (!close) ? (val | HC_CONFIG_0_REG_BLOCK_DISABLE_0) :
8855                        (val & ~(u32)HC_CONFIG_0_REG_BLOCK_DISABLE_0));
8856         } else {
8857                 /* Prevent incoming interrupts in IGU */
8858                 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION);
8859
8860                 REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION,
8861                        (!close) ?
8862                        (val | IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE) :
8863                        (val & ~(u32)IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE));
8864         }
8865
8866         DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "%s gates #2, #3 and #4\n",
8867                 close ? "closing" : "opening");
8868         mmiowb();
8869 }
8870
8871 #define SHARED_MF_CLP_MAGIC  0x80000000 /* `magic' bit */
8872
8873 static void bnx2x_clp_reset_prep(struct bnx2x *bp, u32 *magic_val)
8874 {
8875         /* Do some magic... */
8876         u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb);
8877         *magic_val = val & SHARED_MF_CLP_MAGIC;
8878         MF_CFG_WR(bp, shared_mf_config.clp_mb, val | SHARED_MF_CLP_MAGIC);
8879 }
8880
8881 /**
8882  * bnx2x_clp_reset_done - restore the value of the `magic' bit.
8883  *
8884  * @bp:         driver handle
8885  * @magic_val:  old value of the `magic' bit.
8886  */
8887 static void bnx2x_clp_reset_done(struct bnx2x *bp, u32 magic_val)
8888 {
8889         /* Restore the `magic' bit value... */
8890         u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb);
8891         MF_CFG_WR(bp, shared_mf_config.clp_mb,
8892                 (val & (~SHARED_MF_CLP_MAGIC)) | magic_val);
8893 }
8894
8895 /**
8896  * bnx2x_reset_mcp_prep - prepare for MCP reset.
8897  *
8898  * @bp:         driver handle
8899  * @magic_val:  old value of 'magic' bit.
8900  *
8901  * Takes care of CLP configurations.
8902  */
8903 static void bnx2x_reset_mcp_prep(struct bnx2x *bp, u32 *magic_val)
8904 {
8905         u32 shmem;
8906         u32 validity_offset;
8907
8908         DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "Starting\n");
8909
8910         /* Set `magic' bit in order to save MF config */
8911         if (!CHIP_IS_E1(bp))
8912                 bnx2x_clp_reset_prep(bp, magic_val);
8913
8914         /* Get shmem offset */
8915         shmem = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
8916         validity_offset =
8917                 offsetof(struct shmem_region, validity_map[BP_PORT(bp)]);
8918
8919         /* Clear validity map flags */
8920         if (shmem > 0)
8921                 REG_WR(bp, shmem + validity_offset, 0);
8922 }
8923
8924 #define MCP_TIMEOUT      5000   /* 5 seconds (in ms) */
8925 #define MCP_ONE_TIMEOUT  100    /* 100 ms */
8926
8927 /**
8928  * bnx2x_mcp_wait_one - wait for MCP_ONE_TIMEOUT
8929  *
8930  * @bp: driver handle
8931  */
8932 static void bnx2x_mcp_wait_one(struct bnx2x *bp)
8933 {
8934         /* special handling for emulation and FPGA,
8935            wait 10 times longer */
8936         if (CHIP_REV_IS_SLOW(bp))
8937                 msleep(MCP_ONE_TIMEOUT*10);
8938         else
8939                 msleep(MCP_ONE_TIMEOUT);
8940 }
8941
8942 /*
8943  * initializes bp->common.shmem_base and waits for validity signature to appear
8944  */
8945 static int bnx2x_init_shmem(struct bnx2x *bp)
8946 {
8947         int cnt = 0;
8948         u32 val = 0;
8949
8950         do {
8951                 bp->common.shmem_base = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
8952                 if (bp->common.shmem_base) {
8953                         val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]);
8954                         if (val & SHR_MEM_VALIDITY_MB)
8955                                 return 0;
8956                 }
8957
8958                 bnx2x_mcp_wait_one(bp);
8959
8960         } while (cnt++ < (MCP_TIMEOUT / MCP_ONE_TIMEOUT));
8961
8962         BNX2X_ERR("BAD MCP validity signature\n");
8963
8964         return -ENODEV;
8965 }
8966
8967 static int bnx2x_reset_mcp_comp(struct bnx2x *bp, u32 magic_val)
8968 {
8969         int rc = bnx2x_init_shmem(bp);
8970
8971         /* Restore the `magic' bit value */
8972         if (!CHIP_IS_E1(bp))
8973                 bnx2x_clp_reset_done(bp, magic_val);
8974
8975         return rc;
8976 }
8977
8978 static void bnx2x_pxp_prep(struct bnx2x *bp)
8979 {
8980         if (!CHIP_IS_E1(bp)) {
8981                 REG_WR(bp, PXP2_REG_RD_START_INIT, 0);
8982                 REG_WR(bp, PXP2_REG_RQ_RBC_DONE, 0);
8983                 mmiowb();
8984         }
8985 }
8986
8987 /*
8988  * Reset the whole chip except for:
8989  *      - PCIE core
8990  *      - PCI Glue, PSWHST, PXP/PXP2 RF (all controlled by
8991  *              one reset bit)
8992  *      - IGU
8993  *      - MISC (including AEU)
8994  *      - GRC
8995  *      - RBCN, RBCP
8996  */
8997 static void bnx2x_process_kill_chip_reset(struct bnx2x *bp, bool global)
8998 {
8999         u32 not_reset_mask1, reset_mask1, not_reset_mask2, reset_mask2;
9000         u32 global_bits2, stay_reset2;
9001
9002         /*
9003          * Bits that have to be set in reset_mask2 if we want to reset 'global'
9004          * (per chip) blocks.
9005          */
9006         global_bits2 =
9007                 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU |
9008                 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE;
9009
9010         /* Don't reset the following blocks.
9011          * Important: per port blocks (such as EMAC, BMAC, UMAC) can't be
9012          *            reset, as in 4 port device they might still be owned
9013          *            by the MCP (there is only one leader per path).
9014          */
9015         not_reset_mask1 =
9016                 MISC_REGISTERS_RESET_REG_1_RST_HC |
9017                 MISC_REGISTERS_RESET_REG_1_RST_PXPV |
9018                 MISC_REGISTERS_RESET_REG_1_RST_PXP;
9019
9020         not_reset_mask2 =
9021                 MISC_REGISTERS_RESET_REG_2_RST_PCI_MDIO |
9022                 MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE |
9023                 MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE |
9024                 MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE |
9025                 MISC_REGISTERS_RESET_REG_2_RST_RBCN |
9026                 MISC_REGISTERS_RESET_REG_2_RST_GRC  |
9027                 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE |
9028                 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B |
9029                 MISC_REGISTERS_RESET_REG_2_RST_ATC |
9030                 MISC_REGISTERS_RESET_REG_2_PGLC |
9031                 MISC_REGISTERS_RESET_REG_2_RST_BMAC0 |
9032                 MISC_REGISTERS_RESET_REG_2_RST_BMAC1 |
9033                 MISC_REGISTERS_RESET_REG_2_RST_EMAC0 |
9034                 MISC_REGISTERS_RESET_REG_2_RST_EMAC1 |
9035                 MISC_REGISTERS_RESET_REG_2_UMAC0 |
9036                 MISC_REGISTERS_RESET_REG_2_UMAC1;
9037
9038         /*
9039          * Keep the following blocks in reset:
9040          *  - all xxMACs are handled by the bnx2x_link code.
9041          */
9042         stay_reset2 =
9043                 MISC_REGISTERS_RESET_REG_2_XMAC |
9044                 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT;
9045
9046         /* Full reset masks according to the chip */
9047         reset_mask1 = 0xffffffff;
9048
9049         if (CHIP_IS_E1(bp))
9050                 reset_mask2 = 0xffff;
9051         else if (CHIP_IS_E1H(bp))
9052                 reset_mask2 = 0x1ffff;
9053         else if (CHIP_IS_E2(bp))
9054                 reset_mask2 = 0xfffff;
9055         else /* CHIP_IS_E3 */
9056                 reset_mask2 = 0x3ffffff;
9057
9058         /* Don't reset global blocks unless we need to */
9059         if (!global)
9060                 reset_mask2 &= ~global_bits2;
9061
9062         /*
9063          * In case of attention in the QM, we need to reset PXP
9064          * (MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR) before QM
9065          * because otherwise QM reset would release 'close the gates' shortly
9066          * before resetting the PXP, then the PSWRQ would send a write
9067          * request to PGLUE. Then when PXP is reset, PGLUE would try to
9068          * read the payload data from PSWWR, but PSWWR would not
9069          * respond. The write queue in PGLUE would stuck, dmae commands
9070          * would not return. Therefore it's important to reset the second
9071          * reset register (containing the
9072          * MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR bit) before the
9073          * first one (containing the MISC_REGISTERS_RESET_REG_1_RST_QM
9074          * bit).
9075          */
9076         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
9077                reset_mask2 & (~not_reset_mask2));
9078
9079         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
9080                reset_mask1 & (~not_reset_mask1));
9081
9082         barrier();
9083         mmiowb();
9084
9085         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
9086                reset_mask2 & (~stay_reset2));
9087
9088         barrier();
9089         mmiowb();
9090
9091         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, reset_mask1);
9092         mmiowb();
9093 }
9094
9095 /**
9096  * bnx2x_er_poll_igu_vq - poll for pending writes bit.
9097  * It should get cleared in no more than 1s.
9098  *
9099  * @bp: driver handle
9100  *
9101  * It should get cleared in no more than 1s. Returns 0 if
9102  * pending writes bit gets cleared.
9103  */
9104 static int bnx2x_er_poll_igu_vq(struct bnx2x *bp)
9105 {
9106         u32 cnt = 1000;
9107         u32 pend_bits = 0;
9108
9109         do {
9110                 pend_bits  = REG_RD(bp, IGU_REG_PENDING_BITS_STATUS);
9111
9112                 if (pend_bits == 0)
9113                         break;
9114
9115                 usleep_range(1000, 2000);
9116         } while (cnt-- > 0);
9117
9118         if (cnt <= 0) {
9119                 BNX2X_ERR("Still pending IGU requests pend_bits=%x!\n",
9120                           pend_bits);
9121                 return -EBUSY;
9122         }
9123
9124         return 0;
9125 }
9126
9127 static int bnx2x_process_kill(struct bnx2x *bp, bool global)
9128 {
9129         int cnt = 1000;
9130         u32 val = 0;
9131         u32 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, pgl_exp_rom2;
9132         u32 tags_63_32 = 0;
9133
9134         /* Empty the Tetris buffer, wait for 1s */
9135         do {
9136                 sr_cnt  = REG_RD(bp, PXP2_REG_RD_SR_CNT);
9137                 blk_cnt = REG_RD(bp, PXP2_REG_RD_BLK_CNT);
9138                 port_is_idle_0 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_0);
9139                 port_is_idle_1 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_1);
9140                 pgl_exp_rom2 = REG_RD(bp, PXP2_REG_PGL_EXP_ROM2);
9141                 if (CHIP_IS_E3(bp))
9142                         tags_63_32 = REG_RD(bp, PGLUE_B_REG_TAGS_63_32);
9143
9144                 if ((sr_cnt == 0x7e) && (blk_cnt == 0xa0) &&
9145                     ((port_is_idle_0 & 0x1) == 0x1) &&
9146                     ((port_is_idle_1 & 0x1) == 0x1) &&
9147                     (pgl_exp_rom2 == 0xffffffff) &&
9148                     (!CHIP_IS_E3(bp) || (tags_63_32 == 0xffffffff)))
9149                         break;
9150                 usleep_range(1000, 2000);
9151         } while (cnt-- > 0);
9152
9153         if (cnt <= 0) {
9154                 BNX2X_ERR("Tetris buffer didn't get empty or there are still outstanding read requests after 1s!\n");
9155                 BNX2X_ERR("sr_cnt=0x%08x, blk_cnt=0x%08x, port_is_idle_0=0x%08x, port_is_idle_1=0x%08x, pgl_exp_rom2=0x%08x\n",
9156                           sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1,
9157                           pgl_exp_rom2);
9158                 return -EAGAIN;
9159         }
9160
9161         barrier();
9162
9163         /* Close gates #2, #3 and #4 */
9164         bnx2x_set_234_gates(bp, true);
9165
9166         /* Poll for IGU VQs for 57712 and newer chips */
9167         if (!CHIP_IS_E1x(bp) && bnx2x_er_poll_igu_vq(bp))
9168                 return -EAGAIN;
9169
9170
9171         /* TBD: Indicate that "process kill" is in progress to MCP */
9172
9173         /* Clear "unprepared" bit */
9174         REG_WR(bp, MISC_REG_UNPREPARED, 0);
9175         barrier();
9176
9177         /* Make sure all is written to the chip before the reset */
9178         mmiowb();
9179
9180         /* Wait for 1ms to empty GLUE and PCI-E core queues,
9181          * PSWHST, GRC and PSWRD Tetris buffer.
9182          */
9183         usleep_range(1000, 2000);
9184
9185         /* Prepare to chip reset: */
9186         /* MCP */
9187         if (global)
9188                 bnx2x_reset_mcp_prep(bp, &val);
9189
9190         /* PXP */
9191         bnx2x_pxp_prep(bp);
9192         barrier();
9193
9194         /* reset the chip */
9195         bnx2x_process_kill_chip_reset(bp, global);
9196         barrier();
9197
9198         /* Recover after reset: */
9199         /* MCP */
9200         if (global && bnx2x_reset_mcp_comp(bp, val))
9201                 return -EAGAIN;
9202
9203         /* TBD: Add resetting the NO_MCP mode DB here */
9204
9205         /* Open the gates #2, #3 and #4 */
9206         bnx2x_set_234_gates(bp, false);
9207
9208         /* TBD: IGU/AEU preparation bring back the AEU/IGU to a
9209          * reset state, re-enable attentions. */
9210
9211         return 0;
9212 }
9213
9214 static int bnx2x_leader_reset(struct bnx2x *bp)
9215 {
9216         int rc = 0;
9217         bool global = bnx2x_reset_is_global(bp);
9218         u32 load_code;
9219
9220         /* if not going to reset MCP - load "fake" driver to reset HW while
9221          * driver is owner of the HW
9222          */
9223         if (!global && !BP_NOMCP(bp)) {
9224                 load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_REQ,
9225                                              DRV_MSG_CODE_LOAD_REQ_WITH_LFA);
9226                 if (!load_code) {
9227                         BNX2X_ERR("MCP response failure, aborting\n");
9228                         rc = -EAGAIN;
9229                         goto exit_leader_reset;
9230                 }
9231                 if ((load_code != FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) &&
9232                     (load_code != FW_MSG_CODE_DRV_LOAD_COMMON)) {
9233                         BNX2X_ERR("MCP unexpected resp, aborting\n");
9234                         rc = -EAGAIN;
9235                         goto exit_leader_reset2;
9236                 }
9237                 load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_DONE, 0);
9238                 if (!load_code) {
9239                         BNX2X_ERR("MCP response failure, aborting\n");
9240                         rc = -EAGAIN;
9241                         goto exit_leader_reset2;
9242                 }
9243         }
9244
9245         /* Try to recover after the failure */
9246         if (bnx2x_process_kill(bp, global)) {
9247                 BNX2X_ERR("Something bad had happen on engine %d! Aii!\n",
9248                           BP_PATH(bp));
9249                 rc = -EAGAIN;
9250                 goto exit_leader_reset2;
9251         }
9252
9253         /*
9254          * Clear RESET_IN_PROGRES and RESET_GLOBAL bits and update the driver
9255          * state.
9256          */
9257         bnx2x_set_reset_done(bp);
9258         if (global)
9259                 bnx2x_clear_reset_global(bp);
9260
9261 exit_leader_reset2:
9262         /* unload "fake driver" if it was loaded */
9263         if (!global && !BP_NOMCP(bp)) {
9264                 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP, 0);
9265                 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0);
9266         }
9267 exit_leader_reset:
9268         bp->is_leader = 0;
9269         bnx2x_release_leader_lock(bp);
9270         smp_mb();
9271         return rc;
9272 }
9273
9274 static void bnx2x_recovery_failed(struct bnx2x *bp)
9275 {
9276         netdev_err(bp->dev, "Recovery has failed. Power cycle is needed.\n");
9277
9278         /* Disconnect this device */
9279         netif_device_detach(bp->dev);
9280
9281         /*
9282          * Block ifup for all function on this engine until "process kill"
9283          * or power cycle.
9284          */
9285         bnx2x_set_reset_in_progress(bp);
9286
9287         /* Shut down the power */
9288         bnx2x_set_power_state(bp, PCI_D3hot);
9289
9290         bp->recovery_state = BNX2X_RECOVERY_FAILED;
9291
9292         smp_mb();
9293 }
9294
9295 /*
9296  * Assumption: runs under rtnl lock. This together with the fact
9297  * that it's called only from bnx2x_sp_rtnl() ensure that it
9298  * will never be called when netif_running(bp->dev) is false.
9299  */
9300 static void bnx2x_parity_recover(struct bnx2x *bp)
9301 {
9302         bool global = false;
9303         u32 error_recovered, error_unrecovered;
9304         bool is_parity;
9305
9306         DP(NETIF_MSG_HW, "Handling parity\n");
9307         while (1) {
9308                 switch (bp->recovery_state) {
9309                 case BNX2X_RECOVERY_INIT:
9310                         DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_INIT\n");
9311                         is_parity = bnx2x_chk_parity_attn(bp, &global, false);
9312                         WARN_ON(!is_parity);
9313
9314                         /* Try to get a LEADER_LOCK HW lock */
9315                         if (bnx2x_trylock_leader_lock(bp)) {
9316                                 bnx2x_set_reset_in_progress(bp);
9317                                 /*
9318                                  * Check if there is a global attention and if
9319                                  * there was a global attention, set the global
9320                                  * reset bit.
9321                                  */
9322
9323                                 if (global)
9324                                         bnx2x_set_reset_global(bp);
9325
9326                                 bp->is_leader = 1;
9327                         }
9328
9329                         /* Stop the driver */
9330                         /* If interface has been removed - break */
9331                         if (bnx2x_nic_unload(bp, UNLOAD_RECOVERY, false))
9332                                 return;
9333
9334                         bp->recovery_state = BNX2X_RECOVERY_WAIT;
9335
9336                         /* Ensure "is_leader", MCP command sequence and
9337                          * "recovery_state" update values are seen on other
9338                          * CPUs.
9339                          */
9340                         smp_mb();
9341                         break;
9342
9343                 case BNX2X_RECOVERY_WAIT:
9344                         DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_WAIT\n");
9345                         if (bp->is_leader) {
9346                                 int other_engine = BP_PATH(bp) ? 0 : 1;
9347                                 bool other_load_status =
9348                                         bnx2x_get_load_status(bp, other_engine);
9349                                 bool load_status =
9350                                         bnx2x_get_load_status(bp, BP_PATH(bp));
9351                                 global = bnx2x_reset_is_global(bp);
9352
9353                                 /*
9354                                  * In case of a parity in a global block, let
9355                                  * the first leader that performs a
9356                                  * leader_reset() reset the global blocks in
9357                                  * order to clear global attentions. Otherwise
9358                                  * the the gates will remain closed for that
9359                                  * engine.
9360                                  */
9361                                 if (load_status ||
9362                                     (global && other_load_status)) {
9363                                         /* Wait until all other functions get
9364                                          * down.
9365                                          */
9366                                         schedule_delayed_work(&bp->sp_rtnl_task,
9367                                                                 HZ/10);
9368                                         return;
9369                                 } else {
9370                                         /* If all other functions got down -
9371                                          * try to bring the chip back to
9372                                          * normal. In any case it's an exit
9373                                          * point for a leader.
9374                                          */
9375                                         if (bnx2x_leader_reset(bp)) {
9376                                                 bnx2x_recovery_failed(bp);
9377                                                 return;
9378                                         }
9379
9380                                         /* If we are here, means that the
9381                                          * leader has succeeded and doesn't
9382                                          * want to be a leader any more. Try
9383                                          * to continue as a none-leader.
9384                                          */
9385                                         break;
9386                                 }
9387                         } else { /* non-leader */
9388                                 if (!bnx2x_reset_is_done(bp, BP_PATH(bp))) {
9389                                         /* Try to get a LEADER_LOCK HW lock as
9390                                          * long as a former leader may have
9391                                          * been unloaded by the user or
9392                                          * released a leadership by another
9393                                          * reason.
9394                                          */
9395                                         if (bnx2x_trylock_leader_lock(bp)) {
9396                                                 /* I'm a leader now! Restart a
9397                                                  * switch case.
9398                                                  */
9399                                                 bp->is_leader = 1;
9400                                                 break;
9401                                         }
9402
9403                                         schedule_delayed_work(&bp->sp_rtnl_task,
9404                                                                 HZ/10);
9405                                         return;
9406
9407                                 } else {
9408                                         /*
9409                                          * If there was a global attention, wait
9410                                          * for it to be cleared.
9411                                          */
9412                                         if (bnx2x_reset_is_global(bp)) {
9413                                                 schedule_delayed_work(
9414                                                         &bp->sp_rtnl_task,
9415                                                         HZ/10);
9416                                                 return;
9417                                         }
9418
9419                                         error_recovered =
9420                                           bp->eth_stats.recoverable_error;
9421                                         error_unrecovered =
9422                                           bp->eth_stats.unrecoverable_error;
9423                                         bp->recovery_state =
9424                                                 BNX2X_RECOVERY_NIC_LOADING;
9425                                         if (bnx2x_nic_load(bp, LOAD_NORMAL)) {
9426                                                 error_unrecovered++;
9427                                                 netdev_err(bp->dev,
9428                                                            "Recovery failed. Power cycle needed\n");
9429                                                 /* Disconnect this device */
9430                                                 netif_device_detach(bp->dev);
9431                                                 /* Shut down the power */
9432                                                 bnx2x_set_power_state(
9433                                                         bp, PCI_D3hot);
9434                                                 smp_mb();
9435                                         } else {
9436                                                 bp->recovery_state =
9437                                                         BNX2X_RECOVERY_DONE;
9438                                                 error_recovered++;
9439                                                 smp_mb();
9440                                         }
9441                                         bp->eth_stats.recoverable_error =
9442                                                 error_recovered;
9443                                         bp->eth_stats.unrecoverable_error =
9444                                                 error_unrecovered;
9445
9446                                         return;
9447                                 }
9448                         }
9449                 default:
9450                         return;
9451                 }
9452         }
9453 }
9454
9455 static int bnx2x_close(struct net_device *dev);
9456
9457 /* bnx2x_nic_unload() flushes the bnx2x_wq, thus reset task is
9458  * scheduled on a general queue in order to prevent a dead lock.
9459  */
9460 static void bnx2x_sp_rtnl_task(struct work_struct *work)
9461 {
9462         struct bnx2x *bp = container_of(work, struct bnx2x, sp_rtnl_task.work);
9463
9464         rtnl_lock();
9465
9466         if (!netif_running(bp->dev)) {
9467                 rtnl_unlock();
9468                 return;
9469         }
9470
9471         /* if stop on error is defined no recovery flows should be executed */
9472 #ifdef BNX2X_STOP_ON_ERROR
9473         BNX2X_ERR("recovery flow called but STOP_ON_ERROR defined so reset not done to allow debug dump,\n"
9474                   "you will need to reboot when done\n");
9475         goto sp_rtnl_not_reset;
9476 #endif
9477
9478         if (unlikely(bp->recovery_state != BNX2X_RECOVERY_DONE)) {
9479                 /*
9480                  * Clear all pending SP commands as we are going to reset the
9481                  * function anyway.
9482                  */
9483                 bp->sp_rtnl_state = 0;
9484                 smp_mb();
9485
9486                 bnx2x_parity_recover(bp);
9487
9488                 rtnl_unlock();
9489                 return;
9490         }
9491
9492         if (test_and_clear_bit(BNX2X_SP_RTNL_TX_TIMEOUT, &bp->sp_rtnl_state)) {
9493                 /*
9494                  * Clear all pending SP commands as we are going to reset the
9495                  * function anyway.
9496                  */
9497                 bp->sp_rtnl_state = 0;
9498                 smp_mb();
9499
9500                 bnx2x_nic_unload(bp, UNLOAD_NORMAL, true);
9501                 bnx2x_nic_load(bp, LOAD_NORMAL);
9502
9503                 rtnl_unlock();
9504                 return;
9505         }
9506 #ifdef BNX2X_STOP_ON_ERROR
9507 sp_rtnl_not_reset:
9508 #endif
9509         if (test_and_clear_bit(BNX2X_SP_RTNL_SETUP_TC, &bp->sp_rtnl_state))
9510                 bnx2x_setup_tc(bp->dev, bp->dcbx_port_params.ets.num_of_cos);
9511         if (test_and_clear_bit(BNX2X_SP_RTNL_AFEX_F_UPDATE, &bp->sp_rtnl_state))
9512                 bnx2x_after_function_update(bp);
9513         /*
9514          * in case of fan failure we need to reset id if the "stop on error"
9515          * debug flag is set, since we trying to prevent permanent overheating
9516          * damage
9517          */
9518         if (test_and_clear_bit(BNX2X_SP_RTNL_FAN_FAILURE, &bp->sp_rtnl_state)) {
9519                 DP(NETIF_MSG_HW, "fan failure detected. Unloading driver\n");
9520                 netif_device_detach(bp->dev);
9521                 bnx2x_close(bp->dev);
9522                 rtnl_unlock();
9523                 return;
9524         }
9525
9526         if (test_and_clear_bit(BNX2X_SP_RTNL_VFPF_MCAST, &bp->sp_rtnl_state)) {
9527                 DP(BNX2X_MSG_SP,
9528                    "sending set mcast vf pf channel message from rtnl sp-task\n");
9529                 bnx2x_vfpf_set_mcast(bp->dev);
9530         }
9531
9532         if (test_and_clear_bit(BNX2X_SP_RTNL_VFPF_STORM_RX_MODE,
9533                                &bp->sp_rtnl_state)) {
9534                 DP(BNX2X_MSG_SP,
9535                    "sending set storm rx mode vf pf channel message from rtnl sp-task\n");
9536                 bnx2x_vfpf_storm_rx_mode(bp);
9537         }
9538
9539         if (test_and_clear_bit(BNX2X_SP_RTNL_HYPERVISOR_VLAN,
9540                                &bp->sp_rtnl_state))
9541                 bnx2x_pf_set_vfs_vlan(bp);
9542
9543         /* work which needs rtnl lock not-taken (as it takes the lock itself and
9544          * can be called from other contexts as well)
9545          */
9546         rtnl_unlock();
9547
9548         /* enable SR-IOV if applicable */
9549         if (IS_SRIOV(bp) && test_and_clear_bit(BNX2X_SP_RTNL_ENABLE_SRIOV,
9550                                                &bp->sp_rtnl_state)) {
9551                 bnx2x_disable_sriov(bp);
9552                 bnx2x_enable_sriov(bp);
9553         }
9554 }
9555
9556 static void bnx2x_period_task(struct work_struct *work)
9557 {
9558         struct bnx2x *bp = container_of(work, struct bnx2x, period_task.work);
9559
9560         if (!netif_running(bp->dev))
9561                 goto period_task_exit;
9562
9563         if (CHIP_REV_IS_SLOW(bp)) {
9564                 BNX2X_ERR("period task called on emulation, ignoring\n");
9565                 goto period_task_exit;
9566         }
9567
9568         bnx2x_acquire_phy_lock(bp);
9569         /*
9570          * The barrier is needed to ensure the ordering between the writing to
9571          * the bp->port.pmf in the bnx2x_nic_load() or bnx2x_pmf_update() and
9572          * the reading here.
9573          */
9574         smp_mb();
9575         if (bp->port.pmf) {
9576                 bnx2x_period_func(&bp->link_params, &bp->link_vars);
9577
9578                 /* Re-queue task in 1 sec */
9579                 queue_delayed_work(bnx2x_wq, &bp->period_task, 1*HZ);
9580         }
9581
9582         bnx2x_release_phy_lock(bp);
9583 period_task_exit:
9584         return;
9585 }
9586
9587 /*
9588  * Init service functions
9589  */
9590
9591 u32 bnx2x_get_pretend_reg(struct bnx2x *bp)
9592 {
9593         u32 base = PXP2_REG_PGL_PRETEND_FUNC_F0;
9594         u32 stride = PXP2_REG_PGL_PRETEND_FUNC_F1 - base;
9595         return base + (BP_ABS_FUNC(bp)) * stride;
9596 }
9597
9598 static void bnx2x_prev_unload_close_mac(struct bnx2x *bp,
9599                                         struct bnx2x_mac_vals *vals)
9600 {
9601         u32 val, base_addr, offset, mask, reset_reg;
9602         bool mac_stopped = false;
9603         u8 port = BP_PORT(bp);
9604
9605         /* reset addresses as they also mark which values were changed */
9606         vals->bmac_addr = 0;
9607         vals->umac_addr = 0;
9608         vals->xmac_addr = 0;
9609         vals->emac_addr = 0;
9610
9611         reset_reg = REG_RD(bp, MISC_REG_RESET_REG_2);
9612
9613         if (!CHIP_IS_E3(bp)) {
9614                 val = REG_RD(bp, NIG_REG_BMAC0_REGS_OUT_EN + port * 4);
9615                 mask = MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port;
9616                 if ((mask & reset_reg) && val) {
9617                         u32 wb_data[2];
9618                         BNX2X_DEV_INFO("Disable bmac Rx\n");
9619                         base_addr = BP_PORT(bp) ? NIG_REG_INGRESS_BMAC1_MEM
9620                                                 : NIG_REG_INGRESS_BMAC0_MEM;
9621                         offset = CHIP_IS_E2(bp) ? BIGMAC2_REGISTER_BMAC_CONTROL
9622                                                 : BIGMAC_REGISTER_BMAC_CONTROL;
9623
9624                         /*
9625                          * use rd/wr since we cannot use dmae. This is safe
9626                          * since MCP won't access the bus due to the request
9627                          * to unload, and no function on the path can be
9628                          * loaded at this time.
9629                          */
9630                         wb_data[0] = REG_RD(bp, base_addr + offset);
9631                         wb_data[1] = REG_RD(bp, base_addr + offset + 0x4);
9632                         vals->bmac_addr = base_addr + offset;
9633                         vals->bmac_val[0] = wb_data[0];
9634                         vals->bmac_val[1] = wb_data[1];
9635                         wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE;
9636                         REG_WR(bp, vals->bmac_addr, wb_data[0]);
9637                         REG_WR(bp, vals->bmac_addr + 0x4, wb_data[1]);
9638
9639                 }
9640                 BNX2X_DEV_INFO("Disable emac Rx\n");
9641                 vals->emac_addr = NIG_REG_NIG_EMAC0_EN + BP_PORT(bp)*4;
9642                 vals->emac_val = REG_RD(bp, vals->emac_addr);
9643                 REG_WR(bp, vals->emac_addr, 0);
9644                 mac_stopped = true;
9645         } else {
9646                 if (reset_reg & MISC_REGISTERS_RESET_REG_2_XMAC) {
9647                         BNX2X_DEV_INFO("Disable xmac Rx\n");
9648                         base_addr = BP_PORT(bp) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
9649                         val = REG_RD(bp, base_addr + XMAC_REG_PFC_CTRL_HI);
9650                         REG_WR(bp, base_addr + XMAC_REG_PFC_CTRL_HI,
9651                                val & ~(1 << 1));
9652                         REG_WR(bp, base_addr + XMAC_REG_PFC_CTRL_HI,
9653                                val | (1 << 1));
9654                         vals->xmac_addr = base_addr + XMAC_REG_CTRL;
9655                         vals->xmac_val = REG_RD(bp, vals->xmac_addr);
9656                         REG_WR(bp, vals->xmac_addr, 0);
9657                         mac_stopped = true;
9658                 }
9659                 mask = MISC_REGISTERS_RESET_REG_2_UMAC0 << port;
9660                 if (mask & reset_reg) {
9661                         BNX2X_DEV_INFO("Disable umac Rx\n");
9662                         base_addr = BP_PORT(bp) ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
9663                         vals->umac_addr = base_addr + UMAC_REG_COMMAND_CONFIG;
9664                         vals->umac_val = REG_RD(bp, vals->umac_addr);
9665                         REG_WR(bp, vals->umac_addr, 0);
9666                         mac_stopped = true;
9667                 }
9668         }
9669
9670         if (mac_stopped)
9671                 msleep(20);
9672
9673 }
9674
9675 #define BNX2X_PREV_UNDI_PROD_ADDR(p) (BAR_TSTRORM_INTMEM + 0x1508 + ((p) << 4))
9676 #define BNX2X_PREV_UNDI_RCQ(val)        ((val) & 0xffff)
9677 #define BNX2X_PREV_UNDI_BD(val)         ((val) >> 16 & 0xffff)
9678 #define BNX2X_PREV_UNDI_PROD(rcq, bd)   ((bd) << 16 | (rcq))
9679
9680 static void bnx2x_prev_unload_undi_inc(struct bnx2x *bp, u8 port, u8 inc)
9681 {
9682         u16 rcq, bd;
9683         u32 tmp_reg = REG_RD(bp, BNX2X_PREV_UNDI_PROD_ADDR(port));
9684
9685         rcq = BNX2X_PREV_UNDI_RCQ(tmp_reg) + inc;
9686         bd = BNX2X_PREV_UNDI_BD(tmp_reg) + inc;
9687
9688         tmp_reg = BNX2X_PREV_UNDI_PROD(rcq, bd);
9689         REG_WR(bp, BNX2X_PREV_UNDI_PROD_ADDR(port), tmp_reg);
9690
9691         BNX2X_DEV_INFO("UNDI producer [%d] rings bd -> 0x%04x, rcq -> 0x%04x\n",
9692                        port, bd, rcq);
9693 }
9694
9695 static int bnx2x_prev_mcp_done(struct bnx2x *bp)
9696 {
9697         u32 rc = bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE,
9698                                   DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET);
9699         if (!rc) {
9700                 BNX2X_ERR("MCP response failure, aborting\n");
9701                 return -EBUSY;
9702         }
9703
9704         return 0;
9705 }
9706
9707 static struct bnx2x_prev_path_list *
9708                 bnx2x_prev_path_get_entry(struct bnx2x *bp)
9709 {
9710         struct bnx2x_prev_path_list *tmp_list;
9711
9712         list_for_each_entry(tmp_list, &bnx2x_prev_list, list)
9713                 if (PCI_SLOT(bp->pdev->devfn) == tmp_list->slot &&
9714                     bp->pdev->bus->number == tmp_list->bus &&
9715                     BP_PATH(bp) == tmp_list->path)
9716                         return tmp_list;
9717
9718         return NULL;
9719 }
9720
9721 static int bnx2x_prev_path_mark_eeh(struct bnx2x *bp)
9722 {
9723         struct bnx2x_prev_path_list *tmp_list;
9724         int rc;
9725
9726         rc = down_interruptible(&bnx2x_prev_sem);
9727         if (rc) {
9728                 BNX2X_ERR("Received %d when tried to take lock\n", rc);
9729                 return rc;
9730         }
9731
9732         tmp_list = bnx2x_prev_path_get_entry(bp);
9733         if (tmp_list) {
9734                 tmp_list->aer = 1;
9735                 rc = 0;
9736         } else {
9737                 BNX2X_ERR("path %d: Entry does not exist for eeh; Flow occurs before initial insmod is over ?\n",
9738                           BP_PATH(bp));
9739         }
9740
9741         up(&bnx2x_prev_sem);
9742
9743         return rc;
9744 }
9745
9746 static bool bnx2x_prev_is_path_marked(struct bnx2x *bp)
9747 {
9748         struct bnx2x_prev_path_list *tmp_list;
9749         int rc = false;
9750
9751         if (down_trylock(&bnx2x_prev_sem))
9752                 return false;
9753
9754         tmp_list = bnx2x_prev_path_get_entry(bp);
9755         if (tmp_list) {
9756                 if (tmp_list->aer) {
9757                         DP(NETIF_MSG_HW, "Path %d was marked by AER\n",
9758                            BP_PATH(bp));
9759                 } else {
9760                         rc = true;
9761                         BNX2X_DEV_INFO("Path %d was already cleaned from previous drivers\n",
9762                                        BP_PATH(bp));
9763                 }
9764         }
9765
9766         up(&bnx2x_prev_sem);
9767
9768         return rc;
9769 }
9770
9771 static int bnx2x_prev_mark_path(struct bnx2x *bp, bool after_undi)
9772 {
9773         struct bnx2x_prev_path_list *tmp_list;
9774         int rc;
9775
9776         rc = down_interruptible(&bnx2x_prev_sem);
9777         if (rc) {
9778                 BNX2X_ERR("Received %d when tried to take lock\n", rc);
9779                 return rc;
9780         }
9781
9782         /* Check whether the entry for this path already exists */
9783         tmp_list = bnx2x_prev_path_get_entry(bp);
9784         if (tmp_list) {
9785                 if (!tmp_list->aer) {
9786                         BNX2X_ERR("Re-Marking the path.\n");
9787                 } else {
9788                         DP(NETIF_MSG_HW, "Removing AER indication from path %d\n",
9789                            BP_PATH(bp));
9790                         tmp_list->aer = 0;
9791                 }
9792                 up(&bnx2x_prev_sem);
9793                 return 0;
9794         }
9795         up(&bnx2x_prev_sem);
9796
9797         /* Create an entry for this path and add it */
9798         tmp_list = kmalloc(sizeof(struct bnx2x_prev_path_list), GFP_KERNEL);
9799         if (!tmp_list) {
9800                 BNX2X_ERR("Failed to allocate 'bnx2x_prev_path_list'\n");
9801                 return -ENOMEM;
9802         }
9803
9804         tmp_list->bus = bp->pdev->bus->number;
9805         tmp_list->slot = PCI_SLOT(bp->pdev->devfn);
9806         tmp_list->path = BP_PATH(bp);
9807         tmp_list->aer = 0;
9808         tmp_list->undi = after_undi ? (1 << BP_PORT(bp)) : 0;
9809
9810         rc = down_interruptible(&bnx2x_prev_sem);
9811         if (rc) {
9812                 BNX2X_ERR("Received %d when tried to take lock\n", rc);
9813                 kfree(tmp_list);
9814         } else {
9815                 DP(NETIF_MSG_HW, "Marked path [%d] - finished previous unload\n",
9816                    BP_PATH(bp));
9817                 list_add(&tmp_list->list, &bnx2x_prev_list);
9818                 up(&bnx2x_prev_sem);
9819         }
9820
9821         return rc;
9822 }
9823
9824 static int bnx2x_do_flr(struct bnx2x *bp)
9825 {
9826         int i;
9827         u16 status;
9828         struct pci_dev *dev = bp->pdev;
9829
9830
9831         if (CHIP_IS_E1x(bp)) {
9832                 BNX2X_DEV_INFO("FLR not supported in E1/E1H\n");
9833                 return -EINVAL;
9834         }
9835
9836         /* only bootcode REQ_BC_VER_4_INITIATE_FLR and onwards support flr */
9837         if (bp->common.bc_ver < REQ_BC_VER_4_INITIATE_FLR) {
9838                 BNX2X_ERR("FLR not supported by BC_VER: 0x%x\n",
9839                           bp->common.bc_ver);
9840                 return -EINVAL;
9841         }
9842
9843         /* Wait for Transaction Pending bit clean */
9844         for (i = 0; i < 4; i++) {
9845                 if (i)
9846                         msleep((1 << (i - 1)) * 100);
9847
9848                 pcie_capability_read_word(dev, PCI_EXP_DEVSTA, &status);
9849                 if (!(status & PCI_EXP_DEVSTA_TRPND))
9850                         goto clear;
9851         }
9852
9853         dev_err(&dev->dev,
9854                 "transaction is not cleared; proceeding with reset anyway\n");
9855
9856 clear:
9857
9858         BNX2X_DEV_INFO("Initiating FLR\n");
9859         bnx2x_fw_command(bp, DRV_MSG_CODE_INITIATE_FLR, 0);
9860
9861         return 0;
9862 }
9863
9864 static int bnx2x_prev_unload_uncommon(struct bnx2x *bp)
9865 {
9866         int rc;
9867
9868         BNX2X_DEV_INFO("Uncommon unload Flow\n");
9869
9870         /* Test if previous unload process was already finished for this path */
9871         if (bnx2x_prev_is_path_marked(bp))
9872                 return bnx2x_prev_mcp_done(bp);
9873
9874         BNX2X_DEV_INFO("Path is unmarked\n");
9875
9876         /* If function has FLR capabilities, and existing FW version matches
9877          * the one required, then FLR will be sufficient to clean any residue
9878          * left by previous driver
9879          */
9880         rc = bnx2x_nic_load_analyze_req(bp, FW_MSG_CODE_DRV_LOAD_FUNCTION);
9881
9882         if (!rc) {
9883                 /* fw version is good */
9884                 BNX2X_DEV_INFO("FW version matches our own. Attempting FLR\n");
9885                 rc = bnx2x_do_flr(bp);
9886         }
9887
9888         if (!rc) {
9889                 /* FLR was performed */
9890                 BNX2X_DEV_INFO("FLR successful\n");
9891                 return 0;
9892         }
9893
9894         BNX2X_DEV_INFO("Could not FLR\n");
9895
9896         /* Close the MCP request, return failure*/
9897         rc = bnx2x_prev_mcp_done(bp);
9898         if (!rc)
9899                 rc = BNX2X_PREV_WAIT_NEEDED;
9900
9901         return rc;
9902 }
9903
9904 static int bnx2x_prev_unload_common(struct bnx2x *bp)
9905 {
9906         u32 reset_reg, tmp_reg = 0, rc;
9907         bool prev_undi = false;
9908         struct bnx2x_mac_vals mac_vals;
9909
9910         /* It is possible a previous function received 'common' answer,
9911          * but hasn't loaded yet, therefore creating a scenario of
9912          * multiple functions receiving 'common' on the same path.
9913          */
9914         BNX2X_DEV_INFO("Common unload Flow\n");
9915
9916         memset(&mac_vals, 0, sizeof(mac_vals));
9917
9918         if (bnx2x_prev_is_path_marked(bp))
9919                 return bnx2x_prev_mcp_done(bp);
9920
9921         reset_reg = REG_RD(bp, MISC_REG_RESET_REG_1);
9922
9923         /* Reset should be performed after BRB is emptied */
9924         if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_BRB1) {
9925                 u32 timer_count = 1000;
9926
9927                 /* Close the MAC Rx to prevent BRB from filling up */
9928                 bnx2x_prev_unload_close_mac(bp, &mac_vals);
9929
9930                 /* close LLH filters towards the BRB */
9931                 bnx2x_set_rx_filter(&bp->link_params, 0);
9932
9933                 /* Check if the UNDI driver was previously loaded
9934                  * UNDI driver initializes CID offset for normal bell to 0x7
9935                  */
9936                 if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_DORQ) {
9937                         tmp_reg = REG_RD(bp, DORQ_REG_NORM_CID_OFST);
9938                         if (tmp_reg == 0x7) {
9939                                 BNX2X_DEV_INFO("UNDI previously loaded\n");
9940                                 prev_undi = true;
9941                                 /* clear the UNDI indication */
9942                                 REG_WR(bp, DORQ_REG_NORM_CID_OFST, 0);
9943                                 /* clear possible idle check errors */
9944                                 REG_RD(bp, NIG_REG_NIG_INT_STS_CLR_0);
9945                         }
9946                 }
9947                 /* wait until BRB is empty */
9948                 tmp_reg = REG_RD(bp, BRB1_REG_NUM_OF_FULL_BLOCKS);
9949                 while (timer_count) {
9950                         u32 prev_brb = tmp_reg;
9951
9952                         tmp_reg = REG_RD(bp, BRB1_REG_NUM_OF_FULL_BLOCKS);
9953                         if (!tmp_reg)
9954                                 break;
9955
9956                         BNX2X_DEV_INFO("BRB still has 0x%08x\n", tmp_reg);
9957
9958                         /* reset timer as long as BRB actually gets emptied */
9959                         if (prev_brb > tmp_reg)
9960                                 timer_count = 1000;
9961                         else
9962                                 timer_count--;
9963
9964                         /* If UNDI resides in memory, manually increment it */
9965                         if (prev_undi)
9966                                 bnx2x_prev_unload_undi_inc(bp, BP_PORT(bp), 1);
9967
9968                         udelay(10);
9969                 }
9970
9971                 if (!timer_count)
9972                         BNX2X_ERR("Failed to empty BRB, hope for the best\n");
9973
9974         }
9975
9976         /* No packets are in the pipeline, path is ready for reset */
9977         bnx2x_reset_common(bp);
9978
9979         if (mac_vals.xmac_addr)
9980                 REG_WR(bp, mac_vals.xmac_addr, mac_vals.xmac_val);
9981         if (mac_vals.umac_addr)
9982                 REG_WR(bp, mac_vals.umac_addr, mac_vals.umac_val);
9983         if (mac_vals.emac_addr)
9984                 REG_WR(bp, mac_vals.emac_addr, mac_vals.emac_val);
9985         if (mac_vals.bmac_addr) {
9986                 REG_WR(bp, mac_vals.bmac_addr, mac_vals.bmac_val[0]);
9987                 REG_WR(bp, mac_vals.bmac_addr + 4, mac_vals.bmac_val[1]);
9988         }
9989
9990         rc = bnx2x_prev_mark_path(bp, prev_undi);
9991         if (rc) {
9992                 bnx2x_prev_mcp_done(bp);
9993                 return rc;
9994         }
9995
9996         return bnx2x_prev_mcp_done(bp);
9997 }
9998
9999 /* previous driver DMAE transaction may have occurred when pre-boot stage ended
10000  * and boot began, or when kdump kernel was loaded. Either case would invalidate
10001  * the addresses of the transaction, resulting in was-error bit set in the pci
10002  * causing all hw-to-host pcie transactions to timeout. If this happened we want
10003  * to clear the interrupt which detected this from the pglueb and the was done
10004  * bit
10005  */
10006 static void bnx2x_prev_interrupted_dmae(struct bnx2x *bp)
10007 {
10008         if (!CHIP_IS_E1x(bp)) {
10009                 u32 val = REG_RD(bp, PGLUE_B_REG_PGLUE_B_INT_STS);
10010                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN) {
10011                         DP(BNX2X_MSG_SP,
10012                            "'was error' bit was found to be set in pglueb upon startup. Clearing\n");
10013                         REG_WR(bp, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR,
10014                                1 << BP_FUNC(bp));
10015                 }
10016         }
10017 }
10018
10019 static int bnx2x_prev_unload(struct bnx2x *bp)
10020 {
10021         int time_counter = 10;
10022         u32 rc, fw, hw_lock_reg, hw_lock_val;
10023         struct bnx2x_prev_path_list *prev_list;
10024         BNX2X_DEV_INFO("Entering Previous Unload Flow\n");
10025
10026         /* clear hw from errors which may have resulted from an interrupted
10027          * dmae transaction.
10028          */
10029         bnx2x_prev_interrupted_dmae(bp);
10030
10031         /* Release previously held locks */
10032         hw_lock_reg = (BP_FUNC(bp) <= 5) ?
10033                       (MISC_REG_DRIVER_CONTROL_1 + BP_FUNC(bp) * 8) :
10034                       (MISC_REG_DRIVER_CONTROL_7 + (BP_FUNC(bp) - 6) * 8);
10035
10036         hw_lock_val = (REG_RD(bp, hw_lock_reg));
10037         if (hw_lock_val) {
10038                 if (hw_lock_val & HW_LOCK_RESOURCE_NVRAM) {
10039                         BNX2X_DEV_INFO("Release Previously held NVRAM lock\n");
10040                         REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
10041                                (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << BP_PORT(bp)));
10042                 }
10043
10044                 BNX2X_DEV_INFO("Release Previously held hw lock\n");
10045                 REG_WR(bp, hw_lock_reg, 0xffffffff);
10046         } else
10047                 BNX2X_DEV_INFO("No need to release hw/nvram locks\n");
10048
10049         if (MCPR_ACCESS_LOCK_LOCK & REG_RD(bp, MCP_REG_MCPR_ACCESS_LOCK)) {
10050                 BNX2X_DEV_INFO("Release previously held alr\n");
10051                 REG_WR(bp, MCP_REG_MCPR_ACCESS_LOCK, 0);
10052         }
10053
10054         do {
10055                 int aer = 0;
10056                 /* Lock MCP using an unload request */
10057                 fw = bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS, 0);
10058                 if (!fw) {
10059                         BNX2X_ERR("MCP response failure, aborting\n");
10060                         rc = -EBUSY;
10061                         break;
10062                 }
10063
10064                 rc = down_interruptible(&bnx2x_prev_sem);
10065                 if (rc) {
10066                         BNX2X_ERR("Cannot check for AER; Received %d when tried to take lock\n",
10067                                   rc);
10068                 } else {
10069                         /* If Path is marked by EEH, ignore unload status */
10070                         aer = !!(bnx2x_prev_path_get_entry(bp) &&
10071                                  bnx2x_prev_path_get_entry(bp)->aer);
10072                 }
10073                 up(&bnx2x_prev_sem);
10074
10075                 if (fw == FW_MSG_CODE_DRV_UNLOAD_COMMON || aer) {
10076                         rc = bnx2x_prev_unload_common(bp);
10077                         break;
10078                 }
10079
10080                 /* non-common reply from MCP night require looping */
10081                 rc = bnx2x_prev_unload_uncommon(bp);
10082                 if (rc != BNX2X_PREV_WAIT_NEEDED)
10083                         break;
10084
10085                 msleep(20);
10086         } while (--time_counter);
10087
10088         if (!time_counter || rc) {
10089                 BNX2X_ERR("Failed unloading previous driver, aborting\n");
10090                 rc = -EBUSY;
10091         }
10092
10093         /* Mark function if its port was used to boot from SAN */
10094         prev_list = bnx2x_prev_path_get_entry(bp);
10095         if (prev_list && (prev_list->undi & (1 << BP_PORT(bp))))
10096                 bp->link_params.feature_config_flags |=
10097                         FEATURE_CONFIG_BOOT_FROM_SAN;
10098
10099         BNX2X_DEV_INFO("Finished Previous Unload Flow [%d]\n", rc);
10100
10101         return rc;
10102 }
10103
10104 static void bnx2x_get_common_hwinfo(struct bnx2x *bp)
10105 {
10106         u32 val, val2, val3, val4, id, boot_mode;
10107         u16 pmc;
10108
10109         /* Get the chip revision id and number. */
10110         /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
10111         val = REG_RD(bp, MISC_REG_CHIP_NUM);
10112         id = ((val & 0xffff) << 16);
10113         val = REG_RD(bp, MISC_REG_CHIP_REV);
10114         id |= ((val & 0xf) << 12);
10115
10116         /* Metal is read from PCI regs, but we can't access >=0x400 from
10117          * the configuration space (so we need to reg_rd)
10118          */
10119         val = REG_RD(bp, PCICFG_OFFSET + PCI_ID_VAL3);
10120         id |= (((val >> 24) & 0xf) << 4);
10121         val = REG_RD(bp, MISC_REG_BOND_ID);
10122         id |= (val & 0xf);
10123         bp->common.chip_id = id;
10124
10125         /* force 57811 according to MISC register */
10126         if (REG_RD(bp, MISC_REG_CHIP_TYPE) & MISC_REG_CHIP_TYPE_57811_MASK) {
10127                 if (CHIP_IS_57810(bp))
10128                         bp->common.chip_id = (CHIP_NUM_57811 << 16) |
10129                                 (bp->common.chip_id & 0x0000FFFF);
10130                 else if (CHIP_IS_57810_MF(bp))
10131                         bp->common.chip_id = (CHIP_NUM_57811_MF << 16) |
10132                                 (bp->common.chip_id & 0x0000FFFF);
10133                 bp->common.chip_id |= 0x1;
10134         }
10135
10136         /* Set doorbell size */
10137         bp->db_size = (1 << BNX2X_DB_SHIFT);
10138
10139         if (!CHIP_IS_E1x(bp)) {
10140                 val = REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR);
10141                 if ((val & 1) == 0)
10142                         val = REG_RD(bp, MISC_REG_PORT4MODE_EN);
10143                 else
10144                         val = (val >> 1) & 1;
10145                 BNX2X_DEV_INFO("chip is in %s\n", val ? "4_PORT_MODE" :
10146                                                        "2_PORT_MODE");
10147                 bp->common.chip_port_mode = val ? CHIP_4_PORT_MODE :
10148                                                  CHIP_2_PORT_MODE;
10149
10150                 if (CHIP_MODE_IS_4_PORT(bp))
10151                         bp->pfid = (bp->pf_num >> 1);   /* 0..3 */
10152                 else
10153                         bp->pfid = (bp->pf_num & 0x6);  /* 0, 2, 4, 6 */
10154         } else {
10155                 bp->common.chip_port_mode = CHIP_PORT_MODE_NONE; /* N/A */
10156                 bp->pfid = bp->pf_num;                  /* 0..7 */
10157         }
10158
10159         BNX2X_DEV_INFO("pf_id: %x", bp->pfid);
10160
10161         bp->link_params.chip_id = bp->common.chip_id;
10162         BNX2X_DEV_INFO("chip ID is 0x%x\n", id);
10163
10164         val = (REG_RD(bp, 0x2874) & 0x55);
10165         if ((bp->common.chip_id & 0x1) ||
10166             (CHIP_IS_E1(bp) && val) || (CHIP_IS_E1H(bp) && (val == 0x55))) {
10167                 bp->flags |= ONE_PORT_FLAG;
10168                 BNX2X_DEV_INFO("single port device\n");
10169         }
10170
10171         val = REG_RD(bp, MCP_REG_MCPR_NVM_CFG4);
10172         bp->common.flash_size = (BNX2X_NVRAM_1MB_SIZE <<
10173                                  (val & MCPR_NVM_CFG4_FLASH_SIZE));
10174         BNX2X_DEV_INFO("flash_size 0x%x (%d)\n",
10175                        bp->common.flash_size, bp->common.flash_size);
10176
10177         bnx2x_init_shmem(bp);
10178
10179
10180
10181         bp->common.shmem2_base = REG_RD(bp, (BP_PATH(bp) ?
10182                                         MISC_REG_GENERIC_CR_1 :
10183                                         MISC_REG_GENERIC_CR_0));
10184
10185         bp->link_params.shmem_base = bp->common.shmem_base;
10186         bp->link_params.shmem2_base = bp->common.shmem2_base;
10187         if (SHMEM2_RD(bp, size) >
10188             (u32)offsetof(struct shmem2_region, lfa_host_addr[BP_PORT(bp)]))
10189                 bp->link_params.lfa_base =
10190                 REG_RD(bp, bp->common.shmem2_base +
10191                        (u32)offsetof(struct shmem2_region,
10192                                      lfa_host_addr[BP_PORT(bp)]));
10193         else
10194                 bp->link_params.lfa_base = 0;
10195         BNX2X_DEV_INFO("shmem offset 0x%x  shmem2 offset 0x%x\n",
10196                        bp->common.shmem_base, bp->common.shmem2_base);
10197
10198         if (!bp->common.shmem_base) {
10199                 BNX2X_DEV_INFO("MCP not active\n");
10200                 bp->flags |= NO_MCP_FLAG;
10201                 return;
10202         }
10203
10204         bp->common.hw_config = SHMEM_RD(bp, dev_info.shared_hw_config.config);
10205         BNX2X_DEV_INFO("hw_config 0x%08x\n", bp->common.hw_config);
10206
10207         bp->link_params.hw_led_mode = ((bp->common.hw_config &
10208                                         SHARED_HW_CFG_LED_MODE_MASK) >>
10209                                        SHARED_HW_CFG_LED_MODE_SHIFT);
10210
10211         bp->link_params.feature_config_flags = 0;
10212         val = SHMEM_RD(bp, dev_info.shared_feature_config.config);
10213         if (val & SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED)
10214                 bp->link_params.feature_config_flags |=
10215                                 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
10216         else
10217                 bp->link_params.feature_config_flags &=
10218                                 ~FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
10219
10220         val = SHMEM_RD(bp, dev_info.bc_rev) >> 8;
10221         bp->common.bc_ver = val;
10222         BNX2X_DEV_INFO("bc_ver %X\n", val);
10223         if (val < BNX2X_BC_VER) {
10224                 /* for now only warn
10225                  * later we might need to enforce this */
10226                 BNX2X_ERR("This driver needs bc_ver %X but found %X, please upgrade BC\n",
10227                           BNX2X_BC_VER, val);
10228         }
10229         bp->link_params.feature_config_flags |=
10230                                 (val >= REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL) ?
10231                                 FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY : 0;
10232
10233         bp->link_params.feature_config_flags |=
10234                 (val >= REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL) ?
10235                 FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY : 0;
10236         bp->link_params.feature_config_flags |=
10237                 (val >= REQ_BC_VER_4_VRFY_AFEX_SUPPORTED) ?
10238                 FEATURE_CONFIG_BC_SUPPORTS_AFEX : 0;
10239         bp->link_params.feature_config_flags |=
10240                 (val >= REQ_BC_VER_4_SFP_TX_DISABLE_SUPPORTED) ?
10241                 FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED : 0;
10242
10243         bp->link_params.feature_config_flags |=
10244                 (val >= REQ_BC_VER_4_MT_SUPPORTED) ?
10245                 FEATURE_CONFIG_MT_SUPPORT : 0;
10246
10247         bp->flags |= (val >= REQ_BC_VER_4_PFC_STATS_SUPPORTED) ?
10248                         BC_SUPPORTS_PFC_STATS : 0;
10249
10250         bp->flags |= (val >= REQ_BC_VER_4_FCOE_FEATURES) ?
10251                         BC_SUPPORTS_FCOE_FEATURES : 0;
10252
10253         bp->flags |= (val >= REQ_BC_VER_4_DCBX_ADMIN_MSG_NON_PMF) ?
10254                         BC_SUPPORTS_DCBX_MSG_NON_PMF : 0;
10255         boot_mode = SHMEM_RD(bp,
10256                         dev_info.port_feature_config[BP_PORT(bp)].mba_config) &
10257                         PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK;
10258         switch (boot_mode) {
10259         case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE:
10260                 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_PXE;
10261                 break;
10262         case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_ISCSIB:
10263                 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_ISCSI;
10264                 break;
10265         case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_FCOE_BOOT:
10266                 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_FCOE;
10267                 break;
10268         case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_NONE:
10269                 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_NONE;
10270                 break;
10271         }
10272
10273         pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_PMC, &pmc);
10274         bp->flags |= (pmc & PCI_PM_CAP_PME_D3cold) ? 0 : NO_WOL_FLAG;
10275
10276         BNX2X_DEV_INFO("%sWoL capable\n",
10277                        (bp->flags & NO_WOL_FLAG) ? "not " : "");
10278
10279         val = SHMEM_RD(bp, dev_info.shared_hw_config.part_num);
10280         val2 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[4]);
10281         val3 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[8]);
10282         val4 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[12]);
10283
10284         dev_info(&bp->pdev->dev, "part number %X-%X-%X-%X\n",
10285                  val, val2, val3, val4);
10286 }
10287
10288 #define IGU_FID(val)    GET_FIELD((val), IGU_REG_MAPPING_MEMORY_FID)
10289 #define IGU_VEC(val)    GET_FIELD((val), IGU_REG_MAPPING_MEMORY_VECTOR)
10290
10291 static int bnx2x_get_igu_cam_info(struct bnx2x *bp)
10292 {
10293         int pfid = BP_FUNC(bp);
10294         int igu_sb_id;
10295         u32 val;
10296         u8 fid, igu_sb_cnt = 0;
10297
10298         bp->igu_base_sb = 0xff;
10299         if (CHIP_INT_MODE_IS_BC(bp)) {
10300                 int vn = BP_VN(bp);
10301                 igu_sb_cnt = bp->igu_sb_cnt;
10302                 bp->igu_base_sb = (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn) *
10303                         FP_SB_MAX_E1x;
10304
10305                 bp->igu_dsb_id =  E1HVN_MAX * FP_SB_MAX_E1x +
10306                         (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn);
10307
10308                 return 0;
10309         }
10310
10311         /* IGU in normal mode - read CAM */
10312         for (igu_sb_id = 0; igu_sb_id < IGU_REG_MAPPING_MEMORY_SIZE;
10313              igu_sb_id++) {
10314                 val = REG_RD(bp, IGU_REG_MAPPING_MEMORY + igu_sb_id * 4);
10315                 if (!(val & IGU_REG_MAPPING_MEMORY_VALID))
10316                         continue;
10317                 fid = IGU_FID(val);
10318                 if ((fid & IGU_FID_ENCODE_IS_PF)) {
10319                         if ((fid & IGU_FID_PF_NUM_MASK) != pfid)
10320                                 continue;
10321                         if (IGU_VEC(val) == 0)
10322                                 /* default status block */
10323                                 bp->igu_dsb_id = igu_sb_id;
10324                         else {
10325                                 if (bp->igu_base_sb == 0xff)
10326                                         bp->igu_base_sb = igu_sb_id;
10327                                 igu_sb_cnt++;
10328                         }
10329                 }
10330         }
10331
10332 #ifdef CONFIG_PCI_MSI
10333         /* Due to new PF resource allocation by MFW T7.4 and above, it's
10334          * optional that number of CAM entries will not be equal to the value
10335          * advertised in PCI.
10336          * Driver should use the minimal value of both as the actual status
10337          * block count
10338          */
10339         bp->igu_sb_cnt = min_t(int, bp->igu_sb_cnt, igu_sb_cnt);
10340 #endif
10341
10342         if (igu_sb_cnt == 0) {
10343                 BNX2X_ERR("CAM configuration error\n");
10344                 return -EINVAL;
10345         }
10346
10347         return 0;
10348 }
10349
10350 static void bnx2x_link_settings_supported(struct bnx2x *bp, u32 switch_cfg)
10351 {
10352         int cfg_size = 0, idx, port = BP_PORT(bp);
10353
10354         /* Aggregation of supported attributes of all external phys */
10355         bp->port.supported[0] = 0;
10356         bp->port.supported[1] = 0;
10357         switch (bp->link_params.num_phys) {
10358         case 1:
10359                 bp->port.supported[0] = bp->link_params.phy[INT_PHY].supported;
10360                 cfg_size = 1;
10361                 break;
10362         case 2:
10363                 bp->port.supported[0] = bp->link_params.phy[EXT_PHY1].supported;
10364                 cfg_size = 1;
10365                 break;
10366         case 3:
10367                 if (bp->link_params.multi_phy_config &
10368                     PORT_HW_CFG_PHY_SWAPPED_ENABLED) {
10369                         bp->port.supported[1] =
10370                                 bp->link_params.phy[EXT_PHY1].supported;
10371                         bp->port.supported[0] =
10372                                 bp->link_params.phy[EXT_PHY2].supported;
10373                 } else {
10374                         bp->port.supported[0] =
10375                                 bp->link_params.phy[EXT_PHY1].supported;
10376                         bp->port.supported[1] =
10377                                 bp->link_params.phy[EXT_PHY2].supported;
10378                 }
10379                 cfg_size = 2;
10380                 break;
10381         }
10382
10383         if (!(bp->port.supported[0] || bp->port.supported[1])) {
10384                 BNX2X_ERR("NVRAM config error. BAD phy config. PHY1 config 0x%x, PHY2 config 0x%x\n",
10385                            SHMEM_RD(bp,
10386                            dev_info.port_hw_config[port].external_phy_config),
10387                            SHMEM_RD(bp,
10388                            dev_info.port_hw_config[port].external_phy_config2));
10389                         return;
10390         }
10391
10392         if (CHIP_IS_E3(bp))
10393                 bp->port.phy_addr = REG_RD(bp, MISC_REG_WC0_CTRL_PHY_ADDR);
10394         else {
10395                 switch (switch_cfg) {
10396                 case SWITCH_CFG_1G:
10397                         bp->port.phy_addr = REG_RD(
10398                                 bp, NIG_REG_SERDES0_CTRL_PHY_ADDR + port*0x10);
10399                         break;
10400                 case SWITCH_CFG_10G:
10401                         bp->port.phy_addr = REG_RD(
10402                                 bp, NIG_REG_XGXS0_CTRL_PHY_ADDR + port*0x18);
10403                         break;
10404                 default:
10405                         BNX2X_ERR("BAD switch_cfg link_config 0x%x\n",
10406                                   bp->port.link_config[0]);
10407                         return;
10408                 }
10409         }
10410         BNX2X_DEV_INFO("phy_addr 0x%x\n", bp->port.phy_addr);
10411         /* mask what we support according to speed_cap_mask per configuration */
10412         for (idx = 0; idx < cfg_size; idx++) {
10413                 if (!(bp->link_params.speed_cap_mask[idx] &
10414                                 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF))
10415                         bp->port.supported[idx] &= ~SUPPORTED_10baseT_Half;
10416
10417                 if (!(bp->link_params.speed_cap_mask[idx] &
10418                                 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL))
10419                         bp->port.supported[idx] &= ~SUPPORTED_10baseT_Full;
10420
10421                 if (!(bp->link_params.speed_cap_mask[idx] &
10422                                 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF))
10423                         bp->port.supported[idx] &= ~SUPPORTED_100baseT_Half;
10424
10425                 if (!(bp->link_params.speed_cap_mask[idx] &
10426                                 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL))
10427                         bp->port.supported[idx] &= ~SUPPORTED_100baseT_Full;
10428
10429                 if (!(bp->link_params.speed_cap_mask[idx] &
10430                                         PORT_HW_CFG_SPEED_CAPABILITY_D0_1G))
10431                         bp->port.supported[idx] &= ~(SUPPORTED_1000baseT_Half |
10432                                                      SUPPORTED_1000baseT_Full);
10433
10434                 if (!(bp->link_params.speed_cap_mask[idx] &
10435                                         PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G))
10436                         bp->port.supported[idx] &= ~SUPPORTED_2500baseX_Full;
10437
10438                 if (!(bp->link_params.speed_cap_mask[idx] &
10439                                         PORT_HW_CFG_SPEED_CAPABILITY_D0_10G))
10440                         bp->port.supported[idx] &= ~SUPPORTED_10000baseT_Full;
10441
10442         }
10443
10444         BNX2X_DEV_INFO("supported 0x%x 0x%x\n", bp->port.supported[0],
10445                        bp->port.supported[1]);
10446 }
10447
10448 static void bnx2x_link_settings_requested(struct bnx2x *bp)
10449 {
10450         u32 link_config, idx, cfg_size = 0;
10451         bp->port.advertising[0] = 0;
10452         bp->port.advertising[1] = 0;
10453         switch (bp->link_params.num_phys) {
10454         case 1:
10455         case 2:
10456                 cfg_size = 1;
10457                 break;
10458         case 3:
10459                 cfg_size = 2;
10460                 break;
10461         }
10462         for (idx = 0; idx < cfg_size; idx++) {
10463                 bp->link_params.req_duplex[idx] = DUPLEX_FULL;
10464                 link_config = bp->port.link_config[idx];
10465                 switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) {
10466                 case PORT_FEATURE_LINK_SPEED_AUTO:
10467                         if (bp->port.supported[idx] & SUPPORTED_Autoneg) {
10468                                 bp->link_params.req_line_speed[idx] =
10469                                         SPEED_AUTO_NEG;
10470                                 bp->port.advertising[idx] |=
10471                                         bp->port.supported[idx];
10472                                 if (bp->link_params.phy[EXT_PHY1].type ==
10473                                     PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833)
10474                                         bp->port.advertising[idx] |=
10475                                         (SUPPORTED_100baseT_Half |
10476                                          SUPPORTED_100baseT_Full);
10477                         } else {
10478                                 /* force 10G, no AN */
10479                                 bp->link_params.req_line_speed[idx] =
10480                                         SPEED_10000;
10481                                 bp->port.advertising[idx] |=
10482                                         (ADVERTISED_10000baseT_Full |
10483                                          ADVERTISED_FIBRE);
10484                                 continue;
10485                         }
10486                         break;
10487
10488                 case PORT_FEATURE_LINK_SPEED_10M_FULL:
10489                         if (bp->port.supported[idx] & SUPPORTED_10baseT_Full) {
10490                                 bp->link_params.req_line_speed[idx] =
10491                                         SPEED_10;
10492                                 bp->port.advertising[idx] |=
10493                                         (ADVERTISED_10baseT_Full |
10494                                          ADVERTISED_TP);
10495                         } else {
10496                                 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x  speed_cap_mask 0x%x\n",
10497                                             link_config,
10498                                     bp->link_params.speed_cap_mask[idx]);
10499                                 return;
10500                         }
10501                         break;
10502
10503                 case PORT_FEATURE_LINK_SPEED_10M_HALF:
10504                         if (bp->port.supported[idx] & SUPPORTED_10baseT_Half) {
10505                                 bp->link_params.req_line_speed[idx] =
10506                                         SPEED_10;
10507                                 bp->link_params.req_duplex[idx] =
10508                                         DUPLEX_HALF;
10509                                 bp->port.advertising[idx] |=
10510                                         (ADVERTISED_10baseT_Half |
10511                                          ADVERTISED_TP);
10512                         } else {
10513                                 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x  speed_cap_mask 0x%x\n",
10514                                             link_config,
10515                                           bp->link_params.speed_cap_mask[idx]);
10516                                 return;
10517                         }
10518                         break;
10519
10520                 case PORT_FEATURE_LINK_SPEED_100M_FULL:
10521                         if (bp->port.supported[idx] &
10522                             SUPPORTED_100baseT_Full) {
10523                                 bp->link_params.req_line_speed[idx] =
10524                                         SPEED_100;
10525                                 bp->port.advertising[idx] |=
10526                                         (ADVERTISED_100baseT_Full |
10527                                          ADVERTISED_TP);
10528                         } else {
10529                                 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x  speed_cap_mask 0x%x\n",
10530                                             link_config,
10531                                           bp->link_params.speed_cap_mask[idx]);
10532                                 return;
10533                         }
10534                         break;
10535
10536                 case PORT_FEATURE_LINK_SPEED_100M_HALF:
10537                         if (bp->port.supported[idx] &
10538                             SUPPORTED_100baseT_Half) {
10539                                 bp->link_params.req_line_speed[idx] =
10540                                                                 SPEED_100;
10541                                 bp->link_params.req_duplex[idx] =
10542                                                                 DUPLEX_HALF;
10543                                 bp->port.advertising[idx] |=
10544                                         (ADVERTISED_100baseT_Half |
10545                                          ADVERTISED_TP);
10546                         } else {
10547                                 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x  speed_cap_mask 0x%x\n",
10548                                     link_config,
10549                                     bp->link_params.speed_cap_mask[idx]);
10550                                 return;
10551                         }
10552                         break;
10553
10554                 case PORT_FEATURE_LINK_SPEED_1G:
10555                         if (bp->port.supported[idx] &
10556                             SUPPORTED_1000baseT_Full) {
10557                                 bp->link_params.req_line_speed[idx] =
10558                                         SPEED_1000;
10559                                 bp->port.advertising[idx] |=
10560                                         (ADVERTISED_1000baseT_Full |
10561                                          ADVERTISED_TP);
10562                         } else {
10563                                 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x  speed_cap_mask 0x%x\n",
10564                                     link_config,
10565                                     bp->link_params.speed_cap_mask[idx]);
10566                                 return;
10567                         }
10568                         break;
10569
10570                 case PORT_FEATURE_LINK_SPEED_2_5G:
10571                         if (bp->port.supported[idx] &
10572                             SUPPORTED_2500baseX_Full) {
10573                                 bp->link_params.req_line_speed[idx] =
10574                                         SPEED_2500;
10575                                 bp->port.advertising[idx] |=
10576                                         (ADVERTISED_2500baseX_Full |
10577                                                 ADVERTISED_TP);
10578                         } else {
10579                                 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x  speed_cap_mask 0x%x\n",
10580                                     link_config,
10581                                     bp->link_params.speed_cap_mask[idx]);
10582                                 return;
10583                         }
10584                         break;
10585
10586                 case PORT_FEATURE_LINK_SPEED_10G_CX4:
10587                         if (bp->port.supported[idx] &
10588                             SUPPORTED_10000baseT_Full) {
10589                                 bp->link_params.req_line_speed[idx] =
10590                                         SPEED_10000;
10591                                 bp->port.advertising[idx] |=
10592                                         (ADVERTISED_10000baseT_Full |
10593                                                 ADVERTISED_FIBRE);
10594                         } else {
10595                                 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x  speed_cap_mask 0x%x\n",
10596                                     link_config,
10597                                     bp->link_params.speed_cap_mask[idx]);
10598                                 return;
10599                         }
10600                         break;
10601                 case PORT_FEATURE_LINK_SPEED_20G:
10602                         bp->link_params.req_line_speed[idx] = SPEED_20000;
10603
10604                         break;
10605                 default:
10606                         BNX2X_ERR("NVRAM config error. BAD link speed link_config 0x%x\n",
10607                                   link_config);
10608                                 bp->link_params.req_line_speed[idx] =
10609                                                         SPEED_AUTO_NEG;
10610                                 bp->port.advertising[idx] =
10611                                                 bp->port.supported[idx];
10612                         break;
10613                 }
10614
10615                 bp->link_params.req_flow_ctrl[idx] = (link_config &
10616                                          PORT_FEATURE_FLOW_CONTROL_MASK);
10617                 if (bp->link_params.req_flow_ctrl[idx] ==
10618                     BNX2X_FLOW_CTRL_AUTO) {
10619                         if (!(bp->port.supported[idx] & SUPPORTED_Autoneg))
10620                                 bp->link_params.req_flow_ctrl[idx] =
10621                                                         BNX2X_FLOW_CTRL_NONE;
10622                         else
10623                                 bnx2x_set_requested_fc(bp);
10624                 }
10625
10626                 BNX2X_DEV_INFO("req_line_speed %d  req_duplex %d req_flow_ctrl 0x%x advertising 0x%x\n",
10627                                bp->link_params.req_line_speed[idx],
10628                                bp->link_params.req_duplex[idx],
10629                                bp->link_params.req_flow_ctrl[idx],
10630                                bp->port.advertising[idx]);
10631         }
10632 }
10633
10634 static void bnx2x_set_mac_buf(u8 *mac_buf, u32 mac_lo, u16 mac_hi)
10635 {
10636         __be16 mac_hi_be = cpu_to_be16(mac_hi);
10637         __be32 mac_lo_be = cpu_to_be32(mac_lo);
10638         memcpy(mac_buf, &mac_hi_be, sizeof(mac_hi_be));
10639         memcpy(mac_buf + sizeof(mac_hi_be), &mac_lo_be, sizeof(mac_lo_be));
10640 }
10641
10642 static void bnx2x_get_port_hwinfo(struct bnx2x *bp)
10643 {
10644         int port = BP_PORT(bp);
10645         u32 config;
10646         u32 ext_phy_type, ext_phy_config, eee_mode;
10647
10648         bp->link_params.bp = bp;
10649         bp->link_params.port = port;
10650
10651         bp->link_params.lane_config =
10652                 SHMEM_RD(bp, dev_info.port_hw_config[port].lane_config);
10653
10654         bp->link_params.speed_cap_mask[0] =
10655                 SHMEM_RD(bp,
10656                          dev_info.port_hw_config[port].speed_capability_mask);
10657         bp->link_params.speed_cap_mask[1] =
10658                 SHMEM_RD(bp,
10659                          dev_info.port_hw_config[port].speed_capability_mask2);
10660         bp->port.link_config[0] =
10661                 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config);
10662
10663         bp->port.link_config[1] =
10664                 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config2);
10665
10666         bp->link_params.multi_phy_config =
10667                 SHMEM_RD(bp, dev_info.port_hw_config[port].multi_phy_config);
10668         /* If the device is capable of WoL, set the default state according
10669          * to the HW
10670          */
10671         config = SHMEM_RD(bp, dev_info.port_feature_config[port].config);
10672         bp->wol = (!(bp->flags & NO_WOL_FLAG) &&
10673                    (config & PORT_FEATURE_WOL_ENABLED));
10674
10675         if ((config & PORT_FEAT_CFG_STORAGE_PERSONALITY_MASK) ==
10676             PORT_FEAT_CFG_STORAGE_PERSONALITY_FCOE && !IS_MF(bp))
10677                 bp->flags |= NO_ISCSI_FLAG;
10678         if ((config & PORT_FEAT_CFG_STORAGE_PERSONALITY_MASK) ==
10679             PORT_FEAT_CFG_STORAGE_PERSONALITY_ISCSI && !(IS_MF(bp)))
10680                 bp->flags |= NO_FCOE_FLAG;
10681
10682         BNX2X_DEV_INFO("lane_config 0x%08x  speed_cap_mask0 0x%08x  link_config0 0x%08x\n",
10683                        bp->link_params.lane_config,
10684                        bp->link_params.speed_cap_mask[0],
10685                        bp->port.link_config[0]);
10686
10687         bp->link_params.switch_cfg = (bp->port.link_config[0] &
10688                                       PORT_FEATURE_CONNECTED_SWITCH_MASK);
10689         bnx2x_phy_probe(&bp->link_params);
10690         bnx2x_link_settings_supported(bp, bp->link_params.switch_cfg);
10691
10692         bnx2x_link_settings_requested(bp);
10693
10694         /*
10695          * If connected directly, work with the internal PHY, otherwise, work
10696          * with the external PHY
10697          */
10698         ext_phy_config =
10699                 SHMEM_RD(bp,
10700                          dev_info.port_hw_config[port].external_phy_config);
10701         ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
10702         if (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
10703                 bp->mdio.prtad = bp->port.phy_addr;
10704
10705         else if ((ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) &&
10706                  (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN))
10707                 bp->mdio.prtad =
10708                         XGXS_EXT_PHY_ADDR(ext_phy_config);
10709
10710         /* Configure link feature according to nvram value */
10711         eee_mode = (((SHMEM_RD(bp, dev_info.
10712                       port_feature_config[port].eee_power_mode)) &
10713                      PORT_FEAT_CFG_EEE_POWER_MODE_MASK) >>
10714                     PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT);
10715         if (eee_mode != PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED) {
10716                 bp->link_params.eee_mode = EEE_MODE_ADV_LPI |
10717                                            EEE_MODE_ENABLE_LPI |
10718                                            EEE_MODE_OUTPUT_TIME;
10719         } else {
10720                 bp->link_params.eee_mode = 0;
10721         }
10722 }
10723
10724 void bnx2x_get_iscsi_info(struct bnx2x *bp)
10725 {
10726         u32 no_flags = NO_ISCSI_FLAG;
10727         int port = BP_PORT(bp);
10728         u32 max_iscsi_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp,
10729                                 drv_lic_key[port].max_iscsi_conn);
10730
10731         if (!CNIC_SUPPORT(bp)) {
10732                 bp->flags |= no_flags;
10733                 return;
10734         }
10735
10736         /* Get the number of maximum allowed iSCSI connections */
10737         bp->cnic_eth_dev.max_iscsi_conn =
10738                 (max_iscsi_conn & BNX2X_MAX_ISCSI_INIT_CONN_MASK) >>
10739                 BNX2X_MAX_ISCSI_INIT_CONN_SHIFT;
10740
10741         BNX2X_DEV_INFO("max_iscsi_conn 0x%x\n",
10742                        bp->cnic_eth_dev.max_iscsi_conn);
10743
10744         /*
10745          * If maximum allowed number of connections is zero -
10746          * disable the feature.
10747          */
10748         if (!bp->cnic_eth_dev.max_iscsi_conn)
10749                 bp->flags |= no_flags;
10750
10751 }
10752
10753 static void bnx2x_get_ext_wwn_info(struct bnx2x *bp, int func)
10754 {
10755         /* Port info */
10756         bp->cnic_eth_dev.fcoe_wwn_port_name_hi =
10757                 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_port_name_upper);
10758         bp->cnic_eth_dev.fcoe_wwn_port_name_lo =
10759                 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_port_name_lower);
10760
10761         /* Node info */
10762         bp->cnic_eth_dev.fcoe_wwn_node_name_hi =
10763                 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_node_name_upper);
10764         bp->cnic_eth_dev.fcoe_wwn_node_name_lo =
10765                 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_node_name_lower);
10766 }
10767 static void bnx2x_get_fcoe_info(struct bnx2x *bp)
10768 {
10769         int port = BP_PORT(bp);
10770         int func = BP_ABS_FUNC(bp);
10771         u32 max_fcoe_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp,
10772                                 drv_lic_key[port].max_fcoe_conn);
10773
10774         if (!CNIC_SUPPORT(bp)) {
10775                 bp->flags |= NO_FCOE_FLAG;
10776                 return;
10777         }
10778
10779         /* Get the number of maximum allowed FCoE connections */
10780         bp->cnic_eth_dev.max_fcoe_conn =
10781                 (max_fcoe_conn & BNX2X_MAX_FCOE_INIT_CONN_MASK) >>
10782                 BNX2X_MAX_FCOE_INIT_CONN_SHIFT;
10783
10784         /* Read the WWN: */
10785         if (!IS_MF(bp)) {
10786                 /* Port info */
10787                 bp->cnic_eth_dev.fcoe_wwn_port_name_hi =
10788                         SHMEM_RD(bp,
10789                                  dev_info.port_hw_config[port].
10790                                  fcoe_wwn_port_name_upper);
10791                 bp->cnic_eth_dev.fcoe_wwn_port_name_lo =
10792                         SHMEM_RD(bp,
10793                                  dev_info.port_hw_config[port].
10794                                  fcoe_wwn_port_name_lower);
10795
10796                 /* Node info */
10797                 bp->cnic_eth_dev.fcoe_wwn_node_name_hi =
10798                         SHMEM_RD(bp,
10799                                  dev_info.port_hw_config[port].
10800                                  fcoe_wwn_node_name_upper);
10801                 bp->cnic_eth_dev.fcoe_wwn_node_name_lo =
10802                         SHMEM_RD(bp,
10803                                  dev_info.port_hw_config[port].
10804                                  fcoe_wwn_node_name_lower);
10805         } else if (!IS_MF_SD(bp)) {
10806                 /*
10807                  * Read the WWN info only if the FCoE feature is enabled for
10808                  * this function.
10809                  */
10810                 if (BNX2X_MF_EXT_PROTOCOL_FCOE(bp) && !CHIP_IS_E1x(bp))
10811                         bnx2x_get_ext_wwn_info(bp, func);
10812
10813         } else if (IS_MF_FCOE_SD(bp) && !CHIP_IS_E1x(bp)) {
10814                 bnx2x_get_ext_wwn_info(bp, func);
10815         }
10816
10817         BNX2X_DEV_INFO("max_fcoe_conn 0x%x\n", bp->cnic_eth_dev.max_fcoe_conn);
10818
10819         /*
10820          * If maximum allowed number of connections is zero -
10821          * disable the feature.
10822          */
10823         if (!bp->cnic_eth_dev.max_fcoe_conn)
10824                 bp->flags |= NO_FCOE_FLAG;
10825 }
10826
10827 static void bnx2x_get_cnic_info(struct bnx2x *bp)
10828 {
10829         /*
10830          * iSCSI may be dynamically disabled but reading
10831          * info here we will decrease memory usage by driver
10832          * if the feature is disabled for good
10833          */
10834         bnx2x_get_iscsi_info(bp);
10835         bnx2x_get_fcoe_info(bp);
10836 }
10837
10838 static void bnx2x_get_cnic_mac_hwinfo(struct bnx2x *bp)
10839 {
10840         u32 val, val2;
10841         int func = BP_ABS_FUNC(bp);
10842         int port = BP_PORT(bp);
10843         u8 *iscsi_mac = bp->cnic_eth_dev.iscsi_mac;
10844         u8 *fip_mac = bp->fip_mac;
10845
10846         if (IS_MF(bp)) {
10847                 /* iSCSI and FCoE NPAR MACs: if there is no either iSCSI or
10848                  * FCoE MAC then the appropriate feature should be disabled.
10849                  * In non SD mode features configuration comes from struct
10850                  * func_ext_config.
10851                  */
10852                 if (!IS_MF_SD(bp) && !CHIP_IS_E1x(bp)) {
10853                         u32 cfg = MF_CFG_RD(bp, func_ext_config[func].func_cfg);
10854                         if (cfg & MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD) {
10855                                 val2 = MF_CFG_RD(bp, func_ext_config[func].
10856                                                  iscsi_mac_addr_upper);
10857                                 val = MF_CFG_RD(bp, func_ext_config[func].
10858                                                 iscsi_mac_addr_lower);
10859                                 bnx2x_set_mac_buf(iscsi_mac, val, val2);
10860                                 BNX2X_DEV_INFO
10861                                         ("Read iSCSI MAC: %pM\n", iscsi_mac);
10862                         } else {
10863                                 bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG;
10864                         }
10865
10866                         if (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) {
10867                                 val2 = MF_CFG_RD(bp, func_ext_config[func].
10868                                                  fcoe_mac_addr_upper);
10869                                 val = MF_CFG_RD(bp, func_ext_config[func].
10870                                                 fcoe_mac_addr_lower);
10871                                 bnx2x_set_mac_buf(fip_mac, val, val2);
10872                                 BNX2X_DEV_INFO
10873                                         ("Read FCoE L2 MAC: %pM\n", fip_mac);
10874                         } else {
10875                                 bp->flags |= NO_FCOE_FLAG;
10876                         }
10877
10878                         bp->mf_ext_config = cfg;
10879
10880                 } else { /* SD MODE */
10881                         if (BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp)) {
10882                                 /* use primary mac as iscsi mac */
10883                                 memcpy(iscsi_mac, bp->dev->dev_addr, ETH_ALEN);
10884
10885                                 BNX2X_DEV_INFO("SD ISCSI MODE\n");
10886                                 BNX2X_DEV_INFO
10887                                         ("Read iSCSI MAC: %pM\n", iscsi_mac);
10888                         } else if (BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp)) {
10889                                 /* use primary mac as fip mac */
10890                                 memcpy(fip_mac, bp->dev->dev_addr, ETH_ALEN);
10891                                 BNX2X_DEV_INFO("SD FCoE MODE\n");
10892                                 BNX2X_DEV_INFO
10893                                         ("Read FIP MAC: %pM\n", fip_mac);
10894                         }
10895                 }
10896
10897                 /* If this is a storage-only interface, use SAN mac as
10898                  * primary MAC. Notice that for SD this is already the case,
10899                  * as the SAN mac was copied from the primary MAC.
10900                  */
10901                 if (IS_MF_FCOE_AFEX(bp))
10902                         memcpy(bp->dev->dev_addr, fip_mac, ETH_ALEN);
10903         } else {
10904                 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].
10905                                 iscsi_mac_upper);
10906                 val = SHMEM_RD(bp, dev_info.port_hw_config[port].
10907                                iscsi_mac_lower);
10908                 bnx2x_set_mac_buf(iscsi_mac, val, val2);
10909
10910                 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].
10911                                 fcoe_fip_mac_upper);
10912                 val = SHMEM_RD(bp, dev_info.port_hw_config[port].
10913                                fcoe_fip_mac_lower);
10914                 bnx2x_set_mac_buf(fip_mac, val, val2);
10915         }
10916
10917         /* Disable iSCSI OOO if MAC configuration is invalid. */
10918         if (!is_valid_ether_addr(iscsi_mac)) {
10919                 bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG;
10920                 memset(iscsi_mac, 0, ETH_ALEN);
10921         }
10922
10923         /* Disable FCoE if MAC configuration is invalid. */
10924         if (!is_valid_ether_addr(fip_mac)) {
10925                 bp->flags |= NO_FCOE_FLAG;
10926                 memset(bp->fip_mac, 0, ETH_ALEN);
10927         }
10928 }
10929
10930 static void bnx2x_get_mac_hwinfo(struct bnx2x *bp)
10931 {
10932         u32 val, val2;
10933         int func = BP_ABS_FUNC(bp);
10934         int port = BP_PORT(bp);
10935
10936         /* Zero primary MAC configuration */
10937         memset(bp->dev->dev_addr, 0, ETH_ALEN);
10938
10939         if (BP_NOMCP(bp)) {
10940                 BNX2X_ERROR("warning: random MAC workaround active\n");
10941                 eth_hw_addr_random(bp->dev);
10942         } else if (IS_MF(bp)) {
10943                 val2 = MF_CFG_RD(bp, func_mf_config[func].mac_upper);
10944                 val = MF_CFG_RD(bp, func_mf_config[func].mac_lower);
10945                 if ((val2 != FUNC_MF_CFG_UPPERMAC_DEFAULT) &&
10946                     (val != FUNC_MF_CFG_LOWERMAC_DEFAULT))
10947                         bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2);
10948
10949                 if (CNIC_SUPPORT(bp))
10950                         bnx2x_get_cnic_mac_hwinfo(bp);
10951         } else {
10952                 /* in SF read MACs from port configuration */
10953                 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_upper);
10954                 val = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_lower);
10955                 bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2);
10956
10957                 if (CNIC_SUPPORT(bp))
10958                         bnx2x_get_cnic_mac_hwinfo(bp);
10959         }
10960
10961         memcpy(bp->link_params.mac_addr, bp->dev->dev_addr, ETH_ALEN);
10962
10963         if (!bnx2x_is_valid_ether_addr(bp, bp->dev->dev_addr))
10964                 dev_err(&bp->pdev->dev,
10965                         "bad Ethernet MAC address configuration: %pM\n"
10966                         "change it manually before bringing up the appropriate network interface\n",
10967                         bp->dev->dev_addr);
10968 }
10969
10970 static bool bnx2x_get_dropless_info(struct bnx2x *bp)
10971 {
10972         int tmp;
10973         u32 cfg;
10974
10975         if (IS_MF(bp) && !CHIP_IS_E1x(bp)) {
10976                 /* Take function: tmp = func */
10977                 tmp = BP_ABS_FUNC(bp);
10978                 cfg = MF_CFG_RD(bp, func_ext_config[tmp].func_cfg);
10979                 cfg = !!(cfg & MACP_FUNC_CFG_PAUSE_ON_HOST_RING);
10980         } else {
10981                 /* Take port: tmp = port */
10982                 tmp = BP_PORT(bp);
10983                 cfg = SHMEM_RD(bp,
10984                                dev_info.port_hw_config[tmp].generic_features);
10985                 cfg = !!(cfg & PORT_HW_CFG_PAUSE_ON_HOST_RING_ENABLED);
10986         }
10987         return cfg;
10988 }
10989
10990 static int bnx2x_get_hwinfo(struct bnx2x *bp)
10991 {
10992         int /*abs*/func = BP_ABS_FUNC(bp);
10993         int vn;
10994         u32 val = 0;
10995         int rc = 0;
10996
10997         bnx2x_get_common_hwinfo(bp);
10998
10999         /*
11000          * initialize IGU parameters
11001          */
11002         if (CHIP_IS_E1x(bp)) {
11003                 bp->common.int_block = INT_BLOCK_HC;
11004
11005                 bp->igu_dsb_id = DEF_SB_IGU_ID;
11006                 bp->igu_base_sb = 0;
11007         } else {
11008                 bp->common.int_block = INT_BLOCK_IGU;
11009
11010                 /* do not allow device reset during IGU info preocessing */
11011                 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
11012
11013                 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION);
11014
11015                 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
11016                         int tout = 5000;
11017
11018                         BNX2X_DEV_INFO("FORCING Normal Mode\n");
11019
11020                         val &= ~(IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN);
11021                         REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION, val);
11022                         REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x7f);
11023
11024                         while (tout && REG_RD(bp, IGU_REG_RESET_MEMORIES)) {
11025                                 tout--;
11026                                 usleep_range(1000, 2000);
11027                         }
11028
11029                         if (REG_RD(bp, IGU_REG_RESET_MEMORIES)) {
11030                                 dev_err(&bp->pdev->dev,
11031                                         "FORCING Normal Mode failed!!!\n");
11032                                 bnx2x_release_hw_lock(bp,
11033                                                       HW_LOCK_RESOURCE_RESET);
11034                                 return -EPERM;
11035                         }
11036                 }
11037
11038                 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
11039                         BNX2X_DEV_INFO("IGU Backward Compatible Mode\n");
11040                         bp->common.int_block |= INT_BLOCK_MODE_BW_COMP;
11041                 } else
11042                         BNX2X_DEV_INFO("IGU Normal Mode\n");
11043
11044                 rc = bnx2x_get_igu_cam_info(bp);
11045                 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
11046                 if (rc)
11047                         return rc;
11048         }
11049
11050         /*
11051          * set base FW non-default (fast path) status block id, this value is
11052          * used to initialize the fw_sb_id saved on the fp/queue structure to
11053          * determine the id used by the FW.
11054          */
11055         if (CHIP_IS_E1x(bp))
11056                 bp->base_fw_ndsb = BP_PORT(bp) * FP_SB_MAX_E1x + BP_L_ID(bp);
11057         else /*
11058               * 57712 - we currently use one FW SB per IGU SB (Rx and Tx of
11059               * the same queue are indicated on the same IGU SB). So we prefer
11060               * FW and IGU SBs to be the same value.
11061               */
11062                 bp->base_fw_ndsb = bp->igu_base_sb;
11063
11064         BNX2X_DEV_INFO("igu_dsb_id %d  igu_base_sb %d  igu_sb_cnt %d\n"
11065                        "base_fw_ndsb %d\n", bp->igu_dsb_id, bp->igu_base_sb,
11066                        bp->igu_sb_cnt, bp->base_fw_ndsb);
11067
11068         /*
11069          * Initialize MF configuration
11070          */
11071
11072         bp->mf_ov = 0;
11073         bp->mf_mode = 0;
11074         vn = BP_VN(bp);
11075
11076         if (!CHIP_IS_E1(bp) && !BP_NOMCP(bp)) {
11077                 BNX2X_DEV_INFO("shmem2base 0x%x, size %d, mfcfg offset %d\n",
11078                                bp->common.shmem2_base, SHMEM2_RD(bp, size),
11079                               (u32)offsetof(struct shmem2_region, mf_cfg_addr));
11080
11081                 if (SHMEM2_HAS(bp, mf_cfg_addr))
11082                         bp->common.mf_cfg_base = SHMEM2_RD(bp, mf_cfg_addr);
11083                 else
11084                         bp->common.mf_cfg_base = bp->common.shmem_base +
11085                                 offsetof(struct shmem_region, func_mb) +
11086                                 E1H_FUNC_MAX * sizeof(struct drv_func_mb);
11087                 /*
11088                  * get mf configuration:
11089                  * 1. existence of MF configuration
11090                  * 2. MAC address must be legal (check only upper bytes)
11091                  *    for  Switch-Independent mode;
11092                  *    OVLAN must be legal for Switch-Dependent mode
11093                  * 3. SF_MODE configures specific MF mode
11094                  */
11095                 if (bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) {
11096                         /* get mf configuration */
11097                         val = SHMEM_RD(bp,
11098                                        dev_info.shared_feature_config.config);
11099                         val &= SHARED_FEAT_CFG_FORCE_SF_MODE_MASK;
11100
11101                         switch (val) {
11102                         case SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT:
11103                                 val = MF_CFG_RD(bp, func_mf_config[func].
11104                                                 mac_upper);
11105                                 /* check for legal mac (upper bytes)*/
11106                                 if (val != 0xffff) {
11107                                         bp->mf_mode = MULTI_FUNCTION_SI;
11108                                         bp->mf_config[vn] = MF_CFG_RD(bp,
11109                                                    func_mf_config[func].config);
11110                                 } else
11111                                         BNX2X_DEV_INFO("illegal MAC address for SI\n");
11112                                 break;
11113                         case SHARED_FEAT_CFG_FORCE_SF_MODE_AFEX_MODE:
11114                                 if ((!CHIP_IS_E1x(bp)) &&
11115                                     (MF_CFG_RD(bp, func_mf_config[func].
11116                                                mac_upper) != 0xffff) &&
11117                                     (SHMEM2_HAS(bp,
11118                                                 afex_driver_support))) {
11119                                         bp->mf_mode = MULTI_FUNCTION_AFEX;
11120                                         bp->mf_config[vn] = MF_CFG_RD(bp,
11121                                                 func_mf_config[func].config);
11122                                 } else {
11123                                         BNX2X_DEV_INFO("can not configure afex mode\n");
11124                                 }
11125                                 break;
11126                         case SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED:
11127                                 /* get OV configuration */
11128                                 val = MF_CFG_RD(bp,
11129                                         func_mf_config[FUNC_0].e1hov_tag);
11130                                 val &= FUNC_MF_CFG_E1HOV_TAG_MASK;
11131
11132                                 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
11133                                         bp->mf_mode = MULTI_FUNCTION_SD;
11134                                         bp->mf_config[vn] = MF_CFG_RD(bp,
11135                                                 func_mf_config[func].config);
11136                                 } else
11137                                         BNX2X_DEV_INFO("illegal OV for SD\n");
11138                                 break;
11139                         case SHARED_FEAT_CFG_FORCE_SF_MODE_FORCED_SF:
11140                                 bp->mf_config[vn] = 0;
11141                                 break;
11142                         default:
11143                                 /* Unknown configuration: reset mf_config */
11144                                 bp->mf_config[vn] = 0;
11145                                 BNX2X_DEV_INFO("unknown MF mode 0x%x\n", val);
11146                         }
11147                 }
11148
11149                 BNX2X_DEV_INFO("%s function mode\n",
11150                                IS_MF(bp) ? "multi" : "single");
11151
11152                 switch (bp->mf_mode) {
11153                 case MULTI_FUNCTION_SD:
11154                         val = MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
11155                               FUNC_MF_CFG_E1HOV_TAG_MASK;
11156                         if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
11157                                 bp->mf_ov = val;
11158                                 bp->path_has_ovlan = true;
11159
11160                                 BNX2X_DEV_INFO("MF OV for func %d is %d (0x%04x)\n",
11161                                                func, bp->mf_ov, bp->mf_ov);
11162                         } else {
11163                                 dev_err(&bp->pdev->dev,
11164                                         "No valid MF OV for func %d, aborting\n",
11165                                         func);
11166                                 return -EPERM;
11167                         }
11168                         break;
11169                 case MULTI_FUNCTION_AFEX:
11170                         BNX2X_DEV_INFO("func %d is in MF afex mode\n", func);
11171                         break;
11172                 case MULTI_FUNCTION_SI:
11173                         BNX2X_DEV_INFO("func %d is in MF switch-independent mode\n",
11174                                        func);
11175                         break;
11176                 default:
11177                         if (vn) {
11178                                 dev_err(&bp->pdev->dev,
11179                                         "VN %d is in a single function mode, aborting\n",
11180                                         vn);
11181                                 return -EPERM;
11182                         }
11183                         break;
11184                 }
11185
11186                 /* check if other port on the path needs ovlan:
11187                  * Since MF configuration is shared between ports
11188                  * Possible mixed modes are only
11189                  * {SF, SI} {SF, SD} {SD, SF} {SI, SF}
11190                  */
11191                 if (CHIP_MODE_IS_4_PORT(bp) &&
11192                     !bp->path_has_ovlan &&
11193                     !IS_MF(bp) &&
11194                     bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) {
11195                         u8 other_port = !BP_PORT(bp);
11196                         u8 other_func = BP_PATH(bp) + 2*other_port;
11197                         val = MF_CFG_RD(bp,
11198                                         func_mf_config[other_func].e1hov_tag);
11199                         if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT)
11200                                 bp->path_has_ovlan = true;
11201                 }
11202         }
11203
11204         /* adjust igu_sb_cnt to MF for E1x */
11205         if (CHIP_IS_E1x(bp) && IS_MF(bp))
11206                 bp->igu_sb_cnt /= E1HVN_MAX;
11207
11208         /* port info */
11209         bnx2x_get_port_hwinfo(bp);
11210
11211         /* Get MAC addresses */
11212         bnx2x_get_mac_hwinfo(bp);
11213
11214         bnx2x_get_cnic_info(bp);
11215
11216         return rc;
11217 }
11218
11219 static void bnx2x_read_fwinfo(struct bnx2x *bp)
11220 {
11221         int cnt, i, block_end, rodi;
11222         char vpd_start[BNX2X_VPD_LEN+1];
11223         char str_id_reg[VENDOR_ID_LEN+1];
11224         char str_id_cap[VENDOR_ID_LEN+1];
11225         char *vpd_data;
11226         char *vpd_extended_data = NULL;
11227         u8 len;
11228
11229         cnt = pci_read_vpd(bp->pdev, 0, BNX2X_VPD_LEN, vpd_start);
11230         memset(bp->fw_ver, 0, sizeof(bp->fw_ver));
11231
11232         if (cnt < BNX2X_VPD_LEN)
11233                 goto out_not_found;
11234
11235         /* VPD RO tag should be first tag after identifier string, hence
11236          * we should be able to find it in first BNX2X_VPD_LEN chars
11237          */
11238         i = pci_vpd_find_tag(vpd_start, 0, BNX2X_VPD_LEN,
11239                              PCI_VPD_LRDT_RO_DATA);
11240         if (i < 0)
11241                 goto out_not_found;
11242
11243         block_end = i + PCI_VPD_LRDT_TAG_SIZE +
11244                     pci_vpd_lrdt_size(&vpd_start[i]);
11245
11246         i += PCI_VPD_LRDT_TAG_SIZE;
11247
11248         if (block_end > BNX2X_VPD_LEN) {
11249                 vpd_extended_data = kmalloc(block_end, GFP_KERNEL);
11250                 if (vpd_extended_data  == NULL)
11251                         goto out_not_found;
11252
11253                 /* read rest of vpd image into vpd_extended_data */
11254                 memcpy(vpd_extended_data, vpd_start, BNX2X_VPD_LEN);
11255                 cnt = pci_read_vpd(bp->pdev, BNX2X_VPD_LEN,
11256                                    block_end - BNX2X_VPD_LEN,
11257                                    vpd_extended_data + BNX2X_VPD_LEN);
11258                 if (cnt < (block_end - BNX2X_VPD_LEN))
11259                         goto out_not_found;
11260                 vpd_data = vpd_extended_data;
11261         } else
11262                 vpd_data = vpd_start;
11263
11264         /* now vpd_data holds full vpd content in both cases */
11265
11266         rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end,
11267                                    PCI_VPD_RO_KEYWORD_MFR_ID);
11268         if (rodi < 0)
11269                 goto out_not_found;
11270
11271         len = pci_vpd_info_field_size(&vpd_data[rodi]);
11272
11273         if (len != VENDOR_ID_LEN)
11274                 goto out_not_found;
11275
11276         rodi += PCI_VPD_INFO_FLD_HDR_SIZE;
11277
11278         /* vendor specific info */
11279         snprintf(str_id_reg, VENDOR_ID_LEN + 1, "%04x", PCI_VENDOR_ID_DELL);
11280         snprintf(str_id_cap, VENDOR_ID_LEN + 1, "%04X", PCI_VENDOR_ID_DELL);
11281         if (!strncmp(str_id_reg, &vpd_data[rodi], VENDOR_ID_LEN) ||
11282             !strncmp(str_id_cap, &vpd_data[rodi], VENDOR_ID_LEN)) {
11283
11284                 rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end,
11285                                                 PCI_VPD_RO_KEYWORD_VENDOR0);
11286                 if (rodi >= 0) {
11287                         len = pci_vpd_info_field_size(&vpd_data[rodi]);
11288
11289                         rodi += PCI_VPD_INFO_FLD_HDR_SIZE;
11290
11291                         if (len < 32 && (len + rodi) <= BNX2X_VPD_LEN) {
11292                                 memcpy(bp->fw_ver, &vpd_data[rodi], len);
11293                                 bp->fw_ver[len] = ' ';
11294                         }
11295                 }
11296                 kfree(vpd_extended_data);
11297                 return;
11298         }
11299 out_not_found:
11300         kfree(vpd_extended_data);
11301         return;
11302 }
11303
11304 static void bnx2x_set_modes_bitmap(struct bnx2x *bp)
11305 {
11306         u32 flags = 0;
11307
11308         if (CHIP_REV_IS_FPGA(bp))
11309                 SET_FLAGS(flags, MODE_FPGA);
11310         else if (CHIP_REV_IS_EMUL(bp))
11311                 SET_FLAGS(flags, MODE_EMUL);
11312         else
11313                 SET_FLAGS(flags, MODE_ASIC);
11314
11315         if (CHIP_MODE_IS_4_PORT(bp))
11316                 SET_FLAGS(flags, MODE_PORT4);
11317         else
11318                 SET_FLAGS(flags, MODE_PORT2);
11319
11320         if (CHIP_IS_E2(bp))
11321                 SET_FLAGS(flags, MODE_E2);
11322         else if (CHIP_IS_E3(bp)) {
11323                 SET_FLAGS(flags, MODE_E3);
11324                 if (CHIP_REV(bp) == CHIP_REV_Ax)
11325                         SET_FLAGS(flags, MODE_E3_A0);
11326                 else /*if (CHIP_REV(bp) == CHIP_REV_Bx)*/
11327                         SET_FLAGS(flags, MODE_E3_B0 | MODE_COS3);
11328         }
11329
11330         if (IS_MF(bp)) {
11331                 SET_FLAGS(flags, MODE_MF);
11332                 switch (bp->mf_mode) {
11333                 case MULTI_FUNCTION_SD:
11334                         SET_FLAGS(flags, MODE_MF_SD);
11335                         break;
11336                 case MULTI_FUNCTION_SI:
11337                         SET_FLAGS(flags, MODE_MF_SI);
11338                         break;
11339                 case MULTI_FUNCTION_AFEX:
11340                         SET_FLAGS(flags, MODE_MF_AFEX);
11341                         break;
11342                 }
11343         } else
11344                 SET_FLAGS(flags, MODE_SF);
11345
11346 #if defined(__LITTLE_ENDIAN)
11347         SET_FLAGS(flags, MODE_LITTLE_ENDIAN);
11348 #else /*(__BIG_ENDIAN)*/
11349         SET_FLAGS(flags, MODE_BIG_ENDIAN);
11350 #endif
11351         INIT_MODE_FLAGS(bp) = flags;
11352 }
11353
11354 static int bnx2x_init_bp(struct bnx2x *bp)
11355 {
11356         int func;
11357         int rc;
11358
11359         mutex_init(&bp->port.phy_mutex);
11360         mutex_init(&bp->fw_mb_mutex);
11361         spin_lock_init(&bp->stats_lock);
11362
11363
11364         INIT_DELAYED_WORK(&bp->sp_task, bnx2x_sp_task);
11365         INIT_DELAYED_WORK(&bp->sp_rtnl_task, bnx2x_sp_rtnl_task);
11366         INIT_DELAYED_WORK(&bp->period_task, bnx2x_period_task);
11367         if (IS_PF(bp)) {
11368                 rc = bnx2x_get_hwinfo(bp);
11369                 if (rc)
11370                         return rc;
11371         } else {
11372                 random_ether_addr(bp->dev->dev_addr);
11373         }
11374
11375         bnx2x_set_modes_bitmap(bp);
11376
11377         rc = bnx2x_alloc_mem_bp(bp);
11378         if (rc)
11379                 return rc;
11380
11381         bnx2x_read_fwinfo(bp);
11382
11383         func = BP_FUNC(bp);
11384
11385         /* need to reset chip if undi was active */
11386         if (IS_PF(bp) && !BP_NOMCP(bp)) {
11387                 /* init fw_seq */
11388                 bp->fw_seq =
11389                         SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) &
11390                                                         DRV_MSG_SEQ_NUMBER_MASK;
11391                 BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp->fw_seq);
11392
11393                 bnx2x_prev_unload(bp);
11394         }
11395
11396
11397         if (CHIP_REV_IS_FPGA(bp))
11398                 dev_err(&bp->pdev->dev, "FPGA detected\n");
11399
11400         if (BP_NOMCP(bp) && (func == 0))
11401                 dev_err(&bp->pdev->dev, "MCP disabled, must load devices in order!\n");
11402
11403         bp->disable_tpa = disable_tpa;
11404         bp->disable_tpa |= IS_MF_STORAGE_SD(bp) || IS_MF_FCOE_AFEX(bp);
11405
11406         /* Set TPA flags */
11407         if (bp->disable_tpa) {
11408                 bp->flags &= ~(TPA_ENABLE_FLAG | GRO_ENABLE_FLAG);
11409                 bp->dev->features &= ~NETIF_F_LRO;
11410         } else {
11411                 bp->flags |= (TPA_ENABLE_FLAG | GRO_ENABLE_FLAG);
11412                 bp->dev->features |= NETIF_F_LRO;
11413         }
11414
11415         if (CHIP_IS_E1(bp))
11416                 bp->dropless_fc = 0;
11417         else
11418                 bp->dropless_fc = dropless_fc | bnx2x_get_dropless_info(bp);
11419
11420         bp->mrrs = mrrs;
11421
11422         bp->tx_ring_size = IS_MF_FCOE_AFEX(bp) ? 0 : MAX_TX_AVAIL;
11423         if (IS_VF(bp))
11424                 bp->rx_ring_size = MAX_RX_AVAIL;
11425
11426         /* make sure that the numbers are in the right granularity */
11427         bp->tx_ticks = (50 / BNX2X_BTR) * BNX2X_BTR;
11428         bp->rx_ticks = (25 / BNX2X_BTR) * BNX2X_BTR;
11429
11430         bp->current_interval = CHIP_REV_IS_SLOW(bp) ? 5*HZ : HZ;
11431
11432         init_timer(&bp->timer);
11433         bp->timer.expires = jiffies + bp->current_interval;
11434         bp->timer.data = (unsigned long) bp;
11435         bp->timer.function = bnx2x_timer;
11436
11437         if (SHMEM2_HAS(bp, dcbx_lldp_params_offset) &&
11438             SHMEM2_HAS(bp, dcbx_lldp_dcbx_stat_offset) &&
11439             SHMEM2_RD(bp, dcbx_lldp_params_offset) &&
11440             SHMEM2_RD(bp, dcbx_lldp_dcbx_stat_offset)) {
11441                 bnx2x_dcbx_set_state(bp, true, BNX2X_DCBX_ENABLED_ON_NEG_ON);
11442                 bnx2x_dcbx_init_params(bp);
11443         } else {
11444                 bnx2x_dcbx_set_state(bp, false, BNX2X_DCBX_ENABLED_OFF);
11445         }
11446
11447         if (CHIP_IS_E1x(bp))
11448                 bp->cnic_base_cl_id = FP_SB_MAX_E1x;
11449         else
11450                 bp->cnic_base_cl_id = FP_SB_MAX_E2;
11451
11452         /* multiple tx priority */
11453         if (IS_VF(bp))
11454                 bp->max_cos = 1;
11455         else if (CHIP_IS_E1x(bp))
11456                 bp->max_cos = BNX2X_MULTI_TX_COS_E1X;
11457         else if (CHIP_IS_E2(bp) || CHIP_IS_E3A0(bp))
11458                 bp->max_cos = BNX2X_MULTI_TX_COS_E2_E3A0;
11459         else if (CHIP_IS_E3B0(bp))
11460                 bp->max_cos = BNX2X_MULTI_TX_COS_E3B0;
11461         else
11462                 BNX2X_ERR("unknown chip %x revision %x\n",
11463                           CHIP_NUM(bp), CHIP_REV(bp));
11464         BNX2X_DEV_INFO("set bp->max_cos to %d\n", bp->max_cos);
11465
11466         /* We need at least one default status block for slow-path events,
11467          * second status block for the L2 queue, and a third status block for
11468          * CNIC if supproted.
11469          */
11470         if (CNIC_SUPPORT(bp))
11471                 bp->min_msix_vec_cnt = 3;
11472         else
11473                 bp->min_msix_vec_cnt = 2;
11474         BNX2X_DEV_INFO("bp->min_msix_vec_cnt %d", bp->min_msix_vec_cnt);
11475
11476         return rc;
11477 }
11478
11479
11480 /****************************************************************************
11481 * General service functions
11482 ****************************************************************************/
11483
11484 /*
11485  * net_device service functions
11486  */
11487
11488 /* called with rtnl_lock */
11489 static int bnx2x_open(struct net_device *dev)
11490 {
11491         struct bnx2x *bp = netdev_priv(dev);
11492         bool global = false;
11493         int other_engine = BP_PATH(bp) ? 0 : 1;
11494         bool other_load_status, load_status;
11495         int rc;
11496
11497         bp->stats_init = true;
11498
11499         netif_carrier_off(dev);
11500
11501         bnx2x_set_power_state(bp, PCI_D0);
11502
11503         /* If parity had happen during the unload, then attentions
11504          * and/or RECOVERY_IN_PROGRES may still be set. In this case we
11505          * want the first function loaded on the current engine to
11506          * complete the recovery.
11507          * Parity recovery is only relevant for PF driver.
11508          */
11509         if (IS_PF(bp)) {
11510                 other_load_status = bnx2x_get_load_status(bp, other_engine);
11511                 load_status = bnx2x_get_load_status(bp, BP_PATH(bp));
11512                 if (!bnx2x_reset_is_done(bp, BP_PATH(bp)) ||
11513                     bnx2x_chk_parity_attn(bp, &global, true)) {
11514                         do {
11515                                 /* If there are attentions and they are in a
11516                                  * global blocks, set the GLOBAL_RESET bit
11517                                  * regardless whether it will be this function
11518                                  * that will complete the recovery or not.
11519                                  */
11520                                 if (global)
11521                                         bnx2x_set_reset_global(bp);
11522
11523                                 /* Only the first function on the current
11524                                  * engine should try to recover in open. In case
11525                                  * of attentions in global blocks only the first
11526                                  * in the chip should try to recover.
11527                                  */
11528                                 if ((!load_status &&
11529                                      (!global || !other_load_status)) &&
11530                                       bnx2x_trylock_leader_lock(bp) &&
11531                                       !bnx2x_leader_reset(bp)) {
11532                                         netdev_info(bp->dev,
11533                                                     "Recovered in open\n");
11534                                         break;
11535                                 }
11536
11537                                 /* recovery has failed... */
11538                                 bnx2x_set_power_state(bp, PCI_D3hot);
11539                                 bp->recovery_state = BNX2X_RECOVERY_FAILED;
11540
11541                                 BNX2X_ERR("Recovery flow hasn't been properly completed yet. Try again later.\n"
11542                                           "If you still see this message after a few retries then power cycle is required.\n");
11543
11544                                 return -EAGAIN;
11545                         } while (0);
11546                 }
11547         }
11548
11549         bp->recovery_state = BNX2X_RECOVERY_DONE;
11550         rc = bnx2x_nic_load(bp, LOAD_OPEN);
11551         if (rc)
11552                 return rc;
11553         return bnx2x_open_epilog(bp);
11554 }
11555
11556 /* called with rtnl_lock */
11557 static int bnx2x_close(struct net_device *dev)
11558 {
11559         struct bnx2x *bp = netdev_priv(dev);
11560
11561         /* Unload the driver, release IRQs */
11562         bnx2x_nic_unload(bp, UNLOAD_CLOSE, false);
11563
11564         /* Power off */
11565         bnx2x_set_power_state(bp, PCI_D3hot);
11566
11567         return 0;
11568 }
11569
11570 static int bnx2x_init_mcast_macs_list(struct bnx2x *bp,
11571                                       struct bnx2x_mcast_ramrod_params *p)
11572 {
11573         int mc_count = netdev_mc_count(bp->dev);
11574         struct bnx2x_mcast_list_elem *mc_mac =
11575                 kzalloc(sizeof(*mc_mac) * mc_count, GFP_ATOMIC);
11576         struct netdev_hw_addr *ha;
11577
11578         if (!mc_mac)
11579                 return -ENOMEM;
11580
11581         INIT_LIST_HEAD(&p->mcast_list);
11582
11583         netdev_for_each_mc_addr(ha, bp->dev) {
11584                 mc_mac->mac = bnx2x_mc_addr(ha);
11585                 list_add_tail(&mc_mac->link, &p->mcast_list);
11586                 mc_mac++;
11587         }
11588
11589         p->mcast_list_len = mc_count;
11590
11591         return 0;
11592 }
11593
11594 static void bnx2x_free_mcast_macs_list(
11595         struct bnx2x_mcast_ramrod_params *p)
11596 {
11597         struct bnx2x_mcast_list_elem *mc_mac =
11598                 list_first_entry(&p->mcast_list, struct bnx2x_mcast_list_elem,
11599                                  link);
11600
11601         WARN_ON(!mc_mac);
11602         kfree(mc_mac);
11603 }
11604
11605 /**
11606  * bnx2x_set_uc_list - configure a new unicast MACs list.
11607  *
11608  * @bp: driver handle
11609  *
11610  * We will use zero (0) as a MAC type for these MACs.
11611  */
11612 static int bnx2x_set_uc_list(struct bnx2x *bp)
11613 {
11614         int rc;
11615         struct net_device *dev = bp->dev;
11616         struct netdev_hw_addr *ha;
11617         struct bnx2x_vlan_mac_obj *mac_obj = &bp->sp_objs->mac_obj;
11618         unsigned long ramrod_flags = 0;
11619
11620         /* First schedule a cleanup up of old configuration */
11621         rc = bnx2x_del_all_macs(bp, mac_obj, BNX2X_UC_LIST_MAC, false);
11622         if (rc < 0) {
11623                 BNX2X_ERR("Failed to schedule DELETE operations: %d\n", rc);
11624                 return rc;
11625         }
11626
11627         netdev_for_each_uc_addr(ha, dev) {
11628                 rc = bnx2x_set_mac_one(bp, bnx2x_uc_addr(ha), mac_obj, true,
11629                                        BNX2X_UC_LIST_MAC, &ramrod_flags);
11630                 if (rc == -EEXIST) {
11631                         DP(BNX2X_MSG_SP,
11632                            "Failed to schedule ADD operations: %d\n", rc);
11633                         /* do not treat adding same MAC as error */
11634                         rc = 0;
11635
11636                 } else if (rc < 0) {
11637
11638                         BNX2X_ERR("Failed to schedule ADD operations: %d\n",
11639                                   rc);
11640                         return rc;
11641                 }
11642         }
11643
11644         /* Execute the pending commands */
11645         __set_bit(RAMROD_CONT, &ramrod_flags);
11646         return bnx2x_set_mac_one(bp, NULL, mac_obj, false /* don't care */,
11647                                  BNX2X_UC_LIST_MAC, &ramrod_flags);
11648 }
11649
11650 static int bnx2x_set_mc_list(struct bnx2x *bp)
11651 {
11652         struct net_device *dev = bp->dev;
11653         struct bnx2x_mcast_ramrod_params rparam = {NULL};
11654         int rc = 0;
11655
11656         rparam.mcast_obj = &bp->mcast_obj;
11657
11658         /* first, clear all configured multicast MACs */
11659         rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL);
11660         if (rc < 0) {
11661                 BNX2X_ERR("Failed to clear multicast configuration: %d\n", rc);
11662                 return rc;
11663         }
11664
11665         /* then, configure a new MACs list */
11666         if (netdev_mc_count(dev)) {
11667                 rc = bnx2x_init_mcast_macs_list(bp, &rparam);
11668                 if (rc) {
11669                         BNX2X_ERR("Failed to create multicast MACs list: %d\n",
11670                                   rc);
11671                         return rc;
11672                 }
11673
11674                 /* Now add the new MACs */
11675                 rc = bnx2x_config_mcast(bp, &rparam,
11676                                         BNX2X_MCAST_CMD_ADD);
11677                 if (rc < 0)
11678                         BNX2X_ERR("Failed to set a new multicast configuration: %d\n",
11679                                   rc);
11680
11681                 bnx2x_free_mcast_macs_list(&rparam);
11682         }
11683
11684         return rc;
11685 }
11686
11687 /* If bp->state is OPEN, should be called with netif_addr_lock_bh() */
11688 void bnx2x_set_rx_mode(struct net_device *dev)
11689 {
11690         struct bnx2x *bp = netdev_priv(dev);
11691         u32 rx_mode = BNX2X_RX_MODE_NORMAL;
11692
11693         if (bp->state != BNX2X_STATE_OPEN) {
11694                 DP(NETIF_MSG_IFUP, "state is %x, returning\n", bp->state);
11695                 return;
11696         }
11697
11698         DP(NETIF_MSG_IFUP, "dev->flags = %x\n", bp->dev->flags);
11699
11700         if (dev->flags & IFF_PROMISC)
11701                 rx_mode = BNX2X_RX_MODE_PROMISC;
11702         else if ((dev->flags & IFF_ALLMULTI) ||
11703                  ((netdev_mc_count(dev) > BNX2X_MAX_MULTICAST) &&
11704                   CHIP_IS_E1(bp)))
11705                 rx_mode = BNX2X_RX_MODE_ALLMULTI;
11706         else {
11707                 if (IS_PF(bp)) {
11708                         /* some multicasts */
11709                         if (bnx2x_set_mc_list(bp) < 0)
11710                                 rx_mode = BNX2X_RX_MODE_ALLMULTI;
11711
11712                         if (bnx2x_set_uc_list(bp) < 0)
11713                                 rx_mode = BNX2X_RX_MODE_PROMISC;
11714                 } else {
11715                         /* configuring mcast to a vf involves sleeping (when we
11716                          * wait for the pf's response). Since this function is
11717                          * called from non sleepable context we must schedule
11718                          * a work item for this purpose
11719                          */
11720                         smp_mb__before_clear_bit();
11721                         set_bit(BNX2X_SP_RTNL_VFPF_MCAST,
11722                                 &bp->sp_rtnl_state);
11723                         smp_mb__after_clear_bit();
11724                         schedule_delayed_work(&bp->sp_rtnl_task, 0);
11725                 }
11726         }
11727
11728         bp->rx_mode = rx_mode;
11729         /* handle ISCSI SD mode */
11730         if (IS_MF_ISCSI_SD(bp))
11731                 bp->rx_mode = BNX2X_RX_MODE_NONE;
11732
11733         /* Schedule the rx_mode command */
11734         if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state)) {
11735                 set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state);
11736                 return;
11737         }
11738
11739         if (IS_PF(bp)) {
11740                 bnx2x_set_storm_rx_mode(bp);
11741         } else {
11742                 /* configuring rx mode to storms in a vf involves sleeping (when
11743                  * we wait for the pf's response). Since this function is
11744                  * called from non sleepable context we must schedule
11745                  * a work item for this purpose
11746                  */
11747                 smp_mb__before_clear_bit();
11748                 set_bit(BNX2X_SP_RTNL_VFPF_STORM_RX_MODE,
11749                         &bp->sp_rtnl_state);
11750                 smp_mb__after_clear_bit();
11751                 schedule_delayed_work(&bp->sp_rtnl_task, 0);
11752         }
11753 }
11754
11755 /* called with rtnl_lock */
11756 static int bnx2x_mdio_read(struct net_device *netdev, int prtad,
11757                            int devad, u16 addr)
11758 {
11759         struct bnx2x *bp = netdev_priv(netdev);
11760         u16 value;
11761         int rc;
11762
11763         DP(NETIF_MSG_LINK, "mdio_read: prtad 0x%x, devad 0x%x, addr 0x%x\n",
11764            prtad, devad, addr);
11765
11766         /* The HW expects different devad if CL22 is used */
11767         devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad;
11768
11769         bnx2x_acquire_phy_lock(bp);
11770         rc = bnx2x_phy_read(&bp->link_params, prtad, devad, addr, &value);
11771         bnx2x_release_phy_lock(bp);
11772         DP(NETIF_MSG_LINK, "mdio_read_val 0x%x rc = 0x%x\n", value, rc);
11773
11774         if (!rc)
11775                 rc = value;
11776         return rc;
11777 }
11778
11779 /* called with rtnl_lock */
11780 static int bnx2x_mdio_write(struct net_device *netdev, int prtad, int devad,
11781                             u16 addr, u16 value)
11782 {
11783         struct bnx2x *bp = netdev_priv(netdev);
11784         int rc;
11785
11786         DP(NETIF_MSG_LINK,
11787            "mdio_write: prtad 0x%x, devad 0x%x, addr 0x%x, value 0x%x\n",
11788            prtad, devad, addr, value);
11789
11790         /* The HW expects different devad if CL22 is used */
11791         devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad;
11792
11793         bnx2x_acquire_phy_lock(bp);
11794         rc = bnx2x_phy_write(&bp->link_params, prtad, devad, addr, value);
11795         bnx2x_release_phy_lock(bp);
11796         return rc;
11797 }
11798
11799 /* called with rtnl_lock */
11800 static int bnx2x_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
11801 {
11802         struct bnx2x *bp = netdev_priv(dev);
11803         struct mii_ioctl_data *mdio = if_mii(ifr);
11804
11805         DP(NETIF_MSG_LINK, "ioctl: phy id 0x%x, reg 0x%x, val_in 0x%x\n",
11806            mdio->phy_id, mdio->reg_num, mdio->val_in);
11807
11808         if (!netif_running(dev))
11809                 return -EAGAIN;
11810
11811         return mdio_mii_ioctl(&bp->mdio, mdio, cmd);
11812 }
11813
11814 #ifdef CONFIG_NET_POLL_CONTROLLER
11815 static void poll_bnx2x(struct net_device *dev)
11816 {
11817         struct bnx2x *bp = netdev_priv(dev);
11818         int i;
11819
11820         for_each_eth_queue(bp, i) {
11821                 struct bnx2x_fastpath *fp = &bp->fp[i];
11822                 napi_schedule(&bnx2x_fp(bp, fp->index, napi));
11823         }
11824 }
11825 #endif
11826
11827 static int bnx2x_validate_addr(struct net_device *dev)
11828 {
11829         struct bnx2x *bp = netdev_priv(dev);
11830
11831         if (!bnx2x_is_valid_ether_addr(bp, dev->dev_addr)) {
11832                 BNX2X_ERR("Non-valid Ethernet address\n");
11833                 return -EADDRNOTAVAIL;
11834         }
11835         return 0;
11836 }
11837
11838 static const struct net_device_ops bnx2x_netdev_ops = {
11839         .ndo_open               = bnx2x_open,
11840         .ndo_stop               = bnx2x_close,
11841         .ndo_start_xmit         = bnx2x_start_xmit,
11842         .ndo_select_queue       = bnx2x_select_queue,
11843         .ndo_set_rx_mode        = bnx2x_set_rx_mode,
11844         .ndo_set_mac_address    = bnx2x_change_mac_addr,
11845         .ndo_validate_addr      = bnx2x_validate_addr,
11846         .ndo_do_ioctl           = bnx2x_ioctl,
11847         .ndo_change_mtu         = bnx2x_change_mtu,
11848         .ndo_fix_features       = bnx2x_fix_features,
11849         .ndo_set_features       = bnx2x_set_features,
11850         .ndo_tx_timeout         = bnx2x_tx_timeout,
11851 #ifdef CONFIG_NET_POLL_CONTROLLER
11852         .ndo_poll_controller    = poll_bnx2x,
11853 #endif
11854         .ndo_setup_tc           = bnx2x_setup_tc,
11855 #ifdef CONFIG_BNX2X_SRIOV
11856         .ndo_set_vf_mac         = bnx2x_set_vf_mac,
11857         .ndo_set_vf_vlan        = bnx2x_set_vf_vlan,
11858         .ndo_get_vf_config      = bnx2x_get_vf_config,
11859 #endif
11860 #ifdef NETDEV_FCOE_WWNN
11861         .ndo_fcoe_get_wwn       = bnx2x_fcoe_get_wwn,
11862 #endif
11863 };
11864
11865 static int bnx2x_set_coherency_mask(struct bnx2x *bp)
11866 {
11867         struct device *dev = &bp->pdev->dev;
11868
11869         if (dma_set_mask(dev, DMA_BIT_MASK(64)) == 0) {
11870                 bp->flags |= USING_DAC_FLAG;
11871                 if (dma_set_coherent_mask(dev, DMA_BIT_MASK(64)) != 0) {
11872                         dev_err(dev, "dma_set_coherent_mask failed, aborting\n");
11873                         return -EIO;
11874                 }
11875         } else if (dma_set_mask(dev, DMA_BIT_MASK(32)) != 0) {
11876                 dev_err(dev, "System does not support DMA, aborting\n");
11877                 return -EIO;
11878         }
11879
11880         return 0;
11881 }
11882
11883 static int bnx2x_init_dev(struct bnx2x *bp, struct pci_dev *pdev,
11884                           struct net_device *dev, unsigned long board_type)
11885 {
11886         int rc;
11887         u32 pci_cfg_dword;
11888         bool chip_is_e1x = (board_type == BCM57710 ||
11889                             board_type == BCM57711 ||
11890                             board_type == BCM57711E);
11891
11892         SET_NETDEV_DEV(dev, &pdev->dev);
11893
11894         bp->dev = dev;
11895         bp->pdev = pdev;
11896
11897         rc = pci_enable_device(pdev);
11898         if (rc) {
11899                 dev_err(&bp->pdev->dev,
11900                         "Cannot enable PCI device, aborting\n");
11901                 goto err_out;
11902         }
11903
11904         if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
11905                 dev_err(&bp->pdev->dev,
11906                         "Cannot find PCI device base address, aborting\n");
11907                 rc = -ENODEV;
11908                 goto err_out_disable;
11909         }
11910
11911         if (IS_PF(bp) && !(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
11912                 dev_err(&bp->pdev->dev, "Cannot find second PCI device base address, aborting\n");
11913                 rc = -ENODEV;
11914                 goto err_out_disable;
11915         }
11916
11917         pci_read_config_dword(pdev, PCICFG_REVISION_ID_OFFSET, &pci_cfg_dword);
11918         if ((pci_cfg_dword & PCICFG_REVESION_ID_MASK) ==
11919             PCICFG_REVESION_ID_ERROR_VAL) {
11920                 pr_err("PCI device error, probably due to fan failure, aborting\n");
11921                 rc = -ENODEV;
11922                 goto err_out_disable;
11923         }
11924
11925         if (atomic_read(&pdev->enable_cnt) == 1) {
11926                 rc = pci_request_regions(pdev, DRV_MODULE_NAME);
11927                 if (rc) {
11928                         dev_err(&bp->pdev->dev,
11929                                 "Cannot obtain PCI resources, aborting\n");
11930                         goto err_out_disable;
11931                 }
11932
11933                 pci_set_master(pdev);
11934                 pci_save_state(pdev);
11935         }
11936
11937         if (IS_PF(bp)) {
11938                 bp->pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
11939                 if (bp->pm_cap == 0) {
11940                         dev_err(&bp->pdev->dev,
11941                                 "Cannot find power management capability, aborting\n");
11942                         rc = -EIO;
11943                         goto err_out_release;
11944                 }
11945         }
11946
11947         if (!pci_is_pcie(pdev)) {
11948                 dev_err(&bp->pdev->dev, "Not PCI Express, aborting\n");
11949                 rc = -EIO;
11950                 goto err_out_release;
11951         }
11952
11953         rc = bnx2x_set_coherency_mask(bp);
11954         if (rc)
11955                 goto err_out_release;
11956
11957         dev->mem_start = pci_resource_start(pdev, 0);
11958         dev->base_addr = dev->mem_start;
11959         dev->mem_end = pci_resource_end(pdev, 0);
11960
11961         dev->irq = pdev->irq;
11962
11963         bp->regview = pci_ioremap_bar(pdev, 0);
11964         if (!bp->regview) {
11965                 dev_err(&bp->pdev->dev,
11966                         "Cannot map register space, aborting\n");
11967                 rc = -ENOMEM;
11968                 goto err_out_release;
11969         }
11970
11971         /* In E1/E1H use pci device function given by kernel.
11972          * In E2/E3 read physical function from ME register since these chips
11973          * support Physical Device Assignment where kernel BDF maybe arbitrary
11974          * (depending on hypervisor).
11975          */
11976         if (chip_is_e1x) {
11977                 bp->pf_num = PCI_FUNC(pdev->devfn);
11978         } else {
11979                 /* chip is E2/3*/
11980                 pci_read_config_dword(bp->pdev,
11981                                       PCICFG_ME_REGISTER, &pci_cfg_dword);
11982                 bp->pf_num = (u8)((pci_cfg_dword & ME_REG_ABS_PF_NUM) >>
11983                                   ME_REG_ABS_PF_NUM_SHIFT);
11984         }
11985         BNX2X_DEV_INFO("me reg PF num: %d\n", bp->pf_num);
11986
11987         bnx2x_set_power_state(bp, PCI_D0);
11988
11989         /* clean indirect addresses */
11990         pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
11991                                PCICFG_VENDOR_ID_OFFSET);
11992         /*
11993          * Clean the following indirect addresses for all functions since it
11994          * is not used by the driver.
11995          */
11996         if (IS_PF(bp)) {
11997                 REG_WR(bp, PXP2_REG_PGL_ADDR_88_F0, 0);
11998                 REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F0, 0);
11999                 REG_WR(bp, PXP2_REG_PGL_ADDR_90_F0, 0);
12000                 REG_WR(bp, PXP2_REG_PGL_ADDR_94_F0, 0);
12001
12002                 if (chip_is_e1x) {
12003                         REG_WR(bp, PXP2_REG_PGL_ADDR_88_F1, 0);
12004                         REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F1, 0);
12005                         REG_WR(bp, PXP2_REG_PGL_ADDR_90_F1, 0);
12006                         REG_WR(bp, PXP2_REG_PGL_ADDR_94_F1, 0);
12007                 }
12008
12009                 /* Enable internal target-read (in case we are probed after PF
12010                  * FLR). Must be done prior to any BAR read access. Only for
12011                  * 57712 and up
12012                  */
12013                 if (!chip_is_e1x)
12014                         REG_WR(bp,
12015                                PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
12016         }
12017
12018         dev->watchdog_timeo = TX_TIMEOUT;
12019
12020         dev->netdev_ops = &bnx2x_netdev_ops;
12021         bnx2x_set_ethtool_ops(bp, dev);
12022
12023         dev->priv_flags |= IFF_UNICAST_FLT;
12024
12025         dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
12026                 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 |
12027                 NETIF_F_RXCSUM | NETIF_F_LRO | NETIF_F_GRO |
12028                 NETIF_F_RXHASH | NETIF_F_HW_VLAN_TX;
12029         if (!CHIP_IS_E1x(bp)) {
12030                 dev->hw_features |= NETIF_F_GSO_GRE;
12031                 dev->hw_enc_features =
12032                         NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG |
12033                         NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 |
12034                         NETIF_F_GSO_GRE;
12035         }
12036
12037         dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
12038                 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 | NETIF_F_HIGHDMA;
12039
12040         dev->features |= dev->hw_features | NETIF_F_HW_VLAN_RX;
12041         if (bp->flags & USING_DAC_FLAG)
12042                 dev->features |= NETIF_F_HIGHDMA;
12043
12044         /* Add Loopback capability to the device */
12045         dev->hw_features |= NETIF_F_LOOPBACK;
12046
12047 #ifdef BCM_DCBNL
12048         dev->dcbnl_ops = &bnx2x_dcbnl_ops;
12049 #endif
12050
12051         /* get_port_hwinfo() will set prtad and mmds properly */
12052         bp->mdio.prtad = MDIO_PRTAD_NONE;
12053         bp->mdio.mmds = 0;
12054         bp->mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
12055         bp->mdio.dev = dev;
12056         bp->mdio.mdio_read = bnx2x_mdio_read;
12057         bp->mdio.mdio_write = bnx2x_mdio_write;
12058
12059         return 0;
12060
12061 err_out_release:
12062         if (atomic_read(&pdev->enable_cnt) == 1)
12063                 pci_release_regions(pdev);
12064
12065 err_out_disable:
12066         pci_disable_device(pdev);
12067         pci_set_drvdata(pdev, NULL);
12068
12069 err_out:
12070         return rc;
12071 }
12072
12073 static void bnx2x_get_pcie_width_speed(struct bnx2x *bp, int *width, int *speed)
12074 {
12075         u32 val = 0;
12076
12077         pci_read_config_dword(bp->pdev, PCICFG_LINK_CONTROL, &val);
12078         *width = (val & PCICFG_LINK_WIDTH) >> PCICFG_LINK_WIDTH_SHIFT;
12079
12080         /* return value of 1=2.5GHz 2=5GHz */
12081         *speed = (val & PCICFG_LINK_SPEED) >> PCICFG_LINK_SPEED_SHIFT;
12082 }
12083
12084 static int bnx2x_check_firmware(struct bnx2x *bp)
12085 {
12086         const struct firmware *firmware = bp->firmware;
12087         struct bnx2x_fw_file_hdr *fw_hdr;
12088         struct bnx2x_fw_file_section *sections;
12089         u32 offset, len, num_ops;
12090         __be16 *ops_offsets;
12091         int i;
12092         const u8 *fw_ver;
12093
12094         if (firmware->size < sizeof(struct bnx2x_fw_file_hdr)) {
12095                 BNX2X_ERR("Wrong FW size\n");
12096                 return -EINVAL;
12097         }
12098
12099         fw_hdr = (struct bnx2x_fw_file_hdr *)firmware->data;
12100         sections = (struct bnx2x_fw_file_section *)fw_hdr;
12101
12102         /* Make sure none of the offsets and sizes make us read beyond
12103          * the end of the firmware data */
12104         for (i = 0; i < sizeof(*fw_hdr) / sizeof(*sections); i++) {
12105                 offset = be32_to_cpu(sections[i].offset);
12106                 len = be32_to_cpu(sections[i].len);
12107                 if (offset + len > firmware->size) {
12108                         BNX2X_ERR("Section %d length is out of bounds\n", i);
12109                         return -EINVAL;
12110                 }
12111         }
12112
12113         /* Likewise for the init_ops offsets */
12114         offset = be32_to_cpu(fw_hdr->init_ops_offsets.offset);
12115         ops_offsets = (__force __be16 *)(firmware->data + offset);
12116         num_ops = be32_to_cpu(fw_hdr->init_ops.len) / sizeof(struct raw_op);
12117
12118         for (i = 0; i < be32_to_cpu(fw_hdr->init_ops_offsets.len) / 2; i++) {
12119                 if (be16_to_cpu(ops_offsets[i]) > num_ops) {
12120                         BNX2X_ERR("Section offset %d is out of bounds\n", i);
12121                         return -EINVAL;
12122                 }
12123         }
12124
12125         /* Check FW version */
12126         offset = be32_to_cpu(fw_hdr->fw_version.offset);
12127         fw_ver = firmware->data + offset;
12128         if ((fw_ver[0] != BCM_5710_FW_MAJOR_VERSION) ||
12129             (fw_ver[1] != BCM_5710_FW_MINOR_VERSION) ||
12130             (fw_ver[2] != BCM_5710_FW_REVISION_VERSION) ||
12131             (fw_ver[3] != BCM_5710_FW_ENGINEERING_VERSION)) {
12132                 BNX2X_ERR("Bad FW version:%d.%d.%d.%d. Should be %d.%d.%d.%d\n",
12133                        fw_ver[0], fw_ver[1], fw_ver[2], fw_ver[3],
12134                        BCM_5710_FW_MAJOR_VERSION,
12135                        BCM_5710_FW_MINOR_VERSION,
12136                        BCM_5710_FW_REVISION_VERSION,
12137                        BCM_5710_FW_ENGINEERING_VERSION);
12138                 return -EINVAL;
12139         }
12140
12141         return 0;
12142 }
12143
12144 static void be32_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
12145 {
12146         const __be32 *source = (const __be32 *)_source;
12147         u32 *target = (u32 *)_target;
12148         u32 i;
12149
12150         for (i = 0; i < n/4; i++)
12151                 target[i] = be32_to_cpu(source[i]);
12152 }
12153
12154 /*
12155    Ops array is stored in the following format:
12156    {op(8bit), offset(24bit, big endian), data(32bit, big endian)}
12157  */
12158 static void bnx2x_prep_ops(const u8 *_source, u8 *_target, u32 n)
12159 {
12160         const __be32 *source = (const __be32 *)_source;
12161         struct raw_op *target = (struct raw_op *)_target;
12162         u32 i, j, tmp;
12163
12164         for (i = 0, j = 0; i < n/8; i++, j += 2) {
12165                 tmp = be32_to_cpu(source[j]);
12166                 target[i].op = (tmp >> 24) & 0xff;
12167                 target[i].offset = tmp & 0xffffff;
12168                 target[i].raw_data = be32_to_cpu(source[j + 1]);
12169         }
12170 }
12171
12172 /* IRO array is stored in the following format:
12173  * {base(24bit), m1(16bit), m2(16bit), m3(16bit), size(16bit) }
12174  */
12175 static void bnx2x_prep_iro(const u8 *_source, u8 *_target, u32 n)
12176 {
12177         const __be32 *source = (const __be32 *)_source;
12178         struct iro *target = (struct iro *)_target;
12179         u32 i, j, tmp;
12180
12181         for (i = 0, j = 0; i < n/sizeof(struct iro); i++) {
12182                 target[i].base = be32_to_cpu(source[j]);
12183                 j++;
12184                 tmp = be32_to_cpu(source[j]);
12185                 target[i].m1 = (tmp >> 16) & 0xffff;
12186                 target[i].m2 = tmp & 0xffff;
12187                 j++;
12188                 tmp = be32_to_cpu(source[j]);
12189                 target[i].m3 = (tmp >> 16) & 0xffff;
12190                 target[i].size = tmp & 0xffff;
12191                 j++;
12192         }
12193 }
12194
12195 static void be16_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
12196 {
12197         const __be16 *source = (const __be16 *)_source;
12198         u16 *target = (u16 *)_target;
12199         u32 i;
12200
12201         for (i = 0; i < n/2; i++)
12202                 target[i] = be16_to_cpu(source[i]);
12203 }
12204
12205 #define BNX2X_ALLOC_AND_SET(arr, lbl, func)                             \
12206 do {                                                                    \
12207         u32 len = be32_to_cpu(fw_hdr->arr.len);                         \
12208         bp->arr = kmalloc(len, GFP_KERNEL);                             \
12209         if (!bp->arr)                                                   \
12210                 goto lbl;                                               \
12211         func(bp->firmware->data + be32_to_cpu(fw_hdr->arr.offset),      \
12212              (u8 *)bp->arr, len);                                       \
12213 } while (0)
12214
12215 static int bnx2x_init_firmware(struct bnx2x *bp)
12216 {
12217         const char *fw_file_name;
12218         struct bnx2x_fw_file_hdr *fw_hdr;
12219         int rc;
12220
12221         if (bp->firmware)
12222                 return 0;
12223
12224         if (CHIP_IS_E1(bp))
12225                 fw_file_name = FW_FILE_NAME_E1;
12226         else if (CHIP_IS_E1H(bp))
12227                 fw_file_name = FW_FILE_NAME_E1H;
12228         else if (!CHIP_IS_E1x(bp))
12229                 fw_file_name = FW_FILE_NAME_E2;
12230         else {
12231                 BNX2X_ERR("Unsupported chip revision\n");
12232                 return -EINVAL;
12233         }
12234         BNX2X_DEV_INFO("Loading %s\n", fw_file_name);
12235
12236         rc = request_firmware(&bp->firmware, fw_file_name, &bp->pdev->dev);
12237         if (rc) {
12238                 BNX2X_ERR("Can't load firmware file %s\n",
12239                           fw_file_name);
12240                 goto request_firmware_exit;
12241         }
12242
12243         rc = bnx2x_check_firmware(bp);
12244         if (rc) {
12245                 BNX2X_ERR("Corrupt firmware file %s\n", fw_file_name);
12246                 goto request_firmware_exit;
12247         }
12248
12249         fw_hdr = (struct bnx2x_fw_file_hdr *)bp->firmware->data;
12250
12251         /* Initialize the pointers to the init arrays */
12252         /* Blob */
12253         BNX2X_ALLOC_AND_SET(init_data, request_firmware_exit, be32_to_cpu_n);
12254
12255         /* Opcodes */
12256         BNX2X_ALLOC_AND_SET(init_ops, init_ops_alloc_err, bnx2x_prep_ops);
12257
12258         /* Offsets */
12259         BNX2X_ALLOC_AND_SET(init_ops_offsets, init_offsets_alloc_err,
12260                             be16_to_cpu_n);
12261
12262         /* STORMs firmware */
12263         INIT_TSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
12264                         be32_to_cpu(fw_hdr->tsem_int_table_data.offset);
12265         INIT_TSEM_PRAM_DATA(bp)      = bp->firmware->data +
12266                         be32_to_cpu(fw_hdr->tsem_pram_data.offset);
12267         INIT_USEM_INT_TABLE_DATA(bp) = bp->firmware->data +
12268                         be32_to_cpu(fw_hdr->usem_int_table_data.offset);
12269         INIT_USEM_PRAM_DATA(bp)      = bp->firmware->data +
12270                         be32_to_cpu(fw_hdr->usem_pram_data.offset);
12271         INIT_XSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
12272                         be32_to_cpu(fw_hdr->xsem_int_table_data.offset);
12273         INIT_XSEM_PRAM_DATA(bp)      = bp->firmware->data +
12274                         be32_to_cpu(fw_hdr->xsem_pram_data.offset);
12275         INIT_CSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
12276                         be32_to_cpu(fw_hdr->csem_int_table_data.offset);
12277         INIT_CSEM_PRAM_DATA(bp)      = bp->firmware->data +
12278                         be32_to_cpu(fw_hdr->csem_pram_data.offset);
12279         /* IRO */
12280         BNX2X_ALLOC_AND_SET(iro_arr, iro_alloc_err, bnx2x_prep_iro);
12281
12282         return 0;
12283
12284 iro_alloc_err:
12285         kfree(bp->init_ops_offsets);
12286 init_offsets_alloc_err:
12287         kfree(bp->init_ops);
12288 init_ops_alloc_err:
12289         kfree(bp->init_data);
12290 request_firmware_exit:
12291         release_firmware(bp->firmware);
12292         bp->firmware = NULL;
12293
12294         return rc;
12295 }
12296
12297 static void bnx2x_release_firmware(struct bnx2x *bp)
12298 {
12299         kfree(bp->init_ops_offsets);
12300         kfree(bp->init_ops);
12301         kfree(bp->init_data);
12302         release_firmware(bp->firmware);
12303         bp->firmware = NULL;
12304 }
12305
12306
12307 static struct bnx2x_func_sp_drv_ops bnx2x_func_sp_drv = {
12308         .init_hw_cmn_chip = bnx2x_init_hw_common_chip,
12309         .init_hw_cmn      = bnx2x_init_hw_common,
12310         .init_hw_port     = bnx2x_init_hw_port,
12311         .init_hw_func     = bnx2x_init_hw_func,
12312
12313         .reset_hw_cmn     = bnx2x_reset_common,
12314         .reset_hw_port    = bnx2x_reset_port,
12315         .reset_hw_func    = bnx2x_reset_func,
12316
12317         .gunzip_init      = bnx2x_gunzip_init,
12318         .gunzip_end       = bnx2x_gunzip_end,
12319
12320         .init_fw          = bnx2x_init_firmware,
12321         .release_fw       = bnx2x_release_firmware,
12322 };
12323
12324 void bnx2x__init_func_obj(struct bnx2x *bp)
12325 {
12326         /* Prepare DMAE related driver resources */
12327         bnx2x_setup_dmae(bp);
12328
12329         bnx2x_init_func_obj(bp, &bp->func_obj,
12330                             bnx2x_sp(bp, func_rdata),
12331                             bnx2x_sp_mapping(bp, func_rdata),
12332                             bnx2x_sp(bp, func_afex_rdata),
12333                             bnx2x_sp_mapping(bp, func_afex_rdata),
12334                             &bnx2x_func_sp_drv);
12335 }
12336
12337 /* must be called after sriov-enable */
12338 static int bnx2x_set_qm_cid_count(struct bnx2x *bp)
12339 {
12340         int cid_count = BNX2X_L2_MAX_CID(bp);
12341
12342         if (IS_SRIOV(bp))
12343                 cid_count += BNX2X_VF_CIDS;
12344
12345         if (CNIC_SUPPORT(bp))
12346                 cid_count += CNIC_CID_MAX;
12347
12348         return roundup(cid_count, QM_CID_ROUND);
12349 }
12350
12351 /**
12352  * bnx2x_get_num_none_def_sbs - return the number of none default SBs
12353  *
12354  * @dev:        pci device
12355  *
12356  */
12357 static int bnx2x_get_num_non_def_sbs(struct pci_dev *pdev,
12358                                      int cnic_cnt, bool is_vf)
12359 {
12360         int pos, index;
12361         u16 control = 0;
12362
12363         pos = pci_find_capability(pdev, PCI_CAP_ID_MSIX);
12364
12365         /*
12366          * If MSI-X is not supported - return number of SBs needed to support
12367          * one fast path queue: one FP queue + SB for CNIC
12368          */
12369         if (!pos) {
12370                 dev_info(&pdev->dev, "no msix capability found\n");
12371                 return 1 + cnic_cnt;
12372         }
12373         dev_info(&pdev->dev, "msix capability found\n");
12374
12375         /*
12376          * The value in the PCI configuration space is the index of the last
12377          * entry, namely one less than the actual size of the table, which is
12378          * exactly what we want to return from this function: number of all SBs
12379          * without the default SB.
12380          * For VFs there is no default SB, then we return (index+1).
12381          */
12382         pci_read_config_word(pdev, pos  + PCI_MSI_FLAGS, &control);
12383
12384         index = control & PCI_MSIX_FLAGS_QSIZE;
12385
12386         return is_vf ? index + 1 : index;
12387 }
12388
12389 static int set_max_cos_est(int chip_id)
12390 {
12391         switch (chip_id) {
12392         case BCM57710:
12393         case BCM57711:
12394         case BCM57711E:
12395                 return BNX2X_MULTI_TX_COS_E1X;
12396         case BCM57712:
12397         case BCM57712_MF:
12398         case BCM57712_VF:
12399                 return BNX2X_MULTI_TX_COS_E2_E3A0;
12400         case BCM57800:
12401         case BCM57800_MF:
12402         case BCM57800_VF:
12403         case BCM57810:
12404         case BCM57810_MF:
12405         case BCM57840_4_10:
12406         case BCM57840_2_20:
12407         case BCM57840_O:
12408         case BCM57840_MFO:
12409         case BCM57810_VF:
12410         case BCM57840_MF:
12411         case BCM57840_VF:
12412         case BCM57811:
12413         case BCM57811_MF:
12414         case BCM57811_VF:
12415                 return BNX2X_MULTI_TX_COS_E3B0;
12416                 return 1;
12417         default:
12418                 pr_err("Unknown board_type (%d), aborting\n", chip_id);
12419                 return -ENODEV;
12420         }
12421 }
12422
12423 static int set_is_vf(int chip_id)
12424 {
12425         switch (chip_id) {
12426         case BCM57712_VF:
12427         case BCM57800_VF:
12428         case BCM57810_VF:
12429         case BCM57840_VF:
12430         case BCM57811_VF:
12431                 return true;
12432         default:
12433                 return false;
12434         }
12435 }
12436
12437 struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev);
12438
12439 static int bnx2x_init_one(struct pci_dev *pdev,
12440                                     const struct pci_device_id *ent)
12441 {
12442         struct net_device *dev = NULL;
12443         struct bnx2x *bp;
12444         int pcie_width, pcie_speed;
12445         int rc, max_non_def_sbs;
12446         int rx_count, tx_count, rss_count, doorbell_size;
12447         int max_cos_est;
12448         bool is_vf;
12449         int cnic_cnt;
12450
12451         /* An estimated maximum supported CoS number according to the chip
12452          * version.
12453          * We will try to roughly estimate the maximum number of CoSes this chip
12454          * may support in order to minimize the memory allocated for Tx
12455          * netdev_queue's. This number will be accurately calculated during the
12456          * initialization of bp->max_cos based on the chip versions AND chip
12457          * revision in the bnx2x_init_bp().
12458          */
12459         max_cos_est = set_max_cos_est(ent->driver_data);
12460         if (max_cos_est < 0)
12461                 return max_cos_est;
12462         is_vf = set_is_vf(ent->driver_data);
12463         cnic_cnt = is_vf ? 0 : 1;
12464
12465         max_non_def_sbs = bnx2x_get_num_non_def_sbs(pdev, cnic_cnt, is_vf);
12466
12467         /* Maximum number of RSS queues: one IGU SB goes to CNIC */
12468         rss_count = is_vf ? 1 : max_non_def_sbs - cnic_cnt;
12469
12470         if (rss_count < 1)
12471                 return -EINVAL;
12472
12473         /* Maximum number of netdev Rx queues: RSS + FCoE L2 */
12474         rx_count = rss_count + cnic_cnt;
12475
12476         /* Maximum number of netdev Tx queues:
12477          * Maximum TSS queues * Maximum supported number of CoS  + FCoE L2
12478          */
12479         tx_count = rss_count * max_cos_est + cnic_cnt;
12480
12481         /* dev zeroed in init_etherdev */
12482         dev = alloc_etherdev_mqs(sizeof(*bp), tx_count, rx_count);
12483         if (!dev)
12484                 return -ENOMEM;
12485
12486         bp = netdev_priv(dev);
12487
12488         bp->flags = 0;
12489         if (is_vf)
12490                 bp->flags |= IS_VF_FLAG;
12491
12492         bp->igu_sb_cnt = max_non_def_sbs;
12493         bp->igu_base_addr = IS_VF(bp) ? PXP_VF_ADDR_IGU_START : BAR_IGU_INTMEM;
12494         bp->msg_enable = debug;
12495         bp->cnic_support = cnic_cnt;
12496         bp->cnic_probe = bnx2x_cnic_probe;
12497
12498         pci_set_drvdata(pdev, dev);
12499
12500         rc = bnx2x_init_dev(bp, pdev, dev, ent->driver_data);
12501         if (rc < 0) {
12502                 free_netdev(dev);
12503                 return rc;
12504         }
12505
12506         BNX2X_DEV_INFO("This is a %s function\n",
12507                        IS_PF(bp) ? "physical" : "virtual");
12508         BNX2X_DEV_INFO("Cnic support is %s\n", CNIC_SUPPORT(bp) ? "on" : "off");
12509         BNX2X_DEV_INFO("Max num of status blocks %d\n", max_non_def_sbs);
12510         BNX2X_DEV_INFO("Allocated netdev with %d tx and %d rx queues\n",
12511                        tx_count, rx_count);
12512
12513         rc = bnx2x_init_bp(bp);
12514         if (rc)
12515                 goto init_one_exit;
12516
12517         /* Map doorbells here as we need the real value of bp->max_cos which
12518          * is initialized in bnx2x_init_bp() to determine the number of
12519          * l2 connections.
12520          */
12521         if (IS_VF(bp)) {
12522                 bnx2x_vf_map_doorbells(bp);
12523                 rc = bnx2x_vf_pci_alloc(bp);
12524                 if (rc)
12525                         goto init_one_exit;
12526         } else {
12527                 doorbell_size = BNX2X_L2_MAX_CID(bp) * (1 << BNX2X_DB_SHIFT);
12528                 if (doorbell_size > pci_resource_len(pdev, 2)) {
12529                         dev_err(&bp->pdev->dev,
12530                                 "Cannot map doorbells, bar size too small, aborting\n");
12531                         rc = -ENOMEM;
12532                         goto init_one_exit;
12533                 }
12534                 bp->doorbells = ioremap_nocache(pci_resource_start(pdev, 2),
12535                                                 doorbell_size);
12536         }
12537         if (!bp->doorbells) {
12538                 dev_err(&bp->pdev->dev,
12539                         "Cannot map doorbell space, aborting\n");
12540                 rc = -ENOMEM;
12541                 goto init_one_exit;
12542         }
12543
12544         if (IS_VF(bp)) {
12545                 rc = bnx2x_vfpf_acquire(bp, tx_count, rx_count);
12546                 if (rc)
12547                         goto init_one_exit;
12548         }
12549
12550         /* Enable SRIOV if capability found in configuration space */
12551         rc = bnx2x_iov_init_one(bp, int_mode, BNX2X_MAX_NUM_OF_VFS);
12552         if (rc)
12553                 goto init_one_exit;
12554
12555         /* calc qm_cid_count */
12556         bp->qm_cid_count = bnx2x_set_qm_cid_count(bp);
12557         BNX2X_DEV_INFO("qm_cid_count %d\n", bp->qm_cid_count);
12558
12559         /* disable FCOE L2 queue for E1x*/
12560         if (CHIP_IS_E1x(bp))
12561                 bp->flags |= NO_FCOE_FLAG;
12562
12563         /* Set bp->num_queues for MSI-X mode*/
12564         bnx2x_set_num_queues(bp);
12565
12566         /* Configure interrupt mode: try to enable MSI-X/MSI if
12567          * needed.
12568          */
12569         rc = bnx2x_set_int_mode(bp);
12570         if (rc) {
12571                 dev_err(&pdev->dev, "Cannot set interrupts\n");
12572                 goto init_one_exit;
12573         }
12574         BNX2X_DEV_INFO("set interrupts successfully\n");
12575
12576         /* register the net device */
12577         rc = register_netdev(dev);
12578         if (rc) {
12579                 dev_err(&pdev->dev, "Cannot register net device\n");
12580                 goto init_one_exit;
12581         }
12582         BNX2X_DEV_INFO("device name after netdev register %s\n", dev->name);
12583
12584
12585         if (!NO_FCOE(bp)) {
12586                 /* Add storage MAC address */
12587                 rtnl_lock();
12588                 dev_addr_add(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN);
12589                 rtnl_unlock();
12590         }
12591
12592         bnx2x_get_pcie_width_speed(bp, &pcie_width, &pcie_speed);
12593         BNX2X_DEV_INFO("got pcie width %d and speed %d\n",
12594                        pcie_width, pcie_speed);
12595
12596         BNX2X_DEV_INFO(
12597                 "%s (%c%d) PCI-E x%d %s found at mem %lx, IRQ %d, node addr %pM\n",
12598                     board_info[ent->driver_data].name,
12599                     (CHIP_REV(bp) >> 12) + 'A', (CHIP_METAL(bp) >> 4),
12600                     pcie_width,
12601                     ((!CHIP_IS_E2(bp) && pcie_speed == 2) ||
12602                      (CHIP_IS_E2(bp) && pcie_speed == 1)) ?
12603                     "5GHz (Gen2)" : "2.5GHz",
12604                     dev->base_addr, bp->pdev->irq, dev->dev_addr);
12605
12606         return 0;
12607
12608 init_one_exit:
12609         if (bp->regview)
12610                 iounmap(bp->regview);
12611
12612         if (IS_PF(bp) && bp->doorbells)
12613                 iounmap(bp->doorbells);
12614
12615         free_netdev(dev);
12616
12617         if (atomic_read(&pdev->enable_cnt) == 1)
12618                 pci_release_regions(pdev);
12619
12620         pci_disable_device(pdev);
12621         pci_set_drvdata(pdev, NULL);
12622
12623         return rc;
12624 }
12625
12626 static void bnx2x_remove_one(struct pci_dev *pdev)
12627 {
12628         struct net_device *dev = pci_get_drvdata(pdev);
12629         struct bnx2x *bp;
12630
12631         if (!dev) {
12632                 dev_err(&pdev->dev, "BAD net device from bnx2x_init_one\n");
12633                 return;
12634         }
12635         bp = netdev_priv(dev);
12636
12637         /* Delete storage MAC address */
12638         if (!NO_FCOE(bp)) {
12639                 rtnl_lock();
12640                 dev_addr_del(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN);
12641                 rtnl_unlock();
12642         }
12643
12644 #ifdef BCM_DCBNL
12645         /* Delete app tlvs from dcbnl */
12646         bnx2x_dcbnl_update_applist(bp, true);
12647 #endif
12648
12649         unregister_netdev(dev);
12650
12651         /* Power on: we can't let PCI layer write to us while we are in D3 */
12652         if (IS_PF(bp))
12653                 bnx2x_set_power_state(bp, PCI_D0);
12654
12655         /* Disable MSI/MSI-X */
12656         bnx2x_disable_msi(bp);
12657
12658         /* Power off */
12659         if (IS_PF(bp))
12660                 bnx2x_set_power_state(bp, PCI_D3hot);
12661
12662         /* Make sure RESET task is not scheduled before continuing */
12663         cancel_delayed_work_sync(&bp->sp_rtnl_task);
12664
12665         bnx2x_iov_remove_one(bp);
12666
12667         /* send message via vfpf channel to release the resources of this vf */
12668         if (IS_VF(bp))
12669                 bnx2x_vfpf_release(bp);
12670
12671         if (bp->regview)
12672                 iounmap(bp->regview);
12673
12674         /* for vf doorbells are part of the regview and were unmapped along with
12675          * it. FW is only loaded by PF.
12676          */
12677         if (IS_PF(bp)) {
12678                 if (bp->doorbells)
12679                         iounmap(bp->doorbells);
12680
12681                 bnx2x_release_firmware(bp);
12682         }
12683         bnx2x_free_mem_bp(bp);
12684
12685         free_netdev(dev);
12686
12687         if (atomic_read(&pdev->enable_cnt) == 1)
12688                 pci_release_regions(pdev);
12689
12690         pci_disable_device(pdev);
12691         pci_set_drvdata(pdev, NULL);
12692 }
12693
12694 static int bnx2x_eeh_nic_unload(struct bnx2x *bp)
12695 {
12696         bp->state = BNX2X_STATE_CLOSING_WAIT4_HALT;
12697
12698         bp->rx_mode = BNX2X_RX_MODE_NONE;
12699
12700         if (CNIC_LOADED(bp))
12701                 bnx2x_cnic_notify(bp, CNIC_CTL_STOP_CMD);
12702
12703         /* Stop Tx */
12704         bnx2x_tx_disable(bp);
12705         /* Delete all NAPI objects */
12706         bnx2x_del_all_napi(bp);
12707         if (CNIC_LOADED(bp))
12708                 bnx2x_del_all_napi_cnic(bp);
12709         netdev_reset_tc(bp->dev);
12710
12711         del_timer_sync(&bp->timer);
12712         cancel_delayed_work(&bp->sp_task);
12713         cancel_delayed_work(&bp->period_task);
12714
12715         spin_lock_bh(&bp->stats_lock);
12716         bp->stats_state = STATS_STATE_DISABLED;
12717         spin_unlock_bh(&bp->stats_lock);
12718
12719         bnx2x_save_statistics(bp);
12720
12721         netif_carrier_off(bp->dev);
12722
12723         return 0;
12724 }
12725
12726 static void bnx2x_eeh_recover(struct bnx2x *bp)
12727 {
12728         u32 val;
12729
12730         mutex_init(&bp->port.phy_mutex);
12731
12732
12733         val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]);
12734         if ((val & (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB))
12735                 != (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB))
12736                 BNX2X_ERR("BAD MCP validity signature\n");
12737 }
12738
12739 /**
12740  * bnx2x_io_error_detected - called when PCI error is detected
12741  * @pdev: Pointer to PCI device
12742  * @state: The current pci connection state
12743  *
12744  * This function is called after a PCI bus error affecting
12745  * this device has been detected.
12746  */
12747 static pci_ers_result_t bnx2x_io_error_detected(struct pci_dev *pdev,
12748                                                 pci_channel_state_t state)
12749 {
12750         struct net_device *dev = pci_get_drvdata(pdev);
12751         struct bnx2x *bp = netdev_priv(dev);
12752
12753         rtnl_lock();
12754
12755         BNX2X_ERR("IO error detected\n");
12756
12757         netif_device_detach(dev);
12758
12759         if (state == pci_channel_io_perm_failure) {
12760                 rtnl_unlock();
12761                 return PCI_ERS_RESULT_DISCONNECT;
12762         }
12763
12764         if (netif_running(dev))
12765                 bnx2x_eeh_nic_unload(bp);
12766
12767         bnx2x_prev_path_mark_eeh(bp);
12768
12769         pci_disable_device(pdev);
12770
12771         rtnl_unlock();
12772
12773         /* Request a slot reset */
12774         return PCI_ERS_RESULT_NEED_RESET;
12775 }
12776
12777 /**
12778  * bnx2x_io_slot_reset - called after the PCI bus has been reset
12779  * @pdev: Pointer to PCI device
12780  *
12781  * Restart the card from scratch, as if from a cold-boot.
12782  */
12783 static pci_ers_result_t bnx2x_io_slot_reset(struct pci_dev *pdev)
12784 {
12785         struct net_device *dev = pci_get_drvdata(pdev);
12786         struct bnx2x *bp = netdev_priv(dev);
12787         int i;
12788
12789         rtnl_lock();
12790         BNX2X_ERR("IO slot reset initializing...\n");
12791         if (pci_enable_device(pdev)) {
12792                 dev_err(&pdev->dev,
12793                         "Cannot re-enable PCI device after reset\n");
12794                 rtnl_unlock();
12795                 return PCI_ERS_RESULT_DISCONNECT;
12796         }
12797
12798         pci_set_master(pdev);
12799         pci_restore_state(pdev);
12800
12801         if (netif_running(dev))
12802                 bnx2x_set_power_state(bp, PCI_D0);
12803
12804         if (netif_running(dev)) {
12805                 BNX2X_ERR("IO slot reset --> driver unload\n");
12806                 if (IS_PF(bp) && SHMEM2_HAS(bp, drv_capabilities_flag)) {
12807                         u32 v;
12808
12809                         v = SHMEM2_RD(bp,
12810                                       drv_capabilities_flag[BP_FW_MB_IDX(bp)]);
12811                         SHMEM2_WR(bp, drv_capabilities_flag[BP_FW_MB_IDX(bp)],
12812                                   v & ~DRV_FLAGS_CAPABILITIES_LOADED_L2);
12813                 }
12814                 bnx2x_drain_tx_queues(bp);
12815                 bnx2x_send_unload_req(bp, UNLOAD_RECOVERY);
12816                 bnx2x_netif_stop(bp, 1);
12817                 bnx2x_free_irq(bp);
12818
12819                 /* Report UNLOAD_DONE to MCP */
12820                 bnx2x_send_unload_done(bp, true);
12821
12822                 bp->sp_state = 0;
12823                 bp->port.pmf = 0;
12824
12825                 bnx2x_prev_unload(bp);
12826
12827                 /* We should have resetted the engine, so It's fair to
12828                  * assume the FW will no longer write to the bnx2x driver.
12829                  */
12830                 bnx2x_squeeze_objects(bp);
12831                 bnx2x_free_skbs(bp);
12832                 for_each_rx_queue(bp, i)
12833                         bnx2x_free_rx_sge_range(bp, bp->fp + i, NUM_RX_SGE);
12834                 bnx2x_free_fp_mem(bp);
12835                 bnx2x_free_mem(bp);
12836
12837                 bp->state = BNX2X_STATE_CLOSED;
12838         }
12839
12840         rtnl_unlock();
12841
12842         return PCI_ERS_RESULT_RECOVERED;
12843 }
12844
12845 /**
12846  * bnx2x_io_resume - called when traffic can start flowing again
12847  * @pdev: Pointer to PCI device
12848  *
12849  * This callback is called when the error recovery driver tells us that
12850  * its OK to resume normal operation.
12851  */
12852 static void bnx2x_io_resume(struct pci_dev *pdev)
12853 {
12854         struct net_device *dev = pci_get_drvdata(pdev);
12855         struct bnx2x *bp = netdev_priv(dev);
12856
12857         if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
12858                 netdev_err(bp->dev, "Handling parity error recovery. Try again later\n");
12859                 return;
12860         }
12861
12862         rtnl_lock();
12863
12864         bnx2x_eeh_recover(bp);
12865
12866         bp->fw_seq = SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) &
12867                                                         DRV_MSG_SEQ_NUMBER_MASK;
12868
12869         if (netif_running(dev))
12870                 bnx2x_nic_load(bp, LOAD_NORMAL);
12871
12872         netif_device_attach(dev);
12873
12874         rtnl_unlock();
12875 }
12876
12877 static const struct pci_error_handlers bnx2x_err_handler = {
12878         .error_detected = bnx2x_io_error_detected,
12879         .slot_reset     = bnx2x_io_slot_reset,
12880         .resume         = bnx2x_io_resume,
12881 };
12882
12883 static struct pci_driver bnx2x_pci_driver = {
12884         .name        = DRV_MODULE_NAME,
12885         .id_table    = bnx2x_pci_tbl,
12886         .probe       = bnx2x_init_one,
12887         .remove      = bnx2x_remove_one,
12888         .suspend     = bnx2x_suspend,
12889         .resume      = bnx2x_resume,
12890         .err_handler = &bnx2x_err_handler,
12891 #ifdef CONFIG_BNX2X_SRIOV
12892         .sriov_configure = bnx2x_sriov_configure,
12893 #endif
12894 };
12895
12896 static int __init bnx2x_init(void)
12897 {
12898         int ret;
12899
12900         pr_info("%s", version);
12901
12902         bnx2x_wq = create_singlethread_workqueue("bnx2x");
12903         if (bnx2x_wq == NULL) {
12904                 pr_err("Cannot create workqueue\n");
12905                 return -ENOMEM;
12906         }
12907
12908         ret = pci_register_driver(&bnx2x_pci_driver);
12909         if (ret) {
12910                 pr_err("Cannot register driver\n");
12911                 destroy_workqueue(bnx2x_wq);
12912         }
12913         return ret;
12914 }
12915
12916 static void __exit bnx2x_cleanup(void)
12917 {
12918         struct list_head *pos, *q;
12919         pci_unregister_driver(&bnx2x_pci_driver);
12920
12921         destroy_workqueue(bnx2x_wq);
12922
12923         /* Free globablly allocated resources */
12924         list_for_each_safe(pos, q, &bnx2x_prev_list) {
12925                 struct bnx2x_prev_path_list *tmp =
12926                         list_entry(pos, struct bnx2x_prev_path_list, list);
12927                 list_del(pos);
12928                 kfree(tmp);
12929         }
12930 }
12931
12932 void bnx2x_notify_link_changed(struct bnx2x *bp)
12933 {
12934         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + BP_FUNC(bp)*sizeof(u32), 1);
12935 }
12936
12937 module_init(bnx2x_init);
12938 module_exit(bnx2x_cleanup);
12939
12940 /**
12941  * bnx2x_set_iscsi_eth_mac_addr - set iSCSI MAC(s).
12942  *
12943  * @bp:         driver handle
12944  * @set:        set or clear the CAM entry
12945  *
12946  * This function will wait until the ramdord completion returns.
12947  * Return 0 if success, -ENODEV if ramrod doesn't return.
12948  */
12949 static int bnx2x_set_iscsi_eth_mac_addr(struct bnx2x *bp)
12950 {
12951         unsigned long ramrod_flags = 0;
12952
12953         __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
12954         return bnx2x_set_mac_one(bp, bp->cnic_eth_dev.iscsi_mac,
12955                                  &bp->iscsi_l2_mac_obj, true,
12956                                  BNX2X_ISCSI_ETH_MAC, &ramrod_flags);
12957 }
12958
12959 /* count denotes the number of new completions we have seen */
12960 static void bnx2x_cnic_sp_post(struct bnx2x *bp, int count)
12961 {
12962         struct eth_spe *spe;
12963         int cxt_index, cxt_offset;
12964
12965 #ifdef BNX2X_STOP_ON_ERROR
12966         if (unlikely(bp->panic))
12967                 return;
12968 #endif
12969
12970         spin_lock_bh(&bp->spq_lock);
12971         BUG_ON(bp->cnic_spq_pending < count);
12972         bp->cnic_spq_pending -= count;
12973
12974
12975         for (; bp->cnic_kwq_pending; bp->cnic_kwq_pending--) {
12976                 u16 type =  (le16_to_cpu(bp->cnic_kwq_cons->hdr.type)
12977                                 & SPE_HDR_CONN_TYPE) >>
12978                                 SPE_HDR_CONN_TYPE_SHIFT;
12979                 u8 cmd = (le32_to_cpu(bp->cnic_kwq_cons->hdr.conn_and_cmd_data)
12980                                 >> SPE_HDR_CMD_ID_SHIFT) & 0xff;
12981
12982                 /* Set validation for iSCSI L2 client before sending SETUP
12983                  *  ramrod
12984                  */
12985                 if (type == ETH_CONNECTION_TYPE) {
12986                         if (cmd == RAMROD_CMD_ID_ETH_CLIENT_SETUP) {
12987                                 cxt_index = BNX2X_ISCSI_ETH_CID(bp) /
12988                                         ILT_PAGE_CIDS;
12989                                 cxt_offset = BNX2X_ISCSI_ETH_CID(bp) -
12990                                         (cxt_index * ILT_PAGE_CIDS);
12991                                 bnx2x_set_ctx_validation(bp,
12992                                         &bp->context[cxt_index].
12993                                                          vcxt[cxt_offset].eth,
12994                                         BNX2X_ISCSI_ETH_CID(bp));
12995                         }
12996                 }
12997
12998                 /*
12999                  * There may be not more than 8 L2, not more than 8 L5 SPEs
13000                  * and in the air. We also check that number of outstanding
13001                  * COMMON ramrods is not more than the EQ and SPQ can
13002                  * accommodate.
13003                  */
13004                 if (type == ETH_CONNECTION_TYPE) {
13005                         if (!atomic_read(&bp->cq_spq_left))
13006                                 break;
13007                         else
13008                                 atomic_dec(&bp->cq_spq_left);
13009                 } else if (type == NONE_CONNECTION_TYPE) {
13010                         if (!atomic_read(&bp->eq_spq_left))
13011                                 break;
13012                         else
13013                                 atomic_dec(&bp->eq_spq_left);
13014                 } else if ((type == ISCSI_CONNECTION_TYPE) ||
13015                            (type == FCOE_CONNECTION_TYPE)) {
13016                         if (bp->cnic_spq_pending >=
13017                             bp->cnic_eth_dev.max_kwqe_pending)
13018                                 break;
13019                         else
13020                                 bp->cnic_spq_pending++;
13021                 } else {
13022                         BNX2X_ERR("Unknown SPE type: %d\n", type);
13023                         bnx2x_panic();
13024                         break;
13025                 }
13026
13027                 spe = bnx2x_sp_get_next(bp);
13028                 *spe = *bp->cnic_kwq_cons;
13029
13030                 DP(BNX2X_MSG_SP, "pending on SPQ %d, on KWQ %d count %d\n",
13031                    bp->cnic_spq_pending, bp->cnic_kwq_pending, count);
13032
13033                 if (bp->cnic_kwq_cons == bp->cnic_kwq_last)
13034                         bp->cnic_kwq_cons = bp->cnic_kwq;
13035                 else
13036                         bp->cnic_kwq_cons++;
13037         }
13038         bnx2x_sp_prod_update(bp);
13039         spin_unlock_bh(&bp->spq_lock);
13040 }
13041
13042 static int bnx2x_cnic_sp_queue(struct net_device *dev,
13043                                struct kwqe_16 *kwqes[], u32 count)
13044 {
13045         struct bnx2x *bp = netdev_priv(dev);
13046         int i;
13047
13048 #ifdef BNX2X_STOP_ON_ERROR
13049         if (unlikely(bp->panic)) {
13050                 BNX2X_ERR("Can't post to SP queue while panic\n");
13051                 return -EIO;
13052         }
13053 #endif
13054
13055         if ((bp->recovery_state != BNX2X_RECOVERY_DONE) &&
13056             (bp->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) {
13057                 BNX2X_ERR("Handling parity error recovery. Try again later\n");
13058                 return -EAGAIN;
13059         }
13060
13061         spin_lock_bh(&bp->spq_lock);
13062
13063         for (i = 0; i < count; i++) {
13064                 struct eth_spe *spe = (struct eth_spe *)kwqes[i];
13065
13066                 if (bp->cnic_kwq_pending == MAX_SP_DESC_CNT)
13067                         break;
13068
13069                 *bp->cnic_kwq_prod = *spe;
13070
13071                 bp->cnic_kwq_pending++;
13072
13073                 DP(BNX2X_MSG_SP, "L5 SPQE %x %x %x:%x pos %d\n",
13074                    spe->hdr.conn_and_cmd_data, spe->hdr.type,
13075                    spe->data.update_data_addr.hi,
13076                    spe->data.update_data_addr.lo,
13077                    bp->cnic_kwq_pending);
13078
13079                 if (bp->cnic_kwq_prod == bp->cnic_kwq_last)
13080                         bp->cnic_kwq_prod = bp->cnic_kwq;
13081                 else
13082                         bp->cnic_kwq_prod++;
13083         }
13084
13085         spin_unlock_bh(&bp->spq_lock);
13086
13087         if (bp->cnic_spq_pending < bp->cnic_eth_dev.max_kwqe_pending)
13088                 bnx2x_cnic_sp_post(bp, 0);
13089
13090         return i;
13091 }
13092
13093 static int bnx2x_cnic_ctl_send(struct bnx2x *bp, struct cnic_ctl_info *ctl)
13094 {
13095         struct cnic_ops *c_ops;
13096         int rc = 0;
13097
13098         mutex_lock(&bp->cnic_mutex);
13099         c_ops = rcu_dereference_protected(bp->cnic_ops,
13100                                           lockdep_is_held(&bp->cnic_mutex));
13101         if (c_ops)
13102                 rc = c_ops->cnic_ctl(bp->cnic_data, ctl);
13103         mutex_unlock(&bp->cnic_mutex);
13104
13105         return rc;
13106 }
13107
13108 static int bnx2x_cnic_ctl_send_bh(struct bnx2x *bp, struct cnic_ctl_info *ctl)
13109 {
13110         struct cnic_ops *c_ops;
13111         int rc = 0;
13112
13113         rcu_read_lock();
13114         c_ops = rcu_dereference(bp->cnic_ops);
13115         if (c_ops)
13116                 rc = c_ops->cnic_ctl(bp->cnic_data, ctl);
13117         rcu_read_unlock();
13118
13119         return rc;
13120 }
13121
13122 /*
13123  * for commands that have no data
13124  */
13125 int bnx2x_cnic_notify(struct bnx2x *bp, int cmd)
13126 {
13127         struct cnic_ctl_info ctl = {0};
13128
13129         ctl.cmd = cmd;
13130
13131         return bnx2x_cnic_ctl_send(bp, &ctl);
13132 }
13133
13134 static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err)
13135 {
13136         struct cnic_ctl_info ctl = {0};
13137
13138         /* first we tell CNIC and only then we count this as a completion */
13139         ctl.cmd = CNIC_CTL_COMPLETION_CMD;
13140         ctl.data.comp.cid = cid;
13141         ctl.data.comp.error = err;
13142
13143         bnx2x_cnic_ctl_send_bh(bp, &ctl);
13144         bnx2x_cnic_sp_post(bp, 0);
13145 }
13146
13147
13148 /* Called with netif_addr_lock_bh() taken.
13149  * Sets an rx_mode config for an iSCSI ETH client.
13150  * Doesn't block.
13151  * Completion should be checked outside.
13152  */
13153 static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start)
13154 {
13155         unsigned long accept_flags = 0, ramrod_flags = 0;
13156         u8 cl_id = bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX);
13157         int sched_state = BNX2X_FILTER_ISCSI_ETH_STOP_SCHED;
13158
13159         if (start) {
13160                 /* Start accepting on iSCSI L2 ring. Accept all multicasts
13161                  * because it's the only way for UIO Queue to accept
13162                  * multicasts (in non-promiscuous mode only one Queue per
13163                  * function will receive multicast packets (leading in our
13164                  * case).
13165                  */
13166                 __set_bit(BNX2X_ACCEPT_UNICAST, &accept_flags);
13167                 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &accept_flags);
13168                 __set_bit(BNX2X_ACCEPT_BROADCAST, &accept_flags);
13169                 __set_bit(BNX2X_ACCEPT_ANY_VLAN, &accept_flags);
13170
13171                 /* Clear STOP_PENDING bit if START is requested */
13172                 clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &bp->sp_state);
13173
13174                 sched_state = BNX2X_FILTER_ISCSI_ETH_START_SCHED;
13175         } else
13176                 /* Clear START_PENDING bit if STOP is requested */
13177                 clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &bp->sp_state);
13178
13179         if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state))
13180                 set_bit(sched_state, &bp->sp_state);
13181         else {
13182                 __set_bit(RAMROD_RX, &ramrod_flags);
13183                 bnx2x_set_q_rx_mode(bp, cl_id, 0, accept_flags, 0,
13184                                     ramrod_flags);
13185         }
13186 }
13187
13188
13189 static int bnx2x_drv_ctl(struct net_device *dev, struct drv_ctl_info *ctl)
13190 {
13191         struct bnx2x *bp = netdev_priv(dev);
13192         int rc = 0;
13193
13194         switch (ctl->cmd) {
13195         case DRV_CTL_CTXTBL_WR_CMD: {
13196                 u32 index = ctl->data.io.offset;
13197                 dma_addr_t addr = ctl->data.io.dma_addr;
13198
13199                 bnx2x_ilt_wr(bp, index, addr);
13200                 break;
13201         }
13202
13203         case DRV_CTL_RET_L5_SPQ_CREDIT_CMD: {
13204                 int count = ctl->data.credit.credit_count;
13205
13206                 bnx2x_cnic_sp_post(bp, count);
13207                 break;
13208         }
13209
13210         /* rtnl_lock is held.  */
13211         case DRV_CTL_START_L2_CMD: {
13212                 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
13213                 unsigned long sp_bits = 0;
13214
13215                 /* Configure the iSCSI classification object */
13216                 bnx2x_init_mac_obj(bp, &bp->iscsi_l2_mac_obj,
13217                                    cp->iscsi_l2_client_id,
13218                                    cp->iscsi_l2_cid, BP_FUNC(bp),
13219                                    bnx2x_sp(bp, mac_rdata),
13220                                    bnx2x_sp_mapping(bp, mac_rdata),
13221                                    BNX2X_FILTER_MAC_PENDING,
13222                                    &bp->sp_state, BNX2X_OBJ_TYPE_RX,
13223                                    &bp->macs_pool);
13224
13225                 /* Set iSCSI MAC address */
13226                 rc = bnx2x_set_iscsi_eth_mac_addr(bp);
13227                 if (rc)
13228                         break;
13229
13230                 mmiowb();
13231                 barrier();
13232
13233                 /* Start accepting on iSCSI L2 ring */
13234
13235                 netif_addr_lock_bh(dev);
13236                 bnx2x_set_iscsi_eth_rx_mode(bp, true);
13237                 netif_addr_unlock_bh(dev);
13238
13239                 /* bits to wait on */
13240                 __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits);
13241                 __set_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &sp_bits);
13242
13243                 if (!bnx2x_wait_sp_comp(bp, sp_bits))
13244                         BNX2X_ERR("rx_mode completion timed out!\n");
13245
13246                 break;
13247         }
13248
13249         /* rtnl_lock is held.  */
13250         case DRV_CTL_STOP_L2_CMD: {
13251                 unsigned long sp_bits = 0;
13252
13253                 /* Stop accepting on iSCSI L2 ring */
13254                 netif_addr_lock_bh(dev);
13255                 bnx2x_set_iscsi_eth_rx_mode(bp, false);
13256                 netif_addr_unlock_bh(dev);
13257
13258                 /* bits to wait on */
13259                 __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits);
13260                 __set_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &sp_bits);
13261
13262                 if (!bnx2x_wait_sp_comp(bp, sp_bits))
13263                         BNX2X_ERR("rx_mode completion timed out!\n");
13264
13265                 mmiowb();
13266                 barrier();
13267
13268                 /* Unset iSCSI L2 MAC */
13269                 rc = bnx2x_del_all_macs(bp, &bp->iscsi_l2_mac_obj,
13270                                         BNX2X_ISCSI_ETH_MAC, true);
13271                 break;
13272         }
13273         case DRV_CTL_RET_L2_SPQ_CREDIT_CMD: {
13274                 int count = ctl->data.credit.credit_count;
13275
13276                 smp_mb__before_atomic_inc();
13277                 atomic_add(count, &bp->cq_spq_left);
13278                 smp_mb__after_atomic_inc();
13279                 break;
13280         }
13281         case DRV_CTL_ULP_REGISTER_CMD: {
13282                 int ulp_type = ctl->data.register_data.ulp_type;
13283
13284                 if (CHIP_IS_E3(bp)) {
13285                         int idx = BP_FW_MB_IDX(bp);
13286                         u32 cap = SHMEM2_RD(bp, drv_capabilities_flag[idx]);
13287                         int path = BP_PATH(bp);
13288                         int port = BP_PORT(bp);
13289                         int i;
13290                         u32 scratch_offset;
13291                         u32 *host_addr;
13292
13293                         /* first write capability to shmem2 */
13294                         if (ulp_type == CNIC_ULP_ISCSI)
13295                                 cap |= DRV_FLAGS_CAPABILITIES_LOADED_ISCSI;
13296                         else if (ulp_type == CNIC_ULP_FCOE)
13297                                 cap |= DRV_FLAGS_CAPABILITIES_LOADED_FCOE;
13298                         SHMEM2_WR(bp, drv_capabilities_flag[idx], cap);
13299
13300                         if ((ulp_type != CNIC_ULP_FCOE) ||
13301                             (!SHMEM2_HAS(bp, ncsi_oem_data_addr)) ||
13302                             (!(bp->flags &  BC_SUPPORTS_FCOE_FEATURES)))
13303                                 break;
13304
13305                         /* if reached here - should write fcoe capabilities */
13306                         scratch_offset = SHMEM2_RD(bp, ncsi_oem_data_addr);
13307                         if (!scratch_offset)
13308                                 break;
13309                         scratch_offset += offsetof(struct glob_ncsi_oem_data,
13310                                                    fcoe_features[path][port]);
13311                         host_addr = (u32 *) &(ctl->data.register_data.
13312                                               fcoe_features);
13313                         for (i = 0; i < sizeof(struct fcoe_capabilities);
13314                              i += 4)
13315                                 REG_WR(bp, scratch_offset + i,
13316                                        *(host_addr + i/4));
13317                 }
13318                 break;
13319         }
13320
13321         case DRV_CTL_ULP_UNREGISTER_CMD: {
13322                 int ulp_type = ctl->data.ulp_type;
13323
13324                 if (CHIP_IS_E3(bp)) {
13325                         int idx = BP_FW_MB_IDX(bp);
13326                         u32 cap;
13327
13328                         cap = SHMEM2_RD(bp, drv_capabilities_flag[idx]);
13329                         if (ulp_type == CNIC_ULP_ISCSI)
13330                                 cap &= ~DRV_FLAGS_CAPABILITIES_LOADED_ISCSI;
13331                         else if (ulp_type == CNIC_ULP_FCOE)
13332                                 cap &= ~DRV_FLAGS_CAPABILITIES_LOADED_FCOE;
13333                         SHMEM2_WR(bp, drv_capabilities_flag[idx], cap);
13334                 }
13335                 break;
13336         }
13337
13338         default:
13339                 BNX2X_ERR("unknown command %x\n", ctl->cmd);
13340                 rc = -EINVAL;
13341         }
13342
13343         return rc;
13344 }
13345
13346 void bnx2x_setup_cnic_irq_info(struct bnx2x *bp)
13347 {
13348         struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
13349
13350         if (bp->flags & USING_MSIX_FLAG) {
13351                 cp->drv_state |= CNIC_DRV_STATE_USING_MSIX;
13352                 cp->irq_arr[0].irq_flags |= CNIC_IRQ_FL_MSIX;
13353                 cp->irq_arr[0].vector = bp->msix_table[1].vector;
13354         } else {
13355                 cp->drv_state &= ~CNIC_DRV_STATE_USING_MSIX;
13356                 cp->irq_arr[0].irq_flags &= ~CNIC_IRQ_FL_MSIX;
13357         }
13358         if (!CHIP_IS_E1x(bp))
13359                 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e2_sb;
13360         else
13361                 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e1x_sb;
13362
13363         cp->irq_arr[0].status_blk_num =  bnx2x_cnic_fw_sb_id(bp);
13364         cp->irq_arr[0].status_blk_num2 = bnx2x_cnic_igu_sb_id(bp);
13365         cp->irq_arr[1].status_blk = bp->def_status_blk;
13366         cp->irq_arr[1].status_blk_num = DEF_SB_ID;
13367         cp->irq_arr[1].status_blk_num2 = DEF_SB_IGU_ID;
13368
13369         cp->num_irq = 2;
13370 }
13371
13372 void bnx2x_setup_cnic_info(struct bnx2x *bp)
13373 {
13374         struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
13375
13376
13377         cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) +
13378                              bnx2x_cid_ilt_lines(bp);
13379         cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS;
13380         cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID(bp);
13381         cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID(bp);
13382
13383         if (NO_ISCSI_OOO(bp))
13384                 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI_OOO;
13385 }
13386
13387 static int bnx2x_register_cnic(struct net_device *dev, struct cnic_ops *ops,
13388                                void *data)
13389 {
13390         struct bnx2x *bp = netdev_priv(dev);
13391         struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
13392         int rc;
13393
13394         DP(NETIF_MSG_IFUP, "Register_cnic called\n");
13395
13396         if (ops == NULL) {
13397                 BNX2X_ERR("NULL ops received\n");
13398                 return -EINVAL;
13399         }
13400
13401         if (!CNIC_SUPPORT(bp)) {
13402                 BNX2X_ERR("Can't register CNIC when not supported\n");
13403                 return -EOPNOTSUPP;
13404         }
13405
13406         if (!CNIC_LOADED(bp)) {
13407                 rc = bnx2x_load_cnic(bp);
13408                 if (rc) {
13409                         BNX2X_ERR("CNIC-related load failed\n");
13410                         return rc;
13411                 }
13412
13413         }
13414
13415         bp->cnic_enabled = true;
13416
13417         bp->cnic_kwq = kzalloc(PAGE_SIZE, GFP_KERNEL);
13418         if (!bp->cnic_kwq)
13419                 return -ENOMEM;
13420
13421         bp->cnic_kwq_cons = bp->cnic_kwq;
13422         bp->cnic_kwq_prod = bp->cnic_kwq;
13423         bp->cnic_kwq_last = bp->cnic_kwq + MAX_SP_DESC_CNT;
13424
13425         bp->cnic_spq_pending = 0;
13426         bp->cnic_kwq_pending = 0;
13427
13428         bp->cnic_data = data;
13429
13430         cp->num_irq = 0;
13431         cp->drv_state |= CNIC_DRV_STATE_REGD;
13432         cp->iro_arr = bp->iro_arr;
13433
13434         bnx2x_setup_cnic_irq_info(bp);
13435
13436         rcu_assign_pointer(bp->cnic_ops, ops);
13437
13438         return 0;
13439 }
13440
13441 static int bnx2x_unregister_cnic(struct net_device *dev)
13442 {
13443         struct bnx2x *bp = netdev_priv(dev);
13444         struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
13445
13446         mutex_lock(&bp->cnic_mutex);
13447         cp->drv_state = 0;
13448         RCU_INIT_POINTER(bp->cnic_ops, NULL);
13449         mutex_unlock(&bp->cnic_mutex);
13450         synchronize_rcu();
13451         kfree(bp->cnic_kwq);
13452         bp->cnic_kwq = NULL;
13453
13454         return 0;
13455 }
13456
13457 struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev)
13458 {
13459         struct bnx2x *bp = netdev_priv(dev);
13460         struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
13461
13462         /* If both iSCSI and FCoE are disabled - return NULL in
13463          * order to indicate CNIC that it should not try to work
13464          * with this device.
13465          */
13466         if (NO_ISCSI(bp) && NO_FCOE(bp))
13467                 return NULL;
13468
13469         cp->drv_owner = THIS_MODULE;
13470         cp->chip_id = CHIP_ID(bp);
13471         cp->pdev = bp->pdev;
13472         cp->io_base = bp->regview;
13473         cp->io_base2 = bp->doorbells;
13474         cp->max_kwqe_pending = 8;
13475         cp->ctx_blk_size = CDU_ILT_PAGE_SZ;
13476         cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) +
13477                              bnx2x_cid_ilt_lines(bp);
13478         cp->ctx_tbl_len = CNIC_ILT_LINES;
13479         cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS;
13480         cp->drv_submit_kwqes_16 = bnx2x_cnic_sp_queue;
13481         cp->drv_ctl = bnx2x_drv_ctl;
13482         cp->drv_register_cnic = bnx2x_register_cnic;
13483         cp->drv_unregister_cnic = bnx2x_unregister_cnic;
13484         cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID(bp);
13485         cp->iscsi_l2_client_id =
13486                 bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX);
13487         cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID(bp);
13488
13489         if (NO_ISCSI_OOO(bp))
13490                 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI_OOO;
13491
13492         if (NO_ISCSI(bp))
13493                 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI;
13494
13495         if (NO_FCOE(bp))
13496                 cp->drv_state |= CNIC_DRV_STATE_NO_FCOE;
13497
13498         BNX2X_DEV_INFO(
13499                 "page_size %d, tbl_offset %d, tbl_lines %d, starting cid %d\n",
13500            cp->ctx_blk_size,
13501            cp->ctx_tbl_offset,
13502            cp->ctx_tbl_len,
13503            cp->starting_cid);
13504         return cp;
13505 }
13506
13507 u32 bnx2x_rx_ustorm_prods_offset(struct bnx2x_fastpath *fp)
13508 {
13509         struct bnx2x *bp = fp->bp;
13510         u32 offset = BAR_USTRORM_INTMEM;
13511
13512         if (IS_VF(bp))
13513                 return bnx2x_vf_ustorm_prods_offset(bp, fp);
13514         else if (!CHIP_IS_E1x(bp))
13515                 offset += USTORM_RX_PRODS_E2_OFFSET(fp->cl_qzone_id);
13516         else
13517                 offset += USTORM_RX_PRODS_E1X_OFFSET(BP_PORT(bp), fp->cl_id);
13518
13519         return offset;
13520 }
13521
13522 /* called only on E1H or E2.
13523  * When pretending to be PF, the pretend value is the function number 0...7
13524  * When pretending to be VF, the pretend val is the PF-num:VF-valid:ABS-VFID
13525  * combination
13526  */
13527 int bnx2x_pretend_func(struct bnx2x *bp, u16 pretend_func_val)
13528 {
13529         u32 pretend_reg;
13530
13531         if (CHIP_IS_E1H(bp) && pretend_func_val >= E1H_FUNC_MAX)
13532                 return -1;
13533
13534         /* get my own pretend register */
13535         pretend_reg = bnx2x_get_pretend_reg(bp);
13536         REG_WR(bp, pretend_reg, pretend_func_val);
13537         REG_RD(bp, pretend_reg);
13538         return 0;
13539 }