drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c

   1 /* Copyright 2008-2013 Broadcom Corporation
   2  * Copyright (c) 2014 QLogic Corporation
   3  * All rights reserved
   4  *
   5  * Unless you and QLogic execute a separate written software license
   6  * agreement governing use of this software, this software is licensed to you
   7  * under the terms of the GNU General Public License version 2, available
   8  * at http://www.gnu.org/licenses/gpl-2.0.html (the "GPL").
   9  *
  10  * Notwithstanding the above, under no circumstances may you combine this
  11  * software in any way with any other Qlogic software provided under a
  12  * license other than the GPL, without Qlogic's express prior written
  13  * consent.
  14  *
  15  * Written by Yaniv Rosner
  16  *
  17  */
  18
  19 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  20
  21 #include <linux/kernel.h>
  22 #include <linux/errno.h>
  23 #include <linux/pci.h>
  24 #include <linux/netdevice.h>
  25 #include <linux/delay.h>
  26 #include <linux/ethtool.h>
  27 #include <linux/mutex.h>
  28
  29 #include "bnx2x.h"
  30 #include "bnx2x_cmn.h"
  31
  32 typedef int (*read_sfp_module_eeprom_func_p)(struct bnx2x_phy *phy,
  33                                              struct link_params *params,
  34                                              u8 dev_addr, u16 addr, u8 byte_cnt,
  35                                              u8 *o_buf, u8);
  36 /********************************************************/
  37 #define MDIO_ACCESS_TIMEOUT             1000
  38 #define WC_LANE_MAX                     4
  39 #define I2C_SWITCH_WIDTH                2
  40 #define I2C_BSC0                        0
  41 #define I2C_BSC1                        1
  42 #define I2C_WA_RETRY_CNT                3
  43 #define I2C_WA_PWR_ITER                 (I2C_WA_RETRY_CNT - 1)
  44 #define MCPR_IMC_COMMAND_READ_OP        1
  45 #define MCPR_IMC_COMMAND_WRITE_OP       2
  46
  47 /* LED Blink rate that will achieve ~15.9Hz */
  48 #define LED_BLINK_RATE_VAL_E3           354
  49 #define LED_BLINK_RATE_VAL_E1X_E2       480
  50 /***********************************************************/
  51 /*                      Shortcut definitions               */
  52 /***********************************************************/
  53
  54 #define NIG_LATCH_BC_ENABLE_MI_INT 0
  55
  56 #define NIG_STATUS_EMAC0_MI_INT \
  57                 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_EMAC0_MISC_MI_INT
  58 #define NIG_STATUS_XGXS0_LINK10G \
  59                 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK10G
  60 #define NIG_STATUS_XGXS0_LINK_STATUS \
  61                 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS
  62 #define NIG_STATUS_XGXS0_LINK_STATUS_SIZE \
  63                 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS_SIZE
  64 #define NIG_STATUS_SERDES0_LINK_STATUS \
  65                 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_LINK_STATUS
  66 #define NIG_MASK_MI_INT \
  67                 NIG_MASK_INTERRUPT_PORT0_REG_MASK_EMAC0_MISC_MI_INT
  68 #define NIG_MASK_XGXS0_LINK10G \
  69                 NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK10G
  70 #define NIG_MASK_XGXS0_LINK_STATUS \
  71                 NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK_STATUS
  72 #define NIG_MASK_SERDES0_LINK_STATUS \
  73                 NIG_MASK_INTERRUPT_PORT0_REG_MASK_SERDES0_LINK_STATUS
  74
  75 #define MDIO_AN_CL73_OR_37_COMPLETE \
  76                 (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE | \
  77                  MDIO_GP_STATUS_TOP_AN_STATUS1_CL37_AUTONEG_COMPLETE)
  78
  79 #define XGXS_RESET_BITS \
  80         (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_RSTB_HW |   \
  81          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_IDDQ |      \
  82          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN |    \
  83          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN_SD | \
  84          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_TXD_FIFO_RSTB)
  85
  86 #define SERDES_RESET_BITS \
  87         (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_RSTB_HW | \
  88          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_IDDQ |    \
  89          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN |  \
  90          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN_SD)
  91
  92 #define AUTONEG_CL37            SHARED_HW_CFG_AN_ENABLE_CL37
  93 #define AUTONEG_CL73            SHARED_HW_CFG_AN_ENABLE_CL73
  94 #define AUTONEG_BAM             SHARED_HW_CFG_AN_ENABLE_BAM
  95 #define AUTONEG_PARALLEL \
  96                                 SHARED_HW_CFG_AN_ENABLE_PARALLEL_DETECTION
  97 #define AUTONEG_SGMII_FIBER_AUTODET \
  98                                 SHARED_HW_CFG_AN_EN_SGMII_FIBER_AUTO_DETECT
  99 #define AUTONEG_REMOTE_PHY      SHARED_HW_CFG_AN_ENABLE_REMOTE_PHY
 100
 101 #define GP_STATUS_PAUSE_RSOLUTION_TXSIDE \
 102                         MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_TXSIDE
 103 #define GP_STATUS_PAUSE_RSOLUTION_RXSIDE \
 104                         MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_RXSIDE
 105 #define GP_STATUS_SPEED_MASK \
 106                         MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_MASK
 107 #define GP_STATUS_10M   MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10M
 108 #define GP_STATUS_100M  MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_100M
 109 #define GP_STATUS_1G    MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G
 110 #define GP_STATUS_2_5G  MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_2_5G
 111 #define GP_STATUS_5G    MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_5G
 112 #define GP_STATUS_6G    MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_6G
 113 #define GP_STATUS_10G_HIG \
 114                         MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_HIG
 115 #define GP_STATUS_10G_CX4 \
 116                         MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_CX4
 117 #define GP_STATUS_1G_KX MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G_KX
 118 #define GP_STATUS_10G_KX4 \
 119                         MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KX4
 120 #define GP_STATUS_10G_KR MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KR
 121 #define GP_STATUS_10G_XFI   MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_XFI
 122 #define GP_STATUS_20G_DXGXS MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_DXGXS
 123 #define GP_STATUS_10G_SFI   MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_SFI
 124 #define GP_STATUS_20G_KR2 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_KR2
 125 #define LINK_10THD              LINK_STATUS_SPEED_AND_DUPLEX_10THD
 126 #define LINK_10TFD              LINK_STATUS_SPEED_AND_DUPLEX_10TFD
 127 #define LINK_100TXHD            LINK_STATUS_SPEED_AND_DUPLEX_100TXHD
 128 #define LINK_100T4              LINK_STATUS_SPEED_AND_DUPLEX_100T4
 129 #define LINK_100TXFD            LINK_STATUS_SPEED_AND_DUPLEX_100TXFD
 130 #define LINK_1000THD            LINK_STATUS_SPEED_AND_DUPLEX_1000THD
 131 #define LINK_1000TFD            LINK_STATUS_SPEED_AND_DUPLEX_1000TFD
 132 #define LINK_1000XFD            LINK_STATUS_SPEED_AND_DUPLEX_1000XFD
 133 #define LINK_2500THD            LINK_STATUS_SPEED_AND_DUPLEX_2500THD
 134 #define LINK_2500TFD            LINK_STATUS_SPEED_AND_DUPLEX_2500TFD
 135 #define LINK_2500XFD            LINK_STATUS_SPEED_AND_DUPLEX_2500XFD
 136 #define LINK_10GTFD             LINK_STATUS_SPEED_AND_DUPLEX_10GTFD
 137 #define LINK_10GXFD             LINK_STATUS_SPEED_AND_DUPLEX_10GXFD
 138 #define LINK_20GTFD             LINK_STATUS_SPEED_AND_DUPLEX_20GTFD
 139 #define LINK_20GXFD             LINK_STATUS_SPEED_AND_DUPLEX_20GXFD
 140
 141 #define LINK_UPDATE_MASK \
 142                         (LINK_STATUS_SPEED_AND_DUPLEX_MASK | \
 143                          LINK_STATUS_LINK_UP | \
 144                          LINK_STATUS_PHYSICAL_LINK_FLAG | \
 145                          LINK_STATUS_AUTO_NEGOTIATE_COMPLETE | \
 146                          LINK_STATUS_RX_FLOW_CONTROL_FLAG_MASK | \
 147                          LINK_STATUS_TX_FLOW_CONTROL_FLAG_MASK | \
 148                          LINK_STATUS_PARALLEL_DETECTION_FLAG_MASK | \
 149                          LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE | \
 150                          LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE)
 151
 152 #define SFP_EEPROM_CON_TYPE_ADDR                0x2
 153         #define SFP_EEPROM_CON_TYPE_VAL_UNKNOWN 0x0
 154         #define SFP_EEPROM_CON_TYPE_VAL_LC      0x7
 155         #define SFP_EEPROM_CON_TYPE_VAL_COPPER  0x21
 156         #define SFP_EEPROM_CON_TYPE_VAL_RJ45    0x22
 157
 158
 159 #define SFP_EEPROM_10G_COMP_CODE_ADDR           0x3
 160         #define SFP_EEPROM_10G_COMP_CODE_SR_MASK        (1<<4)
 161         #define SFP_EEPROM_10G_COMP_CODE_LR_MASK        (1<<5)
 162         #define SFP_EEPROM_10G_COMP_CODE_LRM_MASK       (1<<6)
 163
 164 #define SFP_EEPROM_1G_COMP_CODE_ADDR            0x6
 165         #define SFP_EEPROM_1G_COMP_CODE_SX      (1<<0)
 166         #define SFP_EEPROM_1G_COMP_CODE_LX      (1<<1)
 167         #define SFP_EEPROM_1G_COMP_CODE_CX      (1<<2)
 168         #define SFP_EEPROM_1G_COMP_CODE_BASE_T  (1<<3)
 169
 170 #define SFP_EEPROM_FC_TX_TECH_ADDR              0x8
 171         #define SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE 0x4
 172         #define SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE  0x8
 173
 174 #define SFP_EEPROM_OPTIONS_ADDR                 0x40
 175         #define SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK 0x1
 176 #define SFP_EEPROM_OPTIONS_SIZE                 2
 177
 178 #define EDC_MODE_LINEAR                         0x0022
 179 #define EDC_MODE_LIMITING                               0x0044
 180 #define EDC_MODE_PASSIVE_DAC                    0x0055
 181 #define EDC_MODE_ACTIVE_DAC                     0x0066
 182
 183 /* ETS defines*/
 184 #define DCBX_INVALID_COS                                        (0xFF)
 185
 186 #define ETS_BW_LIMIT_CREDIT_UPPER_BOUND         (0x5000)
 187 #define ETS_BW_LIMIT_CREDIT_WEIGHT              (0x5000)
 188 #define ETS_E3B0_NIG_MIN_W_VAL_UP_TO_10GBPS             (1360)
 189 #define ETS_E3B0_NIG_MIN_W_VAL_20GBPS                   (2720)
 190 #define ETS_E3B0_PBF_MIN_W_VAL                          (10000)
 191
 192 #define MAX_PACKET_SIZE                                 (9700)
 193 #define MAX_KR_LINK_RETRY                               4
 194 #define DEFAULT_TX_DRV_BRDCT            2
 195 #define DEFAULT_TX_DRV_IFIR             0
 196 #define DEFAULT_TX_DRV_POST2            3
 197 #define DEFAULT_TX_DRV_IPRE_DRIVER      6
 198
 199 /**********************************************************/
 200 /*                     INTERFACE                          */
 201 /**********************************************************/
 202
 203 #define CL22_WR_OVER_CL45(_bp, _phy, _bank, _addr, _val) \
 204         bnx2x_cl45_write(_bp, _phy, \
 205                 (_phy)->def_md_devad, \
 206                 (_bank + (_addr & 0xf)), \
 207                 _val)
 208
 209 #define CL22_RD_OVER_CL45(_bp, _phy, _bank, _addr, _val) \
 210         bnx2x_cl45_read(_bp, _phy, \
 211                 (_phy)->def_md_devad, \
 212                 (_bank + (_addr & 0xf)), \
 213                 _val)
 214
 215 static int bnx2x_check_half_open_conn(struct link_params *params,
 216                                       struct link_vars *vars, u8 notify);
 217 static int bnx2x_sfp_module_detection(struct bnx2x_phy *phy,
 218                                       struct link_params *params);
 219
 220 static u32 bnx2x_bits_en(struct bnx2x *bp, u32 reg, u32 bits)
 221 {
 222         u32 val = REG_RD(bp, reg);
 223
 224         val |= bits;
 225         REG_WR(bp, reg, val);
 226         return val;
 227 }
 228
 229 static u32 bnx2x_bits_dis(struct bnx2x *bp, u32 reg, u32 bits)
 230 {
 231         u32 val = REG_RD(bp, reg);
 232
 233         val &= ~bits;
 234         REG_WR(bp, reg, val);
 235         return val;
 236 }
 237
 238 /*
 239  * bnx2x_check_lfa - This function checks if link reinitialization is required,
 240  *                   or link flap can be avoided.
 241  *
 242  * @params:     link parameters
 243  * Returns 0 if Link Flap Avoidance conditions are met otherwise, the failed
 244  *         condition code.
 245  */
 246 static int bnx2x_check_lfa(struct link_params *params)
 247 {
 248         u32 link_status, cfg_idx, lfa_mask, cfg_size;
 249         u32 cur_speed_cap_mask, cur_req_fc_auto_adv, additional_config;
 250         u32 saved_val, req_val, eee_status;
 251         struct bnx2x *bp = params->bp;
 252
 253         additional_config =
 254                 REG_RD(bp, params->lfa_base +
 255                            offsetof(struct shmem_lfa, additional_config));
 256
 257         /* NOTE: must be first condition checked -
 258         * to verify DCC bit is cleared in any case!
 259         */
 260         if (additional_config & NO_LFA_DUE_TO_DCC_MASK) {
 261                 DP(NETIF_MSG_LINK, "No LFA due to DCC flap after clp exit\n");
 262                 REG_WR(bp, params->lfa_base +
 263                            offsetof(struct shmem_lfa, additional_config),
 264                        additional_config & ~NO_LFA_DUE_TO_DCC_MASK);
 265                 return LFA_DCC_LFA_DISABLED;
 266         }
 267
 268         /* Verify that link is up */
 269         link_status = REG_RD(bp, params->shmem_base +
 270                              offsetof(struct shmem_region,
 271                                       port_mb[params->port].link_status));
 272         if (!(link_status & LINK_STATUS_LINK_UP))
 273                 return LFA_LINK_DOWN;
 274
 275         /* if loaded after BOOT from SAN, don't flap the link in any case and
 276          * rely on link set by preboot driver
 277          */
 278         if (params->feature_config_flags & FEATURE_CONFIG_BOOT_FROM_SAN)
 279                 return 0;
 280
 281         /* Verify that loopback mode is not set */
 282         if (params->loopback_mode)
 283                 return LFA_LOOPBACK_ENABLED;
 284
 285         /* Verify that MFW supports LFA */
 286         if (!params->lfa_base)
 287                 return LFA_MFW_IS_TOO_OLD;
 288
 289         if (params->num_phys == 3) {
 290                 cfg_size = 2;
 291                 lfa_mask = 0xffffffff;
 292         } else {
 293                 cfg_size = 1;
 294                 lfa_mask = 0xffff;
 295         }
 296
 297         /* Compare Duplex */
 298         saved_val = REG_RD(bp, params->lfa_base +
 299                            offsetof(struct shmem_lfa, req_duplex));
 300         req_val = params->req_duplex[0] | (params->req_duplex[1] << 16);
 301         if ((saved_val & lfa_mask) != (req_val & lfa_mask)) {
 302                 DP(NETIF_MSG_LINK, "Duplex mismatch %x vs. %x\n",
 303                                (saved_val & lfa_mask), (req_val & lfa_mask));
 304                 return LFA_DUPLEX_MISMATCH;
 305         }
 306         /* Compare Flow Control */
 307         saved_val = REG_RD(bp, params->lfa_base +
 308                            offsetof(struct shmem_lfa, req_flow_ctrl));
 309         req_val = params->req_flow_ctrl[0] | (params->req_flow_ctrl[1] << 16);
 310         if ((saved_val & lfa_mask) != (req_val & lfa_mask)) {
 311                 DP(NETIF_MSG_LINK, "Flow control mismatch %x vs. %x\n",
 312                                (saved_val & lfa_mask), (req_val & lfa_mask));
 313                 return LFA_FLOW_CTRL_MISMATCH;
 314         }
 315         /* Compare Link Speed */
 316         saved_val = REG_RD(bp, params->lfa_base +
 317                            offsetof(struct shmem_lfa, req_line_speed));
 318         req_val = params->req_line_speed[0] | (params->req_line_speed[1] << 16);
 319         if ((saved_val & lfa_mask) != (req_val & lfa_mask)) {
 320                 DP(NETIF_MSG_LINK, "Link speed mismatch %x vs. %x\n",
 321                                (saved_val & lfa_mask), (req_val & lfa_mask));
 322                 return LFA_LINK_SPEED_MISMATCH;
 323         }
 324
 325         for (cfg_idx = 0; cfg_idx < cfg_size; cfg_idx++) {
 326                 cur_speed_cap_mask = REG_RD(bp, params->lfa_base +
 327                                             offsetof(struct shmem_lfa,
 328                                                      speed_cap_mask[cfg_idx]));
 329
 330                 if (cur_speed_cap_mask != params->speed_cap_mask[cfg_idx]) {
 331                         DP(NETIF_MSG_LINK, "Speed Cap mismatch %x vs. %x\n",
 332                                        cur_speed_cap_mask,
 333                                        params->speed_cap_mask[cfg_idx]);
 334                         return LFA_SPEED_CAP_MISMATCH;
 335                 }
 336         }
 337
 338         cur_req_fc_auto_adv =
 339                 REG_RD(bp, params->lfa_base +
 340                        offsetof(struct shmem_lfa, additional_config)) &
 341                 REQ_FC_AUTO_ADV_MASK;
 342
 343         if ((u16)cur_req_fc_auto_adv != params->req_fc_auto_adv) {
 344                 DP(NETIF_MSG_LINK, "Flow Ctrl AN mismatch %x vs. %x\n",
 345                                cur_req_fc_auto_adv, params->req_fc_auto_adv);
 346                 return LFA_FLOW_CTRL_MISMATCH;
 347         }
 348
 349         eee_status = REG_RD(bp, params->shmem2_base +
 350                             offsetof(struct shmem2_region,
 351                                      eee_status[params->port]));
 352
 353         if (((eee_status & SHMEM_EEE_LPI_REQUESTED_BIT) ^
 354              (params->eee_mode & EEE_MODE_ENABLE_LPI)) ||
 355             ((eee_status & SHMEM_EEE_REQUESTED_BIT) ^
 356              (params->eee_mode & EEE_MODE_ADV_LPI))) {
 357                 DP(NETIF_MSG_LINK, "EEE mismatch %x vs. %x\n", params->eee_mode,
 358                                eee_status);
 359                 return LFA_EEE_MISMATCH;
 360         }
 361
 362         /* LFA conditions are met */
 363         return 0;
 364 }
 365 /******************************************************************/
 366 /*                      EPIO/GPIO section                         */
 367 /******************************************************************/
 368 static void bnx2x_get_epio(struct bnx2x *bp, u32 epio_pin, u32 *en)
 369 {
 370         u32 epio_mask, gp_oenable;
 371         *en = 0;
 372         /* Sanity check */
 373         if (epio_pin > 31) {
 374                 DP(NETIF_MSG_LINK, "Invalid EPIO pin %d to get\n", epio_pin);
 375                 return;
 376         }
 377
 378         epio_mask = 1 << epio_pin;
 379         /* Set this EPIO to output */
 380         gp_oenable = REG_RD(bp, MCP_REG_MCPR_GP_OENABLE);
 381         REG_WR(bp, MCP_REG_MCPR_GP_OENABLE, gp_oenable & ~epio_mask);
 382
 383         *en = (REG_RD(bp, MCP_REG_MCPR_GP_INPUTS) & epio_mask) >> epio_pin;
 384 }
 385 static void bnx2x_set_epio(struct bnx2x *bp, u32 epio_pin, u32 en)
 386 {
 387         u32 epio_mask, gp_output, gp_oenable;
 388
 389         /* Sanity check */
 390         if (epio_pin > 31) {
 391                 DP(NETIF_MSG_LINK, "Invalid EPIO pin %d to set\n", epio_pin);
 392                 return;
 393         }
 394         DP(NETIF_MSG_LINK, "Setting EPIO pin %d to %d\n", epio_pin, en);
 395         epio_mask = 1 << epio_pin;
 396         /* Set this EPIO to output */
 397         gp_output = REG_RD(bp, MCP_REG_MCPR_GP_OUTPUTS);
 398         if (en)
 399                 gp_output |= epio_mask;
 400         else
 401                 gp_output &= ~epio_mask;
 402
 403         REG_WR(bp, MCP_REG_MCPR_GP_OUTPUTS, gp_output);
 404
 405         /* Set the value for this EPIO */
 406         gp_oenable = REG_RD(bp, MCP_REG_MCPR_GP_OENABLE);
 407         REG_WR(bp, MCP_REG_MCPR_GP_OENABLE, gp_oenable | epio_mask);
 408 }
 409
 410 static void bnx2x_set_cfg_pin(struct bnx2x *bp, u32 pin_cfg, u32 val)
 411 {
 412         if (pin_cfg == PIN_CFG_NA)
 413                 return;
 414         if (pin_cfg >= PIN_CFG_EPIO0) {
 415                 bnx2x_set_epio(bp, pin_cfg - PIN_CFG_EPIO0, val);
 416         } else {
 417                 u8 gpio_num = (pin_cfg - PIN_CFG_GPIO0_P0) & 0x3;
 418                 u8 gpio_port = (pin_cfg - PIN_CFG_GPIO0_P0) >> 2;
 419                 bnx2x_set_gpio(bp, gpio_num, (u8)val, gpio_port);
 420         }
 421 }
 422
 423 static u32 bnx2x_get_cfg_pin(struct bnx2x *bp, u32 pin_cfg, u32 *val)
 424 {
 425         if (pin_cfg == PIN_CFG_NA)
 426                 return -EINVAL;
 427         if (pin_cfg >= PIN_CFG_EPIO0) {
 428                 bnx2x_get_epio(bp, pin_cfg - PIN_CFG_EPIO0, val);
 429         } else {
 430                 u8 gpio_num = (pin_cfg - PIN_CFG_GPIO0_P0) & 0x3;
 431                 u8 gpio_port = (pin_cfg - PIN_CFG_GPIO0_P0) >> 2;
 432                 *val = bnx2x_get_gpio(bp, gpio_num, gpio_port);
 433         }
 434         return 0;
 435
 436 }
 437 /******************************************************************/
 438 /*                              ETS section                       */
 439 /******************************************************************/
 440 static void bnx2x_ets_e2e3a0_disabled(struct link_params *params)
 441 {
 442         /* ETS disabled configuration*/
 443         struct bnx2x *bp = params->bp;
 444
 445         DP(NETIF_MSG_LINK, "ETS E2E3 disabled configuration\n");
 446
 447         /* mapping between entry  priority to client number (0,1,2 -debug and
 448          * management clients, 3 - COS0 client, 4 - COS client)(HIGHEST)
 449          * 3bits client num.
 450          *   PRI4    |    PRI3    |    PRI2    |    PRI1    |    PRI0
 451          * cos1-100     cos0-011     dbg1-010     dbg0-001     MCP-000
 452          */
 453
 454         REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT, 0x4688);
 455         /* Bitmap of 5bits length. Each bit specifies whether the entry behaves
 456          * as strict.  Bits 0,1,2 - debug and management entries, 3 -
 457          * COS0 entry, 4 - COS1 entry.
 458          * COS1 | COS0 | DEBUG1 | DEBUG0 | MGMT
 459          * bit4   bit3    bit2   bit1     bit0
 460          * MCP and debug are strict
 461          */
 462
 463         REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x7);
 464         /* defines which entries (clients) are subjected to WFQ arbitration */
 465         REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0);
 466         /* For strict priority entries defines the number of consecutive
 467          * slots for the highest priority.
 468          */
 469         REG_WR(bp, NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100);
 470         /* mapping between the CREDIT_WEIGHT registers and actual client
 471          * numbers
 472          */
 473         REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP, 0);
 474         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, 0);
 475         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, 0);
 476
 477         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0, 0);
 478         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1, 0);
 479         REG_WR(bp, PBF_REG_HIGH_PRIORITY_COS_NUM, 0);
 480         /* ETS mode disable */
 481         REG_WR(bp, PBF_REG_ETS_ENABLED, 0);
 482         /* If ETS mode is enabled (there is no strict priority) defines a WFQ
 483          * weight for COS0/COS1.
 484          */
 485         REG_WR(bp, PBF_REG_COS0_WEIGHT, 0x2710);
 486         REG_WR(bp, PBF_REG_COS1_WEIGHT, 0x2710);
 487         /* Upper bound that COS0_WEIGHT can reach in the WFQ arbiter */
 488         REG_WR(bp, PBF_REG_COS0_UPPER_BOUND, 0x989680);
 489         REG_WR(bp, PBF_REG_COS1_UPPER_BOUND, 0x989680);
 490         /* Defines the number of consecutive slots for the strict priority */
 491         REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0);
 492 }
 493 /******************************************************************************
 494 * Description:
 495 *       Getting min_w_val will be set according to line speed .
 496 *.
 497 ******************************************************************************/
 498 static u32 bnx2x_ets_get_min_w_val_nig(const struct link_vars *vars)
 499 {
 500         u32 min_w_val = 0;
 501         /* Calculate min_w_val.*/
 502         if (vars->link_up) {
 503                 if (vars->line_speed == SPEED_20000)
 504                         min_w_val = ETS_E3B0_NIG_MIN_W_VAL_20GBPS;
 505                 else
 506                         min_w_val = ETS_E3B0_NIG_MIN_W_VAL_UP_TO_10GBPS;
 507         } else
 508                 min_w_val = ETS_E3B0_NIG_MIN_W_VAL_20GBPS;
 509         /* If the link isn't up (static configuration for example ) The
 510          * link will be according to 20GBPS.
 511          */
 512         return min_w_val;
 513 }
 514 /******************************************************************************
 515 * Description:
 516 *       Getting credit upper bound form min_w_val.
 517 *.
 518 ******************************************************************************/
 519 static u32 bnx2x_ets_get_credit_upper_bound(const u32 min_w_val)
 520 {
 521         const u32 credit_upper_bound = (u32)MAXVAL((150 * min_w_val),
 522                                                 MAX_PACKET_SIZE);
 523         return credit_upper_bound;
 524 }
 525 /******************************************************************************
 526 * Description:
 527 *       Set credit upper bound for NIG.
 528 *.
 529 ******************************************************************************/
 530 static void bnx2x_ets_e3b0_set_credit_upper_bound_nig(
 531         const struct link_params *params,
 532         const u32 min_w_val)
 533 {
 534         struct bnx2x *bp = params->bp;
 535         const u8 port = params->port;
 536         const u32 credit_upper_bound =
 537             bnx2x_ets_get_credit_upper_bound(min_w_val);
 538
 539         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_0 :
 540                 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0, credit_upper_bound);
 541         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_1 :
 542                    NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1, credit_upper_bound);
 543         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_2 :
 544                    NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_2, credit_upper_bound);
 545         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_3 :
 546                    NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_3, credit_upper_bound);
 547         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_4 :
 548                    NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_4, credit_upper_bound);
 549         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_5 :
 550                    NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_5, credit_upper_bound);
 551
 552         if (!port) {
 553                 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_6,
 554                         credit_upper_bound);
 555                 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_7,
 556                         credit_upper_bound);
 557                 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_8,
 558                         credit_upper_bound);
 559         }
 560 }
 561 /******************************************************************************
 562 * Description:
 563 *       Will return the NIG ETS registers to init values.Except
 564 *       credit_upper_bound.
 565 *       That isn't used in this configuration (No WFQ is enabled) and will be
 566 *       configured according to spec
 567 *.
 568 ******************************************************************************/
 569 static void bnx2x_ets_e3b0_nig_disabled(const struct link_params *params,
 570                                         const struct link_vars *vars)
 571 {
 572         struct bnx2x *bp = params->bp;
 573         const u8 port = params->port;
 574         const u32 min_w_val = bnx2x_ets_get_min_w_val_nig(vars);
 575         /* Mapping between entry  priority to client number (0,1,2 -debug and
 576          * management clients, 3 - COS0 client, 4 - COS1, ... 8 -
 577          * COS5)(HIGHEST) 4bits client num.TODO_ETS - Should be done by
 578          * reset value or init tool
 579          */
 580         if (port) {
 581                 REG_WR(bp, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_LSB, 0x543210);
 582                 REG_WR(bp, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_MSB, 0x0);
 583         } else {
 584                 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_LSB, 0x76543210);
 585                 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_MSB, 0x8);
 586         }
 587         /* For strict priority entries defines the number of consecutive
 588          * slots for the highest priority.
 589          */
 590         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_NUM_STRICT_ARB_SLOTS :
 591                    NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100);
 592         /* Mapping between the CREDIT_WEIGHT registers and actual client
 593          * numbers
 594          */
 595         if (port) {
 596                 /*Port 1 has 6 COS*/
 597                 REG_WR(bp, NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_LSB, 0x210543);
 598                 REG_WR(bp, NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_MSB, 0x0);
 599         } else {
 600                 /*Port 0 has 9 COS*/
 601                 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_LSB,
 602                        0x43210876);
 603                 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_MSB, 0x5);
 604         }
 605
 606         /* Bitmap of 5bits length. Each bit specifies whether the entry behaves
 607          * as strict.  Bits 0,1,2 - debug and management entries, 3 -
 608          * COS0 entry, 4 - COS1 entry.
 609          * COS1 | COS0 | DEBUG1 | DEBUG0 | MGMT
 610          * bit4   bit3    bit2   bit1     bit0
 611          * MCP and debug are strict
 612          */
 613         if (port)
 614                 REG_WR(bp, NIG_REG_P1_TX_ARB_CLIENT_IS_STRICT, 0x3f);
 615         else
 616                 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x1ff);
 617         /* defines which entries (clients) are subjected to WFQ arbitration */
 618         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_SUBJECT2WFQ :
 619                    NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0);
 620
 621         /* Please notice the register address are note continuous and a
 622          * for here is note appropriate.In 2 port mode port0 only COS0-5
 623          * can be used. DEBUG1,DEBUG1,MGMT are never used for WFQ* In 4
 624          * port mode port1 only COS0-2 can be used. DEBUG1,DEBUG1,MGMT
 625          * are never used for WFQ
 626          */
 627         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_0 :
 628                    NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, 0x0);
 629         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_1 :
 630                    NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, 0x0);
 631         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_2 :
 632                    NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_2, 0x0);
 633         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_3 :
 634                    NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_3, 0x0);
 635         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_4 :
 636                    NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_4, 0x0);
 637         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_5 :
 638                    NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_5, 0x0);
 639         if (!port) {
 640                 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_6, 0x0);
 641                 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_7, 0x0);
 642                 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_8, 0x0);
 643         }
 644
 645         bnx2x_ets_e3b0_set_credit_upper_bound_nig(params, min_w_val);
 646 }
 647 /******************************************************************************
 648 * Description:
 649 *       Set credit upper bound for PBF.
 650 *.
 651 ******************************************************************************/
 652 static void bnx2x_ets_e3b0_set_credit_upper_bound_pbf(
 653         const struct link_params *params,
 654         const u32 min_w_val)
 655 {
 656         struct bnx2x *bp = params->bp;
 657         const u32 credit_upper_bound =
 658             bnx2x_ets_get_credit_upper_bound(min_w_val);
 659         const u8 port = params->port;
 660         u32 base_upper_bound = 0;
 661         u8 max_cos = 0;
 662         u8 i = 0;
 663         /* In 2 port mode port0 has COS0-5 that can be used for WFQ.In 4
 664          * port mode port1 has COS0-2 that can be used for WFQ.
 665          */
 666         if (!port) {
 667                 base_upper_bound = PBF_REG_COS0_UPPER_BOUND_P0;
 668                 max_cos = DCBX_E3B0_MAX_NUM_COS_PORT0;
 669         } else {
 670                 base_upper_bound = PBF_REG_COS0_UPPER_BOUND_P1;
 671                 max_cos = DCBX_E3B0_MAX_NUM_COS_PORT1;
 672         }
 673
 674         for (i = 0; i < max_cos; i++)
 675                 REG_WR(bp, base_upper_bound + (i << 2), credit_upper_bound);
 676 }
 677
 678 /******************************************************************************
 679 * Description:
 680 *       Will return the PBF ETS registers to init values.Except
 681 *       credit_upper_bound.
 682 *       That isn't used in this configuration (No WFQ is enabled) and will be
 683 *       configured according to spec
 684 *.
 685 ******************************************************************************/
 686 static void bnx2x_ets_e3b0_pbf_disabled(const struct link_params *params)
 687 {
 688         struct bnx2x *bp = params->bp;
 689         const u8 port = params->port;
 690         const u32 min_w_val_pbf = ETS_E3B0_PBF_MIN_W_VAL;
 691         u8 i = 0;
 692         u32 base_weight = 0;
 693         u8 max_cos = 0;
 694
 695         /* Mapping between entry  priority to client number 0 - COS0
 696          * client, 2 - COS1, ... 5 - COS5)(HIGHEST) 4bits client num.
 697          * TODO_ETS - Should be done by reset value or init tool
 698          */
 699         if (port)
 700                 /*  0x688 (|011|0 10|00 1|000) */
 701                 REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P1 , 0x688);
 702         else
 703                 /*  (10 1|100 |011|0 10|00 1|000) */
 704                 REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P0 , 0x2C688);
 705
 706         /* TODO_ETS - Should be done by reset value or init tool */
 707         if (port)
 708                 /* 0x688 (|011|0 10|00 1|000)*/
 709                 REG_WR(bp, PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P1, 0x688);
 710         else
 711         /* 0x2C688 (10 1|100 |011|0 10|00 1|000) */
 712         REG_WR(bp, PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P0, 0x2C688);
 713
 714         REG_WR(bp, (port) ? PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P1 :
 715                    PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P0 , 0x100);
 716
 717
 718         REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P1 :
 719                    PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P0 , 0);
 720
 721         REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P1 :
 722                    PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P0 , 0);
 723         /* In 2 port mode port0 has COS0-5 that can be used for WFQ.
 724          * In 4 port mode port1 has COS0-2 that can be used for WFQ.
 725          */
 726         if (!port) {
 727                 base_weight = PBF_REG_COS0_WEIGHT_P0;
 728                 max_cos = DCBX_E3B0_MAX_NUM_COS_PORT0;
 729         } else {
 730                 base_weight = PBF_REG_COS0_WEIGHT_P1;
 731                 max_cos = DCBX_E3B0_MAX_NUM_COS_PORT1;
 732         }
 733
 734         for (i = 0; i < max_cos; i++)
 735                 REG_WR(bp, base_weight + (0x4 * i), 0);
 736
 737         bnx2x_ets_e3b0_set_credit_upper_bound_pbf(params, min_w_val_pbf);
 738 }
 739 /******************************************************************************
 740 * Description:
 741 *       E3B0 disable will return basically the values to init values.
 742 *.
 743 ******************************************************************************/
 744 static int bnx2x_ets_e3b0_disabled(const struct link_params *params,
 745                                    const struct link_vars *vars)
 746 {
 747         struct bnx2x *bp = params->bp;
 748
 749         if (!CHIP_IS_E3B0(bp)) {
 750                 DP(NETIF_MSG_LINK,
 751                    "bnx2x_ets_e3b0_disabled the chip isn't E3B0\n");
 752                 return -EINVAL;
 753         }
 754
 755         bnx2x_ets_e3b0_nig_disabled(params, vars);
 756
 757         bnx2x_ets_e3b0_pbf_disabled(params);
 758
 759         return 0;
 760 }
 761
 762 /******************************************************************************
 763 * Description:
 764 *       Disable will return basically the values to init values.
 765 *
 766 ******************************************************************************/
 767 int bnx2x_ets_disabled(struct link_params *params,
 768                       struct link_vars *vars)
 769 {
 770         struct bnx2x *bp = params->bp;
 771         int bnx2x_status = 0;
 772
 773         if ((CHIP_IS_E2(bp)) || (CHIP_IS_E3A0(bp)))
 774                 bnx2x_ets_e2e3a0_disabled(params);
 775         else if (CHIP_IS_E3B0(bp))
 776                 bnx2x_status = bnx2x_ets_e3b0_disabled(params, vars);
 777         else {
 778                 DP(NETIF_MSG_LINK, "bnx2x_ets_disabled - chip not supported\n");
 779                 return -EINVAL;
 780         }
 781
 782         return bnx2x_status;
 783 }
 784
 785 /******************************************************************************
 786 * Description
 787 *       Set the COS mappimg to SP and BW until this point all the COS are not
 788 *       set as SP or BW.
 789 ******************************************************************************/
 790 static int bnx2x_ets_e3b0_cli_map(const struct link_params *params,
 791                                   const struct bnx2x_ets_params *ets_params,
 792                                   const u8 cos_sp_bitmap,
 793                                   const u8 cos_bw_bitmap)
 794 {
 795         struct bnx2x *bp = params->bp;
 796         const u8 port = params->port;
 797         const u8 nig_cli_sp_bitmap = 0x7 | (cos_sp_bitmap << 3);
 798         const u8 pbf_cli_sp_bitmap = cos_sp_bitmap;
 799         const u8 nig_cli_subject2wfq_bitmap = cos_bw_bitmap << 3;
 800         const u8 pbf_cli_subject2wfq_bitmap = cos_bw_bitmap;
 801
 802         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_STRICT :
 803                NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, nig_cli_sp_bitmap);
 804
 805         REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P1 :
 806                PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P0 , pbf_cli_sp_bitmap);
 807
 808         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_SUBJECT2WFQ :
 809                NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ,
 810                nig_cli_subject2wfq_bitmap);
 811
 812         REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P1 :
 813                PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P0,
 814                pbf_cli_subject2wfq_bitmap);
 815
 816         return 0;
 817 }
 818
 819 /******************************************************************************
 820 * Description:
 821 *       This function is needed because NIG ARB_CREDIT_WEIGHT_X are
 822 *       not continues and ARB_CREDIT_WEIGHT_0 + offset is suitable.
 823 ******************************************************************************/
 824 static int bnx2x_ets_e3b0_set_cos_bw(struct bnx2x *bp,
 825                                      const u8 cos_entry,
 826                                      const u32 min_w_val_nig,
 827                                      const u32 min_w_val_pbf,
 828                                      const u16 total_bw,
 829                                      const u8 bw,
 830                                      const u8 port)
 831 {
 832         u32 nig_reg_adress_crd_weight = 0;
 833         u32 pbf_reg_adress_crd_weight = 0;
 834         /* Calculate and set BW for this COS - use 1 instead of 0 for BW */
 835         const u32 cos_bw_nig = ((bw ? bw : 1) * min_w_val_nig) / total_bw;
 836         const u32 cos_bw_pbf = ((bw ? bw : 1) * min_w_val_pbf) / total_bw;
 837
 838         switch (cos_entry) {
 839         case 0:
 840                 nig_reg_adress_crd_weight =
 841                         (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_0 :
 842                         NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0;
 843                 pbf_reg_adress_crd_weight = (port) ?
 844                     PBF_REG_COS0_WEIGHT_P1 : PBF_REG_COS0_WEIGHT_P0;
 845                 break;
 846         case 1:
 847                 nig_reg_adress_crd_weight = (port) ?
 848                         NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_1 :
 849                         NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1;
 850                 pbf_reg_adress_crd_weight = (port) ?
 851                         PBF_REG_COS1_WEIGHT_P1 : PBF_REG_COS1_WEIGHT_P0;
 852                 break;
 853         case 2:
 854                 nig_reg_adress_crd_weight = (port) ?
 855                         NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_2 :
 856                         NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_2;
 857
 858                 pbf_reg_adress_crd_weight = (port) ?
 859                         PBF_REG_COS2_WEIGHT_P1 : PBF_REG_COS2_WEIGHT_P0;
 860                 break;
 861         case 3:
 862                 if (port)
 863                         return -EINVAL;
 864                 nig_reg_adress_crd_weight = NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_3;
 865                 pbf_reg_adress_crd_weight = PBF_REG_COS3_WEIGHT_P0;
 866                 break;
 867         case 4:
 868                 if (port)
 869                         return -EINVAL;
 870                 nig_reg_adress_crd_weight = NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_4;
 871                 pbf_reg_adress_crd_weight = PBF_REG_COS4_WEIGHT_P0;
 872                 break;
 873         case 5:
 874                 if (port)
 875                         return -EINVAL;
 876                 nig_reg_adress_crd_weight = NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_5;
 877                 pbf_reg_adress_crd_weight = PBF_REG_COS5_WEIGHT_P0;
 878                 break;
 879         }
 880
 881         REG_WR(bp, nig_reg_adress_crd_weight, cos_bw_nig);
 882
 883         REG_WR(bp, pbf_reg_adress_crd_weight, cos_bw_pbf);
 884
 885         return 0;
 886 }
 887 /******************************************************************************
 888 * Description:
 889 *       Calculate the total BW.A value of 0 isn't legal.
 890 *
 891 ******************************************************************************/
 892 static int bnx2x_ets_e3b0_get_total_bw(
 893         const struct link_params *params,
 894         struct bnx2x_ets_params *ets_params,
 895         u16 *total_bw)
 896 {
 897         struct bnx2x *bp = params->bp;
 898         u8 cos_idx = 0;
 899         u8 is_bw_cos_exist = 0;
 900
 901         *total_bw = 0 ;
 902         /* Calculate total BW requested */
 903         for (cos_idx = 0; cos_idx < ets_params->num_of_cos; cos_idx++) {
 904                 if (ets_params->cos[cos_idx].state == bnx2x_cos_state_bw) {
 905                         is_bw_cos_exist = 1;
 906                         if (!ets_params->cos[cos_idx].params.bw_params.bw) {
 907                                 DP(NETIF_MSG_LINK, "bnx2x_ets_E3B0_config BW"
 908                                                    "was set to 0\n");
 909                                 /* This is to prevent a state when ramrods
 910                                  * can't be sent
 911                                  */
 912                                 ets_params->cos[cos_idx].params.bw_params.bw
 913                                          = 1;
 914                         }
 915                         *total_bw +=
 916                                 ets_params->cos[cos_idx].params.bw_params.bw;
 917                 }
 918         }
 919
 920         /* Check total BW is valid */
 921         if ((is_bw_cos_exist == 1) && (*total_bw != 100)) {
 922                 if (*total_bw == 0) {
 923                         DP(NETIF_MSG_LINK,
 924                            "bnx2x_ets_E3B0_config total BW shouldn't be 0\n");
 925                         return -EINVAL;
 926                 }
 927                 DP(NETIF_MSG_LINK,
 928                    "bnx2x_ets_E3B0_config total BW should be 100\n");
 929                 /* We can handle a case whre the BW isn't 100 this can happen
 930                  * if the TC are joined.
 931                  */
 932         }
 933         return 0;
 934 }
 935
 936 /******************************************************************************
 937 * Description:
 938 *       Invalidate all the sp_pri_to_cos.
 939 *
 940 ******************************************************************************/
 941 static void bnx2x_ets_e3b0_sp_pri_to_cos_init(u8 *sp_pri_to_cos)
 942 {
 943         u8 pri = 0;
 944         for (pri = 0; pri < DCBX_MAX_NUM_COS; pri++)
 945                 sp_pri_to_cos[pri] = DCBX_INVALID_COS;
 946 }
 947 /******************************************************************************
 948 * Description:
 949 *       Calculate and set the SP (ARB_PRIORITY_CLIENT) NIG and PBF registers
 950 *       according to sp_pri_to_cos.
 951 *
 952 ******************************************************************************/
 953 static int bnx2x_ets_e3b0_sp_pri_to_cos_set(const struct link_params *params,
 954                                             u8 *sp_pri_to_cos, const u8 pri,
 955                                             const u8 cos_entry)
 956 {
 957         struct bnx2x *bp = params->bp;
 958         const u8 port = params->port;
 959         const u8 max_num_of_cos = (port) ? DCBX_E3B0_MAX_NUM_COS_PORT1 :
 960                 DCBX_E3B0_MAX_NUM_COS_PORT0;
 961
 962         if (pri >= max_num_of_cos) {
 963                 DP(NETIF_MSG_LINK, "bnx2x_ets_e3b0_sp_pri_to_cos_set invalid "
 964                    "parameter Illegal strict priority\n");
 965                 return -EINVAL;
 966         }
 967
 968         if (sp_pri_to_cos[pri] != DCBX_INVALID_COS) {
 969                 DP(NETIF_MSG_LINK, "bnx2x_ets_e3b0_sp_pri_to_cos_set invalid "
 970                                    "parameter There can't be two COS's with "
 971                                    "the same strict pri\n");
 972                 return -EINVAL;
 973         }
 974
 975         sp_pri_to_cos[pri] = cos_entry;
 976         return 0;
 977
 978 }
 979
 980 /******************************************************************************
 981 * Description:
 982 *       Returns the correct value according to COS and priority in
 983 *       the sp_pri_cli register.
 984 *
 985 ******************************************************************************/
 986 static u64 bnx2x_e3b0_sp_get_pri_cli_reg(const u8 cos, const u8 cos_offset,
 987                                          const u8 pri_set,
 988                                          const u8 pri_offset,
 989                                          const u8 entry_size)
 990 {
 991         u64 pri_cli_nig = 0;
 992         pri_cli_nig = ((u64)(cos + cos_offset)) << (entry_size *
 993                                                     (pri_set + pri_offset));
 994
 995         return pri_cli_nig;
 996 }
 997 /******************************************************************************
 998 * Description:
 999 *       Returns the correct value according to COS and priority in the
1000 *       sp_pri_cli register for NIG.
1001 *
1002 ******************************************************************************/
1003 static u64 bnx2x_e3b0_sp_get_pri_cli_reg_nig(const u8 cos, const u8 pri_set)
1004 {
1005         /* MCP Dbg0 and dbg1 are always with higher strict pri*/
1006         const u8 nig_cos_offset = 3;
1007         const u8 nig_pri_offset = 3;
1008
1009         return bnx2x_e3b0_sp_get_pri_cli_reg(cos, nig_cos_offset, pri_set,
1010                 nig_pri_offset, 4);
1011
1012 }
1013 /******************************************************************************
1014 * Description:
1015 *       Returns the correct value according to COS and priority in the
1016 *       sp_pri_cli register for PBF.
1017 *
1018 ******************************************************************************/
1019 static u64 bnx2x_e3b0_sp_get_pri_cli_reg_pbf(const u8 cos, const u8 pri_set)
1020 {
1021         const u8 pbf_cos_offset = 0;
1022         const u8 pbf_pri_offset = 0;
1023
1024         return bnx2x_e3b0_sp_get_pri_cli_reg(cos, pbf_cos_offset, pri_set,
1025                 pbf_pri_offset, 3);
1026
1027 }
1028
1029 /******************************************************************************
1030 * Description:
1031 *       Calculate and set the SP (ARB_PRIORITY_CLIENT) NIG and PBF registers
1032 *       according to sp_pri_to_cos.(which COS has higher priority)
1033 *
1034 ******************************************************************************/
1035 static int bnx2x_ets_e3b0_sp_set_pri_cli_reg(const struct link_params *params,
1036                                              u8 *sp_pri_to_cos)
1037 {
1038         struct bnx2x *bp = params->bp;
1039         u8 i = 0;
1040         const u8 port = params->port;
1041         /* MCP Dbg0 and dbg1 are always with higher strict pri*/
1042         u64 pri_cli_nig = 0x210;
1043         u32 pri_cli_pbf = 0x0;
1044         u8 pri_set = 0;
1045         u8 pri_bitmask = 0;
1046         const u8 max_num_of_cos = (port) ? DCBX_E3B0_MAX_NUM_COS_PORT1 :
1047                 DCBX_E3B0_MAX_NUM_COS_PORT0;
1048
1049         u8 cos_bit_to_set = (1 << max_num_of_cos) - 1;
1050
1051         /* Set all the strict priority first */
1052         for (i = 0; i < max_num_of_cos; i++) {
1053                 if (sp_pri_to_cos[i] != DCBX_INVALID_COS) {
1054                         if (sp_pri_to_cos[i] >= DCBX_MAX_NUM_COS) {
1055                                 DP(NETIF_MSG_LINK,
1056                                            "bnx2x_ets_e3b0_sp_set_pri_cli_reg "
1057                                            "invalid cos entry\n");
1058                                 return -EINVAL;
1059                         }
1060
1061                         pri_cli_nig |= bnx2x_e3b0_sp_get_pri_cli_reg_nig(
1062                             sp_pri_to_cos[i], pri_set);
1063
1064                         pri_cli_pbf |= bnx2x_e3b0_sp_get_pri_cli_reg_pbf(
1065                             sp_pri_to_cos[i], pri_set);
1066                         pri_bitmask = 1 << sp_pri_to_cos[i];
1067                         /* COS is used remove it from bitmap.*/
1068                         if (!(pri_bitmask & cos_bit_to_set)) {
1069                                 DP(NETIF_MSG_LINK,
1070                                         "bnx2x_ets_e3b0_sp_set_pri_cli_reg "
1071                                         "invalid There can't be two COS's with"
1072                                         " the same strict pri\n");
1073                                 return -EINVAL;
1074                         }
1075                         cos_bit_to_set &= ~pri_bitmask;
1076                         pri_set++;
1077                 }
1078         }
1079
1080         /* Set all the Non strict priority i= COS*/
1081         for (i = 0; i < max_num_of_cos; i++) {
1082                 pri_bitmask = 1 << i;
1083                 /* Check if COS was already used for SP */
1084                 if (pri_bitmask & cos_bit_to_set) {
1085                         /* COS wasn't used for SP */
1086                         pri_cli_nig |= bnx2x_e3b0_sp_get_pri_cli_reg_nig(
1087                             i, pri_set);
1088
1089                         pri_cli_pbf |= bnx2x_e3b0_sp_get_pri_cli_reg_pbf(
1090                             i, pri_set);
1091                         /* COS is used remove it from bitmap.*/
1092                         cos_bit_to_set &= ~pri_bitmask;
1093                         pri_set++;
1094                 }
1095         }
1096
1097         if (pri_set != max_num_of_cos) {
1098                 DP(NETIF_MSG_LINK, "bnx2x_ets_e3b0_sp_set_pri_cli_reg not all "
1099                                    "entries were set\n");
1100                 return -EINVAL;
1101         }
1102
1103         if (port) {
1104                 /* Only 6 usable clients*/
1105                 REG_WR(bp, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_LSB,
1106                        (u32)pri_cli_nig);
1107
1108                 REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P1 , pri_cli_pbf);
1109         } else {
1110                 /* Only 9 usable clients*/
1111                 const u32 pri_cli_nig_lsb = (u32) (pri_cli_nig);
1112                 const u32 pri_cli_nig_msb = (u32) ((pri_cli_nig >> 32) & 0xF);
1113
1114                 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_LSB,
1115                        pri_cli_nig_lsb);
1116                 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_MSB,
1117                        pri_cli_nig_msb);
1118
1119                 REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P0 , pri_cli_pbf);
1120         }
1121         return 0;
1122 }
1123
1124 /******************************************************************************
1125 * Description:
1126 *       Configure the COS to ETS according to BW and SP settings.
1127 ******************************************************************************/
1128 int bnx2x_ets_e3b0_config(const struct link_params *params,
1129                          const struct link_vars *vars,
1130                          struct bnx2x_ets_params *ets_params)
1131 {
1132         struct bnx2x *bp = params->bp;
1133         int bnx2x_status = 0;
1134         const u8 port = params->port;
1135         u16 total_bw = 0;
1136         const u32 min_w_val_nig = bnx2x_ets_get_min_w_val_nig(vars);
1137         const u32 min_w_val_pbf = ETS_E3B0_PBF_MIN_W_VAL;
1138         u8 cos_bw_bitmap = 0;
1139         u8 cos_sp_bitmap = 0;
1140         u8 sp_pri_to_cos[DCBX_MAX_NUM_COS] = {0};
1141         const u8 max_num_of_cos = (port) ? DCBX_E3B0_MAX_NUM_COS_PORT1 :
1142                 DCBX_E3B0_MAX_NUM_COS_PORT0;
1143         u8 cos_entry = 0;
1144
1145         if (!CHIP_IS_E3B0(bp)) {
1146                 DP(NETIF_MSG_LINK,
1147                    "bnx2x_ets_e3b0_disabled the chip isn't E3B0\n");
1148                 return -EINVAL;
1149         }
1150
1151         if ((ets_params->num_of_cos > max_num_of_cos)) {
1152                 DP(NETIF_MSG_LINK, "bnx2x_ets_E3B0_config the number of COS "
1153                                    "isn't supported\n");
1154                 return -EINVAL;
1155         }
1156
1157         /* Prepare sp strict priority parameters*/
1158         bnx2x_ets_e3b0_sp_pri_to_cos_init(sp_pri_to_cos);
1159
1160         /* Prepare BW parameters*/
1161         bnx2x_status = bnx2x_ets_e3b0_get_total_bw(params, ets_params,
1162                                                    &total_bw);
1163         if (bnx2x_status) {
1164                 DP(NETIF_MSG_LINK,
1165                    "bnx2x_ets_E3B0_config get_total_bw failed\n");
1166                 return -EINVAL;
1167         }
1168
1169         /* Upper bound is set according to current link speed (min_w_val
1170          * should be the same for upper bound and COS credit val).
1171          */
1172         bnx2x_ets_e3b0_set_credit_upper_bound_nig(params, min_w_val_nig);
1173         bnx2x_ets_e3b0_set_credit_upper_bound_pbf(params, min_w_val_pbf);
1174
1175
1176         for (cos_entry = 0; cos_entry < ets_params->num_of_cos; cos_entry++) {
1177                 if (bnx2x_cos_state_bw == ets_params->cos[cos_entry].state) {
1178                         cos_bw_bitmap |= (1 << cos_entry);
1179                         /* The function also sets the BW in HW(not the mappin
1180                          * yet)
1181                          */
1182                         bnx2x_status = bnx2x_ets_e3b0_set_cos_bw(
1183                                 bp, cos_entry, min_w_val_nig, min_w_val_pbf,
1184                                 total_bw,
1185                                 ets_params->cos[cos_entry].params.bw_params.bw,
1186                                  port);
1187                 } else if (bnx2x_cos_state_strict ==
1188                         ets_params->cos[cos_entry].state){
1189                         cos_sp_bitmap |= (1 << cos_entry);
1190
1191                         bnx2x_status = bnx2x_ets_e3b0_sp_pri_to_cos_set(
1192                                 params,
1193                                 sp_pri_to_cos,
1194                                 ets_params->cos[cos_entry].params.sp_params.pri,
1195                                 cos_entry);
1196
1197                 } else {
1198                         DP(NETIF_MSG_LINK,
1199                            "bnx2x_ets_e3b0_config cos state not valid\n");
1200                         return -EINVAL;
1201                 }
1202                 if (bnx2x_status) {
1203                         DP(NETIF_MSG_LINK,
1204                            "bnx2x_ets_e3b0_config set cos bw failed\n");
1205                         return bnx2x_status;
1206                 }
1207         }
1208
1209         /* Set SP register (which COS has higher priority) */
1210         bnx2x_status = bnx2x_ets_e3b0_sp_set_pri_cli_reg(params,
1211                                                          sp_pri_to_cos);
1212
1213         if (bnx2x_status) {
1214                 DP(NETIF_MSG_LINK,
1215                    "bnx2x_ets_E3B0_config set_pri_cli_reg failed\n");
1216                 return bnx2x_status;
1217         }
1218
1219         /* Set client mapping of BW and strict */
1220         bnx2x_status = bnx2x_ets_e3b0_cli_map(params, ets_params,
1221                                               cos_sp_bitmap,
1222                                               cos_bw_bitmap);
1223
1224         if (bnx2x_status) {
1225                 DP(NETIF_MSG_LINK, "bnx2x_ets_E3B0_config SP failed\n");
1226                 return bnx2x_status;
1227         }
1228         return 0;
1229 }
1230 static void bnx2x_ets_bw_limit_common(const struct link_params *params)
1231 {
1232         /* ETS disabled configuration */
1233         struct bnx2x *bp = params->bp;
1234         DP(NETIF_MSG_LINK, "ETS enabled BW limit configuration\n");
1235         /* Defines which entries (clients) are subjected to WFQ arbitration
1236          * COS0 0x8
1237          * COS1 0x10
1238          */
1239         REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0x18);
1240         /* Mapping between the ARB_CREDIT_WEIGHT registers and actual
1241          * client numbers (WEIGHT_0 does not actually have to represent
1242          * client 0)
1243          *    PRI4    |    PRI3    |    PRI2    |    PRI1    |    PRI0
1244          *  cos1-001     cos0-000     dbg1-100     dbg0-011     MCP-010
1245          */
1246         REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP, 0x111A);
1247
1248         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0,
1249                ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
1250         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1,
1251                ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
1252
1253         /* ETS mode enabled*/
1254         REG_WR(bp, PBF_REG_ETS_ENABLED, 1);
1255
1256         /* Defines the number of consecutive slots for the strict priority */
1257         REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0);
1258         /* Bitmap of 5bits length. Each bit specifies whether the entry behaves
1259          * as strict.  Bits 0,1,2 - debug and management entries, 3 - COS0
1260          * entry, 4 - COS1 entry.
1261          * COS1 | COS0 | DEBUG21 | DEBUG0 | MGMT
1262          * bit4   bit3    bit2     bit1    bit0
1263          * MCP and debug are strict
1264          */
1265         REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x7);
1266
1267         /* Upper bound that COS0_WEIGHT can reach in the WFQ arbiter.*/
1268         REG_WR(bp, PBF_REG_COS0_UPPER_BOUND,
1269                ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
1270         REG_WR(bp, PBF_REG_COS1_UPPER_BOUND,
1271                ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
1272 }
1273
1274 void bnx2x_ets_bw_limit(const struct link_params *params, const u32 cos0_bw,
1275                         const u32 cos1_bw)
1276 {
1277         /* ETS disabled configuration*/
1278         struct bnx2x *bp = params->bp;
1279         const u32 total_bw = cos0_bw + cos1_bw;
1280         u32 cos0_credit_weight = 0;
1281         u32 cos1_credit_weight = 0;
1282
1283         DP(NETIF_MSG_LINK, "ETS enabled BW limit configuration\n");
1284
1285         if ((!total_bw) ||
1286             (!cos0_bw) ||
1287             (!cos1_bw)) {
1288                 DP(NETIF_MSG_LINK, "Total BW can't be zero\n");
1289                 return;
1290         }
1291
1292         cos0_credit_weight = (cos0_bw * ETS_BW_LIMIT_CREDIT_WEIGHT)/
1293                 total_bw;
1294         cos1_credit_weight = (cos1_bw * ETS_BW_LIMIT_CREDIT_WEIGHT)/
1295                 total_bw;
1296
1297         bnx2x_ets_bw_limit_common(params);
1298
1299         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, cos0_credit_weight);
1300         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, cos1_credit_weight);
1301
1302         REG_WR(bp, PBF_REG_COS0_WEIGHT, cos0_credit_weight);
1303         REG_WR(bp, PBF_REG_COS1_WEIGHT, cos1_credit_weight);
1304 }
1305
1306 int bnx2x_ets_strict(const struct link_params *params, const u8 strict_cos)
1307 {
1308         /* ETS disabled configuration*/
1309         struct bnx2x *bp = params->bp;
1310         u32 val = 0;
1311
1312         DP(NETIF_MSG_LINK, "ETS enabled strict configuration\n");
1313         /* Bitmap of 5bits length. Each bit specifies whether the entry behaves
1314          * as strict.  Bits 0,1,2 - debug and management entries,
1315          * 3 - COS0 entry, 4 - COS1 entry.
1316          *  COS1 | COS0 | DEBUG21 | DEBUG0 | MGMT
1317          *  bit4   bit3   bit2      bit1     bit0
1318          * MCP and debug are strict
1319          */
1320         REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x1F);
1321         /* For strict priority entries defines the number of consecutive slots
1322          * for the highest priority.
1323          */
1324         REG_WR(bp, NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100);
1325         /* ETS mode disable */
1326         REG_WR(bp, PBF_REG_ETS_ENABLED, 0);
1327         /* Defines the number of consecutive slots for the strict priority */
1328         REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0x100);
1329
1330         /* Defines the number of consecutive slots for the strict priority */
1331         REG_WR(bp, PBF_REG_HIGH_PRIORITY_COS_NUM, strict_cos);
1332
1333         /* Mapping between entry  priority to client number (0,1,2 -debug and
1334          * management clients, 3 - COS0 client, 4 - COS client)(HIGHEST)
1335          * 3bits client num.
1336          *   PRI4    |    PRI3    |    PRI2    |    PRI1    |    PRI0
1337          * dbg0-010     dbg1-001     cos1-100     cos0-011     MCP-000
1338          * dbg0-010     dbg1-001     cos0-011     cos1-100     MCP-000
1339          */
1340         val = (!strict_cos) ? 0x2318 : 0x22E0;
1341         REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT, val);
1342
1343         return 0;
1344 }
1345
1346 /******************************************************************/
1347 /*                      PFC section                               */
1348 /******************************************************************/
1349 static void bnx2x_update_pfc_xmac(struct link_params *params,
1350                                   struct link_vars *vars,
1351                                   u8 is_lb)
1352 {
1353         struct bnx2x *bp = params->bp;
1354         u32 xmac_base;
1355         u32 pause_val, pfc0_val, pfc1_val;
1356
1357         /* XMAC base adrr */
1358         xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
1359
1360         /* Initialize pause and pfc registers */
1361         pause_val = 0x18000;
1362         pfc0_val = 0xFFFF8000;
1363         pfc1_val = 0x2;
1364
1365         /* No PFC support */
1366         if (!(params->feature_config_flags &
1367               FEATURE_CONFIG_PFC_ENABLED)) {
1368
1369                 /* RX flow control - Process pause frame in receive direction
1370                  */
1371                 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)
1372                         pause_val |= XMAC_PAUSE_CTRL_REG_RX_PAUSE_EN;
1373
1374                 /* TX flow control - Send pause packet when buffer is full */
1375                 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)
1376                         pause_val |= XMAC_PAUSE_CTRL_REG_TX_PAUSE_EN;
1377         } else {/* PFC support */
1378                 pfc1_val |= XMAC_PFC_CTRL_HI_REG_PFC_REFRESH_EN |
1379                         XMAC_PFC_CTRL_HI_REG_PFC_STATS_EN |
1380                         XMAC_PFC_CTRL_HI_REG_RX_PFC_EN |
1381                         XMAC_PFC_CTRL_HI_REG_TX_PFC_EN |
1382                         XMAC_PFC_CTRL_HI_REG_FORCE_PFC_XON;
1383                 /* Write pause and PFC registers */
1384                 REG_WR(bp, xmac_base + XMAC_REG_PAUSE_CTRL, pause_val);
1385                 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL, pfc0_val);
1386                 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI, pfc1_val);
1387                 pfc1_val &= ~XMAC_PFC_CTRL_HI_REG_FORCE_PFC_XON;
1388
1389         }
1390
1391         /* Write pause and PFC registers */
1392         REG_WR(bp, xmac_base + XMAC_REG_PAUSE_CTRL, pause_val);
1393         REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL, pfc0_val);
1394         REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI, pfc1_val);
1395
1396
1397         /* Set MAC address for source TX Pause/PFC frames */
1398         REG_WR(bp, xmac_base + XMAC_REG_CTRL_SA_LO,
1399                ((params->mac_addr[2] << 24) |
1400                 (params->mac_addr[3] << 16) |
1401                 (params->mac_addr[4] << 8) |
1402                 (params->mac_addr[5])));
1403         REG_WR(bp, xmac_base + XMAC_REG_CTRL_SA_HI,
1404                ((params->mac_addr[0] << 8) |
1405                 (params->mac_addr[1])));
1406
1407         udelay(30);
1408 }
1409
1410 /******************************************************************/
1411 /*                      MAC/PBF section                           */
1412 /******************************************************************/
1413 static void bnx2x_set_mdio_clk(struct bnx2x *bp, u32 chip_id,
1414                                u32 emac_base)
1415 {
1416         u32 new_mode, cur_mode;
1417         u32 clc_cnt;
1418         /* Set clause 45 mode, slow down the MDIO clock to 2.5MHz
1419          * (a value of 49==0x31) and make sure that the AUTO poll is off
1420          */
1421         cur_mode = REG_RD(bp, emac_base + EMAC_REG_EMAC_MDIO_MODE);
1422
1423         if (USES_WARPCORE(bp))
1424                 clc_cnt = 74L << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT;
1425         else
1426                 clc_cnt = 49L << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT;
1427
1428         if (((cur_mode & EMAC_MDIO_MODE_CLOCK_CNT) == clc_cnt) &&
1429             (cur_mode & (EMAC_MDIO_MODE_CLAUSE_45)))
1430                 return;
1431
1432         new_mode = cur_mode &
1433                 ~(EMAC_MDIO_MODE_AUTO_POLL | EMAC_MDIO_MODE_CLOCK_CNT);
1434         new_mode |= clc_cnt;
1435         new_mode |= (EMAC_MDIO_MODE_CLAUSE_45);
1436
1437         DP(NETIF_MSG_LINK, "Changing emac_mode from 0x%x to 0x%x\n",
1438            cur_mode, new_mode);
1439         REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_MODE, new_mode);
1440         udelay(40);
1441 }
1442
1443 static void bnx2x_set_mdio_emac_per_phy(struct bnx2x *bp,
1444                                         struct link_params *params)
1445 {
1446         u8 phy_index;
1447         /* Set mdio clock per phy */
1448         for (phy_index = INT_PHY; phy_index < params->num_phys;
1449               phy_index++)
1450                 bnx2x_set_mdio_clk(bp, params->chip_id,
1451                                    params->phy[phy_index].mdio_ctrl);
1452 }
1453
1454 static u8 bnx2x_is_4_port_mode(struct bnx2x *bp)
1455 {
1456         u32 port4mode_ovwr_val;
1457         /* Check 4-port override enabled */
1458         port4mode_ovwr_val = REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR);
1459         if (port4mode_ovwr_val & (1<<0)) {
1460                 /* Return 4-port mode override value */
1461                 return ((port4mode_ovwr_val & (1<<1)) == (1<<1));
1462         }
1463         /* Return 4-port mode from input pin */
1464         return (u8)REG_RD(bp, MISC_REG_PORT4MODE_EN);
1465 }
1466
1467 static void bnx2x_emac_init(struct link_params *params,
1468                             struct link_vars *vars)
1469 {
1470         /* reset and unreset the emac core */
1471         struct bnx2x *bp = params->bp;
1472         u8 port = params->port;
1473         u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
1474         u32 val;
1475         u16 timeout;
1476
1477         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1478                (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port));
1479         udelay(5);
1480         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
1481                (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port));
1482
1483         /* init emac - use read-modify-write */
1484         /* self clear reset */
1485         val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
1486         EMAC_WR(bp, EMAC_REG_EMAC_MODE, (val | EMAC_MODE_RESET));
1487
1488         timeout = 200;
1489         do {
1490                 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
1491                 DP(NETIF_MSG_LINK, "EMAC reset reg is %u\n", val);
1492                 if (!timeout) {
1493                         DP(NETIF_MSG_LINK, "EMAC timeout!\n");
1494                         return;
1495                 }
1496                 timeout--;
1497         } while (val & EMAC_MODE_RESET);
1498
1499         bnx2x_set_mdio_emac_per_phy(bp, params);
1500         /* Set mac address */
1501         val = ((params->mac_addr[0] << 8) |
1502                 params->mac_addr[1]);
1503         EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH, val);
1504
1505         val = ((params->mac_addr[2] << 24) |
1506                (params->mac_addr[3] << 16) |
1507                (params->mac_addr[4] << 8) |
1508                 params->mac_addr[5]);
1509         EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + 4, val);
1510 }
1511
1512 static void bnx2x_set_xumac_nig(struct link_params *params,
1513                                 u16 tx_pause_en,
1514                                 u8 enable)
1515 {
1516         struct bnx2x *bp = params->bp;
1517
1518         REG_WR(bp, params->port ? NIG_REG_P1_MAC_IN_EN : NIG_REG_P0_MAC_IN_EN,
1519                enable);
1520         REG_WR(bp, params->port ? NIG_REG_P1_MAC_OUT_EN : NIG_REG_P0_MAC_OUT_EN,
1521                enable);
1522         REG_WR(bp, params->port ? NIG_REG_P1_MAC_PAUSE_OUT_EN :
1523                NIG_REG_P0_MAC_PAUSE_OUT_EN, tx_pause_en);
1524 }
1525
1526 static void bnx2x_set_umac_rxtx(struct link_params *params, u8 en)
1527 {
1528         u32 umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
1529         u32 val;
1530         struct bnx2x *bp = params->bp;
1531         if (!(REG_RD(bp, MISC_REG_RESET_REG_2) &
1532                    (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port)))
1533                 return;
1534         val = REG_RD(bp, umac_base + UMAC_REG_COMMAND_CONFIG);
1535         if (en)
1536                 val |= (UMAC_COMMAND_CONFIG_REG_TX_ENA |
1537                         UMAC_COMMAND_CONFIG_REG_RX_ENA);
1538         else
1539                 val &= ~(UMAC_COMMAND_CONFIG_REG_TX_ENA |
1540                          UMAC_COMMAND_CONFIG_REG_RX_ENA);
1541         /* Disable RX and TX */
1542         REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val);
1543 }
1544
1545 static void bnx2x_umac_enable(struct link_params *params,
1546                             struct link_vars *vars, u8 lb)
1547 {
1548         u32 val;
1549         u32 umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
1550         struct bnx2x *bp = params->bp;
1551         /* Reset UMAC */
1552         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1553                (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port));
1554         usleep_range(1000, 2000);
1555
1556         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
1557                (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port));
1558
1559         DP(NETIF_MSG_LINK, "enabling UMAC\n");
1560
1561         /* This register opens the gate for the UMAC despite its name */
1562         REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 1);
1563
1564         val = UMAC_COMMAND_CONFIG_REG_PROMIS_EN |
1565                 UMAC_COMMAND_CONFIG_REG_PAD_EN |
1566                 UMAC_COMMAND_CONFIG_REG_SW_RESET |
1567                 UMAC_COMMAND_CONFIG_REG_NO_LGTH_CHECK;
1568         switch (vars->line_speed) {
1569         case SPEED_10:
1570                 val |= (0<<2);
1571                 break;
1572         case SPEED_100:
1573                 val |= (1<<2);
1574                 break;
1575         case SPEED_1000:
1576                 val |= (2<<2);
1577                 break;
1578         case SPEED_2500:
1579                 val |= (3<<2);
1580                 break;
1581         default:
1582                 DP(NETIF_MSG_LINK, "Invalid speed for UMAC %d\n",
1583                                vars->line_speed);
1584                 break;
1585         }
1586         if (!(vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
1587                 val |= UMAC_COMMAND_CONFIG_REG_IGNORE_TX_PAUSE;
1588
1589         if (!(vars->flow_ctrl & BNX2X_FLOW_CTRL_RX))
1590                 val |= UMAC_COMMAND_CONFIG_REG_PAUSE_IGNORE;
1591
1592         if (vars->duplex == DUPLEX_HALF)
1593                 val |= UMAC_COMMAND_CONFIG_REG_HD_ENA;
1594
1595         REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val);
1596         udelay(50);
1597
1598         /* Configure UMAC for EEE */
1599         if (vars->eee_status & SHMEM_EEE_ADV_STATUS_MASK) {
1600                 DP(NETIF_MSG_LINK, "configured UMAC for EEE\n");
1601                 REG_WR(bp, umac_base + UMAC_REG_UMAC_EEE_CTRL,
1602                        UMAC_UMAC_EEE_CTRL_REG_EEE_EN);
1603                 REG_WR(bp, umac_base + UMAC_REG_EEE_WAKE_TIMER, 0x11);
1604         } else {
1605                 REG_WR(bp, umac_base + UMAC_REG_UMAC_EEE_CTRL, 0x0);
1606         }
1607
1608         /* Set MAC address for source TX Pause/PFC frames (under SW reset) */
1609         REG_WR(bp, umac_base + UMAC_REG_MAC_ADDR0,
1610                ((params->mac_addr[2] << 24) |
1611                 (params->mac_addr[3] << 16) |
1612                 (params->mac_addr[4] << 8) |
1613                 (params->mac_addr[5])));
1614         REG_WR(bp, umac_base + UMAC_REG_MAC_ADDR1,
1615                ((params->mac_addr[0] << 8) |
1616                 (params->mac_addr[1])));
1617
1618         /* Enable RX and TX */
1619         val &= ~UMAC_COMMAND_CONFIG_REG_PAD_EN;
1620         val |= UMAC_COMMAND_CONFIG_REG_TX_ENA |
1621                 UMAC_COMMAND_CONFIG_REG_RX_ENA;
1622         REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val);
1623         udelay(50);
1624
1625         /* Remove SW Reset */
1626         val &= ~UMAC_COMMAND_CONFIG_REG_SW_RESET;
1627
1628         /* Check loopback mode */
1629         if (lb)
1630                 val |= UMAC_COMMAND_CONFIG_REG_LOOP_ENA;
1631         REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val);
1632
1633         /* Maximum Frame Length (RW). Defines a 14-Bit maximum frame
1634          * length used by the MAC receive logic to check frames.
1635          */
1636         REG_WR(bp, umac_base + UMAC_REG_MAXFR, 0x2710);
1637         bnx2x_set_xumac_nig(params,
1638                             ((vars->flow_ctrl & BNX2X_FLOW_CTRL_TX) != 0), 1);
1639         vars->mac_type = MAC_TYPE_UMAC;
1640
1641 }
1642
1643 /* Define the XMAC mode */
1644 static void bnx2x_xmac_init(struct link_params *params, u32 max_speed)
1645 {
1646         struct bnx2x *bp = params->bp;
1647         u32 is_port4mode = bnx2x_is_4_port_mode(bp);
1648
1649         /* In 4-port mode, need to set the mode only once, so if XMAC is
1650          * already out of reset, it means the mode has already been set,
1651          * and it must not* reset the XMAC again, since it controls both
1652          * ports of the path
1653          */
1654
1655         if (((CHIP_NUM(bp) == CHIP_NUM_57840_4_10) ||
1656              (CHIP_NUM(bp) == CHIP_NUM_57840_2_20) ||
1657              (CHIP_NUM(bp) == CHIP_NUM_57840_OBSOLETE)) &&
1658             is_port4mode &&
1659             (REG_RD(bp, MISC_REG_RESET_REG_2) &
1660              MISC_REGISTERS_RESET_REG_2_XMAC)) {
1661                 DP(NETIF_MSG_LINK,
1662                    "XMAC already out of reset in 4-port mode\n");
1663                 return;
1664         }
1665
1666         /* Hard reset */
1667         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1668                MISC_REGISTERS_RESET_REG_2_XMAC);
1669         usleep_range(1000, 2000);
1670
1671         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
1672                MISC_REGISTERS_RESET_REG_2_XMAC);
1673         if (is_port4mode) {
1674                 DP(NETIF_MSG_LINK, "Init XMAC to 2 ports x 10G per path\n");
1675
1676                 /* Set the number of ports on the system side to up to 2 */
1677                 REG_WR(bp, MISC_REG_XMAC_CORE_PORT_MODE, 1);
1678
1679                 /* Set the number of ports on the Warp Core to 10G */
1680                 REG_WR(bp, MISC_REG_XMAC_PHY_PORT_MODE, 3);
1681         } else {
1682                 /* Set the number of ports on the system side to 1 */
1683                 REG_WR(bp, MISC_REG_XMAC_CORE_PORT_MODE, 0);
1684                 if (max_speed == SPEED_10000) {
1685                         DP(NETIF_MSG_LINK,
1686                            "Init XMAC to 10G x 1 port per path\n");
1687                         /* Set the number of ports on the Warp Core to 10G */
1688                         REG_WR(bp, MISC_REG_XMAC_PHY_PORT_MODE, 3);
1689                 } else {
1690                         DP(NETIF_MSG_LINK,
1691                            "Init XMAC to 20G x 2 ports per path\n");
1692                         /* Set the number of ports on the Warp Core to 20G */
1693                         REG_WR(bp, MISC_REG_XMAC_PHY_PORT_MODE, 1);
1694                 }
1695         }
1696         /* Soft reset */
1697         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1698                MISC_REGISTERS_RESET_REG_2_XMAC_SOFT);
1699         usleep_range(1000, 2000);
1700
1701         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
1702                MISC_REGISTERS_RESET_REG_2_XMAC_SOFT);
1703
1704 }
1705
1706 static void bnx2x_set_xmac_rxtx(struct link_params *params, u8 en)
1707 {
1708         u8 port = params->port;
1709         struct bnx2x *bp = params->bp;
1710         u32 pfc_ctrl, xmac_base = (port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
1711         u32 val;
1712
1713         if (REG_RD(bp, MISC_REG_RESET_REG_2) &
1714             MISC_REGISTERS_RESET_REG_2_XMAC) {
1715                 /* Send an indication to change the state in the NIG back to XON
1716                  * Clearing this bit enables the next set of this bit to get
1717                  * rising edge
1718                  */
1719                 pfc_ctrl = REG_RD(bp, xmac_base + XMAC_REG_PFC_CTRL_HI);
1720                 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI,
1721                        (pfc_ctrl & ~(1<<1)));
1722                 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI,
1723                        (pfc_ctrl | (1<<1)));
1724                 DP(NETIF_MSG_LINK, "Disable XMAC on port %x\n", port);
1725                 val = REG_RD(bp, xmac_base + XMAC_REG_CTRL);
1726                 if (en)
1727                         val |= (XMAC_CTRL_REG_TX_EN | XMAC_CTRL_REG_RX_EN);
1728                 else
1729                         val &= ~(XMAC_CTRL_REG_TX_EN | XMAC_CTRL_REG_RX_EN);
1730                 REG_WR(bp, xmac_base + XMAC_REG_CTRL, val);
1731         }
1732 }
1733
1734 static int bnx2x_xmac_enable(struct link_params *params,
1735                              struct link_vars *vars, u8 lb)
1736 {
1737         u32 val, xmac_base;
1738         struct bnx2x *bp = params->bp;
1739         DP(NETIF_MSG_LINK, "enabling XMAC\n");
1740
1741         xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
1742
1743         bnx2x_xmac_init(params, vars->line_speed);
1744
1745         /* This register determines on which events the MAC will assert
1746          * error on the i/f to the NIG along w/ EOP.
1747          */
1748
1749         /* This register tells the NIG whether to send traffic to UMAC
1750          * or XMAC
1751          */
1752         REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 0);
1753
1754         /* When XMAC is in XLGMII mode, disable sending idles for fault
1755          * detection.
1756          */
1757         if (!(params->phy[INT_PHY].flags & FLAGS_TX_ERROR_CHECK)) {
1758                 REG_WR(bp, xmac_base + XMAC_REG_RX_LSS_CTRL,
1759                        (XMAC_RX_LSS_CTRL_REG_LOCAL_FAULT_DISABLE |
1760                         XMAC_RX_LSS_CTRL_REG_REMOTE_FAULT_DISABLE));
1761                 REG_WR(bp, xmac_base + XMAC_REG_CLEAR_RX_LSS_STATUS, 0);
1762                 REG_WR(bp, xmac_base + XMAC_REG_CLEAR_RX_LSS_STATUS,
1763                        XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_LOCAL_FAULT_STATUS |
1764                        XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_REMOTE_FAULT_STATUS);
1765         }
1766         /* Set Max packet size */
1767         REG_WR(bp, xmac_base + XMAC_REG_RX_MAX_SIZE, 0x2710);
1768
1769         /* CRC append for Tx packets */
1770         REG_WR(bp, xmac_base + XMAC_REG_TX_CTRL, 0xC800);
1771
1772         /* update PFC */
1773         bnx2x_update_pfc_xmac(params, vars, 0);
1774
1775         if (vars->eee_status & SHMEM_EEE_ADV_STATUS_MASK) {
1776                 DP(NETIF_MSG_LINK, "Setting XMAC for EEE\n");
1777                 REG_WR(bp, xmac_base + XMAC_REG_EEE_TIMERS_HI, 0x1380008);
1778                 REG_WR(bp, xmac_base + XMAC_REG_EEE_CTRL, 0x1);
1779         } else {
1780                 REG_WR(bp, xmac_base + XMAC_REG_EEE_CTRL, 0x0);
1781         }
1782
1783         /* Enable TX and RX */
1784         val = XMAC_CTRL_REG_TX_EN | XMAC_CTRL_REG_RX_EN;
1785
1786         /* Set MAC in XLGMII mode for dual-mode */
1787         if ((vars->line_speed == SPEED_20000) &&
1788             (params->phy[INT_PHY].supported &
1789              SUPPORTED_20000baseKR2_Full))
1790                 val |= XMAC_CTRL_REG_XLGMII_ALIGN_ENB;
1791
1792         /* Check loopback mode */
1793         if (lb)
1794                 val |= XMAC_CTRL_REG_LINE_LOCAL_LPBK;
1795         REG_WR(bp, xmac_base + XMAC_REG_CTRL, val);
1796         bnx2x_set_xumac_nig(params,
1797                             ((vars->flow_ctrl & BNX2X_FLOW_CTRL_TX) != 0), 1);
1798
1799         vars->mac_type = MAC_TYPE_XMAC;
1800
1801         return 0;
1802 }
1803
1804 static int bnx2x_emac_enable(struct link_params *params,
1805                              struct link_vars *vars, u8 lb)
1806 {
1807         struct bnx2x *bp = params->bp;
1808         u8 port = params->port;
1809         u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
1810         u32 val;
1811
1812         DP(NETIF_MSG_LINK, "enabling EMAC\n");
1813
1814         /* Disable BMAC */
1815         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1816                (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
1817
1818         /* enable emac and not bmac */
1819         REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + port*4, 1);
1820
1821         /* ASIC */
1822         if (vars->phy_flags & PHY_XGXS_FLAG) {
1823                 u32 ser_lane = ((params->lane_config &
1824                                  PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
1825                                 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
1826
1827                 DP(NETIF_MSG_LINK, "XGXS\n");
1828                 /* select the master lanes (out of 0-3) */
1829                 REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 + port*4, ser_lane);
1830                 /* select XGXS */
1831                 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1);
1832
1833         } else { /* SerDes */
1834                 DP(NETIF_MSG_LINK, "SerDes\n");
1835                 /* select SerDes */
1836                 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0);
1837         }
1838
1839         bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_RX_MODE,
1840                       EMAC_RX_MODE_RESET);
1841         bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_TX_MODE,
1842                       EMAC_TX_MODE_RESET);
1843
1844         /* pause enable/disable */
1845         bnx2x_bits_dis(bp, emac_base + EMAC_REG_EMAC_RX_MODE,
1846                        EMAC_RX_MODE_FLOW_EN);
1847
1848         bnx2x_bits_dis(bp,  emac_base + EMAC_REG_EMAC_TX_MODE,
1849                        (EMAC_TX_MODE_EXT_PAUSE_EN |
1850                         EMAC_TX_MODE_FLOW_EN));
1851         if (!(params->feature_config_flags &
1852               FEATURE_CONFIG_PFC_ENABLED)) {
1853                 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)
1854                         bnx2x_bits_en(bp, emac_base +
1855                                       EMAC_REG_EMAC_RX_MODE,
1856                                       EMAC_RX_MODE_FLOW_EN);
1857
1858                 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)
1859                         bnx2x_bits_en(bp, emac_base +
1860                                       EMAC_REG_EMAC_TX_MODE,
1861                                       (EMAC_TX_MODE_EXT_PAUSE_EN |
1862                                        EMAC_TX_MODE_FLOW_EN));
1863         } else
1864                 bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_TX_MODE,
1865                               EMAC_TX_MODE_FLOW_EN);
1866
1867         /* KEEP_VLAN_TAG, promiscuous */
1868         val = REG_RD(bp, emac_base + EMAC_REG_EMAC_RX_MODE);
1869         val |= EMAC_RX_MODE_KEEP_VLAN_TAG | EMAC_RX_MODE_PROMISCUOUS;
1870
1871         /* Setting this bit causes MAC control frames (except for pause
1872          * frames) to be passed on for processing. This setting has no
1873          * affect on the operation of the pause frames. This bit effects
1874          * all packets regardless of RX Parser packet sorting logic.
1875          * Turn the PFC off to make sure we are in Xon state before
1876          * enabling it.
1877          */
1878         EMAC_WR(bp, EMAC_REG_RX_PFC_MODE, 0);
1879         if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) {
1880                 DP(NETIF_MSG_LINK, "PFC is enabled\n");
1881                 /* Enable PFC again */
1882                 EMAC_WR(bp, EMAC_REG_RX_PFC_MODE,
1883                         EMAC_REG_RX_PFC_MODE_RX_EN |
1884                         EMAC_REG_RX_PFC_MODE_TX_EN |
1885                         EMAC_REG_RX_PFC_MODE_PRIORITIES);
1886
1887                 EMAC_WR(bp, EMAC_REG_RX_PFC_PARAM,
1888                         ((0x0101 <<
1889                           EMAC_REG_RX_PFC_PARAM_OPCODE_BITSHIFT) |
1890                          (0x00ff <<
1891                           EMAC_REG_RX_PFC_PARAM_PRIORITY_EN_BITSHIFT)));
1892                 val |= EMAC_RX_MODE_KEEP_MAC_CONTROL;
1893         }
1894         EMAC_WR(bp, EMAC_REG_EMAC_RX_MODE, val);
1895
1896         /* Set Loopback */
1897         val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
1898         if (lb)
1899                 val |= 0x810;
1900         else
1901                 val &= ~0x810;
1902         EMAC_WR(bp, EMAC_REG_EMAC_MODE, val);
1903
1904         /* Enable emac */
1905         REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 1);
1906
1907         /* Enable emac for jumbo packets */
1908         EMAC_WR(bp, EMAC_REG_EMAC_RX_MTU_SIZE,
1909                 (EMAC_RX_MTU_SIZE_JUMBO_ENA |
1910                  (ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVERHEAD)));
1911
1912         /* Strip CRC */
1913         REG_WR(bp, NIG_REG_NIG_INGRESS_EMAC0_NO_CRC + port*4, 0x1);
1914
1915         /* Disable the NIG in/out to the bmac */
1916         REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0x0);
1917         REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, 0x0);
1918         REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0x0);
1919
1920         /* Enable the NIG in/out to the emac */
1921         REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0x1);
1922         val = 0;
1923         if ((params->feature_config_flags &
1924               FEATURE_CONFIG_PFC_ENABLED) ||
1925             (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
1926                 val = 1;
1927
1928         REG_WR(bp, NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, val);
1929         REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x1);
1930
1931         REG_WR(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x0);
1932
1933         vars->mac_type = MAC_TYPE_EMAC;
1934         return 0;
1935 }
1936
1937 static void bnx2x_update_pfc_bmac1(struct link_params *params,
1938                                    struct link_vars *vars)
1939 {
1940         u32 wb_data[2];
1941         struct bnx2x *bp = params->bp;
1942         u32 bmac_addr =  params->port ? NIG_REG_INGRESS_BMAC1_MEM :
1943                 NIG_REG_INGRESS_BMAC0_MEM;
1944
1945         u32 val = 0x14;
1946         if ((!(params->feature_config_flags &
1947               FEATURE_CONFIG_PFC_ENABLED)) &&
1948                 (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX))
1949                 /* Enable BigMAC to react on received Pause packets */
1950                 val |= (1<<5);
1951         wb_data[0] = val;
1952         wb_data[1] = 0;
1953         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_CONTROL, wb_data, 2);
1954
1955         /* TX control */
1956         val = 0xc0;
1957         if (!(params->feature_config_flags &
1958               FEATURE_CONFIG_PFC_ENABLED) &&
1959                 (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
1960                 val |= 0x800000;
1961         wb_data[0] = val;
1962         wb_data[1] = 0;
1963         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_CONTROL, wb_data, 2);
1964 }
1965
1966 static void bnx2x_update_pfc_bmac2(struct link_params *params,
1967                                    struct link_vars *vars,
1968                                    u8 is_lb)
1969 {
1970         /* Set rx control: Strip CRC and enable BigMAC to relay
1971          * control packets to the system as well
1972          */
1973         u32 wb_data[2];
1974         struct bnx2x *bp = params->bp;
1975         u32 bmac_addr = params->port ? NIG_REG_INGRESS_BMAC1_MEM :
1976                 NIG_REG_INGRESS_BMAC0_MEM;
1977         u32 val = 0x14;
1978
1979         if ((!(params->feature_config_flags &
1980               FEATURE_CONFIG_PFC_ENABLED)) &&
1981                 (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX))
1982                 /* Enable BigMAC to react on received Pause packets */
1983                 val |= (1<<5);
1984         wb_data[0] = val;
1985         wb_data[1] = 0;
1986         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_CONTROL, wb_data, 2);
1987         udelay(30);
1988
1989         /* Tx control */
1990         val = 0xc0;
1991         if (!(params->feature_config_flags &
1992                                 FEATURE_CONFIG_PFC_ENABLED) &&
1993             (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
1994                 val |= 0x800000;
1995         wb_data[0] = val;
1996         wb_data[1] = 0;
1997         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_CONTROL, wb_data, 2);
1998
1999         if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) {
2000                 DP(NETIF_MSG_LINK, "PFC is enabled\n");
2001                 /* Enable PFC RX & TX & STATS and set 8 COS  */
2002                 wb_data[0] = 0x0;
2003                 wb_data[0] |= (1<<0);  /* RX */
2004                 wb_data[0] |= (1<<1);  /* TX */
2005                 wb_data[0] |= (1<<2);  /* Force initial Xon */
2006                 wb_data[0] |= (1<<3);  /* 8 cos */
2007                 wb_data[0] |= (1<<5);  /* STATS */
2008                 wb_data[1] = 0;
2009                 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_PFC_CONTROL,
2010                             wb_data, 2);
2011                 /* Clear the force Xon */
2012                 wb_data[0] &= ~(1<<2);
2013         } else {
2014                 DP(NETIF_MSG_LINK, "PFC is disabled\n");
2015                 /* Disable PFC RX & TX & STATS and set 8 COS */
2016                 wb_data[0] = 0x8;
2017                 wb_data[1] = 0;
2018         }
2019
2020         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_PFC_CONTROL, wb_data, 2);
2021
2022         /* Set Time (based unit is 512 bit time) between automatic
2023          * re-sending of PP packets amd enable automatic re-send of
2024          * Per-Priroity Packet as long as pp_gen is asserted and
2025          * pp_disable is low.
2026          */
2027         val = 0x8000;
2028         if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED)
2029                 val |= (1<<16); /* enable automatic re-send */
2030
2031         wb_data[0] = val;
2032         wb_data[1] = 0;
2033         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_PAUSE_CONTROL,
2034                     wb_data, 2);
2035
2036         /* mac control */
2037         val = 0x3; /* Enable RX and TX */
2038         if (is_lb) {
2039                 val |= 0x4; /* Local loopback */
2040                 DP(NETIF_MSG_LINK, "enable bmac loopback\n");
2041         }
2042         /* When PFC enabled, Pass pause frames towards the NIG. */
2043         if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED)
2044                 val |= ((1<<6)|(1<<5));
2045
2046         wb_data[0] = val;
2047         wb_data[1] = 0;
2048         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL, wb_data, 2);
2049 }
2050
2051 /******************************************************************************
2052 * Description:
2053 *  This function is needed because NIG ARB_CREDIT_WEIGHT_X are
2054 *  not continues and ARB_CREDIT_WEIGHT_0 + offset is suitable.
2055 ******************************************************************************/
2056 static int bnx2x_pfc_nig_rx_priority_mask(struct bnx2x *bp,
2057                                            u8 cos_entry,
2058                                            u32 priority_mask, u8 port)
2059 {
2060         u32 nig_reg_rx_priority_mask_add = 0;
2061
2062         switch (cos_entry) {
2063         case 0:
2064              nig_reg_rx_priority_mask_add = (port) ?
2065                  NIG_REG_P1_RX_COS0_PRIORITY_MASK :
2066                  NIG_REG_P0_RX_COS0_PRIORITY_MASK;
2067              break;
2068         case 1:
2069             nig_reg_rx_priority_mask_add = (port) ?
2070                 NIG_REG_P1_RX_COS1_PRIORITY_MASK :
2071                 NIG_REG_P0_RX_COS1_PRIORITY_MASK;
2072             break;
2073         case 2:
2074             nig_reg_rx_priority_mask_add = (port) ?
2075                 NIG_REG_P1_RX_COS2_PRIORITY_MASK :
2076                 NIG_REG_P0_RX_COS2_PRIORITY_MASK;
2077             break;
2078         case 3:
2079             if (port)
2080                 return -EINVAL;
2081             nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS3_PRIORITY_MASK;
2082             break;
2083         case 4:
2084             if (port)
2085                 return -EINVAL;
2086             nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS4_PRIORITY_MASK;
2087             break;
2088         case 5:
2089             if (port)
2090                 return -EINVAL;
2091             nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS5_PRIORITY_MASK;
2092             break;
2093         }
2094
2095         REG_WR(bp, nig_reg_rx_priority_mask_add, priority_mask);
2096
2097         return 0;
2098 }
2099 static void bnx2x_update_mng(struct link_params *params, u32 link_status)
2100 {
2101         struct bnx2x *bp = params->bp;
2102
2103         REG_WR(bp, params->shmem_base +
2104                offsetof(struct shmem_region,
2105                         port_mb[params->port].link_status), link_status);
2106 }
2107
2108 static void bnx2x_update_link_attr(struct link_params *params, u32 link_attr)
2109 {
2110         struct bnx2x *bp = params->bp;
2111
2112         if (SHMEM2_HAS(bp, link_attr_sync))
2113                 REG_WR(bp, params->shmem2_base +
2114                        offsetof(struct shmem2_region,
2115                                 link_attr_sync[params->port]), link_attr);
2116 }
2117
2118 static void bnx2x_update_pfc_nig(struct link_params *params,
2119                 struct link_vars *vars,
2120                 struct bnx2x_nig_brb_pfc_port_params *nig_params)
2121 {
2122         u32 xcm_mask = 0, ppp_enable = 0, pause_enable = 0, llfc_out_en = 0;
2123         u32 llfc_enable = 0, xcm_out_en = 0, hwpfc_enable = 0;
2124         u32 pkt_priority_to_cos = 0;
2125         struct bnx2x *bp = params->bp;
2126         u8 port = params->port;
2127
2128         int set_pfc = params->feature_config_flags &
2129                 FEATURE_CONFIG_PFC_ENABLED;
2130         DP(NETIF_MSG_LINK, "updating pfc nig parameters\n");
2131
2132         /* When NIG_LLH0_XCM_MASK_REG_LLHX_XCM_MASK_BCN bit is set
2133          * MAC control frames (that are not pause packets)
2134          * will be forwarded to the XCM.
2135          */
2136         xcm_mask = REG_RD(bp, port ? NIG_REG_LLH1_XCM_MASK :
2137                           NIG_REG_LLH0_XCM_MASK);
2138         /* NIG params will override non PFC params, since it's possible to
2139          * do transition from PFC to SAFC
2140          */
2141         if (set_pfc) {
2142                 pause_enable = 0;
2143                 llfc_out_en = 0;
2144                 llfc_enable = 0;
2145                 if (CHIP_IS_E3(bp))
2146                         ppp_enable = 0;
2147                 else
2148                         ppp_enable = 1;
2149                 xcm_mask &= ~(port ? NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN :
2150                                      NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN);
2151                 xcm_out_en = 0;
2152                 hwpfc_enable = 1;
2153         } else  {
2154                 if (nig_params) {
2155                         llfc_out_en = nig_params->llfc_out_en;
2156                         llfc_enable = nig_params->llfc_enable;
2157                         pause_enable = nig_params->pause_enable;
2158                 } else  /* Default non PFC mode - PAUSE */
2159                         pause_enable = 1;
2160
2161                 xcm_mask |= (port ? NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN :
2162                         NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN);
2163                 xcm_out_en = 1;
2164         }
2165
2166         if (CHIP_IS_E3(bp))
2167                 REG_WR(bp, port ? NIG_REG_BRB1_PAUSE_IN_EN :
2168                        NIG_REG_BRB0_PAUSE_IN_EN, pause_enable);
2169         REG_WR(bp, port ? NIG_REG_LLFC_OUT_EN_1 :
2170                NIG_REG_LLFC_OUT_EN_0, llfc_out_en);
2171         REG_WR(bp, port ? NIG_REG_LLFC_ENABLE_1 :
2172                NIG_REG_LLFC_ENABLE_0, llfc_enable);
2173         REG_WR(bp, port ? NIG_REG_PAUSE_ENABLE_1 :
2174                NIG_REG_PAUSE_ENABLE_0, pause_enable);
2175
2176         REG_WR(bp, port ? NIG_REG_PPP_ENABLE_1 :
2177                NIG_REG_PPP_ENABLE_0, ppp_enable);
2178
2179         REG_WR(bp, port ? NIG_REG_LLH1_XCM_MASK :
2180                NIG_REG_LLH0_XCM_MASK, xcm_mask);
2181
2182         REG_WR(bp, port ? NIG_REG_LLFC_EGRESS_SRC_ENABLE_1 :
2183                NIG_REG_LLFC_EGRESS_SRC_ENABLE_0, 0x7);
2184
2185         /* Output enable for RX_XCM # IF */
2186         REG_WR(bp, port ? NIG_REG_XCM1_OUT_EN :
2187                NIG_REG_XCM0_OUT_EN, xcm_out_en);
2188
2189         /* HW PFC TX enable */
2190         REG_WR(bp, port ? NIG_REG_P1_HWPFC_ENABLE :
2191                NIG_REG_P0_HWPFC_ENABLE, hwpfc_enable);
2192
2193         if (nig_params) {
2194                 u8 i = 0;
2195                 pkt_priority_to_cos = nig_params->pkt_priority_to_cos;
2196
2197                 for (i = 0; i < nig_params->num_of_rx_cos_priority_mask; i++)
2198                         bnx2x_pfc_nig_rx_priority_mask(bp, i,
2199                 nig_params->rx_cos_priority_mask[i], port);
2200
2201                 REG_WR(bp, port ? NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_1 :
2202                        NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_0,
2203                        nig_params->llfc_high_priority_classes);
2204
2205                 REG_WR(bp, port ? NIG_REG_LLFC_LOW_PRIORITY_CLASSES_1 :
2206                        NIG_REG_LLFC_LOW_PRIORITY_CLASSES_0,
2207                        nig_params->llfc_low_priority_classes);
2208         }
2209         REG_WR(bp, port ? NIG_REG_P1_PKT_PRIORITY_TO_COS :
2210                NIG_REG_P0_PKT_PRIORITY_TO_COS,
2211                pkt_priority_to_cos);
2212 }
2213
2214 int bnx2x_update_pfc(struct link_params *params,
2215                       struct link_vars *vars,
2216                       struct bnx2x_nig_brb_pfc_port_params *pfc_params)
2217 {
2218         /* The PFC and pause are orthogonal to one another, meaning when
2219          * PFC is enabled, the pause are disabled, and when PFC is
2220          * disabled, pause are set according to the pause result.
2221          */
2222         u32 val;
2223         struct bnx2x *bp = params->bp;
2224         u8 bmac_loopback = (params->loopback_mode == LOOPBACK_BMAC);
2225
2226         if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED)
2227                 vars->link_status |= LINK_STATUS_PFC_ENABLED;
2228         else
2229                 vars->link_status &= ~LINK_STATUS_PFC_ENABLED;
2230
2231         bnx2x_update_mng(params, vars->link_status);
2232
2233         /* Update NIG params */
2234         bnx2x_update_pfc_nig(params, vars, pfc_params);
2235
2236         if (!vars->link_up)
2237                 return 0;
2238
2239         DP(NETIF_MSG_LINK, "About to update PFC in BMAC\n");
2240
2241         if (CHIP_IS_E3(bp)) {
2242                 if (vars->mac_type == MAC_TYPE_XMAC)
2243                         bnx2x_update_pfc_xmac(params, vars, 0);
2244         } else {
2245                 val = REG_RD(bp, MISC_REG_RESET_REG_2);
2246                 if ((val &
2247                      (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << params->port))
2248                     == 0) {
2249                         DP(NETIF_MSG_LINK, "About to update PFC in EMAC\n");
2250                         bnx2x_emac_enable(params, vars, 0);
2251                         return 0;
2252                 }
2253                 if (CHIP_IS_E2(bp))
2254                         bnx2x_update_pfc_bmac2(params, vars, bmac_loopback);
2255                 else
2256                         bnx2x_update_pfc_bmac1(params, vars);
2257
2258                 val = 0;
2259                 if ((params->feature_config_flags &
2260                      FEATURE_CONFIG_PFC_ENABLED) ||
2261                     (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
2262                         val = 1;
2263                 REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + params->port*4, val);
2264         }
2265         return 0;
2266 }
2267
2268 static int bnx2x_bmac1_enable(struct link_params *params,
2269                               struct link_vars *vars,
2270                               u8 is_lb)
2271 {
2272         struct bnx2x *bp = params->bp;
2273         u8 port = params->port;
2274         u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
2275                                NIG_REG_INGRESS_BMAC0_MEM;
2276         u32 wb_data[2];
2277         u32 val;
2278
2279         DP(NETIF_MSG_LINK, "Enabling BigMAC1\n");
2280
2281         /* XGXS control */
2282         wb_data[0] = 0x3c;
2283         wb_data[1] = 0;
2284         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_BMAC_XGXS_CONTROL,
2285                     wb_data, 2);
2286
2287         /* TX MAC SA */
2288         wb_data[0] = ((params->mac_addr[2] << 24) |
2289                        (params->mac_addr[3] << 16) |
2290                        (params->mac_addr[4] << 8) |
2291                         params->mac_addr[5]);
2292         wb_data[1] = ((params->mac_addr[0] << 8) |
2293                         params->mac_addr[1]);
2294         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_SOURCE_ADDR, wb_data, 2);
2295
2296         /* MAC control */
2297         val = 0x3;
2298         if (is_lb) {
2299                 val |= 0x4;
2300                 DP(NETIF_MSG_LINK, "enable bmac loopback\n");
2301         }
2302         wb_data[0] = val;
2303         wb_data[1] = 0;
2304         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_BMAC_CONTROL, wb_data, 2);
2305
2306         /* Set rx mtu */
2307         wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVERHEAD;
2308         wb_data[1] = 0;
2309         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_MAX_SIZE, wb_data, 2);
2310
2311         bnx2x_update_pfc_bmac1(params, vars);
2312
2313         /* Set tx mtu */
2314         wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVERHEAD;
2315         wb_data[1] = 0;
2316         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_MAX_SIZE, wb_data, 2);
2317
2318         /* Set cnt max size */
2319         wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVERHEAD;
2320         wb_data[1] = 0;
2321         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_CNT_MAX_SIZE, wb_data, 2);
2322
2323         /* Configure SAFC */
2324         wb_data[0] = 0x1000200;
2325         wb_data[1] = 0;
2326         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_LLFC_MSG_FLDS,
2327                     wb_data, 2);
2328
2329         return 0;
2330 }
2331
2332 static int bnx2x_bmac2_enable(struct link_params *params,
2333                               struct link_vars *vars,
2334                               u8 is_lb)
2335 {
2336         struct bnx2x *bp = params->bp;
2337         u8 port = params->port;
2338         u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
2339                                NIG_REG_INGRESS_BMAC0_MEM;
2340         u32 wb_data[2];
2341
2342         DP(NETIF_MSG_LINK, "Enabling BigMAC2\n");
2343
2344         wb_data[0] = 0;
2345         wb_data[1] = 0;
2346         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL, wb_data, 2);
2347         udelay(30);
2348
2349         /* XGXS control: Reset phy HW, MDIO registers, PHY PLL and BMAC */
2350         wb_data[0] = 0x3c;
2351         wb_data[1] = 0;
2352         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_XGXS_CONTROL,
2353                     wb_data, 2);
2354
2355         udelay(30);
2356
2357         /* TX MAC SA */
2358         wb_data[0] = ((params->mac_addr[2] << 24) |
2359                        (params->mac_addr[3] << 16) |
2360                        (params->mac_addr[4] << 8) |
2361                         params->mac_addr[5]);
2362         wb_data[1] = ((params->mac_addr[0] << 8) |
2363                         params->mac_addr[1]);
2364         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_SOURCE_ADDR,
2365                     wb_data, 2);
2366
2367         udelay(30);
2368
2369         /* Configure SAFC */
2370         wb_data[0] = 0x1000200;
2371         wb_data[1] = 0;
2372         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_LLFC_MSG_FLDS,
2373                     wb_data, 2);
2374         udelay(30);
2375
2376         /* Set RX MTU */
2377         wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVERHEAD;
2378         wb_data[1] = 0;
2379         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_MAX_SIZE, wb_data, 2);
2380         udelay(30);
2381
2382         /* Set TX MTU */
2383         wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVERHEAD;
2384         wb_data[1] = 0;
2385         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_MAX_SIZE, wb_data, 2);
2386         udelay(30);
2387         /* Set cnt max size */
2388         wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVERHEAD - 2;
2389         wb_data[1] = 0;
2390         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_CNT_MAX_SIZE, wb_data, 2);
2391         udelay(30);
2392         bnx2x_update_pfc_bmac2(params, vars, is_lb);
2393
2394         return 0;
2395 }
2396
2397 static int bnx2x_bmac_enable(struct link_params *params,
2398                              struct link_vars *vars,
2399                              u8 is_lb, u8 reset_bmac)
2400 {
2401         int rc = 0;
2402         u8 port = params->port;
2403         struct bnx2x *bp = params->bp;
2404         u32 val;
2405         /* Reset and unreset the BigMac */
2406         if (reset_bmac) {
2407                 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
2408                        (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
2409                 usleep_range(1000, 2000);
2410         }
2411
2412         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
2413                (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
2414
2415         /* Enable access for bmac registers */
2416         REG_WR(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x1);
2417
2418         /* Enable BMAC according to BMAC type*/
2419         if (CHIP_IS_E2(bp))
2420                 rc = bnx2x_bmac2_enable(params, vars, is_lb);
2421         else
2422                 rc = bnx2x_bmac1_enable(params, vars, is_lb);
2423         REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0x1);
2424         REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 + port*4, 0x0);
2425         REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + port*4, 0x0);
2426         val = 0;
2427         if ((params->feature_config_flags &
2428               FEATURE_CONFIG_PFC_ENABLED) ||
2429             (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
2430                 val = 1;
2431         REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, val);
2432         REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x0);
2433         REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0x0);
2434         REG_WR(bp, NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, 0x0);
2435         REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0x1);
2436         REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0x1);
2437
2438         vars->mac_type = MAC_TYPE_BMAC;
2439         return rc;
2440 }
2441
2442 static void bnx2x_set_bmac_rx(struct bnx2x *bp, u32 chip_id, u8 port, u8 en)
2443 {
2444         u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
2445                         NIG_REG_INGRESS_BMAC0_MEM;
2446         u32 wb_data[2];
2447         u32 nig_bmac_enable = REG_RD(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4);
2448
2449         if (CHIP_IS_E2(bp))
2450                 bmac_addr += BIGMAC2_REGISTER_BMAC_CONTROL;
2451         else
2452                 bmac_addr += BIGMAC_REGISTER_BMAC_CONTROL;
2453         /* Only if the bmac is out of reset */
2454         if (REG_RD(bp, MISC_REG_RESET_REG_2) &
2455                         (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port) &&
2456             nig_bmac_enable) {
2457                 /* Clear Rx Enable bit in BMAC_CONTROL register */
2458                 REG_RD_DMAE(bp, bmac_addr, wb_data, 2);
2459                 if (en)
2460                         wb_data[0] |= BMAC_CONTROL_RX_ENABLE;
2461                 else
2462                         wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE;
2463                 REG_WR_DMAE(bp, bmac_addr, wb_data, 2);
2464                 usleep_range(1000, 2000);
2465         }
2466 }
2467
2468 static int bnx2x_pbf_update(struct link_params *params, u32 flow_ctrl,
2469                             u32 line_speed)
2470 {
2471         struct bnx2x *bp = params->bp;
2472         u8 port = params->port;
2473         u32 init_crd, crd;
2474         u32 count = 1000;
2475
2476         /* Disable port */
2477         REG_WR(bp, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x1);
2478
2479         /* Wait for init credit */
2480         init_crd = REG_RD(bp, PBF_REG_P0_INIT_CRD + port*4);
2481         crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);
2482         DP(NETIF_MSG_LINK, "init_crd 0x%x  crd 0x%x\n", init_crd, crd);
2483
2484         while ((init_crd != crd) && count) {
2485                 usleep_range(5000, 10000);
2486                 crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);
2487                 count--;
2488         }
2489         crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);
2490         if (init_crd != crd) {
2491                 DP(NETIF_MSG_LINK, "BUG! init_crd 0x%x != crd 0x%x\n",
2492                           init_crd, crd);
2493                 return -EINVAL;
2494         }
2495
2496         if (flow_ctrl & BNX2X_FLOW_CTRL_RX ||
2497             line_speed == SPEED_10 ||
2498             line_speed == SPEED_100 ||
2499             line_speed == SPEED_1000 ||
2500             line_speed == SPEED_2500) {
2501                 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 1);
2502                 /* Update threshold */
2503                 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, 0);
2504                 /* Update init credit */
2505                 init_crd = 778;         /* (800-18-4) */
2506
2507         } else {
2508                 u32 thresh = (ETH_MAX_JUMBO_PACKET_SIZE +
2509                               ETH_OVERHEAD)/16;
2510                 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0);
2511                 /* Update threshold */
2512                 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, thresh);
2513                 /* Update init credit */
2514                 switch (line_speed) {
2515                 case SPEED_10000:
2516                         init_crd = thresh + 553 - 22;
2517                         break;
2518                 default:
2519                         DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n",
2520                                   line_speed);
2521                         return -EINVAL;
2522                 }
2523         }
2524         REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, init_crd);
2525         DP(NETIF_MSG_LINK, "PBF updated to speed %d credit %d\n",
2526                  line_speed, init_crd);
2527
2528         /* Probe the credit changes */
2529         REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0x1);
2530         usleep_range(5000, 10000);
2531         REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0x0);
2532
2533         /* Enable port */
2534         REG_WR(bp, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x0);
2535         return 0;
2536 }
2537
2538 /**
2539  * bnx2x_get_emac_base - retrive emac base address
2540  *
2541  * @bp:                 driver handle
2542  * @mdc_mdio_access:    access type
2543  * @port:               port id
2544  *
2545  * This function selects the MDC/MDIO access (through emac0 or
2546  * emac1) depend on the mdc_mdio_access, port, port swapped. Each
2547  * phy has a default access mode, which could also be overridden
2548  * by nvram configuration. This parameter, whether this is the
2549  * default phy configuration, or the nvram overrun
2550  * configuration, is passed here as mdc_mdio_access and selects
2551  * the emac_base for the CL45 read/writes operations
2552  */
2553 static u32 bnx2x_get_emac_base(struct bnx2x *bp,
2554                                u32 mdc_mdio_access, u8 port)
2555 {
2556         u32 emac_base = 0;
2557         switch (mdc_mdio_access) {
2558         case SHARED_HW_CFG_MDC_MDIO_ACCESS1_PHY_TYPE:
2559                 break;
2560         case SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC0:
2561                 if (REG_RD(bp, NIG_REG_PORT_SWAP))
2562                         emac_base = GRCBASE_EMAC1;
2563                 else
2564                         emac_base = GRCBASE_EMAC0;
2565                 break;
2566         case SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1:
2567                 if (REG_RD(bp, NIG_REG_PORT_SWAP))
2568                         emac_base = GRCBASE_EMAC0;
2569                 else
2570                         emac_base = GRCBASE_EMAC1;
2571                 break;
2572         case SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH:
2573                 emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
2574                 break;
2575         case SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED:
2576                 emac_base = (port) ? GRCBASE_EMAC0 : GRCBASE_EMAC1;
2577                 break;
2578         default:
2579                 break;
2580         }
2581         return emac_base;
2582
2583 }
2584
2585 /******************************************************************/
2586 /*                      CL22 access functions                     */
2587 /******************************************************************/
2588 static int bnx2x_cl22_write(struct bnx2x *bp,
2589                                        struct bnx2x_phy *phy,
2590                                        u16 reg, u16 val)
2591 {
2592         u32 tmp, mode;
2593         u8 i;
2594         int rc = 0;
2595         /* Switch to CL22 */
2596         mode = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
2597         REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE,
2598                mode & ~EMAC_MDIO_MODE_CLAUSE_45);
2599
2600         /* Address */
2601         tmp = ((phy->addr << 21) | (reg << 16) | val |
2602                EMAC_MDIO_COMM_COMMAND_WRITE_22 |
2603                EMAC_MDIO_COMM_START_BUSY);
2604         REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
2605
2606         for (i = 0; i < 50; i++) {
2607                 udelay(10);
2608
2609                 tmp = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
2610                 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
2611                         udelay(5);
2612                         break;
2613                 }
2614         }
2615         if (tmp & EMAC_MDIO_COMM_START_BUSY) {
2616                 DP(NETIF_MSG_LINK, "write phy register failed\n");
2617                 rc = -EFAULT;
2618         }
2619         REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, mode);
2620         return rc;
2621 }
2622
2623 static int bnx2x_cl22_read(struct bnx2x *bp,
2624                                       struct bnx2x_phy *phy,
2625                                       u16 reg, u16 *ret_val)
2626 {
2627         u32 val, mode;
2628         u16 i;
2629         int rc = 0;
2630
2631         /* Switch to CL22 */
2632         mode = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
2633         REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE,
2634                mode & ~EMAC_MDIO_MODE_CLAUSE_45);
2635
2636         /* Address */
2637         val = ((phy->addr << 21) | (reg << 16) |
2638                EMAC_MDIO_COMM_COMMAND_READ_22 |
2639                EMAC_MDIO_COMM_START_BUSY);
2640         REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
2641
2642         for (i = 0; i < 50; i++) {
2643                 udelay(10);
2644
2645                 val = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
2646                 if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
2647                         *ret_val = (u16)(val & EMAC_MDIO_COMM_DATA);
2648                         udelay(5);
2649                         break;
2650                 }
2651         }
2652         if (val & EMAC_MDIO_COMM_START_BUSY) {
2653                 DP(NETIF_MSG_LINK, "read phy register failed\n");
2654
2655                 *ret_val = 0;
2656                 rc = -EFAULT;
2657         }
2658         REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, mode);
2659         return rc;
2660 }
2661
2662 /******************************************************************/
2663 /*                      CL45 access functions                     */
2664 /******************************************************************/
2665 static int bnx2x_cl45_read(struct bnx2x *bp, struct bnx2x_phy *phy,
2666                            u8 devad, u16 reg, u16 *ret_val)
2667 {
2668         u32 val;
2669         u16 i;
2670         int rc = 0;
2671         u32 chip_id;
2672         if (phy->flags & FLAGS_MDC_MDIO_WA_G) {
2673                 chip_id = (REG_RD(bp, MISC_REG_CHIP_NUM) << 16) |
2674                           ((REG_RD(bp, MISC_REG_CHIP_REV) & 0xf) << 12);
2675                 bnx2x_set_mdio_clk(bp, chip_id, phy->mdio_ctrl);
2676         }
2677
2678         if (phy->flags & FLAGS_MDC_MDIO_WA_B0)
2679                 bnx2x_bits_en(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,
2680                               EMAC_MDIO_STATUS_10MB);
2681         /* Address */
2682         val = ((phy->addr << 21) | (devad << 16) | reg |
2683                EMAC_MDIO_COMM_COMMAND_ADDRESS |
2684                EMAC_MDIO_COMM_START_BUSY);
2685         REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
2686
2687         for (i = 0; i < 50; i++) {
2688                 udelay(10);
2689
2690                 val = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
2691                 if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
2692                         udelay(5);
2693                         break;
2694                 }
2695         }
2696         if (val & EMAC_MDIO_COMM_START_BUSY) {
2697                 DP(NETIF_MSG_LINK, "read phy register failed\n");
2698                 netdev_err(bp->dev,  "MDC/MDIO access timeout\n");
2699                 *ret_val = 0;
2700                 rc = -EFAULT;
2701         } else {
2702                 /* Data */
2703                 val = ((phy->addr << 21) | (devad << 16) |
2704                        EMAC_MDIO_COMM_COMMAND_READ_45 |
2705                        EMAC_MDIO_COMM_START_BUSY);
2706                 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
2707
2708                 for (i = 0; i < 50; i++) {
2709                         udelay(10);
2710
2711                         val = REG_RD(bp, phy->mdio_ctrl +
2712                                      EMAC_REG_EMAC_MDIO_COMM);
2713                         if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
2714                                 *ret_val = (u16)(val & EMAC_MDIO_COMM_DATA);
2715                                 break;
2716                         }
2717                 }
2718                 if (val & EMAC_MDIO_COMM_START_BUSY) {
2719                         DP(NETIF_MSG_LINK, "read phy register failed\n");
2720                         netdev_err(bp->dev,  "MDC/MDIO access timeout\n");
2721                         *ret_val = 0;
2722                         rc = -EFAULT;
2723                 }
2724         }
2725         /* Work around for E3 A0 */
2726         if (phy->flags & FLAGS_MDC_MDIO_WA) {
2727                 phy->flags ^= FLAGS_DUMMY_READ;
2728                 if (phy->flags & FLAGS_DUMMY_READ) {
2729                         u16 temp_val;
2730                         bnx2x_cl45_read(bp, phy, devad, 0xf, &temp_val);
2731                 }
2732         }
2733
2734         if (phy->flags & FLAGS_MDC_MDIO_WA_B0)
2735                 bnx2x_bits_dis(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,
2736                                EMAC_MDIO_STATUS_10MB);
2737         return rc;
2738 }
2739
2740 static int bnx2x_cl45_write(struct bnx2x *bp, struct bnx2x_phy *phy,
2741                             u8 devad, u16 reg, u16 val)
2742 {
2743         u32 tmp;
2744         u8 i;
2745         int rc = 0;
2746         u32 chip_id;
2747         if (phy->flags & FLAGS_MDC_MDIO_WA_G) {
2748                 chip_id = (REG_RD(bp, MISC_REG_CHIP_NUM) << 16) |
2749                           ((REG_RD(bp, MISC_REG_CHIP_REV) & 0xf) << 12);
2750                 bnx2x_set_mdio_clk(bp, chip_id, phy->mdio_ctrl);
2751         }
2752
2753         if (phy->flags & FLAGS_MDC_MDIO_WA_B0)
2754                 bnx2x_bits_en(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,
2755                               EMAC_MDIO_STATUS_10MB);
2756
2757         /* Address */
2758         tmp = ((phy->addr << 21) | (devad << 16) | reg |
2759                EMAC_MDIO_COMM_COMMAND_ADDRESS |
2760                EMAC_MDIO_COMM_START_BUSY);
2761         REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
2762
2763         for (i = 0; i < 50; i++) {
2764                 udelay(10);
2765
2766                 tmp = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
2767                 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
2768                         udelay(5);
2769                         break;
2770                 }
2771         }
2772         if (tmp & EMAC_MDIO_COMM_START_BUSY) {
2773                 DP(NETIF_MSG_LINK, "write phy register failed\n");
2774                 netdev_err(bp->dev,  "MDC/MDIO access timeout\n");
2775                 rc = -EFAULT;
2776         } else {
2777                 /* Data */
2778                 tmp = ((phy->addr << 21) | (devad << 16) | val |
2779                        EMAC_MDIO_COMM_COMMAND_WRITE_45 |
2780                        EMAC_MDIO_COMM_START_BUSY);
2781                 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
2782
2783                 for (i = 0; i < 50; i++) {
2784                         udelay(10);
2785
2786                         tmp = REG_RD(bp, phy->mdio_ctrl +
2787                                      EMAC_REG_EMAC_MDIO_COMM);
2788                         if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
2789                                 udelay(5);
2790                                 break;
2791                         }
2792                 }
2793                 if (tmp & EMAC_MDIO_COMM_START_BUSY) {
2794                         DP(NETIF_MSG_LINK, "write phy register failed\n");
2795                         netdev_err(bp->dev,  "MDC/MDIO access timeout\n");
2796                         rc = -EFAULT;
2797                 }
2798         }
2799         /* Work around for E3 A0 */
2800         if (phy->flags & FLAGS_MDC_MDIO_WA) {
2801                 phy->flags ^= FLAGS_DUMMY_READ;
2802                 if (phy->flags & FLAGS_DUMMY_READ) {
2803                         u16 temp_val;
2804                         bnx2x_cl45_read(bp, phy, devad, 0xf, &temp_val);
2805                 }
2806         }
2807         if (phy->flags & FLAGS_MDC_MDIO_WA_B0)
2808                 bnx2x_bits_dis(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,
2809                                EMAC_MDIO_STATUS_10MB);
2810         return rc;
2811 }
2812
2813 /******************************************************************/
2814 /*                      EEE section                                */
2815 /******************************************************************/
2816 static u8 bnx2x_eee_has_cap(struct link_params *params)
2817 {
2818         struct bnx2x *bp = params->bp;
2819
2820         if (REG_RD(bp, params->shmem2_base) <=
2821                    offsetof(struct shmem2_region, eee_status[params->port]))
2822                 return 0;
2823
2824         return 1;
2825 }
2826
2827 static int bnx2x_eee_nvram_to_time(u32 nvram_mode, u32 *idle_timer)
2828 {
2829         switch (nvram_mode) {
2830         case PORT_FEAT_CFG_EEE_POWER_MODE_BALANCED:
2831                 *idle_timer = EEE_MODE_NVRAM_BALANCED_TIME;
2832                 break;
2833         case PORT_FEAT_CFG_EEE_POWER_MODE_AGGRESSIVE:
2834                 *idle_timer = EEE_MODE_NVRAM_AGGRESSIVE_TIME;
2835                 break;
2836         case PORT_FEAT_CFG_EEE_POWER_MODE_LOW_LATENCY:
2837                 *idle_timer = EEE_MODE_NVRAM_LATENCY_TIME;
2838                 break;
2839         default:
2840                 *idle_timer = 0;
2841                 break;
2842         }
2843
2844         return 0;
2845 }
2846
2847 static int bnx2x_eee_time_to_nvram(u32 idle_timer, u32 *nvram_mode)
2848 {
2849         switch (idle_timer) {
2850         case EEE_MODE_NVRAM_BALANCED_TIME:
2851                 *nvram_mode = PORT_FEAT_CFG_EEE_POWER_MODE_BALANCED;
2852                 break;
2853         case EEE_MODE_NVRAM_AGGRESSIVE_TIME:
2854                 *nvram_mode = PORT_FEAT_CFG_EEE_POWER_MODE_AGGRESSIVE;
2855                 break;
2856         case EEE_MODE_NVRAM_LATENCY_TIME:
2857                 *nvram_mode = PORT_FEAT_CFG_EEE_POWER_MODE_LOW_LATENCY;
2858                 break;
2859         default:
2860                 *nvram_mode = PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED;
2861                 break;
2862         }
2863
2864         return 0;
2865 }
2866
2867 static u32 bnx2x_eee_calc_timer(struct link_params *params)
2868 {
2869         u32 eee_mode, eee_idle;
2870         struct bnx2x *bp = params->bp;
2871
2872         if (params->eee_mode & EEE_MODE_OVERRIDE_NVRAM) {
2873                 if (params->eee_mode & EEE_MODE_OUTPUT_TIME) {
2874                         /* time value in eee_mode --> used directly*/
2875                         eee_idle = params->eee_mode & EEE_MODE_TIMER_MASK;
2876                 } else {
2877                         /* hsi value in eee_mode --> time */
2878                         if (bnx2x_eee_nvram_to_time(params->eee_mode &
2879                                                     EEE_MODE_NVRAM_MASK,
2880                                                     &eee_idle))
2881                                 return 0;
2882                 }
2883         } else {
2884                 /* hsi values in nvram --> time*/
2885                 eee_mode = ((REG_RD(bp, params->shmem_base +
2886                                     offsetof(struct shmem_region, dev_info.
2887                                     port_feature_config[params->port].
2888                                     eee_power_mode)) &
2889                              PORT_FEAT_CFG_EEE_POWER_MODE_MASK) >>
2890                             PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT);
2891
2892                 if (bnx2x_eee_nvram_to_time(eee_mode, &eee_idle))
2893                         return 0;
2894         }
2895
2896         return eee_idle;
2897 }
2898
2899 static int bnx2x_eee_set_timers(struct link_params *params,
2900                                    struct link_vars *vars)
2901 {
2902         u32 eee_idle = 0, eee_mode;
2903         struct bnx2x *bp = params->bp;
2904
2905         eee_idle = bnx2x_eee_calc_timer(params);
2906
2907         if (eee_idle) {
2908                 REG_WR(bp, MISC_REG_CPMU_LP_IDLE_THR_P0 + (params->port << 2),
2909                        eee_idle);
2910         } else if ((params->eee_mode & EEE_MODE_ENABLE_LPI) &&
2911                    (params->eee_mode & EEE_MODE_OVERRIDE_NVRAM) &&
2912                    (params->eee_mode & EEE_MODE_OUTPUT_TIME)) {
2913                 DP(NETIF_MSG_LINK, "Error: Tx LPI is enabled with timer 0\n");
2914                 return -EINVAL;
2915         }
2916
2917         vars->eee_status &= ~(SHMEM_EEE_TIMER_MASK | SHMEM_EEE_TIME_OUTPUT_BIT);
2918         if (params->eee_mode & EEE_MODE_OUTPUT_TIME) {
2919                 /* eee_idle in 1u --> eee_status in 16u */
2920                 eee_idle >>= 4;
2921                 vars->eee_status |= (eee_idle & SHMEM_EEE_TIMER_MASK) |
2922                                     SHMEM_EEE_TIME_OUTPUT_BIT;
2923         } else {
2924                 if (bnx2x_eee_time_to_nvram(eee_idle, &eee_mode))
2925                         return -EINVAL;
2926                 vars->eee_status |= eee_mode;
2927         }
2928
2929         return 0;
2930 }
2931
2932 static int bnx2x_eee_initial_config(struct link_params *params,
2933                                      struct link_vars *vars, u8 mode)
2934 {
2935         vars->eee_status |= ((u32) mode) << SHMEM_EEE_SUPPORTED_SHIFT;
2936
2937         /* Propagate params' bits --> vars (for migration exposure) */
2938         if (params->eee_mode & EEE_MODE_ENABLE_LPI)
2939                 vars->eee_status |= SHMEM_EEE_LPI_REQUESTED_BIT;
2940         else
2941                 vars->eee_status &= ~SHMEM_EEE_LPI_REQUESTED_BIT;
2942
2943         if (params->eee_mode & EEE_MODE_ADV_LPI)
2944                 vars->eee_status |= SHMEM_EEE_REQUESTED_BIT;
2945         else
2946                 vars->eee_status &= ~SHMEM_EEE_REQUESTED_BIT;
2947
2948         return bnx2x_eee_set_timers(params, vars);
2949 }
2950
2951 static int bnx2x_eee_disable(struct bnx2x_phy *phy,
2952                                 struct link_params *params,
2953                                 struct link_vars *vars)
2954 {
2955         struct bnx2x *bp = params->bp;
2956
2957         /* Make Certain LPI is disabled */
2958         REG_WR(bp, MISC_REG_CPMU_LP_FW_ENABLE_P0 + (params->port << 2), 0);
2959
2960         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_EEE_ADV, 0x0);
2961
2962         vars->eee_status &= ~SHMEM_EEE_ADV_STATUS_MASK;
2963
2964         return 0;
2965 }
2966
2967 static int bnx2x_eee_advertise(struct bnx2x_phy *phy,
2968                                   struct link_params *params,
2969                                   struct link_vars *vars, u8 modes)
2970 {
2971         struct bnx2x *bp = params->bp;
2972         u16 val = 0;
2973
2974         /* Mask events preventing LPI generation */
2975         REG_WR(bp, MISC_REG_CPMU_LP_MASK_EXT_P0 + (params->port << 2), 0xfc20);
2976
2977         if (modes & SHMEM_EEE_10G_ADV) {
2978                 DP(NETIF_MSG_LINK, "Advertise 10GBase-T EEE\n");
2979                 val |= 0x8;
2980         }
2981         if (modes & SHMEM_EEE_1G_ADV) {
2982                 DP(NETIF_MSG_LINK, "Advertise 1GBase-T EEE\n");
2983                 val |= 0x4;
2984         }
2985
2986         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_EEE_ADV, val);
2987
2988         vars->eee_status &= ~SHMEM_EEE_ADV_STATUS_MASK;
2989         vars->eee_status |= (modes << SHMEM_EEE_ADV_STATUS_SHIFT);
2990
2991         return 0;
2992 }
2993
2994 static void bnx2x_update_mng_eee(struct link_params *params, u32 eee_status)
2995 {
2996         struct bnx2x *bp = params->bp;
2997
2998         if (bnx2x_eee_has_cap(params))
2999                 REG_WR(bp, params->shmem2_base +
3000                        offsetof(struct shmem2_region,
3001                                 eee_status[params->port]), eee_status);
3002 }
3003
3004 static void bnx2x_eee_an_resolve(struct bnx2x_phy *phy,
3005                                   struct link_params *params,
3006                                   struct link_vars *vars)
3007 {
3008         struct bnx2x *bp = params->bp;
3009         u16 adv = 0, lp = 0;
3010         u32 lp_adv = 0;
3011         u8 neg = 0;
3012
3013         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_EEE_ADV, &adv);
3014         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_LP_EEE_ADV, &lp);
3015
3016         if (lp & 0x2) {
3017                 lp_adv |= SHMEM_EEE_100M_ADV;
3018                 if (adv & 0x2) {
3019                         if (vars->line_speed == SPEED_100)
3020                                 neg = 1;
3021                         DP(NETIF_MSG_LINK, "EEE negotiated - 100M\n");
3022                 }
3023         }
3024         if (lp & 0x14) {
3025                 lp_adv |= SHMEM_EEE_1G_ADV;
3026                 if (adv & 0x14) {
3027                         if (vars->line_speed == SPEED_1000)
3028                                 neg = 1;
3029                         DP(NETIF_MSG_LINK, "EEE negotiated - 1G\n");
3030                 }
3031         }
3032         if (lp & 0x68) {
3033                 lp_adv |= SHMEM_EEE_10G_ADV;
3034                 if (adv & 0x68) {
3035                         if (vars->line_speed == SPEED_10000)
3036                                 neg = 1;
3037                         DP(NETIF_MSG_LINK, "EEE negotiated - 10G\n");
3038                 }
3039         }
3040
3041         vars->eee_status &= ~SHMEM_EEE_LP_ADV_STATUS_MASK;
3042         vars->eee_status |= (lp_adv << SHMEM_EEE_LP_ADV_STATUS_SHIFT);
3043
3044         if (neg) {
3045                 DP(NETIF_MSG_LINK, "EEE is active\n");
3046                 vars->eee_status |= SHMEM_EEE_ACTIVE_BIT;
3047         }
3048
3049 }
3050
3051 /******************************************************************/
3052 /*                      BSC access functions from E3              */
3053 /******************************************************************/
3054 static void bnx2x_bsc_module_sel(struct link_params *params)
3055 {
3056         int idx;
3057         u32 board_cfg, sfp_ctrl;
3058         u32 i2c_pins[I2C_SWITCH_WIDTH], i2c_val[I2C_SWITCH_WIDTH];
3059         struct bnx2x *bp = params->bp;
3060         u8 port = params->port;
3061         /* Read I2C output PINs */
3062         board_cfg = REG_RD(bp, params->shmem_base +
3063                            offsetof(struct shmem_region,
3064                                     dev_info.shared_hw_config.board));
3065         i2c_pins[I2C_BSC0] = board_cfg & SHARED_HW_CFG_E3_I2C_MUX0_MASK;
3066         i2c_pins[I2C_BSC1] = (board_cfg & SHARED_HW_CFG_E3_I2C_MUX1_MASK) >>
3067                         SHARED_HW_CFG_E3_I2C_MUX1_SHIFT;
3068
3069         /* Read I2C output value */
3070         sfp_ctrl = REG_RD(bp, params->shmem_base +
3071                           offsetof(struct shmem_region,
3072                                  dev_info.port_hw_config[port].e3_cmn_pin_cfg));
3073         i2c_val[I2C_BSC0] = (sfp_ctrl & PORT_HW_CFG_E3_I2C_MUX0_MASK) > 0;
3074         i2c_val[I2C_BSC1] = (sfp_ctrl & PORT_HW_CFG_E3_I2C_MUX1_MASK) > 0;
3075         DP(NETIF_MSG_LINK, "Setting BSC switch\n");
3076         for (idx = 0; idx < I2C_SWITCH_WIDTH; idx++)
3077                 bnx2x_set_cfg_pin(bp, i2c_pins[idx], i2c_val[idx]);
3078 }
3079
3080 static int bnx2x_bsc_read(struct link_params *params,
3081                           struct bnx2x *bp,
3082                           u8 sl_devid,
3083                           u16 sl_addr,
3084                           u8 lc_addr,
3085                           u8 xfer_cnt,
3086                           u32 *data_array)
3087 {
3088         u64 t0, delta;
3089         u32 val, i;
3090         int rc = 0;
3091
3092         if (xfer_cnt > 16) {
3093                 DP(NETIF_MSG_LINK, "invalid xfer_cnt %d. Max is 16 bytes\n",
3094                                         xfer_cnt);
3095                 return -EINVAL;
3096         }
3097         bnx2x_bsc_module_sel(params);
3098
3099         xfer_cnt = 16 - lc_addr;
3100
3101         /* Enable the engine */
3102         val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);
3103         val |= MCPR_IMC_COMMAND_ENABLE;
3104         REG_WR(bp, MCP_REG_MCPR_IMC_COMMAND, val);
3105
3106         /* Program slave device ID */
3107         val = (sl_devid << 16) | sl_addr;
3108         REG_WR(bp, MCP_REG_MCPR_IMC_SLAVE_CONTROL, val);
3109
3110         /* Start xfer with 0 byte to update the address pointer ???*/
3111         val = (MCPR_IMC_COMMAND_ENABLE) |
3112               (MCPR_IMC_COMMAND_WRITE_OP <<
3113                 MCPR_IMC_COMMAND_OPERATION_BITSHIFT) |
3114                 (lc_addr << MCPR_IMC_COMMAND_TRANSFER_ADDRESS_BITSHIFT) | (0);
3115         REG_WR(bp, MCP_REG_MCPR_IMC_COMMAND, val);
3116
3117         /* Poll for completion */
3118         t0 = ktime_get_ns();
3119         val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);
3120         while (((val >> MCPR_IMC_COMMAND_IMC_STATUS_BITSHIFT) & 0x3) != 1) {
3121                 delta = ktime_get_ns() - t0;
3122                 if (delta > 10 * NSEC_PER_MSEC) {
3123                         DP(NETIF_MSG_LINK, "wr 0 byte timed out after %Lu ns\n",
3124                                            delta);
3125                         rc = -EFAULT;
3126                         break;
3127                 }
3128                 usleep_range(10, 20);
3129                 val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);
3130         }
3131         if (rc == -EFAULT)
3132                 return rc;
3133
3134         /* Start xfer with read op */
3135         val = (MCPR_IMC_COMMAND_ENABLE) |
3136                 (MCPR_IMC_COMMAND_READ_OP <<
3137                 MCPR_IMC_COMMAND_OPERATION_BITSHIFT) |
3138                 (lc_addr << MCPR_IMC_COMMAND_TRANSFER_ADDRESS_BITSHIFT) |
3139                   (xfer_cnt);
3140         REG_WR(bp, MCP_REG_MCPR_IMC_COMMAND, val);
3141
3142         /* Poll for completion */
3143         t0 = ktime_get_ns();
3144         val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);
3145         while (((val >> MCPR_IMC_COMMAND_IMC_STATUS_BITSHIFT) & 0x3) != 1) {
3146                 delta = ktime_get_ns() - t0;
3147                 if (delta > 10 * NSEC_PER_MSEC) {
3148                         DP(NETIF_MSG_LINK, "rd op timed out after %Lu ns\n",
3149                                            delta);
3150                         rc = -EFAULT;
3151                         break;
3152                 }
3153                 usleep_range(10, 20);
3154                 val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);
3155         }
3156         if (rc == -EFAULT)
3157                 return rc;
3158
3159         for (i = (lc_addr >> 2); i < 4; i++) {
3160                 data_array[i] = REG_RD(bp, (MCP_REG_MCPR_IMC_DATAREG0 + i*4));
3161 #ifdef __BIG_ENDIAN
3162                 data_array[i] = ((data_array[i] & 0x000000ff) << 24) |
3163                                 ((data_array[i] & 0x0000ff00) << 8) |
3164                                 ((data_array[i] & 0x00ff0000) >> 8) |
3165                                 ((data_array[i] & 0xff000000) >> 24);
3166 #endif
3167         }
3168         return rc;
3169 }
3170
3171 static void bnx2x_cl45_read_or_write(struct bnx2x *bp, struct bnx2x_phy *phy,
3172                                      u8 devad, u16 reg, u16 or_val)
3173 {
3174         u16 val;
3175         bnx2x_cl45_read(bp, phy, devad, reg, &val);
3176         bnx2x_cl45_write(bp, phy, devad, reg, val | or_val);
3177 }
3178
3179 static void bnx2x_cl45_read_and_write(struct bnx2x *bp,
3180                                       struct bnx2x_phy *phy,
3181                                       u8 devad, u16 reg, u16 and_val)
3182 {
3183         u16 val;
3184         bnx2x_cl45_read(bp, phy, devad, reg, &val);
3185         bnx2x_cl45_write(bp, phy, devad, reg, val & and_val);
3186 }
3187
3188 int bnx2x_phy_read(struct link_params *params, u8 phy_addr,
3189                    u8 devad, u16 reg, u16 *ret_val)
3190 {
3191         u8 phy_index;
3192         /* Probe for the phy according to the given phy_addr, and execute
3193          * the read request on it
3194          */
3195         for (phy_index = 0; phy_index < params->num_phys; phy_index++) {
3196                 if (params->phy[phy_index].addr == phy_addr) {
3197                         return bnx2x_cl45_read(params->bp,
3198                                                &params->phy[phy_index], devad,
3199                                                reg, ret_val);
3200                 }
3201         }
3202         return -EINVAL;
3203 }
3204
3205 int bnx2x_phy_write(struct link_params *params, u8 phy_addr,
3206                     u8 devad, u16 reg, u16 val)
3207 {
3208         u8 phy_index;
3209         /* Probe for the phy according to the given phy_addr, and execute
3210          * the write request on it
3211          */
3212         for (phy_index = 0; phy_index < params->num_phys; phy_index++) {
3213                 if (params->phy[phy_index].addr == phy_addr) {
3214                         return bnx2x_cl45_write(params->bp,
3215                                                 &params->phy[phy_index], devad,
3216                                                 reg, val);
3217                 }
3218         }
3219         return -EINVAL;
3220 }
3221 static u8 bnx2x_get_warpcore_lane(struct bnx2x_phy *phy,
3222                                   struct link_params *params)
3223 {
3224         u8 lane = 0;
3225         struct bnx2x *bp = params->bp;
3226         u32 path_swap, path_swap_ovr;
3227         u8 path, port;
3228
3229         path = BP_PATH(bp);
3230         port = params->port;
3231
3232         if (bnx2x_is_4_port_mode(bp)) {
3233                 u32 port_swap, port_swap_ovr;
3234
3235                 /* Figure out path swap value */
3236                 path_swap_ovr = REG_RD(bp, MISC_REG_FOUR_PORT_PATH_SWAP_OVWR);
3237                 if (path_swap_ovr & 0x1)
3238                         path_swap = (path_swap_ovr & 0x2);
3239                 else
3240                         path_swap = REG_RD(bp, MISC_REG_FOUR_PORT_PATH_SWAP);
3241
3242                 if (path_swap)
3243                         path = path ^ 1;
3244
3245                 /* Figure out port swap value */
3246                 port_swap_ovr = REG_RD(bp, MISC_REG_FOUR_PORT_PORT_SWAP_OVWR);
3247                 if (port_swap_ovr & 0x1)
3248                         port_swap = (port_swap_ovr & 0x2);
3249                 else
3250                         port_swap = REG_RD(bp, MISC_REG_FOUR_PORT_PORT_SWAP);
3251
3252                 if (port_swap)
3253                         port = port ^ 1;
3254
3255                 lane = (port<<1) + path;
3256         } else { /* Two port mode - no port swap */
3257
3258                 /* Figure out path swap value */
3259                 path_swap_ovr =
3260                         REG_RD(bp, MISC_REG_TWO_PORT_PATH_SWAP_OVWR);
3261                 if (path_swap_ovr & 0x1) {
3262                         path_swap = (path_swap_ovr & 0x2);
3263                 } else {
3264                         path_swap =
3265                                 REG_RD(bp, MISC_REG_TWO_PORT_PATH_SWAP);
3266                 }
3267                 if (path_swap)
3268                         path = path ^ 1;
3269
3270                 lane = path << 1 ;
3271         }
3272         return lane;
3273 }
3274
3275 static void bnx2x_set_aer_mmd(struct link_params *params,
3276                               struct bnx2x_phy *phy)
3277 {
3278         u32 ser_lane;
3279         u16 offset, aer_val;
3280         struct bnx2x *bp = params->bp;
3281         ser_lane = ((params->lane_config &
3282                      PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
3283                      PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
3284
3285         offset = (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) ?
3286                 (phy->addr + ser_lane) : 0;
3287
3288         if (USES_WARPCORE(bp)) {
3289                 aer_val = bnx2x_get_warpcore_lane(phy, params);
3290                 /* In Dual-lane mode, two lanes are joined together,
3291                  * so in order to configure them, the AER broadcast method is
3292                  * used here.
3293                  * 0x200 is the broadcast address for lanes 0,1
3294                  * 0x201 is the broadcast address for lanes 2,3
3295                  */
3296                 if (phy->flags & FLAGS_WC_DUAL_MODE)
3297                         aer_val = (aer_val >> 1) | 0x200;
3298         } else if (CHIP_IS_E2(bp))
3299                 aer_val = 0x3800 + offset - 1;
3300         else
3301                 aer_val = 0x3800 + offset;
3302
3303         CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
3304                           MDIO_AER_BLOCK_AER_REG, aer_val);
3305
3306 }
3307
3308 /******************************************************************/
3309 /*                      Internal phy section                      */
3310 /******************************************************************/
3311
3312 static void bnx2x_set_serdes_access(struct bnx2x *bp, u8 port)
3313 {
3314         u32 emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
3315
3316         /* Set Clause 22 */
3317         REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_ST + port*0x10, 1);
3318         REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245f8000);
3319         udelay(500);
3320         REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245d000f);
3321         udelay(500);
3322          /* Set Clause 45 */
3323         REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_ST + port*0x10, 0);
3324 }
3325
3326 static void bnx2x_serdes_deassert(struct bnx2x *bp, u8 port)
3327 {
3328         u32 val;
3329
3330         DP(NETIF_MSG_LINK, "bnx2x_serdes_deassert\n");
3331
3332         val = SERDES_RESET_BITS << (port*16);
3333
3334         /* Reset and unreset the SerDes/XGXS */
3335         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val);
3336         udelay(500);
3337         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val);
3338
3339         bnx2x_set_serdes_access(bp, port);
3340
3341         REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_DEVAD + port*0x10,
3342                DEFAULT_PHY_DEV_ADDR);
3343 }
3344
3345 static void bnx2x_xgxs_specific_func(struct bnx2x_phy *phy,
3346                                      struct link_params *params,
3347                                      u32 action)
3348 {
3349         struct bnx2x *bp = params->bp;
3350         switch (action) {
3351         case PHY_INIT:
3352                 /* Set correct devad */
3353                 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_ST + params->port*0x18, 0);
3354                 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + params->port*0x18,
3355                        phy->def_md_devad);
3356                 break;
3357         }
3358 }
3359
3360 static void bnx2x_xgxs_deassert(struct link_params *params)
3361 {
3362         struct bnx2x *bp = params->bp;
3363         u8 port;
3364         u32 val;
3365         DP(NETIF_MSG_LINK, "bnx2x_xgxs_deassert\n");
3366         port = params->port;
3367
3368         val = XGXS_RESET_BITS << (port*16);
3369
3370         /* Reset and unreset the SerDes/XGXS */
3371         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val);
3372         udelay(500);
3373         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val);
3374         bnx2x_xgxs_specific_func(&params->phy[INT_PHY], params,
3375                                  PHY_INIT);
3376 }
3377
3378 static void bnx2x_calc_ieee_aneg_adv(struct bnx2x_phy *phy,
3379                                      struct link_params *params, u16 *ieee_fc)
3380 {
3381         struct bnx2x *bp = params->bp;
3382         *ieee_fc = MDIO_COMBO_IEEE0_AUTO_NEG_ADV_FULL_DUPLEX;
3383         /* Resolve pause mode and advertisement Please refer to Table
3384          * 28B-3 of the 802.3ab-1999 spec
3385          */
3386
3387         switch (phy->req_flow_ctrl) {
3388         case BNX2X_FLOW_CTRL_AUTO:
3389                 switch (params->req_fc_auto_adv) {
3390                 case BNX2X_FLOW_CTRL_BOTH:
3391                 case BNX2X_FLOW_CTRL_RX:
3392                         *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
3393                         break;
3394                 case BNX2X_FLOW_CTRL_TX:
3395                         *ieee_fc |=
3396                                 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
3397                         break;
3398                 default:
3399                         break;
3400                 }
3401                 break;
3402         case BNX2X_FLOW_CTRL_TX:
3403                 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
3404                 break;
3405
3406         case BNX2X_FLOW_CTRL_RX:
3407         case BNX2X_FLOW_CTRL_BOTH:
3408                 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
3409                 break;
3410
3411         case BNX2X_FLOW_CTRL_NONE:
3412         default:
3413                 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE;
3414                 break;
3415         }
3416         DP(NETIF_MSG_LINK, "ieee_fc = 0x%x\n", *ieee_fc);
3417 }
3418
3419 static void set_phy_vars(struct link_params *params,
3420                          struct link_vars *vars)
3421 {
3422         struct bnx2x *bp = params->bp;
3423         u8 actual_phy_idx, phy_index, link_cfg_idx;
3424         u8 phy_config_swapped = params->multi_phy_config &
3425                         PORT_HW_CFG_PHY_SWAPPED_ENABLED;
3426         for (phy_index = INT_PHY; phy_index < params->num_phys;
3427               phy_index++) {
3428                 link_cfg_idx = LINK_CONFIG_IDX(phy_index);
3429                 actual_phy_idx = phy_index;
3430                 if (phy_config_swapped) {
3431                         if (phy_index == EXT_PHY1)
3432                                 actual_phy_idx = EXT_PHY2;
3433                         else if (phy_index == EXT_PHY2)
3434                                 actual_phy_idx = EXT_PHY1;
3435                 }
3436                 params->phy[actual_phy_idx].req_flow_ctrl =
3437                         params->req_flow_ctrl[link_cfg_idx];
3438
3439                 params->phy[actual_phy_idx].req_line_speed =
3440                         params->req_line_speed[link_cfg_idx];
3441
3442                 params->phy[actual_phy_idx].speed_cap_mask =
3443                         params->speed_cap_mask[link_cfg_idx];
3444
3445                 params->phy[actual_phy_idx].req_duplex =
3446                         params->req_duplex[link_cfg_idx];
3447
3448                 if (params->req_line_speed[link_cfg_idx] ==
3449                     SPEED_AUTO_NEG)
3450                         vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_ENABLED;
3451
3452                 DP(NETIF_MSG_LINK, "req_flow_ctrl %x, req_line_speed %x,"
3453                            " speed_cap_mask %x\n",
3454                            params->phy[actual_phy_idx].req_flow_ctrl,
3455                            params->phy[actual_phy_idx].req_line_speed,
3456                            params->phy[actual_phy_idx].speed_cap_mask);
3457         }
3458 }
3459
3460 static void bnx2x_ext_phy_set_pause(struct link_params *params,
3461                                     struct bnx2x_phy *phy,
3462                                     struct link_vars *vars)
3463 {
3464         u16 val;
3465         struct bnx2x *bp = params->bp;
3466         /* Read modify write pause advertizing */
3467         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, &val);
3468
3469         val &= ~MDIO_AN_REG_ADV_PAUSE_BOTH;
3470
3471         /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
3472         bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
3473         if ((vars->ieee_fc &
3474             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
3475             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) {
3476                 val |= MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC;
3477         }
3478         if ((vars->ieee_fc &
3479             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
3480             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) {
3481                 val |= MDIO_AN_REG_ADV_PAUSE_PAUSE;
3482         }
3483         DP(NETIF_MSG_LINK, "Ext phy AN advertize 0x%x\n", val);
3484         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, val);
3485 }
3486
3487 static void bnx2x_pause_resolve(struct bnx2x_phy *phy,
3488                                 struct link_params *params,
3489                                 struct link_vars *vars,
3490                                 u32 pause_result)
3491 {
3492         struct bnx2x *bp = params->bp;
3493                                                 /*  LD      LP   */
3494         switch (pause_result) {                 /* ASYM P ASYM P */
3495         case 0xb:                               /*   1  0   1  1 */
3496                 DP(NETIF_MSG_LINK, "Flow Control: TX only\n");
3497                 vars->flow_ctrl = BNX2X_FLOW_CTRL_TX;
3498                 break;
3499
3500         case 0xe:                               /*   1  1   1  0 */
3501                 DP(NETIF_MSG_LINK, "Flow Control: RX only\n");
3502                 vars->flow_ctrl = BNX2X_FLOW_CTRL_RX;
3503                 break;
3504
3505         case 0x5:                               /*   0  1   0  1 */
3506         case 0x7:                               /*   0  1   1  1 */
3507         case 0xd:                               /*   1  1   0  1 */
3508         case 0xf:                               /*   1  1   1  1 */
3509                 /* If the user selected to advertise RX ONLY,
3510                  * although we advertised both, need to enable
3511                  * RX only.
3512                  */
3513                 if (params->req_fc_auto_adv == BNX2X_FLOW_CTRL_BOTH) {
3514                         DP(NETIF_MSG_LINK, "Flow Control: RX & TX\n");
3515                         vars->flow_ctrl = BNX2X_FLOW_CTRL_BOTH;
3516                 } else {
3517                         DP(NETIF_MSG_LINK, "Flow Control: RX only\n");
3518                         vars->flow_ctrl = BNX2X_FLOW_CTRL_RX;
3519                 }
3520                 break;
3521
3522         default:
3523                 DP(NETIF_MSG_LINK, "Flow Control: None\n");
3524                 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
3525                 break;
3526         }
3527         if (pause_result & (1<<0))
3528                 vars->link_status |= LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE;
3529         if (pause_result & (1<<1))
3530                 vars->link_status |= LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE;
3531
3532 }
3533
3534 static void bnx2x_ext_phy_update_adv_fc(struct bnx2x_phy *phy,
3535                                         struct link_params *params,
3536                                         struct link_vars *vars)
3537 {
3538         u16 ld_pause;           /* local */
3539         u16 lp_pause;           /* link partner */
3540         u16 pause_result;
3541         struct bnx2x *bp = params->bp;
3542         if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE) {
3543                 bnx2x_cl22_read(bp, phy, 0x4, &ld_pause);
3544                 bnx2x_cl22_read(bp, phy, 0x5, &lp_pause);
3545         } else if (CHIP_IS_E3(bp) &&
3546                 SINGLE_MEDIA_DIRECT(params)) {
3547                 u8 lane = bnx2x_get_warpcore_lane(phy, params);
3548                 u16 gp_status, gp_mask;
3549                 bnx2x_cl45_read(bp, phy,
3550                                 MDIO_AN_DEVAD, MDIO_WC_REG_GP2_STATUS_GP_2_4,
3551                                 &gp_status);
3552                 gp_mask = (MDIO_WC_REG_GP2_STATUS_GP_2_4_CL73_AN_CMPL |
3553                            MDIO_WC_REG_GP2_STATUS_GP_2_4_CL37_LP_AN_CAP) <<
3554                         lane;
3555                 if ((gp_status & gp_mask) == gp_mask) {
3556                         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
3557                                         MDIO_AN_REG_ADV_PAUSE, &ld_pause);
3558                         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
3559                                         MDIO_AN_REG_LP_AUTO_NEG, &lp_pause);
3560                 } else {
3561                         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
3562                                         MDIO_AN_REG_CL37_FC_LD, &ld_pause);
3563                         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
3564                                         MDIO_AN_REG_CL37_FC_LP, &lp_pause);
3565                         ld_pause = ((ld_pause &
3566                                      MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH)
3567                                     << 3);
3568                         lp_pause = ((lp_pause &
3569                                      MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH)
3570                                     << 3);
3571                 }
3572         } else {
3573                 bnx2x_cl45_read(bp, phy,
3574                                 MDIO_AN_DEVAD,
3575                                 MDIO_AN_REG_ADV_PAUSE, &ld_pause);
3576                 bnx2x_cl45_read(bp, phy,
3577                                 MDIO_AN_DEVAD,
3578                                 MDIO_AN_REG_LP_AUTO_NEG, &lp_pause);
3579         }
3580         pause_result = (ld_pause &
3581                         MDIO_AN_REG_ADV_PAUSE_MASK) >> 8;
3582         pause_result |= (lp_pause &
3583                          MDIO_AN_REG_ADV_PAUSE_MASK) >> 10;
3584         DP(NETIF_MSG_LINK, "Ext PHY pause result 0x%x\n", pause_result);
3585         bnx2x_pause_resolve(phy, params, vars, pause_result);
3586
3587 }
3588
3589 static u8 bnx2x_ext_phy_resolve_fc(struct bnx2x_phy *phy,
3590                                    struct link_params *params,
3591                                    struct link_vars *vars)
3592 {
3593         u8 ret = 0;
3594         vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
3595         if (phy->req_flow_ctrl != BNX2X_FLOW_CTRL_AUTO) {
3596                 /* Update the advertised flow-controled of LD/LP in AN */
3597                 if (phy->req_line_speed == SPEED_AUTO_NEG)
3598                         bnx2x_ext_phy_update_adv_fc(phy, params, vars);
3599                 /* But set the flow-control result as the requested one */
3600                 vars->flow_ctrl = phy->req_flow_ctrl;
3601         } else if (phy->req_line_speed != SPEED_AUTO_NEG)
3602                 vars->flow_ctrl = params->req_fc_auto_adv;
3603         else if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) {
3604                 ret = 1;
3605                 bnx2x_ext_phy_update_adv_fc(phy, params, vars);
3606         }
3607         return ret;
3608 }
3609 /******************************************************************/
3610 /*                      Warpcore section                          */
3611 /******************************************************************/
3612 /* The init_internal_warpcore should mirror the xgxs,
3613  * i.e. reset the lane (if needed), set aer for the
3614  * init configuration, and set/clear SGMII flag. Internal
3615  * phy init is done purely in phy_init stage.
3616  */
3617 #define WC_TX_DRIVER(post2, idriver, ipre, ifir) \
3618         ((post2 << MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET) | \
3619          (idriver << MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET) | \
3620          (ipre << MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET) | \
3621          (ifir << MDIO_WC_REG_TX0_TX_DRIVER_IFIR_OFFSET))
3622
3623 #define WC_TX_FIR(post, main, pre) \
3624         ((post << MDIO_WC_REG_TX_FIR_TAP_POST_TAP_OFFSET) | \
3625          (main << MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_OFFSET) | \
3626          (pre << MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_OFFSET))
3627
3628 static void bnx2x_warpcore_enable_AN_KR2(struct bnx2x_phy *phy,
3629                                          struct link_params *params,
3630                                          struct link_vars *vars)
3631 {
3632         struct bnx2x *bp = params->bp;
3633         u16 i;
3634         static struct bnx2x_reg_set reg_set[] = {
3635                 /* Step 1 - Program the TX/RX alignment markers */
3636                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL5, 0xa157},
3637                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL7, 0xcbe2},
3638                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL6, 0x7537},
3639                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL9, 0xa157},
3640                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_RX_CTRL11, 0xcbe2},
3641                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_RX_CTRL10, 0x7537},
3642                 /* Step 2 - Configure the NP registers */
3643                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_USERB0_CTRL, 0x000a},
3644                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CTRL1, 0x6400},
3645                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CTRL3, 0x0620},
3646                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CODE_FIELD, 0x0157},
3647                 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI1, 0x6464},
3648                 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI2, 0x3150},
3649                 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI3, 0x3150},
3650                 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_BAM_CODE, 0x0157},
3651                 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_UD_CODE, 0x0620}
3652         };
3653         DP(NETIF_MSG_LINK, "Enabling 20G-KR2\n");
3654
3655         bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
3656                                  MDIO_WC_REG_CL49_USERB0_CTRL, (3<<6));
3657
3658         for (i = 0; i < ARRAY_SIZE(reg_set); i++)
3659                 bnx2x_cl45_write(bp, phy, reg_set[i].devad, reg_set[i].reg,
3660                                  reg_set[i].val);
3661
3662         /* Start KR2 work-around timer which handles BCM8073 link-parner */
3663         params->link_attr_sync |= LINK_ATTR_SYNC_KR2_ENABLE;
3664         bnx2x_update_link_attr(params, params->link_attr_sync);
3665 }
3666
3667 static void bnx2x_disable_kr2(struct link_params *params,
3668                               struct link_vars *vars,
3669                               struct bnx2x_phy *phy)
3670 {
3671         struct bnx2x *bp = params->bp;
3672         int i;
3673         static struct bnx2x_reg_set reg_set[] = {
3674                 /* Step 1 - Program the TX/RX alignment markers */
3675                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL5, 0x7690},
3676                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL7, 0xe647},
3677                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL6, 0xc4f0},
3678                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL9, 0x7690},
3679                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_RX_CTRL11, 0xe647},
3680                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_RX_CTRL10, 0xc4f0},
3681                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_USERB0_CTRL, 0x000c},
3682                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CTRL1, 0x6000},
3683                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CTRL3, 0x0000},
3684                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CODE_FIELD, 0x0002},
3685                 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI1, 0x0000},
3686                 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI2, 0x0af7},
3687                 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI3, 0x0af7},
3688                 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_BAM_CODE, 0x0002},
3689                 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_UD_CODE, 0x0000}
3690         };
3691         DP(NETIF_MSG_LINK, "Disabling 20G-KR2\n");
3692
3693         for (i = 0; i < ARRAY_SIZE(reg_set); i++)
3694                 bnx2x_cl45_write(bp, phy, reg_set[i].devad, reg_set[i].reg,
3695                                  reg_set[i].val);
3696         params->link_attr_sync &= ~LINK_ATTR_SYNC_KR2_ENABLE;
3697         bnx2x_update_link_attr(params, params->link_attr_sync);
3698
3699         vars->check_kr2_recovery_cnt = CHECK_KR2_RECOVERY_CNT;
3700 }
3701
3702 static void bnx2x_warpcore_set_lpi_passthrough(struct bnx2x_phy *phy,
3703                                                struct link_params *params)
3704 {
3705         struct bnx2x *bp = params->bp;
3706
3707         DP(NETIF_MSG_LINK, "Configure WC for LPI pass through\n");
3708         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3709                          MDIO_WC_REG_EEE_COMBO_CONTROL0, 0x7c);
3710         bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
3711                                  MDIO_WC_REG_DIGITAL4_MISC5, 0xc000);
3712 }
3713
3714 static void bnx2x_warpcore_restart_AN_KR(struct bnx2x_phy *phy,
3715                                          struct link_params *params)
3716 {
3717         /* Restart autoneg on the leading lane only */
3718         struct bnx2x *bp = params->bp;
3719         u16 lane = bnx2x_get_warpcore_lane(phy, params);
3720         CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
3721                           MDIO_AER_BLOCK_AER_REG, lane);
3722         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
3723                          MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x1200);
3724
3725         /* Restore AER */
3726         bnx2x_set_aer_mmd(params, phy);
3727 }
3728
3729 static void bnx2x_warpcore_enable_AN_KR(struct bnx2x_phy *phy,
3730                                         struct link_params *params,
3731                                         struct link_vars *vars) {
3732         u16 lane, i, cl72_ctrl, an_adv = 0, val;
3733         u32 wc_lane_config;
3734         struct bnx2x *bp = params->bp;
3735         static struct bnx2x_reg_set reg_set[] = {
3736                 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 0x7},
3737                 {MDIO_PMA_DEVAD, MDIO_WC_REG_IEEE0BLK_AUTONEGNP, 0x0},
3738                 {MDIO_WC_DEVAD, MDIO_WC_REG_RX66_CONTROL, 0x7415},
3739                 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_MISC2, 0x6190},
3740                 /* Disable Autoneg: re-enable it after adv is done. */
3741                 {MDIO_AN_DEVAD, MDIO_WC_REG_IEEE0BLK_MIICNTL, 0},
3742                 {MDIO_PMA_DEVAD, MDIO_WC_REG_PMD_KR_CONTROL, 0x2},
3743                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL72_USERB0_CL72_TX_FIR_TAP, 0},
3744         };
3745         DP(NETIF_MSG_LINK, "Enable Auto Negotiation for KR\n");
3746         /* Set to default registers that may be overriden by 10G force */
3747         for (i = 0; i < ARRAY_SIZE(reg_set); i++)
3748                 bnx2x_cl45_write(bp, phy, reg_set[i].devad, reg_set[i].reg,
3749                                  reg_set[i].val);
3750
3751         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3752                         MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, &cl72_ctrl);
3753         cl72_ctrl &= 0x08ff;
3754         cl72_ctrl |= 0x3800;
3755         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3756                          MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, cl72_ctrl);
3757
3758         /* Check adding advertisement for 1G KX */
3759         if (((vars->line_speed == SPEED_AUTO_NEG) &&
3760              (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
3761             (vars->line_speed == SPEED_1000)) {
3762                 u16 addr = MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2;
3763                 an_adv |= (1<<5);
3764
3765                 /* Enable CL37 1G Parallel Detect */
3766                 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, addr, 0x1);
3767                 DP(NETIF_MSG_LINK, "Advertize 1G\n");
3768         }
3769         if (((vars->line_speed == SPEED_AUTO_NEG) &&
3770              (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) ||
3771             (vars->line_speed ==  SPEED_10000)) {
3772                 /* Check adding advertisement for 10G KR */
3773                 an_adv |= (1<<7);
3774                 /* Enable 10G Parallel Detect */
3775                 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
3776                                   MDIO_AER_BLOCK_AER_REG, 0);
3777
3778                 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
3779                                  MDIO_WC_REG_PAR_DET_10G_CTRL, 1);
3780                 bnx2x_set_aer_mmd(params, phy);
3781                 DP(NETIF_MSG_LINK, "Advertize 10G\n");
3782         }
3783
3784         /* Set Transmit PMD settings */
3785         lane = bnx2x_get_warpcore_lane(phy, params);
3786         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3787                          MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane,
3788                          WC_TX_DRIVER(0x02, 0x06, 0x09, 0));
3789         /* Configure the next lane if dual mode */
3790         if (phy->flags & FLAGS_WC_DUAL_MODE)
3791                 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3792                                  MDIO_WC_REG_TX0_TX_DRIVER + 0x10*(lane+1),
3793                                  WC_TX_DRIVER(0x02, 0x06, 0x09, 0));
3794         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3795                          MDIO_WC_REG_CL72_USERB0_CL72_OS_DEF_CTRL,
3796                          0x03f0);
3797         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3798                          MDIO_WC_REG_CL72_USERB0_CL72_2P5_DEF_CTRL,
3799                          0x03f0);
3800
3801         /* Advertised speeds */
3802         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
3803                          MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT1, an_adv);
3804
3805         /* Advertised and set FEC (Forward Error Correction) */
3806         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
3807                          MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT2,
3808                          (MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_ABILITY |
3809                           MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_REQ));
3810
3811         /* Enable CL37 BAM */
3812         if (REG_RD(bp, params->shmem_base +
3813                    offsetof(struct shmem_region, dev_info.
3814                             port_hw_config[params->port].default_cfg)) &
3815             PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED) {
3816                 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
3817                                          MDIO_WC_REG_DIGITAL6_MP5_NEXTPAGECTRL,
3818                                          1);
3819                 DP(NETIF_MSG_LINK, "Enable CL37 BAM on KR\n");
3820         }
3821
3822         /* Advertise pause */
3823         bnx2x_ext_phy_set_pause(params, phy, vars);
3824         vars->rx_tx_asic_rst = MAX_KR_LINK_RETRY;
3825         bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
3826                                  MDIO_WC_REG_DIGITAL5_MISC7, 0x100);
3827
3828         /* Over 1G - AN local device user page 1 */
3829         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3830                         MDIO_WC_REG_DIGITAL3_UP1, 0x1f);
3831
3832         if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
3833              (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)) ||
3834             (phy->req_line_speed == SPEED_20000)) {
3835
3836                 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
3837                                   MDIO_AER_BLOCK_AER_REG, lane);
3838
3839                 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
3840                                          MDIO_WC_REG_RX1_PCI_CTRL + (0x10*lane),
3841                                          (1<<11));
3842
3843                 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3844                                  MDIO_WC_REG_XGXS_X2_CONTROL3, 0x7);
3845                 bnx2x_set_aer_mmd(params, phy);
3846
3847                 bnx2x_warpcore_enable_AN_KR2(phy, params, vars);
3848         } else {
3849                 /* Enable Auto-Detect to support 1G over CL37 as well */
3850                 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3851                                  MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, 0x10);
3852                 wc_lane_config = REG_RD(bp, params->shmem_base +
3853                                         offsetof(struct shmem_region, dev_info.
3854                                         shared_hw_config.wc_lane_config));
3855                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3856                                 MDIO_WC_REG_RX0_PCI_CTRL + (lane << 4), &val);
3857                 /* Force cl48 sync_status LOW to avoid getting stuck in CL73
3858                  * parallel-detect loop when CL73 and CL37 are enabled.
3859                  */
3860                 val |= 1 << 11;
3861
3862                 /* Restore Polarity settings in case it was run over by
3863                  * previous link owner
3864                  */
3865                 if (wc_lane_config &
3866                     (SHARED_HW_CFG_RX_LANE0_POL_FLIP_ENABLED << lane))
3867                         val |= 3 << 2;
3868                 else
3869                         val &= ~(3 << 2);
3870                 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3871                                  MDIO_WC_REG_RX0_PCI_CTRL + (lane << 4),
3872                                  val);
3873
3874                 bnx2x_disable_kr2(params, vars, phy);
3875         }
3876
3877         /* Enable Autoneg: only on the main lane */
3878         bnx2x_warpcore_restart_AN_KR(phy, params);
3879 }
3880
3881 static void bnx2x_warpcore_set_10G_KR(struct bnx2x_phy *phy,
3882                                       struct link_params *params,
3883                                       struct link_vars *vars)
3884 {
3885         struct bnx2x *bp = params->bp;
3886         u16 val16, i, lane;
3887         static struct bnx2x_reg_set reg_set[] = {
3888                 /* Disable Autoneg */
3889                 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 0x7},
3890                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL,
3891                         0x3f00},
3892                 {MDIO_AN_DEVAD, MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT1, 0},
3893                 {MDIO_AN_DEVAD, MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x0},
3894                 {MDIO_WC_DEVAD, MDIO_WC_REG_DIGITAL3_UP1, 0x1},
3895                 {MDIO_WC_DEVAD, MDIO_WC_REG_DIGITAL5_MISC7, 0xa},
3896                 /* Leave cl72 training enable, needed for KR */
3897                 {MDIO_PMA_DEVAD, MDIO_WC_REG_PMD_KR_CONTROL, 0x2}
3898         };
3899
3900         for (i = 0; i < ARRAY_SIZE(reg_set); i++)
3901                 bnx2x_cl45_write(bp, phy, reg_set[i].devad, reg_set[i].reg,
3902                                  reg_set[i].val);
3903
3904         lane = bnx2x_get_warpcore_lane(phy, params);
3905         /* Global registers */
3906         CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
3907                           MDIO_AER_BLOCK_AER_REG, 0);
3908         /* Disable CL36 PCS Tx */
3909         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3910                         MDIO_WC_REG_XGXSBLK1_LANECTRL0, &val16);
3911         val16 &= ~(0x0011 << lane);
3912         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3913                          MDIO_WC_REG_XGXSBLK1_LANECTRL0, val16);
3914
3915         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3916                         MDIO_WC_REG_XGXSBLK1_LANECTRL1, &val16);
3917         val16 |= (0x0303 << (lane << 1));
3918         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3919                          MDIO_WC_REG_XGXSBLK1_LANECTRL1, val16);
3920         /* Restore AER */
3921         bnx2x_set_aer_mmd(params, phy);
3922         /* Set speed via PMA/PMD register */
3923         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD,
3924                          MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x2040);
3925
3926         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD,
3927                          MDIO_WC_REG_IEEE0BLK_AUTONEGNP, 0xB);
3928
3929         /* Enable encoded forced speed */
3930         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3931                          MDIO_WC_REG_SERDESDIGITAL_MISC2, 0x30);
3932
3933         /* Turn TX scramble payload only the 64/66 scrambler */
3934         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3935                          MDIO_WC_REG_TX66_CONTROL, 0x9);
3936
3937         /* Turn RX scramble payload only the 64/66 scrambler */
3938         bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
3939                                  MDIO_WC_REG_RX66_CONTROL, 0xF9);
3940
3941         /* Set and clear loopback to cause a reset to 64/66 decoder */
3942         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3943                          MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x4000);
3944         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3945                          MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x0);
3946
3947 }
3948
3949 static void bnx2x_warpcore_set_10G_XFI(struct bnx2x_phy *phy,
3950                                        struct link_params *params,
3951                                        u8 is_xfi)
3952 {
3953         struct bnx2x *bp = params->bp;
3954         u16 misc1_val, tap_val, tx_driver_val, lane, val;
3955         u32 cfg_tap_val, tx_drv_brdct, tx_equal;
3956         u32 ifir_val, ipost2_val, ipre_driver_val;
3957
3958         /* Hold rxSeqStart */
3959         bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
3960                                  MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0, 0x8000);
3961
3962         /* Hold tx_fifo_reset */
3963         bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
3964                                  MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3, 0x1);
3965
3966         /* Disable CL73 AN */
3967         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0);
3968
3969         /* Disable 100FX Enable and Auto-Detect */
3970         bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD,
3971                                   MDIO_WC_REG_FX100_CTRL1, 0xFFFA);
3972
3973         /* Disable 100FX Idle detect */
3974         bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
3975                                  MDIO_WC_REG_FX100_CTRL3, 0x0080);
3976
3977         /* Set Block address to Remote PHY & Clear forced_speed[5] */
3978         bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD,
3979                                   MDIO_WC_REG_DIGITAL4_MISC3, 0xFF7F);
3980
3981         /* Turn off auto-detect & fiber mode */
3982         bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD,
3983                                   MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1,
3984                                   0xFFEE);
3985
3986         /* Set filter_force_link, disable_false_link and parallel_detect */
3987         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3988                         MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, &val);
3989         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3990                          MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
3991                          ((val | 0x0006) & 0xFFFE));
3992
3993         /* Set XFI / SFI */
3994         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3995                         MDIO_WC_REG_SERDESDIGITAL_MISC1, &misc1_val);
3996
3997         misc1_val &= ~(0x1f);
3998
3999         if (is_xfi) {
4000                 misc1_val |= 0x5;
4001                 tap_val = WC_TX_FIR(0x08, 0x37, 0x00);
4002                 tx_driver_val = WC_TX_DRIVER(0x00, 0x02, 0x03, 0);
4003         } else {
4004                 cfg_tap_val = REG_RD(bp, params->shmem_base +
4005                                      offsetof(struct shmem_region, dev_info.
4006                                               port_hw_config[params->port].
4007                                               sfi_tap_values));
4008
4009                 tx_equal = cfg_tap_val & PORT_HW_CFG_TX_EQUALIZATION_MASK;
4010
4011                 misc1_val |= 0x9;
4012
4013                 /* TAP values are controlled by nvram, if value there isn't 0 */
4014                 if (tx_equal)
4015                         tap_val = (u16)tx_equal;
4016                 else
4017                         tap_val = WC_TX_FIR(0x0f, 0x2b, 0x02);
4018
4019                 ifir_val = DEFAULT_TX_DRV_IFIR;
4020                 ipost2_val = DEFAULT_TX_DRV_POST2;
4021                 ipre_driver_val = DEFAULT_TX_DRV_IPRE_DRIVER;
4022                 tx_drv_brdct = DEFAULT_TX_DRV_BRDCT;
4023
4024                 /* If any of the IFIR/IPRE_DRIVER/POST@ is set, apply all
4025                  * configuration.
4026                  */
4027                 if (cfg_tap_val & (PORT_HW_CFG_TX_DRV_IFIR_MASK |
4028                                    PORT_HW_CFG_TX_DRV_IPREDRIVER_MASK |
4029                                    PORT_HW_CFG_TX_DRV_POST2_MASK)) {
4030                         ifir_val = (cfg_tap_val &
4031                                     PORT_HW_CFG_TX_DRV_IFIR_MASK) >>
4032                                 PORT_HW_CFG_TX_DRV_IFIR_SHIFT;
4033                         ipre_driver_val = (cfg_tap_val &
4034                                            PORT_HW_CFG_TX_DRV_IPREDRIVER_MASK)
4035                         >> PORT_HW_CFG_TX_DRV_IPREDRIVER_SHIFT;
4036                         ipost2_val = (cfg_tap_val &
4037                                       PORT_HW_CFG_TX_DRV_POST2_MASK) >>
4038                                 PORT_HW_CFG_TX_DRV_POST2_SHIFT;
4039                 }
4040
4041                 if (cfg_tap_val & PORT_HW_CFG_TX_DRV_BROADCAST_MASK) {
4042                         tx_drv_brdct = (cfg_tap_val &
4043                                         PORT_HW_CFG_TX_DRV_BROADCAST_MASK) >>
4044                                 PORT_HW_CFG_TX_DRV_BROADCAST_SHIFT;
4045                 }
4046
4047                 tx_driver_val = WC_TX_DRIVER(ipost2_val, tx_drv_brdct,
4048                                              ipre_driver_val, ifir_val);
4049         }
4050         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4051                          MDIO_WC_REG_SERDESDIGITAL_MISC1, misc1_val);
4052
4053         /* Set Transmit PMD settings */
4054         lane = bnx2x_get_warpcore_lane(phy, params);
4055         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4056                          MDIO_WC_REG_TX_FIR_TAP,
4057                          tap_val | MDIO_WC_REG_TX_FIR_TAP_ENABLE);
4058         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4059                          MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane,
4060                          tx_driver_val);
4061
4062         /* Enable fiber mode, enable and invert sig_det */
4063         bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
4064                                  MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, 0xd);
4065
4066         /* Set Block address to Remote PHY & Set forced_speed[5], 40bit mode */
4067         bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
4068                                  MDIO_WC_REG_DIGITAL4_MISC3, 0x8080);
4069
4070         bnx2x_warpcore_set_lpi_passthrough(phy, params);
4071
4072         /* 10G XFI Full Duplex */
4073         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4074                          MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x100);
4075
4076         /* Release tx_fifo_reset */
4077         bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD,
4078                                   MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3,
4079                                   0xFFFE);
4080         /* Release rxSeqStart */
4081         bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD,
4082                                   MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0, 0x7FFF);
4083 }
4084
4085 static void bnx2x_warpcore_set_20G_force_KR2(struct bnx2x_phy *phy,
4086                                              struct link_params *params)
4087 {
4088         u16 val;
4089         struct bnx2x *bp = params->bp;
4090         /* Set global registers, so set AER lane to 0 */
4091         CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
4092                           MDIO_AER_BLOCK_AER_REG, 0);
4093
4094         /* Disable sequencer */
4095         bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD,
4096                                   MDIO_WC_REG_XGXSBLK0_XGXSCONTROL, ~(1<<13));
4097
4098         bnx2x_set_aer_mmd(params, phy);
4099
4100         bnx2x_cl45_read_and_write(bp, phy, MDIO_PMA_DEVAD,
4101                                   MDIO_WC_REG_PMD_KR_CONTROL, ~(1<<1));
4102         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
4103                          MDIO_AN_REG_CTRL, 0);
4104         /* Turn off CL73 */
4105         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4106                         MDIO_WC_REG_CL73_USERB0_CTRL, &val);
4107         val &= ~(1<<5);
4108         val |= (1<<6);
4109         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4110                          MDIO_WC_REG_CL73_USERB0_CTRL, val);
4111
4112         /* Set 20G KR2 force speed */
4113         bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
4114                                  MDIO_WC_REG_SERDESDIGITAL_MISC1, 0x1f);
4115
4116         bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
4117                                  MDIO_WC_REG_DIGITAL4_MISC3, (1<<7));
4118
4119         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4120                         MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, &val);
4121         val &= ~(3<<14);
4122         val |= (1<<15);
4123         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4124                          MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, val);
4125         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4126                          MDIO_WC_REG_CL72_USERB0_CL72_TX_FIR_TAP, 0x835A);
4127
4128         /* Enable sequencer (over lane 0) */
4129         CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
4130                           MDIO_AER_BLOCK_AER_REG, 0);
4131
4132         bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
4133                                  MDIO_WC_REG_XGXSBLK0_XGXSCONTROL, (1<<13));
4134
4135         bnx2x_set_aer_mmd(params, phy);
4136 }
4137
4138 static void bnx2x_warpcore_set_20G_DXGXS(struct bnx2x *bp,
4139                                          struct bnx2x_phy *phy,
4140                                          u16 lane)
4141 {
4142         /* Rx0 anaRxControl1G */
4143         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4144                          MDIO_WC_REG_RX0_ANARXCONTROL1G, 0x90);
4145
4146         /* Rx2 anaRxControl1G */
4147         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4148                          MDIO_WC_REG_RX2_ANARXCONTROL1G, 0x90);
4149
4150         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4151                          MDIO_WC_REG_RX66_SCW0, 0xE070);
4152
4153         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4154                          MDIO_WC_REG_RX66_SCW1, 0xC0D0);
4155
4156         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4157                          MDIO_WC_REG_RX66_SCW2, 0xA0B0);
4158
4159         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4160                          MDIO_WC_REG_RX66_SCW3, 0x8090);
4161
4162         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4163                          MDIO_WC_REG_RX66_SCW0_MASK, 0xF0F0);
4164
4165         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4166                          MDIO_WC_REG_RX66_SCW1_MASK, 0xF0F0);
4167
4168         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4169                          MDIO_WC_REG_RX66_SCW2_MASK, 0xF0F0);
4170
4171         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4172                          MDIO_WC_REG_RX66_SCW3_MASK, 0xF0F0);
4173
4174         /* Serdes Digital Misc1 */
4175         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4176                          MDIO_WC_REG_SERDESDIGITAL_MISC1, 0x6008);
4177
4178         /* Serdes Digital4 Misc3 */
4179         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4180                          MDIO_WC_REG_DIGITAL4_MISC3, 0x8088);
4181
4182         /* Set Transmit PMD settings */
4183         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4184                          MDIO_WC_REG_TX_FIR_TAP,
4185                          (WC_TX_FIR(0x12, 0x2d, 0x00) |
4186                           MDIO_WC_REG_TX_FIR_TAP_ENABLE));
4187         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4188                          MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane,
4189                          WC_TX_DRIVER(0x02, 0x02, 0x02, 0));
4190 }
4191
4192 static void bnx2x_warpcore_set_sgmii_speed(struct bnx2x_phy *phy,
4193                                            struct link_params *params,
4194                                            u8 fiber_mode,
4195                                            u8 always_autoneg)
4196 {
4197         struct bnx2x *bp = params->bp;
4198         u16 val16, digctrl_kx1, digctrl_kx2;
4199
4200         /* Clear XFI clock comp in non-10G single lane mode. */
4201         bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD,
4202                                   MDIO_WC_REG_RX66_CONTROL, ~(3<<13));
4203
4204         bnx2x_warpcore_set_lpi_passthrough(phy, params);
4205
4206         if (always_autoneg || phy->req_line_speed == SPEED_AUTO_NEG) {
4207                 /* SGMII Autoneg */
4208                 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
4209                                          MDIO_WC_REG_COMBO_IEEE0_MIICTRL,
4210                                          0x1000);
4211                 DP(NETIF_MSG_LINK, "set SGMII AUTONEG\n");
4212         } else {
4213                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4214                                 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16);
4215                 val16 &= 0xcebf;
4216                 switch (phy->req_line_speed) {
4217                 case SPEED_10:
4218                         break;
4219                 case SPEED_100:
4220                         val16 |= 0x2000;
4221                         break;
4222                 case SPEED_1000:
4223                         val16 |= 0x0040;
4224                         break;
4225                 default:
4226                         DP(NETIF_MSG_LINK,
4227                            "Speed not supported: 0x%x\n", phy->req_line_speed);
4228                         return;
4229                 }
4230
4231                 if (phy->req_duplex == DUPLEX_FULL)
4232                         val16 |= 0x0100;
4233
4234                 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4235                                 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, val16);
4236
4237                 DP(NETIF_MSG_LINK, "set SGMII force speed %d\n",
4238                                phy->req_line_speed);
4239                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4240                                 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16);
4241                 DP(NETIF_MSG_LINK, "  (readback) %x\n", val16);
4242         }
4243
4244         /* SGMII Slave mode and disable signal detect */
4245         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4246                         MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, &digctrl_kx1);
4247         if (fiber_mode)
4248                 digctrl_kx1 = 1;
4249         else
4250                 digctrl_kx1 &= 0xff4a;
4251
4252         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4253                         MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1,
4254                         digctrl_kx1);
4255
4256         /* Turn off parallel detect */
4257         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4258                         MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, &digctrl_kx2);
4259         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4260                         MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
4261                         (digctrl_kx2 & ~(1<<2)));
4262
4263         /* Re-enable parallel detect */
4264         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4265                         MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
4266                         (digctrl_kx2 | (1<<2)));
4267
4268         /* Enable autodet */
4269         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4270                         MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1,
4271                         (digctrl_kx1 | 0x10));
4272 }
4273
4274 static void bnx2x_warpcore_reset_lane(struct bnx2x *bp,
4275                                       struct bnx2x_phy *phy,
4276                                       u8 reset)
4277 {
4278         u16 val;
4279         /* Take lane out of reset after configuration is finished */
4280         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4281                         MDIO_WC_REG_DIGITAL5_MISC6, &val);
4282         if (reset)
4283                 val |= 0xC000;
4284         else
4285                 val &= 0x3FFF;
4286         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4287                          MDIO_WC_REG_DIGITAL5_MISC6, val);
4288         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4289                          MDIO_WC_REG_DIGITAL5_MISC6, &val);
4290 }
4291 /* Clear SFI/XFI link settings registers */
4292 static void bnx2x_warpcore_clear_regs(struct bnx2x_phy *phy,
4293                                       struct link_params *params,
4294                                       u16 lane)
4295 {
4296         struct bnx2x *bp = params->bp;
4297         u16 i;
4298         static struct bnx2x_reg_set wc_regs[] = {
4299                 {MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0},
4300                 {MDIO_WC_DEVAD, MDIO_WC_REG_FX100_CTRL1, 0x014a},
4301                 {MDIO_WC_DEVAD, MDIO_WC_REG_FX100_CTRL3, 0x0800},
4302                 {MDIO_WC_DEVAD, MDIO_WC_REG_DIGITAL4_MISC3, 0x8008},
4303                 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1,
4304                         0x0195},
4305                 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
4306                         0x0007},
4307                 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3,
4308                         0x0002},
4309                 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_MISC1, 0x6000},
4310                 {MDIO_WC_DEVAD, MDIO_WC_REG_TX_FIR_TAP, 0x0000},
4311                 {MDIO_WC_DEVAD, MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x2040},
4312                 {MDIO_WC_DEVAD, MDIO_WC_REG_COMBO_IEEE0_MIICTRL, 0x0140}
4313         };
4314         /* Set XFI clock comp as default. */
4315         bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
4316                                  MDIO_WC_REG_RX66_CONTROL, (3<<13));
4317
4318         for (i = 0; i < ARRAY_SIZE(wc_regs); i++)
4319                 bnx2x_cl45_write(bp, phy, wc_regs[i].devad, wc_regs[i].reg,
4320                                  wc_regs[i].val);
4321
4322         lane = bnx2x_get_warpcore_lane(phy, params);
4323         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4324                          MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane, 0x0990);
4325
4326 }
4327
4328 static int bnx2x_get_mod_abs_int_cfg(struct bnx2x *bp,
4329                                                 u32 chip_id,
4330                                                 u32 shmem_base, u8 port,
4331                                                 u8 *gpio_num, u8 *gpio_port)
4332 {
4333         u32 cfg_pin;
4334         *gpio_num = 0;
4335         *gpio_port = 0;
4336         if (CHIP_IS_E3(bp)) {
4337                 cfg_pin = (REG_RD(bp, shmem_base +
4338                                 offsetof(struct shmem_region,
4339                                 dev_info.port_hw_config[port].e3_sfp_ctrl)) &
4340                                 PORT_HW_CFG_E3_MOD_ABS_MASK) >>
4341                                 PORT_HW_CFG_E3_MOD_ABS_SHIFT;
4342
4343                 /* Should not happen. This function called upon interrupt
4344                  * triggered by GPIO ( since EPIO can only generate interrupts
4345                  * to MCP).
4346                  * So if this function was called and none of the GPIOs was set,
4347                  * it means the shit hit the fan.
4348                  */
4349                 if ((cfg_pin < PIN_CFG_GPIO0_P0) ||
4350                     (cfg_pin > PIN_CFG_GPIO3_P1)) {
4351                         DP(NETIF_MSG_LINK,
4352                            "No cfg pin %x for module detect indication\n",
4353                            cfg_pin);
4354                         return -EINVAL;
4355                 }
4356
4357                 *gpio_num = (cfg_pin - PIN_CFG_GPIO0_P0) & 0x3;
4358                 *gpio_port = (cfg_pin - PIN_CFG_GPIO0_P0) >> 2;
4359         } else {
4360                 *gpio_num = MISC_REGISTERS_GPIO_3;
4361                 *gpio_port = port;
4362         }
4363
4364         return 0;
4365 }
4366
4367 static int bnx2x_is_sfp_module_plugged(struct bnx2x_phy *phy,
4368                                        struct link_params *params)
4369 {
4370         struct bnx2x *bp = params->bp;
4371         u8 gpio_num, gpio_port;
4372         u32 gpio_val;
4373         if (bnx2x_get_mod_abs_int_cfg(bp, params->chip_id,
4374                                       params->shmem_base, params->port,
4375                                       &gpio_num, &gpio_port) != 0)
4376                 return 0;
4377         gpio_val = bnx2x_get_gpio(bp, gpio_num, gpio_port);
4378
4379         /* Call the handling function in case module is detected */
4380         if (gpio_val == 0)
4381                 return 1;
4382         else
4383                 return 0;
4384 }
4385 static int bnx2x_warpcore_get_sigdet(struct bnx2x_phy *phy,
4386                                      struct link_params *params)
4387 {
4388         u16 gp2_status_reg0, lane;
4389         struct bnx2x *bp = params->bp;
4390
4391         lane = bnx2x_get_warpcore_lane(phy, params);
4392
4393         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, MDIO_WC_REG_GP2_STATUS_GP_2_0,
4394                                  &gp2_status_reg0);
4395
4396         return (gp2_status_reg0 >> (8+lane)) & 0x1;
4397 }
4398
4399 static void bnx2x_warpcore_config_runtime(struct bnx2x_phy *phy,
4400                                           struct link_params *params,
4401                                           struct link_vars *vars)
4402 {
4403         struct bnx2x *bp = params->bp;
4404         u32 serdes_net_if;
4405         u16 gp_status1 = 0, lnkup = 0, lnkup_kr = 0;
4406
4407         vars->turn_to_run_wc_rt = vars->turn_to_run_wc_rt ? 0 : 1;
4408
4409         if (!vars->turn_to_run_wc_rt)
4410                 return;
4411
4412         if (vars->rx_tx_asic_rst) {
4413                 u16 lane = bnx2x_get_warpcore_lane(phy, params);
4414                 serdes_net_if = (REG_RD(bp, params->shmem_base +
4415                                 offsetof(struct shmem_region, dev_info.
4416                                 port_hw_config[params->port].default_cfg)) &
4417                                 PORT_HW_CFG_NET_SERDES_IF_MASK);
4418
4419                 switch (serdes_net_if) {
4420                 case PORT_HW_CFG_NET_SERDES_IF_KR:
4421                         /* Do we get link yet? */
4422                         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 0x81d1,
4423                                         &gp_status1);
4424                         lnkup = (gp_status1 >> (8+lane)) & 0x1;/* 1G */
4425                                 /*10G KR*/
4426                         lnkup_kr = (gp_status1 >> (12+lane)) & 0x1;
4427
4428                         if (lnkup_kr || lnkup) {
4429                                 vars->rx_tx_asic_rst = 0;
4430                         } else {
4431                                 /* Reset the lane to see if link comes up.*/
4432                                 bnx2x_warpcore_reset_lane(bp, phy, 1);
4433                                 bnx2x_warpcore_reset_lane(bp, phy, 0);
4434
4435                                 /* Restart Autoneg */
4436                                 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
4437                                         MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x1200);
4438
4439                                 vars->rx_tx_asic_rst--;
4440                                 DP(NETIF_MSG_LINK, "0x%x retry left\n",
4441                                 vars->rx_tx_asic_rst);
4442                         }
4443                         break;
4444
4445                 default:
4446                         break;
4447                 }
4448
4449         } /*params->rx_tx_asic_rst*/
4450
4451 }
4452 static void bnx2x_warpcore_config_sfi(struct bnx2x_phy *phy,
4453                                       struct link_params *params)
4454 {
4455         u16 lane = bnx2x_get_warpcore_lane(phy, params);
4456         struct bnx2x *bp = params->bp;
4457         bnx2x_warpcore_clear_regs(phy, params, lane);
4458         if ((params->req_line_speed[LINK_CONFIG_IDX(INT_PHY)] ==
4459              SPEED_10000) &&
4460             (phy->media_type != ETH_PHY_SFP_1G_FIBER)) {
4461                 DP(NETIF_MSG_LINK, "Setting 10G SFI\n");
4462                 bnx2x_warpcore_set_10G_XFI(phy, params, 0);
4463         } else {
4464                 DP(NETIF_MSG_LINK, "Setting 1G Fiber\n");
4465                 bnx2x_warpcore_set_sgmii_speed(phy, params, 1, 0);
4466         }
4467 }
4468
4469 static void bnx2x_sfp_e3_set_transmitter(struct link_params *params,
4470                                          struct bnx2x_phy *phy,
4471                                          u8 tx_en)
4472 {
4473         struct bnx2x *bp = params->bp;
4474         u32 cfg_pin;
4475         u8 port = params->port;
4476
4477         cfg_pin = REG_RD(bp, params->shmem_base +
4478                          offsetof(struct shmem_region,
4479                                   dev_info.port_hw_config[port].e3_sfp_ctrl)) &
4480                 PORT_HW_CFG_E3_TX_LASER_MASK;
4481         /* Set the !tx_en since this pin is DISABLE_TX_LASER */
4482         DP(NETIF_MSG_LINK, "Setting WC TX to %d\n", tx_en);
4483
4484         /* For 20G, the expected pin to be used is 3 pins after the current */
4485         bnx2x_set_cfg_pin(bp, cfg_pin, tx_en ^ 1);
4486         if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)
4487                 bnx2x_set_cfg_pin(bp, cfg_pin + 3, tx_en ^ 1);
4488 }
4489
4490 static void bnx2x_warpcore_config_init(struct bnx2x_phy *phy,
4491                                        struct link_params *params,
4492                                        struct link_vars *vars)
4493 {
4494         struct bnx2x *bp = params->bp;
4495         u32 serdes_net_if;
4496         u8 fiber_mode;
4497         u16 lane = bnx2x_get_warpcore_lane(phy, params);
4498         serdes_net_if = (REG_RD(bp, params->shmem_base +
4499                          offsetof(struct shmem_region, dev_info.
4500                                   port_hw_config[params->port].default_cfg)) &
4501                          PORT_HW_CFG_NET_SERDES_IF_MASK);
4502         DP(NETIF_MSG_LINK, "Begin Warpcore init, link_speed %d, "
4503                            "serdes_net_if = 0x%x\n",
4504                        vars->line_speed, serdes_net_if);
4505         bnx2x_set_aer_mmd(params, phy);
4506         bnx2x_warpcore_reset_lane(bp, phy, 1);
4507         vars->phy_flags |= PHY_XGXS_FLAG;
4508         if ((serdes_net_if == PORT_HW_CFG_NET_SERDES_IF_SGMII) ||
4509             (phy->req_line_speed &&
4510              ((phy->req_line_speed == SPEED_100) ||
4511               (phy->req_line_speed == SPEED_10)))) {
4512                 vars->phy_flags |= PHY_SGMII_FLAG;
4513                 DP(NETIF_MSG_LINK, "Setting SGMII mode\n");
4514                 bnx2x_warpcore_clear_regs(phy, params, lane);
4515                 bnx2x_warpcore_set_sgmii_speed(phy, params, 0, 1);
4516         } else {
4517                 switch (serdes_net_if) {
4518                 case PORT_HW_CFG_NET_SERDES_IF_KR:
4519                         /* Enable KR Auto Neg */
4520                         if (params->loopback_mode != LOOPBACK_EXT)
4521                                 bnx2x_warpcore_enable_AN_KR(phy, params, vars);
4522                         else {
4523                                 DP(NETIF_MSG_LINK, "Setting KR 10G-Force\n");
4524                                 bnx2x_warpcore_set_10G_KR(phy, params, vars);
4525                         }
4526                         break;
4527
4528                 case PORT_HW_CFG_NET_SERDES_IF_XFI:
4529                         bnx2x_warpcore_clear_regs(phy, params, lane);
4530                         if (vars->line_speed == SPEED_10000) {
4531                                 DP(NETIF_MSG_LINK, "Setting 10G XFI\n");
4532                                 bnx2x_warpcore_set_10G_XFI(phy, params, 1);
4533                         } else {
4534                                 if (SINGLE_MEDIA_DIRECT(params)) {
4535                                         DP(NETIF_MSG_LINK, "1G Fiber\n");
4536                                         fiber_mode = 1;
4537                                 } else {
4538                                         DP(NETIF_MSG_LINK, "10/100/1G SGMII\n");
4539                                         fiber_mode = 0;
4540                                 }
4541                                 bnx2x_warpcore_set_sgmii_speed(phy,
4542                                                                 params,
4543                                                                 fiber_mode,
4544                                                                 0);
4545                         }
4546
4547                         break;
4548
4549                 case PORT_HW_CFG_NET_SERDES_IF_SFI:
4550                         /* Issue Module detection if module is plugged, or
4551                          * enabled transmitter to avoid current leakage in case
4552                          * no module is connected
4553                          */
4554                         if ((params->loopback_mode == LOOPBACK_NONE) ||
4555                             (params->loopback_mode == LOOPBACK_EXT)) {
4556                                 if (bnx2x_is_sfp_module_plugged(phy, params))
4557                                         bnx2x_sfp_module_detection(phy, params);
4558                                 else
4559                                         bnx2x_sfp_e3_set_transmitter(params,
4560                                                                      phy, 1);
4561                         }
4562
4563                         bnx2x_warpcore_config_sfi(phy, params);
4564                         break;
4565
4566                 case PORT_HW_CFG_NET_SERDES_IF_DXGXS:
4567                         if (vars->line_speed != SPEED_20000) {
4568                                 DP(NETIF_MSG_LINK, "Speed not supported yet\n");
4569                                 return;
4570                         }
4571                         DP(NETIF_MSG_LINK, "Setting 20G DXGXS\n");
4572                         bnx2x_warpcore_set_20G_DXGXS(bp, phy, lane);
4573                         /* Issue Module detection */
4574
4575                         bnx2x_sfp_module_detection(phy, params);
4576                         break;
4577                 case PORT_HW_CFG_NET_SERDES_IF_KR2:
4578                         if (!params->loopback_mode) {
4579                                 bnx2x_warpcore_enable_AN_KR(phy, params, vars);
4580                         } else {
4581                                 DP(NETIF_MSG_LINK, "Setting KR 20G-Force\n");
4582                                 bnx2x_warpcore_set_20G_force_KR2(phy, params);
4583                         }
4584                         break;
4585                 default:
4586                         DP(NETIF_MSG_LINK,
4587                            "Unsupported Serdes Net Interface 0x%x\n",
4588                            serdes_net_if);
4589                         return;
4590                 }
4591         }
4592
4593         /* Take lane out of reset after configuration is finished */
4594         bnx2x_warpcore_reset_lane(bp, phy, 0);
4595         DP(NETIF_MSG_LINK, "Exit config init\n");
4596 }
4597
4598 static void bnx2x_warpcore_link_reset(struct bnx2x_phy *phy,
4599                                       struct link_params *params)
4600 {
4601         struct bnx2x *bp = params->bp;
4602         u16 val16, lane;
4603         bnx2x_sfp_e3_set_transmitter(params, phy, 0);
4604         bnx2x_set_mdio_emac_per_phy(bp, params);
4605         bnx2x_set_aer_mmd(params, phy);
4606         /* Global register */
4607         bnx2x_warpcore_reset_lane(bp, phy, 1);
4608
4609         /* Clear loopback settings (if any) */
4610         /* 10G & 20G */
4611         bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD,
4612                                   MDIO_WC_REG_COMBO_IEEE0_MIICTRL, 0xBFFF);
4613
4614         bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD,
4615                                   MDIO_WC_REG_IEEE0BLK_MIICNTL, 0xfffe);
4616
4617         /* Update those 1-copy registers */
4618         CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
4619                           MDIO_AER_BLOCK_AER_REG, 0);
4620         /* Enable 1G MDIO (1-copy) */
4621         bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD,
4622                                   MDIO_WC_REG_XGXSBLK0_XGXSCONTROL,
4623                                   ~0x10);
4624
4625         bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD,
4626                                   MDIO_WC_REG_XGXSBLK1_LANECTRL2, 0xff00);
4627         lane = bnx2x_get_warpcore_lane(phy, params);
4628         /* Disable CL36 PCS Tx */
4629         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4630                         MDIO_WC_REG_XGXSBLK1_LANECTRL0, &val16);
4631         val16 |= (0x11 << lane);
4632         if (phy->flags & FLAGS_WC_DUAL_MODE)
4633                 val16 |= (0x22 << lane);
4634         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4635                          MDIO_WC_REG_XGXSBLK1_LANECTRL0, val16);
4636
4637         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4638                         MDIO_WC_REG_XGXSBLK1_LANECTRL1, &val16);
4639         val16 &= ~(0x0303 << (lane << 1));
4640         val16 |= (0x0101 << (lane << 1));
4641         if (phy->flags & FLAGS_WC_DUAL_MODE) {
4642                 val16 &= ~(0x0c0c << (lane << 1));
4643                 val16 |= (0x0404 << (lane << 1));
4644         }
4645
4646         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4647                          MDIO_WC_REG_XGXSBLK1_LANECTRL1, val16);
4648         /* Restore AER */
4649         bnx2x_set_aer_mmd(params, phy);
4650
4651 }
4652
4653 static void bnx2x_set_warpcore_loopback(struct bnx2x_phy *phy,
4654                                         struct link_params *params)
4655 {
4656         struct bnx2x *bp = params->bp;
4657         u16 val16;
4658         u32 lane;
4659         DP(NETIF_MSG_LINK, "Setting Warpcore loopback type %x, speed %d\n",
4660                        params->loopback_mode, phy->req_line_speed);
4661
4662         if (phy->req_line_speed < SPEED_10000 ||
4663             phy->supported & SUPPORTED_20000baseKR2_Full) {
4664                 /* 10/100/1000/20G-KR2 */
4665
4666                 /* Update those 1-copy registers */
4667                 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
4668                                   MDIO_AER_BLOCK_AER_REG, 0);
4669                 /* Enable 1G MDIO (1-copy) */
4670                 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
4671                                          MDIO_WC_REG_XGXSBLK0_XGXSCONTROL,
4672                                          0x10);
4673                 /* Set 1G loopback based on lane (1-copy) */
4674                 lane = bnx2x_get_warpcore_lane(phy, params);
4675                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4676                                 MDIO_WC_REG_XGXSBLK1_LANECTRL2, &val16);
4677                 val16 |= (1<<lane);
4678                 if (phy->flags & FLAGS_WC_DUAL_MODE)
4679                         val16 |= (2<<lane);
4680                 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4681                                  MDIO_WC_REG_XGXSBLK1_LANECTRL2,
4682                                  val16);
4683
4684                 /* Switch back to 4-copy registers */
4685                 bnx2x_set_aer_mmd(params, phy);
4686         } else {
4687                 /* 10G / 20G-DXGXS */
4688                 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
4689                                          MDIO_WC_REG_COMBO_IEEE0_MIICTRL,
4690                                          0x4000);
4691                 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
4692                                          MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x1);
4693         }
4694 }
4695
4696
4697
4698 static void bnx2x_sync_link(struct link_params *params,
4699                              struct link_vars *vars)
4700 {
4701         struct bnx2x *bp = params->bp;
4702         u8 link_10g_plus;
4703         if (vars->link_status & LINK_STATUS_PHYSICAL_LINK_FLAG)
4704                 vars->phy_flags |= PHY_PHYSICAL_LINK_FLAG;
4705         vars->link_up = (vars->link_status & LINK_STATUS_LINK_UP);
4706         if (vars->link_up) {
4707                 DP(NETIF_MSG_LINK, "phy link up\n");
4708
4709                 vars->phy_link_up = 1;
4710                 vars->duplex = DUPLEX_FULL;
4711                 switch (vars->link_status &
4712                         LINK_STATUS_SPEED_AND_DUPLEX_MASK) {
4713                 case LINK_10THD:
4714                         vars->duplex = DUPLEX_HALF;
4715                         fallthrough;
4716                 case LINK_10TFD:
4717                         vars->line_speed = SPEED_10;
4718                         break;
4719
4720                 case LINK_100TXHD:
4721                         vars->duplex = DUPLEX_HALF;
4722                         fallthrough;
4723                 case LINK_100T4:
4724                 case LINK_100TXFD:
4725                         vars->line_speed = SPEED_100;
4726                         break;
4727
4728                 case LINK_1000THD:
4729                         vars->duplex = DUPLEX_HALF;
4730                         fallthrough;
4731                 case LINK_1000TFD:
4732                         vars->line_speed = SPEED_1000;
4733                         break;
4734
4735                 case LINK_2500THD:
4736                         vars->duplex = DUPLEX_HALF;
4737                         fallthrough;
4738                 case LINK_2500TFD:
4739                         vars->line_speed = SPEED_2500;
4740                         break;
4741
4742                 case LINK_10GTFD:
4743                         vars->line_speed = SPEED_10000;
4744                         break;
4745                 case LINK_20GTFD:
4746                         vars->line_speed = SPEED_20000;
4747                         break;
4748                 default:
4749                         break;
4750                 }
4751                 vars->flow_ctrl = 0;
4752                 if (vars->link_status & LINK_STATUS_TX_FLOW_CONTROL_ENABLED)
4753                         vars->flow_ctrl |= BNX2X_FLOW_CTRL_TX;
4754
4755                 if (vars->link_status & LINK_STATUS_RX_FLOW_CONTROL_ENABLED)
4756                         vars->flow_ctrl |= BNX2X_FLOW_CTRL_RX;
4757
4758                 if (!vars->flow_ctrl)
4759                         vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
4760
4761                 if (vars->line_speed &&
4762                     ((vars->line_speed == SPEED_10) ||
4763                      (vars->line_speed == SPEED_100))) {
4764                         vars->phy_flags |= PHY_SGMII_FLAG;
4765                 } else {
4766                         vars->phy_flags &= ~PHY_SGMII_FLAG;
4767                 }
4768                 if (vars->line_speed &&
4769                     USES_WARPCORE(bp) &&
4770                     (vars->line_speed == SPEED_1000))
4771                         vars->phy_flags |= PHY_SGMII_FLAG;
4772                 /* Anything 10 and over uses the bmac */
4773                 link_10g_plus = (vars->line_speed >= SPEED_10000);
4774
4775                 if (link_10g_plus) {
4776                         if (USES_WARPCORE(bp))
4777                                 vars->mac_type = MAC_TYPE_XMAC;
4778                         else
4779                                 vars->mac_type = MAC_TYPE_BMAC;
4780                 } else {
4781                         if (USES_WARPCORE(bp))
4782                                 vars->mac_type = MAC_TYPE_UMAC;
4783                         else
4784                                 vars->mac_type = MAC_TYPE_EMAC;
4785                 }
4786         } else { /* Link down */
4787                 DP(NETIF_MSG_LINK, "phy link down\n");
4788
4789                 vars->phy_link_up = 0;
4790
4791                 vars->line_speed = 0;
4792                 vars->duplex = DUPLEX_FULL;
4793                 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
4794
4795                 /* Indicate no mac active */
4796                 vars->mac_type = MAC_TYPE_NONE;
4797                 if (vars->link_status & LINK_STATUS_PHYSICAL_LINK_FLAG)
4798                         vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG;
4799                 if (vars->link_status & LINK_STATUS_SFP_TX_FAULT)
4800                         vars->phy_flags |= PHY_SFP_TX_FAULT_FLAG;
4801         }
4802 }
4803
4804 void bnx2x_link_status_update(struct link_params *params,
4805                               struct link_vars *vars)
4806 {
4807         struct bnx2x *bp = params->bp;
4808         u8 port = params->port;
4809         u32 sync_offset, media_types;
4810         /* Update PHY configuration */
4811         set_phy_vars(params, vars);
4812
4813         vars->link_status = REG_RD(bp, params->shmem_base +
4814                                    offsetof(struct shmem_region,
4815                                             port_mb[port].link_status));
4816
4817         /* Force link UP in non LOOPBACK_EXT loopback mode(s) */
4818         if (params->loopback_mode != LOOPBACK_NONE &&
4819             params->loopback_mode != LOOPBACK_EXT)
4820                 vars->link_status |= LINK_STATUS_LINK_UP;
4821
4822         if (bnx2x_eee_has_cap(params))
4823                 vars->eee_status = REG_RD(bp, params->shmem2_base +
4824                                           offsetof(struct shmem2_region,
4825                                                    eee_status[params->port]));
4826
4827         vars->phy_flags = PHY_XGXS_FLAG;
4828         bnx2x_sync_link(params, vars);
4829         /* Sync media type */
4830         sync_offset = params->shmem_base +
4831                         offsetof(struct shmem_region,
4832                                  dev_info.port_hw_config[port].media_type);
4833         media_types = REG_RD(bp, sync_offset);
4834
4835         params->phy[INT_PHY].media_type =
4836                 (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) >>
4837                 PORT_HW_CFG_MEDIA_TYPE_PHY0_SHIFT;
4838         params->phy[EXT_PHY1].media_type =
4839                 (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY1_MASK) >>
4840                 PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT;
4841         params->phy[EXT_PHY2].media_type =
4842                 (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY2_MASK) >>
4843                 PORT_HW_CFG_MEDIA_TYPE_PHY2_SHIFT;
4844         DP(NETIF_MSG_LINK, "media_types = 0x%x\n", media_types);
4845
4846         /* Sync AEU offset */
4847         sync_offset = params->shmem_base +
4848                         offsetof(struct shmem_region,
4849                                  dev_info.port_hw_config[port].aeu_int_mask);
4850
4851         vars->aeu_int_mask = REG_RD(bp, sync_offset);
4852
4853         /* Sync PFC status */
4854         if (vars->link_status & LINK_STATUS_PFC_ENABLED)
4855                 params->feature_config_flags |=
4856                                         FEATURE_CONFIG_PFC_ENABLED;
4857         else
4858                 params->feature_config_flags &=
4859                                         ~FEATURE_CONFIG_PFC_ENABLED;
4860
4861         if (SHMEM2_HAS(bp, link_attr_sync))
4862                 params->link_attr_sync = SHMEM2_RD(bp,
4863                                                  link_attr_sync[params->port]);
4864
4865         DP(NETIF_MSG_LINK, "link_status 0x%x  phy_link_up %x int_mask 0x%x\n",
4866                  vars->link_status, vars->phy_link_up, vars->aeu_int_mask);
4867         DP(NETIF_MSG_LINK, "line_speed %x  duplex %x  flow_ctrl 0x%x\n",
4868                  vars->line_speed, vars->duplex, vars->flow_ctrl);
4869 }
4870
4871 static void bnx2x_set_master_ln(struct link_params *params,
4872                                 struct bnx2x_phy *phy)
4873 {
4874         struct bnx2x *bp = params->bp;
4875         u16 new_master_ln, ser_lane;
4876         ser_lane = ((params->lane_config &
4877                      PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
4878                     PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
4879
4880         /* Set the master_ln for AN */
4881         CL22_RD_OVER_CL45(bp, phy,
4882                           MDIO_REG_BANK_XGXS_BLOCK2,
4883                           MDIO_XGXS_BLOCK2_TEST_MODE_LANE,
4884                           &new_master_ln);
4885
4886         CL22_WR_OVER_CL45(bp, phy,
4887                           MDIO_REG_BANK_XGXS_BLOCK2 ,
4888                           MDIO_XGXS_BLOCK2_TEST_MODE_LANE,
4889                           (new_master_ln | ser_lane));
4890 }
4891
4892 static int bnx2x_reset_unicore(struct link_params *params,
4893                                struct bnx2x_phy *phy,
4894                                u8 set_serdes)
4895 {
4896         struct bnx2x *bp = params->bp;
4897         u16 mii_control;
4898         u16 i;
4899         CL22_RD_OVER_CL45(bp, phy,
4900                           MDIO_REG_BANK_COMBO_IEEE0,
4901                           MDIO_COMBO_IEEE0_MII_CONTROL, &mii_control);
4902
4903         /* Reset the unicore */
4904         CL22_WR_OVER_CL45(bp, phy,
4905                           MDIO_REG_BANK_COMBO_IEEE0,
4906                           MDIO_COMBO_IEEE0_MII_CONTROL,
4907                           (mii_control |
4908                            MDIO_COMBO_IEEO_MII_CONTROL_RESET));
4909         if (set_serdes)
4910                 bnx2x_set_serdes_access(bp, params->port);
4911
4912         /* Wait for the reset to self clear */
4913         for (i = 0; i < MDIO_ACCESS_TIMEOUT; i++) {
4914                 udelay(5);
4915
4916                 /* The reset erased the previous bank value */
4917                 CL22_RD_OVER_CL45(bp, phy,
4918                                   MDIO_REG_BANK_COMBO_IEEE0,
4919                                   MDIO_COMBO_IEEE0_MII_CONTROL,
4920                                   &mii_control);
4921
4922                 if (!(mii_control & MDIO_COMBO_IEEO_MII_CONTROL_RESET)) {
4923                         udelay(5);
4924                         return 0;
4925                 }
4926         }
4927
4928         netdev_err(bp->dev,  "Warning: PHY was not initialized,"
4929                               " Port %d\n",
4930                          params->port);
4931         DP(NETIF_MSG_LINK, "BUG! XGXS is still in reset!\n");
4932         return -EINVAL;
4933
4934 }
4935
4936 static void bnx2x_set_swap_lanes(struct link_params *params,
4937                                  struct bnx2x_phy *phy)
4938 {
4939         struct bnx2x *bp = params->bp;
4940         /* Each two bits represents a lane number:
4941          * No swap is 0123 => 0x1b no need to enable the swap
4942          */
4943         u16 rx_lane_swap, tx_lane_swap;
4944
4945         rx_lane_swap = ((params->lane_config &
4946                          PORT_HW_CFG_LANE_SWAP_CFG_RX_MASK) >>
4947                         PORT_HW_CFG_LANE_SWAP_CFG_RX_SHIFT);
4948         tx_lane_swap = ((params->lane_config &
4949                          PORT_HW_CFG_LANE_SWAP_CFG_TX_MASK) >>
4950                         PORT_HW_CFG_LANE_SWAP_CFG_TX_SHIFT);
4951
4952         if (rx_lane_swap != 0x1b) {
4953                 CL22_WR_OVER_CL45(bp, phy,
4954                                   MDIO_REG_BANK_XGXS_BLOCK2,
4955                                   MDIO_XGXS_BLOCK2_RX_LN_SWAP,
4956                                   (rx_lane_swap |
4957                                    MDIO_XGXS_BLOCK2_RX_LN_SWAP_ENABLE |
4958                                    MDIO_XGXS_BLOCK2_RX_LN_SWAP_FORCE_ENABLE));
4959         } else {
4960                 CL22_WR_OVER_CL45(bp, phy,
4961                                   MDIO_REG_BANK_XGXS_BLOCK2,
4962                                   MDIO_XGXS_BLOCK2_RX_LN_SWAP, 0);
4963         }
4964
4965         if (tx_lane_swap != 0x1b) {
4966                 CL22_WR_OVER_CL45(bp, phy,
4967                                   MDIO_REG_BANK_XGXS_BLOCK2,
4968                                   MDIO_XGXS_BLOCK2_TX_LN_SWAP,
4969                                   (tx_lane_swap |
4970                                    MDIO_XGXS_BLOCK2_TX_LN_SWAP_ENABLE));
4971         } else {
4972                 CL22_WR_OVER_CL45(bp, phy,
4973                                   MDIO_REG_BANK_XGXS_BLOCK2,
4974                                   MDIO_XGXS_BLOCK2_TX_LN_SWAP, 0);
4975         }
4976 }
4977
4978 static void bnx2x_set_parallel_detection(struct bnx2x_phy *phy,
4979                                          struct link_params *params)
4980 {
4981         struct bnx2x *bp = params->bp;
4982         u16 control2;
4983         CL22_RD_OVER_CL45(bp, phy,
4984                           MDIO_REG_BANK_SERDES_DIGITAL,
4985                           MDIO_SERDES_DIGITAL_A_1000X_CONTROL2,
4986                           &control2);
4987         if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)
4988                 control2 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN;
4989         else
4990                 control2 &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN;
4991         DP(NETIF_MSG_LINK, "phy->speed_cap_mask = 0x%x, control2 = 0x%x\n",
4992                 phy->speed_cap_mask, control2);
4993         CL22_WR_OVER_CL45(bp, phy,
4994                           MDIO_REG_BANK_SERDES_DIGITAL,
4995                           MDIO_SERDES_DIGITAL_A_1000X_CONTROL2,
4996                           control2);
4997
4998         if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) &&
4999              (phy->speed_cap_mask &
5000                     PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
5001                 DP(NETIF_MSG_LINK, "XGXS\n");
5002
5003                 CL22_WR_OVER_CL45(bp, phy,
5004                                  MDIO_REG_BANK_10G_PARALLEL_DETECT,
5005                                  MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK,
5006                                  MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK_CNT);
5007
5008                 CL22_RD_OVER_CL45(bp, phy,
5009                                   MDIO_REG_BANK_10G_PARALLEL_DETECT,
5010                                   MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL,
5011                                   &control2);
5012
5013
5014                 control2 |=
5015                     MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL_PARDET10G_EN;
5016
5017                 CL22_WR_OVER_CL45(bp, phy,
5018                                   MDIO_REG_BANK_10G_PARALLEL_DETECT,
5019                                   MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL,
5020                                   control2);
5021
5022                 /* Disable parallel detection of HiG */
5023                 CL22_WR_OVER_CL45(bp, phy,
5024                                   MDIO_REG_BANK_XGXS_BLOCK2,
5025                                   MDIO_XGXS_BLOCK2_UNICORE_MODE_10G,
5026                                   MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_CX4_XGXS |
5027                                   MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_HIGIG_XGXS);
5028         }
5029 }
5030
5031 static void bnx2x_set_autoneg(struct bnx2x_phy *phy,
5032                               struct link_params *params,
5033                               struct link_vars *vars,
5034                               u8 enable_cl73)
5035 {
5036         struct bnx2x *bp = params->bp;
5037         u16 reg_val;
5038
5039         /* CL37 Autoneg */
5040         CL22_RD_OVER_CL45(bp, phy,
5041                           MDIO_REG_BANK_COMBO_IEEE0,
5042                           MDIO_COMBO_IEEE0_MII_CONTROL, &reg_val);
5043
5044         /* CL37 Autoneg Enabled */
5045         if (vars->line_speed == SPEED_AUTO_NEG)
5046                 reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_AN_EN;
5047         else /* CL37 Autoneg Disabled */
5048                 reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
5049                              MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN);
5050
5051         CL22_WR_OVER_CL45(bp, phy,
5052                           MDIO_REG_BANK_COMBO_IEEE0,
5053                           MDIO_COMBO_IEEE0_MII_CONTROL, reg_val);
5054
5055         /* Enable/Disable Autodetection */
5056
5057         CL22_RD_OVER_CL45(bp, phy,
5058                           MDIO_REG_BANK_SERDES_DIGITAL,
5059                           MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, &reg_val);
5060         reg_val &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_SIGNAL_DETECT_EN |
5061                     MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT);
5062         reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE;
5063         if (vars->line_speed == SPEED_AUTO_NEG)
5064                 reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET;
5065         else
5066                 reg_val &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET;
5067
5068         CL22_WR_OVER_CL45(bp, phy,
5069                           MDIO_REG_BANK_SERDES_DIGITAL,
5070                           MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, reg_val);
5071
5072         /* Enable TetonII and BAM autoneg */
5073         CL22_RD_OVER_CL45(bp, phy,
5074                           MDIO_REG_BANK_BAM_NEXT_PAGE,
5075                           MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL,
5076                           &reg_val);
5077         if (vars->line_speed == SPEED_AUTO_NEG) {
5078                 /* Enable BAM aneg Mode and TetonII aneg Mode */
5079                 reg_val |= (MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE |
5080                             MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN);
5081         } else {
5082                 /* TetonII and BAM Autoneg Disabled */
5083                 reg_val &= ~(MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE |
5084                              MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN);
5085         }
5086         CL22_WR_OVER_CL45(bp, phy,
5087                           MDIO_REG_BANK_BAM_NEXT_PAGE,
5088                           MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL,
5089                           reg_val);
5090
5091         if (enable_cl73) {
5092                 /* Enable Cl73 FSM status bits */
5093                 CL22_WR_OVER_CL45(bp, phy,
5094                                   MDIO_REG_BANK_CL73_USERB0,
5095                                   MDIO_CL73_USERB0_CL73_UCTRL,
5096                                   0xe);
5097
5098                 /* Enable BAM Station Manager*/
5099                 CL22_WR_OVER_CL45(bp, phy,
5100                         MDIO_REG_BANK_CL73_USERB0,
5101                         MDIO_CL73_USERB0_CL73_BAM_CTRL1,
5102                         MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_EN |
5103                         MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_STATION_MNGR_EN |
5104                         MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_NP_AFTER_BP_EN);
5105
5106                 /* Advertise CL73 link speeds */
5107                 CL22_RD_OVER_CL45(bp, phy,
5108                                   MDIO_REG_BANK_CL73_IEEEB1,
5109                                   MDIO_CL73_IEEEB1_AN_ADV2,
5110                                   &reg_val);
5111                 if (phy->speed_cap_mask &
5112                     PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
5113                         reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4;
5114                 if (phy->speed_cap_mask &
5115                     PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)
5116                         reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX;
5117
5118                 CL22_WR_OVER_CL45(bp, phy,
5119                                   MDIO_REG_BANK_CL73_IEEEB1,
5120                                   MDIO_CL73_IEEEB1_AN_ADV2,
5121                                   reg_val);
5122
5123                 /* CL73 Autoneg Enabled */
5124                 reg_val = MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN;
5125
5126         } else /* CL73 Autoneg Disabled */
5127                 reg_val = 0;
5128
5129         CL22_WR_OVER_CL45(bp, phy,
5130                           MDIO_REG_BANK_CL73_IEEEB0,
5131                           MDIO_CL73_IEEEB0_CL73_AN_CONTROL, reg_val);
5132 }
5133
5134 /* Program SerDes, forced speed */
5135 static void bnx2x_program_serdes(struct bnx2x_phy *phy,
5136                                  struct link_params *params,
5137                                  struct link_vars *vars)
5138 {
5139         struct bnx2x *bp = params->bp;
5140         u16 reg_val;
5141
5142         /* Program duplex, disable autoneg and sgmii*/
5143         CL22_RD_OVER_CL45(bp, phy,
5144                           MDIO_REG_BANK_COMBO_IEEE0,
5145                           MDIO_COMBO_IEEE0_MII_CONTROL, &reg_val);
5146         reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX |
5147                      MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
5148                      MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK);
5149         if (phy->req_duplex == DUPLEX_FULL)
5150                 reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX;
5151         CL22_WR_OVER_CL45(bp, phy,
5152                           MDIO_REG_BANK_COMBO_IEEE0,
5153                           MDIO_COMBO_IEEE0_MII_CONTROL, reg_val);
5154
5155         /* Program speed
5156          *  - needed only if the speed is greater than 1G (2.5G or 10G)
5157          */
5158         CL22_RD_OVER_CL45(bp, phy,
5159                           MDIO_REG_BANK_SERDES_DIGITAL,
5160                           MDIO_SERDES_DIGITAL_MISC1, &reg_val);
5161         /* Clearing the speed value before setting the right speed */
5162         DP(NETIF_MSG_LINK, "MDIO_REG_BANK_SERDES_DIGITAL = 0x%x\n", reg_val);
5163
5164         reg_val &= ~(MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_MASK |
5165                      MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL);
5166
5167         if (!((vars->line_speed == SPEED_1000) ||
5168               (vars->line_speed == SPEED_100) ||
5169               (vars->line_speed == SPEED_10))) {
5170
5171                 reg_val |= (MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_156_25M |
5172                             MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL);
5173                 if (vars->line_speed == SPEED_10000)
5174                         reg_val |=
5175                                 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_CX4;
5176         }
5177
5178         CL22_WR_OVER_CL45(bp, phy,
5179                           MDIO_REG_BANK_SERDES_DIGITAL,
5180                           MDIO_SERDES_DIGITAL_MISC1, reg_val);
5181
5182 }
5183
5184 static void bnx2x_set_brcm_cl37_advertisement(struct bnx2x_phy *phy,
5185                                               struct link_params *params)
5186 {
5187         struct bnx2x *bp = params->bp;
5188         u16 val = 0;
5189
5190         /* Set extended capabilities */
5191         if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G)
5192                 val |= MDIO_OVER_1G_UP1_2_5G;
5193         if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
5194                 val |= MDIO_OVER_1G_UP1_10G;
5195         CL22_WR_OVER_CL45(bp, phy,
5196                           MDIO_REG_BANK_OVER_1G,
5197                           MDIO_OVER_1G_UP1, val);
5198
5199         CL22_WR_OVER_CL45(bp, phy,
5200                           MDIO_REG_BANK_OVER_1G,
5201                           MDIO_OVER_1G_UP3, 0x400);
5202 }
5203
5204 static void bnx2x_set_ieee_aneg_advertisement(struct bnx2x_phy *phy,
5205                                               struct link_params *params,
5206                                               u16 ieee_fc)
5207 {
5208         struct bnx2x *bp = params->bp;
5209         u16 val;
5210         /* For AN, we are always publishing full duplex */
5211
5212         CL22_WR_OVER_CL45(bp, phy,
5213                           MDIO_REG_BANK_COMBO_IEEE0,
5214                           MDIO_COMBO_IEEE0_AUTO_NEG_ADV, ieee_fc);
5215         CL22_RD_OVER_CL45(bp, phy,
5216                           MDIO_REG_BANK_CL73_IEEEB1,
5217                           MDIO_CL73_IEEEB1_AN_ADV1, &val);
5218         val &= ~MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_BOTH;
5219         val |= ((ieee_fc<<3) & MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK);
5220         CL22_WR_OVER_CL45(bp, phy,
5221                           MDIO_REG_BANK_CL73_IEEEB1,
5222                           MDIO_CL73_IEEEB1_AN_ADV1, val);
5223 }
5224
5225 static void bnx2x_restart_autoneg(struct bnx2x_phy *phy,
5226                                   struct link_params *params,
5227                                   u8 enable_cl73)
5228 {
5229         struct bnx2x *bp = params->bp;
5230         u16 mii_control;
5231
5232         DP(NETIF_MSG_LINK, "bnx2x_restart_autoneg\n");
5233         /* Enable and restart BAM/CL37 aneg */
5234
5235         if (enable_cl73) {
5236                 CL22_RD_OVER_CL45(bp, phy,
5237                                   MDIO_REG_BANK_CL73_IEEEB0,
5238                                   MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
5239                                   &mii_control);
5240
5241                 CL22_WR_OVER_CL45(bp, phy,
5242                                   MDIO_REG_BANK_CL73_IEEEB0,
5243                                   MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
5244                                   (mii_control |
5245                                   MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN |
5246                                   MDIO_CL73_IEEEB0_CL73_AN_CONTROL_RESTART_AN));
5247         } else {
5248
5249                 CL22_RD_OVER_CL45(bp, phy,
5250                                   MDIO_REG_BANK_COMBO_IEEE0,
5251                                   MDIO_COMBO_IEEE0_MII_CONTROL,
5252                                   &mii_control);
5253                 DP(NETIF_MSG_LINK,
5254                          "bnx2x_restart_autoneg mii_control before = 0x%x\n",
5255                          mii_control);
5256                 CL22_WR_OVER_CL45(bp, phy,
5257                                   MDIO_REG_BANK_COMBO_IEEE0,
5258                                   MDIO_COMBO_IEEE0_MII_CONTROL,
5259                                   (mii_control |
5260                                    MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
5261                                    MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN));
5262         }
5263 }
5264
5265 static void bnx2x_initialize_sgmii_process(struct bnx2x_phy *phy,
5266                                            struct link_params *params,
5267                                            struct link_vars *vars)
5268 {
5269         struct bnx2x *bp = params->bp;
5270         u16 control1;
5271
5272         /* In SGMII mode, the unicore is always slave */
5273
5274         CL22_RD_OVER_CL45(bp, phy,
5275                           MDIO_REG_BANK_SERDES_DIGITAL,
5276                           MDIO_SERDES_DIGITAL_A_1000X_CONTROL1,
5277                           &control1);
5278         control1 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT;
5279         /* Set sgmii mode (and not fiber) */
5280         control1 &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE |
5281                       MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET |
5282                       MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_MSTR_MODE);
5283         CL22_WR_OVER_CL45(bp, phy,
5284                           MDIO_REG_BANK_SERDES_DIGITAL,
5285                           MDIO_SERDES_DIGITAL_A_1000X_CONTROL1,
5286                           control1);
5287
5288         /* If forced speed */
5289         if (!(vars->line_speed == SPEED_AUTO_NEG)) {
5290                 /* Set speed, disable autoneg */
5291                 u16 mii_control;
5292
5293                 CL22_RD_OVER_CL45(bp, phy,
5294                                   MDIO_REG_BANK_COMBO_IEEE0,
5295                                   MDIO_COMBO_IEEE0_MII_CONTROL,
5296                                   &mii_control);
5297                 mii_control &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
5298                                  MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK|
5299                                  MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX);
5300
5301                 switch (vars->line_speed) {
5302                 case SPEED_100:
5303                         mii_control |=
5304                                 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_100;
5305                         break;
5306                 case SPEED_1000:
5307                         mii_control |=
5308                                 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_1000;
5309                         break;
5310                 case SPEED_10:
5311                         /* There is nothing to set for 10M */
5312                         break;
5313                 default:
5314                         /* Invalid speed for SGMII */
5315                         DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n",
5316                                   vars->line_speed);
5317                         break;
5318                 }
5319
5320                 /* Setting the full duplex */
5321                 if (phy->req_duplex == DUPLEX_FULL)
5322                         mii_control |=
5323                                 MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX;
5324                 CL22_WR_OVER_CL45(bp, phy,
5325                                   MDIO_REG_BANK_COMBO_IEEE0,
5326                                   MDIO_COMBO_IEEE0_MII_CONTROL,
5327                                   mii_control);
5328
5329         } else { /* AN mode */
5330                 /* Enable and restart AN */
5331                 bnx2x_restart_autoneg(phy, params, 0);
5332         }
5333 }
5334
5335 /* Link management
5336  */
5337 static int bnx2x_direct_parallel_detect_used(struct bnx2x_phy *phy,
5338                                              struct link_params *params)
5339 {
5340         struct bnx2x *bp = params->bp;
5341         u16 pd_10g, status2_1000x;
5342         if (phy->req_line_speed != SPEED_AUTO_NEG)
5343                 return 0;
5344         CL22_RD_OVER_CL45(bp, phy,
5345                           MDIO_REG_BANK_SERDES_DIGITAL,
5346                           MDIO_SERDES_DIGITAL_A_1000X_STATUS2,
5347                           &status2_1000x);
5348         CL22_RD_OVER_CL45(bp, phy,
5349                           MDIO_REG_BANK_SERDES_DIGITAL,
5350                           MDIO_SERDES_DIGITAL_A_1000X_STATUS2,
5351                           &status2_1000x);
5352         if (status2_1000x & MDIO_SERDES_DIGITAL_A_1000X_STATUS2_AN_DISABLED) {
5353                 DP(NETIF_MSG_LINK, "1G parallel detect link on port %d\n",
5354                          params->port);
5355                 return 1;
5356         }
5357
5358         CL22_RD_OVER_CL45(bp, phy,
5359                           MDIO_REG_BANK_10G_PARALLEL_DETECT,
5360                           MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS,
5361                           &pd_10g);
5362
5363         if (pd_10g & MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS_PD_LINK) {
5364                 DP(NETIF_MSG_LINK, "10G parallel detect link on port %d\n",
5365                          params->port);
5366                 return 1;
5367         }
5368         return 0;
5369 }
5370
5371 static void bnx2x_update_adv_fc(struct bnx2x_phy *phy,
5372                                 struct link_params *params,
5373                                 struct link_vars *vars,
5374                                 u32 gp_status)
5375 {
5376         u16 ld_pause;   /* local driver */
5377         u16 lp_pause;   /* link partner */
5378         u16 pause_result;
5379         struct bnx2x *bp = params->bp;
5380         if ((gp_status &
5381              (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE |
5382               MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE)) ==
5383             (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE |
5384              MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE)) {
5385
5386                 CL22_RD_OVER_CL45(bp, phy,
5387                                   MDIO_REG_BANK_CL73_IEEEB1,
5388                                   MDIO_CL73_IEEEB1_AN_ADV1,
5389                                   &ld_pause);
5390                 CL22_RD_OVER_CL45(bp, phy,
5391                                   MDIO_REG_BANK_CL73_IEEEB1,
5392                                   MDIO_CL73_IEEEB1_AN_LP_ADV1,
5393                                   &lp_pause);
5394                 pause_result = (ld_pause &
5395                                 MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK) >> 8;
5396                 pause_result |= (lp_pause &
5397                                  MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_MASK) >> 10;
5398                 DP(NETIF_MSG_LINK, "pause_result CL73 0x%x\n", pause_result);
5399         } else {
5400                 CL22_RD_OVER_CL45(bp, phy,
5401                                   MDIO_REG_BANK_COMBO_IEEE0,
5402                                   MDIO_COMBO_IEEE0_AUTO_NEG_ADV,
5403                                   &ld_pause);
5404                 CL22_RD_OVER_CL45(bp, phy,
5405                         MDIO_REG_BANK_COMBO_IEEE0,
5406                         MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1,
5407                         &lp_pause);
5408                 pause_result = (ld_pause &
5409                                 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK)>>5;
5410                 pause_result |= (lp_pause &
5411                                  MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK)>>7;
5412                 DP(NETIF_MSG_LINK, "pause_result CL37 0x%x\n", pause_result);
5413         }
5414         bnx2x_pause_resolve(phy, params, vars, pause_result);
5415
5416 }
5417
5418 static void bnx2x_flow_ctrl_resolve(struct bnx2x_phy *phy,
5419                                     struct link_params *params,
5420                                     struct link_vars *vars,
5421                                     u32 gp_status)
5422 {
5423         struct bnx2x *bp = params->bp;
5424         vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
5425
5426         /* Resolve from gp_status in case of AN complete and not sgmii */
5427         if (phy->req_flow_ctrl != BNX2X_FLOW_CTRL_AUTO) {
5428                 /* Update the advertised flow-controled of LD/LP in AN */
5429                 if (phy->req_line_speed == SPEED_AUTO_NEG)
5430                         bnx2x_update_adv_fc(phy, params, vars, gp_status);
5431                 /* But set the flow-control result as the requested one */
5432                 vars->flow_ctrl = phy->req_flow_ctrl;
5433         } else if (phy->req_line_speed != SPEED_AUTO_NEG)
5434                 vars->flow_ctrl = params->req_fc_auto_adv;
5435         else if ((gp_status & MDIO_AN_CL73_OR_37_COMPLETE) &&
5436                  (!(vars->phy_flags & PHY_SGMII_FLAG))) {
5437                 if (bnx2x_direct_parallel_detect_used(phy, params)) {
5438                         vars->flow_ctrl = params->req_fc_auto_adv;
5439                         return;
5440                 }
5441                 bnx2x_update_adv_fc(phy, params, vars, gp_status);
5442         }
5443         DP(NETIF_MSG_LINK, "flow_ctrl 0x%x\n", vars->flow_ctrl);
5444 }
5445
5446 static void bnx2x_check_fallback_to_cl37(struct bnx2x_phy *phy,
5447                                          struct link_params *params)
5448 {
5449         struct bnx2x *bp = params->bp;
5450         u16 rx_status, ustat_val, cl37_fsm_received;
5451         DP(NETIF_MSG_LINK, "bnx2x_check_fallback_to_cl37\n");
5452         /* Step 1: Make sure signal is detected */
5453         CL22_RD_OVER_CL45(bp, phy,
5454                           MDIO_REG_BANK_RX0,
5455                           MDIO_RX0_RX_STATUS,
5456                           &rx_status);
5457         if ((rx_status & MDIO_RX0_RX_STATUS_SIGDET) !=
5458             (MDIO_RX0_RX_STATUS_SIGDET)) {
5459                 DP(NETIF_MSG_LINK, "Signal is not detected. Restoring CL73."
5460                              "rx_status(0x80b0) = 0x%x\n", rx_status);
5461                 CL22_WR_OVER_CL45(bp, phy,
5462                                   MDIO_REG_BANK_CL73_IEEEB0,
5463                                   MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
5464                                   MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN);
5465                 return;
5466         }
5467         /* Step 2: Check CL73 state machine */
5468         CL22_RD_OVER_CL45(bp, phy,
5469                           MDIO_REG_BANK_CL73_USERB0,
5470                           MDIO_CL73_USERB0_CL73_USTAT1,
5471                           &ustat_val);
5472         if ((ustat_val &
5473              (MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK |
5474               MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37)) !=
5475             (MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK |
5476               MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37)) {
5477                 DP(NETIF_MSG_LINK, "CL73 state-machine is not stable. "
5478                              "ustat_val(0x8371) = 0x%x\n", ustat_val);
5479                 return;
5480         }
5481         /* Step 3: Check CL37 Message Pages received to indicate LP
5482          * supports only CL37
5483          */
5484         CL22_RD_OVER_CL45(bp, phy,
5485                           MDIO_REG_BANK_REMOTE_PHY,
5486                           MDIO_REMOTE_PHY_MISC_RX_STATUS,
5487                           &cl37_fsm_received);
5488         if ((cl37_fsm_received &
5489              (MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG |
5490              MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) !=
5491             (MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG |
5492               MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) {
5493                 DP(NETIF_MSG_LINK, "No CL37 FSM were received. "
5494                              "misc_rx_status(0x8330) = 0x%x\n",
5495                          cl37_fsm_received);
5496                 return;
5497         }
5498         /* The combined cl37/cl73 fsm state information indicating that
5499          * we are connected to a device which does not support cl73, but
5500          * does support cl37 BAM. In this case we disable cl73 and
5501          * restart cl37 auto-neg
5502          */
5503
5504         /* Disable CL73 */
5505         CL22_WR_OVER_CL45(bp, phy,
5506                           MDIO_REG_BANK_CL73_IEEEB0,
5507                           MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
5508                           0);
5509         /* Restart CL37 autoneg */
5510         bnx2x_restart_autoneg(phy, params, 0);
5511         DP(NETIF_MSG_LINK, "Disabling CL73, and restarting CL37 autoneg\n");
5512 }
5513
5514 static void bnx2x_xgxs_an_resolve(struct bnx2x_phy *phy,
5515                                   struct link_params *params,
5516                                   struct link_vars *vars,
5517                                   u32 gp_status)
5518 {
5519         if (gp_status & MDIO_AN_CL73_OR_37_COMPLETE)
5520                 vars->link_status |=
5521                         LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
5522
5523         if (bnx2x_direct_parallel_detect_used(phy, params))
5524                 vars->link_status |=
5525                         LINK_STATUS_PARALLEL_DETECTION_USED;
5526 }
5527 static int bnx2x_get_link_speed_duplex(struct bnx2x_phy *phy,
5528                                      struct link_params *params,
5529                                       struct link_vars *vars,
5530                                       u16 is_link_up,
5531                                       u16 speed_mask,
5532                                       u16 is_duplex)
5533 {
5534         struct bnx2x *bp = params->bp;
5535         if (phy->req_line_speed == SPEED_AUTO_NEG)
5536                 vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_ENABLED;
5537         if (is_link_up) {
5538                 DP(NETIF_MSG_LINK, "phy link up\n");
5539
5540                 vars->phy_link_up = 1;
5541                 vars->link_status |= LINK_STATUS_LINK_UP;
5542
5543                 switch (speed_mask) {
5544                 case GP_STATUS_10M:
5545                         vars->line_speed = SPEED_10;
5546                         if (is_duplex == DUPLEX_FULL)
5547                                 vars->link_status |= LINK_10TFD;
5548                         else
5549                                 vars->link_status |= LINK_10THD;
5550                         break;
5551
5552                 case GP_STATUS_100M:
5553                         vars->line_speed = SPEED_100;
5554                         if (is_duplex == DUPLEX_FULL)
5555                                 vars->link_status |= LINK_100TXFD;
5556                         else
5557                                 vars->link_status |= LINK_100TXHD;
5558                         break;
5559
5560                 case GP_STATUS_1G:
5561                 case GP_STATUS_1G_KX:
5562                         vars->line_speed = SPEED_1000;
5563                         if (is_duplex == DUPLEX_FULL)
5564                                 vars->link_status |= LINK_1000TFD;
5565                         else
5566                                 vars->link_status |= LINK_1000THD;
5567                         break;
5568
5569                 case GP_STATUS_2_5G:
5570                         vars->line_speed = SPEED_2500;
5571                         if (is_duplex == DUPLEX_FULL)
5572                                 vars->link_status |= LINK_2500TFD;
5573                         else
5574                                 vars->link_status |= LINK_2500THD;
5575                         break;
5576
5577                 case GP_STATUS_5G:
5578                 case GP_STATUS_6G:
5579                         DP(NETIF_MSG_LINK,
5580                                  "link speed unsupported  gp_status 0x%x\n",
5581                                   speed_mask);
5582                         return -EINVAL;
5583
5584                 case GP_STATUS_10G_KX4:
5585                 case GP_STATUS_10G_HIG:
5586                 case GP_STATUS_10G_CX4:
5587                 case GP_STATUS_10G_KR:
5588                 case GP_STATUS_10G_SFI:
5589                 case GP_STATUS_10G_XFI:
5590                         vars->line_speed = SPEED_10000;
5591                         vars->link_status |= LINK_10GTFD;
5592                         break;
5593                 case GP_STATUS_20G_DXGXS:
5594                 case GP_STATUS_20G_KR2:
5595                         vars->line_speed = SPEED_20000;
5596                         vars->link_status |= LINK_20GTFD;
5597                         break;
5598                 default:
5599                         DP(NETIF_MSG_LINK,
5600                                   "link speed unsupported gp_status 0x%x\n",
5601                                   speed_mask);
5602                         return -EINVAL;
5603                 }
5604         } else { /* link_down */
5605                 DP(NETIF_MSG_LINK, "phy link down\n");
5606
5607                 vars->phy_link_up = 0;
5608
5609                 vars->duplex = DUPLEX_FULL;
5610                 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
5611                 vars->mac_type = MAC_TYPE_NONE;
5612         }
5613         DP(NETIF_MSG_LINK, " phy_link_up %x line_speed %d\n",
5614                     vars->phy_link_up, vars->line_speed);
5615         return 0;
5616 }
5617
5618 static u8 bnx2x_link_settings_status(struct bnx2x_phy *phy,
5619                                      struct link_params *params,
5620                                      struct link_vars *vars)
5621 {
5622         struct bnx2x *bp = params->bp;
5623
5624         u16 gp_status, duplex = DUPLEX_HALF, link_up = 0, speed_mask;
5625         int rc = 0;
5626
5627         /* Read gp_status */
5628         CL22_RD_OVER_CL45(bp, phy,
5629                           MDIO_REG_BANK_GP_STATUS,
5630                           MDIO_GP_STATUS_TOP_AN_STATUS1,
5631                           &gp_status);
5632         if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_DUPLEX_STATUS)
5633                 duplex = DUPLEX_FULL;
5634         if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS)
5635                 link_up = 1;
5636         speed_mask = gp_status & GP_STATUS_SPEED_MASK;
5637         DP(NETIF_MSG_LINK, "gp_status 0x%x, is_link_up %d, speed_mask 0x%x\n",
5638                        gp_status, link_up, speed_mask);
5639         rc = bnx2x_get_link_speed_duplex(phy, params, vars, link_up, speed_mask,
5640                                          duplex);
5641         if (rc == -EINVAL)
5642                 return rc;
5643
5644         if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS) {
5645                 if (SINGLE_MEDIA_DIRECT(params)) {
5646                         vars->duplex = duplex;
5647                         bnx2x_flow_ctrl_resolve(phy, params, vars, gp_status);
5648                         if (phy->req_line_speed == SPEED_AUTO_NEG)
5649                                 bnx2x_xgxs_an_resolve(phy, params, vars,
5650                                                       gp_status);
5651                 }
5652         } else { /* Link_down */
5653                 if ((phy->req_line_speed == SPEED_AUTO_NEG) &&
5654                     SINGLE_MEDIA_DIRECT(params)) {
5655                         /* Check signal is detected */
5656                         bnx2x_check_fallback_to_cl37(phy, params);
5657                 }
5658         }
5659
5660         /* Read LP advertised speeds*/
5661         if (SINGLE_MEDIA_DIRECT(params) &&
5662             (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE)) {
5663                 u16 val;
5664
5665                 CL22_RD_OVER_CL45(bp, phy, MDIO_REG_BANK_CL73_IEEEB1,
5666                                   MDIO_CL73_IEEEB1_AN_LP_ADV2, &val);
5667
5668                 if (val & MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX)
5669                         vars->link_status |=
5670                                 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;
5671                 if (val & (MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4 |
5672                            MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KR))
5673                         vars->link_status |=
5674                                 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
5675
5676                 CL22_RD_OVER_CL45(bp, phy, MDIO_REG_BANK_OVER_1G,
5677                                   MDIO_OVER_1G_LP_UP1, &val);
5678
5679                 if (val & MDIO_OVER_1G_UP1_2_5G)
5680                         vars->link_status |=
5681                                 LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE;
5682                 if (val & (MDIO_OVER_1G_UP1_10G | MDIO_OVER_1G_UP1_10GH))
5683                         vars->link_status |=
5684                                 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
5685         }
5686
5687         DP(NETIF_MSG_LINK, "duplex %x  flow_ctrl 0x%x link_status 0x%x\n",
5688                    vars->duplex, vars->flow_ctrl, vars->link_status);
5689         return rc;
5690 }
5691
5692 static u8 bnx2x_warpcore_read_status(struct bnx2x_phy *phy,
5693                                      struct link_params *params,
5694                                      struct link_vars *vars)
5695 {
5696         struct bnx2x *bp = params->bp;
5697         u8 lane;
5698         u16 gp_status1, gp_speed, link_up, duplex = DUPLEX_FULL;
5699         int rc = 0;
5700         lane = bnx2x_get_warpcore_lane(phy, params);
5701         /* Read gp_status */
5702         if ((params->loopback_mode) &&
5703             (phy->flags & FLAGS_WC_DUAL_MODE)) {
5704                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5705                                 MDIO_WC_REG_DIGITAL5_LINK_STATUS, &link_up);
5706                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5707                                 MDIO_WC_REG_DIGITAL5_LINK_STATUS, &link_up);
5708                 link_up &= 0x1;
5709         } else if ((phy->req_line_speed > SPEED_10000) &&
5710                 (phy->supported & SUPPORTED_20000baseMLD2_Full)) {
5711                 u16 temp_link_up;
5712                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5713                                 1, &temp_link_up);
5714                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5715                                 1, &link_up);
5716                 DP(NETIF_MSG_LINK, "PCS RX link status = 0x%x-->0x%x\n",
5717                                temp_link_up, link_up);
5718                 link_up &= (1<<2);
5719                 if (link_up)
5720                         bnx2x_ext_phy_resolve_fc(phy, params, vars);
5721         } else {
5722                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5723                                 MDIO_WC_REG_GP2_STATUS_GP_2_1,
5724                                 &gp_status1);
5725                 DP(NETIF_MSG_LINK, "0x81d1 = 0x%x\n", gp_status1);
5726                 /* Check for either KR, 1G, or AN up. */
5727                 link_up = ((gp_status1 >> 8) |
5728                            (gp_status1 >> 12) |
5729                            (gp_status1)) &
5730                         (1 << lane);
5731                 if (phy->supported & SUPPORTED_20000baseKR2_Full) {
5732                         u16 an_link;
5733                         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
5734                                         MDIO_AN_REG_STATUS, &an_link);
5735                         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
5736                                         MDIO_AN_REG_STATUS, &an_link);
5737                         link_up |= (an_link & (1<<2));
5738                 }
5739                 if (link_up && SINGLE_MEDIA_DIRECT(params)) {
5740                         u16 pd, gp_status4;
5741                         if (phy->req_line_speed == SPEED_AUTO_NEG) {
5742                                 /* Check Autoneg complete */
5743                                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5744                                                 MDIO_WC_REG_GP2_STATUS_GP_2_4,
5745                                                 &gp_status4);
5746                                 if (gp_status4 & ((1<<12)<<lane))
5747                                         vars->link_status |=
5748                                         LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
5749
5750                                 /* Check parallel detect used */
5751                                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5752                                                 MDIO_WC_REG_PAR_DET_10G_STATUS,
5753                                                 &pd);
5754                                 if (pd & (1<<15))
5755                                         vars->link_status |=
5756                                         LINK_STATUS_PARALLEL_DETECTION_USED;
5757                         }
5758                         bnx2x_ext_phy_resolve_fc(phy, params, vars);
5759                         vars->duplex = duplex;
5760                 }
5761         }
5762
5763         if ((vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) &&
5764             SINGLE_MEDIA_DIRECT(params)) {
5765                 u16 val;
5766
5767                 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
5768                                 MDIO_AN_REG_LP_AUTO_NEG2, &val);
5769
5770                 if (val & MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX)
5771                         vars->link_status |=
5772                                 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;
5773                 if (val & (MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4 |
5774                            MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KR))
5775                         vars->link_status |=
5776                                 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
5777
5778                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5779                                 MDIO_WC_REG_DIGITAL3_LP_UP1, &val);
5780
5781                 if (val & MDIO_OVER_1G_UP1_2_5G)
5782                         vars->link_status |=
5783                                 LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE;
5784                 if (val & (MDIO_OVER_1G_UP1_10G | MDIO_OVER_1G_UP1_10GH))
5785                         vars->link_status |=
5786                                 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
5787
5788         }
5789
5790
5791         if (lane < 2) {
5792                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5793                                 MDIO_WC_REG_GP2_STATUS_GP_2_2, &gp_speed);
5794         } else {
5795                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5796                                 MDIO_WC_REG_GP2_STATUS_GP_2_3, &gp_speed);
5797         }
5798         DP(NETIF_MSG_LINK, "lane %d gp_speed 0x%x\n", lane, gp_speed);
5799
5800         if ((lane & 1) == 0)
5801                 gp_speed <<= 8;
5802         gp_speed &= 0x3f00;
5803         link_up = !!link_up;
5804
5805         rc = bnx2x_get_link_speed_duplex(phy, params, vars, link_up, gp_speed,
5806                                          duplex);
5807
5808         /* In case of KR link down, start up the recovering procedure */
5809         if ((!link_up) && (phy->media_type == ETH_PHY_KR) &&
5810             (!(phy->flags & FLAGS_WC_DUAL_MODE)))
5811                 vars->rx_tx_asic_rst = MAX_KR_LINK_RETRY;
5812
5813         DP(NETIF_MSG_LINK, "duplex %x  flow_ctrl 0x%x link_status 0x%x\n",
5814                    vars->duplex, vars->flow_ctrl, vars->link_status);
5815         return rc;
5816 }
5817 static void bnx2x_set_gmii_tx_driver(struct link_params *params)
5818 {
5819         struct bnx2x *bp = params->bp;
5820         struct bnx2x_phy *phy = &params->phy[INT_PHY];
5821         u16 lp_up2;
5822         u16 tx_driver;
5823         u16 bank;
5824
5825         /* Read precomp */
5826         CL22_RD_OVER_CL45(bp, phy,
5827                           MDIO_REG_BANK_OVER_1G,
5828                           MDIO_OVER_1G_LP_UP2, &lp_up2);
5829
5830         /* Bits [10:7] at lp_up2, positioned at [15:12] */
5831         lp_up2 = (((lp_up2 & MDIO_OVER_1G_LP_UP2_PREEMPHASIS_MASK) >>
5832                    MDIO_OVER_1G_LP_UP2_PREEMPHASIS_SHIFT) <<
5833                   MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT);
5834
5835         if (lp_up2 == 0)
5836                 return;
5837
5838         for (bank = MDIO_REG_BANK_TX0; bank <= MDIO_REG_BANK_TX3;
5839               bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0)) {
5840                 CL22_RD_OVER_CL45(bp, phy,
5841                                   bank,
5842                                   MDIO_TX0_TX_DRIVER, &tx_driver);
5843
5844                 /* Replace tx_driver bits [15:12] */
5845                 if (lp_up2 !=
5846                     (tx_driver & MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK)) {
5847                         tx_driver &= ~MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK;
5848                         tx_driver |= lp_up2;
5849                         CL22_WR_OVER_CL45(bp, phy,
5850                                           bank,
5851                                           MDIO_TX0_TX_DRIVER, tx_driver);
5852                 }
5853         }
5854 }
5855
5856 static int bnx2x_emac_program(struct link_params *params,
5857                               struct link_vars *vars)
5858 {
5859         struct bnx2x *bp = params->bp;
5860         u8 port = params->port;
5861         u16 mode = 0;
5862
5863         DP(NETIF_MSG_LINK, "setting link speed & duplex\n");
5864         bnx2x_bits_dis(bp, GRCBASE_EMAC0 + port*0x400 +
5865                        EMAC_REG_EMAC_MODE,
5866                        (EMAC_MODE_25G_MODE |
5867                         EMAC_MODE_PORT_MII_10M |
5868                         EMAC_MODE_HALF_DUPLEX));
5869         switch (vars->line_speed) {
5870         case SPEED_10:
5871                 mode |= EMAC_MODE_PORT_MII_10M;
5872                 break;
5873
5874         case SPEED_100:
5875                 mode |= EMAC_MODE_PORT_MII;
5876                 break;
5877
5878         case SPEED_1000:
5879                 mode |= EMAC_MODE_PORT_GMII;
5880                 break;
5881
5882         case SPEED_2500:
5883                 mode |= (EMAC_MODE_25G_MODE | EMAC_MODE_PORT_GMII);
5884                 break;
5885
5886         default:
5887                 /* 10G not valid for EMAC */
5888                 DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n",
5889                            vars->line_speed);
5890                 return -EINVAL;
5891         }
5892
5893         if (vars->duplex == DUPLEX_HALF)
5894                 mode |= EMAC_MODE_HALF_DUPLEX;
5895         bnx2x_bits_en(bp,
5896                       GRCBASE_EMAC0 + port*0x400 + EMAC_REG_EMAC_MODE,
5897                       mode);
5898
5899         bnx2x_set_led(params, vars, LED_MODE_OPER, vars->line_speed);
5900         return 0;
5901 }
5902
5903 static void bnx2x_set_preemphasis(struct bnx2x_phy *phy,
5904                                   struct link_params *params)
5905 {
5906
5907         u16 bank, i = 0;
5908         struct bnx2x *bp = params->bp;
5909
5910         for (bank = MDIO_REG_BANK_RX0, i = 0; bank <= MDIO_REG_BANK_RX3;
5911               bank += (MDIO_REG_BANK_RX1-MDIO_REG_BANK_RX0), i++) {
5912                         CL22_WR_OVER_CL45(bp, phy,
5913                                           bank,
5914                                           MDIO_RX0_RX_EQ_BOOST,
5915                                           phy->rx_preemphasis[i]);
5916         }
5917
5918         for (bank = MDIO_REG_BANK_TX0, i = 0; bank <= MDIO_REG_BANK_TX3;
5919                       bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0), i++) {
5920                         CL22_WR_OVER_CL45(bp, phy,
5921                                           bank,
5922                                           MDIO_TX0_TX_DRIVER,
5923                                           phy->tx_preemphasis[i]);
5924         }
5925 }
5926
5927 static void bnx2x_xgxs_config_init(struct bnx2x_phy *phy,
5928                                    struct link_params *params,
5929                                    struct link_vars *vars)
5930 {
5931         struct bnx2x *bp = params->bp;
5932         u8 enable_cl73 = (SINGLE_MEDIA_DIRECT(params) ||
5933                           (params->loopback_mode == LOOPBACK_XGXS));
5934         if (!(vars->phy_flags & PHY_SGMII_FLAG)) {
5935                 if (SINGLE_MEDIA_DIRECT(params) &&
5936                     (params->feature_config_flags &
5937                      FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED))
5938                         bnx2x_set_preemphasis(phy, params);
5939
5940                 /* Forced speed requested? */
5941                 if (vars->line_speed != SPEED_AUTO_NEG ||
5942                     (SINGLE_MEDIA_DIRECT(params) &&
5943                      params->loopback_mode == LOOPBACK_EXT)) {
5944                         DP(NETIF_MSG_LINK, "not SGMII, no AN\n");
5945
5946                         /* Disable autoneg */
5947                         bnx2x_set_autoneg(phy, params, vars, 0);
5948
5949                         /* Program speed and duplex */
5950                         bnx2x_program_serdes(phy, params, vars);
5951
5952                 } else { /* AN_mode */
5953                         DP(NETIF_MSG_LINK, "not SGMII, AN\n");
5954
5955                         /* AN enabled */
5956                         bnx2x_set_brcm_cl37_advertisement(phy, params);
5957
5958                         /* Program duplex & pause advertisement (for aneg) */
5959                         bnx2x_set_ieee_aneg_advertisement(phy, params,
5960                                                           vars->ieee_fc);
5961
5962                         /* Enable autoneg */
5963                         bnx2x_set_autoneg(phy, params, vars, enable_cl73);
5964
5965                         /* Enable and restart AN */
5966                         bnx2x_restart_autoneg(phy, params, enable_cl73);
5967                 }
5968
5969         } else { /* SGMII mode */
5970                 DP(NETIF_MSG_LINK, "SGMII\n");
5971
5972                 bnx2x_initialize_sgmii_process(phy, params, vars);
5973         }
5974 }
5975
5976 static int bnx2x_prepare_xgxs(struct bnx2x_phy *phy,
5977                           struct link_params *params,
5978                           struct link_vars *vars)
5979 {
5980         int rc;
5981         vars->phy_flags |= PHY_XGXS_FLAG;
5982         if ((phy->req_line_speed &&
5983              ((phy->req_line_speed == SPEED_100) ||
5984               (phy->req_line_speed == SPEED_10))) ||
5985             (!phy->req_line_speed &&
5986              (phy->speed_cap_mask >=
5987               PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL) &&
5988              (phy->speed_cap_mask <
5989               PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
5990             (phy->type == PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT_SD))
5991                 vars->phy_flags |= PHY_SGMII_FLAG;
5992         else
5993                 vars->phy_flags &= ~PHY_SGMII_FLAG;
5994
5995         bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
5996         bnx2x_set_aer_mmd(params, phy);
5997         if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
5998                 bnx2x_set_master_ln(params, phy);
5999
6000         rc = bnx2x_reset_unicore(params, phy, 0);
6001         /* Reset the SerDes and wait for reset bit return low */
6002         if (rc)
6003                 return rc;
6004
6005         bnx2x_set_aer_mmd(params, phy);
6006         /* Setting the masterLn_def again after the reset */
6007         if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) {
6008                 bnx2x_set_master_ln(params, phy);
6009                 bnx2x_set_swap_lanes(params, phy);
6010         }
6011
6012         return rc;
6013 }
6014
6015 static u16 bnx2x_wait_reset_complete(struct bnx2x *bp,
6016                                      struct bnx2x_phy *phy,
6017                                      struct link_params *params)
6018 {
6019         u16 cnt, ctrl;
6020         /* Wait for soft reset to get cleared up to 1 sec */
6021         for (cnt = 0; cnt < 1000; cnt++) {
6022                 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE)
6023                         bnx2x_cl22_read(bp, phy,
6024                                 MDIO_PMA_REG_CTRL, &ctrl);
6025                 else
6026                         bnx2x_cl45_read(bp, phy,
6027                                 MDIO_PMA_DEVAD,
6028                                 MDIO_PMA_REG_CTRL, &ctrl);
6029                 if (!(ctrl & (1<<15)))
6030                         break;
6031                 usleep_range(1000, 2000);
6032         }
6033
6034         if (cnt == 1000)
6035                 netdev_err(bp->dev,  "Warning: PHY was not initialized,"
6036                                       " Port %d\n",
6037                          params->port);
6038         DP(NETIF_MSG_LINK, "control reg 0x%x (after %d ms)\n", ctrl, cnt);
6039         return cnt;
6040 }
6041
6042 static void bnx2x_link_int_enable(struct link_params *params)
6043 {
6044         u8 port = params->port;
6045         u32 mask;
6046         struct bnx2x *bp = params->bp;
6047
6048         /* Setting the status to report on link up for either XGXS or SerDes */
6049         if (CHIP_IS_E3(bp)) {
6050                 mask = NIG_MASK_XGXS0_LINK_STATUS;
6051                 if (!(SINGLE_MEDIA_DIRECT(params)))
6052                         mask |= NIG_MASK_MI_INT;
6053         } else if (params->switch_cfg == SWITCH_CFG_10G) {
6054                 mask = (NIG_MASK_XGXS0_LINK10G |
6055                         NIG_MASK_XGXS0_LINK_STATUS);
6056                 DP(NETIF_MSG_LINK, "enabled XGXS interrupt\n");
6057                 if (!(SINGLE_MEDIA_DIRECT(params)) &&
6058                         params->phy[INT_PHY].type !=
6059                                 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) {
6060                         mask |= NIG_MASK_MI_INT;
6061                         DP(NETIF_MSG_LINK, "enabled external phy int\n");
6062                 }
6063
6064         } else { /* SerDes */
6065                 mask = NIG_MASK_SERDES0_LINK_STATUS;
6066                 DP(NETIF_MSG_LINK, "enabled SerDes interrupt\n");
6067                 if (!(SINGLE_MEDIA_DIRECT(params)) &&
6068                         params->phy[INT_PHY].type !=
6069                                 PORT_HW_CFG_SERDES_EXT_PHY_TYPE_NOT_CONN) {
6070                         mask |= NIG_MASK_MI_INT;
6071                         DP(NETIF_MSG_LINK, "enabled external phy int\n");
6072                 }
6073         }
6074         bnx2x_bits_en(bp,
6075                       NIG_REG_MASK_INTERRUPT_PORT0 + port*4,
6076                       mask);
6077
6078         DP(NETIF_MSG_LINK, "port %x, is_xgxs %x, int_status 0x%x\n", port,
6079                  (params->switch_cfg == SWITCH_CFG_10G),
6080                  REG_RD(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4));
6081         DP(NETIF_MSG_LINK, " int_mask 0x%x, MI_INT %x, SERDES_LINK %x\n",
6082                  REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4),
6083                  REG_RD(bp, NIG_REG_EMAC0_STATUS_MISC_MI_INT + port*0x18),
6084                  REG_RD(bp, NIG_REG_SERDES0_STATUS_LINK_STATUS+port*0x3c));
6085         DP(NETIF_MSG_LINK, " 10G %x, XGXS_LINK %x\n",
6086            REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68),
6087            REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68));
6088 }
6089
6090 static void bnx2x_rearm_latch_signal(struct bnx2x *bp, u8 port,
6091                                      u8 exp_mi_int)
6092 {
6093         u32 latch_status = 0;
6094
6095         /* Disable the MI INT ( external phy int ) by writing 1 to the
6096          * status register. Link down indication is high-active-signal,
6097          * so in this case we need to write the status to clear the XOR
6098          */
6099         /* Read Latched signals */
6100         latch_status = REG_RD(bp,
6101                                     NIG_REG_LATCH_STATUS_0 + port*8);
6102         DP(NETIF_MSG_LINK, "latch_status = 0x%x\n", latch_status);
6103         /* Handle only those with latched-signal=up.*/
6104         if (exp_mi_int)
6105                 bnx2x_bits_en(bp,
6106                               NIG_REG_STATUS_INTERRUPT_PORT0
6107                               + port*4,
6108                               NIG_STATUS_EMAC0_MI_INT);
6109         else
6110                 bnx2x_bits_dis(bp,
6111                                NIG_REG_STATUS_INTERRUPT_PORT0
6112                                + port*4,
6113                                NIG_STATUS_EMAC0_MI_INT);
6114
6115         if (latch_status & 1) {
6116
6117                 /* For all latched-signal=up : Re-Arm Latch signals */
6118                 REG_WR(bp, NIG_REG_LATCH_STATUS_0 + port*8,
6119                        (latch_status & 0xfffe) | (latch_status & 1));
6120         }
6121         /* For all latched-signal=up,Write original_signal to status */
6122 }
6123
6124 static void bnx2x_link_int_ack(struct link_params *params,
6125                                struct link_vars *vars, u8 is_10g_plus)
6126 {
6127         struct bnx2x *bp = params->bp;
6128         u8 port = params->port;
6129         u32 mask;
6130         /* First reset all status we assume only one line will be
6131          * change at a time
6132          */
6133         bnx2x_bits_dis(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
6134                        (NIG_STATUS_XGXS0_LINK10G |
6135                         NIG_STATUS_XGXS0_LINK_STATUS |
6136                         NIG_STATUS_SERDES0_LINK_STATUS));
6137         if (vars->phy_link_up) {
6138                 if (USES_WARPCORE(bp))
6139                         mask = NIG_STATUS_XGXS0_LINK_STATUS;
6140                 else {
6141                         if (is_10g_plus)
6142                                 mask = NIG_STATUS_XGXS0_LINK10G;
6143                         else if (params->switch_cfg == SWITCH_CFG_10G) {
6144                                 /* Disable the link interrupt by writing 1 to
6145                                  * the relevant lane in the status register
6146                                  */
6147                                 u32 ser_lane =
6148                                         ((params->lane_config &
6149                                     PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
6150                                     PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
6151                                 mask = ((1 << ser_lane) <<
6152                                        NIG_STATUS_XGXS0_LINK_STATUS_SIZE);
6153                         } else
6154                                 mask = NIG_STATUS_SERDES0_LINK_STATUS;
6155                 }
6156                 DP(NETIF_MSG_LINK, "Ack link up interrupt with mask 0x%x\n",
6157                                mask);
6158                 bnx2x_bits_en(bp,
6159                               NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
6160                               mask);
6161         }
6162 }
6163
6164 static int bnx2x_null_format_ver(u32 spirom_ver, u8 *str, u16 *len)
6165 {
6166         str[0] = '\0';
6167         (*len)--;
6168         return 0;
6169 }
6170
6171 static int bnx2x_format_ver(u32 num, u8 *str, u16 *len)
6172 {
6173         u16 ret;
6174
6175         if (*len < 10) {
6176                 /* Need more than 10chars for this format */
6177                 bnx2x_null_format_ver(num, str, len);
6178                 return -EINVAL;
6179         }
6180
6181         ret = scnprintf(str, *len, "%hx.%hx", num >> 16, num);
6182         *len -= ret;
6183         return 0;
6184 }
6185
6186 static int bnx2x_3_seq_format_ver(u32 num, u8 *str, u16 *len)
6187 {
6188         u16 ret;
6189
6190         if (*len < 10) {
6191                 /* Need more than 10chars for this format */
6192                 bnx2x_null_format_ver(num, str, len);
6193                 return -EINVAL;
6194         }
6195
6196         ret = scnprintf(str, *len, "%hhx.%hhx.%hhx", num >> 16, num >> 8, num);
6197         *len -= ret;
6198         return 0;
6199 }
6200
6201 int bnx2x_get_ext_phy_fw_version(struct link_params *params, u8 *version,
6202                                  u16 len)
6203 {
6204         struct bnx2x *bp;
6205         u32 spirom_ver = 0;
6206         int status = 0;
6207         u8 *ver_p = version;
6208         u16 remain_len = len;
6209         if (version == NULL || params == NULL)
6210                 return -EINVAL;
6211         bp = params->bp;
6212
6213         /* Extract first external phy*/
6214         version[0] = '\0';
6215         spirom_ver = REG_RD(bp, params->phy[EXT_PHY1].ver_addr);
6216
6217         if (params->phy[EXT_PHY1].format_fw_ver) {
6218                 status |= params->phy[EXT_PHY1].format_fw_ver(spirom_ver,
6219                                                               ver_p,
6220                                                               &remain_len);
6221                 ver_p += (len - remain_len);
6222         }
6223         if ((params->num_phys == MAX_PHYS) &&
6224             (params->phy[EXT_PHY2].ver_addr != 0)) {
6225                 spirom_ver = REG_RD(bp, params->phy[EXT_PHY2].ver_addr);
6226                 if (params->phy[EXT_PHY2].format_fw_ver) {
6227                         *ver_p = '/';
6228                         ver_p++;
6229                         remain_len--;
6230                         status |= params->phy[EXT_PHY2].format_fw_ver(
6231                                 spirom_ver,
6232                                 ver_p,
6233                                 &remain_len);
6234                         ver_p = version + (len - remain_len);
6235                 }
6236         }
6237         *ver_p = '\0';
6238         return status;
6239 }
6240
6241 static void bnx2x_set_xgxs_loopback(struct bnx2x_phy *phy,
6242                                     struct link_params *params)
6243 {
6244         u8 port = params->port;
6245         struct bnx2x *bp = params->bp;
6246
6247         if (phy->req_line_speed != SPEED_1000) {
6248                 u32 md_devad = 0;
6249
6250                 DP(NETIF_MSG_LINK, "XGXS 10G loopback enable\n");
6251
6252                 if (!CHIP_IS_E3(bp)) {
6253                         /* Change the uni_phy_addr in the nig */
6254                         md_devad = REG_RD(bp, (NIG_REG_XGXS0_CTRL_MD_DEVAD +
6255                                                port*0x18));
6256
6257                         REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18,
6258                                0x5);
6259                 }
6260
6261                 bnx2x_cl45_write(bp, phy,
6262                                  5,
6263                                  (MDIO_REG_BANK_AER_BLOCK +
6264                                   (MDIO_AER_BLOCK_AER_REG & 0xf)),
6265                                  0x2800);
6266
6267                 bnx2x_cl45_write(bp, phy,
6268                                  5,
6269                                  (MDIO_REG_BANK_CL73_IEEEB0 +
6270                                   (MDIO_CL73_IEEEB0_CL73_AN_CONTROL & 0xf)),
6271                                  0x6041);
6272                 msleep(200);
6273                 /* Set aer mmd back */
6274                 bnx2x_set_aer_mmd(params, phy);
6275
6276                 if (!CHIP_IS_E3(bp)) {
6277                         /* And md_devad */
6278                         REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18,
6279                                md_devad);
6280                 }
6281         } else {
6282                 u16 mii_ctrl;
6283                 DP(NETIF_MSG_LINK, "XGXS 1G loopback enable\n");
6284                 bnx2x_cl45_read(bp, phy, 5,
6285                                 (MDIO_REG_BANK_COMBO_IEEE0 +
6286                                 (MDIO_COMBO_IEEE0_MII_CONTROL & 0xf)),
6287                                 &mii_ctrl);
6288                 bnx2x_cl45_write(bp, phy, 5,
6289                                  (MDIO_REG_BANK_COMBO_IEEE0 +
6290                                  (MDIO_COMBO_IEEE0_MII_CONTROL & 0xf)),
6291                                  mii_ctrl |
6292                                  MDIO_COMBO_IEEO_MII_CONTROL_LOOPBACK);
6293         }
6294 }
6295
6296 int bnx2x_set_led(struct link_params *params,
6297                   struct link_vars *vars, u8 mode, u32 speed)
6298 {
6299         u8 port = params->port;
6300         u16 hw_led_mode = params->hw_led_mode;
6301         int rc = 0;
6302         u8 phy_idx;
6303         u32 tmp;
6304         u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
6305         struct bnx2x *bp = params->bp;
6306         DP(NETIF_MSG_LINK, "bnx2x_set_led: port %x, mode %d\n", port, mode);
6307         DP(NETIF_MSG_LINK, "speed 0x%x, hw_led_mode 0x%x\n",
6308                  speed, hw_led_mode);
6309         /* In case */
6310         for (phy_idx = EXT_PHY1; phy_idx < MAX_PHYS; phy_idx++) {
6311                 if (params->phy[phy_idx].set_link_led) {
6312                         params->phy[phy_idx].set_link_led(
6313                                 &params->phy[phy_idx], params, mode);
6314                 }
6315         }
6316
6317         switch (mode) {
6318         case LED_MODE_FRONT_PANEL_OFF:
6319         case LED_MODE_OFF:
6320                 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 0);
6321                 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4,
6322                        SHARED_HW_CFG_LED_MAC1);
6323
6324                 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
6325                 if (params->phy[EXT_PHY1].type ==
6326                         PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE)
6327                         tmp &= ~(EMAC_LED_1000MB_OVERRIDE |
6328                                 EMAC_LED_100MB_OVERRIDE |
6329                                 EMAC_LED_10MB_OVERRIDE);
6330                 else
6331                         tmp |= EMAC_LED_OVERRIDE;
6332
6333                 EMAC_WR(bp, EMAC_REG_EMAC_LED, tmp);
6334                 break;
6335
6336         case LED_MODE_OPER:
6337                 /* For all other phys, OPER mode is same as ON, so in case
6338                  * link is down, do nothing
6339                  */
6340                 if (!vars->link_up)
6341                         break;
6342                 fallthrough;
6343         case LED_MODE_ON:
6344                 if (((params->phy[EXT_PHY1].type ==
6345                           PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727) ||
6346                          (params->phy[EXT_PHY1].type ==
6347                           PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722)) &&
6348                     CHIP_IS_E2(bp) && params->num_phys == 2) {
6349                         /* This is a work-around for E2+8727 Configurations */
6350                         if (mode == LED_MODE_ON ||
6351                                 speed == SPEED_10000){
6352                                 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0);
6353                                 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 1);
6354
6355                                 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
6356                                 EMAC_WR(bp, EMAC_REG_EMAC_LED,
6357                                         (tmp | EMAC_LED_OVERRIDE));
6358                                 /* Return here without enabling traffic
6359                                  * LED blink and setting rate in ON mode.
6360                                  * In oper mode, enabling LED blink
6361                                  * and setting rate is needed.
6362                                  */
6363                                 if (mode == LED_MODE_ON)
6364                                         return rc;
6365                         }
6366                 } else if (SINGLE_MEDIA_DIRECT(params)) {
6367                         /* This is a work-around for HW issue found when link
6368                          * is up in CL73
6369                          */
6370                         if ((!CHIP_IS_E3(bp)) ||
6371                             (CHIP_IS_E3(bp) &&
6372                              mode == LED_MODE_ON))
6373                                 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 1);
6374
6375                         if (CHIP_IS_E1x(bp) ||
6376                             CHIP_IS_E2(bp) ||
6377                             (mode == LED_MODE_ON))
6378                                 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0);
6379                         else
6380                                 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4,
6381                                        hw_led_mode);
6382                 } else if ((params->phy[EXT_PHY1].type ==
6383                             PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE) &&
6384                            (mode == LED_MODE_ON)) {
6385                         REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0);
6386                         tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
6387                         EMAC_WR(bp, EMAC_REG_EMAC_LED, tmp |
6388                                 EMAC_LED_OVERRIDE | EMAC_LED_1000MB_OVERRIDE);
6389                         /* Break here; otherwise, it'll disable the
6390                          * intended override.
6391                          */
6392                         break;
6393                 } else {
6394                         u32 nig_led_mode = ((params->hw_led_mode <<
6395                                              SHARED_HW_CFG_LED_MODE_SHIFT) ==
6396                                             SHARED_HW_CFG_LED_EXTPHY2) ?
6397                                 (SHARED_HW_CFG_LED_PHY1 >>
6398                                  SHARED_HW_CFG_LED_MODE_SHIFT) : hw_led_mode;
6399                         REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4,
6400                                nig_led_mode);
6401                 }
6402
6403                 REG_WR(bp, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 + port*4, 0);
6404                 /* Set blinking rate to ~15.9Hz */
6405                 if (CHIP_IS_E3(bp))
6406                         REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_P0 + port*4,
6407                                LED_BLINK_RATE_VAL_E3);
6408                 else
6409                         REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_P0 + port*4,
6410                                LED_BLINK_RATE_VAL_E1X_E2);
6411                 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_ENA_P0 +
6412                        port*4, 1);
6413                 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
6414                 EMAC_WR(bp, EMAC_REG_EMAC_LED,
6415                         (tmp & (~EMAC_LED_OVERRIDE)));
6416
6417                 if (CHIP_IS_E1(bp) &&
6418                     ((speed == SPEED_2500) ||
6419                      (speed == SPEED_1000) ||
6420                      (speed == SPEED_100) ||
6421                      (speed == SPEED_10))) {
6422                         /* For speeds less than 10G LED scheme is different */
6423                         REG_WR(bp, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0
6424                                + port*4, 1);
6425                         REG_WR(bp, NIG_REG_LED_CONTROL_TRAFFIC_P0 +
6426                                port*4, 0);
6427                         REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_TRAFFIC_P0 +
6428                                port*4, 1);
6429                 }
6430                 break;
6431
6432         default:
6433                 rc = -EINVAL;
6434                 DP(NETIF_MSG_LINK, "bnx2x_set_led: Invalid led mode %d\n",
6435                          mode);
6436                 break;
6437         }
6438         return rc;
6439
6440 }
6441
6442 /* This function comes to reflect the actual link state read DIRECTLY from the
6443  * HW
6444  */
6445 int bnx2x_test_link(struct link_params *params, struct link_vars *vars,
6446                     u8 is_serdes)
6447 {
6448         struct bnx2x *bp = params->bp;
6449         u16 gp_status = 0, phy_index = 0;
6450         u8 ext_phy_link_up = 0, serdes_phy_type;
6451         struct link_vars temp_vars;
6452         struct bnx2x_phy *int_phy = &params->phy[INT_PHY];
6453
6454         if (CHIP_IS_E3(bp)) {
6455                 u16 link_up;
6456                 if (params->req_line_speed[LINK_CONFIG_IDX(INT_PHY)]
6457                     > SPEED_10000) {
6458                         /* Check 20G link */
6459                         bnx2x_cl45_read(bp, int_phy, MDIO_WC_DEVAD,
6460                                         1, &link_up);
6461                         bnx2x_cl45_read(bp, int_phy, MDIO_WC_DEVAD,
6462                                         1, &link_up);
6463                         link_up &= (1<<2);
6464                 } else {
6465                         /* Check 10G link and below*/
6466                         u8 lane = bnx2x_get_warpcore_lane(int_phy, params);
6467                         bnx2x_cl45_read(bp, int_phy, MDIO_WC_DEVAD,
6468                                         MDIO_WC_REG_GP2_STATUS_GP_2_1,
6469                                         &gp_status);
6470                         gp_status = ((gp_status >> 8) & 0xf) |
6471                                 ((gp_status >> 12) & 0xf);
6472                         link_up = gp_status & (1 << lane);
6473                 }
6474                 if (!link_up)
6475                         return -ESRCH;
6476         } else {
6477                 CL22_RD_OVER_CL45(bp, int_phy,
6478                           MDIO_REG_BANK_GP_STATUS,
6479                           MDIO_GP_STATUS_TOP_AN_STATUS1,
6480                           &gp_status);
6481                 /* Link is up only if both local phy and external phy are up */
6482                 if (!(gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS))
6483                         return -ESRCH;
6484         }
6485         /* In XGXS loopback mode, do not check external PHY */
6486         if (params->loopback_mode == LOOPBACK_XGXS)
6487                 return 0;
6488
6489         switch (params->num_phys) {
6490         case 1:
6491                 /* No external PHY */
6492                 return 0;
6493         case 2:
6494                 ext_phy_link_up = params->phy[EXT_PHY1].read_status(
6495                         &params->phy[EXT_PHY1],
6496                         params, &temp_vars);
6497                 break;
6498         case 3: /* Dual Media */
6499                 for (phy_index = EXT_PHY1; phy_index < params->num_phys;
6500                       phy_index++) {
6501                         serdes_phy_type = ((params->phy[phy_index].media_type ==
6502                                             ETH_PHY_SFPP_10G_FIBER) ||
6503                                            (params->phy[phy_index].media_type ==
6504                                             ETH_PHY_SFP_1G_FIBER) ||
6505                                            (params->phy[phy_index].media_type ==
6506                                             ETH_PHY_XFP_FIBER) ||
6507                                            (params->phy[phy_index].media_type ==
6508                                             ETH_PHY_DA_TWINAX));
6509
6510                         if (is_serdes != serdes_phy_type)
6511                                 continue;
6512                         if (params->phy[phy_index].read_status) {
6513                                 ext_phy_link_up |=
6514                                         params->phy[phy_index].read_status(
6515                                                 &params->phy[phy_index],
6516                                                 params, &temp_vars);
6517                         }
6518                 }
6519                 break;
6520         }
6521         if (ext_phy_link_up)
6522                 return 0;
6523         return -ESRCH;
6524 }
6525
6526 static int bnx2x_link_initialize(struct link_params *params,
6527                                  struct link_vars *vars)
6528 {
6529         u8 phy_index, non_ext_phy;
6530         struct bnx2x *bp = params->bp;
6531         /* In case of external phy existence, the line speed would be the
6532          * line speed linked up by the external phy. In case it is direct
6533          * only, then the line_speed during initialization will be
6534          * equal to the req_line_speed
6535          */
6536         vars->line_speed = params->phy[INT_PHY].req_line_speed;
6537
6538         /* Initialize the internal phy in case this is a direct board
6539          * (no external phys), or this board has external phy which requires
6540          * to first.
6541          */
6542         if (!USES_WARPCORE(bp))
6543                 bnx2x_prepare_xgxs(&params->phy[INT_PHY], params, vars);
6544         /* init ext phy and enable link state int */
6545         non_ext_phy = (SINGLE_MEDIA_DIRECT(params) ||
6546                        (params->loopback_mode == LOOPBACK_XGXS));
6547
6548         if (non_ext_phy ||
6549             (params->phy[EXT_PHY1].flags & FLAGS_INIT_XGXS_FIRST) ||
6550             (params->loopback_mode == LOOPBACK_EXT_PHY)) {
6551                 struct bnx2x_phy *phy = &params->phy[INT_PHY];
6552                 if (vars->line_speed == SPEED_AUTO_NEG &&
6553                     (CHIP_IS_E1x(bp) ||
6554                      CHIP_IS_E2(bp)))
6555                         bnx2x_set_parallel_detection(phy, params);
6556                 if (params->phy[INT_PHY].config_init)
6557                         params->phy[INT_PHY].config_init(phy, params, vars);
6558         }
6559
6560         /* Re-read this value in case it was changed inside config_init due to
6561          * limitations of optic module
6562          */
6563         vars->line_speed = params->phy[INT_PHY].req_line_speed;
6564
6565         /* Init external phy*/
6566         if (non_ext_phy) {
6567                 if (params->phy[INT_PHY].supported &
6568                     SUPPORTED_FIBRE)
6569                         vars->link_status |= LINK_STATUS_SERDES_LINK;
6570         } else {
6571                 for (phy_index = EXT_PHY1; phy_index < params->num_phys;
6572                       phy_index++) {
6573                         /* No need to initialize second phy in case of first
6574                          * phy only selection. In case of second phy, we do
6575                          * need to initialize the first phy, since they are
6576                          * connected.
6577                          */
6578                         if (params->phy[phy_index].supported &
6579                             SUPPORTED_FIBRE)
6580                                 vars->link_status |= LINK_STATUS_SERDES_LINK;
6581
6582                         if (phy_index == EXT_PHY2 &&
6583                             (bnx2x_phy_selection(params) ==
6584                              PORT_HW_CFG_PHY_SELECTION_FIRST_PHY)) {
6585                                 DP(NETIF_MSG_LINK,
6586                                    "Not initializing second phy\n");
6587                                 continue;
6588                         }
6589                         params->phy[phy_index].config_init(
6590                                 &params->phy[phy_index],
6591                                 params, vars);
6592                 }
6593         }
6594         /* Reset the interrupt indication after phy was initialized */
6595         bnx2x_bits_dis(bp, NIG_REG_STATUS_INTERRUPT_PORT0 +
6596                        params->port*4,
6597                        (NIG_STATUS_XGXS0_LINK10G |
6598                         NIG_STATUS_XGXS0_LINK_STATUS |
6599                         NIG_STATUS_SERDES0_LINK_STATUS |
6600                         NIG_MASK_MI_INT));
6601         return 0;
6602 }
6603
6604 static void bnx2x_int_link_reset(struct bnx2x_phy *phy,
6605                                  struct link_params *params)
6606 {
6607         /* Reset the SerDes/XGXS */
6608         REG_WR(params->bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR,
6609                (0x1ff << (params->port*16)));
6610 }
6611
6612 static void bnx2x_common_ext_link_reset(struct bnx2x_phy *phy,
6613                                         struct link_params *params)
6614 {
6615         struct bnx2x *bp = params->bp;
6616         u8 gpio_port;
6617         /* HW reset */
6618         if (CHIP_IS_E2(bp))
6619                 gpio_port = BP_PATH(bp);
6620         else
6621                 gpio_port = params->port;
6622         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
6623                        MISC_REGISTERS_GPIO_OUTPUT_LOW,
6624                        gpio_port);
6625         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
6626                        MISC_REGISTERS_GPIO_OUTPUT_LOW,
6627                        gpio_port);
6628         DP(NETIF_MSG_LINK, "reset external PHY\n");
6629 }
6630
6631 static int bnx2x_update_link_down(struct link_params *params,
6632                                   struct link_vars *vars)
6633 {
6634         struct bnx2x *bp = params->bp;
6635         u8 port = params->port;
6636
6637         DP(NETIF_MSG_LINK, "Port %x: Link is down\n", port);
6638         bnx2x_set_led(params, vars, LED_MODE_OFF, 0);
6639         vars->phy_flags &= ~PHY_PHYSICAL_LINK_FLAG;
6640         /* Indicate no mac active */
6641         vars->mac_type = MAC_TYPE_NONE;
6642
6643         /* Update shared memory */
6644         vars->link_status &= ~LINK_UPDATE_MASK;
6645         vars->line_speed = 0;
6646         bnx2x_update_mng(params, vars->link_status);
6647
6648         /* Activate nig drain */
6649         REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1);
6650
6651         /* Disable emac */
6652         if (!CHIP_IS_E3(bp))
6653                 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0);
6654
6655         usleep_range(10000, 20000);
6656         /* Reset BigMac/Xmac */
6657         if (CHIP_IS_E1x(bp) ||
6658             CHIP_IS_E2(bp))
6659                 bnx2x_set_bmac_rx(bp, params->chip_id, params->port, 0);
6660
6661         if (CHIP_IS_E3(bp)) {
6662                 /* Prevent LPI Generation by chip */
6663                 REG_WR(bp, MISC_REG_CPMU_LP_FW_ENABLE_P0 + (params->port << 2),
6664                        0);
6665                 REG_WR(bp, MISC_REG_CPMU_LP_MASK_ENT_P0 + (params->port << 2),
6666                        0);
6667                 vars->eee_status &= ~(SHMEM_EEE_LP_ADV_STATUS_MASK |
6668                                       SHMEM_EEE_ACTIVE_BIT);
6669
6670                 bnx2x_update_mng_eee(params, vars->eee_status);
6671                 bnx2x_set_xmac_rxtx(params, 0);
6672                 bnx2x_set_umac_rxtx(params, 0);
6673         }
6674
6675         return 0;
6676 }
6677
6678 static int bnx2x_update_link_up(struct link_params *params,
6679                                 struct link_vars *vars,
6680                                 u8 link_10g)
6681 {
6682         struct bnx2x *bp = params->bp;
6683         u8 phy_idx, port = params->port;
6684         int rc = 0;
6685
6686         vars->link_status |= (LINK_STATUS_LINK_UP |
6687                               LINK_STATUS_PHYSICAL_LINK_FLAG);
6688         vars->phy_flags |= PHY_PHYSICAL_LINK_FLAG;
6689
6690         if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)
6691                 vars->link_status |=
6692                         LINK_STATUS_TX_FLOW_CONTROL_ENABLED;
6693
6694         if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)
6695                 vars->link_status |=
6696                         LINK_STATUS_RX_FLOW_CONTROL_ENABLED;
6697         if (USES_WARPCORE(bp)) {
6698                 if (link_10g) {
6699                         if (bnx2x_xmac_enable(params, vars, 0) ==
6700                             -ESRCH) {
6701                                 DP(NETIF_MSG_LINK, "Found errors on XMAC\n");
6702                                 vars->link_up = 0;
6703                                 vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG;
6704                                 vars->link_status &= ~LINK_STATUS_LINK_UP;
6705                         }
6706                 } else
6707                         bnx2x_umac_enable(params, vars, 0);
6708                 bnx2x_set_led(params, vars,
6709                               LED_MODE_OPER, vars->line_speed);
6710
6711                 if ((vars->eee_status & SHMEM_EEE_ACTIVE_BIT) &&
6712                     (vars->eee_status & SHMEM_EEE_LPI_REQUESTED_BIT)) {
6713                         DP(NETIF_MSG_LINK, "Enabling LPI assertion\n");
6714                         REG_WR(bp, MISC_REG_CPMU_LP_FW_ENABLE_P0 +
6715                                (params->port << 2), 1);
6716                         REG_WR(bp, MISC_REG_CPMU_LP_DR_ENABLE, 1);
6717                         REG_WR(bp, MISC_REG_CPMU_LP_MASK_ENT_P0 +
6718                                (params->port << 2), 0xfc20);
6719                 }
6720         }
6721         if ((CHIP_IS_E1x(bp) ||
6722              CHIP_IS_E2(bp))) {
6723                 if (link_10g) {
6724                         if (bnx2x_bmac_enable(params, vars, 0, 1) ==
6725                             -ESRCH) {
6726                                 DP(NETIF_MSG_LINK, "Found errors on BMAC\n");
6727                                 vars->link_up = 0;
6728                                 vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG;
6729                                 vars->link_status &= ~LINK_STATUS_LINK_UP;
6730                         }
6731
6732                         bnx2x_set_led(params, vars,
6733                                       LED_MODE_OPER, SPEED_10000);
6734                 } else {
6735                         rc = bnx2x_emac_program(params, vars);
6736                         bnx2x_emac_enable(params, vars, 0);
6737
6738                         /* AN complete? */
6739                         if ((vars->link_status &
6740                              LINK_STATUS_AUTO_NEGOTIATE_COMPLETE)
6741                             && (!(vars->phy_flags & PHY_SGMII_FLAG)) &&
6742                             SINGLE_MEDIA_DIRECT(params))
6743                                 bnx2x_set_gmii_tx_driver(params);
6744                 }
6745         }
6746
6747         /* PBF - link up */
6748         if (CHIP_IS_E1x(bp))
6749                 rc |= bnx2x_pbf_update(params, vars->flow_ctrl,
6750                                        vars->line_speed);
6751
6752         /* Disable drain */
6753         REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 0);
6754
6755         /* Update shared memory */
6756         bnx2x_update_mng(params, vars->link_status);
6757         bnx2x_update_mng_eee(params, vars->eee_status);
6758         /* Check remote fault */
6759         for (phy_idx = INT_PHY; phy_idx < MAX_PHYS; phy_idx++) {
6760                 if (params->phy[phy_idx].flags & FLAGS_TX_ERROR_CHECK) {
6761                         bnx2x_check_half_open_conn(params, vars, 0);
6762                         break;
6763                 }
6764         }
6765         msleep(20);
6766         return rc;
6767 }
6768
6769 static void bnx2x_chng_link_count(struct link_params *params, bool clear)
6770 {
6771         struct bnx2x *bp = params->bp;
6772         u32 addr, val;
6773
6774         /* Verify the link_change_count is supported by the MFW */
6775         if (!(SHMEM2_HAS(bp, link_change_count)))
6776                 return;
6777
6778         addr = params->shmem2_base +
6779                 offsetof(struct shmem2_region, link_change_count[params->port]);
6780         if (clear)
6781                 val = 0;
6782         else
6783                 val = REG_RD(bp, addr) + 1;
6784         REG_WR(bp, addr, val);
6785 }
6786
6787 /* The bnx2x_link_update function should be called upon link
6788  * interrupt.
6789  * Link is considered up as follows:
6790  * - DIRECT_SINGLE_MEDIA - Only XGXS link (internal link) needs
6791  *   to be up
6792  * - SINGLE_MEDIA - The link between the 577xx and the external
6793  *   phy (XGXS) need to up as well as the external link of the
6794  *   phy (PHY_EXT1)
6795  * - DUAL_MEDIA - The link between the 577xx and the first
6796  *   external phy needs to be up, and at least one of the 2
6797  *   external phy link must be up.
6798  */
6799 int bnx2x_link_update(struct link_params *params, struct link_vars *vars)
6800 {
6801         struct bnx2x *bp = params->bp;
6802         struct link_vars phy_vars[MAX_PHYS];
6803         u8 port = params->port;
6804         u8 link_10g_plus, phy_index;
6805         u32 prev_link_status = vars->link_status;
6806         u8 ext_phy_link_up = 0, cur_link_up;
6807         int rc = 0;
6808         u8 is_mi_int = 0;
6809         u16 ext_phy_line_speed = 0, prev_line_speed = vars->line_speed;
6810         u8 active_external_phy = INT_PHY;
6811         vars->phy_flags &= ~PHY_HALF_OPEN_CONN_FLAG;
6812         vars->link_status &= ~LINK_UPDATE_MASK;
6813         for (phy_index = INT_PHY; phy_index < params->num_phys;
6814               phy_index++) {
6815                 phy_vars[phy_index].flow_ctrl = 0;
6816                 phy_vars[phy_index].link_status = 0;
6817                 phy_vars[phy_index].line_speed = 0;
6818                 phy_vars[phy_index].duplex = DUPLEX_FULL;
6819                 phy_vars[phy_index].phy_link_up = 0;
6820                 phy_vars[phy_index].link_up = 0;
6821                 phy_vars[phy_index].fault_detected = 0;
6822                 /* different consideration, since vars holds inner state */
6823                 phy_vars[phy_index].eee_status = vars->eee_status;
6824         }
6825
6826         if (USES_WARPCORE(bp))
6827                 bnx2x_set_aer_mmd(params, &params->phy[INT_PHY]);
6828
6829         DP(NETIF_MSG_LINK, "port %x, XGXS?%x, int_status 0x%x\n",
6830                  port, (vars->phy_flags & PHY_XGXS_FLAG),
6831                  REG_RD(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4));
6832
6833         is_mi_int = (u8)(REG_RD(bp, NIG_REG_EMAC0_STATUS_MISC_MI_INT +
6834                                 port*0x18) > 0);
6835         DP(NETIF_MSG_LINK, "int_mask 0x%x MI_INT %x, SERDES_LINK %x\n",
6836                  REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4),
6837                  is_mi_int,
6838                  REG_RD(bp, NIG_REG_SERDES0_STATUS_LINK_STATUS + port*0x3c));
6839
6840         DP(NETIF_MSG_LINK, " 10G %x, XGXS_LINK %x\n",
6841           REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68),
6842           REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68));
6843
6844         /* Disable emac */
6845         if (!CHIP_IS_E3(bp))
6846                 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0);
6847
6848         /* Step 1:
6849          * Check external link change only for external phys, and apply
6850          * priority selection between them in case the link on both phys
6851          * is up. Note that instead of the common vars, a temporary
6852          * vars argument is used since each phy may have different link/
6853          * speed/duplex result
6854          */
6855         for (phy_index = EXT_PHY1; phy_index < params->num_phys;
6856               phy_index++) {
6857                 struct bnx2x_phy *phy = &params->phy[phy_index];
6858                 if (!phy->read_status)
6859                         continue;
6860                 /* Read link status and params of this ext phy */
6861                 cur_link_up = phy->read_status(phy, params,
6862                                                &phy_vars[phy_index]);
6863                 if (cur_link_up) {
6864                         DP(NETIF_MSG_LINK, "phy in index %d link is up\n",
6865                                    phy_index);
6866                 } else {
6867                         DP(NETIF_MSG_LINK, "phy in index %d link is down\n",
6868                                    phy_index);
6869                         continue;
6870                 }
6871
6872                 if (!ext_phy_link_up) {
6873                         ext_phy_link_up = 1;
6874                         active_external_phy = phy_index;
6875                 } else {
6876                         switch (bnx2x_phy_selection(params)) {
6877                         case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT:
6878                         case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
6879                         /* In this option, the first PHY makes sure to pass the
6880                          * traffic through itself only.
6881                          * It's not clear how to reset the link on the second
6882                          * phy.
6883                          */
6884                                 active_external_phy = EXT_PHY1;
6885                                 break;
6886                         case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
6887                         /* In this option, the first PHY makes sure to pass the
6888                          * traffic through the second PHY.
6889                          */
6890                                 active_external_phy = EXT_PHY2;
6891                                 break;
6892                         default:
6893                         /* Link indication on both PHYs with the following cases
6894                          * is invalid:
6895                          * - FIRST_PHY means that second phy wasn't initialized,
6896                          * hence its link is expected to be down
6897                          * - SECOND_PHY means that first phy should not be able
6898                          * to link up by itself (using configuration)
6899                          * - DEFAULT should be overridden during initialization
6900                          */
6901                                 DP(NETIF_MSG_LINK, "Invalid link indication"
6902                                            "mpc=0x%x. DISABLING LINK !!!\n",
6903                                            params->multi_phy_config);
6904                                 ext_phy_link_up = 0;
6905                                 break;
6906                         }
6907                 }
6908         }
6909         prev_line_speed = vars->line_speed;
6910         /* Step 2:
6911          * Read the status of the internal phy. In case of
6912          * DIRECT_SINGLE_MEDIA board, this link is the external link,
6913          * otherwise this is the link between the 577xx and the first
6914          * external phy
6915          */
6916         if (params->phy[INT_PHY].read_status)
6917                 params->phy[INT_PHY].read_status(
6918                         &params->phy[INT_PHY],
6919                         params, vars);
6920         /* The INT_PHY flow control reside in the vars. This include the
6921          * case where the speed or flow control are not set to AUTO.
6922          * Otherwise, the active external phy flow control result is set
6923          * to the vars. The ext_phy_line_speed is needed to check if the
6924          * speed is different between the internal phy and external phy.
6925          * This case may be result of intermediate link speed change.
6926          */
6927         if (active_external_phy > INT_PHY) {
6928                 vars->flow_ctrl = phy_vars[active_external_phy].flow_ctrl;
6929                 /* Link speed is taken from the XGXS. AN and FC result from
6930                  * the external phy.
6931                  */
6932                 vars->link_status |= phy_vars[active_external_phy].link_status;
6933
6934                 /* if active_external_phy is first PHY and link is up - disable
6935                  * disable TX on second external PHY
6936                  */
6937                 if (active_external_phy == EXT_PHY1) {
6938                         if (params->phy[EXT_PHY2].phy_specific_func) {
6939                                 DP(NETIF_MSG_LINK,
6940                                    "Disabling TX on EXT_PHY2\n");
6941                                 params->phy[EXT_PHY2].phy_specific_func(
6942                                         &params->phy[EXT_PHY2],
6943                                         params, DISABLE_TX);
6944                         }
6945                 }
6946
6947                 ext_phy_line_speed = phy_vars[active_external_phy].line_speed;
6948                 vars->duplex = phy_vars[active_external_phy].duplex;
6949                 if (params->phy[active_external_phy].supported &
6950                     SUPPORTED_FIBRE)
6951                         vars->link_status |= LINK_STATUS_SERDES_LINK;
6952                 else
6953                         vars->link_status &= ~LINK_STATUS_SERDES_LINK;
6954
6955                 vars->eee_status = phy_vars[active_external_phy].eee_status;
6956
6957                 DP(NETIF_MSG_LINK, "Active external phy selected: %x\n",
6958                            active_external_phy);
6959         }
6960
6961         for (phy_index = EXT_PHY1; phy_index < params->num_phys;
6962               phy_index++) {
6963                 if (params->phy[phy_index].flags &
6964                     FLAGS_REARM_LATCH_SIGNAL) {
6965                         bnx2x_rearm_latch_signal(bp, port,
6966                                                  phy_index ==
6967                                                  active_external_phy);
6968                         break;
6969                 }
6970         }
6971         DP(NETIF_MSG_LINK, "vars->flow_ctrl = 0x%x, vars->link_status = 0x%x,"
6972                    " ext_phy_line_speed = %d\n", vars->flow_ctrl,
6973                    vars->link_status, ext_phy_line_speed);
6974         /* Upon link speed change set the NIG into drain mode. Comes to
6975          * deals with possible FIFO glitch due to clk change when speed
6976          * is decreased without link down indicator
6977          */
6978
6979         if (vars->phy_link_up) {
6980                 if (!(SINGLE_MEDIA_DIRECT(params)) && ext_phy_link_up &&
6981                     (ext_phy_line_speed != vars->line_speed)) {
6982                         DP(NETIF_MSG_LINK, "Internal link speed %d is"
6983                                    " different than the external"
6984                                    " link speed %d\n", vars->line_speed,
6985                                    ext_phy_line_speed);
6986                         vars->phy_link_up = 0;
6987                 } else if (prev_line_speed != vars->line_speed) {
6988                         REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4,
6989                                0);
6990                         usleep_range(1000, 2000);
6991                 }
6992         }
6993
6994         /* Anything 10 and over uses the bmac */
6995         link_10g_plus = (vars->line_speed >= SPEED_10000);
6996
6997         bnx2x_link_int_ack(params, vars, link_10g_plus);
6998
6999         /* In case external phy link is up, and internal link is down
7000          * (not initialized yet probably after link initialization, it
7001          * needs to be initialized.
7002          * Note that after link down-up as result of cable plug, the xgxs
7003          * link would probably become up again without the need
7004          * initialize it
7005          */
7006         if (!(SINGLE_MEDIA_DIRECT(params))) {
7007                 DP(NETIF_MSG_LINK, "ext_phy_link_up = %d, int_link_up = %d,"
7008                            " init_preceding = %d\n", ext_phy_link_up,
7009                            vars->phy_link_up,
7010                            params->phy[EXT_PHY1].flags &
7011                            FLAGS_INIT_XGXS_FIRST);
7012                 if (!(params->phy[EXT_PHY1].flags &
7013                       FLAGS_INIT_XGXS_FIRST)
7014                     && ext_phy_link_up && !vars->phy_link_up) {
7015                         vars->line_speed = ext_phy_line_speed;
7016                         if (vars->line_speed < SPEED_1000)
7017                                 vars->phy_flags |= PHY_SGMII_FLAG;
7018                         else
7019                                 vars->phy_flags &= ~PHY_SGMII_FLAG;
7020
7021                         if (params->phy[INT_PHY].config_init)
7022                                 params->phy[INT_PHY].config_init(
7023                                         &params->phy[INT_PHY], params,
7024                                                 vars);
7025                 }
7026         }
7027         /* Link is up only if both local phy and external phy (in case of
7028          * non-direct board) are up and no fault detected on active PHY.
7029          */
7030         vars->link_up = (vars->phy_link_up &&
7031                          (ext_phy_link_up ||
7032                           SINGLE_MEDIA_DIRECT(params)) &&
7033                          (phy_vars[active_external_phy].fault_detected == 0));
7034
7035         /* Update the PFC configuration in case it was changed */
7036         if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED)
7037                 vars->link_status |= LINK_STATUS_PFC_ENABLED;
7038         else
7039                 vars->link_status &= ~LINK_STATUS_PFC_ENABLED;
7040
7041         if (vars->link_up)
7042                 rc = bnx2x_update_link_up(params, vars, link_10g_plus);
7043         else
7044                 rc = bnx2x_update_link_down(params, vars);
7045
7046         if ((prev_link_status ^ vars->link_status) & LINK_STATUS_LINK_UP)
7047                 bnx2x_chng_link_count(params, false);
7048
7049         /* Update MCP link status was changed */
7050         if (params->feature_config_flags & FEATURE_CONFIG_BC_SUPPORTS_AFEX)
7051                 bnx2x_fw_command(bp, DRV_MSG_CODE_LINK_STATUS_CHANGED, 0);
7052
7053         return rc;
7054 }
7055
7056 /*****************************************************************************/
7057 /*                          External Phy section                             */
7058 /*****************************************************************************/
7059 void bnx2x_ext_phy_hw_reset(struct bnx2x *bp, u8 port)
7060 {
7061         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
7062                        MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
7063         usleep_range(1000, 2000);
7064         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
7065                        MISC_REGISTERS_GPIO_OUTPUT_HIGH, port);
7066 }
7067
7068 static void bnx2x_save_spirom_version(struct bnx2x *bp, u8 port,
7069                                       u32 spirom_ver, u32 ver_addr)
7070 {
7071         DP(NETIF_MSG_LINK, "FW version 0x%x:0x%x for port %d\n",
7072                  (u16)(spirom_ver>>16), (u16)spirom_ver, port);
7073
7074         if (ver_addr)
7075                 REG_WR(bp, ver_addr, spirom_ver);
7076 }
7077
7078 static void bnx2x_save_bcm_spirom_ver(struct bnx2x *bp,
7079                                       struct bnx2x_phy *phy,
7080                                       u8 port)
7081 {
7082         u16 fw_ver1, fw_ver2;
7083
7084         bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
7085                         MDIO_PMA_REG_ROM_VER1, &fw_ver1);
7086         bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
7087                         MDIO_PMA_REG_ROM_VER2, &fw_ver2);
7088         bnx2x_save_spirom_version(bp, port, (u32)(fw_ver1<<16 | fw_ver2),
7089                                   phy->ver_addr);
7090 }
7091
7092 static void bnx2x_ext_phy_10G_an_resolve(struct bnx2x *bp,
7093                                        struct bnx2x_phy *phy,
7094                                        struct link_vars *vars)
7095 {
7096         u16 val;
7097         bnx2x_cl45_read(bp, phy,
7098                         MDIO_AN_DEVAD,
7099                         MDIO_AN_REG_STATUS, &val);
7100         bnx2x_cl45_read(bp, phy,
7101                         MDIO_AN_DEVAD,
7102                         MDIO_AN_REG_STATUS, &val);
7103         if (val & (1<<5))
7104                 vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
7105         if ((val & (1<<0)) == 0)
7106                 vars->link_status |= LINK_STATUS_PARALLEL_DETECTION_USED;
7107 }
7108
7109 /******************************************************************/
7110 /*              common BCM8073/BCM8727 PHY SECTION                */
7111 /******************************************************************/
7112 static void bnx2x_8073_resolve_fc(struct bnx2x_phy *phy,
7113                                   struct link_params *params,
7114                                   struct link_vars *vars)
7115 {
7116         struct bnx2x *bp = params->bp;
7117         if (phy->req_line_speed == SPEED_10 ||
7118             phy->req_line_speed == SPEED_100) {
7119                 vars->flow_ctrl = phy->req_flow_ctrl;
7120                 return;
7121         }
7122
7123         if (bnx2x_ext_phy_resolve_fc(phy, params, vars) &&
7124             (vars->flow_ctrl == BNX2X_FLOW_CTRL_NONE)) {
7125                 u16 pause_result;
7126                 u16 ld_pause;           /* local */
7127                 u16 lp_pause;           /* link partner */
7128                 bnx2x_cl45_read(bp, phy,
7129                                 MDIO_AN_DEVAD,
7130                                 MDIO_AN_REG_CL37_FC_LD, &ld_pause);
7131
7132                 bnx2x_cl45_read(bp, phy,
7133                                 MDIO_AN_DEVAD,
7134                                 MDIO_AN_REG_CL37_FC_LP, &lp_pause);
7135                 pause_result = (ld_pause &
7136                                 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) >> 5;
7137                 pause_result |= (lp_pause &
7138                                  MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) >> 7;
7139
7140                 bnx2x_pause_resolve(phy, params, vars, pause_result);
7141                 DP(NETIF_MSG_LINK, "Ext PHY CL37 pause result 0x%x\n",
7142                            pause_result);
7143         }
7144 }
7145 static int bnx2x_8073_8727_external_rom_boot(struct bnx2x *bp,
7146                                              struct bnx2x_phy *phy,
7147                                              u8 port)
7148 {
7149         u32 count = 0;
7150         u16 fw_ver1, fw_msgout;
7151         int rc = 0;
7152
7153         /* Boot port from external ROM  */
7154         /* EDC grst */
7155         bnx2x_cl45_write(bp, phy,
7156                          MDIO_PMA_DEVAD,
7157                          MDIO_PMA_REG_GEN_CTRL,
7158                          0x0001);
7159
7160         /* Ucode reboot and rst */
7161         bnx2x_cl45_write(bp, phy,
7162                          MDIO_PMA_DEVAD,
7163                          MDIO_PMA_REG_GEN_CTRL,
7164                          0x008c);
7165
7166         bnx2x_cl45_write(bp, phy,
7167                          MDIO_PMA_DEVAD,
7168                          MDIO_PMA_REG_MISC_CTRL1, 0x0001);
7169
7170         /* Reset internal microprocessor */
7171         bnx2x_cl45_write(bp, phy,
7172                          MDIO_PMA_DEVAD,
7173                          MDIO_PMA_REG_GEN_CTRL,
7174                          MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET);
7175
7176         /* Release srst bit */
7177         bnx2x_cl45_write(bp, phy,
7178                          MDIO_PMA_DEVAD,
7179                          MDIO_PMA_REG_GEN_CTRL,
7180                          MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP);
7181
7182         /* Delay 100ms per the PHY specifications */
7183         msleep(100);
7184
7185         /* 8073 sometimes taking longer to download */
7186         do {
7187                 count++;
7188                 if (count > 300) {
7189                         DP(NETIF_MSG_LINK,
7190                                  "bnx2x_8073_8727_external_rom_boot port %x:"
7191                                  "Download failed. fw version = 0x%x\n",
7192                                  port, fw_ver1);
7193                         rc = -EINVAL;
7194                         break;
7195                 }
7196
7197                 bnx2x_cl45_read(bp, phy,
7198                                 MDIO_PMA_DEVAD,
7199                                 MDIO_PMA_REG_ROM_VER1, &fw_ver1);
7200                 bnx2x_cl45_read(bp, phy,
7201                                 MDIO_PMA_DEVAD,
7202                                 MDIO_PMA_REG_M8051_MSGOUT_REG, &fw_msgout);
7203
7204                 usleep_range(1000, 2000);
7205         } while (fw_ver1 == 0 || fw_ver1 == 0x4321 ||
7206                         ((fw_msgout & 0xff) != 0x03 && (phy->type ==
7207                         PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073)));
7208
7209         /* Clear ser_boot_ctl bit */
7210         bnx2x_cl45_write(bp, phy,
7211                          MDIO_PMA_DEVAD,
7212                          MDIO_PMA_REG_MISC_CTRL1, 0x0000);
7213         bnx2x_save_bcm_spirom_ver(bp, phy, port);
7214
7215         DP(NETIF_MSG_LINK,
7216                  "bnx2x_8073_8727_external_rom_boot port %x:"
7217                  "Download complete. fw version = 0x%x\n",
7218                  port, fw_ver1);
7219
7220         return rc;
7221 }
7222
7223 /******************************************************************/
7224 /*                      BCM8073 PHY SECTION                       */
7225 /******************************************************************/
7226 static int bnx2x_8073_is_snr_needed(struct bnx2x *bp, struct bnx2x_phy *phy)
7227 {
7228         /* This is only required for 8073A1, version 102 only */
7229         u16 val;
7230
7231         /* Read 8073 HW revision*/
7232         bnx2x_cl45_read(bp, phy,
7233                         MDIO_PMA_DEVAD,
7234                         MDIO_PMA_REG_8073_CHIP_REV, &val);
7235
7236         if (val != 1) {
7237                 /* No need to workaround in 8073 A1 */
7238                 return 0;
7239         }
7240
7241         bnx2x_cl45_read(bp, phy,
7242                         MDIO_PMA_DEVAD,
7243                         MDIO_PMA_REG_ROM_VER2, &val);
7244
7245         /* SNR should be applied only for version 0x102 */
7246         if (val != 0x102)
7247                 return 0;
7248
7249         return 1;
7250 }
7251
7252 static int bnx2x_8073_xaui_wa(struct bnx2x *bp, struct bnx2x_phy *phy)
7253 {
7254         u16 val, cnt, cnt1 ;
7255
7256         bnx2x_cl45_read(bp, phy,
7257                         MDIO_PMA_DEVAD,
7258                         MDIO_PMA_REG_8073_CHIP_REV, &val);
7259
7260         if (val > 0) {
7261                 /* No need to workaround in 8073 A1 */
7262                 return 0;
7263         }
7264         /* XAUI workaround in 8073 A0: */
7265
7266         /* After loading the boot ROM and restarting Autoneg, poll
7267          * Dev1, Reg $C820:
7268          */
7269
7270         for (cnt = 0; cnt < 1000; cnt++) {
7271                 bnx2x_cl45_read(bp, phy,
7272                                 MDIO_PMA_DEVAD,
7273                                 MDIO_PMA_REG_8073_SPEED_LINK_STATUS,
7274                                 &val);
7275                   /* If bit [14] = 0 or bit [13] = 0, continue on with
7276                    * system initialization (XAUI work-around not required, as
7277                    * these bits indicate 2.5G or 1G link up).
7278                    */
7279                 if (!(val & (1<<14)) || !(val & (1<<13))) {
7280                         DP(NETIF_MSG_LINK, "XAUI work-around not required\n");
7281                         return 0;
7282                 } else if (!(val & (1<<15))) {
7283                         DP(NETIF_MSG_LINK, "bit 15 went off\n");
7284                         /* If bit 15 is 0, then poll Dev1, Reg $C841 until it's
7285                          * MSB (bit15) goes to 1 (indicating that the XAUI
7286                          * workaround has completed), then continue on with
7287                          * system initialization.
7288                          */
7289                         for (cnt1 = 0; cnt1 < 1000; cnt1++) {
7290                                 bnx2x_cl45_read(bp, phy,
7291                                         MDIO_PMA_DEVAD,
7292                                         MDIO_PMA_REG_8073_XAUI_WA, &val);
7293                                 if (val & (1<<15)) {
7294                                         DP(NETIF_MSG_LINK,
7295                                           "XAUI workaround has completed\n");
7296                                         return 0;
7297                                 }
7298                                 usleep_range(3000, 6000);
7299                         }
7300                         break;
7301                 }
7302                 usleep_range(3000, 6000);
7303         }
7304         DP(NETIF_MSG_LINK, "Warning: XAUI work-around timeout !!!\n");
7305         return -EINVAL;
7306 }
7307
7308 static void bnx2x_807x_force_10G(struct bnx2x *bp, struct bnx2x_phy *phy)
7309 {
7310         /* Force KR or KX */
7311         bnx2x_cl45_write(bp, phy,
7312                          MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x2040);
7313         bnx2x_cl45_write(bp, phy,
7314                          MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0x000b);
7315         bnx2x_cl45_write(bp, phy,
7316                          MDIO_PMA_DEVAD, MDIO_PMA_REG_BCM_CTRL, 0x0000);
7317         bnx2x_cl45_write(bp, phy,
7318                          MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x0000);
7319 }
7320
7321 static void bnx2x_8073_set_pause_cl37(struct link_params *params,
7322                                       struct bnx2x_phy *phy,
7323                                       struct link_vars *vars)
7324 {
7325         u16 cl37_val;
7326         struct bnx2x *bp = params->bp;
7327         bnx2x_cl45_read(bp, phy,
7328                         MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, &cl37_val);
7329
7330         cl37_val &= ~MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
7331         /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
7332         bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
7333         if ((vars->ieee_fc &
7334             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) ==
7335             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) {
7336                 cl37_val |=  MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC;
7337         }
7338         if ((vars->ieee_fc &
7339             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
7340             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) {
7341                 cl37_val |=  MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
7342         }
7343         if ((vars->ieee_fc &
7344             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
7345             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) {
7346                 cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
7347         }
7348         DP(NETIF_MSG_LINK,
7349                  "Ext phy AN advertize cl37 0x%x\n", cl37_val);
7350
7351         bnx2x_cl45_write(bp, phy,
7352                          MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, cl37_val);
7353         msleep(500);
7354 }
7355
7356 static void bnx2x_8073_specific_func(struct bnx2x_phy *phy,
7357                                      struct link_params *params,
7358                                      u32 action)
7359 {
7360         struct bnx2x *bp = params->bp;
7361         switch (action) {
7362         case PHY_INIT:
7363                 /* Enable LASI */
7364                 bnx2x_cl45_write(bp, phy,
7365                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL, (1<<2));
7366                 bnx2x_cl45_write(bp, phy,
7367                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL,  0x0004);
7368                 break;
7369         }
7370 }
7371
7372 static void bnx2x_8073_config_init(struct bnx2x_phy *phy,
7373                                    struct link_params *params,
7374                                    struct link_vars *vars)
7375 {
7376         struct bnx2x *bp = params->bp;
7377         u16 val = 0, tmp1;
7378         u8 gpio_port;
7379         DP(NETIF_MSG_LINK, "Init 8073\n");
7380
7381         if (CHIP_IS_E2(bp))
7382                 gpio_port = BP_PATH(bp);
7383         else
7384                 gpio_port = params->port;
7385         /* Restore normal power mode*/
7386         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
7387                        MISC_REGISTERS_GPIO_OUTPUT_HIGH, gpio_port);
7388
7389         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
7390                        MISC_REGISTERS_GPIO_OUTPUT_HIGH, gpio_port);
7391
7392         bnx2x_8073_specific_func(phy, params, PHY_INIT);
7393         bnx2x_8073_set_pause_cl37(params, phy, vars);
7394
7395         bnx2x_cl45_read(bp, phy,
7396                         MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &tmp1);
7397
7398         bnx2x_cl45_read(bp, phy,
7399                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &tmp1);
7400
7401         DP(NETIF_MSG_LINK, "Before rom RX_ALARM(port1): 0x%x\n", tmp1);
7402
7403         /* Swap polarity if required - Must be done only in non-1G mode */
7404         if (params->lane_config & PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED) {
7405                 /* Configure the 8073 to swap _P and _N of the KR lines */
7406                 DP(NETIF_MSG_LINK, "Swapping polarity for the 8073\n");
7407                 /* 10G Rx/Tx and 1G Tx signal polarity swap */
7408                 bnx2x_cl45_read(bp, phy,
7409                                 MDIO_PMA_DEVAD,
7410                                 MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL, &val);
7411                 bnx2x_cl45_write(bp, phy,
7412                                  MDIO_PMA_DEVAD,
7413                                  MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL,
7414                                  (val | (3<<9)));
7415         }
7416
7417
7418         /* Enable CL37 BAM */
7419         if (REG_RD(bp, params->shmem_base +
7420                          offsetof(struct shmem_region, dev_info.
7421                                   port_hw_config[params->port].default_cfg)) &
7422             PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED) {
7423
7424                 bnx2x_cl45_read(bp, phy,
7425                                 MDIO_AN_DEVAD,
7426                                 MDIO_AN_REG_8073_BAM, &val);
7427                 bnx2x_cl45_write(bp, phy,
7428                                  MDIO_AN_DEVAD,
7429                                  MDIO_AN_REG_8073_BAM, val | 1);
7430                 DP(NETIF_MSG_LINK, "Enable CL37 BAM on KR\n");
7431         }
7432         if (params->loopback_mode == LOOPBACK_EXT) {
7433                 bnx2x_807x_force_10G(bp, phy);
7434                 DP(NETIF_MSG_LINK, "Forced speed 10G on 807X\n");
7435                 return;
7436         } else {
7437                 bnx2x_cl45_write(bp, phy,
7438                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_BCM_CTRL, 0x0002);
7439         }
7440         if (phy->req_line_speed != SPEED_AUTO_NEG) {
7441                 if (phy->req_line_speed == SPEED_10000) {
7442                         val = (1<<7);
7443                 } else if (phy->req_line_speed ==  SPEED_2500) {
7444                         val = (1<<5);
7445                         /* Note that 2.5G works only when used with 1G
7446                          * advertisement
7447                          */
7448                 } else
7449                         val = (1<<5);
7450         } else {
7451                 val = 0;
7452                 if (phy->speed_cap_mask &
7453                         PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
7454                         val |= (1<<7);
7455
7456                 /* Note that 2.5G works only when used with 1G advertisement */
7457                 if (phy->speed_cap_mask &
7458                         (PORT_HW_CFG_SPEED_CAPABILITY_D0_1G |
7459                          PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G))
7460                         val |= (1<<5);
7461                 DP(NETIF_MSG_LINK, "807x autoneg val = 0x%x\n", val);
7462         }
7463
7464         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV, val);
7465         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_8073_2_5G, &tmp1);
7466
7467         if (((phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G) &&
7468              (phy->req_line_speed == SPEED_AUTO_NEG)) ||
7469             (phy->req_line_speed == SPEED_2500)) {
7470                 u16 phy_ver;
7471                 /* Allow 2.5G for A1 and above */
7472                 bnx2x_cl45_read(bp, phy,
7473                                 MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_CHIP_REV,
7474                                 &phy_ver);
7475                 DP(NETIF_MSG_LINK, "Add 2.5G\n");
7476                 if (phy_ver > 0)
7477                         tmp1 |= 1;
7478                 else
7479                         tmp1 &= 0xfffe;
7480         } else {
7481                 DP(NETIF_MSG_LINK, "Disable 2.5G\n");
7482                 tmp1 &= 0xfffe;
7483         }
7484
7485         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_8073_2_5G, tmp1);
7486         /* Add support for CL37 (passive mode) II */
7487
7488         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, &tmp1);
7489         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD,
7490                          (tmp1 | ((phy->req_duplex == DUPLEX_FULL) ?
7491                                   0x20 : 0x40)));
7492
7493         /* Add support for CL37 (passive mode) III */
7494         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);
7495
7496         /* The SNR will improve about 2db by changing BW and FEE main
7497          * tap. Rest commands are executed after link is up
7498          * Change FFE main cursor to 5 in EDC register
7499          */
7500         if (bnx2x_8073_is_snr_needed(bp, phy))
7501                 bnx2x_cl45_write(bp, phy,
7502                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_EDC_FFE_MAIN,
7503                                  0xFB0C);
7504
7505         /* Enable FEC (Forware Error Correction) Request in the AN */
7506         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV2, &tmp1);
7507         tmp1 |= (1<<15);
7508         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV2, tmp1);
7509
7510         bnx2x_ext_phy_set_pause(params, phy, vars);
7511
7512         /* Restart autoneg */
7513         msleep(500);
7514         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);
7515         DP(NETIF_MSG_LINK, "807x Autoneg Restart: Advertise 1G=%x, 10G=%x\n",
7516                    ((val & (1<<5)) > 0), ((val & (1<<7)) > 0));
7517 }
7518
7519 static u8 bnx2x_8073_read_status(struct bnx2x_phy *phy,
7520                                  struct link_params *params,
7521                                  struct link_vars *vars)
7522 {
7523         struct bnx2x *bp = params->bp;
7524         u8 link_up = 0;
7525         u16 val1, val2;
7526         u16 link_status = 0;
7527         u16 an1000_status = 0;
7528
7529         bnx2x_cl45_read(bp, phy,
7530                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
7531
7532         DP(NETIF_MSG_LINK, "8703 LASI status 0x%x\n", val1);
7533
7534         /* Clear the interrupt LASI status register */
7535         bnx2x_cl45_read(bp, phy,
7536                         MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val2);
7537         bnx2x_cl45_read(bp, phy,
7538                         MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val1);
7539         DP(NETIF_MSG_LINK, "807x PCS status 0x%x->0x%x\n", val2, val1);
7540         /* Clear MSG-OUT */
7541         bnx2x_cl45_read(bp, phy,
7542                         MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &val1);
7543
7544         /* Check the LASI */
7545         bnx2x_cl45_read(bp, phy,
7546                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &val2);
7547
7548         DP(NETIF_MSG_LINK, "KR 0x9003 0x%x\n", val2);
7549
7550         /* Check the link status */
7551         bnx2x_cl45_read(bp, phy,
7552                         MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val2);
7553         DP(NETIF_MSG_LINK, "KR PCS status 0x%x\n", val2);
7554
7555         bnx2x_cl45_read(bp, phy,
7556                         MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);
7557         bnx2x_cl45_read(bp, phy,
7558                         MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);
7559         link_up = ((val1 & 4) == 4);
7560         DP(NETIF_MSG_LINK, "PMA_REG_STATUS=0x%x\n", val1);
7561
7562         if (link_up &&
7563              ((phy->req_line_speed != SPEED_10000))) {
7564                 if (bnx2x_8073_xaui_wa(bp, phy) != 0)
7565                         return 0;
7566         }
7567         bnx2x_cl45_read(bp, phy,
7568                         MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &an1000_status);
7569         bnx2x_cl45_read(bp, phy,
7570                         MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &an1000_status);
7571
7572         /* Check the link status on 1.1.2 */
7573         bnx2x_cl45_read(bp, phy,
7574                         MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);
7575         bnx2x_cl45_read(bp, phy,
7576                         MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);
7577         DP(NETIF_MSG_LINK, "KR PMA status 0x%x->0x%x,"
7578                    "an_link_status=0x%x\n", val2, val1, an1000_status);
7579
7580         link_up = (((val1 & 4) == 4) || (an1000_status & (1<<1)));
7581         if (link_up && bnx2x_8073_is_snr_needed(bp, phy)) {
7582                 /* The SNR will improve about 2dbby changing the BW and FEE main
7583                  * tap. The 1st write to change FFE main tap is set before
7584                  * restart AN. Change PLL Bandwidth in EDC register
7585                  */
7586                 bnx2x_cl45_write(bp, phy,
7587                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_PLL_BANDWIDTH,
7588                                  0x26BC);
7589
7590                 /* Change CDR Bandwidth in EDC register */
7591                 bnx2x_cl45_write(bp, phy,
7592                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_CDR_BANDWIDTH,
7593                                  0x0333);
7594         }
7595         bnx2x_cl45_read(bp, phy,
7596                         MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_SPEED_LINK_STATUS,
7597                         &link_status);
7598
7599         /* Bits 0..2 --> speed detected, bits 13..15--> link is down */
7600         if ((link_status & (1<<2)) && (!(link_status & (1<<15)))) {
7601                 link_up = 1;
7602                 vars->line_speed = SPEED_10000;
7603                 DP(NETIF_MSG_LINK, "port %x: External link up in 10G\n",
7604                            params->port);
7605         } else if ((link_status & (1<<1)) && (!(link_status & (1<<14)))) {
7606                 link_up = 1;
7607                 vars->line_speed = SPEED_2500;
7608                 DP(NETIF_MSG_LINK, "port %x: External link up in 2.5G\n",
7609                            params->port);
7610         } else if ((link_status & (1<<0)) && (!(link_status & (1<<13)))) {
7611                 link_up = 1;
7612                 vars->line_speed = SPEED_1000;
7613                 DP(NETIF_MSG_LINK, "port %x: External link up in 1G\n",
7614                            params->port);
7615         } else {
7616                 link_up = 0;
7617                 DP(NETIF_MSG_LINK, "port %x: External link is down\n",
7618                            params->port);
7619         }
7620
7621         if (link_up) {
7622                 /* Swap polarity if required */
7623                 if (params->lane_config &
7624                     PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED) {
7625                         /* Configure the 8073 to swap P and N of the KR lines */
7626                         bnx2x_cl45_read(bp, phy,
7627                                         MDIO_XS_DEVAD,
7628                                         MDIO_XS_REG_8073_RX_CTRL_PCIE, &val1);
7629                         /* Set bit 3 to invert Rx in 1G mode and clear this bit
7630                          * when it`s in 10G mode.
7631                          */
7632                         if (vars->line_speed == SPEED_1000) {
7633                                 DP(NETIF_MSG_LINK, "Swapping 1G polarity for"
7634                                               "the 8073\n");
7635                                 val1 |= (1<<3);
7636                         } else
7637                                 val1 &= ~(1<<3);
7638
7639                         bnx2x_cl45_write(bp, phy,
7640                                          MDIO_XS_DEVAD,
7641                                          MDIO_XS_REG_8073_RX_CTRL_PCIE,
7642                                          val1);
7643                 }
7644                 bnx2x_ext_phy_10G_an_resolve(bp, phy, vars);
7645                 bnx2x_8073_resolve_fc(phy, params, vars);
7646                 vars->duplex = DUPLEX_FULL;
7647         }
7648
7649         if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) {
7650                 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
7651                                 MDIO_AN_REG_LP_AUTO_NEG2, &val1);
7652
7653                 if (val1 & (1<<5))
7654                         vars->link_status |=
7655                                 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;
7656                 if (val1 & (1<<7))
7657                         vars->link_status |=
7658                                 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
7659         }
7660
7661         return link_up;
7662 }
7663
7664 static void bnx2x_8073_link_reset(struct bnx2x_phy *phy,
7665                                   struct link_params *params)
7666 {
7667         struct bnx2x *bp = params->bp;
7668         u8 gpio_port;
7669         if (CHIP_IS_E2(bp))
7670                 gpio_port = BP_PATH(bp);
7671         else
7672                 gpio_port = params->port;
7673         DP(NETIF_MSG_LINK, "Setting 8073 port %d into low power mode\n",
7674            gpio_port);
7675         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
7676                        MISC_REGISTERS_GPIO_OUTPUT_LOW,
7677                        gpio_port);
7678 }
7679
7680 /******************************************************************/
7681 /*                      BCM8705 PHY SECTION                       */
7682 /******************************************************************/
7683 static void bnx2x_8705_config_init(struct bnx2x_phy *phy,
7684                                    struct link_params *params,
7685                                    struct link_vars *vars)
7686 {
7687         struct bnx2x *bp = params->bp;
7688         DP(NETIF_MSG_LINK, "init 8705\n");
7689         /* Restore normal power mode*/
7690         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
7691                        MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
7692         /* HW reset */
7693         bnx2x_ext_phy_hw_reset(bp, params->port);
7694         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040);
7695         bnx2x_wait_reset_complete(bp, phy, params);
7696
7697         bnx2x_cl45_write(bp, phy,
7698                          MDIO_PMA_DEVAD, MDIO_PMA_REG_MISC_CTRL, 0x8288);
7699         bnx2x_cl45_write(bp, phy,
7700                          MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, 0x7fbf);
7701         bnx2x_cl45_write(bp, phy,
7702                          MDIO_PMA_DEVAD, MDIO_PMA_REG_CMU_PLL_BYPASS, 0x0100);
7703         bnx2x_cl45_write(bp, phy,
7704                          MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_CNTL, 0x1);
7705         /* BCM8705 doesn't have microcode, hence the 0 */
7706         bnx2x_save_spirom_version(bp, params->port, params->shmem_base, 0);
7707 }
7708
7709 static u8 bnx2x_8705_read_status(struct bnx2x_phy *phy,
7710                                  struct link_params *params,
7711                                  struct link_vars *vars)
7712 {
7713         u8 link_up = 0;
7714         u16 val1, rx_sd;
7715         struct bnx2x *bp = params->bp;
7716         DP(NETIF_MSG_LINK, "read status 8705\n");
7717         bnx2x_cl45_read(bp, phy,
7718                       MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_STATUS, &val1);
7719         DP(NETIF_MSG_LINK, "8705 LASI status 0x%x\n", val1);
7720
7721         bnx2x_cl45_read(bp, phy,
7722                       MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_STATUS, &val1);
7723         DP(NETIF_MSG_LINK, "8705 LASI status 0x%x\n", val1);
7724
7725         bnx2x_cl45_read(bp, phy,
7726                       MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_SD, &rx_sd);
7727
7728         bnx2x_cl45_read(bp, phy,
7729                       MDIO_PMA_DEVAD, 0xc809, &val1);
7730         bnx2x_cl45_read(bp, phy,
7731                       MDIO_PMA_DEVAD, 0xc809, &val1);
7732
7733         DP(NETIF_MSG_LINK, "8705 1.c809 val=0x%x\n", val1);
7734         link_up = ((rx_sd & 0x1) && (val1 & (1<<9)) && ((val1 & (1<<8)) == 0));
7735         if (link_up) {
7736                 vars->line_speed = SPEED_10000;
7737                 bnx2x_ext_phy_resolve_fc(phy, params, vars);
7738         }
7739         return link_up;
7740 }
7741
7742 /******************************************************************/
7743 /*                      SFP+ module Section                       */
7744 /******************************************************************/
7745 static void bnx2x_set_disable_pmd_transmit(struct link_params *params,
7746                                            struct bnx2x_phy *phy,
7747                                            u8 pmd_dis)
7748 {
7749         struct bnx2x *bp = params->bp;
7750         /* Disable transmitter only for bootcodes which can enable it afterwards
7751          * (for D3 link)
7752          */
7753         if (pmd_dis) {
7754                 if (params->feature_config_flags &
7755                      FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED)
7756                         DP(NETIF_MSG_LINK, "Disabling PMD transmitter\n");
7757                 else {
7758                         DP(NETIF_MSG_LINK, "NOT disabling PMD transmitter\n");
7759                         return;
7760                 }
7761         } else
7762                 DP(NETIF_MSG_LINK, "Enabling PMD transmitter\n");
7763         bnx2x_cl45_write(bp, phy,
7764                          MDIO_PMA_DEVAD,
7765                          MDIO_PMA_REG_TX_DISABLE, pmd_dis);
7766 }
7767
7768 static u8 bnx2x_get_gpio_port(struct link_params *params)
7769 {
7770         u8 gpio_port;
7771         u32 swap_val, swap_override;
7772         struct bnx2x *bp = params->bp;
7773         if (CHIP_IS_E2(bp))
7774                 gpio_port = BP_PATH(bp);
7775         else
7776                 gpio_port = params->port;
7777         swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
7778         swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
7779         return gpio_port ^ (swap_val && swap_override);
7780 }
7781
7782 static void bnx2x_sfp_e1e2_set_transmitter(struct link_params *params,
7783                                            struct bnx2x_phy *phy,
7784                                            u8 tx_en)
7785 {
7786         u16 val;
7787         u8 port = params->port;
7788         struct bnx2x *bp = params->bp;
7789         u32 tx_en_mode;
7790
7791         /* Disable/Enable transmitter ( TX laser of the SFP+ module.)*/
7792         tx_en_mode = REG_RD(bp, params->shmem_base +
7793                             offsetof(struct shmem_region,
7794                                      dev_info.port_hw_config[port].sfp_ctrl)) &
7795                 PORT_HW_CFG_TX_LASER_MASK;
7796         DP(NETIF_MSG_LINK, "Setting transmitter tx_en=%x for port %x "
7797                            "mode = %x\n", tx_en, port, tx_en_mode);
7798         switch (tx_en_mode) {
7799         case PORT_HW_CFG_TX_LASER_MDIO:
7800
7801                 bnx2x_cl45_read(bp, phy,
7802                                 MDIO_PMA_DEVAD,
7803                                 MDIO_PMA_REG_PHY_IDENTIFIER,
7804                                 &val);
7805
7806                 if (tx_en)
7807                         val &= ~(1<<15);
7808                 else
7809                         val |= (1<<15);
7810
7811                 bnx2x_cl45_write(bp, phy,
7812                                  MDIO_PMA_DEVAD,
7813                                  MDIO_PMA_REG_PHY_IDENTIFIER,
7814                                  val);
7815         break;
7816         case PORT_HW_CFG_TX_LASER_GPIO0:
7817         case PORT_HW_CFG_TX_LASER_GPIO1:
7818         case PORT_HW_CFG_TX_LASER_GPIO2:
7819         case PORT_HW_CFG_TX_LASER_GPIO3:
7820         {
7821                 u16 gpio_pin;
7822                 u8 gpio_port, gpio_mode;
7823                 if (tx_en)
7824                         gpio_mode = MISC_REGISTERS_GPIO_OUTPUT_HIGH;
7825                 else
7826                         gpio_mode = MISC_REGISTERS_GPIO_OUTPUT_LOW;
7827
7828                 gpio_pin = tx_en_mode - PORT_HW_CFG_TX_LASER_GPIO0;
7829                 gpio_port = bnx2x_get_gpio_port(params);
7830                 bnx2x_set_gpio(bp, gpio_pin, gpio_mode, gpio_port);
7831                 break;
7832         }
7833         default:
7834                 DP(NETIF_MSG_LINK, "Invalid TX_LASER_MDIO 0x%x\n", tx_en_mode);
7835                 break;
7836         }
7837 }
7838
7839 static void bnx2x_sfp_set_transmitter(struct link_params *params,
7840                                       struct bnx2x_phy *phy,
7841                                       u8 tx_en)
7842 {
7843         struct bnx2x *bp = params->bp;
7844         DP(NETIF_MSG_LINK, "Setting SFP+ transmitter to %d\n", tx_en);
7845         if (CHIP_IS_E3(bp))
7846                 bnx2x_sfp_e3_set_transmitter(params, phy, tx_en);
7847         else
7848                 bnx2x_sfp_e1e2_set_transmitter(params, phy, tx_en);
7849 }
7850
7851 static int bnx2x_8726_read_sfp_module_eeprom(struct bnx2x_phy *phy,
7852                                              struct link_params *params,
7853                                              u8 dev_addr, u16 addr, u8 byte_cnt,
7854                                              u8 *o_buf, u8 is_init)
7855 {
7856         struct bnx2x *bp = params->bp;
7857         u16 val = 0;
7858         u16 i;
7859         if (byte_cnt > SFP_EEPROM_PAGE_SIZE) {
7860                 DP(NETIF_MSG_LINK,
7861                    "Reading from eeprom is limited to 0xf\n");
7862                 return -EINVAL;
7863         }
7864         /* Set the read command byte count */
7865         bnx2x_cl45_write(bp, phy,
7866                          MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT,
7867                          (byte_cnt | (dev_addr << 8)));
7868
7869         /* Set the read command address */
7870         bnx2x_cl45_write(bp, phy,
7871                          MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR,
7872                          addr);
7873
7874         /* Activate read command */
7875         bnx2x_cl45_write(bp, phy,
7876                          MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
7877                          0x2c0f);
7878
7879         /* Wait up to 500us for command complete status */
7880         for (i = 0; i < 100; i++) {
7881                 bnx2x_cl45_read(bp, phy,
7882                                 MDIO_PMA_DEVAD,
7883                                 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
7884                 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
7885                     MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE)
7886                         break;
7887                 udelay(5);
7888         }
7889
7890         if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) !=
7891                     MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) {
7892                 DP(NETIF_MSG_LINK,
7893                          "Got bad status 0x%x when reading from SFP+ EEPROM\n",
7894                          (val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK));
7895                 return -EINVAL;
7896         }
7897
7898         /* Read the buffer */
7899         for (i = 0; i < byte_cnt; i++) {
7900                 bnx2x_cl45_read(bp, phy,
7901                                 MDIO_PMA_DEVAD,
7902                                 MDIO_PMA_REG_8726_TWO_WIRE_DATA_BUF + i, &val);
7903                 o_buf[i] = (u8)(val & MDIO_PMA_REG_8726_TWO_WIRE_DATA_MASK);
7904         }
7905
7906         for (i = 0; i < 100; i++) {
7907                 bnx2x_cl45_read(bp, phy,
7908                                 MDIO_PMA_DEVAD,
7909                                 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
7910                 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
7911                     MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE)
7912                         return 0;
7913                 usleep_range(1000, 2000);
7914         }
7915         return -EINVAL;
7916 }
7917
7918 static void bnx2x_warpcore_power_module(struct link_params *params,
7919                                         u8 power)
7920 {
7921         u32 pin_cfg;
7922         struct bnx2x *bp = params->bp;
7923
7924         pin_cfg = (REG_RD(bp, params->shmem_base +
7925                           offsetof(struct shmem_region,
7926                         dev_info.port_hw_config[params->port].e3_sfp_ctrl)) &
7927                         PORT_HW_CFG_E3_PWR_DIS_MASK) >>
7928                         PORT_HW_CFG_E3_PWR_DIS_SHIFT;
7929
7930         if (pin_cfg == PIN_CFG_NA)
7931                 return;
7932         DP(NETIF_MSG_LINK, "Setting SFP+ module power to %d using pin cfg %d\n",
7933                        power, pin_cfg);
7934         /* Low ==> corresponding SFP+ module is powered
7935          * high ==> the SFP+ module is powered down
7936          */
7937         bnx2x_set_cfg_pin(bp, pin_cfg, power ^ 1);
7938 }
7939 static int bnx2x_warpcore_read_sfp_module_eeprom(struct bnx2x_phy *phy,
7940                                                  struct link_params *params,
7941                                                  u8 dev_addr,
7942                                                  u16 addr, u8 byte_cnt,
7943                                                  u8 *o_buf, u8 is_init)
7944 {
7945         int rc = 0;
7946         u8 i, j = 0, cnt = 0;
7947         u32 data_array[4];
7948         u16 addr32;
7949         struct bnx2x *bp = params->bp;
7950
7951         if (byte_cnt > SFP_EEPROM_PAGE_SIZE) {
7952                 DP(NETIF_MSG_LINK,
7953                    "Reading from eeprom is limited to 16 bytes\n");
7954                 return -EINVAL;
7955         }
7956
7957         /* 4 byte aligned address */
7958         addr32 = addr & (~0x3);
7959         do {
7960                 if ((!is_init) && (cnt == I2C_WA_PWR_ITER)) {
7961                         bnx2x_warpcore_power_module(params, 0);
7962                         /* Note that 100us are not enough here */
7963                         usleep_range(1000, 2000);
7964                         bnx2x_warpcore_power_module(params, 1);
7965                 }
7966                 rc = bnx2x_bsc_read(params, bp, dev_addr, addr32, 0, byte_cnt,
7967                                     data_array);
7968         } while ((rc != 0) && (++cnt < I2C_WA_RETRY_CNT));
7969
7970         if (rc == 0) {
7971                 for (i = (addr - addr32); i < byte_cnt + (addr - addr32); i++) {
7972                         o_buf[j] = *((u8 *)data_array + i);
7973                         j++;
7974                 }
7975         }
7976
7977         return rc;
7978 }
7979
7980 static int bnx2x_8727_read_sfp_module_eeprom(struct bnx2x_phy *phy,
7981                                              struct link_params *params,
7982                                              u8 dev_addr, u16 addr, u8 byte_cnt,
7983                                              u8 *o_buf, u8 is_init)
7984 {
7985         struct bnx2x *bp = params->bp;
7986         u16 val, i;
7987
7988         if (byte_cnt > SFP_EEPROM_PAGE_SIZE) {
7989                 DP(NETIF_MSG_LINK,
7990                    "Reading from eeprom is limited to 0xf\n");
7991                 return -EINVAL;
7992         }
7993
7994         /* Set 2-wire transfer rate of SFP+ module EEPROM
7995          * to 100Khz since some DACs(direct attached cables) do
7996          * not work at 400Khz.
7997          */
7998         bnx2x_cl45_write(bp, phy,
7999                          MDIO_PMA_DEVAD,
8000                          MDIO_PMA_REG_8727_TWO_WIRE_SLAVE_ADDR,
8001                          ((dev_addr << 8) | 1));
8002
8003         /* Need to read from 1.8000 to clear it */
8004         bnx2x_cl45_read(bp, phy,
8005                         MDIO_PMA_DEVAD,
8006                         MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
8007                         &val);
8008
8009         /* Set the read command byte count */
8010         bnx2x_cl45_write(bp, phy,
8011                          MDIO_PMA_DEVAD,
8012                          MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT,
8013                          ((byte_cnt < 2) ? 2 : byte_cnt));
8014
8015         /* Set the read command address */
8016         bnx2x_cl45_write(bp, phy,
8017                          MDIO_PMA_DEVAD,
8018                          MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR,
8019                          addr);
8020         /* Set the destination address */
8021         bnx2x_cl45_write(bp, phy,
8022                          MDIO_PMA_DEVAD,
8023                          0x8004,
8024                          MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF);
8025
8026         /* Activate read command */
8027         bnx2x_cl45_write(bp, phy,
8028                          MDIO_PMA_DEVAD,
8029                          MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
8030                          0x8002);
8031         /* Wait appropriate time for two-wire command to finish before
8032          * polling the status register
8033          */
8034         usleep_range(1000, 2000);
8035
8036         /* Wait up to 500us for command complete status */
8037         for (i = 0; i < 100; i++) {
8038                 bnx2x_cl45_read(bp, phy,
8039                                 MDIO_PMA_DEVAD,
8040                                 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
8041                 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
8042                     MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE)
8043                         break;
8044                 udelay(5);
8045         }
8046
8047         if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) !=
8048                     MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) {
8049                 DP(NETIF_MSG_LINK,
8050                          "Got bad status 0x%x when reading from SFP+ EEPROM\n",
8051                          (val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK));
8052                 return -EFAULT;
8053         }
8054
8055         /* Read the buffer */
8056         for (i = 0; i < byte_cnt; i++) {
8057                 bnx2x_cl45_read(bp, phy,
8058                                 MDIO_PMA_DEVAD,
8059                                 MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF + i, &val);
8060                 o_buf[i] = (u8)(val & MDIO_PMA_REG_8727_TWO_WIRE_DATA_MASK);
8061         }
8062
8063         for (i = 0; i < 100; i++) {
8064                 bnx2x_cl45_read(bp, phy,
8065                                 MDIO_PMA_DEVAD,
8066                                 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
8067                 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
8068                     MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE)
8069                         return 0;
8070                 usleep_range(1000, 2000);
8071         }
8072
8073         return -EINVAL;
8074 }
8075 int bnx2x_read_sfp_module_eeprom(struct bnx2x_phy *phy,
8076                                  struct link_params *params, u8 dev_addr,
8077                                  u16 addr, u16 byte_cnt, u8 *o_buf)
8078 {
8079         int rc = 0;
8080         struct bnx2x *bp = params->bp;
8081         u8 xfer_size;
8082         u8 *user_data = o_buf;
8083         read_sfp_module_eeprom_func_p read_func;
8084
8085         if ((dev_addr != 0xa0) && (dev_addr != 0xa2)) {
8086                 DP(NETIF_MSG_LINK, "invalid dev_addr 0x%x\n", dev_addr);
8087                 return -EINVAL;
8088         }
8089
8090         switch (phy->type) {
8091         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
8092                 read_func = bnx2x_8726_read_sfp_module_eeprom;
8093                 break;
8094         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
8095         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
8096                 read_func = bnx2x_8727_read_sfp_module_eeprom;
8097                 break;
8098         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
8099                 read_func = bnx2x_warpcore_read_sfp_module_eeprom;
8100                 break;
8101         default:
8102                 return -EOPNOTSUPP;
8103         }
8104
8105         while (!rc && (byte_cnt > 0)) {
8106                 xfer_size = (byte_cnt > SFP_EEPROM_PAGE_SIZE) ?
8107                         SFP_EEPROM_PAGE_SIZE : byte_cnt;
8108                 rc = read_func(phy, params, dev_addr, addr, xfer_size,
8109                                user_data, 0);
8110                 byte_cnt -= xfer_size;
8111                 user_data += xfer_size;
8112                 addr += xfer_size;
8113         }
8114         return rc;
8115 }
8116
8117 static int bnx2x_get_edc_mode(struct bnx2x_phy *phy,
8118                               struct link_params *params,
8119                               u16 *edc_mode)
8120 {
8121         struct bnx2x *bp = params->bp;
8122         u32 sync_offset = 0, phy_idx, media_types;
8123         u8 val[SFP_EEPROM_FC_TX_TECH_ADDR + 1], check_limiting_mode = 0;
8124         *edc_mode = EDC_MODE_LIMITING;
8125         phy->media_type = ETH_PHY_UNSPECIFIED;
8126         /* First check for copper cable */
8127         if (bnx2x_read_sfp_module_eeprom(phy,
8128                                          params,
8129                                          I2C_DEV_ADDR_A0,
8130                                          0,
8131                                          SFP_EEPROM_FC_TX_TECH_ADDR + 1,
8132                                          (u8 *)val) != 0) {
8133                 DP(NETIF_MSG_LINK, "Failed to read from SFP+ module EEPROM\n");
8134                 return -EINVAL;
8135         }
8136         params->link_attr_sync &= ~LINK_SFP_EEPROM_COMP_CODE_MASK;
8137         params->link_attr_sync |= val[SFP_EEPROM_10G_COMP_CODE_ADDR] <<
8138                 LINK_SFP_EEPROM_COMP_CODE_SHIFT;
8139         bnx2x_update_link_attr(params, params->link_attr_sync);
8140         switch (val[SFP_EEPROM_CON_TYPE_ADDR]) {
8141         case SFP_EEPROM_CON_TYPE_VAL_COPPER:
8142         {
8143                 u8 copper_module_type;
8144                 phy->media_type = ETH_PHY_DA_TWINAX;
8145                 /* Check if its active cable (includes SFP+ module)
8146                  * of passive cable
8147                  */
8148                 copper_module_type = val[SFP_EEPROM_FC_TX_TECH_ADDR];
8149
8150                 if (copper_module_type &
8151                     SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE) {
8152                         DP(NETIF_MSG_LINK, "Active Copper cable detected\n");
8153                         if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
8154                                 *edc_mode = EDC_MODE_ACTIVE_DAC;
8155                         else
8156                                 check_limiting_mode = 1;
8157                 } else {
8158                         *edc_mode = EDC_MODE_PASSIVE_DAC;
8159                         /* Even in case PASSIVE_DAC indication is not set,
8160                          * treat it as a passive DAC cable, since some cables
8161                          * don't have this indication.
8162                          */
8163                         if (copper_module_type &
8164                             SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE) {
8165                                 DP(NETIF_MSG_LINK,
8166                                    "Passive Copper cable detected\n");
8167                         } else {
8168                                 DP(NETIF_MSG_LINK,
8169                                    "Unknown copper-cable-type\n");
8170                         }
8171                 }
8172                 break;
8173         }
8174         case SFP_EEPROM_CON_TYPE_VAL_UNKNOWN:
8175         case SFP_EEPROM_CON_TYPE_VAL_LC:
8176         case SFP_EEPROM_CON_TYPE_VAL_RJ45:
8177                 check_limiting_mode = 1;
8178                 if (((val[SFP_EEPROM_10G_COMP_CODE_ADDR] &
8179                      (SFP_EEPROM_10G_COMP_CODE_SR_MASK |
8180                       SFP_EEPROM_10G_COMP_CODE_LR_MASK |
8181                        SFP_EEPROM_10G_COMP_CODE_LRM_MASK)) == 0) &&
8182                     (val[SFP_EEPROM_1G_COMP_CODE_ADDR] != 0)) {
8183                         DP(NETIF_MSG_LINK, "1G SFP module detected\n");
8184                         phy->media_type = ETH_PHY_SFP_1G_FIBER;
8185                         if (phy->req_line_speed != SPEED_1000) {
8186                                 u8 gport = params->port;
8187                                 phy->req_line_speed = SPEED_1000;
8188                                 if (!CHIP_IS_E1x(bp)) {
8189                                         gport = BP_PATH(bp) +
8190                                         (params->port << 1);
8191                                 }
8192                                 netdev_err(bp->dev,
8193                                            "Warning: Link speed was forced to 1000Mbps. Current SFP module in port %d is not compliant with 10G Ethernet\n",
8194                                            gport);
8195                         }
8196                         if (val[SFP_EEPROM_1G_COMP_CODE_ADDR] &
8197                             SFP_EEPROM_1G_COMP_CODE_BASE_T) {
8198                                 bnx2x_sfp_set_transmitter(params, phy, 0);
8199                                 msleep(40);
8200                                 bnx2x_sfp_set_transmitter(params, phy, 1);
8201                         }
8202                 } else {
8203                         int idx, cfg_idx = 0;
8204                         DP(NETIF_MSG_LINK, "10G Optic module detected\n");
8205                         for (idx = INT_PHY; idx < MAX_PHYS; idx++) {
8206                                 if (params->phy[idx].type == phy->type) {
8207                                         cfg_idx = LINK_CONFIG_IDX(idx);
8208                                         break;
8209                                 }
8210                         }
8211                         phy->media_type = ETH_PHY_SFPP_10G_FIBER;
8212                         phy->req_line_speed = params->req_line_speed[cfg_idx];
8213                 }
8214                 break;
8215         default:
8216                 DP(NETIF_MSG_LINK, "Unable to determine module type 0x%x !!!\n",
8217                          val[SFP_EEPROM_CON_TYPE_ADDR]);
8218                 return -EINVAL;
8219         }
8220         sync_offset = params->shmem_base +
8221                 offsetof(struct shmem_region,
8222                          dev_info.port_hw_config[params->port].media_type);
8223         media_types = REG_RD(bp, sync_offset);
8224         /* Update media type for non-PMF sync */
8225         for (phy_idx = INT_PHY; phy_idx < MAX_PHYS; phy_idx++) {
8226                 if (&(params->phy[phy_idx]) == phy) {
8227                         media_types &= ~(PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK <<
8228                                 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT * phy_idx));
8229                         media_types |= ((phy->media_type &
8230                                         PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) <<
8231                                 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT * phy_idx));
8232                         break;
8233                 }
8234         }
8235         REG_WR(bp, sync_offset, media_types);
8236         if (check_limiting_mode) {
8237                 u8 options[SFP_EEPROM_OPTIONS_SIZE];
8238                 if (bnx2x_read_sfp_module_eeprom(phy,
8239                                                  params,
8240                                                  I2C_DEV_ADDR_A0,
8241                                                  SFP_EEPROM_OPTIONS_ADDR,
8242                                                  SFP_EEPROM_OPTIONS_SIZE,
8243                                                  options) != 0) {
8244                         DP(NETIF_MSG_LINK,
8245                            "Failed to read Option field from module EEPROM\n");
8246                         return -EINVAL;
8247                 }
8248                 if ((options[0] & SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK))
8249                         *edc_mode = EDC_MODE_LINEAR;
8250                 else
8251                         *edc_mode = EDC_MODE_LIMITING;
8252         }
8253         DP(NETIF_MSG_LINK, "EDC mode is set to 0x%x\n", *edc_mode);
8254         return 0;
8255 }
8256 /* This function read the relevant field from the module (SFP+), and verify it
8257  * is compliant with this board
8258  */
8259 static int bnx2x_verify_sfp_module(struct bnx2x_phy *phy,
8260                                    struct link_params *params)
8261 {
8262         struct bnx2x *bp = params->bp;
8263         u32 val, cmd;
8264         u32 fw_resp, fw_cmd_param;
8265         char vendor_name[SFP_EEPROM_VENDOR_NAME_SIZE+1];
8266         char vendor_pn[SFP_EEPROM_PART_NO_SIZE+1];
8267         phy->flags &= ~FLAGS_SFP_NOT_APPROVED;
8268         val = REG_RD(bp, params->shmem_base +
8269                          offsetof(struct shmem_region, dev_info.
8270                                   port_feature_config[params->port].config));
8271         if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
8272             PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_NO_ENFORCEMENT) {
8273                 DP(NETIF_MSG_LINK, "NOT enforcing module verification\n");
8274                 return 0;
8275         }
8276
8277         if (params->feature_config_flags &
8278             FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY) {
8279                 /* Use specific phy request */
8280                 cmd = DRV_MSG_CODE_VRFY_SPECIFIC_PHY_OPT_MDL;
8281         } else if (params->feature_config_flags &
8282                    FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY) {
8283                 /* Use first phy request only in case of non-dual media*/
8284                 if (DUAL_MEDIA(params)) {
8285                         DP(NETIF_MSG_LINK,
8286                            "FW does not support OPT MDL verification\n");
8287                         return -EINVAL;
8288                 }
8289                 cmd = DRV_MSG_CODE_VRFY_FIRST_PHY_OPT_MDL;
8290         } else {
8291                 /* No support in OPT MDL detection */
8292                 DP(NETIF_MSG_LINK,
8293                    "FW does not support OPT MDL verification\n");
8294                 return -EINVAL;
8295         }
8296
8297         fw_cmd_param = FW_PARAM_SET(phy->addr, phy->type, phy->mdio_ctrl);
8298         fw_resp = bnx2x_fw_command(bp, cmd, fw_cmd_param);
8299         if (fw_resp == FW_MSG_CODE_VRFY_OPT_MDL_SUCCESS) {
8300                 DP(NETIF_MSG_LINK, "Approved module\n");
8301                 return 0;
8302         }
8303
8304         /* Format the warning message */
8305         if (bnx2x_read_sfp_module_eeprom(phy,
8306                                          params,
8307                                          I2C_DEV_ADDR_A0,
8308                                          SFP_EEPROM_VENDOR_NAME_ADDR,
8309                                          SFP_EEPROM_VENDOR_NAME_SIZE,
8310                                          (u8 *)vendor_name))
8311                 vendor_name[0] = '\0';
8312         else
8313                 vendor_name[SFP_EEPROM_VENDOR_NAME_SIZE] = '\0';
8314         if (bnx2x_read_sfp_module_eeprom(phy,
8315                                          params,
8316                                          I2C_DEV_ADDR_A0,
8317                                          SFP_EEPROM_PART_NO_ADDR,
8318                                          SFP_EEPROM_PART_NO_SIZE,
8319                                          (u8 *)vendor_pn))
8320                 vendor_pn[0] = '\0';
8321         else
8322                 vendor_pn[SFP_EEPROM_PART_NO_SIZE] = '\0';
8323
8324         netdev_err(bp->dev,  "Warning: Unqualified SFP+ module detected,"
8325                               " Port %d from %s part number %s\n",
8326                          params->port, vendor_name, vendor_pn);
8327         if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) !=
8328             PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_WARNING_MSG)
8329                 phy->flags |= FLAGS_SFP_NOT_APPROVED;
8330         return -EINVAL;
8331 }
8332
8333 static int bnx2x_wait_for_sfp_module_initialized(struct bnx2x_phy *phy,
8334                                                  struct link_params *params)
8335
8336 {
8337         u8 val;
8338         int rc;
8339         struct bnx2x *bp = params->bp;
8340         u16 timeout;
8341         /* Initialization time after hot-plug may take up to 300ms for
8342          * some phys type ( e.g. JDSU )
8343          */
8344
8345         for (timeout = 0; timeout < 60; timeout++) {
8346                 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
8347                         rc = bnx2x_warpcore_read_sfp_module_eeprom(
8348                                 phy, params, I2C_DEV_ADDR_A0, 1, 1, &val,
8349                                 1);
8350                 else
8351                         rc = bnx2x_read_sfp_module_eeprom(phy, params,
8352                                                           I2C_DEV_ADDR_A0,
8353                                                           1, 1, &val);
8354                 if (rc == 0) {
8355                         DP(NETIF_MSG_LINK,
8356                            "SFP+ module initialization took %d ms\n",
8357                            timeout * 5);
8358                         return 0;
8359                 }
8360                 usleep_range(5000, 10000);
8361         }
8362         rc = bnx2x_read_sfp_module_eeprom(phy, params, I2C_DEV_ADDR_A0,
8363                                           1, 1, &val);
8364         return rc;
8365 }
8366
8367 static void bnx2x_8727_power_module(struct bnx2x *bp,
8368                                     struct bnx2x_phy *phy,
8369                                     u8 is_power_up) {
8370         /* Make sure GPIOs are not using for LED mode */
8371         u16 val;
8372         /* In the GPIO register, bit 4 is use to determine if the GPIOs are
8373          * operating as INPUT or as OUTPUT. Bit 1 is for input, and 0 for
8374          * output
8375          * Bits 0-1 determine the GPIOs value for OUTPUT in case bit 4 val is 0
8376          * Bits 8-9 determine the GPIOs value for INPUT in case bit 4 val is 1
8377          * where the 1st bit is the over-current(only input), and 2nd bit is
8378          * for power( only output )
8379          *
8380          * In case of NOC feature is disabled and power is up, set GPIO control
8381          *  as input to enable listening of over-current indication
8382          */
8383         if (phy->flags & FLAGS_NOC)
8384                 return;
8385         if (is_power_up)
8386                 val = (1<<4);
8387         else
8388                 /* Set GPIO control to OUTPUT, and set the power bit
8389                  * to according to the is_power_up
8390                  */
8391                 val = (1<<1);
8392
8393         bnx2x_cl45_write(bp, phy,
8394                          MDIO_PMA_DEVAD,
8395                          MDIO_PMA_REG_8727_GPIO_CTRL,
8396                          val);
8397 }
8398
8399 static int bnx2x_8726_set_limiting_mode(struct bnx2x *bp,
8400                                         struct bnx2x_phy *phy,
8401                                         u16 edc_mode)
8402 {
8403         u16 cur_limiting_mode;
8404
8405         bnx2x_cl45_read(bp, phy,
8406                         MDIO_PMA_DEVAD,
8407                         MDIO_PMA_REG_ROM_VER2,
8408                         &cur_limiting_mode);
8409         DP(NETIF_MSG_LINK, "Current Limiting mode is 0x%x\n",
8410                  cur_limiting_mode);
8411
8412         if (edc_mode == EDC_MODE_LIMITING) {
8413                 DP(NETIF_MSG_LINK, "Setting LIMITING MODE\n");
8414                 bnx2x_cl45_write(bp, phy,
8415                                  MDIO_PMA_DEVAD,
8416                                  MDIO_PMA_REG_ROM_VER2,
8417                                  EDC_MODE_LIMITING);
8418         } else { /* LRM mode ( default )*/
8419
8420                 DP(NETIF_MSG_LINK, "Setting LRM MODE\n");
8421
8422                 /* Changing to LRM mode takes quite few seconds. So do it only
8423                  * if current mode is limiting (default is LRM)
8424                  */
8425                 if (cur_limiting_mode != EDC_MODE_LIMITING)
8426                         return 0;
8427
8428                 bnx2x_cl45_write(bp, phy,
8429                                  MDIO_PMA_DEVAD,
8430                                  MDIO_PMA_REG_LRM_MODE,
8431                                  0);
8432                 bnx2x_cl45_write(bp, phy,
8433                                  MDIO_PMA_DEVAD,
8434                                  MDIO_PMA_REG_ROM_VER2,
8435                                  0x128);
8436                 bnx2x_cl45_write(bp, phy,
8437                                  MDIO_PMA_DEVAD,
8438                                  MDIO_PMA_REG_MISC_CTRL0,
8439                                  0x4008);
8440                 bnx2x_cl45_write(bp, phy,
8441                                  MDIO_PMA_DEVAD,
8442                                  MDIO_PMA_REG_LRM_MODE,
8443                                  0xaaaa);
8444         }
8445         return 0;
8446 }
8447
8448 static int bnx2x_8727_set_limiting_mode(struct bnx2x *bp,
8449                                         struct bnx2x_phy *phy,
8450                                         u16 edc_mode)
8451 {
8452         u16 phy_identifier;
8453         u16 rom_ver2_val;
8454         bnx2x_cl45_read(bp, phy,
8455                         MDIO_PMA_DEVAD,
8456                         MDIO_PMA_REG_PHY_IDENTIFIER,
8457                         &phy_identifier);
8458
8459         bnx2x_cl45_write(bp, phy,
8460                          MDIO_PMA_DEVAD,
8461                          MDIO_PMA_REG_PHY_IDENTIFIER,
8462                          (phy_identifier & ~(1<<9)));
8463
8464         bnx2x_cl45_read(bp, phy,
8465                         MDIO_PMA_DEVAD,
8466                         MDIO_PMA_REG_ROM_VER2,
8467                         &rom_ver2_val);
8468         /* Keep the MSB 8-bits, and set the LSB 8-bits with the edc_mode */
8469         bnx2x_cl45_write(bp, phy,
8470                          MDIO_PMA_DEVAD,
8471                          MDIO_PMA_REG_ROM_VER2,
8472                          (rom_ver2_val & 0xff00) | (edc_mode & 0x00ff));
8473
8474         bnx2x_cl45_write(bp, phy,
8475                          MDIO_PMA_DEVAD,
8476                          MDIO_PMA_REG_PHY_IDENTIFIER,
8477                          (phy_identifier | (1<<9)));
8478
8479         return 0;
8480 }
8481
8482 static void bnx2x_8727_specific_func(struct bnx2x_phy *phy,
8483                                      struct link_params *params,
8484                                      u32 action)
8485 {
8486         struct bnx2x *bp = params->bp;
8487         u16 val;
8488         switch (action) {
8489         case DISABLE_TX:
8490                 bnx2x_sfp_set_transmitter(params, phy, 0);
8491                 break;
8492         case ENABLE_TX:
8493                 if (!(phy->flags & FLAGS_SFP_NOT_APPROVED))
8494                         bnx2x_sfp_set_transmitter(params, phy, 1);
8495                 break;
8496         case PHY_INIT:
8497                 bnx2x_cl45_write(bp, phy,
8498                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
8499                                  (1<<2) | (1<<5));
8500                 bnx2x_cl45_write(bp, phy,
8501                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_TXCTRL,
8502                                  0);
8503                 bnx2x_cl45_write(bp, phy,
8504                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x0006);
8505                 /* Make MOD_ABS give interrupt on change */
8506                 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
8507                                 MDIO_PMA_REG_8727_PCS_OPT_CTRL,
8508                                 &val);
8509                 val |= (1<<12);
8510                 if (phy->flags & FLAGS_NOC)
8511                         val |= (3<<5);
8512                 /* Set 8727 GPIOs to input to allow reading from the 8727 GPIO0
8513                  * status which reflect SFP+ module over-current
8514                  */
8515                 if (!(phy->flags & FLAGS_NOC))
8516                         val &= 0xff8f; /* Reset bits 4-6 */
8517                 bnx2x_cl45_write(bp, phy,
8518                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_PCS_OPT_CTRL,
8519                                  val);
8520                 break;
8521         default:
8522                 DP(NETIF_MSG_LINK, "Function 0x%x not supported by 8727\n",
8523                    action);
8524                 return;
8525         }
8526 }
8527
8528 static void bnx2x_set_e1e2_module_fault_led(struct link_params *params,
8529                                            u8 gpio_mode)
8530 {
8531         struct bnx2x *bp = params->bp;
8532
8533         u32 fault_led_gpio = REG_RD(bp, params->shmem_base +
8534                             offsetof(struct shmem_region,
8535                         dev_info.port_hw_config[params->port].sfp_ctrl)) &
8536                 PORT_HW_CFG_FAULT_MODULE_LED_MASK;
8537         switch (fault_led_gpio) {
8538         case PORT_HW_CFG_FAULT_MODULE_LED_DISABLED:
8539                 return;
8540         case PORT_HW_CFG_FAULT_MODULE_LED_GPIO0:
8541         case PORT_HW_CFG_FAULT_MODULE_LED_GPIO1:
8542         case PORT_HW_CFG_FAULT_MODULE_LED_GPIO2:
8543         case PORT_HW_CFG_FAULT_MODULE_LED_GPIO3:
8544         {
8545                 u8 gpio_port = bnx2x_get_gpio_port(params);
8546                 u16 gpio_pin = fault_led_gpio -
8547                         PORT_HW_CFG_FAULT_MODULE_LED_GPIO0;
8548                 DP(NETIF_MSG_LINK, "Set fault module-detected led "
8549                                    "pin %x port %x mode %x\n",
8550                                gpio_pin, gpio_port, gpio_mode);
8551                 bnx2x_set_gpio(bp, gpio_pin, gpio_mode, gpio_port);
8552         }
8553         break;
8554         default:
8555                 DP(NETIF_MSG_LINK, "Error: Invalid fault led mode 0x%x\n",
8556                                fault_led_gpio);
8557         }
8558 }
8559
8560 static void bnx2x_set_e3_module_fault_led(struct link_params *params,
8561                                           u8 gpio_mode)
8562 {
8563         u32 pin_cfg;
8564         u8 port = params->port;
8565         struct bnx2x *bp = params->bp;
8566         pin_cfg = (REG_RD(bp, params->shmem_base +
8567                          offsetof(struct shmem_region,
8568                                   dev_info.port_hw_config[port].e3_sfp_ctrl)) &
8569                 PORT_HW_CFG_E3_FAULT_MDL_LED_MASK) >>
8570                 PORT_HW_CFG_E3_FAULT_MDL_LED_SHIFT;
8571         DP(NETIF_MSG_LINK, "Setting Fault LED to %d using pin cfg %d\n",
8572                        gpio_mode, pin_cfg);
8573         bnx2x_set_cfg_pin(bp, pin_cfg, gpio_mode);
8574 }
8575
8576 static void bnx2x_set_sfp_module_fault_led(struct link_params *params,
8577                                            u8 gpio_mode)
8578 {
8579         struct bnx2x *bp = params->bp;
8580         DP(NETIF_MSG_LINK, "Setting SFP+ module fault LED to %d\n", gpio_mode);
8581         if (CHIP_IS_E3(bp)) {
8582                 /* Low ==> if SFP+ module is supported otherwise
8583                  * High ==> if SFP+ module is not on the approved vendor list
8584                  */
8585                 bnx2x_set_e3_module_fault_led(params, gpio_mode);
8586         } else
8587                 bnx2x_set_e1e2_module_fault_led(params, gpio_mode);
8588 }
8589
8590 static void bnx2x_warpcore_hw_reset(struct bnx2x_phy *phy,
8591                                     struct link_params *params)
8592 {
8593         struct bnx2x *bp = params->bp;
8594         bnx2x_warpcore_power_module(params, 0);
8595         /* Put Warpcore in low power mode */
8596         REG_WR(bp, MISC_REG_WC0_RESET, 0x0c0e);
8597
8598         /* Put LCPLL in low power mode */
8599         REG_WR(bp, MISC_REG_LCPLL_E40_PWRDWN, 1);
8600         REG_WR(bp, MISC_REG_LCPLL_E40_RESETB_ANA, 0);
8601         REG_WR(bp, MISC_REG_LCPLL_E40_RESETB_DIG, 0);
8602 }
8603
8604 static void bnx2x_power_sfp_module(struct link_params *params,
8605                                    struct bnx2x_phy *phy,
8606                                    u8 power)
8607 {
8608         struct bnx2x *bp = params->bp;
8609         DP(NETIF_MSG_LINK, "Setting SFP+ power to %x\n", power);
8610
8611         switch (phy->type) {
8612         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
8613         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
8614                 bnx2x_8727_power_module(params->bp, phy, power);
8615                 break;
8616         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
8617                 bnx2x_warpcore_power_module(params, power);
8618                 break;
8619         default:
8620                 break;
8621         }
8622 }
8623 static void bnx2x_warpcore_set_limiting_mode(struct link_params *params,
8624                                              struct bnx2x_phy *phy,
8625                                              u16 edc_mode)
8626 {
8627         u16 val = 0;
8628         u16 mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_DEFAULT;
8629         struct bnx2x *bp = params->bp;
8630
8631         u8 lane = bnx2x_get_warpcore_lane(phy, params);
8632         /* This is a global register which controls all lanes */
8633         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
8634                         MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, &val);
8635         val &= ~(0xf << (lane << 2));
8636
8637         switch (edc_mode) {
8638         case EDC_MODE_LINEAR:
8639         case EDC_MODE_LIMITING:
8640                 mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_DEFAULT;
8641                 break;
8642         case EDC_MODE_PASSIVE_DAC:
8643         case EDC_MODE_ACTIVE_DAC:
8644                 mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_DAC;
8645                 break;
8646         default:
8647                 break;
8648         }
8649
8650         val |= (mode << (lane << 2));
8651         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
8652                          MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, val);
8653         /* A must read */
8654         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
8655                         MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, &val);
8656
8657         /* Restart microcode to re-read the new mode */
8658         bnx2x_warpcore_reset_lane(bp, phy, 1);
8659         bnx2x_warpcore_reset_lane(bp, phy, 0);
8660
8661 }
8662
8663 static void bnx2x_set_limiting_mode(struct link_params *params,
8664                                     struct bnx2x_phy *phy,
8665                                     u16 edc_mode)
8666 {
8667         switch (phy->type) {
8668         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
8669                 bnx2x_8726_set_limiting_mode(params->bp, phy, edc_mode);
8670                 break;
8671         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
8672         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
8673                 bnx2x_8727_set_limiting_mode(params->bp, phy, edc_mode);
8674                 break;
8675         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
8676                 bnx2x_warpcore_set_limiting_mode(params, phy, edc_mode);
8677                 break;
8678         }
8679 }
8680
8681 static int bnx2x_sfp_module_detection(struct bnx2x_phy *phy,
8682                                       struct link_params *params)
8683 {
8684         struct bnx2x *bp = params->bp;
8685         u16 edc_mode;
8686         int rc = 0;
8687
8688         u32 val = REG_RD(bp, params->shmem_base +
8689                              offsetof(struct shmem_region, dev_info.
8690                                      port_feature_config[params->port].config));
8691         /* Enabled transmitter by default */
8692         bnx2x_sfp_set_transmitter(params, phy, 1);
8693         DP(NETIF_MSG_LINK, "SFP+ module plugged in/out detected on port %d\n",
8694                  params->port);
8695         /* Power up module */
8696         bnx2x_power_sfp_module(params, phy, 1);
8697         if (bnx2x_get_edc_mode(phy, params, &edc_mode) != 0) {
8698                 DP(NETIF_MSG_LINK, "Failed to get valid module type\n");
8699                 return -EINVAL;
8700         } else if (bnx2x_verify_sfp_module(phy, params) != 0) {
8701                 /* Check SFP+ module compatibility */
8702                 DP(NETIF_MSG_LINK, "Module verification failed!!\n");
8703                 rc = -EINVAL;
8704                 /* Turn on fault module-detected led */
8705                 bnx2x_set_sfp_module_fault_led(params,
8706                                                MISC_REGISTERS_GPIO_HIGH);
8707
8708                 /* Check if need to power down the SFP+ module */
8709                 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
8710                      PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_POWER_DOWN) {
8711                         DP(NETIF_MSG_LINK, "Shutdown SFP+ module!!\n");
8712                         bnx2x_power_sfp_module(params, phy, 0);
8713                         return rc;
8714                 }
8715         } else {
8716                 /* Turn off fault module-detected led */
8717                 bnx2x_set_sfp_module_fault_led(params, MISC_REGISTERS_GPIO_LOW);
8718         }
8719
8720         /* Check and set limiting mode / LRM mode on 8726. On 8727 it
8721          * is done automatically
8722          */
8723         bnx2x_set_limiting_mode(params, phy, edc_mode);
8724
8725         /* Disable transmit for this module if the module is not approved, and
8726          * laser needs to be disabled.
8727          */
8728         if ((rc) &&
8729             ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
8730              PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER))
8731                 bnx2x_sfp_set_transmitter(params, phy, 0);
8732
8733         return rc;
8734 }
8735
8736 void bnx2x_handle_module_detect_int(struct link_params *params)
8737 {
8738         struct bnx2x *bp = params->bp;
8739         struct bnx2x_phy *phy;
8740         u32 gpio_val;
8741         u8 gpio_num, gpio_port;
8742         if (CHIP_IS_E3(bp)) {
8743                 phy = &params->phy[INT_PHY];
8744                 /* Always enable TX laser,will be disabled in case of fault */
8745                 bnx2x_sfp_set_transmitter(params, phy, 1);
8746         } else {
8747                 phy = &params->phy[EXT_PHY1];
8748         }
8749         if (bnx2x_get_mod_abs_int_cfg(bp, params->chip_id, params->shmem_base,
8750                                       params->port, &gpio_num, &gpio_port) ==
8751             -EINVAL) {
8752                 DP(NETIF_MSG_LINK, "Failed to get MOD_ABS interrupt config\n");
8753                 return;
8754         }
8755
8756         /* Set valid module led off */
8757         bnx2x_set_sfp_module_fault_led(params, MISC_REGISTERS_GPIO_HIGH);
8758
8759         /* Get current gpio val reflecting module plugged in / out*/
8760         gpio_val = bnx2x_get_gpio(bp, gpio_num, gpio_port);
8761
8762         /* Call the handling function in case module is detected */
8763         if (gpio_val == 0) {
8764                 bnx2x_set_mdio_emac_per_phy(bp, params);
8765                 bnx2x_set_aer_mmd(params, phy);
8766
8767                 bnx2x_power_sfp_module(params, phy, 1);
8768                 bnx2x_set_gpio_int(bp, gpio_num,
8769                                    MISC_REGISTERS_GPIO_INT_OUTPUT_CLR,
8770                                    gpio_port);
8771                 if (bnx2x_wait_for_sfp_module_initialized(phy, params) == 0) {
8772                         bnx2x_sfp_module_detection(phy, params);
8773                         if (CHIP_IS_E3(bp)) {
8774                                 u16 rx_tx_in_reset;
8775                                 /* In case WC is out of reset, reconfigure the
8776                                  * link speed while taking into account 1G
8777                                  * module limitation.
8778                                  */
8779                                 bnx2x_cl45_read(bp, phy,
8780                                                 MDIO_WC_DEVAD,
8781                                                 MDIO_WC_REG_DIGITAL5_MISC6,
8782                                                 &rx_tx_in_reset);
8783                                 if ((!rx_tx_in_reset) &&
8784                                     (params->link_flags &
8785                                      PHY_INITIALIZED)) {
8786                                         bnx2x_warpcore_reset_lane(bp, phy, 1);
8787                                         bnx2x_warpcore_config_sfi(phy, params);
8788                                         bnx2x_warpcore_reset_lane(bp, phy, 0);
8789                                 }
8790                         }
8791                 } else {
8792                         DP(NETIF_MSG_LINK, "SFP+ module is not initialized\n");
8793                 }
8794         } else {
8795                 bnx2x_set_gpio_int(bp, gpio_num,
8796                                    MISC_REGISTERS_GPIO_INT_OUTPUT_SET,
8797                                    gpio_port);
8798                 /* Module was plugged out.
8799                  * Disable transmit for this module
8800                  */
8801                 phy->media_type = ETH_PHY_NOT_PRESENT;
8802         }
8803 }
8804
8805 /******************************************************************/
8806 /*              Used by 8706 and 8727                             */
8807 /******************************************************************/
8808 static void bnx2x_sfp_mask_fault(struct bnx2x *bp,
8809                                  struct bnx2x_phy *phy,
8810                                  u16 alarm_status_offset,
8811                                  u16 alarm_ctrl_offset)
8812 {
8813         u16 alarm_status, val;
8814         bnx2x_cl45_read(bp, phy,
8815                         MDIO_PMA_DEVAD, alarm_status_offset,
8816                         &alarm_status);
8817         bnx2x_cl45_read(bp, phy,
8818                         MDIO_PMA_DEVAD, alarm_status_offset,
8819                         &alarm_status);
8820         /* Mask or enable the fault event. */
8821         bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, alarm_ctrl_offset, &val);
8822         if (alarm_status & (1<<0))
8823                 val &= ~(1<<0);
8824         else
8825                 val |= (1<<0);
8826         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, alarm_ctrl_offset, val);
8827 }
8828 /******************************************************************/
8829 /*              common BCM8706/BCM8726 PHY SECTION                */
8830 /******************************************************************/
8831 static u8 bnx2x_8706_8726_read_status(struct bnx2x_phy *phy,
8832                                       struct link_params *params,
8833                                       struct link_vars *vars)
8834 {
8835         u8 link_up = 0;
8836         u16 val1, val2, rx_sd, pcs_status;
8837         struct bnx2x *bp = params->bp;
8838         DP(NETIF_MSG_LINK, "XGXS 8706/8726\n");
8839         /* Clear RX Alarm*/
8840         bnx2x_cl45_read(bp, phy,
8841                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &val2);
8842
8843         bnx2x_sfp_mask_fault(bp, phy, MDIO_PMA_LASI_TXSTAT,
8844                              MDIO_PMA_LASI_TXCTRL);
8845
8846         /* Clear LASI indication*/
8847         bnx2x_cl45_read(bp, phy,
8848                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
8849         bnx2x_cl45_read(bp, phy,
8850                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val2);
8851         DP(NETIF_MSG_LINK, "8706/8726 LASI status 0x%x--> 0x%x\n", val1, val2);
8852
8853         bnx2x_cl45_read(bp, phy,
8854                         MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_SD, &rx_sd);
8855         bnx2x_cl45_read(bp, phy,
8856                         MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &pcs_status);
8857         bnx2x_cl45_read(bp, phy,
8858                         MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &val2);
8859         bnx2x_cl45_read(bp, phy,
8860                         MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &val2);
8861
8862         DP(NETIF_MSG_LINK, "8706/8726 rx_sd 0x%x pcs_status 0x%x 1Gbps"
8863                         " link_status 0x%x\n", rx_sd, pcs_status, val2);
8864         /* Link is up if both bit 0 of pmd_rx_sd and bit 0 of pcs_status
8865          * are set, or if the autoneg bit 1 is set
8866          */
8867         link_up = ((rx_sd & pcs_status & 0x1) || (val2 & (1<<1)));
8868         if (link_up) {
8869                 if (val2 & (1<<1))
8870                         vars->line_speed = SPEED_1000;
8871                 else
8872                         vars->line_speed = SPEED_10000;
8873                 bnx2x_ext_phy_resolve_fc(phy, params, vars);
8874                 vars->duplex = DUPLEX_FULL;
8875         }
8876
8877         /* Capture 10G link fault. Read twice to clear stale value. */
8878         if (vars->line_speed == SPEED_10000) {
8879                 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
8880                             MDIO_PMA_LASI_TXSTAT, &val1);
8881                 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
8882                             MDIO_PMA_LASI_TXSTAT, &val1);
8883                 if (val1 & (1<<0))
8884                         vars->fault_detected = 1;
8885         }
8886
8887         return link_up;
8888 }
8889
8890 /******************************************************************/
8891 /*                      BCM8706 PHY SECTION                       */
8892 /******************************************************************/
8893 static void bnx2x_8706_config_init(struct bnx2x_phy *phy,
8894                                    struct link_params *params,
8895                                    struct link_vars *vars)
8896 {
8897         u32 tx_en_mode;
8898         u16 cnt, val, tmp1;
8899         struct bnx2x *bp = params->bp;
8900
8901         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
8902                        MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
8903         /* HW reset */
8904         bnx2x_ext_phy_hw_reset(bp, params->port);
8905         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040);
8906         bnx2x_wait_reset_complete(bp, phy, params);
8907
8908         /* Wait until fw is loaded */
8909         for (cnt = 0; cnt < 100; cnt++) {
8910                 bnx2x_cl45_read(bp, phy,
8911                                 MDIO_PMA_DEVAD, MDIO_PMA_REG_ROM_VER1, &val);
8912                 if (val)
8913                         break;
8914                 usleep_range(10000, 20000);
8915         }
8916         DP(NETIF_MSG_LINK, "XGXS 8706 is initialized after %d ms\n", cnt);
8917         if ((params->feature_config_flags &
8918              FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
8919                 u8 i;
8920                 u16 reg;
8921                 for (i = 0; i < 4; i++) {
8922                         reg = MDIO_XS_8706_REG_BANK_RX0 +
8923                                 i*(MDIO_XS_8706_REG_BANK_RX1 -
8924                                    MDIO_XS_8706_REG_BANK_RX0);
8925                         bnx2x_cl45_read(bp, phy, MDIO_XS_DEVAD, reg, &val);
8926                         /* Clear first 3 bits of the control */
8927                         val &= ~0x7;
8928                         /* Set control bits according to configuration */
8929                         val |= (phy->rx_preemphasis[i] & 0x7);
8930                         DP(NETIF_MSG_LINK, "Setting RX Equalizer to BCM8706"
8931                                    " reg 0x%x <-- val 0x%x\n", reg, val);
8932                         bnx2x_cl45_write(bp, phy, MDIO_XS_DEVAD, reg, val);
8933                 }
8934         }
8935         /* Force speed */
8936         if (phy->req_line_speed == SPEED_10000) {
8937                 DP(NETIF_MSG_LINK, "XGXS 8706 force 10Gbps\n");
8938
8939                 bnx2x_cl45_write(bp, phy,
8940                                  MDIO_PMA_DEVAD,
8941                                  MDIO_PMA_REG_DIGITAL_CTRL, 0x400);
8942                 bnx2x_cl45_write(bp, phy,
8943                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_TXCTRL,
8944                                  0);
8945                 /* Arm LASI for link and Tx fault. */
8946                 bnx2x_cl45_write(bp, phy,
8947                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 3);
8948         } else {
8949                 /* Force 1Gbps using autoneg with 1G advertisement */
8950
8951                 /* Allow CL37 through CL73 */
8952                 DP(NETIF_MSG_LINK, "XGXS 8706 AutoNeg\n");
8953                 bnx2x_cl45_write(bp, phy,
8954                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_CL73, 0x040c);
8955
8956                 /* Enable Full-Duplex advertisement on CL37 */
8957                 bnx2x_cl45_write(bp, phy,
8958                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LP, 0x0020);
8959                 /* Enable CL37 AN */
8960                 bnx2x_cl45_write(bp, phy,
8961                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);
8962                 /* 1G support */
8963                 bnx2x_cl45_write(bp, phy,
8964                                  MDIO_AN_DEVAD, MDIO_AN_REG_ADV, (1<<5));
8965
8966                 /* Enable clause 73 AN */
8967                 bnx2x_cl45_write(bp, phy,
8968                                  MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);
8969                 bnx2x_cl45_write(bp, phy,
8970                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
8971                                  0x0400);
8972                 bnx2x_cl45_write(bp, phy,
8973                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL,
8974                                  0x0004);
8975         }
8976         bnx2x_save_bcm_spirom_ver(bp, phy, params->port);
8977
8978         /* If TX Laser is controlled by GPIO_0, do not let PHY go into low
8979          * power mode, if TX Laser is disabled
8980          */
8981
8982         tx_en_mode = REG_RD(bp, params->shmem_base +
8983                             offsetof(struct shmem_region,
8984                                 dev_info.port_hw_config[params->port].sfp_ctrl))
8985                         & PORT_HW_CFG_TX_LASER_MASK;
8986
8987         if (tx_en_mode == PORT_HW_CFG_TX_LASER_GPIO0) {
8988                 DP(NETIF_MSG_LINK, "Enabling TXONOFF_PWRDN_DIS\n");
8989                 bnx2x_cl45_read(bp, phy,
8990                         MDIO_PMA_DEVAD, MDIO_PMA_REG_DIGITAL_CTRL, &tmp1);
8991                 tmp1 |= 0x1;
8992                 bnx2x_cl45_write(bp, phy,
8993                         MDIO_PMA_DEVAD, MDIO_PMA_REG_DIGITAL_CTRL, tmp1);
8994         }
8995 }
8996
8997 static u8 bnx2x_8706_read_status(struct bnx2x_phy *phy,
8998                                  struct link_params *params,
8999                                  struct link_vars *vars)
9000 {
9001         return bnx2x_8706_8726_read_status(phy, params, vars);
9002 }
9003
9004 /******************************************************************/
9005 /*                      BCM8726 PHY SECTION                       */
9006 /******************************************************************/
9007 static void bnx2x_8726_config_loopback(struct bnx2x_phy *phy,
9008                                        struct link_params *params)
9009 {
9010         struct bnx2x *bp = params->bp;
9011         DP(NETIF_MSG_LINK, "PMA/PMD ext_phy_loopback: 8726\n");
9012         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x0001);
9013 }
9014
9015 static void bnx2x_8726_external_rom_boot(struct bnx2x_phy *phy,
9016                                          struct link_params *params)
9017 {
9018         struct bnx2x *bp = params->bp;
9019         /* Need to wait 100ms after reset */
9020         msleep(100);
9021
9022         /* Micro controller re-boot */
9023         bnx2x_cl45_write(bp, phy,
9024                          MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x018B);
9025
9026         /* Set soft reset */
9027         bnx2x_cl45_write(bp, phy,
9028                          MDIO_PMA_DEVAD,
9029                          MDIO_PMA_REG_GEN_CTRL,
9030                          MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET);
9031
9032         bnx2x_cl45_write(bp, phy,
9033                          MDIO_PMA_DEVAD,
9034                          MDIO_PMA_REG_MISC_CTRL1, 0x0001);
9035
9036         bnx2x_cl45_write(bp, phy,
9037                          MDIO_PMA_DEVAD,
9038                          MDIO_PMA_REG_GEN_CTRL,
9039                          MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP);
9040
9041         /* Wait for 150ms for microcode load */
9042         msleep(150);
9043
9044         /* Disable serial boot control, tristates pins SS_N, SCK, MOSI, MISO */
9045         bnx2x_cl45_write(bp, phy,
9046                          MDIO_PMA_DEVAD,
9047                          MDIO_PMA_REG_MISC_CTRL1, 0x0000);
9048
9049         msleep(200);
9050         bnx2x_save_bcm_spirom_ver(bp, phy, params->port);
9051 }
9052
9053 static u8 bnx2x_8726_read_status(struct bnx2x_phy *phy,
9054                                  struct link_params *params,
9055                                  struct link_vars *vars)
9056 {
9057         struct bnx2x *bp = params->bp;
9058         u16 val1;
9059         u8 link_up = bnx2x_8706_8726_read_status(phy, params, vars);
9060         if (link_up) {
9061                 bnx2x_cl45_read(bp, phy,
9062                                 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER,
9063                                 &val1);
9064                 if (val1 & (1<<15)) {
9065                         DP(NETIF_MSG_LINK, "Tx is disabled\n");
9066                         link_up = 0;
9067                         vars->line_speed = 0;
9068                 }
9069         }
9070         return link_up;
9071 }
9072
9073
9074 static void bnx2x_8726_config_init(struct bnx2x_phy *phy,
9075                                    struct link_params *params,
9076                                    struct link_vars *vars)
9077 {
9078         struct bnx2x *bp = params->bp;
9079         DP(NETIF_MSG_LINK, "Initializing BCM8726\n");
9080
9081         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15);
9082         bnx2x_wait_reset_complete(bp, phy, params);
9083
9084         bnx2x_8726_external_rom_boot(phy, params);
9085
9086         /* Need to call module detected on initialization since the module
9087          * detection triggered by actual module insertion might occur before
9088          * driver is loaded, and when driver is loaded, it reset all
9089          * registers, including the transmitter
9090          */
9091         bnx2x_sfp_module_detection(phy, params);
9092
9093         if (phy->req_line_speed == SPEED_1000) {
9094                 DP(NETIF_MSG_LINK, "Setting 1G force\n");
9095                 bnx2x_cl45_write(bp, phy,
9096                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x40);
9097                 bnx2x_cl45_write(bp, phy,
9098                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0xD);
9099                 bnx2x_cl45_write(bp, phy,
9100                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x5);
9101                 bnx2x_cl45_write(bp, phy,
9102                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
9103                                  0x400);
9104         } else if ((phy->req_line_speed == SPEED_AUTO_NEG) &&
9105                    (phy->speed_cap_mask &
9106                       PORT_HW_CFG_SPEED_CAPABILITY_D0_1G) &&
9107                    ((phy->speed_cap_mask &
9108                       PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) !=
9109                     PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
9110                 DP(NETIF_MSG_LINK, "Setting 1G clause37\n");
9111                 /* Set Flow control */
9112                 bnx2x_ext_phy_set_pause(params, phy, vars);
9113                 bnx2x_cl45_write(bp, phy,
9114                                  MDIO_AN_DEVAD, MDIO_AN_REG_ADV, 0x20);
9115                 bnx2x_cl45_write(bp, phy,
9116                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_CL73, 0x040c);
9117                 bnx2x_cl45_write(bp, phy,
9118                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, 0x0020);
9119                 bnx2x_cl45_write(bp, phy,
9120                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);
9121                 bnx2x_cl45_write(bp, phy,
9122                                 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);
9123                 /* Enable RX-ALARM control to receive interrupt for 1G speed
9124                  * change
9125                  */
9126                 bnx2x_cl45_write(bp, phy,
9127                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x4);
9128                 bnx2x_cl45_write(bp, phy,
9129                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
9130                                  0x400);
9131
9132         } else { /* Default 10G. Set only LASI control */
9133                 bnx2x_cl45_write(bp, phy,
9134                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 1);
9135         }
9136
9137         /* Set TX PreEmphasis if needed */
9138         if ((params->feature_config_flags &
9139              FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
9140                 DP(NETIF_MSG_LINK,
9141                    "Setting TX_CTRL1 0x%x, TX_CTRL2 0x%x\n",
9142                          phy->tx_preemphasis[0],
9143                          phy->tx_preemphasis[1]);
9144                 bnx2x_cl45_write(bp, phy,
9145                                  MDIO_PMA_DEVAD,
9146                                  MDIO_PMA_REG_8726_TX_CTRL1,
9147                                  phy->tx_preemphasis[0]);
9148
9149                 bnx2x_cl45_write(bp, phy,
9150                                  MDIO_PMA_DEVAD,
9151                                  MDIO_PMA_REG_8726_TX_CTRL2,
9152                                  phy->tx_preemphasis[1]);
9153         }
9154 }
9155
9156 static void bnx2x_8726_link_reset(struct bnx2x_phy *phy,
9157                                   struct link_params *params)
9158 {
9159         struct bnx2x *bp = params->bp;
9160         DP(NETIF_MSG_LINK, "bnx2x_8726_link_reset port %d\n", params->port);
9161         /* Set serial boot control for external load */
9162         bnx2x_cl45_write(bp, phy,
9163                          MDIO_PMA_DEVAD,
9164                          MDIO_PMA_REG_GEN_CTRL, 0x0001);
9165 }
9166
9167 /******************************************************************/
9168 /*                      BCM8727 PHY SECTION                       */
9169 /******************************************************************/
9170
9171 static void bnx2x_8727_set_link_led(struct bnx2x_phy *phy,
9172                                     struct link_params *params, u8 mode)
9173 {
9174         struct bnx2x *bp = params->bp;
9175         u16 led_mode_bitmask = 0;
9176         u16 gpio_pins_bitmask = 0;
9177         u16 val;
9178         /* Only NOC flavor requires to set the LED specifically */
9179         if (!(phy->flags & FLAGS_NOC))
9180                 return;
9181         switch (mode) {
9182         case LED_MODE_FRONT_PANEL_OFF:
9183         case LED_MODE_OFF:
9184                 led_mode_bitmask = 0;
9185                 gpio_pins_bitmask = 0x03;
9186                 break;
9187         case LED_MODE_ON:
9188                 led_mode_bitmask = 0;
9189                 gpio_pins_bitmask = 0x02;
9190                 break;
9191         case LED_MODE_OPER:
9192                 led_mode_bitmask = 0x60;
9193                 gpio_pins_bitmask = 0x11;
9194                 break;
9195         }
9196         bnx2x_cl45_read(bp, phy,
9197                         MDIO_PMA_DEVAD,
9198                         MDIO_PMA_REG_8727_PCS_OPT_CTRL,
9199                         &val);
9200         val &= 0xff8f;
9201         val |= led_mode_bitmask;
9202         bnx2x_cl45_write(bp, phy,
9203                          MDIO_PMA_DEVAD,
9204                          MDIO_PMA_REG_8727_PCS_OPT_CTRL,
9205                          val);
9206         bnx2x_cl45_read(bp, phy,
9207                         MDIO_PMA_DEVAD,
9208                         MDIO_PMA_REG_8727_GPIO_CTRL,
9209                         &val);
9210         val &= 0xffe0;
9211         val |= gpio_pins_bitmask;
9212         bnx2x_cl45_write(bp, phy,
9213                          MDIO_PMA_DEVAD,
9214                          MDIO_PMA_REG_8727_GPIO_CTRL,
9215                          val);
9216 }
9217 static void bnx2x_8727_hw_reset(struct bnx2x_phy *phy,
9218                                 struct link_params *params) {
9219         u32 swap_val, swap_override;
9220         u8 port;
9221         /* The PHY reset is controlled by GPIO 1. Fake the port number
9222          * to cancel the swap done in set_gpio()
9223          */
9224         struct bnx2x *bp = params->bp;
9225         swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
9226         swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
9227         port = (swap_val && swap_override) ^ 1;
9228         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
9229                        MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
9230 }
9231
9232 static void bnx2x_8727_config_speed(struct bnx2x_phy *phy,
9233                                     struct link_params *params)
9234 {
9235         struct bnx2x *bp = params->bp;
9236         u16 tmp1, val;
9237         /* Set option 1G speed */
9238         if ((phy->req_line_speed == SPEED_1000) ||
9239             (phy->media_type == ETH_PHY_SFP_1G_FIBER)) {
9240                 DP(NETIF_MSG_LINK, "Setting 1G force\n");
9241                 bnx2x_cl45_write(bp, phy,
9242                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x40);
9243                 bnx2x_cl45_write(bp, phy,
9244                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0xD);
9245                 bnx2x_cl45_read(bp, phy,
9246                                 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, &tmp1);
9247                 DP(NETIF_MSG_LINK, "1.7 = 0x%x\n", tmp1);
9248                 /* Power down the XAUI until link is up in case of dual-media
9249                  * and 1G
9250                  */
9251                 if (DUAL_MEDIA(params)) {
9252                         bnx2x_cl45_read(bp, phy,
9253                                         MDIO_PMA_DEVAD,
9254                                         MDIO_PMA_REG_8727_PCS_GP, &val);
9255                         val |= (3<<10);
9256                         bnx2x_cl45_write(bp, phy,
9257                                          MDIO_PMA_DEVAD,
9258                                          MDIO_PMA_REG_8727_PCS_GP, val);
9259                 }
9260         } else if ((phy->req_line_speed == SPEED_AUTO_NEG) &&
9261                    ((phy->speed_cap_mask &
9262                      PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) &&
9263                    ((phy->speed_cap_mask &
9264                       PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) !=
9265                    PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
9266
9267                 DP(NETIF_MSG_LINK, "Setting 1G clause37\n");
9268                 bnx2x_cl45_write(bp, phy,
9269                                  MDIO_AN_DEVAD, MDIO_AN_REG_8727_MISC_CTRL, 0);
9270                 bnx2x_cl45_write(bp, phy,
9271                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1300);
9272         } else {
9273                 /* Since the 8727 has only single reset pin, need to set the 10G
9274                  * registers although it is default
9275                  */
9276                 bnx2x_cl45_write(bp, phy,
9277                                  MDIO_AN_DEVAD, MDIO_AN_REG_8727_MISC_CTRL,
9278                                  0x0020);
9279                 bnx2x_cl45_write(bp, phy,
9280                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x0100);
9281                 bnx2x_cl45_write(bp, phy,
9282                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x2040);
9283                 bnx2x_cl45_write(bp, phy,
9284                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2,
9285                                  0x0008);
9286         }
9287 }
9288
9289 static void bnx2x_8727_config_init(struct bnx2x_phy *phy,
9290                                    struct link_params *params,
9291                                    struct link_vars *vars)
9292 {
9293         u32 tx_en_mode;
9294         u16 tmp1, mod_abs, tmp2;
9295         struct bnx2x *bp = params->bp;
9296         /* Enable PMD link, MOD_ABS_FLT, and 1G link alarm */
9297
9298         bnx2x_wait_reset_complete(bp, phy, params);
9299
9300         DP(NETIF_MSG_LINK, "Initializing BCM8727\n");
9301
9302         bnx2x_8727_specific_func(phy, params, PHY_INIT);
9303         /* Initially configure MOD_ABS to interrupt when module is
9304          * presence( bit 8)
9305          */
9306         bnx2x_cl45_read(bp, phy,
9307                         MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, &mod_abs);
9308         /* Set EDC off by setting OPTXLOS signal input to low (bit 9).
9309          * When the EDC is off it locks onto a reference clock and avoids
9310          * becoming 'lost'
9311          */
9312         mod_abs &= ~(1<<8);
9313         if (!(phy->flags & FLAGS_NOC))
9314                 mod_abs &= ~(1<<9);
9315         bnx2x_cl45_write(bp, phy,
9316                          MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
9317
9318         /* Enable/Disable PHY transmitter output */
9319         bnx2x_set_disable_pmd_transmit(params, phy, 0);
9320
9321         bnx2x_8727_power_module(bp, phy, 1);
9322
9323         bnx2x_cl45_read(bp, phy,
9324                         MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &tmp1);
9325
9326         bnx2x_cl45_read(bp, phy,
9327                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &tmp1);
9328
9329         bnx2x_8727_config_speed(phy, params);
9330
9331
9332         /* Set TX PreEmphasis if needed */
9333         if ((params->feature_config_flags &
9334              FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
9335                 DP(NETIF_MSG_LINK, "Setting TX_CTRL1 0x%x, TX_CTRL2 0x%x\n",
9336                            phy->tx_preemphasis[0],
9337                            phy->tx_preemphasis[1]);
9338                 bnx2x_cl45_write(bp, phy,
9339                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TX_CTRL1,
9340                                  phy->tx_preemphasis[0]);
9341
9342                 bnx2x_cl45_write(bp, phy,
9343                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TX_CTRL2,
9344                                  phy->tx_preemphasis[1]);
9345         }
9346
9347         /* If TX Laser is controlled by GPIO_0, do not let PHY go into low
9348          * power mode, if TX Laser is disabled
9349          */
9350         tx_en_mode = REG_RD(bp, params->shmem_base +
9351                             offsetof(struct shmem_region,
9352                                 dev_info.port_hw_config[params->port].sfp_ctrl))
9353                         & PORT_HW_CFG_TX_LASER_MASK;
9354
9355         if (tx_en_mode == PORT_HW_CFG_TX_LASER_GPIO0) {
9356
9357                 DP(NETIF_MSG_LINK, "Enabling TXONOFF_PWRDN_DIS\n");
9358                 bnx2x_cl45_read(bp, phy,
9359                         MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_OPT_CFG_REG, &tmp2);
9360                 tmp2 |= 0x1000;
9361                 tmp2 &= 0xFFEF;
9362                 bnx2x_cl45_write(bp, phy,
9363                         MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_OPT_CFG_REG, tmp2);
9364                 bnx2x_cl45_read(bp, phy,
9365                                 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER,
9366                                 &tmp2);
9367                 bnx2x_cl45_write(bp, phy,
9368                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER,
9369                                  (tmp2 & 0x7fff));
9370         }
9371 }
9372
9373 static void bnx2x_8727_handle_mod_abs(struct bnx2x_phy *phy,
9374                                       struct link_params *params)
9375 {
9376         struct bnx2x *bp = params->bp;
9377         u16 mod_abs, rx_alarm_status;
9378         u32 val = REG_RD(bp, params->shmem_base +
9379                              offsetof(struct shmem_region, dev_info.
9380                                       port_feature_config[params->port].
9381                                       config));
9382         bnx2x_cl45_read(bp, phy,
9383                         MDIO_PMA_DEVAD,
9384                         MDIO_PMA_REG_PHY_IDENTIFIER, &mod_abs);
9385         if (mod_abs & (1<<8)) {
9386
9387                 /* Module is absent */
9388                 DP(NETIF_MSG_LINK,
9389                    "MOD_ABS indication show module is absent\n");
9390                 phy->media_type = ETH_PHY_NOT_PRESENT;
9391                 /* 1. Set mod_abs to detect next module
9392                  *    presence event
9393                  * 2. Set EDC off by setting OPTXLOS signal input to low
9394                  *    (bit 9).
9395                  *    When the EDC is off it locks onto a reference clock and
9396                  *    avoids becoming 'lost'.
9397                  */
9398                 mod_abs &= ~(1<<8);
9399                 if (!(phy->flags & FLAGS_NOC))
9400                         mod_abs &= ~(1<<9);
9401                 bnx2x_cl45_write(bp, phy,
9402                                  MDIO_PMA_DEVAD,
9403                                  MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
9404
9405                 /* Clear RX alarm since it stays up as long as
9406                  * the mod_abs wasn't changed
9407                  */
9408                 bnx2x_cl45_read(bp, phy,
9409                                 MDIO_PMA_DEVAD,
9410                                 MDIO_PMA_LASI_RXSTAT, &rx_alarm_status);
9411
9412         } else {
9413                 /* Module is present */
9414                 DP(NETIF_MSG_LINK,
9415                    "MOD_ABS indication show module is present\n");
9416                 /* First disable transmitter, and if the module is ok, the
9417                  * module_detection will enable it
9418                  * 1. Set mod_abs to detect next module absent event ( bit 8)
9419                  * 2. Restore the default polarity of the OPRXLOS signal and
9420                  * this signal will then correctly indicate the presence or
9421                  * absence of the Rx signal. (bit 9)
9422                  */
9423                 mod_abs |= (1<<8);
9424                 if (!(phy->flags & FLAGS_NOC))
9425                         mod_abs |= (1<<9);
9426                 bnx2x_cl45_write(bp, phy,
9427                                  MDIO_PMA_DEVAD,
9428                                  MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
9429
9430                 /* Clear RX alarm since it stays up as long as the mod_abs
9431                  * wasn't changed. This is need to be done before calling the
9432                  * module detection, otherwise it will clear* the link update
9433                  * alarm
9434                  */
9435                 bnx2x_cl45_read(bp, phy,
9436                                 MDIO_PMA_DEVAD,
9437                                 MDIO_PMA_LASI_RXSTAT, &rx_alarm_status);
9438
9439
9440                 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
9441                     PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER)
9442                         bnx2x_sfp_set_transmitter(params, phy, 0);
9443
9444                 if (bnx2x_wait_for_sfp_module_initialized(phy, params) == 0)
9445                         bnx2x_sfp_module_detection(phy, params);
9446                 else
9447                         DP(NETIF_MSG_LINK, "SFP+ module is not initialized\n");
9448
9449                 /* Reconfigure link speed based on module type limitations */
9450                 bnx2x_8727_config_speed(phy, params);
9451         }
9452
9453         DP(NETIF_MSG_LINK, "8727 RX_ALARM_STATUS 0x%x\n",
9454                    rx_alarm_status);
9455         /* No need to check link status in case of module plugged in/out */
9456 }
9457
9458 static u8 bnx2x_8727_read_status(struct bnx2x_phy *phy,
9459                                  struct link_params *params,
9460                                  struct link_vars *vars)
9461
9462 {
9463         struct bnx2x *bp = params->bp;
9464         u8 link_up = 0, oc_port = params->port;
9465         u16 link_status = 0;
9466         u16 rx_alarm_status, lasi_ctrl, val1;
9467
9468         /* If PHY is not initialized, do not check link status */
9469         bnx2x_cl45_read(bp, phy,
9470                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL,
9471                         &lasi_ctrl);
9472         if (!lasi_ctrl)
9473                 return 0;
9474
9475         /* Check the LASI on Rx */
9476         bnx2x_cl45_read(bp, phy,
9477                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT,
9478                         &rx_alarm_status);
9479         vars->line_speed = 0;
9480         DP(NETIF_MSG_LINK, "8727 RX_ALARM_STATUS  0x%x\n", rx_alarm_status);
9481
9482         bnx2x_sfp_mask_fault(bp, phy, MDIO_PMA_LASI_TXSTAT,
9483                              MDIO_PMA_LASI_TXCTRL);
9484
9485         bnx2x_cl45_read(bp, phy,
9486                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
9487
9488         DP(NETIF_MSG_LINK, "8727 LASI status 0x%x\n", val1);
9489
9490         /* Clear MSG-OUT */
9491         bnx2x_cl45_read(bp, phy,
9492                         MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &val1);
9493
9494         /* If a module is present and there is need to check
9495          * for over current
9496          */
9497         if (!(phy->flags & FLAGS_NOC) && !(rx_alarm_status & (1<<5))) {
9498                 /* Check over-current using 8727 GPIO0 input*/
9499                 bnx2x_cl45_read(bp, phy,
9500                                 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_GPIO_CTRL,
9501                                 &val1);
9502
9503                 if ((val1 & (1<<8)) == 0) {
9504                         if (!CHIP_IS_E1x(bp))
9505                                 oc_port = BP_PATH(bp) + (params->port << 1);
9506                         DP(NETIF_MSG_LINK,
9507                            "8727 Power fault has been detected on port %d\n",
9508                            oc_port);
9509                         netdev_err(bp->dev, "Error: Power fault on Port %d has "
9510                                             "been detected and the power to "
9511                                             "that SFP+ module has been removed "
9512                                             "to prevent failure of the card. "
9513                                             "Please remove the SFP+ module and "
9514                                             "restart the system to clear this "
9515                                             "error.\n",
9516                          oc_port);
9517                         /* Disable all RX_ALARMs except for mod_abs */
9518                         bnx2x_cl45_write(bp, phy,
9519                                          MDIO_PMA_DEVAD,
9520                                          MDIO_PMA_LASI_RXCTRL, (1<<5));
9521
9522                         bnx2x_cl45_read(bp, phy,
9523                                         MDIO_PMA_DEVAD,
9524                                         MDIO_PMA_REG_PHY_IDENTIFIER, &val1);
9525                         /* Wait for module_absent_event */
9526                         val1 |= (1<<8);
9527                         bnx2x_cl45_write(bp, phy,
9528                                          MDIO_PMA_DEVAD,
9529                                          MDIO_PMA_REG_PHY_IDENTIFIER, val1);
9530                         /* Clear RX alarm */
9531                         bnx2x_cl45_read(bp, phy,
9532                                 MDIO_PMA_DEVAD,
9533                                 MDIO_PMA_LASI_RXSTAT, &rx_alarm_status);
9534                         bnx2x_8727_power_module(params->bp, phy, 0);
9535                         return 0;
9536                 }
9537         } /* Over current check */
9538
9539         /* When module absent bit is set, check module */
9540         if (rx_alarm_status & (1<<5)) {
9541                 bnx2x_8727_handle_mod_abs(phy, params);
9542                 /* Enable all mod_abs and link detection bits */
9543                 bnx2x_cl45_write(bp, phy,
9544                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
9545                                  ((1<<5) | (1<<2)));
9546         }
9547
9548         if (!(phy->flags & FLAGS_SFP_NOT_APPROVED)) {
9549                 DP(NETIF_MSG_LINK, "Enabling 8727 TX laser\n");
9550                 bnx2x_sfp_set_transmitter(params, phy, 1);
9551         } else {
9552                 DP(NETIF_MSG_LINK, "Tx is disabled\n");
9553                 return 0;
9554         }
9555
9556         bnx2x_cl45_read(bp, phy,
9557                         MDIO_PMA_DEVAD,
9558                         MDIO_PMA_REG_8073_SPEED_LINK_STATUS, &link_status);
9559
9560         /* Bits 0..2 --> speed detected,
9561          * Bits 13..15--> link is down
9562          */
9563         if ((link_status & (1<<2)) && (!(link_status & (1<<15)))) {
9564                 link_up = 1;
9565                 vars->line_speed = SPEED_10000;
9566                 DP(NETIF_MSG_LINK, "port %x: External link up in 10G\n",
9567                            params->port);
9568         } else if ((link_status & (1<<0)) && (!(link_status & (1<<13)))) {
9569                 link_up = 1;
9570                 vars->line_speed = SPEED_1000;
9571                 DP(NETIF_MSG_LINK, "port %x: External link up in 1G\n",
9572                            params->port);
9573         } else {
9574                 link_up = 0;
9575                 DP(NETIF_MSG_LINK, "port %x: External link is down\n",
9576                            params->port);
9577         }
9578
9579         /* Capture 10G link fault. */
9580         if (vars->line_speed == SPEED_10000) {
9581                 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
9582                             MDIO_PMA_LASI_TXSTAT, &val1);
9583
9584                 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
9585                             MDIO_PMA_LASI_TXSTAT, &val1);
9586
9587                 if (val1 & (1<<0)) {
9588                         vars->fault_detected = 1;
9589                 }
9590         }
9591
9592         if (link_up) {
9593                 bnx2x_ext_phy_resolve_fc(phy, params, vars);
9594                 vars->duplex = DUPLEX_FULL;
9595                 DP(NETIF_MSG_LINK, "duplex = 0x%x\n", vars->duplex);
9596         }
9597
9598         if ((DUAL_MEDIA(params)) &&
9599             (phy->req_line_speed == SPEED_1000)) {
9600                 bnx2x_cl45_read(bp, phy,
9601                                 MDIO_PMA_DEVAD,
9602                                 MDIO_PMA_REG_8727_PCS_GP, &val1);
9603                 /* In case of dual-media board and 1G, power up the XAUI side,
9604                  * otherwise power it down. For 10G it is done automatically
9605                  */
9606                 if (link_up)
9607                         val1 &= ~(3<<10);
9608                 else
9609                         val1 |= (3<<10);
9610                 bnx2x_cl45_write(bp, phy,
9611                                  MDIO_PMA_DEVAD,
9612                                  MDIO_PMA_REG_8727_PCS_GP, val1);
9613         }
9614         return link_up;
9615 }
9616
9617 static void bnx2x_8727_link_reset(struct bnx2x_phy *phy,
9618                                   struct link_params *params)
9619 {
9620         struct bnx2x *bp = params->bp;
9621
9622         /* Enable/Disable PHY transmitter output */
9623         bnx2x_set_disable_pmd_transmit(params, phy, 1);
9624
9625         /* Disable Transmitter */
9626         bnx2x_sfp_set_transmitter(params, phy, 0);
9627         /* Clear LASI */
9628         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0);
9629
9630 }
9631
9632 /******************************************************************/
9633 /*              BCM8481/BCM84823/BCM84833 PHY SECTION             */
9634 /******************************************************************/
9635 static int bnx2x_is_8483x_8485x(struct bnx2x_phy *phy)
9636 {
9637         return ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) ||
9638                 (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834) ||
9639                 (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84858));
9640 }
9641
9642 static void bnx2x_save_848xx_spirom_version(struct bnx2x_phy *phy,
9643                                             struct bnx2x *bp,
9644                                             u8 port)
9645 {
9646         u16 val, fw_ver2, cnt, i;
9647         static struct bnx2x_reg_set reg_set[] = {
9648                 {MDIO_PMA_DEVAD, 0xA819, 0x0014},
9649                 {MDIO_PMA_DEVAD, 0xA81A, 0xc200},
9650                 {MDIO_PMA_DEVAD, 0xA81B, 0x0000},
9651                 {MDIO_PMA_DEVAD, 0xA81C, 0x0300},
9652                 {MDIO_PMA_DEVAD, 0xA817, 0x0009}
9653         };
9654         u16 fw_ver1;
9655
9656         if (bnx2x_is_8483x_8485x(phy)) {
9657                 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD, 0x400f, &fw_ver1);
9658                 if (phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84858)
9659                         fw_ver1 &= 0xfff;
9660                 bnx2x_save_spirom_version(bp, port, fw_ver1, phy->ver_addr);
9661         } else {
9662                 /* For 32-bit registers in 848xx, access via MDIO2ARM i/f. */
9663                 /* (1) set reg 0xc200_0014(SPI_BRIDGE_CTRL_2) to 0x03000000 */
9664                 for (i = 0; i < ARRAY_SIZE(reg_set); i++)
9665                         bnx2x_cl45_write(bp, phy, reg_set[i].devad,
9666                                          reg_set[i].reg, reg_set[i].val);
9667
9668                 for (cnt = 0; cnt < 100; cnt++) {
9669                         bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA818, &val);
9670                         if (val & 1)
9671                                 break;
9672                         udelay(5);
9673                 }
9674                 if (cnt == 100) {
9675                         DP(NETIF_MSG_LINK, "Unable to read 848xx "
9676                                         "phy fw version(1)\n");
9677                         bnx2x_save_spirom_version(bp, port, 0,
9678                                                   phy->ver_addr);
9679                         return;
9680                 }
9681
9682
9683                 /* 2) read register 0xc200_0000 (SPI_FW_STATUS) */
9684                 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA819, 0x0000);
9685                 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81A, 0xc200);
9686                 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA817, 0x000A);
9687                 for (cnt = 0; cnt < 100; cnt++) {
9688                         bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA818, &val);
9689                         if (val & 1)
9690                                 break;
9691                         udelay(5);
9692                 }
9693                 if (cnt == 100) {
9694                         DP(NETIF_MSG_LINK, "Unable to read 848xx phy fw "
9695                                         "version(2)\n");
9696                         bnx2x_save_spirom_version(bp, port, 0,
9697                                                   phy->ver_addr);
9698                         return;
9699                 }
9700
9701                 /* lower 16 bits of the register SPI_FW_STATUS */
9702                 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA81B, &fw_ver1);
9703                 /* upper 16 bits of register SPI_FW_STATUS */
9704                 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA81C, &fw_ver2);
9705
9706                 bnx2x_save_spirom_version(bp, port, (fw_ver2<<16) | fw_ver1,
9707                                           phy->ver_addr);
9708         }
9709
9710 }
9711 static void bnx2x_848xx_set_led(struct bnx2x *bp,
9712                                 struct bnx2x_phy *phy)
9713 {
9714         u16 val, led3_blink_rate, offset, i;
9715         static struct bnx2x_reg_set reg_set[] = {
9716                 {MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LED1_MASK, 0x0080},
9717                 {MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LED2_MASK, 0x0018},
9718                 {MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LED3_MASK, 0x0006},
9719                 {MDIO_PMA_DEVAD, MDIO_PMA_REG_84823_CTL_SLOW_CLK_CNT_HIGH,
9720                         MDIO_PMA_REG_84823_BLINK_RATE_VAL_15P9HZ},
9721                 {MDIO_AN_DEVAD, 0xFFFB, 0xFFFD}
9722         };
9723
9724         if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84858) {
9725                 /* Set LED5 source */
9726                 bnx2x_cl45_write(bp, phy,
9727                                  MDIO_PMA_DEVAD,
9728                                  MDIO_PMA_REG_8481_LED5_MASK,
9729                                  0x90);
9730                 led3_blink_rate = 0x000f;
9731         } else {
9732                 led3_blink_rate = 0x0000;
9733         }
9734         /* Set LED3 BLINK */
9735         bnx2x_cl45_write(bp, phy,
9736                          MDIO_PMA_DEVAD,
9737                          MDIO_PMA_REG_8481_LED3_BLINK,
9738                          led3_blink_rate);
9739
9740         /* PHYC_CTL_LED_CTL */
9741         bnx2x_cl45_read(bp, phy,
9742                         MDIO_PMA_DEVAD,
9743                         MDIO_PMA_REG_8481_LINK_SIGNAL, &val);
9744         val &= 0xFE00;
9745         val |= 0x0092;
9746
9747         if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84858)
9748                 val |= 2 << 12; /* LED5 ON based on source */
9749
9750         bnx2x_cl45_write(bp, phy,
9751                          MDIO_PMA_DEVAD,
9752                          MDIO_PMA_REG_8481_LINK_SIGNAL, val);
9753
9754         for (i = 0; i < ARRAY_SIZE(reg_set); i++)
9755                 bnx2x_cl45_write(bp, phy, reg_set[i].devad, reg_set[i].reg,
9756                                  reg_set[i].val);
9757
9758         if (bnx2x_is_8483x_8485x(phy))
9759                 offset = MDIO_PMA_REG_84833_CTL_LED_CTL_1;
9760         else
9761                 offset = MDIO_PMA_REG_84823_CTL_LED_CTL_1;
9762
9763         if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84858)
9764                 val = MDIO_PMA_REG_84858_ALLOW_GPHY_ACT |
9765                       MDIO_PMA_REG_84823_LED3_STRETCH_EN;
9766         else
9767                 val = MDIO_PMA_REG_84823_LED3_STRETCH_EN;
9768
9769         /* stretch_en for LEDs */
9770         bnx2x_cl45_read_or_write(bp, phy,
9771                                  MDIO_PMA_DEVAD,
9772                                  offset,
9773                                  val);
9774 }
9775
9776 static void bnx2x_848xx_specific_func(struct bnx2x_phy *phy,
9777                                       struct link_params *params,
9778                                       u32 action)
9779 {
9780         struct bnx2x *bp = params->bp;
9781         switch (action) {
9782         case PHY_INIT:
9783                 if (bnx2x_is_8483x_8485x(phy)) {
9784                         /* Save spirom version */
9785                         bnx2x_save_848xx_spirom_version(phy, bp, params->port);
9786                 }
9787                 /* This phy uses the NIG latch mechanism since link indication
9788                  * arrives through its LED4 and not via its LASI signal, so we
9789                  * get steady signal instead of clear on read
9790                  */
9791                 bnx2x_bits_en(bp, NIG_REG_LATCH_BC_0 + params->port*4,
9792                               1 << NIG_LATCH_BC_ENABLE_MI_INT);
9793
9794                 bnx2x_848xx_set_led(bp, phy);
9795                 break;
9796         }
9797 }
9798
9799 static int bnx2x_848xx_cmn_config_init(struct bnx2x_phy *phy,
9800                                        struct link_params *params,
9801                                        struct link_vars *vars)
9802 {
9803         struct bnx2x *bp = params->bp;
9804         u16 autoneg_val, an_1000_val, an_10_100_val;
9805
9806         bnx2x_848xx_specific_func(phy, params, PHY_INIT);
9807         bnx2x_cl45_write(bp, phy,
9808                          MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x0000);
9809
9810         /* set 1000 speed advertisement */
9811         bnx2x_cl45_read(bp, phy,
9812                         MDIO_AN_DEVAD, MDIO_AN_REG_8481_1000T_CTRL,
9813                         &an_1000_val);
9814
9815         bnx2x_ext_phy_set_pause(params, phy, vars);
9816         bnx2x_cl45_read(bp, phy,
9817                         MDIO_AN_DEVAD,
9818                         MDIO_AN_REG_8481_LEGACY_AN_ADV,
9819                         &an_10_100_val);
9820         bnx2x_cl45_read(bp, phy,
9821                         MDIO_AN_DEVAD, MDIO_AN_REG_8481_LEGACY_MII_CTRL,
9822                         &autoneg_val);
9823         /* Disable forced speed */
9824         autoneg_val &= ~((1<<6) | (1<<8) | (1<<9) | (1<<12) | (1<<13));
9825         an_10_100_val &= ~((1<<5) | (1<<6) | (1<<7) | (1<<8));
9826
9827         if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
9828              (phy->speed_cap_mask &
9829              PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
9830             (phy->req_line_speed == SPEED_1000)) {
9831                 an_1000_val |= (1<<8);
9832                 autoneg_val |= (1<<9 | 1<<12);
9833                 if (phy->req_duplex == DUPLEX_FULL)
9834                         an_1000_val |= (1<<9);
9835                 DP(NETIF_MSG_LINK, "Advertising 1G\n");
9836         } else
9837                 an_1000_val &= ~((1<<8) | (1<<9));
9838
9839         bnx2x_cl45_write(bp, phy,
9840                          MDIO_AN_DEVAD, MDIO_AN_REG_8481_1000T_CTRL,
9841                          an_1000_val);
9842
9843         /* Set 10/100 speed advertisement */
9844         if (phy->req_line_speed == SPEED_AUTO_NEG) {
9845                 if (phy->speed_cap_mask &
9846                     PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL) {
9847                         /* Enable autoneg and restart autoneg for legacy speeds
9848                          */
9849                         autoneg_val |= (1<<9 | 1<<12);
9850                         an_10_100_val |= (1<<8);
9851                         DP(NETIF_MSG_LINK, "Advertising 100M-FD\n");
9852                 }
9853
9854                 if (phy->speed_cap_mask &
9855                     PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF) {
9856                         /* Enable autoneg and restart autoneg for legacy speeds
9857                          */
9858                         autoneg_val |= (1<<9 | 1<<12);
9859                         an_10_100_val |= (1<<7);
9860                         DP(NETIF_MSG_LINK, "Advertising 100M-HD\n");
9861                 }
9862
9863                 if ((phy->speed_cap_mask &
9864                      PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL) &&
9865                     (phy->supported & SUPPORTED_10baseT_Full)) {
9866                         an_10_100_val |= (1<<6);
9867                         autoneg_val |= (1<<9 | 1<<12);
9868                         DP(NETIF_MSG_LINK, "Advertising 10M-FD\n");
9869                 }
9870
9871                 if ((phy->speed_cap_mask &
9872                      PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF) &&
9873                     (phy->supported & SUPPORTED_10baseT_Half)) {
9874                         an_10_100_val |= (1<<5);
9875                         autoneg_val |= (1<<9 | 1<<12);
9876                         DP(NETIF_MSG_LINK, "Advertising 10M-HD\n");
9877                 }
9878         }
9879
9880         /* Only 10/100 are allowed to work in FORCE mode */
9881         if ((phy->req_line_speed == SPEED_100) &&
9882             (phy->supported &
9883              (SUPPORTED_100baseT_Half |
9884               SUPPORTED_100baseT_Full))) {
9885                 autoneg_val |= (1<<13);
9886                 /* Enabled AUTO-MDIX when autoneg is disabled */
9887                 bnx2x_cl45_write(bp, phy,
9888                                  MDIO_AN_DEVAD, MDIO_AN_REG_8481_AUX_CTRL,
9889                                  (1<<15 | 1<<9 | 7<<0));
9890                 /* The PHY needs this set even for forced link. */
9891                 an_10_100_val |= (1<<8) | (1<<7);
9892                 DP(NETIF_MSG_LINK, "Setting 100M force\n");
9893         }
9894         if ((phy->req_line_speed == SPEED_10) &&
9895             (phy->supported &
9896              (SUPPORTED_10baseT_Half |
9897               SUPPORTED_10baseT_Full))) {
9898                 /* Enabled AUTO-MDIX when autoneg is disabled */
9899                 bnx2x_cl45_write(bp, phy,
9900                                  MDIO_AN_DEVAD, MDIO_AN_REG_8481_AUX_CTRL,
9901                                  (1<<15 | 1<<9 | 7<<0));
9902                 DP(NETIF_MSG_LINK, "Setting 10M force\n");
9903         }
9904
9905         bnx2x_cl45_write(bp, phy,
9906                          MDIO_AN_DEVAD, MDIO_AN_REG_8481_LEGACY_AN_ADV,
9907                          an_10_100_val);
9908
9909         if (phy->req_duplex == DUPLEX_FULL)
9910                 autoneg_val |= (1<<8);
9911
9912         /* Always write this if this is not 84833/4.
9913          * For 84833/4, write it only when it's a forced speed.
9914          */
9915         if (!bnx2x_is_8483x_8485x(phy) ||
9916             ((autoneg_val & (1<<12)) == 0))
9917                 bnx2x_cl45_write(bp, phy,
9918                          MDIO_AN_DEVAD,
9919                          MDIO_AN_REG_8481_LEGACY_MII_CTRL, autoneg_val);
9920
9921         if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
9922             (phy->speed_cap_mask &
9923              PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) ||
9924                 (phy->req_line_speed == SPEED_10000)) {
9925                         DP(NETIF_MSG_LINK, "Advertising 10G\n");
9926                         /* Restart autoneg for 10G*/
9927
9928                         bnx2x_cl45_read_or_write(
9929                                 bp, phy,
9930                                 MDIO_AN_DEVAD,
9931                                 MDIO_AN_REG_8481_10GBASE_T_AN_CTRL,
9932                                 0x1000);
9933                         bnx2x_cl45_write(bp, phy,
9934                                          MDIO_AN_DEVAD, MDIO_AN_REG_CTRL,
9935                                          0x3200);
9936         } else
9937                 bnx2x_cl45_write(bp, phy,
9938                                  MDIO_AN_DEVAD,
9939                                  MDIO_AN_REG_8481_10GBASE_T_AN_CTRL,
9940                                  1);
9941
9942         return 0;
9943 }
9944
9945 static void bnx2x_8481_config_init(struct bnx2x_phy *phy,
9946                                    struct link_params *params,
9947                                    struct link_vars *vars)
9948 {
9949         struct bnx2x *bp = params->bp;
9950         /* Restore normal power mode*/
9951         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
9952                        MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
9953
9954         /* HW reset */
9955         bnx2x_ext_phy_hw_reset(bp, params->port);
9956         bnx2x_wait_reset_complete(bp, phy, params);
9957
9958         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15);
9959         bnx2x_848xx_cmn_config_init(phy, params, vars);
9960 }
9961
9962 #define PHY848xx_CMDHDLR_WAIT 300
9963 #define PHY848xx_CMDHDLR_MAX_ARGS 5
9964
9965 static int bnx2x_84858_cmd_hdlr(struct bnx2x_phy *phy,
9966                                 struct link_params *params,
9967                                 u16 fw_cmd,
9968                                 u16 cmd_args[], int argc)
9969 {
9970         int idx;
9971         u16 val;
9972         struct bnx2x *bp = params->bp;
9973
9974         /* Step 1: Poll the STATUS register to see whether the previous command
9975          * is in progress or the system is busy (CMD_IN_PROGRESS or
9976          * SYSTEM_BUSY). If previous command is in progress or system is busy,
9977          * check again until the previous command finishes execution and the
9978          * system is available for taking command
9979          */
9980
9981         for (idx = 0; idx < PHY848xx_CMDHDLR_WAIT; idx++) {
9982                 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
9983                                 MDIO_848xx_CMD_HDLR_STATUS, &val);
9984                 if ((val != PHY84858_STATUS_CMD_IN_PROGRESS) &&
9985                     (val != PHY84858_STATUS_CMD_SYSTEM_BUSY))
9986                         break;
9987                 usleep_range(1000, 2000);
9988         }
9989         if (idx >= PHY848xx_CMDHDLR_WAIT) {
9990                 DP(NETIF_MSG_LINK, "FW cmd: FW not ready.\n");
9991                 return -EINVAL;
9992         }
9993
9994         /* Step2: If any parameters are required for the function, write them
9995          * to the required DATA registers
9996          */
9997
9998         for (idx = 0; idx < argc; idx++) {
9999                 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
10000                                  MDIO_848xx_CMD_HDLR_DATA1 + idx,
10001                                  cmd_args[idx]);
10002         }
10003
10004         /* Step3: When the firmware is ready for commands, write the 'Command
10005          * code' to the CMD register
10006          */
10007         bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
10008                          MDIO_848xx_CMD_HDLR_COMMAND, fw_cmd);
10009
10010         /* Step4: Once the command has been written, poll the STATUS register
10011          * to check whether the command has completed (CMD_COMPLETED_PASS/
10012          * CMD_FOR_CMDS or CMD_COMPLETED_ERROR).
10013          */
10014
10015         for (idx = 0; idx < PHY848xx_CMDHDLR_WAIT; idx++) {
10016                 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
10017                                 MDIO_848xx_CMD_HDLR_STATUS, &val);
10018                 if ((val == PHY84858_STATUS_CMD_COMPLETE_PASS) ||
10019                     (val == PHY84858_STATUS_CMD_COMPLETE_ERROR))
10020                         break;
10021                 usleep_range(1000, 2000);
10022         }
10023         if ((idx >= PHY848xx_CMDHDLR_WAIT) ||
10024             (val == PHY84858_STATUS_CMD_COMPLETE_ERROR)) {
10025                 DP(NETIF_MSG_LINK, "FW cmd failed.\n");
10026                 return -EINVAL;
10027         }
10028         /* Step5: Once the command has completed, read the specficied DATA
10029          * registers for any saved results for the command, if applicable
10030          */
10031
10032         /* Gather returning data */
10033         for (idx = 0; idx < argc; idx++) {
10034                 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
10035                                 MDIO_848xx_CMD_HDLR_DATA1 + idx,
10036                                 &cmd_args[idx]);
10037         }
10038
10039         return 0;
10040 }
10041
10042 static int bnx2x_84833_cmd_hdlr(struct bnx2x_phy *phy,
10043                                 struct link_params *params, u16 fw_cmd,
10044                                 u16 cmd_args[], int argc, int process)
10045 {
10046         int idx;
10047         u16 val;
10048         struct bnx2x *bp = params->bp;
10049         int rc = 0;
10050
10051         if (process == PHY84833_MB_PROCESS2) {
10052                 /* Write CMD_OPEN_OVERRIDE to STATUS reg */
10053                 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
10054                                  MDIO_848xx_CMD_HDLR_STATUS,
10055                                  PHY84833_STATUS_CMD_OPEN_OVERRIDE);
10056         }
10057
10058         for (idx = 0; idx < PHY848xx_CMDHDLR_WAIT; idx++) {
10059                 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
10060                                 MDIO_848xx_CMD_HDLR_STATUS, &val);
10061                 if (val == PHY84833_STATUS_CMD_OPEN_FOR_CMDS)
10062                         break;
10063                 usleep_range(1000, 2000);
10064         }
10065         if (idx >= PHY848xx_CMDHDLR_WAIT) {
10066                 DP(NETIF_MSG_LINK, "FW cmd: FW not ready.\n");
10067                 /* if the status is CMD_COMPLETE_PASS or CMD_COMPLETE_ERROR
10068                  * clear the status to CMD_CLEAR_COMPLETE
10069                  */
10070                 if (val == PHY84833_STATUS_CMD_COMPLETE_PASS ||
10071                     val == PHY84833_STATUS_CMD_COMPLETE_ERROR) {
10072                         bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
10073                                          MDIO_848xx_CMD_HDLR_STATUS,
10074                                          PHY84833_STATUS_CMD_CLEAR_COMPLETE);
10075                 }
10076                 return -EINVAL;
10077         }
10078         if (process == PHY84833_MB_PROCESS1 ||
10079             process == PHY84833_MB_PROCESS2) {
10080                 /* Prepare argument(s) */
10081                 for (idx = 0; idx < argc; idx++) {
10082                         bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
10083                                          MDIO_848xx_CMD_HDLR_DATA1 + idx,
10084                                          cmd_args[idx]);
10085                 }
10086         }
10087
10088         bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
10089                         MDIO_848xx_CMD_HDLR_COMMAND, fw_cmd);
10090         for (idx = 0; idx < PHY848xx_CMDHDLR_WAIT; idx++) {
10091                 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
10092                                 MDIO_848xx_CMD_HDLR_STATUS, &val);
10093                 if ((val == PHY84833_STATUS_CMD_COMPLETE_PASS) ||
10094                     (val == PHY84833_STATUS_CMD_COMPLETE_ERROR))
10095                         break;
10096                 usleep_range(1000, 2000);
10097         }
10098         if ((idx >= PHY848xx_CMDHDLR_WAIT) ||
10099             (val == PHY84833_STATUS_CMD_COMPLETE_ERROR)) {
10100                 DP(NETIF_MSG_LINK, "FW cmd failed.\n");
10101                 rc = -EINVAL;
10102         }
10103         if (process == PHY84833_MB_PROCESS3 && rc == 0) {
10104                 /* Gather returning data */
10105                 for (idx = 0; idx < argc; idx++) {
10106                         bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
10107                                         MDIO_848xx_CMD_HDLR_DATA1 + idx,
10108                                         &cmd_args[idx]);
10109                 }
10110         }
10111         if (val == PHY84833_STATUS_CMD_COMPLETE_ERROR ||
10112             val == PHY84833_STATUS_CMD_COMPLETE_PASS) {
10113                 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
10114                                  MDIO_848xx_CMD_HDLR_STATUS,
10115                                  PHY84833_STATUS_CMD_CLEAR_COMPLETE);
10116         }
10117         return rc;
10118 }
10119
10120 static int bnx2x_848xx_cmd_hdlr(struct bnx2x_phy *phy,
10121                                 struct link_params *params,
10122                                 u16 fw_cmd,
10123                                            u16 cmd_args[], int argc,
10124                                            int process)
10125 {
10126         struct bnx2x *bp = params->bp;
10127
10128         if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84858) ||
10129             (REG_RD(bp, params->shmem2_base +
10130                     offsetof(struct shmem2_region,
10131                              link_attr_sync[params->port])) &
10132              LINK_ATTR_84858)) {
10133                 return bnx2x_84858_cmd_hdlr(phy, params, fw_cmd, cmd_args,
10134                                             argc);
10135         } else {
10136                 return bnx2x_84833_cmd_hdlr(phy, params, fw_cmd, cmd_args,
10137                                             argc, process);
10138         }
10139 }
10140
10141 static int bnx2x_848xx_pair_swap_cfg(struct bnx2x_phy *phy,
10142                                      struct link_params *params,
10143                                      struct link_vars *vars)
10144 {
10145         u32 pair_swap;
10146         u16 data[PHY848xx_CMDHDLR_MAX_ARGS];
10147         int status;
10148         struct bnx2x *bp = params->bp;
10149
10150         /* Check for configuration. */
10151         pair_swap = REG_RD(bp, params->shmem_base +
10152                            offsetof(struct shmem_region,
10153                         dev_info.port_hw_config[params->port].xgbt_phy_cfg)) &
10154                 PORT_HW_CFG_RJ45_PAIR_SWAP_MASK;
10155
10156         if (pair_swap == 0)
10157                 return 0;
10158
10159         /* Only the second argument is used for this command */
10160         data[1] = (u16)pair_swap;
10161
10162         status = bnx2x_848xx_cmd_hdlr(phy, params,
10163                                       PHY848xx_CMD_SET_PAIR_SWAP, data,
10164                                       2, PHY84833_MB_PROCESS2);
10165         if (status == 0)
10166                 DP(NETIF_MSG_LINK, "Pairswap OK, val=0x%x\n", data[1]);
10167
10168         return status;
10169 }
10170
10171 static u8 bnx2x_84833_get_reset_gpios(struct bnx2x *bp,
10172                                       u32 shmem_base_path[],
10173                                       u32 chip_id)
10174 {
10175         u32 reset_pin[2];
10176         u32 idx;
10177         u8 reset_gpios;
10178         if (CHIP_IS_E3(bp)) {
10179                 /* Assume that these will be GPIOs, not EPIOs. */
10180                 for (idx = 0; idx < 2; idx++) {
10181                         /* Map config param to register bit. */
10182                         reset_pin[idx] = REG_RD(bp, shmem_base_path[idx] +
10183                                 offsetof(struct shmem_region,
10184                                 dev_info.port_hw_config[0].e3_cmn_pin_cfg));
10185                         reset_pin[idx] = (reset_pin[idx] &
10186                                 PORT_HW_CFG_E3_PHY_RESET_MASK) >>
10187                                 PORT_HW_CFG_E3_PHY_RESET_SHIFT;
10188                         reset_pin[idx] -= PIN_CFG_GPIO0_P0;
10189                         reset_pin[idx] = (1 << reset_pin[idx]);
10190                 }
10191                 reset_gpios = (u8)(reset_pin[0] | reset_pin[1]);
10192         } else {
10193                 /* E2, look from diff place of shmem. */
10194                 for (idx = 0; idx < 2; idx++) {
10195                         reset_pin[idx] = REG_RD(bp, shmem_base_path[idx] +
10196                                 offsetof(struct shmem_region,
10197                                 dev_info.port_hw_config[0].default_cfg));
10198                         reset_pin[idx] &= PORT_HW_CFG_EXT_PHY_GPIO_RST_MASK;
10199                         reset_pin[idx] -= PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0;
10200                         reset_pin[idx] >>= PORT_HW_CFG_EXT_PHY_GPIO_RST_SHIFT;
10201                         reset_pin[idx] = (1 << reset_pin[idx]);
10202                 }
10203                 reset_gpios = (u8)(reset_pin[0] | reset_pin[1]);
10204         }
10205
10206         return reset_gpios;
10207 }
10208
10209 static void bnx2x_84833_hw_reset_phy(struct bnx2x_phy *phy,
10210                                      struct link_params *params)
10211 {
10212         struct bnx2x *bp = params->bp;
10213         u8 reset_gpios;
10214         u32 other_shmem_base_addr = REG_RD(bp, params->shmem2_base +
10215                                 offsetof(struct shmem2_region,
10216                                 other_shmem_base_addr));
10217
10218         u32 shmem_base_path[2];
10219
10220         /* Work around for 84833 LED failure inside RESET status */
10221         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
10222                 MDIO_AN_REG_8481_LEGACY_MII_CTRL,
10223                 MDIO_AN_REG_8481_MII_CTRL_FORCE_1G);
10224         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
10225                 MDIO_AN_REG_8481_1G_100T_EXT_CTRL,
10226                 MIDO_AN_REG_8481_EXT_CTRL_FORCE_LEDS_OFF);
10227
10228         shmem_base_path[0] = params->shmem_base;
10229         shmem_base_path[1] = other_shmem_base_addr;
10230
10231         reset_gpios = bnx2x_84833_get_reset_gpios(bp, shmem_base_path,
10232                                                   params->chip_id);
10233
10234         bnx2x_set_mult_gpio(bp, reset_gpios, MISC_REGISTERS_GPIO_OUTPUT_LOW);
10235         udelay(10);
10236         DP(NETIF_MSG_LINK, "84833 hw reset on pin values 0x%x\n",
10237                 reset_gpios);
10238 }
10239
10240 static int bnx2x_8483x_disable_eee(struct bnx2x_phy *phy,
10241                                    struct link_params *params,
10242                                    struct link_vars *vars)
10243 {
10244         int rc;
10245         struct bnx2x *bp = params->bp;
10246         u16 cmd_args = 0;
10247
10248         DP(NETIF_MSG_LINK, "Don't Advertise 10GBase-T EEE\n");
10249
10250         /* Prevent Phy from working in EEE and advertising it */
10251         rc = bnx2x_848xx_cmd_hdlr(phy, params, PHY848xx_CMD_SET_EEE_MODE,
10252                                   &cmd_args, 1, PHY84833_MB_PROCESS1);
10253         if (rc) {
10254                 DP(NETIF_MSG_LINK, "EEE disable failed.\n");
10255                 return rc;
10256         }
10257
10258         return bnx2x_eee_disable(phy, params, vars);
10259 }
10260
10261 static int bnx2x_8483x_enable_eee(struct bnx2x_phy *phy,
10262                                    struct link_params *params,
10263                                    struct link_vars *vars)
10264 {
10265         int rc;
10266         struct bnx2x *bp = params->bp;
10267         u16 cmd_args = 1;
10268
10269         rc = bnx2x_848xx_cmd_hdlr(phy, params, PHY848xx_CMD_SET_EEE_MODE,
10270                                   &cmd_args, 1, PHY84833_MB_PROCESS1);
10271         if (rc) {
10272                 DP(NETIF_MSG_LINK, "EEE enable failed.\n");
10273                 return rc;
10274         }
10275
10276         return bnx2x_eee_advertise(phy, params, vars, SHMEM_EEE_10G_ADV);
10277 }
10278
10279 #define PHY84833_CONSTANT_LATENCY 1193
10280 static void bnx2x_848x3_config_init(struct bnx2x_phy *phy,
10281                                     struct link_params *params,
10282                                     struct link_vars *vars)
10283 {
10284         struct bnx2x *bp = params->bp;
10285         u8 port, initialize = 1;
10286         u16 val;
10287         u32 actual_phy_selection;
10288         u16 cmd_args[PHY848xx_CMDHDLR_MAX_ARGS];
10289         int rc = 0;
10290
10291         usleep_range(1000, 2000);
10292
10293         if (!(CHIP_IS_E1x(bp)))
10294                 port = BP_PATH(bp);
10295         else
10296                 port = params->port;
10297
10298         if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) {
10299                 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_3,
10300                                MISC_REGISTERS_GPIO_OUTPUT_HIGH,
10301                                port);
10302         } else {
10303                 /* MDIO reset */
10304                 bnx2x_cl45_write(bp, phy,
10305                                 MDIO_PMA_DEVAD,
10306                                 MDIO_PMA_REG_CTRL, 0x8000);
10307         }
10308
10309         bnx2x_wait_reset_complete(bp, phy, params);
10310
10311         /* Wait for GPHY to come out of reset */
10312         msleep(50);
10313         if (!bnx2x_is_8483x_8485x(phy)) {
10314                 /* BCM84823 requires that XGXS links up first @ 10G for normal
10315                  * behavior.
10316                  */
10317                 u16 temp;
10318                 temp = vars->line_speed;
10319                 vars->line_speed = SPEED_10000;
10320                 bnx2x_set_autoneg(&params->phy[INT_PHY], params, vars, 0);
10321                 bnx2x_program_serdes(&params->phy[INT_PHY], params, vars);
10322                 vars->line_speed = temp;
10323         }
10324         /* Check if this is actually BCM84858 */
10325         if (phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84858) {
10326                 u16 hw_rev;
10327
10328                 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
10329                                 MDIO_AN_REG_848xx_ID_MSB, &hw_rev);
10330                 if (hw_rev == BCM84858_PHY_ID) {
10331                         params->link_attr_sync |= LINK_ATTR_84858;
10332                         bnx2x_update_link_attr(params, params->link_attr_sync);
10333                 }
10334         }
10335
10336         /* Set dual-media configuration according to configuration */
10337         bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
10338                         MDIO_CTL_REG_84823_MEDIA, &val);
10339         val &= ~(MDIO_CTL_REG_84823_MEDIA_MAC_MASK |
10340                  MDIO_CTL_REG_84823_MEDIA_LINE_MASK |
10341                  MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN |
10342                  MDIO_CTL_REG_84823_MEDIA_PRIORITY_MASK |
10343                  MDIO_CTL_REG_84823_MEDIA_FIBER_1G);
10344
10345         if (CHIP_IS_E3(bp)) {
10346                 val &= ~(MDIO_CTL_REG_84823_MEDIA_MAC_MASK |
10347                          MDIO_CTL_REG_84823_MEDIA_LINE_MASK);
10348         } else {
10349                 val |= (MDIO_CTL_REG_84823_CTRL_MAC_XFI |
10350                         MDIO_CTL_REG_84823_MEDIA_LINE_XAUI_L);
10351         }
10352
10353         actual_phy_selection = bnx2x_phy_selection(params);
10354
10355         switch (actual_phy_selection) {
10356         case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT:
10357                 /* Do nothing. Essentially this is like the priority copper */
10358                 break;
10359         case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
10360                 val |= MDIO_CTL_REG_84823_MEDIA_PRIORITY_COPPER;
10361                 break;
10362         case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
10363                 val |= MDIO_CTL_REG_84823_MEDIA_PRIORITY_FIBER;
10364                 break;
10365         case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY:
10366                 /* Do nothing here. The first PHY won't be initialized at all */
10367                 break;
10368         case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY:
10369                 val |= MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN;
10370                 initialize = 0;
10371                 break;
10372         }
10373         if (params->phy[EXT_PHY2].req_line_speed == SPEED_1000)
10374                 val |= MDIO_CTL_REG_84823_MEDIA_FIBER_1G;
10375
10376         bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
10377                          MDIO_CTL_REG_84823_MEDIA, val);
10378         DP(NETIF_MSG_LINK, "Multi_phy config = 0x%x, Media control = 0x%x\n",
10379                    params->multi_phy_config, val);
10380
10381         if (bnx2x_is_8483x_8485x(phy)) {
10382                 bnx2x_848xx_pair_swap_cfg(phy, params, vars);
10383
10384                 /* Keep AutogrEEEn disabled. */
10385                 cmd_args[0] = 0x0;
10386                 cmd_args[1] = 0x0;
10387                 cmd_args[2] = PHY84833_CONSTANT_LATENCY + 1;
10388                 cmd_args[3] = PHY84833_CONSTANT_LATENCY;
10389                 rc = bnx2x_848xx_cmd_hdlr(phy, params,
10390                                           PHY848xx_CMD_SET_EEE_MODE, cmd_args,
10391                                           4, PHY84833_MB_PROCESS1);
10392                 if (rc)
10393                         DP(NETIF_MSG_LINK, "Cfg AutogrEEEn failed.\n");
10394         }
10395         if (initialize)
10396                 rc = bnx2x_848xx_cmn_config_init(phy, params, vars);
10397         else
10398                 bnx2x_save_848xx_spirom_version(phy, bp, params->port);
10399         /* 84833 PHY has a better feature and doesn't need to support this. */
10400         if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) {
10401                 u32 cms_enable = REG_RD(bp, params->shmem_base +
10402                         offsetof(struct shmem_region,
10403                         dev_info.port_hw_config[params->port].default_cfg)) &
10404                         PORT_HW_CFG_ENABLE_CMS_MASK;
10405
10406                 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
10407                                 MDIO_CTL_REG_84823_USER_CTRL_REG, &val);
10408                 if (cms_enable)
10409                         val |= MDIO_CTL_REG_84823_USER_CTRL_CMS;
10410                 else
10411                         val &= ~MDIO_CTL_REG_84823_USER_CTRL_CMS;
10412                 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
10413                                  MDIO_CTL_REG_84823_USER_CTRL_REG, val);
10414         }
10415
10416         bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
10417                         MDIO_84833_TOP_CFG_FW_REV, &val);
10418
10419         /* Configure EEE support */
10420         if ((val >= MDIO_84833_TOP_CFG_FW_EEE) &&
10421             (val != MDIO_84833_TOP_CFG_FW_NO_EEE) &&
10422             bnx2x_eee_has_cap(params)) {
10423                 rc = bnx2x_eee_initial_config(params, vars, SHMEM_EEE_10G_ADV);
10424                 if (rc) {
10425                         DP(NETIF_MSG_LINK, "Failed to configure EEE timers\n");
10426                         bnx2x_8483x_disable_eee(phy, params, vars);
10427                         return;
10428                 }
10429
10430                 if ((phy->req_duplex == DUPLEX_FULL) &&
10431                     (params->eee_mode & EEE_MODE_ADV_LPI) &&
10432                     (bnx2x_eee_calc_timer(params) ||
10433                      !(params->eee_mode & EEE_MODE_ENABLE_LPI)))
10434                         rc = bnx2x_8483x_enable_eee(phy, params, vars);
10435                 else
10436                         rc = bnx2x_8483x_disable_eee(phy, params, vars);
10437                 if (rc) {
10438                         DP(NETIF_MSG_LINK, "Failed to set EEE advertisement\n");
10439                         return;
10440                 }
10441         } else {
10442                 vars->eee_status &= ~SHMEM_EEE_SUPPORTED_MASK;
10443         }
10444
10445         if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) {
10446                 /* Additional settings for jumbo packets in 1000BASE-T mode */
10447                 /* Allow rx extended length */
10448                 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
10449                                 MDIO_AN_REG_8481_AUX_CTRL, &val);
10450                 val |= 0x4000;
10451                 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
10452                                  MDIO_AN_REG_8481_AUX_CTRL, val);
10453                 /* TX FIFO Elasticity LSB */
10454                 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
10455                                 MDIO_AN_REG_8481_1G_100T_EXT_CTRL, &val);
10456                 val |= 0x1;
10457                 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
10458                                  MDIO_AN_REG_8481_1G_100T_EXT_CTRL, val);
10459                 /* TX FIFO Elasticity MSB */
10460                 /* Enable expansion register 0x46 (Pattern Generator status) */
10461                 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
10462                                  MDIO_AN_REG_8481_EXPANSION_REG_ACCESS, 0xf46);
10463
10464                 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
10465                                 MDIO_AN_REG_8481_EXPANSION_REG_RD_RW, &val);
10466                 val |= 0x4000;
10467                 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
10468                                  MDIO_AN_REG_8481_EXPANSION_REG_RD_RW, val);
10469         }
10470
10471         if (bnx2x_is_8483x_8485x(phy)) {
10472                 /* Bring PHY out of super isolate mode as the final step. */
10473                 bnx2x_cl45_read_and_write(bp, phy,
10474                                           MDIO_CTL_DEVAD,
10475                                           MDIO_84833_TOP_CFG_XGPHY_STRAP1,
10476                                           (u16)~MDIO_84833_SUPER_ISOLATE);
10477         }
10478 }
10479
10480 static u8 bnx2x_848xx_read_status(struct bnx2x_phy *phy,
10481                                   struct link_params *params,
10482                                   struct link_vars *vars)
10483 {
10484         struct bnx2x *bp = params->bp;
10485         u16 val, val1, val2;
10486         u8 link_up = 0;
10487
10488
10489         /* Check 10G-BaseT link status */
10490         /* Check PMD signal ok */
10491         bnx2x_cl45_read(bp, phy,
10492                         MDIO_AN_DEVAD, 0xFFFA, &val1);
10493         bnx2x_cl45_read(bp, phy,
10494                         MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_PMD_SIGNAL,
10495                         &val2);
10496         DP(NETIF_MSG_LINK, "BCM848xx: PMD_SIGNAL 1.a811 = 0x%x\n", val2);
10497
10498         /* Check link 10G */
10499         if (val2 & (1<<11)) {
10500                 vars->line_speed = SPEED_10000;
10501                 vars->duplex = DUPLEX_FULL;
10502                 link_up = 1;
10503                 bnx2x_ext_phy_10G_an_resolve(bp, phy, vars);
10504         } else { /* Check Legacy speed link */
10505                 u16 legacy_status, legacy_speed;
10506
10507                 /* Enable expansion register 0x42 (Operation mode status) */
10508                 bnx2x_cl45_write(bp, phy,
10509                                  MDIO_AN_DEVAD,
10510                                  MDIO_AN_REG_8481_EXPANSION_REG_ACCESS, 0xf42);
10511
10512                 /* Get legacy speed operation status */
10513                 bnx2x_cl45_read(bp, phy,
10514                                 MDIO_AN_DEVAD,
10515                                 MDIO_AN_REG_8481_EXPANSION_REG_RD_RW,
10516                                 &legacy_status);
10517
10518                 DP(NETIF_MSG_LINK, "Legacy speed status = 0x%x\n",
10519                    legacy_status);
10520                 link_up = ((legacy_status & (1<<11)) == (1<<11));
10521                 legacy_speed = (legacy_status & (3<<9));
10522                 if (legacy_speed == (0<<9))
10523                         vars->line_speed = SPEED_10;
10524                 else if (legacy_speed == (1<<9))
10525                         vars->line_speed = SPEED_100;
10526                 else if (legacy_speed == (2<<9))
10527                         vars->line_speed = SPEED_1000;
10528                 else { /* Should not happen: Treat as link down */
10529                         vars->line_speed = 0;
10530                         link_up = 0;
10531                 }
10532
10533                 if (link_up) {
10534                         if (legacy_status & (1<<8))
10535                                 vars->duplex = DUPLEX_FULL;
10536                         else
10537                                 vars->duplex = DUPLEX_HALF;
10538
10539                         DP(NETIF_MSG_LINK,
10540                            "Link is up in %dMbps, is_duplex_full= %d\n",
10541                            vars->line_speed,
10542                            (vars->duplex == DUPLEX_FULL));
10543                         /* Check legacy speed AN resolution */
10544                         bnx2x_cl45_read(bp, phy,
10545                                         MDIO_AN_DEVAD,
10546                                         MDIO_AN_REG_8481_LEGACY_MII_STATUS,
10547                                         &val);
10548                         if (val & (1<<5))
10549                                 vars->link_status |=
10550                                         LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
10551                         bnx2x_cl45_read(bp, phy,
10552                                         MDIO_AN_DEVAD,
10553                                         MDIO_AN_REG_8481_LEGACY_AN_EXPANSION,
10554                                         &val);
10555                         if ((val & (1<<0)) == 0)
10556                                 vars->link_status |=
10557                                         LINK_STATUS_PARALLEL_DETECTION_USED;
10558                 }
10559         }
10560         if (link_up) {
10561                 DP(NETIF_MSG_LINK, "BCM848x3: link speed is %d\n",
10562                            vars->line_speed);
10563                 bnx2x_ext_phy_resolve_fc(phy, params, vars);
10564
10565                 /* Read LP advertised speeds */
10566                 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
10567                                 MDIO_AN_REG_CL37_FC_LP, &val);
10568                 if (val & (1<<5))
10569                         vars->link_status |=
10570                                 LINK_STATUS_LINK_PARTNER_10THD_CAPABLE;
10571                 if (val & (1<<6))
10572                         vars->link_status |=
10573                                 LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE;
10574                 if (val & (1<<7))
10575                         vars->link_status |=
10576                                 LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE;
10577                 if (val & (1<<8))
10578                         vars->link_status |=
10579                                 LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE;
10580                 if (val & (1<<9))
10581                         vars->link_status |=
10582                                 LINK_STATUS_LINK_PARTNER_100T4_CAPABLE;
10583
10584                 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
10585                                 MDIO_AN_REG_1000T_STATUS, &val);
10586
10587                 if (val & (1<<10))
10588                         vars->link_status |=
10589                                 LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE;
10590                 if (val & (1<<11))
10591                         vars->link_status |=
10592                                 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;
10593
10594                 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
10595                                 MDIO_AN_REG_MASTER_STATUS, &val);
10596
10597                 if (val & (1<<11))
10598                         vars->link_status |=
10599                                 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
10600
10601                 /* Determine if EEE was negotiated */
10602                 if (bnx2x_is_8483x_8485x(phy))
10603                         bnx2x_eee_an_resolve(phy, params, vars);
10604         }
10605
10606         return link_up;
10607 }
10608
10609 static int bnx2x_8485x_format_ver(u32 raw_ver, u8 *str, u16 *len)
10610 {
10611         u32 num;
10612
10613         num = ((raw_ver & 0xF80) >> 7) << 16 | ((raw_ver & 0x7F) << 8) |
10614               ((raw_ver & 0xF000) >> 12);
10615         return bnx2x_3_seq_format_ver(num, str, len);
10616 }
10617
10618 static int bnx2x_848xx_format_ver(u32 raw_ver, u8 *str, u16 *len)
10619 {
10620         u32 spirom_ver;
10621
10622         spirom_ver = ((raw_ver & 0xF80) >> 7) << 16 | (raw_ver & 0x7F);
10623         return bnx2x_format_ver(spirom_ver, str, len);
10624 }
10625
10626 static void bnx2x_8481_hw_reset(struct bnx2x_phy *phy,
10627                                 struct link_params *params)
10628 {
10629         bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1,
10630                        MISC_REGISTERS_GPIO_OUTPUT_LOW, 0);
10631         bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1,
10632                        MISC_REGISTERS_GPIO_OUTPUT_LOW, 1);
10633 }
10634
10635 static void bnx2x_8481_link_reset(struct bnx2x_phy *phy,
10636                                         struct link_params *params)
10637 {
10638         bnx2x_cl45_write(params->bp, phy,
10639                          MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x0000);
10640         bnx2x_cl45_write(params->bp, phy,
10641                          MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1);
10642 }
10643
10644 static void bnx2x_848x3_link_reset(struct bnx2x_phy *phy,
10645                                    struct link_params *params)
10646 {
10647         struct bnx2x *bp = params->bp;
10648         u8 port;
10649         u16 val16;
10650
10651         if (!(CHIP_IS_E1x(bp)))
10652                 port = BP_PATH(bp);
10653         else
10654                 port = params->port;
10655
10656         if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) {
10657                 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_3,
10658                                MISC_REGISTERS_GPIO_OUTPUT_LOW,
10659                                port);
10660         } else {
10661                 bnx2x_cl45_read(bp, phy,
10662                                 MDIO_CTL_DEVAD,
10663                                 MDIO_84833_TOP_CFG_XGPHY_STRAP1, &val16);
10664                 val16 |= MDIO_84833_SUPER_ISOLATE;
10665                 bnx2x_cl45_write(bp, phy,
10666                                  MDIO_CTL_DEVAD,
10667                                  MDIO_84833_TOP_CFG_XGPHY_STRAP1, val16);
10668         }
10669 }
10670
10671 static void bnx2x_848xx_set_link_led(struct bnx2x_phy *phy,
10672                                      struct link_params *params, u8 mode)
10673 {
10674         struct bnx2x *bp = params->bp;
10675         u16 val;
10676         u8 port;
10677
10678         if (!(CHIP_IS_E1x(bp)))
10679                 port = BP_PATH(bp);
10680         else
10681                 port = params->port;
10682
10683         switch (mode) {
10684         case LED_MODE_OFF:
10685
10686                 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE OFF\n", port);
10687
10688                 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
10689                     SHARED_HW_CFG_LED_EXTPHY1) {
10690
10691                         /* Set LED masks */
10692                         bnx2x_cl45_write(bp, phy,
10693                                         MDIO_PMA_DEVAD,
10694                                         MDIO_PMA_REG_8481_LED1_MASK,
10695                                         0x0);
10696
10697                         bnx2x_cl45_write(bp, phy,
10698                                         MDIO_PMA_DEVAD,
10699                                         MDIO_PMA_REG_8481_LED2_MASK,
10700                                         0x0);
10701
10702                         bnx2x_cl45_write(bp, phy,
10703                                         MDIO_PMA_DEVAD,
10704                                         MDIO_PMA_REG_8481_LED3_MASK,
10705                                         0x0);
10706
10707                         bnx2x_cl45_write(bp, phy,
10708                                         MDIO_PMA_DEVAD,
10709                                         MDIO_PMA_REG_8481_LED5_MASK,
10710                                         0x0);
10711
10712                 } else {
10713                         /* LED 1 OFF */
10714                         bnx2x_cl45_write(bp, phy,
10715                                          MDIO_PMA_DEVAD,
10716                                          MDIO_PMA_REG_8481_LED1_MASK,
10717                                          0x0);
10718
10719                         if (phy->type ==
10720                                 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84858) {
10721                                 /* LED 2 OFF */
10722                                 bnx2x_cl45_write(bp, phy,
10723                                                  MDIO_PMA_DEVAD,
10724                                                  MDIO_PMA_REG_8481_LED2_MASK,
10725                                                  0x0);
10726                                 /* LED 3 OFF */
10727                                 bnx2x_cl45_write(bp, phy,
10728                                                  MDIO_PMA_DEVAD,
10729                                                  MDIO_PMA_REG_8481_LED3_MASK,
10730                                                  0x0);
10731                         }
10732                 }
10733                 break;
10734         case LED_MODE_FRONT_PANEL_OFF:
10735
10736                 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE FRONT PANEL OFF\n",
10737                    port);
10738
10739                 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
10740                     SHARED_HW_CFG_LED_EXTPHY1) {
10741
10742                         /* Set LED masks */
10743                         bnx2x_cl45_write(bp, phy,
10744                                          MDIO_PMA_DEVAD,
10745                                          MDIO_PMA_REG_8481_LED1_MASK,
10746                                          0x0);
10747
10748                         bnx2x_cl45_write(bp, phy,
10749                                          MDIO_PMA_DEVAD,
10750                                          MDIO_PMA_REG_8481_LED2_MASK,
10751                                          0x0);
10752
10753                         bnx2x_cl45_write(bp, phy,
10754                                          MDIO_PMA_DEVAD,
10755                                          MDIO_PMA_REG_8481_LED3_MASK,
10756                                          0x0);
10757
10758                         bnx2x_cl45_write(bp, phy,
10759                                          MDIO_PMA_DEVAD,
10760                                          MDIO_PMA_REG_8481_LED5_MASK,
10761                                          0x20);
10762
10763                 } else {
10764                         bnx2x_cl45_write(bp, phy,
10765                                          MDIO_PMA_DEVAD,
10766                                          MDIO_PMA_REG_8481_LED1_MASK,
10767                                          0x0);
10768                         if (phy->type ==
10769                             PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834) {
10770                                 /* Disable MI_INT interrupt before setting LED4
10771                                  * source to constant off.
10772                                  */
10773                                 if (REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 +
10774                                            params->port*4) &
10775                                     NIG_MASK_MI_INT) {
10776                                         params->link_flags |=
10777                                         LINK_FLAGS_INT_DISABLED;
10778
10779                                         bnx2x_bits_dis(
10780                                                 bp,
10781                                                 NIG_REG_MASK_INTERRUPT_PORT0 +
10782                                                 params->port*4,
10783                                                 NIG_MASK_MI_INT);
10784                                 }
10785                                 bnx2x_cl45_write(bp, phy,
10786                                                  MDIO_PMA_DEVAD,
10787                                                  MDIO_PMA_REG_8481_SIGNAL_MASK,
10788                                                  0x0);
10789                         }
10790                         if (phy->type ==
10791                                 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84858) {
10792                                 /* LED 2 OFF */
10793                                 bnx2x_cl45_write(bp, phy,
10794                                                  MDIO_PMA_DEVAD,
10795                                                  MDIO_PMA_REG_8481_LED2_MASK,
10796                                                  0x0);
10797                                 /* LED 3 OFF */
10798                                 bnx2x_cl45_write(bp, phy,
10799                                                  MDIO_PMA_DEVAD,
10800                                                  MDIO_PMA_REG_8481_LED3_MASK,
10801                                                  0x0);
10802                         }
10803                 }
10804                 break;
10805         case LED_MODE_ON:
10806
10807                 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE ON\n", port);
10808
10809                 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
10810                     SHARED_HW_CFG_LED_EXTPHY1) {
10811                         /* Set control reg */
10812                         bnx2x_cl45_read(bp, phy,
10813                                         MDIO_PMA_DEVAD,
10814                                         MDIO_PMA_REG_8481_LINK_SIGNAL,
10815                                         &val);
10816                         val &= 0x8000;
10817                         val |= 0x2492;
10818
10819                         bnx2x_cl45_write(bp, phy,
10820                                          MDIO_PMA_DEVAD,
10821                                          MDIO_PMA_REG_8481_LINK_SIGNAL,
10822                                          val);
10823
10824                         /* Set LED masks */
10825                         bnx2x_cl45_write(bp, phy,
10826                                          MDIO_PMA_DEVAD,
10827                                          MDIO_PMA_REG_8481_LED1_MASK,
10828                                          0x0);
10829
10830                         bnx2x_cl45_write(bp, phy,
10831                                          MDIO_PMA_DEVAD,
10832                                          MDIO_PMA_REG_8481_LED2_MASK,
10833                                          0x20);
10834
10835                         bnx2x_cl45_write(bp, phy,
10836                                          MDIO_PMA_DEVAD,
10837                                          MDIO_PMA_REG_8481_LED3_MASK,
10838                                          0x20);
10839
10840                         bnx2x_cl45_write(bp, phy,
10841                                          MDIO_PMA_DEVAD,
10842                                          MDIO_PMA_REG_8481_LED5_MASK,
10843                                          0x0);
10844                 } else {
10845                         bnx2x_cl45_write(bp, phy,
10846                                          MDIO_PMA_DEVAD,
10847                                          MDIO_PMA_REG_8481_LED1_MASK,
10848                                          0x20);
10849                         if (phy->type ==
10850                             PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834) {
10851                                 /* Disable MI_INT interrupt before setting LED4
10852                                  * source to constant on.
10853                                  */
10854                                 if (REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 +
10855                                            params->port*4) &
10856                                     NIG_MASK_MI_INT) {
10857                                         params->link_flags |=
10858                                         LINK_FLAGS_INT_DISABLED;
10859
10860                                         bnx2x_bits_dis(
10861                                                 bp,
10862                                                 NIG_REG_MASK_INTERRUPT_PORT0 +
10863                                                 params->port*4,
10864                                                 NIG_MASK_MI_INT);
10865                                 }
10866                         }
10867                         if (phy->type ==
10868                             PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84858) {
10869                                 /* Tell LED3 to constant on */
10870                                 bnx2x_cl45_read(bp, phy,
10871                                                 MDIO_PMA_DEVAD,
10872                                                 MDIO_PMA_REG_8481_LINK_SIGNAL,
10873                                                 &val);
10874                                 val &= ~(7<<6);
10875                                 val |= (2<<6);  /* A83B[8:6]= 2 */
10876                                 bnx2x_cl45_write(bp, phy,
10877                                                  MDIO_PMA_DEVAD,
10878                                                  MDIO_PMA_REG_8481_LINK_SIGNAL,
10879                                                  val);
10880                                 bnx2x_cl45_write(bp, phy,
10881                                                  MDIO_PMA_DEVAD,
10882                                                  MDIO_PMA_REG_8481_LED3_MASK,
10883                                                  0x20);
10884                         } else {
10885                                 bnx2x_cl45_write(bp, phy,
10886                                                  MDIO_PMA_DEVAD,
10887                                                  MDIO_PMA_REG_8481_SIGNAL_MASK,
10888                                                  0x20);
10889                         }
10890                 }
10891                 break;
10892
10893         case LED_MODE_OPER:
10894
10895                 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE OPER\n", port);
10896
10897                 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
10898                     SHARED_HW_CFG_LED_EXTPHY1) {
10899
10900                         /* Set control reg */
10901                         bnx2x_cl45_read(bp, phy,
10902                                         MDIO_PMA_DEVAD,
10903                                         MDIO_PMA_REG_8481_LINK_SIGNAL,
10904                                         &val);
10905
10906                         if (!((val &
10907                                MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_MASK)
10908                           >> MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_SHIFT)) {
10909                                 DP(NETIF_MSG_LINK, "Setting LINK_SIGNAL\n");
10910                                 bnx2x_cl45_write(bp, phy,
10911                                                  MDIO_PMA_DEVAD,
10912                                                  MDIO_PMA_REG_8481_LINK_SIGNAL,
10913                                                  0xa492);
10914                         }
10915
10916                         /* Set LED masks */
10917                         bnx2x_cl45_write(bp, phy,
10918                                          MDIO_PMA_DEVAD,
10919                                          MDIO_PMA_REG_8481_LED1_MASK,
10920                                          0x10);
10921
10922                         bnx2x_cl45_write(bp, phy,
10923                                          MDIO_PMA_DEVAD,
10924                                          MDIO_PMA_REG_8481_LED2_MASK,
10925                                          0x80);
10926
10927                         bnx2x_cl45_write(bp, phy,
10928                                          MDIO_PMA_DEVAD,
10929                                          MDIO_PMA_REG_8481_LED3_MASK,
10930                                          0x98);
10931
10932                         bnx2x_cl45_write(bp, phy,
10933                                          MDIO_PMA_DEVAD,
10934                                          MDIO_PMA_REG_8481_LED5_MASK,
10935                                          0x40);
10936
10937                 } else {
10938                         /* EXTPHY2 LED mode indicate that the 100M/1G/10G LED
10939                          * sources are all wired through LED1, rather than only
10940                          * 10G in other modes.
10941                          */
10942                         val = ((params->hw_led_mode <<
10943                                 SHARED_HW_CFG_LED_MODE_SHIFT) ==
10944                                SHARED_HW_CFG_LED_EXTPHY2) ? 0x98 : 0x80;
10945
10946                         bnx2x_cl45_write(bp, phy,
10947                                          MDIO_PMA_DEVAD,
10948                                          MDIO_PMA_REG_8481_LED1_MASK,
10949                                          val);
10950
10951                         /* Tell LED3 to blink on source */
10952                         bnx2x_cl45_read(bp, phy,
10953                                         MDIO_PMA_DEVAD,
10954                                         MDIO_PMA_REG_8481_LINK_SIGNAL,
10955                                         &val);
10956                         val &= ~(7<<6);
10957                         val |= (1<<6); /* A83B[8:6]= 1 */
10958                         bnx2x_cl45_write(bp, phy,
10959                                          MDIO_PMA_DEVAD,
10960                                          MDIO_PMA_REG_8481_LINK_SIGNAL,
10961                                          val);
10962                         if (phy->type ==
10963                             PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84858) {
10964                                 bnx2x_cl45_write(bp, phy,
10965                                                  MDIO_PMA_DEVAD,
10966                                                  MDIO_PMA_REG_8481_LED2_MASK,
10967                                                  0x18);
10968                                 bnx2x_cl45_write(bp, phy,
10969                                                  MDIO_PMA_DEVAD,
10970                                                  MDIO_PMA_REG_8481_LED3_MASK,
10971                                                  0x06);
10972                         }
10973                         if (phy->type ==
10974                             PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834) {
10975                                 /* Restore LED4 source to external link,
10976                                  * and re-enable interrupts.
10977                                  */
10978                                 bnx2x_cl45_write(bp, phy,
10979                                                  MDIO_PMA_DEVAD,
10980                                                  MDIO_PMA_REG_8481_SIGNAL_MASK,
10981                                                  0x40);
10982                                 if (params->link_flags &
10983                                     LINK_FLAGS_INT_DISABLED) {
10984                                         bnx2x_link_int_enable(params);
10985                                         params->link_flags &=
10986                                                 ~LINK_FLAGS_INT_DISABLED;
10987                                 }
10988                         }
10989                 }
10990                 break;
10991         }
10992
10993         /* This is a workaround for E3+84833 until autoneg
10994          * restart is fixed in f/w
10995          */
10996         if (CHIP_IS_E3(bp)) {
10997                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
10998                                 MDIO_WC_REG_GP2_STATUS_GP_2_1, &val);
10999         }
11000 }
11001
11002 /******************************************************************/
11003 /*                      54618SE PHY SECTION                       */
11004 /******************************************************************/
11005 static void bnx2x_54618se_specific_func(struct bnx2x_phy *phy,
11006                                         struct link_params *params,
11007                                         u32 action)
11008 {
11009         struct bnx2x *bp = params->bp;
11010         u16 temp;
11011         switch (action) {
11012         case PHY_INIT:
11013                 /* Configure LED4: set to INTR (0x6). */
11014                 /* Accessing shadow register 0xe. */
11015                 bnx2x_cl22_write(bp, phy,
11016                                  MDIO_REG_GPHY_SHADOW,
11017                                  MDIO_REG_GPHY_SHADOW_LED_SEL2);
11018                 bnx2x_cl22_read(bp, phy,
11019                                 MDIO_REG_GPHY_SHADOW,
11020                                 &temp);
11021                 temp &= ~(0xf << 4);
11022                 temp |= (0x6 << 4);
11023                 bnx2x_cl22_write(bp, phy,
11024                                  MDIO_REG_GPHY_SHADOW,
11025                                  MDIO_REG_GPHY_SHADOW_WR_ENA | temp);
11026                 /* Configure INTR based on link status change. */
11027                 bnx2x_cl22_write(bp, phy,
11028                                  MDIO_REG_INTR_MASK,
11029                                  ~MDIO_REG_INTR_MASK_LINK_STATUS);
11030                 break;
11031         }
11032 }
11033
11034 static void bnx2x_54618se_config_init(struct bnx2x_phy *phy,
11035                                       struct link_params *params,
11036                                       struct link_vars *vars)
11037 {
11038         struct bnx2x *bp = params->bp;
11039         u8 port;
11040         u16 autoneg_val, an_1000_val, an_10_100_val, fc_val, temp;
11041         u32 cfg_pin;
11042
11043         DP(NETIF_MSG_LINK, "54618SE cfg init\n");
11044         usleep_range(1000, 2000);
11045
11046         /* This works with E3 only, no need to check the chip
11047          * before determining the port.
11048          */
11049         port = params->port;
11050
11051         cfg_pin = (REG_RD(bp, params->shmem_base +
11052                         offsetof(struct shmem_region,
11053                         dev_info.port_hw_config[port].e3_cmn_pin_cfg)) &
11054                         PORT_HW_CFG_E3_PHY_RESET_MASK) >>
11055                         PORT_HW_CFG_E3_PHY_RESET_SHIFT;
11056
11057         /* Drive pin high to bring the GPHY out of reset. */
11058         bnx2x_set_cfg_pin(bp, cfg_pin, 1);
11059
11060         /* wait for GPHY to reset */
11061         msleep(50);
11062
11063         /* reset phy */
11064         bnx2x_cl22_write(bp, phy,
11065                          MDIO_PMA_REG_CTRL, 0x8000);
11066         bnx2x_wait_reset_complete(bp, phy, params);
11067
11068         /* Wait for GPHY to reset */
11069         msleep(50);
11070
11071
11072         bnx2x_54618se_specific_func(phy, params, PHY_INIT);
11073         /* Flip the signal detect polarity (set 0x1c.0x1e[8]). */
11074         bnx2x_cl22_write(bp, phy,
11075                         MDIO_REG_GPHY_SHADOW,
11076                         MDIO_REG_GPHY_SHADOW_AUTO_DET_MED);
11077         bnx2x_cl22_read(bp, phy,
11078                         MDIO_REG_GPHY_SHADOW,
11079                         &temp);
11080         temp |= MDIO_REG_GPHY_SHADOW_INVERT_FIB_SD;
11081         bnx2x_cl22_write(bp, phy,
11082                         MDIO_REG_GPHY_SHADOW,
11083                         MDIO_REG_GPHY_SHADOW_WR_ENA | temp);
11084
11085         /* Set up fc */
11086         /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
11087         bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
11088         fc_val = 0;
11089         if ((vars->ieee_fc & MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
11090                         MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC)
11091                 fc_val |= MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC;
11092
11093         if ((vars->ieee_fc & MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
11094                         MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH)
11095                 fc_val |= MDIO_AN_REG_ADV_PAUSE_PAUSE;
11096
11097         /* Read all advertisement */
11098         bnx2x_cl22_read(bp, phy,
11099                         0x09,
11100                         &an_1000_val);
11101
11102         bnx2x_cl22_read(bp, phy,
11103                         0x04,
11104                         &an_10_100_val);
11105
11106         bnx2x_cl22_read(bp, phy,
11107                         MDIO_PMA_REG_CTRL,
11108                         &autoneg_val);
11109
11110         /* Disable forced speed */
11111         autoneg_val &= ~((1<<6) | (1<<8) | (1<<9) | (1<<12) | (1<<13));
11112         an_10_100_val &= ~((1<<5) | (1<<6) | (1<<7) | (1<<8) | (1<<10) |
11113                            (1<<11));
11114
11115         if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
11116              (phy->speed_cap_mask &
11117               PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
11118             (phy->req_line_speed == SPEED_1000)) {
11119                 an_1000_val |= (1<<8);
11120                 autoneg_val |= (1<<9 | 1<<12);
11121                 if (phy->req_duplex == DUPLEX_FULL)
11122                         an_1000_val |= (1<<9);
11123                 DP(NETIF_MSG_LINK, "Advertising 1G\n");
11124         } else
11125                 an_1000_val &= ~((1<<8) | (1<<9));
11126
11127         bnx2x_cl22_write(bp, phy,
11128                         0x09,
11129                         an_1000_val);
11130         bnx2x_cl22_read(bp, phy,
11131                         0x09,
11132                         &an_1000_val);
11133
11134         /* Advertise 10/100 link speed */
11135         if (phy->req_line_speed == SPEED_AUTO_NEG) {
11136                 if (phy->speed_cap_mask &
11137                     PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF) {
11138                         an_10_100_val |= (1<<5);
11139                         autoneg_val |= (1<<9 | 1<<12);
11140                         DP(NETIF_MSG_LINK, "Advertising 10M-HD\n");
11141                 }
11142                 if (phy->speed_cap_mask &
11143                     PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL) {
11144                         an_10_100_val |= (1<<6);
11145                         autoneg_val |= (1<<9 | 1<<12);
11146                         DP(NETIF_MSG_LINK, "Advertising 10M-FD\n");
11147                 }
11148                 if (phy->speed_cap_mask &
11149                     PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF) {
11150                         an_10_100_val |= (1<<7);
11151                         autoneg_val |= (1<<9 | 1<<12);
11152                         DP(NETIF_MSG_LINK, "Advertising 100M-HD\n");
11153                 }
11154                 if (phy->speed_cap_mask &
11155                     PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL) {
11156                         an_10_100_val |= (1<<8);
11157                         autoneg_val |= (1<<9 | 1<<12);
11158                         DP(NETIF_MSG_LINK, "Advertising 100M-FD\n");
11159                 }
11160         }
11161
11162         /* Only 10/100 are allowed to work in FORCE mode */
11163         if (phy->req_line_speed == SPEED_100) {
11164                 autoneg_val |= (1<<13);
11165                 /* Enabled AUTO-MDIX when autoneg is disabled */
11166                 bnx2x_cl22_write(bp, phy,
11167                                 0x18,
11168                                 (1<<15 | 1<<9 | 7<<0));
11169                 DP(NETIF_MSG_LINK, "Setting 100M force\n");
11170         }
11171         if (phy->req_line_speed == SPEED_10) {
11172                 /* Enabled AUTO-MDIX when autoneg is disabled */
11173                 bnx2x_cl22_write(bp, phy,
11174                                 0x18,
11175                                 (1<<15 | 1<<9 | 7<<0));
11176                 DP(NETIF_MSG_LINK, "Setting 10M force\n");
11177         }
11178
11179         if ((phy->flags & FLAGS_EEE) && bnx2x_eee_has_cap(params)) {
11180                 int rc;
11181
11182                 bnx2x_cl22_write(bp, phy, MDIO_REG_GPHY_EXP_ACCESS,
11183                                  MDIO_REG_GPHY_EXP_ACCESS_TOP |
11184                                  MDIO_REG_GPHY_EXP_TOP_2K_BUF);
11185                 bnx2x_cl22_read(bp, phy, MDIO_REG_GPHY_EXP_ACCESS_GATE, &temp);
11186                 temp &= 0xfffe;
11187                 bnx2x_cl22_write(bp, phy, MDIO_REG_GPHY_EXP_ACCESS_GATE, temp);
11188
11189                 rc = bnx2x_eee_initial_config(params, vars, SHMEM_EEE_1G_ADV);
11190                 if (rc) {
11191                         DP(NETIF_MSG_LINK, "Failed to configure EEE timers\n");
11192                         bnx2x_eee_disable(phy, params, vars);
11193                 } else if ((params->eee_mode & EEE_MODE_ADV_LPI) &&
11194                            (phy->req_duplex == DUPLEX_FULL) &&
11195                            (bnx2x_eee_calc_timer(params) ||
11196                             !(params->eee_mode & EEE_MODE_ENABLE_LPI))) {
11197                         /* Need to advertise EEE only when requested,
11198                          * and either no LPI assertion was requested,
11199                          * or it was requested and a valid timer was set.
11200                          * Also notice full duplex is required for EEE.
11201                          */
11202                         bnx2x_eee_advertise(phy, params, vars,
11203                                             SHMEM_EEE_1G_ADV);
11204                 } else {
11205                         DP(NETIF_MSG_LINK, "Don't Advertise 1GBase-T EEE\n");
11206                         bnx2x_eee_disable(phy, params, vars);
11207                 }
11208         } else {
11209                 vars->eee_status &= ~SHMEM_EEE_1G_ADV <<
11210                                     SHMEM_EEE_SUPPORTED_SHIFT;
11211
11212                 if (phy->flags & FLAGS_EEE) {
11213                         /* Handle legacy auto-grEEEn */
11214                         if (params->feature_config_flags &
11215                             FEATURE_CONFIG_AUTOGREEEN_ENABLED) {
11216                                 temp = 6;
11217                                 DP(NETIF_MSG_LINK, "Enabling Auto-GrEEEn\n");
11218                         } else {
11219                                 temp = 0;
11220                                 DP(NETIF_MSG_LINK, "Don't Adv. EEE\n");
11221                         }
11222                         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
11223                                          MDIO_AN_REG_EEE_ADV, temp);
11224                 }
11225         }
11226
11227         bnx2x_cl22_write(bp, phy,
11228                         0x04,
11229                         an_10_100_val | fc_val);
11230
11231         if (phy->req_duplex == DUPLEX_FULL)
11232                 autoneg_val |= (1<<8);
11233
11234         bnx2x_cl22_write(bp, phy,
11235                         MDIO_PMA_REG_CTRL, autoneg_val);
11236 }
11237
11238
11239 static void bnx2x_5461x_set_link_led(struct bnx2x_phy *phy,
11240                                        struct link_params *params, u8 mode)
11241 {
11242         struct bnx2x *bp = params->bp;
11243         u16 temp;
11244
11245         bnx2x_cl22_write(bp, phy,
11246                 MDIO_REG_GPHY_SHADOW,
11247                 MDIO_REG_GPHY_SHADOW_LED_SEL1);
11248         bnx2x_cl22_read(bp, phy,
11249                 MDIO_REG_GPHY_SHADOW,
11250                 &temp);
11251         temp &= 0xff00;
11252
11253         DP(NETIF_MSG_LINK, "54618x set link led (mode=%x)\n", mode);
11254         switch (mode) {
11255         case LED_MODE_FRONT_PANEL_OFF:
11256         case LED_MODE_OFF:
11257                 temp |= 0x00ee;
11258                 break;
11259         case LED_MODE_OPER:
11260                 temp |= 0x0001;
11261                 break;
11262         case LED_MODE_ON:
11263                 temp |= 0x00ff;
11264                 break;
11265         default:
11266                 break;
11267         }
11268         bnx2x_cl22_write(bp, phy,
11269                 MDIO_REG_GPHY_SHADOW,
11270                 MDIO_REG_GPHY_SHADOW_WR_ENA | temp);
11271         return;
11272 }
11273
11274
11275 static void bnx2x_54618se_link_reset(struct bnx2x_phy *phy,
11276                                      struct link_params *params)
11277 {
11278         struct bnx2x *bp = params->bp;
11279         u32 cfg_pin;
11280         u8 port;
11281
11282         /* In case of no EPIO routed to reset the GPHY, put it
11283          * in low power mode.
11284          */
11285         bnx2x_cl22_write(bp, phy, MDIO_PMA_REG_CTRL, 0x800);
11286         /* This works with E3 only, no need to check the chip
11287          * before determining the port.
11288          */
11289         port = params->port;
11290         cfg_pin = (REG_RD(bp, params->shmem_base +
11291                         offsetof(struct shmem_region,
11292                         dev_info.port_hw_config[port].e3_cmn_pin_cfg)) &
11293                         PORT_HW_CFG_E3_PHY_RESET_MASK) >>
11294                         PORT_HW_CFG_E3_PHY_RESET_SHIFT;
11295
11296         /* Drive pin low to put GPHY in reset. */
11297         bnx2x_set_cfg_pin(bp, cfg_pin, 0);
11298 }
11299
11300 static u8 bnx2x_54618se_read_status(struct bnx2x_phy *phy,
11301                                     struct link_params *params,
11302                                     struct link_vars *vars)
11303 {
11304         struct bnx2x *bp = params->bp;
11305         u16 val;
11306         u8 link_up = 0;
11307         u16 legacy_status, legacy_speed;
11308
11309         /* Get speed operation status */
11310         bnx2x_cl22_read(bp, phy,
11311                         MDIO_REG_GPHY_AUX_STATUS,
11312                         &legacy_status);
11313         DP(NETIF_MSG_LINK, "54618SE read_status: 0x%x\n", legacy_status);
11314
11315         /* Read status to clear the PHY interrupt. */
11316         bnx2x_cl22_read(bp, phy,
11317                         MDIO_REG_INTR_STATUS,
11318                         &val);
11319
11320         link_up = ((legacy_status & (1<<2)) == (1<<2));
11321
11322         if (link_up) {
11323                 legacy_speed = (legacy_status & (7<<8));
11324                 if (legacy_speed == (7<<8)) {
11325                         vars->line_speed = SPEED_1000;
11326                         vars->duplex = DUPLEX_FULL;
11327                 } else if (legacy_speed == (6<<8)) {
11328                         vars->line_speed = SPEED_1000;
11329                         vars->duplex = DUPLEX_HALF;
11330                 } else if (legacy_speed == (5<<8)) {
11331                         vars->line_speed = SPEED_100;
11332                         vars->duplex = DUPLEX_FULL;
11333                 }
11334                 /* Omitting 100Base-T4 for now */
11335                 else if (legacy_speed == (3<<8)) {
11336                         vars->line_speed = SPEED_100;
11337                         vars->duplex = DUPLEX_HALF;
11338                 } else if (legacy_speed == (2<<8)) {
11339                         vars->line_speed = SPEED_10;
11340                         vars->duplex = DUPLEX_FULL;
11341                 } else if (legacy_speed == (1<<8)) {
11342                         vars->line_speed = SPEED_10;
11343                         vars->duplex = DUPLEX_HALF;
11344                 } else /* Should not happen */
11345                         vars->line_speed = 0;
11346
11347                 DP(NETIF_MSG_LINK,
11348                    "Link is up in %dMbps, is_duplex_full= %d\n",
11349                    vars->line_speed,
11350                    (vars->duplex == DUPLEX_FULL));
11351
11352                 /* Check legacy speed AN resolution */
11353                 bnx2x_cl22_read(bp, phy,
11354                                 0x01,
11355                                 &val);
11356                 if (val & (1<<5))
11357                         vars->link_status |=
11358                                 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
11359                 bnx2x_cl22_read(bp, phy,
11360                                 0x06,
11361                                 &val);
11362                 if ((val & (1<<0)) == 0)
11363                         vars->link_status |=
11364                                 LINK_STATUS_PARALLEL_DETECTION_USED;
11365
11366                 DP(NETIF_MSG_LINK, "BCM54618SE: link speed is %d\n",
11367                            vars->line_speed);
11368
11369                 bnx2x_ext_phy_resolve_fc(phy, params, vars);
11370
11371                 if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) {
11372                         /* Report LP advertised speeds */
11373                         bnx2x_cl22_read(bp, phy, 0x5, &val);
11374
11375                         if (val & (1<<5))
11376                                 vars->link_status |=
11377                                   LINK_STATUS_LINK_PARTNER_10THD_CAPABLE;
11378                         if (val & (1<<6))
11379                                 vars->link_status |=
11380                                   LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE;
11381                         if (val & (1<<7))
11382                                 vars->link_status |=
11383                                   LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE;
11384                         if (val & (1<<8))
11385                                 vars->link_status |=
11386                                   LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE;
11387                         if (val & (1<<9))
11388                                 vars->link_status |=
11389                                   LINK_STATUS_LINK_PARTNER_100T4_CAPABLE;
11390
11391                         bnx2x_cl22_read(bp, phy, 0xa, &val);
11392                         if (val & (1<<10))
11393                                 vars->link_status |=
11394                                   LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE;
11395                         if (val & (1<<11))
11396                                 vars->link_status |=
11397                                   LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;
11398
11399                         if ((phy->flags & FLAGS_EEE) &&
11400                             bnx2x_eee_has_cap(params))
11401                                 bnx2x_eee_an_resolve(phy, params, vars);
11402                 }
11403         }
11404         return link_up;
11405 }
11406
11407 static void bnx2x_54618se_config_loopback(struct bnx2x_phy *phy,
11408                                           struct link_params *params)
11409 {
11410         struct bnx2x *bp = params->bp;
11411         u16 val;
11412         u32 umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
11413
11414         DP(NETIF_MSG_LINK, "2PMA/PMD ext_phy_loopback: 54618se\n");
11415
11416         /* Enable master/slave manual mmode and set to master */
11417         /* mii write 9 [bits set 11 12] */
11418         bnx2x_cl22_write(bp, phy, 0x09, 3<<11);
11419
11420         /* forced 1G and disable autoneg */
11421         /* set val [mii read 0] */
11422         /* set val [expr $val & [bits clear 6 12 13]] */
11423         /* set val [expr $val | [bits set 6 8]] */
11424         /* mii write 0 $val */
11425         bnx2x_cl22_read(bp, phy, 0x00, &val);
11426         val &= ~((1<<6) | (1<<12) | (1<<13));
11427         val |= (1<<6) | (1<<8);
11428         bnx2x_cl22_write(bp, phy, 0x00, val);
11429
11430         /* Set external loopback and Tx using 6dB coding */
11431         /* mii write 0x18 7 */
11432         /* set val [mii read 0x18] */
11433         /* mii write 0x18 [expr $val | [bits set 10 15]] */
11434         bnx2x_cl22_write(bp, phy, 0x18, 7);
11435         bnx2x_cl22_read(bp, phy, 0x18, &val);
11436         bnx2x_cl22_write(bp, phy, 0x18, val | (1<<10) | (1<<15));
11437
11438         /* This register opens the gate for the UMAC despite its name */
11439         REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 1);
11440
11441         /* Maximum Frame Length (RW). Defines a 14-Bit maximum frame
11442          * length used by the MAC receive logic to check frames.
11443          */
11444         REG_WR(bp, umac_base + UMAC_REG_MAXFR, 0x2710);
11445 }
11446
11447 /******************************************************************/
11448 /*                      SFX7101 PHY SECTION                       */
11449 /******************************************************************/
11450 static void bnx2x_7101_config_loopback(struct bnx2x_phy *phy,
11451                                        struct link_params *params)
11452 {
11453         struct bnx2x *bp = params->bp;
11454         /* SFX7101_XGXS_TEST1 */
11455         bnx2x_cl45_write(bp, phy,
11456                          MDIO_XS_DEVAD, MDIO_XS_SFX7101_XGXS_TEST1, 0x100);
11457 }
11458
11459 static void bnx2x_7101_config_init(struct bnx2x_phy *phy,
11460                                    struct link_params *params,
11461                                    struct link_vars *vars)
11462 {
11463         u16 fw_ver1, fw_ver2, val;
11464         struct bnx2x *bp = params->bp;
11465         DP(NETIF_MSG_LINK, "Setting the SFX7101 LASI indication\n");
11466
11467         /* Restore normal power mode*/
11468         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
11469                        MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
11470         /* HW reset */
11471         bnx2x_ext_phy_hw_reset(bp, params->port);
11472         bnx2x_wait_reset_complete(bp, phy, params);
11473
11474         bnx2x_cl45_write(bp, phy,
11475                          MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x1);
11476         DP(NETIF_MSG_LINK, "Setting the SFX7101 LED to blink on traffic\n");
11477         bnx2x_cl45_write(bp, phy,
11478                          MDIO_PMA_DEVAD, MDIO_PMA_REG_7107_LED_CNTL, (1<<3));
11479
11480         bnx2x_ext_phy_set_pause(params, phy, vars);
11481         /* Restart autoneg */
11482         bnx2x_cl45_read(bp, phy,
11483                         MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, &val);
11484         val |= 0x200;
11485         bnx2x_cl45_write(bp, phy,
11486                          MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, val);
11487
11488         /* Save spirom version */
11489         bnx2x_cl45_read(bp, phy,
11490                         MDIO_PMA_DEVAD, MDIO_PMA_REG_7101_VER1, &fw_ver1);
11491
11492         bnx2x_cl45_read(bp, phy,
11493                         MDIO_PMA_DEVAD, MDIO_PMA_REG_7101_VER2, &fw_ver2);
11494         bnx2x_save_spirom_version(bp, params->port,
11495                                   (u32)(fw_ver1<<16 | fw_ver2), phy->ver_addr);
11496 }
11497
11498 static u8 bnx2x_7101_read_status(struct bnx2x_phy *phy,
11499                                  struct link_params *params,
11500                                  struct link_vars *vars)
11501 {
11502         struct bnx2x *bp = params->bp;
11503         u8 link_up;
11504         u16 val1, val2;
11505         bnx2x_cl45_read(bp, phy,
11506                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val2);
11507         bnx2x_cl45_read(bp, phy,
11508                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
11509         DP(NETIF_MSG_LINK, "10G-base-T LASI status 0x%x->0x%x\n",
11510                    val2, val1);
11511         bnx2x_cl45_read(bp, phy,
11512                         MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);
11513         bnx2x_cl45_read(bp, phy,
11514                         MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);
11515         DP(NETIF_MSG_LINK, "10G-base-T PMA status 0x%x->0x%x\n",
11516                    val2, val1);
11517         link_up = ((val1 & 4) == 4);
11518         /* If link is up print the AN outcome of the SFX7101 PHY */
11519         if (link_up) {
11520                 bnx2x_cl45_read(bp, phy,
11521                                 MDIO_AN_DEVAD, MDIO_AN_REG_MASTER_STATUS,
11522                                 &val2);
11523                 vars->line_speed = SPEED_10000;
11524                 vars->duplex = DUPLEX_FULL;
11525                 DP(NETIF_MSG_LINK, "SFX7101 AN status 0x%x->Master=%x\n",
11526                            val2, (val2 & (1<<14)));
11527                 bnx2x_ext_phy_10G_an_resolve(bp, phy, vars);
11528                 bnx2x_ext_phy_resolve_fc(phy, params, vars);
11529
11530                 /* Read LP advertised speeds */
11531                 if (val2 & (1<<11))
11532                         vars->link_status |=
11533                                 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
11534         }
11535         return link_up;
11536 }
11537
11538 static int bnx2x_7101_format_ver(u32 spirom_ver, u8 *str, u16 *len)
11539 {
11540         if (*len < 5)
11541                 return -EINVAL;
11542         str[0] = (spirom_ver & 0xFF);
11543         str[1] = (spirom_ver & 0xFF00) >> 8;
11544         str[2] = (spirom_ver & 0xFF0000) >> 16;
11545         str[3] = (spirom_ver & 0xFF000000) >> 24;
11546         str[4] = '\0';
11547         *len -= 5;
11548         return 0;
11549 }
11550
11551 void bnx2x_sfx7101_sp_sw_reset(struct bnx2x *bp, struct bnx2x_phy *phy)
11552 {
11553         u16 val, cnt;
11554
11555         bnx2x_cl45_read(bp, phy,
11556                         MDIO_PMA_DEVAD,
11557                         MDIO_PMA_REG_7101_RESET, &val);
11558
11559         for (cnt = 0; cnt < 10; cnt++) {
11560                 msleep(50);
11561                 /* Writes a self-clearing reset */
11562                 bnx2x_cl45_write(bp, phy,
11563                                  MDIO_PMA_DEVAD,
11564                                  MDIO_PMA_REG_7101_RESET,
11565                                  (val | (1<<15)));
11566                 /* Wait for clear */
11567                 bnx2x_cl45_read(bp, phy,
11568                                 MDIO_PMA_DEVAD,
11569                                 MDIO_PMA_REG_7101_RESET, &val);
11570
11571                 if ((val & (1<<15)) == 0)
11572                         break;
11573         }
11574 }
11575
11576 static void bnx2x_7101_hw_reset(struct bnx2x_phy *phy,
11577                                 struct link_params *params) {
11578         /* Low power mode is controlled by GPIO 2 */
11579         bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_2,
11580                        MISC_REGISTERS_GPIO_OUTPUT_LOW, params->port);
11581         /* The PHY reset is controlled by GPIO 1 */
11582         bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1,
11583                        MISC_REGISTERS_GPIO_OUTPUT_LOW, params->port);
11584 }
11585
11586 static void bnx2x_7101_set_link_led(struct bnx2x_phy *phy,
11587                                     struct link_params *params, u8 mode)
11588 {
11589         u16 val = 0;
11590         struct bnx2x *bp = params->bp;
11591         switch (mode) {
11592         case LED_MODE_FRONT_PANEL_OFF:
11593         case LED_MODE_OFF:
11594                 val = 2;
11595                 break;
11596         case LED_MODE_ON:
11597                 val = 1;
11598                 break;
11599         case LED_MODE_OPER:
11600                 val = 0;
11601                 break;
11602         }
11603         bnx2x_cl45_write(bp, phy,
11604                          MDIO_PMA_DEVAD,
11605                          MDIO_PMA_REG_7107_LINK_LED_CNTL,
11606                          val);
11607 }
11608
11609 /******************************************************************/
11610 /*                      STATIC PHY DECLARATION                    */
11611 /******************************************************************/
11612
11613 static const struct bnx2x_phy phy_null = {
11614         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN,
11615         .addr           = 0,
11616         .def_md_devad   = 0,
11617         .flags          = FLAGS_INIT_XGXS_FIRST,
11618         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11619         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11620         .mdio_ctrl      = 0,
11621         .supported      = 0,
11622         .media_type     = ETH_PHY_NOT_PRESENT,
11623         .ver_addr       = 0,
11624         .req_flow_ctrl  = 0,
11625         .req_line_speed = 0,
11626         .speed_cap_mask = 0,
11627         .req_duplex     = 0,
11628         .rsrv           = 0,
11629         .config_init    = NULL,
11630         .read_status    = NULL,
11631         .link_reset     = NULL,
11632         .config_loopback = NULL,
11633         .format_fw_ver  = NULL,
11634         .hw_reset       = NULL,
11635         .set_link_led   = NULL,
11636         .phy_specific_func = NULL
11637 };
11638
11639 static const struct bnx2x_phy phy_serdes = {
11640         .type           = PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT,
11641         .addr           = 0xff,
11642         .def_md_devad   = 0,
11643         .flags          = 0,
11644         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11645         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11646         .mdio_ctrl      = 0,
11647         .supported      = (SUPPORTED_10baseT_Half |
11648                            SUPPORTED_10baseT_Full |
11649                            SUPPORTED_100baseT_Half |
11650                            SUPPORTED_100baseT_Full |
11651                            SUPPORTED_1000baseT_Full |
11652                            SUPPORTED_2500baseX_Full |
11653                            SUPPORTED_TP |
11654                            SUPPORTED_Autoneg |
11655                            SUPPORTED_Pause |
11656                            SUPPORTED_Asym_Pause),
11657         .media_type     = ETH_PHY_BASE_T,
11658         .ver_addr       = 0,
11659         .req_flow_ctrl  = 0,
11660         .req_line_speed = 0,
11661         .speed_cap_mask = 0,
11662         .req_duplex     = 0,
11663         .rsrv           = 0,
11664         .config_init    = bnx2x_xgxs_config_init,
11665         .read_status    = bnx2x_link_settings_status,
11666         .link_reset     = bnx2x_int_link_reset,
11667         .config_loopback = NULL,
11668         .format_fw_ver  = NULL,
11669         .hw_reset       = NULL,
11670         .set_link_led   = NULL,
11671         .phy_specific_func = NULL
11672 };
11673
11674 static const struct bnx2x_phy phy_xgxs = {
11675         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT,
11676         .addr           = 0xff,
11677         .def_md_devad   = 0,
11678         .flags          = 0,
11679         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11680         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11681         .mdio_ctrl      = 0,
11682         .supported      = (SUPPORTED_10baseT_Half |
11683                            SUPPORTED_10baseT_Full |
11684                            SUPPORTED_100baseT_Half |
11685                            SUPPORTED_100baseT_Full |
11686                            SUPPORTED_1000baseT_Full |
11687                            SUPPORTED_2500baseX_Full |
11688                            SUPPORTED_10000baseT_Full |
11689                            SUPPORTED_FIBRE |
11690                            SUPPORTED_Autoneg |
11691                            SUPPORTED_Pause |
11692                            SUPPORTED_Asym_Pause),
11693         .media_type     = ETH_PHY_CX4,
11694         .ver_addr       = 0,
11695         .req_flow_ctrl  = 0,
11696         .req_line_speed = 0,
11697         .speed_cap_mask = 0,
11698         .req_duplex     = 0,
11699         .rsrv           = 0,
11700         .config_init    = bnx2x_xgxs_config_init,
11701         .read_status    = bnx2x_link_settings_status,
11702         .link_reset     = bnx2x_int_link_reset,
11703         .config_loopback = bnx2x_set_xgxs_loopback,
11704         .format_fw_ver  = NULL,
11705         .hw_reset       = NULL,
11706         .set_link_led   = NULL,
11707         .phy_specific_func = bnx2x_xgxs_specific_func
11708 };
11709 static const struct bnx2x_phy phy_warpcore = {
11710         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT,
11711         .addr           = 0xff,
11712         .def_md_devad   = 0,
11713         .flags          = FLAGS_TX_ERROR_CHECK,
11714         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11715         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11716         .mdio_ctrl      = 0,
11717         .supported      = (SUPPORTED_10baseT_Half |
11718                            SUPPORTED_10baseT_Full |
11719                            SUPPORTED_100baseT_Half |
11720                            SUPPORTED_100baseT_Full |
11721                            SUPPORTED_1000baseT_Full |
11722                            SUPPORTED_1000baseKX_Full |
11723                            SUPPORTED_10000baseT_Full |
11724                            SUPPORTED_10000baseKR_Full |
11725                            SUPPORTED_20000baseKR2_Full |
11726                            SUPPORTED_20000baseMLD2_Full |
11727                            SUPPORTED_FIBRE |
11728                            SUPPORTED_Autoneg |
11729                            SUPPORTED_Pause |
11730                            SUPPORTED_Asym_Pause),
11731         .media_type     = ETH_PHY_UNSPECIFIED,
11732         .ver_addr       = 0,
11733         .req_flow_ctrl  = 0,
11734         .req_line_speed = 0,
11735         .speed_cap_mask = 0,
11736         /* req_duplex = */0,
11737         /* rsrv = */0,
11738         .config_init    = bnx2x_warpcore_config_init,
11739         .read_status    = bnx2x_warpcore_read_status,
11740         .link_reset     = bnx2x_warpcore_link_reset,
11741         .config_loopback = bnx2x_set_warpcore_loopback,
11742         .format_fw_ver  = NULL,
11743         .hw_reset       = bnx2x_warpcore_hw_reset,
11744         .set_link_led   = NULL,
11745         .phy_specific_func = NULL
11746 };
11747
11748
11749 static const struct bnx2x_phy phy_7101 = {
11750         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
11751         .addr           = 0xff,
11752         .def_md_devad   = 0,
11753         .flags          = FLAGS_FAN_FAILURE_DET_REQ,
11754         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11755         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11756         .mdio_ctrl      = 0,
11757         .supported      = (SUPPORTED_10000baseT_Full |
11758                            SUPPORTED_TP |
11759                            SUPPORTED_Autoneg |
11760                            SUPPORTED_Pause |
11761                            SUPPORTED_Asym_Pause),
11762         .media_type     = ETH_PHY_BASE_T,
11763         .ver_addr       = 0,
11764         .req_flow_ctrl  = 0,
11765         .req_line_speed = 0,
11766         .speed_cap_mask = 0,
11767         .req_duplex     = 0,
11768         .rsrv           = 0,
11769         .config_init    = bnx2x_7101_config_init,
11770         .read_status    = bnx2x_7101_read_status,
11771         .link_reset     = bnx2x_common_ext_link_reset,
11772         .config_loopback = bnx2x_7101_config_loopback,
11773         .format_fw_ver  = bnx2x_7101_format_ver,
11774         .hw_reset       = bnx2x_7101_hw_reset,
11775         .set_link_led   = bnx2x_7101_set_link_led,
11776         .phy_specific_func = NULL
11777 };
11778 static const struct bnx2x_phy phy_8073 = {
11779         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
11780         .addr           = 0xff,
11781         .def_md_devad   = 0,
11782         .flags          = 0,
11783         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11784         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11785         .mdio_ctrl      = 0,
11786         .supported      = (SUPPORTED_10000baseT_Full |
11787                            SUPPORTED_2500baseX_Full |
11788                            SUPPORTED_1000baseT_Full |
11789                            SUPPORTED_FIBRE |
11790                            SUPPORTED_Autoneg |
11791                            SUPPORTED_Pause |
11792                            SUPPORTED_Asym_Pause),
11793         .media_type     = ETH_PHY_KR,
11794         .ver_addr       = 0,
11795         .req_flow_ctrl  = 0,
11796         .req_line_speed = 0,
11797         .speed_cap_mask = 0,
11798         .req_duplex     = 0,
11799         .rsrv           = 0,
11800         .config_init    = bnx2x_8073_config_init,
11801         .read_status    = bnx2x_8073_read_status,
11802         .link_reset     = bnx2x_8073_link_reset,
11803         .config_loopback = NULL,
11804         .format_fw_ver  = bnx2x_format_ver,
11805         .hw_reset       = NULL,
11806         .set_link_led   = NULL,
11807         .phy_specific_func = bnx2x_8073_specific_func
11808 };
11809 static const struct bnx2x_phy phy_8705 = {
11810         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705,
11811         .addr           = 0xff,
11812         .def_md_devad   = 0,
11813         .flags          = FLAGS_INIT_XGXS_FIRST,
11814         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11815         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11816         .mdio_ctrl      = 0,
11817         .supported      = (SUPPORTED_10000baseT_Full |
11818                            SUPPORTED_FIBRE |
11819                            SUPPORTED_Pause |
11820                            SUPPORTED_Asym_Pause),
11821         .media_type     = ETH_PHY_XFP_FIBER,
11822         .ver_addr       = 0,
11823         .req_flow_ctrl  = 0,
11824         .req_line_speed = 0,
11825         .speed_cap_mask = 0,
11826         .req_duplex     = 0,
11827         .rsrv           = 0,
11828         .config_init    = bnx2x_8705_config_init,
11829         .read_status    = bnx2x_8705_read_status,
11830         .link_reset     = bnx2x_common_ext_link_reset,
11831         .config_loopback = NULL,
11832         .format_fw_ver  = bnx2x_null_format_ver,
11833         .hw_reset       = NULL,
11834         .set_link_led   = NULL,
11835         .phy_specific_func = NULL
11836 };
11837 static const struct bnx2x_phy phy_8706 = {
11838         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706,
11839         .addr           = 0xff,
11840         .def_md_devad   = 0,
11841         .flags          = FLAGS_INIT_XGXS_FIRST,
11842         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11843         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11844         .mdio_ctrl      = 0,
11845         .supported      = (SUPPORTED_10000baseT_Full |
11846                            SUPPORTED_1000baseT_Full |
11847                            SUPPORTED_FIBRE |
11848                            SUPPORTED_Pause |
11849                            SUPPORTED_Asym_Pause),
11850         .media_type     = ETH_PHY_SFPP_10G_FIBER,
11851         .ver_addr       = 0,
11852         .req_flow_ctrl  = 0,
11853         .req_line_speed = 0,
11854         .speed_cap_mask = 0,
11855         .req_duplex     = 0,
11856         .rsrv           = 0,
11857         .config_init    = bnx2x_8706_config_init,
11858         .read_status    = bnx2x_8706_read_status,
11859         .link_reset     = bnx2x_common_ext_link_reset,
11860         .config_loopback = NULL,
11861         .format_fw_ver  = bnx2x_format_ver,
11862         .hw_reset       = NULL,
11863         .set_link_led   = NULL,
11864         .phy_specific_func = NULL
11865 };
11866
11867 static const struct bnx2x_phy phy_8726 = {
11868         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726,
11869         .addr           = 0xff,
11870         .def_md_devad   = 0,
11871         .flags          = (FLAGS_INIT_XGXS_FIRST |
11872                            FLAGS_TX_ERROR_CHECK),
11873         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11874         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11875         .mdio_ctrl      = 0,
11876         .supported      = (SUPPORTED_10000baseT_Full |
11877                            SUPPORTED_1000baseT_Full |
11878                            SUPPORTED_Autoneg |
11879                            SUPPORTED_FIBRE |
11880                            SUPPORTED_Pause |
11881                            SUPPORTED_Asym_Pause),
11882         .media_type     = ETH_PHY_NOT_PRESENT,
11883         .ver_addr       = 0,
11884         .req_flow_ctrl  = 0,
11885         .req_line_speed = 0,
11886         .speed_cap_mask = 0,
11887         .req_duplex     = 0,
11888         .rsrv           = 0,
11889         .config_init    = bnx2x_8726_config_init,
11890         .read_status    = bnx2x_8726_read_status,
11891         .link_reset     = bnx2x_8726_link_reset,
11892         .config_loopback = bnx2x_8726_config_loopback,
11893         .format_fw_ver  = bnx2x_format_ver,
11894         .hw_reset       = NULL,
11895         .set_link_led   = NULL,
11896         .phy_specific_func = NULL
11897 };
11898
11899 static const struct bnx2x_phy phy_8727 = {
11900         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
11901         .addr           = 0xff,
11902         .def_md_devad   = 0,
11903         .flags          = (FLAGS_FAN_FAILURE_DET_REQ |
11904                            FLAGS_TX_ERROR_CHECK),
11905         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11906         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11907         .mdio_ctrl      = 0,
11908         .supported      = (SUPPORTED_10000baseT_Full |
11909                            SUPPORTED_1000baseT_Full |
11910                            SUPPORTED_FIBRE |
11911                            SUPPORTED_Pause |
11912                            SUPPORTED_Asym_Pause),
11913         .media_type     = ETH_PHY_NOT_PRESENT,
11914         .ver_addr       = 0,
11915         .req_flow_ctrl  = 0,
11916         .req_line_speed = 0,
11917         .speed_cap_mask = 0,
11918         .req_duplex     = 0,
11919         .rsrv           = 0,
11920         .config_init    = bnx2x_8727_config_init,
11921         .read_status    = bnx2x_8727_read_status,
11922         .link_reset     = bnx2x_8727_link_reset,
11923         .config_loopback = NULL,
11924         .format_fw_ver  = bnx2x_format_ver,
11925         .hw_reset       = bnx2x_8727_hw_reset,
11926         .set_link_led   = bnx2x_8727_set_link_led,
11927         .phy_specific_func = bnx2x_8727_specific_func
11928 };
11929 static const struct bnx2x_phy phy_8481 = {
11930         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
11931         .addr           = 0xff,
11932         .def_md_devad   = 0,
11933         .flags          = FLAGS_FAN_FAILURE_DET_REQ |
11934                           FLAGS_REARM_LATCH_SIGNAL,
11935         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11936         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11937         .mdio_ctrl      = 0,
11938         .supported      = (SUPPORTED_10baseT_Half |
11939                            SUPPORTED_10baseT_Full |
11940                            SUPPORTED_100baseT_Half |
11941                            SUPPORTED_100baseT_Full |
11942                            SUPPORTED_1000baseT_Full |
11943                            SUPPORTED_10000baseT_Full |
11944                            SUPPORTED_TP |
11945                            SUPPORTED_Autoneg |
11946                            SUPPORTED_Pause |
11947                            SUPPORTED_Asym_Pause),
11948         .media_type     = ETH_PHY_BASE_T,
11949         .ver_addr       = 0,
11950         .req_flow_ctrl  = 0,
11951         .req_line_speed = 0,
11952         .speed_cap_mask = 0,
11953         .req_duplex     = 0,
11954         .rsrv           = 0,
11955         .config_init    = bnx2x_8481_config_init,
11956         .read_status    = bnx2x_848xx_read_status,
11957         .link_reset     = bnx2x_8481_link_reset,
11958         .config_loopback = NULL,
11959         .format_fw_ver  = bnx2x_848xx_format_ver,
11960         .hw_reset       = bnx2x_8481_hw_reset,
11961         .set_link_led   = bnx2x_848xx_set_link_led,
11962         .phy_specific_func = NULL
11963 };
11964
11965 static const struct bnx2x_phy phy_84823 = {
11966         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823,
11967         .addr           = 0xff,
11968         .def_md_devad   = 0,
11969         .flags          = (FLAGS_FAN_FAILURE_DET_REQ |
11970                            FLAGS_REARM_LATCH_SIGNAL |
11971                            FLAGS_TX_ERROR_CHECK),
11972         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11973         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11974         .mdio_ctrl      = 0,
11975         .supported      = (SUPPORTED_10baseT_Half |
11976                            SUPPORTED_10baseT_Full |
11977                            SUPPORTED_100baseT_Half |
11978                            SUPPORTED_100baseT_Full |
11979                            SUPPORTED_1000baseT_Full |
11980                            SUPPORTED_10000baseT_Full |
11981                            SUPPORTED_TP |
11982                            SUPPORTED_Autoneg |
11983                            SUPPORTED_Pause |
11984                            SUPPORTED_Asym_Pause),
11985         .media_type     = ETH_PHY_BASE_T,
11986         .ver_addr       = 0,
11987         .req_flow_ctrl  = 0,
11988         .req_line_speed = 0,
11989         .speed_cap_mask = 0,
11990         .req_duplex     = 0,
11991         .rsrv           = 0,
11992         .config_init    = bnx2x_848x3_config_init,
11993         .read_status    = bnx2x_848xx_read_status,
11994         .link_reset     = bnx2x_848x3_link_reset,
11995         .config_loopback = NULL,
11996         .format_fw_ver  = bnx2x_848xx_format_ver,
11997         .hw_reset       = NULL,
11998         .set_link_led   = bnx2x_848xx_set_link_led,
11999         .phy_specific_func = bnx2x_848xx_specific_func
12000 };
12001
12002 static const struct bnx2x_phy phy_84833 = {
12003         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833,
12004         .addr           = 0xff,
12005         .def_md_devad   = 0,
12006         .flags          = (FLAGS_FAN_FAILURE_DET_REQ |
12007                            FLAGS_REARM_LATCH_SIGNAL |
12008                            FLAGS_TX_ERROR_CHECK),
12009         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
12010         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
12011         .mdio_ctrl      = 0,
12012         .supported      = (SUPPORTED_100baseT_Half |
12013                            SUPPORTED_100baseT_Full |
12014                            SUPPORTED_1000baseT_Full |
12015                            SUPPORTED_10000baseT_Full |
12016                            SUPPORTED_TP |
12017                            SUPPORTED_Autoneg |
12018                            SUPPORTED_Pause |
12019                            SUPPORTED_Asym_Pause),
12020         .media_type     = ETH_PHY_BASE_T,
12021         .ver_addr       = 0,
12022         .req_flow_ctrl  = 0,
12023         .req_line_speed = 0,
12024         .speed_cap_mask = 0,
12025         .req_duplex     = 0,
12026         .rsrv           = 0,
12027         .config_init    = bnx2x_848x3_config_init,
12028         .read_status    = bnx2x_848xx_read_status,
12029         .link_reset     = bnx2x_848x3_link_reset,
12030         .config_loopback = NULL,
12031         .format_fw_ver  = bnx2x_848xx_format_ver,
12032         .hw_reset       = bnx2x_84833_hw_reset_phy,
12033         .set_link_led   = bnx2x_848xx_set_link_led,
12034         .phy_specific_func = bnx2x_848xx_specific_func
12035 };
12036
12037 static const struct bnx2x_phy phy_84834 = {
12038         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834,
12039         .addr           = 0xff,
12040         .def_md_devad   = 0,
12041         .flags          = FLAGS_FAN_FAILURE_DET_REQ |
12042                             FLAGS_REARM_LATCH_SIGNAL,
12043         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
12044         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
12045         .mdio_ctrl      = 0,
12046         .supported      = (SUPPORTED_100baseT_Half |
12047                            SUPPORTED_100baseT_Full |
12048                            SUPPORTED_1000baseT_Full |
12049                            SUPPORTED_10000baseT_Full |
12050                            SUPPORTED_TP |
12051                            SUPPORTED_Autoneg |
12052                            SUPPORTED_Pause |
12053                            SUPPORTED_Asym_Pause),
12054         .media_type     = ETH_PHY_BASE_T,
12055         .ver_addr       = 0,
12056         .req_flow_ctrl  = 0,
12057         .req_line_speed = 0,
12058         .speed_cap_mask = 0,
12059         .req_duplex     = 0,
12060         .rsrv           = 0,
12061         .config_init    = bnx2x_848x3_config_init,
12062         .read_status    = bnx2x_848xx_read_status,
12063         .link_reset     = bnx2x_848x3_link_reset,
12064         .config_loopback = NULL,
12065         .format_fw_ver  = bnx2x_848xx_format_ver,
12066         .hw_reset       = bnx2x_84833_hw_reset_phy,
12067         .set_link_led   = bnx2x_848xx_set_link_led,
12068         .phy_specific_func = bnx2x_848xx_specific_func
12069 };
12070
12071 static const struct bnx2x_phy phy_84858 = {
12072         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84858,
12073         .addr           = 0xff,
12074         .def_md_devad   = 0,
12075         .flags          = FLAGS_FAN_FAILURE_DET_REQ |
12076                             FLAGS_REARM_LATCH_SIGNAL,
12077         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
12078         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
12079         .mdio_ctrl      = 0,
12080         .supported      = (SUPPORTED_100baseT_Half |
12081                            SUPPORTED_100baseT_Full |
12082                            SUPPORTED_1000baseT_Full |
12083                            SUPPORTED_10000baseT_Full |
12084                            SUPPORTED_TP |
12085                            SUPPORTED_Autoneg |
12086                            SUPPORTED_Pause |
12087                            SUPPORTED_Asym_Pause),
12088         .media_type     = ETH_PHY_BASE_T,
12089         .ver_addr       = 0,
12090         .req_flow_ctrl  = 0,
12091         .req_line_speed = 0,
12092         .speed_cap_mask = 0,
12093         .req_duplex     = 0,
12094         .rsrv           = 0,
12095         .config_init    = bnx2x_848x3_config_init,
12096         .read_status    = bnx2x_848xx_read_status,
12097         .link_reset     = bnx2x_848x3_link_reset,
12098         .config_loopback = NULL,
12099         .format_fw_ver  = bnx2x_8485x_format_ver,
12100         .hw_reset       = bnx2x_84833_hw_reset_phy,
12101         .set_link_led   = bnx2x_848xx_set_link_led,
12102         .phy_specific_func = bnx2x_848xx_specific_func
12103 };
12104
12105 static const struct bnx2x_phy phy_54618se = {
12106         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE,
12107         .addr           = 0xff,
12108         .def_md_devad   = 0,
12109         .flags          = FLAGS_INIT_XGXS_FIRST,
12110         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
12111         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
12112         .mdio_ctrl      = 0,
12113         .supported      = (SUPPORTED_10baseT_Half |
12114                            SUPPORTED_10baseT_Full |
12115                            SUPPORTED_100baseT_Half |
12116                            SUPPORTED_100baseT_Full |
12117                            SUPPORTED_1000baseT_Full |
12118                            SUPPORTED_TP |
12119                            SUPPORTED_Autoneg |
12120                            SUPPORTED_Pause |
12121                            SUPPORTED_Asym_Pause),
12122         .media_type     = ETH_PHY_BASE_T,
12123         .ver_addr       = 0,
12124         .req_flow_ctrl  = 0,
12125         .req_line_speed = 0,
12126         .speed_cap_mask = 0,
12127         /* req_duplex = */0,
12128         /* rsrv = */0,
12129         .config_init    = bnx2x_54618se_config_init,
12130         .read_status    = bnx2x_54618se_read_status,
12131         .link_reset     = bnx2x_54618se_link_reset,
12132         .config_loopback = bnx2x_54618se_config_loopback,
12133         .format_fw_ver  = NULL,
12134         .hw_reset       = NULL,
12135         .set_link_led   = bnx2x_5461x_set_link_led,
12136         .phy_specific_func = bnx2x_54618se_specific_func
12137 };
12138 /*****************************************************************/
12139 /*                                                               */
12140 /* Populate the phy according. Main function: bnx2x_populate_phy   */
12141 /*                                                               */
12142 /*****************************************************************/
12143
12144 static void bnx2x_populate_preemphasis(struct bnx2x *bp, u32 shmem_base,
12145                                      struct bnx2x_phy *phy, u8 port,
12146                                      u8 phy_index)
12147 {
12148         /* Get the 4 lanes xgxs config rx and tx */
12149         u32 rx = 0, tx = 0, i;
12150         for (i = 0; i < 2; i++) {
12151                 /* INT_PHY and EXT_PHY1 share the same value location in
12152                  * the shmem. When num_phys is greater than 1, than this value
12153                  * applies only to EXT_PHY1
12154                  */
12155                 if (phy_index == INT_PHY || phy_index == EXT_PHY1) {
12156                         rx = REG_RD(bp, shmem_base +
12157                                     offsetof(struct shmem_region,
12158                           dev_info.port_hw_config[port].xgxs_config_rx[i<<1]));
12159
12160                         tx = REG_RD(bp, shmem_base +
12161                                     offsetof(struct shmem_region,
12162                           dev_info.port_hw_config[port].xgxs_config_tx[i<<1]));
12163                 } else {
12164                         rx = REG_RD(bp, shmem_base +
12165                                     offsetof(struct shmem_region,
12166                          dev_info.port_hw_config[port].xgxs_config2_rx[i<<1]));
12167
12168                         tx = REG_RD(bp, shmem_base +
12169                                     offsetof(struct shmem_region,
12170                          dev_info.port_hw_config[port].xgxs_config2_rx[i<<1]));
12171                 }
12172
12173                 phy->rx_preemphasis[i << 1] = ((rx>>16) & 0xffff);
12174                 phy->rx_preemphasis[(i << 1) + 1] = (rx & 0xffff);
12175
12176                 phy->tx_preemphasis[i << 1] = ((tx>>16) & 0xffff);
12177                 phy->tx_preemphasis[(i << 1) + 1] = (tx & 0xffff);
12178         }
12179 }
12180
12181 static u32 bnx2x_get_ext_phy_config(struct bnx2x *bp, u32 shmem_base,
12182                                     u8 phy_index, u8 port)
12183 {
12184         u32 ext_phy_config = 0;
12185         switch (phy_index) {
12186         case EXT_PHY1:
12187                 ext_phy_config = REG_RD(bp, shmem_base +
12188                                               offsetof(struct shmem_region,
12189                         dev_info.port_hw_config[port].external_phy_config));
12190                 break;
12191         case EXT_PHY2:
12192                 ext_phy_config = REG_RD(bp, shmem_base +
12193                                               offsetof(struct shmem_region,
12194                         dev_info.port_hw_config[port].external_phy_config2));
12195                 break;
12196         default:
12197                 DP(NETIF_MSG_LINK, "Invalid phy_index %d\n", phy_index);
12198                 return -EINVAL;
12199         }
12200
12201         return ext_phy_config;
12202 }
12203 static int bnx2x_populate_int_phy(struct bnx2x *bp, u32 shmem_base, u8 port,
12204                                   struct bnx2x_phy *phy)
12205 {
12206         u32 phy_addr;
12207         u32 chip_id;
12208         u32 switch_cfg = (REG_RD(bp, shmem_base +
12209                                        offsetof(struct shmem_region,
12210                         dev_info.port_feature_config[port].link_config)) &
12211                           PORT_FEATURE_CONNECTED_SWITCH_MASK);
12212         chip_id = (REG_RD(bp, MISC_REG_CHIP_NUM) << 16) |
12213                 ((REG_RD(bp, MISC_REG_CHIP_REV) & 0xf) << 12);
12214
12215         DP(NETIF_MSG_LINK, ":chip_id = 0x%x\n", chip_id);
12216         if (USES_WARPCORE(bp)) {
12217                 u32 serdes_net_if;
12218                 phy_addr = REG_RD(bp,
12219                                   MISC_REG_WC0_CTRL_PHY_ADDR);
12220                 *phy = phy_warpcore;
12221                 if (REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR) == 0x3)
12222                         phy->flags |= FLAGS_4_PORT_MODE;
12223                 else
12224                         phy->flags &= ~FLAGS_4_PORT_MODE;
12225                         /* Check Dual mode */
12226                 serdes_net_if = (REG_RD(bp, shmem_base +
12227                                         offsetof(struct shmem_region, dev_info.
12228                                         port_hw_config[port].default_cfg)) &
12229                                  PORT_HW_CFG_NET_SERDES_IF_MASK);
12230                 /* Set the appropriate supported and flags indications per
12231                  * interface type of the chip
12232                  */
12233                 switch (serdes_net_if) {
12234                 case PORT_HW_CFG_NET_SERDES_IF_SGMII:
12235                         phy->supported &= (SUPPORTED_10baseT_Half |
12236                                            SUPPORTED_10baseT_Full |
12237                                            SUPPORTED_100baseT_Half |
12238                                            SUPPORTED_100baseT_Full |
12239                                            SUPPORTED_1000baseT_Full |
12240                                            SUPPORTED_FIBRE |
12241                                            SUPPORTED_Autoneg |
12242                                            SUPPORTED_Pause |
12243                                            SUPPORTED_Asym_Pause);
12244                         phy->media_type = ETH_PHY_BASE_T;
12245                         break;
12246                 case PORT_HW_CFG_NET_SERDES_IF_XFI:
12247                         phy->supported &= (SUPPORTED_1000baseT_Full |
12248                                            SUPPORTED_10000baseT_Full |
12249                                            SUPPORTED_FIBRE |
12250                                            SUPPORTED_Pause |
12251                                            SUPPORTED_Asym_Pause);
12252                         phy->media_type = ETH_PHY_XFP_FIBER;
12253                         break;
12254                 case PORT_HW_CFG_NET_SERDES_IF_SFI:
12255                         phy->supported &= (SUPPORTED_1000baseT_Full |
12256                                            SUPPORTED_10000baseT_Full |
12257                                            SUPPORTED_FIBRE |
12258                                            SUPPORTED_Pause |
12259                                            SUPPORTED_Asym_Pause);
12260                         phy->media_type = ETH_PHY_SFPP_10G_FIBER;
12261                         break;
12262                 case PORT_HW_CFG_NET_SERDES_IF_KR:
12263                         phy->media_type = ETH_PHY_KR;
12264                         phy->supported &= (SUPPORTED_1000baseKX_Full |
12265                                            SUPPORTED_10000baseKR_Full |
12266                                            SUPPORTED_FIBRE |
12267                                            SUPPORTED_Autoneg |
12268                                            SUPPORTED_Pause |
12269                                            SUPPORTED_Asym_Pause);
12270                         break;
12271                 case PORT_HW_CFG_NET_SERDES_IF_DXGXS:
12272                         phy->media_type = ETH_PHY_KR;
12273                         phy->flags |= FLAGS_WC_DUAL_MODE;
12274                         phy->supported &= (SUPPORTED_20000baseMLD2_Full |
12275                                            SUPPORTED_FIBRE |
12276                                            SUPPORTED_Pause |
12277                                            SUPPORTED_Asym_Pause);
12278                         break;
12279                 case PORT_HW_CFG_NET_SERDES_IF_KR2:
12280                         phy->media_type = ETH_PHY_KR;
12281                         phy->flags |= FLAGS_WC_DUAL_MODE;
12282                         phy->supported &= (SUPPORTED_20000baseKR2_Full |
12283                                            SUPPORTED_10000baseKR_Full |
12284                                            SUPPORTED_1000baseKX_Full |
12285                                            SUPPORTED_Autoneg |
12286                                            SUPPORTED_FIBRE |
12287                                            SUPPORTED_Pause |
12288                                            SUPPORTED_Asym_Pause);
12289                         phy->flags &= ~FLAGS_TX_ERROR_CHECK;
12290                         break;
12291                 default:
12292                         DP(NETIF_MSG_LINK, "Unknown WC interface type 0x%x\n",
12293                                        serdes_net_if);
12294                         break;
12295                 }
12296
12297                 /* Enable MDC/MDIO work-around for E3 A0 since free running MDC
12298                  * was not set as expected. For B0, ECO will be enabled so there
12299                  * won't be an issue there
12300                  */
12301                 if (CHIP_REV(bp) == CHIP_REV_Ax)
12302                         phy->flags |= FLAGS_MDC_MDIO_WA;
12303                 else
12304                         phy->flags |= FLAGS_MDC_MDIO_WA_B0;
12305         } else {
12306                 switch (switch_cfg) {
12307                 case SWITCH_CFG_1G:
12308                         phy_addr = REG_RD(bp,
12309                                           NIG_REG_SERDES0_CTRL_PHY_ADDR +
12310                                           port * 0x10);
12311                         *phy = phy_serdes;
12312                         break;
12313                 case SWITCH_CFG_10G:
12314                         phy_addr = REG_RD(bp,
12315                                           NIG_REG_XGXS0_CTRL_PHY_ADDR +
12316                                           port * 0x18);
12317                         *phy = phy_xgxs;
12318                         break;
12319                 default:
12320                         DP(NETIF_MSG_LINK, "Invalid switch_cfg\n");
12321                         return -EINVAL;
12322                 }
12323         }
12324         phy->addr = (u8)phy_addr;
12325         phy->mdio_ctrl = bnx2x_get_emac_base(bp,
12326                                             SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH,
12327                                             port);
12328         if (CHIP_IS_E2(bp))
12329                 phy->def_md_devad = E2_DEFAULT_PHY_DEV_ADDR;
12330         else
12331                 phy->def_md_devad = DEFAULT_PHY_DEV_ADDR;
12332
12333         DP(NETIF_MSG_LINK, "Internal phy port=%d, addr=0x%x, mdio_ctl=0x%x\n",
12334                    port, phy->addr, phy->mdio_ctrl);
12335
12336         bnx2x_populate_preemphasis(bp, shmem_base, phy, port, INT_PHY);
12337         return 0;
12338 }
12339
12340 static int bnx2x_populate_ext_phy(struct bnx2x *bp,
12341                                   u8 phy_index,
12342                                   u32 shmem_base,
12343                                   u32 shmem2_base,
12344                                   u8 port,
12345                                   struct bnx2x_phy *phy)
12346 {
12347         u32 ext_phy_config, phy_type, config2;
12348         u32 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH;
12349         ext_phy_config = bnx2x_get_ext_phy_config(bp, shmem_base,
12350                                                   phy_index, port);
12351         phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
12352         /* Select the phy type */
12353         switch (phy_type) {
12354         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
12355                 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED;
12356                 *phy = phy_8073;
12357                 break;
12358         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705:
12359                 *phy = phy_8705;
12360                 break;
12361         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706:
12362                 *phy = phy_8706;
12363                 break;
12364         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
12365                 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1;
12366                 *phy = phy_8726;
12367                 break;
12368         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC:
12369                 /* BCM8727_NOC => BCM8727 no over current */
12370                 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1;
12371                 *phy = phy_8727;
12372                 phy->flags |= FLAGS_NOC;
12373                 break;
12374         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
12375         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
12376                 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1;
12377                 *phy = phy_8727;
12378                 break;
12379         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481:
12380                 *phy = phy_8481;
12381                 break;
12382         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823:
12383                 *phy = phy_84823;
12384                 break;
12385         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833:
12386                 *phy = phy_84833;
12387                 break;
12388         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834:
12389                 *phy = phy_84834;
12390                 break;
12391         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84858:
12392                 *phy = phy_84858;
12393                 break;
12394         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54616:
12395         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE:
12396                 *phy = phy_54618se;
12397                 if (phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE)
12398                         phy->flags |= FLAGS_EEE;
12399                 break;
12400         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101:
12401                 *phy = phy_7101;
12402                 break;
12403         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:
12404                 *phy = phy_null;
12405                 return -EINVAL;
12406         default:
12407                 *phy = phy_null;
12408                 /* In case external PHY wasn't found */
12409                 if ((phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) &&
12410                     (phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN))
12411                         return -EINVAL;
12412                 return 0;
12413         }
12414
12415         phy->addr = XGXS_EXT_PHY_ADDR(ext_phy_config);
12416         bnx2x_populate_preemphasis(bp, shmem_base, phy, port, phy_index);
12417
12418         /* The shmem address of the phy version is located on different
12419          * structures. In case this structure is too old, do not set
12420          * the address
12421          */
12422         config2 = REG_RD(bp, shmem_base + offsetof(struct shmem_region,
12423                                         dev_info.shared_hw_config.config2));
12424         if (phy_index == EXT_PHY1) {
12425                 phy->ver_addr = shmem_base + offsetof(struct shmem_region,
12426                                 port_mb[port].ext_phy_fw_version);
12427
12428                 /* Check specific mdc mdio settings */
12429                 if (config2 & SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK)
12430                         mdc_mdio_access = config2 &
12431                         SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK;
12432         } else {
12433                 u32 size = REG_RD(bp, shmem2_base);
12434
12435                 if (size >
12436                     offsetof(struct shmem2_region, ext_phy_fw_version2)) {
12437                         phy->ver_addr = shmem2_base +
12438                             offsetof(struct shmem2_region,
12439                                      ext_phy_fw_version2[port]);
12440                 }
12441                 /* Check specific mdc mdio settings */
12442                 if (config2 & SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK)
12443                         mdc_mdio_access = (config2 &
12444                         SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK) >>
12445                         (SHARED_HW_CFG_MDC_MDIO_ACCESS2_SHIFT -
12446                          SHARED_HW_CFG_MDC_MDIO_ACCESS1_SHIFT);
12447         }
12448         phy->mdio_ctrl = bnx2x_get_emac_base(bp, mdc_mdio_access, port);
12449
12450         if (bnx2x_is_8483x_8485x(phy) && (phy->ver_addr)) {
12451                 /* Remove 100Mb link supported for BCM84833/4 when phy fw
12452                  * version lower than or equal to 1.39
12453                  */
12454                 u32 raw_ver = REG_RD(bp, phy->ver_addr);
12455                 if (((raw_ver & 0x7F) <= 39) &&
12456                     (((raw_ver & 0xF80) >> 7) <= 1))
12457                         phy->supported &= ~(SUPPORTED_100baseT_Half |
12458                                             SUPPORTED_100baseT_Full);
12459         }
12460
12461         DP(NETIF_MSG_LINK, "phy_type 0x%x port %d found in index %d\n",
12462                    phy_type, port, phy_index);
12463         DP(NETIF_MSG_LINK, "             addr=0x%x, mdio_ctl=0x%x\n",
12464                    phy->addr, phy->mdio_ctrl);
12465         return 0;
12466 }
12467
12468 static int bnx2x_populate_phy(struct bnx2x *bp, u8 phy_index, u32 shmem_base,
12469                               u32 shmem2_base, u8 port, struct bnx2x_phy *phy)
12470 {
12471         phy->type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN;
12472         if (phy_index == INT_PHY)
12473                 return bnx2x_populate_int_phy(bp, shmem_base, port, phy);
12474
12475         return bnx2x_populate_ext_phy(bp, phy_index, shmem_base, shmem2_base,
12476                                         port, phy);
12477 }
12478
12479 static void bnx2x_phy_def_cfg(struct link_params *params,
12480                               struct bnx2x_phy *phy,
12481                               u8 phy_index)
12482 {
12483         struct bnx2x *bp = params->bp;
12484         u32 link_config;
12485         /* Populate the default phy configuration for MF mode */
12486         if (phy_index == EXT_PHY2) {
12487                 link_config = REG_RD(bp, params->shmem_base +
12488                                      offsetof(struct shmem_region, dev_info.
12489                         port_feature_config[params->port].link_config2));
12490                 phy->speed_cap_mask = REG_RD(bp, params->shmem_base +
12491                                              offsetof(struct shmem_region,
12492                                                       dev_info.
12493                         port_hw_config[params->port].speed_capability_mask2));
12494         } else {
12495                 link_config = REG_RD(bp, params->shmem_base +
12496                                      offsetof(struct shmem_region, dev_info.
12497                                 port_feature_config[params->port].link_config));
12498                 phy->speed_cap_mask = REG_RD(bp, params->shmem_base +
12499                                              offsetof(struct shmem_region,
12500                                                       dev_info.
12501                         port_hw_config[params->port].speed_capability_mask));
12502         }
12503         DP(NETIF_MSG_LINK,
12504            "Default config phy idx %x cfg 0x%x speed_cap_mask 0x%x\n",
12505            phy_index, link_config, phy->speed_cap_mask);
12506
12507         phy->req_duplex = DUPLEX_FULL;
12508         switch (link_config  & PORT_FEATURE_LINK_SPEED_MASK) {
12509         case PORT_FEATURE_LINK_SPEED_10M_HALF:
12510                 phy->req_duplex = DUPLEX_HALF;
12511                 fallthrough;
12512         case PORT_FEATURE_LINK_SPEED_10M_FULL:
12513                 phy->req_line_speed = SPEED_10;
12514                 break;
12515         case PORT_FEATURE_LINK_SPEED_100M_HALF:
12516                 phy->req_duplex = DUPLEX_HALF;
12517                 fallthrough;
12518         case PORT_FEATURE_LINK_SPEED_100M_FULL:
12519                 phy->req_line_speed = SPEED_100;
12520                 break;
12521         case PORT_FEATURE_LINK_SPEED_1G:
12522                 phy->req_line_speed = SPEED_1000;
12523                 break;
12524         case PORT_FEATURE_LINK_SPEED_2_5G:
12525                 phy->req_line_speed = SPEED_2500;
12526                 break;
12527         case PORT_FEATURE_LINK_SPEED_10G_CX4:
12528                 phy->req_line_speed = SPEED_10000;
12529                 break;
12530         default:
12531                 phy->req_line_speed = SPEED_AUTO_NEG;
12532                 break;
12533         }
12534
12535         switch (link_config  & PORT_FEATURE_FLOW_CONTROL_MASK) {
12536         case PORT_FEATURE_FLOW_CONTROL_AUTO:
12537                 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_AUTO;
12538                 break;
12539         case PORT_FEATURE_FLOW_CONTROL_TX:
12540                 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_TX;
12541                 break;
12542         case PORT_FEATURE_FLOW_CONTROL_RX:
12543                 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_RX;
12544                 break;
12545         case PORT_FEATURE_FLOW_CONTROL_BOTH:
12546                 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_BOTH;
12547                 break;
12548         default:
12549                 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_NONE;
12550                 break;
12551         }
12552 }
12553
12554 u32 bnx2x_phy_selection(struct link_params *params)
12555 {
12556         u32 phy_config_swapped, prio_cfg;
12557         u32 return_cfg = PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT;
12558
12559         phy_config_swapped = params->multi_phy_config &
12560                 PORT_HW_CFG_PHY_SWAPPED_ENABLED;
12561
12562         prio_cfg = params->multi_phy_config &
12563                         PORT_HW_CFG_PHY_SELECTION_MASK;
12564
12565         if (phy_config_swapped) {
12566                 switch (prio_cfg) {
12567                 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
12568                      return_cfg = PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY;
12569                      break;
12570                 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
12571                      return_cfg = PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY;
12572                      break;
12573                 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY:
12574                      return_cfg = PORT_HW_CFG_PHY_SELECTION_FIRST_PHY;
12575                      break;
12576                 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY:
12577                      return_cfg = PORT_HW_CFG_PHY_SELECTION_SECOND_PHY;
12578                      break;
12579                 }
12580         } else
12581                 return_cfg = prio_cfg;
12582
12583         return return_cfg;
12584 }
12585
12586 int bnx2x_phy_probe(struct link_params *params)
12587 {
12588         u8 phy_index, actual_phy_idx;
12589         u32 phy_config_swapped, sync_offset, media_types;
12590         struct bnx2x *bp = params->bp;
12591         struct bnx2x_phy *phy;
12592         params->num_phys = 0;
12593         DP(NETIF_MSG_LINK, "Begin phy probe\n");
12594         phy_config_swapped = params->multi_phy_config &
12595                 PORT_HW_CFG_PHY_SWAPPED_ENABLED;
12596
12597         for (phy_index = INT_PHY; phy_index < MAX_PHYS;
12598               phy_index++) {
12599                 actual_phy_idx = phy_index;
12600                 if (phy_config_swapped) {
12601                         if (phy_index == EXT_PHY1)
12602                                 actual_phy_idx = EXT_PHY2;
12603                         else if (phy_index == EXT_PHY2)
12604                                 actual_phy_idx = EXT_PHY1;
12605                 }
12606                 DP(NETIF_MSG_LINK, "phy_config_swapped %x, phy_index %x,"
12607                                " actual_phy_idx %x\n", phy_config_swapped,
12608                            phy_index, actual_phy_idx);
12609                 phy = &params->phy[actual_phy_idx];
12610                 if (bnx2x_populate_phy(bp, phy_index, params->shmem_base,
12611                                        params->shmem2_base, params->port,
12612                                        phy) != 0) {
12613                         params->num_phys = 0;
12614                         DP(NETIF_MSG_LINK, "phy probe failed in phy index %d\n",
12615                                    phy_index);
12616                         for (phy_index = INT_PHY;
12617                               phy_index < MAX_PHYS;
12618                               phy_index++)
12619                                 *phy = phy_null;
12620                         return -EINVAL;
12621                 }
12622                 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN)
12623                         break;
12624
12625                 if (params->feature_config_flags &
12626                     FEATURE_CONFIG_DISABLE_REMOTE_FAULT_DET)
12627                         phy->flags &= ~FLAGS_TX_ERROR_CHECK;
12628
12629                 if (!(params->feature_config_flags &
12630                       FEATURE_CONFIG_MT_SUPPORT))
12631                         phy->flags |= FLAGS_MDC_MDIO_WA_G;
12632
12633                 sync_offset = params->shmem_base +
12634                         offsetof(struct shmem_region,
12635                         dev_info.port_hw_config[params->port].media_type);
12636                 media_types = REG_RD(bp, sync_offset);
12637
12638                 /* Update media type for non-PMF sync only for the first time
12639                  * In case the media type changes afterwards, it will be updated
12640                  * using the update_status function
12641                  */
12642                 if ((media_types & (PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK <<
12643                                     (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT *
12644                                      actual_phy_idx))) == 0) {
12645                         media_types |= ((phy->media_type &
12646                                         PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) <<
12647                                 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT *
12648                                  actual_phy_idx));
12649                 }
12650                 REG_WR(bp, sync_offset, media_types);
12651
12652                 bnx2x_phy_def_cfg(params, phy, phy_index);
12653                 params->num_phys++;
12654         }
12655
12656         DP(NETIF_MSG_LINK, "End phy probe. #phys found %x\n", params->num_phys);
12657         return 0;
12658 }
12659
12660 static void bnx2x_init_bmac_loopback(struct link_params *params,
12661                                      struct link_vars *vars)
12662 {
12663         struct bnx2x *bp = params->bp;
12664         vars->link_up = 1;
12665         vars->line_speed = SPEED_10000;
12666         vars->duplex = DUPLEX_FULL;
12667         vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
12668         vars->mac_type = MAC_TYPE_BMAC;
12669
12670         vars->phy_flags = PHY_XGXS_FLAG;
12671
12672         bnx2x_xgxs_deassert(params);
12673
12674         /* Set bmac loopback */
12675         bnx2x_bmac_enable(params, vars, 1, 1);
12676
12677         REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port * 4, 0);
12678 }
12679
12680 static void bnx2x_init_emac_loopback(struct link_params *params,
12681                                      struct link_vars *vars)
12682 {
12683         struct bnx2x *bp = params->bp;
12684         vars->link_up = 1;
12685         vars->line_speed = SPEED_1000;
12686         vars->duplex = DUPLEX_FULL;
12687         vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
12688         vars->mac_type = MAC_TYPE_EMAC;
12689
12690         vars->phy_flags = PHY_XGXS_FLAG;
12691
12692         bnx2x_xgxs_deassert(params);
12693         /* Set bmac loopback */
12694         bnx2x_emac_enable(params, vars, 1);
12695         bnx2x_emac_program(params, vars);
12696         REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port * 4, 0);
12697 }
12698
12699 static void bnx2x_init_xmac_loopback(struct link_params *params,
12700                                      struct link_vars *vars)
12701 {
12702         struct bnx2x *bp = params->bp;
12703         vars->link_up = 1;
12704         if (!params->req_line_speed[0])
12705                 vars->line_speed = SPEED_10000;
12706         else
12707                 vars->line_speed = params->req_line_speed[0];
12708         vars->duplex = DUPLEX_FULL;
12709         vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
12710         vars->mac_type = MAC_TYPE_XMAC;
12711         vars->phy_flags = PHY_XGXS_FLAG;
12712         /* Set WC to loopback mode since link is required to provide clock
12713          * to the XMAC in 20G mode
12714          */
12715         bnx2x_set_aer_mmd(params, &params->phy[0]);
12716         bnx2x_warpcore_reset_lane(bp, &params->phy[0], 0);
12717         params->phy[INT_PHY].config_loopback(
12718                         &params->phy[INT_PHY],
12719                         params);
12720
12721         bnx2x_xmac_enable(params, vars, 1);
12722         REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
12723 }
12724
12725 static void bnx2x_init_umac_loopback(struct link_params *params,
12726                                      struct link_vars *vars)
12727 {
12728         struct bnx2x *bp = params->bp;
12729         vars->link_up = 1;
12730         vars->line_speed = SPEED_1000;
12731         vars->duplex = DUPLEX_FULL;
12732         vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
12733         vars->mac_type = MAC_TYPE_UMAC;
12734         vars->phy_flags = PHY_XGXS_FLAG;
12735         bnx2x_umac_enable(params, vars, 1);
12736
12737         REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
12738 }
12739
12740 static void bnx2x_init_xgxs_loopback(struct link_params *params,
12741                                      struct link_vars *vars)
12742 {
12743         struct bnx2x *bp = params->bp;
12744         struct bnx2x_phy *int_phy = &params->phy[INT_PHY];
12745         vars->link_up = 1;
12746         vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
12747         vars->duplex = DUPLEX_FULL;
12748         if (params->req_line_speed[0] == SPEED_1000)
12749                 vars->line_speed = SPEED_1000;
12750         else if ((params->req_line_speed[0] == SPEED_20000) ||
12751                  (int_phy->flags & FLAGS_WC_DUAL_MODE))
12752                 vars->line_speed = SPEED_20000;
12753         else
12754                 vars->line_speed = SPEED_10000;
12755
12756         if (!USES_WARPCORE(bp))
12757                 bnx2x_xgxs_deassert(params);
12758         bnx2x_link_initialize(params, vars);
12759
12760         if (params->req_line_speed[0] == SPEED_1000) {
12761                 if (USES_WARPCORE(bp))
12762                         bnx2x_umac_enable(params, vars, 0);
12763                 else {
12764                         bnx2x_emac_program(params, vars);
12765                         bnx2x_emac_enable(params, vars, 0);
12766                 }
12767         } else {
12768                 if (USES_WARPCORE(bp))
12769                         bnx2x_xmac_enable(params, vars, 0);
12770                 else
12771                         bnx2x_bmac_enable(params, vars, 0, 1);
12772         }
12773
12774         if (params->loopback_mode == LOOPBACK_XGXS) {
12775                 /* Set 10G XGXS loopback */
12776                 int_phy->config_loopback(int_phy, params);
12777         } else {
12778                 /* Set external phy loopback */
12779                 u8 phy_index;
12780                 for (phy_index = EXT_PHY1;
12781                       phy_index < params->num_phys; phy_index++)
12782                         if (params->phy[phy_index].config_loopback)
12783                                 params->phy[phy_index].config_loopback(
12784                                         &params->phy[phy_index],
12785                                         params);
12786         }
12787         REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
12788
12789         bnx2x_set_led(params, vars, LED_MODE_OPER, vars->line_speed);
12790 }
12791
12792 void bnx2x_set_rx_filter(struct link_params *params, u8 en)
12793 {
12794         struct bnx2x *bp = params->bp;
12795         u8 val = en * 0x1F;
12796
12797         /* Open / close the gate between the NIG and the BRB */
12798         if (!CHIP_IS_E1x(bp))
12799                 val |= en * 0x20;
12800         REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK + params->port*4, val);
12801
12802         if (!CHIP_IS_E1(bp)) {
12803                 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK_MF + params->port*4,
12804                        en*0x3);
12805         }
12806
12807         REG_WR(bp, (params->port ? NIG_REG_LLH1_BRB1_NOT_MCP :
12808                     NIG_REG_LLH0_BRB1_NOT_MCP), en);
12809 }
12810 static int bnx2x_avoid_link_flap(struct link_params *params,
12811                                             struct link_vars *vars)
12812 {
12813         u32 phy_idx;
12814         u32 dont_clear_stat, lfa_sts;
12815         struct bnx2x *bp = params->bp;
12816
12817         bnx2x_set_mdio_emac_per_phy(bp, params);
12818         /* Sync the link parameters */
12819         bnx2x_link_status_update(params, vars);
12820
12821         /*
12822          * The module verification was already done by previous link owner,
12823          * so this call is meant only to get warning message
12824          */
12825
12826         for (phy_idx = INT_PHY; phy_idx < params->num_phys; phy_idx++) {
12827                 struct bnx2x_phy *phy = &params->phy[phy_idx];
12828                 if (phy->phy_specific_func) {
12829                         DP(NETIF_MSG_LINK, "Calling PHY specific func\n");
12830                         phy->phy_specific_func(phy, params, PHY_INIT);
12831                 }
12832                 if ((phy->media_type == ETH_PHY_SFPP_10G_FIBER) ||
12833                     (phy->media_type == ETH_PHY_SFP_1G_FIBER) ||
12834                     (phy->media_type == ETH_PHY_DA_TWINAX))
12835                         bnx2x_verify_sfp_module(phy, params);
12836         }
12837         lfa_sts = REG_RD(bp, params->lfa_base +
12838                          offsetof(struct shmem_lfa,
12839                                   lfa_sts));
12840
12841         dont_clear_stat = lfa_sts & SHMEM_LFA_DONT_CLEAR_STAT;
12842
12843         /* Re-enable the NIG/MAC */
12844         if (CHIP_IS_E3(bp)) {
12845                 if (!dont_clear_stat) {
12846                         REG_WR(bp, GRCBASE_MISC +
12847                                MISC_REGISTERS_RESET_REG_2_CLEAR,
12848                                (MISC_REGISTERS_RESET_REG_2_MSTAT0 <<
12849                                 params->port));
12850                         REG_WR(bp, GRCBASE_MISC +
12851                                MISC_REGISTERS_RESET_REG_2_SET,
12852                                (MISC_REGISTERS_RESET_REG_2_MSTAT0 <<
12853                                 params->port));
12854                 }
12855                 if (vars->line_speed < SPEED_10000)
12856                         bnx2x_umac_enable(params, vars, 0);
12857                 else
12858                         bnx2x_xmac_enable(params, vars, 0);
12859         } else {
12860                 if (vars->line_speed < SPEED_10000)
12861                         bnx2x_emac_enable(params, vars, 0);
12862                 else
12863                         bnx2x_bmac_enable(params, vars, 0, !dont_clear_stat);
12864         }
12865
12866         /* Increment LFA count */
12867         lfa_sts = ((lfa_sts & ~LINK_FLAP_AVOIDANCE_COUNT_MASK) |
12868                    (((((lfa_sts & LINK_FLAP_AVOIDANCE_COUNT_MASK) >>
12869                        LINK_FLAP_AVOIDANCE_COUNT_OFFSET) + 1) & 0xff)
12870                     << LINK_FLAP_AVOIDANCE_COUNT_OFFSET));
12871         /* Clear link flap reason */
12872         lfa_sts &= ~LFA_LINK_FLAP_REASON_MASK;
12873
12874         REG_WR(bp, params->lfa_base +
12875                offsetof(struct shmem_lfa, lfa_sts), lfa_sts);
12876
12877         /* Disable NIG DRAIN */
12878         REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
12879
12880         /* Enable interrupts */
12881         bnx2x_link_int_enable(params);
12882         return 0;
12883 }
12884
12885 static void bnx2x_cannot_avoid_link_flap(struct link_params *params,
12886                                          struct link_vars *vars,
12887                                          int lfa_status)
12888 {
12889         u32 lfa_sts, cfg_idx, tmp_val;
12890         struct bnx2x *bp = params->bp;
12891
12892         bnx2x_link_reset(params, vars, 1);
12893
12894         if (!params->lfa_base)
12895                 return;
12896         /* Store the new link parameters */
12897         REG_WR(bp, params->lfa_base +
12898                offsetof(struct shmem_lfa, req_duplex),
12899                params->req_duplex[0] | (params->req_duplex[1] << 16));
12900
12901         REG_WR(bp, params->lfa_base +
12902                offsetof(struct shmem_lfa, req_flow_ctrl),
12903                params->req_flow_ctrl[0] | (params->req_flow_ctrl[1] << 16));
12904
12905         REG_WR(bp, params->lfa_base +
12906                offsetof(struct shmem_lfa, req_line_speed),
12907                params->req_line_speed[0] | (params->req_line_speed[1] << 16));
12908
12909         for (cfg_idx = 0; cfg_idx < SHMEM_LINK_CONFIG_SIZE; cfg_idx++) {
12910                 REG_WR(bp, params->lfa_base +
12911                        offsetof(struct shmem_lfa,
12912                                 speed_cap_mask[cfg_idx]),
12913                        params->speed_cap_mask[cfg_idx]);
12914         }
12915
12916         tmp_val = REG_RD(bp, params->lfa_base +
12917                          offsetof(struct shmem_lfa, additional_config));
12918         tmp_val &= ~REQ_FC_AUTO_ADV_MASK;
12919         tmp_val |= params->req_fc_auto_adv;
12920
12921         REG_WR(bp, params->lfa_base +
12922                offsetof(struct shmem_lfa, additional_config), tmp_val);
12923
12924         lfa_sts = REG_RD(bp, params->lfa_base +
12925                          offsetof(struct shmem_lfa, lfa_sts));
12926
12927         /* Clear the "Don't Clear Statistics" bit, and set reason */
12928         lfa_sts &= ~SHMEM_LFA_DONT_CLEAR_STAT;
12929
12930         /* Set link flap reason */
12931         lfa_sts &= ~LFA_LINK_FLAP_REASON_MASK;
12932         lfa_sts |= ((lfa_status & LFA_LINK_FLAP_REASON_MASK) <<
12933                     LFA_LINK_FLAP_REASON_OFFSET);
12934
12935         /* Increment link flap counter */
12936         lfa_sts = ((lfa_sts & ~LINK_FLAP_COUNT_MASK) |
12937                    (((((lfa_sts & LINK_FLAP_COUNT_MASK) >>
12938                        LINK_FLAP_COUNT_OFFSET) + 1) & 0xff)
12939                     << LINK_FLAP_COUNT_OFFSET));
12940         REG_WR(bp, params->lfa_base +
12941                offsetof(struct shmem_lfa, lfa_sts), lfa_sts);
12942         /* Proceed with regular link initialization */
12943 }
12944
12945 int bnx2x_phy_init(struct link_params *params, struct link_vars *vars)
12946 {
12947         int lfa_status;
12948         struct bnx2x *bp = params->bp;
12949         DP(NETIF_MSG_LINK, "Phy Initialization started\n");
12950         DP(NETIF_MSG_LINK, "(1) req_speed %d, req_flowctrl %d\n",
12951                    params->req_line_speed[0], params->req_flow_ctrl[0]);
12952         DP(NETIF_MSG_LINK, "(2) req_speed %d, req_flowctrl %d\n",
12953                    params->req_line_speed[1], params->req_flow_ctrl[1]);
12954         DP(NETIF_MSG_LINK, "req_adv_flow_ctrl 0x%x\n", params->req_fc_auto_adv);
12955         vars->link_status = 0;
12956         vars->phy_link_up = 0;
12957         vars->link_up = 0;
12958         vars->line_speed = 0;
12959         vars->duplex = DUPLEX_FULL;
12960         vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
12961         vars->mac_type = MAC_TYPE_NONE;
12962         vars->phy_flags = 0;
12963         vars->check_kr2_recovery_cnt = 0;
12964         params->link_flags = PHY_INITIALIZED;
12965         /* Driver opens NIG-BRB filters */
12966         bnx2x_set_rx_filter(params, 1);
12967         bnx2x_chng_link_count(params, true);
12968         /* Check if link flap can be avoided */
12969         lfa_status = bnx2x_check_lfa(params);
12970
12971         if (lfa_status == 0) {
12972                 DP(NETIF_MSG_LINK, "Link Flap Avoidance in progress\n");
12973                 return bnx2x_avoid_link_flap(params, vars);
12974         }
12975
12976         DP(NETIF_MSG_LINK, "Cannot avoid link flap lfa_sta=0x%x\n",
12977                        lfa_status);
12978         bnx2x_cannot_avoid_link_flap(params, vars, lfa_status);
12979
12980         /* Disable attentions */
12981         bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + params->port*4,
12982                        (NIG_MASK_XGXS0_LINK_STATUS |
12983                         NIG_MASK_XGXS0_LINK10G |
12984                         NIG_MASK_SERDES0_LINK_STATUS |
12985                         NIG_MASK_MI_INT));
12986
12987         bnx2x_emac_init(params, vars);
12988
12989         if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED)
12990                 vars->link_status |= LINK_STATUS_PFC_ENABLED;
12991
12992         if (params->num_phys == 0) {
12993                 DP(NETIF_MSG_LINK, "No phy found for initialization !!\n");
12994                 return -EINVAL;
12995         }
12996         set_phy_vars(params, vars);
12997
12998         DP(NETIF_MSG_LINK, "Num of phys on board: %d\n", params->num_phys);
12999         switch (params->loopback_mode) {
13000         case LOOPBACK_BMAC:
13001                 bnx2x_init_bmac_loopback(params, vars);
13002                 break;
13003         case LOOPBACK_EMAC:
13004                 bnx2x_init_emac_loopback(params, vars);
13005                 break;
13006         case LOOPBACK_XMAC:
13007                 bnx2x_init_xmac_loopback(params, vars);
13008                 break;
13009         case LOOPBACK_UMAC:
13010                 bnx2x_init_umac_loopback(params, vars);
13011                 break;
13012         case LOOPBACK_XGXS:
13013         case LOOPBACK_EXT_PHY:
13014                 bnx2x_init_xgxs_loopback(params, vars);
13015                 break;
13016         default:
13017                 if (!CHIP_IS_E3(bp)) {
13018                         if (params->switch_cfg == SWITCH_CFG_10G)
13019                                 bnx2x_xgxs_deassert(params);
13020                         else
13021                                 bnx2x_serdes_deassert(bp, params->port);
13022                 }
13023                 bnx2x_link_initialize(params, vars);
13024                 msleep(30);
13025                 bnx2x_link_int_enable(params);
13026                 break;
13027         }
13028         bnx2x_update_mng(params, vars->link_status);
13029
13030         bnx2x_update_mng_eee(params, vars->eee_status);
13031         return 0;
13032 }
13033
13034 int bnx2x_link_reset(struct link_params *params, struct link_vars *vars,
13035                      u8 reset_ext_phy)
13036 {
13037         struct bnx2x *bp = params->bp;
13038         u8 phy_index, port = params->port, clear_latch_ind = 0;
13039         DP(NETIF_MSG_LINK, "Resetting the link of port %d\n", port);
13040         /* Disable attentions */
13041         vars->link_status = 0;
13042         bnx2x_chng_link_count(params, true);
13043         bnx2x_update_mng(params, vars->link_status);
13044         vars->eee_status &= ~(SHMEM_EEE_LP_ADV_STATUS_MASK |
13045                               SHMEM_EEE_ACTIVE_BIT);
13046         bnx2x_update_mng_eee(params, vars->eee_status);
13047         bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4,
13048                        (NIG_MASK_XGXS0_LINK_STATUS |
13049                         NIG_MASK_XGXS0_LINK10G |
13050                         NIG_MASK_SERDES0_LINK_STATUS |
13051                         NIG_MASK_MI_INT));
13052
13053         /* Activate nig drain */
13054         REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1);
13055
13056         /* Disable nig egress interface */
13057         if (!CHIP_IS_E3(bp)) {
13058                 REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0);
13059                 REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0);
13060         }
13061
13062         if (!CHIP_IS_E3(bp)) {
13063                 bnx2x_set_bmac_rx(bp, params->chip_id, port, 0);
13064         } else {
13065                 bnx2x_set_xmac_rxtx(params, 0);
13066                 bnx2x_set_umac_rxtx(params, 0);
13067         }
13068         /* Disable emac */
13069         if (!CHIP_IS_E3(bp))
13070                 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0);
13071
13072         usleep_range(10000, 20000);
13073         /* The PHY reset is controlled by GPIO 1
13074          * Hold it as vars low
13075          */
13076          /* Clear link led */
13077         bnx2x_set_mdio_emac_per_phy(bp, params);
13078         bnx2x_set_led(params, vars, LED_MODE_OFF, 0);
13079
13080         if (reset_ext_phy) {
13081                 for (phy_index = EXT_PHY1; phy_index < params->num_phys;
13082                       phy_index++) {
13083                         if (params->phy[phy_index].link_reset) {
13084                                 bnx2x_set_aer_mmd(params,
13085                                                   &params->phy[phy_index]);
13086                                 params->phy[phy_index].link_reset(
13087                                         &params->phy[phy_index],
13088                                         params);
13089                         }
13090                         if (params->phy[phy_index].flags &
13091                             FLAGS_REARM_LATCH_SIGNAL)
13092                                 clear_latch_ind = 1;
13093                 }
13094         }
13095
13096         if (clear_latch_ind) {
13097                 /* Clear latching indication */
13098                 bnx2x_rearm_latch_signal(bp, port, 0);
13099                 bnx2x_bits_dis(bp, NIG_REG_LATCH_BC_0 + port*4,
13100                                1 << NIG_LATCH_BC_ENABLE_MI_INT);
13101         }
13102         if (params->phy[INT_PHY].link_reset)
13103                 params->phy[INT_PHY].link_reset(
13104                         &params->phy[INT_PHY], params);
13105
13106         /* Disable nig ingress interface */
13107         if (!CHIP_IS_E3(bp)) {
13108                 /* Reset BigMac */
13109                 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
13110                        (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
13111                 REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0);
13112                 REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0);
13113         } else {
13114                 u32 xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
13115                 bnx2x_set_xumac_nig(params, 0, 0);
13116                 if (REG_RD(bp, MISC_REG_RESET_REG_2) &
13117                     MISC_REGISTERS_RESET_REG_2_XMAC)
13118                         REG_WR(bp, xmac_base + XMAC_REG_CTRL,
13119                                XMAC_CTRL_REG_SOFT_RESET);
13120         }
13121         vars->link_up = 0;
13122         vars->phy_flags = 0;
13123         return 0;
13124 }
13125 int bnx2x_lfa_reset(struct link_params *params,
13126                                struct link_vars *vars)
13127 {
13128         struct bnx2x *bp = params->bp;
13129         vars->link_up = 0;
13130         vars->phy_flags = 0;
13131         params->link_flags &= ~PHY_INITIALIZED;
13132         if (!params->lfa_base)
13133                 return bnx2x_link_reset(params, vars, 1);
13134         /*
13135          * Activate NIG drain so that during this time the device won't send
13136          * anything while it is unable to response.
13137          */
13138         REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 1);
13139
13140         /*
13141          * Close gracefully the gate from BMAC to NIG such that no half packets
13142          * are passed.
13143          */
13144         if (!CHIP_IS_E3(bp))
13145                 bnx2x_set_bmac_rx(bp, params->chip_id, params->port, 0);
13146
13147         if (CHIP_IS_E3(bp)) {
13148                 bnx2x_set_xmac_rxtx(params, 0);
13149                 bnx2x_set_umac_rxtx(params, 0);
13150         }
13151         /* Wait 10ms for the pipe to clean up*/
13152         usleep_range(10000, 20000);
13153
13154         /* Clean the NIG-BRB using the network filters in a way that will
13155          * not cut a packet in the middle.
13156          */
13157         bnx2x_set_rx_filter(params, 0);
13158
13159         /*
13160          * Re-open the gate between the BMAC and the NIG, after verifying the
13161          * gate to the BRB is closed, otherwise packets may arrive to the
13162          * firmware before driver had initialized it. The target is to achieve
13163          * minimum management protocol down time.
13164          */
13165         if (!CHIP_IS_E3(bp))
13166                 bnx2x_set_bmac_rx(bp, params->chip_id, params->port, 1);
13167
13168         if (CHIP_IS_E3(bp)) {
13169                 bnx2x_set_xmac_rxtx(params, 1);
13170                 bnx2x_set_umac_rxtx(params, 1);
13171         }
13172         /* Disable NIG drain */
13173         REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
13174         return 0;
13175 }
13176
13177 /****************************************************************************/
13178 /*                              Common function                             */
13179 /****************************************************************************/
13180 static int bnx2x_8073_common_init_phy(struct bnx2x *bp,
13181                                       u32 shmem_base_path[],
13182                                       u32 shmem2_base_path[], u8 phy_index,
13183                                       u32 chip_id)
13184 {
13185         struct bnx2x_phy phy[PORT_MAX];
13186         struct bnx2x_phy *phy_blk[PORT_MAX];
13187         u16 val;
13188         s8 port = 0;
13189         s8 port_of_path = 0;
13190         u32 swap_val, swap_override;
13191         swap_val = REG_RD(bp,  NIG_REG_PORT_SWAP);
13192         swap_override = REG_RD(bp,  NIG_REG_STRAP_OVERRIDE);
13193         port ^= (swap_val && swap_override);
13194         bnx2x_ext_phy_hw_reset(bp, port);
13195         /* PART1 - Reset both phys */
13196         for (port = PORT_MAX - 1; port >= PORT_0; port--) {
13197                 u32 shmem_base, shmem2_base;
13198                 /* In E2, same phy is using for port0 of the two paths */
13199                 if (CHIP_IS_E1x(bp)) {
13200                         shmem_base = shmem_base_path[0];
13201                         shmem2_base = shmem2_base_path[0];
13202                         port_of_path = port;
13203                 } else {
13204                         shmem_base = shmem_base_path[port];
13205                         shmem2_base = shmem2_base_path[port];
13206                         port_of_path = 0;
13207                 }
13208
13209                 /* Extract the ext phy address for the port */
13210                 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
13211                                        port_of_path, &phy[port]) !=
13212                     0) {
13213                         DP(NETIF_MSG_LINK, "populate_phy failed\n");
13214                         return -EINVAL;
13215                 }
13216                 /* Disable attentions */
13217                 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 +
13218                                port_of_path*4,
13219                                (NIG_MASK_XGXS0_LINK_STATUS |
13220                                 NIG_MASK_XGXS0_LINK10G |
13221                                 NIG_MASK_SERDES0_LINK_STATUS |
13222                                 NIG_MASK_MI_INT));
13223
13224                 /* Need to take the phy out of low power mode in order
13225                  * to write to access its registers
13226                  */
13227                 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
13228                                MISC_REGISTERS_GPIO_OUTPUT_HIGH,
13229                                port);
13230
13231                 /* Reset the phy */
13232                 bnx2x_cl45_write(bp, &phy[port],
13233                                  MDIO_PMA_DEVAD,
13234                                  MDIO_PMA_REG_CTRL,
13235                                  1<<15);
13236         }
13237
13238         /* Add delay of 150ms after reset */
13239         msleep(150);
13240
13241         if (phy[PORT_0].addr & 0x1) {
13242                 phy_blk[PORT_0] = &(phy[PORT_1]);
13243                 phy_blk[PORT_1] = &(phy[PORT_0]);
13244         } else {
13245                 phy_blk[PORT_0] = &(phy[PORT_0]);
13246                 phy_blk[PORT_1] = &(phy[PORT_1]);
13247         }
13248
13249         /* PART2 - Download firmware to both phys */
13250         for (port = PORT_MAX - 1; port >= PORT_0; port--) {
13251                 if (CHIP_IS_E1x(bp))
13252                         port_of_path = port;
13253                 else
13254                         port_of_path = 0;
13255
13256                 DP(NETIF_MSG_LINK, "Loading spirom for phy address 0x%x\n",
13257                            phy_blk[port]->addr);
13258                 if (bnx2x_8073_8727_external_rom_boot(bp, phy_blk[port],
13259                                                       port_of_path))
13260                         return -EINVAL;
13261
13262                 /* Only set bit 10 = 1 (Tx power down) */
13263                 bnx2x_cl45_read(bp, phy_blk[port],
13264                                 MDIO_PMA_DEVAD,
13265                                 MDIO_PMA_REG_TX_POWER_DOWN, &val);
13266
13267                 /* Phase1 of TX_POWER_DOWN reset */
13268                 bnx2x_cl45_write(bp, phy_blk[port],
13269                                  MDIO_PMA_DEVAD,
13270                                  MDIO_PMA_REG_TX_POWER_DOWN,
13271                                  (val | 1<<10));
13272         }
13273
13274         /* Toggle Transmitter: Power down and then up with 600ms delay
13275          * between
13276          */
13277         msleep(600);
13278
13279         /* PART3 - complete TX_POWER_DOWN process, and set GPIO2 back to low */
13280         for (port = PORT_MAX - 1; port >= PORT_0; port--) {
13281                 /* Phase2 of POWER_DOWN_RESET */
13282                 /* Release bit 10 (Release Tx power down) */
13283                 bnx2x_cl45_read(bp, phy_blk[port],
13284                                 MDIO_PMA_DEVAD,
13285                                 MDIO_PMA_REG_TX_POWER_DOWN, &val);
13286
13287                 bnx2x_cl45_write(bp, phy_blk[port],
13288                                 MDIO_PMA_DEVAD,
13289                                 MDIO_PMA_REG_TX_POWER_DOWN, (val & (~(1<<10))));
13290                 usleep_range(15000, 30000);
13291
13292                 /* Read modify write the SPI-ROM version select register */
13293                 bnx2x_cl45_read(bp, phy_blk[port],
13294                                 MDIO_PMA_DEVAD,
13295                                 MDIO_PMA_REG_EDC_FFE_MAIN, &val);
13296                 bnx2x_cl45_write(bp, phy_blk[port],
13297                                  MDIO_PMA_DEVAD,
13298                                  MDIO_PMA_REG_EDC_FFE_MAIN, (val | (1<<12)));
13299
13300                 /* set GPIO2 back to LOW */
13301                 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
13302                                MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
13303         }
13304         return 0;
13305 }
13306 static int bnx2x_8726_common_init_phy(struct bnx2x *bp,
13307                                       u32 shmem_base_path[],
13308                                       u32 shmem2_base_path[], u8 phy_index,
13309                                       u32 chip_id)
13310 {
13311         u32 val;
13312         s8 port;
13313         struct bnx2x_phy phy;
13314         /* Use port1 because of the static port-swap */
13315         /* Enable the module detection interrupt */
13316         val = REG_RD(bp, MISC_REG_GPIO_EVENT_EN);
13317         val |= ((1<<MISC_REGISTERS_GPIO_3)|
13318                 (1<<(MISC_REGISTERS_GPIO_3 + MISC_REGISTERS_GPIO_PORT_SHIFT)));
13319         REG_WR(bp, MISC_REG_GPIO_EVENT_EN, val);
13320
13321         bnx2x_ext_phy_hw_reset(bp, 0);
13322         usleep_range(5000, 10000);
13323         for (port = 0; port < PORT_MAX; port++) {
13324                 u32 shmem_base, shmem2_base;
13325
13326                 /* In E2, same phy is using for port0 of the two paths */
13327                 if (CHIP_IS_E1x(bp)) {
13328                         shmem_base = shmem_base_path[0];
13329                         shmem2_base = shmem2_base_path[0];
13330                 } else {
13331                         shmem_base = shmem_base_path[port];
13332                         shmem2_base = shmem2_base_path[port];
13333                 }
13334                 /* Extract the ext phy address for the port */
13335                 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
13336                                        port, &phy) !=
13337                     0) {
13338                         DP(NETIF_MSG_LINK, "populate phy failed\n");
13339                         return -EINVAL;
13340                 }
13341
13342                 /* Reset phy*/
13343                 bnx2x_cl45_write(bp, &phy,
13344                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x0001);
13345
13346
13347                 /* Set fault module detected LED on */
13348                 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
13349                                MISC_REGISTERS_GPIO_HIGH,
13350                                port);
13351         }
13352
13353         return 0;
13354 }
13355 static void bnx2x_get_ext_phy_reset_gpio(struct bnx2x *bp, u32 shmem_base,
13356                                          u8 *io_gpio, u8 *io_port)
13357 {
13358
13359         u32 phy_gpio_reset = REG_RD(bp, shmem_base +
13360                                           offsetof(struct shmem_region,
13361                                 dev_info.port_hw_config[PORT_0].default_cfg));
13362         switch (phy_gpio_reset) {
13363         case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0:
13364                 *io_gpio = 0;
13365                 *io_port = 0;
13366                 break;
13367         case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P0:
13368                 *io_gpio = 1;
13369                 *io_port = 0;
13370                 break;
13371         case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P0:
13372                 *io_gpio = 2;
13373                 *io_port = 0;
13374                 break;
13375         case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P0:
13376                 *io_gpio = 3;
13377                 *io_port = 0;
13378                 break;
13379         case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P1:
13380                 *io_gpio = 0;
13381                 *io_port = 1;
13382                 break;
13383         case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P1:
13384                 *io_gpio = 1;
13385                 *io_port = 1;
13386                 break;
13387         case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P1:
13388                 *io_gpio = 2;
13389                 *io_port = 1;
13390                 break;
13391         case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P1:
13392                 *io_gpio = 3;
13393                 *io_port = 1;
13394                 break;
13395         default:
13396                 /* Don't override the io_gpio and io_port */
13397                 break;
13398         }
13399 }
13400
13401 static int bnx2x_8727_common_init_phy(struct bnx2x *bp,
13402                                       u32 shmem_base_path[],
13403                                       u32 shmem2_base_path[], u8 phy_index,
13404                                       u32 chip_id)
13405 {
13406         s8 port, reset_gpio;
13407         u32 swap_val, swap_override;
13408         struct bnx2x_phy phy[PORT_MAX];
13409         struct bnx2x_phy *phy_blk[PORT_MAX];
13410         s8 port_of_path;
13411         swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
13412         swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
13413
13414         reset_gpio = MISC_REGISTERS_GPIO_1;
13415         port = 1;
13416
13417         /* Retrieve the reset gpio/port which control the reset.
13418          * Default is GPIO1, PORT1
13419          */
13420         bnx2x_get_ext_phy_reset_gpio(bp, shmem_base_path[0],
13421                                      (u8 *)&reset_gpio, (u8 *)&port);
13422
13423         /* Calculate the port based on port swap */
13424         port ^= (swap_val && swap_override);
13425
13426         /* Initiate PHY reset*/
13427         bnx2x_set_gpio(bp, reset_gpio, MISC_REGISTERS_GPIO_OUTPUT_LOW,
13428                        port);
13429         usleep_range(1000, 2000);
13430         bnx2x_set_gpio(bp, reset_gpio, MISC_REGISTERS_GPIO_OUTPUT_HIGH,
13431                        port);
13432
13433         usleep_range(5000, 10000);
13434
13435         /* PART1 - Reset both phys */
13436         for (port = PORT_MAX - 1; port >= PORT_0; port--) {
13437                 u32 shmem_base, shmem2_base;
13438
13439                 /* In E2, same phy is using for port0 of the two paths */
13440                 if (CHIP_IS_E1x(bp)) {
13441                         shmem_base = shmem_base_path[0];
13442                         shmem2_base = shmem2_base_path[0];
13443                         port_of_path = port;
13444                 } else {
13445                         shmem_base = shmem_base_path[port];
13446                         shmem2_base = shmem2_base_path[port];
13447                         port_of_path = 0;
13448                 }
13449
13450                 /* Extract the ext phy address for the port */
13451                 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
13452                                        port_of_path, &phy[port]) !=
13453                                        0) {
13454                         DP(NETIF_MSG_LINK, "populate phy failed\n");
13455                         return -EINVAL;
13456                 }
13457                 /* disable attentions */
13458                 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 +
13459                                port_of_path*4,
13460                                (NIG_MASK_XGXS0_LINK_STATUS |
13461                                 NIG_MASK_XGXS0_LINK10G |
13462                                 NIG_MASK_SERDES0_LINK_STATUS |
13463                                 NIG_MASK_MI_INT));
13464
13465
13466                 /* Reset the phy */
13467                 bnx2x_cl45_write(bp, &phy[port],
13468                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15);
13469         }
13470
13471         /* Add delay of 150ms after reset */
13472         msleep(150);
13473         if (phy[PORT_0].addr & 0x1) {
13474                 phy_blk[PORT_0] = &(phy[PORT_1]);
13475                 phy_blk[PORT_1] = &(phy[PORT_0]);
13476         } else {
13477                 phy_blk[PORT_0] = &(phy[PORT_0]);
13478                 phy_blk[PORT_1] = &(phy[PORT_1]);
13479         }
13480         /* PART2 - Download firmware to both phys */
13481         for (port = PORT_MAX - 1; port >= PORT_0; port--) {
13482                 if (CHIP_IS_E1x(bp))
13483                         port_of_path = port;
13484                 else
13485                         port_of_path = 0;
13486                 DP(NETIF_MSG_LINK, "Loading spirom for phy address 0x%x\n",
13487                            phy_blk[port]->addr);
13488                 if (bnx2x_8073_8727_external_rom_boot(bp, phy_blk[port],
13489                                                       port_of_path))
13490                         return -EINVAL;
13491                 /* Disable PHY transmitter output */
13492                 bnx2x_cl45_write(bp, phy_blk[port],
13493                                  MDIO_PMA_DEVAD,
13494                                  MDIO_PMA_REG_TX_DISABLE, 1);
13495
13496         }
13497         return 0;
13498 }
13499
13500 static int bnx2x_84833_common_init_phy(struct bnx2x *bp,
13501                                                 u32 shmem_base_path[],
13502                                                 u32 shmem2_base_path[],
13503                                                 u8 phy_index,
13504                                                 u32 chip_id)
13505 {
13506         u8 reset_gpios;
13507         reset_gpios = bnx2x_84833_get_reset_gpios(bp, shmem_base_path, chip_id);
13508         bnx2x_set_mult_gpio(bp, reset_gpios, MISC_REGISTERS_GPIO_OUTPUT_LOW);
13509         udelay(10);
13510         bnx2x_set_mult_gpio(bp, reset_gpios, MISC_REGISTERS_GPIO_OUTPUT_HIGH);
13511         DP(NETIF_MSG_LINK, "84833 reset pulse on pin values 0x%x\n",
13512                 reset_gpios);
13513         return 0;
13514 }
13515
13516 static int bnx2x_ext_phy_common_init(struct bnx2x *bp, u32 shmem_base_path[],
13517                                      u32 shmem2_base_path[], u8 phy_index,
13518                                      u32 ext_phy_type, u32 chip_id)
13519 {
13520         int rc = 0;
13521
13522         switch (ext_phy_type) {
13523         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
13524                 rc = bnx2x_8073_common_init_phy(bp, shmem_base_path,
13525                                                 shmem2_base_path,
13526                                                 phy_index, chip_id);
13527                 break;
13528         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
13529         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
13530         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC:
13531                 rc = bnx2x_8727_common_init_phy(bp, shmem_base_path,
13532                                                 shmem2_base_path,
13533                                                 phy_index, chip_id);
13534                 break;
13535
13536         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
13537                 /* GPIO1 affects both ports, so there's need to pull
13538                  * it for single port alone
13539                  */
13540                 rc = bnx2x_8726_common_init_phy(bp, shmem_base_path,
13541                                                 shmem2_base_path,
13542                                                 phy_index, chip_id);
13543                 break;
13544         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833:
13545         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834:
13546         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84858:
13547                 /* GPIO3's are linked, and so both need to be toggled
13548                  * to obtain required 2us pulse.
13549                  */
13550                 rc = bnx2x_84833_common_init_phy(bp, shmem_base_path,
13551                                                 shmem2_base_path,
13552                                                 phy_index, chip_id);
13553                 break;
13554         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:
13555                 rc = -EINVAL;
13556                 break;
13557         default:
13558                 DP(NETIF_MSG_LINK,
13559                            "ext_phy 0x%x common init not required\n",
13560                            ext_phy_type);
13561                 break;
13562         }
13563
13564         if (rc)
13565                 netdev_err(bp->dev,  "Warning: PHY was not initialized,"
13566                                       " Port %d\n",
13567                          0);
13568         return rc;
13569 }
13570
13571 int bnx2x_common_init_phy(struct bnx2x *bp, u32 shmem_base_path[],
13572                           u32 shmem2_base_path[], u32 chip_id)
13573 {
13574         int rc = 0;
13575         u32 phy_ver, val;
13576         u8 phy_index = 0;
13577         u32 ext_phy_type, ext_phy_config;
13578
13579         bnx2x_set_mdio_clk(bp, chip_id, GRCBASE_EMAC0);
13580         bnx2x_set_mdio_clk(bp, chip_id, GRCBASE_EMAC1);
13581         DP(NETIF_MSG_LINK, "Begin common phy init\n");
13582         if (CHIP_IS_E3(bp)) {
13583                 /* Enable EPIO */
13584                 val = REG_RD(bp, MISC_REG_GEN_PURP_HWG);
13585                 REG_WR(bp, MISC_REG_GEN_PURP_HWG, val | 1);
13586         }
13587         /* Check if common init was already done */
13588         phy_ver = REG_RD(bp, shmem_base_path[0] +
13589                          offsetof(struct shmem_region,
13590                                   port_mb[PORT_0].ext_phy_fw_version));
13591         if (phy_ver) {
13592                 DP(NETIF_MSG_LINK, "Not doing common init; phy ver is 0x%x\n",
13593                                phy_ver);
13594                 return 0;
13595         }
13596
13597         /* Read the ext_phy_type for arbitrary port(0) */
13598         for (phy_index = EXT_PHY1; phy_index < MAX_PHYS;
13599               phy_index++) {
13600                 ext_phy_config = bnx2x_get_ext_phy_config(bp,
13601                                                           shmem_base_path[0],
13602                                                           phy_index, 0);
13603                 ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
13604                 rc |= bnx2x_ext_phy_common_init(bp, shmem_base_path,
13605                                                 shmem2_base_path,
13606                                                 phy_index, ext_phy_type,
13607                                                 chip_id);
13608         }
13609         return rc;
13610 }
13611
13612 static void bnx2x_check_over_curr(struct link_params *params,
13613                                   struct link_vars *vars)
13614 {
13615         struct bnx2x *bp = params->bp;
13616         u32 cfg_pin;
13617         u8 port = params->port;
13618         u32 pin_val;
13619
13620         cfg_pin = (REG_RD(bp, params->shmem_base +
13621                           offsetof(struct shmem_region,
13622                                dev_info.port_hw_config[port].e3_cmn_pin_cfg1)) &
13623                    PORT_HW_CFG_E3_OVER_CURRENT_MASK) >>
13624                 PORT_HW_CFG_E3_OVER_CURRENT_SHIFT;
13625
13626         /* Ignore check if no external input PIN available */
13627         if (bnx2x_get_cfg_pin(bp, cfg_pin, &pin_val) != 0)
13628                 return;
13629
13630         if (!pin_val) {
13631                 if ((vars->phy_flags & PHY_OVER_CURRENT_FLAG) == 0) {
13632                         netdev_err(bp->dev, "Error:  Power fault on Port %d has"
13633                                             " been detected and the power to "
13634                                             "that SFP+ module has been removed"
13635                                             " to prevent failure of the card."
13636                                             " Please remove the SFP+ module and"
13637                                             " restart the system to clear this"
13638                                             " error.\n",
13639                          params->port);
13640                         vars->phy_flags |= PHY_OVER_CURRENT_FLAG;
13641                         bnx2x_warpcore_power_module(params, 0);
13642                 }
13643         } else
13644                 vars->phy_flags &= ~PHY_OVER_CURRENT_FLAG;
13645 }
13646
13647 /* Returns 0 if no change occurred since last check; 1 otherwise. */
13648 static u8 bnx2x_analyze_link_error(struct link_params *params,
13649                                     struct link_vars *vars, u32 status,
13650                                     u32 phy_flag, u32 link_flag, u8 notify)
13651 {
13652         struct bnx2x *bp = params->bp;
13653         /* Compare new value with previous value */
13654         u8 led_mode;
13655         u32 old_status = (vars->phy_flags & phy_flag) ? 1 : 0;
13656
13657         if ((status ^ old_status) == 0)
13658                 return 0;
13659
13660         /* If values differ */
13661         switch (phy_flag) {
13662         case PHY_HALF_OPEN_CONN_FLAG:
13663                 DP(NETIF_MSG_LINK, "Analyze Remote Fault\n");
13664                 break;
13665         case PHY_SFP_TX_FAULT_FLAG:
13666                 DP(NETIF_MSG_LINK, "Analyze TX Fault\n");
13667                 break;
13668         default:
13669                 DP(NETIF_MSG_LINK, "Analyze UNKNOWN\n");
13670         }
13671         DP(NETIF_MSG_LINK, "Link changed:[%x %x]->%x\n", vars->link_up,
13672            old_status, status);
13673
13674         /* Do not touch the link in case physical link down */
13675         if ((vars->phy_flags & PHY_PHYSICAL_LINK_FLAG) == 0)
13676                 return 1;
13677
13678         /* a. Update shmem->link_status accordingly
13679          * b. Update link_vars->link_up
13680          */
13681         if (status) {
13682                 vars->link_status &= ~LINK_STATUS_LINK_UP;
13683                 vars->link_status |= link_flag;
13684                 vars->link_up = 0;
13685                 vars->phy_flags |= phy_flag;
13686
13687                 /* activate nig drain */
13688                 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 1);
13689                 /* Set LED mode to off since the PHY doesn't know about these
13690                  * errors
13691                  */
13692                 led_mode = LED_MODE_OFF;
13693         } else {
13694                 vars->link_status |= LINK_STATUS_LINK_UP;
13695                 vars->link_status &= ~link_flag;
13696                 vars->link_up = 1;
13697                 vars->phy_flags &= ~phy_flag;
13698                 led_mode = LED_MODE_OPER;
13699
13700                 /* Clear nig drain */
13701                 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
13702         }
13703         bnx2x_sync_link(params, vars);
13704         /* Update the LED according to the link state */
13705         bnx2x_set_led(params, vars, led_mode, SPEED_10000);
13706
13707         /* Update link status in the shared memory */
13708         bnx2x_update_mng(params, vars->link_status);
13709
13710         /* C. Trigger General Attention */
13711         vars->periodic_flags |= PERIODIC_FLAGS_LINK_EVENT;
13712         if (notify)
13713                 bnx2x_notify_link_changed(bp);
13714
13715         return 1;
13716 }
13717
13718 /******************************************************************************
13719 * Description:
13720 *       This function checks for half opened connection change indication.
13721 *       When such change occurs, it calls the bnx2x_analyze_link_error
13722 *       to check if Remote Fault is set or cleared. Reception of remote fault
13723 *       status message in the MAC indicates that the peer's MAC has detected
13724 *       a fault, for example, due to break in the TX side of fiber.
13725 *
13726 ******************************************************************************/
13727 static int bnx2x_check_half_open_conn(struct link_params *params,
13728                                       struct link_vars *vars,
13729                                       u8 notify)
13730 {
13731         struct bnx2x *bp = params->bp;
13732         u32 lss_status = 0;
13733         u32 mac_base;
13734         /* In case link status is physically up @ 10G do */
13735         if (((vars->phy_flags & PHY_PHYSICAL_LINK_FLAG) == 0) ||
13736             (REG_RD(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4)))
13737                 return 0;
13738
13739         if (CHIP_IS_E3(bp) &&
13740             (REG_RD(bp, MISC_REG_RESET_REG_2) &
13741               (MISC_REGISTERS_RESET_REG_2_XMAC))) {
13742                 /* Check E3 XMAC */
13743                 /* Note that link speed cannot be queried here, since it may be
13744                  * zero while link is down. In case UMAC is active, LSS will
13745                  * simply not be set
13746                  */
13747                 mac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
13748
13749                 /* Clear stick bits (Requires rising edge) */
13750                 REG_WR(bp, mac_base + XMAC_REG_CLEAR_RX_LSS_STATUS, 0);
13751                 REG_WR(bp, mac_base + XMAC_REG_CLEAR_RX_LSS_STATUS,
13752                        XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_LOCAL_FAULT_STATUS |
13753                        XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_REMOTE_FAULT_STATUS);
13754                 if (REG_RD(bp, mac_base + XMAC_REG_RX_LSS_STATUS))
13755                         lss_status = 1;
13756
13757                 bnx2x_analyze_link_error(params, vars, lss_status,
13758                                          PHY_HALF_OPEN_CONN_FLAG,
13759                                          LINK_STATUS_NONE, notify);
13760         } else if (REG_RD(bp, MISC_REG_RESET_REG_2) &
13761                    (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << params->port)) {
13762                 /* Check E1X / E2 BMAC */
13763                 u32 lss_status_reg;
13764                 u32 wb_data[2];
13765                 mac_base = params->port ? NIG_REG_INGRESS_BMAC1_MEM :
13766                         NIG_REG_INGRESS_BMAC0_MEM;
13767                 /*  Read BIGMAC_REGISTER_RX_LSS_STATUS */
13768                 if (CHIP_IS_E2(bp))
13769                         lss_status_reg = BIGMAC2_REGISTER_RX_LSS_STAT;
13770                 else
13771                         lss_status_reg = BIGMAC_REGISTER_RX_LSS_STATUS;
13772
13773                 REG_RD_DMAE(bp, mac_base + lss_status_reg, wb_data, 2);
13774                 lss_status = (wb_data[0] > 0);
13775
13776                 bnx2x_analyze_link_error(params, vars, lss_status,
13777                                          PHY_HALF_OPEN_CONN_FLAG,
13778                                          LINK_STATUS_NONE, notify);
13779         }
13780         return 0;
13781 }
13782 static void bnx2x_sfp_tx_fault_detection(struct bnx2x_phy *phy,
13783                                          struct link_params *params,
13784                                          struct link_vars *vars)
13785 {
13786         struct bnx2x *bp = params->bp;
13787         u32 cfg_pin, value = 0;
13788         u8 led_change, port = params->port;
13789
13790         /* Get The SFP+ TX_Fault controlling pin ([eg]pio) */
13791         cfg_pin = (REG_RD(bp, params->shmem_base + offsetof(struct shmem_region,
13792                           dev_info.port_hw_config[port].e3_cmn_pin_cfg)) &
13793                    PORT_HW_CFG_E3_TX_FAULT_MASK) >>
13794                   PORT_HW_CFG_E3_TX_FAULT_SHIFT;
13795
13796         if (bnx2x_get_cfg_pin(bp, cfg_pin, &value)) {
13797                 DP(NETIF_MSG_LINK, "Failed to read pin 0x%02x\n", cfg_pin);
13798                 return;
13799         }
13800
13801         led_change = bnx2x_analyze_link_error(params, vars, value,
13802                                               PHY_SFP_TX_FAULT_FLAG,
13803                                               LINK_STATUS_SFP_TX_FAULT, 1);
13804
13805         if (led_change) {
13806                 /* Change TX_Fault led, set link status for further syncs */
13807                 u8 led_mode;
13808
13809                 if (vars->phy_flags & PHY_SFP_TX_FAULT_FLAG) {
13810                         led_mode = MISC_REGISTERS_GPIO_HIGH;
13811                         vars->link_status |= LINK_STATUS_SFP_TX_FAULT;
13812                 } else {
13813                         led_mode = MISC_REGISTERS_GPIO_LOW;
13814                         vars->link_status &= ~LINK_STATUS_SFP_TX_FAULT;
13815                 }
13816
13817                 /* If module is unapproved, led should be on regardless */
13818                 if (!(phy->flags & FLAGS_SFP_NOT_APPROVED)) {
13819                         DP(NETIF_MSG_LINK, "Change TX_Fault LED: ->%x\n",
13820                            led_mode);
13821                         bnx2x_set_e3_module_fault_led(params, led_mode);
13822                 }
13823         }
13824 }
13825 static void bnx2x_kr2_recovery(struct link_params *params,
13826                                struct link_vars *vars,
13827                                struct bnx2x_phy *phy)
13828 {
13829         struct bnx2x *bp = params->bp;
13830         DP(NETIF_MSG_LINK, "KR2 recovery\n");
13831         bnx2x_warpcore_enable_AN_KR2(phy, params, vars);
13832         bnx2x_warpcore_restart_AN_KR(phy, params);
13833 }
13834
13835 static void bnx2x_check_kr2_wa(struct link_params *params,
13836                                struct link_vars *vars,
13837                                struct bnx2x_phy *phy)
13838 {
13839         struct bnx2x *bp = params->bp;
13840         u16 base_page, next_page, not_kr2_device, lane;
13841         int sigdet;
13842
13843         /* Once KR2 was disabled, wait 5 seconds before checking KR2 recovery
13844          * Since some switches tend to reinit the AN process and clear the
13845          * the advertised BP/NP after ~2 seconds causing the KR2 to be disabled
13846          * and recovered many times
13847          */
13848         if (vars->check_kr2_recovery_cnt > 0) {
13849                 vars->check_kr2_recovery_cnt--;
13850                 return;
13851         }
13852
13853         sigdet = bnx2x_warpcore_get_sigdet(phy, params);
13854         if (!sigdet) {
13855                 if (!(params->link_attr_sync & LINK_ATTR_SYNC_KR2_ENABLE)) {
13856                         bnx2x_kr2_recovery(params, vars, phy);
13857                         DP(NETIF_MSG_LINK, "No sigdet\n");
13858                 }
13859                 return;
13860         }
13861
13862         lane = bnx2x_get_warpcore_lane(phy, params);
13863         CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
13864                           MDIO_AER_BLOCK_AER_REG, lane);
13865         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
13866                         MDIO_AN_REG_LP_AUTO_NEG, &base_page);
13867         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
13868                         MDIO_AN_REG_LP_AUTO_NEG2, &next_page);
13869         bnx2x_set_aer_mmd(params, phy);
13870
13871         /* CL73 has not begun yet */
13872         if (base_page == 0) {
13873                 if (!(params->link_attr_sync & LINK_ATTR_SYNC_KR2_ENABLE)) {
13874                         bnx2x_kr2_recovery(params, vars, phy);
13875                         DP(NETIF_MSG_LINK, "No BP\n");
13876                 }
13877                 return;
13878         }
13879
13880         /* In case NP bit is not set in the BasePage, or it is set,
13881          * but only KX is advertised, declare this link partner as non-KR2
13882          * device.
13883          */
13884         not_kr2_device = (((base_page & 0x8000) == 0) ||
13885                           (((base_page & 0x8000) &&
13886                             ((next_page & 0xe0) == 0x20))));
13887
13888         /* In case KR2 is already disabled, check if we need to re-enable it */
13889         if (!(params->link_attr_sync & LINK_ATTR_SYNC_KR2_ENABLE)) {
13890                 if (!not_kr2_device) {
13891                         DP(NETIF_MSG_LINK, "BP=0x%x, NP=0x%x\n", base_page,
13892                            next_page);
13893                         bnx2x_kr2_recovery(params, vars, phy);
13894                 }
13895                 return;
13896         }
13897         /* KR2 is enabled, but not KR2 device */
13898         if (not_kr2_device) {
13899                 /* Disable KR2 on both lanes */
13900                 DP(NETIF_MSG_LINK, "BP=0x%x, NP=0x%x\n", base_page, next_page);
13901                 bnx2x_disable_kr2(params, vars, phy);
13902                 /* Restart AN on leading lane */
13903                 bnx2x_warpcore_restart_AN_KR(phy, params);
13904                 return;
13905         }
13906 }
13907
13908 void bnx2x_period_func(struct link_params *params, struct link_vars *vars)
13909 {
13910         u16 phy_idx;
13911         struct bnx2x *bp = params->bp;
13912         for (phy_idx = INT_PHY; phy_idx < MAX_PHYS; phy_idx++) {
13913                 if (params->phy[phy_idx].flags & FLAGS_TX_ERROR_CHECK) {
13914                         bnx2x_set_aer_mmd(params, &params->phy[phy_idx]);
13915                         if (bnx2x_check_half_open_conn(params, vars, 1) !=
13916                             0)
13917                                 DP(NETIF_MSG_LINK, "Fault detection failed\n");
13918                         break;
13919                 }
13920         }
13921
13922         if (CHIP_IS_E3(bp)) {
13923                 struct bnx2x_phy *phy = &params->phy[INT_PHY];
13924                 bnx2x_set_aer_mmd(params, phy);
13925                 if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
13926                      (phy->speed_cap_mask &
13927                       PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)) ||
13928                     (phy->req_line_speed == SPEED_20000))
13929                         bnx2x_check_kr2_wa(params, vars, phy);
13930                 bnx2x_check_over_curr(params, vars);
13931                 if (vars->rx_tx_asic_rst)
13932                         bnx2x_warpcore_config_runtime(phy, params, vars);
13933
13934                 if ((REG_RD(bp, params->shmem_base +
13935                             offsetof(struct shmem_region, dev_info.
13936                                 port_hw_config[params->port].default_cfg))
13937                     & PORT_HW_CFG_NET_SERDES_IF_MASK) ==
13938                     PORT_HW_CFG_NET_SERDES_IF_SFI) {
13939                         if (bnx2x_is_sfp_module_plugged(phy, params)) {
13940                                 bnx2x_sfp_tx_fault_detection(phy, params, vars);
13941                         } else if (vars->link_status &
13942                                 LINK_STATUS_SFP_TX_FAULT) {
13943                                 /* Clean trail, interrupt corrects the leds */
13944                                 vars->link_status &= ~LINK_STATUS_SFP_TX_FAULT;
13945                                 vars->phy_flags &= ~PHY_SFP_TX_FAULT_FLAG;
13946                                 /* Update link status in the shared memory */
13947                                 bnx2x_update_mng(params, vars->link_status);
13948                         }
13949                 }
13950         }
13951 }
13952
13953 u8 bnx2x_fan_failure_det_req(struct bnx2x *bp,
13954                              u32 shmem_base,
13955                              u32 shmem2_base,
13956                              u8 port)
13957 {
13958         u8 phy_index, fan_failure_det_req = 0;
13959         struct bnx2x_phy phy;
13960         for (phy_index = EXT_PHY1; phy_index < MAX_PHYS;
13961               phy_index++) {
13962                 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
13963                                        port, &phy)
13964                     != 0) {
13965                         DP(NETIF_MSG_LINK, "populate phy failed\n");
13966                         return 0;
13967                 }
13968                 fan_failure_det_req |= (phy.flags &
13969                                         FLAGS_FAN_FAILURE_DET_REQ);
13970         }
13971         return fan_failure_det_req;
13972 }
13973
13974 void bnx2x_hw_reset_phy(struct link_params *params)
13975 {
13976         u8 phy_index;
13977         struct bnx2x *bp = params->bp;
13978         bnx2x_update_mng(params, 0);
13979         bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + params->port*4,
13980                        (NIG_MASK_XGXS0_LINK_STATUS |
13981                         NIG_MASK_XGXS0_LINK10G |
13982                         NIG_MASK_SERDES0_LINK_STATUS |
13983                         NIG_MASK_MI_INT));
13984
13985         for (phy_index = INT_PHY; phy_index < MAX_PHYS;
13986               phy_index++) {
13987                 if (params->phy[phy_index].hw_reset) {
13988                         params->phy[phy_index].hw_reset(
13989                                 &params->phy[phy_index],
13990                                 params);
13991                         params->phy[phy_index] = phy_null;
13992                 }
13993         }
13994 }
13995
13996 void bnx2x_init_mod_abs_int(struct bnx2x *bp, struct link_vars *vars,
13997                             u32 chip_id, u32 shmem_base, u32 shmem2_base,
13998                             u8 port)
13999 {
14000         u8 gpio_num = 0xff, gpio_port = 0xff, phy_index;
14001         u32 val;
14002         u32 offset, aeu_mask, swap_val, swap_override, sync_offset;
14003         if (CHIP_IS_E3(bp)) {
14004                 if (bnx2x_get_mod_abs_int_cfg(bp, chip_id,
14005                                               shmem_base,
14006                                               port,
14007                                               &gpio_num,
14008                                               &gpio_port) != 0)
14009                         return;
14010         } else {
14011                 struct bnx2x_phy phy;
14012                 for (phy_index = EXT_PHY1; phy_index < MAX_PHYS;
14013                       phy_index++) {
14014                         if (bnx2x_populate_phy(bp, phy_index, shmem_base,
14015                                                shmem2_base, port, &phy)
14016                             != 0) {
14017                                 DP(NETIF_MSG_LINK, "populate phy failed\n");
14018                                 return;
14019                         }
14020                         if (phy.type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726) {
14021                                 gpio_num = MISC_REGISTERS_GPIO_3;
14022                                 gpio_port = port;
14023                                 break;
14024                         }
14025                 }
14026         }
14027
14028         if (gpio_num == 0xff)
14029                 return;
14030
14031         /* Set GPIO3 to trigger SFP+ module insertion/removal */
14032         bnx2x_set_gpio(bp, gpio_num, MISC_REGISTERS_GPIO_INPUT_HI_Z, gpio_port);
14033
14034         swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
14035         swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
14036         gpio_port ^= (swap_val && swap_override);
14037
14038         vars->aeu_int_mask = AEU_INPUTS_ATTN_BITS_GPIO0_FUNCTION_0 <<
14039                 (gpio_num + (gpio_port << 2));
14040
14041         sync_offset = shmem_base +
14042                 offsetof(struct shmem_region,
14043                          dev_info.port_hw_config[port].aeu_int_mask);
14044         REG_WR(bp, sync_offset, vars->aeu_int_mask);
14045
14046         DP(NETIF_MSG_LINK, "Setting MOD_ABS (GPIO%d_P%d) AEU to 0x%x\n",
14047                        gpio_num, gpio_port, vars->aeu_int_mask);
14048
14049         if (port == 0)
14050                 offset = MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0;
14051         else
14052                 offset = MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0;
14053
14054         /* Open appropriate AEU for interrupts */
14055         aeu_mask = REG_RD(bp, offset);
14056         aeu_mask |= vars->aeu_int_mask;
14057         REG_WR(bp, offset, aeu_mask);
14058
14059         /* Enable the GPIO to trigger interrupt */
14060         val = REG_RD(bp, MISC_REG_GPIO_EVENT_EN);
14061         val |= 1 << (gpio_num + (gpio_port << 2));
14062         REG_WR(bp, MISC_REG_GPIO_EVENT_EN, val);
14063 }