1 /* bnx2.c: Broadcom NX2 network driver.
3 * Copyright (c) 2004-2011 Broadcom Corporation
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
9 * Written by: Michael Chan (mchan@broadcom.com)
12 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
14 #include <linux/module.h>
15 #include <linux/moduleparam.h>
17 #include <linux/kernel.h>
18 #include <linux/timer.h>
19 #include <linux/errno.h>
20 #include <linux/ioport.h>
21 #include <linux/slab.h>
22 #include <linux/vmalloc.h>
23 #include <linux/interrupt.h>
24 #include <linux/pci.h>
25 #include <linux/init.h>
26 #include <linux/netdevice.h>
27 #include <linux/etherdevice.h>
28 #include <linux/skbuff.h>
29 #include <linux/dma-mapping.h>
30 #include <linux/bitops.h>
33 #include <linux/delay.h>
34 #include <asm/byteorder.h>
36 #include <linux/time.h>
37 #include <linux/ethtool.h>
38 #include <linux/mii.h>
40 #include <linux/if_vlan.h>
43 #include <net/checksum.h>
44 #include <linux/workqueue.h>
45 #include <linux/crc32.h>
46 #include <linux/prefetch.h>
47 #include <linux/cache.h>
48 #include <linux/firmware.h>
49 #include <linux/log2.h>
50 #include <linux/aer.h>
52 #if defined(CONFIG_CNIC) || defined(CONFIG_CNIC_MODULE)
59 #define DRV_MODULE_NAME "bnx2"
60 #define DRV_MODULE_VERSION "2.2.1"
61 #define DRV_MODULE_RELDATE "Dec 18, 2011"
62 #define FW_MIPS_FILE_06 "bnx2/bnx2-mips-06-6.2.3.fw"
63 #define FW_RV2P_FILE_06 "bnx2/bnx2-rv2p-06-6.0.15.fw"
64 #define FW_MIPS_FILE_09 "bnx2/bnx2-mips-09-6.2.1b.fw"
65 #define FW_RV2P_FILE_09_Ax "bnx2/bnx2-rv2p-09ax-6.0.17.fw"
66 #define FW_RV2P_FILE_09 "bnx2/bnx2-rv2p-09-6.0.17.fw"
68 #define RUN_AT(x) (jiffies + (x))
70 /* Time in jiffies before concluding the transmitter is hung. */
71 #define TX_TIMEOUT (5*HZ)
73 static char version[] __devinitdata =
74 "Broadcom NetXtreme II Gigabit Ethernet Driver " DRV_MODULE_NAME " v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
76 MODULE_AUTHOR("Michael Chan <mchan@broadcom.com>");
77 MODULE_DESCRIPTION("Broadcom NetXtreme II BCM5706/5708/5709/5716 Driver");
78 MODULE_LICENSE("GPL");
79 MODULE_VERSION(DRV_MODULE_VERSION);
80 MODULE_FIRMWARE(FW_MIPS_FILE_06);
81 MODULE_FIRMWARE(FW_RV2P_FILE_06);
82 MODULE_FIRMWARE(FW_MIPS_FILE_09);
83 MODULE_FIRMWARE(FW_RV2P_FILE_09);
84 MODULE_FIRMWARE(FW_RV2P_FILE_09_Ax);
86 static int disable_msi = 0;
88 module_param(disable_msi, int, 0);
89 MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
105 /* indexed by board_t, above */
108 } board_info[] __devinitdata = {
109 { "Broadcom NetXtreme II BCM5706 1000Base-T" },
110 { "HP NC370T Multifunction Gigabit Server Adapter" },
111 { "HP NC370i Multifunction Gigabit Server Adapter" },
112 { "Broadcom NetXtreme II BCM5706 1000Base-SX" },
113 { "HP NC370F Multifunction Gigabit Server Adapter" },
114 { "Broadcom NetXtreme II BCM5708 1000Base-T" },
115 { "Broadcom NetXtreme II BCM5708 1000Base-SX" },
116 { "Broadcom NetXtreme II BCM5709 1000Base-T" },
117 { "Broadcom NetXtreme II BCM5709 1000Base-SX" },
118 { "Broadcom NetXtreme II BCM5716 1000Base-T" },
119 { "Broadcom NetXtreme II BCM5716 1000Base-SX" },
122 static DEFINE_PCI_DEVICE_TABLE(bnx2_pci_tbl) = {
123 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
124 PCI_VENDOR_ID_HP, 0x3101, 0, 0, NC370T },
125 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
126 PCI_VENDOR_ID_HP, 0x3106, 0, 0, NC370I },
127 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
128 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706 },
129 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5708,
130 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5708 },
131 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706S,
132 PCI_VENDOR_ID_HP, 0x3102, 0, 0, NC370F },
133 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706S,
134 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706S },
135 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5708S,
136 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5708S },
137 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5709,
138 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5709 },
139 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5709S,
140 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5709S },
141 { PCI_VENDOR_ID_BROADCOM, 0x163b,
142 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5716 },
143 { PCI_VENDOR_ID_BROADCOM, 0x163c,
144 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5716S },
148 static const struct flash_spec flash_table[] =
150 #define BUFFERED_FLAGS (BNX2_NV_BUFFERED | BNX2_NV_TRANSLATE)
151 #define NONBUFFERED_FLAGS (BNX2_NV_WREN)
153 {0x00000000, 0x40830380, 0x009f0081, 0xa184a053, 0xaf000400,
154 BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
155 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
157 /* Expansion entry 0001 */
158 {0x08000002, 0x4b808201, 0x00050081, 0x03840253, 0xaf020406,
159 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
160 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
162 /* Saifun SA25F010 (non-buffered flash) */
163 /* strap, cfg1, & write1 need updates */
164 {0x04000001, 0x47808201, 0x00050081, 0x03840253, 0xaf020406,
165 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
166 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*2,
167 "Non-buffered flash (128kB)"},
168 /* Saifun SA25F020 (non-buffered flash) */
169 /* strap, cfg1, & write1 need updates */
170 {0x0c000003, 0x4f808201, 0x00050081, 0x03840253, 0xaf020406,
171 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
172 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*4,
173 "Non-buffered flash (256kB)"},
174 /* Expansion entry 0100 */
175 {0x11000000, 0x53808201, 0x00050081, 0x03840253, 0xaf020406,
176 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
177 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
179 /* Entry 0101: ST M45PE10 (non-buffered flash, TetonII B0) */
180 {0x19000002, 0x5b808201, 0x000500db, 0x03840253, 0xaf020406,
181 NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
182 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*2,
183 "Entry 0101: ST M45PE10 (128kB non-bufferred)"},
184 /* Entry 0110: ST M45PE20 (non-buffered flash)*/
185 {0x15000001, 0x57808201, 0x000500db, 0x03840253, 0xaf020406,
186 NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
187 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*4,
188 "Entry 0110: ST M45PE20 (256kB non-bufferred)"},
189 /* Saifun SA25F005 (non-buffered flash) */
190 /* strap, cfg1, & write1 need updates */
191 {0x1d000003, 0x5f808201, 0x00050081, 0x03840253, 0xaf020406,
192 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
193 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE,
194 "Non-buffered flash (64kB)"},
196 {0x22000000, 0x62808380, 0x009f0081, 0xa184a053, 0xaf000400,
197 BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
198 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
200 /* Expansion entry 1001 */
201 {0x2a000002, 0x6b808201, 0x00050081, 0x03840253, 0xaf020406,
202 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
203 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
205 /* Expansion entry 1010 */
206 {0x26000001, 0x67808201, 0x00050081, 0x03840253, 0xaf020406,
207 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
208 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
210 /* ATMEL AT45DB011B (buffered flash) */
211 {0x2e000003, 0x6e808273, 0x00570081, 0x68848353, 0xaf000400,
212 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
213 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE,
214 "Buffered flash (128kB)"},
215 /* Expansion entry 1100 */
216 {0x33000000, 0x73808201, 0x00050081, 0x03840253, 0xaf020406,
217 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
218 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
220 /* Expansion entry 1101 */
221 {0x3b000002, 0x7b808201, 0x00050081, 0x03840253, 0xaf020406,
222 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
223 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
225 /* Ateml Expansion entry 1110 */
226 {0x37000001, 0x76808273, 0x00570081, 0x68848353, 0xaf000400,
227 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
228 BUFFERED_FLASH_BYTE_ADDR_MASK, 0,
229 "Entry 1110 (Atmel)"},
230 /* ATMEL AT45DB021B (buffered flash) */
231 {0x3f000003, 0x7e808273, 0x00570081, 0x68848353, 0xaf000400,
232 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
233 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE*2,
234 "Buffered flash (256kB)"},
237 static const struct flash_spec flash_5709 = {
238 .flags = BNX2_NV_BUFFERED,
239 .page_bits = BCM5709_FLASH_PAGE_BITS,
240 .page_size = BCM5709_FLASH_PAGE_SIZE,
241 .addr_mask = BCM5709_FLASH_BYTE_ADDR_MASK,
242 .total_size = BUFFERED_FLASH_TOTAL_SIZE*2,
243 .name = "5709 Buffered flash (256kB)",
246 MODULE_DEVICE_TABLE(pci, bnx2_pci_tbl);
248 static void bnx2_init_napi(struct bnx2 *bp);
249 static void bnx2_del_napi(struct bnx2 *bp);
251 static inline u32 bnx2_tx_avail(struct bnx2 *bp, struct bnx2_tx_ring_info *txr)
255 /* Tell compiler to fetch tx_prod and tx_cons from memory. */
258 /* The ring uses 256 indices for 255 entries, one of them
259 * needs to be skipped.
261 diff = txr->tx_prod - txr->tx_cons;
262 if (unlikely(diff >= TX_DESC_CNT)) {
264 if (diff == TX_DESC_CNT)
265 diff = MAX_TX_DESC_CNT;
267 return bp->tx_ring_size - diff;
271 bnx2_reg_rd_ind(struct bnx2 *bp, u32 offset)
275 spin_lock_bh(&bp->indirect_lock);
276 REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);
277 val = REG_RD(bp, BNX2_PCICFG_REG_WINDOW);
278 spin_unlock_bh(&bp->indirect_lock);
283 bnx2_reg_wr_ind(struct bnx2 *bp, u32 offset, u32 val)
285 spin_lock_bh(&bp->indirect_lock);
286 REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);
287 REG_WR(bp, BNX2_PCICFG_REG_WINDOW, val);
288 spin_unlock_bh(&bp->indirect_lock);
292 bnx2_shmem_wr(struct bnx2 *bp, u32 offset, u32 val)
294 bnx2_reg_wr_ind(bp, bp->shmem_base + offset, val);
298 bnx2_shmem_rd(struct bnx2 *bp, u32 offset)
300 return bnx2_reg_rd_ind(bp, bp->shmem_base + offset);
304 bnx2_ctx_wr(struct bnx2 *bp, u32 cid_addr, u32 offset, u32 val)
307 spin_lock_bh(&bp->indirect_lock);
308 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
311 REG_WR(bp, BNX2_CTX_CTX_DATA, val);
312 REG_WR(bp, BNX2_CTX_CTX_CTRL,
313 offset | BNX2_CTX_CTX_CTRL_WRITE_REQ);
314 for (i = 0; i < 5; i++) {
315 val = REG_RD(bp, BNX2_CTX_CTX_CTRL);
316 if ((val & BNX2_CTX_CTX_CTRL_WRITE_REQ) == 0)
321 REG_WR(bp, BNX2_CTX_DATA_ADR, offset);
322 REG_WR(bp, BNX2_CTX_DATA, val);
324 spin_unlock_bh(&bp->indirect_lock);
329 bnx2_drv_ctl(struct net_device *dev, struct drv_ctl_info *info)
331 struct bnx2 *bp = netdev_priv(dev);
332 struct drv_ctl_io *io = &info->data.io;
335 case DRV_CTL_IO_WR_CMD:
336 bnx2_reg_wr_ind(bp, io->offset, io->data);
338 case DRV_CTL_IO_RD_CMD:
339 io->data = bnx2_reg_rd_ind(bp, io->offset);
341 case DRV_CTL_CTX_WR_CMD:
342 bnx2_ctx_wr(bp, io->cid_addr, io->offset, io->data);
350 static void bnx2_setup_cnic_irq_info(struct bnx2 *bp)
352 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
353 struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
356 if (bp->flags & BNX2_FLAG_USING_MSIX) {
357 cp->drv_state |= CNIC_DRV_STATE_USING_MSIX;
358 bnapi->cnic_present = 0;
359 sb_id = bp->irq_nvecs;
360 cp->irq_arr[0].irq_flags |= CNIC_IRQ_FL_MSIX;
362 cp->drv_state &= ~CNIC_DRV_STATE_USING_MSIX;
363 bnapi->cnic_tag = bnapi->last_status_idx;
364 bnapi->cnic_present = 1;
366 cp->irq_arr[0].irq_flags &= ~CNIC_IRQ_FL_MSIX;
369 cp->irq_arr[0].vector = bp->irq_tbl[sb_id].vector;
370 cp->irq_arr[0].status_blk = (void *)
371 ((unsigned long) bnapi->status_blk.msi +
372 (BNX2_SBLK_MSIX_ALIGN_SIZE * sb_id));
373 cp->irq_arr[0].status_blk_num = sb_id;
377 static int bnx2_register_cnic(struct net_device *dev, struct cnic_ops *ops,
380 struct bnx2 *bp = netdev_priv(dev);
381 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
386 if (cp->drv_state & CNIC_DRV_STATE_REGD)
389 if (!bnx2_reg_rd_ind(bp, BNX2_FW_MAX_ISCSI_CONN))
392 bp->cnic_data = data;
393 rcu_assign_pointer(bp->cnic_ops, ops);
396 cp->drv_state = CNIC_DRV_STATE_REGD;
398 bnx2_setup_cnic_irq_info(bp);
403 static int bnx2_unregister_cnic(struct net_device *dev)
405 struct bnx2 *bp = netdev_priv(dev);
406 struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
407 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
409 mutex_lock(&bp->cnic_lock);
411 bnapi->cnic_present = 0;
412 RCU_INIT_POINTER(bp->cnic_ops, NULL);
413 mutex_unlock(&bp->cnic_lock);
418 struct cnic_eth_dev *bnx2_cnic_probe(struct net_device *dev)
420 struct bnx2 *bp = netdev_priv(dev);
421 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
423 if (!cp->max_iscsi_conn)
426 cp->drv_owner = THIS_MODULE;
427 cp->chip_id = bp->chip_id;
429 cp->io_base = bp->regview;
430 cp->drv_ctl = bnx2_drv_ctl;
431 cp->drv_register_cnic = bnx2_register_cnic;
432 cp->drv_unregister_cnic = bnx2_unregister_cnic;
436 EXPORT_SYMBOL(bnx2_cnic_probe);
439 bnx2_cnic_stop(struct bnx2 *bp)
441 struct cnic_ops *c_ops;
442 struct cnic_ctl_info info;
444 mutex_lock(&bp->cnic_lock);
445 c_ops = rcu_dereference_protected(bp->cnic_ops,
446 lockdep_is_held(&bp->cnic_lock));
448 info.cmd = CNIC_CTL_STOP_CMD;
449 c_ops->cnic_ctl(bp->cnic_data, &info);
451 mutex_unlock(&bp->cnic_lock);
455 bnx2_cnic_start(struct bnx2 *bp)
457 struct cnic_ops *c_ops;
458 struct cnic_ctl_info info;
460 mutex_lock(&bp->cnic_lock);
461 c_ops = rcu_dereference_protected(bp->cnic_ops,
462 lockdep_is_held(&bp->cnic_lock));
464 if (!(bp->flags & BNX2_FLAG_USING_MSIX)) {
465 struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
467 bnapi->cnic_tag = bnapi->last_status_idx;
469 info.cmd = CNIC_CTL_START_CMD;
470 c_ops->cnic_ctl(bp->cnic_data, &info);
472 mutex_unlock(&bp->cnic_lock);
478 bnx2_cnic_stop(struct bnx2 *bp)
483 bnx2_cnic_start(struct bnx2 *bp)
490 bnx2_read_phy(struct bnx2 *bp, u32 reg, u32 *val)
495 if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
496 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
497 val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL;
499 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
500 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
505 val1 = (bp->phy_addr << 21) | (reg << 16) |
506 BNX2_EMAC_MDIO_COMM_COMMAND_READ | BNX2_EMAC_MDIO_COMM_DISEXT |
507 BNX2_EMAC_MDIO_COMM_START_BUSY;
508 REG_WR(bp, BNX2_EMAC_MDIO_COMM, val1);
510 for (i = 0; i < 50; i++) {
513 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
514 if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) {
517 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
518 val1 &= BNX2_EMAC_MDIO_COMM_DATA;
524 if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY) {
533 if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
534 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
535 val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL;
537 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
538 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
547 bnx2_write_phy(struct bnx2 *bp, u32 reg, u32 val)
552 if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
553 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
554 val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL;
556 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
557 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
562 val1 = (bp->phy_addr << 21) | (reg << 16) | val |
563 BNX2_EMAC_MDIO_COMM_COMMAND_WRITE |
564 BNX2_EMAC_MDIO_COMM_START_BUSY | BNX2_EMAC_MDIO_COMM_DISEXT;
565 REG_WR(bp, BNX2_EMAC_MDIO_COMM, val1);
567 for (i = 0; i < 50; i++) {
570 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
571 if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) {
577 if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)
582 if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
583 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
584 val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL;
586 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
587 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
596 bnx2_disable_int(struct bnx2 *bp)
599 struct bnx2_napi *bnapi;
601 for (i = 0; i < bp->irq_nvecs; i++) {
602 bnapi = &bp->bnx2_napi[i];
603 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
604 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
606 REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD);
610 bnx2_enable_int(struct bnx2 *bp)
613 struct bnx2_napi *bnapi;
615 for (i = 0; i < bp->irq_nvecs; i++) {
616 bnapi = &bp->bnx2_napi[i];
618 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
619 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
620 BNX2_PCICFG_INT_ACK_CMD_MASK_INT |
621 bnapi->last_status_idx);
623 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
624 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
625 bnapi->last_status_idx);
627 REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW);
631 bnx2_disable_int_sync(struct bnx2 *bp)
635 atomic_inc(&bp->intr_sem);
636 if (!netif_running(bp->dev))
639 bnx2_disable_int(bp);
640 for (i = 0; i < bp->irq_nvecs; i++)
641 synchronize_irq(bp->irq_tbl[i].vector);
645 bnx2_napi_disable(struct bnx2 *bp)
649 for (i = 0; i < bp->irq_nvecs; i++)
650 napi_disable(&bp->bnx2_napi[i].napi);
654 bnx2_napi_enable(struct bnx2 *bp)
658 for (i = 0; i < bp->irq_nvecs; i++)
659 napi_enable(&bp->bnx2_napi[i].napi);
663 bnx2_netif_stop(struct bnx2 *bp, bool stop_cnic)
667 if (netif_running(bp->dev)) {
668 bnx2_napi_disable(bp);
669 netif_tx_disable(bp->dev);
671 bnx2_disable_int_sync(bp);
672 netif_carrier_off(bp->dev); /* prevent tx timeout */
676 bnx2_netif_start(struct bnx2 *bp, bool start_cnic)
678 if (atomic_dec_and_test(&bp->intr_sem)) {
679 if (netif_running(bp->dev)) {
680 netif_tx_wake_all_queues(bp->dev);
681 spin_lock_bh(&bp->phy_lock);
683 netif_carrier_on(bp->dev);
684 spin_unlock_bh(&bp->phy_lock);
685 bnx2_napi_enable(bp);
694 bnx2_free_tx_mem(struct bnx2 *bp)
698 for (i = 0; i < bp->num_tx_rings; i++) {
699 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
700 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
702 if (txr->tx_desc_ring) {
703 dma_free_coherent(&bp->pdev->dev, TXBD_RING_SIZE,
705 txr->tx_desc_mapping);
706 txr->tx_desc_ring = NULL;
708 kfree(txr->tx_buf_ring);
709 txr->tx_buf_ring = NULL;
714 bnx2_free_rx_mem(struct bnx2 *bp)
718 for (i = 0; i < bp->num_rx_rings; i++) {
719 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
720 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
723 for (j = 0; j < bp->rx_max_ring; j++) {
724 if (rxr->rx_desc_ring[j])
725 dma_free_coherent(&bp->pdev->dev, RXBD_RING_SIZE,
726 rxr->rx_desc_ring[j],
727 rxr->rx_desc_mapping[j]);
728 rxr->rx_desc_ring[j] = NULL;
730 vfree(rxr->rx_buf_ring);
731 rxr->rx_buf_ring = NULL;
733 for (j = 0; j < bp->rx_max_pg_ring; j++) {
734 if (rxr->rx_pg_desc_ring[j])
735 dma_free_coherent(&bp->pdev->dev, RXBD_RING_SIZE,
736 rxr->rx_pg_desc_ring[j],
737 rxr->rx_pg_desc_mapping[j]);
738 rxr->rx_pg_desc_ring[j] = NULL;
740 vfree(rxr->rx_pg_ring);
741 rxr->rx_pg_ring = NULL;
746 bnx2_alloc_tx_mem(struct bnx2 *bp)
750 for (i = 0; i < bp->num_tx_rings; i++) {
751 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
752 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
754 txr->tx_buf_ring = kzalloc(SW_TXBD_RING_SIZE, GFP_KERNEL);
755 if (txr->tx_buf_ring == NULL)
759 dma_alloc_coherent(&bp->pdev->dev, TXBD_RING_SIZE,
760 &txr->tx_desc_mapping, GFP_KERNEL);
761 if (txr->tx_desc_ring == NULL)
768 bnx2_alloc_rx_mem(struct bnx2 *bp)
772 for (i = 0; i < bp->num_rx_rings; i++) {
773 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
774 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
778 vzalloc(SW_RXBD_RING_SIZE * bp->rx_max_ring);
779 if (rxr->rx_buf_ring == NULL)
782 for (j = 0; j < bp->rx_max_ring; j++) {
783 rxr->rx_desc_ring[j] =
784 dma_alloc_coherent(&bp->pdev->dev,
786 &rxr->rx_desc_mapping[j],
788 if (rxr->rx_desc_ring[j] == NULL)
793 if (bp->rx_pg_ring_size) {
794 rxr->rx_pg_ring = vzalloc(SW_RXPG_RING_SIZE *
796 if (rxr->rx_pg_ring == NULL)
801 for (j = 0; j < bp->rx_max_pg_ring; j++) {
802 rxr->rx_pg_desc_ring[j] =
803 dma_alloc_coherent(&bp->pdev->dev,
805 &rxr->rx_pg_desc_mapping[j],
807 if (rxr->rx_pg_desc_ring[j] == NULL)
816 bnx2_free_mem(struct bnx2 *bp)
819 struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
821 bnx2_free_tx_mem(bp);
822 bnx2_free_rx_mem(bp);
824 for (i = 0; i < bp->ctx_pages; i++) {
825 if (bp->ctx_blk[i]) {
826 dma_free_coherent(&bp->pdev->dev, BCM_PAGE_SIZE,
828 bp->ctx_blk_mapping[i]);
829 bp->ctx_blk[i] = NULL;
832 if (bnapi->status_blk.msi) {
833 dma_free_coherent(&bp->pdev->dev, bp->status_stats_size,
834 bnapi->status_blk.msi,
835 bp->status_blk_mapping);
836 bnapi->status_blk.msi = NULL;
837 bp->stats_blk = NULL;
842 bnx2_alloc_mem(struct bnx2 *bp)
844 int i, status_blk_size, err;
845 struct bnx2_napi *bnapi;
848 /* Combine status and statistics blocks into one allocation. */
849 status_blk_size = L1_CACHE_ALIGN(sizeof(struct status_block));
850 if (bp->flags & BNX2_FLAG_MSIX_CAP)
851 status_blk_size = L1_CACHE_ALIGN(BNX2_MAX_MSIX_HW_VEC *
852 BNX2_SBLK_MSIX_ALIGN_SIZE);
853 bp->status_stats_size = status_blk_size +
854 sizeof(struct statistics_block);
856 status_blk = dma_alloc_coherent(&bp->pdev->dev, bp->status_stats_size,
857 &bp->status_blk_mapping, GFP_KERNEL);
858 if (status_blk == NULL)
861 memset(status_blk, 0, bp->status_stats_size);
863 bnapi = &bp->bnx2_napi[0];
864 bnapi->status_blk.msi = status_blk;
865 bnapi->hw_tx_cons_ptr =
866 &bnapi->status_blk.msi->status_tx_quick_consumer_index0;
867 bnapi->hw_rx_cons_ptr =
868 &bnapi->status_blk.msi->status_rx_quick_consumer_index0;
869 if (bp->flags & BNX2_FLAG_MSIX_CAP) {
870 for (i = 1; i < bp->irq_nvecs; i++) {
871 struct status_block_msix *sblk;
873 bnapi = &bp->bnx2_napi[i];
875 sblk = (void *) (status_blk +
876 BNX2_SBLK_MSIX_ALIGN_SIZE * i);
877 bnapi->status_blk.msix = sblk;
878 bnapi->hw_tx_cons_ptr =
879 &sblk->status_tx_quick_consumer_index;
880 bnapi->hw_rx_cons_ptr =
881 &sblk->status_rx_quick_consumer_index;
882 bnapi->int_num = i << 24;
886 bp->stats_blk = status_blk + status_blk_size;
888 bp->stats_blk_mapping = bp->status_blk_mapping + status_blk_size;
890 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
891 bp->ctx_pages = 0x2000 / BCM_PAGE_SIZE;
892 if (bp->ctx_pages == 0)
894 for (i = 0; i < bp->ctx_pages; i++) {
895 bp->ctx_blk[i] = dma_alloc_coherent(&bp->pdev->dev,
897 &bp->ctx_blk_mapping[i],
899 if (bp->ctx_blk[i] == NULL)
904 err = bnx2_alloc_rx_mem(bp);
908 err = bnx2_alloc_tx_mem(bp);
920 bnx2_report_fw_link(struct bnx2 *bp)
922 u32 fw_link_status = 0;
924 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
930 switch (bp->line_speed) {
932 if (bp->duplex == DUPLEX_HALF)
933 fw_link_status = BNX2_LINK_STATUS_10HALF;
935 fw_link_status = BNX2_LINK_STATUS_10FULL;
938 if (bp->duplex == DUPLEX_HALF)
939 fw_link_status = BNX2_LINK_STATUS_100HALF;
941 fw_link_status = BNX2_LINK_STATUS_100FULL;
944 if (bp->duplex == DUPLEX_HALF)
945 fw_link_status = BNX2_LINK_STATUS_1000HALF;
947 fw_link_status = BNX2_LINK_STATUS_1000FULL;
950 if (bp->duplex == DUPLEX_HALF)
951 fw_link_status = BNX2_LINK_STATUS_2500HALF;
953 fw_link_status = BNX2_LINK_STATUS_2500FULL;
957 fw_link_status |= BNX2_LINK_STATUS_LINK_UP;
960 fw_link_status |= BNX2_LINK_STATUS_AN_ENABLED;
962 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
963 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
965 if (!(bmsr & BMSR_ANEGCOMPLETE) ||
966 bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT)
967 fw_link_status |= BNX2_LINK_STATUS_PARALLEL_DET;
969 fw_link_status |= BNX2_LINK_STATUS_AN_COMPLETE;
973 fw_link_status = BNX2_LINK_STATUS_LINK_DOWN;
975 bnx2_shmem_wr(bp, BNX2_LINK_STATUS, fw_link_status);
979 bnx2_xceiver_str(struct bnx2 *bp)
981 return (bp->phy_port == PORT_FIBRE) ? "SerDes" :
982 ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) ? "Remote Copper" :
987 bnx2_report_link(struct bnx2 *bp)
990 netif_carrier_on(bp->dev);
991 netdev_info(bp->dev, "NIC %s Link is Up, %d Mbps %s duplex",
992 bnx2_xceiver_str(bp),
994 bp->duplex == DUPLEX_FULL ? "full" : "half");
997 if (bp->flow_ctrl & FLOW_CTRL_RX) {
998 pr_cont(", receive ");
999 if (bp->flow_ctrl & FLOW_CTRL_TX)
1000 pr_cont("& transmit ");
1003 pr_cont(", transmit ");
1005 pr_cont("flow control ON");
1009 netif_carrier_off(bp->dev);
1010 netdev_err(bp->dev, "NIC %s Link is Down\n",
1011 bnx2_xceiver_str(bp));
1014 bnx2_report_fw_link(bp);
1018 bnx2_resolve_flow_ctrl(struct bnx2 *bp)
1020 u32 local_adv, remote_adv;
1023 if ((bp->autoneg & (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) !=
1024 (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) {
1026 if (bp->duplex == DUPLEX_FULL) {
1027 bp->flow_ctrl = bp->req_flow_ctrl;
1032 if (bp->duplex != DUPLEX_FULL) {
1036 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
1037 (CHIP_NUM(bp) == CHIP_NUM_5708)) {
1040 bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val);
1041 if (val & BCM5708S_1000X_STAT1_TX_PAUSE)
1042 bp->flow_ctrl |= FLOW_CTRL_TX;
1043 if (val & BCM5708S_1000X_STAT1_RX_PAUSE)
1044 bp->flow_ctrl |= FLOW_CTRL_RX;
1048 bnx2_read_phy(bp, bp->mii_adv, &local_adv);
1049 bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);
1051 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
1052 u32 new_local_adv = 0;
1053 u32 new_remote_adv = 0;
1055 if (local_adv & ADVERTISE_1000XPAUSE)
1056 new_local_adv |= ADVERTISE_PAUSE_CAP;
1057 if (local_adv & ADVERTISE_1000XPSE_ASYM)
1058 new_local_adv |= ADVERTISE_PAUSE_ASYM;
1059 if (remote_adv & ADVERTISE_1000XPAUSE)
1060 new_remote_adv |= ADVERTISE_PAUSE_CAP;
1061 if (remote_adv & ADVERTISE_1000XPSE_ASYM)
1062 new_remote_adv |= ADVERTISE_PAUSE_ASYM;
1064 local_adv = new_local_adv;
1065 remote_adv = new_remote_adv;
1068 /* See Table 28B-3 of 802.3ab-1999 spec. */
1069 if (local_adv & ADVERTISE_PAUSE_CAP) {
1070 if(local_adv & ADVERTISE_PAUSE_ASYM) {
1071 if (remote_adv & ADVERTISE_PAUSE_CAP) {
1072 bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
1074 else if (remote_adv & ADVERTISE_PAUSE_ASYM) {
1075 bp->flow_ctrl = FLOW_CTRL_RX;
1079 if (remote_adv & ADVERTISE_PAUSE_CAP) {
1080 bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
1084 else if (local_adv & ADVERTISE_PAUSE_ASYM) {
1085 if ((remote_adv & ADVERTISE_PAUSE_CAP) &&
1086 (remote_adv & ADVERTISE_PAUSE_ASYM)) {
1088 bp->flow_ctrl = FLOW_CTRL_TX;
1094 bnx2_5709s_linkup(struct bnx2 *bp)
1100 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_GP_STATUS);
1101 bnx2_read_phy(bp, MII_BNX2_GP_TOP_AN_STATUS1, &val);
1102 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1104 if ((bp->autoneg & AUTONEG_SPEED) == 0) {
1105 bp->line_speed = bp->req_line_speed;
1106 bp->duplex = bp->req_duplex;
1109 speed = val & MII_BNX2_GP_TOP_AN_SPEED_MSK;
1111 case MII_BNX2_GP_TOP_AN_SPEED_10:
1112 bp->line_speed = SPEED_10;
1114 case MII_BNX2_GP_TOP_AN_SPEED_100:
1115 bp->line_speed = SPEED_100;
1117 case MII_BNX2_GP_TOP_AN_SPEED_1G:
1118 case MII_BNX2_GP_TOP_AN_SPEED_1GKV:
1119 bp->line_speed = SPEED_1000;
1121 case MII_BNX2_GP_TOP_AN_SPEED_2_5G:
1122 bp->line_speed = SPEED_2500;
1125 if (val & MII_BNX2_GP_TOP_AN_FD)
1126 bp->duplex = DUPLEX_FULL;
1128 bp->duplex = DUPLEX_HALF;
1133 bnx2_5708s_linkup(struct bnx2 *bp)
1138 bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val);
1139 switch (val & BCM5708S_1000X_STAT1_SPEED_MASK) {
1140 case BCM5708S_1000X_STAT1_SPEED_10:
1141 bp->line_speed = SPEED_10;
1143 case BCM5708S_1000X_STAT1_SPEED_100:
1144 bp->line_speed = SPEED_100;
1146 case BCM5708S_1000X_STAT1_SPEED_1G:
1147 bp->line_speed = SPEED_1000;
1149 case BCM5708S_1000X_STAT1_SPEED_2G5:
1150 bp->line_speed = SPEED_2500;
1153 if (val & BCM5708S_1000X_STAT1_FD)
1154 bp->duplex = DUPLEX_FULL;
1156 bp->duplex = DUPLEX_HALF;
1162 bnx2_5706s_linkup(struct bnx2 *bp)
1164 u32 bmcr, local_adv, remote_adv, common;
1167 bp->line_speed = SPEED_1000;
1169 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1170 if (bmcr & BMCR_FULLDPLX) {
1171 bp->duplex = DUPLEX_FULL;
1174 bp->duplex = DUPLEX_HALF;
1177 if (!(bmcr & BMCR_ANENABLE)) {
1181 bnx2_read_phy(bp, bp->mii_adv, &local_adv);
1182 bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);
1184 common = local_adv & remote_adv;
1185 if (common & (ADVERTISE_1000XHALF | ADVERTISE_1000XFULL)) {
1187 if (common & ADVERTISE_1000XFULL) {
1188 bp->duplex = DUPLEX_FULL;
1191 bp->duplex = DUPLEX_HALF;
1199 bnx2_copper_linkup(struct bnx2 *bp)
1203 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1204 if (bmcr & BMCR_ANENABLE) {
1205 u32 local_adv, remote_adv, common;
1207 bnx2_read_phy(bp, MII_CTRL1000, &local_adv);
1208 bnx2_read_phy(bp, MII_STAT1000, &remote_adv);
1210 common = local_adv & (remote_adv >> 2);
1211 if (common & ADVERTISE_1000FULL) {
1212 bp->line_speed = SPEED_1000;
1213 bp->duplex = DUPLEX_FULL;
1215 else if (common & ADVERTISE_1000HALF) {
1216 bp->line_speed = SPEED_1000;
1217 bp->duplex = DUPLEX_HALF;
1220 bnx2_read_phy(bp, bp->mii_adv, &local_adv);
1221 bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);
1223 common = local_adv & remote_adv;
1224 if (common & ADVERTISE_100FULL) {
1225 bp->line_speed = SPEED_100;
1226 bp->duplex = DUPLEX_FULL;
1228 else if (common & ADVERTISE_100HALF) {
1229 bp->line_speed = SPEED_100;
1230 bp->duplex = DUPLEX_HALF;
1232 else if (common & ADVERTISE_10FULL) {
1233 bp->line_speed = SPEED_10;
1234 bp->duplex = DUPLEX_FULL;
1236 else if (common & ADVERTISE_10HALF) {
1237 bp->line_speed = SPEED_10;
1238 bp->duplex = DUPLEX_HALF;
1247 if (bmcr & BMCR_SPEED100) {
1248 bp->line_speed = SPEED_100;
1251 bp->line_speed = SPEED_10;
1253 if (bmcr & BMCR_FULLDPLX) {
1254 bp->duplex = DUPLEX_FULL;
1257 bp->duplex = DUPLEX_HALF;
1265 bnx2_init_rx_context(struct bnx2 *bp, u32 cid)
1267 u32 val, rx_cid_addr = GET_CID_ADDR(cid);
1269 val = BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE;
1270 val |= BNX2_L2CTX_CTX_TYPE_SIZE_L2;
1273 if (bp->flow_ctrl & FLOW_CTRL_TX)
1274 val |= BNX2_L2CTX_FLOW_CTRL_ENABLE;
1276 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_CTX_TYPE, val);
1280 bnx2_init_all_rx_contexts(struct bnx2 *bp)
1285 for (i = 0, cid = RX_CID; i < bp->num_rx_rings; i++, cid++) {
1288 bnx2_init_rx_context(bp, cid);
1293 bnx2_set_mac_link(struct bnx2 *bp)
1297 REG_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x2620);
1298 if (bp->link_up && (bp->line_speed == SPEED_1000) &&
1299 (bp->duplex == DUPLEX_HALF)) {
1300 REG_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x26ff);
1303 /* Configure the EMAC mode register. */
1304 val = REG_RD(bp, BNX2_EMAC_MODE);
1306 val &= ~(BNX2_EMAC_MODE_PORT | BNX2_EMAC_MODE_HALF_DUPLEX |
1307 BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK |
1308 BNX2_EMAC_MODE_25G_MODE);
1311 switch (bp->line_speed) {
1313 if (CHIP_NUM(bp) != CHIP_NUM_5706) {
1314 val |= BNX2_EMAC_MODE_PORT_MII_10M;
1319 val |= BNX2_EMAC_MODE_PORT_MII;
1322 val |= BNX2_EMAC_MODE_25G_MODE;
1325 val |= BNX2_EMAC_MODE_PORT_GMII;
1330 val |= BNX2_EMAC_MODE_PORT_GMII;
1333 /* Set the MAC to operate in the appropriate duplex mode. */
1334 if (bp->duplex == DUPLEX_HALF)
1335 val |= BNX2_EMAC_MODE_HALF_DUPLEX;
1336 REG_WR(bp, BNX2_EMAC_MODE, val);
1338 /* Enable/disable rx PAUSE. */
1339 bp->rx_mode &= ~BNX2_EMAC_RX_MODE_FLOW_EN;
1341 if (bp->flow_ctrl & FLOW_CTRL_RX)
1342 bp->rx_mode |= BNX2_EMAC_RX_MODE_FLOW_EN;
1343 REG_WR(bp, BNX2_EMAC_RX_MODE, bp->rx_mode);
1345 /* Enable/disable tx PAUSE. */
1346 val = REG_RD(bp, BNX2_EMAC_TX_MODE);
1347 val &= ~BNX2_EMAC_TX_MODE_FLOW_EN;
1349 if (bp->flow_ctrl & FLOW_CTRL_TX)
1350 val |= BNX2_EMAC_TX_MODE_FLOW_EN;
1351 REG_WR(bp, BNX2_EMAC_TX_MODE, val);
1353 /* Acknowledge the interrupt. */
1354 REG_WR(bp, BNX2_EMAC_STATUS, BNX2_EMAC_STATUS_LINK_CHANGE);
1356 bnx2_init_all_rx_contexts(bp);
1360 bnx2_enable_bmsr1(struct bnx2 *bp)
1362 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
1363 (CHIP_NUM(bp) == CHIP_NUM_5709))
1364 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1365 MII_BNX2_BLK_ADDR_GP_STATUS);
1369 bnx2_disable_bmsr1(struct bnx2 *bp)
1371 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
1372 (CHIP_NUM(bp) == CHIP_NUM_5709))
1373 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1374 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1378 bnx2_test_and_enable_2g5(struct bnx2 *bp)
1383 if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
1386 if (bp->autoneg & AUTONEG_SPEED)
1387 bp->advertising |= ADVERTISED_2500baseX_Full;
1389 if (CHIP_NUM(bp) == CHIP_NUM_5709)
1390 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);
1392 bnx2_read_phy(bp, bp->mii_up1, &up1);
1393 if (!(up1 & BCM5708S_UP1_2G5)) {
1394 up1 |= BCM5708S_UP1_2G5;
1395 bnx2_write_phy(bp, bp->mii_up1, up1);
1399 if (CHIP_NUM(bp) == CHIP_NUM_5709)
1400 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1401 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1407 bnx2_test_and_disable_2g5(struct bnx2 *bp)
1412 if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
1415 if (CHIP_NUM(bp) == CHIP_NUM_5709)
1416 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);
1418 bnx2_read_phy(bp, bp->mii_up1, &up1);
1419 if (up1 & BCM5708S_UP1_2G5) {
1420 up1 &= ~BCM5708S_UP1_2G5;
1421 bnx2_write_phy(bp, bp->mii_up1, up1);
1425 if (CHIP_NUM(bp) == CHIP_NUM_5709)
1426 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1427 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1433 bnx2_enable_forced_2g5(struct bnx2 *bp)
1435 u32 uninitialized_var(bmcr);
1438 if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
1441 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
1444 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1445 MII_BNX2_BLK_ADDR_SERDES_DIG);
1446 if (!bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_MISC1, &val)) {
1447 val &= ~MII_BNX2_SD_MISC1_FORCE_MSK;
1448 val |= MII_BNX2_SD_MISC1_FORCE |
1449 MII_BNX2_SD_MISC1_FORCE_2_5G;
1450 bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_MISC1, val);
1453 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1454 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1455 err = bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1457 } else if (CHIP_NUM(bp) == CHIP_NUM_5708) {
1458 err = bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1460 bmcr |= BCM5708S_BMCR_FORCE_2500;
1468 if (bp->autoneg & AUTONEG_SPEED) {
1469 bmcr &= ~BMCR_ANENABLE;
1470 if (bp->req_duplex == DUPLEX_FULL)
1471 bmcr |= BMCR_FULLDPLX;
1473 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
1477 bnx2_disable_forced_2g5(struct bnx2 *bp)
1479 u32 uninitialized_var(bmcr);
1482 if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
1485 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
1488 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1489 MII_BNX2_BLK_ADDR_SERDES_DIG);
1490 if (!bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_MISC1, &val)) {
1491 val &= ~MII_BNX2_SD_MISC1_FORCE;
1492 bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_MISC1, val);
1495 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1496 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1497 err = bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1499 } else if (CHIP_NUM(bp) == CHIP_NUM_5708) {
1500 err = bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1502 bmcr &= ~BCM5708S_BMCR_FORCE_2500;
1510 if (bp->autoneg & AUTONEG_SPEED)
1511 bmcr |= BMCR_SPEED1000 | BMCR_ANENABLE | BMCR_ANRESTART;
1512 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
1516 bnx2_5706s_force_link_dn(struct bnx2 *bp, int start)
1520 bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS, MII_EXPAND_SERDES_CTL);
1521 bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &val);
1523 bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val & 0xff0f);
1525 bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val | 0xc0);
1529 bnx2_set_link(struct bnx2 *bp)
1534 if (bp->loopback == MAC_LOOPBACK || bp->loopback == PHY_LOOPBACK) {
1539 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
1542 link_up = bp->link_up;
1544 bnx2_enable_bmsr1(bp);
1545 bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
1546 bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
1547 bnx2_disable_bmsr1(bp);
1549 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
1550 (CHIP_NUM(bp) == CHIP_NUM_5706)) {
1553 if (bp->phy_flags & BNX2_PHY_FLAG_FORCED_DOWN) {
1554 bnx2_5706s_force_link_dn(bp, 0);
1555 bp->phy_flags &= ~BNX2_PHY_FLAG_FORCED_DOWN;
1557 val = REG_RD(bp, BNX2_EMAC_STATUS);
1559 bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG);
1560 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
1561 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
1563 if ((val & BNX2_EMAC_STATUS_LINK) &&
1564 !(an_dbg & MISC_SHDW_AN_DBG_NOSYNC))
1565 bmsr |= BMSR_LSTATUS;
1567 bmsr &= ~BMSR_LSTATUS;
1570 if (bmsr & BMSR_LSTATUS) {
1573 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
1574 if (CHIP_NUM(bp) == CHIP_NUM_5706)
1575 bnx2_5706s_linkup(bp);
1576 else if (CHIP_NUM(bp) == CHIP_NUM_5708)
1577 bnx2_5708s_linkup(bp);
1578 else if (CHIP_NUM(bp) == CHIP_NUM_5709)
1579 bnx2_5709s_linkup(bp);
1582 bnx2_copper_linkup(bp);
1584 bnx2_resolve_flow_ctrl(bp);
1587 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
1588 (bp->autoneg & AUTONEG_SPEED))
1589 bnx2_disable_forced_2g5(bp);
1591 if (bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT) {
1594 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1595 bmcr |= BMCR_ANENABLE;
1596 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
1598 bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT;
1603 if (bp->link_up != link_up) {
1604 bnx2_report_link(bp);
1607 bnx2_set_mac_link(bp);
1613 bnx2_reset_phy(struct bnx2 *bp)
1618 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_RESET);
1620 #define PHY_RESET_MAX_WAIT 100
1621 for (i = 0; i < PHY_RESET_MAX_WAIT; i++) {
1624 bnx2_read_phy(bp, bp->mii_bmcr, ®);
1625 if (!(reg & BMCR_RESET)) {
1630 if (i == PHY_RESET_MAX_WAIT) {
1637 bnx2_phy_get_pause_adv(struct bnx2 *bp)
1641 if ((bp->req_flow_ctrl & (FLOW_CTRL_RX | FLOW_CTRL_TX)) ==
1642 (FLOW_CTRL_RX | FLOW_CTRL_TX)) {
1644 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
1645 adv = ADVERTISE_1000XPAUSE;
1648 adv = ADVERTISE_PAUSE_CAP;
1651 else if (bp->req_flow_ctrl & FLOW_CTRL_TX) {
1652 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
1653 adv = ADVERTISE_1000XPSE_ASYM;
1656 adv = ADVERTISE_PAUSE_ASYM;
1659 else if (bp->req_flow_ctrl & FLOW_CTRL_RX) {
1660 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
1661 adv = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1664 adv = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1670 static int bnx2_fw_sync(struct bnx2 *, u32, int, int);
1673 bnx2_setup_remote_phy(struct bnx2 *bp, u8 port)
1674 __releases(&bp->phy_lock)
1675 __acquires(&bp->phy_lock)
1677 u32 speed_arg = 0, pause_adv;
1679 pause_adv = bnx2_phy_get_pause_adv(bp);
1681 if (bp->autoneg & AUTONEG_SPEED) {
1682 speed_arg |= BNX2_NETLINK_SET_LINK_ENABLE_AUTONEG;
1683 if (bp->advertising & ADVERTISED_10baseT_Half)
1684 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_10HALF;
1685 if (bp->advertising & ADVERTISED_10baseT_Full)
1686 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_10FULL;
1687 if (bp->advertising & ADVERTISED_100baseT_Half)
1688 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_100HALF;
1689 if (bp->advertising & ADVERTISED_100baseT_Full)
1690 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_100FULL;
1691 if (bp->advertising & ADVERTISED_1000baseT_Full)
1692 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_1GFULL;
1693 if (bp->advertising & ADVERTISED_2500baseX_Full)
1694 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_2G5FULL;
1696 if (bp->req_line_speed == SPEED_2500)
1697 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_2G5FULL;
1698 else if (bp->req_line_speed == SPEED_1000)
1699 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_1GFULL;
1700 else if (bp->req_line_speed == SPEED_100) {
1701 if (bp->req_duplex == DUPLEX_FULL)
1702 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_100FULL;
1704 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_100HALF;
1705 } else if (bp->req_line_speed == SPEED_10) {
1706 if (bp->req_duplex == DUPLEX_FULL)
1707 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_10FULL;
1709 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_10HALF;
1713 if (pause_adv & (ADVERTISE_1000XPAUSE | ADVERTISE_PAUSE_CAP))
1714 speed_arg |= BNX2_NETLINK_SET_LINK_FC_SYM_PAUSE;
1715 if (pause_adv & (ADVERTISE_1000XPSE_ASYM | ADVERTISE_PAUSE_ASYM))
1716 speed_arg |= BNX2_NETLINK_SET_LINK_FC_ASYM_PAUSE;
1718 if (port == PORT_TP)
1719 speed_arg |= BNX2_NETLINK_SET_LINK_PHY_APP_REMOTE |
1720 BNX2_NETLINK_SET_LINK_ETH_AT_WIRESPEED;
1722 bnx2_shmem_wr(bp, BNX2_DRV_MB_ARG0, speed_arg);
1724 spin_unlock_bh(&bp->phy_lock);
1725 bnx2_fw_sync(bp, BNX2_DRV_MSG_CODE_CMD_SET_LINK, 1, 0);
1726 spin_lock_bh(&bp->phy_lock);
1732 bnx2_setup_serdes_phy(struct bnx2 *bp, u8 port)
1733 __releases(&bp->phy_lock)
1734 __acquires(&bp->phy_lock)
1739 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
1740 return bnx2_setup_remote_phy(bp, port);
1742 if (!(bp->autoneg & AUTONEG_SPEED)) {
1744 int force_link_down = 0;
1746 if (bp->req_line_speed == SPEED_2500) {
1747 if (!bnx2_test_and_enable_2g5(bp))
1748 force_link_down = 1;
1749 } else if (bp->req_line_speed == SPEED_1000) {
1750 if (bnx2_test_and_disable_2g5(bp))
1751 force_link_down = 1;
1753 bnx2_read_phy(bp, bp->mii_adv, &adv);
1754 adv &= ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF);
1756 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1757 new_bmcr = bmcr & ~BMCR_ANENABLE;
1758 new_bmcr |= BMCR_SPEED1000;
1760 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
1761 if (bp->req_line_speed == SPEED_2500)
1762 bnx2_enable_forced_2g5(bp);
1763 else if (bp->req_line_speed == SPEED_1000) {
1764 bnx2_disable_forced_2g5(bp);
1765 new_bmcr &= ~0x2000;
1768 } else if (CHIP_NUM(bp) == CHIP_NUM_5708) {
1769 if (bp->req_line_speed == SPEED_2500)
1770 new_bmcr |= BCM5708S_BMCR_FORCE_2500;
1772 new_bmcr = bmcr & ~BCM5708S_BMCR_FORCE_2500;
1775 if (bp->req_duplex == DUPLEX_FULL) {
1776 adv |= ADVERTISE_1000XFULL;
1777 new_bmcr |= BMCR_FULLDPLX;
1780 adv |= ADVERTISE_1000XHALF;
1781 new_bmcr &= ~BMCR_FULLDPLX;
1783 if ((new_bmcr != bmcr) || (force_link_down)) {
1784 /* Force a link down visible on the other side */
1786 bnx2_write_phy(bp, bp->mii_adv, adv &
1787 ~(ADVERTISE_1000XFULL |
1788 ADVERTISE_1000XHALF));
1789 bnx2_write_phy(bp, bp->mii_bmcr, bmcr |
1790 BMCR_ANRESTART | BMCR_ANENABLE);
1793 netif_carrier_off(bp->dev);
1794 bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);
1795 bnx2_report_link(bp);
1797 bnx2_write_phy(bp, bp->mii_adv, adv);
1798 bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);
1800 bnx2_resolve_flow_ctrl(bp);
1801 bnx2_set_mac_link(bp);
1806 bnx2_test_and_enable_2g5(bp);
1808 if (bp->advertising & ADVERTISED_1000baseT_Full)
1809 new_adv |= ADVERTISE_1000XFULL;
1811 new_adv |= bnx2_phy_get_pause_adv(bp);
1813 bnx2_read_phy(bp, bp->mii_adv, &adv);
1814 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1816 bp->serdes_an_pending = 0;
1817 if ((adv != new_adv) || ((bmcr & BMCR_ANENABLE) == 0)) {
1818 /* Force a link down visible on the other side */
1820 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);
1821 spin_unlock_bh(&bp->phy_lock);
1823 spin_lock_bh(&bp->phy_lock);
1826 bnx2_write_phy(bp, bp->mii_adv, new_adv);
1827 bnx2_write_phy(bp, bp->mii_bmcr, bmcr | BMCR_ANRESTART |
1829 /* Speed up link-up time when the link partner
1830 * does not autonegotiate which is very common
1831 * in blade servers. Some blade servers use
1832 * IPMI for kerboard input and it's important
1833 * to minimize link disruptions. Autoneg. involves
1834 * exchanging base pages plus 3 next pages and
1835 * normally completes in about 120 msec.
1837 bp->current_interval = BNX2_SERDES_AN_TIMEOUT;
1838 bp->serdes_an_pending = 1;
1839 mod_timer(&bp->timer, jiffies + bp->current_interval);
1841 bnx2_resolve_flow_ctrl(bp);
1842 bnx2_set_mac_link(bp);
1848 #define ETHTOOL_ALL_FIBRE_SPEED \
1849 (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) ? \
1850 (ADVERTISED_2500baseX_Full | ADVERTISED_1000baseT_Full) :\
1851 (ADVERTISED_1000baseT_Full)
1853 #define ETHTOOL_ALL_COPPER_SPEED \
1854 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full | \
1855 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full | \
1856 ADVERTISED_1000baseT_Full)
1858 #define PHY_ALL_10_100_SPEED (ADVERTISE_10HALF | ADVERTISE_10FULL | \
1859 ADVERTISE_100HALF | ADVERTISE_100FULL | ADVERTISE_CSMA)
1861 #define PHY_ALL_1000_SPEED (ADVERTISE_1000HALF | ADVERTISE_1000FULL)
1864 bnx2_set_default_remote_link(struct bnx2 *bp)
1868 if (bp->phy_port == PORT_TP)
1869 link = bnx2_shmem_rd(bp, BNX2_RPHY_COPPER_LINK);
1871 link = bnx2_shmem_rd(bp, BNX2_RPHY_SERDES_LINK);
1873 if (link & BNX2_NETLINK_SET_LINK_ENABLE_AUTONEG) {
1874 bp->req_line_speed = 0;
1875 bp->autoneg |= AUTONEG_SPEED;
1876 bp->advertising = ADVERTISED_Autoneg;
1877 if (link & BNX2_NETLINK_SET_LINK_SPEED_10HALF)
1878 bp->advertising |= ADVERTISED_10baseT_Half;
1879 if (link & BNX2_NETLINK_SET_LINK_SPEED_10FULL)
1880 bp->advertising |= ADVERTISED_10baseT_Full;
1881 if (link & BNX2_NETLINK_SET_LINK_SPEED_100HALF)
1882 bp->advertising |= ADVERTISED_100baseT_Half;
1883 if (link & BNX2_NETLINK_SET_LINK_SPEED_100FULL)
1884 bp->advertising |= ADVERTISED_100baseT_Full;
1885 if (link & BNX2_NETLINK_SET_LINK_SPEED_1GFULL)
1886 bp->advertising |= ADVERTISED_1000baseT_Full;
1887 if (link & BNX2_NETLINK_SET_LINK_SPEED_2G5FULL)
1888 bp->advertising |= ADVERTISED_2500baseX_Full;
1891 bp->advertising = 0;
1892 bp->req_duplex = DUPLEX_FULL;
1893 if (link & BNX2_NETLINK_SET_LINK_SPEED_10) {
1894 bp->req_line_speed = SPEED_10;
1895 if (link & BNX2_NETLINK_SET_LINK_SPEED_10HALF)
1896 bp->req_duplex = DUPLEX_HALF;
1898 if (link & BNX2_NETLINK_SET_LINK_SPEED_100) {
1899 bp->req_line_speed = SPEED_100;
1900 if (link & BNX2_NETLINK_SET_LINK_SPEED_100HALF)
1901 bp->req_duplex = DUPLEX_HALF;
1903 if (link & BNX2_NETLINK_SET_LINK_SPEED_1GFULL)
1904 bp->req_line_speed = SPEED_1000;
1905 if (link & BNX2_NETLINK_SET_LINK_SPEED_2G5FULL)
1906 bp->req_line_speed = SPEED_2500;
1911 bnx2_set_default_link(struct bnx2 *bp)
1913 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
1914 bnx2_set_default_remote_link(bp);
1918 bp->autoneg = AUTONEG_SPEED | AUTONEG_FLOW_CTRL;
1919 bp->req_line_speed = 0;
1920 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
1923 bp->advertising = ETHTOOL_ALL_FIBRE_SPEED | ADVERTISED_Autoneg;
1925 reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_CONFIG);
1926 reg &= BNX2_PORT_HW_CFG_CFG_DFLT_LINK_MASK;
1927 if (reg == BNX2_PORT_HW_CFG_CFG_DFLT_LINK_1G) {
1929 bp->req_line_speed = bp->line_speed = SPEED_1000;
1930 bp->req_duplex = DUPLEX_FULL;
1933 bp->advertising = ETHTOOL_ALL_COPPER_SPEED | ADVERTISED_Autoneg;
1937 bnx2_send_heart_beat(struct bnx2 *bp)
1942 spin_lock(&bp->indirect_lock);
1943 msg = (u32) (++bp->fw_drv_pulse_wr_seq & BNX2_DRV_PULSE_SEQ_MASK);
1944 addr = bp->shmem_base + BNX2_DRV_PULSE_MB;
1945 REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, addr);
1946 REG_WR(bp, BNX2_PCICFG_REG_WINDOW, msg);
1947 spin_unlock(&bp->indirect_lock);
1951 bnx2_remote_phy_event(struct bnx2 *bp)
1954 u8 link_up = bp->link_up;
1957 msg = bnx2_shmem_rd(bp, BNX2_LINK_STATUS);
1959 if (msg & BNX2_LINK_STATUS_HEART_BEAT_EXPIRED)
1960 bnx2_send_heart_beat(bp);
1962 msg &= ~BNX2_LINK_STATUS_HEART_BEAT_EXPIRED;
1964 if ((msg & BNX2_LINK_STATUS_LINK_UP) == BNX2_LINK_STATUS_LINK_DOWN)
1970 speed = msg & BNX2_LINK_STATUS_SPEED_MASK;
1971 bp->duplex = DUPLEX_FULL;
1973 case BNX2_LINK_STATUS_10HALF:
1974 bp->duplex = DUPLEX_HALF;
1975 case BNX2_LINK_STATUS_10FULL:
1976 bp->line_speed = SPEED_10;
1978 case BNX2_LINK_STATUS_100HALF:
1979 bp->duplex = DUPLEX_HALF;
1980 case BNX2_LINK_STATUS_100BASE_T4:
1981 case BNX2_LINK_STATUS_100FULL:
1982 bp->line_speed = SPEED_100;
1984 case BNX2_LINK_STATUS_1000HALF:
1985 bp->duplex = DUPLEX_HALF;
1986 case BNX2_LINK_STATUS_1000FULL:
1987 bp->line_speed = SPEED_1000;
1989 case BNX2_LINK_STATUS_2500HALF:
1990 bp->duplex = DUPLEX_HALF;
1991 case BNX2_LINK_STATUS_2500FULL:
1992 bp->line_speed = SPEED_2500;
2000 if ((bp->autoneg & (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) !=
2001 (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) {
2002 if (bp->duplex == DUPLEX_FULL)
2003 bp->flow_ctrl = bp->req_flow_ctrl;
2005 if (msg & BNX2_LINK_STATUS_TX_FC_ENABLED)
2006 bp->flow_ctrl |= FLOW_CTRL_TX;
2007 if (msg & BNX2_LINK_STATUS_RX_FC_ENABLED)
2008 bp->flow_ctrl |= FLOW_CTRL_RX;
2011 old_port = bp->phy_port;
2012 if (msg & BNX2_LINK_STATUS_SERDES_LINK)
2013 bp->phy_port = PORT_FIBRE;
2015 bp->phy_port = PORT_TP;
2017 if (old_port != bp->phy_port)
2018 bnx2_set_default_link(bp);
2021 if (bp->link_up != link_up)
2022 bnx2_report_link(bp);
2024 bnx2_set_mac_link(bp);
2028 bnx2_set_remote_link(struct bnx2 *bp)
2032 evt_code = bnx2_shmem_rd(bp, BNX2_FW_EVT_CODE_MB);
2034 case BNX2_FW_EVT_CODE_LINK_EVENT:
2035 bnx2_remote_phy_event(bp);
2037 case BNX2_FW_EVT_CODE_SW_TIMER_EXPIRATION_EVENT:
2039 bnx2_send_heart_beat(bp);
2046 bnx2_setup_copper_phy(struct bnx2 *bp)
2047 __releases(&bp->phy_lock)
2048 __acquires(&bp->phy_lock)
2053 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
2055 if (bp->autoneg & AUTONEG_SPEED) {
2056 u32 adv_reg, adv1000_reg;
2058 u32 new_adv1000 = 0;
2060 bnx2_read_phy(bp, bp->mii_adv, &adv_reg);
2061 adv_reg &= (PHY_ALL_10_100_SPEED | ADVERTISE_PAUSE_CAP |
2062 ADVERTISE_PAUSE_ASYM);
2064 bnx2_read_phy(bp, MII_CTRL1000, &adv1000_reg);
2065 adv1000_reg &= PHY_ALL_1000_SPEED;
2067 new_adv = ethtool_adv_to_mii_adv_t(bp->advertising);
2068 new_adv |= ADVERTISE_CSMA;
2069 new_adv |= bnx2_phy_get_pause_adv(bp);
2071 new_adv1000 |= ethtool_adv_to_mii_ctrl1000_t(bp->advertising);
2073 if ((adv1000_reg != new_adv1000) ||
2074 (adv_reg != new_adv) ||
2075 ((bmcr & BMCR_ANENABLE) == 0)) {
2077 bnx2_write_phy(bp, bp->mii_adv, new_adv);
2078 bnx2_write_phy(bp, MII_CTRL1000, new_adv1000);
2079 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_ANRESTART |
2082 else if (bp->link_up) {
2083 /* Flow ctrl may have changed from auto to forced */
2084 /* or vice-versa. */
2086 bnx2_resolve_flow_ctrl(bp);
2087 bnx2_set_mac_link(bp);
2093 if (bp->req_line_speed == SPEED_100) {
2094 new_bmcr |= BMCR_SPEED100;
2096 if (bp->req_duplex == DUPLEX_FULL) {
2097 new_bmcr |= BMCR_FULLDPLX;
2099 if (new_bmcr != bmcr) {
2102 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
2103 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
2105 if (bmsr & BMSR_LSTATUS) {
2106 /* Force link down */
2107 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);
2108 spin_unlock_bh(&bp->phy_lock);
2110 spin_lock_bh(&bp->phy_lock);
2112 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
2113 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
2116 bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);
2118 /* Normally, the new speed is setup after the link has
2119 * gone down and up again. In some cases, link will not go
2120 * down so we need to set up the new speed here.
2122 if (bmsr & BMSR_LSTATUS) {
2123 bp->line_speed = bp->req_line_speed;
2124 bp->duplex = bp->req_duplex;
2125 bnx2_resolve_flow_ctrl(bp);
2126 bnx2_set_mac_link(bp);
2129 bnx2_resolve_flow_ctrl(bp);
2130 bnx2_set_mac_link(bp);
2136 bnx2_setup_phy(struct bnx2 *bp, u8 port)
2137 __releases(&bp->phy_lock)
2138 __acquires(&bp->phy_lock)
2140 if (bp->loopback == MAC_LOOPBACK)
2143 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
2144 return bnx2_setup_serdes_phy(bp, port);
2147 return bnx2_setup_copper_phy(bp);
2152 bnx2_init_5709s_phy(struct bnx2 *bp, int reset_phy)
2156 bp->mii_bmcr = MII_BMCR + 0x10;
2157 bp->mii_bmsr = MII_BMSR + 0x10;
2158 bp->mii_bmsr1 = MII_BNX2_GP_TOP_AN_STATUS1;
2159 bp->mii_adv = MII_ADVERTISE + 0x10;
2160 bp->mii_lpa = MII_LPA + 0x10;
2161 bp->mii_up1 = MII_BNX2_OVER1G_UP1;
2163 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_AER);
2164 bnx2_write_phy(bp, MII_BNX2_AER_AER, MII_BNX2_AER_AER_AN_MMD);
2166 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
2170 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_SERDES_DIG);
2172 bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_1000XCTL1, &val);
2173 val &= ~MII_BNX2_SD_1000XCTL1_AUTODET;
2174 val |= MII_BNX2_SD_1000XCTL1_FIBER;
2175 bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_1000XCTL1, val);
2177 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);
2178 bnx2_read_phy(bp, MII_BNX2_OVER1G_UP1, &val);
2179 if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE)
2180 val |= BCM5708S_UP1_2G5;
2182 val &= ~BCM5708S_UP1_2G5;
2183 bnx2_write_phy(bp, MII_BNX2_OVER1G_UP1, val);
2185 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_BAM_NXTPG);
2186 bnx2_read_phy(bp, MII_BNX2_BAM_NXTPG_CTL, &val);
2187 val |= MII_BNX2_NXTPG_CTL_T2 | MII_BNX2_NXTPG_CTL_BAM;
2188 bnx2_write_phy(bp, MII_BNX2_BAM_NXTPG_CTL, val);
2190 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_CL73_USERB0);
2192 val = MII_BNX2_CL73_BAM_EN | MII_BNX2_CL73_BAM_STA_MGR_EN |
2193 MII_BNX2_CL73_BAM_NP_AFT_BP_EN;
2194 bnx2_write_phy(bp, MII_BNX2_CL73_BAM_CTL1, val);
2196 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
2202 bnx2_init_5708s_phy(struct bnx2 *bp, int reset_phy)
2209 bp->mii_up1 = BCM5708S_UP1;
2211 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG3);
2212 bnx2_write_phy(bp, BCM5708S_DIG_3_0, BCM5708S_DIG_3_0_USE_IEEE);
2213 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG);
2215 bnx2_read_phy(bp, BCM5708S_1000X_CTL1, &val);
2216 val |= BCM5708S_1000X_CTL1_FIBER_MODE | BCM5708S_1000X_CTL1_AUTODET_EN;
2217 bnx2_write_phy(bp, BCM5708S_1000X_CTL1, val);
2219 bnx2_read_phy(bp, BCM5708S_1000X_CTL2, &val);
2220 val |= BCM5708S_1000X_CTL2_PLLEL_DET_EN;
2221 bnx2_write_phy(bp, BCM5708S_1000X_CTL2, val);
2223 if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) {
2224 bnx2_read_phy(bp, BCM5708S_UP1, &val);
2225 val |= BCM5708S_UP1_2G5;
2226 bnx2_write_phy(bp, BCM5708S_UP1, val);
2229 if ((CHIP_ID(bp) == CHIP_ID_5708_A0) ||
2230 (CHIP_ID(bp) == CHIP_ID_5708_B0) ||
2231 (CHIP_ID(bp) == CHIP_ID_5708_B1)) {
2232 /* increase tx signal amplitude */
2233 bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
2234 BCM5708S_BLK_ADDR_TX_MISC);
2235 bnx2_read_phy(bp, BCM5708S_TX_ACTL1, &val);
2236 val &= ~BCM5708S_TX_ACTL1_DRIVER_VCM;
2237 bnx2_write_phy(bp, BCM5708S_TX_ACTL1, val);
2238 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG);
2241 val = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_CONFIG) &
2242 BNX2_PORT_HW_CFG_CFG_TXCTL3_MASK;
2247 is_backplane = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG);
2248 if (is_backplane & BNX2_SHARED_HW_CFG_PHY_BACKPLANE) {
2249 bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
2250 BCM5708S_BLK_ADDR_TX_MISC);
2251 bnx2_write_phy(bp, BCM5708S_TX_ACTL3, val);
2252 bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
2253 BCM5708S_BLK_ADDR_DIG);
2260 bnx2_init_5706s_phy(struct bnx2 *bp, int reset_phy)
2265 bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT;
2267 if (CHIP_NUM(bp) == CHIP_NUM_5706)
2268 REG_WR(bp, BNX2_MISC_GP_HW_CTL0, 0x300);
2270 if (bp->dev->mtu > 1500) {
2273 /* Set extended packet length bit */
2274 bnx2_write_phy(bp, 0x18, 0x7);
2275 bnx2_read_phy(bp, 0x18, &val);
2276 bnx2_write_phy(bp, 0x18, (val & 0xfff8) | 0x4000);
2278 bnx2_write_phy(bp, 0x1c, 0x6c00);
2279 bnx2_read_phy(bp, 0x1c, &val);
2280 bnx2_write_phy(bp, 0x1c, (val & 0x3ff) | 0xec02);
2285 bnx2_write_phy(bp, 0x18, 0x7);
2286 bnx2_read_phy(bp, 0x18, &val);
2287 bnx2_write_phy(bp, 0x18, val & ~0x4007);
2289 bnx2_write_phy(bp, 0x1c, 0x6c00);
2290 bnx2_read_phy(bp, 0x1c, &val);
2291 bnx2_write_phy(bp, 0x1c, (val & 0x3fd) | 0xec00);
2298 bnx2_init_copper_phy(struct bnx2 *bp, int reset_phy)
2305 if (bp->phy_flags & BNX2_PHY_FLAG_CRC_FIX) {
2306 bnx2_write_phy(bp, 0x18, 0x0c00);
2307 bnx2_write_phy(bp, 0x17, 0x000a);
2308 bnx2_write_phy(bp, 0x15, 0x310b);
2309 bnx2_write_phy(bp, 0x17, 0x201f);
2310 bnx2_write_phy(bp, 0x15, 0x9506);
2311 bnx2_write_phy(bp, 0x17, 0x401f);
2312 bnx2_write_phy(bp, 0x15, 0x14e2);
2313 bnx2_write_phy(bp, 0x18, 0x0400);
2316 if (bp->phy_flags & BNX2_PHY_FLAG_DIS_EARLY_DAC) {
2317 bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS,
2318 MII_BNX2_DSP_EXPAND_REG | 0x8);
2319 bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &val);
2321 bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val);
2324 if (bp->dev->mtu > 1500) {
2325 /* Set extended packet length bit */
2326 bnx2_write_phy(bp, 0x18, 0x7);
2327 bnx2_read_phy(bp, 0x18, &val);
2328 bnx2_write_phy(bp, 0x18, val | 0x4000);
2330 bnx2_read_phy(bp, 0x10, &val);
2331 bnx2_write_phy(bp, 0x10, val | 0x1);
2334 bnx2_write_phy(bp, 0x18, 0x7);
2335 bnx2_read_phy(bp, 0x18, &val);
2336 bnx2_write_phy(bp, 0x18, val & ~0x4007);
2338 bnx2_read_phy(bp, 0x10, &val);
2339 bnx2_write_phy(bp, 0x10, val & ~0x1);
2342 /* ethernet@wirespeed */
2343 bnx2_write_phy(bp, 0x18, 0x7007);
2344 bnx2_read_phy(bp, 0x18, &val);
2345 bnx2_write_phy(bp, 0x18, val | (1 << 15) | (1 << 4));
2351 bnx2_init_phy(struct bnx2 *bp, int reset_phy)
2352 __releases(&bp->phy_lock)
2353 __acquires(&bp->phy_lock)
2358 bp->phy_flags &= ~BNX2_PHY_FLAG_INT_MODE_MASK;
2359 bp->phy_flags |= BNX2_PHY_FLAG_INT_MODE_LINK_READY;
2361 bp->mii_bmcr = MII_BMCR;
2362 bp->mii_bmsr = MII_BMSR;
2363 bp->mii_bmsr1 = MII_BMSR;
2364 bp->mii_adv = MII_ADVERTISE;
2365 bp->mii_lpa = MII_LPA;
2367 REG_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);
2369 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
2372 bnx2_read_phy(bp, MII_PHYSID1, &val);
2373 bp->phy_id = val << 16;
2374 bnx2_read_phy(bp, MII_PHYSID2, &val);
2375 bp->phy_id |= val & 0xffff;
2377 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
2378 if (CHIP_NUM(bp) == CHIP_NUM_5706)
2379 rc = bnx2_init_5706s_phy(bp, reset_phy);
2380 else if (CHIP_NUM(bp) == CHIP_NUM_5708)
2381 rc = bnx2_init_5708s_phy(bp, reset_phy);
2382 else if (CHIP_NUM(bp) == CHIP_NUM_5709)
2383 rc = bnx2_init_5709s_phy(bp, reset_phy);
2386 rc = bnx2_init_copper_phy(bp, reset_phy);
2391 rc = bnx2_setup_phy(bp, bp->phy_port);
2397 bnx2_set_mac_loopback(struct bnx2 *bp)
2401 mac_mode = REG_RD(bp, BNX2_EMAC_MODE);
2402 mac_mode &= ~BNX2_EMAC_MODE_PORT;
2403 mac_mode |= BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK;
2404 REG_WR(bp, BNX2_EMAC_MODE, mac_mode);
2409 static int bnx2_test_link(struct bnx2 *);
2412 bnx2_set_phy_loopback(struct bnx2 *bp)
2417 spin_lock_bh(&bp->phy_lock);
2418 rc = bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK | BMCR_FULLDPLX |
2420 spin_unlock_bh(&bp->phy_lock);
2424 for (i = 0; i < 10; i++) {
2425 if (bnx2_test_link(bp) == 0)
2430 mac_mode = REG_RD(bp, BNX2_EMAC_MODE);
2431 mac_mode &= ~(BNX2_EMAC_MODE_PORT | BNX2_EMAC_MODE_HALF_DUPLEX |
2432 BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK |
2433 BNX2_EMAC_MODE_25G_MODE);
2435 mac_mode |= BNX2_EMAC_MODE_PORT_GMII;
2436 REG_WR(bp, BNX2_EMAC_MODE, mac_mode);
2442 bnx2_dump_mcp_state(struct bnx2 *bp)
2444 struct net_device *dev = bp->dev;
2447 netdev_err(dev, "<--- start MCP states dump --->\n");
2448 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
2449 mcp_p0 = BNX2_MCP_STATE_P0;
2450 mcp_p1 = BNX2_MCP_STATE_P1;
2452 mcp_p0 = BNX2_MCP_STATE_P0_5708;
2453 mcp_p1 = BNX2_MCP_STATE_P1_5708;
2455 netdev_err(dev, "DEBUG: MCP_STATE_P0[%08x] MCP_STATE_P1[%08x]\n",
2456 bnx2_reg_rd_ind(bp, mcp_p0), bnx2_reg_rd_ind(bp, mcp_p1));
2457 netdev_err(dev, "DEBUG: MCP mode[%08x] state[%08x] evt_mask[%08x]\n",
2458 bnx2_reg_rd_ind(bp, BNX2_MCP_CPU_MODE),
2459 bnx2_reg_rd_ind(bp, BNX2_MCP_CPU_STATE),
2460 bnx2_reg_rd_ind(bp, BNX2_MCP_CPU_EVENT_MASK));
2461 netdev_err(dev, "DEBUG: pc[%08x] pc[%08x] instr[%08x]\n",
2462 bnx2_reg_rd_ind(bp, BNX2_MCP_CPU_PROGRAM_COUNTER),
2463 bnx2_reg_rd_ind(bp, BNX2_MCP_CPU_PROGRAM_COUNTER),
2464 bnx2_reg_rd_ind(bp, BNX2_MCP_CPU_INSTRUCTION));
2465 netdev_err(dev, "DEBUG: shmem states:\n");
2466 netdev_err(dev, "DEBUG: drv_mb[%08x] fw_mb[%08x] link_status[%08x]",
2467 bnx2_shmem_rd(bp, BNX2_DRV_MB),
2468 bnx2_shmem_rd(bp, BNX2_FW_MB),
2469 bnx2_shmem_rd(bp, BNX2_LINK_STATUS));
2470 pr_cont(" drv_pulse_mb[%08x]\n", bnx2_shmem_rd(bp, BNX2_DRV_PULSE_MB));
2471 netdev_err(dev, "DEBUG: dev_info_signature[%08x] reset_type[%08x]",
2472 bnx2_shmem_rd(bp, BNX2_DEV_INFO_SIGNATURE),
2473 bnx2_shmem_rd(bp, BNX2_BC_STATE_RESET_TYPE));
2474 pr_cont(" condition[%08x]\n",
2475 bnx2_shmem_rd(bp, BNX2_BC_STATE_CONDITION));
2476 DP_SHMEM_LINE(bp, 0x3cc);
2477 DP_SHMEM_LINE(bp, 0x3dc);
2478 DP_SHMEM_LINE(bp, 0x3ec);
2479 netdev_err(dev, "DEBUG: 0x3fc[%08x]\n", bnx2_shmem_rd(bp, 0x3fc));
2480 netdev_err(dev, "<--- end MCP states dump --->\n");
2484 bnx2_fw_sync(struct bnx2 *bp, u32 msg_data, int ack, int silent)
2490 msg_data |= bp->fw_wr_seq;
2492 bnx2_shmem_wr(bp, BNX2_DRV_MB, msg_data);
2497 /* wait for an acknowledgement. */
2498 for (i = 0; i < (BNX2_FW_ACK_TIME_OUT_MS / 10); i++) {
2501 val = bnx2_shmem_rd(bp, BNX2_FW_MB);
2503 if ((val & BNX2_FW_MSG_ACK) == (msg_data & BNX2_DRV_MSG_SEQ))
2506 if ((msg_data & BNX2_DRV_MSG_DATA) == BNX2_DRV_MSG_DATA_WAIT0)
2509 /* If we timed out, inform the firmware that this is the case. */
2510 if ((val & BNX2_FW_MSG_ACK) != (msg_data & BNX2_DRV_MSG_SEQ)) {
2511 msg_data &= ~BNX2_DRV_MSG_CODE;
2512 msg_data |= BNX2_DRV_MSG_CODE_FW_TIMEOUT;
2514 bnx2_shmem_wr(bp, BNX2_DRV_MB, msg_data);
2516 pr_err("fw sync timeout, reset code = %x\n", msg_data);
2517 bnx2_dump_mcp_state(bp);
2523 if ((val & BNX2_FW_MSG_STATUS_MASK) != BNX2_FW_MSG_STATUS_OK)
2530 bnx2_init_5709_context(struct bnx2 *bp)
2535 val = BNX2_CTX_COMMAND_ENABLED | BNX2_CTX_COMMAND_MEM_INIT | (1 << 12);
2536 val |= (BCM_PAGE_BITS - 8) << 16;
2537 REG_WR(bp, BNX2_CTX_COMMAND, val);
2538 for (i = 0; i < 10; i++) {
2539 val = REG_RD(bp, BNX2_CTX_COMMAND);
2540 if (!(val & BNX2_CTX_COMMAND_MEM_INIT))
2544 if (val & BNX2_CTX_COMMAND_MEM_INIT)
2547 for (i = 0; i < bp->ctx_pages; i++) {
2551 memset(bp->ctx_blk[i], 0, BCM_PAGE_SIZE);
2555 REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_DATA0,
2556 (bp->ctx_blk_mapping[i] & 0xffffffff) |
2557 BNX2_CTX_HOST_PAGE_TBL_DATA0_VALID);
2558 REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_DATA1,
2559 (u64) bp->ctx_blk_mapping[i] >> 32);
2560 REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_CTRL, i |
2561 BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ);
2562 for (j = 0; j < 10; j++) {
2564 val = REG_RD(bp, BNX2_CTX_HOST_PAGE_TBL_CTRL);
2565 if (!(val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ))
2569 if (val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) {
2578 bnx2_init_context(struct bnx2 *bp)
2584 u32 vcid_addr, pcid_addr, offset;
2589 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
2592 vcid_addr = GET_PCID_ADDR(vcid);
2594 new_vcid = 0x60 + (vcid & 0xf0) + (vcid & 0x7);
2599 pcid_addr = GET_PCID_ADDR(new_vcid);
2602 vcid_addr = GET_CID_ADDR(vcid);
2603 pcid_addr = vcid_addr;
2606 for (i = 0; i < (CTX_SIZE / PHY_CTX_SIZE); i++) {
2607 vcid_addr += (i << PHY_CTX_SHIFT);
2608 pcid_addr += (i << PHY_CTX_SHIFT);
2610 REG_WR(bp, BNX2_CTX_VIRT_ADDR, vcid_addr);
2611 REG_WR(bp, BNX2_CTX_PAGE_TBL, pcid_addr);
2613 /* Zero out the context. */
2614 for (offset = 0; offset < PHY_CTX_SIZE; offset += 4)
2615 bnx2_ctx_wr(bp, vcid_addr, offset, 0);
2621 bnx2_alloc_bad_rbuf(struct bnx2 *bp)
2627 good_mbuf = kmalloc(512 * sizeof(u16), GFP_KERNEL);
2628 if (good_mbuf == NULL)
2631 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
2632 BNX2_MISC_ENABLE_SET_BITS_RX_MBUF_ENABLE);
2636 /* Allocate a bunch of mbufs and save the good ones in an array. */
2637 val = bnx2_reg_rd_ind(bp, BNX2_RBUF_STATUS1);
2638 while (val & BNX2_RBUF_STATUS1_FREE_COUNT) {
2639 bnx2_reg_wr_ind(bp, BNX2_RBUF_COMMAND,
2640 BNX2_RBUF_COMMAND_ALLOC_REQ);
2642 val = bnx2_reg_rd_ind(bp, BNX2_RBUF_FW_BUF_ALLOC);
2644 val &= BNX2_RBUF_FW_BUF_ALLOC_VALUE;
2646 /* The addresses with Bit 9 set are bad memory blocks. */
2647 if (!(val & (1 << 9))) {
2648 good_mbuf[good_mbuf_cnt] = (u16) val;
2652 val = bnx2_reg_rd_ind(bp, BNX2_RBUF_STATUS1);
2655 /* Free the good ones back to the mbuf pool thus discarding
2656 * all the bad ones. */
2657 while (good_mbuf_cnt) {
2660 val = good_mbuf[good_mbuf_cnt];
2661 val = (val << 9) | val | 1;
2663 bnx2_reg_wr_ind(bp, BNX2_RBUF_FW_BUF_FREE, val);
2670 bnx2_set_mac_addr(struct bnx2 *bp, u8 *mac_addr, u32 pos)
2674 val = (mac_addr[0] << 8) | mac_addr[1];
2676 REG_WR(bp, BNX2_EMAC_MAC_MATCH0 + (pos * 8), val);
2678 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
2679 (mac_addr[4] << 8) | mac_addr[5];
2681 REG_WR(bp, BNX2_EMAC_MAC_MATCH1 + (pos * 8), val);
2685 bnx2_alloc_rx_page(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, u16 index, gfp_t gfp)
2688 struct sw_pg *rx_pg = &rxr->rx_pg_ring[index];
2689 struct rx_bd *rxbd =
2690 &rxr->rx_pg_desc_ring[RX_RING(index)][RX_IDX(index)];
2691 struct page *page = alloc_page(gfp);
2695 mapping = dma_map_page(&bp->pdev->dev, page, 0, PAGE_SIZE,
2696 PCI_DMA_FROMDEVICE);
2697 if (dma_mapping_error(&bp->pdev->dev, mapping)) {
2703 dma_unmap_addr_set(rx_pg, mapping, mapping);
2704 rxbd->rx_bd_haddr_hi = (u64) mapping >> 32;
2705 rxbd->rx_bd_haddr_lo = (u64) mapping & 0xffffffff;
2710 bnx2_free_rx_page(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, u16 index)
2712 struct sw_pg *rx_pg = &rxr->rx_pg_ring[index];
2713 struct page *page = rx_pg->page;
2718 dma_unmap_page(&bp->pdev->dev, dma_unmap_addr(rx_pg, mapping),
2719 PAGE_SIZE, PCI_DMA_FROMDEVICE);
2726 bnx2_alloc_rx_data(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, u16 index, gfp_t gfp)
2729 struct sw_bd *rx_buf = &rxr->rx_buf_ring[index];
2731 struct rx_bd *rxbd = &rxr->rx_desc_ring[RX_RING(index)][RX_IDX(index)];
2733 data = kmalloc(bp->rx_buf_size, gfp);
2737 mapping = dma_map_single(&bp->pdev->dev,
2739 bp->rx_buf_use_size,
2740 PCI_DMA_FROMDEVICE);
2741 if (dma_mapping_error(&bp->pdev->dev, mapping)) {
2746 rx_buf->data = data;
2747 dma_unmap_addr_set(rx_buf, mapping, mapping);
2749 rxbd->rx_bd_haddr_hi = (u64) mapping >> 32;
2750 rxbd->rx_bd_haddr_lo = (u64) mapping & 0xffffffff;
2752 rxr->rx_prod_bseq += bp->rx_buf_use_size;
2758 bnx2_phy_event_is_set(struct bnx2 *bp, struct bnx2_napi *bnapi, u32 event)
2760 struct status_block *sblk = bnapi->status_blk.msi;
2761 u32 new_link_state, old_link_state;
2764 new_link_state = sblk->status_attn_bits & event;
2765 old_link_state = sblk->status_attn_bits_ack & event;
2766 if (new_link_state != old_link_state) {
2768 REG_WR(bp, BNX2_PCICFG_STATUS_BIT_SET_CMD, event);
2770 REG_WR(bp, BNX2_PCICFG_STATUS_BIT_CLEAR_CMD, event);
2778 bnx2_phy_int(struct bnx2 *bp, struct bnx2_napi *bnapi)
2780 spin_lock(&bp->phy_lock);
2782 if (bnx2_phy_event_is_set(bp, bnapi, STATUS_ATTN_BITS_LINK_STATE))
2784 if (bnx2_phy_event_is_set(bp, bnapi, STATUS_ATTN_BITS_TIMER_ABORT))
2785 bnx2_set_remote_link(bp);
2787 spin_unlock(&bp->phy_lock);
2792 bnx2_get_hw_tx_cons(struct bnx2_napi *bnapi)
2796 /* Tell compiler that status block fields can change. */
2798 cons = *bnapi->hw_tx_cons_ptr;
2800 if (unlikely((cons & MAX_TX_DESC_CNT) == MAX_TX_DESC_CNT))
2806 bnx2_tx_int(struct bnx2 *bp, struct bnx2_napi *bnapi, int budget)
2808 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
2809 u16 hw_cons, sw_cons, sw_ring_cons;
2810 int tx_pkt = 0, index;
2811 unsigned int tx_bytes = 0;
2812 struct netdev_queue *txq;
2814 index = (bnapi - bp->bnx2_napi);
2815 txq = netdev_get_tx_queue(bp->dev, index);
2817 hw_cons = bnx2_get_hw_tx_cons(bnapi);
2818 sw_cons = txr->tx_cons;
2820 while (sw_cons != hw_cons) {
2821 struct sw_tx_bd *tx_buf;
2822 struct sk_buff *skb;
2825 sw_ring_cons = TX_RING_IDX(sw_cons);
2827 tx_buf = &txr->tx_buf_ring[sw_ring_cons];
2830 /* prefetch skb_end_pointer() to speedup skb_shinfo(skb) */
2831 prefetch(&skb->end);
2833 /* partial BD completions possible with TSO packets */
2834 if (tx_buf->is_gso) {
2835 u16 last_idx, last_ring_idx;
2837 last_idx = sw_cons + tx_buf->nr_frags + 1;
2838 last_ring_idx = sw_ring_cons + tx_buf->nr_frags + 1;
2839 if (unlikely(last_ring_idx >= MAX_TX_DESC_CNT)) {
2842 if (((s16) ((s16) last_idx - (s16) hw_cons)) > 0) {
2847 dma_unmap_single(&bp->pdev->dev, dma_unmap_addr(tx_buf, mapping),
2848 skb_headlen(skb), PCI_DMA_TODEVICE);
2851 last = tx_buf->nr_frags;
2853 for (i = 0; i < last; i++) {
2854 sw_cons = NEXT_TX_BD(sw_cons);
2856 dma_unmap_page(&bp->pdev->dev,
2858 &txr->tx_buf_ring[TX_RING_IDX(sw_cons)],
2860 skb_frag_size(&skb_shinfo(skb)->frags[i]),
2864 sw_cons = NEXT_TX_BD(sw_cons);
2866 tx_bytes += skb->len;
2869 if (tx_pkt == budget)
2872 if (hw_cons == sw_cons)
2873 hw_cons = bnx2_get_hw_tx_cons(bnapi);
2876 netdev_tx_completed_queue(txq, tx_pkt, tx_bytes);
2877 txr->hw_tx_cons = hw_cons;
2878 txr->tx_cons = sw_cons;
2880 /* Need to make the tx_cons update visible to bnx2_start_xmit()
2881 * before checking for netif_tx_queue_stopped(). Without the
2882 * memory barrier, there is a small possibility that bnx2_start_xmit()
2883 * will miss it and cause the queue to be stopped forever.
2887 if (unlikely(netif_tx_queue_stopped(txq)) &&
2888 (bnx2_tx_avail(bp, txr) > bp->tx_wake_thresh)) {
2889 __netif_tx_lock(txq, smp_processor_id());
2890 if ((netif_tx_queue_stopped(txq)) &&
2891 (bnx2_tx_avail(bp, txr) > bp->tx_wake_thresh))
2892 netif_tx_wake_queue(txq);
2893 __netif_tx_unlock(txq);
2900 bnx2_reuse_rx_skb_pages(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr,
2901 struct sk_buff *skb, int count)
2903 struct sw_pg *cons_rx_pg, *prod_rx_pg;
2904 struct rx_bd *cons_bd, *prod_bd;
2907 u16 cons = rxr->rx_pg_cons;
2909 cons_rx_pg = &rxr->rx_pg_ring[cons];
2911 /* The caller was unable to allocate a new page to replace the
2912 * last one in the frags array, so we need to recycle that page
2913 * and then free the skb.
2917 struct skb_shared_info *shinfo;
2919 shinfo = skb_shinfo(skb);
2921 page = skb_frag_page(&shinfo->frags[shinfo->nr_frags]);
2922 __skb_frag_set_page(&shinfo->frags[shinfo->nr_frags], NULL);
2924 cons_rx_pg->page = page;
2928 hw_prod = rxr->rx_pg_prod;
2930 for (i = 0; i < count; i++) {
2931 prod = RX_PG_RING_IDX(hw_prod);
2933 prod_rx_pg = &rxr->rx_pg_ring[prod];
2934 cons_rx_pg = &rxr->rx_pg_ring[cons];
2935 cons_bd = &rxr->rx_pg_desc_ring[RX_RING(cons)][RX_IDX(cons)];
2936 prod_bd = &rxr->rx_pg_desc_ring[RX_RING(prod)][RX_IDX(prod)];
2939 prod_rx_pg->page = cons_rx_pg->page;
2940 cons_rx_pg->page = NULL;
2941 dma_unmap_addr_set(prod_rx_pg, mapping,
2942 dma_unmap_addr(cons_rx_pg, mapping));
2944 prod_bd->rx_bd_haddr_hi = cons_bd->rx_bd_haddr_hi;
2945 prod_bd->rx_bd_haddr_lo = cons_bd->rx_bd_haddr_lo;
2948 cons = RX_PG_RING_IDX(NEXT_RX_BD(cons));
2949 hw_prod = NEXT_RX_BD(hw_prod);
2951 rxr->rx_pg_prod = hw_prod;
2952 rxr->rx_pg_cons = cons;
2956 bnx2_reuse_rx_data(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr,
2957 u8 *data, u16 cons, u16 prod)
2959 struct sw_bd *cons_rx_buf, *prod_rx_buf;
2960 struct rx_bd *cons_bd, *prod_bd;
2962 cons_rx_buf = &rxr->rx_buf_ring[cons];
2963 prod_rx_buf = &rxr->rx_buf_ring[prod];
2965 dma_sync_single_for_device(&bp->pdev->dev,
2966 dma_unmap_addr(cons_rx_buf, mapping),
2967 BNX2_RX_OFFSET + BNX2_RX_COPY_THRESH, PCI_DMA_FROMDEVICE);
2969 rxr->rx_prod_bseq += bp->rx_buf_use_size;
2971 prod_rx_buf->data = data;
2976 dma_unmap_addr_set(prod_rx_buf, mapping,
2977 dma_unmap_addr(cons_rx_buf, mapping));
2979 cons_bd = &rxr->rx_desc_ring[RX_RING(cons)][RX_IDX(cons)];
2980 prod_bd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
2981 prod_bd->rx_bd_haddr_hi = cons_bd->rx_bd_haddr_hi;
2982 prod_bd->rx_bd_haddr_lo = cons_bd->rx_bd_haddr_lo;
2985 static struct sk_buff *
2986 bnx2_rx_skb(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, u8 *data,
2987 unsigned int len, unsigned int hdr_len, dma_addr_t dma_addr,
2991 u16 prod = ring_idx & 0xffff;
2992 struct sk_buff *skb;
2994 err = bnx2_alloc_rx_data(bp, rxr, prod, GFP_ATOMIC);
2995 if (unlikely(err)) {
2996 bnx2_reuse_rx_data(bp, rxr, data, (u16) (ring_idx >> 16), prod);
2999 unsigned int raw_len = len + 4;
3000 int pages = PAGE_ALIGN(raw_len - hdr_len) >> PAGE_SHIFT;
3002 bnx2_reuse_rx_skb_pages(bp, rxr, NULL, pages);
3007 dma_unmap_single(&bp->pdev->dev, dma_addr, bp->rx_buf_use_size,
3008 PCI_DMA_FROMDEVICE);
3009 skb = build_skb(data);
3014 skb_reserve(skb, ((u8 *)get_l2_fhdr(data) - data) + BNX2_RX_OFFSET);
3019 unsigned int i, frag_len, frag_size, pages;
3020 struct sw_pg *rx_pg;
3021 u16 pg_cons = rxr->rx_pg_cons;
3022 u16 pg_prod = rxr->rx_pg_prod;
3024 frag_size = len + 4 - hdr_len;
3025 pages = PAGE_ALIGN(frag_size) >> PAGE_SHIFT;
3026 skb_put(skb, hdr_len);
3028 for (i = 0; i < pages; i++) {
3029 dma_addr_t mapping_old;
3031 frag_len = min(frag_size, (unsigned int) PAGE_SIZE);
3032 if (unlikely(frag_len <= 4)) {
3033 unsigned int tail = 4 - frag_len;
3035 rxr->rx_pg_cons = pg_cons;
3036 rxr->rx_pg_prod = pg_prod;
3037 bnx2_reuse_rx_skb_pages(bp, rxr, NULL,
3044 &skb_shinfo(skb)->frags[i - 1];
3045 skb_frag_size_sub(frag, tail);
3046 skb->data_len -= tail;
3050 rx_pg = &rxr->rx_pg_ring[pg_cons];
3052 /* Don't unmap yet. If we're unable to allocate a new
3053 * page, we need to recycle the page and the DMA addr.
3055 mapping_old = dma_unmap_addr(rx_pg, mapping);
3059 skb_fill_page_desc(skb, i, rx_pg->page, 0, frag_len);
3062 err = bnx2_alloc_rx_page(bp, rxr,
3063 RX_PG_RING_IDX(pg_prod),
3065 if (unlikely(err)) {
3066 rxr->rx_pg_cons = pg_cons;
3067 rxr->rx_pg_prod = pg_prod;
3068 bnx2_reuse_rx_skb_pages(bp, rxr, skb,
3073 dma_unmap_page(&bp->pdev->dev, mapping_old,
3074 PAGE_SIZE, PCI_DMA_FROMDEVICE);
3076 frag_size -= frag_len;
3077 skb->data_len += frag_len;
3078 skb->truesize += PAGE_SIZE;
3079 skb->len += frag_len;
3081 pg_prod = NEXT_RX_BD(pg_prod);
3082 pg_cons = RX_PG_RING_IDX(NEXT_RX_BD(pg_cons));
3084 rxr->rx_pg_prod = pg_prod;
3085 rxr->rx_pg_cons = pg_cons;
3091 bnx2_get_hw_rx_cons(struct bnx2_napi *bnapi)
3095 /* Tell compiler that status block fields can change. */
3097 cons = *bnapi->hw_rx_cons_ptr;
3099 if (unlikely((cons & MAX_RX_DESC_CNT) == MAX_RX_DESC_CNT))
3105 bnx2_rx_int(struct bnx2 *bp, struct bnx2_napi *bnapi, int budget)
3107 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
3108 u16 hw_cons, sw_cons, sw_ring_cons, sw_prod, sw_ring_prod;
3109 struct l2_fhdr *rx_hdr;
3110 int rx_pkt = 0, pg_ring_used = 0;
3112 hw_cons = bnx2_get_hw_rx_cons(bnapi);
3113 sw_cons = rxr->rx_cons;
3114 sw_prod = rxr->rx_prod;
3116 /* Memory barrier necessary as speculative reads of the rx
3117 * buffer can be ahead of the index in the status block
3120 while (sw_cons != hw_cons) {
3121 unsigned int len, hdr_len;
3123 struct sw_bd *rx_buf, *next_rx_buf;
3124 struct sk_buff *skb;
3125 dma_addr_t dma_addr;
3128 sw_ring_cons = RX_RING_IDX(sw_cons);
3129 sw_ring_prod = RX_RING_IDX(sw_prod);
3131 rx_buf = &rxr->rx_buf_ring[sw_ring_cons];
3132 data = rx_buf->data;
3133 rx_buf->data = NULL;
3135 rx_hdr = get_l2_fhdr(data);
3138 dma_addr = dma_unmap_addr(rx_buf, mapping);
3140 dma_sync_single_for_cpu(&bp->pdev->dev, dma_addr,
3141 BNX2_RX_OFFSET + BNX2_RX_COPY_THRESH,
3142 PCI_DMA_FROMDEVICE);
3145 &rxr->rx_buf_ring[RX_RING_IDX(NEXT_RX_BD(sw_cons))];
3146 prefetch(get_l2_fhdr(next_rx_buf->data));
3148 len = rx_hdr->l2_fhdr_pkt_len;
3149 status = rx_hdr->l2_fhdr_status;
3152 if (status & L2_FHDR_STATUS_SPLIT) {
3153 hdr_len = rx_hdr->l2_fhdr_ip_xsum;
3155 } else if (len > bp->rx_jumbo_thresh) {
3156 hdr_len = bp->rx_jumbo_thresh;
3160 if (unlikely(status & (L2_FHDR_ERRORS_BAD_CRC |
3161 L2_FHDR_ERRORS_PHY_DECODE |
3162 L2_FHDR_ERRORS_ALIGNMENT |
3163 L2_FHDR_ERRORS_TOO_SHORT |
3164 L2_FHDR_ERRORS_GIANT_FRAME))) {
3166 bnx2_reuse_rx_data(bp, rxr, data, sw_ring_cons,
3171 pages = PAGE_ALIGN(len - hdr_len) >> PAGE_SHIFT;
3173 bnx2_reuse_rx_skb_pages(bp, rxr, NULL, pages);
3180 if (len <= bp->rx_copy_thresh) {
3181 skb = netdev_alloc_skb(bp->dev, len + 6);
3183 bnx2_reuse_rx_data(bp, rxr, data, sw_ring_cons,
3190 (u8 *)rx_hdr + BNX2_RX_OFFSET - 6,
3192 skb_reserve(skb, 6);
3195 bnx2_reuse_rx_data(bp, rxr, data,
3196 sw_ring_cons, sw_ring_prod);
3199 skb = bnx2_rx_skb(bp, rxr, data, len, hdr_len, dma_addr,
3200 (sw_ring_cons << 16) | sw_ring_prod);
3204 if ((status & L2_FHDR_STATUS_L2_VLAN_TAG) &&
3205 !(bp->rx_mode & BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG))
3206 __vlan_hwaccel_put_tag(skb, rx_hdr->l2_fhdr_vlan_tag);
3208 skb->protocol = eth_type_trans(skb, bp->dev);
3210 if ((len > (bp->dev->mtu + ETH_HLEN)) &&
3211 (ntohs(skb->protocol) != 0x8100)) {
3218 skb_checksum_none_assert(skb);
3219 if ((bp->dev->features & NETIF_F_RXCSUM) &&
3220 (status & (L2_FHDR_STATUS_TCP_SEGMENT |
3221 L2_FHDR_STATUS_UDP_DATAGRAM))) {
3223 if (likely((status & (L2_FHDR_ERRORS_TCP_XSUM |
3224 L2_FHDR_ERRORS_UDP_XSUM)) == 0))
3225 skb->ip_summed = CHECKSUM_UNNECESSARY;
3227 if ((bp->dev->features & NETIF_F_RXHASH) &&
3228 ((status & L2_FHDR_STATUS_USE_RXHASH) ==
3229 L2_FHDR_STATUS_USE_RXHASH))
3230 skb->rxhash = rx_hdr->l2_fhdr_hash;
3232 skb_record_rx_queue(skb, bnapi - &bp->bnx2_napi[0]);
3233 napi_gro_receive(&bnapi->napi, skb);
3237 sw_cons = NEXT_RX_BD(sw_cons);
3238 sw_prod = NEXT_RX_BD(sw_prod);
3240 if ((rx_pkt == budget))
3243 /* Refresh hw_cons to see if there is new work */
3244 if (sw_cons == hw_cons) {
3245 hw_cons = bnx2_get_hw_rx_cons(bnapi);
3249 rxr->rx_cons = sw_cons;
3250 rxr->rx_prod = sw_prod;
3253 REG_WR16(bp, rxr->rx_pg_bidx_addr, rxr->rx_pg_prod);
3255 REG_WR16(bp, rxr->rx_bidx_addr, sw_prod);
3257 REG_WR(bp, rxr->rx_bseq_addr, rxr->rx_prod_bseq);
3265 /* MSI ISR - The only difference between this and the INTx ISR
3266 * is that the MSI interrupt is always serviced.
3269 bnx2_msi(int irq, void *dev_instance)
3271 struct bnx2_napi *bnapi = dev_instance;
3272 struct bnx2 *bp = bnapi->bp;
3274 prefetch(bnapi->status_blk.msi);
3275 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3276 BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
3277 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
3279 /* Return here if interrupt is disabled. */
3280 if (unlikely(atomic_read(&bp->intr_sem) != 0))
3283 napi_schedule(&bnapi->napi);
3289 bnx2_msi_1shot(int irq, void *dev_instance)
3291 struct bnx2_napi *bnapi = dev_instance;
3292 struct bnx2 *bp = bnapi->bp;
3294 prefetch(bnapi->status_blk.msi);
3296 /* Return here if interrupt is disabled. */
3297 if (unlikely(atomic_read(&bp->intr_sem) != 0))
3300 napi_schedule(&bnapi->napi);
3306 bnx2_interrupt(int irq, void *dev_instance)
3308 struct bnx2_napi *bnapi = dev_instance;
3309 struct bnx2 *bp = bnapi->bp;
3310 struct status_block *sblk = bnapi->status_blk.msi;
3312 /* When using INTx, it is possible for the interrupt to arrive
3313 * at the CPU before the status block posted prior to the
3314 * interrupt. Reading a register will flush the status block.
3315 * When using MSI, the MSI message will always complete after
3316 * the status block write.
3318 if ((sblk->status_idx == bnapi->last_status_idx) &&
3319 (REG_RD(bp, BNX2_PCICFG_MISC_STATUS) &
3320 BNX2_PCICFG_MISC_STATUS_INTA_VALUE))
3323 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3324 BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
3325 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
3327 /* Read back to deassert IRQ immediately to avoid too many
3328 * spurious interrupts.
3330 REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD);
3332 /* Return here if interrupt is shared and is disabled. */
3333 if (unlikely(atomic_read(&bp->intr_sem) != 0))
3336 if (napi_schedule_prep(&bnapi->napi)) {
3337 bnapi->last_status_idx = sblk->status_idx;
3338 __napi_schedule(&bnapi->napi);
3345 bnx2_has_fast_work(struct bnx2_napi *bnapi)
3347 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
3348 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
3350 if ((bnx2_get_hw_rx_cons(bnapi) != rxr->rx_cons) ||
3351 (bnx2_get_hw_tx_cons(bnapi) != txr->hw_tx_cons))
3356 #define STATUS_ATTN_EVENTS (STATUS_ATTN_BITS_LINK_STATE | \
3357 STATUS_ATTN_BITS_TIMER_ABORT)
3360 bnx2_has_work(struct bnx2_napi *bnapi)
3362 struct status_block *sblk = bnapi->status_blk.msi;
3364 if (bnx2_has_fast_work(bnapi))
3368 if (bnapi->cnic_present && (bnapi->cnic_tag != sblk->status_idx))
3372 if ((sblk->status_attn_bits & STATUS_ATTN_EVENTS) !=
3373 (sblk->status_attn_bits_ack & STATUS_ATTN_EVENTS))
3380 bnx2_chk_missed_msi(struct bnx2 *bp)
3382 struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
3385 if (bnx2_has_work(bnapi)) {
3386 msi_ctrl = REG_RD(bp, BNX2_PCICFG_MSI_CONTROL);
3387 if (!(msi_ctrl & BNX2_PCICFG_MSI_CONTROL_ENABLE))
3390 if (bnapi->last_status_idx == bp->idle_chk_status_idx) {
3391 REG_WR(bp, BNX2_PCICFG_MSI_CONTROL, msi_ctrl &
3392 ~BNX2_PCICFG_MSI_CONTROL_ENABLE);
3393 REG_WR(bp, BNX2_PCICFG_MSI_CONTROL, msi_ctrl);
3394 bnx2_msi(bp->irq_tbl[0].vector, bnapi);
3398 bp->idle_chk_status_idx = bnapi->last_status_idx;
3402 static void bnx2_poll_cnic(struct bnx2 *bp, struct bnx2_napi *bnapi)
3404 struct cnic_ops *c_ops;
3406 if (!bnapi->cnic_present)
3410 c_ops = rcu_dereference(bp->cnic_ops);
3412 bnapi->cnic_tag = c_ops->cnic_handler(bp->cnic_data,
3413 bnapi->status_blk.msi);
3418 static void bnx2_poll_link(struct bnx2 *bp, struct bnx2_napi *bnapi)
3420 struct status_block *sblk = bnapi->status_blk.msi;
3421 u32 status_attn_bits = sblk->status_attn_bits;
3422 u32 status_attn_bits_ack = sblk->status_attn_bits_ack;
3424 if ((status_attn_bits & STATUS_ATTN_EVENTS) !=
3425 (status_attn_bits_ack & STATUS_ATTN_EVENTS)) {
3427 bnx2_phy_int(bp, bnapi);
3429 /* This is needed to take care of transient status
3430 * during link changes.
3432 REG_WR(bp, BNX2_HC_COMMAND,
3433 bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
3434 REG_RD(bp, BNX2_HC_COMMAND);
3438 static int bnx2_poll_work(struct bnx2 *bp, struct bnx2_napi *bnapi,
3439 int work_done, int budget)
3441 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
3442 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
3444 if (bnx2_get_hw_tx_cons(bnapi) != txr->hw_tx_cons)
3445 bnx2_tx_int(bp, bnapi, 0);
3447 if (bnx2_get_hw_rx_cons(bnapi) != rxr->rx_cons)
3448 work_done += bnx2_rx_int(bp, bnapi, budget - work_done);
3453 static int bnx2_poll_msix(struct napi_struct *napi, int budget)
3455 struct bnx2_napi *bnapi = container_of(napi, struct bnx2_napi, napi);
3456 struct bnx2 *bp = bnapi->bp;
3458 struct status_block_msix *sblk = bnapi->status_blk.msix;
3461 work_done = bnx2_poll_work(bp, bnapi, work_done, budget);
3462 if (unlikely(work_done >= budget))
3465 bnapi->last_status_idx = sblk->status_idx;
3466 /* status idx must be read before checking for more work. */
3468 if (likely(!bnx2_has_fast_work(bnapi))) {
3470 napi_complete(napi);
3471 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
3472 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
3473 bnapi->last_status_idx);
3480 static int bnx2_poll(struct napi_struct *napi, int budget)
3482 struct bnx2_napi *bnapi = container_of(napi, struct bnx2_napi, napi);
3483 struct bnx2 *bp = bnapi->bp;
3485 struct status_block *sblk = bnapi->status_blk.msi;
3488 bnx2_poll_link(bp, bnapi);
3490 work_done = bnx2_poll_work(bp, bnapi, work_done, budget);
3493 bnx2_poll_cnic(bp, bnapi);
3496 /* bnapi->last_status_idx is used below to tell the hw how
3497 * much work has been processed, so we must read it before
3498 * checking for more work.
3500 bnapi->last_status_idx = sblk->status_idx;
3502 if (unlikely(work_done >= budget))
3506 if (likely(!bnx2_has_work(bnapi))) {
3507 napi_complete(napi);
3508 if (likely(bp->flags & BNX2_FLAG_USING_MSI_OR_MSIX)) {
3509 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3510 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
3511 bnapi->last_status_idx);
3514 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3515 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
3516 BNX2_PCICFG_INT_ACK_CMD_MASK_INT |
3517 bnapi->last_status_idx);
3519 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3520 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
3521 bnapi->last_status_idx);
3529 /* Called with rtnl_lock from vlan functions and also netif_tx_lock
3530 * from set_multicast.
3533 bnx2_set_rx_mode(struct net_device *dev)
3535 struct bnx2 *bp = netdev_priv(dev);
3536 u32 rx_mode, sort_mode;
3537 struct netdev_hw_addr *ha;
3540 if (!netif_running(dev))
3543 spin_lock_bh(&bp->phy_lock);
3545 rx_mode = bp->rx_mode & ~(BNX2_EMAC_RX_MODE_PROMISCUOUS |
3546 BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG);
3547 sort_mode = 1 | BNX2_RPM_SORT_USER0_BC_EN;
3548 if (!(dev->features & NETIF_F_HW_VLAN_RX) &&
3549 (bp->flags & BNX2_FLAG_CAN_KEEP_VLAN))
3550 rx_mode |= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG;
3551 if (dev->flags & IFF_PROMISC) {
3552 /* Promiscuous mode. */
3553 rx_mode |= BNX2_EMAC_RX_MODE_PROMISCUOUS;
3554 sort_mode |= BNX2_RPM_SORT_USER0_PROM_EN |
3555 BNX2_RPM_SORT_USER0_PROM_VLAN;
3557 else if (dev->flags & IFF_ALLMULTI) {
3558 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
3559 REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
3562 sort_mode |= BNX2_RPM_SORT_USER0_MC_EN;
3565 /* Accept one or more multicast(s). */
3566 u32 mc_filter[NUM_MC_HASH_REGISTERS];
3571 memset(mc_filter, 0, 4 * NUM_MC_HASH_REGISTERS);
3573 netdev_for_each_mc_addr(ha, dev) {
3574 crc = ether_crc_le(ETH_ALEN, ha->addr);
3576 regidx = (bit & 0xe0) >> 5;
3578 mc_filter[regidx] |= (1 << bit);
3581 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
3582 REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
3586 sort_mode |= BNX2_RPM_SORT_USER0_MC_HSH_EN;
3589 if (netdev_uc_count(dev) > BNX2_MAX_UNICAST_ADDRESSES) {
3590 rx_mode |= BNX2_EMAC_RX_MODE_PROMISCUOUS;
3591 sort_mode |= BNX2_RPM_SORT_USER0_PROM_EN |
3592 BNX2_RPM_SORT_USER0_PROM_VLAN;
3593 } else if (!(dev->flags & IFF_PROMISC)) {
3594 /* Add all entries into to the match filter list */
3596 netdev_for_each_uc_addr(ha, dev) {
3597 bnx2_set_mac_addr(bp, ha->addr,
3598 i + BNX2_START_UNICAST_ADDRESS_INDEX);
3600 (i + BNX2_START_UNICAST_ADDRESS_INDEX));
3606 if (rx_mode != bp->rx_mode) {
3607 bp->rx_mode = rx_mode;
3608 REG_WR(bp, BNX2_EMAC_RX_MODE, rx_mode);
3611 REG_WR(bp, BNX2_RPM_SORT_USER0, 0x0);
3612 REG_WR(bp, BNX2_RPM_SORT_USER0, sort_mode);
3613 REG_WR(bp, BNX2_RPM_SORT_USER0, sort_mode | BNX2_RPM_SORT_USER0_ENA);
3615 spin_unlock_bh(&bp->phy_lock);
3619 check_fw_section(const struct firmware *fw,
3620 const struct bnx2_fw_file_section *section,
3621 u32 alignment, bool non_empty)
3623 u32 offset = be32_to_cpu(section->offset);
3624 u32 len = be32_to_cpu(section->len);
3626 if ((offset == 0 && len != 0) || offset >= fw->size || offset & 3)
3628 if ((non_empty && len == 0) || len > fw->size - offset ||
3629 len & (alignment - 1))
3635 check_mips_fw_entry(const struct firmware *fw,
3636 const struct bnx2_mips_fw_file_entry *entry)
3638 if (check_fw_section(fw, &entry->text, 4, true) ||
3639 check_fw_section(fw, &entry->data, 4, false) ||
3640 check_fw_section(fw, &entry->rodata, 4, false))
3645 static void bnx2_release_firmware(struct bnx2 *bp)
3647 if (bp->rv2p_firmware) {
3648 release_firmware(bp->mips_firmware);
3649 release_firmware(bp->rv2p_firmware);
3650 bp->rv2p_firmware = NULL;
3654 static int bnx2_request_uncached_firmware(struct bnx2 *bp)
3656 const char *mips_fw_file, *rv2p_fw_file;
3657 const struct bnx2_mips_fw_file *mips_fw;
3658 const struct bnx2_rv2p_fw_file *rv2p_fw;
3661 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
3662 mips_fw_file = FW_MIPS_FILE_09;
3663 if ((CHIP_ID(bp) == CHIP_ID_5709_A0) ||
3664 (CHIP_ID(bp) == CHIP_ID_5709_A1))
3665 rv2p_fw_file = FW_RV2P_FILE_09_Ax;
3667 rv2p_fw_file = FW_RV2P_FILE_09;
3669 mips_fw_file = FW_MIPS_FILE_06;
3670 rv2p_fw_file = FW_RV2P_FILE_06;
3673 rc = request_firmware(&bp->mips_firmware, mips_fw_file, &bp->pdev->dev);
3675 pr_err("Can't load firmware file \"%s\"\n", mips_fw_file);
3679 rc = request_firmware(&bp->rv2p_firmware, rv2p_fw_file, &bp->pdev->dev);
3681 pr_err("Can't load firmware file \"%s\"\n", rv2p_fw_file);
3682 goto err_release_mips_firmware;
3684 mips_fw = (const struct bnx2_mips_fw_file *) bp->mips_firmware->data;
3685 rv2p_fw = (const struct bnx2_rv2p_fw_file *) bp->rv2p_firmware->data;
3686 if (bp->mips_firmware->size < sizeof(*mips_fw) ||
3687 check_mips_fw_entry(bp->mips_firmware, &mips_fw->com) ||
3688 check_mips_fw_entry(bp->mips_firmware, &mips_fw->cp) ||
3689 check_mips_fw_entry(bp->mips_firmware, &mips_fw->rxp) ||
3690 check_mips_fw_entry(bp->mips_firmware, &mips_fw->tpat) ||
3691 check_mips_fw_entry(bp->mips_firmware, &mips_fw->txp)) {
3692 pr_err("Firmware file \"%s\" is invalid\n", mips_fw_file);
3694 goto err_release_firmware;
3696 if (bp->rv2p_firmware->size < sizeof(*rv2p_fw) ||
3697 check_fw_section(bp->rv2p_firmware, &rv2p_fw->proc1.rv2p, 8, true) ||
3698 check_fw_section(bp->rv2p_firmware, &rv2p_fw->proc2.rv2p, 8, true)) {
3699 pr_err("Firmware file \"%s\" is invalid\n", rv2p_fw_file);
3701 goto err_release_firmware;
3706 err_release_firmware:
3707 release_firmware(bp->rv2p_firmware);
3708 bp->rv2p_firmware = NULL;
3709 err_release_mips_firmware:
3710 release_firmware(bp->mips_firmware);
3714 static int bnx2_request_firmware(struct bnx2 *bp)
3716 return bp->rv2p_firmware ? 0 : bnx2_request_uncached_firmware(bp);
3720 rv2p_fw_fixup(u32 rv2p_proc, int idx, u32 loc, u32 rv2p_code)
3723 case RV2P_P1_FIXUP_PAGE_SIZE_IDX:
3724 rv2p_code &= ~RV2P_BD_PAGE_SIZE_MSK;
3725 rv2p_code |= RV2P_BD_PAGE_SIZE;
3732 load_rv2p_fw(struct bnx2 *bp, u32 rv2p_proc,
3733 const struct bnx2_rv2p_fw_file_entry *fw_entry)
3735 u32 rv2p_code_len, file_offset;
3740 rv2p_code_len = be32_to_cpu(fw_entry->rv2p.len);
3741 file_offset = be32_to_cpu(fw_entry->rv2p.offset);
3743 rv2p_code = (__be32 *)(bp->rv2p_firmware->data + file_offset);
3745 if (rv2p_proc == RV2P_PROC1) {
3746 cmd = BNX2_RV2P_PROC1_ADDR_CMD_RDWR;
3747 addr = BNX2_RV2P_PROC1_ADDR_CMD;
3749 cmd = BNX2_RV2P_PROC2_ADDR_CMD_RDWR;
3750 addr = BNX2_RV2P_PROC2_ADDR_CMD;
3753 for (i = 0; i < rv2p_code_len; i += 8) {
3754 REG_WR(bp, BNX2_RV2P_INSTR_HIGH, be32_to_cpu(*rv2p_code));
3756 REG_WR(bp, BNX2_RV2P_INSTR_LOW, be32_to_cpu(*rv2p_code));
3759 val = (i / 8) | cmd;
3760 REG_WR(bp, addr, val);
3763 rv2p_code = (__be32 *)(bp->rv2p_firmware->data + file_offset);
3764 for (i = 0; i < 8; i++) {
3767 loc = be32_to_cpu(fw_entry->fixup[i]);
3768 if (loc && ((loc * 4) < rv2p_code_len)) {
3769 code = be32_to_cpu(*(rv2p_code + loc - 1));
3770 REG_WR(bp, BNX2_RV2P_INSTR_HIGH, code);
3771 code = be32_to_cpu(*(rv2p_code + loc));
3772 code = rv2p_fw_fixup(rv2p_proc, i, loc, code);
3773 REG_WR(bp, BNX2_RV2P_INSTR_LOW, code);
3775 val = (loc / 2) | cmd;
3776 REG_WR(bp, addr, val);
3780 /* Reset the processor, un-stall is done later. */
3781 if (rv2p_proc == RV2P_PROC1) {
3782 REG_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC1_RESET);
3785 REG_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC2_RESET);
3792 load_cpu_fw(struct bnx2 *bp, const struct cpu_reg *cpu_reg,
3793 const struct bnx2_mips_fw_file_entry *fw_entry)
3795 u32 addr, len, file_offset;
3801 val = bnx2_reg_rd_ind(bp, cpu_reg->mode);
3802 val |= cpu_reg->mode_value_halt;
3803 bnx2_reg_wr_ind(bp, cpu_reg->mode, val);
3804 bnx2_reg_wr_ind(bp, cpu_reg->state, cpu_reg->state_value_clear);
3806 /* Load the Text area. */
3807 addr = be32_to_cpu(fw_entry->text.addr);
3808 len = be32_to_cpu(fw_entry->text.len);
3809 file_offset = be32_to_cpu(fw_entry->text.offset);
3810 data = (__be32 *)(bp->mips_firmware->data + file_offset);
3812 offset = cpu_reg->spad_base + (addr - cpu_reg->mips_view_base);
3816 for (j = 0; j < (len / 4); j++, offset += 4)
3817 bnx2_reg_wr_ind(bp, offset, be32_to_cpu(data[j]));
3820 /* Load the Data area. */
3821 addr = be32_to_cpu(fw_entry->data.addr);
3822 len = be32_to_cpu(fw_entry->data.len);
3823 file_offset = be32_to_cpu(fw_entry->data.offset);
3824 data = (__be32 *)(bp->mips_firmware->data + file_offset);
3826 offset = cpu_reg->spad_base + (addr - cpu_reg->mips_view_base);
3830 for (j = 0; j < (len / 4); j++, offset += 4)
3831 bnx2_reg_wr_ind(bp, offset, be32_to_cpu(data[j]));
3834 /* Load the Read-Only area. */
3835 addr = be32_to_cpu(fw_entry->rodata.addr);
3836 len = be32_to_cpu(fw_entry->rodata.len);
3837 file_offset = be32_to_cpu(fw_entry->rodata.offset);
3838 data = (__be32 *)(bp->mips_firmware->data + file_offset);
3840 offset = cpu_reg->spad_base + (addr - cpu_reg->mips_view_base);
3844 for (j = 0; j < (len / 4); j++, offset += 4)
3845 bnx2_reg_wr_ind(bp, offset, be32_to_cpu(data[j]));
3848 /* Clear the pre-fetch instruction. */
3849 bnx2_reg_wr_ind(bp, cpu_reg->inst, 0);
3851 val = be32_to_cpu(fw_entry->start_addr);
3852 bnx2_reg_wr_ind(bp, cpu_reg->pc, val);
3854 /* Start the CPU. */
3855 val = bnx2_reg_rd_ind(bp, cpu_reg->mode);
3856 val &= ~cpu_reg->mode_value_halt;
3857 bnx2_reg_wr_ind(bp, cpu_reg->state, cpu_reg->state_value_clear);
3858 bnx2_reg_wr_ind(bp, cpu_reg->mode, val);
3864 bnx2_init_cpus(struct bnx2 *bp)
3866 const struct bnx2_mips_fw_file *mips_fw =
3867 (const struct bnx2_mips_fw_file *) bp->mips_firmware->data;
3868 const struct bnx2_rv2p_fw_file *rv2p_fw =
3869 (const struct bnx2_rv2p_fw_file *) bp->rv2p_firmware->data;
3872 /* Initialize the RV2P processor. */
3873 load_rv2p_fw(bp, RV2P_PROC1, &rv2p_fw->proc1);
3874 load_rv2p_fw(bp, RV2P_PROC2, &rv2p_fw->proc2);
3876 /* Initialize the RX Processor. */
3877 rc = load_cpu_fw(bp, &cpu_reg_rxp, &mips_fw->rxp);
3881 /* Initialize the TX Processor. */
3882 rc = load_cpu_fw(bp, &cpu_reg_txp, &mips_fw->txp);
3886 /* Initialize the TX Patch-up Processor. */
3887 rc = load_cpu_fw(bp, &cpu_reg_tpat, &mips_fw->tpat);
3891 /* Initialize the Completion Processor. */
3892 rc = load_cpu_fw(bp, &cpu_reg_com, &mips_fw->com);
3896 /* Initialize the Command Processor. */
3897 rc = load_cpu_fw(bp, &cpu_reg_cp, &mips_fw->cp);
3904 bnx2_set_power_state(struct bnx2 *bp, pci_power_t state)
3908 pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, &pmcsr);
3914 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL,
3915 (pmcsr & ~PCI_PM_CTRL_STATE_MASK) |
3916 PCI_PM_CTRL_PME_STATUS);
3918 if (pmcsr & PCI_PM_CTRL_STATE_MASK)
3919 /* delay required during transition out of D3hot */
3922 val = REG_RD(bp, BNX2_EMAC_MODE);
3923 val |= BNX2_EMAC_MODE_MPKT_RCVD | BNX2_EMAC_MODE_ACPI_RCVD;
3924 val &= ~BNX2_EMAC_MODE_MPKT;
3925 REG_WR(bp, BNX2_EMAC_MODE, val);
3927 val = REG_RD(bp, BNX2_RPM_CONFIG);
3928 val &= ~BNX2_RPM_CONFIG_ACPI_ENA;
3929 REG_WR(bp, BNX2_RPM_CONFIG, val);
3940 autoneg = bp->autoneg;
3941 advertising = bp->advertising;
3943 if (bp->phy_port == PORT_TP) {
3944 bp->autoneg = AUTONEG_SPEED;
3945 bp->advertising = ADVERTISED_10baseT_Half |
3946 ADVERTISED_10baseT_Full |
3947 ADVERTISED_100baseT_Half |
3948 ADVERTISED_100baseT_Full |
3952 spin_lock_bh(&bp->phy_lock);
3953 bnx2_setup_phy(bp, bp->phy_port);
3954 spin_unlock_bh(&bp->phy_lock);
3956 bp->autoneg = autoneg;
3957 bp->advertising = advertising;
3959 bnx2_set_mac_addr(bp, bp->dev->dev_addr, 0);
3961 val = REG_RD(bp, BNX2_EMAC_MODE);
3963 /* Enable port mode. */
3964 val &= ~BNX2_EMAC_MODE_PORT;
3965 val |= BNX2_EMAC_MODE_MPKT_RCVD |
3966 BNX2_EMAC_MODE_ACPI_RCVD |
3967 BNX2_EMAC_MODE_MPKT;
3968 if (bp->phy_port == PORT_TP)
3969 val |= BNX2_EMAC_MODE_PORT_MII;
3971 val |= BNX2_EMAC_MODE_PORT_GMII;
3972 if (bp->line_speed == SPEED_2500)
3973 val |= BNX2_EMAC_MODE_25G_MODE;
3976 REG_WR(bp, BNX2_EMAC_MODE, val);
3978 /* receive all multicast */
3979 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
3980 REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
3983 REG_WR(bp, BNX2_EMAC_RX_MODE,
3984 BNX2_EMAC_RX_MODE_SORT_MODE);
3986 val = 1 | BNX2_RPM_SORT_USER0_BC_EN |
3987 BNX2_RPM_SORT_USER0_MC_EN;
3988 REG_WR(bp, BNX2_RPM_SORT_USER0, 0x0);
3989 REG_WR(bp, BNX2_RPM_SORT_USER0, val);
3990 REG_WR(bp, BNX2_RPM_SORT_USER0, val |
3991 BNX2_RPM_SORT_USER0_ENA);
3993 /* Need to enable EMAC and RPM for WOL. */
3994 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
3995 BNX2_MISC_ENABLE_SET_BITS_RX_PARSER_MAC_ENABLE |
3996 BNX2_MISC_ENABLE_SET_BITS_TX_HEADER_Q_ENABLE |
3997 BNX2_MISC_ENABLE_SET_BITS_EMAC_ENABLE);
3999 val = REG_RD(bp, BNX2_RPM_CONFIG);
4000 val &= ~BNX2_RPM_CONFIG_ACPI_ENA;
4001 REG_WR(bp, BNX2_RPM_CONFIG, val);
4003 wol_msg = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
4006 wol_msg = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
4009 if (!(bp->flags & BNX2_FLAG_NO_WOL))
4010 bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT3 | wol_msg,
4013 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
4014 if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
4015 (CHIP_ID(bp) == CHIP_ID_5706_A1)) {
4024 pmcsr |= PCI_PM_CTRL_PME_ENABLE;
4026 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL,
4029 /* No more memory access after this point until
4030 * device is brought back to D0.
4042 bnx2_acquire_nvram_lock(struct bnx2 *bp)
4047 /* Request access to the flash interface. */
4048 REG_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_SET2);
4049 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
4050 val = REG_RD(bp, BNX2_NVM_SW_ARB);
4051 if (val & BNX2_NVM_SW_ARB_ARB_ARB2)
4057 if (j >= NVRAM_TIMEOUT_COUNT)
4064 bnx2_release_nvram_lock(struct bnx2 *bp)
4069 /* Relinquish nvram interface. */
4070 REG_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_CLR2);
4072 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
4073 val = REG_RD(bp, BNX2_NVM_SW_ARB);
4074 if (!(val & BNX2_NVM_SW_ARB_ARB_ARB2))
4080 if (j >= NVRAM_TIMEOUT_COUNT)
4088 bnx2_enable_nvram_write(struct bnx2 *bp)
4092 val = REG_RD(bp, BNX2_MISC_CFG);
4093 REG_WR(bp, BNX2_MISC_CFG, val | BNX2_MISC_CFG_NVM_WR_EN_PCI);
4095 if (bp->flash_info->flags & BNX2_NV_WREN) {
4098 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
4099 REG_WR(bp, BNX2_NVM_COMMAND,
4100 BNX2_NVM_COMMAND_WREN | BNX2_NVM_COMMAND_DOIT);
4102 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
4105 val = REG_RD(bp, BNX2_NVM_COMMAND);
4106 if (val & BNX2_NVM_COMMAND_DONE)
4110 if (j >= NVRAM_TIMEOUT_COUNT)
4117 bnx2_disable_nvram_write(struct bnx2 *bp)
4121 val = REG_RD(bp, BNX2_MISC_CFG);
4122 REG_WR(bp, BNX2_MISC_CFG, val & ~BNX2_MISC_CFG_NVM_WR_EN);
4127 bnx2_enable_nvram_access(struct bnx2 *bp)
4131 val = REG_RD(bp, BNX2_NVM_ACCESS_ENABLE);
4132 /* Enable both bits, even on read. */
4133 REG_WR(bp, BNX2_NVM_ACCESS_ENABLE,
4134 val | BNX2_NVM_ACCESS_ENABLE_EN | BNX2_NVM_ACCESS_ENABLE_WR_EN);
4138 bnx2_disable_nvram_access(struct bnx2 *bp)
4142 val = REG_RD(bp, BNX2_NVM_ACCESS_ENABLE);
4143 /* Disable both bits, even after read. */
4144 REG_WR(bp, BNX2_NVM_ACCESS_ENABLE,
4145 val & ~(BNX2_NVM_ACCESS_ENABLE_EN |
4146 BNX2_NVM_ACCESS_ENABLE_WR_EN));
4150 bnx2_nvram_erase_page(struct bnx2 *bp, u32 offset)
4155 if (bp->flash_info->flags & BNX2_NV_BUFFERED)
4156 /* Buffered flash, no erase needed */
4159 /* Build an erase command */
4160 cmd = BNX2_NVM_COMMAND_ERASE | BNX2_NVM_COMMAND_WR |
4161 BNX2_NVM_COMMAND_DOIT;
4163 /* Need to clear DONE bit separately. */
4164 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
4166 /* Address of the NVRAM to read from. */
4167 REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
4169 /* Issue an erase command. */
4170 REG_WR(bp, BNX2_NVM_COMMAND, cmd);
4172 /* Wait for completion. */
4173 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
4178 val = REG_RD(bp, BNX2_NVM_COMMAND);
4179 if (val & BNX2_NVM_COMMAND_DONE)
4183 if (j >= NVRAM_TIMEOUT_COUNT)
4190 bnx2_nvram_read_dword(struct bnx2 *bp, u32 offset, u8 *ret_val, u32 cmd_flags)
4195 /* Build the command word. */
4196 cmd = BNX2_NVM_COMMAND_DOIT | cmd_flags;
4198 /* Calculate an offset of a buffered flash, not needed for 5709. */
4199 if (bp->flash_info->flags & BNX2_NV_TRANSLATE) {
4200 offset = ((offset / bp->flash_info->page_size) <<
4201 bp->flash_info->page_bits) +
4202 (offset % bp->flash_info->page_size);
4205 /* Need to clear DONE bit separately. */
4206 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
4208 /* Address of the NVRAM to read from. */
4209 REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
4211 /* Issue a read command. */
4212 REG_WR(bp, BNX2_NVM_COMMAND, cmd);
4214 /* Wait for completion. */
4215 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
4220 val = REG_RD(bp, BNX2_NVM_COMMAND);
4221 if (val & BNX2_NVM_COMMAND_DONE) {
4222 __be32 v = cpu_to_be32(REG_RD(bp, BNX2_NVM_READ));
4223 memcpy(ret_val, &v, 4);
4227 if (j >= NVRAM_TIMEOUT_COUNT)
4235 bnx2_nvram_write_dword(struct bnx2 *bp, u32 offset, u8 *val, u32 cmd_flags)
4241 /* Build the command word. */
4242 cmd = BNX2_NVM_COMMAND_DOIT | BNX2_NVM_COMMAND_WR | cmd_flags;
4244 /* Calculate an offset of a buffered flash, not needed for 5709. */
4245 if (bp->flash_info->flags & BNX2_NV_TRANSLATE) {
4246 offset = ((offset / bp->flash_info->page_size) <<
4247 bp->flash_info->page_bits) +
4248 (offset % bp->flash_info->page_size);
4251 /* Need to clear DONE bit separately. */
4252 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
4254 memcpy(&val32, val, 4);
4256 /* Write the data. */
4257 REG_WR(bp, BNX2_NVM_WRITE, be32_to_cpu(val32));
4259 /* Address of the NVRAM to write to. */
4260 REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
4262 /* Issue the write command. */
4263 REG_WR(bp, BNX2_NVM_COMMAND, cmd);
4265 /* Wait for completion. */
4266 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
4269 if (REG_RD(bp, BNX2_NVM_COMMAND) & BNX2_NVM_COMMAND_DONE)
4272 if (j >= NVRAM_TIMEOUT_COUNT)
4279 bnx2_init_nvram(struct bnx2 *bp)
4282 int j, entry_count, rc = 0;
4283 const struct flash_spec *flash;
4285 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4286 bp->flash_info = &flash_5709;
4287 goto get_flash_size;
4290 /* Determine the selected interface. */
4291 val = REG_RD(bp, BNX2_NVM_CFG1);
4293 entry_count = ARRAY_SIZE(flash_table);
4295 if (val & 0x40000000) {
4297 /* Flash interface has been reconfigured */
4298 for (j = 0, flash = &flash_table[0]; j < entry_count;
4300 if ((val & FLASH_BACKUP_STRAP_MASK) ==
4301 (flash->config1 & FLASH_BACKUP_STRAP_MASK)) {
4302 bp->flash_info = flash;
4309 /* Not yet been reconfigured */
4311 if (val & (1 << 23))
4312 mask = FLASH_BACKUP_STRAP_MASK;
4314 mask = FLASH_STRAP_MASK;
4316 for (j = 0, flash = &flash_table[0]; j < entry_count;
4319 if ((val & mask) == (flash->strapping & mask)) {
4320 bp->flash_info = flash;
4322 /* Request access to the flash interface. */
4323 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
4326 /* Enable access to flash interface */
4327 bnx2_enable_nvram_access(bp);
4329 /* Reconfigure the flash interface */
4330 REG_WR(bp, BNX2_NVM_CFG1, flash->config1);
4331 REG_WR(bp, BNX2_NVM_CFG2, flash->config2);
4332 REG_WR(bp, BNX2_NVM_CFG3, flash->config3);
4333 REG_WR(bp, BNX2_NVM_WRITE1, flash->write1);
4335 /* Disable access to flash interface */
4336 bnx2_disable_nvram_access(bp);
4337 bnx2_release_nvram_lock(bp);
4342 } /* if (val & 0x40000000) */
4344 if (j == entry_count) {
4345 bp->flash_info = NULL;
4346 pr_alert("Unknown flash/EEPROM type\n");
4351 val = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG2);
4352 val &= BNX2_SHARED_HW_CFG2_NVM_SIZE_MASK;
4354 bp->flash_size = val;
4356 bp->flash_size = bp->flash_info->total_size;
4362 bnx2_nvram_read(struct bnx2 *bp, u32 offset, u8 *ret_buf,
4366 u32 cmd_flags, offset32, len32, extra;
4371 /* Request access to the flash interface. */
4372 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
4375 /* Enable access to flash interface */
4376 bnx2_enable_nvram_access(bp);
4389 pre_len = 4 - (offset & 3);
4391 if (pre_len >= len32) {
4393 cmd_flags = BNX2_NVM_COMMAND_FIRST |
4394 BNX2_NVM_COMMAND_LAST;
4397 cmd_flags = BNX2_NVM_COMMAND_FIRST;
4400 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
4405 memcpy(ret_buf, buf + (offset & 3), pre_len);
4412 extra = 4 - (len32 & 3);
4413 len32 = (len32 + 4) & ~3;
4420 cmd_flags = BNX2_NVM_COMMAND_LAST;
4422 cmd_flags = BNX2_NVM_COMMAND_FIRST |
4423 BNX2_NVM_COMMAND_LAST;
4425 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
4427 memcpy(ret_buf, buf, 4 - extra);
4429 else if (len32 > 0) {
4432 /* Read the first word. */
4436 cmd_flags = BNX2_NVM_COMMAND_FIRST;
4438 rc = bnx2_nvram_read_dword(bp, offset32, ret_buf, cmd_flags);
4440 /* Advance to the next dword. */
4445 while (len32 > 4 && rc == 0) {
4446 rc = bnx2_nvram_read_dword(bp, offset32, ret_buf, 0);
4448 /* Advance to the next dword. */
4457 cmd_flags = BNX2_NVM_COMMAND_LAST;
4458 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
4460 memcpy(ret_buf, buf, 4 - extra);
4463 /* Disable access to flash interface */
4464 bnx2_disable_nvram_access(bp);
4466 bnx2_release_nvram_lock(bp);
4472 bnx2_nvram_write(struct bnx2 *bp, u32 offset, u8 *data_buf,
4475 u32 written, offset32, len32;
4476 u8 *buf, start[4], end[4], *align_buf = NULL, *flash_buffer = NULL;
4478 int align_start, align_end;
4483 align_start = align_end = 0;
4485 if ((align_start = (offset32 & 3))) {
4487 len32 += align_start;
4490 if ((rc = bnx2_nvram_read(bp, offset32, start, 4)))
4495 align_end = 4 - (len32 & 3);
4497 if ((rc = bnx2_nvram_read(bp, offset32 + len32 - 4, end, 4)))
4501 if (align_start || align_end) {
4502 align_buf = kmalloc(len32, GFP_KERNEL);
4503 if (align_buf == NULL)
4506 memcpy(align_buf, start, 4);
4509 memcpy(align_buf + len32 - 4, end, 4);
4511 memcpy(align_buf + align_start, data_buf, buf_size);
4515 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
4516 flash_buffer = kmalloc(264, GFP_KERNEL);
4517 if (flash_buffer == NULL) {
4519 goto nvram_write_end;
4524 while ((written < len32) && (rc == 0)) {
4525 u32 page_start, page_end, data_start, data_end;
4526 u32 addr, cmd_flags;
4529 /* Find the page_start addr */
4530 page_start = offset32 + written;
4531 page_start -= (page_start % bp->flash_info->page_size);
4532 /* Find the page_end addr */
4533 page_end = page_start + bp->flash_info->page_size;
4534 /* Find the data_start addr */
4535 data_start = (written == 0) ? offset32 : page_start;
4536 /* Find the data_end addr */
4537 data_end = (page_end > offset32 + len32) ?
4538 (offset32 + len32) : page_end;
4540 /* Request access to the flash interface. */
4541 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
4542 goto nvram_write_end;
4544 /* Enable access to flash interface */
4545 bnx2_enable_nvram_access(bp);
4547 cmd_flags = BNX2_NVM_COMMAND_FIRST;
4548 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
4551 /* Read the whole page into the buffer
4552 * (non-buffer flash only) */
4553 for (j = 0; j < bp->flash_info->page_size; j += 4) {
4554 if (j == (bp->flash_info->page_size - 4)) {
4555 cmd_flags |= BNX2_NVM_COMMAND_LAST;
4557 rc = bnx2_nvram_read_dword(bp,
4563 goto nvram_write_end;
4569 /* Enable writes to flash interface (unlock write-protect) */
4570 if ((rc = bnx2_enable_nvram_write(bp)) != 0)
4571 goto nvram_write_end;
4573 /* Loop to write back the buffer data from page_start to
4576 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
4577 /* Erase the page */
4578 if ((rc = bnx2_nvram_erase_page(bp, page_start)) != 0)
4579 goto nvram_write_end;
4581 /* Re-enable the write again for the actual write */
4582 bnx2_enable_nvram_write(bp);
4584 for (addr = page_start; addr < data_start;
4585 addr += 4, i += 4) {
4587 rc = bnx2_nvram_write_dword(bp, addr,
4588 &flash_buffer[i], cmd_flags);
4591 goto nvram_write_end;
4597 /* Loop to write the new data from data_start to data_end */
4598 for (addr = data_start; addr < data_end; addr += 4, i += 4) {
4599 if ((addr == page_end - 4) ||
4600 ((bp->flash_info->flags & BNX2_NV_BUFFERED) &&
4601 (addr == data_end - 4))) {
4603 cmd_flags |= BNX2_NVM_COMMAND_LAST;
4605 rc = bnx2_nvram_write_dword(bp, addr, buf,
4609 goto nvram_write_end;
4615 /* Loop to write back the buffer data from data_end
4617 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
4618 for (addr = data_end; addr < page_end;
4619 addr += 4, i += 4) {
4621 if (addr == page_end-4) {
4622 cmd_flags = BNX2_NVM_COMMAND_LAST;
4624 rc = bnx2_nvram_write_dword(bp, addr,
4625 &flash_buffer[i], cmd_flags);
4628 goto nvram_write_end;
4634 /* Disable writes to flash interface (lock write-protect) */
4635 bnx2_disable_nvram_write(bp);
4637 /* Disable access to flash interface */
4638 bnx2_disable_nvram_access(bp);
4639 bnx2_release_nvram_lock(bp);
4641 /* Increment written */
4642 written += data_end - data_start;
4646 kfree(flash_buffer);
4652 bnx2_init_fw_cap(struct bnx2 *bp)
4656 bp->phy_flags &= ~BNX2_PHY_FLAG_REMOTE_PHY_CAP;
4657 bp->flags &= ~BNX2_FLAG_CAN_KEEP_VLAN;
4659 if (!(bp->flags & BNX2_FLAG_ASF_ENABLE))
4660 bp->flags |= BNX2_FLAG_CAN_KEEP_VLAN;
4662 val = bnx2_shmem_rd(bp, BNX2_FW_CAP_MB);
4663 if ((val & BNX2_FW_CAP_SIGNATURE_MASK) != BNX2_FW_CAP_SIGNATURE)
4666 if ((val & BNX2_FW_CAP_CAN_KEEP_VLAN) == BNX2_FW_CAP_CAN_KEEP_VLAN) {
4667 bp->flags |= BNX2_FLAG_CAN_KEEP_VLAN;
4668 sig |= BNX2_DRV_ACK_CAP_SIGNATURE | BNX2_FW_CAP_CAN_KEEP_VLAN;
4671 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
4672 (val & BNX2_FW_CAP_REMOTE_PHY_CAPABLE)) {
4675 bp->phy_flags |= BNX2_PHY_FLAG_REMOTE_PHY_CAP;
4677 link = bnx2_shmem_rd(bp, BNX2_LINK_STATUS);
4678 if (link & BNX2_LINK_STATUS_SERDES_LINK)
4679 bp->phy_port = PORT_FIBRE;
4681 bp->phy_port = PORT_TP;
4683 sig |= BNX2_DRV_ACK_CAP_SIGNATURE |
4684 BNX2_FW_CAP_REMOTE_PHY_CAPABLE;
4687 if (netif_running(bp->dev) && sig)
4688 bnx2_shmem_wr(bp, BNX2_DRV_ACK_CAP_MB, sig);
4692 bnx2_setup_msix_tbl(struct bnx2 *bp)
4694 REG_WR(bp, BNX2_PCI_GRC_WINDOW_ADDR, BNX2_PCI_GRC_WINDOW_ADDR_SEP_WIN);
4696 REG_WR(bp, BNX2_PCI_GRC_WINDOW2_ADDR, BNX2_MSIX_TABLE_ADDR);
4697 REG_WR(bp, BNX2_PCI_GRC_WINDOW3_ADDR, BNX2_MSIX_PBA_ADDR);
4701 bnx2_reset_chip(struct bnx2 *bp, u32 reset_code)
4707 /* Wait for the current PCI transaction to complete before
4708 * issuing a reset. */
4709 if ((CHIP_NUM(bp) == CHIP_NUM_5706) ||
4710 (CHIP_NUM(bp) == CHIP_NUM_5708)) {
4711 REG_WR(bp, BNX2_MISC_ENABLE_CLR_BITS,
4712 BNX2_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE |
4713 BNX2_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE |
4714 BNX2_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE |
4715 BNX2_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE);
4716 val = REG_RD(bp, BNX2_MISC_ENABLE_CLR_BITS);
4719 val = REG_RD(bp, BNX2_MISC_NEW_CORE_CTL);
4720 val &= ~BNX2_MISC_NEW_CORE_CTL_DMA_ENABLE;
4721 REG_WR(bp, BNX2_MISC_NEW_CORE_CTL, val);
4722 val = REG_RD(bp, BNX2_MISC_NEW_CORE_CTL);
4724 for (i = 0; i < 100; i++) {
4726 val = REG_RD(bp, BNX2_PCICFG_DEVICE_CONTROL);
4727 if (!(val & BNX2_PCICFG_DEVICE_STATUS_NO_PEND))
4732 /* Wait for the firmware to tell us it is ok to issue a reset. */
4733 bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT0 | reset_code, 1, 1);
4735 /* Deposit a driver reset signature so the firmware knows that
4736 * this is a soft reset. */
4737 bnx2_shmem_wr(bp, BNX2_DRV_RESET_SIGNATURE,
4738 BNX2_DRV_RESET_SIGNATURE_MAGIC);
4740 /* Do a dummy read to force the chip to complete all current transaction
4741 * before we issue a reset. */
4742 val = REG_RD(bp, BNX2_MISC_ID);
4744 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4745 REG_WR(bp, BNX2_MISC_COMMAND, BNX2_MISC_COMMAND_SW_RESET);
4746 REG_RD(bp, BNX2_MISC_COMMAND);
4749 val = BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
4750 BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
4752 REG_WR(bp, BNX2_PCICFG_MISC_CONFIG, val);
4755 val = BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
4756 BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
4757 BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
4760 REG_WR(bp, BNX2_PCICFG_MISC_CONFIG, val);
4762 /* Reading back any register after chip reset will hang the
4763 * bus on 5706 A0 and A1. The msleep below provides plenty
4764 * of margin for write posting.
4766 if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
4767 (CHIP_ID(bp) == CHIP_ID_5706_A1))
4770 /* Reset takes approximate 30 usec */
4771 for (i = 0; i < 10; i++) {
4772 val = REG_RD(bp, BNX2_PCICFG_MISC_CONFIG);
4773 if ((val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
4774 BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0)
4779 if (val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
4780 BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) {
4781 pr_err("Chip reset did not complete\n");
4786 /* Make sure byte swapping is properly configured. */
4787 val = REG_RD(bp, BNX2_PCI_SWAP_DIAG0);
4788 if (val != 0x01020304) {
4789 pr_err("Chip not in correct endian mode\n");
4793 /* Wait for the firmware to finish its initialization. */
4794 rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT1 | reset_code, 1, 0);
4798 spin_lock_bh(&bp->phy_lock);
4799 old_port = bp->phy_port;
4800 bnx2_init_fw_cap(bp);
4801 if ((bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) &&
4802 old_port != bp->phy_port)
4803 bnx2_set_default_remote_link(bp);
4804 spin_unlock_bh(&bp->phy_lock);
4806 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
4807 /* Adjust the voltage regular to two steps lower. The default
4808 * of this register is 0x0000000e. */
4809 REG_WR(bp, BNX2_MISC_VREG_CONTROL, 0x000000fa);
4811 /* Remove bad rbuf memory from the free pool. */
4812 rc = bnx2_alloc_bad_rbuf(bp);
4815 if (bp->flags & BNX2_FLAG_USING_MSIX) {
4816 bnx2_setup_msix_tbl(bp);
4817 /* Prevent MSIX table reads and write from timing out */
4818 REG_WR(bp, BNX2_MISC_ECO_HW_CTL,
4819 BNX2_MISC_ECO_HW_CTL_LARGE_GRC_TMOUT_EN);
4826 bnx2_init_chip(struct bnx2 *bp)
4831 /* Make sure the interrupt is not active. */
4832 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
4834 val = BNX2_DMA_CONFIG_DATA_BYTE_SWAP |
4835 BNX2_DMA_CONFIG_DATA_WORD_SWAP |
4837 BNX2_DMA_CONFIG_CNTL_BYTE_SWAP |
4839 BNX2_DMA_CONFIG_CNTL_WORD_SWAP |
4840 DMA_READ_CHANS << 12 |
4841 DMA_WRITE_CHANS << 16;
4843 val |= (0x2 << 20) | (1 << 11);
4845 if ((bp->flags & BNX2_FLAG_PCIX) && (bp->bus_speed_mhz == 133))
4848 if ((CHIP_NUM(bp) == CHIP_NUM_5706) &&
4849 (CHIP_ID(bp) != CHIP_ID_5706_A0) && !(bp->flags & BNX2_FLAG_PCIX))
4850 val |= BNX2_DMA_CONFIG_CNTL_PING_PONG_DMA;
4852 REG_WR(bp, BNX2_DMA_CONFIG, val);
4854 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
4855 val = REG_RD(bp, BNX2_TDMA_CONFIG);
4856 val |= BNX2_TDMA_CONFIG_ONE_DMA;
4857 REG_WR(bp, BNX2_TDMA_CONFIG, val);
4860 if (bp->flags & BNX2_FLAG_PCIX) {
4863 pci_read_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD,
4865 pci_write_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD,
4866 val16 & ~PCI_X_CMD_ERO);
4869 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
4870 BNX2_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE |
4871 BNX2_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE |
4872 BNX2_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE);
4874 /* Initialize context mapping and zero out the quick contexts. The
4875 * context block must have already been enabled. */
4876 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4877 rc = bnx2_init_5709_context(bp);
4881 bnx2_init_context(bp);
4883 if ((rc = bnx2_init_cpus(bp)) != 0)
4886 bnx2_init_nvram(bp);
4888 bnx2_set_mac_addr(bp, bp->dev->dev_addr, 0);
4890 val = REG_RD(bp, BNX2_MQ_CONFIG);
4891 val &= ~BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE;
4892 val |= BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_256;
4893 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4894 val |= BNX2_MQ_CONFIG_BIN_MQ_MODE;
4895 if (CHIP_REV(bp) == CHIP_REV_Ax)
4896 val |= BNX2_MQ_CONFIG_HALT_DIS;
4899 REG_WR(bp, BNX2_MQ_CONFIG, val);
4901 val = 0x10000 + (MAX_CID_CNT * MB_KERNEL_CTX_SIZE);
4902 REG_WR(bp, BNX2_MQ_KNL_BYP_WIND_START, val);
4903 REG_WR(bp, BNX2_MQ_KNL_WIND_END, val);
4905 val = (BCM_PAGE_BITS - 8) << 24;
4906 REG_WR(bp, BNX2_RV2P_CONFIG, val);
4908 /* Configure page size. */
4909 val = REG_RD(bp, BNX2_TBDR_CONFIG);
4910 val &= ~BNX2_TBDR_CONFIG_PAGE_SIZE;
4911 val |= (BCM_PAGE_BITS - 8) << 24 | 0x40;
4912 REG_WR(bp, BNX2_TBDR_CONFIG, val);
4914 val = bp->mac_addr[0] +
4915 (bp->mac_addr[1] << 8) +
4916 (bp->mac_addr[2] << 16) +
4918 (bp->mac_addr[4] << 8) +
4919 (bp->mac_addr[5] << 16);
4920 REG_WR(bp, BNX2_EMAC_BACKOFF_SEED, val);
4922 /* Program the MTU. Also include 4 bytes for CRC32. */
4924 val = mtu + ETH_HLEN + ETH_FCS_LEN;
4925 if (val > (MAX_ETHERNET_PACKET_SIZE + 4))
4926 val |= BNX2_EMAC_RX_MTU_SIZE_JUMBO_ENA;
4927 REG_WR(bp, BNX2_EMAC_RX_MTU_SIZE, val);
4932 bnx2_reg_wr_ind(bp, BNX2_RBUF_CONFIG, BNX2_RBUF_CONFIG_VAL(mtu));
4933 bnx2_reg_wr_ind(bp, BNX2_RBUF_CONFIG2, BNX2_RBUF_CONFIG2_VAL(mtu));
4934 bnx2_reg_wr_ind(bp, BNX2_RBUF_CONFIG3, BNX2_RBUF_CONFIG3_VAL(mtu));
4936 memset(bp->bnx2_napi[0].status_blk.msi, 0, bp->status_stats_size);
4937 for (i = 0; i < BNX2_MAX_MSIX_VEC; i++)
4938 bp->bnx2_napi[i].last_status_idx = 0;
4940 bp->idle_chk_status_idx = 0xffff;
4942 bp->rx_mode = BNX2_EMAC_RX_MODE_SORT_MODE;
4944 /* Set up how to generate a link change interrupt. */
4945 REG_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);
4947 REG_WR(bp, BNX2_HC_STATUS_ADDR_L,
4948 (u64) bp->status_blk_mapping & 0xffffffff);
4949 REG_WR(bp, BNX2_HC_STATUS_ADDR_H, (u64) bp->status_blk_mapping >> 32);
4951 REG_WR(bp, BNX2_HC_STATISTICS_ADDR_L,
4952 (u64) bp->stats_blk_mapping & 0xffffffff);
4953 REG_WR(bp, BNX2_HC_STATISTICS_ADDR_H,
4954 (u64) bp->stats_blk_mapping >> 32);
4956 REG_WR(bp, BNX2_HC_TX_QUICK_CONS_TRIP,
4957 (bp->tx_quick_cons_trip_int << 16) | bp->tx_quick_cons_trip);
4959 REG_WR(bp, BNX2_HC_RX_QUICK_CONS_TRIP,
4960 (bp->rx_quick_cons_trip_int << 16) | bp->rx_quick_cons_trip);
4962 REG_WR(bp, BNX2_HC_COMP_PROD_TRIP,
4963 (bp->comp_prod_trip_int << 16) | bp->comp_prod_trip);
4965 REG_WR(bp, BNX2_HC_TX_TICKS, (bp->tx_ticks_int << 16) | bp->tx_ticks);
4967 REG_WR(bp, BNX2_HC_RX_TICKS, (bp->rx_ticks_int << 16) | bp->rx_ticks);
4969 REG_WR(bp, BNX2_HC_COM_TICKS,
4970 (bp->com_ticks_int << 16) | bp->com_ticks);
4972 REG_WR(bp, BNX2_HC_CMD_TICKS,
4973 (bp->cmd_ticks_int << 16) | bp->cmd_ticks);
4975 if (bp->flags & BNX2_FLAG_BROKEN_STATS)
4976 REG_WR(bp, BNX2_HC_STATS_TICKS, 0);
4978 REG_WR(bp, BNX2_HC_STATS_TICKS, bp->stats_ticks);
4979 REG_WR(bp, BNX2_HC_STAT_COLLECT_TICKS, 0xbb8); /* 3ms */
4981 if (CHIP_ID(bp) == CHIP_ID_5706_A1)
4982 val = BNX2_HC_CONFIG_COLLECT_STATS;
4984 val = BNX2_HC_CONFIG_RX_TMR_MODE | BNX2_HC_CONFIG_TX_TMR_MODE |
4985 BNX2_HC_CONFIG_COLLECT_STATS;
4988 if (bp->flags & BNX2_FLAG_USING_MSIX) {
4989 REG_WR(bp, BNX2_HC_MSIX_BIT_VECTOR,
4990 BNX2_HC_MSIX_BIT_VECTOR_VAL);
4992 val |= BNX2_HC_CONFIG_SB_ADDR_INC_128B;
4995 if (bp->flags & BNX2_FLAG_ONE_SHOT_MSI)
4996 val |= BNX2_HC_CONFIG_ONE_SHOT | BNX2_HC_CONFIG_USE_INT_PARAM;
4998 REG_WR(bp, BNX2_HC_CONFIG, val);
5000 if (bp->rx_ticks < 25)
5001 bnx2_reg_wr_ind(bp, BNX2_FW_RX_LOW_LATENCY, 1);
5003 bnx2_reg_wr_ind(bp, BNX2_FW_RX_LOW_LATENCY, 0);
5005 for (i = 1; i < bp->irq_nvecs; i++) {
5006 u32 base = ((i - 1) * BNX2_HC_SB_CONFIG_SIZE) +
5007 BNX2_HC_SB_CONFIG_1;
5010 BNX2_HC_SB_CONFIG_1_TX_TMR_MODE |
5011 BNX2_HC_SB_CONFIG_1_RX_TMR_MODE |
5012 BNX2_HC_SB_CONFIG_1_ONE_SHOT);
5014 REG_WR(bp, base + BNX2_HC_TX_QUICK_CONS_TRIP_OFF,
5015 (bp->tx_quick_cons_trip_int << 16) |
5016 bp->tx_quick_cons_trip);
5018 REG_WR(bp, base + BNX2_HC_TX_TICKS_OFF,
5019 (bp->tx_ticks_int << 16) | bp->tx_ticks);
5021 REG_WR(bp, base + BNX2_HC_RX_QUICK_CONS_TRIP_OFF,
5022 (bp->rx_quick_cons_trip_int << 16) |
5023 bp->rx_quick_cons_trip);
5025 REG_WR(bp, base + BNX2_HC_RX_TICKS_OFF,
5026 (bp->rx_ticks_int << 16) | bp->rx_ticks);
5029 /* Clear internal stats counters. */
5030 REG_WR(bp, BNX2_HC_COMMAND, BNX2_HC_COMMAND_CLR_STAT_NOW);
5032 REG_WR(bp, BNX2_HC_ATTN_BITS_ENABLE, STATUS_ATTN_EVENTS);
5034 /* Initialize the receive filter. */
5035 bnx2_set_rx_mode(bp->dev);
5037 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
5038 val = REG_RD(bp, BNX2_MISC_NEW_CORE_CTL);
5039 val |= BNX2_MISC_NEW_CORE_CTL_DMA_ENABLE;
5040 REG_WR(bp, BNX2_MISC_NEW_CORE_CTL, val);
5042 rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT2 | BNX2_DRV_MSG_CODE_RESET,
5045 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS, BNX2_MISC_ENABLE_DEFAULT);
5046 REG_RD(bp, BNX2_MISC_ENABLE_SET_BITS);
5050 bp->hc_cmd = REG_RD(bp, BNX2_HC_COMMAND);
5056 bnx2_clear_ring_states(struct bnx2 *bp)
5058 struct bnx2_napi *bnapi;
5059 struct bnx2_tx_ring_info *txr;
5060 struct bnx2_rx_ring_info *rxr;
5063 for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) {
5064 bnapi = &bp->bnx2_napi[i];
5065 txr = &bnapi->tx_ring;
5066 rxr = &bnapi->rx_ring;
5069 txr->hw_tx_cons = 0;
5070 rxr->rx_prod_bseq = 0;
5073 rxr->rx_pg_prod = 0;
5074 rxr->rx_pg_cons = 0;
5079 bnx2_init_tx_context(struct bnx2 *bp, u32 cid, struct bnx2_tx_ring_info *txr)
5081 u32 val, offset0, offset1, offset2, offset3;
5082 u32 cid_addr = GET_CID_ADDR(cid);
5084 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
5085 offset0 = BNX2_L2CTX_TYPE_XI;
5086 offset1 = BNX2_L2CTX_CMD_TYPE_XI;
5087 offset2 = BNX2_L2CTX_TBDR_BHADDR_HI_XI;
5088 offset3 = BNX2_L2CTX_TBDR_BHADDR_LO_XI;
5090 offset0 = BNX2_L2CTX_TYPE;
5091 offset1 = BNX2_L2CTX_CMD_TYPE;
5092 offset2 = BNX2_L2CTX_TBDR_BHADDR_HI;
5093 offset3 = BNX2_L2CTX_TBDR_BHADDR_LO;
5095 val = BNX2_L2CTX_TYPE_TYPE_L2 | BNX2_L2CTX_TYPE_SIZE_L2;
5096 bnx2_ctx_wr(bp, cid_addr, offset0, val);
5098 val = BNX2_L2CTX_CMD_TYPE_TYPE_L2 | (8 << 16);
5099 bnx2_ctx_wr(bp, cid_addr, offset1, val);
5101 val = (u64) txr->tx_desc_mapping >> 32;
5102 bnx2_ctx_wr(bp, cid_addr, offset2, val);
5104 val = (u64) txr->tx_desc_mapping & 0xffffffff;
5105 bnx2_ctx_wr(bp, cid_addr, offset3, val);
5109 bnx2_init_tx_ring(struct bnx2 *bp, int ring_num)
5113 struct bnx2_napi *bnapi;
5114 struct bnx2_tx_ring_info *txr;
5116 bnapi = &bp->bnx2_napi[ring_num];
5117 txr = &bnapi->tx_ring;
5122 cid = TX_TSS_CID + ring_num - 1;
5124 bp->tx_wake_thresh = bp->tx_ring_size / 2;
5126 txbd = &txr->tx_desc_ring[MAX_TX_DESC_CNT];
5128 txbd->tx_bd_haddr_hi = (u64) txr->tx_desc_mapping >> 32;
5129 txbd->tx_bd_haddr_lo = (u64) txr->tx_desc_mapping & 0xffffffff;
5132 txr->tx_prod_bseq = 0;
5134 txr->tx_bidx_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_TX_HOST_BIDX;
5135 txr->tx_bseq_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_TX_HOST_BSEQ;
5137 bnx2_init_tx_context(bp, cid, txr);
5141 bnx2_init_rxbd_rings(struct rx_bd *rx_ring[], dma_addr_t dma[], u32 buf_size,
5147 for (i = 0; i < num_rings; i++) {
5150 rxbd = &rx_ring[i][0];
5151 for (j = 0; j < MAX_RX_DESC_CNT; j++, rxbd++) {
5152 rxbd->rx_bd_len = buf_size;
5153 rxbd->rx_bd_flags = RX_BD_FLAGS_START | RX_BD_FLAGS_END;
5155 if (i == (num_rings - 1))
5159 rxbd->rx_bd_haddr_hi = (u64) dma[j] >> 32;
5160 rxbd->rx_bd_haddr_lo = (u64) dma[j] & 0xffffffff;
5165 bnx2_init_rx_ring(struct bnx2 *bp, int ring_num)
5168 u16 prod, ring_prod;
5169 u32 cid, rx_cid_addr, val;
5170 struct bnx2_napi *bnapi = &bp->bnx2_napi[ring_num];
5171 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
5176 cid = RX_RSS_CID + ring_num - 1;
5178 rx_cid_addr = GET_CID_ADDR(cid);
5180 bnx2_init_rxbd_rings(rxr->rx_desc_ring, rxr->rx_desc_mapping,
5181 bp->rx_buf_use_size, bp->rx_max_ring);
5183 bnx2_init_rx_context(bp, cid);
5185 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
5186 val = REG_RD(bp, BNX2_MQ_MAP_L2_5);
5187 REG_WR(bp, BNX2_MQ_MAP_L2_5, val | BNX2_MQ_MAP_L2_5_ARM);
5190 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_PG_BUF_SIZE, 0);
5191 if (bp->rx_pg_ring_size) {
5192 bnx2_init_rxbd_rings(rxr->rx_pg_desc_ring,
5193 rxr->rx_pg_desc_mapping,
5194 PAGE_SIZE, bp->rx_max_pg_ring);
5195 val = (bp->rx_buf_use_size << 16) | PAGE_SIZE;
5196 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_PG_BUF_SIZE, val);
5197 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_RBDC_KEY,
5198 BNX2_L2CTX_RBDC_JUMBO_KEY - ring_num);
5200 val = (u64) rxr->rx_pg_desc_mapping[0] >> 32;
5201 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_PG_BDHADDR_HI, val);
5203 val = (u64) rxr->rx_pg_desc_mapping[0] & 0xffffffff;
5204 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_PG_BDHADDR_LO, val);
5206 if (CHIP_NUM(bp) == CHIP_NUM_5709)
5207 REG_WR(bp, BNX2_MQ_MAP_L2_3, BNX2_MQ_MAP_L2_3_DEFAULT);
5210 val = (u64) rxr->rx_desc_mapping[0] >> 32;
5211 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_BDHADDR_HI, val);
5213 val = (u64) rxr->rx_desc_mapping[0] & 0xffffffff;
5214 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_BDHADDR_LO, val);
5216 ring_prod = prod = rxr->rx_pg_prod;
5217 for (i = 0; i < bp->rx_pg_ring_size; i++) {
5218 if (bnx2_alloc_rx_page(bp, rxr, ring_prod, GFP_KERNEL) < 0) {
5219 netdev_warn(bp->dev, "init'ed rx page ring %d with %d/%d pages only\n",
5220 ring_num, i, bp->rx_pg_ring_size);
5223 prod = NEXT_RX_BD(prod);
5224 ring_prod = RX_PG_RING_IDX(prod);
5226 rxr->rx_pg_prod = prod;
5228 ring_prod = prod = rxr->rx_prod;
5229 for (i = 0; i < bp->rx_ring_size; i++) {
5230 if (bnx2_alloc_rx_data(bp, rxr, ring_prod, GFP_KERNEL) < 0) {
5231 netdev_warn(bp->dev, "init'ed rx ring %d with %d/%d skbs only\n",
5232 ring_num, i, bp->rx_ring_size);
5235 prod = NEXT_RX_BD(prod);
5236 ring_prod = RX_RING_IDX(prod);
5238 rxr->rx_prod = prod;
5240 rxr->rx_bidx_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_HOST_BDIDX;
5241 rxr->rx_bseq_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_HOST_BSEQ;
5242 rxr->rx_pg_bidx_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_HOST_PG_BDIDX;
5244 REG_WR16(bp, rxr->rx_pg_bidx_addr, rxr->rx_pg_prod);
5245 REG_WR16(bp, rxr->rx_bidx_addr, prod);
5247 REG_WR(bp, rxr->rx_bseq_addr, rxr->rx_prod_bseq);
5251 bnx2_init_all_rings(struct bnx2 *bp)
5256 bnx2_clear_ring_states(bp);
5258 REG_WR(bp, BNX2_TSCH_TSS_CFG, 0);
5259 for (i = 0; i < bp->num_tx_rings; i++)
5260 bnx2_init_tx_ring(bp, i);
5262 if (bp->num_tx_rings > 1)
5263 REG_WR(bp, BNX2_TSCH_TSS_CFG, ((bp->num_tx_rings - 1) << 24) |
5266 REG_WR(bp, BNX2_RLUP_RSS_CONFIG, 0);
5267 bnx2_reg_wr_ind(bp, BNX2_RXP_SCRATCH_RSS_TBL_SZ, 0);
5269 for (i = 0; i < bp->num_rx_rings; i++)
5270 bnx2_init_rx_ring(bp, i);
5272 if (bp->num_rx_rings > 1) {
5275 for (i = 0; i < BNX2_RXP_SCRATCH_RSS_TBL_MAX_ENTRIES; i++) {
5276 int shift = (i % 8) << 2;
5278 tbl_32 |= (i % (bp->num_rx_rings - 1)) << shift;
5280 REG_WR(bp, BNX2_RLUP_RSS_DATA, tbl_32);
5281 REG_WR(bp, BNX2_RLUP_RSS_COMMAND, (i >> 3) |
5282 BNX2_RLUP_RSS_COMMAND_RSS_WRITE_MASK |
5283 BNX2_RLUP_RSS_COMMAND_WRITE |
5284 BNX2_RLUP_RSS_COMMAND_HASH_MASK);
5289 val = BNX2_RLUP_RSS_CONFIG_IPV4_RSS_TYPE_ALL_XI |
5290 BNX2_RLUP_RSS_CONFIG_IPV6_RSS_TYPE_ALL_XI;
5292 REG_WR(bp, BNX2_RLUP_RSS_CONFIG, val);
5297 static u32 bnx2_find_max_ring(u32 ring_size, u32 max_size)
5299 u32 max, num_rings = 1;
5301 while (ring_size > MAX_RX_DESC_CNT) {
5302 ring_size -= MAX_RX_DESC_CNT;
5305 /* round to next power of 2 */
5307 while ((max & num_rings) == 0)
5310 if (num_rings != max)
5317 bnx2_set_rx_ring_size(struct bnx2 *bp, u32 size)
5319 u32 rx_size, rx_space, jumbo_size;
5321 /* 8 for CRC and VLAN */
5322 rx_size = bp->dev->mtu + ETH_HLEN + BNX2_RX_OFFSET + 8;
5324 rx_space = SKB_DATA_ALIGN(rx_size + BNX2_RX_ALIGN) + NET_SKB_PAD +
5325 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
5327 bp->rx_copy_thresh = BNX2_RX_COPY_THRESH;
5328 bp->rx_pg_ring_size = 0;
5329 bp->rx_max_pg_ring = 0;
5330 bp->rx_max_pg_ring_idx = 0;
5331 if ((rx_space > PAGE_SIZE) && !(bp->flags & BNX2_FLAG_JUMBO_BROKEN)) {
5332 int pages = PAGE_ALIGN(bp->dev->mtu - 40) >> PAGE_SHIFT;
5334 jumbo_size = size * pages;
5335 if (jumbo_size > MAX_TOTAL_RX_PG_DESC_CNT)
5336 jumbo_size = MAX_TOTAL_RX_PG_DESC_CNT;
5338 bp->rx_pg_ring_size = jumbo_size;
5339 bp->rx_max_pg_ring = bnx2_find_max_ring(jumbo_size,
5341 bp->rx_max_pg_ring_idx = (bp->rx_max_pg_ring * RX_DESC_CNT) - 1;
5342 rx_size = BNX2_RX_COPY_THRESH + BNX2_RX_OFFSET;
5343 bp->rx_copy_thresh = 0;
5346 bp->rx_buf_use_size = rx_size;
5347 /* hw alignment + build_skb() overhead*/
5348 bp->rx_buf_size = SKB_DATA_ALIGN(bp->rx_buf_use_size + BNX2_RX_ALIGN) +
5349 NET_SKB_PAD + SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
5350 bp->rx_jumbo_thresh = rx_size - BNX2_RX_OFFSET;
5351 bp->rx_ring_size = size;
5352 bp->rx_max_ring = bnx2_find_max_ring(size, MAX_RX_RINGS);
5353 bp->rx_max_ring_idx = (bp->rx_max_ring * RX_DESC_CNT) - 1;
5357 bnx2_free_tx_skbs(struct bnx2 *bp)
5361 for (i = 0; i < bp->num_tx_rings; i++) {
5362 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
5363 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
5366 if (txr->tx_buf_ring == NULL)
5369 for (j = 0; j < TX_DESC_CNT; ) {
5370 struct sw_tx_bd *tx_buf = &txr->tx_buf_ring[j];
5371 struct sk_buff *skb = tx_buf->skb;
5379 dma_unmap_single(&bp->pdev->dev,
5380 dma_unmap_addr(tx_buf, mapping),
5386 last = tx_buf->nr_frags;
5388 for (k = 0; k < last; k++, j++) {
5389 tx_buf = &txr->tx_buf_ring[TX_RING_IDX(j)];
5390 dma_unmap_page(&bp->pdev->dev,
5391 dma_unmap_addr(tx_buf, mapping),
5392 skb_frag_size(&skb_shinfo(skb)->frags[k]),
5397 netdev_tx_reset_queue(netdev_get_tx_queue(bp->dev, i));
5402 bnx2_free_rx_skbs(struct bnx2 *bp)
5406 for (i = 0; i < bp->num_rx_rings; i++) {
5407 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
5408 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
5411 if (rxr->rx_buf_ring == NULL)
5414 for (j = 0; j < bp->rx_max_ring_idx; j++) {
5415 struct sw_bd *rx_buf = &rxr->rx_buf_ring[j];
5416 u8 *data = rx_buf->data;
5421 dma_unmap_single(&bp->pdev->dev,
5422 dma_unmap_addr(rx_buf, mapping),
5423 bp->rx_buf_use_size,
5424 PCI_DMA_FROMDEVICE);
5426 rx_buf->data = NULL;
5430 for (j = 0; j < bp->rx_max_pg_ring_idx; j++)
5431 bnx2_free_rx_page(bp, rxr, j);
5436 bnx2_free_skbs(struct bnx2 *bp)
5438 bnx2_free_tx_skbs(bp);
5439 bnx2_free_rx_skbs(bp);
5443 bnx2_reset_nic(struct bnx2 *bp, u32 reset_code)
5447 rc = bnx2_reset_chip(bp, reset_code);
5452 if ((rc = bnx2_init_chip(bp)) != 0)
5455 bnx2_init_all_rings(bp);
5460 bnx2_init_nic(struct bnx2 *bp, int reset_phy)
5464 if ((rc = bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET)) != 0)
5467 spin_lock_bh(&bp->phy_lock);
5468 bnx2_init_phy(bp, reset_phy);
5470 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
5471 bnx2_remote_phy_event(bp);
5472 spin_unlock_bh(&bp->phy_lock);
5477 bnx2_shutdown_chip(struct bnx2 *bp)
5481 if (bp->flags & BNX2_FLAG_NO_WOL)
5482 reset_code = BNX2_DRV_MSG_CODE_UNLOAD_LNK_DN;
5484 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
5486 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
5488 return bnx2_reset_chip(bp, reset_code);
5492 bnx2_test_registers(struct bnx2 *bp)
5496 static const struct {
5499 #define BNX2_FL_NOT_5709 1
5503 { 0x006c, 0, 0x00000000, 0x0000003f },
5504 { 0x0090, 0, 0xffffffff, 0x00000000 },
5505 { 0x0094, 0, 0x00000000, 0x00000000 },
5507 { 0x0404, BNX2_FL_NOT_5709, 0x00003f00, 0x00000000 },
5508 { 0x0418, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5509 { 0x041c, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5510 { 0x0420, BNX2_FL_NOT_5709, 0x00000000, 0x80ffffff },
5511 { 0x0424, BNX2_FL_NOT_5709, 0x00000000, 0x00000000 },
5512 { 0x0428, BNX2_FL_NOT_5709, 0x00000000, 0x00000001 },
5513 { 0x0450, BNX2_FL_NOT_5709, 0x00000000, 0x0000ffff },
5514 { 0x0454, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5515 { 0x0458, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5517 { 0x0808, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5518 { 0x0854, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5519 { 0x0868, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
5520 { 0x086c, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
5521 { 0x0870, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
5522 { 0x0874, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
5524 { 0x0c00, BNX2_FL_NOT_5709, 0x00000000, 0x00000001 },
5525 { 0x0c04, BNX2_FL_NOT_5709, 0x00000000, 0x03ff0001 },
5526 { 0x0c08, BNX2_FL_NOT_5709, 0x0f0ff073, 0x00000000 },
5528 { 0x1000, 0, 0x00000000, 0x00000001 },
5529 { 0x1004, BNX2_FL_NOT_5709, 0x00000000, 0x000f0001 },
5531 { 0x1408, 0, 0x01c00800, 0x00000000 },
5532 { 0x149c, 0, 0x8000ffff, 0x00000000 },
5533 { 0x14a8, 0, 0x00000000, 0x000001ff },
5534 { 0x14ac, 0, 0x0fffffff, 0x10000000 },
5535 { 0x14b0, 0, 0x00000002, 0x00000001 },
5536 { 0x14b8, 0, 0x00000000, 0x00000000 },
5537 { 0x14c0, 0, 0x00000000, 0x00000009 },
5538 { 0x14c4, 0, 0x00003fff, 0x00000000 },
5539 { 0x14cc, 0, 0x00000000, 0x00000001 },
5540 { 0x14d0, 0, 0xffffffff, 0x00000000 },
5542 { 0x1800, 0, 0x00000000, 0x00000001 },
5543 { 0x1804, 0, 0x00000000, 0x00000003 },
5545 { 0x2800, 0, 0x00000000, 0x00000001 },
5546 { 0x2804, 0, 0x00000000, 0x00003f01 },
5547 { 0x2808, 0, 0x0f3f3f03, 0x00000000 },
5548 { 0x2810, 0, 0xffff0000, 0x00000000 },
5549 { 0x2814, 0, 0xffff0000, 0x00000000 },
5550 { 0x2818, 0, 0xffff0000, 0x00000000 },
5551 { 0x281c, 0, 0xffff0000, 0x00000000 },
5552 { 0x2834, 0, 0xffffffff, 0x00000000 },
5553 { 0x2840, 0, 0x00000000, 0xffffffff },
5554 { 0x2844, 0, 0x00000000, 0xffffffff },
5555 { 0x2848, 0, 0xffffffff, 0x00000000 },
5556 { 0x284c, 0, 0xf800f800, 0x07ff07ff },
5558 { 0x2c00, 0, 0x00000000, 0x00000011 },
5559 { 0x2c04, 0, 0x00000000, 0x00030007 },
5561 { 0x3c00, 0, 0x00000000, 0x00000001 },
5562 { 0x3c04, 0, 0x00000000, 0x00070000 },
5563 { 0x3c08, 0, 0x00007f71, 0x07f00000 },
5564 { 0x3c0c, 0, 0x1f3ffffc, 0x00000000 },
5565 { 0x3c10, 0, 0xffffffff, 0x00000000 },
5566 { 0x3c14, 0, 0x00000000, 0xffffffff },
5567 { 0x3c18, 0, 0x00000000, 0xffffffff },
5568 { 0x3c1c, 0, 0xfffff000, 0x00000000 },
5569 { 0x3c20, 0, 0xffffff00, 0x00000000 },
5571 { 0x5004, 0, 0x00000000, 0x0000007f },
5572 { 0x5008, 0, 0x0f0007ff, 0x00000000 },
5574 { 0x5c00, 0, 0x00000000, 0x00000001 },
5575 { 0x5c04, 0, 0x00000000, 0x0003000f },
5576 { 0x5c08, 0, 0x00000003, 0x00000000 },
5577 { 0x5c0c, 0, 0x0000fff8, 0x00000000 },
5578 { 0x5c10, 0, 0x00000000, 0xffffffff },
5579 { 0x5c80, 0, 0x00000000, 0x0f7113f1 },
5580 { 0x5c84, 0, 0x00000000, 0x0000f333 },
5581 { 0x5c88, 0, 0x00000000, 0x00077373 },
5582 { 0x5c8c, 0, 0x00000000, 0x0007f737 },
5584 { 0x6808, 0, 0x0000ff7f, 0x00000000 },
5585 { 0x680c, 0, 0xffffffff, 0x00000000 },
5586 { 0x6810, 0, 0xffffffff, 0x00000000 },
5587 { 0x6814, 0, 0xffffffff, 0x00000000 },
5588 { 0x6818, 0, 0xffffffff, 0x00000000 },
5589 { 0x681c, 0, 0xffffffff, 0x00000000 },
5590 { 0x6820, 0, 0x00ff00ff, 0x00000000 },
5591 { 0x6824, 0, 0x00ff00ff, 0x00000000 },
5592 { 0x6828, 0, 0x00ff00ff, 0x00000000 },
5593 { 0x682c, 0, 0x03ff03ff, 0x00000000 },
5594 { 0x6830, 0, 0x03ff03ff, 0x00000000 },
5595 { 0x6834, 0, 0x03ff03ff, 0x00000000 },
5596 { 0x6838, 0, 0x03ff03ff, 0x00000000 },
5597 { 0x683c, 0, 0x0000ffff, 0x00000000 },
5598 { 0x6840, 0, 0x00000ff0, 0x00000000 },
5599 { 0x6844, 0, 0x00ffff00, 0x00000000 },
5600 { 0x684c, 0, 0xffffffff, 0x00000000 },
5601 { 0x6850, 0, 0x7f7f7f7f, 0x00000000 },
5602 { 0x6854, 0, 0x7f7f7f7f, 0x00000000 },
5603 { 0x6858, 0, 0x7f7f7f7f, 0x00000000 },
5604 { 0x685c, 0, 0x7f7f7f7f, 0x00000000 },
5605 { 0x6908, 0, 0x00000000, 0x0001ff0f },
5606 { 0x690c, 0, 0x00000000, 0x0ffe00f0 },
5608 { 0xffff, 0, 0x00000000, 0x00000000 },
5613 if (CHIP_NUM(bp) == CHIP_NUM_5709)
5616 for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
5617 u32 offset, rw_mask, ro_mask, save_val, val;
5618 u16 flags = reg_tbl[i].flags;
5620 if (is_5709 && (flags & BNX2_FL_NOT_5709))
5623 offset = (u32) reg_tbl[i].offset;
5624 rw_mask = reg_tbl[i].rw_mask;
5625 ro_mask = reg_tbl[i].ro_mask;
5627 save_val = readl(bp->regview + offset);
5629 writel(0, bp->regview + offset);
5631 val = readl(bp->regview + offset);
5632 if ((val & rw_mask) != 0) {
5636 if ((val & ro_mask) != (save_val & ro_mask)) {
5640 writel(0xffffffff, bp->regview + offset);
5642 val = readl(bp->regview + offset);
5643 if ((val & rw_mask) != rw_mask) {
5647 if ((val & ro_mask) != (save_val & ro_mask)) {
5651 writel(save_val, bp->regview + offset);
5655 writel(save_val, bp->regview + offset);
5663 bnx2_do_mem_test(struct bnx2 *bp, u32 start, u32 size)
5665 static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0x55555555,
5666 0xaaaaaaaa , 0xaa55aa55, 0x55aa55aa };
5669 for (i = 0; i < sizeof(test_pattern) / 4; i++) {
5672 for (offset = 0; offset < size; offset += 4) {
5674 bnx2_reg_wr_ind(bp, start + offset, test_pattern[i]);
5676 if (bnx2_reg_rd_ind(bp, start + offset) !=
5686 bnx2_test_memory(struct bnx2 *bp)
5690 static struct mem_entry {
5693 } mem_tbl_5706[] = {
5694 { 0x60000, 0x4000 },
5695 { 0xa0000, 0x3000 },
5696 { 0xe0000, 0x4000 },
5697 { 0x120000, 0x4000 },
5698 { 0x1a0000, 0x4000 },
5699 { 0x160000, 0x4000 },
5703 { 0x60000, 0x4000 },
5704 { 0xa0000, 0x3000 },
5705 { 0xe0000, 0x4000 },
5706 { 0x120000, 0x4000 },
5707 { 0x1a0000, 0x4000 },
5710 struct mem_entry *mem_tbl;
5712 if (CHIP_NUM(bp) == CHIP_NUM_5709)
5713 mem_tbl = mem_tbl_5709;
5715 mem_tbl = mem_tbl_5706;
5717 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
5718 if ((ret = bnx2_do_mem_test(bp, mem_tbl[i].offset,
5719 mem_tbl[i].len)) != 0) {
5727 #define BNX2_MAC_LOOPBACK 0
5728 #define BNX2_PHY_LOOPBACK 1
5731 bnx2_run_loopback(struct bnx2 *bp, int loopback_mode)
5733 unsigned int pkt_size, num_pkts, i;
5734 struct sk_buff *skb;
5736 unsigned char *packet;
5737 u16 rx_start_idx, rx_idx;
5740 struct sw_bd *rx_buf;
5741 struct l2_fhdr *rx_hdr;
5743 struct bnx2_napi *bnapi = &bp->bnx2_napi[0], *tx_napi;
5744 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
5745 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
5749 txr = &tx_napi->tx_ring;
5750 rxr = &bnapi->rx_ring;
5751 if (loopback_mode == BNX2_MAC_LOOPBACK) {
5752 bp->loopback = MAC_LOOPBACK;
5753 bnx2_set_mac_loopback(bp);
5755 else if (loopback_mode == BNX2_PHY_LOOPBACK) {
5756 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
5759 bp->loopback = PHY_LOOPBACK;
5760 bnx2_set_phy_loopback(bp);
5765 pkt_size = min(bp->dev->mtu + ETH_HLEN, bp->rx_jumbo_thresh - 4);
5766 skb = netdev_alloc_skb(bp->dev, pkt_size);
5769 packet = skb_put(skb, pkt_size);
5770 memcpy(packet, bp->dev->dev_addr, 6);
5771 memset(packet + 6, 0x0, 8);
5772 for (i = 14; i < pkt_size; i++)
5773 packet[i] = (unsigned char) (i & 0xff);
5775 map = dma_map_single(&bp->pdev->dev, skb->data, pkt_size,
5777 if (dma_mapping_error(&bp->pdev->dev, map)) {
5782 REG_WR(bp, BNX2_HC_COMMAND,
5783 bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
5785 REG_RD(bp, BNX2_HC_COMMAND);
5788 rx_start_idx = bnx2_get_hw_rx_cons(bnapi);
5792 txbd = &txr->tx_desc_ring[TX_RING_IDX(txr->tx_prod)];
5794 txbd->tx_bd_haddr_hi = (u64) map >> 32;
5795 txbd->tx_bd_haddr_lo = (u64) map & 0xffffffff;
5796 txbd->tx_bd_mss_nbytes = pkt_size;
5797 txbd->tx_bd_vlan_tag_flags = TX_BD_FLAGS_START | TX_BD_FLAGS_END;
5800 txr->tx_prod = NEXT_TX_BD(txr->tx_prod);
5801 txr->tx_prod_bseq += pkt_size;
5803 REG_WR16(bp, txr->tx_bidx_addr, txr->tx_prod);
5804 REG_WR(bp, txr->tx_bseq_addr, txr->tx_prod_bseq);
5808 REG_WR(bp, BNX2_HC_COMMAND,
5809 bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
5811 REG_RD(bp, BNX2_HC_COMMAND);
5815 dma_unmap_single(&bp->pdev->dev, map, pkt_size, PCI_DMA_TODEVICE);
5818 if (bnx2_get_hw_tx_cons(tx_napi) != txr->tx_prod)
5819 goto loopback_test_done;
5821 rx_idx = bnx2_get_hw_rx_cons(bnapi);
5822 if (rx_idx != rx_start_idx + num_pkts) {
5823 goto loopback_test_done;
5826 rx_buf = &rxr->rx_buf_ring[rx_start_idx];
5827 data = rx_buf->data;
5829 rx_hdr = get_l2_fhdr(data);
5830 data = (u8 *)rx_hdr + BNX2_RX_OFFSET;
5832 dma_sync_single_for_cpu(&bp->pdev->dev,
5833 dma_unmap_addr(rx_buf, mapping),
5834 bp->rx_buf_use_size, PCI_DMA_FROMDEVICE);
5836 if (rx_hdr->l2_fhdr_status &
5837 (L2_FHDR_ERRORS_BAD_CRC |
5838 L2_FHDR_ERRORS_PHY_DECODE |
5839 L2_FHDR_ERRORS_ALIGNMENT |
5840 L2_FHDR_ERRORS_TOO_SHORT |
5841 L2_FHDR_ERRORS_GIANT_FRAME)) {
5843 goto loopback_test_done;
5846 if ((rx_hdr->l2_fhdr_pkt_len - 4) != pkt_size) {
5847 goto loopback_test_done;
5850 for (i = 14; i < pkt_size; i++) {
5851 if (*(data + i) != (unsigned char) (i & 0xff)) {
5852 goto loopback_test_done;
5863 #define BNX2_MAC_LOOPBACK_FAILED 1
5864 #define BNX2_PHY_LOOPBACK_FAILED 2
5865 #define BNX2_LOOPBACK_FAILED (BNX2_MAC_LOOPBACK_FAILED | \
5866 BNX2_PHY_LOOPBACK_FAILED)
5869 bnx2_test_loopback(struct bnx2 *bp)
5873 if (!netif_running(bp->dev))
5874 return BNX2_LOOPBACK_FAILED;
5876 bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET);
5877 spin_lock_bh(&bp->phy_lock);
5878 bnx2_init_phy(bp, 1);
5879 spin_unlock_bh(&bp->phy_lock);
5880 if (bnx2_run_loopback(bp, BNX2_MAC_LOOPBACK))
5881 rc |= BNX2_MAC_LOOPBACK_FAILED;
5882 if (bnx2_run_loopback(bp, BNX2_PHY_LOOPBACK))
5883 rc |= BNX2_PHY_LOOPBACK_FAILED;
5887 #define NVRAM_SIZE 0x200
5888 #define CRC32_RESIDUAL 0xdebb20e3
5891 bnx2_test_nvram(struct bnx2 *bp)
5893 __be32 buf[NVRAM_SIZE / 4];
5894 u8 *data = (u8 *) buf;
5898 if ((rc = bnx2_nvram_read(bp, 0, data, 4)) != 0)
5899 goto test_nvram_done;
5901 magic = be32_to_cpu(buf[0]);
5902 if (magic != 0x669955aa) {
5904 goto test_nvram_done;
5907 if ((rc = bnx2_nvram_read(bp, 0x100, data, NVRAM_SIZE)) != 0)
5908 goto test_nvram_done;
5910 csum = ether_crc_le(0x100, data);
5911 if (csum != CRC32_RESIDUAL) {
5913 goto test_nvram_done;
5916 csum = ether_crc_le(0x100, data + 0x100);
5917 if (csum != CRC32_RESIDUAL) {
5926 bnx2_test_link(struct bnx2 *bp)
5930 if (!netif_running(bp->dev))
5933 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
5938 spin_lock_bh(&bp->phy_lock);
5939 bnx2_enable_bmsr1(bp);
5940 bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
5941 bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
5942 bnx2_disable_bmsr1(bp);
5943 spin_unlock_bh(&bp->phy_lock);
5945 if (bmsr & BMSR_LSTATUS) {
5952 bnx2_test_intr(struct bnx2 *bp)
5957 if (!netif_running(bp->dev))
5960 status_idx = REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff;
5962 /* This register is not touched during run-time. */
5963 REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW);
5964 REG_RD(bp, BNX2_HC_COMMAND);
5966 for (i = 0; i < 10; i++) {
5967 if ((REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff) !=
5973 msleep_interruptible(10);
5981 /* Determining link for parallel detection. */
5983 bnx2_5706_serdes_has_link(struct bnx2 *bp)
5985 u32 mode_ctl, an_dbg, exp;
5987 if (bp->phy_flags & BNX2_PHY_FLAG_NO_PARALLEL)
5990 bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_MODE_CTL);
5991 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &mode_ctl);
5993 if (!(mode_ctl & MISC_SHDW_MODE_CTL_SIG_DET))
5996 bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG);
5997 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
5998 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
6000 if (an_dbg & (MISC_SHDW_AN_DBG_NOSYNC | MISC_SHDW_AN_DBG_RUDI_INVALID))
6003 bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS, MII_EXPAND_REG1);
6004 bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &exp);
6005 bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &exp);
6007 if (exp & MII_EXPAND_REG1_RUDI_C) /* receiving CONFIG */
6014 bnx2_5706_serdes_timer(struct bnx2 *bp)
6018 spin_lock(&bp->phy_lock);
6019 if (bp->serdes_an_pending) {
6020 bp->serdes_an_pending--;
6022 } else if ((bp->link_up == 0) && (bp->autoneg & AUTONEG_SPEED)) {
6025 bp->current_interval = BNX2_TIMER_INTERVAL;
6027 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
6029 if (bmcr & BMCR_ANENABLE) {
6030 if (bnx2_5706_serdes_has_link(bp)) {
6031 bmcr &= ~BMCR_ANENABLE;
6032 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
6033 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
6034 bp->phy_flags |= BNX2_PHY_FLAG_PARALLEL_DETECT;
6038 else if ((bp->link_up) && (bp->autoneg & AUTONEG_SPEED) &&
6039 (bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT)) {
6042 bnx2_write_phy(bp, 0x17, 0x0f01);
6043 bnx2_read_phy(bp, 0x15, &phy2);
6047 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
6048 bmcr |= BMCR_ANENABLE;
6049 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
6051 bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT;
6054 bp->current_interval = BNX2_TIMER_INTERVAL;
6059 bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG);
6060 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &val);
6061 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &val);
6063 if (bp->link_up && (val & MISC_SHDW_AN_DBG_NOSYNC)) {
6064 if (!(bp->phy_flags & BNX2_PHY_FLAG_FORCED_DOWN)) {
6065 bnx2_5706s_force_link_dn(bp, 1);
6066 bp->phy_flags |= BNX2_PHY_FLAG_FORCED_DOWN;
6069 } else if (!bp->link_up && !(val & MISC_SHDW_AN_DBG_NOSYNC))
6072 spin_unlock(&bp->phy_lock);
6076 bnx2_5708_serdes_timer(struct bnx2 *bp)
6078 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
6081 if ((bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) == 0) {
6082 bp->serdes_an_pending = 0;
6086 spin_lock(&bp->phy_lock);
6087 if (bp->serdes_an_pending)
6088 bp->serdes_an_pending--;
6089 else if ((bp->link_up == 0) && (bp->autoneg & AUTONEG_SPEED)) {
6092 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
6093 if (bmcr & BMCR_ANENABLE) {
6094 bnx2_enable_forced_2g5(bp);
6095 bp->current_interval = BNX2_SERDES_FORCED_TIMEOUT;
6097 bnx2_disable_forced_2g5(bp);
6098 bp->serdes_an_pending = 2;
6099 bp->current_interval = BNX2_TIMER_INTERVAL;
6103 bp->current_interval = BNX2_TIMER_INTERVAL;
6105 spin_unlock(&bp->phy_lock);
6109 bnx2_timer(unsigned long data)
6111 struct bnx2 *bp = (struct bnx2 *) data;
6113 if (!netif_running(bp->dev))
6116 if (atomic_read(&bp->intr_sem) != 0)
6117 goto bnx2_restart_timer;
6119 if ((bp->flags & (BNX2_FLAG_USING_MSI | BNX2_FLAG_ONE_SHOT_MSI)) ==
6120 BNX2_FLAG_USING_MSI)
6121 bnx2_chk_missed_msi(bp);
6123 bnx2_send_heart_beat(bp);
6125 bp->stats_blk->stat_FwRxDrop =
6126 bnx2_reg_rd_ind(bp, BNX2_FW_RX_DROP_COUNT);
6128 /* workaround occasional corrupted counters */
6129 if ((bp->flags & BNX2_FLAG_BROKEN_STATS) && bp->stats_ticks)
6130 REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd |
6131 BNX2_HC_COMMAND_STATS_NOW);
6133 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
6134 if (CHIP_NUM(bp) == CHIP_NUM_5706)
6135 bnx2_5706_serdes_timer(bp);
6137 bnx2_5708_serdes_timer(bp);
6141 mod_timer(&bp->timer, jiffies + bp->current_interval);
6145 bnx2_request_irq(struct bnx2 *bp)
6147 unsigned long flags;
6148 struct bnx2_irq *irq;
6151 if (bp->flags & BNX2_FLAG_USING_MSI_OR_MSIX)
6154 flags = IRQF_SHARED;
6156 for (i = 0; i < bp->irq_nvecs; i++) {
6157 irq = &bp->irq_tbl[i];
6158 rc = request_irq(irq->vector, irq->handler, flags, irq->name,
6168 __bnx2_free_irq(struct bnx2 *bp)
6170 struct bnx2_irq *irq;
6173 for (i = 0; i < bp->irq_nvecs; i++) {
6174 irq = &bp->irq_tbl[i];
6176 free_irq(irq->vector, &bp->bnx2_napi[i]);
6182 bnx2_free_irq(struct bnx2 *bp)
6185 __bnx2_free_irq(bp);
6186 if (bp->flags & BNX2_FLAG_USING_MSI)
6187 pci_disable_msi(bp->pdev);
6188 else if (bp->flags & BNX2_FLAG_USING_MSIX)
6189 pci_disable_msix(bp->pdev);
6191 bp->flags &= ~(BNX2_FLAG_USING_MSI_OR_MSIX | BNX2_FLAG_ONE_SHOT_MSI);
6195 bnx2_enable_msix(struct bnx2 *bp, int msix_vecs)
6197 int i, total_vecs, rc;
6198 struct msix_entry msix_ent[BNX2_MAX_MSIX_VEC];
6199 struct net_device *dev = bp->dev;
6200 const int len = sizeof(bp->irq_tbl[0].name);
6202 bnx2_setup_msix_tbl(bp);
6203 REG_WR(bp, BNX2_PCI_MSIX_CONTROL, BNX2_MAX_MSIX_HW_VEC - 1);
6204 REG_WR(bp, BNX2_PCI_MSIX_TBL_OFF_BIR, BNX2_PCI_GRC_WINDOW2_BASE);
6205 REG_WR(bp, BNX2_PCI_MSIX_PBA_OFF_BIT, BNX2_PCI_GRC_WINDOW3_BASE);
6207 /* Need to flush the previous three writes to ensure MSI-X
6208 * is setup properly */
6209 REG_RD(bp, BNX2_PCI_MSIX_CONTROL);
6211 for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) {
6212 msix_ent[i].entry = i;
6213 msix_ent[i].vector = 0;
6216 total_vecs = msix_vecs;
6221 while (total_vecs >= BNX2_MIN_MSIX_VEC) {
6222 rc = pci_enable_msix(bp->pdev, msix_ent, total_vecs);
6232 msix_vecs = total_vecs;
6236 bp->irq_nvecs = msix_vecs;
6237 bp->flags |= BNX2_FLAG_USING_MSIX | BNX2_FLAG_ONE_SHOT_MSI;
6238 for (i = 0; i < total_vecs; i++) {
6239 bp->irq_tbl[i].vector = msix_ent[i].vector;
6240 snprintf(bp->irq_tbl[i].name, len, "%s-%d", dev->name, i);
6241 bp->irq_tbl[i].handler = bnx2_msi_1shot;
6246 bnx2_setup_int_mode(struct bnx2 *bp, int dis_msi)
6248 int cpus = num_online_cpus();
6249 int msix_vecs = min(cpus + 1, RX_MAX_RINGS);
6251 bp->irq_tbl[0].handler = bnx2_interrupt;
6252 strcpy(bp->irq_tbl[0].name, bp->dev->name);
6254 bp->irq_tbl[0].vector = bp->pdev->irq;
6256 if ((bp->flags & BNX2_FLAG_MSIX_CAP) && !dis_msi)
6257 bnx2_enable_msix(bp, msix_vecs);
6259 if ((bp->flags & BNX2_FLAG_MSI_CAP) && !dis_msi &&
6260 !(bp->flags & BNX2_FLAG_USING_MSIX)) {
6261 if (pci_enable_msi(bp->pdev) == 0) {
6262 bp->flags |= BNX2_FLAG_USING_MSI;
6263 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
6264 bp->flags |= BNX2_FLAG_ONE_SHOT_MSI;
6265 bp->irq_tbl[0].handler = bnx2_msi_1shot;
6267 bp->irq_tbl[0].handler = bnx2_msi;
6269 bp->irq_tbl[0].vector = bp->pdev->irq;
6273 bp->num_tx_rings = rounddown_pow_of_two(bp->irq_nvecs);
6274 netif_set_real_num_tx_queues(bp->dev, bp->num_tx_rings);
6276 bp->num_rx_rings = bp->irq_nvecs;
6277 return netif_set_real_num_rx_queues(bp->dev, bp->num_rx_rings);
6280 /* Called with rtnl_lock */
6282 bnx2_open(struct net_device *dev)
6284 struct bnx2 *bp = netdev_priv(dev);
6287 rc = bnx2_request_firmware(bp);
6291 netif_carrier_off(dev);
6293 bnx2_set_power_state(bp, PCI_D0);
6294 bnx2_disable_int(bp);
6296 rc = bnx2_setup_int_mode(bp, disable_msi);
6300 bnx2_napi_enable(bp);
6301 rc = bnx2_alloc_mem(bp);
6305 rc = bnx2_request_irq(bp);
6309 rc = bnx2_init_nic(bp, 1);
6313 mod_timer(&bp->timer, jiffies + bp->current_interval);
6315 atomic_set(&bp->intr_sem, 0);
6317 memset(bp->temp_stats_blk, 0, sizeof(struct statistics_block));
6319 bnx2_enable_int(bp);
6321 if (bp->flags & BNX2_FLAG_USING_MSI) {
6322 /* Test MSI to make sure it is working
6323 * If MSI test fails, go back to INTx mode
6325 if (bnx2_test_intr(bp) != 0) {
6326 netdev_warn(bp->dev, "No interrupt was generated using MSI, switching to INTx mode. Please report this failure to the PCI maintainer and include system chipset information.\n");
6328 bnx2_disable_int(bp);
6331 bnx2_setup_int_mode(bp, 1);
6333 rc = bnx2_init_nic(bp, 0);
6336 rc = bnx2_request_irq(bp);
6339 del_timer_sync(&bp->timer);
6342 bnx2_enable_int(bp);
6345 if (bp->flags & BNX2_FLAG_USING_MSI)
6346 netdev_info(dev, "using MSI\n");
6347 else if (bp->flags & BNX2_FLAG_USING_MSIX)
6348 netdev_info(dev, "using MSIX\n");
6350 netif_tx_start_all_queues(dev);
6355 bnx2_napi_disable(bp);
6360 bnx2_release_firmware(bp);
6365 bnx2_reset_task(struct work_struct *work)
6367 struct bnx2 *bp = container_of(work, struct bnx2, reset_task);
6371 if (!netif_running(bp->dev)) {
6376 bnx2_netif_stop(bp, true);
6378 rc = bnx2_init_nic(bp, 1);
6380 netdev_err(bp->dev, "failed to reset NIC, closing\n");
6381 bnx2_napi_enable(bp);
6387 atomic_set(&bp->intr_sem, 1);
6388 bnx2_netif_start(bp, true);
6393 bnx2_dump_state(struct bnx2 *bp)
6395 struct net_device *dev = bp->dev;
6398 pci_read_config_dword(bp->pdev, PCI_COMMAND, &val1);
6399 netdev_err(dev, "DEBUG: intr_sem[%x] PCI_CMD[%08x]\n",
6400 atomic_read(&bp->intr_sem), val1);
6401 pci_read_config_dword(bp->pdev, bp->pm_cap + PCI_PM_CTRL, &val1);
6402 pci_read_config_dword(bp->pdev, BNX2_PCICFG_MISC_CONFIG, &val2);
6403 netdev_err(dev, "DEBUG: PCI_PM[%08x] PCI_MISC_CFG[%08x]\n", val1, val2);
6404 netdev_err(dev, "DEBUG: EMAC_TX_STATUS[%08x] EMAC_RX_STATUS[%08x]\n",
6405 REG_RD(bp, BNX2_EMAC_TX_STATUS),
6406 REG_RD(bp, BNX2_EMAC_RX_STATUS));
6407 netdev_err(dev, "DEBUG: RPM_MGMT_PKT_CTRL[%08x]\n",
6408 REG_RD(bp, BNX2_RPM_MGMT_PKT_CTRL));
6409 netdev_err(dev, "DEBUG: HC_STATS_INTERRUPT_STATUS[%08x]\n",
6410 REG_RD(bp, BNX2_HC_STATS_INTERRUPT_STATUS));
6411 if (bp->flags & BNX2_FLAG_USING_MSIX)
6412 netdev_err(dev, "DEBUG: PBA[%08x]\n",
6413 REG_RD(bp, BNX2_PCI_GRC_WINDOW3_BASE));
6417 bnx2_tx_timeout(struct net_device *dev)
6419 struct bnx2 *bp = netdev_priv(dev);
6421 bnx2_dump_state(bp);
6422 bnx2_dump_mcp_state(bp);
6424 /* This allows the netif to be shutdown gracefully before resetting */
6425 schedule_work(&bp->reset_task);
6428 /* Called with netif_tx_lock.
6429 * bnx2_tx_int() runs without netif_tx_lock unless it needs to call
6430 * netif_wake_queue().
6433 bnx2_start_xmit(struct sk_buff *skb, struct net_device *dev)
6435 struct bnx2 *bp = netdev_priv(dev);
6438 struct sw_tx_bd *tx_buf;
6439 u32 len, vlan_tag_flags, last_frag, mss;
6440 u16 prod, ring_prod;
6442 struct bnx2_napi *bnapi;
6443 struct bnx2_tx_ring_info *txr;
6444 struct netdev_queue *txq;
6446 /* Determine which tx ring we will be placed on */
6447 i = skb_get_queue_mapping(skb);
6448 bnapi = &bp->bnx2_napi[i];
6449 txr = &bnapi->tx_ring;
6450 txq = netdev_get_tx_queue(dev, i);
6452 if (unlikely(bnx2_tx_avail(bp, txr) <
6453 (skb_shinfo(skb)->nr_frags + 1))) {
6454 netif_tx_stop_queue(txq);
6455 netdev_err(dev, "BUG! Tx ring full when queue awake!\n");
6457 return NETDEV_TX_BUSY;
6459 len = skb_headlen(skb);
6460 prod = txr->tx_prod;
6461 ring_prod = TX_RING_IDX(prod);
6464 if (skb->ip_summed == CHECKSUM_PARTIAL) {
6465 vlan_tag_flags |= TX_BD_FLAGS_TCP_UDP_CKSUM;
6468 if (vlan_tx_tag_present(skb)) {
6470 (TX_BD_FLAGS_VLAN_TAG | (vlan_tx_tag_get(skb) << 16));
6473 if ((mss = skb_shinfo(skb)->gso_size)) {
6477 vlan_tag_flags |= TX_BD_FLAGS_SW_LSO;
6479 tcp_opt_len = tcp_optlen(skb);
6481 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6) {
6482 u32 tcp_off = skb_transport_offset(skb) -
6483 sizeof(struct ipv6hdr) - ETH_HLEN;
6485 vlan_tag_flags |= ((tcp_opt_len >> 2) << 8) |
6486 TX_BD_FLAGS_SW_FLAGS;
6487 if (likely(tcp_off == 0))
6488 vlan_tag_flags &= ~TX_BD_FLAGS_TCP6_OFF0_MSK;
6491 vlan_tag_flags |= ((tcp_off & 0x3) <<
6492 TX_BD_FLAGS_TCP6_OFF0_SHL) |
6493 ((tcp_off & 0x10) <<
6494 TX_BD_FLAGS_TCP6_OFF4_SHL);
6495 mss |= (tcp_off & 0xc) << TX_BD_TCP6_OFF2_SHL;
6499 if (tcp_opt_len || (iph->ihl > 5)) {
6500 vlan_tag_flags |= ((iph->ihl - 5) +
6501 (tcp_opt_len >> 2)) << 8;
6507 mapping = dma_map_single(&bp->pdev->dev, skb->data, len, PCI_DMA_TODEVICE);
6508 if (dma_mapping_error(&bp->pdev->dev, mapping)) {
6510 return NETDEV_TX_OK;
6513 tx_buf = &txr->tx_buf_ring[ring_prod];
6515 dma_unmap_addr_set(tx_buf, mapping, mapping);
6517 txbd = &txr->tx_desc_ring[ring_prod];
6519 txbd->tx_bd_haddr_hi = (u64) mapping >> 32;
6520 txbd->tx_bd_haddr_lo = (u64) mapping & 0xffffffff;
6521 txbd->tx_bd_mss_nbytes = len | (mss << 16);
6522 txbd->tx_bd_vlan_tag_flags = vlan_tag_flags | TX_BD_FLAGS_START;
6524 last_frag = skb_shinfo(skb)->nr_frags;
6525 tx_buf->nr_frags = last_frag;
6526 tx_buf->is_gso = skb_is_gso(skb);
6528 for (i = 0; i < last_frag; i++) {
6529 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
6531 prod = NEXT_TX_BD(prod);
6532 ring_prod = TX_RING_IDX(prod);
6533 txbd = &txr->tx_desc_ring[ring_prod];
6535 len = skb_frag_size(frag);
6536 mapping = skb_frag_dma_map(&bp->pdev->dev, frag, 0, len,
6538 if (dma_mapping_error(&bp->pdev->dev, mapping))
6540 dma_unmap_addr_set(&txr->tx_buf_ring[ring_prod], mapping,
6543 txbd->tx_bd_haddr_hi = (u64) mapping >> 32;
6544 txbd->tx_bd_haddr_lo = (u64) mapping & 0xffffffff;
6545 txbd->tx_bd_mss_nbytes = len | (mss << 16);
6546 txbd->tx_bd_vlan_tag_flags = vlan_tag_flags;
6549 txbd->tx_bd_vlan_tag_flags |= TX_BD_FLAGS_END;
6551 netdev_tx_sent_queue(txq, skb->len);
6553 prod = NEXT_TX_BD(prod);
6554 txr->tx_prod_bseq += skb->len;
6556 REG_WR16(bp, txr->tx_bidx_addr, prod);
6557 REG_WR(bp, txr->tx_bseq_addr, txr->tx_prod_bseq);
6561 txr->tx_prod = prod;
6563 if (unlikely(bnx2_tx_avail(bp, txr) <= MAX_SKB_FRAGS)) {
6564 netif_tx_stop_queue(txq);
6566 /* netif_tx_stop_queue() must be done before checking
6567 * tx index in bnx2_tx_avail() below, because in
6568 * bnx2_tx_int(), we update tx index before checking for
6569 * netif_tx_queue_stopped().
6572 if (bnx2_tx_avail(bp, txr) > bp->tx_wake_thresh)
6573 netif_tx_wake_queue(txq);
6576 return NETDEV_TX_OK;
6578 /* save value of frag that failed */
6581 /* start back at beginning and unmap skb */
6582 prod = txr->tx_prod;
6583 ring_prod = TX_RING_IDX(prod);
6584 tx_buf = &txr->tx_buf_ring[ring_prod];
6586 dma_unmap_single(&bp->pdev->dev, dma_unmap_addr(tx_buf, mapping),
6587 skb_headlen(skb), PCI_DMA_TODEVICE);
6589 /* unmap remaining mapped pages */
6590 for (i = 0; i < last_frag; i++) {
6591 prod = NEXT_TX_BD(prod);
6592 ring_prod = TX_RING_IDX(prod);
6593 tx_buf = &txr->tx_buf_ring[ring_prod];
6594 dma_unmap_page(&bp->pdev->dev, dma_unmap_addr(tx_buf, mapping),
6595 skb_frag_size(&skb_shinfo(skb)->frags[i]),
6600 return NETDEV_TX_OK;
6603 /* Called with rtnl_lock */
6605 bnx2_close(struct net_device *dev)
6607 struct bnx2 *bp = netdev_priv(dev);
6609 bnx2_disable_int_sync(bp);
6610 bnx2_napi_disable(bp);
6611 del_timer_sync(&bp->timer);
6612 bnx2_shutdown_chip(bp);
6618 netif_carrier_off(bp->dev);
6619 bnx2_set_power_state(bp, PCI_D3hot);
6624 bnx2_save_stats(struct bnx2 *bp)
6626 u32 *hw_stats = (u32 *) bp->stats_blk;
6627 u32 *temp_stats = (u32 *) bp->temp_stats_blk;
6630 /* The 1st 10 counters are 64-bit counters */
6631 for (i = 0; i < 20; i += 2) {
6635 hi = temp_stats[i] + hw_stats[i];
6636 lo = (u64) temp_stats[i + 1] + (u64) hw_stats[i + 1];
6637 if (lo > 0xffffffff)
6640 temp_stats[i + 1] = lo & 0xffffffff;
6643 for ( ; i < sizeof(struct statistics_block) / 4; i++)
6644 temp_stats[i] += hw_stats[i];
6647 #define GET_64BIT_NET_STATS64(ctr) \
6648 (((u64) (ctr##_hi) << 32) + (u64) (ctr##_lo))
6650 #define GET_64BIT_NET_STATS(ctr) \
6651 GET_64BIT_NET_STATS64(bp->stats_blk->ctr) + \
6652 GET_64BIT_NET_STATS64(bp->temp_stats_blk->ctr)
6654 #define GET_32BIT_NET_STATS(ctr) \
6655 (unsigned long) (bp->stats_blk->ctr + \
6656 bp->temp_stats_blk->ctr)
6658 static struct rtnl_link_stats64 *
6659 bnx2_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *net_stats)
6661 struct bnx2 *bp = netdev_priv(dev);
6663 if (bp->stats_blk == NULL)
6666 net_stats->rx_packets =
6667 GET_64BIT_NET_STATS(stat_IfHCInUcastPkts) +
6668 GET_64BIT_NET_STATS(stat_IfHCInMulticastPkts) +
6669 GET_64BIT_NET_STATS(stat_IfHCInBroadcastPkts);
6671 net_stats->tx_packets =
6672 GET_64BIT_NET_STATS(stat_IfHCOutUcastPkts) +
6673 GET_64BIT_NET_STATS(stat_IfHCOutMulticastPkts) +
6674 GET_64BIT_NET_STATS(stat_IfHCOutBroadcastPkts);
6676 net_stats->rx_bytes =
6677 GET_64BIT_NET_STATS(stat_IfHCInOctets);
6679 net_stats->tx_bytes =
6680 GET_64BIT_NET_STATS(stat_IfHCOutOctets);
6682 net_stats->multicast =
6683 GET_64BIT_NET_STATS(stat_IfHCInMulticastPkts);
6685 net_stats->collisions =
6686 GET_32BIT_NET_STATS(stat_EtherStatsCollisions);
6688 net_stats->rx_length_errors =
6689 GET_32BIT_NET_STATS(stat_EtherStatsUndersizePkts) +
6690 GET_32BIT_NET_STATS(stat_EtherStatsOverrsizePkts);
6692 net_stats->rx_over_errors =
6693 GET_32BIT_NET_STATS(stat_IfInFTQDiscards) +
6694 GET_32BIT_NET_STATS(stat_IfInMBUFDiscards);
6696 net_stats->rx_frame_errors =
6697 GET_32BIT_NET_STATS(stat_Dot3StatsAlignmentErrors);
6699 net_stats->rx_crc_errors =
6700 GET_32BIT_NET_STATS(stat_Dot3StatsFCSErrors);
6702 net_stats->rx_errors = net_stats->rx_length_errors +
6703 net_stats->rx_over_errors + net_stats->rx_frame_errors +
6704 net_stats->rx_crc_errors;
6706 net_stats->tx_aborted_errors =
6707 GET_32BIT_NET_STATS(stat_Dot3StatsExcessiveCollisions) +
6708 GET_32BIT_NET_STATS(stat_Dot3StatsLateCollisions);
6710 if ((CHIP_NUM(bp) == CHIP_NUM_5706) ||
6711 (CHIP_ID(bp) == CHIP_ID_5708_A0))
6712 net_stats->tx_carrier_errors = 0;
6714 net_stats->tx_carrier_errors =
6715 GET_32BIT_NET_STATS(stat_Dot3StatsCarrierSenseErrors);
6718 net_stats->tx_errors =
6719 GET_32BIT_NET_STATS(stat_emac_tx_stat_dot3statsinternalmactransmiterrors) +
6720 net_stats->tx_aborted_errors +
6721 net_stats->tx_carrier_errors;
6723 net_stats->rx_missed_errors =
6724 GET_32BIT_NET_STATS(stat_IfInFTQDiscards) +
6725 GET_32BIT_NET_STATS(stat_IfInMBUFDiscards) +
6726 GET_32BIT_NET_STATS(stat_FwRxDrop);
6731 /* All ethtool functions called with rtnl_lock */
6734 bnx2_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
6736 struct bnx2 *bp = netdev_priv(dev);
6737 int support_serdes = 0, support_copper = 0;
6739 cmd->supported = SUPPORTED_Autoneg;
6740 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
6743 } else if (bp->phy_port == PORT_FIBRE)
6748 if (support_serdes) {
6749 cmd->supported |= SUPPORTED_1000baseT_Full |
6751 if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE)
6752 cmd->supported |= SUPPORTED_2500baseX_Full;
6755 if (support_copper) {
6756 cmd->supported |= SUPPORTED_10baseT_Half |
6757 SUPPORTED_10baseT_Full |
6758 SUPPORTED_100baseT_Half |
6759 SUPPORTED_100baseT_Full |
6760 SUPPORTED_1000baseT_Full |
6765 spin_lock_bh(&bp->phy_lock);
6766 cmd->port = bp->phy_port;
6767 cmd->advertising = bp->advertising;
6769 if (bp->autoneg & AUTONEG_SPEED) {
6770 cmd->autoneg = AUTONEG_ENABLE;
6772 cmd->autoneg = AUTONEG_DISABLE;
6775 if (netif_carrier_ok(dev)) {
6776 ethtool_cmd_speed_set(cmd, bp->line_speed);
6777 cmd->duplex = bp->duplex;
6780 ethtool_cmd_speed_set(cmd, -1);
6783 spin_unlock_bh(&bp->phy_lock);
6785 cmd->transceiver = XCVR_INTERNAL;
6786 cmd->phy_address = bp->phy_addr;
6792 bnx2_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
6794 struct bnx2 *bp = netdev_priv(dev);
6795 u8 autoneg = bp->autoneg;
6796 u8 req_duplex = bp->req_duplex;
6797 u16 req_line_speed = bp->req_line_speed;
6798 u32 advertising = bp->advertising;
6801 spin_lock_bh(&bp->phy_lock);
6803 if (cmd->port != PORT_TP && cmd->port != PORT_FIBRE)
6804 goto err_out_unlock;
6806 if (cmd->port != bp->phy_port &&
6807 !(bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP))
6808 goto err_out_unlock;
6810 /* If device is down, we can store the settings only if the user
6811 * is setting the currently active port.
6813 if (!netif_running(dev) && cmd->port != bp->phy_port)
6814 goto err_out_unlock;
6816 if (cmd->autoneg == AUTONEG_ENABLE) {
6817 autoneg |= AUTONEG_SPEED;
6819 advertising = cmd->advertising;
6820 if (cmd->port == PORT_TP) {
6821 advertising &= ETHTOOL_ALL_COPPER_SPEED;
6823 advertising = ETHTOOL_ALL_COPPER_SPEED;
6825 advertising &= ETHTOOL_ALL_FIBRE_SPEED;
6827 advertising = ETHTOOL_ALL_FIBRE_SPEED;
6829 advertising |= ADVERTISED_Autoneg;
6832 u32 speed = ethtool_cmd_speed(cmd);
6833 if (cmd->port == PORT_FIBRE) {
6834 if ((speed != SPEED_1000 &&
6835 speed != SPEED_2500) ||
6836 (cmd->duplex != DUPLEX_FULL))
6837 goto err_out_unlock;
6839 if (speed == SPEED_2500 &&
6840 !(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
6841 goto err_out_unlock;
6842 } else if (speed == SPEED_1000 || speed == SPEED_2500)
6843 goto err_out_unlock;
6845 autoneg &= ~AUTONEG_SPEED;
6846 req_line_speed = speed;
6847 req_duplex = cmd->duplex;
6851 bp->autoneg = autoneg;
6852 bp->advertising = advertising;
6853 bp->req_line_speed = req_line_speed;
6854 bp->req_duplex = req_duplex;
6857 /* If device is down, the new settings will be picked up when it is
6860 if (netif_running(dev))
6861 err = bnx2_setup_phy(bp, cmd->port);
6864 spin_unlock_bh(&bp->phy_lock);
6870 bnx2_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
6872 struct bnx2 *bp = netdev_priv(dev);
6874 strlcpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver));
6875 strlcpy(info->version, DRV_MODULE_VERSION, sizeof(info->version));
6876 strlcpy(info->bus_info, pci_name(bp->pdev), sizeof(info->bus_info));
6877 strlcpy(info->fw_version, bp->fw_version, sizeof(info->fw_version));
6880 #define BNX2_REGDUMP_LEN (32 * 1024)
6883 bnx2_get_regs_len(struct net_device *dev)
6885 return BNX2_REGDUMP_LEN;
6889 bnx2_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *_p)
6891 u32 *p = _p, i, offset;
6893 struct bnx2 *bp = netdev_priv(dev);
6894 static const u32 reg_boundaries[] = {
6895 0x0000, 0x0098, 0x0400, 0x045c,
6896 0x0800, 0x0880, 0x0c00, 0x0c10,
6897 0x0c30, 0x0d08, 0x1000, 0x101c,
6898 0x1040, 0x1048, 0x1080, 0x10a4,
6899 0x1400, 0x1490, 0x1498, 0x14f0,
6900 0x1500, 0x155c, 0x1580, 0x15dc,
6901 0x1600, 0x1658, 0x1680, 0x16d8,
6902 0x1800, 0x1820, 0x1840, 0x1854,
6903 0x1880, 0x1894, 0x1900, 0x1984,
6904 0x1c00, 0x1c0c, 0x1c40, 0x1c54,
6905 0x1c80, 0x1c94, 0x1d00, 0x1d84,
6906 0x2000, 0x2030, 0x23c0, 0x2400,
6907 0x2800, 0x2820, 0x2830, 0x2850,
6908 0x2b40, 0x2c10, 0x2fc0, 0x3058,
6909 0x3c00, 0x3c94, 0x4000, 0x4010,
6910 0x4080, 0x4090, 0x43c0, 0x4458,
6911 0x4c00, 0x4c18, 0x4c40, 0x4c54,
6912 0x4fc0, 0x5010, 0x53c0, 0x5444,
6913 0x5c00, 0x5c18, 0x5c80, 0x5c90,
6914 0x5fc0, 0x6000, 0x6400, 0x6428,
6915 0x6800, 0x6848, 0x684c, 0x6860,
6916 0x6888, 0x6910, 0x8000
6921 memset(p, 0, BNX2_REGDUMP_LEN);
6923 if (!netif_running(bp->dev))
6927 offset = reg_boundaries[0];
6929 while (offset < BNX2_REGDUMP_LEN) {
6930 *p++ = REG_RD(bp, offset);
6932 if (offset == reg_boundaries[i + 1]) {
6933 offset = reg_boundaries[i + 2];
6934 p = (u32 *) (orig_p + offset);
6941 bnx2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
6943 struct bnx2 *bp = netdev_priv(dev);
6945 if (bp->flags & BNX2_FLAG_NO_WOL) {
6950 wol->supported = WAKE_MAGIC;
6952 wol->wolopts = WAKE_MAGIC;
6956 memset(&wol->sopass, 0, sizeof(wol->sopass));
6960 bnx2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
6962 struct bnx2 *bp = netdev_priv(dev);
6964 if (wol->wolopts & ~WAKE_MAGIC)
6967 if (wol->wolopts & WAKE_MAGIC) {
6968 if (bp->flags & BNX2_FLAG_NO_WOL)
6980 bnx2_nway_reset(struct net_device *dev)
6982 struct bnx2 *bp = netdev_priv(dev);
6985 if (!netif_running(dev))
6988 if (!(bp->autoneg & AUTONEG_SPEED)) {
6992 spin_lock_bh(&bp->phy_lock);
6994 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
6997 rc = bnx2_setup_remote_phy(bp, bp->phy_port);
6998 spin_unlock_bh(&bp->phy_lock);
7002 /* Force a link down visible on the other side */
7003 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
7004 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);
7005 spin_unlock_bh(&bp->phy_lock);
7009 spin_lock_bh(&bp->phy_lock);
7011 bp->current_interval = BNX2_SERDES_AN_TIMEOUT;
7012 bp->serdes_an_pending = 1;
7013 mod_timer(&bp->timer, jiffies + bp->current_interval);
7016 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
7017 bmcr &= ~BMCR_LOOPBACK;
7018 bnx2_write_phy(bp, bp->mii_bmcr, bmcr | BMCR_ANRESTART | BMCR_ANENABLE);
7020 spin_unlock_bh(&bp->phy_lock);
7026 bnx2_get_link(struct net_device *dev)
7028 struct bnx2 *bp = netdev_priv(dev);
7034 bnx2_get_eeprom_len(struct net_device *dev)
7036 struct bnx2 *bp = netdev_priv(dev);
7038 if (bp->flash_info == NULL)
7041 return (int) bp->flash_size;
7045 bnx2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
7048 struct bnx2 *bp = netdev_priv(dev);
7051 if (!netif_running(dev))
7054 /* parameters already validated in ethtool_get_eeprom */
7056 rc = bnx2_nvram_read(bp, eeprom->offset, eebuf, eeprom->len);
7062 bnx2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
7065 struct bnx2 *bp = netdev_priv(dev);
7068 if (!netif_running(dev))
7071 /* parameters already validated in ethtool_set_eeprom */
7073 rc = bnx2_nvram_write(bp, eeprom->offset, eebuf, eeprom->len);
7079 bnx2_get_coalesce(struct net_device *dev, struct ethtool_coalesce *coal)
7081 struct bnx2 *bp = netdev_priv(dev);
7083 memset(coal, 0, sizeof(struct ethtool_coalesce));
7085 coal->rx_coalesce_usecs = bp->rx_ticks;
7086 coal->rx_max_coalesced_frames = bp->rx_quick_cons_trip;
7087 coal->rx_coalesce_usecs_irq = bp->rx_ticks_int;
7088 coal->rx_max_coalesced_frames_irq = bp->rx_quick_cons_trip_int;
7090 coal->tx_coalesce_usecs = bp->tx_ticks;
7091 coal->tx_max_coalesced_frames = bp->tx_quick_cons_trip;
7092 coal->tx_coalesce_usecs_irq = bp->tx_ticks_int;
7093 coal->tx_max_coalesced_frames_irq = bp->tx_quick_cons_trip_int;
7095 coal->stats_block_coalesce_usecs = bp->stats_ticks;
7101 bnx2_set_coalesce(struct net_device *dev, struct ethtool_coalesce *coal)
7103 struct bnx2 *bp = netdev_priv(dev);
7105 bp->rx_ticks = (u16) coal->rx_coalesce_usecs;
7106 if (bp->rx_ticks > 0x3ff) bp->rx_ticks = 0x3ff;
7108 bp->rx_quick_cons_trip = (u16) coal->rx_max_coalesced_frames;
7109 if (bp->rx_quick_cons_trip > 0xff) bp->rx_quick_cons_trip = 0xff;
7111 bp->rx_ticks_int = (u16) coal->rx_coalesce_usecs_irq;
7112 if (bp->rx_ticks_int > 0x3ff) bp->rx_ticks_int = 0x3ff;
7114 bp->rx_quick_cons_trip_int = (u16) coal->rx_max_coalesced_frames_irq;
7115 if (bp->rx_quick_cons_trip_int > 0xff)
7116 bp->rx_quick_cons_trip_int = 0xff;
7118 bp->tx_ticks = (u16) coal->tx_coalesce_usecs;
7119 if (bp->tx_ticks > 0x3ff) bp->tx_ticks = 0x3ff;
7121 bp->tx_quick_cons_trip = (u16) coal->tx_max_coalesced_frames;
7122 if (bp->tx_quick_cons_trip > 0xff) bp->tx_quick_cons_trip = 0xff;
7124 bp->tx_ticks_int = (u16) coal->tx_coalesce_usecs_irq;
7125 if (bp->tx_ticks_int > 0x3ff) bp->tx_ticks_int = 0x3ff;
7127 bp->tx_quick_cons_trip_int = (u16) coal->tx_max_coalesced_frames_irq;
7128 if (bp->tx_quick_cons_trip_int > 0xff) bp->tx_quick_cons_trip_int =
7131 bp->stats_ticks = coal->stats_block_coalesce_usecs;
7132 if (bp->flags & BNX2_FLAG_BROKEN_STATS) {
7133 if (bp->stats_ticks != 0 && bp->stats_ticks != USEC_PER_SEC)
7134 bp->stats_ticks = USEC_PER_SEC;
7136 if (bp->stats_ticks > BNX2_HC_STATS_TICKS_HC_STAT_TICKS)
7137 bp->stats_ticks = BNX2_HC_STATS_TICKS_HC_STAT_TICKS;
7138 bp->stats_ticks &= BNX2_HC_STATS_TICKS_HC_STAT_TICKS;
7140 if (netif_running(bp->dev)) {
7141 bnx2_netif_stop(bp, true);
7142 bnx2_init_nic(bp, 0);
7143 bnx2_netif_start(bp, true);
7150 bnx2_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
7152 struct bnx2 *bp = netdev_priv(dev);
7154 ering->rx_max_pending = MAX_TOTAL_RX_DESC_CNT;
7155 ering->rx_jumbo_max_pending = MAX_TOTAL_RX_PG_DESC_CNT;
7157 ering->rx_pending = bp->rx_ring_size;
7158 ering->rx_jumbo_pending = bp->rx_pg_ring_size;
7160 ering->tx_max_pending = MAX_TX_DESC_CNT;
7161 ering->tx_pending = bp->tx_ring_size;
7165 bnx2_change_ring_size(struct bnx2 *bp, u32 rx, u32 tx)
7167 if (netif_running(bp->dev)) {
7168 /* Reset will erase chipset stats; save them */
7169 bnx2_save_stats(bp);
7171 bnx2_netif_stop(bp, true);
7172 bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_RESET);
7173 __bnx2_free_irq(bp);
7178 bnx2_set_rx_ring_size(bp, rx);
7179 bp->tx_ring_size = tx;
7181 if (netif_running(bp->dev)) {
7184 rc = bnx2_alloc_mem(bp);
7186 rc = bnx2_request_irq(bp);
7189 rc = bnx2_init_nic(bp, 0);
7192 bnx2_napi_enable(bp);
7197 mutex_lock(&bp->cnic_lock);
7198 /* Let cnic know about the new status block. */
7199 if (bp->cnic_eth_dev.drv_state & CNIC_DRV_STATE_REGD)
7200 bnx2_setup_cnic_irq_info(bp);
7201 mutex_unlock(&bp->cnic_lock);
7203 bnx2_netif_start(bp, true);
7209 bnx2_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
7211 struct bnx2 *bp = netdev_priv(dev);
7214 if ((ering->rx_pending > MAX_TOTAL_RX_DESC_CNT) ||
7215 (ering->tx_pending > MAX_TX_DESC_CNT) ||
7216 (ering->tx_pending <= MAX_SKB_FRAGS)) {
7220 rc = bnx2_change_ring_size(bp, ering->rx_pending, ering->tx_pending);
7225 bnx2_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
7227 struct bnx2 *bp = netdev_priv(dev);
7229 epause->autoneg = ((bp->autoneg & AUTONEG_FLOW_CTRL) != 0);
7230 epause->rx_pause = ((bp->flow_ctrl & FLOW_CTRL_RX) != 0);
7231 epause->tx_pause = ((bp->flow_ctrl & FLOW_CTRL_TX) != 0);
7235 bnx2_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
7237 struct bnx2 *bp = netdev_priv(dev);
7239 bp->req_flow_ctrl = 0;
7240 if (epause->rx_pause)
7241 bp->req_flow_ctrl |= FLOW_CTRL_RX;
7242 if (epause->tx_pause)
7243 bp->req_flow_ctrl |= FLOW_CTRL_TX;
7245 if (epause->autoneg) {
7246 bp->autoneg |= AUTONEG_FLOW_CTRL;
7249 bp->autoneg &= ~AUTONEG_FLOW_CTRL;
7252 if (netif_running(dev)) {
7253 spin_lock_bh(&bp->phy_lock);
7254 bnx2_setup_phy(bp, bp->phy_port);
7255 spin_unlock_bh(&bp->phy_lock);
7262 char string[ETH_GSTRING_LEN];
7263 } bnx2_stats_str_arr[] = {
7265 { "rx_error_bytes" },
7267 { "tx_error_bytes" },
7268 { "rx_ucast_packets" },
7269 { "rx_mcast_packets" },
7270 { "rx_bcast_packets" },
7271 { "tx_ucast_packets" },
7272 { "tx_mcast_packets" },
7273 { "tx_bcast_packets" },
7274 { "tx_mac_errors" },
7275 { "tx_carrier_errors" },
7276 { "rx_crc_errors" },
7277 { "rx_align_errors" },
7278 { "tx_single_collisions" },
7279 { "tx_multi_collisions" },
7281 { "tx_excess_collisions" },
7282 { "tx_late_collisions" },
7283 { "tx_total_collisions" },
7286 { "rx_undersize_packets" },
7287 { "rx_oversize_packets" },
7288 { "rx_64_byte_packets" },
7289 { "rx_65_to_127_byte_packets" },
7290 { "rx_128_to_255_byte_packets" },
7291 { "rx_256_to_511_byte_packets" },
7292 { "rx_512_to_1023_byte_packets" },
7293 { "rx_1024_to_1522_byte_packets" },
7294 { "rx_1523_to_9022_byte_packets" },
7295 { "tx_64_byte_packets" },
7296 { "tx_65_to_127_byte_packets" },
7297 { "tx_128_to_255_byte_packets" },
7298 { "tx_256_to_511_byte_packets" },
7299 { "tx_512_to_1023_byte_packets" },
7300 { "tx_1024_to_1522_byte_packets" },
7301 { "tx_1523_to_9022_byte_packets" },
7302 { "rx_xon_frames" },
7303 { "rx_xoff_frames" },
7304 { "tx_xon_frames" },
7305 { "tx_xoff_frames" },
7306 { "rx_mac_ctrl_frames" },
7307 { "rx_filtered_packets" },
7308 { "rx_ftq_discards" },
7310 { "rx_fw_discards" },
7313 #define BNX2_NUM_STATS (sizeof(bnx2_stats_str_arr)/\
7314 sizeof(bnx2_stats_str_arr[0]))
7316 #define STATS_OFFSET32(offset_name) (offsetof(struct statistics_block, offset_name) / 4)
7318 static const unsigned long bnx2_stats_offset_arr[BNX2_NUM_STATS] = {
7319 STATS_OFFSET32(stat_IfHCInOctets_hi),
7320 STATS_OFFSET32(stat_IfHCInBadOctets_hi),
7321 STATS_OFFSET32(stat_IfHCOutOctets_hi),
7322 STATS_OFFSET32(stat_IfHCOutBadOctets_hi),
7323 STATS_OFFSET32(stat_IfHCInUcastPkts_hi),
7324 STATS_OFFSET32(stat_IfHCInMulticastPkts_hi),
7325 STATS_OFFSET32(stat_IfHCInBroadcastPkts_hi),
7326 STATS_OFFSET32(stat_IfHCOutUcastPkts_hi),
7327 STATS_OFFSET32(stat_IfHCOutMulticastPkts_hi),
7328 STATS_OFFSET32(stat_IfHCOutBroadcastPkts_hi),
7329 STATS_OFFSET32(stat_emac_tx_stat_dot3statsinternalmactransmiterrors),
7330 STATS_OFFSET32(stat_Dot3StatsCarrierSenseErrors),
7331 STATS_OFFSET32(stat_Dot3StatsFCSErrors),
7332 STATS_OFFSET32(stat_Dot3StatsAlignmentErrors),
7333 STATS_OFFSET32(stat_Dot3StatsSingleCollisionFrames),
7334 STATS_OFFSET32(stat_Dot3StatsMultipleCollisionFrames),
7335 STATS_OFFSET32(stat_Dot3StatsDeferredTransmissions),
7336 STATS_OFFSET32(stat_Dot3StatsExcessiveCollisions),
7337 STATS_OFFSET32(stat_Dot3StatsLateCollisions),
7338 STATS_OFFSET32(stat_EtherStatsCollisions),
7339 STATS_OFFSET32(stat_EtherStatsFragments),
7340 STATS_OFFSET32(stat_EtherStatsJabbers),
7341 STATS_OFFSET32(stat_EtherStatsUndersizePkts),
7342 STATS_OFFSET32(stat_EtherStatsOverrsizePkts),
7343 STATS_OFFSET32(stat_EtherStatsPktsRx64Octets),
7344 STATS_OFFSET32(stat_EtherStatsPktsRx65Octetsto127Octets),
7345 STATS_OFFSET32(stat_EtherStatsPktsRx128Octetsto255Octets),
7346 STATS_OFFSET32(stat_EtherStatsPktsRx256Octetsto511Octets),
7347 STATS_OFFSET32(stat_EtherStatsPktsRx512Octetsto1023Octets),
7348 STATS_OFFSET32(stat_EtherStatsPktsRx1024Octetsto1522Octets),
7349 STATS_OFFSET32(stat_EtherStatsPktsRx1523Octetsto9022Octets),
7350 STATS_OFFSET32(stat_EtherStatsPktsTx64Octets),
7351 STATS_OFFSET32(stat_EtherStatsPktsTx65Octetsto127Octets),
7352 STATS_OFFSET32(stat_EtherStatsPktsTx128Octetsto255Octets),
7353 STATS_OFFSET32(stat_EtherStatsPktsTx256Octetsto511Octets),
7354 STATS_OFFSET32(stat_EtherStatsPktsTx512Octetsto1023Octets),
7355 STATS_OFFSET32(stat_EtherStatsPktsTx1024Octetsto1522Octets),
7356 STATS_OFFSET32(stat_EtherStatsPktsTx1523Octetsto9022Octets),
7357 STATS_OFFSET32(stat_XonPauseFramesReceived),
7358 STATS_OFFSET32(stat_XoffPauseFramesReceived),
7359 STATS_OFFSET32(stat_OutXonSent),
7360 STATS_OFFSET32(stat_OutXoffSent),
7361 STATS_OFFSET32(stat_MacControlFramesReceived),
7362 STATS_OFFSET32(stat_IfInFramesL2FilterDiscards),
7363 STATS_OFFSET32(stat_IfInFTQDiscards),
7364 STATS_OFFSET32(stat_IfInMBUFDiscards),
7365 STATS_OFFSET32(stat_FwRxDrop),
7368 /* stat_IfHCInBadOctets and stat_Dot3StatsCarrierSenseErrors are
7369 * skipped because of errata.
7371 static u8 bnx2_5706_stats_len_arr[BNX2_NUM_STATS] = {
7372 8,0,8,8,8,8,8,8,8,8,
7373 4,0,4,4,4,4,4,4,4,4,
7374 4,4,4,4,4,4,4,4,4,4,
7375 4,4,4,4,4,4,4,4,4,4,
7379 static u8 bnx2_5708_stats_len_arr[BNX2_NUM_STATS] = {
7380 8,0,8,8,8,8,8,8,8,8,
7381 4,4,4,4,4,4,4,4,4,4,
7382 4,4,4,4,4,4,4,4,4,4,
7383 4,4,4,4,4,4,4,4,4,4,
7387 #define BNX2_NUM_TESTS 6
7390 char string[ETH_GSTRING_LEN];
7391 } bnx2_tests_str_arr[BNX2_NUM_TESTS] = {
7392 { "register_test (offline)" },
7393 { "memory_test (offline)" },
7394 { "loopback_test (offline)" },
7395 { "nvram_test (online)" },
7396 { "interrupt_test (online)" },
7397 { "link_test (online)" },
7401 bnx2_get_sset_count(struct net_device *dev, int sset)
7405 return BNX2_NUM_TESTS;
7407 return BNX2_NUM_STATS;
7414 bnx2_self_test(struct net_device *dev, struct ethtool_test *etest, u64 *buf)
7416 struct bnx2 *bp = netdev_priv(dev);
7418 bnx2_set_power_state(bp, PCI_D0);
7420 memset(buf, 0, sizeof(u64) * BNX2_NUM_TESTS);
7421 if (etest->flags & ETH_TEST_FL_OFFLINE) {
7424 bnx2_netif_stop(bp, true);
7425 bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_DIAG);
7428 if (bnx2_test_registers(bp) != 0) {
7430 etest->flags |= ETH_TEST_FL_FAILED;
7432 if (bnx2_test_memory(bp) != 0) {
7434 etest->flags |= ETH_TEST_FL_FAILED;
7436 if ((buf[2] = bnx2_test_loopback(bp)) != 0)
7437 etest->flags |= ETH_TEST_FL_FAILED;
7439 if (!netif_running(bp->dev))
7440 bnx2_shutdown_chip(bp);
7442 bnx2_init_nic(bp, 1);
7443 bnx2_netif_start(bp, true);
7446 /* wait for link up */
7447 for (i = 0; i < 7; i++) {
7450 msleep_interruptible(1000);
7454 if (bnx2_test_nvram(bp) != 0) {
7456 etest->flags |= ETH_TEST_FL_FAILED;
7458 if (bnx2_test_intr(bp) != 0) {
7460 etest->flags |= ETH_TEST_FL_FAILED;
7463 if (bnx2_test_link(bp) != 0) {
7465 etest->flags |= ETH_TEST_FL_FAILED;
7468 if (!netif_running(bp->dev))
7469 bnx2_set_power_state(bp, PCI_D3hot);
7473 bnx2_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
7475 switch (stringset) {
7477 memcpy(buf, bnx2_stats_str_arr,
7478 sizeof(bnx2_stats_str_arr));
7481 memcpy(buf, bnx2_tests_str_arr,
7482 sizeof(bnx2_tests_str_arr));
7488 bnx2_get_ethtool_stats(struct net_device *dev,
7489 struct ethtool_stats *stats, u64 *buf)
7491 struct bnx2 *bp = netdev_priv(dev);
7493 u32 *hw_stats = (u32 *) bp->stats_blk;
7494 u32 *temp_stats = (u32 *) bp->temp_stats_blk;
7495 u8 *stats_len_arr = NULL;
7497 if (hw_stats == NULL) {
7498 memset(buf, 0, sizeof(u64) * BNX2_NUM_STATS);
7502 if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
7503 (CHIP_ID(bp) == CHIP_ID_5706_A1) ||
7504 (CHIP_ID(bp) == CHIP_ID_5706_A2) ||
7505 (CHIP_ID(bp) == CHIP_ID_5708_A0))
7506 stats_len_arr = bnx2_5706_stats_len_arr;
7508 stats_len_arr = bnx2_5708_stats_len_arr;
7510 for (i = 0; i < BNX2_NUM_STATS; i++) {
7511 unsigned long offset;
7513 if (stats_len_arr[i] == 0) {
7514 /* skip this counter */
7519 offset = bnx2_stats_offset_arr[i];
7520 if (stats_len_arr[i] == 4) {
7521 /* 4-byte counter */
7522 buf[i] = (u64) *(hw_stats + offset) +
7523 *(temp_stats + offset);
7526 /* 8-byte counter */
7527 buf[i] = (((u64) *(hw_stats + offset)) << 32) +
7528 *(hw_stats + offset + 1) +
7529 (((u64) *(temp_stats + offset)) << 32) +
7530 *(temp_stats + offset + 1);
7535 bnx2_set_phys_id(struct net_device *dev, enum ethtool_phys_id_state state)
7537 struct bnx2 *bp = netdev_priv(dev);
7540 case ETHTOOL_ID_ACTIVE:
7541 bnx2_set_power_state(bp, PCI_D0);
7543 bp->leds_save = REG_RD(bp, BNX2_MISC_CFG);
7544 REG_WR(bp, BNX2_MISC_CFG, BNX2_MISC_CFG_LEDMODE_MAC);
7545 return 1; /* cycle on/off once per second */
7548 REG_WR(bp, BNX2_EMAC_LED, BNX2_EMAC_LED_OVERRIDE |
7549 BNX2_EMAC_LED_1000MB_OVERRIDE |
7550 BNX2_EMAC_LED_100MB_OVERRIDE |
7551 BNX2_EMAC_LED_10MB_OVERRIDE |
7552 BNX2_EMAC_LED_TRAFFIC_OVERRIDE |
7553 BNX2_EMAC_LED_TRAFFIC);
7556 case ETHTOOL_ID_OFF:
7557 REG_WR(bp, BNX2_EMAC_LED, BNX2_EMAC_LED_OVERRIDE);
7560 case ETHTOOL_ID_INACTIVE:
7561 REG_WR(bp, BNX2_EMAC_LED, 0);
7562 REG_WR(bp, BNX2_MISC_CFG, bp->leds_save);
7564 if (!netif_running(dev))
7565 bnx2_set_power_state(bp, PCI_D3hot);
7572 static netdev_features_t
7573 bnx2_fix_features(struct net_device *dev, netdev_features_t features)
7575 struct bnx2 *bp = netdev_priv(dev);
7577 if (!(bp->flags & BNX2_FLAG_CAN_KEEP_VLAN))
7578 features |= NETIF_F_HW_VLAN_RX;
7584 bnx2_set_features(struct net_device *dev, netdev_features_t features)
7586 struct bnx2 *bp = netdev_priv(dev);
7588 /* TSO with VLAN tag won't work with current firmware */
7589 if (features & NETIF_F_HW_VLAN_TX)
7590 dev->vlan_features |= (dev->hw_features & NETIF_F_ALL_TSO);
7592 dev->vlan_features &= ~NETIF_F_ALL_TSO;
7594 if ((!!(features & NETIF_F_HW_VLAN_RX) !=
7595 !!(bp->rx_mode & BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG)) &&
7596 netif_running(dev)) {
7597 bnx2_netif_stop(bp, false);
7598 dev->features = features;
7599 bnx2_set_rx_mode(dev);
7600 bnx2_fw_sync(bp, BNX2_DRV_MSG_CODE_KEEP_VLAN_UPDATE, 0, 1);
7601 bnx2_netif_start(bp, false);
7608 static const struct ethtool_ops bnx2_ethtool_ops = {
7609 .get_settings = bnx2_get_settings,
7610 .set_settings = bnx2_set_settings,
7611 .get_drvinfo = bnx2_get_drvinfo,
7612 .get_regs_len = bnx2_get_regs_len,
7613 .get_regs = bnx2_get_regs,
7614 .get_wol = bnx2_get_wol,
7615 .set_wol = bnx2_set_wol,
7616 .nway_reset = bnx2_nway_reset,
7617 .get_link = bnx2_get_link,
7618 .get_eeprom_len = bnx2_get_eeprom_len,
7619 .get_eeprom = bnx2_get_eeprom,
7620 .set_eeprom = bnx2_set_eeprom,
7621 .get_coalesce = bnx2_get_coalesce,
7622 .set_coalesce = bnx2_set_coalesce,
7623 .get_ringparam = bnx2_get_ringparam,
7624 .set_ringparam = bnx2_set_ringparam,
7625 .get_pauseparam = bnx2_get_pauseparam,
7626 .set_pauseparam = bnx2_set_pauseparam,
7627 .self_test = bnx2_self_test,
7628 .get_strings = bnx2_get_strings,
7629 .set_phys_id = bnx2_set_phys_id,
7630 .get_ethtool_stats = bnx2_get_ethtool_stats,
7631 .get_sset_count = bnx2_get_sset_count,
7634 /* Called with rtnl_lock */
7636 bnx2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
7638 struct mii_ioctl_data *data = if_mii(ifr);
7639 struct bnx2 *bp = netdev_priv(dev);
7644 data->phy_id = bp->phy_addr;
7650 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
7653 if (!netif_running(dev))
7656 spin_lock_bh(&bp->phy_lock);
7657 err = bnx2_read_phy(bp, data->reg_num & 0x1f, &mii_regval);
7658 spin_unlock_bh(&bp->phy_lock);
7660 data->val_out = mii_regval;
7666 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
7669 if (!netif_running(dev))
7672 spin_lock_bh(&bp->phy_lock);
7673 err = bnx2_write_phy(bp, data->reg_num & 0x1f, data->val_in);
7674 spin_unlock_bh(&bp->phy_lock);
7685 /* Called with rtnl_lock */
7687 bnx2_change_mac_addr(struct net_device *dev, void *p)
7689 struct sockaddr *addr = p;
7690 struct bnx2 *bp = netdev_priv(dev);
7692 if (!is_valid_ether_addr(addr->sa_data))
7695 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
7696 if (netif_running(dev))
7697 bnx2_set_mac_addr(bp, bp->dev->dev_addr, 0);
7702 /* Called with rtnl_lock */
7704 bnx2_change_mtu(struct net_device *dev, int new_mtu)
7706 struct bnx2 *bp = netdev_priv(dev);
7708 if (((new_mtu + ETH_HLEN) > MAX_ETHERNET_JUMBO_PACKET_SIZE) ||
7709 ((new_mtu + ETH_HLEN) < MIN_ETHERNET_PACKET_SIZE))
7713 return bnx2_change_ring_size(bp, bp->rx_ring_size, bp->tx_ring_size);
7716 #ifdef CONFIG_NET_POLL_CONTROLLER
7718 poll_bnx2(struct net_device *dev)
7720 struct bnx2 *bp = netdev_priv(dev);
7723 for (i = 0; i < bp->irq_nvecs; i++) {
7724 struct bnx2_irq *irq = &bp->irq_tbl[i];
7726 disable_irq(irq->vector);
7727 irq->handler(irq->vector, &bp->bnx2_napi[i]);
7728 enable_irq(irq->vector);
7733 static void __devinit
7734 bnx2_get_5709_media(struct bnx2 *bp)
7736 u32 val = REG_RD(bp, BNX2_MISC_DUAL_MEDIA_CTRL);
7737 u32 bond_id = val & BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID;
7740 if (bond_id == BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID_C)
7742 else if (bond_id == BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID_S) {
7743 bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
7747 if (val & BNX2_MISC_DUAL_MEDIA_CTRL_STRAP_OVERRIDE)
7748 strap = (val & BNX2_MISC_DUAL_MEDIA_CTRL_PHY_CTRL) >> 21;
7750 strap = (val & BNX2_MISC_DUAL_MEDIA_CTRL_PHY_CTRL_STRAP) >> 8;
7752 if (PCI_FUNC(bp->pdev->devfn) == 0) {
7757 bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
7765 bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
7771 static void __devinit
7772 bnx2_get_pci_speed(struct bnx2 *bp)
7776 reg = REG_RD(bp, BNX2_PCICFG_MISC_STATUS);
7777 if (reg & BNX2_PCICFG_MISC_STATUS_PCIX_DET) {
7780 bp->flags |= BNX2_FLAG_PCIX;
7782 clkreg = REG_RD(bp, BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS);
7784 clkreg &= BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET;
7786 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ:
7787 bp->bus_speed_mhz = 133;
7790 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ:
7791 bp->bus_speed_mhz = 100;
7794 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ:
7795 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ:
7796 bp->bus_speed_mhz = 66;
7799 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ:
7800 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ:
7801 bp->bus_speed_mhz = 50;
7804 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW:
7805 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ:
7806 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ:
7807 bp->bus_speed_mhz = 33;
7812 if (reg & BNX2_PCICFG_MISC_STATUS_M66EN)
7813 bp->bus_speed_mhz = 66;
7815 bp->bus_speed_mhz = 33;
7818 if (reg & BNX2_PCICFG_MISC_STATUS_32BIT_DET)
7819 bp->flags |= BNX2_FLAG_PCI_32BIT;
7823 static void __devinit
7824 bnx2_read_vpd_fw_ver(struct bnx2 *bp)
7828 unsigned int block_end, rosize, len;
7830 #define BNX2_VPD_NVRAM_OFFSET 0x300
7831 #define BNX2_VPD_LEN 128
7832 #define BNX2_MAX_VER_SLEN 30
7834 data = kmalloc(256, GFP_KERNEL);
7838 rc = bnx2_nvram_read(bp, BNX2_VPD_NVRAM_OFFSET, data + BNX2_VPD_LEN,
7843 for (i = 0; i < BNX2_VPD_LEN; i += 4) {
7844 data[i] = data[i + BNX2_VPD_LEN + 3];
7845 data[i + 1] = data[i + BNX2_VPD_LEN + 2];
7846 data[i + 2] = data[i + BNX2_VPD_LEN + 1];
7847 data[i + 3] = data[i + BNX2_VPD_LEN];
7850 i = pci_vpd_find_tag(data, 0, BNX2_VPD_LEN, PCI_VPD_LRDT_RO_DATA);
7854 rosize = pci_vpd_lrdt_size(&data[i]);
7855 i += PCI_VPD_LRDT_TAG_SIZE;
7856 block_end = i + rosize;
7858 if (block_end > BNX2_VPD_LEN)
7861 j = pci_vpd_find_info_keyword(data, i, rosize,
7862 PCI_VPD_RO_KEYWORD_MFR_ID);
7866 len = pci_vpd_info_field_size(&data[j]);
7868 j += PCI_VPD_INFO_FLD_HDR_SIZE;
7869 if (j + len > block_end || len != 4 ||
7870 memcmp(&data[j], "1028", 4))
7873 j = pci_vpd_find_info_keyword(data, i, rosize,
7874 PCI_VPD_RO_KEYWORD_VENDOR0);
7878 len = pci_vpd_info_field_size(&data[j]);
7880 j += PCI_VPD_INFO_FLD_HDR_SIZE;
7881 if (j + len > block_end || len > BNX2_MAX_VER_SLEN)
7884 memcpy(bp->fw_version, &data[j], len);
7885 bp->fw_version[len] = ' ';
7891 static int __devinit
7892 bnx2_init_board(struct pci_dev *pdev, struct net_device *dev)
7895 unsigned long mem_len;
7898 u64 dma_mask, persist_dma_mask;
7901 SET_NETDEV_DEV(dev, &pdev->dev);
7902 bp = netdev_priv(dev);
7907 bp->temp_stats_blk =
7908 kzalloc(sizeof(struct statistics_block), GFP_KERNEL);
7910 if (bp->temp_stats_blk == NULL) {
7915 /* enable device (incl. PCI PM wakeup), and bus-mastering */
7916 rc = pci_enable_device(pdev);
7918 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
7922 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
7924 "Cannot find PCI device base address, aborting\n");
7926 goto err_out_disable;
7929 rc = pci_request_regions(pdev, DRV_MODULE_NAME);
7931 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n");
7932 goto err_out_disable;
7935 pci_set_master(pdev);
7937 bp->pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
7938 if (bp->pm_cap == 0) {
7940 "Cannot find power management capability, aborting\n");
7942 goto err_out_release;
7948 spin_lock_init(&bp->phy_lock);
7949 spin_lock_init(&bp->indirect_lock);
7951 mutex_init(&bp->cnic_lock);
7953 INIT_WORK(&bp->reset_task, bnx2_reset_task);
7955 dev->base_addr = dev->mem_start = pci_resource_start(pdev, 0);
7956 mem_len = MB_GET_CID_ADDR(TX_TSS_CID + TX_MAX_TSS_RINGS + 1);
7957 dev->mem_end = dev->mem_start + mem_len;
7958 dev->irq = pdev->irq;
7960 bp->regview = ioremap_nocache(dev->base_addr, mem_len);
7963 dev_err(&pdev->dev, "Cannot map register space, aborting\n");
7965 goto err_out_release;
7968 bnx2_set_power_state(bp, PCI_D0);
7970 /* Configure byte swap and enable write to the reg_window registers.
7971 * Rely on CPU to do target byte swapping on big endian systems
7972 * The chip's target access swapping will not swap all accesses
7974 REG_WR(bp, BNX2_PCICFG_MISC_CONFIG,
7975 BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
7976 BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP);
7978 bp->chip_id = REG_RD(bp, BNX2_MISC_ID);
7980 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
7981 if (!pci_is_pcie(pdev)) {
7982 dev_err(&pdev->dev, "Not PCIE, aborting\n");
7986 bp->flags |= BNX2_FLAG_PCIE;
7987 if (CHIP_REV(bp) == CHIP_REV_Ax)
7988 bp->flags |= BNX2_FLAG_JUMBO_BROKEN;
7990 /* AER (Advanced Error Reporting) hooks */
7991 err = pci_enable_pcie_error_reporting(pdev);
7993 bp->flags |= BNX2_FLAG_AER_ENABLED;
7996 bp->pcix_cap = pci_find_capability(pdev, PCI_CAP_ID_PCIX);
7997 if (bp->pcix_cap == 0) {
7999 "Cannot find PCIX capability, aborting\n");
8003 bp->flags |= BNX2_FLAG_BROKEN_STATS;
8006 if (CHIP_NUM(bp) == CHIP_NUM_5709 && CHIP_REV(bp) != CHIP_REV_Ax) {
8007 if (pci_find_capability(pdev, PCI_CAP_ID_MSIX))
8008 bp->flags |= BNX2_FLAG_MSIX_CAP;
8011 if (CHIP_ID(bp) != CHIP_ID_5706_A0 && CHIP_ID(bp) != CHIP_ID_5706_A1) {
8012 if (pci_find_capability(pdev, PCI_CAP_ID_MSI))
8013 bp->flags |= BNX2_FLAG_MSI_CAP;
8016 /* 5708 cannot support DMA addresses > 40-bit. */
8017 if (CHIP_NUM(bp) == CHIP_NUM_5708)
8018 persist_dma_mask = dma_mask = DMA_BIT_MASK(40);
8020 persist_dma_mask = dma_mask = DMA_BIT_MASK(64);
8022 /* Configure DMA attributes. */
8023 if (pci_set_dma_mask(pdev, dma_mask) == 0) {
8024 dev->features |= NETIF_F_HIGHDMA;
8025 rc = pci_set_consistent_dma_mask(pdev, persist_dma_mask);
8028 "pci_set_consistent_dma_mask failed, aborting\n");
8031 } else if ((rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) != 0) {
8032 dev_err(&pdev->dev, "System does not support DMA, aborting\n");
8036 if (!(bp->flags & BNX2_FLAG_PCIE))
8037 bnx2_get_pci_speed(bp);
8039 /* 5706A0 may falsely detect SERR and PERR. */
8040 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
8041 reg = REG_RD(bp, PCI_COMMAND);
8042 reg &= ~(PCI_COMMAND_SERR | PCI_COMMAND_PARITY);
8043 REG_WR(bp, PCI_COMMAND, reg);
8045 else if ((CHIP_ID(bp) == CHIP_ID_5706_A1) &&
8046 !(bp->flags & BNX2_FLAG_PCIX)) {
8049 "5706 A1 can only be used in a PCIX bus, aborting\n");
8053 bnx2_init_nvram(bp);
8055 reg = bnx2_reg_rd_ind(bp, BNX2_SHM_HDR_SIGNATURE);
8057 if ((reg & BNX2_SHM_HDR_SIGNATURE_SIG_MASK) ==
8058 BNX2_SHM_HDR_SIGNATURE_SIG) {
8059 u32 off = PCI_FUNC(pdev->devfn) << 2;
8061 bp->shmem_base = bnx2_reg_rd_ind(bp, BNX2_SHM_HDR_ADDR_0 + off);
8063 bp->shmem_base = HOST_VIEW_SHMEM_BASE;
8065 /* Get the permanent MAC address. First we need to make sure the
8066 * firmware is actually running.
8068 reg = bnx2_shmem_rd(bp, BNX2_DEV_INFO_SIGNATURE);
8070 if ((reg & BNX2_DEV_INFO_SIGNATURE_MAGIC_MASK) !=
8071 BNX2_DEV_INFO_SIGNATURE_MAGIC) {
8072 dev_err(&pdev->dev, "Firmware not running, aborting\n");
8077 bnx2_read_vpd_fw_ver(bp);
8079 j = strlen(bp->fw_version);
8080 reg = bnx2_shmem_rd(bp, BNX2_DEV_INFO_BC_REV);
8081 for (i = 0; i < 3 && j < 24; i++) {
8085 bp->fw_version[j++] = 'b';
8086 bp->fw_version[j++] = 'c';
8087 bp->fw_version[j++] = ' ';
8089 num = (u8) (reg >> (24 - (i * 8)));
8090 for (k = 100, skip0 = 1; k >= 1; num %= k, k /= 10) {
8091 if (num >= k || !skip0 || k == 1) {
8092 bp->fw_version[j++] = (num / k) + '0';
8097 bp->fw_version[j++] = '.';
8099 reg = bnx2_shmem_rd(bp, BNX2_PORT_FEATURE);
8100 if (reg & BNX2_PORT_FEATURE_WOL_ENABLED)
8103 if (reg & BNX2_PORT_FEATURE_ASF_ENABLED) {
8104 bp->flags |= BNX2_FLAG_ASF_ENABLE;
8106 for (i = 0; i < 30; i++) {
8107 reg = bnx2_shmem_rd(bp, BNX2_BC_STATE_CONDITION);
8108 if (reg & BNX2_CONDITION_MFW_RUN_MASK)
8113 reg = bnx2_shmem_rd(bp, BNX2_BC_STATE_CONDITION);
8114 reg &= BNX2_CONDITION_MFW_RUN_MASK;
8115 if (reg != BNX2_CONDITION_MFW_RUN_UNKNOWN &&
8116 reg != BNX2_CONDITION_MFW_RUN_NONE) {
8117 u32 addr = bnx2_shmem_rd(bp, BNX2_MFW_VER_PTR);
8120 bp->fw_version[j++] = ' ';
8121 for (i = 0; i < 3 && j < 28; i++) {
8122 reg = bnx2_reg_rd_ind(bp, addr + i * 4);
8123 reg = be32_to_cpu(reg);
8124 memcpy(&bp->fw_version[j], ®, 4);
8129 reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_MAC_UPPER);
8130 bp->mac_addr[0] = (u8) (reg >> 8);
8131 bp->mac_addr[1] = (u8) reg;
8133 reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_MAC_LOWER);
8134 bp->mac_addr[2] = (u8) (reg >> 24);
8135 bp->mac_addr[3] = (u8) (reg >> 16);
8136 bp->mac_addr[4] = (u8) (reg >> 8);
8137 bp->mac_addr[5] = (u8) reg;
8139 bp->tx_ring_size = MAX_TX_DESC_CNT;
8140 bnx2_set_rx_ring_size(bp, 255);
8142 bp->tx_quick_cons_trip_int = 2;
8143 bp->tx_quick_cons_trip = 20;
8144 bp->tx_ticks_int = 18;
8147 bp->rx_quick_cons_trip_int = 2;
8148 bp->rx_quick_cons_trip = 12;
8149 bp->rx_ticks_int = 18;
8152 bp->stats_ticks = USEC_PER_SEC & BNX2_HC_STATS_TICKS_HC_STAT_TICKS;
8154 bp->current_interval = BNX2_TIMER_INTERVAL;
8158 /* Disable WOL support if we are running on a SERDES chip. */
8159 if (CHIP_NUM(bp) == CHIP_NUM_5709)
8160 bnx2_get_5709_media(bp);
8161 else if (CHIP_BOND_ID(bp) & CHIP_BOND_ID_SERDES_BIT)
8162 bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
8164 bp->phy_port = PORT_TP;
8165 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
8166 bp->phy_port = PORT_FIBRE;
8167 reg = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG);
8168 if (!(reg & BNX2_SHARED_HW_CFG_GIG_LINK_ON_VAUX)) {
8169 bp->flags |= BNX2_FLAG_NO_WOL;
8172 if (CHIP_NUM(bp) == CHIP_NUM_5706) {
8173 /* Don't do parallel detect on this board because of
8174 * some board problems. The link will not go down
8175 * if we do parallel detect.
8177 if (pdev->subsystem_vendor == PCI_VENDOR_ID_HP &&
8178 pdev->subsystem_device == 0x310c)
8179 bp->phy_flags |= BNX2_PHY_FLAG_NO_PARALLEL;
8182 if (reg & BNX2_SHARED_HW_CFG_PHY_2_5G)
8183 bp->phy_flags |= BNX2_PHY_FLAG_2_5G_CAPABLE;
8185 } else if (CHIP_NUM(bp) == CHIP_NUM_5706 ||
8186 CHIP_NUM(bp) == CHIP_NUM_5708)
8187 bp->phy_flags |= BNX2_PHY_FLAG_CRC_FIX;
8188 else if (CHIP_NUM(bp) == CHIP_NUM_5709 &&
8189 (CHIP_REV(bp) == CHIP_REV_Ax ||
8190 CHIP_REV(bp) == CHIP_REV_Bx))
8191 bp->phy_flags |= BNX2_PHY_FLAG_DIS_EARLY_DAC;
8193 bnx2_init_fw_cap(bp);
8195 if ((CHIP_ID(bp) == CHIP_ID_5708_A0) ||
8196 (CHIP_ID(bp) == CHIP_ID_5708_B0) ||
8197 (CHIP_ID(bp) == CHIP_ID_5708_B1) ||
8198 !(REG_RD(bp, BNX2_PCI_CONFIG_3) & BNX2_PCI_CONFIG_3_VAUX_PRESET)) {
8199 bp->flags |= BNX2_FLAG_NO_WOL;
8203 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
8204 bp->tx_quick_cons_trip_int =
8205 bp->tx_quick_cons_trip;
8206 bp->tx_ticks_int = bp->tx_ticks;
8207 bp->rx_quick_cons_trip_int =
8208 bp->rx_quick_cons_trip;
8209 bp->rx_ticks_int = bp->rx_ticks;
8210 bp->comp_prod_trip_int = bp->comp_prod_trip;
8211 bp->com_ticks_int = bp->com_ticks;
8212 bp->cmd_ticks_int = bp->cmd_ticks;
8215 /* Disable MSI on 5706 if AMD 8132 bridge is found.
8217 * MSI is defined to be 32-bit write. The 5706 does 64-bit MSI writes
8218 * with byte enables disabled on the unused 32-bit word. This is legal
8219 * but causes problems on the AMD 8132 which will eventually stop
8220 * responding after a while.
8222 * AMD believes this incompatibility is unique to the 5706, and
8223 * prefers to locally disable MSI rather than globally disabling it.
8225 if (CHIP_NUM(bp) == CHIP_NUM_5706 && disable_msi == 0) {
8226 struct pci_dev *amd_8132 = NULL;
8228 while ((amd_8132 = pci_get_device(PCI_VENDOR_ID_AMD,
8229 PCI_DEVICE_ID_AMD_8132_BRIDGE,
8232 if (amd_8132->revision >= 0x10 &&
8233 amd_8132->revision <= 0x13) {
8235 pci_dev_put(amd_8132);
8241 bnx2_set_default_link(bp);
8242 bp->req_flow_ctrl = FLOW_CTRL_RX | FLOW_CTRL_TX;
8244 init_timer(&bp->timer);
8245 bp->timer.expires = RUN_AT(BNX2_TIMER_INTERVAL);
8246 bp->timer.data = (unsigned long) bp;
8247 bp->timer.function = bnx2_timer;
8250 if (bnx2_shmem_rd(bp, BNX2_ISCSI_INITIATOR) & BNX2_ISCSI_INITIATOR_EN)
8251 bp->cnic_eth_dev.max_iscsi_conn =
8252 (bnx2_shmem_rd(bp, BNX2_ISCSI_MAX_CONN) &
8253 BNX2_ISCSI_MAX_CONN_MASK) >> BNX2_ISCSI_MAX_CONN_SHIFT;
8255 pci_save_state(pdev);
8260 if (bp->flags & BNX2_FLAG_AER_ENABLED) {
8261 pci_disable_pcie_error_reporting(pdev);
8262 bp->flags &= ~BNX2_FLAG_AER_ENABLED;
8266 iounmap(bp->regview);
8271 pci_release_regions(pdev);
8274 pci_disable_device(pdev);
8275 pci_set_drvdata(pdev, NULL);
8281 static char * __devinit
8282 bnx2_bus_string(struct bnx2 *bp, char *str)
8286 if (bp->flags & BNX2_FLAG_PCIE) {
8287 s += sprintf(s, "PCI Express");
8289 s += sprintf(s, "PCI");
8290 if (bp->flags & BNX2_FLAG_PCIX)
8291 s += sprintf(s, "-X");
8292 if (bp->flags & BNX2_FLAG_PCI_32BIT)
8293 s += sprintf(s, " 32-bit");
8295 s += sprintf(s, " 64-bit");
8296 s += sprintf(s, " %dMHz", bp->bus_speed_mhz);
8302 bnx2_del_napi(struct bnx2 *bp)
8306 for (i = 0; i < bp->irq_nvecs; i++)
8307 netif_napi_del(&bp->bnx2_napi[i].napi);
8311 bnx2_init_napi(struct bnx2 *bp)
8315 for (i = 0; i < bp->irq_nvecs; i++) {
8316 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
8317 int (*poll)(struct napi_struct *, int);
8322 poll = bnx2_poll_msix;
8324 netif_napi_add(bp->dev, &bp->bnx2_napi[i].napi, poll, 64);
8329 static const struct net_device_ops bnx2_netdev_ops = {
8330 .ndo_open = bnx2_open,
8331 .ndo_start_xmit = bnx2_start_xmit,
8332 .ndo_stop = bnx2_close,
8333 .ndo_get_stats64 = bnx2_get_stats64,
8334 .ndo_set_rx_mode = bnx2_set_rx_mode,
8335 .ndo_do_ioctl = bnx2_ioctl,
8336 .ndo_validate_addr = eth_validate_addr,
8337 .ndo_set_mac_address = bnx2_change_mac_addr,
8338 .ndo_change_mtu = bnx2_change_mtu,
8339 .ndo_fix_features = bnx2_fix_features,
8340 .ndo_set_features = bnx2_set_features,
8341 .ndo_tx_timeout = bnx2_tx_timeout,
8342 #ifdef CONFIG_NET_POLL_CONTROLLER
8343 .ndo_poll_controller = poll_bnx2,
8347 static int __devinit
8348 bnx2_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
8350 static int version_printed = 0;
8351 struct net_device *dev = NULL;
8356 if (version_printed++ == 0)
8357 pr_info("%s", version);
8359 /* dev zeroed in init_etherdev */
8360 dev = alloc_etherdev_mq(sizeof(*bp), TX_MAX_RINGS);
8365 rc = bnx2_init_board(pdev, dev);
8371 dev->netdev_ops = &bnx2_netdev_ops;
8372 dev->watchdog_timeo = TX_TIMEOUT;
8373 dev->ethtool_ops = &bnx2_ethtool_ops;
8375 bp = netdev_priv(dev);
8377 pci_set_drvdata(pdev, dev);
8379 memcpy(dev->dev_addr, bp->mac_addr, 6);
8380 memcpy(dev->perm_addr, bp->mac_addr, 6);
8382 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_SG |
8383 NETIF_F_TSO | NETIF_F_TSO_ECN |
8384 NETIF_F_RXHASH | NETIF_F_RXCSUM;
8386 if (CHIP_NUM(bp) == CHIP_NUM_5709)
8387 dev->hw_features |= NETIF_F_IPV6_CSUM | NETIF_F_TSO6;
8389 dev->vlan_features = dev->hw_features;
8390 dev->hw_features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
8391 dev->features |= dev->hw_features;
8392 dev->priv_flags |= IFF_UNICAST_FLT;
8394 if ((rc = register_netdev(dev))) {
8395 dev_err(&pdev->dev, "Cannot register net device\n");
8399 netdev_info(dev, "%s (%c%d) %s found at mem %lx, IRQ %d, node addr %pM\n",
8400 board_info[ent->driver_data].name,
8401 ((CHIP_ID(bp) & 0xf000) >> 12) + 'A',
8402 ((CHIP_ID(bp) & 0x0ff0) >> 4),
8403 bnx2_bus_string(bp, str),
8405 bp->pdev->irq, dev->dev_addr);
8411 iounmap(bp->regview);
8412 pci_release_regions(pdev);
8413 pci_disable_device(pdev);
8414 pci_set_drvdata(pdev, NULL);
8419 static void __devexit
8420 bnx2_remove_one(struct pci_dev *pdev)
8422 struct net_device *dev = pci_get_drvdata(pdev);
8423 struct bnx2 *bp = netdev_priv(dev);
8425 unregister_netdev(dev);
8427 del_timer_sync(&bp->timer);
8428 cancel_work_sync(&bp->reset_task);
8431 iounmap(bp->regview);
8433 kfree(bp->temp_stats_blk);
8435 if (bp->flags & BNX2_FLAG_AER_ENABLED) {
8436 pci_disable_pcie_error_reporting(pdev);
8437 bp->flags &= ~BNX2_FLAG_AER_ENABLED;
8440 bnx2_release_firmware(bp);
8444 pci_release_regions(pdev);
8445 pci_disable_device(pdev);
8446 pci_set_drvdata(pdev, NULL);
8450 bnx2_suspend(struct pci_dev *pdev, pm_message_t state)
8452 struct net_device *dev = pci_get_drvdata(pdev);
8453 struct bnx2 *bp = netdev_priv(dev);
8455 /* PCI register 4 needs to be saved whether netif_running() or not.
8456 * MSI address and data need to be saved if using MSI and
8459 pci_save_state(pdev);
8460 if (!netif_running(dev))
8463 cancel_work_sync(&bp->reset_task);
8464 bnx2_netif_stop(bp, true);
8465 netif_device_detach(dev);
8466 del_timer_sync(&bp->timer);
8467 bnx2_shutdown_chip(bp);
8469 bnx2_set_power_state(bp, pci_choose_state(pdev, state));
8474 bnx2_resume(struct pci_dev *pdev)
8476 struct net_device *dev = pci_get_drvdata(pdev);
8477 struct bnx2 *bp = netdev_priv(dev);
8479 pci_restore_state(pdev);
8480 if (!netif_running(dev))
8483 bnx2_set_power_state(bp, PCI_D0);
8484 netif_device_attach(dev);
8485 bnx2_init_nic(bp, 1);
8486 bnx2_netif_start(bp, true);
8491 * bnx2_io_error_detected - called when PCI error is detected
8492 * @pdev: Pointer to PCI device
8493 * @state: The current pci connection state
8495 * This function is called after a PCI bus error affecting
8496 * this device has been detected.
8498 static pci_ers_result_t bnx2_io_error_detected(struct pci_dev *pdev,
8499 pci_channel_state_t state)
8501 struct net_device *dev = pci_get_drvdata(pdev);
8502 struct bnx2 *bp = netdev_priv(dev);
8505 netif_device_detach(dev);
8507 if (state == pci_channel_io_perm_failure) {
8509 return PCI_ERS_RESULT_DISCONNECT;
8512 if (netif_running(dev)) {
8513 bnx2_netif_stop(bp, true);
8514 del_timer_sync(&bp->timer);
8515 bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET);
8518 pci_disable_device(pdev);
8521 /* Request a slot slot reset. */
8522 return PCI_ERS_RESULT_NEED_RESET;
8526 * bnx2_io_slot_reset - called after the pci bus has been reset.
8527 * @pdev: Pointer to PCI device
8529 * Restart the card from scratch, as if from a cold-boot.
8531 static pci_ers_result_t bnx2_io_slot_reset(struct pci_dev *pdev)
8533 struct net_device *dev = pci_get_drvdata(pdev);
8534 struct bnx2 *bp = netdev_priv(dev);
8535 pci_ers_result_t result;
8539 if (pci_enable_device(pdev)) {
8541 "Cannot re-enable PCI device after reset\n");
8542 result = PCI_ERS_RESULT_DISCONNECT;
8544 pci_set_master(pdev);
8545 pci_restore_state(pdev);
8546 pci_save_state(pdev);
8548 if (netif_running(dev)) {
8549 bnx2_set_power_state(bp, PCI_D0);
8550 bnx2_init_nic(bp, 1);
8552 result = PCI_ERS_RESULT_RECOVERED;
8556 if (!(bp->flags & BNX2_FLAG_AER_ENABLED))
8559 err = pci_cleanup_aer_uncorrect_error_status(pdev);
8562 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n",
8563 err); /* non-fatal, continue */
8570 * bnx2_io_resume - called when traffic can start flowing again.
8571 * @pdev: Pointer to PCI device
8573 * This callback is called when the error recovery driver tells us that
8574 * its OK to resume normal operation.
8576 static void bnx2_io_resume(struct pci_dev *pdev)
8578 struct net_device *dev = pci_get_drvdata(pdev);
8579 struct bnx2 *bp = netdev_priv(dev);
8582 if (netif_running(dev))
8583 bnx2_netif_start(bp, true);
8585 netif_device_attach(dev);
8589 static struct pci_error_handlers bnx2_err_handler = {
8590 .error_detected = bnx2_io_error_detected,
8591 .slot_reset = bnx2_io_slot_reset,
8592 .resume = bnx2_io_resume,
8595 static struct pci_driver bnx2_pci_driver = {
8596 .name = DRV_MODULE_NAME,
8597 .id_table = bnx2_pci_tbl,
8598 .probe = bnx2_init_one,
8599 .remove = __devexit_p(bnx2_remove_one),
8600 .suspend = bnx2_suspend,
8601 .resume = bnx2_resume,
8602 .err_handler = &bnx2_err_handler,
8605 static int __init bnx2_init(void)
8607 return pci_register_driver(&bnx2_pci_driver);
8610 static void __exit bnx2_cleanup(void)
8612 pci_unregister_driver(&bnx2_pci_driver);
8615 module_init(bnx2_init);
8616 module_exit(bnx2_cleanup);