2 * Broadcom BCM7xxx System Port Ethernet MAC driver
4 * Copyright (C) 2014 Broadcom Corporation
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
11 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
13 #include <linux/init.h>
14 #include <linux/interrupt.h>
15 #include <linux/module.h>
16 #include <linux/kernel.h>
17 #include <linux/netdevice.h>
18 #include <linux/etherdevice.h>
19 #include <linux/platform_device.h>
21 #include <linux/of_net.h>
22 #include <linux/of_mdio.h>
23 #include <linux/phy.h>
24 #include <linux/phy_fixed.h>
28 #include "bcmsysport.h"
30 /* I/O accessors register helpers */
31 #define BCM_SYSPORT_IO_MACRO(name, offset) \
32 static inline u32 name##_readl(struct bcm_sysport_priv *priv, u32 off) \
34 u32 reg = __raw_readl(priv->base + offset + off); \
37 static inline void name##_writel(struct bcm_sysport_priv *priv, \
40 __raw_writel(val, priv->base + offset + off); \
43 BCM_SYSPORT_IO_MACRO(intrl2_0, SYS_PORT_INTRL2_0_OFFSET);
44 BCM_SYSPORT_IO_MACRO(intrl2_1, SYS_PORT_INTRL2_1_OFFSET);
45 BCM_SYSPORT_IO_MACRO(umac, SYS_PORT_UMAC_OFFSET);
46 BCM_SYSPORT_IO_MACRO(tdma, SYS_PORT_TDMA_OFFSET);
47 BCM_SYSPORT_IO_MACRO(rdma, SYS_PORT_RDMA_OFFSET);
48 BCM_SYSPORT_IO_MACRO(rxchk, SYS_PORT_RXCHK_OFFSET);
49 BCM_SYSPORT_IO_MACRO(txchk, SYS_PORT_TXCHK_OFFSET);
50 BCM_SYSPORT_IO_MACRO(rbuf, SYS_PORT_RBUF_OFFSET);
51 BCM_SYSPORT_IO_MACRO(tbuf, SYS_PORT_TBUF_OFFSET);
52 BCM_SYSPORT_IO_MACRO(topctrl, SYS_PORT_TOPCTRL_OFFSET);
54 /* L2-interrupt masking/unmasking helpers, does automatic saving of the applied
55 * mask in a software copy to avoid CPU_MASK_STATUS reads in hot-paths.
57 #define BCM_SYSPORT_INTR_L2(which) \
58 static inline void intrl2_##which##_mask_clear(struct bcm_sysport_priv *priv, \
61 priv->irq##which##_mask &= ~(mask); \
62 intrl2_##which##_writel(priv, mask, INTRL2_CPU_MASK_CLEAR); \
64 static inline void intrl2_##which##_mask_set(struct bcm_sysport_priv *priv, \
67 intrl2_## which##_writel(priv, mask, INTRL2_CPU_MASK_SET); \
68 priv->irq##which##_mask |= (mask); \
71 BCM_SYSPORT_INTR_L2(0)
72 BCM_SYSPORT_INTR_L2(1)
74 /* Register accesses to GISB/RBUS registers are expensive (few hundred
75 * nanoseconds), so keep the check for 64-bits explicit here to save
76 * one register write per-packet on 32-bits platforms.
78 static inline void dma_desc_set_addr(struct bcm_sysport_priv *priv,
82 #ifdef CONFIG_PHYS_ADDR_T_64BIT
83 __raw_writel(upper_32_bits(addr) & DESC_ADDR_HI_MASK,
84 d + DESC_ADDR_HI_STATUS_LEN);
86 __raw_writel(lower_32_bits(addr), d + DESC_ADDR_LO);
89 static inline void tdma_port_write_desc_addr(struct bcm_sysport_priv *priv,
90 struct dma_desc *desc,
93 /* Ports are latched, so write upper address first */
94 tdma_writel(priv, desc->addr_status_len, TDMA_WRITE_PORT_HI(port));
95 tdma_writel(priv, desc->addr_lo, TDMA_WRITE_PORT_LO(port));
98 /* Ethtool operations */
99 static int bcm_sysport_set_rx_csum(struct net_device *dev,
100 netdev_features_t wanted)
102 struct bcm_sysport_priv *priv = netdev_priv(dev);
105 priv->rx_chk_en = !!(wanted & NETIF_F_RXCSUM);
106 reg = rxchk_readl(priv, RXCHK_CONTROL);
112 /* If UniMAC forwards CRC, we need to skip over it to get
113 * a valid CHK bit to be set in the per-packet status word
115 if (priv->rx_chk_en && priv->crc_fwd)
116 reg |= RXCHK_SKIP_FCS;
118 reg &= ~RXCHK_SKIP_FCS;
120 /* If Broadcom tags are enabled (e.g: using a switch), make
121 * sure we tell the RXCHK hardware to expect a 4-bytes Broadcom
122 * tag after the Ethernet MAC Source Address.
124 if (netdev_uses_dsa(dev))
125 reg |= RXCHK_BRCM_TAG_EN;
127 reg &= ~RXCHK_BRCM_TAG_EN;
129 rxchk_writel(priv, reg, RXCHK_CONTROL);
134 static int bcm_sysport_set_tx_csum(struct net_device *dev,
135 netdev_features_t wanted)
137 struct bcm_sysport_priv *priv = netdev_priv(dev);
140 /* Hardware transmit checksum requires us to enable the Transmit status
141 * block prepended to the packet contents
143 priv->tsb_en = !!(wanted & (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM));
144 reg = tdma_readl(priv, TDMA_CONTROL);
149 tdma_writel(priv, reg, TDMA_CONTROL);
154 static int bcm_sysport_set_features(struct net_device *dev,
155 netdev_features_t features)
157 netdev_features_t changed = features ^ dev->features;
158 netdev_features_t wanted = dev->wanted_features;
161 if (changed & NETIF_F_RXCSUM)
162 ret = bcm_sysport_set_rx_csum(dev, wanted);
163 if (changed & (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM))
164 ret = bcm_sysport_set_tx_csum(dev, wanted);
169 /* Hardware counters must be kept in sync because the order/offset
170 * is important here (order in structure declaration = order in hardware)
172 static const struct bcm_sysport_stats bcm_sysport_gstrings_stats[] = {
174 STAT_NETDEV(rx_packets),
175 STAT_NETDEV(tx_packets),
176 STAT_NETDEV(rx_bytes),
177 STAT_NETDEV(tx_bytes),
178 STAT_NETDEV(rx_errors),
179 STAT_NETDEV(tx_errors),
180 STAT_NETDEV(rx_dropped),
181 STAT_NETDEV(tx_dropped),
182 STAT_NETDEV(multicast),
183 /* UniMAC RSV counters */
184 STAT_MIB_RX("rx_64_octets", mib.rx.pkt_cnt.cnt_64),
185 STAT_MIB_RX("rx_65_127_oct", mib.rx.pkt_cnt.cnt_127),
186 STAT_MIB_RX("rx_128_255_oct", mib.rx.pkt_cnt.cnt_255),
187 STAT_MIB_RX("rx_256_511_oct", mib.rx.pkt_cnt.cnt_511),
188 STAT_MIB_RX("rx_512_1023_oct", mib.rx.pkt_cnt.cnt_1023),
189 STAT_MIB_RX("rx_1024_1518_oct", mib.rx.pkt_cnt.cnt_1518),
190 STAT_MIB_RX("rx_vlan_1519_1522_oct", mib.rx.pkt_cnt.cnt_mgv),
191 STAT_MIB_RX("rx_1522_2047_oct", mib.rx.pkt_cnt.cnt_2047),
192 STAT_MIB_RX("rx_2048_4095_oct", mib.rx.pkt_cnt.cnt_4095),
193 STAT_MIB_RX("rx_4096_9216_oct", mib.rx.pkt_cnt.cnt_9216),
194 STAT_MIB_RX("rx_pkts", mib.rx.pkt),
195 STAT_MIB_RX("rx_bytes", mib.rx.bytes),
196 STAT_MIB_RX("rx_multicast", mib.rx.mca),
197 STAT_MIB_RX("rx_broadcast", mib.rx.bca),
198 STAT_MIB_RX("rx_fcs", mib.rx.fcs),
199 STAT_MIB_RX("rx_control", mib.rx.cf),
200 STAT_MIB_RX("rx_pause", mib.rx.pf),
201 STAT_MIB_RX("rx_unknown", mib.rx.uo),
202 STAT_MIB_RX("rx_align", mib.rx.aln),
203 STAT_MIB_RX("rx_outrange", mib.rx.flr),
204 STAT_MIB_RX("rx_code", mib.rx.cde),
205 STAT_MIB_RX("rx_carrier", mib.rx.fcr),
206 STAT_MIB_RX("rx_oversize", mib.rx.ovr),
207 STAT_MIB_RX("rx_jabber", mib.rx.jbr),
208 STAT_MIB_RX("rx_mtu_err", mib.rx.mtue),
209 STAT_MIB_RX("rx_good_pkts", mib.rx.pok),
210 STAT_MIB_RX("rx_unicast", mib.rx.uc),
211 STAT_MIB_RX("rx_ppp", mib.rx.ppp),
212 STAT_MIB_RX("rx_crc", mib.rx.rcrc),
213 /* UniMAC TSV counters */
214 STAT_MIB_TX("tx_64_octets", mib.tx.pkt_cnt.cnt_64),
215 STAT_MIB_TX("tx_65_127_oct", mib.tx.pkt_cnt.cnt_127),
216 STAT_MIB_TX("tx_128_255_oct", mib.tx.pkt_cnt.cnt_255),
217 STAT_MIB_TX("tx_256_511_oct", mib.tx.pkt_cnt.cnt_511),
218 STAT_MIB_TX("tx_512_1023_oct", mib.tx.pkt_cnt.cnt_1023),
219 STAT_MIB_TX("tx_1024_1518_oct", mib.tx.pkt_cnt.cnt_1518),
220 STAT_MIB_TX("tx_vlan_1519_1522_oct", mib.tx.pkt_cnt.cnt_mgv),
221 STAT_MIB_TX("tx_1522_2047_oct", mib.tx.pkt_cnt.cnt_2047),
222 STAT_MIB_TX("tx_2048_4095_oct", mib.tx.pkt_cnt.cnt_4095),
223 STAT_MIB_TX("tx_4096_9216_oct", mib.tx.pkt_cnt.cnt_9216),
224 STAT_MIB_TX("tx_pkts", mib.tx.pkts),
225 STAT_MIB_TX("tx_multicast", mib.tx.mca),
226 STAT_MIB_TX("tx_broadcast", mib.tx.bca),
227 STAT_MIB_TX("tx_pause", mib.tx.pf),
228 STAT_MIB_TX("tx_control", mib.tx.cf),
229 STAT_MIB_TX("tx_fcs_err", mib.tx.fcs),
230 STAT_MIB_TX("tx_oversize", mib.tx.ovr),
231 STAT_MIB_TX("tx_defer", mib.tx.drf),
232 STAT_MIB_TX("tx_excess_defer", mib.tx.edf),
233 STAT_MIB_TX("tx_single_col", mib.tx.scl),
234 STAT_MIB_TX("tx_multi_col", mib.tx.mcl),
235 STAT_MIB_TX("tx_late_col", mib.tx.lcl),
236 STAT_MIB_TX("tx_excess_col", mib.tx.ecl),
237 STAT_MIB_TX("tx_frags", mib.tx.frg),
238 STAT_MIB_TX("tx_total_col", mib.tx.ncl),
239 STAT_MIB_TX("tx_jabber", mib.tx.jbr),
240 STAT_MIB_TX("tx_bytes", mib.tx.bytes),
241 STAT_MIB_TX("tx_good_pkts", mib.tx.pok),
242 STAT_MIB_TX("tx_unicast", mib.tx.uc),
243 /* UniMAC RUNT counters */
244 STAT_RUNT("rx_runt_pkts", mib.rx_runt_cnt),
245 STAT_RUNT("rx_runt_valid_fcs", mib.rx_runt_fcs),
246 STAT_RUNT("rx_runt_inval_fcs_align", mib.rx_runt_fcs_align),
247 STAT_RUNT("rx_runt_bytes", mib.rx_runt_bytes),
248 /* RXCHK misc statistics */
249 STAT_RXCHK("rxchk_bad_csum", mib.rxchk_bad_csum, RXCHK_BAD_CSUM_CNTR),
250 STAT_RXCHK("rxchk_other_pkt_disc", mib.rxchk_other_pkt_disc,
251 RXCHK_OTHER_DISC_CNTR),
252 /* RBUF misc statistics */
253 STAT_RBUF("rbuf_ovflow_cnt", mib.rbuf_ovflow_cnt, RBUF_OVFL_DISC_CNTR),
254 STAT_RBUF("rbuf_err_cnt", mib.rbuf_err_cnt, RBUF_ERR_PKT_CNTR),
255 STAT_MIB_SOFT("alloc_rx_buff_failed", mib.alloc_rx_buff_failed),
256 STAT_MIB_SOFT("rx_dma_failed", mib.rx_dma_failed),
257 STAT_MIB_SOFT("tx_dma_failed", mib.tx_dma_failed),
260 #define BCM_SYSPORT_STATS_LEN ARRAY_SIZE(bcm_sysport_gstrings_stats)
262 static void bcm_sysport_get_drvinfo(struct net_device *dev,
263 struct ethtool_drvinfo *info)
265 strlcpy(info->driver, KBUILD_MODNAME, sizeof(info->driver));
266 strlcpy(info->version, "0.1", sizeof(info->version));
267 strlcpy(info->bus_info, "platform", sizeof(info->bus_info));
270 static u32 bcm_sysport_get_msglvl(struct net_device *dev)
272 struct bcm_sysport_priv *priv = netdev_priv(dev);
274 return priv->msg_enable;
277 static void bcm_sysport_set_msglvl(struct net_device *dev, u32 enable)
279 struct bcm_sysport_priv *priv = netdev_priv(dev);
281 priv->msg_enable = enable;
284 static int bcm_sysport_get_sset_count(struct net_device *dev, int string_set)
286 switch (string_set) {
288 return BCM_SYSPORT_STATS_LEN;
294 static void bcm_sysport_get_strings(struct net_device *dev,
295 u32 stringset, u8 *data)
301 for (i = 0; i < BCM_SYSPORT_STATS_LEN; i++) {
302 memcpy(data + i * ETH_GSTRING_LEN,
303 bcm_sysport_gstrings_stats[i].stat_string,
312 static void bcm_sysport_update_mib_counters(struct bcm_sysport_priv *priv)
316 for (i = 0; i < BCM_SYSPORT_STATS_LEN; i++) {
317 const struct bcm_sysport_stats *s;
322 s = &bcm_sysport_gstrings_stats[i];
324 case BCM_SYSPORT_STAT_NETDEV:
325 case BCM_SYSPORT_STAT_SOFT:
327 case BCM_SYSPORT_STAT_MIB_RX:
328 case BCM_SYSPORT_STAT_MIB_TX:
329 case BCM_SYSPORT_STAT_RUNT:
330 if (s->type != BCM_SYSPORT_STAT_MIB_RX)
331 offset = UMAC_MIB_STAT_OFFSET;
332 val = umac_readl(priv, UMAC_MIB_START + j + offset);
334 case BCM_SYSPORT_STAT_RXCHK:
335 val = rxchk_readl(priv, s->reg_offset);
337 rxchk_writel(priv, 0, s->reg_offset);
339 case BCM_SYSPORT_STAT_RBUF:
340 val = rbuf_readl(priv, s->reg_offset);
342 rbuf_writel(priv, 0, s->reg_offset);
347 p = (char *)priv + s->stat_offset;
351 netif_dbg(priv, hw, priv->netdev, "updated MIB counters\n");
354 static void bcm_sysport_get_stats(struct net_device *dev,
355 struct ethtool_stats *stats, u64 *data)
357 struct bcm_sysport_priv *priv = netdev_priv(dev);
360 if (netif_running(dev))
361 bcm_sysport_update_mib_counters(priv);
363 for (i = 0; i < BCM_SYSPORT_STATS_LEN; i++) {
364 const struct bcm_sysport_stats *s;
367 s = &bcm_sysport_gstrings_stats[i];
368 if (s->type == BCM_SYSPORT_STAT_NETDEV)
369 p = (char *)&dev->stats;
373 data[i] = *(unsigned long *)p;
377 static void bcm_sysport_get_wol(struct net_device *dev,
378 struct ethtool_wolinfo *wol)
380 struct bcm_sysport_priv *priv = netdev_priv(dev);
383 wol->supported = WAKE_MAGIC | WAKE_MAGICSECURE;
384 wol->wolopts = priv->wolopts;
386 if (!(priv->wolopts & WAKE_MAGICSECURE))
389 /* Return the programmed SecureOn password */
390 reg = umac_readl(priv, UMAC_PSW_MS);
391 put_unaligned_be16(reg, &wol->sopass[0]);
392 reg = umac_readl(priv, UMAC_PSW_LS);
393 put_unaligned_be32(reg, &wol->sopass[2]);
396 static int bcm_sysport_set_wol(struct net_device *dev,
397 struct ethtool_wolinfo *wol)
399 struct bcm_sysport_priv *priv = netdev_priv(dev);
400 struct device *kdev = &priv->pdev->dev;
401 u32 supported = WAKE_MAGIC | WAKE_MAGICSECURE;
403 if (!device_can_wakeup(kdev))
406 if (wol->wolopts & ~supported)
409 /* Program the SecureOn password */
410 if (wol->wolopts & WAKE_MAGICSECURE) {
411 umac_writel(priv, get_unaligned_be16(&wol->sopass[0]),
413 umac_writel(priv, get_unaligned_be32(&wol->sopass[2]),
417 /* Flag the device and relevant IRQ as wakeup capable */
419 device_set_wakeup_enable(kdev, 1);
420 if (priv->wol_irq_disabled)
421 enable_irq_wake(priv->wol_irq);
422 priv->wol_irq_disabled = 0;
424 device_set_wakeup_enable(kdev, 0);
425 /* Avoid unbalanced disable_irq_wake calls */
426 if (!priv->wol_irq_disabled)
427 disable_irq_wake(priv->wol_irq);
428 priv->wol_irq_disabled = 1;
431 priv->wolopts = wol->wolopts;
436 static int bcm_sysport_get_coalesce(struct net_device *dev,
437 struct ethtool_coalesce *ec)
439 struct bcm_sysport_priv *priv = netdev_priv(dev);
442 reg = tdma_readl(priv, TDMA_DESC_RING_INTR_CONTROL(0));
444 ec->tx_coalesce_usecs = (reg >> RING_TIMEOUT_SHIFT) * 8192 / 1000;
445 ec->tx_max_coalesced_frames = reg & RING_INTR_THRESH_MASK;
447 reg = rdma_readl(priv, RDMA_MBDONE_INTR);
449 ec->rx_coalesce_usecs = (reg >> RDMA_TIMEOUT_SHIFT) * 8192 / 1000;
450 ec->rx_max_coalesced_frames = reg & RDMA_INTR_THRESH_MASK;
455 static int bcm_sysport_set_coalesce(struct net_device *dev,
456 struct ethtool_coalesce *ec)
458 struct bcm_sysport_priv *priv = netdev_priv(dev);
462 /* Base system clock is 125Mhz, DMA timeout is this reference clock
463 * divided by 1024, which yield roughly 8.192 us, our maximum value has
464 * to fit in the RING_TIMEOUT_MASK (16 bits).
466 if (ec->tx_max_coalesced_frames > RING_INTR_THRESH_MASK ||
467 ec->tx_coalesce_usecs > (RING_TIMEOUT_MASK * 8) + 1 ||
468 ec->rx_max_coalesced_frames > RDMA_INTR_THRESH_MASK ||
469 ec->rx_coalesce_usecs > (RDMA_TIMEOUT_MASK * 8) + 1)
472 if ((ec->tx_coalesce_usecs == 0 && ec->tx_max_coalesced_frames == 0) ||
473 (ec->rx_coalesce_usecs == 0 && ec->rx_max_coalesced_frames == 0))
476 for (i = 0; i < dev->num_tx_queues; i++) {
477 reg = tdma_readl(priv, TDMA_DESC_RING_INTR_CONTROL(i));
478 reg &= ~(RING_INTR_THRESH_MASK |
479 RING_TIMEOUT_MASK << RING_TIMEOUT_SHIFT);
480 reg |= ec->tx_max_coalesced_frames;
481 reg |= DIV_ROUND_UP(ec->tx_coalesce_usecs * 1000, 8192) <<
483 tdma_writel(priv, reg, TDMA_DESC_RING_INTR_CONTROL(i));
486 reg = rdma_readl(priv, RDMA_MBDONE_INTR);
487 reg &= ~(RDMA_INTR_THRESH_MASK |
488 RDMA_TIMEOUT_MASK << RDMA_TIMEOUT_SHIFT);
489 reg |= ec->rx_max_coalesced_frames;
490 reg |= DIV_ROUND_UP(ec->rx_coalesce_usecs * 1000, 8192) <<
492 rdma_writel(priv, reg, RDMA_MBDONE_INTR);
497 static void bcm_sysport_free_cb(struct bcm_sysport_cb *cb)
499 dev_kfree_skb_any(cb->skb);
501 dma_unmap_addr_set(cb, dma_addr, 0);
504 static struct sk_buff *bcm_sysport_rx_refill(struct bcm_sysport_priv *priv,
505 struct bcm_sysport_cb *cb)
507 struct device *kdev = &priv->pdev->dev;
508 struct net_device *ndev = priv->netdev;
509 struct sk_buff *skb, *rx_skb;
512 /* Allocate a new SKB for a new packet */
513 skb = netdev_alloc_skb(priv->netdev, RX_BUF_LENGTH);
515 priv->mib.alloc_rx_buff_failed++;
516 netif_err(priv, rx_err, ndev, "SKB alloc failed\n");
520 mapping = dma_map_single(kdev, skb->data,
521 RX_BUF_LENGTH, DMA_FROM_DEVICE);
522 if (dma_mapping_error(kdev, mapping)) {
523 priv->mib.rx_dma_failed++;
524 dev_kfree_skb_any(skb);
525 netif_err(priv, rx_err, ndev, "DMA mapping failure\n");
529 /* Grab the current SKB on the ring */
532 dma_unmap_single(kdev, dma_unmap_addr(cb, dma_addr),
533 RX_BUF_LENGTH, DMA_FROM_DEVICE);
535 /* Put the new SKB on the ring */
537 dma_unmap_addr_set(cb, dma_addr, mapping);
538 dma_desc_set_addr(priv, cb->bd_addr, mapping);
540 netif_dbg(priv, rx_status, ndev, "RX refill\n");
542 /* Return the current SKB to the caller */
546 static int bcm_sysport_alloc_rx_bufs(struct bcm_sysport_priv *priv)
548 struct bcm_sysport_cb *cb;
552 for (i = 0; i < priv->num_rx_bds; i++) {
553 cb = &priv->rx_cbs[i];
554 skb = bcm_sysport_rx_refill(priv, cb);
564 /* Poll the hardware for up to budget packets to process */
565 static unsigned int bcm_sysport_desc_rx(struct bcm_sysport_priv *priv,
568 struct net_device *ndev = priv->netdev;
569 unsigned int processed = 0, to_process;
570 struct bcm_sysport_cb *cb;
572 unsigned int p_index;
576 /* Determine how much we should process since last call */
577 p_index = rdma_readl(priv, RDMA_PROD_INDEX);
578 p_index &= RDMA_PROD_INDEX_MASK;
580 if (p_index < priv->rx_c_index)
581 to_process = (RDMA_CONS_INDEX_MASK + 1) -
582 priv->rx_c_index + p_index;
584 to_process = p_index - priv->rx_c_index;
586 netif_dbg(priv, rx_status, ndev,
587 "p_index=%d rx_c_index=%d to_process=%d\n",
588 p_index, priv->rx_c_index, to_process);
590 while ((processed < to_process) && (processed < budget)) {
591 cb = &priv->rx_cbs[priv->rx_read_ptr];
592 skb = bcm_sysport_rx_refill(priv, cb);
595 /* We do not have a backing SKB, so we do not a corresponding
596 * DMA mapping for this incoming packet since
597 * bcm_sysport_rx_refill always either has both skb and mapping
600 if (unlikely(!skb)) {
601 netif_err(priv, rx_err, ndev, "out of memory!\n");
602 ndev->stats.rx_dropped++;
603 ndev->stats.rx_errors++;
607 /* Extract the Receive Status Block prepended */
608 rsb = (struct bcm_rsb *)skb->data;
609 len = (rsb->rx_status_len >> DESC_LEN_SHIFT) & DESC_LEN_MASK;
610 status = (rsb->rx_status_len >> DESC_STATUS_SHIFT) &
613 netif_dbg(priv, rx_status, ndev,
614 "p=%d, c=%d, rd_ptr=%d, len=%d, flag=0x%04x\n",
615 p_index, priv->rx_c_index, priv->rx_read_ptr,
618 if (unlikely(len > RX_BUF_LENGTH)) {
619 netif_err(priv, rx_status, ndev, "oversized packet\n");
620 ndev->stats.rx_length_errors++;
621 ndev->stats.rx_errors++;
622 dev_kfree_skb_any(skb);
626 if (unlikely(!(status & DESC_EOP) || !(status & DESC_SOP))) {
627 netif_err(priv, rx_status, ndev, "fragmented packet!\n");
628 ndev->stats.rx_dropped++;
629 ndev->stats.rx_errors++;
630 dev_kfree_skb_any(skb);
634 if (unlikely(status & (RX_STATUS_ERR | RX_STATUS_OVFLOW))) {
635 netif_err(priv, rx_err, ndev, "error packet\n");
636 if (status & RX_STATUS_OVFLOW)
637 ndev->stats.rx_over_errors++;
638 ndev->stats.rx_dropped++;
639 ndev->stats.rx_errors++;
640 dev_kfree_skb_any(skb);
646 /* Hardware validated our checksum */
647 if (likely(status & DESC_L4_CSUM))
648 skb->ip_summed = CHECKSUM_UNNECESSARY;
650 /* Hardware pre-pends packets with 2bytes before Ethernet
651 * header plus we have the Receive Status Block, strip off all
652 * of this from the SKB.
654 skb_pull(skb, sizeof(*rsb) + 2);
655 len -= (sizeof(*rsb) + 2);
657 /* UniMAC may forward CRC */
659 skb_trim(skb, len - ETH_FCS_LEN);
663 skb->protocol = eth_type_trans(skb, ndev);
664 ndev->stats.rx_packets++;
665 ndev->stats.rx_bytes += len;
667 napi_gro_receive(&priv->napi, skb);
672 if (priv->rx_read_ptr == priv->num_rx_bds)
673 priv->rx_read_ptr = 0;
679 static void bcm_sysport_tx_reclaim_one(struct bcm_sysport_priv *priv,
680 struct bcm_sysport_cb *cb,
681 unsigned int *bytes_compl,
682 unsigned int *pkts_compl)
684 struct device *kdev = &priv->pdev->dev;
685 struct net_device *ndev = priv->netdev;
688 ndev->stats.tx_bytes += cb->skb->len;
689 *bytes_compl += cb->skb->len;
690 dma_unmap_single(kdev, dma_unmap_addr(cb, dma_addr),
691 dma_unmap_len(cb, dma_len),
693 ndev->stats.tx_packets++;
695 bcm_sysport_free_cb(cb);
697 } else if (dma_unmap_addr(cb, dma_addr)) {
698 ndev->stats.tx_bytes += dma_unmap_len(cb, dma_len);
699 dma_unmap_page(kdev, dma_unmap_addr(cb, dma_addr),
700 dma_unmap_len(cb, dma_len), DMA_TO_DEVICE);
701 dma_unmap_addr_set(cb, dma_addr, 0);
705 /* Reclaim queued SKBs for transmission completion, lockless version */
706 static unsigned int __bcm_sysport_tx_reclaim(struct bcm_sysport_priv *priv,
707 struct bcm_sysport_tx_ring *ring)
709 struct net_device *ndev = priv->netdev;
710 unsigned int c_index, last_c_index, last_tx_cn, num_tx_cbs;
711 unsigned int pkts_compl = 0, bytes_compl = 0;
712 struct bcm_sysport_cb *cb;
713 struct netdev_queue *txq;
716 txq = netdev_get_tx_queue(ndev, ring->index);
718 /* Compute how many descriptors have been processed since last call */
719 hw_ind = tdma_readl(priv, TDMA_DESC_RING_PROD_CONS_INDEX(ring->index));
720 c_index = (hw_ind >> RING_CONS_INDEX_SHIFT) & RING_CONS_INDEX_MASK;
721 ring->p_index = (hw_ind & RING_PROD_INDEX_MASK);
723 last_c_index = ring->c_index;
724 num_tx_cbs = ring->size;
726 c_index &= (num_tx_cbs - 1);
728 if (c_index >= last_c_index)
729 last_tx_cn = c_index - last_c_index;
731 last_tx_cn = num_tx_cbs - last_c_index + c_index;
733 netif_dbg(priv, tx_done, ndev,
734 "ring=%d c_index=%d last_tx_cn=%d last_c_index=%d\n",
735 ring->index, c_index, last_tx_cn, last_c_index);
737 while (last_tx_cn-- > 0) {
738 cb = ring->cbs + last_c_index;
739 bcm_sysport_tx_reclaim_one(priv, cb, &bytes_compl, &pkts_compl);
743 last_c_index &= (num_tx_cbs - 1);
746 ring->c_index = c_index;
748 if (netif_tx_queue_stopped(txq) && pkts_compl)
749 netif_tx_wake_queue(txq);
751 netif_dbg(priv, tx_done, ndev,
752 "ring=%d c_index=%d pkts_compl=%d, bytes_compl=%d\n",
753 ring->index, ring->c_index, pkts_compl, bytes_compl);
758 /* Locked version of the per-ring TX reclaim routine */
759 static unsigned int bcm_sysport_tx_reclaim(struct bcm_sysport_priv *priv,
760 struct bcm_sysport_tx_ring *ring)
762 unsigned int released;
765 spin_lock_irqsave(&ring->lock, flags);
766 released = __bcm_sysport_tx_reclaim(priv, ring);
767 spin_unlock_irqrestore(&ring->lock, flags);
772 static int bcm_sysport_tx_poll(struct napi_struct *napi, int budget)
774 struct bcm_sysport_tx_ring *ring =
775 container_of(napi, struct bcm_sysport_tx_ring, napi);
776 unsigned int work_done = 0;
778 work_done = bcm_sysport_tx_reclaim(ring->priv, ring);
780 if (work_done == 0) {
782 /* re-enable TX interrupt */
783 intrl2_1_mask_clear(ring->priv, BIT(ring->index));
791 static void bcm_sysport_tx_reclaim_all(struct bcm_sysport_priv *priv)
795 for (q = 0; q < priv->netdev->num_tx_queues; q++)
796 bcm_sysport_tx_reclaim(priv, &priv->tx_rings[q]);
799 static int bcm_sysport_poll(struct napi_struct *napi, int budget)
801 struct bcm_sysport_priv *priv =
802 container_of(napi, struct bcm_sysport_priv, napi);
803 unsigned int work_done = 0;
805 work_done = bcm_sysport_desc_rx(priv, budget);
807 priv->rx_c_index += work_done;
808 priv->rx_c_index &= RDMA_CONS_INDEX_MASK;
809 rdma_writel(priv, priv->rx_c_index, RDMA_CONS_INDEX);
811 if (work_done < budget) {
812 napi_complete_done(napi, work_done);
813 /* re-enable RX interrupts */
814 intrl2_0_mask_clear(priv, INTRL2_0_RDMA_MBDONE);
820 static void bcm_sysport_resume_from_wol(struct bcm_sysport_priv *priv)
824 /* Stop monitoring MPD interrupt */
825 intrl2_0_mask_set(priv, INTRL2_0_MPD);
827 /* Clear the MagicPacket detection logic */
828 reg = umac_readl(priv, UMAC_MPD_CTRL);
830 umac_writel(priv, reg, UMAC_MPD_CTRL);
832 netif_dbg(priv, wol, priv->netdev, "resumed from WOL\n");
835 /* RX and misc interrupt routine */
836 static irqreturn_t bcm_sysport_rx_isr(int irq, void *dev_id)
838 struct net_device *dev = dev_id;
839 struct bcm_sysport_priv *priv = netdev_priv(dev);
841 priv->irq0_stat = intrl2_0_readl(priv, INTRL2_CPU_STATUS) &
842 ~intrl2_0_readl(priv, INTRL2_CPU_MASK_STATUS);
843 intrl2_0_writel(priv, priv->irq0_stat, INTRL2_CPU_CLEAR);
845 if (unlikely(priv->irq0_stat == 0)) {
846 netdev_warn(priv->netdev, "spurious RX interrupt\n");
850 if (priv->irq0_stat & INTRL2_0_RDMA_MBDONE) {
851 if (likely(napi_schedule_prep(&priv->napi))) {
852 /* disable RX interrupts */
853 intrl2_0_mask_set(priv, INTRL2_0_RDMA_MBDONE);
854 __napi_schedule_irqoff(&priv->napi);
858 /* TX ring is full, perform a full reclaim since we do not know
859 * which one would trigger this interrupt
861 if (priv->irq0_stat & INTRL2_0_TX_RING_FULL)
862 bcm_sysport_tx_reclaim_all(priv);
864 if (priv->irq0_stat & INTRL2_0_MPD) {
865 netdev_info(priv->netdev, "Wake-on-LAN interrupt!\n");
866 bcm_sysport_resume_from_wol(priv);
872 /* TX interrupt service routine */
873 static irqreturn_t bcm_sysport_tx_isr(int irq, void *dev_id)
875 struct net_device *dev = dev_id;
876 struct bcm_sysport_priv *priv = netdev_priv(dev);
877 struct bcm_sysport_tx_ring *txr;
880 priv->irq1_stat = intrl2_1_readl(priv, INTRL2_CPU_STATUS) &
881 ~intrl2_1_readl(priv, INTRL2_CPU_MASK_STATUS);
882 intrl2_1_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR);
884 if (unlikely(priv->irq1_stat == 0)) {
885 netdev_warn(priv->netdev, "spurious TX interrupt\n");
889 for (ring = 0; ring < dev->num_tx_queues; ring++) {
890 if (!(priv->irq1_stat & BIT(ring)))
893 txr = &priv->tx_rings[ring];
895 if (likely(napi_schedule_prep(&txr->napi))) {
896 intrl2_1_mask_set(priv, BIT(ring));
897 __napi_schedule_irqoff(&txr->napi);
904 static irqreturn_t bcm_sysport_wol_isr(int irq, void *dev_id)
906 struct bcm_sysport_priv *priv = dev_id;
908 pm_wakeup_event(&priv->pdev->dev, 0);
913 #ifdef CONFIG_NET_POLL_CONTROLLER
914 static void bcm_sysport_poll_controller(struct net_device *dev)
916 struct bcm_sysport_priv *priv = netdev_priv(dev);
918 disable_irq(priv->irq0);
919 bcm_sysport_rx_isr(priv->irq0, priv);
920 enable_irq(priv->irq0);
922 disable_irq(priv->irq1);
923 bcm_sysport_tx_isr(priv->irq1, priv);
924 enable_irq(priv->irq1);
928 static struct sk_buff *bcm_sysport_insert_tsb(struct sk_buff *skb,
929 struct net_device *dev)
931 struct sk_buff *nskb;
938 /* Re-allocate SKB if needed */
939 if (unlikely(skb_headroom(skb) < sizeof(*tsb))) {
940 nskb = skb_realloc_headroom(skb, sizeof(*tsb));
943 dev->stats.tx_errors++;
944 dev->stats.tx_dropped++;
950 tsb = (struct bcm_tsb *)skb_push(skb, sizeof(*tsb));
951 /* Zero-out TSB by default */
952 memset(tsb, 0, sizeof(*tsb));
954 if (skb->ip_summed == CHECKSUM_PARTIAL) {
955 ip_ver = htons(skb->protocol);
958 ip_proto = ip_hdr(skb)->protocol;
961 ip_proto = ipv6_hdr(skb)->nexthdr;
967 /* Get the checksum offset and the L4 (transport) offset */
968 csum_start = skb_checksum_start_offset(skb) - sizeof(*tsb);
969 csum_info = (csum_start + skb->csum_offset) & L4_CSUM_PTR_MASK;
970 csum_info |= (csum_start << L4_PTR_SHIFT);
972 if (ip_proto == IPPROTO_TCP || ip_proto == IPPROTO_UDP) {
973 csum_info |= L4_LENGTH_VALID;
974 if (ip_proto == IPPROTO_UDP && ip_ver == ETH_P_IP)
980 tsb->l4_ptr_dest_map = csum_info;
986 static netdev_tx_t bcm_sysport_xmit(struct sk_buff *skb,
987 struct net_device *dev)
989 struct bcm_sysport_priv *priv = netdev_priv(dev);
990 struct device *kdev = &priv->pdev->dev;
991 struct bcm_sysport_tx_ring *ring;
992 struct bcm_sysport_cb *cb;
993 struct netdev_queue *txq;
994 struct dma_desc *desc;
995 unsigned int skb_len;
1002 queue = skb_get_queue_mapping(skb);
1003 txq = netdev_get_tx_queue(dev, queue);
1004 ring = &priv->tx_rings[queue];
1006 /* lock against tx reclaim in BH context and TX ring full interrupt */
1007 spin_lock_irqsave(&ring->lock, flags);
1008 if (unlikely(ring->desc_count == 0)) {
1009 netif_tx_stop_queue(txq);
1010 netdev_err(dev, "queue %d awake and ring full!\n", queue);
1011 ret = NETDEV_TX_BUSY;
1015 /* The Ethernet switch we are interfaced with needs packets to be at
1016 * least 64 bytes (including FCS) otherwise they will be discarded when
1017 * they enter the switch port logic. When Broadcom tags are enabled, we
1018 * need to make sure that packets are at least 68 bytes
1019 * (including FCS and tag) because the length verification is done after
1020 * the Broadcom tag is stripped off the ingress packet.
1022 if (skb_put_padto(skb, ETH_ZLEN + ENET_BRCM_TAG_LEN)) {
1027 /* Insert TSB and checksum infos */
1029 skb = bcm_sysport_insert_tsb(skb, dev);
1038 mapping = dma_map_single(kdev, skb->data, skb_len, DMA_TO_DEVICE);
1039 if (dma_mapping_error(kdev, mapping)) {
1040 priv->mib.tx_dma_failed++;
1041 netif_err(priv, tx_err, dev, "DMA map failed at %p (len=%d)\n",
1042 skb->data, skb_len);
1047 /* Remember the SKB for future freeing */
1048 cb = &ring->cbs[ring->curr_desc];
1050 dma_unmap_addr_set(cb, dma_addr, mapping);
1051 dma_unmap_len_set(cb, dma_len, skb_len);
1053 /* Fetch a descriptor entry from our pool */
1054 desc = ring->desc_cpu;
1056 desc->addr_lo = lower_32_bits(mapping);
1057 len_status = upper_32_bits(mapping) & DESC_ADDR_HI_MASK;
1058 len_status |= (skb_len << DESC_LEN_SHIFT);
1059 len_status |= (DESC_SOP | DESC_EOP | TX_STATUS_APP_CRC) <<
1061 if (skb->ip_summed == CHECKSUM_PARTIAL)
1062 len_status |= (DESC_L4_CSUM << DESC_STATUS_SHIFT);
1065 if (ring->curr_desc == ring->size)
1066 ring->curr_desc = 0;
1069 /* Ensure write completion of the descriptor status/length
1070 * in DRAM before the System Port WRITE_PORT register latches
1074 desc->addr_status_len = len_status;
1077 /* Write this descriptor address to the RING write port */
1078 tdma_port_write_desc_addr(priv, desc, ring->index);
1080 /* Check ring space and update SW control flow */
1081 if (ring->desc_count == 0)
1082 netif_tx_stop_queue(txq);
1084 netif_dbg(priv, tx_queued, dev, "ring=%d desc_count=%d, curr_desc=%d\n",
1085 ring->index, ring->desc_count, ring->curr_desc);
1089 spin_unlock_irqrestore(&ring->lock, flags);
1093 static void bcm_sysport_tx_timeout(struct net_device *dev)
1095 netdev_warn(dev, "transmit timeout!\n");
1097 netif_trans_update(dev);
1098 dev->stats.tx_errors++;
1100 netif_tx_wake_all_queues(dev);
1103 /* phylib adjust link callback */
1104 static void bcm_sysport_adj_link(struct net_device *dev)
1106 struct bcm_sysport_priv *priv = netdev_priv(dev);
1107 struct phy_device *phydev = dev->phydev;
1108 unsigned int changed = 0;
1109 u32 cmd_bits = 0, reg;
1111 if (priv->old_link != phydev->link) {
1113 priv->old_link = phydev->link;
1116 if (priv->old_duplex != phydev->duplex) {
1118 priv->old_duplex = phydev->duplex;
1121 switch (phydev->speed) {
1123 cmd_bits = CMD_SPEED_2500;
1126 cmd_bits = CMD_SPEED_1000;
1129 cmd_bits = CMD_SPEED_100;
1132 cmd_bits = CMD_SPEED_10;
1137 cmd_bits <<= CMD_SPEED_SHIFT;
1139 if (phydev->duplex == DUPLEX_HALF)
1140 cmd_bits |= CMD_HD_EN;
1142 if (priv->old_pause != phydev->pause) {
1144 priv->old_pause = phydev->pause;
1148 cmd_bits |= CMD_RX_PAUSE_IGNORE | CMD_TX_PAUSE_IGNORE;
1154 reg = umac_readl(priv, UMAC_CMD);
1155 reg &= ~((CMD_SPEED_MASK << CMD_SPEED_SHIFT) |
1156 CMD_HD_EN | CMD_RX_PAUSE_IGNORE |
1157 CMD_TX_PAUSE_IGNORE);
1159 umac_writel(priv, reg, UMAC_CMD);
1162 phy_print_status(phydev);
1165 static int bcm_sysport_init_tx_ring(struct bcm_sysport_priv *priv,
1168 struct bcm_sysport_tx_ring *ring = &priv->tx_rings[index];
1169 struct device *kdev = &priv->pdev->dev;
1174 /* Simple descriptors partitioning for now */
1177 /* We just need one DMA descriptor which is DMA-able, since writing to
1178 * the port will allocate a new descriptor in its internal linked-list
1180 p = dma_zalloc_coherent(kdev, sizeof(struct dma_desc), &ring->desc_dma,
1183 netif_err(priv, hw, priv->netdev, "DMA alloc failed\n");
1187 ring->cbs = kcalloc(size, sizeof(struct bcm_sysport_cb), GFP_KERNEL);
1189 netif_err(priv, hw, priv->netdev, "CB allocation failed\n");
1193 /* Initialize SW view of the ring */
1194 spin_lock_init(&ring->lock);
1196 netif_tx_napi_add(priv->netdev, &ring->napi, bcm_sysport_tx_poll, 64);
1197 ring->index = index;
1199 ring->alloc_size = ring->size;
1201 ring->desc_count = ring->size;
1202 ring->curr_desc = 0;
1204 /* Initialize HW ring */
1205 tdma_writel(priv, RING_EN, TDMA_DESC_RING_HEAD_TAIL_PTR(index));
1206 tdma_writel(priv, 0, TDMA_DESC_RING_COUNT(index));
1207 tdma_writel(priv, 1, TDMA_DESC_RING_INTR_CONTROL(index));
1208 tdma_writel(priv, 0, TDMA_DESC_RING_PROD_CONS_INDEX(index));
1209 tdma_writel(priv, RING_IGNORE_STATUS, TDMA_DESC_RING_MAPPING(index));
1210 tdma_writel(priv, 0, TDMA_DESC_RING_PCP_DEI_VID(index));
1212 /* Program the number of descriptors as MAX_THRESHOLD and half of
1213 * its size for the hysteresis trigger
1215 tdma_writel(priv, ring->size |
1216 1 << RING_HYST_THRESH_SHIFT,
1217 TDMA_DESC_RING_MAX_HYST(index));
1219 /* Enable the ring queue in the arbiter */
1220 reg = tdma_readl(priv, TDMA_TIER1_ARB_0_QUEUE_EN);
1221 reg |= (1 << index);
1222 tdma_writel(priv, reg, TDMA_TIER1_ARB_0_QUEUE_EN);
1224 napi_enable(&ring->napi);
1226 netif_dbg(priv, hw, priv->netdev,
1227 "TDMA cfg, size=%d, desc_cpu=%p\n",
1228 ring->size, ring->desc_cpu);
1233 static void bcm_sysport_fini_tx_ring(struct bcm_sysport_priv *priv,
1236 struct bcm_sysport_tx_ring *ring = &priv->tx_rings[index];
1237 struct device *kdev = &priv->pdev->dev;
1240 /* Caller should stop the TDMA engine */
1241 reg = tdma_readl(priv, TDMA_STATUS);
1242 if (!(reg & TDMA_DISABLED))
1243 netdev_warn(priv->netdev, "TDMA not stopped!\n");
1245 /* ring->cbs is the last part in bcm_sysport_init_tx_ring which could
1246 * fail, so by checking this pointer we know whether the TX ring was
1247 * fully initialized or not.
1252 napi_disable(&ring->napi);
1253 netif_napi_del(&ring->napi);
1255 bcm_sysport_tx_reclaim(priv, ring);
1260 if (ring->desc_dma) {
1261 dma_free_coherent(kdev, sizeof(struct dma_desc),
1262 ring->desc_cpu, ring->desc_dma);
1266 ring->alloc_size = 0;
1268 netif_dbg(priv, hw, priv->netdev, "TDMA fini done\n");
1272 static inline int rdma_enable_set(struct bcm_sysport_priv *priv,
1273 unsigned int enable)
1275 unsigned int timeout = 1000;
1278 reg = rdma_readl(priv, RDMA_CONTROL);
1283 rdma_writel(priv, reg, RDMA_CONTROL);
1285 /* Poll for RMDA disabling completion */
1287 reg = rdma_readl(priv, RDMA_STATUS);
1288 if (!!(reg & RDMA_DISABLED) == !enable)
1290 usleep_range(1000, 2000);
1291 } while (timeout-- > 0);
1293 netdev_err(priv->netdev, "timeout waiting for RDMA to finish\n");
1299 static inline int tdma_enable_set(struct bcm_sysport_priv *priv,
1300 unsigned int enable)
1302 unsigned int timeout = 1000;
1305 reg = tdma_readl(priv, TDMA_CONTROL);
1310 tdma_writel(priv, reg, TDMA_CONTROL);
1312 /* Poll for TMDA disabling completion */
1314 reg = tdma_readl(priv, TDMA_STATUS);
1315 if (!!(reg & TDMA_DISABLED) == !enable)
1318 usleep_range(1000, 2000);
1319 } while (timeout-- > 0);
1321 netdev_err(priv->netdev, "timeout waiting for TDMA to finish\n");
1326 static int bcm_sysport_init_rx_ring(struct bcm_sysport_priv *priv)
1328 struct bcm_sysport_cb *cb;
1333 /* Initialize SW view of the RX ring */
1334 priv->num_rx_bds = NUM_RX_DESC;
1335 priv->rx_bds = priv->base + SYS_PORT_RDMA_OFFSET;
1336 priv->rx_c_index = 0;
1337 priv->rx_read_ptr = 0;
1338 priv->rx_cbs = kcalloc(priv->num_rx_bds, sizeof(struct bcm_sysport_cb),
1340 if (!priv->rx_cbs) {
1341 netif_err(priv, hw, priv->netdev, "CB allocation failed\n");
1345 for (i = 0; i < priv->num_rx_bds; i++) {
1346 cb = priv->rx_cbs + i;
1347 cb->bd_addr = priv->rx_bds + i * DESC_SIZE;
1350 ret = bcm_sysport_alloc_rx_bufs(priv);
1352 netif_err(priv, hw, priv->netdev, "SKB allocation failed\n");
1356 /* Initialize HW, ensure RDMA is disabled */
1357 reg = rdma_readl(priv, RDMA_STATUS);
1358 if (!(reg & RDMA_DISABLED))
1359 rdma_enable_set(priv, 0);
1361 rdma_writel(priv, 0, RDMA_WRITE_PTR_LO);
1362 rdma_writel(priv, 0, RDMA_WRITE_PTR_HI);
1363 rdma_writel(priv, 0, RDMA_PROD_INDEX);
1364 rdma_writel(priv, 0, RDMA_CONS_INDEX);
1365 rdma_writel(priv, priv->num_rx_bds << RDMA_RING_SIZE_SHIFT |
1366 RX_BUF_LENGTH, RDMA_RING_BUF_SIZE);
1367 /* Operate the queue in ring mode */
1368 rdma_writel(priv, 0, RDMA_START_ADDR_HI);
1369 rdma_writel(priv, 0, RDMA_START_ADDR_LO);
1370 rdma_writel(priv, 0, RDMA_END_ADDR_HI);
1371 rdma_writel(priv, NUM_HW_RX_DESC_WORDS - 1, RDMA_END_ADDR_LO);
1373 rdma_writel(priv, 1, RDMA_MBDONE_INTR);
1375 netif_dbg(priv, hw, priv->netdev,
1376 "RDMA cfg, num_rx_bds=%d, rx_bds=%p\n",
1377 priv->num_rx_bds, priv->rx_bds);
1382 static void bcm_sysport_fini_rx_ring(struct bcm_sysport_priv *priv)
1384 struct bcm_sysport_cb *cb;
1388 /* Caller should ensure RDMA is disabled */
1389 reg = rdma_readl(priv, RDMA_STATUS);
1390 if (!(reg & RDMA_DISABLED))
1391 netdev_warn(priv->netdev, "RDMA not stopped!\n");
1393 for (i = 0; i < priv->num_rx_bds; i++) {
1394 cb = &priv->rx_cbs[i];
1395 if (dma_unmap_addr(cb, dma_addr))
1396 dma_unmap_single(&priv->pdev->dev,
1397 dma_unmap_addr(cb, dma_addr),
1398 RX_BUF_LENGTH, DMA_FROM_DEVICE);
1399 bcm_sysport_free_cb(cb);
1402 kfree(priv->rx_cbs);
1403 priv->rx_cbs = NULL;
1405 netif_dbg(priv, hw, priv->netdev, "RDMA fini done\n");
1408 static void bcm_sysport_set_rx_mode(struct net_device *dev)
1410 struct bcm_sysport_priv *priv = netdev_priv(dev);
1413 reg = umac_readl(priv, UMAC_CMD);
1414 if (dev->flags & IFF_PROMISC)
1417 reg &= ~CMD_PROMISC;
1418 umac_writel(priv, reg, UMAC_CMD);
1420 /* No support for ALLMULTI */
1421 if (dev->flags & IFF_ALLMULTI)
1425 static inline void umac_enable_set(struct bcm_sysport_priv *priv,
1426 u32 mask, unsigned int enable)
1430 reg = umac_readl(priv, UMAC_CMD);
1435 umac_writel(priv, reg, UMAC_CMD);
1437 /* UniMAC stops on a packet boundary, wait for a full-sized packet
1438 * to be processed (1 msec).
1441 usleep_range(1000, 2000);
1444 static inline void umac_reset(struct bcm_sysport_priv *priv)
1448 reg = umac_readl(priv, UMAC_CMD);
1449 reg |= CMD_SW_RESET;
1450 umac_writel(priv, reg, UMAC_CMD);
1452 reg = umac_readl(priv, UMAC_CMD);
1453 reg &= ~CMD_SW_RESET;
1454 umac_writel(priv, reg, UMAC_CMD);
1457 static void umac_set_hw_addr(struct bcm_sysport_priv *priv,
1458 unsigned char *addr)
1460 umac_writel(priv, (addr[0] << 24) | (addr[1] << 16) |
1461 (addr[2] << 8) | addr[3], UMAC_MAC0);
1462 umac_writel(priv, (addr[4] << 8) | addr[5], UMAC_MAC1);
1465 static void topctrl_flush(struct bcm_sysport_priv *priv)
1467 topctrl_writel(priv, RX_FLUSH, RX_FLUSH_CNTL);
1468 topctrl_writel(priv, TX_FLUSH, TX_FLUSH_CNTL);
1470 topctrl_writel(priv, 0, RX_FLUSH_CNTL);
1471 topctrl_writel(priv, 0, TX_FLUSH_CNTL);
1474 static int bcm_sysport_change_mac(struct net_device *dev, void *p)
1476 struct bcm_sysport_priv *priv = netdev_priv(dev);
1477 struct sockaddr *addr = p;
1479 if (!is_valid_ether_addr(addr->sa_data))
1482 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
1484 /* interface is disabled, changes to MAC will be reflected on next
1487 if (!netif_running(dev))
1490 umac_set_hw_addr(priv, dev->dev_addr);
1495 static void bcm_sysport_netif_start(struct net_device *dev)
1497 struct bcm_sysport_priv *priv = netdev_priv(dev);
1500 napi_enable(&priv->napi);
1502 /* Enable RX interrupt and TX ring full interrupt */
1503 intrl2_0_mask_clear(priv, INTRL2_0_RDMA_MBDONE | INTRL2_0_TX_RING_FULL);
1505 phy_start(dev->phydev);
1507 /* Enable TX interrupts for the 32 TXQs */
1508 intrl2_1_mask_clear(priv, 0xffffffff);
1510 /* Last call before we start the real business */
1511 netif_tx_start_all_queues(dev);
1514 static void rbuf_init(struct bcm_sysport_priv *priv)
1518 reg = rbuf_readl(priv, RBUF_CONTROL);
1519 reg |= RBUF_4B_ALGN | RBUF_RSB_EN;
1520 rbuf_writel(priv, reg, RBUF_CONTROL);
1523 static int bcm_sysport_open(struct net_device *dev)
1525 struct bcm_sysport_priv *priv = netdev_priv(dev);
1526 struct phy_device *phydev;
1533 /* Flush TX and RX FIFOs at TOPCTRL level */
1534 topctrl_flush(priv);
1536 /* Disable the UniMAC RX/TX */
1537 umac_enable_set(priv, CMD_RX_EN | CMD_TX_EN, 0);
1539 /* Enable RBUF 2bytes alignment and Receive Status Block */
1542 /* Set maximum frame length */
1543 umac_writel(priv, UMAC_MAX_MTU_SIZE, UMAC_MAX_FRAME_LEN);
1545 /* Set MAC address */
1546 umac_set_hw_addr(priv, dev->dev_addr);
1548 /* Read CRC forward */
1549 priv->crc_fwd = !!(umac_readl(priv, UMAC_CMD) & CMD_CRC_FWD);
1551 phydev = of_phy_connect(dev, priv->phy_dn, bcm_sysport_adj_link,
1552 0, priv->phy_interface);
1554 netdev_err(dev, "could not attach to PHY\n");
1558 /* Reset house keeping link status */
1559 priv->old_duplex = -1;
1560 priv->old_link = -1;
1561 priv->old_pause = -1;
1563 /* mask all interrupts and request them */
1564 intrl2_0_writel(priv, 0xffffffff, INTRL2_CPU_MASK_SET);
1565 intrl2_0_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR);
1566 intrl2_0_writel(priv, 0, INTRL2_CPU_MASK_CLEAR);
1567 intrl2_1_writel(priv, 0xffffffff, INTRL2_CPU_MASK_SET);
1568 intrl2_1_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR);
1569 intrl2_1_writel(priv, 0, INTRL2_CPU_MASK_CLEAR);
1571 ret = request_irq(priv->irq0, bcm_sysport_rx_isr, 0, dev->name, dev);
1573 netdev_err(dev, "failed to request RX interrupt\n");
1574 goto out_phy_disconnect;
1577 ret = request_irq(priv->irq1, bcm_sysport_tx_isr, 0, dev->name, dev);
1579 netdev_err(dev, "failed to request TX interrupt\n");
1583 /* Initialize both hardware and software ring */
1584 for (i = 0; i < dev->num_tx_queues; i++) {
1585 ret = bcm_sysport_init_tx_ring(priv, i);
1587 netdev_err(dev, "failed to initialize TX ring %d\n",
1589 goto out_free_tx_ring;
1593 /* Initialize linked-list */
1594 tdma_writel(priv, TDMA_LL_RAM_INIT_BUSY, TDMA_STATUS);
1596 /* Initialize RX ring */
1597 ret = bcm_sysport_init_rx_ring(priv);
1599 netdev_err(dev, "failed to initialize RX ring\n");
1600 goto out_free_rx_ring;
1604 ret = rdma_enable_set(priv, 1);
1606 goto out_free_rx_ring;
1609 ret = tdma_enable_set(priv, 1);
1611 goto out_clear_rx_int;
1613 /* Turn on UniMAC TX/RX */
1614 umac_enable_set(priv, CMD_RX_EN | CMD_TX_EN, 1);
1616 bcm_sysport_netif_start(dev);
1621 intrl2_0_mask_set(priv, INTRL2_0_RDMA_MBDONE | INTRL2_0_TX_RING_FULL);
1623 bcm_sysport_fini_rx_ring(priv);
1625 for (i = 0; i < dev->num_tx_queues; i++)
1626 bcm_sysport_fini_tx_ring(priv, i);
1627 free_irq(priv->irq1, dev);
1629 free_irq(priv->irq0, dev);
1631 phy_disconnect(phydev);
1635 static void bcm_sysport_netif_stop(struct net_device *dev)
1637 struct bcm_sysport_priv *priv = netdev_priv(dev);
1639 /* stop all software from updating hardware */
1640 netif_tx_stop_all_queues(dev);
1641 napi_disable(&priv->napi);
1642 phy_stop(dev->phydev);
1644 /* mask all interrupts */
1645 intrl2_0_mask_set(priv, 0xffffffff);
1646 intrl2_0_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR);
1647 intrl2_1_mask_set(priv, 0xffffffff);
1648 intrl2_1_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR);
1651 static int bcm_sysport_stop(struct net_device *dev)
1653 struct bcm_sysport_priv *priv = netdev_priv(dev);
1657 bcm_sysport_netif_stop(dev);
1659 /* Disable UniMAC RX */
1660 umac_enable_set(priv, CMD_RX_EN, 0);
1662 ret = tdma_enable_set(priv, 0);
1664 netdev_err(dev, "timeout disabling RDMA\n");
1668 /* Wait for a maximum packet size to be drained */
1669 usleep_range(2000, 3000);
1671 ret = rdma_enable_set(priv, 0);
1673 netdev_err(dev, "timeout disabling TDMA\n");
1677 /* Disable UniMAC TX */
1678 umac_enable_set(priv, CMD_TX_EN, 0);
1680 /* Free RX/TX rings SW structures */
1681 for (i = 0; i < dev->num_tx_queues; i++)
1682 bcm_sysport_fini_tx_ring(priv, i);
1683 bcm_sysport_fini_rx_ring(priv);
1685 free_irq(priv->irq0, dev);
1686 free_irq(priv->irq1, dev);
1688 /* Disconnect from PHY */
1689 phy_disconnect(dev->phydev);
1694 static const struct ethtool_ops bcm_sysport_ethtool_ops = {
1695 .get_drvinfo = bcm_sysport_get_drvinfo,
1696 .get_msglevel = bcm_sysport_get_msglvl,
1697 .set_msglevel = bcm_sysport_set_msglvl,
1698 .get_link = ethtool_op_get_link,
1699 .get_strings = bcm_sysport_get_strings,
1700 .get_ethtool_stats = bcm_sysport_get_stats,
1701 .get_sset_count = bcm_sysport_get_sset_count,
1702 .get_wol = bcm_sysport_get_wol,
1703 .set_wol = bcm_sysport_set_wol,
1704 .get_coalesce = bcm_sysport_get_coalesce,
1705 .set_coalesce = bcm_sysport_set_coalesce,
1706 .get_link_ksettings = phy_ethtool_get_link_ksettings,
1707 .set_link_ksettings = phy_ethtool_set_link_ksettings,
1710 static const struct net_device_ops bcm_sysport_netdev_ops = {
1711 .ndo_start_xmit = bcm_sysport_xmit,
1712 .ndo_tx_timeout = bcm_sysport_tx_timeout,
1713 .ndo_open = bcm_sysport_open,
1714 .ndo_stop = bcm_sysport_stop,
1715 .ndo_set_features = bcm_sysport_set_features,
1716 .ndo_set_rx_mode = bcm_sysport_set_rx_mode,
1717 .ndo_set_mac_address = bcm_sysport_change_mac,
1718 #ifdef CONFIG_NET_POLL_CONTROLLER
1719 .ndo_poll_controller = bcm_sysport_poll_controller,
1723 #define REV_FMT "v%2x.%02x"
1725 static int bcm_sysport_probe(struct platform_device *pdev)
1727 struct bcm_sysport_priv *priv;
1728 struct device_node *dn;
1729 struct net_device *dev;
1730 const void *macaddr;
1735 dn = pdev->dev.of_node;
1736 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1738 /* Read the Transmit/Receive Queue properties */
1739 if (of_property_read_u32(dn, "systemport,num-txq", &txq))
1740 txq = TDMA_NUM_RINGS;
1741 if (of_property_read_u32(dn, "systemport,num-rxq", &rxq))
1744 dev = alloc_etherdev_mqs(sizeof(*priv), txq, rxq);
1748 /* Initialize private members */
1749 priv = netdev_priv(dev);
1751 priv->irq0 = platform_get_irq(pdev, 0);
1752 priv->irq1 = platform_get_irq(pdev, 1);
1753 priv->wol_irq = platform_get_irq(pdev, 2);
1754 if (priv->irq0 <= 0 || priv->irq1 <= 0) {
1755 dev_err(&pdev->dev, "invalid interrupts\n");
1757 goto err_free_netdev;
1760 priv->base = devm_ioremap_resource(&pdev->dev, r);
1761 if (IS_ERR(priv->base)) {
1762 ret = PTR_ERR(priv->base);
1763 goto err_free_netdev;
1769 priv->phy_interface = of_get_phy_mode(dn);
1770 /* Default to GMII interface mode */
1771 if (priv->phy_interface < 0)
1772 priv->phy_interface = PHY_INTERFACE_MODE_GMII;
1774 /* In the case of a fixed PHY, the DT node associated
1775 * to the PHY is the Ethernet MAC DT node.
1777 if (of_phy_is_fixed_link(dn)) {
1778 ret = of_phy_register_fixed_link(dn);
1780 dev_err(&pdev->dev, "failed to register fixed PHY\n");
1781 goto err_free_netdev;
1787 /* Initialize netdevice members */
1788 macaddr = of_get_mac_address(dn);
1789 if (!macaddr || !is_valid_ether_addr(macaddr)) {
1790 dev_warn(&pdev->dev, "using random Ethernet MAC\n");
1791 eth_hw_addr_random(dev);
1793 ether_addr_copy(dev->dev_addr, macaddr);
1796 SET_NETDEV_DEV(dev, &pdev->dev);
1797 dev_set_drvdata(&pdev->dev, dev);
1798 dev->ethtool_ops = &bcm_sysport_ethtool_ops;
1799 dev->netdev_ops = &bcm_sysport_netdev_ops;
1800 netif_napi_add(dev, &priv->napi, bcm_sysport_poll, 64);
1802 /* HW supported features, none enabled by default */
1803 dev->hw_features |= NETIF_F_RXCSUM | NETIF_F_HIGHDMA |
1804 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
1806 /* Request the WOL interrupt and advertise suspend if available */
1807 priv->wol_irq_disabled = 1;
1808 ret = devm_request_irq(&pdev->dev, priv->wol_irq,
1809 bcm_sysport_wol_isr, 0, dev->name, priv);
1811 device_set_wakeup_capable(&pdev->dev, 1);
1813 /* Set the needed headroom once and for all */
1814 BUILD_BUG_ON(sizeof(struct bcm_tsb) != 8);
1815 dev->needed_headroom += sizeof(struct bcm_tsb);
1817 /* libphy will adjust the link state accordingly */
1818 netif_carrier_off(dev);
1820 ret = register_netdev(dev);
1822 dev_err(&pdev->dev, "failed to register net_device\n");
1823 goto err_deregister_fixed_link;
1826 priv->rev = topctrl_readl(priv, REV_CNTL) & REV_MASK;
1827 dev_info(&pdev->dev,
1828 "Broadcom SYSTEMPORT" REV_FMT
1829 " at 0x%p (irqs: %d, %d, TXQs: %d, RXQs: %d)\n",
1830 (priv->rev >> 8) & 0xff, priv->rev & 0xff,
1831 priv->base, priv->irq0, priv->irq1, txq, rxq);
1835 err_deregister_fixed_link:
1836 if (of_phy_is_fixed_link(dn))
1837 of_phy_deregister_fixed_link(dn);
1843 static int bcm_sysport_remove(struct platform_device *pdev)
1845 struct net_device *dev = dev_get_drvdata(&pdev->dev);
1846 struct device_node *dn = pdev->dev.of_node;
1848 /* Not much to do, ndo_close has been called
1849 * and we use managed allocations
1851 unregister_netdev(dev);
1852 if (of_phy_is_fixed_link(dn))
1853 of_phy_deregister_fixed_link(dn);
1855 dev_set_drvdata(&pdev->dev, NULL);
1860 #ifdef CONFIG_PM_SLEEP
1861 static int bcm_sysport_suspend_to_wol(struct bcm_sysport_priv *priv)
1863 struct net_device *ndev = priv->netdev;
1864 unsigned int timeout = 1000;
1867 /* Password has already been programmed */
1868 reg = umac_readl(priv, UMAC_MPD_CTRL);
1871 if (priv->wolopts & WAKE_MAGICSECURE)
1873 umac_writel(priv, reg, UMAC_MPD_CTRL);
1875 /* Make sure RBUF entered WoL mode as result */
1877 reg = rbuf_readl(priv, RBUF_STATUS);
1878 if (reg & RBUF_WOL_MODE)
1882 } while (timeout-- > 0);
1884 /* Do not leave the UniMAC RBUF matching only MPD packets */
1886 reg = umac_readl(priv, UMAC_MPD_CTRL);
1888 umac_writel(priv, reg, UMAC_MPD_CTRL);
1889 netif_err(priv, wol, ndev, "failed to enter WOL mode\n");
1893 /* UniMAC receive needs to be turned on */
1894 umac_enable_set(priv, CMD_RX_EN, 1);
1896 /* Enable the interrupt wake-up source */
1897 intrl2_0_mask_clear(priv, INTRL2_0_MPD);
1899 netif_dbg(priv, wol, ndev, "entered WOL mode\n");
1904 static int bcm_sysport_suspend(struct device *d)
1906 struct net_device *dev = dev_get_drvdata(d);
1907 struct bcm_sysport_priv *priv = netdev_priv(dev);
1912 if (!netif_running(dev))
1915 bcm_sysport_netif_stop(dev);
1917 phy_suspend(dev->phydev);
1919 netif_device_detach(dev);
1921 /* Disable UniMAC RX */
1922 umac_enable_set(priv, CMD_RX_EN, 0);
1924 ret = rdma_enable_set(priv, 0);
1926 netdev_err(dev, "RDMA timeout!\n");
1930 /* Disable RXCHK if enabled */
1931 if (priv->rx_chk_en) {
1932 reg = rxchk_readl(priv, RXCHK_CONTROL);
1934 rxchk_writel(priv, reg, RXCHK_CONTROL);
1939 topctrl_writel(priv, RX_FLUSH, RX_FLUSH_CNTL);
1941 ret = tdma_enable_set(priv, 0);
1943 netdev_err(dev, "TDMA timeout!\n");
1947 /* Wait for a packet boundary */
1948 usleep_range(2000, 3000);
1950 umac_enable_set(priv, CMD_TX_EN, 0);
1952 topctrl_writel(priv, TX_FLUSH, TX_FLUSH_CNTL);
1954 /* Free RX/TX rings SW structures */
1955 for (i = 0; i < dev->num_tx_queues; i++)
1956 bcm_sysport_fini_tx_ring(priv, i);
1957 bcm_sysport_fini_rx_ring(priv);
1959 /* Get prepared for Wake-on-LAN */
1960 if (device_may_wakeup(d) && priv->wolopts)
1961 ret = bcm_sysport_suspend_to_wol(priv);
1966 static int bcm_sysport_resume(struct device *d)
1968 struct net_device *dev = dev_get_drvdata(d);
1969 struct bcm_sysport_priv *priv = netdev_priv(dev);
1974 if (!netif_running(dev))
1979 /* We may have been suspended and never received a WOL event that
1980 * would turn off MPD detection, take care of that now
1982 bcm_sysport_resume_from_wol(priv);
1984 /* Initialize both hardware and software ring */
1985 for (i = 0; i < dev->num_tx_queues; i++) {
1986 ret = bcm_sysport_init_tx_ring(priv, i);
1988 netdev_err(dev, "failed to initialize TX ring %d\n",
1990 goto out_free_tx_rings;
1994 /* Initialize linked-list */
1995 tdma_writel(priv, TDMA_LL_RAM_INIT_BUSY, TDMA_STATUS);
1997 /* Initialize RX ring */
1998 ret = bcm_sysport_init_rx_ring(priv);
2000 netdev_err(dev, "failed to initialize RX ring\n");
2001 goto out_free_rx_ring;
2004 netif_device_attach(dev);
2006 /* RX pipe enable */
2007 topctrl_writel(priv, 0, RX_FLUSH_CNTL);
2009 ret = rdma_enable_set(priv, 1);
2011 netdev_err(dev, "failed to enable RDMA\n");
2012 goto out_free_rx_ring;
2016 if (priv->rx_chk_en) {
2017 reg = rxchk_readl(priv, RXCHK_CONTROL);
2019 rxchk_writel(priv, reg, RXCHK_CONTROL);
2024 /* Set maximum frame length */
2025 umac_writel(priv, UMAC_MAX_MTU_SIZE, UMAC_MAX_FRAME_LEN);
2027 /* Set MAC address */
2028 umac_set_hw_addr(priv, dev->dev_addr);
2030 umac_enable_set(priv, CMD_RX_EN, 1);
2032 /* TX pipe enable */
2033 topctrl_writel(priv, 0, TX_FLUSH_CNTL);
2035 umac_enable_set(priv, CMD_TX_EN, 1);
2037 ret = tdma_enable_set(priv, 1);
2039 netdev_err(dev, "TDMA timeout!\n");
2040 goto out_free_rx_ring;
2043 phy_resume(dev->phydev);
2045 bcm_sysport_netif_start(dev);
2050 bcm_sysport_fini_rx_ring(priv);
2052 for (i = 0; i < dev->num_tx_queues; i++)
2053 bcm_sysport_fini_tx_ring(priv, i);
2058 static SIMPLE_DEV_PM_OPS(bcm_sysport_pm_ops,
2059 bcm_sysport_suspend, bcm_sysport_resume);
2061 static const struct of_device_id bcm_sysport_of_match[] = {
2062 { .compatible = "brcm,systemport-v1.00" },
2063 { .compatible = "brcm,systemport" },
2066 MODULE_DEVICE_TABLE(of, bcm_sysport_of_match);
2068 static struct platform_driver bcm_sysport_driver = {
2069 .probe = bcm_sysport_probe,
2070 .remove = bcm_sysport_remove,
2072 .name = "brcm-systemport",
2073 .of_match_table = bcm_sysport_of_match,
2074 .pm = &bcm_sysport_pm_ops,
2077 module_platform_driver(bcm_sysport_driver);
2079 MODULE_AUTHOR("Broadcom Corporation");
2080 MODULE_DESCRIPTION("Broadcom System Port Ethernet MAC driver");
2081 MODULE_ALIAS("platform:brcm-systemport");
2082 MODULE_LICENSE("GPL");