2 * Copyright (c) 2013 Johannes Berg <johannes@sipsolutions.net>
4 * This file is free software: you may copy, redistribute and/or modify it
5 * under the terms of the GNU General Public License as published by the
6 * Free Software Foundation, either version 2 of the License, or (at your
7 * option) any later version.
9 * This file is distributed in the hope that it will be useful, but
10 * WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
12 * General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program. If not, see <http://www.gnu.org/licenses/>.
17 * This file incorporates work covered by the following copyright and
20 * Copyright (c) 2012 Qualcomm Atheros, Inc.
22 * Permission to use, copy, modify, and/or distribute this software for any
23 * purpose with or without fee is hereby granted, provided that the above
24 * copyright notice and this permission notice appear in all copies.
26 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
27 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
28 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
29 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
30 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
31 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
32 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
35 #include <linux/module.h>
36 #include <linux/pci.h>
37 #include <linux/interrupt.h>
39 #include <linux/ipv6.h>
40 #include <linux/if_vlan.h>
41 #include <linux/mdio.h>
42 #include <linux/aer.h>
43 #include <linux/bitops.h>
44 #include <linux/netdevice.h>
45 #include <linux/etherdevice.h>
46 #include <net/ip6_checksum.h>
47 #include <linux/crc32.h>
52 const char alx_drv_name[] = "alx";
55 static void alx_free_txbuf(struct alx_priv *alx, int entry)
57 struct alx_buffer *txb = &alx->txq.bufs[entry];
59 if (dma_unmap_len(txb, size)) {
60 dma_unmap_single(&alx->hw.pdev->dev,
61 dma_unmap_addr(txb, dma),
62 dma_unmap_len(txb, size),
64 dma_unmap_len_set(txb, size, 0);
68 dev_kfree_skb_any(txb->skb);
73 static int alx_refill_rx_ring(struct alx_priv *alx, gfp_t gfp)
75 struct alx_rx_queue *rxq = &alx->rxq;
77 struct alx_buffer *cur_buf;
79 u16 cur, next, count = 0;
81 next = cur = rxq->write_idx;
82 if (++next == alx->rx_ringsz)
84 cur_buf = &rxq->bufs[cur];
86 while (!cur_buf->skb && next != rxq->read_idx) {
87 struct alx_rfd *rfd = &rxq->rfd[cur];
90 * When DMA RX address is set to something like
91 * 0x....fc0, it will be very likely to cause DMA
94 * To work around it, we apply rx skb with 64 bytes
95 * longer space, and offset the address whenever
96 * 0x....fc0 is detected.
98 skb = __netdev_alloc_skb(alx->dev, alx->rxbuf_size + 64, gfp);
102 if (((unsigned long)skb->data & 0xfff) == 0xfc0)
103 skb_reserve(skb, 64);
105 dma = dma_map_single(&alx->hw.pdev->dev,
106 skb->data, alx->rxbuf_size,
108 if (dma_mapping_error(&alx->hw.pdev->dev, dma)) {
113 /* Unfortunately, RX descriptor buffers must be 4-byte
114 * aligned, so we can't use IP alignment.
116 if (WARN_ON(dma & 3)) {
122 dma_unmap_len_set(cur_buf, size, alx->rxbuf_size);
123 dma_unmap_addr_set(cur_buf, dma, dma);
124 rfd->addr = cpu_to_le64(dma);
127 if (++next == alx->rx_ringsz)
129 cur_buf = &rxq->bufs[cur];
134 /* flush all updates before updating hardware */
136 rxq->write_idx = cur;
137 alx_write_mem16(&alx->hw, ALX_RFD_PIDX, cur);
143 static inline int alx_tpd_avail(struct alx_priv *alx)
145 struct alx_tx_queue *txq = &alx->txq;
147 if (txq->write_idx >= txq->read_idx)
148 return alx->tx_ringsz + txq->read_idx - txq->write_idx - 1;
149 return txq->read_idx - txq->write_idx - 1;
152 static bool alx_clean_tx_irq(struct alx_priv *alx)
154 struct alx_tx_queue *txq = &alx->txq;
155 u16 hw_read_idx, sw_read_idx;
156 unsigned int total_bytes = 0, total_packets = 0;
157 int budget = ALX_DEFAULT_TX_WORK;
159 sw_read_idx = txq->read_idx;
160 hw_read_idx = alx_read_mem16(&alx->hw, ALX_TPD_PRI0_CIDX);
162 if (sw_read_idx != hw_read_idx) {
163 while (sw_read_idx != hw_read_idx && budget > 0) {
166 skb = txq->bufs[sw_read_idx].skb;
168 total_bytes += skb->len;
173 alx_free_txbuf(alx, sw_read_idx);
175 if (++sw_read_idx == alx->tx_ringsz)
178 txq->read_idx = sw_read_idx;
180 netdev_completed_queue(alx->dev, total_packets, total_bytes);
183 if (netif_queue_stopped(alx->dev) && netif_carrier_ok(alx->dev) &&
184 alx_tpd_avail(alx) > alx->tx_ringsz/4)
185 netif_wake_queue(alx->dev);
187 return sw_read_idx == hw_read_idx;
190 static void alx_schedule_link_check(struct alx_priv *alx)
192 schedule_work(&alx->link_check_wk);
195 static void alx_schedule_reset(struct alx_priv *alx)
197 schedule_work(&alx->reset_wk);
200 static int alx_clean_rx_irq(struct alx_priv *alx, int budget)
202 struct alx_rx_queue *rxq = &alx->rxq;
204 struct alx_buffer *rxb;
206 u16 length, rfd_cleaned = 0;
209 while (work < budget) {
210 rrd = &rxq->rrd[rxq->rrd_read_idx];
211 if (!(rrd->word3 & cpu_to_le32(1 << RRD_UPDATED_SHIFT)))
213 rrd->word3 &= ~cpu_to_le32(1 << RRD_UPDATED_SHIFT);
215 if (ALX_GET_FIELD(le32_to_cpu(rrd->word0),
216 RRD_SI) != rxq->read_idx ||
217 ALX_GET_FIELD(le32_to_cpu(rrd->word0),
219 alx_schedule_reset(alx);
223 rxb = &rxq->bufs[rxq->read_idx];
224 dma_unmap_single(&alx->hw.pdev->dev,
225 dma_unmap_addr(rxb, dma),
226 dma_unmap_len(rxb, size),
228 dma_unmap_len_set(rxb, size, 0);
232 if (rrd->word3 & cpu_to_le32(1 << RRD_ERR_RES_SHIFT) ||
233 rrd->word3 & cpu_to_le32(1 << RRD_ERR_LEN_SHIFT)) {
235 dev_kfree_skb_any(skb);
239 length = ALX_GET_FIELD(le32_to_cpu(rrd->word3),
240 RRD_PKTLEN) - ETH_FCS_LEN;
241 skb_put(skb, length);
242 skb->protocol = eth_type_trans(skb, alx->dev);
244 skb_checksum_none_assert(skb);
245 if (alx->dev->features & NETIF_F_RXCSUM &&
246 !(rrd->word3 & (cpu_to_le32(1 << RRD_ERR_L4_SHIFT) |
247 cpu_to_le32(1 << RRD_ERR_IPV4_SHIFT)))) {
248 switch (ALX_GET_FIELD(le32_to_cpu(rrd->word2),
250 case RRD_PID_IPV6UDP:
251 case RRD_PID_IPV4UDP:
252 case RRD_PID_IPV4TCP:
253 case RRD_PID_IPV6TCP:
254 skb->ip_summed = CHECKSUM_UNNECESSARY;
259 napi_gro_receive(&alx->napi, skb);
263 if (++rxq->read_idx == alx->rx_ringsz)
265 if (++rxq->rrd_read_idx == alx->rx_ringsz)
266 rxq->rrd_read_idx = 0;
268 if (++rfd_cleaned > ALX_RX_ALLOC_THRESH)
269 rfd_cleaned -= alx_refill_rx_ring(alx, GFP_ATOMIC);
273 alx_refill_rx_ring(alx, GFP_ATOMIC);
278 static int alx_poll(struct napi_struct *napi, int budget)
280 struct alx_priv *alx = container_of(napi, struct alx_priv, napi);
281 struct alx_hw *hw = &alx->hw;
286 tx_complete = alx_clean_tx_irq(alx);
287 work = alx_clean_rx_irq(alx, budget);
289 if (!tx_complete || work == budget)
292 napi_complete(&alx->napi);
294 /* enable interrupt */
295 spin_lock_irqsave(&alx->irq_lock, flags);
296 alx->int_mask |= ALX_ISR_TX_Q0 | ALX_ISR_RX_Q0;
297 alx_write_mem32(hw, ALX_IMR, alx->int_mask);
298 spin_unlock_irqrestore(&alx->irq_lock, flags);
305 static irqreturn_t alx_intr_handle(struct alx_priv *alx, u32 intr)
307 struct alx_hw *hw = &alx->hw;
308 bool write_int_mask = false;
310 spin_lock(&alx->irq_lock);
313 alx_write_mem32(hw, ALX_ISR, intr | ALX_ISR_DIS);
314 intr &= alx->int_mask;
316 if (intr & ALX_ISR_FATAL) {
317 netif_warn(alx, hw, alx->dev,
318 "fatal interrupt 0x%x, resetting\n", intr);
319 alx_schedule_reset(alx);
323 if (intr & ALX_ISR_ALERT)
324 netdev_warn(alx->dev, "alert interrupt: 0x%x\n", intr);
326 if (intr & ALX_ISR_PHY) {
327 /* suppress PHY interrupt, because the source
328 * is from PHY internal. only the internal status
329 * is cleared, the interrupt status could be cleared.
331 alx->int_mask &= ~ALX_ISR_PHY;
332 write_int_mask = true;
333 alx_schedule_link_check(alx);
336 if (intr & (ALX_ISR_TX_Q0 | ALX_ISR_RX_Q0)) {
337 napi_schedule(&alx->napi);
338 /* mask rx/tx interrupt, enable them when napi complete */
339 alx->int_mask &= ~ALX_ISR_ALL_QUEUES;
340 write_int_mask = true;
344 alx_write_mem32(hw, ALX_IMR, alx->int_mask);
346 alx_write_mem32(hw, ALX_ISR, 0);
349 spin_unlock(&alx->irq_lock);
353 static irqreturn_t alx_intr_msi(int irq, void *data)
355 struct alx_priv *alx = data;
357 return alx_intr_handle(alx, alx_read_mem32(&alx->hw, ALX_ISR));
360 static irqreturn_t alx_intr_legacy(int irq, void *data)
362 struct alx_priv *alx = data;
363 struct alx_hw *hw = &alx->hw;
366 intr = alx_read_mem32(hw, ALX_ISR);
368 if (intr & ALX_ISR_DIS || !(intr & alx->int_mask))
371 return alx_intr_handle(alx, intr);
374 static void alx_init_ring_ptrs(struct alx_priv *alx)
376 struct alx_hw *hw = &alx->hw;
377 u32 addr_hi = ((u64)alx->descmem.dma) >> 32;
379 alx->rxq.read_idx = 0;
380 alx->rxq.write_idx = 0;
381 alx->rxq.rrd_read_idx = 0;
382 alx_write_mem32(hw, ALX_RX_BASE_ADDR_HI, addr_hi);
383 alx_write_mem32(hw, ALX_RRD_ADDR_LO, alx->rxq.rrd_dma);
384 alx_write_mem32(hw, ALX_RRD_RING_SZ, alx->rx_ringsz);
385 alx_write_mem32(hw, ALX_RFD_ADDR_LO, alx->rxq.rfd_dma);
386 alx_write_mem32(hw, ALX_RFD_RING_SZ, alx->rx_ringsz);
387 alx_write_mem32(hw, ALX_RFD_BUF_SZ, alx->rxbuf_size);
389 alx->txq.read_idx = 0;
390 alx->txq.write_idx = 0;
391 alx_write_mem32(hw, ALX_TX_BASE_ADDR_HI, addr_hi);
392 alx_write_mem32(hw, ALX_TPD_PRI0_ADDR_LO, alx->txq.tpd_dma);
393 alx_write_mem32(hw, ALX_TPD_RING_SZ, alx->tx_ringsz);
395 /* load these pointers into the chip */
396 alx_write_mem32(hw, ALX_SRAM9, ALX_SRAM_LOAD_PTR);
399 static void alx_free_txring_buf(struct alx_priv *alx)
401 struct alx_tx_queue *txq = &alx->txq;
407 for (i = 0; i < alx->tx_ringsz; i++)
408 alx_free_txbuf(alx, i);
410 memset(txq->bufs, 0, alx->tx_ringsz * sizeof(struct alx_buffer));
411 memset(txq->tpd, 0, alx->tx_ringsz * sizeof(struct alx_txd));
415 netdev_reset_queue(alx->dev);
418 static void alx_free_rxring_buf(struct alx_priv *alx)
420 struct alx_rx_queue *rxq = &alx->rxq;
421 struct alx_buffer *cur_buf;
427 for (i = 0; i < alx->rx_ringsz; i++) {
428 cur_buf = rxq->bufs + i;
430 dma_unmap_single(&alx->hw.pdev->dev,
431 dma_unmap_addr(cur_buf, dma),
432 dma_unmap_len(cur_buf, size),
434 dev_kfree_skb(cur_buf->skb);
436 dma_unmap_len_set(cur_buf, size, 0);
437 dma_unmap_addr_set(cur_buf, dma, 0);
443 rxq->rrd_read_idx = 0;
446 static void alx_free_buffers(struct alx_priv *alx)
448 alx_free_txring_buf(alx);
449 alx_free_rxring_buf(alx);
452 static int alx_reinit_rings(struct alx_priv *alx)
454 alx_free_buffers(alx);
456 alx_init_ring_ptrs(alx);
458 if (!alx_refill_rx_ring(alx, GFP_KERNEL))
464 static void alx_add_mc_addr(struct alx_hw *hw, const u8 *addr, u32 *mc_hash)
468 crc32 = ether_crc(ETH_ALEN, addr);
469 reg = (crc32 >> 31) & 0x1;
470 bit = (crc32 >> 26) & 0x1F;
472 mc_hash[reg] |= BIT(bit);
475 static void __alx_set_rx_mode(struct net_device *netdev)
477 struct alx_priv *alx = netdev_priv(netdev);
478 struct alx_hw *hw = &alx->hw;
479 struct netdev_hw_addr *ha;
482 if (!(netdev->flags & IFF_ALLMULTI)) {
483 netdev_for_each_mc_addr(ha, netdev)
484 alx_add_mc_addr(hw, ha->addr, mc_hash);
486 alx_write_mem32(hw, ALX_HASH_TBL0, mc_hash[0]);
487 alx_write_mem32(hw, ALX_HASH_TBL1, mc_hash[1]);
490 hw->rx_ctrl &= ~(ALX_MAC_CTRL_MULTIALL_EN | ALX_MAC_CTRL_PROMISC_EN);
491 if (netdev->flags & IFF_PROMISC)
492 hw->rx_ctrl |= ALX_MAC_CTRL_PROMISC_EN;
493 if (netdev->flags & IFF_ALLMULTI)
494 hw->rx_ctrl |= ALX_MAC_CTRL_MULTIALL_EN;
496 alx_write_mem32(hw, ALX_MAC_CTRL, hw->rx_ctrl);
499 static void alx_set_rx_mode(struct net_device *netdev)
501 __alx_set_rx_mode(netdev);
504 static int alx_set_mac_address(struct net_device *netdev, void *data)
506 struct alx_priv *alx = netdev_priv(netdev);
507 struct alx_hw *hw = &alx->hw;
508 struct sockaddr *addr = data;
510 if (!is_valid_ether_addr(addr->sa_data))
511 return -EADDRNOTAVAIL;
513 if (netdev->addr_assign_type & NET_ADDR_RANDOM)
514 netdev->addr_assign_type ^= NET_ADDR_RANDOM;
516 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
517 memcpy(hw->mac_addr, addr->sa_data, netdev->addr_len);
518 alx_set_macaddr(hw, hw->mac_addr);
523 static int alx_alloc_descriptors(struct alx_priv *alx)
525 alx->txq.bufs = kcalloc(alx->tx_ringsz,
526 sizeof(struct alx_buffer),
531 alx->rxq.bufs = kcalloc(alx->rx_ringsz,
532 sizeof(struct alx_buffer),
537 /* physical tx/rx ring descriptors
539 * Allocate them as a single chunk because they must not cross a
540 * 4G boundary (hardware has a single register for high 32 bits
543 alx->descmem.size = sizeof(struct alx_txd) * alx->tx_ringsz +
544 sizeof(struct alx_rrd) * alx->rx_ringsz +
545 sizeof(struct alx_rfd) * alx->rx_ringsz;
546 alx->descmem.virt = dma_zalloc_coherent(&alx->hw.pdev->dev,
550 if (!alx->descmem.virt)
553 alx->txq.tpd = alx->descmem.virt;
554 alx->txq.tpd_dma = alx->descmem.dma;
556 /* alignment requirement for next block */
557 BUILD_BUG_ON(sizeof(struct alx_txd) % 8);
560 (void *)((u8 *)alx->descmem.virt +
561 sizeof(struct alx_txd) * alx->tx_ringsz);
562 alx->rxq.rrd_dma = alx->descmem.dma +
563 sizeof(struct alx_txd) * alx->tx_ringsz;
565 /* alignment requirement for next block */
566 BUILD_BUG_ON(sizeof(struct alx_rrd) % 8);
569 (void *)((u8 *)alx->descmem.virt +
570 sizeof(struct alx_txd) * alx->tx_ringsz +
571 sizeof(struct alx_rrd) * alx->rx_ringsz);
572 alx->rxq.rfd_dma = alx->descmem.dma +
573 sizeof(struct alx_txd) * alx->tx_ringsz +
574 sizeof(struct alx_rrd) * alx->rx_ringsz;
578 kfree(alx->txq.bufs);
579 kfree(alx->rxq.bufs);
583 static int alx_alloc_rings(struct alx_priv *alx)
587 err = alx_alloc_descriptors(alx);
591 alx->int_mask &= ~ALX_ISR_ALL_QUEUES;
592 alx->int_mask |= ALX_ISR_TX_Q0 | ALX_ISR_RX_Q0;
594 netif_napi_add(alx->dev, &alx->napi, alx_poll, 64);
596 alx_reinit_rings(alx);
600 static void alx_free_rings(struct alx_priv *alx)
602 netif_napi_del(&alx->napi);
603 alx_free_buffers(alx);
605 kfree(alx->txq.bufs);
606 kfree(alx->rxq.bufs);
608 dma_free_coherent(&alx->hw.pdev->dev,
614 static void alx_config_vector_mapping(struct alx_priv *alx)
616 struct alx_hw *hw = &alx->hw;
618 alx_write_mem32(hw, ALX_MSI_MAP_TBL1, 0);
619 alx_write_mem32(hw, ALX_MSI_MAP_TBL2, 0);
620 alx_write_mem32(hw, ALX_MSI_ID_MAP, 0);
623 static void alx_irq_enable(struct alx_priv *alx)
625 struct alx_hw *hw = &alx->hw;
627 /* level-1 interrupt switch */
628 alx_write_mem32(hw, ALX_ISR, 0);
629 alx_write_mem32(hw, ALX_IMR, alx->int_mask);
633 static void alx_irq_disable(struct alx_priv *alx)
635 struct alx_hw *hw = &alx->hw;
637 alx_write_mem32(hw, ALX_ISR, ALX_ISR_DIS);
638 alx_write_mem32(hw, ALX_IMR, 0);
641 synchronize_irq(alx->hw.pdev->irq);
644 static int alx_request_irq(struct alx_priv *alx)
646 struct pci_dev *pdev = alx->hw.pdev;
647 struct alx_hw *hw = &alx->hw;
651 msi_ctrl = (hw->imt >> 1) << ALX_MSI_RETRANS_TM_SHIFT;
653 if (!pci_enable_msi(alx->hw.pdev)) {
656 alx_write_mem32(hw, ALX_MSI_RETRANS_TIMER,
657 msi_ctrl | ALX_MSI_MASK_SEL_LINE);
658 err = request_irq(pdev->irq, alx_intr_msi, 0,
659 alx->dev->name, alx);
662 /* fall back to legacy interrupt */
663 pci_disable_msi(alx->hw.pdev);
666 alx_write_mem32(hw, ALX_MSI_RETRANS_TIMER, 0);
667 err = request_irq(pdev->irq, alx_intr_legacy, IRQF_SHARED,
668 alx->dev->name, alx);
671 alx_config_vector_mapping(alx);
675 static void alx_free_irq(struct alx_priv *alx)
677 struct pci_dev *pdev = alx->hw.pdev;
679 free_irq(pdev->irq, alx);
682 pci_disable_msi(alx->hw.pdev);
687 static int alx_identify_hw(struct alx_priv *alx)
689 struct alx_hw *hw = &alx->hw;
690 int rev = alx_hw_revision(hw);
692 if (rev > ALX_REV_C0)
695 hw->max_dma_chnl = rev >= ALX_REV_B0 ? 4 : 2;
700 static int alx_init_sw(struct alx_priv *alx)
702 struct pci_dev *pdev = alx->hw.pdev;
703 struct alx_hw *hw = &alx->hw;
706 err = alx_identify_hw(alx);
708 dev_err(&pdev->dev, "unrecognized chip, aborting\n");
713 pdev->device == ALX_DEV_ID_AR8161 &&
714 pdev->subsystem_vendor == PCI_VENDOR_ID_ATTANSIC &&
715 pdev->subsystem_device == 0x0091 &&
719 hw->mtu = alx->dev->mtu;
720 alx->rxbuf_size = ALX_MAX_FRAME_LEN(hw->mtu);
721 alx->tx_ringsz = 256;
722 alx->rx_ringsz = 512;
724 alx->int_mask = ALX_ISR_MISC;
725 hw->dma_chnl = hw->max_dma_chnl;
726 hw->ith_tpd = alx->tx_ringsz / 3;
727 hw->link_speed = SPEED_UNKNOWN;
728 hw->duplex = DUPLEX_UNKNOWN;
729 hw->adv_cfg = ADVERTISED_Autoneg |
730 ADVERTISED_10baseT_Half |
731 ADVERTISED_10baseT_Full |
732 ADVERTISED_100baseT_Full |
733 ADVERTISED_100baseT_Half |
734 ADVERTISED_1000baseT_Full;
735 hw->flowctrl = ALX_FC_ANEG | ALX_FC_RX | ALX_FC_TX;
737 hw->rx_ctrl = ALX_MAC_CTRL_WOLSPED_SWEN |
738 ALX_MAC_CTRL_MHASH_ALG_HI5B |
739 ALX_MAC_CTRL_BRD_EN |
742 ALX_MAC_CTRL_RXFC_EN |
743 ALX_MAC_CTRL_TXFC_EN |
744 7 << ALX_MAC_CTRL_PRMBLEN_SHIFT;
750 static netdev_features_t alx_fix_features(struct net_device *netdev,
751 netdev_features_t features)
753 if (netdev->mtu > ALX_MAX_TSO_PKT_SIZE)
754 features &= ~(NETIF_F_TSO | NETIF_F_TSO6);
759 static void alx_netif_stop(struct alx_priv *alx)
761 netif_trans_update(alx->dev);
762 if (netif_carrier_ok(alx->dev)) {
763 netif_carrier_off(alx->dev);
764 netif_tx_disable(alx->dev);
765 napi_disable(&alx->napi);
769 static void alx_halt(struct alx_priv *alx)
771 struct alx_hw *hw = &alx->hw;
774 hw->link_speed = SPEED_UNKNOWN;
775 hw->duplex = DUPLEX_UNKNOWN;
780 alx_enable_aspm(hw, false, false);
781 alx_irq_disable(alx);
782 alx_free_buffers(alx);
785 static void alx_configure(struct alx_priv *alx)
787 struct alx_hw *hw = &alx->hw;
789 alx_configure_basic(hw);
791 __alx_set_rx_mode(alx->dev);
793 alx_write_mem32(hw, ALX_MAC_CTRL, hw->rx_ctrl);
796 static void alx_activate(struct alx_priv *alx)
798 /* hardware setting lost, restore it */
799 alx_reinit_rings(alx);
802 /* clear old interrupts */
803 alx_write_mem32(&alx->hw, ALX_ISR, ~(u32)ALX_ISR_DIS);
807 alx_schedule_link_check(alx);
810 static void alx_reinit(struct alx_priv *alx)
818 static int alx_change_mtu(struct net_device *netdev, int mtu)
820 struct alx_priv *alx = netdev_priv(netdev);
821 int max_frame = ALX_MAX_FRAME_LEN(mtu);
823 if ((max_frame < ALX_MIN_FRAME_SIZE) ||
824 (max_frame > ALX_MAX_FRAME_SIZE))
827 if (netdev->mtu == mtu)
832 alx->rxbuf_size = max(max_frame, ALX_DEF_RXBUF_SIZE);
833 netdev_update_features(netdev);
834 if (netif_running(netdev))
839 static void alx_netif_start(struct alx_priv *alx)
841 netif_tx_wake_all_queues(alx->dev);
842 napi_enable(&alx->napi);
843 netif_carrier_on(alx->dev);
846 static int __alx_open(struct alx_priv *alx, bool resume)
851 netif_carrier_off(alx->dev);
853 err = alx_alloc_rings(alx);
859 err = alx_request_irq(alx);
863 /* clear old interrupts */
864 alx_write_mem32(&alx->hw, ALX_ISR, ~(u32)ALX_ISR_DIS);
869 netif_tx_start_all_queues(alx->dev);
871 alx_schedule_link_check(alx);
879 static void __alx_stop(struct alx_priv *alx)
886 static const char *alx_speed_desc(struct alx_hw *hw)
888 switch (alx_speed_to_ethadv(hw->link_speed, hw->duplex)) {
889 case ADVERTISED_1000baseT_Full:
890 return "1 Gbps Full";
891 case ADVERTISED_100baseT_Full:
892 return "100 Mbps Full";
893 case ADVERTISED_100baseT_Half:
894 return "100 Mbps Half";
895 case ADVERTISED_10baseT_Full:
896 return "10 Mbps Full";
897 case ADVERTISED_10baseT_Half:
898 return "10 Mbps Half";
900 return "Unknown speed";
904 static void alx_check_link(struct alx_priv *alx)
906 struct alx_hw *hw = &alx->hw;
912 /* clear PHY internal interrupt status, otherwise the main
913 * interrupt status will be asserted forever
915 alx_clear_phy_intr(hw);
917 old_speed = hw->link_speed;
918 old_duplex = hw->duplex;
919 err = alx_read_phy_link(hw);
923 spin_lock_irqsave(&alx->irq_lock, flags);
924 alx->int_mask |= ALX_ISR_PHY;
925 alx_write_mem32(hw, ALX_IMR, alx->int_mask);
926 spin_unlock_irqrestore(&alx->irq_lock, flags);
928 if (old_speed == hw->link_speed)
931 if (hw->link_speed != SPEED_UNKNOWN) {
932 netif_info(alx, link, alx->dev,
933 "NIC Up: %s\n", alx_speed_desc(hw));
934 alx_post_phy_link(hw);
935 alx_enable_aspm(hw, true, true);
938 if (old_speed == SPEED_UNKNOWN)
939 alx_netif_start(alx);
941 /* link is now down */
943 netif_info(alx, link, alx->dev, "Link Down\n");
944 err = alx_reset_mac(hw);
947 alx_irq_disable(alx);
949 /* MAC reset causes all HW settings to be lost, restore all */
950 err = alx_reinit_rings(alx);
954 alx_enable_aspm(hw, false, true);
955 alx_post_phy_link(hw);
962 alx_schedule_reset(alx);
965 static int alx_open(struct net_device *netdev)
967 return __alx_open(netdev_priv(netdev), false);
970 static int alx_stop(struct net_device *netdev)
972 __alx_stop(netdev_priv(netdev));
976 static void alx_link_check(struct work_struct *work)
978 struct alx_priv *alx;
980 alx = container_of(work, struct alx_priv, link_check_wk);
987 static void alx_reset(struct work_struct *work)
989 struct alx_priv *alx = container_of(work, struct alx_priv, reset_wk);
996 static int alx_tx_csum(struct sk_buff *skb, struct alx_txd *first)
1000 if (skb->ip_summed != CHECKSUM_PARTIAL)
1003 cso = skb_checksum_start_offset(skb);
1007 css = cso + skb->csum_offset;
1008 first->word1 |= cpu_to_le32((cso >> 1) << TPD_CXSUMSTART_SHIFT);
1009 first->word1 |= cpu_to_le32((css >> 1) << TPD_CXSUMOFFSET_SHIFT);
1010 first->word1 |= cpu_to_le32(1 << TPD_CXSUM_EN_SHIFT);
1015 static int alx_map_tx_skb(struct alx_priv *alx, struct sk_buff *skb)
1017 struct alx_tx_queue *txq = &alx->txq;
1018 struct alx_txd *tpd, *first_tpd;
1020 int maplen, f, first_idx = txq->write_idx;
1022 first_tpd = &txq->tpd[txq->write_idx];
1025 maplen = skb_headlen(skb);
1026 dma = dma_map_single(&alx->hw.pdev->dev, skb->data, maplen,
1028 if (dma_mapping_error(&alx->hw.pdev->dev, dma))
1031 dma_unmap_len_set(&txq->bufs[txq->write_idx], size, maplen);
1032 dma_unmap_addr_set(&txq->bufs[txq->write_idx], dma, dma);
1034 tpd->adrl.addr = cpu_to_le64(dma);
1035 tpd->len = cpu_to_le16(maplen);
1037 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) {
1038 struct skb_frag_struct *frag;
1040 frag = &skb_shinfo(skb)->frags[f];
1042 if (++txq->write_idx == alx->tx_ringsz)
1044 tpd = &txq->tpd[txq->write_idx];
1046 tpd->word1 = first_tpd->word1;
1048 maplen = skb_frag_size(frag);
1049 dma = skb_frag_dma_map(&alx->hw.pdev->dev, frag, 0,
1050 maplen, DMA_TO_DEVICE);
1051 if (dma_mapping_error(&alx->hw.pdev->dev, dma))
1053 dma_unmap_len_set(&txq->bufs[txq->write_idx], size, maplen);
1054 dma_unmap_addr_set(&txq->bufs[txq->write_idx], dma, dma);
1056 tpd->adrl.addr = cpu_to_le64(dma);
1057 tpd->len = cpu_to_le16(maplen);
1060 /* last TPD, set EOP flag and store skb */
1061 tpd->word1 |= cpu_to_le32(1 << TPD_EOP_SHIFT);
1062 txq->bufs[txq->write_idx].skb = skb;
1064 if (++txq->write_idx == alx->tx_ringsz)
1071 while (f != txq->write_idx) {
1072 alx_free_txbuf(alx, f);
1073 if (++f == alx->tx_ringsz)
1079 static netdev_tx_t alx_start_xmit(struct sk_buff *skb,
1080 struct net_device *netdev)
1082 struct alx_priv *alx = netdev_priv(netdev);
1083 struct alx_tx_queue *txq = &alx->txq;
1084 struct alx_txd *first;
1085 int tpdreq = skb_shinfo(skb)->nr_frags + 1;
1087 if (alx_tpd_avail(alx) < tpdreq) {
1088 netif_stop_queue(alx->dev);
1092 first = &txq->tpd[txq->write_idx];
1093 memset(first, 0, sizeof(*first));
1095 if (alx_tx_csum(skb, first))
1098 if (alx_map_tx_skb(alx, skb) < 0)
1101 netdev_sent_queue(alx->dev, skb->len);
1103 /* flush updates before updating hardware */
1105 alx_write_mem16(&alx->hw, ALX_TPD_PRI0_PIDX, txq->write_idx);
1107 if (alx_tpd_avail(alx) < alx->tx_ringsz/8)
1108 netif_stop_queue(alx->dev);
1110 return NETDEV_TX_OK;
1113 dev_kfree_skb_any(skb);
1114 return NETDEV_TX_OK;
1117 static void alx_tx_timeout(struct net_device *dev)
1119 struct alx_priv *alx = netdev_priv(dev);
1121 alx_schedule_reset(alx);
1124 static int alx_mdio_read(struct net_device *netdev,
1125 int prtad, int devad, u16 addr)
1127 struct alx_priv *alx = netdev_priv(netdev);
1128 struct alx_hw *hw = &alx->hw;
1132 if (prtad != hw->mdio.prtad)
1135 if (devad == MDIO_DEVAD_NONE)
1136 err = alx_read_phy_reg(hw, addr, &val);
1138 err = alx_read_phy_ext(hw, devad, addr, &val);
1145 static int alx_mdio_write(struct net_device *netdev,
1146 int prtad, int devad, u16 addr, u16 val)
1148 struct alx_priv *alx = netdev_priv(netdev);
1149 struct alx_hw *hw = &alx->hw;
1151 if (prtad != hw->mdio.prtad)
1154 if (devad == MDIO_DEVAD_NONE)
1155 return alx_write_phy_reg(hw, addr, val);
1157 return alx_write_phy_ext(hw, devad, addr, val);
1160 static int alx_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
1162 struct alx_priv *alx = netdev_priv(netdev);
1164 if (!netif_running(netdev))
1167 return mdio_mii_ioctl(&alx->hw.mdio, if_mii(ifr), cmd);
1170 #ifdef CONFIG_NET_POLL_CONTROLLER
1171 static void alx_poll_controller(struct net_device *netdev)
1173 struct alx_priv *alx = netdev_priv(netdev);
1176 alx_intr_msi(0, alx);
1178 alx_intr_legacy(0, alx);
1182 static struct rtnl_link_stats64 *alx_get_stats64(struct net_device *dev,
1183 struct rtnl_link_stats64 *net_stats)
1185 struct alx_priv *alx = netdev_priv(dev);
1186 struct alx_hw_stats *hw_stats = &alx->hw.stats;
1188 spin_lock(&alx->stats_lock);
1190 alx_update_hw_stats(&alx->hw);
1192 net_stats->tx_bytes = hw_stats->tx_byte_cnt;
1193 net_stats->rx_bytes = hw_stats->rx_byte_cnt;
1194 net_stats->multicast = hw_stats->rx_mcast;
1195 net_stats->collisions = hw_stats->tx_single_col +
1196 hw_stats->tx_multi_col +
1197 hw_stats->tx_late_col +
1198 hw_stats->tx_abort_col;
1200 net_stats->rx_errors = hw_stats->rx_frag +
1201 hw_stats->rx_fcs_err +
1202 hw_stats->rx_len_err +
1203 hw_stats->rx_ov_sz +
1204 hw_stats->rx_ov_rrd +
1205 hw_stats->rx_align_err +
1206 hw_stats->rx_ov_rxf;
1208 net_stats->rx_fifo_errors = hw_stats->rx_ov_rxf;
1209 net_stats->rx_length_errors = hw_stats->rx_len_err;
1210 net_stats->rx_crc_errors = hw_stats->rx_fcs_err;
1211 net_stats->rx_frame_errors = hw_stats->rx_align_err;
1212 net_stats->rx_dropped = hw_stats->rx_ov_rrd;
1214 net_stats->tx_errors = hw_stats->tx_late_col +
1215 hw_stats->tx_abort_col +
1216 hw_stats->tx_underrun +
1219 net_stats->tx_aborted_errors = hw_stats->tx_abort_col;
1220 net_stats->tx_fifo_errors = hw_stats->tx_underrun;
1221 net_stats->tx_window_errors = hw_stats->tx_late_col;
1223 net_stats->tx_packets = hw_stats->tx_ok + net_stats->tx_errors;
1224 net_stats->rx_packets = hw_stats->rx_ok + net_stats->rx_errors;
1226 spin_unlock(&alx->stats_lock);
1231 static const struct net_device_ops alx_netdev_ops = {
1232 .ndo_open = alx_open,
1233 .ndo_stop = alx_stop,
1234 .ndo_start_xmit = alx_start_xmit,
1235 .ndo_get_stats64 = alx_get_stats64,
1236 .ndo_set_rx_mode = alx_set_rx_mode,
1237 .ndo_validate_addr = eth_validate_addr,
1238 .ndo_set_mac_address = alx_set_mac_address,
1239 .ndo_change_mtu = alx_change_mtu,
1240 .ndo_do_ioctl = alx_ioctl,
1241 .ndo_tx_timeout = alx_tx_timeout,
1242 .ndo_fix_features = alx_fix_features,
1243 #ifdef CONFIG_NET_POLL_CONTROLLER
1244 .ndo_poll_controller = alx_poll_controller,
1248 static int alx_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
1250 struct net_device *netdev;
1251 struct alx_priv *alx;
1253 bool phy_configured;
1256 err = pci_enable_device_mem(pdev);
1260 /* The alx chip can DMA to 64-bit addresses, but it uses a single
1261 * shared register for the high 32 bits, so only a single, aligned,
1262 * 4 GB physical address range can be used for descriptors.
1264 if (!dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64))) {
1265 dev_dbg(&pdev->dev, "DMA to 64-BIT addresses\n");
1267 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
1269 dev_err(&pdev->dev, "No usable DMA config, aborting\n");
1270 goto out_pci_disable;
1274 err = pci_request_mem_regions(pdev, alx_drv_name);
1277 "pci_request_mem_regions failed\n");
1278 goto out_pci_disable;
1281 pci_enable_pcie_error_reporting(pdev);
1282 pci_set_master(pdev);
1284 if (!pdev->pm_cap) {
1286 "Can't find power management capability, aborting\n");
1288 goto out_pci_release;
1291 netdev = alloc_etherdev(sizeof(*alx));
1294 goto out_pci_release;
1297 SET_NETDEV_DEV(netdev, &pdev->dev);
1298 alx = netdev_priv(netdev);
1299 spin_lock_init(&alx->hw.mdio_lock);
1300 spin_lock_init(&alx->irq_lock);
1301 spin_lock_init(&alx->stats_lock);
1303 alx->hw.pdev = pdev;
1304 alx->msg_enable = NETIF_MSG_LINK | NETIF_MSG_HW | NETIF_MSG_IFUP |
1305 NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR | NETIF_MSG_WOL;
1307 pci_set_drvdata(pdev, alx);
1309 hw->hw_addr = pci_ioremap_bar(pdev, 0);
1311 dev_err(&pdev->dev, "cannot map device registers\n");
1313 goto out_free_netdev;
1316 netdev->netdev_ops = &alx_netdev_ops;
1317 netdev->ethtool_ops = &alx_ethtool_ops;
1318 netdev->irq = pdev->irq;
1319 netdev->watchdog_timeo = ALX_WATCHDOG_TIME;
1321 if (ent->driver_data & ALX_DEV_QUIRK_MSI_INTX_DISABLE_BUG)
1322 pdev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
1324 err = alx_init_sw(alx);
1326 dev_err(&pdev->dev, "net device private data init failed\n");
1332 phy_configured = alx_phy_configured(hw);
1334 if (!phy_configured)
1337 err = alx_reset_mac(hw);
1339 dev_err(&pdev->dev, "MAC Reset failed, error = %d\n", err);
1343 /* setup link to put it in a known good starting state */
1344 if (!phy_configured) {
1345 err = alx_setup_speed_duplex(hw, hw->adv_cfg, hw->flowctrl);
1348 "failed to configure PHY speed/duplex (err=%d)\n",
1354 netdev->hw_features = NETIF_F_SG | NETIF_F_HW_CSUM;
1356 if (alx_get_perm_macaddr(hw, hw->perm_addr)) {
1357 dev_warn(&pdev->dev,
1358 "Invalid permanent address programmed, using random one\n");
1359 eth_hw_addr_random(netdev);
1360 memcpy(hw->perm_addr, netdev->dev_addr, netdev->addr_len);
1363 memcpy(hw->mac_addr, hw->perm_addr, ETH_ALEN);
1364 memcpy(netdev->dev_addr, hw->mac_addr, ETH_ALEN);
1365 memcpy(netdev->perm_addr, hw->perm_addr, ETH_ALEN);
1369 hw->mdio.dev = netdev;
1370 hw->mdio.mode_support = MDIO_SUPPORTS_C45 |
1373 hw->mdio.mdio_read = alx_mdio_read;
1374 hw->mdio.mdio_write = alx_mdio_write;
1376 if (!alx_get_phy_info(hw)) {
1377 dev_err(&pdev->dev, "failed to identify PHY\n");
1382 INIT_WORK(&alx->link_check_wk, alx_link_check);
1383 INIT_WORK(&alx->reset_wk, alx_reset);
1384 netif_carrier_off(netdev);
1386 err = register_netdev(netdev);
1388 dev_err(&pdev->dev, "register netdevice failed\n");
1393 "Qualcomm Atheros AR816x/AR817x Ethernet [%pM]\n",
1399 iounmap(hw->hw_addr);
1401 free_netdev(netdev);
1403 pci_release_mem_regions(pdev);
1405 pci_disable_device(pdev);
1409 static void alx_remove(struct pci_dev *pdev)
1411 struct alx_priv *alx = pci_get_drvdata(pdev);
1412 struct alx_hw *hw = &alx->hw;
1414 cancel_work_sync(&alx->link_check_wk);
1415 cancel_work_sync(&alx->reset_wk);
1417 /* restore permanent mac address */
1418 alx_set_macaddr(hw, hw->perm_addr);
1420 unregister_netdev(alx->dev);
1421 iounmap(hw->hw_addr);
1422 pci_release_mem_regions(pdev);
1424 pci_disable_pcie_error_reporting(pdev);
1425 pci_disable_device(pdev);
1427 free_netdev(alx->dev);
1430 #ifdef CONFIG_PM_SLEEP
1431 static int alx_suspend(struct device *dev)
1433 struct pci_dev *pdev = to_pci_dev(dev);
1434 struct alx_priv *alx = pci_get_drvdata(pdev);
1436 if (!netif_running(alx->dev))
1438 netif_device_detach(alx->dev);
1443 static int alx_resume(struct device *dev)
1445 struct pci_dev *pdev = to_pci_dev(dev);
1446 struct alx_priv *alx = pci_get_drvdata(pdev);
1447 struct alx_hw *hw = &alx->hw;
1451 if (!netif_running(alx->dev))
1453 netif_device_attach(alx->dev);
1454 return __alx_open(alx, true);
1457 static SIMPLE_DEV_PM_OPS(alx_pm_ops, alx_suspend, alx_resume);
1458 #define ALX_PM_OPS (&alx_pm_ops)
1460 #define ALX_PM_OPS NULL
1464 static pci_ers_result_t alx_pci_error_detected(struct pci_dev *pdev,
1465 pci_channel_state_t state)
1467 struct alx_priv *alx = pci_get_drvdata(pdev);
1468 struct net_device *netdev = alx->dev;
1469 pci_ers_result_t rc = PCI_ERS_RESULT_NEED_RESET;
1471 dev_info(&pdev->dev, "pci error detected\n");
1475 if (netif_running(netdev)) {
1476 netif_device_detach(netdev);
1480 if (state == pci_channel_io_perm_failure)
1481 rc = PCI_ERS_RESULT_DISCONNECT;
1483 pci_disable_device(pdev);
1490 static pci_ers_result_t alx_pci_error_slot_reset(struct pci_dev *pdev)
1492 struct alx_priv *alx = pci_get_drvdata(pdev);
1493 struct alx_hw *hw = &alx->hw;
1494 pci_ers_result_t rc = PCI_ERS_RESULT_DISCONNECT;
1496 dev_info(&pdev->dev, "pci error slot reset\n");
1500 if (pci_enable_device(pdev)) {
1501 dev_err(&pdev->dev, "Failed to re-enable PCI device after reset\n");
1505 pci_set_master(pdev);
1508 if (!alx_reset_mac(hw))
1509 rc = PCI_ERS_RESULT_RECOVERED;
1511 pci_cleanup_aer_uncorrect_error_status(pdev);
1518 static void alx_pci_error_resume(struct pci_dev *pdev)
1520 struct alx_priv *alx = pci_get_drvdata(pdev);
1521 struct net_device *netdev = alx->dev;
1523 dev_info(&pdev->dev, "pci error resume\n");
1527 if (netif_running(netdev)) {
1529 netif_device_attach(netdev);
1535 static const struct pci_error_handlers alx_err_handlers = {
1536 .error_detected = alx_pci_error_detected,
1537 .slot_reset = alx_pci_error_slot_reset,
1538 .resume = alx_pci_error_resume,
1541 static const struct pci_device_id alx_pci_tbl[] = {
1542 { PCI_VDEVICE(ATTANSIC, ALX_DEV_ID_AR8161),
1543 .driver_data = ALX_DEV_QUIRK_MSI_INTX_DISABLE_BUG },
1544 { PCI_VDEVICE(ATTANSIC, ALX_DEV_ID_E2200),
1545 .driver_data = ALX_DEV_QUIRK_MSI_INTX_DISABLE_BUG },
1546 { PCI_VDEVICE(ATTANSIC, ALX_DEV_ID_E2400),
1547 .driver_data = ALX_DEV_QUIRK_MSI_INTX_DISABLE_BUG },
1548 { PCI_VDEVICE(ATTANSIC, ALX_DEV_ID_E2500),
1549 .driver_data = ALX_DEV_QUIRK_MSI_INTX_DISABLE_BUG },
1550 { PCI_VDEVICE(ATTANSIC, ALX_DEV_ID_AR8162),
1551 .driver_data = ALX_DEV_QUIRK_MSI_INTX_DISABLE_BUG },
1552 { PCI_VDEVICE(ATTANSIC, ALX_DEV_ID_AR8171) },
1553 { PCI_VDEVICE(ATTANSIC, ALX_DEV_ID_AR8172) },
1557 static struct pci_driver alx_driver = {
1558 .name = alx_drv_name,
1559 .id_table = alx_pci_tbl,
1561 .remove = alx_remove,
1562 .err_handler = &alx_err_handlers,
1563 .driver.pm = ALX_PM_OPS,
1566 module_pci_driver(alx_driver);
1567 MODULE_DEVICE_TABLE(pci, alx_pci_tbl);
1568 MODULE_AUTHOR("Johannes Berg <johannes@sipsolutions.net>");
1569 MODULE_AUTHOR("Qualcomm Corporation, <nic-devel@qualcomm.com>");
1571 "Qualcomm Atheros(R) AR816x/AR817x PCI-E Ethernet Network Driver");
1572 MODULE_LICENSE("GPL");