1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Driver for the Macintosh 68K onboard MACE controller with PSC
4 * driven DMA. The MACE driver code is derived from mace.c. The
5 * Mac68k theory of operation is courtesy of the MacBSD wizards.
7 * Copyright (C) 1996 Paul Mackerras.
8 * Copyright (C) 1998 Alan Cox <alan@lxorguk.ukuu.org.uk>
10 * Modified heavily by Joshua M. Thompson based on Dave Huang's NetBSD driver
12 * Copyright (C) 2007 Finn Thain
14 * Converted to DMA API, converted to unified driver model,
15 * sync'd some routines with mace.c and fixed various bugs.
19 #include <linux/kernel.h>
20 #include <linux/module.h>
21 #include <linux/netdevice.h>
22 #include <linux/etherdevice.h>
23 #include <linux/delay.h>
24 #include <linux/string.h>
25 #include <linux/crc32.h>
26 #include <linux/bitrev.h>
27 #include <linux/dma-mapping.h>
28 #include <linux/platform_device.h>
29 #include <linux/gfp.h>
30 #include <linux/interrupt.h>
32 #include <asm/macints.h>
33 #include <asm/mac_psc.h>
37 static char mac_mace_string[] = "macmace";
39 #define N_TX_BUFF_ORDER 0
40 #define N_TX_RING (1 << N_TX_BUFF_ORDER)
41 #define N_RX_BUFF_ORDER 3
42 #define N_RX_RING (1 << N_RX_BUFF_ORDER)
46 #define MACE_BUFF_SIZE 0x800
48 /* Chip rev needs workaround on HW & multicast addr change */
49 #define BROKEN_ADDRCHG_REV 0x0941
51 /* The MACE is simply wired down on a Mac68K box */
53 #define MACE_BASE (void *)(0x50F1C000)
54 #define MACE_PROM (void *)(0x50F08001)
57 volatile struct mace *mace;
58 unsigned char *tx_ring;
59 dma_addr_t tx_ring_phys;
60 unsigned char *rx_ring;
61 dma_addr_t rx_ring_phys;
64 int tx_slot, tx_sloti, tx_count;
66 struct device *device;
81 /* And frame continues.. */
84 #define PRIV_BYTES sizeof(struct mace_data)
86 static int mace_open(struct net_device *dev);
87 static int mace_close(struct net_device *dev);
88 static netdev_tx_t mace_xmit_start(struct sk_buff *skb, struct net_device *dev);
89 static void mace_set_multicast(struct net_device *dev);
90 static int mace_set_address(struct net_device *dev, void *addr);
91 static void mace_reset(struct net_device *dev);
92 static irqreturn_t mace_interrupt(int irq, void *dev_id);
93 static irqreturn_t mace_dma_intr(int irq, void *dev_id);
94 static void mace_tx_timeout(struct net_device *dev, unsigned int txqueue);
95 static void __mace_set_address(struct net_device *dev, const void *addr);
98 * Load a receive DMA channel with a base address and ring length
101 static void mace_load_rxdma_base(struct net_device *dev, int set)
103 struct mace_data *mp = netdev_priv(dev);
105 psc_write_word(PSC_ENETRD_CMD + set, 0x0100);
106 psc_write_long(PSC_ENETRD_ADDR + set, (u32) mp->rx_ring_phys);
107 psc_write_long(PSC_ENETRD_LEN + set, N_RX_RING);
108 psc_write_word(PSC_ENETRD_CMD + set, 0x9800);
113 * Reset the receive DMA subsystem
116 static void mace_rxdma_reset(struct net_device *dev)
118 struct mace_data *mp = netdev_priv(dev);
119 volatile struct mace *mace = mp->mace;
120 u8 maccc = mace->maccc;
122 mace->maccc = maccc & ~ENRCV;
124 psc_write_word(PSC_ENETRD_CTL, 0x8800);
125 mace_load_rxdma_base(dev, 0x00);
126 psc_write_word(PSC_ENETRD_CTL, 0x0400);
128 psc_write_word(PSC_ENETRD_CTL, 0x8800);
129 mace_load_rxdma_base(dev, 0x10);
130 psc_write_word(PSC_ENETRD_CTL, 0x0400);
135 psc_write_word(PSC_ENETRD_CMD + PSC_SET0, 0x9800);
136 psc_write_word(PSC_ENETRD_CMD + PSC_SET1, 0x9800);
140 * Reset the transmit DMA subsystem
143 static void mace_txdma_reset(struct net_device *dev)
145 struct mace_data *mp = netdev_priv(dev);
146 volatile struct mace *mace = mp->mace;
149 psc_write_word(PSC_ENETWR_CTL, 0x8800);
152 mace->maccc = maccc & ~ENXMT;
154 mp->tx_slot = mp->tx_sloti = 0;
155 mp->tx_count = N_TX_RING;
157 psc_write_word(PSC_ENETWR_CTL, 0x0400);
165 static void mace_dma_off(struct net_device *dev)
167 psc_write_word(PSC_ENETRD_CTL, 0x8800);
168 psc_write_word(PSC_ENETRD_CTL, 0x1000);
169 psc_write_word(PSC_ENETRD_CMD + PSC_SET0, 0x1100);
170 psc_write_word(PSC_ENETRD_CMD + PSC_SET1, 0x1100);
172 psc_write_word(PSC_ENETWR_CTL, 0x8800);
173 psc_write_word(PSC_ENETWR_CTL, 0x1000);
174 psc_write_word(PSC_ENETWR_CMD + PSC_SET0, 0x1100);
175 psc_write_word(PSC_ENETWR_CMD + PSC_SET1, 0x1100);
178 static const struct net_device_ops mace_netdev_ops = {
179 .ndo_open = mace_open,
180 .ndo_stop = mace_close,
181 .ndo_start_xmit = mace_xmit_start,
182 .ndo_tx_timeout = mace_tx_timeout,
183 .ndo_set_rx_mode = mace_set_multicast,
184 .ndo_set_mac_address = mace_set_address,
185 .ndo_validate_addr = eth_validate_addr,
189 * Not really much of a probe. The hardware table tells us if this
190 * model of Macintrash has a MACE (AV macintoshes)
193 static int mace_probe(struct platform_device *pdev)
196 struct mace_data *mp;
198 struct net_device *dev;
199 unsigned char checksum = 0;
200 u8 macaddr[ETH_ALEN];
203 dev = alloc_etherdev(PRIV_BYTES);
207 mp = netdev_priv(dev);
209 mp->device = &pdev->dev;
210 platform_set_drvdata(pdev, dev);
211 SET_NETDEV_DEV(dev, &pdev->dev);
213 dev->base_addr = (u32)MACE_BASE;
214 mp->mace = MACE_BASE;
216 dev->irq = IRQ_MAC_MACE;
217 mp->dma_intr = IRQ_MAC_MACE_DMA;
219 mp->chipid = mp->mace->chipid_hi << 8 | mp->mace->chipid_lo;
222 * The PROM contains 8 bytes which total 0xFF when XOR'd
223 * together. Due to the usual peculiar apple brain damage
224 * the bytes are spaced out in a strange boundary and the
230 for (j = 0; j < 6; ++j) {
231 u8 v = bitrev8(addr[j<<4]);
235 eth_hw_addr_set(dev, macaddr);
237 checksum ^= bitrev8(addr[j<<4]);
240 if (checksum != 0xFF) {
245 dev->netdev_ops = &mace_netdev_ops;
246 dev->watchdog_timeo = TX_TIMEOUT;
248 pr_info("Onboard MACE, hardware address %pM, chip revision 0x%04X\n",
249 dev->dev_addr, mp->chipid);
251 err = register_netdev(dev);
263 static void mace_reset(struct net_device *dev)
265 struct mace_data *mp = netdev_priv(dev);
266 volatile struct mace *mb = mp->mace;
269 /* soft-reset the chip */
273 if (mb->biucc & SWRST) {
280 printk(KERN_ERR "macmace: cannot reset chip!\n");
284 mb->maccc = 0; /* turn off tx, rx */
285 mb->imr = 0xFF; /* disable all intrs for now */
288 mb->biucc = XMTSP_64;
290 mb->fifocc = XMTFW_8 | RCVFW_64 | XMTFWU | RCVFWU;
292 mb->xmtfc = AUTO_PAD_XMIT; /* auto-pad short frames */
295 /* load up the hardware address */
296 __mace_set_address(dev, dev->dev_addr);
298 /* clear the multicast filter */
299 if (mp->chipid == BROKEN_ADDRCHG_REV)
302 mb->iac = ADDRCHG | LOGADDR;
303 while ((mb->iac & ADDRCHG) != 0)
306 for (i = 0; i < 8; ++i)
309 /* done changing address */
310 if (mp->chipid != BROKEN_ADDRCHG_REV)
313 mb->plscc = PORTSEL_AUI;
317 * Load the address on a mace controller.
320 static void __mace_set_address(struct net_device *dev, const void *addr)
322 struct mace_data *mp = netdev_priv(dev);
323 volatile struct mace *mb = mp->mace;
324 const unsigned char *p = addr;
325 u8 macaddr[ETH_ALEN];
328 /* load up the hardware address */
329 if (mp->chipid == BROKEN_ADDRCHG_REV)
332 mb->iac = ADDRCHG | PHYADDR;
333 while ((mb->iac & ADDRCHG) != 0)
336 for (i = 0; i < 6; ++i)
337 mb->padr = macaddr[i] = p[i];
338 eth_hw_addr_set(dev, macaddr);
339 if (mp->chipid != BROKEN_ADDRCHG_REV)
343 static int mace_set_address(struct net_device *dev, void *addr)
345 struct mace_data *mp = netdev_priv(dev);
346 volatile struct mace *mb = mp->mace;
350 local_irq_save(flags);
354 __mace_set_address(dev, addr);
358 local_irq_restore(flags);
364 * Open the Macintosh MACE. Most of this is playing with the DMA
365 * engine. The ethernet chip is quite friendly.
368 static int mace_open(struct net_device *dev)
370 struct mace_data *mp = netdev_priv(dev);
371 volatile struct mace *mb = mp->mace;
376 if (request_irq(dev->irq, mace_interrupt, 0, dev->name, dev)) {
377 printk(KERN_ERR "%s: can't get irq %d\n", dev->name, dev->irq);
380 if (request_irq(mp->dma_intr, mace_dma_intr, 0, dev->name, dev)) {
381 printk(KERN_ERR "%s: can't get irq %d\n", dev->name, mp->dma_intr);
382 free_irq(dev->irq, dev);
386 /* Allocate the DMA ring buffers */
388 mp->tx_ring = dma_alloc_coherent(mp->device,
389 N_TX_RING * MACE_BUFF_SIZE,
390 &mp->tx_ring_phys, GFP_KERNEL);
391 if (mp->tx_ring == NULL)
394 mp->rx_ring = dma_alloc_coherent(mp->device,
395 N_RX_RING * MACE_BUFF_SIZE,
396 &mp->rx_ring_phys, GFP_KERNEL);
397 if (mp->rx_ring == NULL)
402 /* Not sure what these do */
404 psc_write_word(PSC_ENETWR_CTL, 0x9000);
405 psc_write_word(PSC_ENETRD_CTL, 0x9000);
406 psc_write_word(PSC_ENETWR_CTL, 0x0400);
407 psc_write_word(PSC_ENETRD_CTL, 0x0400);
409 mace_rxdma_reset(dev);
410 mace_txdma_reset(dev);
413 mb->maccc = ENXMT | ENRCV;
414 /* enable all interrupts except receive interrupts */
419 dma_free_coherent(mp->device, N_TX_RING * MACE_BUFF_SIZE,
420 mp->tx_ring, mp->tx_ring_phys);
422 free_irq(dev->irq, dev);
423 free_irq(mp->dma_intr, dev);
428 * Shut down the mace and its interrupt channel
431 static int mace_close(struct net_device *dev)
433 struct mace_data *mp = netdev_priv(dev);
434 volatile struct mace *mb = mp->mace;
436 mb->maccc = 0; /* disable rx and tx */
437 mb->imr = 0xFF; /* disable all irqs */
438 mace_dma_off(dev); /* disable rx and tx dma */
447 static netdev_tx_t mace_xmit_start(struct sk_buff *skb, struct net_device *dev)
449 struct mace_data *mp = netdev_priv(dev);
452 /* Stop the queue since there's only the one buffer */
454 local_irq_save(flags);
455 netif_stop_queue(dev);
457 printk(KERN_ERR "macmace: tx queue running but no free buffers.\n");
458 local_irq_restore(flags);
459 return NETDEV_TX_BUSY;
462 local_irq_restore(flags);
464 dev->stats.tx_packets++;
465 dev->stats.tx_bytes += skb->len;
467 /* We need to copy into our xmit buffer to take care of alignment and caching issues */
468 skb_copy_from_linear_data(skb, mp->tx_ring, skb->len);
470 /* load the Tx DMA and fire it off */
472 psc_write_long(PSC_ENETWR_ADDR + mp->tx_slot, (u32) mp->tx_ring_phys);
473 psc_write_long(PSC_ENETWR_LEN + mp->tx_slot, skb->len);
474 psc_write_word(PSC_ENETWR_CMD + mp->tx_slot, 0x9800);
483 static void mace_set_multicast(struct net_device *dev)
485 struct mace_data *mp = netdev_priv(dev);
486 volatile struct mace *mb = mp->mace;
492 local_irq_save(flags);
496 if (dev->flags & IFF_PROMISC) {
499 unsigned char multicast_filter[8];
500 struct netdev_hw_addr *ha;
502 if (dev->flags & IFF_ALLMULTI) {
503 for (i = 0; i < 8; i++) {
504 multicast_filter[i] = 0xFF;
507 for (i = 0; i < 8; i++)
508 multicast_filter[i] = 0;
509 netdev_for_each_mc_addr(ha, dev) {
510 crc = ether_crc_le(6, ha->addr);
511 /* bit number in multicast_filter */
513 multicast_filter[i >> 3] |= 1 << (i & 7);
517 if (mp->chipid == BROKEN_ADDRCHG_REV)
520 mb->iac = ADDRCHG | LOGADDR;
521 while ((mb->iac & ADDRCHG) != 0)
524 for (i = 0; i < 8; ++i)
525 mb->ladrf = multicast_filter[i];
526 if (mp->chipid != BROKEN_ADDRCHG_REV)
531 local_irq_restore(flags);
534 static void mace_handle_misc_intrs(struct net_device *dev, int intr)
536 struct mace_data *mp = netdev_priv(dev);
537 volatile struct mace *mb = mp->mace;
538 static int mace_babbles, mace_jabbers;
541 dev->stats.rx_missed_errors += 256;
542 dev->stats.rx_missed_errors += mb->mpc; /* reading clears it */
544 dev->stats.rx_length_errors += 256;
545 dev->stats.rx_length_errors += mb->rntpc; /* reading clears it */
547 ++dev->stats.tx_heartbeat_errors;
549 if (mace_babbles++ < 4)
550 printk(KERN_DEBUG "macmace: babbling transmitter\n");
552 if (mace_jabbers++ < 4)
553 printk(KERN_DEBUG "macmace: jabbering transceiver\n");
556 static irqreturn_t mace_interrupt(int irq, void *dev_id)
558 struct net_device *dev = (struct net_device *) dev_id;
559 struct mace_data *mp = netdev_priv(dev);
560 volatile struct mace *mb = mp->mace;
564 /* don't want the dma interrupt handler to fire */
565 local_irq_save(flags);
567 intr = mb->ir; /* read interrupt register */
568 mace_handle_misc_intrs(dev, intr);
572 if ((fs & XMTSV) == 0) {
573 printk(KERN_ERR "macmace: xmtfs not valid! (fs=%x)\n", fs);
576 * XXX mace likes to hang the machine after a xmtfs error.
577 * This is hard to reproduce, resetting *may* help
580 /* dma should have finished */
582 printk(KERN_DEBUG "macmace: tx ring ran out? (fs=%x)\n", fs);
585 if (fs & (UFLO|LCOL|LCAR|RTRY)) {
586 ++dev->stats.tx_errors;
588 ++dev->stats.tx_carrier_errors;
589 else if (fs & (UFLO|LCOL|RTRY)) {
590 ++dev->stats.tx_aborted_errors;
591 if (mb->xmtfs & UFLO) {
592 dev->stats.tx_fifo_errors++;
593 mace_txdma_reset(dev);
600 netif_wake_queue(dev);
602 local_irq_restore(flags);
607 static void mace_tx_timeout(struct net_device *dev, unsigned int txqueue)
609 struct mace_data *mp = netdev_priv(dev);
610 volatile struct mace *mb = mp->mace;
613 local_irq_save(flags);
615 /* turn off both tx and rx and reset the chip */
617 printk(KERN_ERR "macmace: transmit timeout - resetting\n");
618 mace_txdma_reset(dev);
622 mace_rxdma_reset(dev);
624 mp->tx_count = N_TX_RING;
625 netif_wake_queue(dev);
628 mb->maccc = ENXMT | ENRCV;
629 /* enable all interrupts except receive interrupts */
632 local_irq_restore(flags);
636 * Handle a newly arrived frame
639 static void mace_dma_rx_frame(struct net_device *dev, struct mace_frame *mf)
642 unsigned int frame_status = mf->rcvsts;
644 if (frame_status & (RS_OFLO | RS_CLSN | RS_FRAMERR | RS_FCSERR)) {
645 dev->stats.rx_errors++;
646 if (frame_status & RS_OFLO)
647 dev->stats.rx_fifo_errors++;
648 if (frame_status & RS_CLSN)
649 dev->stats.collisions++;
650 if (frame_status & RS_FRAMERR)
651 dev->stats.rx_frame_errors++;
652 if (frame_status & RS_FCSERR)
653 dev->stats.rx_crc_errors++;
655 unsigned int frame_length = mf->rcvcnt + ((frame_status & 0x0F) << 8 );
657 skb = netdev_alloc_skb(dev, frame_length + 2);
659 dev->stats.rx_dropped++;
663 skb_put_data(skb, mf->data, frame_length);
665 skb->protocol = eth_type_trans(skb, dev);
667 dev->stats.rx_packets++;
668 dev->stats.rx_bytes += frame_length;
673 * The PSC has passed us a DMA interrupt event.
676 static irqreturn_t mace_dma_intr(int irq, void *dev_id)
678 struct net_device *dev = (struct net_device *) dev_id;
679 struct mace_data *mp = netdev_priv(dev);
684 /* Not sure what this does */
686 while ((baka = psc_read_long(PSC_MYSTERY)) != psc_read_long(PSC_MYSTERY));
687 if (!(baka & 0x60000000)) return IRQ_NONE;
690 * Process the read queue
693 status = psc_read_word(PSC_ENETRD_CTL);
695 if (status & 0x2000) {
696 mace_rxdma_reset(dev);
697 } else if (status & 0x0100) {
698 psc_write_word(PSC_ENETRD_CMD + mp->rx_slot, 0x1100);
700 left = psc_read_long(PSC_ENETRD_LEN + mp->rx_slot);
701 head = N_RX_RING - left;
703 /* Loop through the ring buffer and process new packages */
705 while (mp->rx_tail < head) {
706 mace_dma_rx_frame(dev, (struct mace_frame*) (mp->rx_ring
707 + (mp->rx_tail * MACE_BUFF_SIZE)));
711 /* If we're out of buffers in this ring then switch to */
712 /* the other set, otherwise just reactivate this one. */
715 mace_load_rxdma_base(dev, mp->rx_slot);
718 psc_write_word(PSC_ENETRD_CMD + mp->rx_slot, 0x9800);
723 * Process the write queue
726 status = psc_read_word(PSC_ENETWR_CTL);
728 if (status & 0x2000) {
729 mace_txdma_reset(dev);
730 } else if (status & 0x0100) {
731 psc_write_word(PSC_ENETWR_CMD + mp->tx_sloti, 0x0100);
732 mp->tx_sloti ^= 0x10;
738 MODULE_LICENSE("GPL");
739 MODULE_DESCRIPTION("Macintosh MACE ethernet driver");
740 MODULE_ALIAS("platform:macmace");
742 static int mac_mace_device_remove(struct platform_device *pdev)
744 struct net_device *dev = platform_get_drvdata(pdev);
745 struct mace_data *mp = netdev_priv(dev);
747 unregister_netdev(dev);
749 free_irq(dev->irq, dev);
750 free_irq(IRQ_MAC_MACE_DMA, dev);
752 dma_free_coherent(mp->device, N_RX_RING * MACE_BUFF_SIZE,
753 mp->rx_ring, mp->rx_ring_phys);
754 dma_free_coherent(mp->device, N_TX_RING * MACE_BUFF_SIZE,
755 mp->tx_ring, mp->tx_ring_phys);
762 static struct platform_driver mac_mace_driver = {
764 .remove = mac_mace_device_remove,
766 .name = mac_mace_string,
770 module_platform_driver(mac_mace_driver);