drivers/net/ethernet/apm/xgene/xgene_enet_sgmac.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /* Applied Micro X-Gene SoC Ethernet Driver
   3  *
   4  * Copyright (c) 2014, Applied Micro Circuits Corporation
   5  * Authors: Iyappan Subramanian <isubramanian@apm.com>
   6  *          Keyur Chudgar <kchudgar@apm.com>
   7  */
   8
   9 #include "xgene_enet_main.h"
  10 #include "xgene_enet_hw.h"
  11 #include "xgene_enet_sgmac.h"
  12 #include "xgene_enet_xgmac.h"
  13
  14 static void xgene_enet_wr_csr(struct xgene_enet_pdata *p, u32 offset, u32 val)
  15 {
  16         iowrite32(val, p->eth_csr_addr + offset);
  17 }
  18
  19 static void xgene_enet_wr_clkrst_csr(struct xgene_enet_pdata *p, u32 offset,
  20                                      u32 val)
  21 {
  22         iowrite32(val, p->base_addr + offset);
  23 }
  24
  25 static void xgene_enet_wr_ring_if(struct xgene_enet_pdata *p,
  26                                   u32 offset, u32 val)
  27 {
  28         iowrite32(val, p->eth_ring_if_addr + offset);
  29 }
  30
  31 static void xgene_enet_wr_diag_csr(struct xgene_enet_pdata *p,
  32                                    u32 offset, u32 val)
  33 {
  34         iowrite32(val, p->eth_diag_csr_addr + offset);
  35 }
  36
  37 static void xgene_enet_wr_mcx_csr(struct xgene_enet_pdata *pdata,
  38                                   u32 offset, u32 val)
  39 {
  40         void __iomem *addr = pdata->mcx_mac_csr_addr + offset;
  41
  42         iowrite32(val, addr);
  43 }
  44
  45 static u32 xgene_enet_rd_csr(struct xgene_enet_pdata *p, u32 offset)
  46 {
  47         return ioread32(p->eth_csr_addr + offset);
  48 }
  49
  50 static u32 xgene_enet_rd_diag_csr(struct xgene_enet_pdata *p, u32 offset)
  51 {
  52         return ioread32(p->eth_diag_csr_addr + offset);
  53 }
  54
  55 static u32 xgene_enet_rd_mcx_csr(struct xgene_enet_pdata *p, u32 offset)
  56 {
  57         return ioread32(p->mcx_mac_csr_addr + offset);
  58 }
  59
  60 static int xgene_enet_ecc_init(struct xgene_enet_pdata *p)
  61 {
  62         struct net_device *ndev = p->ndev;
  63         u32 data, shutdown;
  64         int i = 0;
  65
  66         shutdown = xgene_enet_rd_diag_csr(p, ENET_CFG_MEM_RAM_SHUTDOWN_ADDR);
  67         data = xgene_enet_rd_diag_csr(p, ENET_BLOCK_MEM_RDY_ADDR);
  68
  69         if (!shutdown && data == ~0U) {
  70                 netdev_dbg(ndev, "+ ecc_init done, skipping\n");
  71                 return 0;
  72         }
  73
  74         xgene_enet_wr_diag_csr(p, ENET_CFG_MEM_RAM_SHUTDOWN_ADDR, 0);
  75         do {
  76                 usleep_range(100, 110);
  77                 data = xgene_enet_rd_diag_csr(p, ENET_BLOCK_MEM_RDY_ADDR);
  78                 if (data == ~0U)
  79                         return 0;
  80         } while (++i < 10);
  81
  82         netdev_err(ndev, "Failed to release memory from shutdown\n");
  83         return -ENODEV;
  84 }
  85
  86 static void xgene_sgmac_get_drop_cnt(struct xgene_enet_pdata *pdata,
  87                                      u32 *rx, u32 *tx)
  88 {
  89         u32 addr, count;
  90
  91         addr = (pdata->enet_id != XGENE_ENET1) ?
  92                 XG_MCX_ICM_ECM_DROP_COUNT_REG0_ADDR :
  93                 ICM_ECM_DROP_COUNT_REG0_ADDR + pdata->port_id * OFFSET_4;
  94         count = xgene_enet_rd_mcx_csr(pdata, addr);
  95         *rx = ICM_DROP_COUNT(count);
  96         *tx = ECM_DROP_COUNT(count);
  97         /* Errata: 10GE_4 - ICM_ECM_DROP_COUNT not clear-on-read */
  98         addr = (pdata->enet_id != XGENE_ENET1) ?
  99                 XG_MCX_ECM_CONFIG0_REG_0_ADDR :
 100                 ECM_CONFIG0_REG_0_ADDR + pdata->port_id * OFFSET_4;
 101         xgene_enet_rd_mcx_csr(pdata, addr);
 102 }
 103
 104 static void xgene_enet_config_ring_if_assoc(struct xgene_enet_pdata *p)
 105 {
 106         u32 val;
 107
 108         val = (p->enet_id == XGENE_ENET1) ? 0xffffffff : 0;
 109         xgene_enet_wr_ring_if(p, ENET_CFGSSQMIWQASSOC_ADDR, val);
 110         xgene_enet_wr_ring_if(p, ENET_CFGSSQMIFPQASSOC_ADDR, val);
 111 }
 112
 113 static void xgene_mii_phy_write(struct xgene_enet_pdata *p, u8 phy_id,
 114                                 u32 reg, u16 data)
 115 {
 116         u32 addr, wr_data, done;
 117         int i;
 118
 119         addr = PHY_ADDR(phy_id) | REG_ADDR(reg);
 120         xgene_enet_wr_mac(p, MII_MGMT_ADDRESS_ADDR, addr);
 121
 122         wr_data = PHY_CONTROL(data);
 123         xgene_enet_wr_mac(p, MII_MGMT_CONTROL_ADDR, wr_data);
 124
 125         for (i = 0; i < 10; i++) {
 126                 done = xgene_enet_rd_mac(p, MII_MGMT_INDICATORS_ADDR);
 127                 if (!(done & BUSY_MASK))
 128                         return;
 129                 usleep_range(10, 20);
 130         }
 131
 132         netdev_err(p->ndev, "MII_MGMT write failed\n");
 133 }
 134
 135 static u32 xgene_mii_phy_read(struct xgene_enet_pdata *p, u8 phy_id, u32 reg)
 136 {
 137         u32 addr, data, done;
 138         int i;
 139
 140         addr = PHY_ADDR(phy_id) | REG_ADDR(reg);
 141         xgene_enet_wr_mac(p, MII_MGMT_ADDRESS_ADDR, addr);
 142         xgene_enet_wr_mac(p, MII_MGMT_COMMAND_ADDR, READ_CYCLE_MASK);
 143
 144         for (i = 0; i < 10; i++) {
 145                 done = xgene_enet_rd_mac(p, MII_MGMT_INDICATORS_ADDR);
 146                 if (!(done & BUSY_MASK)) {
 147                         data = xgene_enet_rd_mac(p, MII_MGMT_STATUS_ADDR);
 148                         xgene_enet_wr_mac(p, MII_MGMT_COMMAND_ADDR, 0);
 149
 150                         return data;
 151                 }
 152                 usleep_range(10, 20);
 153         }
 154
 155         netdev_err(p->ndev, "MII_MGMT read failed\n");
 156
 157         return 0;
 158 }
 159
 160 static void xgene_sgmac_reset(struct xgene_enet_pdata *p)
 161 {
 162         xgene_enet_wr_mac(p, MAC_CONFIG_1_ADDR, SOFT_RESET1);
 163         xgene_enet_wr_mac(p, MAC_CONFIG_1_ADDR, 0);
 164 }
 165
 166 static void xgene_sgmac_set_mac_addr(struct xgene_enet_pdata *p)
 167 {
 168         const u8 *dev_addr = p->ndev->dev_addr;
 169         u32 addr0, addr1;
 170
 171         addr0 = (dev_addr[3] << 24) | (dev_addr[2] << 16) |
 172                 (dev_addr[1] << 8) | dev_addr[0];
 173         xgene_enet_wr_mac(p, STATION_ADDR0_ADDR, addr0);
 174
 175         addr1 = xgene_enet_rd_mac(p, STATION_ADDR1_ADDR);
 176         addr1 |= (dev_addr[5] << 24) | (dev_addr[4] << 16);
 177         xgene_enet_wr_mac(p, STATION_ADDR1_ADDR, addr1);
 178 }
 179
 180 static u32 xgene_enet_link_status(struct xgene_enet_pdata *p)
 181 {
 182         u32 data;
 183
 184         data = xgene_mii_phy_read(p, INT_PHY_ADDR,
 185                                   SGMII_BASE_PAGE_ABILITY_ADDR >> 2);
 186
 187         if (LINK_SPEED(data) == PHY_SPEED_1000)
 188                 p->phy_speed = SPEED_1000;
 189         else if (LINK_SPEED(data) == PHY_SPEED_100)
 190                 p->phy_speed = SPEED_100;
 191         else
 192                 p->phy_speed = SPEED_10;
 193
 194         return data & LINK_UP;
 195 }
 196
 197 static void xgene_sgmii_configure(struct xgene_enet_pdata *p)
 198 {
 199         xgene_mii_phy_write(p, INT_PHY_ADDR, SGMII_TBI_CONTROL_ADDR >> 2,
 200                             0x8000);
 201         xgene_mii_phy_write(p, INT_PHY_ADDR, SGMII_CONTROL_ADDR >> 2, 0x9000);
 202         xgene_mii_phy_write(p, INT_PHY_ADDR, SGMII_TBI_CONTROL_ADDR >> 2, 0);
 203 }
 204
 205 static void xgene_sgmii_tbi_control_reset(struct xgene_enet_pdata *p)
 206 {
 207         xgene_mii_phy_write(p, INT_PHY_ADDR, SGMII_TBI_CONTROL_ADDR >> 2,
 208                             0x8000);
 209         xgene_mii_phy_write(p, INT_PHY_ADDR, SGMII_TBI_CONTROL_ADDR >> 2, 0);
 210 }
 211
 212 static void xgene_sgmii_reset(struct xgene_enet_pdata *p)
 213 {
 214         u32 value;
 215
 216         if (p->phy_speed == SPEED_UNKNOWN)
 217                 return;
 218
 219         value = xgene_mii_phy_read(p, INT_PHY_ADDR,
 220                                    SGMII_BASE_PAGE_ABILITY_ADDR >> 2);
 221         if (!(value & LINK_UP))
 222                 xgene_sgmii_tbi_control_reset(p);
 223 }
 224
 225 static void xgene_sgmac_set_speed(struct xgene_enet_pdata *p)
 226 {
 227         u32 icm0_addr, icm2_addr, debug_addr;
 228         u32 icm0, icm2, intf_ctl;
 229         u32 mc2, value;
 230
 231         xgene_sgmii_reset(p);
 232
 233         if (p->enet_id == XGENE_ENET1) {
 234                 icm0_addr = ICM_CONFIG0_REG_0_ADDR + p->port_id * OFFSET_8;
 235                 icm2_addr = ICM_CONFIG2_REG_0_ADDR + p->port_id * OFFSET_4;
 236                 debug_addr = DEBUG_REG_ADDR;
 237         } else {
 238                 icm0_addr = XG_MCX_ICM_CONFIG0_REG_0_ADDR;
 239                 icm2_addr = XG_MCX_ICM_CONFIG2_REG_0_ADDR;
 240                 debug_addr = XG_DEBUG_REG_ADDR;
 241         }
 242
 243         icm0 = xgene_enet_rd_mcx_csr(p, icm0_addr);
 244         icm2 = xgene_enet_rd_mcx_csr(p, icm2_addr);
 245         mc2 = xgene_enet_rd_mac(p, MAC_CONFIG_2_ADDR);
 246         intf_ctl = xgene_enet_rd_mac(p, INTERFACE_CONTROL_ADDR);
 247
 248         switch (p->phy_speed) {
 249         case SPEED_10:
 250                 ENET_INTERFACE_MODE2_SET(&mc2, 1);
 251                 intf_ctl &= ~(ENET_LHD_MODE | ENET_GHD_MODE);
 252                 CFG_MACMODE_SET(&icm0, 0);
 253                 CFG_WAITASYNCRD_SET(&icm2, 500);
 254                 break;
 255         case SPEED_100:
 256                 ENET_INTERFACE_MODE2_SET(&mc2, 1);
 257                 intf_ctl &= ~ENET_GHD_MODE;
 258                 intf_ctl |= ENET_LHD_MODE;
 259                 CFG_MACMODE_SET(&icm0, 1);
 260                 CFG_WAITASYNCRD_SET(&icm2, 80);
 261                 break;
 262         default:
 263                 ENET_INTERFACE_MODE2_SET(&mc2, 2);
 264                 intf_ctl &= ~ENET_LHD_MODE;
 265                 intf_ctl |= ENET_GHD_MODE;
 266                 CFG_MACMODE_SET(&icm0, 2);
 267                 CFG_WAITASYNCRD_SET(&icm2, 16);
 268                 value = xgene_enet_rd_csr(p, debug_addr);
 269                 value |= CFG_BYPASS_UNISEC_TX | CFG_BYPASS_UNISEC_RX;
 270                 xgene_enet_wr_csr(p, debug_addr, value);
 271                 break;
 272         }
 273
 274         mc2 |= FULL_DUPLEX2 | PAD_CRC;
 275         xgene_enet_wr_mac(p, MAC_CONFIG_2_ADDR, mc2);
 276         xgene_enet_wr_mac(p, INTERFACE_CONTROL_ADDR, intf_ctl);
 277         xgene_enet_wr_mcx_csr(p, icm0_addr, icm0);
 278         xgene_enet_wr_mcx_csr(p, icm2_addr, icm2);
 279 }
 280
 281 static void xgene_sgmac_set_frame_size(struct xgene_enet_pdata *pdata, int size)
 282 {
 283         xgene_enet_wr_mac(pdata, MAX_FRAME_LEN_ADDR, size);
 284 }
 285
 286 static void xgene_sgmii_enable_autoneg(struct xgene_enet_pdata *p)
 287 {
 288         u32 data, loop = 10;
 289
 290         xgene_sgmii_configure(p);
 291
 292         while (loop--) {
 293                 data = xgene_mii_phy_read(p, INT_PHY_ADDR,
 294                                           SGMII_STATUS_ADDR >> 2);
 295                 if ((data & AUTO_NEG_COMPLETE) && (data & LINK_STATUS))
 296                         break;
 297                 usleep_range(1000, 2000);
 298         }
 299         if (!(data & AUTO_NEG_COMPLETE) || !(data & LINK_STATUS))
 300                 netdev_err(p->ndev, "Auto-negotiation failed\n");
 301 }
 302
 303 static void xgene_sgmac_rxtx(struct xgene_enet_pdata *p, u32 bits, bool set)
 304 {
 305         u32 data;
 306
 307         data = xgene_enet_rd_mac(p, MAC_CONFIG_1_ADDR);
 308
 309         if (set)
 310                 data |= bits;
 311         else
 312                 data &= ~bits;
 313
 314         xgene_enet_wr_mac(p, MAC_CONFIG_1_ADDR, data);
 315 }
 316
 317 static void xgene_sgmac_flowctl_tx(struct xgene_enet_pdata *p, bool enable)
 318 {
 319         xgene_sgmac_rxtx(p, TX_FLOW_EN, enable);
 320
 321         p->mac_ops->enable_tx_pause(p, enable);
 322 }
 323
 324 static void xgene_sgmac_flowctl_rx(struct xgene_enet_pdata *pdata, bool enable)
 325 {
 326         xgene_sgmac_rxtx(pdata, RX_FLOW_EN, enable);
 327 }
 328
 329 static void xgene_sgmac_init(struct xgene_enet_pdata *p)
 330 {
 331         u32 pause_thres_reg, pause_off_thres_reg;
 332         u32 enet_spare_cfg_reg, rsif_config_reg;
 333         u32 cfg_bypass_reg, rx_dv_gate_reg;
 334         u32 data, data1, data2, offset;
 335         u32 multi_dpf_reg;
 336
 337         if (!(p->enet_id == XGENE_ENET2 && p->mdio_driver))
 338                 xgene_sgmac_reset(p);
 339
 340         xgene_sgmii_enable_autoneg(p);
 341         xgene_sgmac_set_speed(p);
 342         xgene_sgmac_set_mac_addr(p);
 343
 344         if (p->enet_id == XGENE_ENET1) {
 345                 enet_spare_cfg_reg = ENET_SPARE_CFG_REG_ADDR;
 346                 rsif_config_reg = RSIF_CONFIG_REG_ADDR;
 347                 cfg_bypass_reg = CFG_BYPASS_ADDR;
 348                 offset = p->port_id * OFFSET_4;
 349                 rx_dv_gate_reg = SG_RX_DV_GATE_REG_0_ADDR + offset;
 350         } else {
 351                 enet_spare_cfg_reg = XG_ENET_SPARE_CFG_REG_ADDR;
 352                 rsif_config_reg = XG_RSIF_CONFIG_REG_ADDR;
 353                 cfg_bypass_reg = XG_CFG_BYPASS_ADDR;
 354                 rx_dv_gate_reg = XG_MCX_RX_DV_GATE_REG_0_ADDR;
 355         }
 356
 357         data = xgene_enet_rd_csr(p, enet_spare_cfg_reg);
 358         data |= MPA_IDLE_WITH_QMI_EMPTY;
 359         xgene_enet_wr_csr(p, enet_spare_cfg_reg, data);
 360
 361         /* Adjust MDC clock frequency */
 362         data = xgene_enet_rd_mac(p, MII_MGMT_CONFIG_ADDR);
 363         MGMT_CLOCK_SEL_SET(&data, 7);
 364         xgene_enet_wr_mac(p, MII_MGMT_CONFIG_ADDR, data);
 365
 366         /* Enable drop if bufpool not available */
 367         data = xgene_enet_rd_csr(p, rsif_config_reg);
 368         data |= CFG_RSIF_FPBUFF_TIMEOUT_EN;
 369         xgene_enet_wr_csr(p, rsif_config_reg, data);
 370
 371         /* Configure HW pause frame generation */
 372         multi_dpf_reg = (p->enet_id == XGENE_ENET1) ? CSR_MULTI_DPF0_ADDR :
 373                          XG_MCX_MULTI_DPF0_ADDR;
 374         data = xgene_enet_rd_mcx_csr(p, multi_dpf_reg);
 375         data = (DEF_QUANTA << 16) | (data & 0xffff);
 376         xgene_enet_wr_mcx_csr(p, multi_dpf_reg, data);
 377
 378         if (p->enet_id != XGENE_ENET1) {
 379                 data = xgene_enet_rd_mcx_csr(p, XG_MCX_MULTI_DPF1_ADDR);
 380                 data =  (NORM_PAUSE_OPCODE << 16) | (data & 0xFFFF);
 381                 xgene_enet_wr_mcx_csr(p, XG_MCX_MULTI_DPF1_ADDR, data);
 382         }
 383
 384         pause_thres_reg = (p->enet_id == XGENE_ENET1) ? RXBUF_PAUSE_THRESH :
 385                            XG_RXBUF_PAUSE_THRESH;
 386         pause_off_thres_reg = (p->enet_id == XGENE_ENET1) ?
 387                                RXBUF_PAUSE_OFF_THRESH : 0;
 388
 389         if (p->enet_id == XGENE_ENET1) {
 390                 data1 = xgene_enet_rd_csr(p, pause_thres_reg);
 391                 data2 = xgene_enet_rd_csr(p, pause_off_thres_reg);
 392
 393                 if (!(p->port_id % 2)) {
 394                         data1 = (data1 & 0xffff0000) | DEF_PAUSE_THRES;
 395                         data2 = (data2 & 0xffff0000) | DEF_PAUSE_OFF_THRES;
 396                 } else {
 397                         data1 = (data1 & 0xffff) | (DEF_PAUSE_THRES << 16);
 398                         data2 = (data2 & 0xffff) | (DEF_PAUSE_OFF_THRES << 16);
 399                 }
 400
 401                 xgene_enet_wr_csr(p, pause_thres_reg, data1);
 402                 xgene_enet_wr_csr(p, pause_off_thres_reg, data2);
 403         } else {
 404                 data = (DEF_PAUSE_OFF_THRES << 16) | DEF_PAUSE_THRES;
 405                 xgene_enet_wr_csr(p, pause_thres_reg, data);
 406         }
 407
 408         xgene_sgmac_flowctl_tx(p, p->tx_pause);
 409         xgene_sgmac_flowctl_rx(p, p->rx_pause);
 410
 411         /* Bypass traffic gating */
 412         xgene_enet_wr_csr(p, XG_ENET_SPARE_CFG_REG_1_ADDR, 0x84);
 413         xgene_enet_wr_csr(p, cfg_bypass_reg, RESUME_TX);
 414         xgene_enet_wr_mcx_csr(p, rx_dv_gate_reg, RESUME_RX0);
 415 }
 416
 417 static void xgene_sgmac_rx_enable(struct xgene_enet_pdata *p)
 418 {
 419         xgene_sgmac_rxtx(p, RX_EN, true);
 420 }
 421
 422 static void xgene_sgmac_tx_enable(struct xgene_enet_pdata *p)
 423 {
 424         xgene_sgmac_rxtx(p, TX_EN, true);
 425 }
 426
 427 static void xgene_sgmac_rx_disable(struct xgene_enet_pdata *p)
 428 {
 429         xgene_sgmac_rxtx(p, RX_EN, false);
 430 }
 431
 432 static void xgene_sgmac_tx_disable(struct xgene_enet_pdata *p)
 433 {
 434         xgene_sgmac_rxtx(p, TX_EN, false);
 435 }
 436
 437 static int xgene_enet_reset(struct xgene_enet_pdata *p)
 438 {
 439         struct device *dev = &p->pdev->dev;
 440
 441         if (!xgene_ring_mgr_init(p))
 442                 return -ENODEV;
 443
 444         if (p->mdio_driver && p->enet_id == XGENE_ENET2) {
 445                 xgene_enet_config_ring_if_assoc(p);
 446                 return 0;
 447         }
 448
 449         if (p->enet_id == XGENE_ENET2)
 450                 xgene_enet_wr_clkrst_csr(p, XGENET_CONFIG_REG_ADDR, SGMII_EN);
 451
 452         if (dev->of_node) {
 453                 if (!IS_ERR(p->clk)) {
 454                         clk_prepare_enable(p->clk);
 455                         udelay(5);
 456                         clk_disable_unprepare(p->clk);
 457                         udelay(5);
 458                         clk_prepare_enable(p->clk);
 459                         udelay(5);
 460                 }
 461         } else {
 462 #ifdef CONFIG_ACPI
 463                 acpi_status status;
 464
 465                 status = acpi_evaluate_object(ACPI_HANDLE(&p->pdev->dev),
 466                                               "_RST", NULL, NULL);
 467                 if (ACPI_FAILURE(status)) {
 468                         acpi_evaluate_object(ACPI_HANDLE(&p->pdev->dev),
 469                                              "_INI", NULL, NULL);
 470                 }
 471 #endif
 472         }
 473
 474         if (!p->port_id) {
 475                 xgene_enet_ecc_init(p);
 476                 xgene_enet_config_ring_if_assoc(p);
 477         }
 478
 479         return 0;
 480 }
 481
 482 static void xgene_enet_cle_bypass(struct xgene_enet_pdata *p,
 483                                   u32 dst_ring_num, u16 bufpool_id,
 484                                   u16 nxtbufpool_id)
 485 {
 486         u32 cle_bypass_reg0, cle_bypass_reg1;
 487         u32 offset = p->port_id * MAC_OFFSET;
 488         u32 data, fpsel, nxtfpsel;
 489
 490         if (p->enet_id == XGENE_ENET1) {
 491                 cle_bypass_reg0 = CLE_BYPASS_REG0_0_ADDR;
 492                 cle_bypass_reg1 = CLE_BYPASS_REG1_0_ADDR;
 493         } else {
 494                 cle_bypass_reg0 = XCLE_BYPASS_REG0_ADDR;
 495                 cle_bypass_reg1 = XCLE_BYPASS_REG1_ADDR;
 496         }
 497
 498         data = CFG_CLE_BYPASS_EN0;
 499         xgene_enet_wr_csr(p, cle_bypass_reg0 + offset, data);
 500
 501         fpsel = xgene_enet_get_fpsel(bufpool_id);
 502         nxtfpsel = xgene_enet_get_fpsel(nxtbufpool_id);
 503         data = CFG_CLE_DSTQID0(dst_ring_num) | CFG_CLE_FPSEL0(fpsel) |
 504                CFG_CLE_NXTFPSEL0(nxtfpsel);
 505         xgene_enet_wr_csr(p, cle_bypass_reg1 + offset, data);
 506 }
 507
 508 static void xgene_enet_clear(struct xgene_enet_pdata *pdata,
 509                              struct xgene_enet_desc_ring *ring)
 510 {
 511         u32 addr, data;
 512
 513         if (xgene_enet_is_bufpool(ring->id)) {
 514                 addr = ENET_CFGSSQMIFPRESET_ADDR;
 515                 data = BIT(xgene_enet_get_fpsel(ring->id));
 516         } else {
 517                 addr = ENET_CFGSSQMIWQRESET_ADDR;
 518                 data = BIT(xgene_enet_ring_bufnum(ring->id));
 519         }
 520
 521         xgene_enet_wr_ring_if(pdata, addr, data);
 522 }
 523
 524 static void xgene_enet_shutdown(struct xgene_enet_pdata *p)
 525 {
 526         struct device *dev = &p->pdev->dev;
 527
 528         if (dev->of_node) {
 529                 if (!IS_ERR(p->clk))
 530                         clk_disable_unprepare(p->clk);
 531         }
 532 }
 533
 534 static void xgene_enet_link_state(struct work_struct *work)
 535 {
 536         struct xgene_enet_pdata *p = container_of(to_delayed_work(work),
 537                                      struct xgene_enet_pdata, link_work);
 538         struct net_device *ndev = p->ndev;
 539         u32 link, poll_interval;
 540
 541         link = xgene_enet_link_status(p);
 542         if (link) {
 543                 if (!netif_carrier_ok(ndev)) {
 544                         netif_carrier_on(ndev);
 545                         xgene_sgmac_set_speed(p);
 546                         xgene_sgmac_rx_enable(p);
 547                         xgene_sgmac_tx_enable(p);
 548                         netdev_info(ndev, "Link is Up - %dMbps\n",
 549                                     p->phy_speed);
 550                 }
 551                 poll_interval = PHY_POLL_LINK_ON;
 552         } else {
 553                 if (netif_carrier_ok(ndev)) {
 554                         xgene_sgmac_rx_disable(p);
 555                         xgene_sgmac_tx_disable(p);
 556                         netif_carrier_off(ndev);
 557                         netdev_info(ndev, "Link is Down\n");
 558                 }
 559                 poll_interval = PHY_POLL_LINK_OFF;
 560         }
 561
 562         schedule_delayed_work(&p->link_work, poll_interval);
 563 }
 564
 565 static void xgene_sgmac_enable_tx_pause(struct xgene_enet_pdata *p, bool enable)
 566 {
 567         u32 data, ecm_cfg_addr;
 568
 569         if (p->enet_id == XGENE_ENET1) {
 570                 ecm_cfg_addr = (!(p->port_id % 2)) ? CSR_ECM_CFG_0_ADDR :
 571                                 CSR_ECM_CFG_1_ADDR;
 572         } else {
 573                 ecm_cfg_addr = XG_MCX_ECM_CFG_0_ADDR;
 574         }
 575
 576         data = xgene_enet_rd_mcx_csr(p, ecm_cfg_addr);
 577         if (enable)
 578                 data |= MULTI_DPF_AUTOCTRL | PAUSE_XON_EN;
 579         else
 580                 data &= ~(MULTI_DPF_AUTOCTRL | PAUSE_XON_EN);
 581         xgene_enet_wr_mcx_csr(p, ecm_cfg_addr, data);
 582 }
 583
 584 const struct xgene_mac_ops xgene_sgmac_ops = {
 585         .init           = xgene_sgmac_init,
 586         .reset          = xgene_sgmac_reset,
 587         .rx_enable      = xgene_sgmac_rx_enable,
 588         .tx_enable      = xgene_sgmac_tx_enable,
 589         .rx_disable     = xgene_sgmac_rx_disable,
 590         .tx_disable     = xgene_sgmac_tx_disable,
 591         .get_drop_cnt   = xgene_sgmac_get_drop_cnt,
 592         .set_speed      = xgene_sgmac_set_speed,
 593         .set_mac_addr   = xgene_sgmac_set_mac_addr,
 594         .set_framesize  = xgene_sgmac_set_frame_size,
 595         .link_state     = xgene_enet_link_state,
 596         .enable_tx_pause = xgene_sgmac_enable_tx_pause,
 597         .flowctl_tx     = xgene_sgmac_flowctl_tx,
 598         .flowctl_rx     = xgene_sgmac_flowctl_rx
 599 };
 600
 601 const struct xgene_port_ops xgene_sgport_ops = {
 602         .reset          = xgene_enet_reset,
 603         .clear          = xgene_enet_clear,
 604         .cle_bypass     = xgene_enet_cle_bypass,
 605         .shutdown       = xgene_enet_shutdown
 606 };