1 /* Applied Micro X-Gene SoC Ethernet Driver
3 * Copyright (c) 2014, Applied Micro Circuits Corporation
4 * Authors: Iyappan Subramanian <isubramanian@apm.com>
5 * Ravi Patel <rapatel@apm.com>
6 * Keyur Chudgar <kchudgar@apm.com>
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program. If not, see <http://www.gnu.org/licenses/>.
22 #ifndef __XGENE_ENET_HW_H__
23 #define __XGENE_ENET_HW_H__
25 #include "xgene_enet_main.h"
27 struct xgene_enet_pdata;
28 struct xgene_enet_stats;
29 struct xgene_enet_desc_ring;
31 /* clears and then set bits */
32 static inline void xgene_set_bits(u32 *dst, u32 val, u32 start, u32 len)
34 u32 end = start + len - 1;
35 u32 mask = GENMASK(end, start);
38 *dst |= (val << start) & mask;
41 static inline u32 xgene_get_bits(u32 val, u32 start, u32 end)
43 return (val & GENMASK(end, start)) >> start;
52 #define CSR_RING_ID 0x0008
53 #define OVERWRITE BIT(31)
54 #define IS_BUFFER_POOL BIT(20)
55 #define PREFETCH_BUF_EN BIT(21)
56 #define CSR_RING_ID_BUF 0x000c
57 #define CSR_RING_NE_INT_MODE 0x017c
58 #define CSR_RING_CONFIG 0x006c
59 #define CSR_RING_WR_BASE 0x0070
60 #define NUM_RING_CONFIG 5
61 #define BUFPOOL_MODE 3
62 #define INC_DEC_CMD_ADDR 0x002c
63 #define UDP_HDR_SIZE 2
64 #define BUF_LEN_CODE_2K 0x5000
66 #define CREATE_MASK(pos, len) GENMASK((pos)+(len)-1, (pos))
67 #define CREATE_MASK_ULL(pos, len) GENMASK_ULL((pos)+(len)-1, (pos))
69 /* Empty slot soft signature */
70 #define EMPTY_SLOT_INDEX 1
71 #define EMPTY_SLOT ~0ULL
73 #define WORK_DESC_SIZE 32
74 #define BUFPOOL_DESC_SIZE 16
76 #define RING_OWNER_MASK GENMASK(9, 6)
77 #define RING_BUFNUM_MASK GENMASK(5, 0)
79 #define SELTHRSH_POS 3
80 #define SELTHRSH_LEN 3
81 #define RINGADDRL_POS 5
82 #define RINGADDRL_LEN 27
83 #define RINGADDRH_POS 0
84 #define RINGADDRH_LEN 6
85 #define RINGSIZE_POS 23
86 #define RINGSIZE_LEN 3
87 #define RINGTYPE_POS 19
88 #define RINGTYPE_LEN 2
89 #define RINGMODE_POS 20
90 #define RINGMODE_LEN 3
91 #define RECOMTIMEOUTL_POS 28
92 #define RECOMTIMEOUTL_LEN 3
93 #define RECOMTIMEOUTH_POS 0
94 #define RECOMTIMEOUTH_LEN 2
95 #define NUMMSGSINQ_POS 1
96 #define NUMMSGSINQ_LEN 16
97 #define ACCEPTLERR BIT(19)
98 #define QCOHERENT BIT(4)
99 #define RECOMBBUF BIT(27)
101 #define MAC_OFFSET 0x30
103 #define BLOCK_ETH_CSR_OFFSET 0x2000
104 #define BLOCK_ETH_RING_IF_OFFSET 0x9000
105 #define BLOCK_ETH_CLKRST_CSR_OFFSET 0xc000
106 #define BLOCK_ETH_DIAG_CSR_OFFSET 0xD000
107 #define BLOCK_ETH_MAC_OFFSET 0x0000
108 #define BLOCK_ETH_MAC_CSR_OFFSET 0x2800
110 #define CLKEN_ADDR 0xc208
111 #define SRST_ADDR 0xc200
113 #define MAC_ADDR_REG_OFFSET 0x00
114 #define MAC_COMMAND_REG_OFFSET 0x04
115 #define MAC_WRITE_REG_OFFSET 0x08
116 #define MAC_READ_REG_OFFSET 0x0c
117 #define MAC_COMMAND_DONE_REG_OFFSET 0x10
119 #define MII_MGMT_CONFIG_ADDR 0x20
120 #define MII_MGMT_COMMAND_ADDR 0x24
121 #define MII_MGMT_ADDRESS_ADDR 0x28
122 #define MII_MGMT_CONTROL_ADDR 0x2c
123 #define MII_MGMT_STATUS_ADDR 0x30
124 #define MII_MGMT_INDICATORS_ADDR 0x34
126 #define BUSY_MASK BIT(0)
127 #define READ_CYCLE_MASK BIT(0)
128 #define PHY_CONTROL_SET(dst, val) xgene_set_bits(dst, val, 0, 16)
130 #define ENET_SPARE_CFG_REG_ADDR 0x0750
131 #define RSIF_CONFIG_REG_ADDR 0x0010
132 #define RSIF_RAM_DBG_REG0_ADDR 0x0048
133 #define RGMII_REG_0_ADDR 0x07e0
134 #define CFG_LINK_AGGR_RESUME_0_ADDR 0x07c8
135 #define DEBUG_REG_ADDR 0x0700
136 #define CFG_BYPASS_ADDR 0x0294
137 #define CLE_BYPASS_REG0_0_ADDR 0x0490
138 #define CLE_BYPASS_REG1_0_ADDR 0x0494
139 #define CFG_RSIF_FPBUFF_TIMEOUT_EN BIT(31)
140 #define RESUME_TX BIT(0)
141 #define CFG_SPEED_1250 BIT(24)
142 #define TX_PORT0 BIT(0)
143 #define CFG_BYPASS_UNISEC_TX BIT(2)
144 #define CFG_BYPASS_UNISEC_RX BIT(1)
145 #define CFG_CLE_BYPASS_EN0 BIT(31)
146 #define CFG_TXCLK_MUXSEL0_SET(dst, val) xgene_set_bits(dst, val, 29, 3)
147 #define CFG_RXCLK_MUXSEL0_SET(dst, val) xgene_set_bits(dst, val, 26, 3)
149 #define CFG_CLE_IP_PROTOCOL0_SET(dst, val) xgene_set_bits(dst, val, 16, 2)
150 #define CFG_CLE_DSTQID0_SET(dst, val) xgene_set_bits(dst, val, 0, 12)
151 #define CFG_CLE_FPSEL0_SET(dst, val) xgene_set_bits(dst, val, 16, 4)
152 #define CFG_MACMODE_SET(dst, val) xgene_set_bits(dst, val, 18, 2)
153 #define CFG_WAITASYNCRD_SET(dst, val) xgene_set_bits(dst, val, 0, 16)
154 #define CFG_CLE_DSTQID0(val) (val & GENMASK(11, 0))
155 #define CFG_CLE_FPSEL0(val) ((val << 16) & GENMASK(19, 16))
156 #define ICM_CONFIG0_REG_0_ADDR 0x0400
157 #define ICM_CONFIG2_REG_0_ADDR 0x0410
158 #define RX_DV_GATE_REG_0_ADDR 0x05fc
159 #define TX_DV_GATE_EN0 BIT(2)
160 #define RX_DV_GATE_EN0 BIT(1)
161 #define RESUME_RX0 BIT(0)
162 #define ENET_CFGSSQMIWQASSOC_ADDR 0xe0
163 #define ENET_CFGSSQMIFPQASSOC_ADDR 0xdc
164 #define ENET_CFGSSQMIQMLITEFPQASSOC_ADDR 0xf0
165 #define ENET_CFGSSQMIQMLITEWQASSOC_ADDR 0xf4
166 #define ENET_CFG_MEM_RAM_SHUTDOWN_ADDR 0x70
167 #define ENET_BLOCK_MEM_RDY_ADDR 0x74
168 #define MAC_CONFIG_1_ADDR 0x00
169 #define MAC_CONFIG_2_ADDR 0x04
170 #define MAX_FRAME_LEN_ADDR 0x10
171 #define INTERFACE_CONTROL_ADDR 0x38
172 #define STATION_ADDR0_ADDR 0x40
173 #define STATION_ADDR1_ADDR 0x44
174 #define PHY_ADDR_SET(dst, val) xgene_set_bits(dst, val, 8, 5)
175 #define REG_ADDR_SET(dst, val) xgene_set_bits(dst, val, 0, 5)
176 #define ENET_INTERFACE_MODE2_SET(dst, val) xgene_set_bits(dst, val, 8, 2)
177 #define MGMT_CLOCK_SEL_SET(dst, val) xgene_set_bits(dst, val, 0, 3)
178 #define SOFT_RESET1 BIT(31)
181 #define ENET_LHD_MODE BIT(25)
182 #define ENET_GHD_MODE BIT(26)
183 #define FULL_DUPLEX2 BIT(0)
184 #define PAD_CRC BIT(2)
185 #define SCAN_AUTO_INCR BIT(5)
186 #define TBYT_ADDR 0x38
187 #define TPKT_ADDR 0x39
188 #define TDRP_ADDR 0x45
189 #define TFCS_ADDR 0x47
190 #define TUND_ADDR 0x4a
192 #define TSO_IPPROTO_TCP 1
194 #define USERINFO_POS 0
195 #define USERINFO_LEN 32
196 #define FPQNUM_POS 32
197 #define FPQNUM_LEN 12
206 #define BUFDATALEN_POS 48
207 #define BUFDATALEN_LEN 15
208 #define DATAADDR_POS 0
209 #define DATAADDR_LEN 42
210 #define COHERENT_POS 63
211 #define HENQNUM_POS 48
212 #define HENQNUM_LEN 12
213 #define TYPESEL_POS 44
214 #define TYPESEL_LEN 4
215 #define ETHHDR_POS 12
217 #define IC_POS 35 /* Insert CRC */
222 #define EC_POS 22 /* Enable checksum */
224 #define ET_POS 23 /* Enable TSO */
225 #define IS_POS 24 /* IP protocol select */
227 #define TYPE_ETH_WORK_MESSAGE_POS 44
228 #define LL_BYTES_MSB_POS 56
229 #define LL_BYTES_MSB_LEN 8
230 #define LL_BYTES_LSB_POS 48
231 #define LL_BYTES_LSB_LEN 12
232 #define LL_LEN_POS 48
234 #define DATALEN_MASK GENMASK(11, 0)
236 #define LAST_BUFFER (0x7800ULL << BUFDATALEN_POS)
238 struct xgene_enet_raw_desc {
245 struct xgene_enet_raw_desc16 {
250 static inline void xgene_enet_mark_desc_slot_empty(void *desc_slot_ptr)
252 __le64 *desc_slot = desc_slot_ptr;
254 desc_slot[EMPTY_SLOT_INDEX] = cpu_to_le64(EMPTY_SLOT);
257 static inline bool xgene_enet_is_desc_slot_empty(void *desc_slot_ptr)
259 __le64 *desc_slot = desc_slot_ptr;
261 return (desc_slot[EMPTY_SLOT_INDEX] == cpu_to_le64(EMPTY_SLOT));
264 enum xgene_enet_ring_cfgsize {
273 enum xgene_enet_ring_type {
279 enum xgene_ring_owner {
286 enum xgene_enet_ring_bufnum {
287 RING_BUFNUM_REGULAR = 0x0,
288 RING_BUFNUM_BUFPOOL = 0x20,
292 enum xgene_enet_cmd {
293 XGENE_ENET_WR_CMD = BIT(31),
294 XGENE_ENET_RD_CMD = BIT(30)
297 enum xgene_enet_err_code {
301 BUFPOOL_TIMEOUT = 15,
303 INGRESS_CHECKSUM = 17,
304 INGRESS_TRUNC_FRAME = 18,
305 INGRESS_PKT_LEN = 19,
306 INGRESS_PKT_UNDER = 20,
307 INGRESS_FIFO_OVERRUN = 21,
308 INGRESS_CHECKSUM_COMPUTE = 26,
312 static inline enum xgene_ring_owner xgene_enet_ring_owner(u16 id)
314 return (id & RING_OWNER_MASK) >> 6;
317 static inline u8 xgene_enet_ring_bufnum(u16 id)
319 return id & RING_BUFNUM_MASK;
322 static inline bool xgene_enet_is_bufpool(u16 id)
324 return ((id & RING_BUFNUM_MASK) >= 0x20) ? true : false;
327 static inline u16 xgene_enet_get_numslots(u16 id, u32 size)
329 bool is_bufpool = xgene_enet_is_bufpool(id);
331 return (is_bufpool) ? size / BUFPOOL_DESC_SIZE :
332 size / WORK_DESC_SIZE;
335 void xgene_enet_parse_error(struct xgene_enet_desc_ring *ring,
336 struct xgene_enet_pdata *pdata,
337 enum xgene_enet_err_code status);
339 int xgene_enet_mdio_config(struct xgene_enet_pdata *pdata);
340 void xgene_enet_mdio_remove(struct xgene_enet_pdata *pdata);
341 bool xgene_ring_mgr_init(struct xgene_enet_pdata *p);
343 extern const struct xgene_mac_ops xgene_gmac_ops;
344 extern const struct xgene_port_ops xgene_gport_ops;
345 extern struct xgene_ring_ops xgene_ring1_ops;
347 #endif /* __XGENE_ENET_HW_H__ */