1 /* Applied Micro X-Gene SoC Ethernet Driver
3 * Copyright (c) 2014, Applied Micro Circuits Corporation
4 * Authors: Iyappan Subramanian <isubramanian@apm.com>
5 * Ravi Patel <rapatel@apm.com>
6 * Keyur Chudgar <kchudgar@apm.com>
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program. If not, see <http://www.gnu.org/licenses/>.
22 #ifndef __XGENE_ENET_HW_H__
23 #define __XGENE_ENET_HW_H__
25 #include "xgene_enet_main.h"
27 struct xgene_enet_pdata;
28 struct xgene_enet_stats;
30 /* clears and then set bits */
31 static inline void xgene_set_bits(u32 *dst, u32 val, u32 start, u32 len)
33 u32 end = start + len - 1;
34 u32 mask = GENMASK(end, start);
37 *dst |= (val << start) & mask;
40 static inline u32 xgene_get_bits(u32 val, u32 start, u32 end)
42 return (val & GENMASK(end, start)) >> start;
45 #define CSR_RING_ID 0x0008
46 #define OVERWRITE BIT(31)
47 #define IS_BUFFER_POOL BIT(20)
48 #define PREFETCH_BUF_EN BIT(21)
49 #define CSR_RING_ID_BUF 0x000c
50 #define CSR_RING_NE_INT_MODE 0x017c
51 #define CSR_RING_CONFIG 0x006c
52 #define CSR_RING_WR_BASE 0x0070
53 #define NUM_RING_CONFIG 5
54 #define BUFPOOL_MODE 3
56 #define INC_DEC_CMD_ADDR 0x002c
57 #define UDP_HDR_SIZE 2
58 #define BUF_LEN_CODE_2K 0x5000
60 #define CREATE_MASK(pos, len) GENMASK((pos)+(len)-1, (pos))
61 #define CREATE_MASK_ULL(pos, len) GENMASK_ULL((pos)+(len)-1, (pos))
63 /* Empty slot soft signature */
64 #define EMPTY_SLOT_INDEX 1
65 #define EMPTY_SLOT ~0ULL
67 #define WORK_DESC_SIZE 32
68 #define BUFPOOL_DESC_SIZE 16
70 #define RING_OWNER_MASK GENMASK(9, 6)
71 #define RING_BUFNUM_MASK GENMASK(5, 0)
73 #define SELTHRSH_POS 3
74 #define SELTHRSH_LEN 3
75 #define RINGADDRL_POS 5
76 #define RINGADDRL_LEN 27
77 #define RINGADDRH_POS 0
78 #define RINGADDRH_LEN 6
79 #define RINGSIZE_POS 23
80 #define RINGSIZE_LEN 3
81 #define RINGTYPE_POS 19
82 #define RINGTYPE_LEN 2
83 #define RINGMODE_POS 20
84 #define RINGMODE_LEN 3
85 #define RECOMTIMEOUTL_POS 28
86 #define RECOMTIMEOUTL_LEN 3
87 #define RECOMTIMEOUTH_POS 0
88 #define RECOMTIMEOUTH_LEN 2
89 #define NUMMSGSINQ_POS 1
90 #define NUMMSGSINQ_LEN 16
91 #define ACCEPTLERR BIT(19)
92 #define QCOHERENT BIT(4)
93 #define RECOMBBUF BIT(27)
95 #define BLOCK_ETH_CSR_OFFSET 0x2000
96 #define BLOCK_ETH_RING_IF_OFFSET 0x9000
97 #define BLOCK_ETH_CLKRST_CSR_OFFSET 0xC000
98 #define BLOCK_ETH_DIAG_CSR_OFFSET 0xD000
100 #define BLOCK_ETH_MAC_OFFSET 0x0000
101 #define BLOCK_ETH_STATS_OFFSET 0x0014
102 #define BLOCK_ETH_MAC_CSR_OFFSET 0x2800
104 #define MAC_ADDR_REG_OFFSET 0x00
105 #define MAC_COMMAND_REG_OFFSET 0x04
106 #define MAC_WRITE_REG_OFFSET 0x08
107 #define MAC_READ_REG_OFFSET 0x0c
108 #define MAC_COMMAND_DONE_REG_OFFSET 0x10
110 #define STAT_ADDR_REG_OFFSET 0x00
111 #define STAT_COMMAND_REG_OFFSET 0x04
112 #define STAT_WRITE_REG_OFFSET 0x08
113 #define STAT_READ_REG_OFFSET 0x0c
114 #define STAT_COMMAND_DONE_REG_OFFSET 0x10
116 #define MII_MGMT_CONFIG_ADDR 0x20
117 #define MII_MGMT_COMMAND_ADDR 0x24
118 #define MII_MGMT_ADDRESS_ADDR 0x28
119 #define MII_MGMT_CONTROL_ADDR 0x2c
120 #define MII_MGMT_STATUS_ADDR 0x30
121 #define MII_MGMT_INDICATORS_ADDR 0x34
123 #define BUSY_MASK BIT(0)
124 #define READ_CYCLE_MASK BIT(0)
125 #define PHY_CONTROL_SET(dst, val) xgene_set_bits(dst, val, 0, 16)
127 #define ENET_SPARE_CFG_REG_ADDR 0x0750
128 #define RSIF_CONFIG_REG_ADDR 0x0010
129 #define RSIF_RAM_DBG_REG0_ADDR 0x0048
130 #define RGMII_REG_0_ADDR 0x07e0
131 #define CFG_LINK_AGGR_RESUME_0_ADDR 0x07c8
132 #define DEBUG_REG_ADDR 0x0700
133 #define CFG_BYPASS_ADDR 0x0294
134 #define CLE_BYPASS_REG0_0_ADDR 0x0490
135 #define CLE_BYPASS_REG1_0_ADDR 0x0494
136 #define CFG_RSIF_FPBUFF_TIMEOUT_EN BIT(31)
137 #define RESUME_TX BIT(0)
138 #define CFG_SPEED_1250 BIT(24)
139 #define TX_PORT0 BIT(0)
140 #define CFG_BYPASS_UNISEC_TX BIT(2)
141 #define CFG_BYPASS_UNISEC_RX BIT(1)
142 #define CFG_CLE_BYPASS_EN0 BIT(31)
143 #define CFG_TXCLK_MUXSEL0_SET(dst, val) xgene_set_bits(dst, val, 29, 3)
145 #define CFG_CLE_IP_PROTOCOL0_SET(dst, val) xgene_set_bits(dst, val, 16, 2)
146 #define CFG_CLE_DSTQID0_SET(dst, val) xgene_set_bits(dst, val, 0, 12)
147 #define CFG_CLE_FPSEL0_SET(dst, val) xgene_set_bits(dst, val, 16, 4)
148 #define CFG_MACMODE_SET(dst, val) xgene_set_bits(dst, val, 18, 2)
149 #define CFG_WAITASYNCRD_SET(dst, val) xgene_set_bits(dst, val, 0, 16)
150 #define ICM_CONFIG0_REG_0_ADDR 0x0400
151 #define ICM_CONFIG2_REG_0_ADDR 0x0410
152 #define RX_DV_GATE_REG_0_ADDR 0x05fc
153 #define TX_DV_GATE_EN0 BIT(2)
154 #define RX_DV_GATE_EN0 BIT(1)
155 #define RESUME_RX0 BIT(0)
156 #define ENET_CFGSSQMIWQASSOC_ADDR 0xe0
157 #define ENET_CFGSSQMIFPQASSOC_ADDR 0xdc
158 #define ENET_CFGSSQMIQMLITEFPQASSOC_ADDR 0xf0
159 #define ENET_CFGSSQMIQMLITEWQASSOC_ADDR 0xf4
160 #define ENET_CFG_MEM_RAM_SHUTDOWN_ADDR 0x70
161 #define ENET_BLOCK_MEM_RDY_ADDR 0x74
162 #define MAC_CONFIG_1_ADDR 0x00
163 #define MAC_CONFIG_2_ADDR 0x04
164 #define MAX_FRAME_LEN_ADDR 0x10
165 #define INTERFACE_CONTROL_ADDR 0x38
166 #define STATION_ADDR0_ADDR 0x40
167 #define STATION_ADDR1_ADDR 0x44
168 #define PHY_ADDR_SET(dst, val) xgene_set_bits(dst, val, 8, 5)
169 #define REG_ADDR_SET(dst, val) xgene_set_bits(dst, val, 0, 5)
170 #define ENET_INTERFACE_MODE2_SET(dst, val) xgene_set_bits(dst, val, 8, 2)
171 #define MGMT_CLOCK_SEL_SET(dst, val) xgene_set_bits(dst, val, 0, 3)
172 #define SOFT_RESET1 BIT(31)
175 #define ENET_LHD_MODE BIT(25)
176 #define ENET_GHD_MODE BIT(26)
177 #define FULL_DUPLEX2 BIT(0)
178 #define SCAN_AUTO_INCR BIT(5)
179 #define TBYT_ADDR 0x38
180 #define TPKT_ADDR 0x39
181 #define TDRP_ADDR 0x45
182 #define TFCS_ADDR 0x47
183 #define TUND_ADDR 0x4a
185 #define TSO_IPPROTO_TCP 1
186 #define FULL_DUPLEX 2
188 #define USERINFO_POS 0
189 #define USERINFO_LEN 32
190 #define FPQNUM_POS 32
191 #define FPQNUM_LEN 12
196 #define BUFDATALEN_POS 48
197 #define BUFDATALEN_LEN 12
198 #define DATAADDR_POS 0
199 #define DATAADDR_LEN 42
200 #define COHERENT_POS 63
201 #define HENQNUM_POS 48
202 #define HENQNUM_LEN 12
203 #define TYPESEL_POS 44
204 #define TYPESEL_LEN 4
205 #define ETHHDR_POS 12
207 #define IC_POS 35 /* Insert CRC */
212 #define EC_POS 22 /* Enable checksum */
214 #define IS_POS 24 /* IP protocol select */
216 #define TYPE_ETH_WORK_MESSAGE_POS 44
218 struct xgene_enet_raw_desc {
225 struct xgene_enet_raw_desc16 {
230 static inline void xgene_enet_mark_desc_slot_empty(void *desc_slot_ptr)
232 __le64 *desc_slot = desc_slot_ptr;
234 desc_slot[EMPTY_SLOT_INDEX] = cpu_to_le64(EMPTY_SLOT);
237 static inline bool xgene_enet_is_desc_slot_empty(void *desc_slot_ptr)
239 __le64 *desc_slot = desc_slot_ptr;
241 return (desc_slot[EMPTY_SLOT_INDEX] == cpu_to_le64(EMPTY_SLOT));
244 enum xgene_enet_ring_cfgsize {
253 enum xgene_enet_ring_type {
259 enum xgene_ring_owner {
265 enum xgene_enet_ring_bufnum {
266 RING_BUFNUM_REGULAR = 0x0,
267 RING_BUFNUM_BUFPOOL = 0x20,
271 enum xgene_enet_cmd {
272 XGENE_ENET_WR_CMD = BIT(31),
273 XGENE_ENET_RD_CMD = BIT(30)
276 enum xgene_enet_err_code {
280 BUFPOOL_TIMEOUT = 15,
282 INGRESS_CHECKSUM = 17,
283 INGRESS_TRUNC_FRAME = 18,
284 INGRESS_PKT_LEN = 19,
285 INGRESS_PKT_UNDER = 20,
286 INGRESS_FIFO_OVERRUN = 21,
287 INGRESS_CHECKSUM_COMPUTE = 26,
291 static inline enum xgene_ring_owner xgene_enet_ring_owner(u16 id)
293 return (id & RING_OWNER_MASK) >> 6;
296 static inline u8 xgene_enet_ring_bufnum(u16 id)
298 return id & RING_BUFNUM_MASK;
301 static inline bool xgene_enet_is_bufpool(u16 id)
303 return ((id & RING_BUFNUM_MASK) >= 0x20) ? true : false;
306 static inline u16 xgene_enet_get_numslots(u16 id, u32 size)
308 bool is_bufpool = xgene_enet_is_bufpool(id);
310 return (is_bufpool) ? size / BUFPOOL_DESC_SIZE :
311 size / WORK_DESC_SIZE;
314 struct xgene_enet_desc_ring *xgene_enet_setup_ring(
315 struct xgene_enet_desc_ring *ring);
316 void xgene_enet_clear_ring(struct xgene_enet_desc_ring *ring);
317 void xgene_enet_parse_error(struct xgene_enet_desc_ring *ring,
318 struct xgene_enet_pdata *pdata,
319 enum xgene_enet_err_code status);
321 void xgene_enet_reset(struct xgene_enet_pdata *priv);
322 void xgene_gmac_reset(struct xgene_enet_pdata *priv);
323 void xgene_gmac_init(struct xgene_enet_pdata *priv, int speed);
324 void xgene_gmac_tx_enable(struct xgene_enet_pdata *priv);
325 void xgene_gmac_rx_enable(struct xgene_enet_pdata *priv);
326 void xgene_gmac_tx_disable(struct xgene_enet_pdata *priv);
327 void xgene_gmac_rx_disable(struct xgene_enet_pdata *priv);
328 void xgene_gmac_set_mac_addr(struct xgene_enet_pdata *pdata);
329 void xgene_enet_cle_bypass(struct xgene_enet_pdata *pdata,
330 u32 dst_ring_num, u16 bufpool_id);
331 void xgene_gport_shutdown(struct xgene_enet_pdata *priv);
332 void xgene_gmac_get_tx_stats(struct xgene_enet_pdata *pdata);
334 int xgene_enet_mdio_config(struct xgene_enet_pdata *pdata);
335 void xgene_enet_mdio_remove(struct xgene_enet_pdata *pdata);
337 #endif /* __XGENE_ENET_HW_H__ */