1 /* Applied Micro X-Gene SoC Ethernet Driver
3 * Copyright (c) 2014, Applied Micro Circuits Corporation
4 * Authors: Iyappan Subramanian <isubramanian@apm.com>
5 * Ravi Patel <rapatel@apm.com>
6 * Keyur Chudgar <kchudgar@apm.com>
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program. If not, see <http://www.gnu.org/licenses/>.
22 #include "xgene_enet_main.h"
23 #include "xgene_enet_hw.h"
25 static void xgene_enet_ring_init(struct xgene_enet_desc_ring *ring)
27 u32 *ring_cfg = ring->state;
29 enum xgene_enet_ring_cfgsize cfgsize = ring->cfgsize;
31 ring_cfg[4] |= (1 << SELTHRSH_POS) &
32 CREATE_MASK(SELTHRSH_POS, SELTHRSH_LEN);
33 ring_cfg[3] |= ACCEPTLERR;
34 ring_cfg[2] |= QCOHERENT;
37 ring_cfg[2] |= (addr << RINGADDRL_POS) &
38 CREATE_MASK_ULL(RINGADDRL_POS, RINGADDRL_LEN);
39 addr >>= RINGADDRL_LEN;
40 ring_cfg[3] |= addr & CREATE_MASK_ULL(RINGADDRH_POS, RINGADDRH_LEN);
41 ring_cfg[3] |= ((u32)cfgsize << RINGSIZE_POS) &
42 CREATE_MASK(RINGSIZE_POS, RINGSIZE_LEN);
45 static void xgene_enet_ring_set_type(struct xgene_enet_desc_ring *ring)
47 u32 *ring_cfg = ring->state;
51 is_bufpool = xgene_enet_is_bufpool(ring->id);
52 val = (is_bufpool) ? RING_BUFPOOL : RING_REGULAR;
53 ring_cfg[4] |= (val << RINGTYPE_POS) &
54 CREATE_MASK(RINGTYPE_POS, RINGTYPE_LEN);
57 ring_cfg[3] |= (BUFPOOL_MODE << RINGMODE_POS) &
58 CREATE_MASK(RINGMODE_POS, RINGMODE_LEN);
62 static void xgene_enet_ring_set_recombbuf(struct xgene_enet_desc_ring *ring)
64 u32 *ring_cfg = ring->state;
66 ring_cfg[3] |= RECOMBBUF;
67 ring_cfg[3] |= (0xf << RECOMTIMEOUTL_POS) &
68 CREATE_MASK(RECOMTIMEOUTL_POS, RECOMTIMEOUTL_LEN);
69 ring_cfg[4] |= 0x7 & CREATE_MASK(RECOMTIMEOUTH_POS, RECOMTIMEOUTH_LEN);
72 static void xgene_enet_ring_wr32(struct xgene_enet_desc_ring *ring,
75 struct xgene_enet_pdata *pdata = netdev_priv(ring->ndev);
77 iowrite32(data, pdata->ring_csr_addr + offset);
80 static void xgene_enet_ring_rd32(struct xgene_enet_desc_ring *ring,
81 u32 offset, u32 *data)
83 struct xgene_enet_pdata *pdata = netdev_priv(ring->ndev);
85 *data = ioread32(pdata->ring_csr_addr + offset);
88 static void xgene_enet_write_ring_state(struct xgene_enet_desc_ring *ring)
90 struct xgene_enet_pdata *pdata = netdev_priv(ring->ndev);
93 xgene_enet_ring_wr32(ring, CSR_RING_CONFIG, ring->num);
94 for (i = 0; i < pdata->ring_ops->num_ring_config; i++) {
95 xgene_enet_ring_wr32(ring, CSR_RING_WR_BASE + (i * 4),
100 static void xgene_enet_clr_ring_state(struct xgene_enet_desc_ring *ring)
102 memset(ring->state, 0, sizeof(ring->state));
103 xgene_enet_write_ring_state(ring);
106 static void xgene_enet_set_ring_state(struct xgene_enet_desc_ring *ring)
108 xgene_enet_ring_set_type(ring);
110 if (xgene_enet_ring_owner(ring->id) == RING_OWNER_ETH0 ||
111 xgene_enet_ring_owner(ring->id) == RING_OWNER_ETH1)
112 xgene_enet_ring_set_recombbuf(ring);
114 xgene_enet_ring_init(ring);
115 xgene_enet_write_ring_state(ring);
118 static void xgene_enet_set_ring_id(struct xgene_enet_desc_ring *ring)
120 u32 ring_id_val, ring_id_buf;
123 is_bufpool = xgene_enet_is_bufpool(ring->id);
125 ring_id_val = ring->id & GENMASK(9, 0);
126 ring_id_val |= OVERWRITE;
128 ring_id_buf = (ring->num << 9) & GENMASK(18, 9);
129 ring_id_buf |= PREFETCH_BUF_EN;
131 ring_id_buf |= IS_BUFFER_POOL;
133 xgene_enet_ring_wr32(ring, CSR_RING_ID, ring_id_val);
134 xgene_enet_ring_wr32(ring, CSR_RING_ID_BUF, ring_id_buf);
137 static void xgene_enet_clr_desc_ring_id(struct xgene_enet_desc_ring *ring)
141 ring_id = ring->id | OVERWRITE;
142 xgene_enet_ring_wr32(ring, CSR_RING_ID, ring_id);
143 xgene_enet_ring_wr32(ring, CSR_RING_ID_BUF, 0);
146 static struct xgene_enet_desc_ring *xgene_enet_setup_ring(
147 struct xgene_enet_desc_ring *ring)
149 u32 size = ring->size;
153 xgene_enet_clr_ring_state(ring);
154 xgene_enet_set_ring_state(ring);
155 xgene_enet_set_ring_id(ring);
157 ring->slots = xgene_enet_get_numslots(ring->id, size);
159 is_bufpool = xgene_enet_is_bufpool(ring->id);
160 if (is_bufpool || xgene_enet_ring_owner(ring->id) != RING_OWNER_CPU)
163 for (i = 0; i < ring->slots; i++)
164 xgene_enet_mark_desc_slot_empty(&ring->raw_desc[i]);
166 xgene_enet_ring_rd32(ring, CSR_RING_NE_INT_MODE, &data);
167 data |= BIT(31 - xgene_enet_ring_bufnum(ring->id));
168 xgene_enet_ring_wr32(ring, CSR_RING_NE_INT_MODE, data);
173 static void xgene_enet_clear_ring(struct xgene_enet_desc_ring *ring)
178 is_bufpool = xgene_enet_is_bufpool(ring->id);
179 if (is_bufpool || xgene_enet_ring_owner(ring->id) != RING_OWNER_CPU)
182 xgene_enet_ring_rd32(ring, CSR_RING_NE_INT_MODE, &data);
183 data &= ~BIT(31 - xgene_enet_ring_bufnum(ring->id));
184 xgene_enet_ring_wr32(ring, CSR_RING_NE_INT_MODE, data);
187 xgene_enet_clr_desc_ring_id(ring);
188 xgene_enet_clr_ring_state(ring);
191 static void xgene_enet_wr_cmd(struct xgene_enet_desc_ring *ring, int count)
193 iowrite32(count, ring->cmd);
196 static u32 xgene_enet_ring_len(struct xgene_enet_desc_ring *ring)
198 u32 __iomem *cmd_base = ring->cmd_base;
199 u32 ring_state, num_msgs;
201 ring_state = ioread32(&cmd_base[1]);
202 num_msgs = GET_VAL(NUMMSGSINQ, ring_state);
207 static void xgene_enet_setup_coalescing(struct xgene_enet_desc_ring *ring)
211 xgene_enet_ring_wr32(ring, CSR_PBM_COAL, 0x8e);
212 xgene_enet_ring_wr32(ring, CSR_PBM_CTICK1, data);
213 xgene_enet_ring_wr32(ring, CSR_PBM_CTICK2, data << 16);
214 xgene_enet_ring_wr32(ring, CSR_THRESHOLD0_SET1, 0x40);
215 xgene_enet_ring_wr32(ring, CSR_THRESHOLD1_SET1, 0x80);
218 void xgene_enet_parse_error(struct xgene_enet_desc_ring *ring,
219 struct xgene_enet_pdata *pdata,
220 enum xgene_enet_err_code status)
224 ring->rx_crc_errors++;
227 case INGRESS_CHECKSUM:
228 case INGRESS_CHECKSUM_COMPUTE:
232 case INGRESS_TRUNC_FRAME:
233 ring->rx_frame_errors++;
236 case INGRESS_PKT_LEN:
237 ring->rx_length_errors++;
240 case INGRESS_PKT_UNDER:
241 ring->rx_frame_errors++;
244 case INGRESS_FIFO_OVERRUN:
245 ring->rx_fifo_errors++;
252 static void xgene_enet_wr_csr(struct xgene_enet_pdata *pdata,
255 void __iomem *addr = pdata->eth_csr_addr + offset;
257 iowrite32(val, addr);
260 static void xgene_enet_wr_ring_if(struct xgene_enet_pdata *pdata,
263 void __iomem *addr = pdata->eth_ring_if_addr + offset;
265 iowrite32(val, addr);
268 static void xgene_enet_wr_diag_csr(struct xgene_enet_pdata *pdata,
271 void __iomem *addr = pdata->eth_diag_csr_addr + offset;
273 iowrite32(val, addr);
276 static void xgene_enet_wr_mcx_csr(struct xgene_enet_pdata *pdata,
279 void __iomem *addr = pdata->mcx_mac_csr_addr + offset;
281 iowrite32(val, addr);
284 static bool xgene_enet_wr_indirect(void __iomem *addr, void __iomem *wr,
285 void __iomem *cmd, void __iomem *cmd_done,
286 u32 wr_addr, u32 wr_data)
291 iowrite32(wr_addr, addr);
292 iowrite32(wr_data, wr);
293 iowrite32(XGENE_ENET_WR_CMD, cmd);
295 /* wait for write command to complete */
296 while (!(done = ioread32(cmd_done)) && wait--)
307 static void xgene_enet_wr_mcx_mac(struct xgene_enet_pdata *pdata,
308 u32 wr_addr, u32 wr_data)
310 void __iomem *addr, *wr, *cmd, *cmd_done;
312 addr = pdata->mcx_mac_addr + MAC_ADDR_REG_OFFSET;
313 wr = pdata->mcx_mac_addr + MAC_WRITE_REG_OFFSET;
314 cmd = pdata->mcx_mac_addr + MAC_COMMAND_REG_OFFSET;
315 cmd_done = pdata->mcx_mac_addr + MAC_COMMAND_DONE_REG_OFFSET;
317 if (!xgene_enet_wr_indirect(addr, wr, cmd, cmd_done, wr_addr, wr_data))
318 netdev_err(pdata->ndev, "MCX mac write failed, addr: %04x\n",
322 static void xgene_enet_rd_csr(struct xgene_enet_pdata *pdata,
323 u32 offset, u32 *val)
325 void __iomem *addr = pdata->eth_csr_addr + offset;
327 *val = ioread32(addr);
330 static void xgene_enet_rd_diag_csr(struct xgene_enet_pdata *pdata,
331 u32 offset, u32 *val)
333 void __iomem *addr = pdata->eth_diag_csr_addr + offset;
335 *val = ioread32(addr);
338 static void xgene_enet_rd_mcx_csr(struct xgene_enet_pdata *pdata,
339 u32 offset, u32 *val)
341 void __iomem *addr = pdata->mcx_mac_csr_addr + offset;
343 *val = ioread32(addr);
346 static bool xgene_enet_rd_indirect(void __iomem *addr, void __iomem *rd,
347 void __iomem *cmd, void __iomem *cmd_done,
348 u32 rd_addr, u32 *rd_data)
353 iowrite32(rd_addr, addr);
354 iowrite32(XGENE_ENET_RD_CMD, cmd);
356 /* wait for read command to complete */
357 while (!(done = ioread32(cmd_done)) && wait--)
363 *rd_data = ioread32(rd);
369 static void xgene_enet_rd_mcx_mac(struct xgene_enet_pdata *pdata,
370 u32 rd_addr, u32 *rd_data)
372 void __iomem *addr, *rd, *cmd, *cmd_done;
374 addr = pdata->mcx_mac_addr + MAC_ADDR_REG_OFFSET;
375 rd = pdata->mcx_mac_addr + MAC_READ_REG_OFFSET;
376 cmd = pdata->mcx_mac_addr + MAC_COMMAND_REG_OFFSET;
377 cmd_done = pdata->mcx_mac_addr + MAC_COMMAND_DONE_REG_OFFSET;
379 if (!xgene_enet_rd_indirect(addr, rd, cmd, cmd_done, rd_addr, rd_data))
380 netdev_err(pdata->ndev, "MCX mac read failed, addr: %04x\n",
384 static int xgene_mii_phy_write(struct xgene_enet_pdata *pdata, int phy_id,
387 u32 addr = 0, wr_data = 0;
391 PHY_ADDR_SET(&addr, phy_id);
392 REG_ADDR_SET(&addr, reg);
393 xgene_enet_wr_mcx_mac(pdata, MII_MGMT_ADDRESS_ADDR, addr);
395 PHY_CONTROL_SET(&wr_data, data);
396 xgene_enet_wr_mcx_mac(pdata, MII_MGMT_CONTROL_ADDR, wr_data);
399 xgene_enet_rd_mcx_mac(pdata, MII_MGMT_INDICATORS_ADDR, &done);
400 } while ((done & BUSY_MASK) && wait--);
402 if (done & BUSY_MASK) {
403 netdev_err(pdata->ndev, "MII_MGMT write failed\n");
410 static int xgene_mii_phy_read(struct xgene_enet_pdata *pdata,
417 PHY_ADDR_SET(&addr, phy_id);
418 REG_ADDR_SET(&addr, reg);
419 xgene_enet_wr_mcx_mac(pdata, MII_MGMT_ADDRESS_ADDR, addr);
420 xgene_enet_wr_mcx_mac(pdata, MII_MGMT_COMMAND_ADDR, READ_CYCLE_MASK);
423 xgene_enet_rd_mcx_mac(pdata, MII_MGMT_INDICATORS_ADDR, &done);
424 } while ((done & BUSY_MASK) && wait--);
426 if (done & BUSY_MASK) {
427 netdev_err(pdata->ndev, "MII_MGMT read failed\n");
431 xgene_enet_rd_mcx_mac(pdata, MII_MGMT_STATUS_ADDR, &data);
432 xgene_enet_wr_mcx_mac(pdata, MII_MGMT_COMMAND_ADDR, 0);
437 static void xgene_gmac_set_mac_addr(struct xgene_enet_pdata *pdata)
440 u8 *dev_addr = pdata->ndev->dev_addr;
442 addr0 = (dev_addr[3] << 24) | (dev_addr[2] << 16) |
443 (dev_addr[1] << 8) | dev_addr[0];
444 addr1 = (dev_addr[5] << 24) | (dev_addr[4] << 16);
446 xgene_enet_wr_mcx_mac(pdata, STATION_ADDR0_ADDR, addr0);
447 xgene_enet_wr_mcx_mac(pdata, STATION_ADDR1_ADDR, addr1);
450 static int xgene_enet_ecc_init(struct xgene_enet_pdata *pdata)
452 struct net_device *ndev = pdata->ndev;
456 xgene_enet_wr_diag_csr(pdata, ENET_CFG_MEM_RAM_SHUTDOWN_ADDR, 0x0);
458 usleep_range(100, 110);
459 xgene_enet_rd_diag_csr(pdata, ENET_BLOCK_MEM_RDY_ADDR, &data);
460 } while ((data != 0xffffffff) && wait--);
462 if (data != 0xffffffff) {
463 netdev_err(ndev, "Failed to release memory from shutdown\n");
470 static void xgene_gmac_reset(struct xgene_enet_pdata *pdata)
472 xgene_enet_wr_mcx_mac(pdata, MAC_CONFIG_1_ADDR, SOFT_RESET1);
473 xgene_enet_wr_mcx_mac(pdata, MAC_CONFIG_1_ADDR, 0);
476 static void xgene_enet_configure_clock(struct xgene_enet_pdata *pdata)
478 struct device *dev = &pdata->pdev->dev;
481 struct clk *parent = clk_get_parent(pdata->clk);
483 switch (pdata->phy_speed) {
485 clk_set_rate(parent, 2500000);
488 clk_set_rate(parent, 25000000);
491 clk_set_rate(parent, 125000000);
497 switch (pdata->phy_speed) {
499 acpi_evaluate_object(ACPI_HANDLE(dev),
503 acpi_evaluate_object(ACPI_HANDLE(dev),
507 acpi_evaluate_object(ACPI_HANDLE(dev),
515 static void xgene_gmac_init(struct xgene_enet_pdata *pdata)
517 struct device *dev = &pdata->pdev->dev;
522 xgene_gmac_reset(pdata);
524 xgene_enet_rd_mcx_csr(pdata, ICM_CONFIG0_REG_0_ADDR, &icm0);
525 xgene_enet_rd_mcx_csr(pdata, ICM_CONFIG2_REG_0_ADDR, &icm2);
526 xgene_enet_rd_mcx_mac(pdata, MAC_CONFIG_2_ADDR, &mc2);
527 xgene_enet_rd_mcx_mac(pdata, INTERFACE_CONTROL_ADDR, &intf_ctl);
528 xgene_enet_rd_csr(pdata, RGMII_REG_0_ADDR, &rgmii);
530 switch (pdata->phy_speed) {
532 ENET_INTERFACE_MODE2_SET(&mc2, 1);
533 intf_ctl &= ~(ENET_LHD_MODE | ENET_GHD_MODE);
534 CFG_MACMODE_SET(&icm0, 0);
535 CFG_WAITASYNCRD_SET(&icm2, 500);
536 rgmii &= ~CFG_SPEED_1250;
539 ENET_INTERFACE_MODE2_SET(&mc2, 1);
540 intf_ctl &= ~ENET_GHD_MODE;
541 intf_ctl |= ENET_LHD_MODE;
542 CFG_MACMODE_SET(&icm0, 1);
543 CFG_WAITASYNCRD_SET(&icm2, 80);
544 rgmii &= ~CFG_SPEED_1250;
547 ENET_INTERFACE_MODE2_SET(&mc2, 2);
548 intf_ctl &= ~ENET_LHD_MODE;
549 intf_ctl |= ENET_GHD_MODE;
550 CFG_MACMODE_SET(&icm0, 2);
551 CFG_WAITASYNCRD_SET(&icm2, 0);
553 CFG_TXCLK_MUXSEL0_SET(&rgmii, pdata->tx_delay);
554 CFG_RXCLK_MUXSEL0_SET(&rgmii, pdata->rx_delay);
556 rgmii |= CFG_SPEED_1250;
558 xgene_enet_rd_csr(pdata, DEBUG_REG_ADDR, &value);
559 value |= CFG_BYPASS_UNISEC_TX | CFG_BYPASS_UNISEC_RX;
560 xgene_enet_wr_csr(pdata, DEBUG_REG_ADDR, value);
564 mc2 |= FULL_DUPLEX2 | PAD_CRC;
565 xgene_enet_wr_mcx_mac(pdata, MAC_CONFIG_2_ADDR, mc2);
566 xgene_enet_wr_mcx_mac(pdata, INTERFACE_CONTROL_ADDR, intf_ctl);
568 xgene_gmac_set_mac_addr(pdata);
570 /* Adjust MDC clock frequency */
571 xgene_enet_rd_mcx_mac(pdata, MII_MGMT_CONFIG_ADDR, &value);
572 MGMT_CLOCK_SEL_SET(&value, 7);
573 xgene_enet_wr_mcx_mac(pdata, MII_MGMT_CONFIG_ADDR, value);
575 /* Enable drop if bufpool not available */
576 xgene_enet_rd_csr(pdata, RSIF_CONFIG_REG_ADDR, &value);
577 value |= CFG_RSIF_FPBUFF_TIMEOUT_EN;
578 xgene_enet_wr_csr(pdata, RSIF_CONFIG_REG_ADDR, value);
580 /* Rtype should be copied from FP */
581 xgene_enet_wr_csr(pdata, RSIF_RAM_DBG_REG0_ADDR, 0);
582 xgene_enet_wr_csr(pdata, RGMII_REG_0_ADDR, rgmii);
583 xgene_enet_configure_clock(pdata);
585 /* Rx-Tx traffic resume */
586 xgene_enet_wr_csr(pdata, CFG_LINK_AGGR_RESUME_0_ADDR, TX_PORT0);
588 xgene_enet_wr_mcx_csr(pdata, ICM_CONFIG0_REG_0_ADDR, icm0);
589 xgene_enet_wr_mcx_csr(pdata, ICM_CONFIG2_REG_0_ADDR, icm2);
591 xgene_enet_rd_mcx_csr(pdata, RX_DV_GATE_REG_0_ADDR, &value);
592 value &= ~TX_DV_GATE_EN0;
593 value &= ~RX_DV_GATE_EN0;
595 xgene_enet_wr_mcx_csr(pdata, RX_DV_GATE_REG_0_ADDR, value);
597 xgene_enet_wr_csr(pdata, CFG_BYPASS_ADDR, RESUME_TX);
600 static void xgene_enet_config_ring_if_assoc(struct xgene_enet_pdata *pdata)
602 u32 val = 0xffffffff;
604 xgene_enet_wr_ring_if(pdata, ENET_CFGSSQMIWQASSOC_ADDR, val);
605 xgene_enet_wr_ring_if(pdata, ENET_CFGSSQMIFPQASSOC_ADDR, val);
606 xgene_enet_wr_ring_if(pdata, ENET_CFGSSQMIQMLITEWQASSOC_ADDR, val);
607 xgene_enet_wr_ring_if(pdata, ENET_CFGSSQMIQMLITEFPQASSOC_ADDR, val);
610 static void xgene_enet_cle_bypass(struct xgene_enet_pdata *pdata,
611 u32 dst_ring_num, u16 bufpool_id)
616 fpsel = xgene_enet_ring_bufnum(bufpool_id) - 0x20;
618 xgene_enet_rd_csr(pdata, CLE_BYPASS_REG0_0_ADDR, &cb);
619 cb |= CFG_CLE_BYPASS_EN0;
620 CFG_CLE_IP_PROTOCOL0_SET(&cb, 3);
621 xgene_enet_wr_csr(pdata, CLE_BYPASS_REG0_0_ADDR, cb);
623 xgene_enet_rd_csr(pdata, CLE_BYPASS_REG1_0_ADDR, &cb);
624 CFG_CLE_DSTQID0_SET(&cb, dst_ring_num);
625 CFG_CLE_FPSEL0_SET(&cb, fpsel);
626 xgene_enet_wr_csr(pdata, CLE_BYPASS_REG1_0_ADDR, cb);
629 static void xgene_gmac_rx_enable(struct xgene_enet_pdata *pdata)
633 xgene_enet_rd_mcx_mac(pdata, MAC_CONFIG_1_ADDR, &data);
634 xgene_enet_wr_mcx_mac(pdata, MAC_CONFIG_1_ADDR, data | RX_EN);
637 static void xgene_gmac_tx_enable(struct xgene_enet_pdata *pdata)
641 xgene_enet_rd_mcx_mac(pdata, MAC_CONFIG_1_ADDR, &data);
642 xgene_enet_wr_mcx_mac(pdata, MAC_CONFIG_1_ADDR, data | TX_EN);
645 static void xgene_gmac_rx_disable(struct xgene_enet_pdata *pdata)
649 xgene_enet_rd_mcx_mac(pdata, MAC_CONFIG_1_ADDR, &data);
650 xgene_enet_wr_mcx_mac(pdata, MAC_CONFIG_1_ADDR, data & ~RX_EN);
653 static void xgene_gmac_tx_disable(struct xgene_enet_pdata *pdata)
657 xgene_enet_rd_mcx_mac(pdata, MAC_CONFIG_1_ADDR, &data);
658 xgene_enet_wr_mcx_mac(pdata, MAC_CONFIG_1_ADDR, data & ~TX_EN);
661 bool xgene_ring_mgr_init(struct xgene_enet_pdata *p)
663 if (!ioread32(p->ring_csr_addr + CLKEN_ADDR))
666 if (ioread32(p->ring_csr_addr + SRST_ADDR))
672 static int xgene_enet_reset(struct xgene_enet_pdata *pdata)
676 if (!xgene_ring_mgr_init(pdata))
679 if (!IS_ERR(pdata->clk)) {
680 clk_prepare_enable(pdata->clk);
681 clk_disable_unprepare(pdata->clk);
682 clk_prepare_enable(pdata->clk);
683 xgene_enet_ecc_init(pdata);
685 xgene_enet_config_ring_if_assoc(pdata);
687 /* Enable auto-incr for scanning */
688 xgene_enet_rd_mcx_mac(pdata, MII_MGMT_CONFIG_ADDR, &val);
689 val |= SCAN_AUTO_INCR;
690 MGMT_CLOCK_SEL_SET(&val, 1);
691 xgene_enet_wr_mcx_mac(pdata, MII_MGMT_CONFIG_ADDR, val);
696 static void xgene_gport_shutdown(struct xgene_enet_pdata *pdata)
698 if (!IS_ERR(pdata->clk))
699 clk_disable_unprepare(pdata->clk);
702 static int xgene_enet_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
704 struct xgene_enet_pdata *pdata = bus->priv;
707 val = xgene_mii_phy_read(pdata, mii_id, regnum);
708 netdev_dbg(pdata->ndev, "mdio_rd: bus=%d reg=%d val=%x\n",
709 mii_id, regnum, val);
714 static int xgene_enet_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
717 struct xgene_enet_pdata *pdata = bus->priv;
719 netdev_dbg(pdata->ndev, "mdio_wr: bus=%d reg=%d val=%x\n",
720 mii_id, regnum, val);
721 return xgene_mii_phy_write(pdata, mii_id, regnum, val);
724 static void xgene_enet_adjust_link(struct net_device *ndev)
726 struct xgene_enet_pdata *pdata = netdev_priv(ndev);
727 struct phy_device *phydev = pdata->phy_dev;
730 if (pdata->phy_speed != phydev->speed) {
731 pdata->phy_speed = phydev->speed;
732 xgene_gmac_init(pdata);
733 xgene_gmac_rx_enable(pdata);
734 xgene_gmac_tx_enable(pdata);
735 phy_print_status(phydev);
738 xgene_gmac_rx_disable(pdata);
739 xgene_gmac_tx_disable(pdata);
740 pdata->phy_speed = SPEED_UNKNOWN;
741 phy_print_status(phydev);
745 static int xgene_enet_phy_connect(struct net_device *ndev)
747 struct xgene_enet_pdata *pdata = netdev_priv(ndev);
748 struct device_node *phy_np;
749 struct phy_device *phy_dev;
750 struct device *dev = &pdata->pdev->dev;
753 phy_np = of_parse_phandle(dev->of_node, "phy-handle", 0);
755 netdev_dbg(ndev, "No phy-handle found in DT\n");
759 phy_dev = of_phy_connect(ndev, phy_np, &xgene_enet_adjust_link,
762 netdev_err(ndev, "Could not connect to PHY\n");
766 pdata->phy_dev = phy_dev;
768 phy_dev = pdata->phy_dev;
771 phy_connect_direct(ndev, phy_dev, &xgene_enet_adjust_link,
773 netdev_err(ndev, "Could not connect to PHY\n");
778 pdata->phy_speed = SPEED_UNKNOWN;
779 phy_dev->supported &= ~SUPPORTED_10baseT_Half &
780 ~SUPPORTED_100baseT_Half &
781 ~SUPPORTED_1000baseT_Half;
782 phy_dev->advertising = phy_dev->supported;
787 static int xgene_mdiobus_register(struct xgene_enet_pdata *pdata,
788 struct mii_bus *mdio)
790 struct device *dev = &pdata->pdev->dev;
791 struct net_device *ndev = pdata->ndev;
792 struct phy_device *phy;
793 struct device_node *child_np;
794 struct device_node *mdio_np = NULL;
799 for_each_child_of_node(dev->of_node, child_np) {
800 if (of_device_is_compatible(child_np,
808 netdev_dbg(ndev, "No mdio node in the dts\n");
812 return of_mdiobus_register(mdio, mdio_np);
815 /* Mask out all PHYs from auto probing. */
818 /* Register the MDIO bus */
819 ret = mdiobus_register(mdio);
823 ret = device_property_read_u32(dev, "phy-channel", &phy_id);
825 ret = device_property_read_u32(dev, "phy-addr", &phy_id);
829 phy = get_phy_device(mdio, phy_id, false);
833 ret = phy_device_register(phy);
835 phy_device_free(phy);
837 pdata->phy_dev = phy;
842 int xgene_enet_mdio_config(struct xgene_enet_pdata *pdata)
844 struct net_device *ndev = pdata->ndev;
845 struct mii_bus *mdio_bus;
848 mdio_bus = mdiobus_alloc();
852 mdio_bus->name = "APM X-Gene MDIO bus";
853 mdio_bus->read = xgene_enet_mdio_read;
854 mdio_bus->write = xgene_enet_mdio_write;
855 snprintf(mdio_bus->id, MII_BUS_ID_SIZE, "%s-%s", "xgene-mii",
858 mdio_bus->priv = pdata;
859 mdio_bus->parent = &ndev->dev;
861 ret = xgene_mdiobus_register(pdata, mdio_bus);
863 netdev_err(ndev, "Failed to register MDIO bus\n");
864 mdiobus_free(mdio_bus);
867 pdata->mdio_bus = mdio_bus;
869 ret = xgene_enet_phy_connect(ndev);
871 xgene_enet_mdio_remove(pdata);
876 void xgene_enet_mdio_remove(struct xgene_enet_pdata *pdata)
879 phy_disconnect(pdata->phy_dev);
881 mdiobus_unregister(pdata->mdio_bus);
882 mdiobus_free(pdata->mdio_bus);
883 pdata->mdio_bus = NULL;
886 const struct xgene_mac_ops xgene_gmac_ops = {
887 .init = xgene_gmac_init,
888 .reset = xgene_gmac_reset,
889 .rx_enable = xgene_gmac_rx_enable,
890 .tx_enable = xgene_gmac_tx_enable,
891 .rx_disable = xgene_gmac_rx_disable,
892 .tx_disable = xgene_gmac_tx_disable,
893 .set_mac_addr = xgene_gmac_set_mac_addr,
896 const struct xgene_port_ops xgene_gport_ops = {
897 .reset = xgene_enet_reset,
898 .cle_bypass = xgene_enet_cle_bypass,
899 .shutdown = xgene_gport_shutdown,
902 struct xgene_ring_ops xgene_ring1_ops = {
903 .num_ring_config = NUM_RING_CONFIG,
904 .num_ring_id_shift = 6,
905 .setup = xgene_enet_setup_ring,
906 .clear = xgene_enet_clear_ring,
907 .wr_cmd = xgene_enet_wr_cmd,
908 .len = xgene_enet_ring_len,
909 .coalesce = xgene_enet_setup_coalescing,