2 * AMD 10Gb Ethernet driver
4 * This file is available to you under your choice of the following two
9 * Copyright (c) 2014 Advanced Micro Devices, Inc.
11 * This file is free software; you may copy, redistribute and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation, either version 2 of the License, or (at
14 * your option) any later version.
16 * This file is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19 * General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program. If not, see <http://www.gnu.org/licenses/>.
24 * This file incorporates work covered by the following copyright and
26 * The Synopsys DWC ETHER XGMAC Software Driver and documentation
27 * (hereinafter "Software") is an unsupported proprietary work of Synopsys,
28 * Inc. unless otherwise expressly agreed to in writing between Synopsys
31 * The Software IS NOT an item of Licensed Software or Licensed Product
32 * under any End User Software License Agreement or Agreement for Licensed
33 * Product with Synopsys or any supplement thereto. Permission is hereby
34 * granted, free of charge, to any person obtaining a copy of this software
35 * annotated with this license and the Software, to deal in the Software
36 * without restriction, including without limitation the rights to use,
37 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies
38 * of the Software, and to permit persons to whom the Software is furnished
39 * to do so, subject to the following conditions:
41 * The above copyright notice and this permission notice shall be included
42 * in all copies or substantial portions of the Software.
44 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
45 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
46 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
47 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
48 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
49 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
50 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
51 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
52 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
53 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
54 * THE POSSIBILITY OF SUCH DAMAGE.
57 * License 2: Modified BSD
59 * Copyright (c) 2014 Advanced Micro Devices, Inc.
60 * All rights reserved.
62 * Redistribution and use in source and binary forms, with or without
63 * modification, are permitted provided that the following conditions are met:
64 * * Redistributions of source code must retain the above copyright
65 * notice, this list of conditions and the following disclaimer.
66 * * Redistributions in binary form must reproduce the above copyright
67 * notice, this list of conditions and the following disclaimer in the
68 * documentation and/or other materials provided with the distribution.
69 * * Neither the name of Advanced Micro Devices, Inc. nor the
70 * names of its contributors may be used to endorse or promote products
71 * derived from this software without specific prior written permission.
73 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
74 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
75 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
76 * ARE DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
77 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
78 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
79 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
80 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
81 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
82 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
84 * This file incorporates work covered by the following copyright and
86 * The Synopsys DWC ETHER XGMAC Software Driver and documentation
87 * (hereinafter "Software") is an unsupported proprietary work of Synopsys,
88 * Inc. unless otherwise expressly agreed to in writing between Synopsys
91 * The Software IS NOT an item of Licensed Software or Licensed Product
92 * under any End User Software License Agreement or Agreement for Licensed
93 * Product with Synopsys or any supplement thereto. Permission is hereby
94 * granted, free of charge, to any person obtaining a copy of this software
95 * annotated with this license and the Software, to deal in the Software
96 * without restriction, including without limitation the rights to use,
97 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies
98 * of the Software, and to permit persons to whom the Software is furnished
99 * to do so, subject to the following conditions:
101 * The above copyright notice and this permission notice shall be included
102 * in all copies or substantial portions of the Software.
104 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
105 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
106 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
107 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
108 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
109 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
110 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
111 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
112 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
113 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
114 * THE POSSIBILITY OF SUCH DAMAGE.
117 #include <linux/phy.h>
118 #include <linux/clk.h>
119 #include <linux/bitrev.h>
120 #include <linux/crc32.h>
123 #include "xgbe-common.h"
126 static unsigned int xgbe_usec_to_riwt(struct xgbe_prv_data *pdata,
132 DBGPR("-->xgbe_usec_to_riwt\n");
134 rate = clk_get_rate(pdata->sysclk);
137 * Convert the input usec value to the watchdog timer value. Each
138 * watchdog timer value is equivalent to 256 clock cycles.
139 * Calculate the required value as:
140 * ( usec * ( system_clock_mhz / 10^6 ) / 256
142 ret = (usec * (rate / 1000000)) / 256;
144 DBGPR("<--xgbe_usec_to_riwt\n");
149 static unsigned int xgbe_riwt_to_usec(struct xgbe_prv_data *pdata,
155 DBGPR("-->xgbe_riwt_to_usec\n");
157 rate = clk_get_rate(pdata->sysclk);
160 * Convert the input watchdog timer value to the usec value. Each
161 * watchdog timer value is equivalent to 256 clock cycles.
162 * Calculate the required value as:
163 * ( riwt * 256 ) / ( system_clock_mhz / 10^6 )
165 ret = (riwt * 256) / (rate / 1000000);
167 DBGPR("<--xgbe_riwt_to_usec\n");
172 static int xgbe_config_pblx8(struct xgbe_prv_data *pdata)
174 struct xgbe_channel *channel;
177 channel = pdata->channel;
178 for (i = 0; i < pdata->channel_count; i++, channel++)
179 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_CR, PBLX8,
185 static int xgbe_get_tx_pbl_val(struct xgbe_prv_data *pdata)
187 return XGMAC_DMA_IOREAD_BITS(pdata->channel, DMA_CH_TCR, PBL);
190 static int xgbe_config_tx_pbl_val(struct xgbe_prv_data *pdata)
192 struct xgbe_channel *channel;
195 channel = pdata->channel;
196 for (i = 0; i < pdata->channel_count; i++, channel++) {
197 if (!channel->tx_ring)
200 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_TCR, PBL,
207 static int xgbe_get_rx_pbl_val(struct xgbe_prv_data *pdata)
209 return XGMAC_DMA_IOREAD_BITS(pdata->channel, DMA_CH_RCR, PBL);
212 static int xgbe_config_rx_pbl_val(struct xgbe_prv_data *pdata)
214 struct xgbe_channel *channel;
217 channel = pdata->channel;
218 for (i = 0; i < pdata->channel_count; i++, channel++) {
219 if (!channel->rx_ring)
222 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_RCR, PBL,
229 static int xgbe_config_osp_mode(struct xgbe_prv_data *pdata)
231 struct xgbe_channel *channel;
234 channel = pdata->channel;
235 for (i = 0; i < pdata->channel_count; i++, channel++) {
236 if (!channel->tx_ring)
239 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_TCR, OSP,
246 static int xgbe_config_rsf_mode(struct xgbe_prv_data *pdata, unsigned int val)
250 for (i = 0; i < pdata->rx_q_count; i++)
251 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, RSF, val);
256 static int xgbe_config_tsf_mode(struct xgbe_prv_data *pdata, unsigned int val)
260 for (i = 0; i < pdata->tx_q_count; i++)
261 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, TSF, val);
266 static int xgbe_config_rx_threshold(struct xgbe_prv_data *pdata,
271 for (i = 0; i < pdata->rx_q_count; i++)
272 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, RTC, val);
277 static int xgbe_config_tx_threshold(struct xgbe_prv_data *pdata,
282 for (i = 0; i < pdata->tx_q_count; i++)
283 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, TTC, val);
288 static int xgbe_config_rx_coalesce(struct xgbe_prv_data *pdata)
290 struct xgbe_channel *channel;
293 channel = pdata->channel;
294 for (i = 0; i < pdata->channel_count; i++, channel++) {
295 if (!channel->rx_ring)
298 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_RIWT, RWT,
305 static int xgbe_config_tx_coalesce(struct xgbe_prv_data *pdata)
310 static void xgbe_config_rx_buffer_size(struct xgbe_prv_data *pdata)
312 struct xgbe_channel *channel;
315 channel = pdata->channel;
316 for (i = 0; i < pdata->channel_count; i++, channel++) {
317 if (!channel->rx_ring)
320 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_RCR, RBSZ,
325 static void xgbe_config_tso_mode(struct xgbe_prv_data *pdata)
327 struct xgbe_channel *channel;
330 channel = pdata->channel;
331 for (i = 0; i < pdata->channel_count; i++, channel++) {
332 if (!channel->tx_ring)
335 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_TCR, TSE, 1);
339 static int xgbe_disable_tx_flow_control(struct xgbe_prv_data *pdata)
341 unsigned int max_q_count, q_count;
342 unsigned int reg, reg_val;
345 /* Clear MTL flow control */
346 for (i = 0; i < pdata->rx_q_count; i++)
347 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, EHFC, 0);
349 /* Clear MAC flow control */
350 max_q_count = XGMAC_MAX_FLOW_CONTROL_QUEUES;
351 q_count = min_t(unsigned int, pdata->rx_q_count, max_q_count);
353 for (i = 0; i < q_count; i++) {
354 reg_val = XGMAC_IOREAD(pdata, reg);
355 XGMAC_SET_BITS(reg_val, MAC_Q0TFCR, TFE, 0);
356 XGMAC_IOWRITE(pdata, reg, reg_val);
358 reg += MAC_QTFCR_INC;
364 static int xgbe_enable_tx_flow_control(struct xgbe_prv_data *pdata)
366 unsigned int max_q_count, q_count;
367 unsigned int reg, reg_val;
370 /* Set MTL flow control */
371 for (i = 0; i < pdata->rx_q_count; i++)
372 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, EHFC, 1);
374 /* Set MAC flow control */
375 max_q_count = XGMAC_MAX_FLOW_CONTROL_QUEUES;
376 q_count = min_t(unsigned int, pdata->rx_q_count, max_q_count);
378 for (i = 0; i < q_count; i++) {
379 reg_val = XGMAC_IOREAD(pdata, reg);
381 /* Enable transmit flow control */
382 XGMAC_SET_BITS(reg_val, MAC_Q0TFCR, TFE, 1);
384 XGMAC_SET_BITS(reg_val, MAC_Q0TFCR, PT, 0xffff);
386 XGMAC_IOWRITE(pdata, reg, reg_val);
388 reg += MAC_QTFCR_INC;
394 static int xgbe_disable_rx_flow_control(struct xgbe_prv_data *pdata)
396 XGMAC_IOWRITE_BITS(pdata, MAC_RFCR, RFE, 0);
401 static int xgbe_enable_rx_flow_control(struct xgbe_prv_data *pdata)
403 XGMAC_IOWRITE_BITS(pdata, MAC_RFCR, RFE, 1);
408 static int xgbe_config_tx_flow_control(struct xgbe_prv_data *pdata)
410 struct ieee_pfc *pfc = pdata->pfc;
412 if (pdata->tx_pause || (pfc && pfc->pfc_en))
413 xgbe_enable_tx_flow_control(pdata);
415 xgbe_disable_tx_flow_control(pdata);
420 static int xgbe_config_rx_flow_control(struct xgbe_prv_data *pdata)
422 struct ieee_pfc *pfc = pdata->pfc;
424 if (pdata->rx_pause || (pfc && pfc->pfc_en))
425 xgbe_enable_rx_flow_control(pdata);
427 xgbe_disable_rx_flow_control(pdata);
432 static void xgbe_config_flow_control(struct xgbe_prv_data *pdata)
434 struct ieee_pfc *pfc = pdata->pfc;
436 xgbe_config_tx_flow_control(pdata);
437 xgbe_config_rx_flow_control(pdata);
439 XGMAC_IOWRITE_BITS(pdata, MAC_RFCR, PFCE,
440 (pfc && pfc->pfc_en) ? 1 : 0);
443 static void xgbe_enable_dma_interrupts(struct xgbe_prv_data *pdata)
445 struct xgbe_channel *channel;
446 unsigned int dma_ch_isr, dma_ch_ier;
449 channel = pdata->channel;
450 for (i = 0; i < pdata->channel_count; i++, channel++) {
451 /* Clear all the interrupts which are set */
452 dma_ch_isr = XGMAC_DMA_IOREAD(channel, DMA_CH_SR);
453 XGMAC_DMA_IOWRITE(channel, DMA_CH_SR, dma_ch_isr);
455 /* Clear all interrupt enable bits */
458 /* Enable following interrupts
459 * NIE - Normal Interrupt Summary Enable
460 * AIE - Abnormal Interrupt Summary Enable
461 * FBEE - Fatal Bus Error Enable
463 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, NIE, 1);
464 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, AIE, 1);
465 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, FBEE, 1);
467 if (channel->tx_ring) {
468 /* Enable the following Tx interrupts
469 * TIE - Transmit Interrupt Enable (unless polling)
471 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, TIE, 1);
473 if (channel->rx_ring) {
474 /* Enable following Rx interrupts
475 * RBUE - Receive Buffer Unavailable Enable
476 * RIE - Receive Interrupt Enable
478 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, RBUE, 1);
479 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, RIE, 1);
482 XGMAC_DMA_IOWRITE(channel, DMA_CH_IER, dma_ch_ier);
486 static void xgbe_enable_mtl_interrupts(struct xgbe_prv_data *pdata)
488 unsigned int mtl_q_isr;
489 unsigned int q_count, i;
491 q_count = max(pdata->hw_feat.tx_q_cnt, pdata->hw_feat.rx_q_cnt);
492 for (i = 0; i < q_count; i++) {
493 /* Clear all the interrupts which are set */
494 mtl_q_isr = XGMAC_MTL_IOREAD(pdata, i, MTL_Q_ISR);
495 XGMAC_MTL_IOWRITE(pdata, i, MTL_Q_ISR, mtl_q_isr);
497 /* No MTL interrupts to be enabled */
498 XGMAC_MTL_IOWRITE(pdata, i, MTL_Q_IER, 0);
502 static void xgbe_enable_mac_interrupts(struct xgbe_prv_data *pdata)
504 unsigned int mac_ier = 0;
506 /* Enable Timestamp interrupt */
507 XGMAC_SET_BITS(mac_ier, MAC_IER, TSIE, 1);
509 XGMAC_IOWRITE(pdata, MAC_IER, mac_ier);
511 /* Enable all counter interrupts */
512 XGMAC_IOWRITE_BITS(pdata, MMC_RIER, ALL_INTERRUPTS, 0xff);
513 XGMAC_IOWRITE_BITS(pdata, MMC_TIER, ALL_INTERRUPTS, 0xff);
516 static int xgbe_set_gmii_speed(struct xgbe_prv_data *pdata)
518 XGMAC_IOWRITE_BITS(pdata, MAC_TCR, SS, 0x3);
523 static int xgbe_set_gmii_2500_speed(struct xgbe_prv_data *pdata)
525 XGMAC_IOWRITE_BITS(pdata, MAC_TCR, SS, 0x2);
530 static int xgbe_set_xgmii_speed(struct xgbe_prv_data *pdata)
532 XGMAC_IOWRITE_BITS(pdata, MAC_TCR, SS, 0);
537 static int xgbe_set_promiscuous_mode(struct xgbe_prv_data *pdata,
540 unsigned int val = enable ? 1 : 0;
542 if (XGMAC_IOREAD_BITS(pdata, MAC_PFR, PR) == val)
545 DBGPR(" %s promiscuous mode\n", enable ? "entering" : "leaving");
546 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, PR, val);
551 static int xgbe_set_all_multicast_mode(struct xgbe_prv_data *pdata,
554 unsigned int val = enable ? 1 : 0;
556 if (XGMAC_IOREAD_BITS(pdata, MAC_PFR, PM) == val)
559 DBGPR(" %s allmulti mode\n", enable ? "entering" : "leaving");
560 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, PM, val);
565 static void xgbe_set_mac_reg(struct xgbe_prv_data *pdata,
566 struct netdev_hw_addr *ha, unsigned int *mac_reg)
568 unsigned int mac_addr_hi, mac_addr_lo;
575 mac_addr = (u8 *)&mac_addr_lo;
576 mac_addr[0] = ha->addr[0];
577 mac_addr[1] = ha->addr[1];
578 mac_addr[2] = ha->addr[2];
579 mac_addr[3] = ha->addr[3];
580 mac_addr = (u8 *)&mac_addr_hi;
581 mac_addr[0] = ha->addr[4];
582 mac_addr[1] = ha->addr[5];
584 DBGPR(" adding mac address %pM at 0x%04x\n", ha->addr,
587 XGMAC_SET_BITS(mac_addr_hi, MAC_MACA1HR, AE, 1);
590 XGMAC_IOWRITE(pdata, *mac_reg, mac_addr_hi);
591 *mac_reg += MAC_MACA_INC;
592 XGMAC_IOWRITE(pdata, *mac_reg, mac_addr_lo);
593 *mac_reg += MAC_MACA_INC;
596 static void xgbe_set_mac_addn_addrs(struct xgbe_prv_data *pdata)
598 struct net_device *netdev = pdata->netdev;
599 struct netdev_hw_addr *ha;
600 unsigned int mac_reg;
601 unsigned int addn_macs;
603 mac_reg = MAC_MACA1HR;
604 addn_macs = pdata->hw_feat.addn_mac;
606 if (netdev_uc_count(netdev) > addn_macs) {
607 xgbe_set_promiscuous_mode(pdata, 1);
609 netdev_for_each_uc_addr(ha, netdev) {
610 xgbe_set_mac_reg(pdata, ha, &mac_reg);
614 if (netdev_mc_count(netdev) > addn_macs) {
615 xgbe_set_all_multicast_mode(pdata, 1);
617 netdev_for_each_mc_addr(ha, netdev) {
618 xgbe_set_mac_reg(pdata, ha, &mac_reg);
624 /* Clear remaining additional MAC address entries */
626 xgbe_set_mac_reg(pdata, NULL, &mac_reg);
629 static void xgbe_set_mac_hash_table(struct xgbe_prv_data *pdata)
631 struct net_device *netdev = pdata->netdev;
632 struct netdev_hw_addr *ha;
633 unsigned int hash_reg;
634 unsigned int hash_table_shift, hash_table_count;
635 u32 hash_table[XGBE_MAC_HASH_TABLE_SIZE];
639 hash_table_shift = 26 - (pdata->hw_feat.hash_table_size >> 7);
640 hash_table_count = pdata->hw_feat.hash_table_size / 32;
641 memset(hash_table, 0, sizeof(hash_table));
643 /* Build the MAC Hash Table register values */
644 netdev_for_each_uc_addr(ha, netdev) {
645 crc = bitrev32(~crc32_le(~0, ha->addr, ETH_ALEN));
646 crc >>= hash_table_shift;
647 hash_table[crc >> 5] |= (1 << (crc & 0x1f));
650 netdev_for_each_mc_addr(ha, netdev) {
651 crc = bitrev32(~crc32_le(~0, ha->addr, ETH_ALEN));
652 crc >>= hash_table_shift;
653 hash_table[crc >> 5] |= (1 << (crc & 0x1f));
656 /* Set the MAC Hash Table registers */
658 for (i = 0; i < hash_table_count; i++) {
659 XGMAC_IOWRITE(pdata, hash_reg, hash_table[i]);
660 hash_reg += MAC_HTR_INC;
664 static int xgbe_add_mac_addresses(struct xgbe_prv_data *pdata)
666 if (pdata->hw_feat.hash_table_size)
667 xgbe_set_mac_hash_table(pdata);
669 xgbe_set_mac_addn_addrs(pdata);
674 static int xgbe_set_mac_address(struct xgbe_prv_data *pdata, u8 *addr)
676 unsigned int mac_addr_hi, mac_addr_lo;
678 mac_addr_hi = (addr[5] << 8) | (addr[4] << 0);
679 mac_addr_lo = (addr[3] << 24) | (addr[2] << 16) |
680 (addr[1] << 8) | (addr[0] << 0);
682 XGMAC_IOWRITE(pdata, MAC_MACA0HR, mac_addr_hi);
683 XGMAC_IOWRITE(pdata, MAC_MACA0LR, mac_addr_lo);
688 static int xgbe_read_mmd_regs(struct xgbe_prv_data *pdata, int prtad,
691 unsigned int mmd_address;
694 if (mmd_reg & MII_ADDR_C45)
695 mmd_address = mmd_reg & ~MII_ADDR_C45;
697 mmd_address = (pdata->mdio_mmd << 16) | (mmd_reg & 0xffff);
699 /* The PCS registers are accessed using mmio. The underlying APB3
700 * management interface uses indirect addressing to access the MMD
701 * register sets. This requires accessing of the PCS register in two
702 * phases, an address phase and a data phase.
704 * The mmio interface is based on 32-bit offsets and values. All
705 * register offsets must therefore be adjusted by left shifting the
706 * offset 2 bits and reading 32 bits of data.
708 mutex_lock(&pdata->xpcs_mutex);
709 XPCS_IOWRITE(pdata, PCS_MMD_SELECT << 2, mmd_address >> 8);
710 mmd_data = XPCS_IOREAD(pdata, (mmd_address & 0xff) << 2);
711 mutex_unlock(&pdata->xpcs_mutex);
716 static void xgbe_write_mmd_regs(struct xgbe_prv_data *pdata, int prtad,
717 int mmd_reg, int mmd_data)
719 unsigned int mmd_address;
721 if (mmd_reg & MII_ADDR_C45)
722 mmd_address = mmd_reg & ~MII_ADDR_C45;
724 mmd_address = (pdata->mdio_mmd << 16) | (mmd_reg & 0xffff);
726 /* The PCS registers are accessed using mmio. The underlying APB3
727 * management interface uses indirect addressing to access the MMD
728 * register sets. This requires accessing of the PCS register in two
729 * phases, an address phase and a data phase.
731 * The mmio interface is based on 32-bit offsets and values. All
732 * register offsets must therefore be adjusted by left shifting the
733 * offset 2 bits and reading 32 bits of data.
735 mutex_lock(&pdata->xpcs_mutex);
736 XPCS_IOWRITE(pdata, PCS_MMD_SELECT << 2, mmd_address >> 8);
737 XPCS_IOWRITE(pdata, (mmd_address & 0xff) << 2, mmd_data);
738 mutex_unlock(&pdata->xpcs_mutex);
741 static int xgbe_tx_complete(struct xgbe_ring_desc *rdesc)
743 return !XGMAC_GET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, OWN);
746 static int xgbe_disable_rx_csum(struct xgbe_prv_data *pdata)
748 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, IPC, 0);
753 static int xgbe_enable_rx_csum(struct xgbe_prv_data *pdata)
755 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, IPC, 1);
760 static int xgbe_enable_rx_vlan_stripping(struct xgbe_prv_data *pdata)
762 /* Put the VLAN tag in the Rx descriptor */
763 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, EVLRXS, 1);
765 /* Don't check the VLAN type */
766 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, DOVLTC, 1);
768 /* Check only C-TAG (0x8100) packets */
769 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, ERSVLM, 0);
771 /* Don't consider an S-TAG (0x88A8) packet as a VLAN packet */
772 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, ESVL, 0);
774 /* Enable VLAN tag stripping */
775 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, EVLS, 0x3);
780 static int xgbe_disable_rx_vlan_stripping(struct xgbe_prv_data *pdata)
782 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, EVLS, 0);
787 static int xgbe_enable_rx_vlan_filtering(struct xgbe_prv_data *pdata)
789 /* Enable VLAN filtering */
790 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, VTFE, 1);
792 /* Enable VLAN Hash Table filtering */
793 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, VTHM, 1);
795 /* Disable VLAN tag inverse matching */
796 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, VTIM, 0);
798 /* Only filter on the lower 12-bits of the VLAN tag */
799 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, ETV, 1);
801 /* In order for the VLAN Hash Table filtering to be effective,
802 * the VLAN tag identifier in the VLAN Tag Register must not
803 * be zero. Set the VLAN tag identifier to "1" to enable the
804 * VLAN Hash Table filtering. This implies that a VLAN tag of
805 * 1 will always pass filtering.
807 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, VL, 1);
812 static int xgbe_disable_rx_vlan_filtering(struct xgbe_prv_data *pdata)
814 /* Disable VLAN filtering */
815 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, VTFE, 0);
821 #define CRCPOLY_LE 0xedb88320
823 static u32 xgbe_vid_crc32_le(__le16 vid_le)
825 u32 poly = CRCPOLY_LE;
828 unsigned char *data = (unsigned char *)&vid_le;
829 unsigned char data_byte = 0;
832 bits = get_bitmask_order(VLAN_VID_MASK);
833 for (i = 0; i < bits; i++) {
835 data_byte = data[i / 8];
837 temp = ((crc & 1) ^ data_byte) & 1;
848 static int xgbe_update_vlan_hash_table(struct xgbe_prv_data *pdata)
853 u16 vlan_hash_table = 0;
855 /* Generate the VLAN Hash Table value */
856 for_each_set_bit(vid, pdata->active_vlans, VLAN_N_VID) {
857 /* Get the CRC32 value of the VLAN ID */
858 vid_le = cpu_to_le16(vid);
859 crc = bitrev32(~xgbe_vid_crc32_le(vid_le)) >> 28;
861 vlan_hash_table |= (1 << crc);
864 /* Set the VLAN Hash Table filtering register */
865 XGMAC_IOWRITE_BITS(pdata, MAC_VLANHTR, VLHT, vlan_hash_table);
870 static void xgbe_tx_desc_reset(struct xgbe_ring_data *rdata)
872 struct xgbe_ring_desc *rdesc = rdata->rdesc;
874 /* Reset the Tx descriptor
875 * Set buffer 1 (lo) address to zero
876 * Set buffer 1 (hi) address to zero
877 * Reset all other control bits (IC, TTSE, B2L & B1L)
878 * Reset all other control bits (OWN, CTXT, FD, LD, CPC, CIC, etc)
886 static void xgbe_tx_desc_init(struct xgbe_channel *channel)
888 struct xgbe_ring *ring = channel->tx_ring;
889 struct xgbe_ring_data *rdata;
890 struct xgbe_ring_desc *rdesc;
892 int start_index = ring->cur;
894 DBGPR("-->tx_desc_init\n");
896 /* Initialze all descriptors */
897 for (i = 0; i < ring->rdesc_count; i++) {
898 rdata = XGBE_GET_DESC_DATA(ring, i);
899 rdesc = rdata->rdesc;
901 /* Initialize Tx descriptor
902 * Set buffer 1 (lo) address to zero
903 * Set buffer 1 (hi) address to zero
904 * Reset all other control bits (IC, TTSE, B2L & B1L)
905 * Reset all other control bits (OWN, CTXT, FD, LD, CPC, CIC,
914 /* Make sure everything is written to the descriptor(s) before
915 * telling the device about them
919 /* Update the total number of Tx descriptors */
920 XGMAC_DMA_IOWRITE(channel, DMA_CH_TDRLR, ring->rdesc_count - 1);
922 /* Update the starting address of descriptor ring */
923 rdata = XGBE_GET_DESC_DATA(ring, start_index);
924 XGMAC_DMA_IOWRITE(channel, DMA_CH_TDLR_HI,
925 upper_32_bits(rdata->rdesc_dma));
926 XGMAC_DMA_IOWRITE(channel, DMA_CH_TDLR_LO,
927 lower_32_bits(rdata->rdesc_dma));
929 DBGPR("<--tx_desc_init\n");
932 static void xgbe_rx_desc_reset(struct xgbe_ring_data *rdata)
934 struct xgbe_ring_desc *rdesc = rdata->rdesc;
936 /* Reset the Rx descriptor
937 * Set buffer 1 (lo) address to dma address (lo)
938 * Set buffer 1 (hi) address to dma address (hi)
939 * Set buffer 2 (lo) address to zero
940 * Set buffer 2 (hi) address to zero and set control bits
943 rdesc->desc0 = cpu_to_le32(lower_32_bits(rdata->skb_dma));
944 rdesc->desc1 = cpu_to_le32(upper_32_bits(rdata->skb_dma));
948 if (rdata->interrupt)
949 XGMAC_SET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, INTE, 1);
951 /* Since the Rx DMA engine is likely running, make sure everything
952 * is written to the descriptor(s) before setting the OWN bit
957 XGMAC_SET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, OWN, 1);
959 /* Make sure ownership is written to the descriptor */
963 static void xgbe_rx_desc_init(struct xgbe_channel *channel)
965 struct xgbe_prv_data *pdata = channel->pdata;
966 struct xgbe_ring *ring = channel->rx_ring;
967 struct xgbe_ring_data *rdata;
968 struct xgbe_ring_desc *rdesc;
969 unsigned int start_index = ring->cur;
970 unsigned int rx_coalesce, rx_frames;
973 DBGPR("-->rx_desc_init\n");
975 rx_coalesce = (pdata->rx_riwt || pdata->rx_frames) ? 1 : 0;
976 rx_frames = pdata->rx_frames;
978 /* Initialize all descriptors */
979 for (i = 0; i < ring->rdesc_count; i++) {
980 rdata = XGBE_GET_DESC_DATA(ring, i);
981 rdesc = rdata->rdesc;
983 /* Initialize Rx descriptor
984 * Set buffer 1 (lo) address to dma address (lo)
985 * Set buffer 1 (hi) address to dma address (hi)
986 * Set buffer 2 (lo) address to zero
987 * Set buffer 2 (hi) address to zero and set control
988 * bits OWN and INTE appropriateley
990 rdesc->desc0 = cpu_to_le32(lower_32_bits(rdata->skb_dma));
991 rdesc->desc1 = cpu_to_le32(upper_32_bits(rdata->skb_dma));
994 XGMAC_SET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, OWN, 1);
995 XGMAC_SET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, INTE, 1);
996 rdata->interrupt = 1;
997 if (rx_coalesce && (!rx_frames || ((i + 1) % rx_frames))) {
998 /* Clear interrupt on completion bit */
999 XGMAC_SET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, INTE,
1001 rdata->interrupt = 0;
1005 /* Make sure everything is written to the descriptors before
1006 * telling the device about them
1010 /* Update the total number of Rx descriptors */
1011 XGMAC_DMA_IOWRITE(channel, DMA_CH_RDRLR, ring->rdesc_count - 1);
1013 /* Update the starting address of descriptor ring */
1014 rdata = XGBE_GET_DESC_DATA(ring, start_index);
1015 XGMAC_DMA_IOWRITE(channel, DMA_CH_RDLR_HI,
1016 upper_32_bits(rdata->rdesc_dma));
1017 XGMAC_DMA_IOWRITE(channel, DMA_CH_RDLR_LO,
1018 lower_32_bits(rdata->rdesc_dma));
1020 /* Update the Rx Descriptor Tail Pointer */
1021 rdata = XGBE_GET_DESC_DATA(ring, start_index + ring->rdesc_count - 1);
1022 XGMAC_DMA_IOWRITE(channel, DMA_CH_RDTR_LO,
1023 lower_32_bits(rdata->rdesc_dma));
1025 DBGPR("<--rx_desc_init\n");
1028 static void xgbe_update_tstamp_addend(struct xgbe_prv_data *pdata,
1029 unsigned int addend)
1031 /* Set the addend register value and tell the device */
1032 XGMAC_IOWRITE(pdata, MAC_TSAR, addend);
1033 XGMAC_IOWRITE_BITS(pdata, MAC_TSCR, TSADDREG, 1);
1035 /* Wait for addend update to complete */
1036 while (XGMAC_IOREAD_BITS(pdata, MAC_TSCR, TSADDREG))
1040 static void xgbe_set_tstamp_time(struct xgbe_prv_data *pdata, unsigned int sec,
1043 /* Set the time values and tell the device */
1044 XGMAC_IOWRITE(pdata, MAC_STSUR, sec);
1045 XGMAC_IOWRITE(pdata, MAC_STNUR, nsec);
1046 XGMAC_IOWRITE_BITS(pdata, MAC_TSCR, TSINIT, 1);
1048 /* Wait for time update to complete */
1049 while (XGMAC_IOREAD_BITS(pdata, MAC_TSCR, TSINIT))
1053 static u64 xgbe_get_tstamp_time(struct xgbe_prv_data *pdata)
1057 nsec = XGMAC_IOREAD(pdata, MAC_STSR);
1058 nsec *= NSEC_PER_SEC;
1059 nsec += XGMAC_IOREAD(pdata, MAC_STNR);
1064 static u64 xgbe_get_tx_tstamp(struct xgbe_prv_data *pdata)
1066 unsigned int tx_snr;
1069 tx_snr = XGMAC_IOREAD(pdata, MAC_TXSNR);
1070 if (XGMAC_GET_BITS(tx_snr, MAC_TXSNR, TXTSSTSMIS))
1073 nsec = XGMAC_IOREAD(pdata, MAC_TXSSR);
1074 nsec *= NSEC_PER_SEC;
1080 static void xgbe_get_rx_tstamp(struct xgbe_packet_data *packet,
1081 struct xgbe_ring_desc *rdesc)
1085 if (XGMAC_GET_BITS_LE(rdesc->desc3, RX_CONTEXT_DESC3, TSA) &&
1086 !XGMAC_GET_BITS_LE(rdesc->desc3, RX_CONTEXT_DESC3, TSD)) {
1087 nsec = le32_to_cpu(rdesc->desc1);
1089 nsec |= le32_to_cpu(rdesc->desc0);
1090 if (nsec != 0xffffffffffffffffULL) {
1091 packet->rx_tstamp = nsec;
1092 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
1098 static int xgbe_config_tstamp(struct xgbe_prv_data *pdata,
1099 unsigned int mac_tscr)
1101 /* Set one nano-second accuracy */
1102 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSCTRLSSR, 1);
1104 /* Set fine timestamp update */
1105 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSCFUPDT, 1);
1107 /* Overwrite earlier timestamps */
1108 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TXTSSTSM, 1);
1110 XGMAC_IOWRITE(pdata, MAC_TSCR, mac_tscr);
1112 /* Exit if timestamping is not enabled */
1113 if (!XGMAC_GET_BITS(mac_tscr, MAC_TSCR, TSENA))
1116 /* Initialize time registers */
1117 XGMAC_IOWRITE_BITS(pdata, MAC_SSIR, SSINC, XGBE_TSTAMP_SSINC);
1118 XGMAC_IOWRITE_BITS(pdata, MAC_SSIR, SNSINC, XGBE_TSTAMP_SNSINC);
1119 xgbe_update_tstamp_addend(pdata, pdata->tstamp_addend);
1120 xgbe_set_tstamp_time(pdata, 0, 0);
1122 /* Initialize the timecounter */
1123 timecounter_init(&pdata->tstamp_tc, &pdata->tstamp_cc,
1124 ktime_to_ns(ktime_get_real()));
1129 static void xgbe_config_dcb_tc(struct xgbe_prv_data *pdata)
1131 struct ieee_ets *ets = pdata->ets;
1132 unsigned int total_weight, min_weight, weight;
1138 /* Set Tx to deficit weighted round robin scheduling algorithm (when
1139 * traffic class is using ETS algorithm)
1141 XGMAC_IOWRITE_BITS(pdata, MTL_OMR, ETSALG, MTL_ETSALG_DWRR);
1143 /* Set Traffic Class algorithms */
1144 total_weight = pdata->netdev->mtu * pdata->hw_feat.tc_cnt;
1145 min_weight = total_weight / 100;
1149 for (i = 0; i < pdata->hw_feat.tc_cnt; i++) {
1150 switch (ets->tc_tsa[i]) {
1151 case IEEE_8021QAZ_TSA_STRICT:
1152 DBGPR(" TC%u using SP\n", i);
1153 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_TC_ETSCR, TSA,
1156 case IEEE_8021QAZ_TSA_ETS:
1157 weight = total_weight * ets->tc_tx_bw[i] / 100;
1158 weight = clamp(weight, min_weight, total_weight);
1160 DBGPR(" TC%u using DWRR (weight %u)\n", i, weight);
1161 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_TC_ETSCR, TSA,
1163 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_TC_QWR, QW,
1170 static void xgbe_config_dcb_pfc(struct xgbe_prv_data *pdata)
1172 struct ieee_pfc *pfc = pdata->pfc;
1173 struct ieee_ets *ets = pdata->ets;
1174 unsigned int mask, reg, reg_val;
1175 unsigned int tc, prio;
1180 for (tc = 0; tc < pdata->hw_feat.tc_cnt; tc++) {
1182 for (prio = 0; prio < IEEE_8021QAZ_MAX_TCS; prio++) {
1183 if ((pfc->pfc_en & (1 << prio)) &&
1184 (ets->prio_tc[prio] == tc))
1185 mask |= (1 << prio);
1189 DBGPR(" TC%u PFC mask=%#x\n", tc, mask);
1190 reg = MTL_TCPM0R + (MTL_TCPM_INC * (tc / MTL_TCPM_TC_PER_REG));
1191 reg_val = XGMAC_IOREAD(pdata, reg);
1193 reg_val &= ~(0xff << ((tc % MTL_TCPM_TC_PER_REG) << 3));
1194 reg_val |= (mask << ((tc % MTL_TCPM_TC_PER_REG) << 3));
1196 XGMAC_IOWRITE(pdata, reg, reg_val);
1199 xgbe_config_flow_control(pdata);
1202 static void xgbe_pre_xmit(struct xgbe_channel *channel)
1204 struct xgbe_prv_data *pdata = channel->pdata;
1205 struct xgbe_ring *ring = channel->tx_ring;
1206 struct xgbe_ring_data *rdata;
1207 struct xgbe_ring_desc *rdesc;
1208 struct xgbe_packet_data *packet = &ring->packet_data;
1209 unsigned int csum, tso, vlan;
1210 unsigned int tso_context, vlan_context;
1211 unsigned int tx_coalesce, tx_frames;
1212 int start_index = ring->cur;
1215 DBGPR("-->xgbe_pre_xmit\n");
1217 csum = XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES,
1219 tso = XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES,
1221 vlan = XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES,
1224 if (tso && (packet->mss != ring->tx.cur_mss))
1229 if (vlan && (packet->vlan_ctag != ring->tx.cur_vlan_ctag))
1234 tx_coalesce = (pdata->tx_usecs || pdata->tx_frames) ? 1 : 0;
1235 tx_frames = pdata->tx_frames;
1236 if (tx_coalesce && !channel->tx_timer_active)
1237 ring->coalesce_count = 0;
1239 rdata = XGBE_GET_DESC_DATA(ring, ring->cur);
1240 rdesc = rdata->rdesc;
1242 /* Create a context descriptor if this is a TSO packet */
1243 if (tso_context || vlan_context) {
1245 DBGPR(" TSO context descriptor, mss=%u\n",
1248 /* Set the MSS size */
1249 XGMAC_SET_BITS_LE(rdesc->desc2, TX_CONTEXT_DESC2,
1252 /* Mark it as a CONTEXT descriptor */
1253 XGMAC_SET_BITS_LE(rdesc->desc3, TX_CONTEXT_DESC3,
1256 /* Indicate this descriptor contains the MSS */
1257 XGMAC_SET_BITS_LE(rdesc->desc3, TX_CONTEXT_DESC3,
1260 ring->tx.cur_mss = packet->mss;
1264 DBGPR(" VLAN context descriptor, ctag=%u\n",
1267 /* Mark it as a CONTEXT descriptor */
1268 XGMAC_SET_BITS_LE(rdesc->desc3, TX_CONTEXT_DESC3,
1271 /* Set the VLAN tag */
1272 XGMAC_SET_BITS_LE(rdesc->desc3, TX_CONTEXT_DESC3,
1273 VT, packet->vlan_ctag);
1275 /* Indicate this descriptor contains the VLAN tag */
1276 XGMAC_SET_BITS_LE(rdesc->desc3, TX_CONTEXT_DESC3,
1279 ring->tx.cur_vlan_ctag = packet->vlan_ctag;
1283 rdata = XGBE_GET_DESC_DATA(ring, ring->cur);
1284 rdesc = rdata->rdesc;
1287 /* Update buffer address (for TSO this is the header) */
1288 rdesc->desc0 = cpu_to_le32(lower_32_bits(rdata->skb_dma));
1289 rdesc->desc1 = cpu_to_le32(upper_32_bits(rdata->skb_dma));
1291 /* Update the buffer length */
1292 XGMAC_SET_BITS_LE(rdesc->desc2, TX_NORMAL_DESC2, HL_B1L,
1293 rdata->skb_dma_len);
1295 /* VLAN tag insertion check */
1297 XGMAC_SET_BITS_LE(rdesc->desc2, TX_NORMAL_DESC2, VTIR,
1298 TX_NORMAL_DESC2_VLAN_INSERT);
1300 /* Timestamp enablement check */
1301 if (XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES, PTP))
1302 XGMAC_SET_BITS_LE(rdesc->desc2, TX_NORMAL_DESC2, TTSE, 1);
1304 /* Set IC bit based on Tx coalescing settings */
1305 XGMAC_SET_BITS_LE(rdesc->desc2, TX_NORMAL_DESC2, IC, 1);
1306 if (tx_coalesce && (!tx_frames ||
1307 (++ring->coalesce_count % tx_frames)))
1309 XGMAC_SET_BITS_LE(rdesc->desc2, TX_NORMAL_DESC2, IC, 0);
1311 /* Mark it as First Descriptor */
1312 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, FD, 1);
1314 /* Mark it as a NORMAL descriptor */
1315 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, CTXT, 0);
1317 /* Set OWN bit if not the first descriptor */
1318 if (ring->cur != start_index)
1319 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, OWN, 1);
1323 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, TSE, 1);
1324 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, TCPPL,
1325 packet->tcp_payload_len);
1326 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, TCPHDRLEN,
1327 packet->tcp_header_len / 4);
1329 /* Enable CRC and Pad Insertion */
1330 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, CPC, 0);
1332 /* Enable HW CSUM */
1334 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3,
1337 /* Set the total length to be transmitted */
1338 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, FL,
1342 for (i = ring->cur - start_index + 1; i < packet->rdesc_count; i++) {
1344 rdata = XGBE_GET_DESC_DATA(ring, ring->cur);
1345 rdesc = rdata->rdesc;
1347 /* Update buffer address */
1348 rdesc->desc0 = cpu_to_le32(lower_32_bits(rdata->skb_dma));
1349 rdesc->desc1 = cpu_to_le32(upper_32_bits(rdata->skb_dma));
1351 /* Update the buffer length */
1352 XGMAC_SET_BITS_LE(rdesc->desc2, TX_NORMAL_DESC2, HL_B1L,
1353 rdata->skb_dma_len);
1355 /* Set IC bit based on Tx coalescing settings */
1356 XGMAC_SET_BITS_LE(rdesc->desc2, TX_NORMAL_DESC2, IC, 1);
1357 if (tx_coalesce && (!tx_frames ||
1358 (++ring->coalesce_count % tx_frames)))
1360 XGMAC_SET_BITS_LE(rdesc->desc2, TX_NORMAL_DESC2, IC, 0);
1363 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, OWN, 1);
1365 /* Mark it as NORMAL descriptor */
1366 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, CTXT, 0);
1368 /* Enable HW CSUM */
1370 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3,
1374 /* Set LAST bit for the last descriptor */
1375 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, LD, 1);
1377 /* In case the Tx DMA engine is running, make sure everything
1378 * is written to the descriptor(s) before setting the OWN bit
1379 * for the first descriptor
1383 /* Set OWN bit for the first descriptor */
1384 rdata = XGBE_GET_DESC_DATA(ring, start_index);
1385 rdesc = rdata->rdesc;
1386 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, OWN, 1);
1388 #ifdef XGMAC_ENABLE_TX_DESC_DUMP
1389 xgbe_dump_tx_desc(ring, start_index, packet->rdesc_count, 1);
1392 /* Make sure ownership is written to the descriptor */
1395 /* Issue a poll command to Tx DMA by writing address
1396 * of next immediate free descriptor */
1398 rdata = XGBE_GET_DESC_DATA(ring, ring->cur);
1399 XGMAC_DMA_IOWRITE(channel, DMA_CH_TDTR_LO,
1400 lower_32_bits(rdata->rdesc_dma));
1402 /* Start the Tx coalescing timer */
1403 if (tx_coalesce && !channel->tx_timer_active) {
1404 channel->tx_timer_active = 1;
1405 hrtimer_start(&channel->tx_timer,
1406 ktime_set(0, pdata->tx_usecs * NSEC_PER_USEC),
1410 DBGPR(" %s: descriptors %u to %u written\n",
1411 channel->name, start_index & (ring->rdesc_count - 1),
1412 (ring->cur - 1) & (ring->rdesc_count - 1));
1414 DBGPR("<--xgbe_pre_xmit\n");
1417 static int xgbe_dev_read(struct xgbe_channel *channel)
1419 struct xgbe_ring *ring = channel->rx_ring;
1420 struct xgbe_ring_data *rdata;
1421 struct xgbe_ring_desc *rdesc;
1422 struct xgbe_packet_data *packet = &ring->packet_data;
1423 struct net_device *netdev = channel->pdata->netdev;
1424 unsigned int err, etlt;
1426 DBGPR("-->xgbe_dev_read: cur = %d\n", ring->cur);
1428 rdata = XGBE_GET_DESC_DATA(ring, ring->cur);
1429 rdesc = rdata->rdesc;
1431 /* Check for data availability */
1432 if (XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, OWN))
1435 #ifdef XGMAC_ENABLE_RX_DESC_DUMP
1436 xgbe_dump_rx_desc(ring, rdesc, ring->cur);
1439 if (XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, CTXT)) {
1440 /* Timestamp Context Descriptor */
1441 xgbe_get_rx_tstamp(packet, rdesc);
1443 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
1445 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
1450 /* Normal Descriptor, be sure Context Descriptor bit is off */
1451 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, CONTEXT, 0);
1453 /* Indicate if a Context Descriptor is next */
1454 if (XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, CDA))
1455 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
1458 /* Get the packet length */
1459 rdata->len = XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, PL);
1461 if (!XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, LD)) {
1462 /* Not all the data has been transferred for this packet */
1463 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
1468 /* This is the last of the data for this packet */
1469 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
1472 /* Set checksum done indicator as appropriate */
1473 if (channel->pdata->netdev->features & NETIF_F_RXCSUM)
1474 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
1477 /* Check for errors (only valid in last descriptor) */
1478 err = XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, ES);
1479 etlt = XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, ETLT);
1480 DBGPR(" err=%u, etlt=%#x\n", err, etlt);
1482 if (!err || (err && !etlt)) {
1483 if ((etlt == 0x09) &&
1484 (netdev->features & NETIF_F_HW_VLAN_CTAG_RX)) {
1485 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
1487 packet->vlan_ctag = XGMAC_GET_BITS_LE(rdesc->desc0,
1490 DBGPR(" vlan-ctag=0x%04x\n", packet->vlan_ctag);
1493 if ((etlt == 0x05) || (etlt == 0x06))
1494 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
1497 XGMAC_SET_BITS(packet->errors, RX_PACKET_ERRORS,
1501 DBGPR("<--xgbe_dev_read: %s - descriptor=%u (cur=%d)\n", channel->name,
1502 ring->cur & (ring->rdesc_count - 1), ring->cur);
1507 static int xgbe_is_context_desc(struct xgbe_ring_desc *rdesc)
1509 /* Rx and Tx share CTXT bit, so check TDES3.CTXT bit */
1510 return XGMAC_GET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, CTXT);
1513 static int xgbe_is_last_desc(struct xgbe_ring_desc *rdesc)
1515 /* Rx and Tx share LD bit, so check TDES3.LD bit */
1516 return XGMAC_GET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, LD);
1519 static int xgbe_enable_int(struct xgbe_channel *channel,
1520 enum xgbe_int int_id)
1522 unsigned int dma_ch_ier;
1524 dma_ch_ier = XGMAC_DMA_IOREAD(channel, DMA_CH_IER);
1527 case XGMAC_INT_DMA_CH_SR_TI:
1528 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, TIE, 1);
1530 case XGMAC_INT_DMA_CH_SR_TPS:
1531 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, TXSE, 1);
1533 case XGMAC_INT_DMA_CH_SR_TBU:
1534 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, TBUE, 1);
1536 case XGMAC_INT_DMA_CH_SR_RI:
1537 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, RIE, 1);
1539 case XGMAC_INT_DMA_CH_SR_RBU:
1540 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, RBUE, 1);
1542 case XGMAC_INT_DMA_CH_SR_RPS:
1543 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, RSE, 1);
1545 case XGMAC_INT_DMA_CH_SR_TI_RI:
1546 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, TIE, 1);
1547 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, RIE, 1);
1549 case XGMAC_INT_DMA_CH_SR_FBE:
1550 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, FBEE, 1);
1552 case XGMAC_INT_DMA_ALL:
1553 dma_ch_ier |= channel->saved_ier;
1559 XGMAC_DMA_IOWRITE(channel, DMA_CH_IER, dma_ch_ier);
1564 static int xgbe_disable_int(struct xgbe_channel *channel,
1565 enum xgbe_int int_id)
1567 unsigned int dma_ch_ier;
1569 dma_ch_ier = XGMAC_DMA_IOREAD(channel, DMA_CH_IER);
1572 case XGMAC_INT_DMA_CH_SR_TI:
1573 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, TIE, 0);
1575 case XGMAC_INT_DMA_CH_SR_TPS:
1576 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, TXSE, 0);
1578 case XGMAC_INT_DMA_CH_SR_TBU:
1579 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, TBUE, 0);
1581 case XGMAC_INT_DMA_CH_SR_RI:
1582 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, RIE, 0);
1584 case XGMAC_INT_DMA_CH_SR_RBU:
1585 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, RBUE, 0);
1587 case XGMAC_INT_DMA_CH_SR_RPS:
1588 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, RSE, 0);
1590 case XGMAC_INT_DMA_CH_SR_TI_RI:
1591 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, TIE, 0);
1592 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, RIE, 0);
1594 case XGMAC_INT_DMA_CH_SR_FBE:
1595 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, FBEE, 0);
1597 case XGMAC_INT_DMA_ALL:
1598 channel->saved_ier = dma_ch_ier & XGBE_DMA_INTERRUPT_MASK;
1599 dma_ch_ier &= ~XGBE_DMA_INTERRUPT_MASK;
1605 XGMAC_DMA_IOWRITE(channel, DMA_CH_IER, dma_ch_ier);
1610 static int xgbe_exit(struct xgbe_prv_data *pdata)
1612 unsigned int count = 2000;
1614 DBGPR("-->xgbe_exit\n");
1616 /* Issue a software reset */
1617 XGMAC_IOWRITE_BITS(pdata, DMA_MR, SWR, 1);
1618 usleep_range(10, 15);
1620 /* Poll Until Poll Condition */
1621 while (count-- && XGMAC_IOREAD_BITS(pdata, DMA_MR, SWR))
1622 usleep_range(500, 600);
1627 DBGPR("<--xgbe_exit\n");
1632 static int xgbe_flush_tx_queues(struct xgbe_prv_data *pdata)
1634 unsigned int i, count;
1636 for (i = 0; i < pdata->tx_q_count; i++)
1637 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, FTQ, 1);
1639 /* Poll Until Poll Condition */
1640 for (i = 0; i < pdata->tx_q_count; i++) {
1642 while (count-- && XGMAC_MTL_IOREAD_BITS(pdata, i,
1644 usleep_range(500, 600);
1653 static void xgbe_config_dma_bus(struct xgbe_prv_data *pdata)
1655 /* Set enhanced addressing mode */
1656 XGMAC_IOWRITE_BITS(pdata, DMA_SBMR, EAME, 1);
1658 /* Set the System Bus mode */
1659 XGMAC_IOWRITE_BITS(pdata, DMA_SBMR, UNDEF, 1);
1660 XGMAC_IOWRITE_BITS(pdata, DMA_SBMR, BLEN_256, 1);
1663 static void xgbe_config_dma_cache(struct xgbe_prv_data *pdata)
1665 unsigned int arcache, awcache;
1668 XGMAC_SET_BITS(arcache, DMA_AXIARCR, DRC, pdata->arcache);
1669 XGMAC_SET_BITS(arcache, DMA_AXIARCR, DRD, pdata->axdomain);
1670 XGMAC_SET_BITS(arcache, DMA_AXIARCR, TEC, pdata->arcache);
1671 XGMAC_SET_BITS(arcache, DMA_AXIARCR, TED, pdata->axdomain);
1672 XGMAC_SET_BITS(arcache, DMA_AXIARCR, THC, pdata->arcache);
1673 XGMAC_SET_BITS(arcache, DMA_AXIARCR, THD, pdata->axdomain);
1674 XGMAC_IOWRITE(pdata, DMA_AXIARCR, arcache);
1677 XGMAC_SET_BITS(awcache, DMA_AXIAWCR, DWC, pdata->awcache);
1678 XGMAC_SET_BITS(awcache, DMA_AXIAWCR, DWD, pdata->axdomain);
1679 XGMAC_SET_BITS(awcache, DMA_AXIAWCR, RPC, pdata->awcache);
1680 XGMAC_SET_BITS(awcache, DMA_AXIAWCR, RPD, pdata->axdomain);
1681 XGMAC_SET_BITS(awcache, DMA_AXIAWCR, RHC, pdata->awcache);
1682 XGMAC_SET_BITS(awcache, DMA_AXIAWCR, RHD, pdata->axdomain);
1683 XGMAC_SET_BITS(awcache, DMA_AXIAWCR, TDC, pdata->awcache);
1684 XGMAC_SET_BITS(awcache, DMA_AXIAWCR, TDD, pdata->axdomain);
1685 XGMAC_IOWRITE(pdata, DMA_AXIAWCR, awcache);
1688 static void xgbe_config_mtl_mode(struct xgbe_prv_data *pdata)
1692 /* Set Tx to weighted round robin scheduling algorithm */
1693 XGMAC_IOWRITE_BITS(pdata, MTL_OMR, ETSALG, MTL_ETSALG_WRR);
1695 /* Set Tx traffic classes to use WRR algorithm with equal weights */
1696 for (i = 0; i < pdata->hw_feat.tc_cnt; i++) {
1697 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_TC_ETSCR, TSA,
1699 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_TC_QWR, QW, 1);
1702 /* Set Rx to strict priority algorithm */
1703 XGMAC_IOWRITE_BITS(pdata, MTL_OMR, RAA, MTL_RAA_SP);
1706 static unsigned int xgbe_calculate_per_queue_fifo(unsigned long fifo_size,
1707 unsigned char queue_count)
1709 unsigned int q_fifo_size = 0;
1710 enum xgbe_mtl_fifo_size p_fifo = XGMAC_MTL_FIFO_SIZE_256;
1712 /* Calculate Tx/Rx fifo share per queue */
1713 switch (fifo_size) {
1715 q_fifo_size = XGBE_FIFO_SIZE_B(128);
1718 q_fifo_size = XGBE_FIFO_SIZE_B(256);
1721 q_fifo_size = XGBE_FIFO_SIZE_B(512);
1724 q_fifo_size = XGBE_FIFO_SIZE_KB(1);
1727 q_fifo_size = XGBE_FIFO_SIZE_KB(2);
1730 q_fifo_size = XGBE_FIFO_SIZE_KB(4);
1733 q_fifo_size = XGBE_FIFO_SIZE_KB(8);
1736 q_fifo_size = XGBE_FIFO_SIZE_KB(16);
1739 q_fifo_size = XGBE_FIFO_SIZE_KB(32);
1742 q_fifo_size = XGBE_FIFO_SIZE_KB(64);
1745 q_fifo_size = XGBE_FIFO_SIZE_KB(128);
1748 q_fifo_size = XGBE_FIFO_SIZE_KB(256);
1751 q_fifo_size = q_fifo_size / queue_count;
1753 /* Set the queue fifo size programmable value */
1754 if (q_fifo_size >= XGBE_FIFO_SIZE_KB(256))
1755 p_fifo = XGMAC_MTL_FIFO_SIZE_256K;
1756 else if (q_fifo_size >= XGBE_FIFO_SIZE_KB(128))
1757 p_fifo = XGMAC_MTL_FIFO_SIZE_128K;
1758 else if (q_fifo_size >= XGBE_FIFO_SIZE_KB(64))
1759 p_fifo = XGMAC_MTL_FIFO_SIZE_64K;
1760 else if (q_fifo_size >= XGBE_FIFO_SIZE_KB(32))
1761 p_fifo = XGMAC_MTL_FIFO_SIZE_32K;
1762 else if (q_fifo_size >= XGBE_FIFO_SIZE_KB(16))
1763 p_fifo = XGMAC_MTL_FIFO_SIZE_16K;
1764 else if (q_fifo_size >= XGBE_FIFO_SIZE_KB(8))
1765 p_fifo = XGMAC_MTL_FIFO_SIZE_8K;
1766 else if (q_fifo_size >= XGBE_FIFO_SIZE_KB(4))
1767 p_fifo = XGMAC_MTL_FIFO_SIZE_4K;
1768 else if (q_fifo_size >= XGBE_FIFO_SIZE_KB(2))
1769 p_fifo = XGMAC_MTL_FIFO_SIZE_2K;
1770 else if (q_fifo_size >= XGBE_FIFO_SIZE_KB(1))
1771 p_fifo = XGMAC_MTL_FIFO_SIZE_1K;
1772 else if (q_fifo_size >= XGBE_FIFO_SIZE_B(512))
1773 p_fifo = XGMAC_MTL_FIFO_SIZE_512;
1774 else if (q_fifo_size >= XGBE_FIFO_SIZE_B(256))
1775 p_fifo = XGMAC_MTL_FIFO_SIZE_256;
1780 static void xgbe_config_tx_fifo_size(struct xgbe_prv_data *pdata)
1782 enum xgbe_mtl_fifo_size fifo_size;
1785 fifo_size = xgbe_calculate_per_queue_fifo(pdata->hw_feat.tx_fifo_size,
1788 for (i = 0; i < pdata->tx_q_count; i++)
1789 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, TQS, fifo_size);
1791 netdev_notice(pdata->netdev, "%d Tx queues, %d byte fifo per queue\n",
1792 pdata->tx_q_count, ((fifo_size + 1) * 256));
1795 static void xgbe_config_rx_fifo_size(struct xgbe_prv_data *pdata)
1797 enum xgbe_mtl_fifo_size fifo_size;
1800 fifo_size = xgbe_calculate_per_queue_fifo(pdata->hw_feat.rx_fifo_size,
1803 for (i = 0; i < pdata->rx_q_count; i++)
1804 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, RQS, fifo_size);
1806 netdev_notice(pdata->netdev, "%d Rx queues, %d byte fifo per queue\n",
1807 pdata->rx_q_count, ((fifo_size + 1) * 256));
1810 static void xgbe_config_queue_mapping(struct xgbe_prv_data *pdata)
1812 unsigned int qptc, qptc_extra, queue;
1813 unsigned int prio_queues;
1814 unsigned int ppq, ppq_extra, prio;
1816 unsigned int i, j, reg, reg_val;
1818 /* Map the MTL Tx Queues to Traffic Classes
1819 * Note: Tx Queues >= Traffic Classes
1821 qptc = pdata->tx_q_count / pdata->hw_feat.tc_cnt;
1822 qptc_extra = pdata->tx_q_count % pdata->hw_feat.tc_cnt;
1824 for (i = 0, queue = 0; i < pdata->hw_feat.tc_cnt; i++) {
1825 for (j = 0; j < qptc; j++) {
1826 DBGPR(" TXq%u mapped to TC%u\n", queue, i);
1827 XGMAC_MTL_IOWRITE_BITS(pdata, queue, MTL_Q_TQOMR,
1829 pdata->q2tc_map[queue++] = i;
1832 if (i < qptc_extra) {
1833 DBGPR(" TXq%u mapped to TC%u\n", queue, i);
1834 XGMAC_MTL_IOWRITE_BITS(pdata, queue, MTL_Q_TQOMR,
1836 pdata->q2tc_map[queue++] = i;
1840 /* Map the 8 VLAN priority values to available MTL Rx queues */
1841 prio_queues = min_t(unsigned int, IEEE_8021QAZ_MAX_TCS,
1843 ppq = IEEE_8021QAZ_MAX_TCS / prio_queues;
1844 ppq_extra = IEEE_8021QAZ_MAX_TCS % prio_queues;
1848 for (i = 0, prio = 0; i < prio_queues;) {
1850 for (j = 0; j < ppq; j++) {
1851 DBGPR(" PRIO%u mapped to RXq%u\n", prio, i);
1852 mask |= (1 << prio);
1853 pdata->prio2q_map[prio++] = i;
1856 if (i < ppq_extra) {
1857 DBGPR(" PRIO%u mapped to RXq%u\n", prio, i);
1858 mask |= (1 << prio);
1859 pdata->prio2q_map[prio++] = i;
1862 reg_val |= (mask << ((i++ % MAC_RQC2_Q_PER_REG) << 3));
1864 if ((i % MAC_RQC2_Q_PER_REG) && (i != prio_queues))
1867 XGMAC_IOWRITE(pdata, reg, reg_val);
1868 reg += MAC_RQC2_INC;
1872 /* Select dynamic mapping of MTL Rx queue to DMA Rx channel */
1875 for (i = 0; i < pdata->rx_q_count;) {
1876 reg_val |= (0x80 << ((i++ % MTL_RQDCM_Q_PER_REG) << 3));
1878 if ((i % MTL_RQDCM_Q_PER_REG) && (i != pdata->rx_q_count))
1881 XGMAC_IOWRITE(pdata, reg, reg_val);
1883 reg += MTL_RQDCM_INC;
1888 static void xgbe_config_flow_control_threshold(struct xgbe_prv_data *pdata)
1892 for (i = 0; i < pdata->rx_q_count; i++) {
1893 /* Activate flow control when less than 4k left in fifo */
1894 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, RFA, 2);
1896 /* De-activate flow control when more than 6k left in fifo */
1897 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, RFD, 4);
1901 static void xgbe_config_mac_address(struct xgbe_prv_data *pdata)
1903 xgbe_set_mac_address(pdata, pdata->netdev->dev_addr);
1905 /* Filtering is done using perfect filtering and hash filtering */
1906 if (pdata->hw_feat.hash_table_size) {
1907 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, HPF, 1);
1908 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, HUC, 1);
1909 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, HMC, 1);
1913 static void xgbe_config_jumbo_enable(struct xgbe_prv_data *pdata)
1917 val = (pdata->netdev->mtu > XGMAC_STD_PACKET_MTU) ? 1 : 0;
1919 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, JE, val);
1922 static void xgbe_config_checksum_offload(struct xgbe_prv_data *pdata)
1924 if (pdata->netdev->features & NETIF_F_RXCSUM)
1925 xgbe_enable_rx_csum(pdata);
1927 xgbe_disable_rx_csum(pdata);
1930 static void xgbe_config_vlan_support(struct xgbe_prv_data *pdata)
1932 /* Indicate that VLAN Tx CTAGs come from context descriptors */
1933 XGMAC_IOWRITE_BITS(pdata, MAC_VLANIR, CSVL, 0);
1934 XGMAC_IOWRITE_BITS(pdata, MAC_VLANIR, VLTI, 1);
1936 /* Set the current VLAN Hash Table register value */
1937 xgbe_update_vlan_hash_table(pdata);
1939 if (pdata->netdev->features & NETIF_F_HW_VLAN_CTAG_FILTER)
1940 xgbe_enable_rx_vlan_filtering(pdata);
1942 xgbe_disable_rx_vlan_filtering(pdata);
1944 if (pdata->netdev->features & NETIF_F_HW_VLAN_CTAG_RX)
1945 xgbe_enable_rx_vlan_stripping(pdata);
1947 xgbe_disable_rx_vlan_stripping(pdata);
1950 static void xgbe_tx_mmc_int(struct xgbe_prv_data *pdata)
1952 struct xgbe_mmc_stats *stats = &pdata->mmc_stats;
1953 unsigned int mmc_isr = XGMAC_IOREAD(pdata, MMC_TISR);
1955 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXOCTETCOUNT_GB))
1956 stats->txoctetcount_gb +=
1957 XGMAC_IOREAD(pdata, MMC_TXOCTETCOUNT_GB_LO);
1959 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXFRAMECOUNT_GB))
1960 stats->txframecount_gb +=
1961 XGMAC_IOREAD(pdata, MMC_TXFRAMECOUNT_GB_LO);
1963 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXBROADCASTFRAMES_G))
1964 stats->txbroadcastframes_g +=
1965 XGMAC_IOREAD(pdata, MMC_TXBROADCASTFRAMES_G_LO);
1967 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXMULTICASTFRAMES_G))
1968 stats->txmulticastframes_g +=
1969 XGMAC_IOREAD(pdata, MMC_TXMULTICASTFRAMES_G_LO);
1971 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TX64OCTETS_GB))
1972 stats->tx64octets_gb +=
1973 XGMAC_IOREAD(pdata, MMC_TX64OCTETS_GB_LO);
1975 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TX65TO127OCTETS_GB))
1976 stats->tx65to127octets_gb +=
1977 XGMAC_IOREAD(pdata, MMC_TX65TO127OCTETS_GB_LO);
1979 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TX128TO255OCTETS_GB))
1980 stats->tx128to255octets_gb +=
1981 XGMAC_IOREAD(pdata, MMC_TX128TO255OCTETS_GB_LO);
1983 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TX256TO511OCTETS_GB))
1984 stats->tx256to511octets_gb +=
1985 XGMAC_IOREAD(pdata, MMC_TX256TO511OCTETS_GB_LO);
1987 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TX512TO1023OCTETS_GB))
1988 stats->tx512to1023octets_gb +=
1989 XGMAC_IOREAD(pdata, MMC_TX512TO1023OCTETS_GB_LO);
1991 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TX1024TOMAXOCTETS_GB))
1992 stats->tx1024tomaxoctets_gb +=
1993 XGMAC_IOREAD(pdata, MMC_TX1024TOMAXOCTETS_GB_LO);
1995 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXUNICASTFRAMES_GB))
1996 stats->txunicastframes_gb +=
1997 XGMAC_IOREAD(pdata, MMC_TXUNICASTFRAMES_GB_LO);
1999 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXMULTICASTFRAMES_GB))
2000 stats->txmulticastframes_gb +=
2001 XGMAC_IOREAD(pdata, MMC_TXMULTICASTFRAMES_GB_LO);
2003 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXBROADCASTFRAMES_GB))
2004 stats->txbroadcastframes_g +=
2005 XGMAC_IOREAD(pdata, MMC_TXBROADCASTFRAMES_GB_LO);
2007 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXUNDERFLOWERROR))
2008 stats->txunderflowerror +=
2009 XGMAC_IOREAD(pdata, MMC_TXUNDERFLOWERROR_LO);
2011 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXOCTETCOUNT_G))
2012 stats->txoctetcount_g +=
2013 XGMAC_IOREAD(pdata, MMC_TXOCTETCOUNT_G_LO);
2015 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXFRAMECOUNT_G))
2016 stats->txframecount_g +=
2017 XGMAC_IOREAD(pdata, MMC_TXFRAMECOUNT_G_LO);
2019 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXPAUSEFRAMES))
2020 stats->txpauseframes +=
2021 XGMAC_IOREAD(pdata, MMC_TXPAUSEFRAMES_LO);
2023 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXVLANFRAMES_G))
2024 stats->txvlanframes_g +=
2025 XGMAC_IOREAD(pdata, MMC_TXVLANFRAMES_G_LO);
2028 static void xgbe_rx_mmc_int(struct xgbe_prv_data *pdata)
2030 struct xgbe_mmc_stats *stats = &pdata->mmc_stats;
2031 unsigned int mmc_isr = XGMAC_IOREAD(pdata, MMC_RISR);
2033 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXFRAMECOUNT_GB))
2034 stats->rxframecount_gb +=
2035 XGMAC_IOREAD(pdata, MMC_RXFRAMECOUNT_GB_LO);
2037 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXOCTETCOUNT_GB))
2038 stats->rxoctetcount_gb +=
2039 XGMAC_IOREAD(pdata, MMC_RXOCTETCOUNT_GB_LO);
2041 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXOCTETCOUNT_G))
2042 stats->rxoctetcount_g +=
2043 XGMAC_IOREAD(pdata, MMC_RXOCTETCOUNT_G_LO);
2045 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXBROADCASTFRAMES_G))
2046 stats->rxbroadcastframes_g +=
2047 XGMAC_IOREAD(pdata, MMC_RXBROADCASTFRAMES_G_LO);
2049 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXMULTICASTFRAMES_G))
2050 stats->rxmulticastframes_g +=
2051 XGMAC_IOREAD(pdata, MMC_RXMULTICASTFRAMES_G_LO);
2053 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXCRCERROR))
2054 stats->rxcrcerror +=
2055 XGMAC_IOREAD(pdata, MMC_RXCRCERROR_LO);
2057 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXRUNTERROR))
2058 stats->rxrunterror +=
2059 XGMAC_IOREAD(pdata, MMC_RXRUNTERROR);
2061 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXJABBERERROR))
2062 stats->rxjabbererror +=
2063 XGMAC_IOREAD(pdata, MMC_RXJABBERERROR);
2065 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXUNDERSIZE_G))
2066 stats->rxundersize_g +=
2067 XGMAC_IOREAD(pdata, MMC_RXUNDERSIZE_G);
2069 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXOVERSIZE_G))
2070 stats->rxoversize_g +=
2071 XGMAC_IOREAD(pdata, MMC_RXOVERSIZE_G);
2073 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RX64OCTETS_GB))
2074 stats->rx64octets_gb +=
2075 XGMAC_IOREAD(pdata, MMC_RX64OCTETS_GB_LO);
2077 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RX65TO127OCTETS_GB))
2078 stats->rx65to127octets_gb +=
2079 XGMAC_IOREAD(pdata, MMC_RX65TO127OCTETS_GB_LO);
2081 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RX128TO255OCTETS_GB))
2082 stats->rx128to255octets_gb +=
2083 XGMAC_IOREAD(pdata, MMC_RX128TO255OCTETS_GB_LO);
2085 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RX256TO511OCTETS_GB))
2086 stats->rx256to511octets_gb +=
2087 XGMAC_IOREAD(pdata, MMC_RX256TO511OCTETS_GB_LO);
2089 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RX512TO1023OCTETS_GB))
2090 stats->rx512to1023octets_gb +=
2091 XGMAC_IOREAD(pdata, MMC_RX512TO1023OCTETS_GB_LO);
2093 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RX1024TOMAXOCTETS_GB))
2094 stats->rx1024tomaxoctets_gb +=
2095 XGMAC_IOREAD(pdata, MMC_RX1024TOMAXOCTETS_GB_LO);
2097 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXUNICASTFRAMES_G))
2098 stats->rxunicastframes_g +=
2099 XGMAC_IOREAD(pdata, MMC_RXUNICASTFRAMES_G_LO);
2101 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXLENGTHERROR))
2102 stats->rxlengtherror +=
2103 XGMAC_IOREAD(pdata, MMC_RXLENGTHERROR_LO);
2105 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXOUTOFRANGETYPE))
2106 stats->rxoutofrangetype +=
2107 XGMAC_IOREAD(pdata, MMC_RXOUTOFRANGETYPE_LO);
2109 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXPAUSEFRAMES))
2110 stats->rxpauseframes +=
2111 XGMAC_IOREAD(pdata, MMC_RXPAUSEFRAMES_LO);
2113 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXFIFOOVERFLOW))
2114 stats->rxfifooverflow +=
2115 XGMAC_IOREAD(pdata, MMC_RXFIFOOVERFLOW_LO);
2117 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXVLANFRAMES_GB))
2118 stats->rxvlanframes_gb +=
2119 XGMAC_IOREAD(pdata, MMC_RXVLANFRAMES_GB_LO);
2121 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXWATCHDOGERROR))
2122 stats->rxwatchdogerror +=
2123 XGMAC_IOREAD(pdata, MMC_RXWATCHDOGERROR);
2126 static void xgbe_read_mmc_stats(struct xgbe_prv_data *pdata)
2128 struct xgbe_mmc_stats *stats = &pdata->mmc_stats;
2130 /* Freeze counters */
2131 XGMAC_IOWRITE_BITS(pdata, MMC_CR, MCF, 1);
2133 stats->txoctetcount_gb +=
2134 XGMAC_IOREAD(pdata, MMC_TXOCTETCOUNT_GB_LO);
2136 stats->txframecount_gb +=
2137 XGMAC_IOREAD(pdata, MMC_TXFRAMECOUNT_GB_LO);
2139 stats->txbroadcastframes_g +=
2140 XGMAC_IOREAD(pdata, MMC_TXBROADCASTFRAMES_G_LO);
2142 stats->txmulticastframes_g +=
2143 XGMAC_IOREAD(pdata, MMC_TXMULTICASTFRAMES_G_LO);
2145 stats->tx64octets_gb +=
2146 XGMAC_IOREAD(pdata, MMC_TX64OCTETS_GB_LO);
2148 stats->tx65to127octets_gb +=
2149 XGMAC_IOREAD(pdata, MMC_TX65TO127OCTETS_GB_LO);
2151 stats->tx128to255octets_gb +=
2152 XGMAC_IOREAD(pdata, MMC_TX128TO255OCTETS_GB_LO);
2154 stats->tx256to511octets_gb +=
2155 XGMAC_IOREAD(pdata, MMC_TX256TO511OCTETS_GB_LO);
2157 stats->tx512to1023octets_gb +=
2158 XGMAC_IOREAD(pdata, MMC_TX512TO1023OCTETS_GB_LO);
2160 stats->tx1024tomaxoctets_gb +=
2161 XGMAC_IOREAD(pdata, MMC_TX1024TOMAXOCTETS_GB_LO);
2163 stats->txunicastframes_gb +=
2164 XGMAC_IOREAD(pdata, MMC_TXUNICASTFRAMES_GB_LO);
2166 stats->txmulticastframes_gb +=
2167 XGMAC_IOREAD(pdata, MMC_TXMULTICASTFRAMES_GB_LO);
2169 stats->txbroadcastframes_g +=
2170 XGMAC_IOREAD(pdata, MMC_TXBROADCASTFRAMES_GB_LO);
2172 stats->txunderflowerror +=
2173 XGMAC_IOREAD(pdata, MMC_TXUNDERFLOWERROR_LO);
2175 stats->txoctetcount_g +=
2176 XGMAC_IOREAD(pdata, MMC_TXOCTETCOUNT_G_LO);
2178 stats->txframecount_g +=
2179 XGMAC_IOREAD(pdata, MMC_TXFRAMECOUNT_G_LO);
2181 stats->txpauseframes +=
2182 XGMAC_IOREAD(pdata, MMC_TXPAUSEFRAMES_LO);
2184 stats->txvlanframes_g +=
2185 XGMAC_IOREAD(pdata, MMC_TXVLANFRAMES_G_LO);
2187 stats->rxframecount_gb +=
2188 XGMAC_IOREAD(pdata, MMC_RXFRAMECOUNT_GB_LO);
2190 stats->rxoctetcount_gb +=
2191 XGMAC_IOREAD(pdata, MMC_RXOCTETCOUNT_GB_LO);
2193 stats->rxoctetcount_g +=
2194 XGMAC_IOREAD(pdata, MMC_RXOCTETCOUNT_G_LO);
2196 stats->rxbroadcastframes_g +=
2197 XGMAC_IOREAD(pdata, MMC_RXBROADCASTFRAMES_G_LO);
2199 stats->rxmulticastframes_g +=
2200 XGMAC_IOREAD(pdata, MMC_RXMULTICASTFRAMES_G_LO);
2202 stats->rxcrcerror +=
2203 XGMAC_IOREAD(pdata, MMC_RXCRCERROR_LO);
2205 stats->rxrunterror +=
2206 XGMAC_IOREAD(pdata, MMC_RXRUNTERROR);
2208 stats->rxjabbererror +=
2209 XGMAC_IOREAD(pdata, MMC_RXJABBERERROR);
2211 stats->rxundersize_g +=
2212 XGMAC_IOREAD(pdata, MMC_RXUNDERSIZE_G);
2214 stats->rxoversize_g +=
2215 XGMAC_IOREAD(pdata, MMC_RXOVERSIZE_G);
2217 stats->rx64octets_gb +=
2218 XGMAC_IOREAD(pdata, MMC_RX64OCTETS_GB_LO);
2220 stats->rx65to127octets_gb +=
2221 XGMAC_IOREAD(pdata, MMC_RX65TO127OCTETS_GB_LO);
2223 stats->rx128to255octets_gb +=
2224 XGMAC_IOREAD(pdata, MMC_RX128TO255OCTETS_GB_LO);
2226 stats->rx256to511octets_gb +=
2227 XGMAC_IOREAD(pdata, MMC_RX256TO511OCTETS_GB_LO);
2229 stats->rx512to1023octets_gb +=
2230 XGMAC_IOREAD(pdata, MMC_RX512TO1023OCTETS_GB_LO);
2232 stats->rx1024tomaxoctets_gb +=
2233 XGMAC_IOREAD(pdata, MMC_RX1024TOMAXOCTETS_GB_LO);
2235 stats->rxunicastframes_g +=
2236 XGMAC_IOREAD(pdata, MMC_RXUNICASTFRAMES_G_LO);
2238 stats->rxlengtherror +=
2239 XGMAC_IOREAD(pdata, MMC_RXLENGTHERROR_LO);
2241 stats->rxoutofrangetype +=
2242 XGMAC_IOREAD(pdata, MMC_RXOUTOFRANGETYPE_LO);
2244 stats->rxpauseframes +=
2245 XGMAC_IOREAD(pdata, MMC_RXPAUSEFRAMES_LO);
2247 stats->rxfifooverflow +=
2248 XGMAC_IOREAD(pdata, MMC_RXFIFOOVERFLOW_LO);
2250 stats->rxvlanframes_gb +=
2251 XGMAC_IOREAD(pdata, MMC_RXVLANFRAMES_GB_LO);
2253 stats->rxwatchdogerror +=
2254 XGMAC_IOREAD(pdata, MMC_RXWATCHDOGERROR);
2256 /* Un-freeze counters */
2257 XGMAC_IOWRITE_BITS(pdata, MMC_CR, MCF, 0);
2260 static void xgbe_config_mmc(struct xgbe_prv_data *pdata)
2262 /* Set counters to reset on read */
2263 XGMAC_IOWRITE_BITS(pdata, MMC_CR, ROR, 1);
2265 /* Reset the counters */
2266 XGMAC_IOWRITE_BITS(pdata, MMC_CR, CR, 1);
2269 static void xgbe_enable_tx(struct xgbe_prv_data *pdata)
2271 struct xgbe_channel *channel;
2274 /* Enable each Tx DMA channel */
2275 channel = pdata->channel;
2276 for (i = 0; i < pdata->channel_count; i++, channel++) {
2277 if (!channel->tx_ring)
2280 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_TCR, ST, 1);
2283 /* Enable each Tx queue */
2284 for (i = 0; i < pdata->tx_q_count; i++)
2285 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, TXQEN,
2289 XGMAC_IOWRITE_BITS(pdata, MAC_TCR, TE, 1);
2292 static void xgbe_disable_tx(struct xgbe_prv_data *pdata)
2294 struct xgbe_channel *channel;
2297 /* Disable MAC Tx */
2298 XGMAC_IOWRITE_BITS(pdata, MAC_TCR, TE, 0);
2300 /* Disable each Tx queue */
2301 for (i = 0; i < pdata->tx_q_count; i++)
2302 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, TXQEN, 0);
2304 /* Disable each Tx DMA channel */
2305 channel = pdata->channel;
2306 for (i = 0; i < pdata->channel_count; i++, channel++) {
2307 if (!channel->tx_ring)
2310 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_TCR, ST, 0);
2314 static void xgbe_enable_rx(struct xgbe_prv_data *pdata)
2316 struct xgbe_channel *channel;
2317 unsigned int reg_val, i;
2319 /* Enable each Rx DMA channel */
2320 channel = pdata->channel;
2321 for (i = 0; i < pdata->channel_count; i++, channel++) {
2322 if (!channel->rx_ring)
2325 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_RCR, SR, 1);
2328 /* Enable each Rx queue */
2330 for (i = 0; i < pdata->rx_q_count; i++)
2331 reg_val |= (0x02 << (i << 1));
2332 XGMAC_IOWRITE(pdata, MAC_RQC0R, reg_val);
2335 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, DCRCC, 1);
2336 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, CST, 1);
2337 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, ACS, 1);
2338 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, RE, 1);
2341 static void xgbe_disable_rx(struct xgbe_prv_data *pdata)
2343 struct xgbe_channel *channel;
2346 /* Disable MAC Rx */
2347 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, DCRCC, 0);
2348 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, CST, 0);
2349 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, ACS, 0);
2350 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, RE, 0);
2352 /* Disable each Rx queue */
2353 XGMAC_IOWRITE(pdata, MAC_RQC0R, 0);
2355 /* Disable each Rx DMA channel */
2356 channel = pdata->channel;
2357 for (i = 0; i < pdata->channel_count; i++, channel++) {
2358 if (!channel->rx_ring)
2361 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_RCR, SR, 0);
2365 static void xgbe_powerup_tx(struct xgbe_prv_data *pdata)
2367 struct xgbe_channel *channel;
2370 /* Enable each Tx DMA channel */
2371 channel = pdata->channel;
2372 for (i = 0; i < pdata->channel_count; i++, channel++) {
2373 if (!channel->tx_ring)
2376 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_TCR, ST, 1);
2380 XGMAC_IOWRITE_BITS(pdata, MAC_TCR, TE, 1);
2383 static void xgbe_powerdown_tx(struct xgbe_prv_data *pdata)
2385 struct xgbe_channel *channel;
2388 /* Disable MAC Tx */
2389 XGMAC_IOWRITE_BITS(pdata, MAC_TCR, TE, 0);
2391 /* Disable each Tx DMA channel */
2392 channel = pdata->channel;
2393 for (i = 0; i < pdata->channel_count; i++, channel++) {
2394 if (!channel->tx_ring)
2397 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_TCR, ST, 0);
2401 static void xgbe_powerup_rx(struct xgbe_prv_data *pdata)
2403 struct xgbe_channel *channel;
2406 /* Enable each Rx DMA channel */
2407 channel = pdata->channel;
2408 for (i = 0; i < pdata->channel_count; i++, channel++) {
2409 if (!channel->rx_ring)
2412 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_RCR, SR, 1);
2416 static void xgbe_powerdown_rx(struct xgbe_prv_data *pdata)
2418 struct xgbe_channel *channel;
2421 /* Disable each Rx DMA channel */
2422 channel = pdata->channel;
2423 for (i = 0; i < pdata->channel_count; i++, channel++) {
2424 if (!channel->rx_ring)
2427 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_RCR, SR, 0);
2431 static int xgbe_init(struct xgbe_prv_data *pdata)
2433 struct xgbe_desc_if *desc_if = &pdata->desc_if;
2436 DBGPR("-->xgbe_init\n");
2438 /* Flush Tx queues */
2439 ret = xgbe_flush_tx_queues(pdata);
2444 * Initialize DMA related features
2446 xgbe_config_dma_bus(pdata);
2447 xgbe_config_dma_cache(pdata);
2448 xgbe_config_osp_mode(pdata);
2449 xgbe_config_pblx8(pdata);
2450 xgbe_config_tx_pbl_val(pdata);
2451 xgbe_config_rx_pbl_val(pdata);
2452 xgbe_config_rx_coalesce(pdata);
2453 xgbe_config_tx_coalesce(pdata);
2454 xgbe_config_rx_buffer_size(pdata);
2455 xgbe_config_tso_mode(pdata);
2456 desc_if->wrapper_tx_desc_init(pdata);
2457 desc_if->wrapper_rx_desc_init(pdata);
2458 xgbe_enable_dma_interrupts(pdata);
2461 * Initialize MTL related features
2463 xgbe_config_mtl_mode(pdata);
2464 xgbe_config_queue_mapping(pdata);
2465 xgbe_config_tsf_mode(pdata, pdata->tx_sf_mode);
2466 xgbe_config_rsf_mode(pdata, pdata->rx_sf_mode);
2467 xgbe_config_tx_threshold(pdata, pdata->tx_threshold);
2468 xgbe_config_rx_threshold(pdata, pdata->rx_threshold);
2469 xgbe_config_tx_fifo_size(pdata);
2470 xgbe_config_rx_fifo_size(pdata);
2471 xgbe_config_flow_control_threshold(pdata);
2472 /*TODO: Error Packet and undersized good Packet forwarding enable
2475 xgbe_config_dcb_tc(pdata);
2476 xgbe_config_dcb_pfc(pdata);
2477 xgbe_enable_mtl_interrupts(pdata);
2480 * Initialize MAC related features
2482 xgbe_config_mac_address(pdata);
2483 xgbe_config_jumbo_enable(pdata);
2484 xgbe_config_flow_control(pdata);
2485 xgbe_config_checksum_offload(pdata);
2486 xgbe_config_vlan_support(pdata);
2487 xgbe_config_mmc(pdata);
2488 xgbe_enable_mac_interrupts(pdata);
2490 DBGPR("<--xgbe_init\n");
2495 void xgbe_init_function_ptrs_dev(struct xgbe_hw_if *hw_if)
2497 DBGPR("-->xgbe_init_function_ptrs\n");
2499 hw_if->tx_complete = xgbe_tx_complete;
2501 hw_if->set_promiscuous_mode = xgbe_set_promiscuous_mode;
2502 hw_if->set_all_multicast_mode = xgbe_set_all_multicast_mode;
2503 hw_if->add_mac_addresses = xgbe_add_mac_addresses;
2504 hw_if->set_mac_address = xgbe_set_mac_address;
2506 hw_if->enable_rx_csum = xgbe_enable_rx_csum;
2507 hw_if->disable_rx_csum = xgbe_disable_rx_csum;
2509 hw_if->enable_rx_vlan_stripping = xgbe_enable_rx_vlan_stripping;
2510 hw_if->disable_rx_vlan_stripping = xgbe_disable_rx_vlan_stripping;
2511 hw_if->enable_rx_vlan_filtering = xgbe_enable_rx_vlan_filtering;
2512 hw_if->disable_rx_vlan_filtering = xgbe_disable_rx_vlan_filtering;
2513 hw_if->update_vlan_hash_table = xgbe_update_vlan_hash_table;
2515 hw_if->read_mmd_regs = xgbe_read_mmd_regs;
2516 hw_if->write_mmd_regs = xgbe_write_mmd_regs;
2518 hw_if->set_gmii_speed = xgbe_set_gmii_speed;
2519 hw_if->set_gmii_2500_speed = xgbe_set_gmii_2500_speed;
2520 hw_if->set_xgmii_speed = xgbe_set_xgmii_speed;
2522 hw_if->enable_tx = xgbe_enable_tx;
2523 hw_if->disable_tx = xgbe_disable_tx;
2524 hw_if->enable_rx = xgbe_enable_rx;
2525 hw_if->disable_rx = xgbe_disable_rx;
2527 hw_if->powerup_tx = xgbe_powerup_tx;
2528 hw_if->powerdown_tx = xgbe_powerdown_tx;
2529 hw_if->powerup_rx = xgbe_powerup_rx;
2530 hw_if->powerdown_rx = xgbe_powerdown_rx;
2532 hw_if->pre_xmit = xgbe_pre_xmit;
2533 hw_if->dev_read = xgbe_dev_read;
2534 hw_if->enable_int = xgbe_enable_int;
2535 hw_if->disable_int = xgbe_disable_int;
2536 hw_if->init = xgbe_init;
2537 hw_if->exit = xgbe_exit;
2539 /* Descriptor related Sequences have to be initialized here */
2540 hw_if->tx_desc_init = xgbe_tx_desc_init;
2541 hw_if->rx_desc_init = xgbe_rx_desc_init;
2542 hw_if->tx_desc_reset = xgbe_tx_desc_reset;
2543 hw_if->rx_desc_reset = xgbe_rx_desc_reset;
2544 hw_if->is_last_desc = xgbe_is_last_desc;
2545 hw_if->is_context_desc = xgbe_is_context_desc;
2548 hw_if->config_tx_flow_control = xgbe_config_tx_flow_control;
2549 hw_if->config_rx_flow_control = xgbe_config_rx_flow_control;
2551 /* For RX coalescing */
2552 hw_if->config_rx_coalesce = xgbe_config_rx_coalesce;
2553 hw_if->config_tx_coalesce = xgbe_config_tx_coalesce;
2554 hw_if->usec_to_riwt = xgbe_usec_to_riwt;
2555 hw_if->riwt_to_usec = xgbe_riwt_to_usec;
2557 /* For RX and TX threshold config */
2558 hw_if->config_rx_threshold = xgbe_config_rx_threshold;
2559 hw_if->config_tx_threshold = xgbe_config_tx_threshold;
2561 /* For RX and TX Store and Forward Mode config */
2562 hw_if->config_rsf_mode = xgbe_config_rsf_mode;
2563 hw_if->config_tsf_mode = xgbe_config_tsf_mode;
2565 /* For TX DMA Operating on Second Frame config */
2566 hw_if->config_osp_mode = xgbe_config_osp_mode;
2568 /* For RX and TX PBL config */
2569 hw_if->config_rx_pbl_val = xgbe_config_rx_pbl_val;
2570 hw_if->get_rx_pbl_val = xgbe_get_rx_pbl_val;
2571 hw_if->config_tx_pbl_val = xgbe_config_tx_pbl_val;
2572 hw_if->get_tx_pbl_val = xgbe_get_tx_pbl_val;
2573 hw_if->config_pblx8 = xgbe_config_pblx8;
2575 /* For MMC statistics support */
2576 hw_if->tx_mmc_int = xgbe_tx_mmc_int;
2577 hw_if->rx_mmc_int = xgbe_rx_mmc_int;
2578 hw_if->read_mmc_stats = xgbe_read_mmc_stats;
2580 /* For PTP config */
2581 hw_if->config_tstamp = xgbe_config_tstamp;
2582 hw_if->update_tstamp_addend = xgbe_update_tstamp_addend;
2583 hw_if->set_tstamp_time = xgbe_set_tstamp_time;
2584 hw_if->get_tstamp_time = xgbe_get_tstamp_time;
2585 hw_if->get_tx_tstamp = xgbe_get_tx_tstamp;
2587 /* For Data Center Bridging config */
2588 hw_if->config_dcb_tc = xgbe_config_dcb_tc;
2589 hw_if->config_dcb_pfc = xgbe_config_dcb_pfc;
2591 DBGPR("<--xgbe_init_function_ptrs\n");