2 * AMD 10Gb Ethernet driver
4 * This file is available to you under your choice of the following two
9 * Copyright (c) 2014 Advanced Micro Devices, Inc.
11 * This file is free software; you may copy, redistribute and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation, either version 2 of the License, or (at
14 * your option) any later version.
16 * This file is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19 * General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program. If not, see <http://www.gnu.org/licenses/>.
24 * This file incorporates work covered by the following copyright and
26 * The Synopsys DWC ETHER XGMAC Software Driver and documentation
27 * (hereinafter "Software") is an unsupported proprietary work of Synopsys,
28 * Inc. unless otherwise expressly agreed to in writing between Synopsys
31 * The Software IS NOT an item of Licensed Software or Licensed Product
32 * under any End User Software License Agreement or Agreement for Licensed
33 * Product with Synopsys or any supplement thereto. Permission is hereby
34 * granted, free of charge, to any person obtaining a copy of this software
35 * annotated with this license and the Software, to deal in the Software
36 * without restriction, including without limitation the rights to use,
37 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies
38 * of the Software, and to permit persons to whom the Software is furnished
39 * to do so, subject to the following conditions:
41 * The above copyright notice and this permission notice shall be included
42 * in all copies or substantial portions of the Software.
44 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
45 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
46 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
47 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
48 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
49 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
50 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
51 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
52 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
53 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
54 * THE POSSIBILITY OF SUCH DAMAGE.
57 * License 2: Modified BSD
59 * Copyright (c) 2014 Advanced Micro Devices, Inc.
60 * All rights reserved.
62 * Redistribution and use in source and binary forms, with or without
63 * modification, are permitted provided that the following conditions are met:
64 * * Redistributions of source code must retain the above copyright
65 * notice, this list of conditions and the following disclaimer.
66 * * Redistributions in binary form must reproduce the above copyright
67 * notice, this list of conditions and the following disclaimer in the
68 * documentation and/or other materials provided with the distribution.
69 * * Neither the name of Advanced Micro Devices, Inc. nor the
70 * names of its contributors may be used to endorse or promote products
71 * derived from this software without specific prior written permission.
73 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
74 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
75 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
76 * ARE DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
77 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
78 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
79 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
80 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
81 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
82 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
84 * This file incorporates work covered by the following copyright and
86 * The Synopsys DWC ETHER XGMAC Software Driver and documentation
87 * (hereinafter "Software") is an unsupported proprietary work of Synopsys,
88 * Inc. unless otherwise expressly agreed to in writing between Synopsys
91 * The Software IS NOT an item of Licensed Software or Licensed Product
92 * under any End User Software License Agreement or Agreement for Licensed
93 * Product with Synopsys or any supplement thereto. Permission is hereby
94 * granted, free of charge, to any person obtaining a copy of this software
95 * annotated with this license and the Software, to deal in the Software
96 * without restriction, including without limitation the rights to use,
97 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies
98 * of the Software, and to permit persons to whom the Software is furnished
99 * to do so, subject to the following conditions:
101 * The above copyright notice and this permission notice shall be included
102 * in all copies or substantial portions of the Software.
104 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
105 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
106 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
107 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
108 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
109 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
110 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
111 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
112 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
113 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
114 * THE POSSIBILITY OF SUCH DAMAGE.
117 #include <linux/phy.h>
118 #include <linux/mdio.h>
119 #include <linux/clk.h>
120 #include <linux/bitrev.h>
121 #include <linux/crc32.h>
124 #include "xgbe-common.h"
126 static unsigned int xgbe_usec_to_riwt(struct xgbe_prv_data *pdata,
132 DBGPR("-->xgbe_usec_to_riwt\n");
134 rate = pdata->sysclk_rate;
137 * Convert the input usec value to the watchdog timer value. Each
138 * watchdog timer value is equivalent to 256 clock cycles.
139 * Calculate the required value as:
140 * ( usec * ( system_clock_mhz / 10^6 ) / 256
142 ret = (usec * (rate / 1000000)) / 256;
144 DBGPR("<--xgbe_usec_to_riwt\n");
149 static unsigned int xgbe_riwt_to_usec(struct xgbe_prv_data *pdata,
155 DBGPR("-->xgbe_riwt_to_usec\n");
157 rate = pdata->sysclk_rate;
160 * Convert the input watchdog timer value to the usec value. Each
161 * watchdog timer value is equivalent to 256 clock cycles.
162 * Calculate the required value as:
163 * ( riwt * 256 ) / ( system_clock_mhz / 10^6 )
165 ret = (riwt * 256) / (rate / 1000000);
167 DBGPR("<--xgbe_riwt_to_usec\n");
172 static int xgbe_config_pblx8(struct xgbe_prv_data *pdata)
174 struct xgbe_channel *channel;
177 channel = pdata->channel;
178 for (i = 0; i < pdata->channel_count; i++, channel++)
179 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_CR, PBLX8,
185 static int xgbe_get_tx_pbl_val(struct xgbe_prv_data *pdata)
187 return XGMAC_DMA_IOREAD_BITS(pdata->channel, DMA_CH_TCR, PBL);
190 static int xgbe_config_tx_pbl_val(struct xgbe_prv_data *pdata)
192 struct xgbe_channel *channel;
195 channel = pdata->channel;
196 for (i = 0; i < pdata->channel_count; i++, channel++) {
197 if (!channel->tx_ring)
200 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_TCR, PBL,
207 static int xgbe_get_rx_pbl_val(struct xgbe_prv_data *pdata)
209 return XGMAC_DMA_IOREAD_BITS(pdata->channel, DMA_CH_RCR, PBL);
212 static int xgbe_config_rx_pbl_val(struct xgbe_prv_data *pdata)
214 struct xgbe_channel *channel;
217 channel = pdata->channel;
218 for (i = 0; i < pdata->channel_count; i++, channel++) {
219 if (!channel->rx_ring)
222 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_RCR, PBL,
229 static int xgbe_config_osp_mode(struct xgbe_prv_data *pdata)
231 struct xgbe_channel *channel;
234 channel = pdata->channel;
235 for (i = 0; i < pdata->channel_count; i++, channel++) {
236 if (!channel->tx_ring)
239 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_TCR, OSP,
246 static int xgbe_config_rsf_mode(struct xgbe_prv_data *pdata, unsigned int val)
250 for (i = 0; i < pdata->rx_q_count; i++)
251 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, RSF, val);
256 static int xgbe_config_tsf_mode(struct xgbe_prv_data *pdata, unsigned int val)
260 for (i = 0; i < pdata->tx_q_count; i++)
261 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, TSF, val);
266 static int xgbe_config_rx_threshold(struct xgbe_prv_data *pdata,
271 for (i = 0; i < pdata->rx_q_count; i++)
272 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, RTC, val);
277 static int xgbe_config_tx_threshold(struct xgbe_prv_data *pdata,
282 for (i = 0; i < pdata->tx_q_count; i++)
283 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, TTC, val);
288 static int xgbe_config_rx_coalesce(struct xgbe_prv_data *pdata)
290 struct xgbe_channel *channel;
293 channel = pdata->channel;
294 for (i = 0; i < pdata->channel_count; i++, channel++) {
295 if (!channel->rx_ring)
298 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_RIWT, RWT,
305 static int xgbe_config_tx_coalesce(struct xgbe_prv_data *pdata)
310 static void xgbe_config_rx_buffer_size(struct xgbe_prv_data *pdata)
312 struct xgbe_channel *channel;
315 channel = pdata->channel;
316 for (i = 0; i < pdata->channel_count; i++, channel++) {
317 if (!channel->rx_ring)
320 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_RCR, RBSZ,
325 static void xgbe_config_tso_mode(struct xgbe_prv_data *pdata)
327 struct xgbe_channel *channel;
330 channel = pdata->channel;
331 for (i = 0; i < pdata->channel_count; i++, channel++) {
332 if (!channel->tx_ring)
335 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_TCR, TSE, 1);
339 static void xgbe_config_sph_mode(struct xgbe_prv_data *pdata)
341 struct xgbe_channel *channel;
344 channel = pdata->channel;
345 for (i = 0; i < pdata->channel_count; i++, channel++) {
346 if (!channel->rx_ring)
349 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_CR, SPH, 1);
352 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, HDSMS, XGBE_SPH_HDSMS_SIZE);
355 static int xgbe_write_rss_reg(struct xgbe_prv_data *pdata, unsigned int type,
356 unsigned int index, unsigned int val)
361 mutex_lock(&pdata->rss_mutex);
363 if (XGMAC_IOREAD_BITS(pdata, MAC_RSSAR, OB)) {
368 XGMAC_IOWRITE(pdata, MAC_RSSDR, val);
370 XGMAC_IOWRITE_BITS(pdata, MAC_RSSAR, RSSIA, index);
371 XGMAC_IOWRITE_BITS(pdata, MAC_RSSAR, ADDRT, type);
372 XGMAC_IOWRITE_BITS(pdata, MAC_RSSAR, CT, 0);
373 XGMAC_IOWRITE_BITS(pdata, MAC_RSSAR, OB, 1);
377 if (!XGMAC_IOREAD_BITS(pdata, MAC_RSSAR, OB))
380 usleep_range(1000, 1500);
386 mutex_unlock(&pdata->rss_mutex);
391 static int xgbe_write_rss_hash_key(struct xgbe_prv_data *pdata)
393 unsigned int key_regs = sizeof(pdata->rss_key) / sizeof(u32);
394 unsigned int *key = (unsigned int *)&pdata->rss_key;
398 ret = xgbe_write_rss_reg(pdata, XGBE_RSS_HASH_KEY_TYPE,
407 static int xgbe_write_rss_lookup_table(struct xgbe_prv_data *pdata)
412 for (i = 0; i < ARRAY_SIZE(pdata->rss_table); i++) {
413 ret = xgbe_write_rss_reg(pdata,
414 XGBE_RSS_LOOKUP_TABLE_TYPE, i,
415 pdata->rss_table[i]);
423 static int xgbe_set_rss_hash_key(struct xgbe_prv_data *pdata, const u8 *key)
425 memcpy(pdata->rss_key, key, sizeof(pdata->rss_key));
427 return xgbe_write_rss_hash_key(pdata);
430 static int xgbe_set_rss_lookup_table(struct xgbe_prv_data *pdata,
435 for (i = 0; i < ARRAY_SIZE(pdata->rss_table); i++)
436 XGMAC_SET_BITS(pdata->rss_table[i], MAC_RSSDR, DMCH, table[i]);
438 return xgbe_write_rss_lookup_table(pdata);
441 static int xgbe_enable_rss(struct xgbe_prv_data *pdata)
445 if (!pdata->hw_feat.rss)
448 /* Program the hash key */
449 ret = xgbe_write_rss_hash_key(pdata);
453 /* Program the lookup table */
454 ret = xgbe_write_rss_lookup_table(pdata);
458 /* Set the RSS options */
459 XGMAC_IOWRITE(pdata, MAC_RSSCR, pdata->rss_options);
462 XGMAC_IOWRITE_BITS(pdata, MAC_RSSCR, RSSE, 1);
467 static int xgbe_disable_rss(struct xgbe_prv_data *pdata)
469 if (!pdata->hw_feat.rss)
472 XGMAC_IOWRITE_BITS(pdata, MAC_RSSCR, RSSE, 0);
477 static void xgbe_config_rss(struct xgbe_prv_data *pdata)
481 if (!pdata->hw_feat.rss)
484 if (pdata->netdev->features & NETIF_F_RXHASH)
485 ret = xgbe_enable_rss(pdata);
487 ret = xgbe_disable_rss(pdata);
490 netdev_err(pdata->netdev,
491 "error configuring RSS, RSS disabled\n");
494 static int xgbe_disable_tx_flow_control(struct xgbe_prv_data *pdata)
496 unsigned int max_q_count, q_count;
497 unsigned int reg, reg_val;
500 /* Clear MTL flow control */
501 for (i = 0; i < pdata->rx_q_count; i++)
502 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, EHFC, 0);
504 /* Clear MAC flow control */
505 max_q_count = XGMAC_MAX_FLOW_CONTROL_QUEUES;
506 q_count = min_t(unsigned int, pdata->tx_q_count, max_q_count);
508 for (i = 0; i < q_count; i++) {
509 reg_val = XGMAC_IOREAD(pdata, reg);
510 XGMAC_SET_BITS(reg_val, MAC_Q0TFCR, TFE, 0);
511 XGMAC_IOWRITE(pdata, reg, reg_val);
513 reg += MAC_QTFCR_INC;
519 static int xgbe_enable_tx_flow_control(struct xgbe_prv_data *pdata)
521 unsigned int max_q_count, q_count;
522 unsigned int reg, reg_val;
525 /* Set MTL flow control */
526 for (i = 0; i < pdata->rx_q_count; i++)
527 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, EHFC, 1);
529 /* Set MAC flow control */
530 max_q_count = XGMAC_MAX_FLOW_CONTROL_QUEUES;
531 q_count = min_t(unsigned int, pdata->tx_q_count, max_q_count);
533 for (i = 0; i < q_count; i++) {
534 reg_val = XGMAC_IOREAD(pdata, reg);
536 /* Enable transmit flow control */
537 XGMAC_SET_BITS(reg_val, MAC_Q0TFCR, TFE, 1);
539 XGMAC_SET_BITS(reg_val, MAC_Q0TFCR, PT, 0xffff);
541 XGMAC_IOWRITE(pdata, reg, reg_val);
543 reg += MAC_QTFCR_INC;
549 static int xgbe_disable_rx_flow_control(struct xgbe_prv_data *pdata)
551 XGMAC_IOWRITE_BITS(pdata, MAC_RFCR, RFE, 0);
556 static int xgbe_enable_rx_flow_control(struct xgbe_prv_data *pdata)
558 XGMAC_IOWRITE_BITS(pdata, MAC_RFCR, RFE, 1);
563 static int xgbe_config_tx_flow_control(struct xgbe_prv_data *pdata)
565 struct ieee_pfc *pfc = pdata->pfc;
567 if (pdata->tx_pause || (pfc && pfc->pfc_en))
568 xgbe_enable_tx_flow_control(pdata);
570 xgbe_disable_tx_flow_control(pdata);
575 static int xgbe_config_rx_flow_control(struct xgbe_prv_data *pdata)
577 struct ieee_pfc *pfc = pdata->pfc;
579 if (pdata->rx_pause || (pfc && pfc->pfc_en))
580 xgbe_enable_rx_flow_control(pdata);
582 xgbe_disable_rx_flow_control(pdata);
587 static void xgbe_config_flow_control(struct xgbe_prv_data *pdata)
589 struct ieee_pfc *pfc = pdata->pfc;
591 xgbe_config_tx_flow_control(pdata);
592 xgbe_config_rx_flow_control(pdata);
594 XGMAC_IOWRITE_BITS(pdata, MAC_RFCR, PFCE,
595 (pfc && pfc->pfc_en) ? 1 : 0);
598 static void xgbe_enable_dma_interrupts(struct xgbe_prv_data *pdata)
600 struct xgbe_channel *channel;
601 unsigned int dma_ch_isr, dma_ch_ier;
604 channel = pdata->channel;
605 for (i = 0; i < pdata->channel_count; i++, channel++) {
606 /* Clear all the interrupts which are set */
607 dma_ch_isr = XGMAC_DMA_IOREAD(channel, DMA_CH_SR);
608 XGMAC_DMA_IOWRITE(channel, DMA_CH_SR, dma_ch_isr);
610 /* Clear all interrupt enable bits */
613 /* Enable following interrupts
614 * NIE - Normal Interrupt Summary Enable
615 * AIE - Abnormal Interrupt Summary Enable
616 * FBEE - Fatal Bus Error Enable
618 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, NIE, 1);
619 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, AIE, 1);
620 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, FBEE, 1);
622 if (channel->tx_ring) {
623 /* Enable the following Tx interrupts
624 * TIE - Transmit Interrupt Enable (unless using
625 * per channel interrupts)
627 if (!pdata->per_channel_irq)
628 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, TIE, 1);
630 if (channel->rx_ring) {
631 /* Enable following Rx interrupts
632 * RBUE - Receive Buffer Unavailable Enable
633 * RIE - Receive Interrupt Enable (unless using
634 * per channel interrupts)
636 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, RBUE, 1);
637 if (!pdata->per_channel_irq)
638 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, RIE, 1);
641 XGMAC_DMA_IOWRITE(channel, DMA_CH_IER, dma_ch_ier);
645 static void xgbe_enable_mtl_interrupts(struct xgbe_prv_data *pdata)
647 unsigned int mtl_q_isr;
648 unsigned int q_count, i;
650 q_count = max(pdata->hw_feat.tx_q_cnt, pdata->hw_feat.rx_q_cnt);
651 for (i = 0; i < q_count; i++) {
652 /* Clear all the interrupts which are set */
653 mtl_q_isr = XGMAC_MTL_IOREAD(pdata, i, MTL_Q_ISR);
654 XGMAC_MTL_IOWRITE(pdata, i, MTL_Q_ISR, mtl_q_isr);
656 /* No MTL interrupts to be enabled */
657 XGMAC_MTL_IOWRITE(pdata, i, MTL_Q_IER, 0);
661 static void xgbe_enable_mac_interrupts(struct xgbe_prv_data *pdata)
663 unsigned int mac_ier = 0;
665 /* Enable Timestamp interrupt */
666 XGMAC_SET_BITS(mac_ier, MAC_IER, TSIE, 1);
668 XGMAC_IOWRITE(pdata, MAC_IER, mac_ier);
670 /* Enable all counter interrupts */
671 XGMAC_IOWRITE_BITS(pdata, MMC_RIER, ALL_INTERRUPTS, 0xffffffff);
672 XGMAC_IOWRITE_BITS(pdata, MMC_TIER, ALL_INTERRUPTS, 0xffffffff);
675 static int xgbe_set_gmii_speed(struct xgbe_prv_data *pdata)
677 if (XGMAC_IOREAD_BITS(pdata, MAC_TCR, SS) == 0x3)
680 XGMAC_IOWRITE_BITS(pdata, MAC_TCR, SS, 0x3);
685 static int xgbe_set_gmii_2500_speed(struct xgbe_prv_data *pdata)
687 if (XGMAC_IOREAD_BITS(pdata, MAC_TCR, SS) == 0x2)
690 XGMAC_IOWRITE_BITS(pdata, MAC_TCR, SS, 0x2);
695 static int xgbe_set_xgmii_speed(struct xgbe_prv_data *pdata)
697 if (XGMAC_IOREAD_BITS(pdata, MAC_TCR, SS) == 0)
700 XGMAC_IOWRITE_BITS(pdata, MAC_TCR, SS, 0);
705 static int xgbe_set_promiscuous_mode(struct xgbe_prv_data *pdata,
708 unsigned int val = enable ? 1 : 0;
710 if (XGMAC_IOREAD_BITS(pdata, MAC_PFR, PR) == val)
713 DBGPR(" %s promiscuous mode\n", enable ? "entering" : "leaving");
714 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, PR, val);
719 static int xgbe_set_all_multicast_mode(struct xgbe_prv_data *pdata,
722 unsigned int val = enable ? 1 : 0;
724 if (XGMAC_IOREAD_BITS(pdata, MAC_PFR, PM) == val)
727 DBGPR(" %s allmulti mode\n", enable ? "entering" : "leaving");
728 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, PM, val);
733 static void xgbe_set_mac_reg(struct xgbe_prv_data *pdata,
734 struct netdev_hw_addr *ha, unsigned int *mac_reg)
736 unsigned int mac_addr_hi, mac_addr_lo;
743 mac_addr = (u8 *)&mac_addr_lo;
744 mac_addr[0] = ha->addr[0];
745 mac_addr[1] = ha->addr[1];
746 mac_addr[2] = ha->addr[2];
747 mac_addr[3] = ha->addr[3];
748 mac_addr = (u8 *)&mac_addr_hi;
749 mac_addr[0] = ha->addr[4];
750 mac_addr[1] = ha->addr[5];
752 DBGPR(" adding mac address %pM at 0x%04x\n", ha->addr,
755 XGMAC_SET_BITS(mac_addr_hi, MAC_MACA1HR, AE, 1);
758 XGMAC_IOWRITE(pdata, *mac_reg, mac_addr_hi);
759 *mac_reg += MAC_MACA_INC;
760 XGMAC_IOWRITE(pdata, *mac_reg, mac_addr_lo);
761 *mac_reg += MAC_MACA_INC;
764 static void xgbe_set_mac_addn_addrs(struct xgbe_prv_data *pdata)
766 struct net_device *netdev = pdata->netdev;
767 struct netdev_hw_addr *ha;
768 unsigned int mac_reg;
769 unsigned int addn_macs;
771 mac_reg = MAC_MACA1HR;
772 addn_macs = pdata->hw_feat.addn_mac;
774 if (netdev_uc_count(netdev) > addn_macs) {
775 xgbe_set_promiscuous_mode(pdata, 1);
777 netdev_for_each_uc_addr(ha, netdev) {
778 xgbe_set_mac_reg(pdata, ha, &mac_reg);
782 if (netdev_mc_count(netdev) > addn_macs) {
783 xgbe_set_all_multicast_mode(pdata, 1);
785 netdev_for_each_mc_addr(ha, netdev) {
786 xgbe_set_mac_reg(pdata, ha, &mac_reg);
792 /* Clear remaining additional MAC address entries */
794 xgbe_set_mac_reg(pdata, NULL, &mac_reg);
797 static void xgbe_set_mac_hash_table(struct xgbe_prv_data *pdata)
799 struct net_device *netdev = pdata->netdev;
800 struct netdev_hw_addr *ha;
801 unsigned int hash_reg;
802 unsigned int hash_table_shift, hash_table_count;
803 u32 hash_table[XGBE_MAC_HASH_TABLE_SIZE];
807 hash_table_shift = 26 - (pdata->hw_feat.hash_table_size >> 7);
808 hash_table_count = pdata->hw_feat.hash_table_size / 32;
809 memset(hash_table, 0, sizeof(hash_table));
811 /* Build the MAC Hash Table register values */
812 netdev_for_each_uc_addr(ha, netdev) {
813 crc = bitrev32(~crc32_le(~0, ha->addr, ETH_ALEN));
814 crc >>= hash_table_shift;
815 hash_table[crc >> 5] |= (1 << (crc & 0x1f));
818 netdev_for_each_mc_addr(ha, netdev) {
819 crc = bitrev32(~crc32_le(~0, ha->addr, ETH_ALEN));
820 crc >>= hash_table_shift;
821 hash_table[crc >> 5] |= (1 << (crc & 0x1f));
824 /* Set the MAC Hash Table registers */
826 for (i = 0; i < hash_table_count; i++) {
827 XGMAC_IOWRITE(pdata, hash_reg, hash_table[i]);
828 hash_reg += MAC_HTR_INC;
832 static int xgbe_add_mac_addresses(struct xgbe_prv_data *pdata)
834 if (pdata->hw_feat.hash_table_size)
835 xgbe_set_mac_hash_table(pdata);
837 xgbe_set_mac_addn_addrs(pdata);
842 static int xgbe_set_mac_address(struct xgbe_prv_data *pdata, u8 *addr)
844 unsigned int mac_addr_hi, mac_addr_lo;
846 mac_addr_hi = (addr[5] << 8) | (addr[4] << 0);
847 mac_addr_lo = (addr[3] << 24) | (addr[2] << 16) |
848 (addr[1] << 8) | (addr[0] << 0);
850 XGMAC_IOWRITE(pdata, MAC_MACA0HR, mac_addr_hi);
851 XGMAC_IOWRITE(pdata, MAC_MACA0LR, mac_addr_lo);
856 static int xgbe_read_mmd_regs(struct xgbe_prv_data *pdata, int prtad,
859 unsigned int mmd_address;
862 if (mmd_reg & MII_ADDR_C45)
863 mmd_address = mmd_reg & ~MII_ADDR_C45;
865 mmd_address = (pdata->mdio_mmd << 16) | (mmd_reg & 0xffff);
867 /* The PCS registers are accessed using mmio. The underlying APB3
868 * management interface uses indirect addressing to access the MMD
869 * register sets. This requires accessing of the PCS register in two
870 * phases, an address phase and a data phase.
872 * The mmio interface is based on 32-bit offsets and values. All
873 * register offsets must therefore be adjusted by left shifting the
874 * offset 2 bits and reading 32 bits of data.
876 mutex_lock(&pdata->xpcs_mutex);
877 XPCS_IOWRITE(pdata, PCS_MMD_SELECT << 2, mmd_address >> 8);
878 mmd_data = XPCS_IOREAD(pdata, (mmd_address & 0xff) << 2);
879 mutex_unlock(&pdata->xpcs_mutex);
884 static void xgbe_write_mmd_regs(struct xgbe_prv_data *pdata, int prtad,
885 int mmd_reg, int mmd_data)
887 unsigned int mmd_address;
889 if (mmd_reg & MII_ADDR_C45)
890 mmd_address = mmd_reg & ~MII_ADDR_C45;
892 mmd_address = (pdata->mdio_mmd << 16) | (mmd_reg & 0xffff);
894 /* If the PCS is changing modes, match the MAC speed to it */
895 if (((mmd_address >> 16) == MDIO_MMD_PCS) &&
896 ((mmd_address & 0xffff) == MDIO_CTRL2)) {
897 struct phy_device *phydev = pdata->phydev;
899 if (mmd_data & MDIO_PCS_CTRL2_TYPE) {
901 if (phydev->supported & SUPPORTED_1000baseKX_Full)
902 xgbe_set_gmii_speed(pdata);
904 xgbe_set_gmii_2500_speed(pdata);
907 xgbe_set_xgmii_speed(pdata);
911 /* The PCS registers are accessed using mmio. The underlying APB3
912 * management interface uses indirect addressing to access the MMD
913 * register sets. This requires accessing of the PCS register in two
914 * phases, an address phase and a data phase.
916 * The mmio interface is based on 32-bit offsets and values. All
917 * register offsets must therefore be adjusted by left shifting the
918 * offset 2 bits and reading 32 bits of data.
920 mutex_lock(&pdata->xpcs_mutex);
921 XPCS_IOWRITE(pdata, PCS_MMD_SELECT << 2, mmd_address >> 8);
922 XPCS_IOWRITE(pdata, (mmd_address & 0xff) << 2, mmd_data);
923 mutex_unlock(&pdata->xpcs_mutex);
926 static int xgbe_tx_complete(struct xgbe_ring_desc *rdesc)
928 return !XGMAC_GET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, OWN);
931 static int xgbe_disable_rx_csum(struct xgbe_prv_data *pdata)
933 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, IPC, 0);
938 static int xgbe_enable_rx_csum(struct xgbe_prv_data *pdata)
940 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, IPC, 1);
945 static int xgbe_enable_rx_vlan_stripping(struct xgbe_prv_data *pdata)
947 /* Put the VLAN tag in the Rx descriptor */
948 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, EVLRXS, 1);
950 /* Don't check the VLAN type */
951 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, DOVLTC, 1);
953 /* Check only C-TAG (0x8100) packets */
954 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, ERSVLM, 0);
956 /* Don't consider an S-TAG (0x88A8) packet as a VLAN packet */
957 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, ESVL, 0);
959 /* Enable VLAN tag stripping */
960 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, EVLS, 0x3);
965 static int xgbe_disable_rx_vlan_stripping(struct xgbe_prv_data *pdata)
967 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, EVLS, 0);
972 static int xgbe_enable_rx_vlan_filtering(struct xgbe_prv_data *pdata)
974 /* Enable VLAN filtering */
975 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, VTFE, 1);
977 /* Enable VLAN Hash Table filtering */
978 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, VTHM, 1);
980 /* Disable VLAN tag inverse matching */
981 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, VTIM, 0);
983 /* Only filter on the lower 12-bits of the VLAN tag */
984 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, ETV, 1);
986 /* In order for the VLAN Hash Table filtering to be effective,
987 * the VLAN tag identifier in the VLAN Tag Register must not
988 * be zero. Set the VLAN tag identifier to "1" to enable the
989 * VLAN Hash Table filtering. This implies that a VLAN tag of
990 * 1 will always pass filtering.
992 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, VL, 1);
997 static int xgbe_disable_rx_vlan_filtering(struct xgbe_prv_data *pdata)
999 /* Disable VLAN filtering */
1000 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, VTFE, 0);
1006 #define CRCPOLY_LE 0xedb88320
1008 static u32 xgbe_vid_crc32_le(__le16 vid_le)
1010 u32 poly = CRCPOLY_LE;
1013 unsigned char *data = (unsigned char *)&vid_le;
1014 unsigned char data_byte = 0;
1017 bits = get_bitmask_order(VLAN_VID_MASK);
1018 for (i = 0; i < bits; i++) {
1020 data_byte = data[i / 8];
1022 temp = ((crc & 1) ^ data_byte) & 1;
1033 static int xgbe_update_vlan_hash_table(struct xgbe_prv_data *pdata)
1038 u16 vlan_hash_table = 0;
1040 /* Generate the VLAN Hash Table value */
1041 for_each_set_bit(vid, pdata->active_vlans, VLAN_N_VID) {
1042 /* Get the CRC32 value of the VLAN ID */
1043 vid_le = cpu_to_le16(vid);
1044 crc = bitrev32(~xgbe_vid_crc32_le(vid_le)) >> 28;
1046 vlan_hash_table |= (1 << crc);
1049 /* Set the VLAN Hash Table filtering register */
1050 XGMAC_IOWRITE_BITS(pdata, MAC_VLANHTR, VLHT, vlan_hash_table);
1055 static void xgbe_tx_desc_reset(struct xgbe_ring_data *rdata)
1057 struct xgbe_ring_desc *rdesc = rdata->rdesc;
1059 /* Reset the Tx descriptor
1060 * Set buffer 1 (lo) address to zero
1061 * Set buffer 1 (hi) address to zero
1062 * Reset all other control bits (IC, TTSE, B2L & B1L)
1063 * Reset all other control bits (OWN, CTXT, FD, LD, CPC, CIC, etc)
1070 /* Make sure ownership is written to the descriptor */
1074 static void xgbe_tx_desc_init(struct xgbe_channel *channel)
1076 struct xgbe_ring *ring = channel->tx_ring;
1077 struct xgbe_ring_data *rdata;
1079 int start_index = ring->cur;
1081 DBGPR("-->tx_desc_init\n");
1083 /* Initialze all descriptors */
1084 for (i = 0; i < ring->rdesc_count; i++) {
1085 rdata = XGBE_GET_DESC_DATA(ring, i);
1087 /* Initialize Tx descriptor */
1088 xgbe_tx_desc_reset(rdata);
1091 /* Update the total number of Tx descriptors */
1092 XGMAC_DMA_IOWRITE(channel, DMA_CH_TDRLR, ring->rdesc_count - 1);
1094 /* Update the starting address of descriptor ring */
1095 rdata = XGBE_GET_DESC_DATA(ring, start_index);
1096 XGMAC_DMA_IOWRITE(channel, DMA_CH_TDLR_HI,
1097 upper_32_bits(rdata->rdesc_dma));
1098 XGMAC_DMA_IOWRITE(channel, DMA_CH_TDLR_LO,
1099 lower_32_bits(rdata->rdesc_dma));
1101 DBGPR("<--tx_desc_init\n");
1104 static void xgbe_rx_desc_reset(struct xgbe_ring_data *rdata)
1106 struct xgbe_ring_desc *rdesc = rdata->rdesc;
1108 /* Reset the Rx descriptor
1109 * Set buffer 1 (lo) address to header dma address (lo)
1110 * Set buffer 1 (hi) address to header dma address (hi)
1111 * Set buffer 2 (lo) address to buffer dma address (lo)
1112 * Set buffer 2 (hi) address to buffer dma address (hi) and
1113 * set control bits OWN and INTE
1115 rdesc->desc0 = cpu_to_le32(lower_32_bits(rdata->rx.hdr.dma));
1116 rdesc->desc1 = cpu_to_le32(upper_32_bits(rdata->rx.hdr.dma));
1117 rdesc->desc2 = cpu_to_le32(lower_32_bits(rdata->rx.buf.dma));
1118 rdesc->desc3 = cpu_to_le32(upper_32_bits(rdata->rx.buf.dma));
1120 XGMAC_SET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, INTE,
1121 rdata->interrupt ? 1 : 0);
1123 /* Since the Rx DMA engine is likely running, make sure everything
1124 * is written to the descriptor(s) before setting the OWN bit
1125 * for the descriptor
1129 XGMAC_SET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, OWN, 1);
1131 /* Make sure ownership is written to the descriptor */
1135 static void xgbe_rx_desc_init(struct xgbe_channel *channel)
1137 struct xgbe_prv_data *pdata = channel->pdata;
1138 struct xgbe_ring *ring = channel->rx_ring;
1139 struct xgbe_ring_data *rdata;
1140 unsigned int start_index = ring->cur;
1141 unsigned int rx_coalesce, rx_frames;
1144 DBGPR("-->rx_desc_init\n");
1146 rx_coalesce = (pdata->rx_riwt || pdata->rx_frames) ? 1 : 0;
1147 rx_frames = pdata->rx_frames;
1149 /* Initialize all descriptors */
1150 for (i = 0; i < ring->rdesc_count; i++) {
1151 rdata = XGBE_GET_DESC_DATA(ring, i);
1153 /* Set interrupt on completion bit as appropriate */
1154 if (rx_coalesce && (!rx_frames || ((i + 1) % rx_frames)))
1155 rdata->interrupt = 0;
1157 rdata->interrupt = 1;
1159 /* Initialize Rx descriptor */
1160 xgbe_rx_desc_reset(rdata);
1163 /* Update the total number of Rx descriptors */
1164 XGMAC_DMA_IOWRITE(channel, DMA_CH_RDRLR, ring->rdesc_count - 1);
1166 /* Update the starting address of descriptor ring */
1167 rdata = XGBE_GET_DESC_DATA(ring, start_index);
1168 XGMAC_DMA_IOWRITE(channel, DMA_CH_RDLR_HI,
1169 upper_32_bits(rdata->rdesc_dma));
1170 XGMAC_DMA_IOWRITE(channel, DMA_CH_RDLR_LO,
1171 lower_32_bits(rdata->rdesc_dma));
1173 /* Update the Rx Descriptor Tail Pointer */
1174 rdata = XGBE_GET_DESC_DATA(ring, start_index + ring->rdesc_count - 1);
1175 XGMAC_DMA_IOWRITE(channel, DMA_CH_RDTR_LO,
1176 lower_32_bits(rdata->rdesc_dma));
1178 DBGPR("<--rx_desc_init\n");
1181 static void xgbe_update_tstamp_addend(struct xgbe_prv_data *pdata,
1182 unsigned int addend)
1184 /* Set the addend register value and tell the device */
1185 XGMAC_IOWRITE(pdata, MAC_TSAR, addend);
1186 XGMAC_IOWRITE_BITS(pdata, MAC_TSCR, TSADDREG, 1);
1188 /* Wait for addend update to complete */
1189 while (XGMAC_IOREAD_BITS(pdata, MAC_TSCR, TSADDREG))
1193 static void xgbe_set_tstamp_time(struct xgbe_prv_data *pdata, unsigned int sec,
1196 /* Set the time values and tell the device */
1197 XGMAC_IOWRITE(pdata, MAC_STSUR, sec);
1198 XGMAC_IOWRITE(pdata, MAC_STNUR, nsec);
1199 XGMAC_IOWRITE_BITS(pdata, MAC_TSCR, TSINIT, 1);
1201 /* Wait for time update to complete */
1202 while (XGMAC_IOREAD_BITS(pdata, MAC_TSCR, TSINIT))
1206 static u64 xgbe_get_tstamp_time(struct xgbe_prv_data *pdata)
1210 nsec = XGMAC_IOREAD(pdata, MAC_STSR);
1211 nsec *= NSEC_PER_SEC;
1212 nsec += XGMAC_IOREAD(pdata, MAC_STNR);
1217 static u64 xgbe_get_tx_tstamp(struct xgbe_prv_data *pdata)
1219 unsigned int tx_snr;
1222 tx_snr = XGMAC_IOREAD(pdata, MAC_TXSNR);
1223 if (XGMAC_GET_BITS(tx_snr, MAC_TXSNR, TXTSSTSMIS))
1226 nsec = XGMAC_IOREAD(pdata, MAC_TXSSR);
1227 nsec *= NSEC_PER_SEC;
1233 static void xgbe_get_rx_tstamp(struct xgbe_packet_data *packet,
1234 struct xgbe_ring_desc *rdesc)
1238 if (XGMAC_GET_BITS_LE(rdesc->desc3, RX_CONTEXT_DESC3, TSA) &&
1239 !XGMAC_GET_BITS_LE(rdesc->desc3, RX_CONTEXT_DESC3, TSD)) {
1240 nsec = le32_to_cpu(rdesc->desc1);
1242 nsec |= le32_to_cpu(rdesc->desc0);
1243 if (nsec != 0xffffffffffffffffULL) {
1244 packet->rx_tstamp = nsec;
1245 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
1251 static int xgbe_config_tstamp(struct xgbe_prv_data *pdata,
1252 unsigned int mac_tscr)
1254 /* Set one nano-second accuracy */
1255 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSCTRLSSR, 1);
1257 /* Set fine timestamp update */
1258 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSCFUPDT, 1);
1260 /* Overwrite earlier timestamps */
1261 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TXTSSTSM, 1);
1263 XGMAC_IOWRITE(pdata, MAC_TSCR, mac_tscr);
1265 /* Exit if timestamping is not enabled */
1266 if (!XGMAC_GET_BITS(mac_tscr, MAC_TSCR, TSENA))
1269 /* Initialize time registers */
1270 XGMAC_IOWRITE_BITS(pdata, MAC_SSIR, SSINC, XGBE_TSTAMP_SSINC);
1271 XGMAC_IOWRITE_BITS(pdata, MAC_SSIR, SNSINC, XGBE_TSTAMP_SNSINC);
1272 xgbe_update_tstamp_addend(pdata, pdata->tstamp_addend);
1273 xgbe_set_tstamp_time(pdata, 0, 0);
1275 /* Initialize the timecounter */
1276 timecounter_init(&pdata->tstamp_tc, &pdata->tstamp_cc,
1277 ktime_to_ns(ktime_get_real()));
1282 static void xgbe_config_dcb_tc(struct xgbe_prv_data *pdata)
1284 struct ieee_ets *ets = pdata->ets;
1285 unsigned int total_weight, min_weight, weight;
1291 /* Set Tx to deficit weighted round robin scheduling algorithm (when
1292 * traffic class is using ETS algorithm)
1294 XGMAC_IOWRITE_BITS(pdata, MTL_OMR, ETSALG, MTL_ETSALG_DWRR);
1296 /* Set Traffic Class algorithms */
1297 total_weight = pdata->netdev->mtu * pdata->hw_feat.tc_cnt;
1298 min_weight = total_weight / 100;
1302 for (i = 0; i < pdata->hw_feat.tc_cnt; i++) {
1303 switch (ets->tc_tsa[i]) {
1304 case IEEE_8021QAZ_TSA_STRICT:
1305 DBGPR(" TC%u using SP\n", i);
1306 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_TC_ETSCR, TSA,
1309 case IEEE_8021QAZ_TSA_ETS:
1310 weight = total_weight * ets->tc_tx_bw[i] / 100;
1311 weight = clamp(weight, min_weight, total_weight);
1313 DBGPR(" TC%u using DWRR (weight %u)\n", i, weight);
1314 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_TC_ETSCR, TSA,
1316 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_TC_QWR, QW,
1323 static void xgbe_config_dcb_pfc(struct xgbe_prv_data *pdata)
1325 struct ieee_pfc *pfc = pdata->pfc;
1326 struct ieee_ets *ets = pdata->ets;
1327 unsigned int mask, reg, reg_val;
1328 unsigned int tc, prio;
1333 for (tc = 0; tc < pdata->hw_feat.tc_cnt; tc++) {
1335 for (prio = 0; prio < IEEE_8021QAZ_MAX_TCS; prio++) {
1336 if ((pfc->pfc_en & (1 << prio)) &&
1337 (ets->prio_tc[prio] == tc))
1338 mask |= (1 << prio);
1342 DBGPR(" TC%u PFC mask=%#x\n", tc, mask);
1343 reg = MTL_TCPM0R + (MTL_TCPM_INC * (tc / MTL_TCPM_TC_PER_REG));
1344 reg_val = XGMAC_IOREAD(pdata, reg);
1346 reg_val &= ~(0xff << ((tc % MTL_TCPM_TC_PER_REG) << 3));
1347 reg_val |= (mask << ((tc % MTL_TCPM_TC_PER_REG) << 3));
1349 XGMAC_IOWRITE(pdata, reg, reg_val);
1352 xgbe_config_flow_control(pdata);
1355 static void xgbe_tx_start_xmit(struct xgbe_channel *channel,
1356 struct xgbe_ring *ring)
1358 struct xgbe_prv_data *pdata = channel->pdata;
1359 struct xgbe_ring_data *rdata;
1361 /* Issue a poll command to Tx DMA by writing address
1362 * of next immediate free descriptor */
1363 rdata = XGBE_GET_DESC_DATA(ring, ring->cur);
1364 XGMAC_DMA_IOWRITE(channel, DMA_CH_TDTR_LO,
1365 lower_32_bits(rdata->rdesc_dma));
1367 /* Start the Tx coalescing timer */
1368 if (pdata->tx_usecs && !channel->tx_timer_active) {
1369 channel->tx_timer_active = 1;
1370 hrtimer_start(&channel->tx_timer,
1371 ktime_set(0, pdata->tx_usecs * NSEC_PER_USEC),
1375 ring->tx.xmit_more = 0;
1378 static void xgbe_dev_xmit(struct xgbe_channel *channel)
1380 struct xgbe_prv_data *pdata = channel->pdata;
1381 struct xgbe_ring *ring = channel->tx_ring;
1382 struct xgbe_ring_data *rdata;
1383 struct xgbe_ring_desc *rdesc;
1384 struct xgbe_packet_data *packet = &ring->packet_data;
1385 unsigned int csum, tso, vlan;
1386 unsigned int tso_context, vlan_context;
1387 unsigned int tx_set_ic;
1388 int start_index = ring->cur;
1389 int cur_index = ring->cur;
1392 DBGPR("-->xgbe_dev_xmit\n");
1394 csum = XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES,
1396 tso = XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES,
1398 vlan = XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES,
1401 if (tso && (packet->mss != ring->tx.cur_mss))
1406 if (vlan && (packet->vlan_ctag != ring->tx.cur_vlan_ctag))
1411 /* Determine if an interrupt should be generated for this Tx:
1413 * - Tx frame count exceeds the frame count setting
1414 * - Addition of Tx frame count to the frame count since the
1415 * last interrupt was set exceeds the frame count setting
1417 * - No frame count setting specified (ethtool -C ethX tx-frames 0)
1418 * - Addition of Tx frame count to the frame count since the
1419 * last interrupt was set does not exceed the frame count setting
1421 ring->coalesce_count += packet->tx_packets;
1422 if (!pdata->tx_frames)
1424 else if (packet->tx_packets > pdata->tx_frames)
1426 else if ((ring->coalesce_count % pdata->tx_frames) <
1432 rdata = XGBE_GET_DESC_DATA(ring, cur_index);
1433 rdesc = rdata->rdesc;
1435 /* Create a context descriptor if this is a TSO packet */
1436 if (tso_context || vlan_context) {
1438 DBGPR(" TSO context descriptor, mss=%u\n",
1441 /* Set the MSS size */
1442 XGMAC_SET_BITS_LE(rdesc->desc2, TX_CONTEXT_DESC2,
1445 /* Mark it as a CONTEXT descriptor */
1446 XGMAC_SET_BITS_LE(rdesc->desc3, TX_CONTEXT_DESC3,
1449 /* Indicate this descriptor contains the MSS */
1450 XGMAC_SET_BITS_LE(rdesc->desc3, TX_CONTEXT_DESC3,
1453 ring->tx.cur_mss = packet->mss;
1457 DBGPR(" VLAN context descriptor, ctag=%u\n",
1460 /* Mark it as a CONTEXT descriptor */
1461 XGMAC_SET_BITS_LE(rdesc->desc3, TX_CONTEXT_DESC3,
1464 /* Set the VLAN tag */
1465 XGMAC_SET_BITS_LE(rdesc->desc3, TX_CONTEXT_DESC3,
1466 VT, packet->vlan_ctag);
1468 /* Indicate this descriptor contains the VLAN tag */
1469 XGMAC_SET_BITS_LE(rdesc->desc3, TX_CONTEXT_DESC3,
1472 ring->tx.cur_vlan_ctag = packet->vlan_ctag;
1476 rdata = XGBE_GET_DESC_DATA(ring, cur_index);
1477 rdesc = rdata->rdesc;
1480 /* Update buffer address (for TSO this is the header) */
1481 rdesc->desc0 = cpu_to_le32(lower_32_bits(rdata->skb_dma));
1482 rdesc->desc1 = cpu_to_le32(upper_32_bits(rdata->skb_dma));
1484 /* Update the buffer length */
1485 XGMAC_SET_BITS_LE(rdesc->desc2, TX_NORMAL_DESC2, HL_B1L,
1486 rdata->skb_dma_len);
1488 /* VLAN tag insertion check */
1490 XGMAC_SET_BITS_LE(rdesc->desc2, TX_NORMAL_DESC2, VTIR,
1491 TX_NORMAL_DESC2_VLAN_INSERT);
1493 /* Timestamp enablement check */
1494 if (XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES, PTP))
1495 XGMAC_SET_BITS_LE(rdesc->desc2, TX_NORMAL_DESC2, TTSE, 1);
1497 /* Mark it as First Descriptor */
1498 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, FD, 1);
1500 /* Mark it as a NORMAL descriptor */
1501 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, CTXT, 0);
1503 /* Set OWN bit if not the first descriptor */
1504 if (cur_index != start_index)
1505 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, OWN, 1);
1509 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, TSE, 1);
1510 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, TCPPL,
1511 packet->tcp_payload_len);
1512 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, TCPHDRLEN,
1513 packet->tcp_header_len / 4);
1515 /* Enable CRC and Pad Insertion */
1516 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, CPC, 0);
1518 /* Enable HW CSUM */
1520 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3,
1523 /* Set the total length to be transmitted */
1524 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, FL,
1528 for (i = cur_index - start_index + 1; i < packet->rdesc_count; i++) {
1530 rdata = XGBE_GET_DESC_DATA(ring, cur_index);
1531 rdesc = rdata->rdesc;
1533 /* Update buffer address */
1534 rdesc->desc0 = cpu_to_le32(lower_32_bits(rdata->skb_dma));
1535 rdesc->desc1 = cpu_to_le32(upper_32_bits(rdata->skb_dma));
1537 /* Update the buffer length */
1538 XGMAC_SET_BITS_LE(rdesc->desc2, TX_NORMAL_DESC2, HL_B1L,
1539 rdata->skb_dma_len);
1542 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, OWN, 1);
1544 /* Mark it as NORMAL descriptor */
1545 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, CTXT, 0);
1547 /* Enable HW CSUM */
1549 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3,
1553 /* Set LAST bit for the last descriptor */
1554 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, LD, 1);
1556 /* Set IC bit based on Tx coalescing settings */
1558 XGMAC_SET_BITS_LE(rdesc->desc2, TX_NORMAL_DESC2, IC, 1);
1560 /* Save the Tx info to report back during cleanup */
1561 rdata->tx.packets = packet->tx_packets;
1562 rdata->tx.bytes = packet->tx_bytes;
1564 /* In case the Tx DMA engine is running, make sure everything
1565 * is written to the descriptor(s) before setting the OWN bit
1566 * for the first descriptor
1570 /* Set OWN bit for the first descriptor */
1571 rdata = XGBE_GET_DESC_DATA(ring, start_index);
1572 rdesc = rdata->rdesc;
1573 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, OWN, 1);
1575 #ifdef XGMAC_ENABLE_TX_DESC_DUMP
1576 xgbe_dump_tx_desc(ring, start_index, packet->rdesc_count, 1);
1579 /* Make sure ownership is written to the descriptor */
1582 ring->cur = cur_index + 1;
1583 if (!packet->skb->xmit_more ||
1584 netif_xmit_stopped(netdev_get_tx_queue(pdata->netdev,
1585 channel->queue_index)))
1586 xgbe_tx_start_xmit(channel, ring);
1588 ring->tx.xmit_more = 1;
1590 DBGPR(" %s: descriptors %u to %u written\n",
1591 channel->name, start_index & (ring->rdesc_count - 1),
1592 (ring->cur - 1) & (ring->rdesc_count - 1));
1594 DBGPR("<--xgbe_dev_xmit\n");
1597 static int xgbe_dev_read(struct xgbe_channel *channel)
1599 struct xgbe_ring *ring = channel->rx_ring;
1600 struct xgbe_ring_data *rdata;
1601 struct xgbe_ring_desc *rdesc;
1602 struct xgbe_packet_data *packet = &ring->packet_data;
1603 struct net_device *netdev = channel->pdata->netdev;
1604 unsigned int err, etlt, l34t;
1606 DBGPR("-->xgbe_dev_read: cur = %d\n", ring->cur);
1608 rdata = XGBE_GET_DESC_DATA(ring, ring->cur);
1609 rdesc = rdata->rdesc;
1611 /* Check for data availability */
1612 if (XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, OWN))
1615 /* Make sure descriptor fields are read after reading the OWN bit */
1618 #ifdef XGMAC_ENABLE_RX_DESC_DUMP
1619 xgbe_dump_rx_desc(ring, rdesc, ring->cur);
1622 if (XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, CTXT)) {
1623 /* Timestamp Context Descriptor */
1624 xgbe_get_rx_tstamp(packet, rdesc);
1626 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
1628 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
1633 /* Normal Descriptor, be sure Context Descriptor bit is off */
1634 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, CONTEXT, 0);
1636 /* Indicate if a Context Descriptor is next */
1637 if (XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, CDA))
1638 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
1641 /* Get the header length */
1642 if (XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, FD))
1643 rdata->rx.hdr_len = XGMAC_GET_BITS_LE(rdesc->desc2,
1644 RX_NORMAL_DESC2, HL);
1646 /* Get the RSS hash */
1647 if (XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, RSV)) {
1648 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
1651 packet->rss_hash = le32_to_cpu(rdesc->desc1);
1653 l34t = XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, L34T);
1655 case RX_DESC3_L34T_IPV4_TCP:
1656 case RX_DESC3_L34T_IPV4_UDP:
1657 case RX_DESC3_L34T_IPV6_TCP:
1658 case RX_DESC3_L34T_IPV6_UDP:
1659 packet->rss_hash_type = PKT_HASH_TYPE_L4;
1662 packet->rss_hash_type = PKT_HASH_TYPE_L3;
1666 /* Get the packet length */
1667 rdata->rx.len = XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, PL);
1669 if (!XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, LD)) {
1670 /* Not all the data has been transferred for this packet */
1671 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
1676 /* This is the last of the data for this packet */
1677 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
1680 /* Set checksum done indicator as appropriate */
1681 if (channel->pdata->netdev->features & NETIF_F_RXCSUM)
1682 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
1685 /* Check for errors (only valid in last descriptor) */
1686 err = XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, ES);
1687 etlt = XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, ETLT);
1688 DBGPR(" err=%u, etlt=%#x\n", err, etlt);
1690 if (!err || !etlt) {
1691 /* No error if err is 0 or etlt is 0 */
1692 if ((etlt == 0x09) &&
1693 (netdev->features & NETIF_F_HW_VLAN_CTAG_RX)) {
1694 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
1696 packet->vlan_ctag = XGMAC_GET_BITS_LE(rdesc->desc0,
1699 DBGPR(" vlan-ctag=0x%04x\n", packet->vlan_ctag);
1702 if ((etlt == 0x05) || (etlt == 0x06))
1703 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
1706 XGMAC_SET_BITS(packet->errors, RX_PACKET_ERRORS,
1710 DBGPR("<--xgbe_dev_read: %s - descriptor=%u (cur=%d)\n", channel->name,
1711 ring->cur & (ring->rdesc_count - 1), ring->cur);
1716 static int xgbe_is_context_desc(struct xgbe_ring_desc *rdesc)
1718 /* Rx and Tx share CTXT bit, so check TDES3.CTXT bit */
1719 return XGMAC_GET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, CTXT);
1722 static int xgbe_is_last_desc(struct xgbe_ring_desc *rdesc)
1724 /* Rx and Tx share LD bit, so check TDES3.LD bit */
1725 return XGMAC_GET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, LD);
1728 static int xgbe_enable_int(struct xgbe_channel *channel,
1729 enum xgbe_int int_id)
1731 unsigned int dma_ch_ier;
1733 dma_ch_ier = XGMAC_DMA_IOREAD(channel, DMA_CH_IER);
1736 case XGMAC_INT_DMA_CH_SR_TI:
1737 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, TIE, 1);
1739 case XGMAC_INT_DMA_CH_SR_TPS:
1740 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, TXSE, 1);
1742 case XGMAC_INT_DMA_CH_SR_TBU:
1743 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, TBUE, 1);
1745 case XGMAC_INT_DMA_CH_SR_RI:
1746 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, RIE, 1);
1748 case XGMAC_INT_DMA_CH_SR_RBU:
1749 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, RBUE, 1);
1751 case XGMAC_INT_DMA_CH_SR_RPS:
1752 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, RSE, 1);
1754 case XGMAC_INT_DMA_CH_SR_TI_RI:
1755 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, TIE, 1);
1756 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, RIE, 1);
1758 case XGMAC_INT_DMA_CH_SR_FBE:
1759 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, FBEE, 1);
1761 case XGMAC_INT_DMA_ALL:
1762 dma_ch_ier |= channel->saved_ier;
1768 XGMAC_DMA_IOWRITE(channel, DMA_CH_IER, dma_ch_ier);
1773 static int xgbe_disable_int(struct xgbe_channel *channel,
1774 enum xgbe_int int_id)
1776 unsigned int dma_ch_ier;
1778 dma_ch_ier = XGMAC_DMA_IOREAD(channel, DMA_CH_IER);
1781 case XGMAC_INT_DMA_CH_SR_TI:
1782 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, TIE, 0);
1784 case XGMAC_INT_DMA_CH_SR_TPS:
1785 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, TXSE, 0);
1787 case XGMAC_INT_DMA_CH_SR_TBU:
1788 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, TBUE, 0);
1790 case XGMAC_INT_DMA_CH_SR_RI:
1791 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, RIE, 0);
1793 case XGMAC_INT_DMA_CH_SR_RBU:
1794 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, RBUE, 0);
1796 case XGMAC_INT_DMA_CH_SR_RPS:
1797 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, RSE, 0);
1799 case XGMAC_INT_DMA_CH_SR_TI_RI:
1800 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, TIE, 0);
1801 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, RIE, 0);
1803 case XGMAC_INT_DMA_CH_SR_FBE:
1804 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, FBEE, 0);
1806 case XGMAC_INT_DMA_ALL:
1807 channel->saved_ier = dma_ch_ier & XGBE_DMA_INTERRUPT_MASK;
1808 dma_ch_ier &= ~XGBE_DMA_INTERRUPT_MASK;
1814 XGMAC_DMA_IOWRITE(channel, DMA_CH_IER, dma_ch_ier);
1819 static int xgbe_exit(struct xgbe_prv_data *pdata)
1821 unsigned int count = 2000;
1823 DBGPR("-->xgbe_exit\n");
1825 /* Issue a software reset */
1826 XGMAC_IOWRITE_BITS(pdata, DMA_MR, SWR, 1);
1827 usleep_range(10, 15);
1829 /* Poll Until Poll Condition */
1830 while (count-- && XGMAC_IOREAD_BITS(pdata, DMA_MR, SWR))
1831 usleep_range(500, 600);
1836 DBGPR("<--xgbe_exit\n");
1841 static int xgbe_flush_tx_queues(struct xgbe_prv_data *pdata)
1843 unsigned int i, count;
1845 if (XGMAC_GET_BITS(pdata->hw_feat.version, MAC_VR, SNPSVER) < 0x21)
1848 for (i = 0; i < pdata->tx_q_count; i++)
1849 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, FTQ, 1);
1851 /* Poll Until Poll Condition */
1852 for (i = 0; i < pdata->tx_q_count; i++) {
1854 while (count-- && XGMAC_MTL_IOREAD_BITS(pdata, i,
1856 usleep_range(500, 600);
1865 static void xgbe_config_dma_bus(struct xgbe_prv_data *pdata)
1867 /* Set enhanced addressing mode */
1868 XGMAC_IOWRITE_BITS(pdata, DMA_SBMR, EAME, 1);
1870 /* Set the System Bus mode */
1871 XGMAC_IOWRITE_BITS(pdata, DMA_SBMR, UNDEF, 1);
1872 XGMAC_IOWRITE_BITS(pdata, DMA_SBMR, BLEN_256, 1);
1875 static void xgbe_config_dma_cache(struct xgbe_prv_data *pdata)
1877 unsigned int arcache, awcache;
1880 XGMAC_SET_BITS(arcache, DMA_AXIARCR, DRC, pdata->arcache);
1881 XGMAC_SET_BITS(arcache, DMA_AXIARCR, DRD, pdata->axdomain);
1882 XGMAC_SET_BITS(arcache, DMA_AXIARCR, TEC, pdata->arcache);
1883 XGMAC_SET_BITS(arcache, DMA_AXIARCR, TED, pdata->axdomain);
1884 XGMAC_SET_BITS(arcache, DMA_AXIARCR, THC, pdata->arcache);
1885 XGMAC_SET_BITS(arcache, DMA_AXIARCR, THD, pdata->axdomain);
1886 XGMAC_IOWRITE(pdata, DMA_AXIARCR, arcache);
1889 XGMAC_SET_BITS(awcache, DMA_AXIAWCR, DWC, pdata->awcache);
1890 XGMAC_SET_BITS(awcache, DMA_AXIAWCR, DWD, pdata->axdomain);
1891 XGMAC_SET_BITS(awcache, DMA_AXIAWCR, RPC, pdata->awcache);
1892 XGMAC_SET_BITS(awcache, DMA_AXIAWCR, RPD, pdata->axdomain);
1893 XGMAC_SET_BITS(awcache, DMA_AXIAWCR, RHC, pdata->awcache);
1894 XGMAC_SET_BITS(awcache, DMA_AXIAWCR, RHD, pdata->axdomain);
1895 XGMAC_SET_BITS(awcache, DMA_AXIAWCR, TDC, pdata->awcache);
1896 XGMAC_SET_BITS(awcache, DMA_AXIAWCR, TDD, pdata->axdomain);
1897 XGMAC_IOWRITE(pdata, DMA_AXIAWCR, awcache);
1900 static void xgbe_config_mtl_mode(struct xgbe_prv_data *pdata)
1904 /* Set Tx to weighted round robin scheduling algorithm */
1905 XGMAC_IOWRITE_BITS(pdata, MTL_OMR, ETSALG, MTL_ETSALG_WRR);
1907 /* Set Tx traffic classes to use WRR algorithm with equal weights */
1908 for (i = 0; i < pdata->hw_feat.tc_cnt; i++) {
1909 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_TC_ETSCR, TSA,
1911 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_TC_QWR, QW, 1);
1914 /* Set Rx to strict priority algorithm */
1915 XGMAC_IOWRITE_BITS(pdata, MTL_OMR, RAA, MTL_RAA_SP);
1918 static unsigned int xgbe_calculate_per_queue_fifo(unsigned int fifo_size,
1919 unsigned int queue_count)
1921 unsigned int q_fifo_size = 0;
1922 enum xgbe_mtl_fifo_size p_fifo = XGMAC_MTL_FIFO_SIZE_256;
1924 /* Calculate Tx/Rx fifo share per queue */
1925 switch (fifo_size) {
1927 q_fifo_size = XGBE_FIFO_SIZE_B(128);
1930 q_fifo_size = XGBE_FIFO_SIZE_B(256);
1933 q_fifo_size = XGBE_FIFO_SIZE_B(512);
1936 q_fifo_size = XGBE_FIFO_SIZE_KB(1);
1939 q_fifo_size = XGBE_FIFO_SIZE_KB(2);
1942 q_fifo_size = XGBE_FIFO_SIZE_KB(4);
1945 q_fifo_size = XGBE_FIFO_SIZE_KB(8);
1948 q_fifo_size = XGBE_FIFO_SIZE_KB(16);
1951 q_fifo_size = XGBE_FIFO_SIZE_KB(32);
1954 q_fifo_size = XGBE_FIFO_SIZE_KB(64);
1957 q_fifo_size = XGBE_FIFO_SIZE_KB(128);
1960 q_fifo_size = XGBE_FIFO_SIZE_KB(256);
1964 /* The configured value is not the actual amount of fifo RAM */
1965 q_fifo_size = min_t(unsigned int, XGBE_FIFO_MAX, q_fifo_size);
1967 q_fifo_size = q_fifo_size / queue_count;
1969 /* Set the queue fifo size programmable value */
1970 if (q_fifo_size >= XGBE_FIFO_SIZE_KB(256))
1971 p_fifo = XGMAC_MTL_FIFO_SIZE_256K;
1972 else if (q_fifo_size >= XGBE_FIFO_SIZE_KB(128))
1973 p_fifo = XGMAC_MTL_FIFO_SIZE_128K;
1974 else if (q_fifo_size >= XGBE_FIFO_SIZE_KB(64))
1975 p_fifo = XGMAC_MTL_FIFO_SIZE_64K;
1976 else if (q_fifo_size >= XGBE_FIFO_SIZE_KB(32))
1977 p_fifo = XGMAC_MTL_FIFO_SIZE_32K;
1978 else if (q_fifo_size >= XGBE_FIFO_SIZE_KB(16))
1979 p_fifo = XGMAC_MTL_FIFO_SIZE_16K;
1980 else if (q_fifo_size >= XGBE_FIFO_SIZE_KB(8))
1981 p_fifo = XGMAC_MTL_FIFO_SIZE_8K;
1982 else if (q_fifo_size >= XGBE_FIFO_SIZE_KB(4))
1983 p_fifo = XGMAC_MTL_FIFO_SIZE_4K;
1984 else if (q_fifo_size >= XGBE_FIFO_SIZE_KB(2))
1985 p_fifo = XGMAC_MTL_FIFO_SIZE_2K;
1986 else if (q_fifo_size >= XGBE_FIFO_SIZE_KB(1))
1987 p_fifo = XGMAC_MTL_FIFO_SIZE_1K;
1988 else if (q_fifo_size >= XGBE_FIFO_SIZE_B(512))
1989 p_fifo = XGMAC_MTL_FIFO_SIZE_512;
1990 else if (q_fifo_size >= XGBE_FIFO_SIZE_B(256))
1991 p_fifo = XGMAC_MTL_FIFO_SIZE_256;
1996 static void xgbe_config_tx_fifo_size(struct xgbe_prv_data *pdata)
1998 enum xgbe_mtl_fifo_size fifo_size;
2001 fifo_size = xgbe_calculate_per_queue_fifo(pdata->hw_feat.tx_fifo_size,
2004 for (i = 0; i < pdata->tx_q_count; i++)
2005 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, TQS, fifo_size);
2007 netdev_notice(pdata->netdev, "%d Tx queues, %d byte fifo per queue\n",
2008 pdata->tx_q_count, ((fifo_size + 1) * 256));
2011 static void xgbe_config_rx_fifo_size(struct xgbe_prv_data *pdata)
2013 enum xgbe_mtl_fifo_size fifo_size;
2016 fifo_size = xgbe_calculate_per_queue_fifo(pdata->hw_feat.rx_fifo_size,
2019 for (i = 0; i < pdata->rx_q_count; i++)
2020 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, RQS, fifo_size);
2022 netdev_notice(pdata->netdev, "%d Rx queues, %d byte fifo per queue\n",
2023 pdata->rx_q_count, ((fifo_size + 1) * 256));
2026 static void xgbe_config_queue_mapping(struct xgbe_prv_data *pdata)
2028 unsigned int qptc, qptc_extra, queue;
2029 unsigned int prio_queues;
2030 unsigned int ppq, ppq_extra, prio;
2032 unsigned int i, j, reg, reg_val;
2034 /* Map the MTL Tx Queues to Traffic Classes
2035 * Note: Tx Queues >= Traffic Classes
2037 qptc = pdata->tx_q_count / pdata->hw_feat.tc_cnt;
2038 qptc_extra = pdata->tx_q_count % pdata->hw_feat.tc_cnt;
2040 for (i = 0, queue = 0; i < pdata->hw_feat.tc_cnt; i++) {
2041 for (j = 0; j < qptc; j++) {
2042 DBGPR(" TXq%u mapped to TC%u\n", queue, i);
2043 XGMAC_MTL_IOWRITE_BITS(pdata, queue, MTL_Q_TQOMR,
2045 pdata->q2tc_map[queue++] = i;
2048 if (i < qptc_extra) {
2049 DBGPR(" TXq%u mapped to TC%u\n", queue, i);
2050 XGMAC_MTL_IOWRITE_BITS(pdata, queue, MTL_Q_TQOMR,
2052 pdata->q2tc_map[queue++] = i;
2056 /* Map the 8 VLAN priority values to available MTL Rx queues */
2057 prio_queues = min_t(unsigned int, IEEE_8021QAZ_MAX_TCS,
2059 ppq = IEEE_8021QAZ_MAX_TCS / prio_queues;
2060 ppq_extra = IEEE_8021QAZ_MAX_TCS % prio_queues;
2064 for (i = 0, prio = 0; i < prio_queues;) {
2066 for (j = 0; j < ppq; j++) {
2067 DBGPR(" PRIO%u mapped to RXq%u\n", prio, i);
2068 mask |= (1 << prio);
2069 pdata->prio2q_map[prio++] = i;
2072 if (i < ppq_extra) {
2073 DBGPR(" PRIO%u mapped to RXq%u\n", prio, i);
2074 mask |= (1 << prio);
2075 pdata->prio2q_map[prio++] = i;
2078 reg_val |= (mask << ((i++ % MAC_RQC2_Q_PER_REG) << 3));
2080 if ((i % MAC_RQC2_Q_PER_REG) && (i != prio_queues))
2083 XGMAC_IOWRITE(pdata, reg, reg_val);
2084 reg += MAC_RQC2_INC;
2088 /* Select dynamic mapping of MTL Rx queue to DMA Rx channel */
2091 for (i = 0; i < pdata->rx_q_count;) {
2092 reg_val |= (0x80 << ((i++ % MTL_RQDCM_Q_PER_REG) << 3));
2094 if ((i % MTL_RQDCM_Q_PER_REG) && (i != pdata->rx_q_count))
2097 XGMAC_IOWRITE(pdata, reg, reg_val);
2099 reg += MTL_RQDCM_INC;
2104 static void xgbe_config_flow_control_threshold(struct xgbe_prv_data *pdata)
2108 for (i = 0; i < pdata->rx_q_count; i++) {
2109 /* Activate flow control when less than 4k left in fifo */
2110 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQFCR, RFA, 2);
2112 /* De-activate flow control when more than 6k left in fifo */
2113 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQFCR, RFD, 4);
2117 static void xgbe_config_mac_address(struct xgbe_prv_data *pdata)
2119 xgbe_set_mac_address(pdata, pdata->netdev->dev_addr);
2121 /* Filtering is done using perfect filtering and hash filtering */
2122 if (pdata->hw_feat.hash_table_size) {
2123 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, HPF, 1);
2124 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, HUC, 1);
2125 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, HMC, 1);
2129 static void xgbe_config_jumbo_enable(struct xgbe_prv_data *pdata)
2133 val = (pdata->netdev->mtu > XGMAC_STD_PACKET_MTU) ? 1 : 0;
2135 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, JE, val);
2138 static void xgbe_config_mac_speed(struct xgbe_prv_data *pdata)
2140 switch (pdata->phy_speed) {
2142 xgbe_set_xgmii_speed(pdata);
2146 xgbe_set_gmii_2500_speed(pdata);
2150 xgbe_set_gmii_speed(pdata);
2155 static void xgbe_config_checksum_offload(struct xgbe_prv_data *pdata)
2157 if (pdata->netdev->features & NETIF_F_RXCSUM)
2158 xgbe_enable_rx_csum(pdata);
2160 xgbe_disable_rx_csum(pdata);
2163 static void xgbe_config_vlan_support(struct xgbe_prv_data *pdata)
2165 /* Indicate that VLAN Tx CTAGs come from context descriptors */
2166 XGMAC_IOWRITE_BITS(pdata, MAC_VLANIR, CSVL, 0);
2167 XGMAC_IOWRITE_BITS(pdata, MAC_VLANIR, VLTI, 1);
2169 /* Set the current VLAN Hash Table register value */
2170 xgbe_update_vlan_hash_table(pdata);
2172 if (pdata->netdev->features & NETIF_F_HW_VLAN_CTAG_FILTER)
2173 xgbe_enable_rx_vlan_filtering(pdata);
2175 xgbe_disable_rx_vlan_filtering(pdata);
2177 if (pdata->netdev->features & NETIF_F_HW_VLAN_CTAG_RX)
2178 xgbe_enable_rx_vlan_stripping(pdata);
2180 xgbe_disable_rx_vlan_stripping(pdata);
2183 static u64 xgbe_mmc_read(struct xgbe_prv_data *pdata, unsigned int reg_lo)
2189 /* These registers are always 64 bit */
2190 case MMC_TXOCTETCOUNT_GB_LO:
2191 case MMC_TXOCTETCOUNT_G_LO:
2192 case MMC_RXOCTETCOUNT_GB_LO:
2193 case MMC_RXOCTETCOUNT_G_LO:
2201 val = XGMAC_IOREAD(pdata, reg_lo);
2204 val |= ((u64)XGMAC_IOREAD(pdata, reg_lo + 4) << 32);
2209 static void xgbe_tx_mmc_int(struct xgbe_prv_data *pdata)
2211 struct xgbe_mmc_stats *stats = &pdata->mmc_stats;
2212 unsigned int mmc_isr = XGMAC_IOREAD(pdata, MMC_TISR);
2214 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXOCTETCOUNT_GB))
2215 stats->txoctetcount_gb +=
2216 xgbe_mmc_read(pdata, MMC_TXOCTETCOUNT_GB_LO);
2218 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXFRAMECOUNT_GB))
2219 stats->txframecount_gb +=
2220 xgbe_mmc_read(pdata, MMC_TXFRAMECOUNT_GB_LO);
2222 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXBROADCASTFRAMES_G))
2223 stats->txbroadcastframes_g +=
2224 xgbe_mmc_read(pdata, MMC_TXBROADCASTFRAMES_G_LO);
2226 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXMULTICASTFRAMES_G))
2227 stats->txmulticastframes_g +=
2228 xgbe_mmc_read(pdata, MMC_TXMULTICASTFRAMES_G_LO);
2230 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TX64OCTETS_GB))
2231 stats->tx64octets_gb +=
2232 xgbe_mmc_read(pdata, MMC_TX64OCTETS_GB_LO);
2234 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TX65TO127OCTETS_GB))
2235 stats->tx65to127octets_gb +=
2236 xgbe_mmc_read(pdata, MMC_TX65TO127OCTETS_GB_LO);
2238 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TX128TO255OCTETS_GB))
2239 stats->tx128to255octets_gb +=
2240 xgbe_mmc_read(pdata, MMC_TX128TO255OCTETS_GB_LO);
2242 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TX256TO511OCTETS_GB))
2243 stats->tx256to511octets_gb +=
2244 xgbe_mmc_read(pdata, MMC_TX256TO511OCTETS_GB_LO);
2246 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TX512TO1023OCTETS_GB))
2247 stats->tx512to1023octets_gb +=
2248 xgbe_mmc_read(pdata, MMC_TX512TO1023OCTETS_GB_LO);
2250 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TX1024TOMAXOCTETS_GB))
2251 stats->tx1024tomaxoctets_gb +=
2252 xgbe_mmc_read(pdata, MMC_TX1024TOMAXOCTETS_GB_LO);
2254 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXUNICASTFRAMES_GB))
2255 stats->txunicastframes_gb +=
2256 xgbe_mmc_read(pdata, MMC_TXUNICASTFRAMES_GB_LO);
2258 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXMULTICASTFRAMES_GB))
2259 stats->txmulticastframes_gb +=
2260 xgbe_mmc_read(pdata, MMC_TXMULTICASTFRAMES_GB_LO);
2262 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXBROADCASTFRAMES_GB))
2263 stats->txbroadcastframes_g +=
2264 xgbe_mmc_read(pdata, MMC_TXBROADCASTFRAMES_GB_LO);
2266 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXUNDERFLOWERROR))
2267 stats->txunderflowerror +=
2268 xgbe_mmc_read(pdata, MMC_TXUNDERFLOWERROR_LO);
2270 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXOCTETCOUNT_G))
2271 stats->txoctetcount_g +=
2272 xgbe_mmc_read(pdata, MMC_TXOCTETCOUNT_G_LO);
2274 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXFRAMECOUNT_G))
2275 stats->txframecount_g +=
2276 xgbe_mmc_read(pdata, MMC_TXFRAMECOUNT_G_LO);
2278 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXPAUSEFRAMES))
2279 stats->txpauseframes +=
2280 xgbe_mmc_read(pdata, MMC_TXPAUSEFRAMES_LO);
2282 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXVLANFRAMES_G))
2283 stats->txvlanframes_g +=
2284 xgbe_mmc_read(pdata, MMC_TXVLANFRAMES_G_LO);
2287 static void xgbe_rx_mmc_int(struct xgbe_prv_data *pdata)
2289 struct xgbe_mmc_stats *stats = &pdata->mmc_stats;
2290 unsigned int mmc_isr = XGMAC_IOREAD(pdata, MMC_RISR);
2292 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXFRAMECOUNT_GB))
2293 stats->rxframecount_gb +=
2294 xgbe_mmc_read(pdata, MMC_RXFRAMECOUNT_GB_LO);
2296 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXOCTETCOUNT_GB))
2297 stats->rxoctetcount_gb +=
2298 xgbe_mmc_read(pdata, MMC_RXOCTETCOUNT_GB_LO);
2300 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXOCTETCOUNT_G))
2301 stats->rxoctetcount_g +=
2302 xgbe_mmc_read(pdata, MMC_RXOCTETCOUNT_G_LO);
2304 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXBROADCASTFRAMES_G))
2305 stats->rxbroadcastframes_g +=
2306 xgbe_mmc_read(pdata, MMC_RXBROADCASTFRAMES_G_LO);
2308 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXMULTICASTFRAMES_G))
2309 stats->rxmulticastframes_g +=
2310 xgbe_mmc_read(pdata, MMC_RXMULTICASTFRAMES_G_LO);
2312 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXCRCERROR))
2313 stats->rxcrcerror +=
2314 xgbe_mmc_read(pdata, MMC_RXCRCERROR_LO);
2316 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXRUNTERROR))
2317 stats->rxrunterror +=
2318 xgbe_mmc_read(pdata, MMC_RXRUNTERROR);
2320 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXJABBERERROR))
2321 stats->rxjabbererror +=
2322 xgbe_mmc_read(pdata, MMC_RXJABBERERROR);
2324 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXUNDERSIZE_G))
2325 stats->rxundersize_g +=
2326 xgbe_mmc_read(pdata, MMC_RXUNDERSIZE_G);
2328 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXOVERSIZE_G))
2329 stats->rxoversize_g +=
2330 xgbe_mmc_read(pdata, MMC_RXOVERSIZE_G);
2332 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RX64OCTETS_GB))
2333 stats->rx64octets_gb +=
2334 xgbe_mmc_read(pdata, MMC_RX64OCTETS_GB_LO);
2336 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RX65TO127OCTETS_GB))
2337 stats->rx65to127octets_gb +=
2338 xgbe_mmc_read(pdata, MMC_RX65TO127OCTETS_GB_LO);
2340 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RX128TO255OCTETS_GB))
2341 stats->rx128to255octets_gb +=
2342 xgbe_mmc_read(pdata, MMC_RX128TO255OCTETS_GB_LO);
2344 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RX256TO511OCTETS_GB))
2345 stats->rx256to511octets_gb +=
2346 xgbe_mmc_read(pdata, MMC_RX256TO511OCTETS_GB_LO);
2348 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RX512TO1023OCTETS_GB))
2349 stats->rx512to1023octets_gb +=
2350 xgbe_mmc_read(pdata, MMC_RX512TO1023OCTETS_GB_LO);
2352 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RX1024TOMAXOCTETS_GB))
2353 stats->rx1024tomaxoctets_gb +=
2354 xgbe_mmc_read(pdata, MMC_RX1024TOMAXOCTETS_GB_LO);
2356 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXUNICASTFRAMES_G))
2357 stats->rxunicastframes_g +=
2358 xgbe_mmc_read(pdata, MMC_RXUNICASTFRAMES_G_LO);
2360 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXLENGTHERROR))
2361 stats->rxlengtherror +=
2362 xgbe_mmc_read(pdata, MMC_RXLENGTHERROR_LO);
2364 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXOUTOFRANGETYPE))
2365 stats->rxoutofrangetype +=
2366 xgbe_mmc_read(pdata, MMC_RXOUTOFRANGETYPE_LO);
2368 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXPAUSEFRAMES))
2369 stats->rxpauseframes +=
2370 xgbe_mmc_read(pdata, MMC_RXPAUSEFRAMES_LO);
2372 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXFIFOOVERFLOW))
2373 stats->rxfifooverflow +=
2374 xgbe_mmc_read(pdata, MMC_RXFIFOOVERFLOW_LO);
2376 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXVLANFRAMES_GB))
2377 stats->rxvlanframes_gb +=
2378 xgbe_mmc_read(pdata, MMC_RXVLANFRAMES_GB_LO);
2380 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXWATCHDOGERROR))
2381 stats->rxwatchdogerror +=
2382 xgbe_mmc_read(pdata, MMC_RXWATCHDOGERROR);
2385 static void xgbe_read_mmc_stats(struct xgbe_prv_data *pdata)
2387 struct xgbe_mmc_stats *stats = &pdata->mmc_stats;
2389 /* Freeze counters */
2390 XGMAC_IOWRITE_BITS(pdata, MMC_CR, MCF, 1);
2392 stats->txoctetcount_gb +=
2393 xgbe_mmc_read(pdata, MMC_TXOCTETCOUNT_GB_LO);
2395 stats->txframecount_gb +=
2396 xgbe_mmc_read(pdata, MMC_TXFRAMECOUNT_GB_LO);
2398 stats->txbroadcastframes_g +=
2399 xgbe_mmc_read(pdata, MMC_TXBROADCASTFRAMES_G_LO);
2401 stats->txmulticastframes_g +=
2402 xgbe_mmc_read(pdata, MMC_TXMULTICASTFRAMES_G_LO);
2404 stats->tx64octets_gb +=
2405 xgbe_mmc_read(pdata, MMC_TX64OCTETS_GB_LO);
2407 stats->tx65to127octets_gb +=
2408 xgbe_mmc_read(pdata, MMC_TX65TO127OCTETS_GB_LO);
2410 stats->tx128to255octets_gb +=
2411 xgbe_mmc_read(pdata, MMC_TX128TO255OCTETS_GB_LO);
2413 stats->tx256to511octets_gb +=
2414 xgbe_mmc_read(pdata, MMC_TX256TO511OCTETS_GB_LO);
2416 stats->tx512to1023octets_gb +=
2417 xgbe_mmc_read(pdata, MMC_TX512TO1023OCTETS_GB_LO);
2419 stats->tx1024tomaxoctets_gb +=
2420 xgbe_mmc_read(pdata, MMC_TX1024TOMAXOCTETS_GB_LO);
2422 stats->txunicastframes_gb +=
2423 xgbe_mmc_read(pdata, MMC_TXUNICASTFRAMES_GB_LO);
2425 stats->txmulticastframes_gb +=
2426 xgbe_mmc_read(pdata, MMC_TXMULTICASTFRAMES_GB_LO);
2428 stats->txbroadcastframes_g +=
2429 xgbe_mmc_read(pdata, MMC_TXBROADCASTFRAMES_GB_LO);
2431 stats->txunderflowerror +=
2432 xgbe_mmc_read(pdata, MMC_TXUNDERFLOWERROR_LO);
2434 stats->txoctetcount_g +=
2435 xgbe_mmc_read(pdata, MMC_TXOCTETCOUNT_G_LO);
2437 stats->txframecount_g +=
2438 xgbe_mmc_read(pdata, MMC_TXFRAMECOUNT_G_LO);
2440 stats->txpauseframes +=
2441 xgbe_mmc_read(pdata, MMC_TXPAUSEFRAMES_LO);
2443 stats->txvlanframes_g +=
2444 xgbe_mmc_read(pdata, MMC_TXVLANFRAMES_G_LO);
2446 stats->rxframecount_gb +=
2447 xgbe_mmc_read(pdata, MMC_RXFRAMECOUNT_GB_LO);
2449 stats->rxoctetcount_gb +=
2450 xgbe_mmc_read(pdata, MMC_RXOCTETCOUNT_GB_LO);
2452 stats->rxoctetcount_g +=
2453 xgbe_mmc_read(pdata, MMC_RXOCTETCOUNT_G_LO);
2455 stats->rxbroadcastframes_g +=
2456 xgbe_mmc_read(pdata, MMC_RXBROADCASTFRAMES_G_LO);
2458 stats->rxmulticastframes_g +=
2459 xgbe_mmc_read(pdata, MMC_RXMULTICASTFRAMES_G_LO);
2461 stats->rxcrcerror +=
2462 xgbe_mmc_read(pdata, MMC_RXCRCERROR_LO);
2464 stats->rxrunterror +=
2465 xgbe_mmc_read(pdata, MMC_RXRUNTERROR);
2467 stats->rxjabbererror +=
2468 xgbe_mmc_read(pdata, MMC_RXJABBERERROR);
2470 stats->rxundersize_g +=
2471 xgbe_mmc_read(pdata, MMC_RXUNDERSIZE_G);
2473 stats->rxoversize_g +=
2474 xgbe_mmc_read(pdata, MMC_RXOVERSIZE_G);
2476 stats->rx64octets_gb +=
2477 xgbe_mmc_read(pdata, MMC_RX64OCTETS_GB_LO);
2479 stats->rx65to127octets_gb +=
2480 xgbe_mmc_read(pdata, MMC_RX65TO127OCTETS_GB_LO);
2482 stats->rx128to255octets_gb +=
2483 xgbe_mmc_read(pdata, MMC_RX128TO255OCTETS_GB_LO);
2485 stats->rx256to511octets_gb +=
2486 xgbe_mmc_read(pdata, MMC_RX256TO511OCTETS_GB_LO);
2488 stats->rx512to1023octets_gb +=
2489 xgbe_mmc_read(pdata, MMC_RX512TO1023OCTETS_GB_LO);
2491 stats->rx1024tomaxoctets_gb +=
2492 xgbe_mmc_read(pdata, MMC_RX1024TOMAXOCTETS_GB_LO);
2494 stats->rxunicastframes_g +=
2495 xgbe_mmc_read(pdata, MMC_RXUNICASTFRAMES_G_LO);
2497 stats->rxlengtherror +=
2498 xgbe_mmc_read(pdata, MMC_RXLENGTHERROR_LO);
2500 stats->rxoutofrangetype +=
2501 xgbe_mmc_read(pdata, MMC_RXOUTOFRANGETYPE_LO);
2503 stats->rxpauseframes +=
2504 xgbe_mmc_read(pdata, MMC_RXPAUSEFRAMES_LO);
2506 stats->rxfifooverflow +=
2507 xgbe_mmc_read(pdata, MMC_RXFIFOOVERFLOW_LO);
2509 stats->rxvlanframes_gb +=
2510 xgbe_mmc_read(pdata, MMC_RXVLANFRAMES_GB_LO);
2512 stats->rxwatchdogerror +=
2513 xgbe_mmc_read(pdata, MMC_RXWATCHDOGERROR);
2515 /* Un-freeze counters */
2516 XGMAC_IOWRITE_BITS(pdata, MMC_CR, MCF, 0);
2519 static void xgbe_config_mmc(struct xgbe_prv_data *pdata)
2521 /* Set counters to reset on read */
2522 XGMAC_IOWRITE_BITS(pdata, MMC_CR, ROR, 1);
2524 /* Reset the counters */
2525 XGMAC_IOWRITE_BITS(pdata, MMC_CR, CR, 1);
2528 static void xgbe_prepare_tx_stop(struct xgbe_prv_data *pdata,
2529 struct xgbe_channel *channel)
2531 unsigned int tx_dsr, tx_pos, tx_qidx;
2532 unsigned int tx_status;
2533 unsigned long tx_timeout;
2535 /* Calculate the status register to read and the position within */
2536 if (channel->queue_index < DMA_DSRX_FIRST_QUEUE) {
2538 tx_pos = (channel->queue_index * DMA_DSR_Q_WIDTH) +
2541 tx_qidx = channel->queue_index - DMA_DSRX_FIRST_QUEUE;
2543 tx_dsr = DMA_DSR1 + ((tx_qidx / DMA_DSRX_QPR) * DMA_DSRX_INC);
2544 tx_pos = ((tx_qidx % DMA_DSRX_QPR) * DMA_DSR_Q_WIDTH) +
2548 /* The Tx engine cannot be stopped if it is actively processing
2549 * descriptors. Wait for the Tx engine to enter the stopped or
2550 * suspended state. Don't wait forever though...
2552 tx_timeout = jiffies + (XGBE_DMA_STOP_TIMEOUT * HZ);
2553 while (time_before(jiffies, tx_timeout)) {
2554 tx_status = XGMAC_IOREAD(pdata, tx_dsr);
2555 tx_status = GET_BITS(tx_status, tx_pos, DMA_DSR_TPS_WIDTH);
2556 if ((tx_status == DMA_TPS_STOPPED) ||
2557 (tx_status == DMA_TPS_SUSPENDED))
2560 usleep_range(500, 1000);
2563 if (!time_before(jiffies, tx_timeout))
2564 netdev_info(pdata->netdev,
2565 "timed out waiting for Tx DMA channel %u to stop\n",
2566 channel->queue_index);
2569 static void xgbe_enable_tx(struct xgbe_prv_data *pdata)
2571 struct xgbe_channel *channel;
2574 /* Enable each Tx DMA channel */
2575 channel = pdata->channel;
2576 for (i = 0; i < pdata->channel_count; i++, channel++) {
2577 if (!channel->tx_ring)
2580 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_TCR, ST, 1);
2583 /* Enable each Tx queue */
2584 for (i = 0; i < pdata->tx_q_count; i++)
2585 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, TXQEN,
2589 XGMAC_IOWRITE_BITS(pdata, MAC_TCR, TE, 1);
2592 static void xgbe_disable_tx(struct xgbe_prv_data *pdata)
2594 struct xgbe_channel *channel;
2597 /* Prepare for Tx DMA channel stop */
2598 channel = pdata->channel;
2599 for (i = 0; i < pdata->channel_count; i++, channel++) {
2600 if (!channel->tx_ring)
2603 xgbe_prepare_tx_stop(pdata, channel);
2606 /* Disable MAC Tx */
2607 XGMAC_IOWRITE_BITS(pdata, MAC_TCR, TE, 0);
2609 /* Disable each Tx queue */
2610 for (i = 0; i < pdata->tx_q_count; i++)
2611 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, TXQEN, 0);
2613 /* Disable each Tx DMA channel */
2614 channel = pdata->channel;
2615 for (i = 0; i < pdata->channel_count; i++, channel++) {
2616 if (!channel->tx_ring)
2619 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_TCR, ST, 0);
2623 static void xgbe_enable_rx(struct xgbe_prv_data *pdata)
2625 struct xgbe_channel *channel;
2626 unsigned int reg_val, i;
2628 /* Enable each Rx DMA channel */
2629 channel = pdata->channel;
2630 for (i = 0; i < pdata->channel_count; i++, channel++) {
2631 if (!channel->rx_ring)
2634 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_RCR, SR, 1);
2637 /* Enable each Rx queue */
2639 for (i = 0; i < pdata->rx_q_count; i++)
2640 reg_val |= (0x02 << (i << 1));
2641 XGMAC_IOWRITE(pdata, MAC_RQC0R, reg_val);
2644 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, DCRCC, 1);
2645 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, CST, 1);
2646 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, ACS, 1);
2647 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, RE, 1);
2650 static void xgbe_disable_rx(struct xgbe_prv_data *pdata)
2652 struct xgbe_channel *channel;
2655 /* Disable MAC Rx */
2656 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, DCRCC, 0);
2657 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, CST, 0);
2658 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, ACS, 0);
2659 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, RE, 0);
2661 /* Disable each Rx queue */
2662 XGMAC_IOWRITE(pdata, MAC_RQC0R, 0);
2664 /* Disable each Rx DMA channel */
2665 channel = pdata->channel;
2666 for (i = 0; i < pdata->channel_count; i++, channel++) {
2667 if (!channel->rx_ring)
2670 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_RCR, SR, 0);
2674 static void xgbe_powerup_tx(struct xgbe_prv_data *pdata)
2676 struct xgbe_channel *channel;
2679 /* Enable each Tx DMA channel */
2680 channel = pdata->channel;
2681 for (i = 0; i < pdata->channel_count; i++, channel++) {
2682 if (!channel->tx_ring)
2685 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_TCR, ST, 1);
2689 XGMAC_IOWRITE_BITS(pdata, MAC_TCR, TE, 1);
2692 static void xgbe_powerdown_tx(struct xgbe_prv_data *pdata)
2694 struct xgbe_channel *channel;
2697 /* Prepare for Tx DMA channel stop */
2698 channel = pdata->channel;
2699 for (i = 0; i < pdata->channel_count; i++, channel++) {
2700 if (!channel->tx_ring)
2703 xgbe_prepare_tx_stop(pdata, channel);
2706 /* Disable MAC Tx */
2707 XGMAC_IOWRITE_BITS(pdata, MAC_TCR, TE, 0);
2709 /* Disable each Tx DMA channel */
2710 channel = pdata->channel;
2711 for (i = 0; i < pdata->channel_count; i++, channel++) {
2712 if (!channel->tx_ring)
2715 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_TCR, ST, 0);
2719 static void xgbe_powerup_rx(struct xgbe_prv_data *pdata)
2721 struct xgbe_channel *channel;
2724 /* Enable each Rx DMA channel */
2725 channel = pdata->channel;
2726 for (i = 0; i < pdata->channel_count; i++, channel++) {
2727 if (!channel->rx_ring)
2730 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_RCR, SR, 1);
2734 static void xgbe_powerdown_rx(struct xgbe_prv_data *pdata)
2736 struct xgbe_channel *channel;
2739 /* Disable each Rx DMA channel */
2740 channel = pdata->channel;
2741 for (i = 0; i < pdata->channel_count; i++, channel++) {
2742 if (!channel->rx_ring)
2745 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_RCR, SR, 0);
2749 static int xgbe_init(struct xgbe_prv_data *pdata)
2751 struct xgbe_desc_if *desc_if = &pdata->desc_if;
2754 DBGPR("-->xgbe_init\n");
2756 /* Flush Tx queues */
2757 ret = xgbe_flush_tx_queues(pdata);
2762 * Initialize DMA related features
2764 xgbe_config_dma_bus(pdata);
2765 xgbe_config_dma_cache(pdata);
2766 xgbe_config_osp_mode(pdata);
2767 xgbe_config_pblx8(pdata);
2768 xgbe_config_tx_pbl_val(pdata);
2769 xgbe_config_rx_pbl_val(pdata);
2770 xgbe_config_rx_coalesce(pdata);
2771 xgbe_config_tx_coalesce(pdata);
2772 xgbe_config_rx_buffer_size(pdata);
2773 xgbe_config_tso_mode(pdata);
2774 xgbe_config_sph_mode(pdata);
2775 xgbe_config_rss(pdata);
2776 desc_if->wrapper_tx_desc_init(pdata);
2777 desc_if->wrapper_rx_desc_init(pdata);
2778 xgbe_enable_dma_interrupts(pdata);
2781 * Initialize MTL related features
2783 xgbe_config_mtl_mode(pdata);
2784 xgbe_config_queue_mapping(pdata);
2785 xgbe_config_tsf_mode(pdata, pdata->tx_sf_mode);
2786 xgbe_config_rsf_mode(pdata, pdata->rx_sf_mode);
2787 xgbe_config_tx_threshold(pdata, pdata->tx_threshold);
2788 xgbe_config_rx_threshold(pdata, pdata->rx_threshold);
2789 xgbe_config_tx_fifo_size(pdata);
2790 xgbe_config_rx_fifo_size(pdata);
2791 xgbe_config_flow_control_threshold(pdata);
2792 /*TODO: Error Packet and undersized good Packet forwarding enable
2795 xgbe_config_dcb_tc(pdata);
2796 xgbe_config_dcb_pfc(pdata);
2797 xgbe_enable_mtl_interrupts(pdata);
2800 * Initialize MAC related features
2802 xgbe_config_mac_address(pdata);
2803 xgbe_config_jumbo_enable(pdata);
2804 xgbe_config_flow_control(pdata);
2805 xgbe_config_mac_speed(pdata);
2806 xgbe_config_checksum_offload(pdata);
2807 xgbe_config_vlan_support(pdata);
2808 xgbe_config_mmc(pdata);
2809 xgbe_enable_mac_interrupts(pdata);
2811 DBGPR("<--xgbe_init\n");
2816 void xgbe_init_function_ptrs_dev(struct xgbe_hw_if *hw_if)
2818 DBGPR("-->xgbe_init_function_ptrs\n");
2820 hw_if->tx_complete = xgbe_tx_complete;
2822 hw_if->set_promiscuous_mode = xgbe_set_promiscuous_mode;
2823 hw_if->set_all_multicast_mode = xgbe_set_all_multicast_mode;
2824 hw_if->add_mac_addresses = xgbe_add_mac_addresses;
2825 hw_if->set_mac_address = xgbe_set_mac_address;
2827 hw_if->enable_rx_csum = xgbe_enable_rx_csum;
2828 hw_if->disable_rx_csum = xgbe_disable_rx_csum;
2830 hw_if->enable_rx_vlan_stripping = xgbe_enable_rx_vlan_stripping;
2831 hw_if->disable_rx_vlan_stripping = xgbe_disable_rx_vlan_stripping;
2832 hw_if->enable_rx_vlan_filtering = xgbe_enable_rx_vlan_filtering;
2833 hw_if->disable_rx_vlan_filtering = xgbe_disable_rx_vlan_filtering;
2834 hw_if->update_vlan_hash_table = xgbe_update_vlan_hash_table;
2836 hw_if->read_mmd_regs = xgbe_read_mmd_regs;
2837 hw_if->write_mmd_regs = xgbe_write_mmd_regs;
2839 hw_if->set_gmii_speed = xgbe_set_gmii_speed;
2840 hw_if->set_gmii_2500_speed = xgbe_set_gmii_2500_speed;
2841 hw_if->set_xgmii_speed = xgbe_set_xgmii_speed;
2843 hw_if->enable_tx = xgbe_enable_tx;
2844 hw_if->disable_tx = xgbe_disable_tx;
2845 hw_if->enable_rx = xgbe_enable_rx;
2846 hw_if->disable_rx = xgbe_disable_rx;
2848 hw_if->powerup_tx = xgbe_powerup_tx;
2849 hw_if->powerdown_tx = xgbe_powerdown_tx;
2850 hw_if->powerup_rx = xgbe_powerup_rx;
2851 hw_if->powerdown_rx = xgbe_powerdown_rx;
2853 hw_if->dev_xmit = xgbe_dev_xmit;
2854 hw_if->dev_read = xgbe_dev_read;
2855 hw_if->enable_int = xgbe_enable_int;
2856 hw_if->disable_int = xgbe_disable_int;
2857 hw_if->init = xgbe_init;
2858 hw_if->exit = xgbe_exit;
2860 /* Descriptor related Sequences have to be initialized here */
2861 hw_if->tx_desc_init = xgbe_tx_desc_init;
2862 hw_if->rx_desc_init = xgbe_rx_desc_init;
2863 hw_if->tx_desc_reset = xgbe_tx_desc_reset;
2864 hw_if->rx_desc_reset = xgbe_rx_desc_reset;
2865 hw_if->is_last_desc = xgbe_is_last_desc;
2866 hw_if->is_context_desc = xgbe_is_context_desc;
2867 hw_if->tx_start_xmit = xgbe_tx_start_xmit;
2870 hw_if->config_tx_flow_control = xgbe_config_tx_flow_control;
2871 hw_if->config_rx_flow_control = xgbe_config_rx_flow_control;
2873 /* For RX coalescing */
2874 hw_if->config_rx_coalesce = xgbe_config_rx_coalesce;
2875 hw_if->config_tx_coalesce = xgbe_config_tx_coalesce;
2876 hw_if->usec_to_riwt = xgbe_usec_to_riwt;
2877 hw_if->riwt_to_usec = xgbe_riwt_to_usec;
2879 /* For RX and TX threshold config */
2880 hw_if->config_rx_threshold = xgbe_config_rx_threshold;
2881 hw_if->config_tx_threshold = xgbe_config_tx_threshold;
2883 /* For RX and TX Store and Forward Mode config */
2884 hw_if->config_rsf_mode = xgbe_config_rsf_mode;
2885 hw_if->config_tsf_mode = xgbe_config_tsf_mode;
2887 /* For TX DMA Operating on Second Frame config */
2888 hw_if->config_osp_mode = xgbe_config_osp_mode;
2890 /* For RX and TX PBL config */
2891 hw_if->config_rx_pbl_val = xgbe_config_rx_pbl_val;
2892 hw_if->get_rx_pbl_val = xgbe_get_rx_pbl_val;
2893 hw_if->config_tx_pbl_val = xgbe_config_tx_pbl_val;
2894 hw_if->get_tx_pbl_val = xgbe_get_tx_pbl_val;
2895 hw_if->config_pblx8 = xgbe_config_pblx8;
2897 /* For MMC statistics support */
2898 hw_if->tx_mmc_int = xgbe_tx_mmc_int;
2899 hw_if->rx_mmc_int = xgbe_rx_mmc_int;
2900 hw_if->read_mmc_stats = xgbe_read_mmc_stats;
2902 /* For PTP config */
2903 hw_if->config_tstamp = xgbe_config_tstamp;
2904 hw_if->update_tstamp_addend = xgbe_update_tstamp_addend;
2905 hw_if->set_tstamp_time = xgbe_set_tstamp_time;
2906 hw_if->get_tstamp_time = xgbe_get_tstamp_time;
2907 hw_if->get_tx_tstamp = xgbe_get_tx_tstamp;
2909 /* For Data Center Bridging config */
2910 hw_if->config_dcb_tc = xgbe_config_dcb_tc;
2911 hw_if->config_dcb_pfc = xgbe_config_dcb_pfc;
2913 /* For Receive Side Scaling */
2914 hw_if->enable_rss = xgbe_enable_rss;
2915 hw_if->disable_rss = xgbe_disable_rss;
2916 hw_if->set_rss_hash_key = xgbe_set_rss_hash_key;
2917 hw_if->set_rss_lookup_table = xgbe_set_rss_lookup_table;
2919 DBGPR("<--xgbe_init_function_ptrs\n");