1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /* Altera Triple-Speed Ethernet MAC driver
3 * Copyright (C) 2008-2014 Altera Corporation. All rights reserved
16 * Original driver contributed by SLS.
17 * Major updates contributed by GlobalLogic
20 #ifndef __ALTERA_TSE_H__
21 #define __ALTERA_TSE_H__
23 #define ALTERA_TSE_RESOURCE_NAME "altera_tse"
25 #include <linux/bitops.h>
26 #include <linux/if_vlan.h>
27 #include <linux/list.h>
28 #include <linux/netdevice.h>
29 #include <linux/phy.h>
30 #include <linux/phylink.h>
32 #define ALTERA_TSE_SW_RESET_WATCHDOG_CNTR 10000
33 #define ALTERA_TSE_MAC_FIFO_WIDTH 4 /* TX/RX FIFO width in
36 /* Rx FIFO default settings */
37 #define ALTERA_TSE_RX_SECTION_EMPTY 16
38 #define ALTERA_TSE_RX_SECTION_FULL 0
39 #define ALTERA_TSE_RX_ALMOST_EMPTY 8
40 #define ALTERA_TSE_RX_ALMOST_FULL 8
42 /* Tx FIFO default settings */
43 #define ALTERA_TSE_TX_SECTION_EMPTY 16
44 #define ALTERA_TSE_TX_SECTION_FULL 0
45 #define ALTERA_TSE_TX_ALMOST_EMPTY 8
46 #define ALTERA_TSE_TX_ALMOST_FULL 3
48 /* MAC function configuration default settings */
49 #define ALTERA_TSE_TX_IPG_LENGTH 12
51 #define ALTERA_TSE_PAUSE_QUANTA 0xffff
53 #define GET_BIT_VALUE(v, bit) (((v) >> (bit)) & 0x1)
55 /* MAC Command_Config Register Bit Definitions
57 #define MAC_CMDCFG_TX_ENA BIT(0)
58 #define MAC_CMDCFG_RX_ENA BIT(1)
59 #define MAC_CMDCFG_XON_GEN BIT(2)
60 #define MAC_CMDCFG_ETH_SPEED BIT(3)
61 #define MAC_CMDCFG_PROMIS_EN BIT(4)
62 #define MAC_CMDCFG_PAD_EN BIT(5)
63 #define MAC_CMDCFG_CRC_FWD BIT(6)
64 #define MAC_CMDCFG_PAUSE_FWD BIT(7)
65 #define MAC_CMDCFG_PAUSE_IGNORE BIT(8)
66 #define MAC_CMDCFG_TX_ADDR_INS BIT(9)
67 #define MAC_CMDCFG_HD_ENA BIT(10)
68 #define MAC_CMDCFG_EXCESS_COL BIT(11)
69 #define MAC_CMDCFG_LATE_COL BIT(12)
70 #define MAC_CMDCFG_SW_RESET BIT(13)
71 #define MAC_CMDCFG_MHASH_SEL BIT(14)
72 #define MAC_CMDCFG_LOOP_ENA BIT(15)
73 #define MAC_CMDCFG_TX_ADDR_SEL(v) (((v) & 0x7) << 16)
74 #define MAC_CMDCFG_MAGIC_ENA BIT(19)
75 #define MAC_CMDCFG_SLEEP BIT(20)
76 #define MAC_CMDCFG_WAKEUP BIT(21)
77 #define MAC_CMDCFG_XOFF_GEN BIT(22)
78 #define MAC_CMDCFG_CNTL_FRM_ENA BIT(23)
79 #define MAC_CMDCFG_NO_LGTH_CHECK BIT(24)
80 #define MAC_CMDCFG_ENA_10 BIT(25)
81 #define MAC_CMDCFG_RX_ERR_DISC BIT(26)
82 #define MAC_CMDCFG_DISABLE_READ_TIMEOUT BIT(27)
83 #define MAC_CMDCFG_CNT_RESET BIT(31)
85 #define MAC_CMDCFG_TX_ENA_GET(v) GET_BIT_VALUE(v, 0)
86 #define MAC_CMDCFG_RX_ENA_GET(v) GET_BIT_VALUE(v, 1)
87 #define MAC_CMDCFG_XON_GEN_GET(v) GET_BIT_VALUE(v, 2)
88 #define MAC_CMDCFG_ETH_SPEED_GET(v) GET_BIT_VALUE(v, 3)
89 #define MAC_CMDCFG_PROMIS_EN_GET(v) GET_BIT_VALUE(v, 4)
90 #define MAC_CMDCFG_PAD_EN_GET(v) GET_BIT_VALUE(v, 5)
91 #define MAC_CMDCFG_CRC_FWD_GET(v) GET_BIT_VALUE(v, 6)
92 #define MAC_CMDCFG_PAUSE_FWD_GET(v) GET_BIT_VALUE(v, 7)
93 #define MAC_CMDCFG_PAUSE_IGNORE_GET(v) GET_BIT_VALUE(v, 8)
94 #define MAC_CMDCFG_TX_ADDR_INS_GET(v) GET_BIT_VALUE(v, 9)
95 #define MAC_CMDCFG_HD_ENA_GET(v) GET_BIT_VALUE(v, 10)
96 #define MAC_CMDCFG_EXCESS_COL_GET(v) GET_BIT_VALUE(v, 11)
97 #define MAC_CMDCFG_LATE_COL_GET(v) GET_BIT_VALUE(v, 12)
98 #define MAC_CMDCFG_SW_RESET_GET(v) GET_BIT_VALUE(v, 13)
99 #define MAC_CMDCFG_MHASH_SEL_GET(v) GET_BIT_VALUE(v, 14)
100 #define MAC_CMDCFG_LOOP_ENA_GET(v) GET_BIT_VALUE(v, 15)
101 #define MAC_CMDCFG_TX_ADDR_SEL_GET(v) (((v) >> 16) & 0x7)
102 #define MAC_CMDCFG_MAGIC_ENA_GET(v) GET_BIT_VALUE(v, 19)
103 #define MAC_CMDCFG_SLEEP_GET(v) GET_BIT_VALUE(v, 20)
104 #define MAC_CMDCFG_WAKEUP_GET(v) GET_BIT_VALUE(v, 21)
105 #define MAC_CMDCFG_XOFF_GEN_GET(v) GET_BIT_VALUE(v, 22)
106 #define MAC_CMDCFG_CNTL_FRM_ENA_GET(v) GET_BIT_VALUE(v, 23)
107 #define MAC_CMDCFG_NO_LGTH_CHECK_GET(v) GET_BIT_VALUE(v, 24)
108 #define MAC_CMDCFG_ENA_10_GET(v) GET_BIT_VALUE(v, 25)
109 #define MAC_CMDCFG_RX_ERR_DISC_GET(v) GET_BIT_VALUE(v, 26)
110 #define MAC_CMDCFG_DISABLE_READ_TIMEOUT_GET(v) GET_BIT_VALUE(v, 27)
111 #define MAC_CMDCFG_CNT_RESET_GET(v) GET_BIT_VALUE(v, 31)
113 /* MDIO registers within MAC register Space
115 struct altera_tse_mdio {
116 u32 control; /* PHY device operation control register */
117 u32 status; /* PHY device operation status register */
118 u32 phy_id1; /* Bits 31:16 of PHY identifier */
119 u32 phy_id2; /* Bits 15:0 of PHY identifier */
120 u32 auto_negotiation_advertisement; /* Auto-negotiation
124 u32 remote_partner_base_page_ability;
154 /* MAC register Space. Note that some of these registers may or may not be
155 * present depending upon options chosen by the user when the core was
156 * configured and built. Please consult the Altera Triple Speed Ethernet User
159 struct altera_tse_mac {
160 /* Bits 15:0: MegaCore function revision (0x0800). Bit 31:16: Customer
163 u32 megacore_revision;
164 /* Provides a memory location for user applications to test the device
168 /* The host processor uses this register to control and configure the
172 /* 32-bit primary MAC address word 0 bits 0 to 31 of the primary
176 /* 32-bit primary MAC address word 1 bits 32 to 47 of the primary
180 /* 14-bit maximum frame length. The MAC receive logic */
182 /* The pause quanta is used in each pause frame sent to a remote
183 * Ethernet device, in increments of 512 Ethernet bit times
186 /* 12-bit receive FIFO section-empty threshold */
187 u32 rx_section_empty;
188 /* 12-bit receive FIFO section-full threshold */
190 /* 12-bit transmit FIFO section-empty threshold */
191 u32 tx_section_empty;
192 /* 12-bit transmit FIFO section-full threshold */
194 /* 12-bit receive FIFO almost-empty threshold */
196 /* 12-bit receive FIFO almost-full threshold */
198 /* 12-bit transmit FIFO almost-empty threshold */
200 /* 12-bit transmit FIFO almost-full threshold */
202 /* MDIO address of PHY Device 0. Bits 0 to 4 hold a 5-bit PHY address */
204 /* MDIO address of PHY Device 1. Bits 0 to 4 hold a 5-bit PHY address */
207 /* Bit[15:0]—16-bit holdoff quanta */
210 /* only if 100/1000 BaseX PCS, reserved otherwise */
213 /* Minimum IPG between consecutive transmit frame in terms of bytes */
216 /* IEEE 802.3 oEntity Managed Object Support */
218 /* The MAC addresses */
222 /* Number of frames transmitted without error including pause frames */
223 u32 frames_transmitted_ok;
224 /* Number of frames received without error including pause frames */
225 u32 frames_received_ok;
226 /* Number of frames received with a CRC error */
227 u32 frames_check_sequence_errors;
228 /* Frame received with an alignment error */
229 u32 alignment_errors;
230 /* Sum of payload and padding octets of frames transmitted without
233 u32 octets_transmitted_ok;
234 /* Sum of payload and padding octets of frames received without error */
235 u32 octets_received_ok;
237 /* IEEE 802.3 oPausedEntity Managed Object Support */
239 /* Number of transmitted pause frames */
240 u32 tx_pause_mac_ctrl_frames;
241 /* Number of Received pause frames */
242 u32 rx_pause_mac_ctrl_frames;
244 /* IETF MIB (MIB-II) Object Support */
246 /* Number of frames received with error */
248 /* Number of frames transmitted with error */
250 /* Number of valid received unicast frames */
251 u32 if_in_ucast_pkts;
252 /* Number of valid received multicasts frames (without pause) */
253 u32 if_in_multicast_pkts;
254 /* Number of valid received broadcast frames */
255 u32 if_in_broadcast_pkts;
257 /* The number of valid unicast frames transmitted */
258 u32 if_out_ucast_pkts;
259 /* The number of valid multicast frames transmitted,
260 * excluding pause frames
262 u32 if_out_multicast_pkts;
263 u32 if_out_broadcast_pkts;
265 /* IETF RMON MIB Object Support */
267 /* Counts the number of dropped packets due to internal errors
270 u32 ether_stats_drop_events;
271 /* Total number of bytes received. Good and bad frames. */
272 u32 ether_stats_octets;
273 /* Total number of packets received. Counts good and bad packets. */
274 u32 ether_stats_pkts;
275 /* Number of packets received with less than 64 bytes. */
276 u32 ether_stats_undersize_pkts;
277 /* The number of frames received that are longer than the
278 * value configured in the frm_length register
280 u32 ether_stats_oversize_pkts;
281 /* Number of received packet with 64 bytes */
282 u32 ether_stats_pkts_64_octets;
283 /* Frames (good and bad) with 65 to 127 bytes */
284 u32 ether_stats_pkts_65to127_octets;
285 /* Frames (good and bad) with 128 to 255 bytes */
286 u32 ether_stats_pkts_128to255_octets;
287 /* Frames (good and bad) with 256 to 511 bytes */
288 u32 ether_stats_pkts_256to511_octets;
289 /* Frames (good and bad) with 512 to 1023 bytes */
290 u32 ether_stats_pkts_512to1023_octets;
291 /* Frames (good and bad) with 1024 to 1518 bytes */
292 u32 ether_stats_pkts_1024to1518_octets;
294 /* Any frame length from 1519 to the maximum length configured in the
295 * frm_length register, if it is greater than 1518
297 u32 ether_stats_pkts_1519tox_octets;
298 /* Too long frames with CRC error */
299 u32 ether_stats_jabbers;
300 /* Too short frames with CRC error */
301 u32 ether_stats_fragments;
305 /* FIFO control register */
309 /* Extended Statistics Counters */
310 u32 msb_octets_transmitted_ok;
311 u32 msb_octets_received_ok;
312 u32 msb_ether_stats_octets;
316 /* Multicast address resolution table, mapped in the controller address
321 /* Registers 0 to 31 within PHY device 0/1 connected to the MDIO PHY
322 * management interface
324 struct altera_tse_mdio mdio_phy0;
325 struct altera_tse_mdio mdio_phy1;
327 /* 4 Supplemental MAC Addresses */
328 u32 supp_mac_addr_0_0;
329 u32 supp_mac_addr_0_1;
330 u32 supp_mac_addr_1_0;
331 u32 supp_mac_addr_1_1;
332 u32 supp_mac_addr_2_0;
333 u32 supp_mac_addr_2_1;
334 u32 supp_mac_addr_3_0;
335 u32 supp_mac_addr_3_1;
339 /* IEEE 1588v2 Feature */
350 #define tse_csroffs(a) (offsetof(struct altera_tse_mac, a))
352 /* Transmit and Receive Command Registers Bit Definitions
354 #define ALTERA_TSE_TX_CMD_STAT_OMIT_CRC BIT(17)
355 #define ALTERA_TSE_TX_CMD_STAT_TX_SHIFT16 BIT(18)
356 #define ALTERA_TSE_RX_CMD_STAT_RX_SHIFT16 BIT(25)
358 /* Wrapper around a pointer to a socket buffer,
359 * so a DMA handle can be stored along with the buffer
369 struct altera_tse_private;
371 #define ALTERA_DTYPE_SGDMA 1
372 #define ALTERA_DTYPE_MSGDMA 2
374 /* standard DMA interface for SGDMA and MSGDMA */
375 struct altera_dmaops {
378 void (*reset_dma)(struct altera_tse_private *);
379 void (*enable_txirq)(struct altera_tse_private *);
380 void (*enable_rxirq)(struct altera_tse_private *);
381 void (*disable_txirq)(struct altera_tse_private *);
382 void (*disable_rxirq)(struct altera_tse_private *);
383 void (*clear_txirq)(struct altera_tse_private *);
384 void (*clear_rxirq)(struct altera_tse_private *);
385 int (*tx_buffer)(struct altera_tse_private *, struct tse_buffer *);
386 u32 (*tx_completions)(struct altera_tse_private *);
387 void (*add_rx_desc)(struct altera_tse_private *, struct tse_buffer *);
388 u32 (*get_rx_status)(struct altera_tse_private *);
389 int (*init_dma)(struct altera_tse_private *);
390 void (*uninit_dma)(struct altera_tse_private *);
391 void (*start_rxdma)(struct altera_tse_private *);
394 /* This structure is private to each device.
396 struct altera_tse_private {
397 struct net_device *dev;
398 struct device *device;
399 struct napi_struct napi;
401 /* MAC address space */
402 struct altera_tse_mac __iomem *mac_dev;
407 /* mSGDMA Rx Dispatcher address space */
408 void __iomem *rx_dma_csr;
409 void __iomem *rx_dma_desc;
410 void __iomem *rx_dma_resp;
412 /* mSGDMA Tx Dispatcher address space */
413 void __iomem *tx_dma_csr;
414 void __iomem *tx_dma_desc;
416 /* SGMII PCS address space */
417 void __iomem *pcs_base;
419 /* Rx buffers queue */
420 struct tse_buffer *rx_ring;
427 struct tse_buffer *tx_ring;
436 /* RX/TX MAC FIFO configs */
440 /* Hash filter settings */
444 /* Descriptor memory info for managing SGDMA */
447 dma_addr_t rxdescmem_busaddr;
448 dma_addr_t txdescmem_busaddr;
451 dma_addr_t rxdescphys;
452 dma_addr_t txdescphys;
454 struct list_head txlisthd;
455 struct list_head rxlisthd;
457 /* MAC command_config register protection */
458 spinlock_t mac_cfg_lock;
459 /* Tx path protection */
461 /* Rx DMA & interrupt control protection */
462 spinlock_t rxdma_irq_lock;
465 int phy_addr; /* PHY's MDIO address, -1 for autodetection */
466 phy_interface_t phy_iface;
467 struct mii_bus *mdio;
472 /* ethtool msglvl option */
475 const struct altera_dmaops *dmaops;
477 struct phylink *phylink;
478 struct phylink_config phylink_config;
479 struct phylink_pcs *pcs;
482 /* Function prototypes
484 void altera_tse_set_ethtool_ops(struct net_device *);
487 u32 csrrd32(void __iomem *mac, size_t offs)
489 void __iomem *paddr = (void __iomem *)((uintptr_t)mac + offs);
494 u16 csrrd16(void __iomem *mac, size_t offs)
496 void __iomem *paddr = (void __iomem *)((uintptr_t)mac + offs);
501 u8 csrrd8(void __iomem *mac, size_t offs)
503 void __iomem *paddr = (void __iomem *)((uintptr_t)mac + offs);
508 void csrwr32(u32 val, void __iomem *mac, size_t offs)
510 void __iomem *paddr = (void __iomem *)((uintptr_t)mac + offs);
516 void csrwr16(u16 val, void __iomem *mac, size_t offs)
518 void __iomem *paddr = (void __iomem *)((uintptr_t)mac + offs);
524 void csrwr8(u8 val, void __iomem *mac, size_t offs)
526 void __iomem *paddr = (void __iomem *)((uintptr_t)mac + offs);
531 #endif /* __ALTERA_TSE_H__ */