1 /* Altera Triple-Speed Ethernet MAC driver
2 * Copyright (C) 2008-2014 Altera Corporation. All rights reserved
15 * Original driver contributed by SLS.
16 * Major updates contributed by GlobalLogic
18 * This program is free software; you can redistribute it and/or modify it
19 * under the terms and conditions of the GNU General Public License,
20 * version 2, as published by the Free Software Foundation.
22 * This program is distributed in the hope it will be useful, but WITHOUT
23 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
24 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
27 * You should have received a copy of the GNU General Public License along with
28 * this program. If not, see <http://www.gnu.org/licenses/>.
31 #ifndef __ALTERA_TSE_H__
32 #define __ALTERA_TSE_H__
34 #define ALTERA_TSE_RESOURCE_NAME "altera_tse"
36 #include <linux/bitops.h>
37 #include <linux/if_vlan.h>
38 #include <linux/list.h>
39 #include <linux/netdevice.h>
40 #include <linux/phy.h>
42 #define ALTERA_TSE_SW_RESET_WATCHDOG_CNTR 10000
43 #define ALTERA_TSE_MAC_FIFO_WIDTH 4 /* TX/RX FIFO width in
46 /* Rx FIFO default settings */
47 #define ALTERA_TSE_RX_SECTION_EMPTY 16
48 #define ALTERA_TSE_RX_SECTION_FULL 0
49 #define ALTERA_TSE_RX_ALMOST_EMPTY 8
50 #define ALTERA_TSE_RX_ALMOST_FULL 8
52 /* Tx FIFO default settings */
53 #define ALTERA_TSE_TX_SECTION_EMPTY 16
54 #define ALTERA_TSE_TX_SECTION_FULL 0
55 #define ALTERA_TSE_TX_ALMOST_EMPTY 8
56 #define ALTERA_TSE_TX_ALMOST_FULL 3
58 /* MAC function configuration default settings */
59 #define ALTERA_TSE_TX_IPG_LENGTH 12
61 #define GET_BIT_VALUE(v, bit) (((v) >> (bit)) & 0x1)
63 /* MAC Command_Config Register Bit Definitions
65 #define MAC_CMDCFG_TX_ENA BIT(0)
66 #define MAC_CMDCFG_RX_ENA BIT(1)
67 #define MAC_CMDCFG_XON_GEN BIT(2)
68 #define MAC_CMDCFG_ETH_SPEED BIT(3)
69 #define MAC_CMDCFG_PROMIS_EN BIT(4)
70 #define MAC_CMDCFG_PAD_EN BIT(5)
71 #define MAC_CMDCFG_CRC_FWD BIT(6)
72 #define MAC_CMDCFG_PAUSE_FWD BIT(7)
73 #define MAC_CMDCFG_PAUSE_IGNORE BIT(8)
74 #define MAC_CMDCFG_TX_ADDR_INS BIT(9)
75 #define MAC_CMDCFG_HD_ENA BIT(10)
76 #define MAC_CMDCFG_EXCESS_COL BIT(11)
77 #define MAC_CMDCFG_LATE_COL BIT(12)
78 #define MAC_CMDCFG_SW_RESET BIT(13)
79 #define MAC_CMDCFG_MHASH_SEL BIT(14)
80 #define MAC_CMDCFG_LOOP_ENA BIT(15)
81 #define MAC_CMDCFG_TX_ADDR_SEL(v) (((v) & 0x7) << 16)
82 #define MAC_CMDCFG_MAGIC_ENA BIT(19)
83 #define MAC_CMDCFG_SLEEP BIT(20)
84 #define MAC_CMDCFG_WAKEUP BIT(21)
85 #define MAC_CMDCFG_XOFF_GEN BIT(22)
86 #define MAC_CMDCFG_CNTL_FRM_ENA BIT(23)
87 #define MAC_CMDCFG_NO_LGTH_CHECK BIT(24)
88 #define MAC_CMDCFG_ENA_10 BIT(25)
89 #define MAC_CMDCFG_RX_ERR_DISC BIT(26)
90 #define MAC_CMDCFG_DISABLE_READ_TIMEOUT BIT(27)
91 #define MAC_CMDCFG_CNT_RESET BIT(31)
93 #define MAC_CMDCFG_TX_ENA_GET(v) GET_BIT_VALUE(v, 0)
94 #define MAC_CMDCFG_RX_ENA_GET(v) GET_BIT_VALUE(v, 1)
95 #define MAC_CMDCFG_XON_GEN_GET(v) GET_BIT_VALUE(v, 2)
96 #define MAC_CMDCFG_ETH_SPEED_GET(v) GET_BIT_VALUE(v, 3)
97 #define MAC_CMDCFG_PROMIS_EN_GET(v) GET_BIT_VALUE(v, 4)
98 #define MAC_CMDCFG_PAD_EN_GET(v) GET_BIT_VALUE(v, 5)
99 #define MAC_CMDCFG_CRC_FWD_GET(v) GET_BIT_VALUE(v, 6)
100 #define MAC_CMDCFG_PAUSE_FWD_GET(v) GET_BIT_VALUE(v, 7)
101 #define MAC_CMDCFG_PAUSE_IGNORE_GET(v) GET_BIT_VALUE(v, 8)
102 #define MAC_CMDCFG_TX_ADDR_INS_GET(v) GET_BIT_VALUE(v, 9)
103 #define MAC_CMDCFG_HD_ENA_GET(v) GET_BIT_VALUE(v, 10)
104 #define MAC_CMDCFG_EXCESS_COL_GET(v) GET_BIT_VALUE(v, 11)
105 #define MAC_CMDCFG_LATE_COL_GET(v) GET_BIT_VALUE(v, 12)
106 #define MAC_CMDCFG_SW_RESET_GET(v) GET_BIT_VALUE(v, 13)
107 #define MAC_CMDCFG_MHASH_SEL_GET(v) GET_BIT_VALUE(v, 14)
108 #define MAC_CMDCFG_LOOP_ENA_GET(v) GET_BIT_VALUE(v, 15)
109 #define MAC_CMDCFG_TX_ADDR_SEL_GET(v) (((v) >> 16) & 0x7)
110 #define MAC_CMDCFG_MAGIC_ENA_GET(v) GET_BIT_VALUE(v, 19)
111 #define MAC_CMDCFG_SLEEP_GET(v) GET_BIT_VALUE(v, 20)
112 #define MAC_CMDCFG_WAKEUP_GET(v) GET_BIT_VALUE(v, 21)
113 #define MAC_CMDCFG_XOFF_GEN_GET(v) GET_BIT_VALUE(v, 22)
114 #define MAC_CMDCFG_CNTL_FRM_ENA_GET(v) GET_BIT_VALUE(v, 23)
115 #define MAC_CMDCFG_NO_LGTH_CHECK_GET(v) GET_BIT_VALUE(v, 24)
116 #define MAC_CMDCFG_ENA_10_GET(v) GET_BIT_VALUE(v, 25)
117 #define MAC_CMDCFG_RX_ERR_DISC_GET(v) GET_BIT_VALUE(v, 26)
118 #define MAC_CMDCFG_DISABLE_READ_TIMEOUT_GET(v) GET_BIT_VALUE(v, 27)
119 #define MAC_CMDCFG_CNT_RESET_GET(v) GET_BIT_VALUE(v, 31)
121 /* MDIO registers within MAC register Space
123 struct altera_tse_mdio {
124 u32 control; /* PHY device operation control register */
125 u32 status; /* PHY device operation status register */
126 u32 phy_id1; /* Bits 31:16 of PHY identifier */
127 u32 phy_id2; /* Bits 15:0 of PHY identifier */
128 u32 auto_negotiation_advertisement; /* Auto-negotiation
132 u32 remote_partner_base_page_ability;
162 /* MAC register Space. Note that some of these registers may or may not be
163 * present depending upon options chosen by the user when the core was
164 * configured and built. Please consult the Altera Triple Speed Ethernet User
167 struct altera_tse_mac {
168 /* Bits 15:0: MegaCore function revision (0x0800). Bit 31:16: Customer
171 u32 megacore_revision;
172 /* Provides a memory location for user applications to test the device
176 /* The host processor uses this register to control and configure the
180 /* 32-bit primary MAC address word 0 bits 0 to 31 of the primary
184 /* 32-bit primary MAC address word 1 bits 32 to 47 of the primary
188 /* 14-bit maximum frame length. The MAC receive logic */
190 /* The pause quanta is used in each pause frame sent to a remote
191 * Ethernet device, in increments of 512 Ethernet bit times
194 /* 12-bit receive FIFO section-empty threshold */
195 u32 rx_section_empty;
196 /* 12-bit receive FIFO section-full threshold */
198 /* 12-bit transmit FIFO section-empty threshold */
199 u32 tx_section_empty;
200 /* 12-bit transmit FIFO section-full threshold */
202 /* 12-bit receive FIFO almost-empty threshold */
204 /* 12-bit receive FIFO almost-full threshold */
206 /* 12-bit transmit FIFO almost-empty threshold */
208 /* 12-bit transmit FIFO almost-full threshold */
210 /* MDIO address of PHY Device 0. Bits 0 to 4 hold a 5-bit PHY address */
212 /* MDIO address of PHY Device 1. Bits 0 to 4 hold a 5-bit PHY address */
215 /* Bit[15:0]—16-bit holdoff quanta */
218 /* only if 100/1000 BaseX PCS, reserved otherwise */
221 /* Minimum IPG between consecutive transmit frame in terms of bytes */
224 /* IEEE 802.3 oEntity Managed Object Support */
226 /* The MAC addresses */
230 /* Number of frames transmitted without error including pause frames */
231 u32 frames_transmitted_ok;
232 /* Number of frames received without error including pause frames */
233 u32 frames_received_ok;
234 /* Number of frames received with a CRC error */
235 u32 frames_check_sequence_errors;
236 /* Frame received with an alignment error */
237 u32 alignment_errors;
238 /* Sum of payload and padding octets of frames transmitted without
241 u32 octets_transmitted_ok;
242 /* Sum of payload and padding octets of frames received without error */
243 u32 octets_received_ok;
245 /* IEEE 802.3 oPausedEntity Managed Object Support */
247 /* Number of transmitted pause frames */
248 u32 tx_pause_mac_ctrl_frames;
249 /* Number of Received pause frames */
250 u32 rx_pause_mac_ctrl_frames;
252 /* IETF MIB (MIB-II) Object Support */
254 /* Number of frames received with error */
256 /* Number of frames transmitted with error */
258 /* Number of valid received unicast frames */
259 u32 if_in_ucast_pkts;
260 /* Number of valid received multicasts frames (without pause) */
261 u32 if_in_multicast_pkts;
262 /* Number of valid received broadcast frames */
263 u32 if_in_broadcast_pkts;
265 /* The number of valid unicast frames transmitted */
266 u32 if_out_ucast_pkts;
267 /* The number of valid multicast frames transmitted,
268 * excluding pause frames
270 u32 if_out_multicast_pkts;
271 u32 if_out_broadcast_pkts;
273 /* IETF RMON MIB Object Support */
275 /* Counts the number of dropped packets due to internal errors
278 u32 ether_stats_drop_events;
279 /* Total number of bytes received. Good and bad frames. */
280 u32 ether_stats_octets;
281 /* Total number of packets received. Counts good and bad packets. */
282 u32 ether_stats_pkts;
283 /* Number of packets received with less than 64 bytes. */
284 u32 ether_stats_undersize_pkts;
285 /* The number of frames received that are longer than the
286 * value configured in the frm_length register
288 u32 ether_stats_oversize_pkts;
289 /* Number of received packet with 64 bytes */
290 u32 ether_stats_pkts_64_octets;
291 /* Frames (good and bad) with 65 to 127 bytes */
292 u32 ether_stats_pkts_65to127_octets;
293 /* Frames (good and bad) with 128 to 255 bytes */
294 u32 ether_stats_pkts_128to255_octets;
295 /* Frames (good and bad) with 256 to 511 bytes */
296 u32 ether_stats_pkts_256to511_octets;
297 /* Frames (good and bad) with 512 to 1023 bytes */
298 u32 ether_stats_pkts_512to1023_octets;
299 /* Frames (good and bad) with 1024 to 1518 bytes */
300 u32 ether_stats_pkts_1024to1518_octets;
302 /* Any frame length from 1519 to the maximum length configured in the
303 * frm_length register, if it is greater than 1518
305 u32 ether_stats_pkts_1519tox_octets;
306 /* Too long frames with CRC error */
307 u32 ether_stats_jabbers;
308 /* Too short frames with CRC error */
309 u32 ether_stats_fragments;
313 /* FIFO control register */
317 /* Extended Statistics Counters */
318 u32 msb_octets_transmitted_ok;
319 u32 msb_octets_received_ok;
320 u32 msb_ether_stats_octets;
324 /* Multicast address resolution table, mapped in the controller address
329 /* Registers 0 to 31 within PHY device 0/1 connected to the MDIO PHY
330 * management interface
332 struct altera_tse_mdio mdio_phy0;
333 struct altera_tse_mdio mdio_phy1;
335 /* 4 Supplemental MAC Addresses */
336 u32 supp_mac_addr_0_0;
337 u32 supp_mac_addr_0_1;
338 u32 supp_mac_addr_1_0;
339 u32 supp_mac_addr_1_1;
340 u32 supp_mac_addr_2_0;
341 u32 supp_mac_addr_2_1;
342 u32 supp_mac_addr_3_0;
343 u32 supp_mac_addr_3_1;
347 /* IEEE 1588v2 Feature */
358 /* Transmit and Receive Command Registers Bit Definitions
360 #define ALTERA_TSE_TX_CMD_STAT_OMIT_CRC BIT(17)
361 #define ALTERA_TSE_TX_CMD_STAT_TX_SHIFT16 BIT(18)
362 #define ALTERA_TSE_RX_CMD_STAT_RX_SHIFT16 BIT(25)
364 /* Wrapper around a pointer to a socket buffer,
365 * so a DMA handle can be stored along with the buffer
375 struct altera_tse_private;
377 #define ALTERA_DTYPE_SGDMA 1
378 #define ALTERA_DTYPE_MSGDMA 2
380 /* standard DMA interface for SGDMA and MSGDMA */
381 struct altera_dmaops {
384 void (*reset_dma)(struct altera_tse_private *);
385 void (*enable_txirq)(struct altera_tse_private *);
386 void (*enable_rxirq)(struct altera_tse_private *);
387 void (*disable_txirq)(struct altera_tse_private *);
388 void (*disable_rxirq)(struct altera_tse_private *);
389 void (*clear_txirq)(struct altera_tse_private *);
390 void (*clear_rxirq)(struct altera_tse_private *);
391 int (*tx_buffer)(struct altera_tse_private *, struct tse_buffer *);
392 u32 (*tx_completions)(struct altera_tse_private *);
393 int (*add_rx_desc)(struct altera_tse_private *, struct tse_buffer *);
394 u32 (*get_rx_status)(struct altera_tse_private *);
395 int (*init_dma)(struct altera_tse_private *);
396 void (*uninit_dma)(struct altera_tse_private *);
399 /* This structure is private to each device.
401 struct altera_tse_private {
402 struct net_device *dev;
403 struct device *device;
404 struct napi_struct napi;
406 /* MAC address space */
407 struct altera_tse_mac __iomem *mac_dev;
412 /* mSGDMA Rx Dispatcher address space */
413 void __iomem *rx_dma_csr;
414 void __iomem *rx_dma_desc;
415 void __iomem *rx_dma_resp;
417 /* mSGDMA Tx Dispatcher address space */
418 void __iomem *tx_dma_csr;
419 void __iomem *tx_dma_desc;
421 /* Rx buffers queue */
422 struct tse_buffer *rx_ring;
429 struct tse_buffer *tx_ring;
438 /* RX/TX MAC FIFO configs */
443 /* Hash filter settings */
447 /* Descriptor memory info for managing SGDMA */
450 dma_addr_t rxdescmem_busaddr;
451 dma_addr_t txdescmem_busaddr;
454 dma_addr_t rxdescphys;
455 dma_addr_t txdescphys;
457 struct list_head txlisthd;
458 struct list_head rxlisthd;
460 /* MAC command_config register protection */
461 spinlock_t mac_cfg_lock;
462 /* Tx path protection */
464 /* Rx DMA & interrupt control protection */
465 spinlock_t rxdma_irq_lock;
468 int phy_addr; /* PHY's MDIO address, -1 for autodetection */
469 phy_interface_t phy_iface;
470 struct mii_bus *mdio;
471 struct phy_device *phydev;
476 /* ethtool msglvl option */
479 struct altera_dmaops *dmaops;
482 /* Function prototypes
484 void altera_tse_set_ethtool_ops(struct net_device *);
486 #endif /* __ALTERA_TSE_H__ */